Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 58
- Errors: 1
1 11:43:51.340126 lava-dispatcher, installed at version: 2023.05.1
2 11:43:51.340345 start: 0 validate
3 11:43:51.340486 Start time: 2023-06-15 11:43:51.340477+00:00 (UTC)
4 11:43:51.340622 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:43:51.340752 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 11:43:51.601434 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:43:51.601688 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:43:51.852838 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:43:51.853075 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:43:52.121408 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:43:52.121696 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:43:52.381862 validate duration: 1.04
14 11:43:52.382130 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:43:52.382245 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:43:52.382335 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:43:52.382462 Not decompressing ramdisk as can be used compressed.
18 11:43:52.382548 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230609.0/arm64/rootfs.cpio.gz
19 11:43:52.382616 saving as /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/ramdisk/rootfs.cpio.gz
20 11:43:52.382680 total size: 27153005 (25MB)
21 11:43:52.383741 progress 0% (0MB)
22 11:43:52.391542 progress 5% (1MB)
23 11:43:52.401551 progress 10% (2MB)
24 11:43:52.408730 progress 15% (3MB)
25 11:43:52.415706 progress 20% (5MB)
26 11:43:52.422806 progress 25% (6MB)
27 11:43:52.429748 progress 30% (7MB)
28 11:43:52.436849 progress 35% (9MB)
29 11:43:52.464309 progress 40% (10MB)
30 11:43:52.471911 progress 45% (11MB)
31 11:43:52.479281 progress 50% (12MB)
32 11:43:52.486634 progress 55% (14MB)
33 11:43:52.494193 progress 60% (15MB)
34 11:43:52.501762 progress 65% (16MB)
35 11:43:52.509416 progress 70% (18MB)
36 11:43:52.516801 progress 75% (19MB)
37 11:43:52.524268 progress 80% (20MB)
38 11:43:52.531799 progress 85% (22MB)
39 11:43:52.539053 progress 90% (23MB)
40 11:43:52.546646 progress 95% (24MB)
41 11:43:52.554012 progress 100% (25MB)
42 11:43:52.554303 25MB downloaded in 0.17s (150.89MB/s)
43 11:43:52.554525 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:43:52.554927 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:43:52.555053 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:43:52.555184 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:43:52.555370 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:43:52.555452 saving as /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/kernel/Image
50 11:43:52.555518 total size: 47581696 (45MB)
51 11:43:52.555582 No compression specified
52 11:43:52.556745 progress 0% (0MB)
53 11:43:52.569580 progress 5% (2MB)
54 11:43:52.603800 progress 10% (4MB)
55 11:43:52.616723 progress 15% (6MB)
56 11:43:52.634408 progress 20% (9MB)
57 11:43:52.649212 progress 25% (11MB)
58 11:43:52.662127 progress 30% (13MB)
59 11:43:52.675191 progress 35% (15MB)
60 11:43:52.688231 progress 40% (18MB)
61 11:43:52.702130 progress 45% (20MB)
62 11:43:52.716003 progress 50% (22MB)
63 11:43:52.729568 progress 55% (24MB)
64 11:43:52.743471 progress 60% (27MB)
65 11:43:52.780978 progress 65% (29MB)
66 11:43:52.798894 progress 70% (31MB)
67 11:43:52.813129 progress 75% (34MB)
68 11:43:52.848271 progress 80% (36MB)
69 11:43:52.860612 progress 85% (38MB)
70 11:43:52.895501 progress 90% (40MB)
71 11:43:52.907504 progress 95% (43MB)
72 11:43:52.943152 progress 100% (45MB)
73 11:43:52.943324 45MB downloaded in 0.39s (117.01MB/s)
74 11:43:52.943486 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:43:52.943725 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:43:52.943814 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:43:52.943901 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:43:52.970436 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:43:52.970578 saving as /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/dtb/mt8192-asurada-spherion-r0.dtb
81 11:43:52.970670 total size: 46924 (0MB)
82 11:43:52.970755 No compression specified
83 11:43:52.972200 progress 69% (0MB)
84 11:43:52.972553 progress 100% (0MB)
85 11:43:52.972750 0MB downloaded in 0.00s (21.55MB/s)
86 11:43:52.972921 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:43:52.973214 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:43:52.973341 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:43:52.973459 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:43:52.973617 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:43:52.973714 saving as /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/modules/modules.tar
93 11:43:52.973802 total size: 8555256 (8MB)
94 11:43:52.973886 Using unxz to decompress xz
95 11:43:52.978603 progress 0% (0MB)
96 11:43:53.010025 progress 5% (0MB)
97 11:43:53.038397 progress 10% (0MB)
98 11:43:53.067741 progress 15% (1MB)
99 11:43:53.095860 progress 20% (1MB)
100 11:43:53.122239 progress 25% (2MB)
101 11:43:53.147075 progress 30% (2MB)
102 11:43:53.174641 progress 35% (2MB)
103 11:43:53.201751 progress 40% (3MB)
104 11:43:53.225932 progress 45% (3MB)
105 11:43:53.253395 progress 50% (4MB)
106 11:43:53.278374 progress 55% (4MB)
107 11:43:53.304341 progress 60% (4MB)
108 11:43:53.330713 progress 65% (5MB)
109 11:43:53.355554 progress 70% (5MB)
110 11:43:53.379165 progress 75% (6MB)
111 11:43:53.402559 progress 80% (6MB)
112 11:43:53.427007 progress 85% (6MB)
113 11:43:53.455898 progress 90% (7MB)
114 11:43:53.482729 progress 95% (7MB)
115 11:43:53.507842 progress 100% (8MB)
116 11:43:53.512522 8MB downloaded in 0.54s (15.15MB/s)
117 11:43:53.512974 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:43:53.513500 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:43:53.513692 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:43:53.513869 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:43:53.514024 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:43:53.514197 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:43:53.514535 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk
125 11:43:53.514756 makedir: /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin
126 11:43:53.514946 makedir: /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/tests
127 11:43:53.515120 makedir: /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/results
128 11:43:53.515310 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-add-keys
129 11:43:53.515607 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-add-sources
130 11:43:53.515899 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-background-process-start
131 11:43:53.516148 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-background-process-stop
132 11:43:53.516360 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-common-functions
133 11:43:53.516569 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-echo-ipv4
134 11:43:53.516778 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-install-packages
135 11:43:53.516987 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-installed-packages
136 11:43:53.518032 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-os-build
137 11:43:53.518256 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-probe-channel
138 11:43:53.519371 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-probe-ip
139 11:43:53.519589 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-target-ip
140 11:43:53.519805 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-target-mac
141 11:43:53.520029 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-target-storage
142 11:43:53.520258 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-test-case
143 11:43:53.520481 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-test-event
144 11:43:53.520695 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-test-feedback
145 11:43:53.520919 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-test-raise
146 11:43:53.521149 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-test-reference
147 11:43:53.521374 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-test-runner
148 11:43:53.521590 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-test-set
149 11:43:53.521812 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-test-shell
150 11:43:53.522028 Updating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-install-packages (oe)
151 11:43:53.533131 Updating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/bin/lava-installed-packages (oe)
152 11:43:53.558178 Creating /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/environment
153 11:43:53.561982 LAVA metadata
154 11:43:53.562139 - LAVA_JOB_ID=10742249
155 11:43:53.562267 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:43:53.562432 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:43:53.562534 skipped lava-vland-overlay
158 11:43:53.562645 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:43:53.562760 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:43:53.562854 skipped lava-multinode-overlay
161 11:43:53.562964 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:43:53.563080 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:43:53.563189 Loading test definitions
164 11:43:53.563319 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:43:53.563421 Using /lava-10742249 at stage 0
166 11:43:53.564588 uuid=10742249_1.5.2.3.1 testdef=None
167 11:43:53.564746 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:43:53.564904 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:43:53.565837 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:43:53.566287 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:43:53.600453 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:43:53.600937 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:43:53.662716 runner path: /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/0/tests/0_v4l2-compliance-uvc test_uuid 10742249_1.5.2.3.1
176 11:43:53.663068 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:43:53.663527 Creating lava-test-runner.conf files
179 11:43:53.663654 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742249/lava-overlay-wkhekkvk/lava-10742249/0 for stage 0
180 11:43:53.663816 - 0_v4l2-compliance-uvc
181 11:43:53.663993 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:43:53.664154 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:43:53.675163 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:43:53.675413 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:43:53.675588 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:43:53.675762 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:43:53.675941 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:43:55.303635 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 11:43:55.304823 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 11:43:55.305309 extracting modules file /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742249/extract-overlay-ramdisk-tyyam9z1/ramdisk
191 11:43:56.125149 end: 1.5.4 extract-modules (duration 00:00:01) [common]
192 11:43:56.125358 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 11:43:56.125526 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742249/compress-overlay-k0rj6ida/overlay-1.5.2.4.tar.gz to ramdisk
194 11:43:56.125689 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742249/compress-overlay-k0rj6ida/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742249/extract-overlay-ramdisk-tyyam9z1/ramdisk
195 11:43:56.137502 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:43:56.137708 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 11:43:56.137849 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:43:56.137989 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 11:43:56.138113 Building ramdisk /var/lib/lava/dispatcher/tmp/10742249/extract-overlay-ramdisk-tyyam9z1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742249/extract-overlay-ramdisk-tyyam9z1/ramdisk
200 11:44:01.705776 >> 230341 blocks
201 11:44:07.360642 rename /var/lib/lava/dispatcher/tmp/10742249/extract-overlay-ramdisk-tyyam9z1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/ramdisk/ramdisk.cpio.gz
202 11:44:07.361156 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
203 11:44:07.361328 start: 1.5.8 prepare-kernel (timeout 00:09:45) [common]
204 11:44:07.361483 start: 1.5.8.1 prepare-fit (timeout 00:09:45) [common]
205 11:44:07.361645 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/kernel/Image'
206 11:44:19.662671 Returned 0 in 12 seconds
207 11:44:19.763661 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/kernel/image.itb
208 11:44:30.516736 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:44:30.517093 output: Created: Thu Jun 15 12:44:30 2023
210 11:44:30.517171 output: Image 0 (kernel-1)
211 11:44:30.517236 output: Description:
212 11:44:30.517299 output: Created: Thu Jun 15 12:44:30 2023
213 11:44:30.517360 output: Type: Kernel Image
214 11:44:30.517419 output: Compression: lzma compressed
215 11:44:30.517479 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
216 11:44:30.517539 output: Architecture: AArch64
217 11:44:30.517596 output: OS: Linux
218 11:44:30.517653 output: Load Address: 0x00000000
219 11:44:30.517710 output: Entry Point: 0x00000000
220 11:44:30.517765 output: Hash algo: crc32
221 11:44:30.517827 output: Hash value: cd22d0e5
222 11:44:30.517885 output: Image 1 (fdt-1)
223 11:44:30.517942 output: Description: mt8192-asurada-spherion-r0
224 11:44:30.517998 output: Created: Thu Jun 15 12:44:30 2023
225 11:44:30.518052 output: Type: Flat Device Tree
226 11:44:30.518105 output: Compression: uncompressed
227 11:44:30.518157 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:44:30.518210 output: Architecture: AArch64
229 11:44:30.518263 output: Hash algo: crc32
230 11:44:30.518315 output: Hash value: 1df858fa
231 11:44:30.518367 output: Image 2 (ramdisk-1)
232 11:44:30.518419 output: Description: unavailable
233 11:44:30.518470 output: Created: Thu Jun 15 12:44:30 2023
234 11:44:30.518523 output: Type: RAMDisk Image
235 11:44:30.518575 output: Compression: Unknown Compression
236 11:44:30.518627 output: Data Size: 40139190 Bytes = 39198.43 KiB = 38.28 MiB
237 11:44:30.518680 output: Architecture: AArch64
238 11:44:30.518732 output: OS: Linux
239 11:44:30.518785 output: Load Address: unavailable
240 11:44:30.518837 output: Entry Point: unavailable
241 11:44:30.518889 output: Hash algo: crc32
242 11:44:30.518940 output: Hash value: 4d54463a
243 11:44:30.518992 output: Default Configuration: 'conf-1'
244 11:44:30.519044 output: Configuration 0 (conf-1)
245 11:44:30.519096 output: Description: mt8192-asurada-spherion-r0
246 11:44:30.519148 output: Kernel: kernel-1
247 11:44:30.519200 output: Init Ramdisk: ramdisk-1
248 11:44:30.519252 output: FDT: fdt-1
249 11:44:30.519305 output: Loadables: kernel-1
250 11:44:30.519400 output:
251 11:44:30.519587 end: 1.5.8.1 prepare-fit (duration 00:00:23) [common]
252 11:44:30.519685 end: 1.5.8 prepare-kernel (duration 00:00:23) [common]
253 11:44:30.519790 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
254 11:44:30.519882 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:22) [common]
255 11:44:30.519957 No LXC device requested
256 11:44:30.520034 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:44:30.520123 start: 1.7 deploy-device-env (timeout 00:09:22) [common]
258 11:44:30.520199 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:44:30.520266 Checking files for TFTP limit of 4294967296 bytes.
260 11:44:30.520752 end: 1 tftp-deploy (duration 00:00:38) [common]
261 11:44:30.520858 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:44:30.520946 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:44:30.521067 substitutions:
264 11:44:30.521135 - {DTB}: 10742249/tftp-deploy-_g234_cb/dtb/mt8192-asurada-spherion-r0.dtb
265 11:44:30.521198 - {INITRD}: 10742249/tftp-deploy-_g234_cb/ramdisk/ramdisk.cpio.gz
266 11:44:30.521257 - {KERNEL}: 10742249/tftp-deploy-_g234_cb/kernel/Image
267 11:44:30.521313 - {LAVA_MAC}: None
268 11:44:30.521368 - {PRESEED_CONFIG}: None
269 11:44:30.521422 - {PRESEED_LOCAL}: None
270 11:44:30.521476 - {RAMDISK}: 10742249/tftp-deploy-_g234_cb/ramdisk/ramdisk.cpio.gz
271 11:44:30.521529 - {ROOT_PART}: None
272 11:44:30.521583 - {ROOT}: None
273 11:44:30.521663 - {SERVER_IP}: 192.168.201.1
274 11:44:30.521724 - {TEE}: None
275 11:44:30.521783 Parsed boot commands:
276 11:44:30.521836 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:44:30.521997 Parsed boot commands: tftpboot 192.168.201.1 10742249/tftp-deploy-_g234_cb/kernel/image.itb 10742249/tftp-deploy-_g234_cb/kernel/cmdline
278 11:44:30.522086 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:44:30.522168 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:44:30.522257 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:44:30.522342 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:44:30.522413 Not connected, no need to disconnect.
283 11:44:30.522486 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:44:30.522564 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:44:30.522639 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
286 11:44:30.525954 Setting prompt string to ['lava-test: # ']
287 11:44:30.526298 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:44:30.526404 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:44:30.526499 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:44:30.526591 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:44:30.526790 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 11:44:35.675875 >> Command sent successfully.
293 11:44:35.689839 Returned 0 in 5 seconds
294 11:44:35.791060 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:44:35.794351 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:44:35.795087 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:44:35.795754 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:44:35.796199 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:44:35.796572 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:44:35.797792 [Enter `^Ec?' for help]
302 11:44:35.953049
303 11:44:35.953594
304 11:44:35.953975 F0: 102B 0000
305 11:44:35.954300
306 11:44:35.954607 F3: 1001 0000 [0200]
307 11:44:35.956139
308 11:44:35.956573 F3: 1001 0000
309 11:44:35.956921
310 11:44:35.957238 F7: 102D 0000
311 11:44:35.957548
312 11:44:35.959639 F1: 0000 0000
313 11:44:35.960072
314 11:44:35.960414 V0: 0000 0000 [0001]
315 11:44:35.960774
316 11:44:35.962532 00: 0007 8000
317 11:44:35.962983
318 11:44:35.963329 01: 0000 0000
319 11:44:35.963724
320 11:44:35.966011 BP: 0C00 0209 [0000]
321 11:44:35.966450
322 11:44:35.966795 G0: 1182 0000
323 11:44:35.967114
324 11:44:35.969924 EC: 0000 0021 [4000]
325 11:44:35.970611
326 11:44:35.971142 S7: 0000 0000 [0000]
327 11:44:35.971748
328 11:44:35.972774 CC: 0000 0000 [0001]
329 11:44:35.973210
330 11:44:35.973555 T0: 0000 0040 [010F]
331 11:44:35.973875
332 11:44:35.974179 Jump to BL
333 11:44:35.976370
334 11:44:35.999871
335 11:44:36.000155
336 11:44:36.000346
337 11:44:36.006351 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:44:36.013490 ARM64: Exception handlers installed.
339 11:44:36.013669 ARM64: Testing exception
340 11:44:36.016935 ARM64: Done test exception
341 11:44:36.023627 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:44:36.033776 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:44:36.040488 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:44:36.050627 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:44:36.057304 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:44:36.066963 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:44:36.077688 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:44:36.084490 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:44:36.102590 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:44:36.105572 WDT: Last reset was cold boot
351 11:44:36.109194 SPI1(PAD0) initialized at 2873684 Hz
352 11:44:36.112629 SPI5(PAD0) initialized at 992727 Hz
353 11:44:36.115684 VBOOT: Loading verstage.
354 11:44:36.122238 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:44:36.126201 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:44:36.129291 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:44:36.132404 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:44:36.140573 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:44:36.146509 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:44:36.157478 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 11:44:36.158036
362 11:44:36.158520
363 11:44:36.167826 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:44:36.170945 ARM64: Exception handlers installed.
365 11:44:36.174115 ARM64: Testing exception
366 11:44:36.174648 ARM64: Done test exception
367 11:44:36.180923 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:44:36.184497 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:44:36.200386 Probing TPM: . done!
370 11:44:36.200910 TPM ready after 0 ms
371 11:44:36.207320 Connected to device vid:did:rid of 1ae0:0028:00
372 11:44:36.213921 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 11:44:36.273774 Initialized TPM device CR50 revision 0
374 11:44:36.284093 tlcl_send_startup: Startup return code is 0
375 11:44:36.284687 TPM: setup succeeded
376 11:44:36.295720 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:44:36.304509 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:44:36.316768 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:44:36.327059 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:44:36.329927 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:44:36.334105 in-header: 03 07 00 00 08 00 00 00
382 11:44:36.337718 in-data: aa e4 47 04 13 02 00 00
383 11:44:36.341533 Chrome EC: UHEPI supported
384 11:44:36.348116 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:44:36.352012 in-header: 03 ad 00 00 08 00 00 00
386 11:44:36.355583 in-data: 00 20 20 08 00 00 00 00
387 11:44:36.356012 Phase 1
388 11:44:36.358993 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:44:36.366720 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:44:36.370181 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:44:36.374100 Recovery requested (1009000e)
392 11:44:36.383431 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:44:36.389406 tlcl_extend: response is 0
394 11:44:36.401049 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:44:36.404594 tlcl_extend: response is 0
396 11:44:36.411802 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:44:36.430924 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:44:36.437486 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:44:36.437935
400 11:44:36.438276
401 11:44:36.448728 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:44:36.451772 ARM64: Exception handlers installed.
403 11:44:36.452350 ARM64: Testing exception
404 11:44:36.455021 ARM64: Done test exception
405 11:44:36.476556 pmic_efuse_setting: Set efuses in 11 msecs
406 11:44:36.479572 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:44:36.486268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:44:36.490019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:44:36.497245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:44:36.500236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:44:36.504047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:44:36.511377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:44:36.515066 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:44:36.518568 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:44:36.522640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:44:36.529466 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:44:36.533280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:44:36.537020 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:44:36.543917 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:44:36.547789 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:44:36.554767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:44:36.558488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:44:36.565819 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:44:36.572879 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:44:36.576422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:44:36.584469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:44:36.588073 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:44:36.595404 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:44:36.599156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:44:36.606541 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:44:36.610117 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:44:36.617812 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:44:36.621346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:44:36.624755 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:44:36.632327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:44:36.635799 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:44:36.639103 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:44:36.646679 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:44:36.650231 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:44:36.657653 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:44:36.661148 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:44:36.664965 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:44:36.672518 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:44:36.676436 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:44:36.679870 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:44:36.683382 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:44:36.687093 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:44:36.694513 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:44:36.698055 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:44:36.701725 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:44:36.705404 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:44:36.709293 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:44:36.712892 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:44:36.720352 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:44:36.724026 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:44:36.727663 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:44:36.731009 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:44:36.738722 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:44:36.749537 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:44:36.753481 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:44:36.760418 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:44:36.767750 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:44:36.774809 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:44:36.778806 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:44:36.781913 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:44:36.790210 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 11:44:36.793451 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:44:36.801408 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:44:36.805216 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:44:36.814068 [RTC]rtc_get_frequency_meter,154: input=15, output=789
471 11:44:36.823379 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 11:44:36.832998 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 11:44:36.842296 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 11:44:36.851871 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 11:44:36.860964 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 11:44:36.871344 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 11:44:36.875707 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 11:44:36.878824 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 11:44:36.886446 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:44:36.889986 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:44:36.893950 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:44:36.896992 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:44:36.900713 ADC[4]: Raw value=901697 ID=7
484 11:44:36.901154 ADC[3]: Raw value=213336 ID=1
485 11:44:36.904912 RAM Code: 0x71
486 11:44:36.908652 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:44:36.912005 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:44:36.923108 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:44:36.926917 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:44:36.930945 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:44:36.933998 in-header: 03 07 00 00 08 00 00 00
492 11:44:36.937898 in-data: aa e4 47 04 13 02 00 00
493 11:44:36.941417 Chrome EC: UHEPI supported
494 11:44:36.948750 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:44:36.952348 in-header: 03 ed 00 00 08 00 00 00
496 11:44:36.956033 in-data: 80 20 60 08 00 00 00 00
497 11:44:36.956326 MRC: failed to locate region type 0.
498 11:44:36.963473 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:44:36.967684 DRAM-K: Running full calibration
500 11:44:36.975327 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:44:36.975712 header.status = 0x0
502 11:44:36.978799 header.version = 0x6 (expected: 0x6)
503 11:44:36.982238 header.size = 0xd00 (expected: 0xd00)
504 11:44:36.982772 header.flags = 0x0
505 11:44:36.989840 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:44:37.008427 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 11:44:37.015951 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:44:37.019807 dram_init: ddr_geometry: 2
509 11:44:37.019995 [EMI] MDL number = 2
510 11:44:37.023334 [EMI] Get MDL freq = 0
511 11:44:37.023503 dram_init: ddr_type: 0
512 11:44:37.026529 is_discrete_lpddr4: 1
513 11:44:37.030253 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:44:37.030377
515 11:44:37.030480
516 11:44:37.030578 [Bian_co] ETT version 0.0.0.1
517 11:44:37.037724 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:44:37.037887
519 11:44:37.041506 dramc_set_vcore_voltage set vcore to 650000
520 11:44:37.041688 Read voltage for 800, 4
521 11:44:37.045150 Vio18 = 0
522 11:44:37.045313 Vcore = 650000
523 11:44:37.045459 Vdram = 0
524 11:44:37.048144 Vddq = 0
525 11:44:37.048271 Vmddr = 0
526 11:44:37.048375 dram_init: config_dvfs: 1
527 11:44:37.055037 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:44:37.058996 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:44:37.065517 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 11:44:37.068661 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 11:44:37.071806 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 11:44:37.075285 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 11:44:37.078860 MEM_TYPE=3, freq_sel=18
534 11:44:37.081834 sv_algorithm_assistance_LP4_1600
535 11:44:37.085310 ============ PULL DRAM RESETB DOWN ============
536 11:44:37.088736 ========== PULL DRAM RESETB DOWN end =========
537 11:44:37.094968 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:44:37.098619 ===================================
539 11:44:37.098906 LPDDR4 DRAM CONFIGURATION
540 11:44:37.101595 ===================================
541 11:44:37.105080 EX_ROW_EN[0] = 0x0
542 11:44:37.105361 EX_ROW_EN[1] = 0x0
543 11:44:37.108832 LP4Y_EN = 0x0
544 11:44:37.109146 WORK_FSP = 0x0
545 11:44:37.111924 WL = 0x2
546 11:44:37.115116 RL = 0x2
547 11:44:37.115434 BL = 0x2
548 11:44:37.118832 RPST = 0x0
549 11:44:37.119107 RD_PRE = 0x0
550 11:44:37.122058 WR_PRE = 0x1
551 11:44:37.122360 WR_PST = 0x0
552 11:44:37.125327 DBI_WR = 0x0
553 11:44:37.125557 DBI_RD = 0x0
554 11:44:37.128761 OTF = 0x1
555 11:44:37.131845 ===================================
556 11:44:37.135504 ===================================
557 11:44:37.135939 ANA top config
558 11:44:37.138454 ===================================
559 11:44:37.142240 DLL_ASYNC_EN = 0
560 11:44:37.145415 ALL_SLAVE_EN = 1
561 11:44:37.145658 NEW_RANK_MODE = 1
562 11:44:37.148403 DLL_IDLE_MODE = 1
563 11:44:37.152003 LP45_APHY_COMB_EN = 1
564 11:44:37.154927 TX_ODT_DIS = 1
565 11:44:37.155139 NEW_8X_MODE = 1
566 11:44:37.158718 ===================================
567 11:44:37.161580 ===================================
568 11:44:37.165186 data_rate = 1600
569 11:44:37.168471 CKR = 1
570 11:44:37.172079 DQ_P2S_RATIO = 8
571 11:44:37.174955 ===================================
572 11:44:37.178549 CA_P2S_RATIO = 8
573 11:44:37.182010 DQ_CA_OPEN = 0
574 11:44:37.182167 DQ_SEMI_OPEN = 0
575 11:44:37.184834 CA_SEMI_OPEN = 0
576 11:44:37.188208 CA_FULL_RATE = 0
577 11:44:37.191727 DQ_CKDIV4_EN = 1
578 11:44:37.195138 CA_CKDIV4_EN = 1
579 11:44:37.198383 CA_PREDIV_EN = 0
580 11:44:37.198540 PH8_DLY = 0
581 11:44:37.201890 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:44:37.205471 DQ_AAMCK_DIV = 4
583 11:44:37.208753 CA_AAMCK_DIV = 4
584 11:44:37.212123 CA_ADMCK_DIV = 4
585 11:44:37.212301 DQ_TRACK_CA_EN = 0
586 11:44:37.214996 CA_PICK = 800
587 11:44:37.218827 CA_MCKIO = 800
588 11:44:37.221889 MCKIO_SEMI = 0
589 11:44:37.225629 PLL_FREQ = 3068
590 11:44:37.229420 DQ_UI_PI_RATIO = 32
591 11:44:37.229589 CA_UI_PI_RATIO = 0
592 11:44:37.233248 ===================================
593 11:44:37.236867 ===================================
594 11:44:37.240038 memory_type:LPDDR4
595 11:44:37.240275 GP_NUM : 10
596 11:44:37.244406 SRAM_EN : 1
597 11:44:37.247412 MD32_EN : 0
598 11:44:37.247635 ===================================
599 11:44:37.251420 [ANA_INIT] >>>>>>>>>>>>>>
600 11:44:37.254942 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:44:37.258524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:44:37.262097 ===================================
603 11:44:37.265807 data_rate = 1600,PCW = 0X7600
604 11:44:37.266207 ===================================
605 11:44:37.272752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:44:37.275861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:44:37.282332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:44:37.286029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:44:37.288944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:44:37.292695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:44:37.295923 [ANA_INIT] flow start
612 11:44:37.299451 [ANA_INIT] PLL >>>>>>>>
613 11:44:37.299852 [ANA_INIT] PLL <<<<<<<<
614 11:44:37.302215 [ANA_INIT] MIDPI >>>>>>>>
615 11:44:37.305534 [ANA_INIT] MIDPI <<<<<<<<
616 11:44:37.305970 [ANA_INIT] DLL >>>>>>>>
617 11:44:37.309009 [ANA_INIT] flow end
618 11:44:37.312291 ============ LP4 DIFF to SE enter ============
619 11:44:37.315625 ============ LP4 DIFF to SE exit ============
620 11:44:37.319132 [ANA_INIT] <<<<<<<<<<<<<
621 11:44:37.322065 [Flow] Enable top DCM control >>>>>
622 11:44:37.325342 [Flow] Enable top DCM control <<<<<
623 11:44:37.329088 Enable DLL master slave shuffle
624 11:44:37.335911 ==============================================================
625 11:44:37.336343 Gating Mode config
626 11:44:37.342175 ==============================================================
627 11:44:37.342572 Config description:
628 11:44:37.351965 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:44:37.358774 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:44:37.365263 SELPH_MODE 0: By rank 1: By Phase
631 11:44:37.368917 ==============================================================
632 11:44:37.371932 GAT_TRACK_EN = 1
633 11:44:37.375946 RX_GATING_MODE = 2
634 11:44:37.378881 RX_GATING_TRACK_MODE = 2
635 11:44:37.382151 SELPH_MODE = 1
636 11:44:37.385682 PICG_EARLY_EN = 1
637 11:44:37.388732 VALID_LAT_VALUE = 1
638 11:44:37.395271 ==============================================================
639 11:44:37.398653 Enter into Gating configuration >>>>
640 11:44:37.402560 Exit from Gating configuration <<<<
641 11:44:37.402997 Enter into DVFS_PRE_config >>>>>
642 11:44:37.415520 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:44:37.418638 Exit from DVFS_PRE_config <<<<<
644 11:44:37.421847 Enter into PICG configuration >>>>
645 11:44:37.425723 Exit from PICG configuration <<<<
646 11:44:37.426290 [RX_INPUT] configuration >>>>>
647 11:44:37.429260 [RX_INPUT] configuration <<<<<
648 11:44:37.435770 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:44:37.438676 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:44:37.446306 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:44:37.452731 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:44:37.459979 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:44:37.466561 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:44:37.469482 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:44:37.473191 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:44:37.476376 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:44:37.483076 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:44:37.486781 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:44:37.489622 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:44:37.493095 ===================================
661 11:44:37.496646 LPDDR4 DRAM CONFIGURATION
662 11:44:37.499732 ===================================
663 11:44:37.500166 EX_ROW_EN[0] = 0x0
664 11:44:37.503204 EX_ROW_EN[1] = 0x0
665 11:44:37.503669 LP4Y_EN = 0x0
666 11:44:37.506655 WORK_FSP = 0x0
667 11:44:37.507085 WL = 0x2
668 11:44:37.509650 RL = 0x2
669 11:44:37.510086 BL = 0x2
670 11:44:37.512990 RPST = 0x0
671 11:44:37.516558 RD_PRE = 0x0
672 11:44:37.517022 WR_PRE = 0x1
673 11:44:37.520034 WR_PST = 0x0
674 11:44:37.520558 DBI_WR = 0x0
675 11:44:37.522984 DBI_RD = 0x0
676 11:44:37.523385 OTF = 0x1
677 11:44:37.526349 ===================================
678 11:44:37.529715 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:44:37.533395 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:44:37.539711 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:44:37.543097 ===================================
682 11:44:37.546398 LPDDR4 DRAM CONFIGURATION
683 11:44:37.549898 ===================================
684 11:44:37.550412 EX_ROW_EN[0] = 0x10
685 11:44:37.552968 EX_ROW_EN[1] = 0x0
686 11:44:37.553477 LP4Y_EN = 0x0
687 11:44:37.556556 WORK_FSP = 0x0
688 11:44:37.557080 WL = 0x2
689 11:44:37.559797 RL = 0x2
690 11:44:37.560273 BL = 0x2
691 11:44:37.563662 RPST = 0x0
692 11:44:37.564537 RD_PRE = 0x0
693 11:44:37.567029 WR_PRE = 0x1
694 11:44:37.567870 WR_PST = 0x0
695 11:44:37.570195 DBI_WR = 0x0
696 11:44:37.570627 DBI_RD = 0x0
697 11:44:37.573734 OTF = 0x1
698 11:44:37.576796 ===================================
699 11:44:37.583628 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:44:37.586704 nWR fixed to 40
701 11:44:37.590351 [ModeRegInit_LP4] CH0 RK0
702 11:44:37.590822 [ModeRegInit_LP4] CH0 RK1
703 11:44:37.593295 [ModeRegInit_LP4] CH1 RK0
704 11:44:37.596847 [ModeRegInit_LP4] CH1 RK1
705 11:44:37.597287 match AC timing 13
706 11:44:37.603751 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:44:37.606690 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:44:37.610207 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:44:37.616853 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:44:37.619754 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:44:37.620201 [EMI DOE] emi_dcm 0
712 11:44:37.626891 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:44:37.627389 ==
714 11:44:37.629686 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:44:37.633149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:44:37.633594 ==
717 11:44:37.640047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:44:37.643084 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:44:37.653603 [CA 0] Center 37 (7~68) winsize 62
720 11:44:37.657350 [CA 1] Center 37 (7~68) winsize 62
721 11:44:37.660365 [CA 2] Center 34 (4~65) winsize 62
722 11:44:37.663329 [CA 3] Center 34 (4~65) winsize 62
723 11:44:37.666937 [CA 4] Center 33 (3~64) winsize 62
724 11:44:37.670068 [CA 5] Center 33 (3~64) winsize 62
725 11:44:37.670443
726 11:44:37.673854 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 11:44:37.674219
728 11:44:37.677447 [CATrainingPosCal] consider 1 rank data
729 11:44:37.680322 u2DelayCellTimex100 = 270/100 ps
730 11:44:37.684139 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:44:37.687341 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 11:44:37.694017 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 11:44:37.696907 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:44:37.700414 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 11:44:37.704084 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:44:37.704518
737 11:44:37.707593 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:44:37.708039
739 11:44:37.710751 [CBTSetCACLKResult] CA Dly = 33
740 11:44:37.711192 CS Dly: 5 (0~36)
741 11:44:37.711674 ==
742 11:44:37.714267 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:44:37.720735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:44:37.721180 ==
745 11:44:37.723986 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:44:37.730363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:44:37.740203 [CA 0] Center 37 (7~68) winsize 62
748 11:44:37.742975 [CA 1] Center 37 (6~68) winsize 63
749 11:44:37.746390 [CA 2] Center 35 (4~66) winsize 63
750 11:44:37.750058 [CA 3] Center 35 (4~66) winsize 63
751 11:44:37.753397 [CA 4] Center 34 (4~64) winsize 61
752 11:44:37.756902 [CA 5] Center 33 (3~64) winsize 62
753 11:44:37.757344
754 11:44:37.760164 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:44:37.760607
756 11:44:37.763271 [CATrainingPosCal] consider 2 rank data
757 11:44:37.766877 u2DelayCellTimex100 = 270/100 ps
758 11:44:37.770113 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:44:37.773146 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:44:37.779971 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 11:44:37.783477 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:44:37.786568 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 11:44:37.790291 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:44:37.790747
765 11:44:37.793370 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:44:37.793838
767 11:44:37.797039 [CBTSetCACLKResult] CA Dly = 33
768 11:44:37.797400 CS Dly: 5 (0~37)
769 11:44:37.797719
770 11:44:37.800095 ----->DramcWriteLeveling(PI) begin...
771 11:44:37.800533 ==
772 11:44:37.803660 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:44:37.810844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:44:37.811278 ==
775 11:44:37.811656 Write leveling (Byte 0): 31 => 31
776 11:44:37.814501 Write leveling (Byte 1): 26 => 26
777 11:44:37.818217 DramcWriteLeveling(PI) end<-----
778 11:44:37.818645
779 11:44:37.819023 ==
780 11:44:37.821603 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:44:37.824952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:44:37.825388 ==
783 11:44:37.828972 [Gating] SW mode calibration
784 11:44:37.836007 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:44:37.842899 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:44:37.846429 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:44:37.849513 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 11:44:37.853181 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
789 11:44:37.859980 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:44:37.863387 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:44:37.866382 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:44:37.873351 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:44:37.876477 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:44:37.880109 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:44:37.886523 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:44:37.889907 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:44:37.893279 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:44:37.900118 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:44:37.903121 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:44:37.906204 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:44:37.913164 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:44:37.916245 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:44:37.919947 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:44:37.926656 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 11:44:37.929961 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 11:44:37.932950 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:44:37.936334 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:44:37.942832 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:44:37.946263 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:44:37.949672 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:44:37.956257 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:44:37.959909 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:44:37.962812 0 9 12 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 1)
814 11:44:37.969661 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
815 11:44:37.973087 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:44:37.976347 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:44:37.983326 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:44:37.986292 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:44:37.989863 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
820 11:44:37.996430 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
821 11:44:38.000070 0 10 12 | B1->B0 | 2c2c 2424 | 0 0 | (1 1) (1 0)
822 11:44:38.003159 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:44:38.009922 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:44:38.012722 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:44:38.016132 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:44:38.022971 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:44:38.026032 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:44:38.029602 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
829 11:44:38.032865 0 11 12 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
830 11:44:38.039608 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:44:38.042994 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:44:38.046331 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:44:38.052844 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:44:38.056244 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:44:38.059838 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 11:44:38.066358 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 11:44:38.069939 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
838 11:44:38.072916 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:44:38.079402 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:44:38.082919 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:44:38.085919 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:44:38.092564 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:44:38.096160 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:44:38.099757 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:44:38.106411 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:44:38.109560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:44:38.112610 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:44:38.119837 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:44:38.122761 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:44:38.126339 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:44:38.129511 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:44:38.136031 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 11:44:38.139340 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 11:44:38.142846 Total UI for P1: 0, mck2ui 16
855 11:44:38.146317 best dqsien dly found for B0: ( 0, 14, 8)
856 11:44:38.149850 Total UI for P1: 0, mck2ui 16
857 11:44:38.152677 best dqsien dly found for B1: ( 0, 14, 8)
858 11:44:38.156113 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 11:44:38.159707 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 11:44:38.159814
861 11:44:38.162610 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 11:44:38.166384 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:44:38.169457 [Gating] SW calibration Done
864 11:44:38.169572 ==
865 11:44:38.172990 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:44:38.175950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:44:38.176067 ==
868 11:44:38.179551 RX Vref Scan: 0
869 11:44:38.179680
870 11:44:38.182486 RX Vref 0 -> 0, step: 1
871 11:44:38.182570
872 11:44:38.186344 RX Delay -130 -> 252, step: 16
873 11:44:38.189271 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 11:44:38.192943 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
875 11:44:38.196147 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 11:44:38.199687 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 11:44:38.206417 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
878 11:44:38.209407 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
879 11:44:38.212541 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
880 11:44:38.215556 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
881 11:44:38.219122 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
882 11:44:38.225811 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 11:44:38.228933 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 11:44:38.232800 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
885 11:44:38.235924 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
886 11:44:38.238932 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
887 11:44:38.245943 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
888 11:44:38.249346 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
889 11:44:38.249459 ==
890 11:44:38.252749 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:44:38.255819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:44:38.255897 ==
893 11:44:38.259287 DQS Delay:
894 11:44:38.259387 DQS0 = 0, DQS1 = 0
895 11:44:38.259452 DQM Delay:
896 11:44:38.262248 DQM0 = 83, DQM1 = 77
897 11:44:38.262332 DQ Delay:
898 11:44:38.265685 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 11:44:38.269224 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
900 11:44:38.272380 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 11:44:38.275945 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
902 11:44:38.276027
903 11:44:38.276094
904 11:44:38.276156 ==
905 11:44:38.279366 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:44:38.283036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:44:38.285987 ==
908 11:44:38.286333
909 11:44:38.286651
910 11:44:38.286954 TX Vref Scan disable
911 11:44:38.289422 == TX Byte 0 ==
912 11:44:38.292568 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 11:44:38.296208 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 11:44:38.299204 == TX Byte 1 ==
915 11:44:38.302845 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
916 11:44:38.306450 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
917 11:44:38.309489 ==
918 11:44:38.313352 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:44:38.316440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:44:38.316895 ==
921 11:44:38.329357 TX Vref=22, minBit 12, minWin=26, winSum=435
922 11:44:38.332521 TX Vref=24, minBit 12, minWin=26, winSum=442
923 11:44:38.335561 TX Vref=26, minBit 12, minWin=26, winSum=444
924 11:44:38.339263 TX Vref=28, minBit 8, minWin=27, winSum=452
925 11:44:38.342356 TX Vref=30, minBit 10, minWin=27, winSum=448
926 11:44:38.349504 TX Vref=32, minBit 9, minWin=27, winSum=450
927 11:44:38.352808 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 28
928 11:44:38.353314
929 11:44:38.356286 Final TX Range 1 Vref 28
930 11:44:38.356922
931 11:44:38.357527 ==
932 11:44:38.359300 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:44:38.362904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:44:38.363560 ==
935 11:44:38.365801
936 11:44:38.366402
937 11:44:38.366785 TX Vref Scan disable
938 11:44:38.369331 == TX Byte 0 ==
939 11:44:38.372856 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 11:44:38.376588 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 11:44:38.379658 == TX Byte 1 ==
942 11:44:38.382838 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
943 11:44:38.386419 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
944 11:44:38.389385
945 11:44:38.389695 [DATLAT]
946 11:44:38.390006 Freq=800, CH0 RK0
947 11:44:38.390262
948 11:44:38.392581 DATLAT Default: 0xa
949 11:44:38.392773 0, 0xFFFF, sum = 0
950 11:44:38.396107 1, 0xFFFF, sum = 0
951 11:44:38.396303 2, 0xFFFF, sum = 0
952 11:44:38.399794 3, 0xFFFF, sum = 0
953 11:44:38.400017 4, 0xFFFF, sum = 0
954 11:44:38.402834 5, 0xFFFF, sum = 0
955 11:44:38.405841 6, 0xFFFF, sum = 0
956 11:44:38.406023 7, 0xFFFF, sum = 0
957 11:44:38.409469 8, 0xFFFF, sum = 0
958 11:44:38.409606 9, 0x0, sum = 1
959 11:44:38.409744 10, 0x0, sum = 2
960 11:44:38.412563 11, 0x0, sum = 3
961 11:44:38.412669 12, 0x0, sum = 4
962 11:44:38.416254 best_step = 10
963 11:44:38.416357
964 11:44:38.416439 ==
965 11:44:38.419285 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:44:38.422470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:44:38.422547 ==
968 11:44:38.426171 RX Vref Scan: 1
969 11:44:38.426258
970 11:44:38.426320 Set Vref Range= 32 -> 127
971 11:44:38.426380
972 11:44:38.429155 RX Vref 32 -> 127, step: 1
973 11:44:38.429225
974 11:44:38.432564 RX Delay -95 -> 252, step: 8
975 11:44:38.432641
976 11:44:38.436330 Set Vref, RX VrefLevel [Byte0]: 32
977 11:44:38.439381 [Byte1]: 32
978 11:44:38.439469
979 11:44:38.442926 Set Vref, RX VrefLevel [Byte0]: 33
980 11:44:38.446615 [Byte1]: 33
981 11:44:38.446701
982 11:44:38.450228 Set Vref, RX VrefLevel [Byte0]: 34
983 11:44:38.453327 [Byte1]: 34
984 11:44:38.457489
985 11:44:38.457602 Set Vref, RX VrefLevel [Byte0]: 35
986 11:44:38.460511 [Byte1]: 35
987 11:44:38.465154
988 11:44:38.465277 Set Vref, RX VrefLevel [Byte0]: 36
989 11:44:38.468112 [Byte1]: 36
990 11:44:38.472832
991 11:44:38.473037 Set Vref, RX VrefLevel [Byte0]: 37
992 11:44:38.475841 [Byte1]: 37
993 11:44:38.480037
994 11:44:38.480207 Set Vref, RX VrefLevel [Byte0]: 38
995 11:44:38.483658 [Byte1]: 38
996 11:44:38.487694
997 11:44:38.490644 Set Vref, RX VrefLevel [Byte0]: 39
998 11:44:38.490899 [Byte1]: 39
999 11:44:38.495683
1000 11:44:38.495994 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:44:38.499180 [Byte1]: 40
1002 11:44:38.503582
1003 11:44:38.504021 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:44:38.506832 [Byte1]: 41
1005 11:44:38.510788
1006 11:44:38.511238 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:44:38.513906 [Byte1]: 42
1008 11:44:38.518151
1009 11:44:38.518605 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:44:38.521915 [Byte1]: 43
1011 11:44:38.525562
1012 11:44:38.526009 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:44:38.529164 [Byte1]: 44
1014 11:44:38.533583
1015 11:44:38.534032 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:44:38.536431 [Byte1]: 45
1017 11:44:38.541111
1018 11:44:38.541560 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:44:38.544197 [Byte1]: 46
1020 11:44:38.548605
1021 11:44:38.549053 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:44:38.552207 [Byte1]: 47
1023 11:44:38.556501
1024 11:44:38.556952 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:44:38.559843 [Byte1]: 48
1026 11:44:38.563999
1027 11:44:38.564437 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:44:38.566963 [Byte1]: 49
1029 11:44:38.571442
1030 11:44:38.571885 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:44:38.574473 [Byte1]: 50
1032 11:44:38.579035
1033 11:44:38.579645 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:44:38.582266 [Byte1]: 51
1035 11:44:38.586767
1036 11:44:38.587201 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:44:38.589954 [Byte1]: 52
1038 11:44:38.594214
1039 11:44:38.594642 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:44:38.597795 [Byte1]: 53
1041 11:44:38.601873
1042 11:44:38.602304 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:44:38.604913 [Byte1]: 54
1044 11:44:38.609291
1045 11:44:38.609734 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:44:38.612610 [Byte1]: 55
1047 11:44:38.617176
1048 11:44:38.617620 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:44:38.620339 [Byte1]: 56
1050 11:44:38.624615
1051 11:44:38.625057 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:44:38.627752 [Byte1]: 57
1053 11:44:38.632038
1054 11:44:38.632481 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:44:38.635684 [Byte1]: 58
1056 11:44:38.639821
1057 11:44:38.640415 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:44:38.642856 [Byte1]: 59
1059 11:44:38.647592
1060 11:44:38.648048 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:44:38.650567 [Byte1]: 60
1062 11:44:38.655008
1063 11:44:38.655570 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:44:38.658090 [Byte1]: 61
1065 11:44:38.662485
1066 11:44:38.663086 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:44:38.665756 [Byte1]: 62
1068 11:44:38.670038
1069 11:44:38.670766 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:44:38.673563 [Byte1]: 63
1071 11:44:38.677679
1072 11:44:38.678101 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:44:38.681296 [Byte1]: 64
1074 11:44:38.685215
1075 11:44:38.685643 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:44:38.688837 [Byte1]: 65
1077 11:44:38.693161
1078 11:44:38.693615 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:44:38.696263 [Byte1]: 66
1080 11:44:38.700344
1081 11:44:38.700844 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:44:38.703873 [Byte1]: 67
1083 11:44:38.708101
1084 11:44:38.708580 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:44:38.714446 [Byte1]: 68
1086 11:44:38.714888
1087 11:44:38.718231 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:44:38.721663 [Byte1]: 69
1089 11:44:38.722313
1090 11:44:38.724387 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:44:38.728135 [Byte1]: 70
1092 11:44:38.728644
1093 11:44:38.731071 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:44:38.734735 [Byte1]: 71
1095 11:44:38.738475
1096 11:44:38.738913 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:44:38.741632 [Byte1]: 72
1098 11:44:38.745994
1099 11:44:38.746560 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:44:38.749232 [Byte1]: 73
1101 11:44:38.753429
1102 11:44:38.753959 Set Vref, RX VrefLevel [Byte0]: 74
1103 11:44:38.757126 [Byte1]: 74
1104 11:44:38.761080
1105 11:44:38.761520 Set Vref, RX VrefLevel [Byte0]: 75
1106 11:44:38.764418 [Byte1]: 75
1107 11:44:38.769201
1108 11:44:38.769626 Set Vref, RX VrefLevel [Byte0]: 76
1109 11:44:38.772198 [Byte1]: 76
1110 11:44:38.776670
1111 11:44:38.777092 Final RX Vref Byte 0 = 60 to rank0
1112 11:44:38.779588 Final RX Vref Byte 1 = 59 to rank0
1113 11:44:38.783048 Final RX Vref Byte 0 = 60 to rank1
1114 11:44:38.786391 Final RX Vref Byte 1 = 59 to rank1==
1115 11:44:38.790068 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 11:44:38.796392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 11:44:38.796904 ==
1118 11:44:38.797240 DQS Delay:
1119 11:44:38.797551 DQS0 = 0, DQS1 = 0
1120 11:44:38.800022 DQM Delay:
1121 11:44:38.800484 DQM0 = 87, DQM1 = 79
1122 11:44:38.803102 DQ Delay:
1123 11:44:38.806558 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 11:44:38.807033 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1125 11:44:38.810127 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1126 11:44:38.813689 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1127 11:44:38.816791
1128 11:44:38.817213
1129 11:44:38.823466 [DQSOSCAuto] RK0, (LSB)MR18= 0x230a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
1130 11:44:38.826282 CH0 RK0: MR19=606, MR18=230A
1131 11:44:38.833705 CH0_RK0: MR19=0x606, MR18=0x230A, DQSOSC=401, MR23=63, INC=91, DEC=61
1132 11:44:38.834131
1133 11:44:38.836825 ----->DramcWriteLeveling(PI) begin...
1134 11:44:38.837359 ==
1135 11:44:38.839812 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 11:44:38.843574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 11:44:38.844132 ==
1138 11:44:38.847136 Write leveling (Byte 0): 30 => 30
1139 11:44:38.850164 Write leveling (Byte 1): 26 => 26
1140 11:44:38.853786 DramcWriteLeveling(PI) end<-----
1141 11:44:38.854214
1142 11:44:38.854549 ==
1143 11:44:38.857018 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 11:44:38.860049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 11:44:38.860485 ==
1146 11:44:38.863099 [Gating] SW mode calibration
1147 11:44:38.869922 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 11:44:38.876497 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 11:44:38.880152 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 11:44:38.883257 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 11:44:38.930885 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 11:44:38.931401 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:44:38.932081 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:44:38.932429 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:44:38.932739 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:44:38.933037 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:44:38.933334 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:44:38.933625 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:44:38.933913 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:44:38.934259 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:44:38.975176 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:44:38.975726 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:44:38.976084 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:44:38.976720 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:44:38.977060 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:44:38.977374 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 11:44:38.977675 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1168 11:44:38.977966 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1169 11:44:38.978257 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:44:38.978545 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:44:38.978832 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:44:39.017205 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:44:39.018203 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:44:39.018602 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1175 11:44:39.018936 0 9 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
1176 11:44:39.019254 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1177 11:44:39.019596 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 11:44:39.019899 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 11:44:39.020191 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 11:44:39.021612 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 11:44:39.022045 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1182 11:44:39.024795 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1183 11:44:39.027837 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 1) (1 1)
1184 11:44:39.034702 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1185 11:44:39.038017 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:44:39.041683 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:44:39.048476 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:44:39.051290 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:44:39.055067 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:44:39.061719 0 11 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
1191 11:44:39.065628 0 11 8 | B1->B0 | 2e2e 4444 | 0 0 | (0 0) (0 0)
1192 11:44:39.069101 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1193 11:44:39.073001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 11:44:39.076671 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 11:44:39.083340 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 11:44:39.086327 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:44:39.089914 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:44:39.093554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 11:44:39.099984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 11:44:39.103689 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:44:39.106593 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:44:39.113791 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:44:39.116780 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:44:39.120144 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:44:39.126925 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:44:39.130058 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:44:39.134008 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:44:39.140446 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:44:39.143870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:44:39.147275 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:44:39.153446 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:44:39.157170 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:44:39.160283 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:44:39.167097 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 11:44:39.169994 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 11:44:39.173649 Total UI for P1: 0, mck2ui 16
1217 11:44:39.176743 best dqsien dly found for B0: ( 0, 14, 4)
1218 11:44:39.180498 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 11:44:39.183485 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 11:44:39.187254 Total UI for P1: 0, mck2ui 16
1221 11:44:39.190332 best dqsien dly found for B1: ( 0, 14, 10)
1222 11:44:39.193996 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 11:44:39.200199 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1224 11:44:39.200763
1225 11:44:39.203414 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 11:44:39.206749 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1227 11:44:39.210278 [Gating] SW calibration Done
1228 11:44:39.210707 ==
1229 11:44:39.213790 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 11:44:39.217171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 11:44:39.217752 ==
1232 11:44:39.218298 RX Vref Scan: 0
1233 11:44:39.220250
1234 11:44:39.220675 RX Vref 0 -> 0, step: 1
1235 11:44:39.221019
1236 11:44:39.223206 RX Delay -130 -> 252, step: 16
1237 11:44:39.226616 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1238 11:44:39.230555 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1239 11:44:39.236537 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1240 11:44:39.240393 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1241 11:44:39.243514 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1242 11:44:39.246537 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1243 11:44:39.249830 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1244 11:44:39.256746 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1245 11:44:39.260407 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1246 11:44:39.263470 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1247 11:44:39.266533 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 11:44:39.270138 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1249 11:44:39.276796 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1250 11:44:39.280315 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1251 11:44:39.283339 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1252 11:44:39.286916 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1253 11:44:39.287538 ==
1254 11:44:39.290106 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 11:44:39.296697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 11:44:39.297225 ==
1257 11:44:39.297692 DQS Delay:
1258 11:44:39.299761 DQS0 = 0, DQS1 = 0
1259 11:44:39.300250 DQM Delay:
1260 11:44:39.300701 DQM0 = 87, DQM1 = 77
1261 11:44:39.303500 DQ Delay:
1262 11:44:39.307017 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1263 11:44:39.310387 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1264 11:44:39.313501 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1265 11:44:39.316929 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1266 11:44:39.317428
1267 11:44:39.317885
1268 11:44:39.318326 ==
1269 11:44:39.320384 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 11:44:39.323525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 11:44:39.324084 ==
1272 11:44:39.324560
1273 11:44:39.325084
1274 11:44:39.326976 TX Vref Scan disable
1275 11:44:39.327497 == TX Byte 0 ==
1276 11:44:39.333612 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1277 11:44:39.336768 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1278 11:44:39.337330 == TX Byte 1 ==
1279 11:44:39.343336 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1280 11:44:39.346858 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1281 11:44:39.347287 ==
1282 11:44:39.349903 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 11:44:39.353402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 11:44:39.354164 ==
1285 11:44:39.367982 TX Vref=22, minBit 9, minWin=26, winSum=437
1286 11:44:39.371032 TX Vref=24, minBit 9, minWin=26, winSum=444
1287 11:44:39.374779 TX Vref=26, minBit 9, minWin=26, winSum=444
1288 11:44:39.377957 TX Vref=28, minBit 9, minWin=27, winSum=448
1289 11:44:39.381379 TX Vref=30, minBit 12, minWin=27, winSum=451
1290 11:44:39.388174 TX Vref=32, minBit 9, minWin=27, winSum=447
1291 11:44:39.391211 [TxChooseVref] Worse bit 12, Min win 27, Win sum 451, Final Vref 30
1292 11:44:39.391783
1293 11:44:39.394840 Final TX Range 1 Vref 30
1294 11:44:39.395324
1295 11:44:39.395811 ==
1296 11:44:39.397865 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 11:44:39.401297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 11:44:39.401878 ==
1299 11:44:39.404941
1300 11:44:39.405482
1301 11:44:39.405952 TX Vref Scan disable
1302 11:44:39.408497 == TX Byte 0 ==
1303 11:44:39.411858 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1304 11:44:39.418111 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1305 11:44:39.418692 == TX Byte 1 ==
1306 11:44:39.421571 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1307 11:44:39.428034 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1308 11:44:39.428278
1309 11:44:39.428457 [DATLAT]
1310 11:44:39.428631 Freq=800, CH0 RK1
1311 11:44:39.428759
1312 11:44:39.431134 DATLAT Default: 0xa
1313 11:44:39.431316 0, 0xFFFF, sum = 0
1314 11:44:39.434659 1, 0xFFFF, sum = 0
1315 11:44:39.434843 2, 0xFFFF, sum = 0
1316 11:44:39.437616 3, 0xFFFF, sum = 0
1317 11:44:39.437773 4, 0xFFFF, sum = 0
1318 11:44:39.441540 5, 0xFFFF, sum = 0
1319 11:44:39.444672 6, 0xFFFF, sum = 0
1320 11:44:39.445102 7, 0xFFFF, sum = 0
1321 11:44:39.448365 8, 0xFFFF, sum = 0
1322 11:44:39.448796 9, 0x0, sum = 1
1323 11:44:39.449136 10, 0x0, sum = 2
1324 11:44:39.451319 11, 0x0, sum = 3
1325 11:44:39.451721 12, 0x0, sum = 4
1326 11:44:39.454963 best_step = 10
1327 11:44:39.455344
1328 11:44:39.455703 ==
1329 11:44:39.457928 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 11:44:39.461557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 11:44:39.462074 ==
1332 11:44:39.464596 RX Vref Scan: 0
1333 11:44:39.464945
1334 11:44:39.465241 RX Vref 0 -> 0, step: 1
1335 11:44:39.465532
1336 11:44:39.468135 RX Delay -95 -> 252, step: 8
1337 11:44:39.474971 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1338 11:44:39.478004 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1339 11:44:39.481772 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1340 11:44:39.484730 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1341 11:44:39.488279 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1342 11:44:39.495203 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1343 11:44:39.498265 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1344 11:44:39.501957 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1345 11:44:39.504840 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1346 11:44:39.508792 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1347 11:44:39.515093 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1348 11:44:39.518260 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1349 11:44:39.521793 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1350 11:44:39.524977 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1351 11:44:39.528574 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1352 11:44:39.534828 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1353 11:44:39.535342 ==
1354 11:44:39.538197 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 11:44:39.541746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 11:44:39.542242 ==
1357 11:44:39.542694 DQS Delay:
1358 11:44:39.544745 DQS0 = 0, DQS1 = 0
1359 11:44:39.545452 DQM Delay:
1360 11:44:39.548278 DQM0 = 87, DQM1 = 78
1361 11:44:39.548987 DQ Delay:
1362 11:44:39.551197 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1363 11:44:39.554860 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1364 11:44:39.558063 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1365 11:44:39.561563 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1366 11:44:39.561912
1367 11:44:39.562221
1368 11:44:39.567914 [DQSOSCAuto] RK1, (LSB)MR18= 0x3019, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1369 11:44:39.571567 CH0 RK1: MR19=606, MR18=3019
1370 11:44:39.578266 CH0_RK1: MR19=0x606, MR18=0x3019, DQSOSC=397, MR23=63, INC=93, DEC=62
1371 11:44:39.581282 [RxdqsGatingPostProcess] freq 800
1372 11:44:39.588116 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 11:44:39.591542 Pre-setting of DQS Precalculation
1374 11:44:39.594705 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 11:44:39.595086 ==
1376 11:44:39.598269 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 11:44:39.601333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 11:44:39.601840 ==
1379 11:44:39.608267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 11:44:39.615137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 11:44:39.622795 [CA 0] Center 36 (6~66) winsize 61
1382 11:44:39.626472 [CA 1] Center 36 (6~66) winsize 61
1383 11:44:39.629507 [CA 2] Center 34 (4~65) winsize 62
1384 11:44:39.633264 [CA 3] Center 34 (3~65) winsize 63
1385 11:44:39.636668 [CA 4] Center 34 (3~65) winsize 63
1386 11:44:39.639971 [CA 5] Center 33 (3~64) winsize 62
1387 11:44:39.640691
1388 11:44:39.643187 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 11:44:39.643653
1390 11:44:39.646129 [CATrainingPosCal] consider 1 rank data
1391 11:44:39.649634 u2DelayCellTimex100 = 270/100 ps
1392 11:44:39.652789 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 11:44:39.656373 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1394 11:44:39.663067 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 11:44:39.665940 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1396 11:44:39.669552 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1397 11:44:39.672660 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 11:44:39.673055
1399 11:44:39.676337 CA PerBit enable=1, Macro0, CA PI delay=33
1400 11:44:39.676691
1401 11:44:39.679854 [CBTSetCACLKResult] CA Dly = 33
1402 11:44:39.680212 CS Dly: 4 (0~35)
1403 11:44:39.680517 ==
1404 11:44:39.682856 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 11:44:39.689691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 11:44:39.690124 ==
1407 11:44:39.693284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 11:44:39.699774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 11:44:39.709055 [CA 0] Center 36 (6~66) winsize 61
1410 11:44:39.712146 [CA 1] Center 36 (6~66) winsize 61
1411 11:44:39.715440 [CA 2] Center 34 (4~64) winsize 61
1412 11:44:39.718861 [CA 3] Center 33 (3~64) winsize 62
1413 11:44:39.722613 [CA 4] Center 34 (4~65) winsize 62
1414 11:44:39.726187 [CA 5] Center 33 (3~64) winsize 62
1415 11:44:39.726644
1416 11:44:39.729528 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1417 11:44:39.730089
1418 11:44:39.733175 [CATrainingPosCal] consider 2 rank data
1419 11:44:39.736905 u2DelayCellTimex100 = 270/100 ps
1420 11:44:39.740908 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 11:44:39.744396 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1422 11:44:39.748151 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1423 11:44:39.751572 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 11:44:39.754982 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1425 11:44:39.759213 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 11:44:39.759846
1427 11:44:39.762321 CA PerBit enable=1, Macro0, CA PI delay=33
1428 11:44:39.762881
1429 11:44:39.766064 [CBTSetCACLKResult] CA Dly = 33
1430 11:44:39.766669 CS Dly: 5 (0~37)
1431 11:44:39.767197
1432 11:44:39.769247 ----->DramcWriteLeveling(PI) begin...
1433 11:44:39.769825 ==
1434 11:44:39.772427 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 11:44:39.778880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 11:44:39.779458 ==
1437 11:44:39.781849 Write leveling (Byte 0): 26 => 26
1438 11:44:39.785569 Write leveling (Byte 1): 30 => 30
1439 11:44:39.788798 DramcWriteLeveling(PI) end<-----
1440 11:44:39.789357
1441 11:44:39.789838 ==
1442 11:44:39.792382 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:44:39.795336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:44:39.795792 ==
1445 11:44:39.798959 [Gating] SW mode calibration
1446 11:44:39.805881 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 11:44:39.808939 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 11:44:39.815404 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1449 11:44:39.818631 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 11:44:39.822474 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 11:44:39.828659 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:44:39.832152 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:44:39.835714 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:44:39.842468 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:44:39.845920 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:44:39.848797 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:44:39.855617 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:44:39.858531 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1459 11:44:39.861938 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:44:39.868524 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:44:39.872219 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:44:39.875122 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:44:39.881636 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:44:39.885355 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:44:39.888578 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:44:39.895260 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1467 11:44:39.899025 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:44:39.901996 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:44:39.905530 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:44:39.912261 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1471 11:44:39.915329 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:44:39.918879 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:44:39.925759 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:44:39.929196 0 9 8 | B1->B0 | 2424 2626 | 1 1 | (1 1) (1 1)
1475 11:44:39.932394 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 11:44:39.938812 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1477 11:44:39.942337 0 9 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1478 11:44:39.945992 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 11:44:39.952357 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 11:44:39.955423 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:44:39.959082 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1482 11:44:39.965503 0 10 8 | B1->B0 | 3030 3232 | 0 0 | (0 1) (0 1)
1483 11:44:39.968667 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:44:39.972010 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1485 11:44:39.978774 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1486 11:44:39.981953 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1487 11:44:39.985456 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:44:39.992201 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:44:39.995158 0 11 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1490 11:44:39.998986 0 11 8 | B1->B0 | 3939 3939 | 0 0 | (0 0) (1 1)
1491 11:44:40.005614 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 11:44:40.008729 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 11:44:40.012028 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 11:44:40.018916 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 11:44:40.021794 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 11:44:40.025485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:44:40.032258 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 11:44:40.035797 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1499 11:44:40.038887 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:44:40.041657 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:44:40.048081 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:44:40.051640 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:44:40.054522 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:44:40.061713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:44:40.064804 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:44:40.068063 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:44:40.074957 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:44:40.078262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:44:40.081147 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:44:40.088413 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:44:40.091193 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:44:40.094852 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:44:40.101551 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:44:40.104652 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1515 11:44:40.108234 Total UI for P1: 0, mck2ui 16
1516 11:44:40.111405 best dqsien dly found for B1: ( 0, 14, 6)
1517 11:44:40.114883 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 11:44:40.117853 Total UI for P1: 0, mck2ui 16
1519 11:44:40.121620 best dqsien dly found for B0: ( 0, 14, 8)
1520 11:44:40.124692 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1521 11:44:40.128272 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1522 11:44:40.128672
1523 11:44:40.134941 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1524 11:44:40.138342 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 11:44:40.139000 [Gating] SW calibration Done
1526 11:44:40.141013 ==
1527 11:44:40.141405 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 11:44:40.147818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 11:44:40.148263 ==
1530 11:44:40.148703 RX Vref Scan: 0
1531 11:44:40.149217
1532 11:44:40.151178 RX Vref 0 -> 0, step: 1
1533 11:44:40.151749
1534 11:44:40.154643 RX Delay -130 -> 252, step: 16
1535 11:44:40.158218 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1536 11:44:40.161167 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1537 11:44:40.164710 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1538 11:44:40.171252 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1539 11:44:40.174741 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1540 11:44:40.177652 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1541 11:44:40.181108 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1542 11:44:40.184742 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1543 11:44:40.191059 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1544 11:44:40.194727 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1545 11:44:40.197672 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1546 11:44:40.201274 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1547 11:44:40.204431 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1548 11:44:40.211109 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1549 11:44:40.214058 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1550 11:44:40.217769 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1551 11:44:40.218260 ==
1552 11:44:40.220743 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 11:44:40.224319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 11:44:40.227867 ==
1555 11:44:40.228300 DQS Delay:
1556 11:44:40.228759 DQS0 = 0, DQS1 = 0
1557 11:44:40.231034 DQM Delay:
1558 11:44:40.231586 DQM0 = 83, DQM1 = 76
1559 11:44:40.234069 DQ Delay:
1560 11:44:40.237661 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1561 11:44:40.238093 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1562 11:44:40.240777 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1563 11:44:40.244680 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1564 11:44:40.247454
1565 11:44:40.247880
1566 11:44:40.248219 ==
1567 11:44:40.250538 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 11:44:40.254052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 11:44:40.254618 ==
1570 11:44:40.255106
1571 11:44:40.255694
1572 11:44:40.257255 TX Vref Scan disable
1573 11:44:40.257765 == TX Byte 0 ==
1574 11:44:40.264324 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 11:44:40.267645 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 11:44:40.268195 == TX Byte 1 ==
1577 11:44:40.274297 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1578 11:44:40.277223 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1579 11:44:40.277658 ==
1580 11:44:40.280627 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 11:44:40.283816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 11:44:40.284304 ==
1583 11:44:40.298039 TX Vref=22, minBit 11, minWin=26, winSum=437
1584 11:44:40.301588 TX Vref=24, minBit 11, minWin=26, winSum=443
1585 11:44:40.304804 TX Vref=26, minBit 7, minWin=27, winSum=444
1586 11:44:40.308369 TX Vref=28, minBit 0, minWin=28, winSum=451
1587 11:44:40.311420 TX Vref=30, minBit 2, minWin=28, winSum=455
1588 11:44:40.315141 TX Vref=32, minBit 9, minWin=27, winSum=456
1589 11:44:40.321655 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
1590 11:44:40.322219
1591 11:44:40.325193 Final TX Range 1 Vref 30
1592 11:44:40.325625
1593 11:44:40.325962 ==
1594 11:44:40.328195 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 11:44:40.331940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 11:44:40.332394 ==
1597 11:44:40.332730
1598 11:44:40.333043
1599 11:44:40.334788 TX Vref Scan disable
1600 11:44:40.338295 == TX Byte 0 ==
1601 11:44:40.341214 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1602 11:44:40.344893 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1603 11:44:40.347815 == TX Byte 1 ==
1604 11:44:40.351499 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1605 11:44:40.354568 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1606 11:44:40.354681
1607 11:44:40.358194 [DATLAT]
1608 11:44:40.358302 Freq=800, CH1 RK0
1609 11:44:40.358398
1610 11:44:40.361750 DATLAT Default: 0xa
1611 11:44:40.361837 0, 0xFFFF, sum = 0
1612 11:44:40.364815 1, 0xFFFF, sum = 0
1613 11:44:40.364914 2, 0xFFFF, sum = 0
1614 11:44:40.367900 3, 0xFFFF, sum = 0
1615 11:44:40.368000 4, 0xFFFF, sum = 0
1616 11:44:40.371204 5, 0xFFFF, sum = 0
1617 11:44:40.371283 6, 0xFFFF, sum = 0
1618 11:44:40.374578 7, 0xFFFF, sum = 0
1619 11:44:40.374666 8, 0xFFFF, sum = 0
1620 11:44:40.377941 9, 0x0, sum = 1
1621 11:44:40.378072 10, 0x0, sum = 2
1622 11:44:40.381617 11, 0x0, sum = 3
1623 11:44:40.381738 12, 0x0, sum = 4
1624 11:44:40.384468 best_step = 10
1625 11:44:40.384552
1626 11:44:40.384619 ==
1627 11:44:40.387980 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 11:44:40.391542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 11:44:40.391627 ==
1630 11:44:40.395085 RX Vref Scan: 1
1631 11:44:40.395170
1632 11:44:40.395238 Set Vref Range= 32 -> 127
1633 11:44:40.395302
1634 11:44:40.398018 RX Vref 32 -> 127, step: 1
1635 11:44:40.398102
1636 11:44:40.401580 RX Delay -95 -> 252, step: 8
1637 11:44:40.401657
1638 11:44:40.404440 Set Vref, RX VrefLevel [Byte0]: 32
1639 11:44:40.408173 [Byte1]: 32
1640 11:44:40.408258
1641 11:44:40.411177 Set Vref, RX VrefLevel [Byte0]: 33
1642 11:44:40.414924 [Byte1]: 33
1643 11:44:40.418067
1644 11:44:40.418147 Set Vref, RX VrefLevel [Byte0]: 34
1645 11:44:40.421093 [Byte1]: 34
1646 11:44:40.425368
1647 11:44:40.425444 Set Vref, RX VrefLevel [Byte0]: 35
1648 11:44:40.428890 [Byte1]: 35
1649 11:44:40.433076
1650 11:44:40.433154 Set Vref, RX VrefLevel [Byte0]: 36
1651 11:44:40.436741 [Byte1]: 36
1652 11:44:40.440998
1653 11:44:40.441074 Set Vref, RX VrefLevel [Byte0]: 37
1654 11:44:40.444164 [Byte1]: 37
1655 11:44:40.448585
1656 11:44:40.448667 Set Vref, RX VrefLevel [Byte0]: 38
1657 11:44:40.451576 [Byte1]: 38
1658 11:44:40.455785
1659 11:44:40.455899 Set Vref, RX VrefLevel [Byte0]: 39
1660 11:44:40.459496 [Byte1]: 39
1661 11:44:40.463478
1662 11:44:40.463593 Set Vref, RX VrefLevel [Byte0]: 40
1663 11:44:40.466967 [Byte1]: 40
1664 11:44:40.471344
1665 11:44:40.471472 Set Vref, RX VrefLevel [Byte0]: 41
1666 11:44:40.474332 [Byte1]: 41
1667 11:44:40.478947
1668 11:44:40.479018 Set Vref, RX VrefLevel [Byte0]: 42
1669 11:44:40.482159 [Byte1]: 42
1670 11:44:40.486249
1671 11:44:40.486323 Set Vref, RX VrefLevel [Byte0]: 43
1672 11:44:40.489689 [Byte1]: 43
1673 11:44:40.494337
1674 11:44:40.494411 Set Vref, RX VrefLevel [Byte0]: 44
1675 11:44:40.497261 [Byte1]: 44
1676 11:44:40.501382
1677 11:44:40.501461 Set Vref, RX VrefLevel [Byte0]: 45
1678 11:44:40.504957 [Byte1]: 45
1679 11:44:40.508957
1680 11:44:40.509030 Set Vref, RX VrefLevel [Byte0]: 46
1681 11:44:40.515760 [Byte1]: 46
1682 11:44:40.515847
1683 11:44:40.518846 Set Vref, RX VrefLevel [Byte0]: 47
1684 11:44:40.522580 [Byte1]: 47
1685 11:44:40.522652
1686 11:44:40.525524 Set Vref, RX VrefLevel [Byte0]: 48
1687 11:44:40.529158 [Byte1]: 48
1688 11:44:40.529236
1689 11:44:40.532591 Set Vref, RX VrefLevel [Byte0]: 49
1690 11:44:40.535650 [Byte1]: 49
1691 11:44:40.539901
1692 11:44:40.539982 Set Vref, RX VrefLevel [Byte0]: 50
1693 11:44:40.542838 [Byte1]: 50
1694 11:44:40.547109
1695 11:44:40.547180 Set Vref, RX VrefLevel [Byte0]: 51
1696 11:44:40.550192 [Byte1]: 51
1697 11:44:40.554520
1698 11:44:40.554593 Set Vref, RX VrefLevel [Byte0]: 52
1699 11:44:40.558092 [Byte1]: 52
1700 11:44:40.562413
1701 11:44:40.562487 Set Vref, RX VrefLevel [Byte0]: 53
1702 11:44:40.565523 [Byte1]: 53
1703 11:44:40.569792
1704 11:44:40.569868 Set Vref, RX VrefLevel [Byte0]: 54
1705 11:44:40.573417 [Byte1]: 54
1706 11:44:40.577856
1707 11:44:40.577945 Set Vref, RX VrefLevel [Byte0]: 55
1708 11:44:40.581144 [Byte1]: 55
1709 11:44:40.585258
1710 11:44:40.585364 Set Vref, RX VrefLevel [Byte0]: 56
1711 11:44:40.588427 [Byte1]: 56
1712 11:44:40.592924
1713 11:44:40.593039 Set Vref, RX VrefLevel [Byte0]: 57
1714 11:44:40.595855 [Byte1]: 57
1715 11:44:40.600472
1716 11:44:40.600610 Set Vref, RX VrefLevel [Byte0]: 58
1717 11:44:40.603916 [Byte1]: 58
1718 11:44:40.608073
1719 11:44:40.608245 Set Vref, RX VrefLevel [Byte0]: 59
1720 11:44:40.611702 [Byte1]: 59
1721 11:44:40.615694
1722 11:44:40.615902 Set Vref, RX VrefLevel [Byte0]: 60
1723 11:44:40.618701 [Byte1]: 60
1724 11:44:40.623039
1725 11:44:40.623390 Set Vref, RX VrefLevel [Byte0]: 61
1726 11:44:40.626860 [Byte1]: 61
1727 11:44:40.631316
1728 11:44:40.631762 Set Vref, RX VrefLevel [Byte0]: 62
1729 11:44:40.634236 [Byte1]: 62
1730 11:44:40.638950
1731 11:44:40.639414 Set Vref, RX VrefLevel [Byte0]: 63
1732 11:44:40.642023 [Byte1]: 63
1733 11:44:40.646276
1734 11:44:40.646708 Set Vref, RX VrefLevel [Byte0]: 64
1735 11:44:40.649550 [Byte1]: 64
1736 11:44:40.653815
1737 11:44:40.654246 Set Vref, RX VrefLevel [Byte0]: 65
1738 11:44:40.656896 [Byte1]: 65
1739 11:44:40.661281
1740 11:44:40.661719 Set Vref, RX VrefLevel [Byte0]: 66
1741 11:44:40.664972 [Byte1]: 66
1742 11:44:40.669034
1743 11:44:40.669678 Set Vref, RX VrefLevel [Byte0]: 67
1744 11:44:40.672113 [Byte1]: 67
1745 11:44:40.676750
1746 11:44:40.677182 Set Vref, RX VrefLevel [Byte0]: 68
1747 11:44:40.680358 [Byte1]: 68
1748 11:44:40.684628
1749 11:44:40.685058 Set Vref, RX VrefLevel [Byte0]: 69
1750 11:44:40.687394 [Byte1]: 69
1751 11:44:40.691617
1752 11:44:40.692038 Set Vref, RX VrefLevel [Byte0]: 70
1753 11:44:40.695015 [Byte1]: 70
1754 11:44:40.699602
1755 11:44:40.700202 Set Vref, RX VrefLevel [Byte0]: 71
1756 11:44:40.702373 [Byte1]: 71
1757 11:44:40.706779
1758 11:44:40.707211 Set Vref, RX VrefLevel [Byte0]: 72
1759 11:44:40.710107 [Byte1]: 72
1760 11:44:40.714668
1761 11:44:40.715187 Set Vref, RX VrefLevel [Byte0]: 73
1762 11:44:40.718013 [Byte1]: 73
1763 11:44:40.722020
1764 11:44:40.722532 Set Vref, RX VrefLevel [Byte0]: 74
1765 11:44:40.725705 [Byte1]: 74
1766 11:44:40.729997
1767 11:44:40.730483 Set Vref, RX VrefLevel [Byte0]: 75
1768 11:44:40.733063 [Byte1]: 75
1769 11:44:40.737247
1770 11:44:40.737752 Set Vref, RX VrefLevel [Byte0]: 76
1771 11:44:40.740623 [Byte1]: 76
1772 11:44:40.745290
1773 11:44:40.745733 Set Vref, RX VrefLevel [Byte0]: 77
1774 11:44:40.748463 [Byte1]: 77
1775 11:44:40.752797
1776 11:44:40.753494 Set Vref, RX VrefLevel [Byte0]: 78
1777 11:44:40.755762 [Byte1]: 78
1778 11:44:40.760029
1779 11:44:40.760458 Final RX Vref Byte 0 = 59 to rank0
1780 11:44:40.763690 Final RX Vref Byte 1 = 60 to rank0
1781 11:44:40.766741 Final RX Vref Byte 0 = 59 to rank1
1782 11:44:40.769929 Final RX Vref Byte 1 = 60 to rank1==
1783 11:44:40.773611 Dram Type= 6, Freq= 0, CH_1, rank 0
1784 11:44:40.780183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 11:44:40.780792 ==
1786 11:44:40.781279 DQS Delay:
1787 11:44:40.781742 DQS0 = 0, DQS1 = 0
1788 11:44:40.783209 DQM Delay:
1789 11:44:40.783813 DQM0 = 84, DQM1 = 74
1790 11:44:40.786938 DQ Delay:
1791 11:44:40.789838 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1792 11:44:40.790357 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1793 11:44:40.793454 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
1794 11:44:40.796720 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1795 11:44:40.800249
1796 11:44:40.800680
1797 11:44:40.806932 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1798 11:44:40.810375 CH1 RK0: MR19=605, MR18=26FB
1799 11:44:40.817357 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1800 11:44:40.817924
1801 11:44:40.820283 ----->DramcWriteLeveling(PI) begin...
1802 11:44:40.820809 ==
1803 11:44:40.831072 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 11:44:40.831552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 11:44:40.831905 ==
1806 11:44:40.832224 Write leveling (Byte 0): 26 => 26
1807 11:44:40.834141 Write leveling (Byte 1): 27 => 27
1808 11:44:40.837296 DramcWriteLeveling(PI) end<-----
1809 11:44:40.837727
1810 11:44:40.838071 ==
1811 11:44:40.840240 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 11:44:40.843694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 11:44:40.844175 ==
1814 11:44:40.847224 [Gating] SW mode calibration
1815 11:44:40.853776 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1816 11:44:40.860692 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1817 11:44:40.863718 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1818 11:44:40.867424 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1819 11:44:40.873928 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:44:40.876983 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:44:40.880199 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:44:40.886549 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:44:40.890218 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:44:40.893788 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:44:40.900573 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:44:40.903516 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:44:40.906990 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:44:40.913370 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1829 11:44:40.976879 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:44:40.977847 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:44:40.978329 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:44:40.978844 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1833 11:44:40.979205 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1834 11:44:40.979657 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1835 11:44:40.980000 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1836 11:44:40.980386 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:44:40.980736 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:44:40.981064 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:44:40.981399 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:44:40.981744 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:44:40.982054 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:44:40.982362 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1843 11:44:40.982787 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1844 11:44:41.019708 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 11:44:41.020187 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1846 11:44:41.020532 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 11:44:41.020864 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1848 11:44:41.021489 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1849 11:44:41.021825 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1850 11:44:41.022130 0 10 4 | B1->B0 | 3232 2c2c | 1 0 | (0 0) (0 0)
1851 11:44:41.022421 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
1852 11:44:41.022709 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1853 11:44:41.067823 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:44:41.068327 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:44:41.068675 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:44:41.069023 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:44:41.069352 0 11 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1858 11:44:41.069654 0 11 4 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
1859 11:44:41.069947 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1860 11:44:41.070542 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 11:44:41.070862 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 11:44:41.071154 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 11:44:41.071491 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 11:44:41.111702 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 11:44:41.112584 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 11:44:41.113304 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1867 11:44:41.113994 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1868 11:44:41.114694 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:44:41.115036 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:44:41.115380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:44:41.115688 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:44:41.115979 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:44:41.116266 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:44:41.116551 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:44:41.119745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:44:41.123190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:44:41.126768 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 11:44:41.133185 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 11:44:41.136521 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 11:44:41.140061 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 11:44:41.143130 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 11:44:41.150247 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1883 11:44:41.153394 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 11:44:41.156483 Total UI for P1: 0, mck2ui 16
1885 11:44:41.160506 best dqsien dly found for B0: ( 0, 14, 4)
1886 11:44:41.163037 Total UI for P1: 0, mck2ui 16
1887 11:44:41.166631 best dqsien dly found for B1: ( 0, 14, 6)
1888 11:44:41.169778 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1889 11:44:41.173555 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1890 11:44:41.174015
1891 11:44:41.176710 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1892 11:44:41.179967 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1893 11:44:41.183423 [Gating] SW calibration Done
1894 11:44:41.184073 ==
1895 11:44:41.186381 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 11:44:41.189990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 11:44:41.193293 ==
1898 11:44:41.193728 RX Vref Scan: 0
1899 11:44:41.194088
1900 11:44:41.196668 RX Vref 0 -> 0, step: 1
1901 11:44:41.197105
1902 11:44:41.199657 RX Delay -130 -> 252, step: 16
1903 11:44:41.203436 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1904 11:44:41.206379 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1905 11:44:41.210112 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1906 11:44:41.213078 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1907 11:44:41.219659 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1908 11:44:41.488415 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1909 11:44:41.489637 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1910 11:44:41.490355 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1911 11:44:41.491060 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1912 11:44:41.491788 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1913 11:44:41.492398 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1914 11:44:41.493081 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1915 11:44:41.493741 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1916 11:44:41.494382 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1917 11:44:41.495061 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1918 11:44:41.495754 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1919 11:44:41.496412 ==
1920 11:44:41.497058 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 11:44:41.497684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 11:44:41.498333 ==
1923 11:44:41.498975 DQS Delay:
1924 11:44:41.499635 DQS0 = 0, DQS1 = 0
1925 11:44:41.500294 DQM Delay:
1926 11:44:41.500941 DQM0 = 79, DQM1 = 77
1927 11:44:41.501601 DQ Delay:
1928 11:44:41.502256 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1929 11:44:41.502917 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1930 11:44:41.503599 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1931 11:44:41.504221 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1932 11:44:41.504813
1933 11:44:41.505474
1934 11:44:41.506116 ==
1935 11:44:41.506773 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 11:44:41.507462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 11:44:41.508116 ==
1938 11:44:41.508767
1939 11:44:41.509404
1940 11:44:41.510039 TX Vref Scan disable
1941 11:44:41.510678 == TX Byte 0 ==
1942 11:44:41.511315 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1943 11:44:41.511989 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1944 11:44:41.512630 == TX Byte 1 ==
1945 11:44:41.513266 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1946 11:44:41.513903 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1947 11:44:41.514537 ==
1948 11:44:41.515176 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 11:44:41.515889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 11:44:41.516536 ==
1951 11:44:41.517184 TX Vref=22, minBit 1, minWin=27, winSum=441
1952 11:44:41.517834 TX Vref=24, minBit 9, minWin=27, winSum=444
1953 11:44:41.518471 TX Vref=26, minBit 10, minWin=27, winSum=445
1954 11:44:41.518980 TX Vref=28, minBit 11, minWin=27, winSum=449
1955 11:44:41.519447 TX Vref=30, minBit 1, minWin=28, winSum=454
1956 11:44:41.519907 TX Vref=32, minBit 0, minWin=28, winSum=452
1957 11:44:41.520363 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 30
1958 11:44:41.520819
1959 11:44:41.521274 Final TX Range 1 Vref 30
1960 11:44:41.521726
1961 11:44:41.522174 ==
1962 11:44:41.522507 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 11:44:41.522815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 11:44:41.523120 ==
1965 11:44:41.523436
1966 11:44:41.523648
1967 11:44:41.523797 TX Vref Scan disable
1968 11:44:41.523950 == TX Byte 0 ==
1969 11:44:41.524103 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1970 11:44:41.524256 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1971 11:44:41.524406 == TX Byte 1 ==
1972 11:44:41.524555 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1973 11:44:41.524703 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1974 11:44:41.524853
1975 11:44:41.525000 [DATLAT]
1976 11:44:41.525148 Freq=800, CH1 RK1
1977 11:44:41.525297
1978 11:44:41.525445 DATLAT Default: 0xa
1979 11:44:41.525594 0, 0xFFFF, sum = 0
1980 11:44:41.525749 1, 0xFFFF, sum = 0
1981 11:44:41.525900 2, 0xFFFF, sum = 0
1982 11:44:41.526051 3, 0xFFFF, sum = 0
1983 11:44:41.526200 4, 0xFFFF, sum = 0
1984 11:44:41.526349 5, 0xFFFF, sum = 0
1985 11:44:41.526499 6, 0xFFFF, sum = 0
1986 11:44:41.526650 7, 0xFFFF, sum = 0
1987 11:44:41.526799 8, 0xFFFF, sum = 0
1988 11:44:41.526950 9, 0x0, sum = 1
1989 11:44:41.527101 10, 0x0, sum = 2
1990 11:44:41.527253 11, 0x0, sum = 3
1991 11:44:41.527423 12, 0x0, sum = 4
1992 11:44:41.527577 best_step = 10
1993 11:44:41.527724
1994 11:44:41.527872 ==
1995 11:44:41.528021 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 11:44:41.528171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 11:44:41.528323 ==
1998 11:44:41.528472 RX Vref Scan: 0
1999 11:44:41.528622
2000 11:44:41.528740 RX Vref 0 -> 0, step: 1
2001 11:44:41.528859
2002 11:44:41.528977 RX Delay -95 -> 252, step: 8
2003 11:44:41.529096 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2004 11:44:41.529216 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2005 11:44:41.529334 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2006 11:44:41.529453 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2007 11:44:41.529572 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2008 11:44:41.529690 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2009 11:44:41.529809 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2010 11:44:41.529927 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2011 11:44:41.530047 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2012 11:44:41.530165 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2013 11:44:41.530284 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2014 11:44:41.530442 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2015 11:44:41.530568 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2016 11:44:41.530689 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2017 11:44:41.530808 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2018 11:44:41.530928 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2019 11:44:41.531048 ==
2020 11:44:41.531169 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 11:44:41.531289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 11:44:41.531428 ==
2023 11:44:41.531550 DQS Delay:
2024 11:44:41.531668 DQS0 = 0, DQS1 = 0
2025 11:44:41.531788 DQM Delay:
2026 11:44:41.531905 DQM0 = 81, DQM1 = 76
2027 11:44:41.532024 DQ Delay:
2028 11:44:41.532142 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2029 11:44:41.532262 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2030 11:44:41.532410 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2031 11:44:41.535210 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2032 11:44:41.535382
2033 11:44:41.535508
2034 11:44:41.541814 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2035 11:44:41.545383 CH1 RK1: MR19=606, MR18=1E2A
2036 11:44:41.551525 CH1_RK1: MR19=0x606, MR18=0x1E2A, DQSOSC=399, MR23=63, INC=92, DEC=61
2037 11:44:41.554949 [RxdqsGatingPostProcess] freq 800
2038 11:44:41.561312 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 11:44:41.565505 Pre-setting of DQS Precalculation
2040 11:44:41.568499 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 11:44:41.575587 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 11:44:41.582117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 11:44:41.582552
2044 11:44:41.582892
2045 11:44:41.585148 [Calibration Summary] 1600 Mbps
2046 11:44:41.588930 CH 0, Rank 0
2047 11:44:41.589361 SW Impedance : PASS
2048 11:44:41.591822 DUTY Scan : NO K
2049 11:44:41.595536 ZQ Calibration : PASS
2050 11:44:41.595969 Jitter Meter : NO K
2051 11:44:41.598668 CBT Training : PASS
2052 11:44:41.601771 Write leveling : PASS
2053 11:44:41.602200 RX DQS gating : PASS
2054 11:44:41.605479 RX DQ/DQS(RDDQC) : PASS
2055 11:44:41.608665 TX DQ/DQS : PASS
2056 11:44:41.609100 RX DATLAT : PASS
2057 11:44:41.611683 RX DQ/DQS(Engine): PASS
2058 11:44:41.612117 TX OE : NO K
2059 11:44:41.615081 All Pass.
2060 11:44:41.615595
2061 11:44:41.616163 CH 0, Rank 1
2062 11:44:41.618761 SW Impedance : PASS
2063 11:44:41.619398 DUTY Scan : NO K
2064 11:44:41.621623 ZQ Calibration : PASS
2065 11:44:41.625400 Jitter Meter : NO K
2066 11:44:41.625934 CBT Training : PASS
2067 11:44:41.628438 Write leveling : PASS
2068 11:44:41.632354 RX DQS gating : PASS
2069 11:44:41.632908 RX DQ/DQS(RDDQC) : PASS
2070 11:44:41.634728 TX DQ/DQS : PASS
2071 11:44:41.638302 RX DATLAT : PASS
2072 11:44:41.638843 RX DQ/DQS(Engine): PASS
2073 11:44:41.641970 TX OE : NO K
2074 11:44:41.642405 All Pass.
2075 11:44:41.642744
2076 11:44:41.644853 CH 1, Rank 0
2077 11:44:41.645307 SW Impedance : PASS
2078 11:44:41.648416 DUTY Scan : NO K
2079 11:44:41.652163 ZQ Calibration : PASS
2080 11:44:41.652688 Jitter Meter : NO K
2081 11:44:41.655096 CBT Training : PASS
2082 11:44:41.655574 Write leveling : PASS
2083 11:44:41.658352 RX DQS gating : PASS
2084 11:44:41.661897 RX DQ/DQS(RDDQC) : PASS
2085 11:44:41.662522 TX DQ/DQS : PASS
2086 11:44:41.665396 RX DATLAT : PASS
2087 11:44:41.668879 RX DQ/DQS(Engine): PASS
2088 11:44:41.669315 TX OE : NO K
2089 11:44:41.671797 All Pass.
2090 11:44:41.672229
2091 11:44:41.672567 CH 1, Rank 1
2092 11:44:41.675044 SW Impedance : PASS
2093 11:44:41.675645 DUTY Scan : NO K
2094 11:44:41.678158 ZQ Calibration : PASS
2095 11:44:41.681917 Jitter Meter : NO K
2096 11:44:41.682489 CBT Training : PASS
2097 11:44:41.685058 Write leveling : PASS
2098 11:44:41.688240 RX DQS gating : PASS
2099 11:44:41.688682 RX DQ/DQS(RDDQC) : PASS
2100 11:44:41.691605 TX DQ/DQS : PASS
2101 11:44:41.694660 RX DATLAT : PASS
2102 11:44:41.695216 RX DQ/DQS(Engine): PASS
2103 11:44:41.698479 TX OE : NO K
2104 11:44:41.698933 All Pass.
2105 11:44:41.699276
2106 11:44:41.701499 DramC Write-DBI off
2107 11:44:41.705240 PER_BANK_REFRESH: Hybrid Mode
2108 11:44:41.705672 TX_TRACKING: ON
2109 11:44:41.708317 [GetDramInforAfterCalByMRR] Vendor 6.
2110 11:44:41.711901 [GetDramInforAfterCalByMRR] Revision 606.
2111 11:44:41.714967 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 11:44:41.718518 MR0 0x3b3b
2113 11:44:41.718946 MR8 0x5151
2114 11:44:41.721471 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 11:44:41.721902
2116 11:44:41.722242 MR0 0x3b3b
2117 11:44:41.724818 MR8 0x5151
2118 11:44:41.728865 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 11:44:41.729395
2120 11:44:41.735036 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 11:44:41.741547 [FAST_K] Save calibration result to emmc
2122 11:44:41.745081 [FAST_K] Save calibration result to emmc
2123 11:44:41.745697 dram_init: config_dvfs: 1
2124 11:44:41.751739 dramc_set_vcore_voltage set vcore to 662500
2125 11:44:41.752238 Read voltage for 1200, 2
2126 11:44:41.752639 Vio18 = 0
2127 11:44:41.754899 Vcore = 662500
2128 11:44:41.755545 Vdram = 0
2129 11:44:41.756077 Vddq = 0
2130 11:44:41.758469 Vmddr = 0
2131 11:44:41.761437 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 11:44:41.768338 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 11:44:41.768799 MEM_TYPE=3, freq_sel=15
2134 11:44:41.772018 sv_algorithm_assistance_LP4_1600
2135 11:44:41.778330 ============ PULL DRAM RESETB DOWN ============
2136 11:44:41.781441 ========== PULL DRAM RESETB DOWN end =========
2137 11:44:41.785213 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 11:44:41.788354 ===================================
2139 11:44:41.792119 LPDDR4 DRAM CONFIGURATION
2140 11:44:41.794856 ===================================
2141 11:44:41.798549 EX_ROW_EN[0] = 0x0
2142 11:44:41.799115 EX_ROW_EN[1] = 0x0
2143 11:44:41.801855 LP4Y_EN = 0x0
2144 11:44:41.802416 WORK_FSP = 0x0
2145 11:44:41.804926 WL = 0x4
2146 11:44:41.805376 RL = 0x4
2147 11:44:41.808596 BL = 0x2
2148 11:44:41.809057 RPST = 0x0
2149 11:44:41.811681 RD_PRE = 0x0
2150 11:44:41.812140 WR_PRE = 0x1
2151 11:44:41.814850 WR_PST = 0x0
2152 11:44:41.815437 DBI_WR = 0x0
2153 11:44:41.818466 DBI_RD = 0x0
2154 11:44:41.819030 OTF = 0x1
2155 11:44:41.822052 ===================================
2156 11:44:41.824965 ===================================
2157 11:44:41.828491 ANA top config
2158 11:44:41.831867 ===================================
2159 11:44:41.832301 DLL_ASYNC_EN = 0
2160 11:44:41.835394 ALL_SLAVE_EN = 0
2161 11:44:41.838512 NEW_RANK_MODE = 1
2162 11:44:41.842185 DLL_IDLE_MODE = 1
2163 11:44:41.845279 LP45_APHY_COMB_EN = 1
2164 11:44:41.845712 TX_ODT_DIS = 1
2165 11:44:41.848483 NEW_8X_MODE = 1
2166 11:44:41.851918 ===================================
2167 11:44:41.855176 ===================================
2168 11:44:41.858578 data_rate = 2400
2169 11:44:41.861895 CKR = 1
2170 11:44:41.864775 DQ_P2S_RATIO = 8
2171 11:44:41.868471 ===================================
2172 11:44:41.868904 CA_P2S_RATIO = 8
2173 11:44:41.871794 DQ_CA_OPEN = 0
2174 11:44:41.874620 DQ_SEMI_OPEN = 0
2175 11:44:41.878271 CA_SEMI_OPEN = 0
2176 11:44:41.881885 CA_FULL_RATE = 0
2177 11:44:41.884973 DQ_CKDIV4_EN = 0
2178 11:44:41.885427 CA_CKDIV4_EN = 0
2179 11:44:41.887970 CA_PREDIV_EN = 0
2180 11:44:41.891593 PH8_DLY = 17
2181 11:44:41.894541 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 11:44:41.897969 DQ_AAMCK_DIV = 4
2183 11:44:41.901082 CA_AAMCK_DIV = 4
2184 11:44:41.901613 CA_ADMCK_DIV = 4
2185 11:44:41.904730 DQ_TRACK_CA_EN = 0
2186 11:44:41.907816 CA_PICK = 1200
2187 11:44:41.911543 CA_MCKIO = 1200
2188 11:44:41.914646 MCKIO_SEMI = 0
2189 11:44:41.918391 PLL_FREQ = 2366
2190 11:44:41.921373 DQ_UI_PI_RATIO = 32
2191 11:44:41.925163 CA_UI_PI_RATIO = 0
2192 11:44:41.925739 ===================================
2193 11:44:41.928073 ===================================
2194 11:44:41.931770 memory_type:LPDDR4
2195 11:44:41.934617 GP_NUM : 10
2196 11:44:41.935240 SRAM_EN : 1
2197 11:44:41.938088 MD32_EN : 0
2198 11:44:41.941215 ===================================
2199 11:44:41.944921 [ANA_INIT] >>>>>>>>>>>>>>
2200 11:44:41.947870 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 11:44:41.951763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 11:44:41.954838 ===================================
2203 11:44:41.955263 data_rate = 2400,PCW = 0X5b00
2204 11:44:41.958270 ===================================
2205 11:44:41.961039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 11:44:41.968207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 11:44:41.974691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 11:44:41.978070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 11:44:41.981179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 11:44:41.984558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 11:44:41.987960 [ANA_INIT] flow start
2212 11:44:41.991640 [ANA_INIT] PLL >>>>>>>>
2213 11:44:41.992068 [ANA_INIT] PLL <<<<<<<<
2214 11:44:41.994619 [ANA_INIT] MIDPI >>>>>>>>
2215 11:44:41.998447 [ANA_INIT] MIDPI <<<<<<<<
2216 11:44:41.998872 [ANA_INIT] DLL >>>>>>>>
2217 11:44:42.001221 [ANA_INIT] DLL <<<<<<<<
2218 11:44:42.004839 [ANA_INIT] flow end
2219 11:44:42.008018 ============ LP4 DIFF to SE enter ============
2220 11:44:42.011305 ============ LP4 DIFF to SE exit ============
2221 11:44:42.014741 [ANA_INIT] <<<<<<<<<<<<<
2222 11:44:42.017713 [Flow] Enable top DCM control >>>>>
2223 11:44:42.021383 [Flow] Enable top DCM control <<<<<
2224 11:44:42.024684 Enable DLL master slave shuffle
2225 11:44:42.028162 ==============================================================
2226 11:44:42.031403 Gating Mode config
2227 11:44:42.034854 ==============================================================
2228 11:44:42.037971 Config description:
2229 11:44:42.047895 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 11:44:42.054930 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 11:44:42.057780 SELPH_MODE 0: By rank 1: By Phase
2232 11:44:42.064357 ==============================================================
2233 11:44:42.067860 GAT_TRACK_EN = 1
2234 11:44:42.070785 RX_GATING_MODE = 2
2235 11:44:42.074468 RX_GATING_TRACK_MODE = 2
2236 11:44:42.077290 SELPH_MODE = 1
2237 11:44:42.081023 PICG_EARLY_EN = 1
2238 11:44:42.084233 VALID_LAT_VALUE = 1
2239 11:44:42.087558 ==============================================================
2240 11:44:42.090735 Enter into Gating configuration >>>>
2241 11:44:42.094255 Exit from Gating configuration <<<<
2242 11:44:42.097667 Enter into DVFS_PRE_config >>>>>
2243 11:44:42.107832 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 11:44:42.110862 Exit from DVFS_PRE_config <<<<<
2245 11:44:42.114689 Enter into PICG configuration >>>>
2246 11:44:42.117758 Exit from PICG configuration <<<<
2247 11:44:42.121305 [RX_INPUT] configuration >>>>>
2248 11:44:42.124325 [RX_INPUT] configuration <<<<<
2249 11:44:42.128182 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 11:44:42.134327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 11:44:42.140921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 11:44:42.147879 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 11:44:42.154584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 11:44:42.157735 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 11:44:42.164695 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 11:44:42.167749 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 11:44:42.171239 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 11:44:42.174338 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 11:44:42.180897 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 11:44:42.184194 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 11:44:42.187338 ===================================
2262 11:44:42.190756 LPDDR4 DRAM CONFIGURATION
2263 11:44:42.194128 ===================================
2264 11:44:42.194682 EX_ROW_EN[0] = 0x0
2265 11:44:42.197380 EX_ROW_EN[1] = 0x0
2266 11:44:42.197970 LP4Y_EN = 0x0
2267 11:44:42.200978 WORK_FSP = 0x0
2268 11:44:42.201471 WL = 0x4
2269 11:44:42.203815 RL = 0x4
2270 11:44:42.204392 BL = 0x2
2271 11:44:42.207229 RPST = 0x0
2272 11:44:42.210465 RD_PRE = 0x0
2273 11:44:42.211005 WR_PRE = 0x1
2274 11:44:42.214043 WR_PST = 0x0
2275 11:44:42.214544 DBI_WR = 0x0
2276 11:44:42.216868 DBI_RD = 0x0
2277 11:44:42.216961 OTF = 0x1
2278 11:44:42.220606 ===================================
2279 11:44:42.223812 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 11:44:42.226859 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 11:44:42.233472 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 11:44:42.237128 ===================================
2283 11:44:42.240237 LPDDR4 DRAM CONFIGURATION
2284 11:44:42.243805 ===================================
2285 11:44:42.243903 EX_ROW_EN[0] = 0x10
2286 11:44:42.246879 EX_ROW_EN[1] = 0x0
2287 11:44:42.246976 LP4Y_EN = 0x0
2288 11:44:42.250516 WORK_FSP = 0x0
2289 11:44:42.250612 WL = 0x4
2290 11:44:42.253993 RL = 0x4
2291 11:44:42.254094 BL = 0x2
2292 11:44:42.257067 RPST = 0x0
2293 11:44:42.257167 RD_PRE = 0x0
2294 11:44:42.260233 WR_PRE = 0x1
2295 11:44:42.260326 WR_PST = 0x0
2296 11:44:42.263944 DBI_WR = 0x0
2297 11:44:42.264069 DBI_RD = 0x0
2298 11:44:42.267044 OTF = 0x1
2299 11:44:42.270640 ===================================
2300 11:44:42.277233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 11:44:42.277344 ==
2302 11:44:42.280378 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 11:44:42.283525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 11:44:42.283668 ==
2305 11:44:42.286832 [Duty_Offset_Calibration]
2306 11:44:42.286933 B0:3 B1:-1 CA:1
2307 11:44:42.287026
2308 11:44:42.290159 [DutyScan_Calibration_Flow] k_type=0
2309 11:44:42.300256
2310 11:44:42.300812 ==CLK 0==
2311 11:44:42.303639 Final CLK duty delay cell = -4
2312 11:44:42.307000 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2313 11:44:42.310520 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2314 11:44:42.313860 [-4] AVG Duty = 4953%(X100)
2315 11:44:42.314284
2316 11:44:42.317055 CH0 CLK Duty spec in!! Max-Min= 156%
2317 11:44:42.320582 [DutyScan_Calibration_Flow] ====Done====
2318 11:44:42.321002
2319 11:44:42.323729 [DutyScan_Calibration_Flow] k_type=1
2320 11:44:42.339657
2321 11:44:42.340075 ==DQS 0 ==
2322 11:44:42.342573 Final DQS duty delay cell = 0
2323 11:44:42.346334 [0] MAX Duty = 5156%(X100), DQS PI = 48
2324 11:44:42.349183 [0] MIN Duty = 4969%(X100), DQS PI = 14
2325 11:44:42.349615 [0] AVG Duty = 5062%(X100)
2326 11:44:42.352953
2327 11:44:42.353367 ==DQS 1 ==
2328 11:44:42.356431 Final DQS duty delay cell = -4
2329 11:44:42.359408 [-4] MAX Duty = 5093%(X100), DQS PI = 6
2330 11:44:42.363092 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2331 11:44:42.366087 [-4] AVG Duty = 5046%(X100)
2332 11:44:42.366609
2333 11:44:42.369167 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2334 11:44:42.369590
2335 11:44:42.372871 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2336 11:44:42.376532 [DutyScan_Calibration_Flow] ====Done====
2337 11:44:42.377090
2338 11:44:42.379204 [DutyScan_Calibration_Flow] k_type=3
2339 11:44:42.396183
2340 11:44:42.396657 ==DQM 0 ==
2341 11:44:42.399593 Final DQM duty delay cell = 0
2342 11:44:42.402983 [0] MAX Duty = 5000%(X100), DQS PI = 46
2343 11:44:42.406389 [0] MIN Duty = 4906%(X100), DQS PI = 2
2344 11:44:42.406952 [0] AVG Duty = 4953%(X100)
2345 11:44:42.409403
2346 11:44:42.409799 ==DQM 1 ==
2347 11:44:42.412723 Final DQM duty delay cell = 0
2348 11:44:42.416357 [0] MAX Duty = 5156%(X100), DQS PI = 62
2349 11:44:42.419345 [0] MIN Duty = 5000%(X100), DQS PI = 10
2350 11:44:42.420075 [0] AVG Duty = 5078%(X100)
2351 11:44:42.422857
2352 11:44:42.426144 CH0 DQM 0 Duty spec in!! Max-Min= 94%
2353 11:44:42.426693
2354 11:44:42.429658 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2355 11:44:42.432686 [DutyScan_Calibration_Flow] ====Done====
2356 11:44:42.433028
2357 11:44:42.436451 [DutyScan_Calibration_Flow] k_type=2
2358 11:44:42.452120
2359 11:44:42.452917 ==DQ 0 ==
2360 11:44:42.455117 Final DQ duty delay cell = -4
2361 11:44:42.458790 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2362 11:44:42.461807 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2363 11:44:42.465468 [-4] AVG Duty = 4968%(X100)
2364 11:44:42.465884
2365 11:44:42.466208 ==DQ 1 ==
2366 11:44:42.468542 Final DQ duty delay cell = 0
2367 11:44:42.471573 [0] MAX Duty = 5031%(X100), DQS PI = 18
2368 11:44:42.475247 [0] MIN Duty = 4907%(X100), DQS PI = 46
2369 11:44:42.478377 [0] AVG Duty = 4969%(X100)
2370 11:44:42.478881
2371 11:44:42.481991 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2372 11:44:42.482417
2373 11:44:42.485035 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2374 11:44:42.488765 [DutyScan_Calibration_Flow] ====Done====
2375 11:44:42.489186 ==
2376 11:44:42.491837 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 11:44:42.495321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 11:44:42.495774 ==
2379 11:44:42.498927 [Duty_Offset_Calibration]
2380 11:44:42.499375 B0:1 B1:1 CA:2
2381 11:44:42.499713
2382 11:44:42.501978 [DutyScan_Calibration_Flow] k_type=0
2383 11:44:42.511933
2384 11:44:42.512353 ==CLK 0==
2385 11:44:42.515440 Final CLK duty delay cell = 0
2386 11:44:42.518729 [0] MAX Duty = 5156%(X100), DQS PI = 24
2387 11:44:42.522172 [0] MIN Duty = 4969%(X100), DQS PI = 40
2388 11:44:42.522713 [0] AVG Duty = 5062%(X100)
2389 11:44:42.525423
2390 11:44:42.528765 CH1 CLK Duty spec in!! Max-Min= 187%
2391 11:44:42.532326 [DutyScan_Calibration_Flow] ====Done====
2392 11:44:42.532776
2393 11:44:42.535558 [DutyScan_Calibration_Flow] k_type=1
2394 11:44:42.551620
2395 11:44:42.552385 ==DQS 0 ==
2396 11:44:42.554548 Final DQS duty delay cell = 0
2397 11:44:42.558325 [0] MAX Duty = 5031%(X100), DQS PI = 18
2398 11:44:42.561382 [0] MIN Duty = 4844%(X100), DQS PI = 50
2399 11:44:42.564780 [0] AVG Duty = 4937%(X100)
2400 11:44:42.565485
2401 11:44:42.565834 ==DQS 1 ==
2402 11:44:42.568517 Final DQS duty delay cell = 0
2403 11:44:42.571610 [0] MAX Duty = 5062%(X100), DQS PI = 36
2404 11:44:42.574624 [0] MIN Duty = 4938%(X100), DQS PI = 0
2405 11:44:42.575048 [0] AVG Duty = 5000%(X100)
2406 11:44:42.578310
2407 11:44:42.581871 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2408 11:44:42.582293
2409 11:44:42.584921 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2410 11:44:42.588400 [DutyScan_Calibration_Flow] ====Done====
2411 11:44:42.588821
2412 11:44:42.591508 [DutyScan_Calibration_Flow] k_type=3
2413 11:44:42.607904
2414 11:44:42.608327 ==DQM 0 ==
2415 11:44:42.611716 Final DQM duty delay cell = 0
2416 11:44:42.614501 [0] MAX Duty = 5093%(X100), DQS PI = 16
2417 11:44:42.618281 [0] MIN Duty = 4907%(X100), DQS PI = 48
2418 11:44:42.621180 [0] AVG Duty = 5000%(X100)
2419 11:44:42.621733
2420 11:44:42.622207 ==DQM 1 ==
2421 11:44:42.624582 Final DQM duty delay cell = 0
2422 11:44:42.628180 [0] MAX Duty = 5156%(X100), DQS PI = 62
2423 11:44:42.631571 [0] MIN Duty = 4938%(X100), DQS PI = 24
2424 11:44:42.634692 [0] AVG Duty = 5047%(X100)
2425 11:44:42.635257
2426 11:44:42.638097 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2427 11:44:42.638598
2428 11:44:42.641535 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2429 11:44:42.644668 [DutyScan_Calibration_Flow] ====Done====
2430 11:44:42.645145
2431 11:44:42.648058 [DutyScan_Calibration_Flow] k_type=2
2432 11:44:42.664493
2433 11:44:42.664922 ==DQ 0 ==
2434 11:44:42.668499 Final DQ duty delay cell = 0
2435 11:44:42.671412 [0] MAX Duty = 5156%(X100), DQS PI = 18
2436 11:44:42.674551 [0] MIN Duty = 4907%(X100), DQS PI = 50
2437 11:44:42.675026 [0] AVG Duty = 5031%(X100)
2438 11:44:42.675424
2439 11:44:42.677542 ==DQ 1 ==
2440 11:44:42.681208 Final DQ duty delay cell = 0
2441 11:44:42.684332 [0] MAX Duty = 5124%(X100), DQS PI = 56
2442 11:44:42.688157 [0] MIN Duty = 5031%(X100), DQS PI = 2
2443 11:44:42.688584 [0] AVG Duty = 5077%(X100)
2444 11:44:42.688921
2445 11:44:42.691023 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2446 11:44:42.691679
2447 11:44:42.694655 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2448 11:44:42.700900 [DutyScan_Calibration_Flow] ====Done====
2449 11:44:42.704294 nWR fixed to 30
2450 11:44:42.704726 [ModeRegInit_LP4] CH0 RK0
2451 11:44:42.707867 [ModeRegInit_LP4] CH0 RK1
2452 11:44:42.711338 [ModeRegInit_LP4] CH1 RK0
2453 11:44:42.711830 [ModeRegInit_LP4] CH1 RK1
2454 11:44:42.714667 match AC timing 7
2455 11:44:42.717958 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 11:44:42.721427 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 11:44:42.728044 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 11:44:42.731628 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 11:44:42.738072 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 11:44:42.738501 ==
2461 11:44:42.741563 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 11:44:42.744523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 11:44:42.744951 ==
2464 11:44:42.751199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 11:44:42.754761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2466 11:44:42.764480 [CA 0] Center 40 (10~71) winsize 62
2467 11:44:42.768226 [CA 1] Center 39 (9~70) winsize 62
2468 11:44:42.771165 [CA 2] Center 36 (6~67) winsize 62
2469 11:44:42.774758 [CA 3] Center 36 (5~67) winsize 63
2470 11:44:42.777802 [CA 4] Center 35 (5~65) winsize 61
2471 11:44:42.780954 [CA 5] Center 34 (4~64) winsize 61
2472 11:44:42.781386
2473 11:44:42.784645 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2474 11:44:42.785084
2475 11:44:42.787687 [CATrainingPosCal] consider 1 rank data
2476 11:44:42.790853 u2DelayCellTimex100 = 270/100 ps
2477 11:44:42.794887 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2478 11:44:42.801416 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2479 11:44:42.804520 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2480 11:44:42.807529 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2481 11:44:42.811285 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2482 11:44:42.814296 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2483 11:44:42.814718
2484 11:44:42.817706 CA PerBit enable=1, Macro0, CA PI delay=34
2485 11:44:42.818221
2486 11:44:42.821264 [CBTSetCACLKResult] CA Dly = 34
2487 11:44:42.821816 CS Dly: 7 (0~38)
2488 11:44:42.822324 ==
2489 11:44:42.824719 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 11:44:42.831433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 11:44:42.832193 ==
2492 11:44:42.834310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 11:44:42.841262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2494 11:44:42.850040 [CA 0] Center 39 (9~70) winsize 62
2495 11:44:42.853549 [CA 1] Center 40 (10~70) winsize 61
2496 11:44:42.857154 [CA 2] Center 36 (6~67) winsize 62
2497 11:44:42.860640 [CA 3] Center 36 (5~67) winsize 63
2498 11:44:42.863432 [CA 4] Center 34 (4~65) winsize 62
2499 11:44:42.867084 [CA 5] Center 34 (4~64) winsize 61
2500 11:44:42.867611
2501 11:44:42.870102 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2502 11:44:42.870536
2503 11:44:42.873816 [CATrainingPosCal] consider 2 rank data
2504 11:44:42.876664 u2DelayCellTimex100 = 270/100 ps
2505 11:44:42.880130 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2506 11:44:42.886880 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2507 11:44:42.889839 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2508 11:44:42.893571 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2509 11:44:42.896665 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2510 11:44:42.900291 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2511 11:44:42.900725
2512 11:44:42.903411 CA PerBit enable=1, Macro0, CA PI delay=34
2513 11:44:42.903854
2514 11:44:42.906985 [CBTSetCACLKResult] CA Dly = 34
2515 11:44:42.907453 CS Dly: 8 (0~41)
2516 11:44:42.910161
2517 11:44:42.913794 ----->DramcWriteLeveling(PI) begin...
2518 11:44:42.914232 ==
2519 11:44:42.916863 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 11:44:42.920430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 11:44:42.920864 ==
2522 11:44:42.923336 Write leveling (Byte 0): 30 => 30
2523 11:44:42.927094 Write leveling (Byte 1): 30 => 30
2524 11:44:42.930035 DramcWriteLeveling(PI) end<-----
2525 11:44:42.930463
2526 11:44:42.930801 ==
2527 11:44:42.933644 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 11:44:42.936719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 11:44:42.937149 ==
2530 11:44:42.940103 [Gating] SW mode calibration
2531 11:44:42.946500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 11:44:42.953299 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 11:44:42.956907 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 11:44:42.960092 0 15 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2535 11:44:42.967013 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2536 11:44:42.970502 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 11:44:42.973387 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 11:44:42.977090 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 11:44:42.983683 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 11:44:42.986646 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 11:44:42.990487 1 0 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
2542 11:44:42.996773 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2543 11:44:43.000409 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 11:44:43.003610 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 11:44:43.010083 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 11:44:43.013761 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 11:44:43.016715 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 11:44:43.023424 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 11:44:43.026947 1 1 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2550 11:44:43.030114 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2551 11:44:43.036993 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 11:44:43.040227 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 11:44:43.043881 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 11:44:43.050434 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 11:44:43.053367 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 11:44:43.057055 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 11:44:43.063592 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2558 11:44:43.066848 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:44:43.070412 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:44:43.073805 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:44:43.080519 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:44:43.083713 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:44:43.086465 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:44:43.093679 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:44:43.096815 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:44:43.099807 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:44:43.106687 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:44:43.110635 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 11:44:43.113791 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 11:44:43.120429 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 11:44:43.123391 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 11:44:43.126864 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 11:44:43.133454 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2574 11:44:43.137211 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 11:44:43.140512 Total UI for P1: 0, mck2ui 16
2576 11:44:43.143615 best dqsien dly found for B0: ( 1, 3, 30)
2577 11:44:43.146827 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 11:44:43.149817 Total UI for P1: 0, mck2ui 16
2579 11:44:43.153242 best dqsien dly found for B1: ( 1, 4, 2)
2580 11:44:43.156819 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2581 11:44:43.160157 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2582 11:44:43.160713
2583 11:44:43.163800 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2584 11:44:43.170240 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2585 11:44:43.170799 [Gating] SW calibration Done
2586 11:44:43.171280 ==
2587 11:44:43.173112 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 11:44:43.180076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 11:44:43.180593 ==
2590 11:44:43.181062 RX Vref Scan: 0
2591 11:44:43.181513
2592 11:44:43.183268 RX Vref 0 -> 0, step: 1
2593 11:44:43.183936
2594 11:44:43.186914 RX Delay -40 -> 252, step: 8
2595 11:44:43.189908 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2596 11:44:43.193382 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2597 11:44:43.196981 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2598 11:44:43.203749 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2599 11:44:43.206775 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2600 11:44:43.209994 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2601 11:44:43.213572 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2602 11:44:43.216894 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2603 11:44:43.220076 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2604 11:44:43.226674 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2605 11:44:43.229817 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2606 11:44:43.233387 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2607 11:44:43.237014 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2608 11:44:43.240098 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2609 11:44:43.246784 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2610 11:44:43.250421 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2611 11:44:43.251023 ==
2612 11:44:43.253692 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 11:44:43.256872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 11:44:43.257303 ==
2615 11:44:43.260212 DQS Delay:
2616 11:44:43.260581 DQS0 = 0, DQS1 = 0
2617 11:44:43.260903 DQM Delay:
2618 11:44:43.263838 DQM0 = 115, DQM1 = 107
2619 11:44:43.264201 DQ Delay:
2620 11:44:43.266750 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2621 11:44:43.270196 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2622 11:44:43.273350 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2623 11:44:43.279931 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2624 11:44:43.280465
2625 11:44:43.280979
2626 11:44:43.281435 ==
2627 11:44:43.283555 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 11:44:43.286541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 11:44:43.287048 ==
2630 11:44:43.287542
2631 11:44:43.287985
2632 11:44:43.290178 TX Vref Scan disable
2633 11:44:43.290650 == TX Byte 0 ==
2634 11:44:43.296811 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2635 11:44:43.300431 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2636 11:44:43.300875 == TX Byte 1 ==
2637 11:44:43.306689 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2638 11:44:43.309715 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2639 11:44:43.310140 ==
2640 11:44:43.313500 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 11:44:43.316559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 11:44:43.316985 ==
2643 11:44:43.329093 TX Vref=22, minBit 1, minWin=25, winSum=419
2644 11:44:43.332129 TX Vref=24, minBit 5, minWin=25, winSum=422
2645 11:44:43.335886 TX Vref=26, minBit 5, minWin=25, winSum=425
2646 11:44:43.338921 TX Vref=28, minBit 1, minWin=26, winSum=435
2647 11:44:43.342349 TX Vref=30, minBit 1, minWin=26, winSum=438
2648 11:44:43.346139 TX Vref=32, minBit 0, minWin=26, winSum=434
2649 11:44:43.352700 [TxChooseVref] Worse bit 1, Min win 26, Win sum 438, Final Vref 30
2650 11:44:43.353135
2651 11:44:43.355640 Final TX Range 1 Vref 30
2652 11:44:43.356070
2653 11:44:43.356408 ==
2654 11:44:43.359279 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 11:44:43.362634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 11:44:43.363064 ==
2657 11:44:43.363428
2658 11:44:43.365788
2659 11:44:43.366342 TX Vref Scan disable
2660 11:44:43.369138 == TX Byte 0 ==
2661 11:44:43.372356 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2662 11:44:43.375416 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2663 11:44:43.378693 == TX Byte 1 ==
2664 11:44:43.382207 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2665 11:44:43.385567 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2666 11:44:43.386076
2667 11:44:43.389001 [DATLAT]
2668 11:44:43.389490 Freq=1200, CH0 RK0
2669 11:44:43.389943
2670 11:44:43.392027 DATLAT Default: 0xd
2671 11:44:43.392496 0, 0xFFFF, sum = 0
2672 11:44:43.395115 1, 0xFFFF, sum = 0
2673 11:44:43.395602 2, 0xFFFF, sum = 0
2674 11:44:43.398745 3, 0xFFFF, sum = 0
2675 11:44:43.399229 4, 0xFFFF, sum = 0
2676 11:44:43.402621 5, 0xFFFF, sum = 0
2677 11:44:43.403280 6, 0xFFFF, sum = 0
2678 11:44:43.405699 7, 0xFFFF, sum = 0
2679 11:44:43.408708 8, 0xFFFF, sum = 0
2680 11:44:43.409150 9, 0xFFFF, sum = 0
2681 11:44:43.411865 10, 0xFFFF, sum = 0
2682 11:44:43.412306 11, 0xFFFF, sum = 0
2683 11:44:43.415576 12, 0x0, sum = 1
2684 11:44:43.416015 13, 0x0, sum = 2
2685 11:44:43.419053 14, 0x0, sum = 3
2686 11:44:43.419637 15, 0x0, sum = 4
2687 11:44:43.419994 best_step = 13
2688 11:44:43.420317
2689 11:44:43.422166 ==
2690 11:44:43.425209 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 11:44:43.428662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 11:44:43.429217 ==
2693 11:44:43.429765 RX Vref Scan: 1
2694 11:44:43.430143
2695 11:44:43.432296 Set Vref Range= 32 -> 127
2696 11:44:43.432664
2697 11:44:43.435405 RX Vref 32 -> 127, step: 1
2698 11:44:43.435863
2699 11:44:43.438662 RX Delay -21 -> 252, step: 4
2700 11:44:43.439127
2701 11:44:43.442207 Set Vref, RX VrefLevel [Byte0]: 32
2702 11:44:43.445213 [Byte1]: 32
2703 11:44:43.445794
2704 11:44:43.448781 Set Vref, RX VrefLevel [Byte0]: 33
2705 11:44:43.451925 [Byte1]: 33
2706 11:44:43.455340
2707 11:44:43.455789 Set Vref, RX VrefLevel [Byte0]: 34
2708 11:44:43.458489 [Byte1]: 34
2709 11:44:43.462702
2710 11:44:43.463108 Set Vref, RX VrefLevel [Byte0]: 35
2711 11:44:43.466316 [Byte1]: 35
2712 11:44:43.470842
2713 11:44:43.471246 Set Vref, RX VrefLevel [Byte0]: 36
2714 11:44:43.474522 [Byte1]: 36
2715 11:44:43.479106
2716 11:44:43.479723 Set Vref, RX VrefLevel [Byte0]: 37
2717 11:44:43.482080 [Byte1]: 37
2718 11:44:43.486634
2719 11:44:43.487144 Set Vref, RX VrefLevel [Byte0]: 38
2720 11:44:43.490214 [Byte1]: 38
2721 11:44:43.494629
2722 11:44:43.495142 Set Vref, RX VrefLevel [Byte0]: 39
2723 11:44:43.497810 [Byte1]: 39
2724 11:44:43.502810
2725 11:44:43.505482 Set Vref, RX VrefLevel [Byte0]: 40
2726 11:44:43.509223 [Byte1]: 40
2727 11:44:43.509645
2728 11:44:43.513048 Set Vref, RX VrefLevel [Byte0]: 41
2729 11:44:43.515950 [Byte1]: 41
2730 11:44:43.516547
2731 11:44:43.519114 Set Vref, RX VrefLevel [Byte0]: 42
2732 11:44:43.522863 [Byte1]: 42
2733 11:44:43.526388
2734 11:44:43.526832 Set Vref, RX VrefLevel [Byte0]: 43
2735 11:44:43.529984 [Byte1]: 43
2736 11:44:43.534233
2737 11:44:43.534655 Set Vref, RX VrefLevel [Byte0]: 44
2738 11:44:43.538081 [Byte1]: 44
2739 11:44:43.542215
2740 11:44:43.542636 Set Vref, RX VrefLevel [Byte0]: 45
2741 11:44:43.545401 [Byte1]: 45
2742 11:44:43.550595
2743 11:44:43.551023 Set Vref, RX VrefLevel [Byte0]: 46
2744 11:44:43.553621 [Byte1]: 46
2745 11:44:43.558598
2746 11:44:43.559027 Set Vref, RX VrefLevel [Byte0]: 47
2747 11:44:43.561660 [Byte1]: 47
2748 11:44:43.565909
2749 11:44:43.566395 Set Vref, RX VrefLevel [Byte0]: 48
2750 11:44:43.572323 [Byte1]: 48
2751 11:44:43.572785
2752 11:44:43.575946 Set Vref, RX VrefLevel [Byte0]: 49
2753 11:44:43.579069 [Byte1]: 49
2754 11:44:43.579544
2755 11:44:43.582819 Set Vref, RX VrefLevel [Byte0]: 50
2756 11:44:43.585804 [Byte1]: 50
2757 11:44:43.589819
2758 11:44:43.590261 Set Vref, RX VrefLevel [Byte0]: 51
2759 11:44:43.593308 [Byte1]: 51
2760 11:44:43.597512
2761 11:44:43.597955 Set Vref, RX VrefLevel [Byte0]: 52
2762 11:44:43.601039 [Byte1]: 52
2763 11:44:43.605924
2764 11:44:43.606364 Set Vref, RX VrefLevel [Byte0]: 53
2765 11:44:43.608892 [Byte1]: 53
2766 11:44:43.613857
2767 11:44:43.614310 Set Vref, RX VrefLevel [Byte0]: 54
2768 11:44:43.616709 [Byte1]: 54
2769 11:44:43.621511
2770 11:44:43.621949 Set Vref, RX VrefLevel [Byte0]: 55
2771 11:44:43.625164 [Byte1]: 55
2772 11:44:43.629532
2773 11:44:43.629995 Set Vref, RX VrefLevel [Byte0]: 56
2774 11:44:43.632506 [Byte1]: 56
2775 11:44:43.637149
2776 11:44:43.637589 Set Vref, RX VrefLevel [Byte0]: 57
2777 11:44:43.640568 [Byte1]: 57
2778 11:44:43.645540
2779 11:44:43.645982 Set Vref, RX VrefLevel [Byte0]: 58
2780 11:44:43.648638 [Byte1]: 58
2781 11:44:43.653612
2782 11:44:43.654176 Set Vref, RX VrefLevel [Byte0]: 59
2783 11:44:43.656993 [Byte1]: 59
2784 11:44:43.661379
2785 11:44:43.661821 Set Vref, RX VrefLevel [Byte0]: 60
2786 11:44:43.664392 [Byte1]: 60
2787 11:44:43.668719
2788 11:44:43.672550 Set Vref, RX VrefLevel [Byte0]: 61
2789 11:44:43.676010 [Byte1]: 61
2790 11:44:43.676454
2791 11:44:43.678848 Set Vref, RX VrefLevel [Byte0]: 62
2792 11:44:43.682488 [Byte1]: 62
2793 11:44:43.682931
2794 11:44:43.685896 Set Vref, RX VrefLevel [Byte0]: 63
2795 11:44:43.688824 [Byte1]: 63
2796 11:44:43.693188
2797 11:44:43.693613 Set Vref, RX VrefLevel [Byte0]: 64
2798 11:44:43.696649 [Byte1]: 64
2799 11:44:43.701183
2800 11:44:43.701610 Set Vref, RX VrefLevel [Byte0]: 65
2801 11:44:43.704133 [Byte1]: 65
2802 11:44:43.708765
2803 11:44:43.709324 Set Vref, RX VrefLevel [Byte0]: 66
2804 11:44:43.712399 [Byte1]: 66
2805 11:44:43.716591
2806 11:44:43.717014 Set Vref, RX VrefLevel [Byte0]: 67
2807 11:44:43.720146 [Byte1]: 67
2808 11:44:43.725036
2809 11:44:43.725556 Set Vref, RX VrefLevel [Byte0]: 68
2810 11:44:43.727980 [Byte1]: 68
2811 11:44:43.732702
2812 11:44:43.733219 Final RX Vref Byte 0 = 51 to rank0
2813 11:44:43.736046 Final RX Vref Byte 1 = 51 to rank0
2814 11:44:43.739368 Final RX Vref Byte 0 = 51 to rank1
2815 11:44:43.742736 Final RX Vref Byte 1 = 51 to rank1==
2816 11:44:43.746332 Dram Type= 6, Freq= 0, CH_0, rank 0
2817 11:44:43.752871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 11:44:43.753436 ==
2819 11:44:43.753812 DQS Delay:
2820 11:44:43.754160 DQS0 = 0, DQS1 = 0
2821 11:44:43.755933 DQM Delay:
2822 11:44:43.756357 DQM0 = 115, DQM1 = 104
2823 11:44:43.759325 DQ Delay:
2824 11:44:43.763210 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2825 11:44:43.766280 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2826 11:44:43.769515 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2827 11:44:43.772544 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2828 11:44:43.773037
2829 11:44:43.773413
2830 11:44:43.779120 [DQSOSCAuto] RK0, (LSB)MR18= 0xfceb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2831 11:44:43.782636 CH0 RK0: MR19=303, MR18=FCEB
2832 11:44:43.789079 CH0_RK0: MR19=0x303, MR18=0xFCEB, DQSOSC=411, MR23=63, INC=38, DEC=25
2833 11:44:43.789517
2834 11:44:43.792481 ----->DramcWriteLeveling(PI) begin...
2835 11:44:43.792920 ==
2836 11:44:43.795980 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 11:44:43.798949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 11:44:43.799416 ==
2839 11:44:43.802428 Write leveling (Byte 0): 30 => 30
2840 11:44:43.805749 Write leveling (Byte 1): 27 => 27
2841 11:44:43.808840 DramcWriteLeveling(PI) end<-----
2842 11:44:43.809270
2843 11:44:43.809608 ==
2844 11:44:43.812632 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 11:44:43.819390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 11:44:43.819833 ==
2847 11:44:43.820174 [Gating] SW mode calibration
2848 11:44:43.828871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2849 11:44:43.832980 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2850 11:44:43.835915 0 15 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2851 11:44:43.842447 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
2852 11:44:43.846373 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 11:44:43.848907 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 11:44:43.855601 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 11:44:43.963712 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 11:44:43.964649 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2857 11:44:43.965086 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2858 11:44:43.965453 1 0 0 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (0 0)
2859 11:44:43.965951 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 11:44:43.966275 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 11:44:43.966576 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 11:44:43.966871 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 11:44:43.967161 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 11:44:43.967493 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2865 11:44:43.967790 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2866 11:44:43.968078 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2867 11:44:43.968362 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2868 11:44:43.968646 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 11:44:43.968929 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 11:44:43.969348 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 11:44:43.969684 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:44:43.969997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 11:44:43.970312 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2874 11:44:43.970625 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2875 11:44:43.970937 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:44:43.971399 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:44:43.971867 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:44:43.972347 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:44:43.972960 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:44:43.973465 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:44:43.973884 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:44:43.979243 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:44:43.982936 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:44:43.985956 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:44:43.992869 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:44:43.996178 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:44:43.999207 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:44:44.002684 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:44:44.009747 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2890 11:44:44.012866 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2891 11:44:44.016506 Total UI for P1: 0, mck2ui 16
2892 11:44:44.019116 best dqsien dly found for B0: ( 1, 3, 28)
2893 11:44:44.064346 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2894 11:44:44.064984 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 11:44:44.065358 Total UI for P1: 0, mck2ui 16
2896 11:44:44.065702 best dqsien dly found for B1: ( 1, 4, 2)
2897 11:44:44.066019 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2898 11:44:44.066324 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2899 11:44:44.066658
2900 11:44:44.066953 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2901 11:44:44.067245 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2902 11:44:44.067573 [Gating] SW calibration Done
2903 11:44:44.067891 ==
2904 11:44:44.068178 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 11:44:44.068465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 11:44:44.068751 ==
2907 11:44:44.069030 RX Vref Scan: 0
2908 11:44:44.069307
2909 11:44:44.069588 RX Vref 0 -> 0, step: 1
2910 11:44:44.069868
2911 11:44:44.070457 RX Delay -40 -> 252, step: 8
2912 11:44:44.070772 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2913 11:44:44.075922 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2914 11:44:44.079012 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
2915 11:44:44.082172 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2916 11:44:44.086003 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2917 11:44:44.089109 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2918 11:44:44.096343 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2919 11:44:44.099044 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2920 11:44:44.102508 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2921 11:44:44.105994 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2922 11:44:44.109504 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2923 11:44:44.112682 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2924 11:44:44.119046 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2925 11:44:44.122365 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2926 11:44:44.125834 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2927 11:44:44.129099 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2928 11:44:44.129533 ==
2929 11:44:44.132775 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 11:44:44.139475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 11:44:44.139969 ==
2932 11:44:44.140311 DQS Delay:
2933 11:44:44.142762 DQS0 = 0, DQS1 = 0
2934 11:44:44.143224 DQM Delay:
2935 11:44:44.143710 DQM0 = 114, DQM1 = 106
2936 11:44:44.145832 DQ Delay:
2937 11:44:44.149495 DQ0 =115, DQ1 =115, DQ2 =107, DQ3 =115
2938 11:44:44.152604 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2939 11:44:44.156224 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2940 11:44:44.159226 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2941 11:44:44.159710
2942 11:44:44.160140
2943 11:44:44.160549 ==
2944 11:44:44.162969 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 11:44:44.165883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 11:44:44.166324 ==
2947 11:44:44.169463
2948 11:44:44.169895
2949 11:44:44.170326 TX Vref Scan disable
2950 11:44:44.172653 == TX Byte 0 ==
2951 11:44:44.176207 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2952 11:44:44.179561 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2953 11:44:44.182676 == TX Byte 1 ==
2954 11:44:44.186313 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2955 11:44:44.189656 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2956 11:44:44.190082 ==
2957 11:44:44.192724 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 11:44:44.199295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 11:44:44.199779 ==
2960 11:44:44.210742 TX Vref=22, minBit 5, minWin=25, winSum=422
2961 11:44:44.213433 TX Vref=24, minBit 5, minWin=25, winSum=430
2962 11:44:44.216964 TX Vref=26, minBit 2, minWin=26, winSum=436
2963 11:44:44.220459 TX Vref=28, minBit 0, minWin=27, winSum=440
2964 11:44:44.223441 TX Vref=30, minBit 0, minWin=27, winSum=438
2965 11:44:44.226865 TX Vref=32, minBit 0, minWin=27, winSum=440
2966 11:44:44.233441 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 28
2967 11:44:44.234051
2968 11:44:44.236523 Final TX Range 1 Vref 28
2969 11:44:44.236953
2970 11:44:44.237320 ==
2971 11:44:44.240301 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 11:44:44.243734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 11:44:44.244464 ==
2974 11:44:44.245140
2975 11:44:44.246809
2976 11:44:44.247250 TX Vref Scan disable
2977 11:44:44.250434 == TX Byte 0 ==
2978 11:44:44.253647 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2979 11:44:44.257247 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2980 11:44:44.260176 == TX Byte 1 ==
2981 11:44:44.263973 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2982 11:44:44.267102 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2983 11:44:44.267642
2984 11:44:44.270519 [DATLAT]
2985 11:44:44.271112 Freq=1200, CH0 RK1
2986 11:44:44.271679
2987 11:44:44.273514 DATLAT Default: 0xd
2988 11:44:44.274155 0, 0xFFFF, sum = 0
2989 11:44:44.276648 1, 0xFFFF, sum = 0
2990 11:44:44.277341 2, 0xFFFF, sum = 0
2991 11:44:44.280092 3, 0xFFFF, sum = 0
2992 11:44:44.280576 4, 0xFFFF, sum = 0
2993 11:44:44.283670 5, 0xFFFF, sum = 0
2994 11:44:44.284064 6, 0xFFFF, sum = 0
2995 11:44:44.286726 7, 0xFFFF, sum = 0
2996 11:44:44.286997 8, 0xFFFF, sum = 0
2997 11:44:44.289844 9, 0xFFFF, sum = 0
2998 11:44:44.293572 10, 0xFFFF, sum = 0
2999 11:44:44.293885 11, 0xFFFF, sum = 0
3000 11:44:44.296656 12, 0x0, sum = 1
3001 11:44:44.296964 13, 0x0, sum = 2
3002 11:44:44.297191 14, 0x0, sum = 3
3003 11:44:44.299701 15, 0x0, sum = 4
3004 11:44:44.299936 best_step = 13
3005 11:44:44.300119
3006 11:44:44.303500 ==
3007 11:44:44.306746 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 11:44:44.310279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 11:44:44.310716 ==
3010 11:44:44.311061 RX Vref Scan: 0
3011 11:44:44.311412
3012 11:44:44.313143 RX Vref 0 -> 0, step: 1
3013 11:44:44.313720
3014 11:44:44.316755 RX Delay -21 -> 252, step: 4
3015 11:44:44.380305 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3016 11:44:44.381666 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3017 11:44:44.382500 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3018 11:44:44.383177 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3019 11:44:44.383670 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3020 11:44:44.384028 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3021 11:44:44.384362 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3022 11:44:44.384686 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3023 11:44:44.385004 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3024 11:44:44.385319 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3025 11:44:44.385630 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3026 11:44:44.385943 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3027 11:44:44.386253 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3028 11:44:44.386563 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3029 11:44:44.386871 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3030 11:44:44.387180 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3031 11:44:44.387536 ==
3032 11:44:44.387925 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 11:44:44.390477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 11:44:44.390958 ==
3035 11:44:44.391335 DQS Delay:
3036 11:44:44.391746 DQS0 = 0, DQS1 = 0
3037 11:44:44.394043 DQM Delay:
3038 11:44:44.394606 DQM0 = 114, DQM1 = 104
3039 11:44:44.397239 DQ Delay:
3040 11:44:44.400190 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3041 11:44:44.403750 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =120
3042 11:44:44.406846 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3043 11:44:44.410421 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3044 11:44:44.410932
3045 11:44:44.411423
3046 11:44:44.417056 [DQSOSCAuto] RK1, (LSB)MR18= 0xfff0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3047 11:44:44.420485 CH0 RK1: MR19=303, MR18=FFF0
3048 11:44:44.427024 CH0_RK1: MR19=0x303, MR18=0xFFF0, DQSOSC=410, MR23=63, INC=39, DEC=26
3049 11:44:44.430473 [RxdqsGatingPostProcess] freq 1200
3050 11:44:44.436817 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3051 11:44:44.437250 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 11:44:44.440321 best DQS1 dly(2T, 0.5T) = (0, 12)
3053 11:44:44.444097 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 11:44:44.446756 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3055 11:44:44.450465 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 11:44:44.453983 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 11:44:44.457108 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 11:44:44.460596 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 11:44:44.464020 Pre-setting of DQS Precalculation
3060 11:44:44.467165 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3061 11:44:44.470666 ==
3062 11:44:44.473688 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 11:44:44.477117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 11:44:44.477552 ==
3065 11:44:44.480115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 11:44:44.486821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3067 11:44:44.496331 [CA 0] Center 38 (8~68) winsize 61
3068 11:44:44.499213 [CA 1] Center 38 (8~68) winsize 61
3069 11:44:44.502762 [CA 2] Center 35 (5~65) winsize 61
3070 11:44:44.506494 [CA 3] Center 34 (4~65) winsize 62
3071 11:44:44.509419 [CA 4] Center 34 (4~65) winsize 62
3072 11:44:44.512630 [CA 5] Center 34 (4~64) winsize 61
3073 11:44:44.513105
3074 11:44:44.516186 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3075 11:44:44.516629
3076 11:44:44.519649 [CATrainingPosCal] consider 1 rank data
3077 11:44:44.522988 u2DelayCellTimex100 = 270/100 ps
3078 11:44:44.526514 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3079 11:44:44.529628 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3080 11:44:44.535902 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3081 11:44:44.539439 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3082 11:44:44.542818 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3083 11:44:44.545744 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3084 11:44:44.546171
3085 11:44:44.549365 CA PerBit enable=1, Macro0, CA PI delay=34
3086 11:44:44.549790
3087 11:44:44.552462 [CBTSetCACLKResult] CA Dly = 34
3088 11:44:44.552820 CS Dly: 6 (0~37)
3089 11:44:44.553136 ==
3090 11:44:44.556084 Dram Type= 6, Freq= 0, CH_1, rank 1
3091 11:44:44.562643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 11:44:44.563072 ==
3093 11:44:44.565677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 11:44:44.572299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3095 11:44:44.581410 [CA 0] Center 38 (8~68) winsize 61
3096 11:44:44.584944 [CA 1] Center 38 (8~68) winsize 61
3097 11:44:44.588220 [CA 2] Center 35 (5~65) winsize 61
3098 11:44:44.591828 [CA 3] Center 34 (4~65) winsize 62
3099 11:44:44.594729 [CA 4] Center 34 (4~65) winsize 62
3100 11:44:44.598124 [CA 5] Center 33 (3~63) winsize 61
3101 11:44:44.598600
3102 11:44:44.601288 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3103 11:44:44.601731
3104 11:44:44.604894 [CATrainingPosCal] consider 2 rank data
3105 11:44:44.608534 u2DelayCellTimex100 = 270/100 ps
3106 11:44:44.611616 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3107 11:44:44.614739 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3108 11:44:44.621658 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3109 11:44:44.624604 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3110 11:44:44.628045 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3111 11:44:44.631598 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3112 11:44:44.631757
3113 11:44:44.634965 CA PerBit enable=1, Macro0, CA PI delay=33
3114 11:44:44.635300
3115 11:44:44.638252 [CBTSetCACLKResult] CA Dly = 33
3116 11:44:44.638589 CS Dly: 7 (0~40)
3117 11:44:44.638855
3118 11:44:44.641190 ----->DramcWriteLeveling(PI) begin...
3119 11:44:44.644764 ==
3120 11:44:44.648155 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 11:44:44.651207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 11:44:44.651577 ==
3123 11:44:44.654905 Write leveling (Byte 0): 25 => 25
3124 11:44:44.657906 Write leveling (Byte 1): 28 => 28
3125 11:44:44.661382 DramcWriteLeveling(PI) end<-----
3126 11:44:44.661801
3127 11:44:44.662072 ==
3128 11:44:44.664857 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 11:44:44.668057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 11:44:44.668392 ==
3131 11:44:44.671003 [Gating] SW mode calibration
3132 11:44:44.677695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3133 11:44:44.684511 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3134 11:44:44.687711 0 15 0 | B1->B0 | 2626 2323 | 1 1 | (0 0) (1 1)
3135 11:44:44.691235 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 11:44:44.694863 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 11:44:44.701548 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 11:44:44.704946 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3139 11:44:44.707849 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 11:44:44.714498 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 11:44:44.718295 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3142 11:44:44.721309 1 0 0 | B1->B0 | 2727 2e2e | 0 1 | (1 0) (1 0)
3143 11:44:44.727729 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 11:44:44.731124 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 11:44:44.734582 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 11:44:44.741094 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 11:44:44.744337 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 11:44:44.747871 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 11:44:44.754259 1 0 28 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
3150 11:44:44.758141 1 1 0 | B1->B0 | 4545 3737 | 0 1 | (0 0) (0 0)
3151 11:44:44.761147 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 11:44:44.768101 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 11:44:44.770993 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 11:44:44.774616 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 11:44:44.780929 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 11:44:44.784698 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 11:44:44.787537 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 11:44:44.794239 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3159 11:44:44.797815 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:44:44.801066 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:44:44.807621 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:44:44.811124 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:44:44.814317 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:44:44.817830 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:44:44.824506 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:44:44.827691 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:44:44.831287 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 11:44:44.837878 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:44:44.840806 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:44:44.844122 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:44:44.850796 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:44:44.854146 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:44:44.857694 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3174 11:44:44.864508 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3175 11:44:44.867628 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 11:44:44.871039 Total UI for P1: 0, mck2ui 16
3177 11:44:44.874508 best dqsien dly found for B0: ( 1, 3, 30)
3178 11:44:44.877968 Total UI for P1: 0, mck2ui 16
3179 11:44:44.881081 best dqsien dly found for B1: ( 1, 4, 0)
3180 11:44:44.884157 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3181 11:44:44.887662 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3182 11:44:44.888109
3183 11:44:44.890635 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3184 11:44:44.894277 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3185 11:44:44.897372 [Gating] SW calibration Done
3186 11:44:44.897826 ==
3187 11:44:44.900896 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 11:44:44.904071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 11:44:44.904500 ==
3190 11:44:44.907655 RX Vref Scan: 0
3191 11:44:44.908080
3192 11:44:44.910676 RX Vref 0 -> 0, step: 1
3193 11:44:44.911098
3194 11:44:44.911542 RX Delay -40 -> 252, step: 8
3195 11:44:44.917620 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3196 11:44:44.921129 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3197 11:44:44.924223 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3198 11:44:44.927396 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3199 11:44:44.931088 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3200 11:44:44.937542 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3201 11:44:44.941001 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3202 11:44:44.944265 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3203 11:44:44.947693 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3204 11:44:44.950844 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3205 11:44:44.957329 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3206 11:44:44.960674 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3207 11:44:44.964206 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3208 11:44:44.967458 iDelay=200, Bit 13, Center 119 (56 ~ 183) 128
3209 11:44:44.970899 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3210 11:44:44.977358 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3211 11:44:44.977887 ==
3212 11:44:44.980703 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 11:44:44.983951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 11:44:44.984386 ==
3215 11:44:44.984726 DQS Delay:
3216 11:44:44.987654 DQS0 = 0, DQS1 = 0
3217 11:44:44.988082 DQM Delay:
3218 11:44:44.990667 DQM0 = 116, DQM1 = 109
3219 11:44:44.991096 DQ Delay:
3220 11:44:44.994002 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3221 11:44:44.997341 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3222 11:44:45.001012 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3223 11:44:45.004099 DQ12 =123, DQ13 =119, DQ14 =111, DQ15 =111
3224 11:44:45.004534
3225 11:44:45.004875
3226 11:44:45.007777 ==
3227 11:44:45.008210 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 11:44:45.014439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 11:44:45.014873 ==
3230 11:44:45.015217
3231 11:44:45.015604
3232 11:44:45.017208 TX Vref Scan disable
3233 11:44:45.017737 == TX Byte 0 ==
3234 11:44:45.020674 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3235 11:44:45.027236 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3236 11:44:45.027759 == TX Byte 1 ==
3237 11:44:45.031012 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3238 11:44:45.037728 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3239 11:44:45.038159 ==
3240 11:44:45.040775 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 11:44:45.044417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 11:44:45.044975 ==
3243 11:44:45.056023 TX Vref=22, minBit 1, minWin=25, winSum=410
3244 11:44:45.059062 TX Vref=24, minBit 1, minWin=25, winSum=414
3245 11:44:45.062556 TX Vref=26, minBit 1, minWin=25, winSum=423
3246 11:44:45.066018 TX Vref=28, minBit 1, minWin=26, winSum=428
3247 11:44:45.068912 TX Vref=30, minBit 0, minWin=26, winSum=426
3248 11:44:45.075672 TX Vref=32, minBit 3, minWin=25, winSum=427
3249 11:44:45.079170 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3250 11:44:45.079905
3251 11:44:45.082690 Final TX Range 1 Vref 28
3252 11:44:45.083253
3253 11:44:45.083726 ==
3254 11:44:45.085622 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 11:44:45.089277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 11:44:45.089860 ==
3257 11:44:45.090367
3258 11:44:45.092380
3259 11:44:45.092821 TX Vref Scan disable
3260 11:44:45.095963 == TX Byte 0 ==
3261 11:44:45.098951 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3262 11:44:45.102604 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3263 11:44:45.105673 == TX Byte 1 ==
3264 11:44:45.109297 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 11:44:45.112238 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 11:44:45.116021
3267 11:44:45.116451 [DATLAT]
3268 11:44:45.116887 Freq=1200, CH1 RK0
3269 11:44:45.117297
3270 11:44:45.118925 DATLAT Default: 0xd
3271 11:44:45.119398 0, 0xFFFF, sum = 0
3272 11:44:45.122586 1, 0xFFFF, sum = 0
3273 11:44:45.123027 2, 0xFFFF, sum = 0
3274 11:44:45.125508 3, 0xFFFF, sum = 0
3275 11:44:45.126037 4, 0xFFFF, sum = 0
3276 11:44:45.128935 5, 0xFFFF, sum = 0
3277 11:44:45.132045 6, 0xFFFF, sum = 0
3278 11:44:45.132495 7, 0xFFFF, sum = 0
3279 11:44:45.135763 8, 0xFFFF, sum = 0
3280 11:44:45.136169 9, 0xFFFF, sum = 0
3281 11:44:45.138959 10, 0xFFFF, sum = 0
3282 11:44:45.139419 11, 0xFFFF, sum = 0
3283 11:44:45.141956 12, 0x0, sum = 1
3284 11:44:45.142371 13, 0x0, sum = 2
3285 11:44:45.145514 14, 0x0, sum = 3
3286 11:44:45.145908 15, 0x0, sum = 4
3287 11:44:45.146258 best_step = 13
3288 11:44:45.149078
3289 11:44:45.149477 ==
3290 11:44:45.152128 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 11:44:45.155791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 11:44:45.156208 ==
3293 11:44:45.156574 RX Vref Scan: 1
3294 11:44:45.156910
3295 11:44:45.158921 Set Vref Range= 32 -> 127
3296 11:44:45.159610
3297 11:44:45.161924 RX Vref 32 -> 127, step: 1
3298 11:44:45.162435
3299 11:44:45.165550 RX Delay -21 -> 252, step: 4
3300 11:44:45.166057
3301 11:44:45.168989 Set Vref, RX VrefLevel [Byte0]: 32
3302 11:44:45.172420 [Byte1]: 32
3303 11:44:45.172836
3304 11:44:45.175524 Set Vref, RX VrefLevel [Byte0]: 33
3305 11:44:45.178529 [Byte1]: 33
3306 11:44:45.182147
3307 11:44:45.182602 Set Vref, RX VrefLevel [Byte0]: 34
3308 11:44:45.185177 [Byte1]: 34
3309 11:44:45.189762
3310 11:44:45.190014 Set Vref, RX VrefLevel [Byte0]: 35
3311 11:44:45.193610 [Byte1]: 35
3312 11:44:45.197728
3313 11:44:45.197969 Set Vref, RX VrefLevel [Byte0]: 36
3314 11:44:45.201353 [Byte1]: 36
3315 11:44:45.205588
3316 11:44:45.205829 Set Vref, RX VrefLevel [Byte0]: 37
3317 11:44:45.209143 [Byte1]: 37
3318 11:44:45.213704
3319 11:44:45.214007 Set Vref, RX VrefLevel [Byte0]: 38
3320 11:44:45.217078 [Byte1]: 38
3321 11:44:45.221587
3322 11:44:45.221889 Set Vref, RX VrefLevel [Byte0]: 39
3323 11:44:45.225177 [Byte1]: 39
3324 11:44:45.229232
3325 11:44:45.229504 Set Vref, RX VrefLevel [Byte0]: 40
3326 11:44:45.232840 [Byte1]: 40
3327 11:44:45.237624
3328 11:44:45.237920 Set Vref, RX VrefLevel [Byte0]: 41
3329 11:44:45.240797 [Byte1]: 41
3330 11:44:45.245611
3331 11:44:45.245993 Set Vref, RX VrefLevel [Byte0]: 42
3332 11:44:45.248780 [Byte1]: 42
3333 11:44:45.253542
3334 11:44:45.253927 Set Vref, RX VrefLevel [Byte0]: 43
3335 11:44:45.256545 [Byte1]: 43
3336 11:44:45.261428
3337 11:44:45.264266 Set Vref, RX VrefLevel [Byte0]: 44
3338 11:44:45.264646 [Byte1]: 44
3339 11:44:45.269490
3340 11:44:45.269904 Set Vref, RX VrefLevel [Byte0]: 45
3341 11:44:45.272344 [Byte1]: 45
3342 11:44:45.277111
3343 11:44:45.277689 Set Vref, RX VrefLevel [Byte0]: 46
3344 11:44:45.280057 [Byte1]: 46
3345 11:44:45.285071
3346 11:44:45.285492 Set Vref, RX VrefLevel [Byte0]: 47
3347 11:44:45.288598 [Byte1]: 47
3348 11:44:45.292693
3349 11:44:45.293095 Set Vref, RX VrefLevel [Byte0]: 48
3350 11:44:45.296388 [Byte1]: 48
3351 11:44:45.300815
3352 11:44:45.301188 Set Vref, RX VrefLevel [Byte0]: 49
3353 11:44:45.304164 [Byte1]: 49
3354 11:44:45.309061
3355 11:44:45.309407 Set Vref, RX VrefLevel [Byte0]: 50
3356 11:44:45.312248 [Byte1]: 50
3357 11:44:45.316609
3358 11:44:45.317026 Set Vref, RX VrefLevel [Byte0]: 51
3359 11:44:45.319913 [Byte1]: 51
3360 11:44:45.324623
3361 11:44:45.325037 Set Vref, RX VrefLevel [Byte0]: 52
3362 11:44:45.328075 [Byte1]: 52
3363 11:44:45.332552
3364 11:44:45.332974 Set Vref, RX VrefLevel [Byte0]: 53
3365 11:44:45.336181 [Byte1]: 53
3366 11:44:45.340195
3367 11:44:45.340627 Set Vref, RX VrefLevel [Byte0]: 54
3368 11:44:45.343850 [Byte1]: 54
3369 11:44:45.348148
3370 11:44:45.348579 Set Vref, RX VrefLevel [Byte0]: 55
3371 11:44:45.351811 [Byte1]: 55
3372 11:44:45.356029
3373 11:44:45.356459 Set Vref, RX VrefLevel [Byte0]: 56
3374 11:44:45.359449 [Byte1]: 56
3375 11:44:45.364253
3376 11:44:45.364686 Set Vref, RX VrefLevel [Byte0]: 57
3377 11:44:45.367868 [Byte1]: 57
3378 11:44:45.371988
3379 11:44:45.372418 Set Vref, RX VrefLevel [Byte0]: 58
3380 11:44:45.375464 [Byte1]: 58
3381 11:44:45.380058
3382 11:44:45.380623 Set Vref, RX VrefLevel [Byte0]: 59
3383 11:44:45.383552 [Byte1]: 59
3384 11:44:45.387973
3385 11:44:45.388400 Set Vref, RX VrefLevel [Byte0]: 60
3386 11:44:45.390940 [Byte1]: 60
3387 11:44:45.395874
3388 11:44:45.396367 Set Vref, RX VrefLevel [Byte0]: 61
3389 11:44:45.398933 [Byte1]: 61
3390 11:44:45.403868
3391 11:44:45.404291 Set Vref, RX VrefLevel [Byte0]: 62
3392 11:44:45.407017 [Byte1]: 62
3393 11:44:45.411957
3394 11:44:45.412386 Set Vref, RX VrefLevel [Byte0]: 63
3395 11:44:45.414998 [Byte1]: 63
3396 11:44:45.419845
3397 11:44:45.420274 Set Vref, RX VrefLevel [Byte0]: 64
3398 11:44:45.423392 [Byte1]: 64
3399 11:44:45.428071
3400 11:44:45.428629 Set Vref, RX VrefLevel [Byte0]: 65
3401 11:44:45.430885 [Byte1]: 65
3402 11:44:45.435192
3403 11:44:45.435659 Set Vref, RX VrefLevel [Byte0]: 66
3404 11:44:45.438982 [Byte1]: 66
3405 11:44:45.443639
3406 11:44:45.444069 Set Vref, RX VrefLevel [Byte0]: 67
3407 11:44:45.446656 [Byte1]: 67
3408 11:44:45.451493
3409 11:44:45.452089 Set Vref, RX VrefLevel [Byte0]: 68
3410 11:44:45.454527 [Byte1]: 68
3411 11:44:45.459341
3412 11:44:45.459896 Set Vref, RX VrefLevel [Byte0]: 69
3413 11:44:45.462892 [Byte1]: 69
3414 11:44:45.467153
3415 11:44:45.467620 Set Vref, RX VrefLevel [Byte0]: 70
3416 11:44:45.470624 [Byte1]: 70
3417 11:44:45.475180
3418 11:44:45.475765 Set Vref, RX VrefLevel [Byte0]: 71
3419 11:44:45.478109 [Byte1]: 71
3420 11:44:45.482704
3421 11:44:45.483239 Set Vref, RX VrefLevel [Byte0]: 72
3422 11:44:45.486114 [Byte1]: 72
3423 11:44:45.490791
3424 11:44:45.491217 Final RX Vref Byte 0 = 59 to rank0
3425 11:44:45.494540 Final RX Vref Byte 1 = 54 to rank0
3426 11:44:45.497633 Final RX Vref Byte 0 = 59 to rank1
3427 11:44:45.501265 Final RX Vref Byte 1 = 54 to rank1==
3428 11:44:45.504539 Dram Type= 6, Freq= 0, CH_1, rank 0
3429 11:44:45.511383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 11:44:45.511827 ==
3431 11:44:45.512166 DQS Delay:
3432 11:44:45.512481 DQS0 = 0, DQS1 = 0
3433 11:44:45.514479 DQM Delay:
3434 11:44:45.514907 DQM0 = 116, DQM1 = 109
3435 11:44:45.517545 DQ Delay:
3436 11:44:45.521140 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3437 11:44:45.524160 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3438 11:44:45.527783 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3439 11:44:45.530690 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =114
3440 11:44:45.531170
3441 11:44:45.531742
3442 11:44:45.537508 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3443 11:44:45.541088 CH1 RK0: MR19=303, MR18=FDE1
3444 11:44:45.547568 CH1_RK0: MR19=0x303, MR18=0xFDE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3445 11:44:45.548233
3446 11:44:45.550834 ----->DramcWriteLeveling(PI) begin...
3447 11:44:45.551379 ==
3448 11:44:45.554393 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 11:44:45.557545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 11:44:45.558039 ==
3451 11:44:45.560768 Write leveling (Byte 0): 26 => 26
3452 11:44:45.564401 Write leveling (Byte 1): 27 => 27
3453 11:44:45.568041 DramcWriteLeveling(PI) end<-----
3454 11:44:45.568561
3455 11:44:45.569025 ==
3456 11:44:45.570959 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 11:44:45.577434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 11:44:45.577949 ==
3459 11:44:45.578451 [Gating] SW mode calibration
3460 11:44:45.587595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3461 11:44:45.591112 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3462 11:44:45.593994 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3463 11:44:45.601021 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 11:44:45.604656 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 11:44:45.607602 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 11:44:45.614407 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3467 11:44:45.617958 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3468 11:44:45.621026 0 15 24 | B1->B0 | 3434 2929 | 0 0 | (0 0) (1 0)
3469 11:44:45.627694 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3470 11:44:45.630837 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 11:44:45.634268 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 11:44:45.640746 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 11:44:45.644369 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 11:44:45.647407 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 11:44:45.654019 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3476 11:44:45.657694 1 0 24 | B1->B0 | 2828 4242 | 0 0 | (0 0) (0 0)
3477 11:44:45.660722 1 0 28 | B1->B0 | 4241 4646 | 1 0 | (1 1) (0 0)
3478 11:44:45.667246 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 11:44:45.670153 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 11:44:45.674097 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 11:44:45.680179 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 11:44:45.683720 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 11:44:45.687136 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3484 11:44:45.693678 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3485 11:44:45.697158 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3486 11:44:45.700141 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 11:44:45.703937 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 11:44:45.710490 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 11:44:45.713411 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 11:44:45.716977 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 11:44:45.723277 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 11:44:45.726863 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 11:44:45.729917 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 11:44:45.736653 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 11:44:45.740295 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 11:44:45.743713 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 11:44:45.750310 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 11:44:45.753388 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 11:44:45.756418 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3500 11:44:45.763212 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3501 11:44:45.766804 Total UI for P1: 0, mck2ui 16
3502 11:44:45.769860 best dqsien dly found for B0: ( 1, 3, 20)
3503 11:44:45.773306 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3504 11:44:45.776242 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 11:44:45.779842 Total UI for P1: 0, mck2ui 16
3506 11:44:45.783281 best dqsien dly found for B1: ( 1, 3, 26)
3507 11:44:45.786169 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3508 11:44:45.789774 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3509 11:44:45.789857
3510 11:44:45.796441 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3511 11:44:45.799880 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3512 11:44:45.802849 [Gating] SW calibration Done
3513 11:44:45.802963 ==
3514 11:44:45.806556 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 11:44:45.809625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 11:44:45.809759 ==
3517 11:44:45.809853 RX Vref Scan: 0
3518 11:44:45.809943
3519 11:44:45.812690 RX Vref 0 -> 0, step: 1
3520 11:44:45.812766
3521 11:44:45.816328 RX Delay -40 -> 252, step: 8
3522 11:44:45.819143 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3523 11:44:45.822908 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3524 11:44:45.829510 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3525 11:44:45.832664 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3526 11:44:45.836640 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3527 11:44:45.839481 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3528 11:44:45.843133 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3529 11:44:45.849716 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3530 11:44:45.852786 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3531 11:44:45.856343 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3532 11:44:45.859289 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3533 11:44:45.862778 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3534 11:44:45.869688 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3535 11:44:45.872646 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3536 11:44:45.876253 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3537 11:44:45.879253 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3538 11:44:45.879771 ==
3539 11:44:45.882850 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 11:44:45.889521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 11:44:45.889959 ==
3542 11:44:45.890302 DQS Delay:
3543 11:44:45.892722 DQS0 = 0, DQS1 = 0
3544 11:44:45.893152 DQM Delay:
3545 11:44:45.893495 DQM0 = 114, DQM1 = 111
3546 11:44:45.896101 DQ Delay:
3547 11:44:45.898979 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3548 11:44:45.902674 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3549 11:44:45.905977 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3550 11:44:45.909643 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3551 11:44:45.910079
3552 11:44:45.910420
3553 11:44:45.910738 ==
3554 11:44:45.912727 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 11:44:45.915921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 11:44:45.919599 ==
3557 11:44:45.920025
3558 11:44:45.920360
3559 11:44:45.920668 TX Vref Scan disable
3560 11:44:45.922225 == TX Byte 0 ==
3561 11:44:45.925919 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3562 11:44:45.929424 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3563 11:44:45.932752 == TX Byte 1 ==
3564 11:44:45.935839 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3565 11:44:45.939270 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3566 11:44:45.942367 ==
3567 11:44:45.942926 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 11:44:45.948993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 11:44:45.949427 ==
3570 11:44:45.959950 TX Vref=22, minBit 2, minWin=25, winSum=418
3571 11:44:45.963390 TX Vref=24, minBit 0, minWin=25, winSum=419
3572 11:44:45.966833 TX Vref=26, minBit 0, minWin=26, winSum=429
3573 11:44:45.969901 TX Vref=28, minBit 1, minWin=26, winSum=431
3574 11:44:45.972977 TX Vref=30, minBit 4, minWin=26, winSum=431
3575 11:44:45.979783 TX Vref=32, minBit 2, minWin=26, winSum=430
3576 11:44:45.983247 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3577 11:44:45.983848
3578 11:44:45.986371 Final TX Range 1 Vref 28
3579 11:44:45.986746
3580 11:44:45.987063 ==
3581 11:44:45.989925 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 11:44:45.993216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 11:44:45.993641 ==
3584 11:44:45.996194
3585 11:44:45.996616
3586 11:44:45.996947 TX Vref Scan disable
3587 11:44:45.999887 == TX Byte 0 ==
3588 11:44:46.003400 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3589 11:44:46.006477 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3590 11:44:46.009940 == TX Byte 1 ==
3591 11:44:46.013442 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3592 11:44:46.016500 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3593 11:44:46.016926
3594 11:44:46.019668 [DATLAT]
3595 11:44:46.020093 Freq=1200, CH1 RK1
3596 11:44:46.020431
3597 11:44:46.023270 DATLAT Default: 0xd
3598 11:44:46.023726 0, 0xFFFF, sum = 0
3599 11:44:46.026248 1, 0xFFFF, sum = 0
3600 11:44:46.026683 2, 0xFFFF, sum = 0
3601 11:44:46.029772 3, 0xFFFF, sum = 0
3602 11:44:46.030207 4, 0xFFFF, sum = 0
3603 11:44:46.033390 5, 0xFFFF, sum = 0
3604 11:44:46.036386 6, 0xFFFF, sum = 0
3605 11:44:46.036817 7, 0xFFFF, sum = 0
3606 11:44:46.039492 8, 0xFFFF, sum = 0
3607 11:44:46.039889 9, 0xFFFF, sum = 0
3608 11:44:46.043197 10, 0xFFFF, sum = 0
3609 11:44:46.043665 11, 0xFFFF, sum = 0
3610 11:44:46.046217 12, 0x0, sum = 1
3611 11:44:46.046651 13, 0x0, sum = 2
3612 11:44:46.049908 14, 0x0, sum = 3
3613 11:44:46.050342 15, 0x0, sum = 4
3614 11:44:46.050683 best_step = 13
3615 11:44:46.053019
3616 11:44:46.053443 ==
3617 11:44:46.055979 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 11:44:46.059790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 11:44:46.060227 ==
3620 11:44:46.060570 RX Vref Scan: 0
3621 11:44:46.060885
3622 11:44:46.063229 RX Vref 0 -> 0, step: 1
3623 11:44:46.063728
3624 11:44:46.066245 RX Delay -21 -> 252, step: 4
3625 11:44:46.069364 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3626 11:44:46.075831 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3627 11:44:46.079607 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3628 11:44:46.082631 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3629 11:44:46.085781 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3630 11:44:46.089457 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3631 11:44:46.096483 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3632 11:44:46.099608 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3633 11:44:46.102670 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3634 11:44:46.106363 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3635 11:44:46.109189 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3636 11:44:46.116281 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3637 11:44:46.119167 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3638 11:44:46.122941 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3639 11:44:46.125921 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3640 11:44:46.128941 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3641 11:44:46.132479 ==
3642 11:44:46.136343 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 11:44:46.139259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 11:44:46.139711 ==
3645 11:44:46.140050 DQS Delay:
3646 11:44:46.142278 DQS0 = 0, DQS1 = 0
3647 11:44:46.142704 DQM Delay:
3648 11:44:46.145999 DQM0 = 113, DQM1 = 110
3649 11:44:46.146423 DQ Delay:
3650 11:44:46.149513 DQ0 =112, DQ1 =110, DQ2 =106, DQ3 =112
3651 11:44:46.152627 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3652 11:44:46.155657 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3653 11:44:46.159345 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =120
3654 11:44:46.159806
3655 11:44:46.160146
3656 11:44:46.169223 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3657 11:44:46.172162 CH1 RK1: MR19=303, MR18=F7FE
3658 11:44:46.175647 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3659 11:44:46.178497 [RxdqsGatingPostProcess] freq 1200
3660 11:44:46.185273 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3661 11:44:46.188998 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 11:44:46.191846 best DQS1 dly(2T, 0.5T) = (0, 12)
3663 11:44:46.195566 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 11:44:46.198504 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3665 11:44:46.202041 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 11:44:46.205087 best DQS1 dly(2T, 0.5T) = (0, 11)
3667 11:44:46.208825 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 11:44:46.212324 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3669 11:44:46.215193 Pre-setting of DQS Precalculation
3670 11:44:46.218627 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3671 11:44:46.225130 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3672 11:44:46.231840 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3673 11:44:46.232367
3674 11:44:46.235313
3675 11:44:46.235731 [Calibration Summary] 2400 Mbps
3676 11:44:46.238996 CH 0, Rank 0
3677 11:44:46.239462 SW Impedance : PASS
3678 11:44:46.241814 DUTY Scan : NO K
3679 11:44:46.244970 ZQ Calibration : PASS
3680 11:44:46.245406 Jitter Meter : NO K
3681 11:44:46.248620 CBT Training : PASS
3682 11:44:46.252090 Write leveling : PASS
3683 11:44:46.252856 RX DQS gating : PASS
3684 11:44:46.255050 RX DQ/DQS(RDDQC) : PASS
3685 11:44:46.258766 TX DQ/DQS : PASS
3686 11:44:46.259200 RX DATLAT : PASS
3687 11:44:46.261808 RX DQ/DQS(Engine): PASS
3688 11:44:46.262239 TX OE : NO K
3689 11:44:46.265045 All Pass.
3690 11:44:46.265475
3691 11:44:46.265814 CH 0, Rank 1
3692 11:44:46.268672 SW Impedance : PASS
3693 11:44:46.269103 DUTY Scan : NO K
3694 11:44:46.271779 ZQ Calibration : PASS
3695 11:44:46.275295 Jitter Meter : NO K
3696 11:44:46.275732 CBT Training : PASS
3697 11:44:46.278471 Write leveling : PASS
3698 11:44:46.281816 RX DQS gating : PASS
3699 11:44:46.282427 RX DQ/DQS(RDDQC) : PASS
3700 11:44:46.284824 TX DQ/DQS : PASS
3701 11:44:46.288605 RX DATLAT : PASS
3702 11:44:46.289072 RX DQ/DQS(Engine): PASS
3703 11:44:46.291771 TX OE : NO K
3704 11:44:46.292218 All Pass.
3705 11:44:46.292559
3706 11:44:46.294885 CH 1, Rank 0
3707 11:44:46.295309 SW Impedance : PASS
3708 11:44:46.298481 DUTY Scan : NO K
3709 11:44:46.301478 ZQ Calibration : PASS
3710 11:44:46.301982 Jitter Meter : NO K
3711 11:44:46.304896 CBT Training : PASS
3712 11:44:46.308384 Write leveling : PASS
3713 11:44:46.308976 RX DQS gating : PASS
3714 11:44:46.311996 RX DQ/DQS(RDDQC) : PASS
3715 11:44:46.312430 TX DQ/DQS : PASS
3716 11:44:46.315041 RX DATLAT : PASS
3717 11:44:46.318443 RX DQ/DQS(Engine): PASS
3718 11:44:46.318972 TX OE : NO K
3719 11:44:46.321974 All Pass.
3720 11:44:46.322342
3721 11:44:46.322657 CH 1, Rank 1
3722 11:44:46.324874 SW Impedance : PASS
3723 11:44:46.325299 DUTY Scan : NO K
3724 11:44:46.328443 ZQ Calibration : PASS
3725 11:44:46.331452 Jitter Meter : NO K
3726 11:44:46.331828 CBT Training : PASS
3727 11:44:46.335413 Write leveling : PASS
3728 11:44:46.338424 RX DQS gating : PASS
3729 11:44:46.338855 RX DQ/DQS(RDDQC) : PASS
3730 11:44:46.341814 TX DQ/DQS : PASS
3731 11:44:46.345397 RX DATLAT : PASS
3732 11:44:46.345874 RX DQ/DQS(Engine): PASS
3733 11:44:46.348490 TX OE : NO K
3734 11:44:46.348923 All Pass.
3735 11:44:46.349261
3736 11:44:46.351647 DramC Write-DBI off
3737 11:44:46.355006 PER_BANK_REFRESH: Hybrid Mode
3738 11:44:46.355451 TX_TRACKING: ON
3739 11:44:46.364945 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3740 11:44:46.367977 [FAST_K] Save calibration result to emmc
3741 11:44:46.371734 dramc_set_vcore_voltage set vcore to 650000
3742 11:44:46.374680 Read voltage for 600, 5
3743 11:44:46.375105 Vio18 = 0
3744 11:44:46.375485 Vcore = 650000
3745 11:44:46.377915 Vdram = 0
3746 11:44:46.378362 Vddq = 0
3747 11:44:46.378685 Vmddr = 0
3748 11:44:46.384574 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3749 11:44:46.388130 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3750 11:44:46.391051 MEM_TYPE=3, freq_sel=19
3751 11:44:46.394782 sv_algorithm_assistance_LP4_1600
3752 11:44:46.397851 ============ PULL DRAM RESETB DOWN ============
3753 11:44:46.401477 ========== PULL DRAM RESETB DOWN end =========
3754 11:44:46.408003 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3755 11:44:46.411447 ===================================
3756 11:44:46.411995 LPDDR4 DRAM CONFIGURATION
3757 11:44:46.414354 ===================================
3758 11:44:46.418135 EX_ROW_EN[0] = 0x0
3759 11:44:46.421225 EX_ROW_EN[1] = 0x0
3760 11:44:46.421788 LP4Y_EN = 0x0
3761 11:44:46.424749 WORK_FSP = 0x0
3762 11:44:46.425183 WL = 0x2
3763 11:44:46.428214 RL = 0x2
3764 11:44:46.428668 BL = 0x2
3765 11:44:46.431768 RPST = 0x0
3766 11:44:46.432429 RD_PRE = 0x0
3767 11:44:46.434915 WR_PRE = 0x1
3768 11:44:46.435365 WR_PST = 0x0
3769 11:44:46.437986 DBI_WR = 0x0
3770 11:44:46.438611 DBI_RD = 0x0
3771 11:44:46.441608 OTF = 0x1
3772 11:44:46.444586 ===================================
3773 11:44:46.447800 ===================================
3774 11:44:46.448248 ANA top config
3775 11:44:46.451159 ===================================
3776 11:44:46.454582 DLL_ASYNC_EN = 0
3777 11:44:46.457623 ALL_SLAVE_EN = 1
3778 11:44:46.461409 NEW_RANK_MODE = 1
3779 11:44:46.461839 DLL_IDLE_MODE = 1
3780 11:44:46.464437 LP45_APHY_COMB_EN = 1
3781 11:44:46.468174 TX_ODT_DIS = 1
3782 11:44:46.471141 NEW_8X_MODE = 1
3783 11:44:46.474366 ===================================
3784 11:44:46.477834 ===================================
3785 11:44:46.481465 data_rate = 1200
3786 11:44:46.482008 CKR = 1
3787 11:44:46.484450 DQ_P2S_RATIO = 8
3788 11:44:46.487449 ===================================
3789 11:44:46.490969 CA_P2S_RATIO = 8
3790 11:44:46.494716 DQ_CA_OPEN = 0
3791 11:44:46.497825 DQ_SEMI_OPEN = 0
3792 11:44:46.500819 CA_SEMI_OPEN = 0
3793 11:44:46.501361 CA_FULL_RATE = 0
3794 11:44:46.504471 DQ_CKDIV4_EN = 1
3795 11:44:46.507894 CA_CKDIV4_EN = 1
3796 11:44:46.510685 CA_PREDIV_EN = 0
3797 11:44:46.514394 PH8_DLY = 0
3798 11:44:46.517887 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3799 11:44:46.518318 DQ_AAMCK_DIV = 4
3800 11:44:46.520885 CA_AAMCK_DIV = 4
3801 11:44:46.524478 CA_ADMCK_DIV = 4
3802 11:44:46.527532 DQ_TRACK_CA_EN = 0
3803 11:44:46.531031 CA_PICK = 600
3804 11:44:46.534598 CA_MCKIO = 600
3805 11:44:46.535032 MCKIO_SEMI = 0
3806 11:44:46.537506 PLL_FREQ = 2288
3807 11:44:46.541113 DQ_UI_PI_RATIO = 32
3808 11:44:46.544199 CA_UI_PI_RATIO = 0
3809 11:44:46.547769 ===================================
3810 11:44:46.551686 ===================================
3811 11:44:46.554238 memory_type:LPDDR4
3812 11:44:46.554671 GP_NUM : 10
3813 11:44:46.557605 SRAM_EN : 1
3814 11:44:46.561196 MD32_EN : 0
3815 11:44:46.564356 ===================================
3816 11:44:46.564788 [ANA_INIT] >>>>>>>>>>>>>>
3817 11:44:46.567925 <<<<<< [CONFIGURE PHASE]: ANA_TX
3818 11:44:46.570947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3819 11:44:46.574064 ===================================
3820 11:44:46.577827 data_rate = 1200,PCW = 0X5800
3821 11:44:46.580732 ===================================
3822 11:44:46.584386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3823 11:44:46.590507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 11:44:46.594079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 11:44:46.600867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3826 11:44:46.603995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3827 11:44:46.606975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3828 11:44:46.607454 [ANA_INIT] flow start
3829 11:44:46.610614 [ANA_INIT] PLL >>>>>>>>
3830 11:44:46.614193 [ANA_INIT] PLL <<<<<<<<
3831 11:44:46.614629 [ANA_INIT] MIDPI >>>>>>>>
3832 11:44:46.617270 [ANA_INIT] MIDPI <<<<<<<<
3833 11:44:46.620528 [ANA_INIT] DLL >>>>>>>>
3834 11:44:46.620915 [ANA_INIT] flow end
3835 11:44:46.627226 ============ LP4 DIFF to SE enter ============
3836 11:44:46.630701 ============ LP4 DIFF to SE exit ============
3837 11:44:46.633630 [ANA_INIT] <<<<<<<<<<<<<
3838 11:44:46.637137 [Flow] Enable top DCM control >>>>>
3839 11:44:46.640700 [Flow] Enable top DCM control <<<<<
3840 11:44:46.643913 Enable DLL master slave shuffle
3841 11:44:46.646887 ==============================================================
3842 11:44:46.650662 Gating Mode config
3843 11:44:46.653502 ==============================================================
3844 11:44:46.657035 Config description:
3845 11:44:46.666849 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3846 11:44:46.673809 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3847 11:44:46.676734 SELPH_MODE 0: By rank 1: By Phase
3848 11:44:46.683449 ==============================================================
3849 11:44:46.687040 GAT_TRACK_EN = 1
3850 11:44:46.689998 RX_GATING_MODE = 2
3851 11:44:46.693659 RX_GATING_TRACK_MODE = 2
3852 11:44:46.696814 SELPH_MODE = 1
3853 11:44:46.700356 PICG_EARLY_EN = 1
3854 11:44:46.700787 VALID_LAT_VALUE = 1
3855 11:44:46.706954 ==============================================================
3856 11:44:46.709966 Enter into Gating configuration >>>>
3857 11:44:46.713629 Exit from Gating configuration <<<<
3858 11:44:46.717030 Enter into DVFS_PRE_config >>>>>
3859 11:44:46.726693 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3860 11:44:46.730196 Exit from DVFS_PRE_config <<<<<
3861 11:44:46.733079 Enter into PICG configuration >>>>
3862 11:44:46.736663 Exit from PICG configuration <<<<
3863 11:44:46.740232 [RX_INPUT] configuration >>>>>
3864 11:44:46.742988 [RX_INPUT] configuration <<<<<
3865 11:44:46.746714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3866 11:44:46.753475 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3867 11:44:46.760113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 11:44:46.766479 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 11:44:46.773015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 11:44:46.779659 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 11:44:46.783473 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3872 11:44:46.786363 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3873 11:44:46.789508 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3874 11:44:46.793069 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3875 11:44:46.799710 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3876 11:44:46.802588 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 11:44:46.806372 ===================================
3878 11:44:46.809384 LPDDR4 DRAM CONFIGURATION
3879 11:44:46.813185 ===================================
3880 11:44:46.813615 EX_ROW_EN[0] = 0x0
3881 11:44:46.816427 EX_ROW_EN[1] = 0x0
3882 11:44:46.816856 LP4Y_EN = 0x0
3883 11:44:46.819846 WORK_FSP = 0x0
3884 11:44:46.820435 WL = 0x2
3885 11:44:46.822617 RL = 0x2
3886 11:44:46.826243 BL = 0x2
3887 11:44:46.826612 RPST = 0x0
3888 11:44:46.829275 RD_PRE = 0x0
3889 11:44:46.829669 WR_PRE = 0x1
3890 11:44:46.832751 WR_PST = 0x0
3891 11:44:46.833172 DBI_WR = 0x0
3892 11:44:46.836347 DBI_RD = 0x0
3893 11:44:46.836650 OTF = 0x1
3894 11:44:46.839427 ===================================
3895 11:44:46.842966 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3896 11:44:46.849497 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3897 11:44:46.852550 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 11:44:46.856155 ===================================
3899 11:44:46.859875 LPDDR4 DRAM CONFIGURATION
3900 11:44:46.862775 ===================================
3901 11:44:46.863203 EX_ROW_EN[0] = 0x10
3902 11:44:46.866276 EX_ROW_EN[1] = 0x0
3903 11:44:46.866836 LP4Y_EN = 0x0
3904 11:44:46.869293 WORK_FSP = 0x0
3905 11:44:46.869719 WL = 0x2
3906 11:44:46.872728 RL = 0x2
3907 11:44:46.873153 BL = 0x2
3908 11:44:46.876147 RPST = 0x0
3909 11:44:46.876671 RD_PRE = 0x0
3910 11:44:46.879747 WR_PRE = 0x1
3911 11:44:46.880175 WR_PST = 0x0
3912 11:44:46.882894 DBI_WR = 0x0
3913 11:44:46.883504 DBI_RD = 0x0
3914 11:44:46.886024 OTF = 0x1
3915 11:44:46.889656 ===================================
3916 11:44:46.896301 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3917 11:44:46.899260 nWR fixed to 30
3918 11:44:46.902496 [ModeRegInit_LP4] CH0 RK0
3919 11:44:46.902929 [ModeRegInit_LP4] CH0 RK1
3920 11:44:46.906280 [ModeRegInit_LP4] CH1 RK0
3921 11:44:46.909781 [ModeRegInit_LP4] CH1 RK1
3922 11:44:46.910212 match AC timing 17
3923 11:44:46.915879 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3924 11:44:46.919702 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3925 11:44:46.922620 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3926 11:44:46.929041 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3927 11:44:46.932623 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3928 11:44:46.933055 ==
3929 11:44:46.935639 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 11:44:46.939061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 11:44:46.939530 ==
3932 11:44:46.946134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 11:44:46.952647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3934 11:44:46.956174 [CA 0] Center 36 (6~66) winsize 61
3935 11:44:46.959168 [CA 1] Center 36 (6~66) winsize 61
3936 11:44:46.962789 [CA 2] Center 34 (4~65) winsize 62
3937 11:44:46.965779 [CA 3] Center 34 (4~65) winsize 62
3938 11:44:46.969493 [CA 4] Center 34 (4~64) winsize 61
3939 11:44:46.972606 [CA 5] Center 33 (3~64) winsize 62
3940 11:44:46.973036
3941 11:44:46.976018 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3942 11:44:46.976452
3943 11:44:46.979504 [CATrainingPosCal] consider 1 rank data
3944 11:44:46.982859 u2DelayCellTimex100 = 270/100 ps
3945 11:44:46.985943 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3946 11:44:46.989545 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3947 11:44:46.992549 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 11:44:46.996224 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3949 11:44:46.999378 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3950 11:44:47.002909 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 11:44:47.003498
3952 11:44:47.009507 CA PerBit enable=1, Macro0, CA PI delay=33
3953 11:44:47.010070
3954 11:44:47.012520 [CBTSetCACLKResult] CA Dly = 33
3955 11:44:47.013153 CS Dly: 4 (0~35)
3956 11:44:47.013716 ==
3957 11:44:47.015988 Dram Type= 6, Freq= 0, CH_0, rank 1
3958 11:44:47.018985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 11:44:47.019526 ==
3960 11:44:47.025914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 11:44:47.032779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3962 11:44:47.036360 [CA 0] Center 36 (6~66) winsize 61
3963 11:44:47.038800 [CA 1] Center 35 (5~66) winsize 62
3964 11:44:47.042356 [CA 2] Center 34 (4~65) winsize 62
3965 11:44:47.045773 [CA 3] Center 34 (4~65) winsize 62
3966 11:44:47.049184 [CA 4] Center 33 (3~64) winsize 62
3967 11:44:47.052395 [CA 5] Center 33 (3~64) winsize 62
3968 11:44:47.052827
3969 11:44:47.055899 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3970 11:44:47.056339
3971 11:44:47.059175 [CATrainingPosCal] consider 2 rank data
3972 11:44:47.062232 u2DelayCellTimex100 = 270/100 ps
3973 11:44:47.065307 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 11:44:47.068917 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 11:44:47.072089 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 11:44:47.075563 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3977 11:44:47.081889 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3978 11:44:47.085154 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 11:44:47.085716
3980 11:44:47.089032 CA PerBit enable=1, Macro0, CA PI delay=33
3981 11:44:47.089466
3982 11:44:47.091994 [CBTSetCACLKResult] CA Dly = 33
3983 11:44:47.092426 CS Dly: 4 (0~36)
3984 11:44:47.092767
3985 11:44:47.095620 ----->DramcWriteLeveling(PI) begin...
3986 11:44:47.096060 ==
3987 11:44:47.098491 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 11:44:47.105393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 11:44:47.105831 ==
3990 11:44:47.108682 Write leveling (Byte 0): 34 => 34
3991 11:44:47.109113 Write leveling (Byte 1): 31 => 31
3992 11:44:47.112114 DramcWriteLeveling(PI) end<-----
3993 11:44:47.112676
3994 11:44:47.115189 ==
3995 11:44:47.115662 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 11:44:47.121754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 11:44:47.122320 ==
3998 11:44:47.125363 [Gating] SW mode calibration
3999 11:44:47.131454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4000 11:44:47.135234 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4001 11:44:47.141542 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 11:44:47.145219 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 11:44:47.148740 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 11:44:47.154877 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4005 11:44:47.158274 0 9 16 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (0 0)
4006 11:44:47.161679 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 11:44:47.168183 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 11:44:47.171844 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 11:44:47.175410 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 11:44:47.181519 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 11:44:47.184467 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 11:44:47.188094 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4013 11:44:47.194714 0 10 16 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
4014 11:44:47.198092 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4015 11:44:47.201545 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 11:44:47.207768 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 11:44:47.211446 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 11:44:47.214512 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 11:44:47.221016 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 11:44:47.224357 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 11:44:47.228087 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4022 11:44:47.231110 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 11:44:47.238299 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 11:44:47.241290 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 11:44:47.244607 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 11:44:47.251269 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 11:44:47.254715 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 11:44:47.257969 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 11:44:47.264581 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 11:44:47.268010 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 11:44:47.271029 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 11:44:47.278089 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 11:44:47.281284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 11:44:47.284120 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 11:44:47.290917 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 11:44:47.294287 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 11:44:47.297338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4038 11:44:47.300993 Total UI for P1: 0, mck2ui 16
4039 11:44:47.304096 best dqsien dly found for B0: ( 0, 13, 14)
4040 11:44:47.310988 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 11:44:47.311460 Total UI for P1: 0, mck2ui 16
4042 11:44:47.317652 best dqsien dly found for B1: ( 0, 13, 16)
4043 11:44:47.320644 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4044 11:44:47.323762 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4045 11:44:47.324197
4046 11:44:47.327316 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4047 11:44:47.330961 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4048 11:44:47.333963 [Gating] SW calibration Done
4049 11:44:47.334397 ==
4050 11:44:47.337671 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 11:44:47.340801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 11:44:47.341237 ==
4053 11:44:47.343887 RX Vref Scan: 0
4054 11:44:47.344319
4055 11:44:47.344664 RX Vref 0 -> 0, step: 1
4056 11:44:47.347408
4057 11:44:47.347840 RX Delay -230 -> 252, step: 16
4058 11:44:47.353959 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4059 11:44:47.357418 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4060 11:44:47.360417 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4061 11:44:47.363961 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4062 11:44:47.370326 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4063 11:44:47.373840 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4064 11:44:47.377358 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4065 11:44:47.380143 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4066 11:44:47.384007 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4067 11:44:47.390647 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4068 11:44:47.393550 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4069 11:44:47.397169 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4070 11:44:47.400106 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4071 11:44:47.406771 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4072 11:44:47.409962 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4073 11:44:47.413512 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4074 11:44:47.413982 ==
4075 11:44:47.416974 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 11:44:47.420154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 11:44:47.423843 ==
4078 11:44:47.424277 DQS Delay:
4079 11:44:47.424621 DQS0 = 0, DQS1 = 0
4080 11:44:47.426824 DQM Delay:
4081 11:44:47.427256 DQM0 = 40, DQM1 = 33
4082 11:44:47.429955 DQ Delay:
4083 11:44:47.430387 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4084 11:44:47.433412 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4085 11:44:47.436564 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4086 11:44:47.440174 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4087 11:44:47.443138
4088 11:44:47.443595
4089 11:44:47.443937 ==
4090 11:44:47.446885 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 11:44:47.449894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 11:44:47.450331 ==
4093 11:44:47.450672
4094 11:44:47.450988
4095 11:44:47.453436 TX Vref Scan disable
4096 11:44:47.453868 == TX Byte 0 ==
4097 11:44:47.459942 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4098 11:44:47.463603 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4099 11:44:47.464074 == TX Byte 1 ==
4100 11:44:47.469628 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4101 11:44:47.473106 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4102 11:44:47.473631 ==
4103 11:44:47.476588 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 11:44:47.479595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 11:44:47.480078 ==
4106 11:44:47.480422
4107 11:44:47.480738
4108 11:44:47.482958 TX Vref Scan disable
4109 11:44:47.486548 == TX Byte 0 ==
4110 11:44:47.489496 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4111 11:44:47.493227 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4112 11:44:47.496372 == TX Byte 1 ==
4113 11:44:47.499545 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4114 11:44:47.502942 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4115 11:44:47.506623
4116 11:44:47.507053 [DATLAT]
4117 11:44:47.507433 Freq=600, CH0 RK0
4118 11:44:47.507773
4119 11:44:47.509702 DATLAT Default: 0x9
4120 11:44:47.510132 0, 0xFFFF, sum = 0
4121 11:44:47.512763 1, 0xFFFF, sum = 0
4122 11:44:47.513203 2, 0xFFFF, sum = 0
4123 11:44:47.516473 3, 0xFFFF, sum = 0
4124 11:44:47.516913 4, 0xFFFF, sum = 0
4125 11:44:47.519683 5, 0xFFFF, sum = 0
4126 11:44:47.522706 6, 0xFFFF, sum = 0
4127 11:44:47.523148 7, 0xFFFF, sum = 0
4128 11:44:47.523569 8, 0x0, sum = 1
4129 11:44:47.526279 9, 0x0, sum = 2
4130 11:44:47.526718 10, 0x0, sum = 3
4131 11:44:47.529358 11, 0x0, sum = 4
4132 11:44:47.529797 best_step = 9
4133 11:44:47.530139
4134 11:44:47.530456 ==
4135 11:44:47.532965 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 11:44:47.539623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 11:44:47.540062 ==
4138 11:44:47.540406 RX Vref Scan: 1
4139 11:44:47.540725
4140 11:44:47.542712 RX Vref 0 -> 0, step: 1
4141 11:44:47.543139
4142 11:44:47.545849 RX Delay -195 -> 252, step: 8
4143 11:44:47.546278
4144 11:44:47.549542 Set Vref, RX VrefLevel [Byte0]: 51
4145 11:44:47.552414 [Byte1]: 51
4146 11:44:47.552846
4147 11:44:47.556065 Final RX Vref Byte 0 = 51 to rank0
4148 11:44:47.559297 Final RX Vref Byte 1 = 51 to rank0
4149 11:44:47.563112 Final RX Vref Byte 0 = 51 to rank1
4150 11:44:47.565792 Final RX Vref Byte 1 = 51 to rank1==
4151 11:44:47.569267 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 11:44:47.572728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 11:44:47.573482 ==
4154 11:44:47.575813 DQS Delay:
4155 11:44:47.576370 DQS0 = 0, DQS1 = 0
4156 11:44:47.579173 DQM Delay:
4157 11:44:47.579681 DQM0 = 42, DQM1 = 33
4158 11:44:47.580031 DQ Delay:
4159 11:44:47.582642 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4160 11:44:47.585523 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4161 11:44:47.588909 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4162 11:44:47.592583 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4163 11:44:47.593016
4164 11:44:47.593361
4165 11:44:47.602349 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4166 11:44:47.605493 CH0 RK0: MR19=808, MR18=3F1E
4167 11:44:47.612502 CH0_RK0: MR19=0x808, MR18=0x3F1E, DQSOSC=397, MR23=63, INC=166, DEC=110
4168 11:44:47.613037
4169 11:44:47.615618 ----->DramcWriteLeveling(PI) begin...
4170 11:44:47.616056 ==
4171 11:44:47.618850 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 11:44:47.621913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 11:44:47.622344 ==
4174 11:44:47.624982 Write leveling (Byte 0): 34 => 34
4175 11:44:47.628664 Write leveling (Byte 1): 30 => 30
4176 11:44:47.631721 DramcWriteLeveling(PI) end<-----
4177 11:44:47.632146
4178 11:44:47.632488 ==
4179 11:44:47.635385 Dram Type= 6, Freq= 0, CH_0, rank 1
4180 11:44:47.638523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 11:44:47.638953 ==
4182 11:44:47.641961 [Gating] SW mode calibration
4183 11:44:47.648691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4184 11:44:47.655433 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4185 11:44:47.658457 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 11:44:47.661979 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 11:44:47.668545 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 11:44:47.671899 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
4189 11:44:47.674806 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
4190 11:44:47.681413 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4191 11:44:47.684796 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 11:44:47.688269 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 11:44:47.694808 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 11:44:47.698336 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 11:44:47.701328 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 11:44:47.708144 0 10 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
4197 11:44:47.711800 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4198 11:44:47.715050 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 11:44:47.721724 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 11:44:47.724834 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 11:44:47.728144 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 11:44:47.734669 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 11:44:47.738383 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 11:44:47.741392 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4205 11:44:47.744567 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4206 11:44:47.751498 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 11:44:47.754465 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 11:44:47.758254 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 11:44:47.764437 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 11:44:47.767926 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 11:44:47.770972 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 11:44:47.778006 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 11:44:47.781116 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 11:44:47.784584 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 11:44:47.790946 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 11:44:47.794693 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 11:44:47.797529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 11:44:47.804557 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 11:44:47.807625 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 11:44:47.811216 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4221 11:44:47.818003 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4222 11:44:47.820949 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 11:44:47.824645 Total UI for P1: 0, mck2ui 16
4224 11:44:47.827925 best dqsien dly found for B0: ( 0, 13, 14)
4225 11:44:47.830843 Total UI for P1: 0, mck2ui 16
4226 11:44:47.834590 best dqsien dly found for B1: ( 0, 13, 16)
4227 11:44:47.837693 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4228 11:44:47.841444 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4229 11:44:47.842006
4230 11:44:47.844364 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4231 11:44:47.847384 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4232 11:44:47.851156 [Gating] SW calibration Done
4233 11:44:47.851628 ==
4234 11:44:47.854124 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 11:44:47.860893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 11:44:47.861322 ==
4237 11:44:47.861658 RX Vref Scan: 0
4238 11:44:47.861972
4239 11:44:47.863990 RX Vref 0 -> 0, step: 1
4240 11:44:47.864417
4241 11:44:47.867795 RX Delay -230 -> 252, step: 16
4242 11:44:47.870680 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4243 11:44:47.874188 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4244 11:44:47.877694 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4245 11:44:47.883872 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4246 11:44:47.887258 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4247 11:44:47.890553 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4248 11:44:47.894231 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4249 11:44:47.897107 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4250 11:44:47.904055 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4251 11:44:47.907421 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4252 11:44:47.910548 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4253 11:44:47.913642 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4254 11:44:47.920454 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4255 11:44:47.924171 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4256 11:44:47.926968 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4257 11:44:47.930562 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4258 11:44:47.933688 ==
4259 11:44:47.934248 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 11:44:47.940517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 11:44:47.941073 ==
4262 11:44:47.941554 DQS Delay:
4263 11:44:47.943484 DQS0 = 0, DQS1 = 0
4264 11:44:47.943917 DQM Delay:
4265 11:44:47.947233 DQM0 = 42, DQM1 = 35
4266 11:44:47.947711 DQ Delay:
4267 11:44:47.950319 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4268 11:44:47.953360 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4269 11:44:47.957001 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4270 11:44:47.960428 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4271 11:44:47.960853
4272 11:44:47.961196
4273 11:44:47.961512 ==
4274 11:44:47.963693 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 11:44:47.966554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 11:44:47.966909 ==
4277 11:44:47.967475
4278 11:44:47.967799
4279 11:44:47.970372 TX Vref Scan disable
4280 11:44:47.973449 == TX Byte 0 ==
4281 11:44:47.976346 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4282 11:44:47.979861 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4283 11:44:47.983377 == TX Byte 1 ==
4284 11:44:47.986301 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4285 11:44:47.989726 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4286 11:44:47.990353 ==
4287 11:44:47.992863 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 11:44:47.999344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 11:44:47.999819 ==
4290 11:44:48.000262
4291 11:44:48.000597
4292 11:44:48.000908 TX Vref Scan disable
4293 11:44:48.004055 == TX Byte 0 ==
4294 11:44:48.007449 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4295 11:44:48.014002 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4296 11:44:48.014429 == TX Byte 1 ==
4297 11:44:48.017188 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4298 11:44:48.023920 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4299 11:44:48.024346
4300 11:44:48.024679 [DATLAT]
4301 11:44:48.024986 Freq=600, CH0 RK1
4302 11:44:48.025284
4303 11:44:48.027029 DATLAT Default: 0x9
4304 11:44:48.027490 0, 0xFFFF, sum = 0
4305 11:44:48.030481 1, 0xFFFF, sum = 0
4306 11:44:48.033727 2, 0xFFFF, sum = 0
4307 11:44:48.034153 3, 0xFFFF, sum = 0
4308 11:44:48.037413 4, 0xFFFF, sum = 0
4309 11:44:48.037840 5, 0xFFFF, sum = 0
4310 11:44:48.040420 6, 0xFFFF, sum = 0
4311 11:44:48.040847 7, 0xFFFF, sum = 0
4312 11:44:48.043793 8, 0x0, sum = 1
4313 11:44:48.044219 9, 0x0, sum = 2
4314 11:44:48.044556 10, 0x0, sum = 3
4315 11:44:48.047195 11, 0x0, sum = 4
4316 11:44:48.047651 best_step = 9
4317 11:44:48.048008
4318 11:44:48.050431 ==
4319 11:44:48.053915 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 11:44:48.057040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 11:44:48.057462 ==
4322 11:44:48.057868 RX Vref Scan: 0
4323 11:44:48.058196
4324 11:44:48.060015 RX Vref 0 -> 0, step: 1
4325 11:44:48.060439
4326 11:44:48.063535 RX Delay -195 -> 252, step: 8
4327 11:44:48.070129 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4328 11:44:48.073259 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4329 11:44:48.076878 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4330 11:44:48.079943 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4331 11:44:48.083390 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4332 11:44:48.089633 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4333 11:44:48.093082 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4334 11:44:48.096489 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4335 11:44:48.099425 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4336 11:44:48.106135 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4337 11:44:48.109693 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4338 11:44:48.113165 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4339 11:44:48.116587 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4340 11:44:48.123420 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4341 11:44:48.126307 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4342 11:44:48.129384 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4343 11:44:48.129937 ==
4344 11:44:48.132947 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 11:44:48.136546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 11:44:48.139552 ==
4347 11:44:48.139982 DQS Delay:
4348 11:44:48.140319 DQS0 = 0, DQS1 = 0
4349 11:44:48.142654 DQM Delay:
4350 11:44:48.143077 DQM0 = 40, DQM1 = 33
4351 11:44:48.146192 DQ Delay:
4352 11:44:48.146612 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4353 11:44:48.149191 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4354 11:44:48.152414 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4355 11:44:48.156141 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4356 11:44:48.156223
4357 11:44:48.156287
4358 11:44:48.165850 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4359 11:44:48.169423 CH0 RK1: MR19=808, MR18=4E2F
4360 11:44:48.175563 CH0_RK1: MR19=0x808, MR18=0x4E2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4361 11:44:48.178663 [RxdqsGatingPostProcess] freq 600
4362 11:44:48.182221 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4363 11:44:48.185754 Pre-setting of DQS Precalculation
4364 11:44:48.192406 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4365 11:44:48.192497 ==
4366 11:44:48.195906 Dram Type= 6, Freq= 0, CH_1, rank 0
4367 11:44:48.199341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 11:44:48.199451 ==
4369 11:44:48.205746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 11:44:48.208692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4371 11:44:48.212801 [CA 0] Center 35 (5~65) winsize 61
4372 11:44:48.216189 [CA 1] Center 35 (5~66) winsize 62
4373 11:44:48.219625 [CA 2] Center 34 (4~64) winsize 61
4374 11:44:48.222896 [CA 3] Center 33 (3~64) winsize 62
4375 11:44:48.226666 [CA 4] Center 34 (3~65) winsize 63
4376 11:44:48.229706 [CA 5] Center 33 (3~64) winsize 62
4377 11:44:48.229834
4378 11:44:48.232883 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4379 11:44:48.232967
4380 11:44:48.402869 [CATrainingPosCal] consider 1 rank data
4381 11:44:48.404258 u2DelayCellTimex100 = 270/100 ps
4382 11:44:48.404955 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4383 11:44:48.405658 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4384 11:44:48.406345 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4385 11:44:48.407021 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4386 11:44:48.407719 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4387 11:44:48.408376 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 11:44:48.409021
4389 11:44:48.409665 CA PerBit enable=1, Macro0, CA PI delay=33
4390 11:44:48.410326
4391 11:44:48.410909 [CBTSetCACLKResult] CA Dly = 33
4392 11:44:48.411599 CS Dly: 4 (0~35)
4393 11:44:48.412195 ==
4394 11:44:48.412873 Dram Type= 6, Freq= 0, CH_1, rank 1
4395 11:44:48.413539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 11:44:48.414192 ==
4397 11:44:48.414852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 11:44:48.417570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4399 11:44:48.418342 [CA 0] Center 35 (5~66) winsize 62
4400 11:44:48.418962 [CA 1] Center 35 (5~66) winsize 62
4401 11:44:48.419645 [CA 2] Center 34 (4~65) winsize 62
4402 11:44:48.420311 [CA 3] Center 34 (3~65) winsize 63
4403 11:44:48.420956 [CA 4] Center 34 (4~65) winsize 62
4404 11:44:48.421606 [CA 5] Center 33 (3~64) winsize 62
4405 11:44:48.422252
4406 11:44:48.422886 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4407 11:44:48.423442
4408 11:44:48.423956 [CATrainingPosCal] consider 2 rank data
4409 11:44:48.424494 u2DelayCellTimex100 = 270/100 ps
4410 11:44:48.424876 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4411 11:44:48.425232 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 11:44:48.425577 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4413 11:44:48.425934 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 11:44:48.426273 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 11:44:48.426596 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 11:44:48.426879
4417 11:44:48.427222 CA PerBit enable=1, Macro0, CA PI delay=33
4418 11:44:48.427553
4419 11:44:48.427795 [CBTSetCACLKResult] CA Dly = 33
4420 11:44:48.428138 CS Dly: 4 (0~36)
4421 11:44:48.428472
4422 11:44:48.428824 ----->DramcWriteLeveling(PI) begin...
4423 11:44:48.429169 ==
4424 11:44:48.429514 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 11:44:48.429831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 11:44:48.430094 ==
4427 11:44:48.430348 Write leveling (Byte 0): 27 => 27
4428 11:44:48.430550 Write leveling (Byte 1): 31 => 31
4429 11:44:48.430810 DramcWriteLeveling(PI) end<-----
4430 11:44:48.431085
4431 11:44:48.431341 ==
4432 11:44:48.431535 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 11:44:48.431710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 11:44:48.431964 ==
4435 11:44:48.432213 [Gating] SW mode calibration
4436 11:44:48.432461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4437 11:44:48.432719 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4438 11:44:48.432971 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 11:44:48.433227 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 11:44:48.433536 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 11:44:48.433832 0 9 12 | B1->B0 | 3333 3131 | 1 0 | (0 1) (0 0)
4442 11:44:48.434096 0 9 16 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (1 1)
4443 11:44:48.434404 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 11:44:48.434703 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 11:44:48.434940 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 11:44:48.435163 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 11:44:48.439506 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 11:44:48.442569 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 11:44:48.445552 0 10 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
4450 11:44:48.452483 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
4451 11:44:48.455478 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 11:44:48.459061 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 11:44:48.465676 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 11:44:48.468833 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 11:44:48.472539 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 11:44:48.479086 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 11:44:48.481923 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 11:44:48.485643 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 11:44:48.492416 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 11:44:48.495418 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 11:44:48.499048 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 11:44:48.505782 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 11:44:48.508737 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 11:44:48.512443 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 11:44:48.519148 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 11:44:48.522058 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 11:44:48.525426 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 11:44:48.532046 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 11:44:48.535503 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 11:44:48.538940 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 11:44:48.545727 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 11:44:48.548817 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 11:44:48.552466 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 11:44:48.555538 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 11:44:48.558737 Total UI for P1: 0, mck2ui 16
4476 11:44:48.562445 best dqsien dly found for B0: ( 0, 13, 14)
4477 11:44:48.565521 Total UI for P1: 0, mck2ui 16
4478 11:44:48.569095 best dqsien dly found for B1: ( 0, 13, 14)
4479 11:44:48.572057 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4480 11:44:48.578700 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4481 11:44:48.579192
4482 11:44:48.581756 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4483 11:44:48.585300 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4484 11:44:48.588408 [Gating] SW calibration Done
4485 11:44:48.588839 ==
4486 11:44:48.592020 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 11:44:48.595159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 11:44:48.595497 ==
4489 11:44:48.598174 RX Vref Scan: 0
4490 11:44:48.598531
4491 11:44:48.598783 RX Vref 0 -> 0, step: 1
4492 11:44:48.599020
4493 11:44:48.601907 RX Delay -230 -> 252, step: 16
4494 11:44:48.604853 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4495 11:44:48.611836 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4496 11:44:48.615346 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4497 11:44:48.618252 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4498 11:44:48.621855 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4499 11:44:48.628416 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4500 11:44:48.631816 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4501 11:44:48.634979 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4502 11:44:48.637979 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4503 11:44:48.641505 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4504 11:44:48.648270 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4505 11:44:48.651308 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4506 11:44:48.654839 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4507 11:44:48.657962 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4508 11:44:48.664691 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4509 11:44:48.668333 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4510 11:44:48.668879 ==
4511 11:44:48.671399 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 11:44:48.674527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 11:44:48.674877 ==
4514 11:44:48.677831 DQS Delay:
4515 11:44:48.678158 DQS0 = 0, DQS1 = 0
4516 11:44:48.678490 DQM Delay:
4517 11:44:48.681417 DQM0 = 44, DQM1 = 35
4518 11:44:48.681661 DQ Delay:
4519 11:44:48.684521 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4520 11:44:48.729856 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4521 11:44:48.730246 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4522 11:44:48.730530 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4523 11:44:48.730962
4524 11:44:48.731236
4525 11:44:48.731520 ==
4526 11:44:48.731757 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 11:44:48.731940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 11:44:48.732116 ==
4529 11:44:48.732311
4530 11:44:48.732483
4531 11:44:48.732653 TX Vref Scan disable
4532 11:44:48.732823 == TX Byte 0 ==
4533 11:44:48.732991 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4534 11:44:48.733160 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4535 11:44:48.733327 == TX Byte 1 ==
4536 11:44:48.733494 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4537 11:44:48.733661 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4538 11:44:48.733827 ==
4539 11:44:48.734245 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 11:44:48.735099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 11:44:48.735322 ==
4542 11:44:48.735550
4543 11:44:48.735748
4544 11:44:48.738053 TX Vref Scan disable
4545 11:44:48.741439 == TX Byte 0 ==
4546 11:44:48.744928 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4547 11:44:48.747892 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4548 11:44:48.751696 == TX Byte 1 ==
4549 11:44:48.754760 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4550 11:44:48.758133 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4551 11:44:48.758384
4552 11:44:48.758602 [DATLAT]
4553 11:44:48.761340 Freq=600, CH1 RK0
4554 11:44:48.761504
4555 11:44:48.765417 DATLAT Default: 0x9
4556 11:44:48.765565 0, 0xFFFF, sum = 0
4557 11:44:48.768087 1, 0xFFFF, sum = 0
4558 11:44:48.768235 2, 0xFFFF, sum = 0
4559 11:44:48.771177 3, 0xFFFF, sum = 0
4560 11:44:48.771299 4, 0xFFFF, sum = 0
4561 11:44:48.774762 5, 0xFFFF, sum = 0
4562 11:44:48.774872 6, 0xFFFF, sum = 0
4563 11:44:48.777978 7, 0xFFFF, sum = 0
4564 11:44:48.778087 8, 0x0, sum = 1
4565 11:44:48.781655 9, 0x0, sum = 2
4566 11:44:48.781753 10, 0x0, sum = 3
4567 11:44:48.781829 11, 0x0, sum = 4
4568 11:44:48.784678 best_step = 9
4569 11:44:48.784764
4570 11:44:48.784832 ==
4571 11:44:48.788221 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 11:44:48.791194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 11:44:48.791307 ==
4574 11:44:48.794881 RX Vref Scan: 1
4575 11:44:48.794993
4576 11:44:48.795090 RX Vref 0 -> 0, step: 1
4577 11:44:48.797958
4578 11:44:48.798044 RX Delay -195 -> 252, step: 8
4579 11:44:48.798111
4580 11:44:48.801574 Set Vref, RX VrefLevel [Byte0]: 59
4581 11:44:48.804724 [Byte1]: 54
4582 11:44:48.808995
4583 11:44:48.809080 Final RX Vref Byte 0 = 59 to rank0
4584 11:44:48.811905 Final RX Vref Byte 1 = 54 to rank0
4585 11:44:48.815500 Final RX Vref Byte 0 = 59 to rank1
4586 11:44:48.818485 Final RX Vref Byte 1 = 54 to rank1==
4587 11:44:48.822044 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 11:44:48.828463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 11:44:48.828618 ==
4590 11:44:48.828752 DQS Delay:
4591 11:44:48.832322 DQS0 = 0, DQS1 = 0
4592 11:44:48.832820 DQM Delay:
4593 11:44:48.833270 DQM0 = 40, DQM1 = 33
4594 11:44:48.835647 DQ Delay:
4595 11:44:48.838748 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4596 11:44:48.842282 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4597 11:44:48.845746 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4598 11:44:48.848584 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4599 11:44:48.849008
4600 11:44:48.849343
4601 11:44:48.855779 [DQSOSCAuto] RK0, (LSB)MR18= 0x4107, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4602 11:44:48.859031 CH1 RK0: MR19=808, MR18=4107
4603 11:44:48.865368 CH1_RK0: MR19=0x808, MR18=0x4107, DQSOSC=397, MR23=63, INC=166, DEC=110
4604 11:44:48.865794
4605 11:44:48.868941 ----->DramcWriteLeveling(PI) begin...
4606 11:44:48.869370 ==
4607 11:44:48.872024 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 11:44:48.875773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 11:44:48.876198 ==
4610 11:44:48.878770 Write leveling (Byte 0): 31 => 31
4611 11:44:48.882123 Write leveling (Byte 1): 31 => 31
4612 11:44:48.885271 DramcWriteLeveling(PI) end<-----
4613 11:44:48.886005
4614 11:44:48.886677 ==
4615 11:44:48.888785 Dram Type= 6, Freq= 0, CH_1, rank 1
4616 11:44:48.891918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 11:44:48.892405 ==
4618 11:44:48.895589 [Gating] SW mode calibration
4619 11:44:48.902117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4620 11:44:48.908282 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4621 11:44:48.911726 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 11:44:48.918217 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 11:44:48.921734 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
4624 11:44:48.925054 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4625 11:44:48.931670 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4626 11:44:48.934699 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 11:44:48.938060 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 11:44:48.941688 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 11:44:48.948207 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 11:44:48.951626 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 11:44:48.955142 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4632 11:44:48.961352 0 10 12 | B1->B0 | 2f2f 3939 | 0 1 | (1 1) (0 0)
4633 11:44:48.965170 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4634 11:44:48.968015 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 11:44:49.070313 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 11:44:49.071506 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 11:44:49.072185 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 11:44:49.072807 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 11:44:49.073394 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4640 11:44:49.073904 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4641 11:44:49.074364 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 11:44:49.074723 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 11:44:49.075139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 11:44:49.075474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 11:44:49.075875 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 11:44:49.076222 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 11:44:49.076734 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 11:44:49.077044 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 11:44:49.077382 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 11:44:49.077676 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 11:44:49.078077 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 11:44:49.078544 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 11:44:49.078911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 11:44:49.079206 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 11:44:49.079554 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 11:44:49.079850 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4657 11:44:49.080133 Total UI for P1: 0, mck2ui 16
4658 11:44:49.080498 best dqsien dly found for B0: ( 0, 13, 10)
4659 11:44:49.080836 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 11:44:49.081239 Total UI for P1: 0, mck2ui 16
4661 11:44:49.084271 best dqsien dly found for B1: ( 0, 13, 12)
4662 11:44:49.087395 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4663 11:44:49.090963 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4664 11:44:49.091608
4665 11:44:49.094544 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4666 11:44:49.097617 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4667 11:44:49.100726 [Gating] SW calibration Done
4668 11:44:49.101399 ==
4669 11:44:49.104561 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 11:44:49.107332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 11:44:49.110959 ==
4672 11:44:49.111677 RX Vref Scan: 0
4673 11:44:49.112284
4674 11:44:49.113914 RX Vref 0 -> 0, step: 1
4675 11:44:49.114435
4676 11:44:49.121039 RX Delay -230 -> 252, step: 16
4677 11:44:49.121371 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4678 11:44:49.124294 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4679 11:44:49.127258 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4680 11:44:49.134175 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4681 11:44:49.137436 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4682 11:44:49.140524 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4683 11:44:49.143879 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4684 11:44:49.147291 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4685 11:44:49.153937 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4686 11:44:49.157386 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4687 11:44:49.160821 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4688 11:44:49.163833 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4689 11:44:49.170395 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4690 11:44:49.174124 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4691 11:44:49.177214 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4692 11:44:49.180552 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4693 11:44:49.180928 ==
4694 11:44:49.183820 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 11:44:49.190408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 11:44:49.190894 ==
4697 11:44:49.191230 DQS Delay:
4698 11:44:49.193647 DQS0 = 0, DQS1 = 0
4699 11:44:49.194040 DQM Delay:
4700 11:44:49.194344 DQM0 = 40, DQM1 = 37
4701 11:44:49.197325 DQ Delay:
4702 11:44:49.200118 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4703 11:44:49.203783 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4704 11:44:49.206828 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4705 11:44:49.210577 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4706 11:44:49.210993
4707 11:44:49.211395
4708 11:44:49.211655 ==
4709 11:44:49.213643 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 11:44:49.216577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 11:44:49.216993 ==
4712 11:44:49.217371
4713 11:44:49.217738
4714 11:44:49.220320 TX Vref Scan disable
4715 11:44:49.220645 == TX Byte 0 ==
4716 11:44:49.227037 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4717 11:44:49.230236 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4718 11:44:49.233405 == TX Byte 1 ==
4719 11:44:49.236962 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4720 11:44:49.239834 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4721 11:44:49.239989 ==
4722 11:44:49.243389 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 11:44:49.246308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 11:44:49.246473 ==
4725 11:44:49.249905
4726 11:44:49.250090
4727 11:44:49.250242 TX Vref Scan disable
4728 11:44:49.260913 == TX Byte 0 ==
4729 11:44:49.261255 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4730 11:44:49.263366 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4731 11:44:49.263492 == TX Byte 1 ==
4732 11:44:49.266901 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4733 11:44:49.273553 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4734 11:44:49.273779
4735 11:44:49.273964 [DATLAT]
4736 11:44:49.274133 Freq=600, CH1 RK1
4737 11:44:49.274297
4738 11:44:49.276660 DATLAT Default: 0x9
4739 11:44:49.276847 0, 0xFFFF, sum = 0
4740 11:44:49.280172 1, 0xFFFF, sum = 0
4741 11:44:49.280334 2, 0xFFFF, sum = 0
4742 11:44:49.283689 3, 0xFFFF, sum = 0
4743 11:44:49.286705 4, 0xFFFF, sum = 0
4744 11:44:49.286867 5, 0xFFFF, sum = 0
4745 11:44:49.293222 6, 0xFFFF, sum = 0
4746 11:44:49.293470 7, 0xFFFF, sum = 0
4747 11:44:49.293616 8, 0x0, sum = 1
4748 11:44:49.293966 9, 0x0, sum = 2
4749 11:44:49.294107 10, 0x0, sum = 3
4750 11:44:49.296786 11, 0x0, sum = 4
4751 11:44:49.297010 best_step = 9
4752 11:44:49.297269
4753 11:44:49.297432 ==
4754 11:44:49.300482 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 11:44:49.306967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 11:44:49.307308 ==
4757 11:44:49.307592 RX Vref Scan: 0
4758 11:44:49.307825
4759 11:44:49.309999 RX Vref 0 -> 0, step: 1
4760 11:44:49.310308
4761 11:44:49.313577 RX Delay -179 -> 252, step: 8
4762 11:44:49.316515 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4763 11:44:49.323662 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4764 11:44:49.326365 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4765 11:44:49.329913 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4766 11:44:49.332959 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4767 11:44:49.339627 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4768 11:44:49.343287 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4769 11:44:49.346087 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4770 11:44:49.349631 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4771 11:44:49.352587 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4772 11:44:49.359638 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4773 11:44:49.363137 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4774 11:44:49.366493 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4775 11:44:49.370011 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4776 11:44:49.376681 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4777 11:44:49.379760 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4778 11:44:49.380195 ==
4779 11:44:49.382766 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 11:44:49.386343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 11:44:49.386810 ==
4782 11:44:49.389872 DQS Delay:
4783 11:44:49.390462 DQS0 = 0, DQS1 = 0
4784 11:44:49.392895 DQM Delay:
4785 11:44:49.393485 DQM0 = 39, DQM1 = 32
4786 11:44:49.393980 DQ Delay:
4787 11:44:49.395989 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4788 11:44:49.399690 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4789 11:44:49.402563 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4790 11:44:49.406386 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4791 11:44:49.406616
4792 11:44:49.406821
4793 11:44:49.416132 [DQSOSCAuto] RK1, (LSB)MR18= 0x3947, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4794 11:44:49.419015 CH1 RK1: MR19=808, MR18=3947
4795 11:44:49.422594 CH1_RK1: MR19=0x808, MR18=0x3947, DQSOSC=396, MR23=63, INC=167, DEC=111
4796 11:44:49.425598 [RxdqsGatingPostProcess] freq 600
4797 11:44:49.433037 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4798 11:44:49.435973 Pre-setting of DQS Precalculation
4799 11:44:49.439571 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4800 11:44:49.449288 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4801 11:44:49.456367 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4802 11:44:49.456800
4803 11:44:49.457136
4804 11:44:49.459439 [Calibration Summary] 1200 Mbps
4805 11:44:49.459867 CH 0, Rank 0
4806 11:44:49.462434 SW Impedance : PASS
4807 11:44:49.462864 DUTY Scan : NO K
4808 11:44:49.465855 ZQ Calibration : PASS
4809 11:44:49.469388 Jitter Meter : NO K
4810 11:44:49.469816 CBT Training : PASS
4811 11:44:49.473054 Write leveling : PASS
4812 11:44:49.475800 RX DQS gating : PASS
4813 11:44:49.476228 RX DQ/DQS(RDDQC) : PASS
4814 11:44:49.479630 TX DQ/DQS : PASS
4815 11:44:49.482655 RX DATLAT : PASS
4816 11:44:49.483314 RX DQ/DQS(Engine): PASS
4817 11:44:49.486035 TX OE : NO K
4818 11:44:49.486550 All Pass.
4819 11:44:49.487013
4820 11:44:49.489154 CH 0, Rank 1
4821 11:44:49.489730 SW Impedance : PASS
4822 11:44:49.492505 DUTY Scan : NO K
4823 11:44:49.493100 ZQ Calibration : PASS
4824 11:44:49.495565 Jitter Meter : NO K
4825 11:44:49.499056 CBT Training : PASS
4826 11:44:49.499478 Write leveling : PASS
4827 11:44:49.502156 RX DQS gating : PASS
4828 11:44:49.505968 RX DQ/DQS(RDDQC) : PASS
4829 11:44:49.506405 TX DQ/DQS : PASS
4830 11:44:49.508967 RX DATLAT : PASS
4831 11:44:49.512714 RX DQ/DQS(Engine): PASS
4832 11:44:49.513141 TX OE : NO K
4833 11:44:49.515712 All Pass.
4834 11:44:49.516188
4835 11:44:49.516571 CH 1, Rank 0
4836 11:44:49.519187 SW Impedance : PASS
4837 11:44:49.519645 DUTY Scan : NO K
4838 11:44:49.522264 ZQ Calibration : PASS
4839 11:44:49.525709 Jitter Meter : NO K
4840 11:44:49.526091 CBT Training : PASS
4841 11:44:49.529162 Write leveling : PASS
4842 11:44:49.532376 RX DQS gating : PASS
4843 11:44:49.532807 RX DQ/DQS(RDDQC) : PASS
4844 11:44:49.536074 TX DQ/DQS : PASS
4845 11:44:49.536501 RX DATLAT : PASS
4846 11:44:49.539065 RX DQ/DQS(Engine): PASS
4847 11:44:49.542261 TX OE : NO K
4848 11:44:49.542872 All Pass.
4849 11:44:49.543416
4850 11:44:49.543755 CH 1, Rank 1
4851 11:44:49.545790 SW Impedance : PASS
4852 11:44:49.548917 DUTY Scan : NO K
4853 11:44:49.549485 ZQ Calibration : PASS
4854 11:44:49.552674 Jitter Meter : NO K
4855 11:44:49.555460 CBT Training : PASS
4856 11:44:49.555888 Write leveling : PASS
4857 11:44:49.559039 RX DQS gating : PASS
4858 11:44:49.562000 RX DQ/DQS(RDDQC) : PASS
4859 11:44:49.562398 TX DQ/DQS : PASS
4860 11:44:49.565598 RX DATLAT : PASS
4861 11:44:49.569238 RX DQ/DQS(Engine): PASS
4862 11:44:49.569737 TX OE : NO K
4863 11:44:49.572085 All Pass.
4864 11:44:49.572519
4865 11:44:49.572889 DramC Write-DBI off
4866 11:44:49.575387 PER_BANK_REFRESH: Hybrid Mode
4867 11:44:49.575854 TX_TRACKING: ON
4868 11:44:49.585640 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4869 11:44:49.588688 [FAST_K] Save calibration result to emmc
4870 11:44:49.591747 dramc_set_vcore_voltage set vcore to 662500
4871 11:44:49.595328 Read voltage for 933, 3
4872 11:44:49.595775 Vio18 = 0
4873 11:44:49.598895 Vcore = 662500
4874 11:44:49.599486 Vdram = 0
4875 11:44:49.599844 Vddq = 0
4876 11:44:49.602211 Vmddr = 0
4877 11:44:49.605151 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4878 11:44:49.611804 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4879 11:44:49.612234 MEM_TYPE=3, freq_sel=17
4880 11:44:49.615299 sv_algorithm_assistance_LP4_1600
4881 11:44:49.618361 ============ PULL DRAM RESETB DOWN ============
4882 11:44:49.625149 ========== PULL DRAM RESETB DOWN end =========
4883 11:44:49.628776 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4884 11:44:49.631717 ===================================
4885 11:44:49.635224 LPDDR4 DRAM CONFIGURATION
4886 11:44:49.638443 ===================================
4887 11:44:49.638931 EX_ROW_EN[0] = 0x0
4888 11:44:49.641952 EX_ROW_EN[1] = 0x0
4889 11:44:49.644892 LP4Y_EN = 0x0
4890 11:44:49.645448 WORK_FSP = 0x0
4891 11:44:49.648486 WL = 0x3
4892 11:44:49.648883 RL = 0x3
4893 11:44:49.651375 BL = 0x2
4894 11:44:49.651579 RPST = 0x0
4895 11:44:49.654563 RD_PRE = 0x0
4896 11:44:49.654807 WR_PRE = 0x1
4897 11:44:49.658139 WR_PST = 0x0
4898 11:44:49.658359 DBI_WR = 0x0
4899 11:44:49.661173 DBI_RD = 0x0
4900 11:44:49.661378 OTF = 0x1
4901 11:44:49.664760 ===================================
4902 11:44:49.668269 ===================================
4903 11:44:49.671287 ANA top config
4904 11:44:49.675133 ===================================
4905 11:44:49.675614 DLL_ASYNC_EN = 0
4906 11:44:49.678094 ALL_SLAVE_EN = 1
4907 11:44:49.681574 NEW_RANK_MODE = 1
4908 11:44:49.685031 DLL_IDLE_MODE = 1
4909 11:44:49.687950 LP45_APHY_COMB_EN = 1
4910 11:44:49.688383 TX_ODT_DIS = 1
4911 11:44:49.691474 NEW_8X_MODE = 1
4912 11:44:49.694533 ===================================
4913 11:44:49.698212 ===================================
4914 11:44:49.701840 data_rate = 1866
4915 11:44:49.704729 CKR = 1
4916 11:44:49.708283 DQ_P2S_RATIO = 8
4917 11:44:49.711319 ===================================
4918 11:44:49.711812 CA_P2S_RATIO = 8
4919 11:44:49.715008 DQ_CA_OPEN = 0
4920 11:44:49.718050 DQ_SEMI_OPEN = 0
4921 11:44:49.721715 CA_SEMI_OPEN = 0
4922 11:44:49.724700 CA_FULL_RATE = 0
4923 11:44:49.728468 DQ_CKDIV4_EN = 1
4924 11:44:49.728900 CA_CKDIV4_EN = 1
4925 11:44:49.731409 CA_PREDIV_EN = 0
4926 11:44:49.735018 PH8_DLY = 0
4927 11:44:49.738478 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4928 11:44:49.741403 DQ_AAMCK_DIV = 4
4929 11:44:49.744880 CA_AAMCK_DIV = 4
4930 11:44:49.745316 CA_ADMCK_DIV = 4
4931 11:44:49.747889 DQ_TRACK_CA_EN = 0
4932 11:44:49.751442 CA_PICK = 933
4933 11:44:49.754524 CA_MCKIO = 933
4934 11:44:49.758037 MCKIO_SEMI = 0
4935 11:44:49.761073 PLL_FREQ = 3732
4936 11:44:49.764604 DQ_UI_PI_RATIO = 32
4937 11:44:49.764758 CA_UI_PI_RATIO = 0
4938 11:44:49.767972 ===================================
4939 11:44:49.771187 ===================================
4940 11:44:49.774720 memory_type:LPDDR4
4941 11:44:49.778082 GP_NUM : 10
4942 11:44:49.778237 SRAM_EN : 1
4943 11:44:49.781165 MD32_EN : 0
4944 11:44:49.784599 ===================================
4945 11:44:49.787490 [ANA_INIT] >>>>>>>>>>>>>>
4946 11:44:49.791123 <<<<<< [CONFIGURE PHASE]: ANA_TX
4947 11:44:49.794720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4948 11:44:49.797770 ===================================
4949 11:44:49.797948 data_rate = 1866,PCW = 0X8f00
4950 11:44:49.800766 ===================================
4951 11:44:49.804669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4952 11:44:49.810962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 11:44:49.817826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 11:44:49.821221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4955 11:44:49.824639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4956 11:44:49.827699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4957 11:44:49.831238 [ANA_INIT] flow start
4958 11:44:49.831714 [ANA_INIT] PLL >>>>>>>>
4959 11:44:49.834238 [ANA_INIT] PLL <<<<<<<<
4960 11:44:49.838036 [ANA_INIT] MIDPI >>>>>>>>
4961 11:44:49.841102 [ANA_INIT] MIDPI <<<<<<<<
4962 11:44:49.841535 [ANA_INIT] DLL >>>>>>>>
4963 11:44:49.844558 [ANA_INIT] flow end
4964 11:44:49.847999 ============ LP4 DIFF to SE enter ============
4965 11:44:49.851112 ============ LP4 DIFF to SE exit ============
4966 11:44:49.854784 [ANA_INIT] <<<<<<<<<<<<<
4967 11:44:49.857674 [Flow] Enable top DCM control >>>>>
4968 11:44:49.861091 [Flow] Enable top DCM control <<<<<
4969 11:44:49.864192 Enable DLL master slave shuffle
4970 11:44:49.870977 ==============================================================
4971 11:44:49.871245 Gating Mode config
4972 11:44:49.877945 ==============================================================
4973 11:44:49.878175 Config description:
4974 11:44:49.887189 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4975 11:44:49.894266 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4976 11:44:49.901228 SELPH_MODE 0: By rank 1: By Phase
4977 11:44:49.904318 ==============================================================
4978 11:44:49.907186 GAT_TRACK_EN = 1
4979 11:44:49.910826 RX_GATING_MODE = 2
4980 11:44:49.914478 RX_GATING_TRACK_MODE = 2
4981 11:44:49.917672 SELPH_MODE = 1
4982 11:44:49.921115 PICG_EARLY_EN = 1
4983 11:44:49.923973 VALID_LAT_VALUE = 1
4984 11:44:49.927495 ==============================================================
4985 11:44:49.930846 Enter into Gating configuration >>>>
4986 11:44:49.934373 Exit from Gating configuration <<<<
4987 11:44:49.937204 Enter into DVFS_PRE_config >>>>>
4988 11:44:49.950554 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4989 11:44:49.954067 Exit from DVFS_PRE_config <<<<<
4990 11:44:49.957210 Enter into PICG configuration >>>>
4991 11:44:49.960851 Exit from PICG configuration <<<<
4992 11:44:49.961282 [RX_INPUT] configuration >>>>>
4993 11:44:49.963742 [RX_INPUT] configuration <<<<<
4994 11:44:49.970589 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4995 11:44:49.973420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4996 11:44:49.980575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4997 11:44:49.987180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4998 11:44:49.993409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 11:44:50.000493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 11:44:50.003659 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5001 11:44:50.006659 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5002 11:44:50.013394 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5003 11:44:50.016977 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5004 11:44:50.020480 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5005 11:44:50.023525 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 11:44:50.026567 ===================================
5007 11:44:50.030336 LPDDR4 DRAM CONFIGURATION
5008 11:44:50.033424 ===================================
5009 11:44:50.037046 EX_ROW_EN[0] = 0x0
5010 11:44:50.037482 EX_ROW_EN[1] = 0x0
5011 11:44:50.040011 LP4Y_EN = 0x0
5012 11:44:50.040444 WORK_FSP = 0x0
5013 11:44:50.043648 WL = 0x3
5014 11:44:50.044080 RL = 0x3
5015 11:44:50.046766 BL = 0x2
5016 11:44:50.047195 RPST = 0x0
5017 11:44:50.050411 RD_PRE = 0x0
5018 11:44:50.050847 WR_PRE = 0x1
5019 11:44:50.053362 WR_PST = 0x0
5020 11:44:50.053792 DBI_WR = 0x0
5021 11:44:50.057086 DBI_RD = 0x0
5022 11:44:50.060162 OTF = 0x1
5023 11:44:50.063514 ===================================
5024 11:44:50.066440 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5025 11:44:50.070099 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5026 11:44:50.073628 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 11:44:50.076681 ===================================
5028 11:44:50.080268 LPDDR4 DRAM CONFIGURATION
5029 11:44:50.083666 ===================================
5030 11:44:50.086650 EX_ROW_EN[0] = 0x10
5031 11:44:50.087212 EX_ROW_EN[1] = 0x0
5032 11:44:50.090210 LP4Y_EN = 0x0
5033 11:44:50.090760 WORK_FSP = 0x0
5034 11:44:50.093016 WL = 0x3
5035 11:44:50.093745 RL = 0x3
5036 11:44:50.096570 BL = 0x2
5037 11:44:50.097002 RPST = 0x0
5038 11:44:50.099950 RD_PRE = 0x0
5039 11:44:50.100515 WR_PRE = 0x1
5040 11:44:50.103393 WR_PST = 0x0
5041 11:44:50.103788 DBI_WR = 0x0
5042 11:44:50.106317 DBI_RD = 0x0
5043 11:44:50.106751 OTF = 0x1
5044 11:44:50.109995 ===================================
5045 11:44:50.116213 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5046 11:44:50.121554 nWR fixed to 30
5047 11:44:50.124279 [ModeRegInit_LP4] CH0 RK0
5048 11:44:50.124712 [ModeRegInit_LP4] CH0 RK1
5049 11:44:50.128005 [ModeRegInit_LP4] CH1 RK0
5050 11:44:50.131030 [ModeRegInit_LP4] CH1 RK1
5051 11:44:50.131483 match AC timing 9
5052 11:44:50.137712 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5053 11:44:50.141328 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5054 11:44:50.144206 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5055 11:44:50.151085 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5056 11:44:50.154181 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5057 11:44:50.154610 ==
5058 11:44:50.157661 Dram Type= 6, Freq= 0, CH_0, rank 0
5059 11:44:50.161066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 11:44:50.161565 ==
5061 11:44:50.167508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 11:44:50.173843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5063 11:44:50.177400 [CA 0] Center 38 (8~69) winsize 62
5064 11:44:50.181189 [CA 1] Center 38 (7~69) winsize 63
5065 11:44:50.184184 [CA 2] Center 35 (5~66) winsize 62
5066 11:44:50.187641 [CA 3] Center 35 (4~66) winsize 63
5067 11:44:50.190764 [CA 4] Center 34 (4~64) winsize 61
5068 11:44:50.194070 [CA 5] Center 34 (4~64) winsize 61
5069 11:44:50.194720
5070 11:44:50.197700 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5071 11:44:50.198130
5072 11:44:50.200672 [CATrainingPosCal] consider 1 rank data
5073 11:44:50.204079 u2DelayCellTimex100 = 270/100 ps
5074 11:44:50.207452 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5075 11:44:50.210944 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5076 11:44:50.213994 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5077 11:44:50.217639 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5078 11:44:50.220610 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5079 11:44:50.227342 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5080 11:44:50.228064
5081 11:44:50.230733 CA PerBit enable=1, Macro0, CA PI delay=34
5082 11:44:50.231276
5083 11:44:50.233864 [CBTSetCACLKResult] CA Dly = 34
5084 11:44:50.234296 CS Dly: 6 (0~37)
5085 11:44:50.234639 ==
5086 11:44:50.237919 Dram Type= 6, Freq= 0, CH_0, rank 1
5087 11:44:50.240822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 11:44:50.241258 ==
5089 11:44:50.247210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 11:44:50.253987 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5091 11:44:50.256959 [CA 0] Center 38 (7~69) winsize 63
5092 11:44:50.260659 [CA 1] Center 38 (7~69) winsize 63
5093 11:44:50.263879 [CA 2] Center 35 (5~66) winsize 62
5094 11:44:50.267392 [CA 3] Center 34 (4~65) winsize 62
5095 11:44:50.270846 [CA 4] Center 34 (4~64) winsize 61
5096 11:44:50.274183 [CA 5] Center 33 (3~64) winsize 62
5097 11:44:50.274724
5098 11:44:50.277318 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5099 11:44:50.277855
5100 11:44:50.280658 [CATrainingPosCal] consider 2 rank data
5101 11:44:50.283681 u2DelayCellTimex100 = 270/100 ps
5102 11:44:50.287252 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5103 11:44:50.290148 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5104 11:44:50.293981 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5105 11:44:50.297245 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5106 11:44:50.303573 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5107 11:44:50.307189 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5108 11:44:50.307826
5109 11:44:50.310490 CA PerBit enable=1, Macro0, CA PI delay=34
5110 11:44:50.310920
5111 11:44:50.313394 [CBTSetCACLKResult] CA Dly = 34
5112 11:44:50.313979 CS Dly: 7 (0~39)
5113 11:44:50.314487
5114 11:44:50.316983 ----->DramcWriteLeveling(PI) begin...
5115 11:44:50.317418 ==
5116 11:44:50.320034 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 11:44:50.327316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 11:44:50.328116 ==
5119 11:44:50.330229 Write leveling (Byte 0): 30 => 30
5120 11:44:50.330765 Write leveling (Byte 1): 28 => 28
5121 11:44:50.333894 DramcWriteLeveling(PI) end<-----
5122 11:44:50.334323
5123 11:44:50.336722 ==
5124 11:44:50.337153 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 11:44:50.343423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 11:44:50.343859 ==
5127 11:44:50.346566 [Gating] SW mode calibration
5128 11:44:50.353678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5129 11:44:50.357141 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5130 11:44:50.363737 0 14 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
5131 11:44:50.366710 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5132 11:44:50.369756 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 11:44:50.376834 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 11:44:50.380430 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 11:44:50.383442 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 11:44:50.390096 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 11:44:50.392994 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 11:44:50.396728 0 15 0 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 1)
5139 11:44:50.403100 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
5140 11:44:50.406750 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 11:44:50.410102 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 11:44:50.413399 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 11:44:50.419910 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 11:44:50.423012 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 11:44:50.426852 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 11:44:50.433753 1 0 0 | B1->B0 | 2e2e 4141 | 0 0 | (0 0) (0 0)
5147 11:44:50.436358 1 0 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5148 11:44:50.439979 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 11:44:50.446731 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 11:44:50.449925 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 11:44:50.452907 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 11:44:50.459447 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 11:44:50.463225 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 11:44:50.466592 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5155 11:44:50.473575 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 11:44:50.476656 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 11:44:50.479773 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 11:44:50.486894 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 11:44:50.489525 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 11:44:50.493157 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 11:44:50.499711 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 11:44:50.503412 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 11:44:50.506049 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 11:44:50.512881 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 11:44:50.515893 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 11:44:50.519443 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 11:44:50.525778 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 11:44:50.529420 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 11:44:50.532636 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 11:44:50.539212 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5171 11:44:50.542718 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 11:44:50.546243 Total UI for P1: 0, mck2ui 16
5173 11:44:50.549284 best dqsien dly found for B0: ( 1, 3, 0)
5174 11:44:50.552392 Total UI for P1: 0, mck2ui 16
5175 11:44:50.555957 best dqsien dly found for B1: ( 1, 3, 0)
5176 11:44:50.559651 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5177 11:44:50.562456 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5178 11:44:50.562888
5179 11:44:50.565921 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5180 11:44:50.568982 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5181 11:44:50.572765 [Gating] SW calibration Done
5182 11:44:50.573197 ==
5183 11:44:50.575763 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 11:44:50.579273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 11:44:50.579737 ==
5186 11:44:50.582330 RX Vref Scan: 0
5187 11:44:50.582758
5188 11:44:50.585281 RX Vref 0 -> 0, step: 1
5189 11:44:50.585714
5190 11:44:50.586055 RX Delay -80 -> 252, step: 8
5191 11:44:50.592408 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5192 11:44:50.595554 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5193 11:44:50.598627 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5194 11:44:50.602100 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5195 11:44:50.605597 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5196 11:44:50.608582 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5197 11:44:50.615373 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5198 11:44:50.619001 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5199 11:44:50.621966 iDelay=208, Bit 8, Center 79 (-8 ~ 167) 176
5200 11:44:50.625237 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5201 11:44:50.628611 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5202 11:44:50.635523 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5203 11:44:50.638396 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5204 11:44:50.641890 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5205 11:44:50.644778 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5206 11:44:50.648284 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5207 11:44:50.648885 ==
5208 11:44:50.651995 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 11:44:50.658261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 11:44:50.658699 ==
5211 11:44:50.659040 DQS Delay:
5212 11:44:50.661797 DQS0 = 0, DQS1 = 0
5213 11:44:50.662225 DQM Delay:
5214 11:44:50.662572 DQM0 = 99, DQM1 = 87
5215 11:44:50.664718 DQ Delay:
5216 11:44:50.668261 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5217 11:44:50.671550 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5218 11:44:50.674801 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5219 11:44:50.678362 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5220 11:44:50.678795
5221 11:44:50.679134
5222 11:44:50.679505 ==
5223 11:44:50.681356 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 11:44:50.685100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 11:44:50.685578 ==
5226 11:44:50.685929
5227 11:44:50.686245
5228 11:44:50.687971 TX Vref Scan disable
5229 11:44:50.691288 == TX Byte 0 ==
5230 11:44:50.695075 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5231 11:44:50.698070 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5232 11:44:50.701743 == TX Byte 1 ==
5233 11:44:50.704870 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5234 11:44:50.707933 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5235 11:44:50.708367 ==
5236 11:44:50.711438 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 11:44:50.714608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 11:44:50.718093 ==
5239 11:44:50.718652
5240 11:44:50.719159
5241 11:44:50.719605 TX Vref Scan disable
5242 11:44:50.721653 == TX Byte 0 ==
5243 11:44:50.724670 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5244 11:44:50.731569 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5245 11:44:50.732011 == TX Byte 1 ==
5246 11:44:50.734964 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5247 11:44:50.741135 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5248 11:44:50.741566
5249 11:44:50.741905 [DATLAT]
5250 11:44:50.742226 Freq=933, CH0 RK0
5251 11:44:50.742537
5252 11:44:50.744928 DATLAT Default: 0xd
5253 11:44:50.745360 0, 0xFFFF, sum = 0
5254 11:44:50.748026 1, 0xFFFF, sum = 0
5255 11:44:50.748463 2, 0xFFFF, sum = 0
5256 11:44:50.751301 3, 0xFFFF, sum = 0
5257 11:44:50.754950 4, 0xFFFF, sum = 0
5258 11:44:50.755420 5, 0xFFFF, sum = 0
5259 11:44:50.757936 6, 0xFFFF, sum = 0
5260 11:44:50.758373 7, 0xFFFF, sum = 0
5261 11:44:50.761452 8, 0xFFFF, sum = 0
5262 11:44:50.761895 9, 0xFFFF, sum = 0
5263 11:44:50.764734 10, 0x0, sum = 1
5264 11:44:50.765457 11, 0x0, sum = 2
5265 11:44:50.765960 12, 0x0, sum = 3
5266 11:44:50.767781 13, 0x0, sum = 4
5267 11:44:50.768217 best_step = 11
5268 11:44:50.768557
5269 11:44:50.771331 ==
5270 11:44:50.774949 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 11:44:50.777784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 11:44:50.778285 ==
5273 11:44:50.778631 RX Vref Scan: 1
5274 11:44:50.778955
5275 11:44:50.781204 RX Vref 0 -> 0, step: 1
5276 11:44:50.781638
5277 11:44:50.784789 RX Delay -61 -> 252, step: 4
5278 11:44:50.785463
5279 11:44:50.787746 Set Vref, RX VrefLevel [Byte0]: 51
5280 11:44:50.791477 [Byte1]: 51
5281 11:44:50.791912
5282 11:44:50.794376 Final RX Vref Byte 0 = 51 to rank0
5283 11:44:50.797966 Final RX Vref Byte 1 = 51 to rank0
5284 11:44:50.801065 Final RX Vref Byte 0 = 51 to rank1
5285 11:44:50.804307 Final RX Vref Byte 1 = 51 to rank1==
5286 11:44:50.807866 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 11:44:50.810932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 11:44:50.814375 ==
5289 11:44:50.814805 DQS Delay:
5290 11:44:50.815146 DQS0 = 0, DQS1 = 0
5291 11:44:50.817888 DQM Delay:
5292 11:44:50.818482 DQM0 = 97, DQM1 = 89
5293 11:44:50.820839 DQ Delay:
5294 11:44:50.821260 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =96
5295 11:44:50.824261 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5296 11:44:50.827989 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
5297 11:44:50.830856 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =98
5298 11:44:50.834320
5299 11:44:50.834737
5300 11:44:50.841210 [DQSOSCAuto] RK0, (LSB)MR18= 0x15ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5301 11:44:50.844312 CH0 RK0: MR19=504, MR18=15FF
5302 11:44:50.850837 CH0_RK0: MR19=0x504, MR18=0x15FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5303 11:44:50.851139
5304 11:44:50.854394 ----->DramcWriteLeveling(PI) begin...
5305 11:44:50.854671 ==
5306 11:44:50.857788 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 11:44:50.860857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 11:44:50.861042 ==
5309 11:44:50.863894 Write leveling (Byte 0): 33 => 33
5310 11:44:50.867492 Write leveling (Byte 1): 30 => 30
5311 11:44:50.870457 DramcWriteLeveling(PI) end<-----
5312 11:44:50.870588
5313 11:44:50.870690 ==
5314 11:44:50.874102 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 11:44:50.877185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 11:44:50.877301 ==
5317 11:44:50.880876 [Gating] SW mode calibration
5318 11:44:50.887096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5319 11:44:50.893906 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5320 11:44:50.897668 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
5321 11:44:50.901001 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 11:44:50.907697 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 11:44:50.910781 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 11:44:50.913882 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 11:44:50.921359 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 11:44:50.923873 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 11:44:50.927254 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 1)
5328 11:44:50.933843 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
5329 11:44:50.937242 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 11:44:50.940711 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 11:44:50.947450 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 11:44:50.950433 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 11:44:50.953538 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 11:44:50.960209 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 11:44:50.963664 0 15 28 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
5336 11:44:50.967294 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5337 11:44:50.973949 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 11:44:50.976904 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 11:44:50.980633 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 11:44:50.987147 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 11:44:50.989814 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 11:44:50.993493 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5343 11:44:51.007868 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5344 11:44:51.008632 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5345 11:44:51.008989 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 11:44:51.013625 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 11:44:51.016692 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 11:44:51.019735 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 11:44:51.026949 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 11:44:51.030129 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 11:44:51.033030 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 11:44:51.040162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 11:44:51.042929 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 11:44:51.046384 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 11:44:51.050036 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 11:44:51.056606 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 11:44:51.060270 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 11:44:51.063334 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5359 11:44:51.069659 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 11:44:51.073362 Total UI for P1: 0, mck2ui 16
5361 11:44:51.076729 best dqsien dly found for B0: ( 1, 2, 24)
5362 11:44:51.080128 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5363 11:44:51.083008 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 11:44:51.086712 Total UI for P1: 0, mck2ui 16
5365 11:44:51.089784 best dqsien dly found for B1: ( 1, 2, 30)
5366 11:44:51.093235 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5367 11:44:51.096184 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5368 11:44:51.099877
5369 11:44:51.102659 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5370 11:44:51.106237 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5371 11:44:51.109695 [Gating] SW calibration Done
5372 11:44:51.110292 ==
5373 11:44:51.112923 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 11:44:51.116559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 11:44:51.117038 ==
5376 11:44:51.117415 RX Vref Scan: 0
5377 11:44:51.117790
5378 11:44:51.119555 RX Vref 0 -> 0, step: 1
5379 11:44:51.120071
5380 11:44:51.122730 RX Delay -80 -> 252, step: 8
5381 11:44:51.126328 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5382 11:44:51.129775 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5383 11:44:51.132968 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5384 11:44:51.139720 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5385 11:44:51.142670 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5386 11:44:51.146251 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5387 11:44:51.149836 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5388 11:44:51.153178 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5389 11:44:51.156178 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5390 11:44:51.162768 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5391 11:44:51.165934 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5392 11:44:51.169753 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5393 11:44:51.172932 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5394 11:44:51.176371 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5395 11:44:51.179808 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5396 11:44:51.186017 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5397 11:44:51.186673 ==
5398 11:44:51.189744 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 11:44:51.192789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 11:44:51.193542 ==
5401 11:44:51.194366 DQS Delay:
5402 11:44:51.196237 DQS0 = 0, DQS1 = 0
5403 11:44:51.196851 DQM Delay:
5404 11:44:51.199118 DQM0 = 97, DQM1 = 88
5405 11:44:51.199812 DQ Delay:
5406 11:44:51.202799 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5407 11:44:51.205886 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5408 11:44:51.209008 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5409 11:44:51.212550 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5410 11:44:51.213219
5411 11:44:51.213777
5412 11:44:51.214255 ==
5413 11:44:51.215990 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 11:44:51.218842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 11:44:51.222689 ==
5416 11:44:51.223238
5417 11:44:51.223791
5418 11:44:51.224286 TX Vref Scan disable
5419 11:44:51.225770 == TX Byte 0 ==
5420 11:44:51.229433 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5421 11:44:51.232282 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5422 11:44:51.236055 == TX Byte 1 ==
5423 11:44:51.238786 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5424 11:44:51.242278 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5425 11:44:51.245843 ==
5426 11:44:51.248712 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 11:44:51.252320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 11:44:51.253074 ==
5429 11:44:51.253762
5430 11:44:51.254436
5431 11:44:51.255630 TX Vref Scan disable
5432 11:44:51.256096 == TX Byte 0 ==
5433 11:44:51.262192 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5434 11:44:51.265207 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5435 11:44:51.265728 == TX Byte 1 ==
5436 11:44:51.271894 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5437 11:44:51.275577 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5438 11:44:51.275983
5439 11:44:51.276321 [DATLAT]
5440 11:44:51.278532 Freq=933, CH0 RK1
5441 11:44:51.278970
5442 11:44:51.279481 DATLAT Default: 0xb
5443 11:44:51.282128 0, 0xFFFF, sum = 0
5444 11:44:51.282681 1, 0xFFFF, sum = 0
5445 11:44:51.285827 2, 0xFFFF, sum = 0
5446 11:44:51.286409 3, 0xFFFF, sum = 0
5447 11:44:51.288849 4, 0xFFFF, sum = 0
5448 11:44:51.289295 5, 0xFFFF, sum = 0
5449 11:44:51.291764 6, 0xFFFF, sum = 0
5450 11:44:51.292197 7, 0xFFFF, sum = 0
5451 11:44:51.295452 8, 0xFFFF, sum = 0
5452 11:44:51.298776 9, 0xFFFF, sum = 0
5453 11:44:51.299210 10, 0x0, sum = 1
5454 11:44:51.299607 11, 0x0, sum = 2
5455 11:44:51.302105 12, 0x0, sum = 3
5456 11:44:51.302566 13, 0x0, sum = 4
5457 11:44:51.305117 best_step = 11
5458 11:44:51.305567
5459 11:44:51.305933 ==
5460 11:44:51.308933 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 11:44:51.311849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 11:44:51.312307 ==
5463 11:44:51.315390 RX Vref Scan: 0
5464 11:44:51.316034
5465 11:44:51.316412 RX Vref 0 -> 0, step: 1
5466 11:44:51.318408
5467 11:44:51.318843 RX Delay -61 -> 252, step: 4
5468 11:44:51.326157 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5469 11:44:51.329283 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5470 11:44:51.332242 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5471 11:44:51.335716 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5472 11:44:51.338644 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5473 11:44:51.342478 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5474 11:44:51.348879 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5475 11:44:51.351901 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5476 11:44:51.355389 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5477 11:44:51.358754 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5478 11:44:51.362231 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5479 11:44:51.368487 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5480 11:44:51.372191 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5481 11:44:51.375104 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5482 11:44:51.378752 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5483 11:44:51.381807 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5484 11:44:51.382437 ==
5485 11:44:51.385221 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 11:44:51.391846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 11:44:51.392422 ==
5488 11:44:51.392930 DQS Delay:
5489 11:44:51.395706 DQS0 = 0, DQS1 = 0
5490 11:44:51.396266 DQM Delay:
5491 11:44:51.396788 DQM0 = 96, DQM1 = 88
5492 11:44:51.398473 DQ Delay:
5493 11:44:51.402101 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5494 11:44:51.405178 DQ4 =96, DQ5 =86, DQ6 =108, DQ7 =102
5495 11:44:51.408845 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =78
5496 11:44:51.411815 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =94
5497 11:44:51.412246
5498 11:44:51.412586
5499 11:44:51.418553 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a07, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5500 11:44:51.422204 CH0 RK1: MR19=505, MR18=1A07
5501 11:44:51.428718 CH0_RK1: MR19=0x505, MR18=0x1A07, DQSOSC=413, MR23=63, INC=63, DEC=42
5502 11:44:51.431709 [RxdqsGatingPostProcess] freq 933
5503 11:44:51.435273 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5504 11:44:51.438528 best DQS0 dly(2T, 0.5T) = (0, 11)
5505 11:44:51.441859 best DQS1 dly(2T, 0.5T) = (0, 11)
5506 11:44:51.445413 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5507 11:44:51.448431 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5508 11:44:51.451822 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 11:44:51.455427 best DQS1 dly(2T, 0.5T) = (0, 10)
5510 11:44:51.458311 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 11:44:51.461777 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5512 11:44:51.465239 Pre-setting of DQS Precalculation
5513 11:44:51.468167 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5514 11:44:51.471919 ==
5515 11:44:51.472336 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 11:44:51.478584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 11:44:51.478988 ==
5518 11:44:51.481473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 11:44:51.488460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5520 11:44:51.491845 [CA 0] Center 36 (6~67) winsize 62
5521 11:44:51.495183 [CA 1] Center 36 (6~67) winsize 62
5522 11:44:51.498268 [CA 2] Center 34 (4~64) winsize 61
5523 11:44:51.501924 [CA 3] Center 33 (3~64) winsize 62
5524 11:44:51.505006 [CA 4] Center 34 (4~64) winsize 61
5525 11:44:51.508625 [CA 5] Center 33 (3~64) winsize 62
5526 11:44:51.509064
5527 11:44:51.511729 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5528 11:44:51.512243
5529 11:44:51.515067 [CATrainingPosCal] consider 1 rank data
5530 11:44:51.518208 u2DelayCellTimex100 = 270/100 ps
5531 11:44:51.521364 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 11:44:51.527908 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5533 11:44:51.531320 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 11:44:51.534984 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 11:44:51.538073 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5536 11:44:51.541097 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 11:44:51.541289
5538 11:44:51.544624 CA PerBit enable=1, Macro0, CA PI delay=33
5539 11:44:51.544826
5540 11:44:51.547504 [CBTSetCACLKResult] CA Dly = 33
5541 11:44:51.551167 CS Dly: 5 (0~36)
5542 11:44:51.551325 ==
5543 11:44:51.554490 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 11:44:51.557517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 11:44:51.557656 ==
5546 11:44:51.564565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 11:44:51.567505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5548 11:44:51.571698 [CA 0] Center 36 (6~67) winsize 62
5549 11:44:51.574734 [CA 1] Center 36 (6~67) winsize 62
5550 11:44:51.578303 [CA 2] Center 33 (3~64) winsize 62
5551 11:44:51.581368 [CA 3] Center 33 (3~64) winsize 62
5552 11:44:51.584422 [CA 4] Center 34 (4~64) winsize 61
5553 11:44:51.588244 [CA 5] Center 33 (3~63) winsize 61
5554 11:44:51.588415
5555 11:44:51.591218 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5556 11:44:51.591474
5557 11:44:51.594825 [CATrainingPosCal] consider 2 rank data
5558 11:44:51.598180 u2DelayCellTimex100 = 270/100 ps
5559 11:44:51.601275 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 11:44:51.604986 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 11:44:51.611793 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5562 11:44:51.614712 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5563 11:44:51.618526 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5564 11:44:51.621518 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5565 11:44:51.622084
5566 11:44:51.624642 CA PerBit enable=1, Macro0, CA PI delay=33
5567 11:44:51.625380
5568 11:44:51.628293 [CBTSetCACLKResult] CA Dly = 33
5569 11:44:51.628727 CS Dly: 5 (0~37)
5570 11:44:51.631327
5571 11:44:51.634844 ----->DramcWriteLeveling(PI) begin...
5572 11:44:51.635450 ==
5573 11:44:51.637863 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 11:44:51.641653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 11:44:51.642226 ==
5576 11:44:51.644724 Write leveling (Byte 0): 24 => 24
5577 11:44:51.647868 Write leveling (Byte 1): 28 => 28
5578 11:44:51.651164 DramcWriteLeveling(PI) end<-----
5579 11:44:51.651668
5580 11:44:51.652010 ==
5581 11:44:51.654809 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 11:44:51.658143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 11:44:51.658712 ==
5584 11:44:51.661502 [Gating] SW mode calibration
5585 11:44:51.667814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5586 11:44:51.674730 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5587 11:44:51.677615 0 14 0 | B1->B0 | 3131 3232 | 0 1 | (0 0) (1 1)
5588 11:44:51.681162 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5589 11:44:51.687987 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 11:44:51.690937 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5591 11:44:51.694611 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 11:44:51.701465 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 11:44:51.704401 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5594 11:44:51.708045 0 14 28 | B1->B0 | 3131 3131 | 1 0 | (1 0) (0 1)
5595 11:44:51.714686 0 15 0 | B1->B0 | 2d2d 2a2a | 0 0 | (1 0) (0 0)
5596 11:44:51.717704 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 11:44:51.720777 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 11:44:51.724395 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5599 11:44:51.731157 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 11:44:51.734181 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5601 11:44:51.737702 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 11:44:51.744467 0 15 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
5603 11:44:51.747456 1 0 0 | B1->B0 | 3d3d 4545 | 1 1 | (0 0) (0 0)
5604 11:44:51.751158 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 11:44:51.757615 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 11:44:51.761147 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 11:44:51.764204 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 11:44:51.771107 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 11:44:51.774139 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 11:44:51.777679 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5611 11:44:51.784078 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5612 11:44:51.787743 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 11:44:51.790849 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 11:44:51.797508 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 11:44:51.800502 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 11:44:51.803990 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 11:44:51.810814 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 11:44:51.814005 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 11:44:51.817536 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 11:44:51.823769 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 11:44:51.827461 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 11:44:51.830441 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 11:44:51.837304 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 11:44:51.840341 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 11:44:51.843948 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5626 11:44:51.850644 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5627 11:44:51.853568 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 11:44:51.857250 Total UI for P1: 0, mck2ui 16
5629 11:44:51.860320 best dqsien dly found for B0: ( 1, 2, 26)
5630 11:44:51.863943 Total UI for P1: 0, mck2ui 16
5631 11:44:51.867199 best dqsien dly found for B1: ( 1, 2, 26)
5632 11:44:51.870148 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5633 11:44:51.873764 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5634 11:44:51.874200
5635 11:44:51.877215 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5636 11:44:51.880102 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5637 11:44:51.883421 [Gating] SW calibration Done
5638 11:44:51.883946 ==
5639 11:44:51.886795 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 11:44:51.890424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 11:44:51.890946 ==
5642 11:44:51.893463 RX Vref Scan: 0
5643 11:44:51.893972
5644 11:44:51.896613 RX Vref 0 -> 0, step: 1
5645 11:44:51.897044
5646 11:44:51.897389 RX Delay -80 -> 252, step: 8
5647 11:44:51.903748 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5648 11:44:51.906701 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5649 11:44:51.910343 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5650 11:44:51.913137 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5651 11:44:51.916566 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5652 11:44:51.920145 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5653 11:44:51.926333 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5654 11:44:51.929940 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5655 11:44:51.933506 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5656 11:44:51.936660 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5657 11:44:51.940347 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5658 11:44:51.946510 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5659 11:44:51.950109 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5660 11:44:51.953795 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5661 11:44:51.956902 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5662 11:44:51.960371 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5663 11:44:51.960819 ==
5664 11:44:51.963405 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 11:44:51.966951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 11:44:51.970419 ==
5667 11:44:51.970857 DQS Delay:
5668 11:44:51.971200 DQS0 = 0, DQS1 = 0
5669 11:44:51.973322 DQM Delay:
5670 11:44:51.973757 DQM0 = 96, DQM1 = 88
5671 11:44:51.976838 DQ Delay:
5672 11:44:51.977270 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5673 11:44:51.980264 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5674 11:44:51.984104 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5675 11:44:51.986835 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5676 11:44:51.990317
5677 11:44:51.990833
5678 11:44:51.991421 ==
5679 11:44:51.993063 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 11:44:51.996681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 11:44:51.997119 ==
5682 11:44:51.997460
5683 11:44:51.997775
5684 11:44:51.999765 TX Vref Scan disable
5685 11:44:52.000222 == TX Byte 0 ==
5686 11:44:52.006901 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5687 11:44:52.010044 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5688 11:44:52.010481 == TX Byte 1 ==
5689 11:44:52.016606 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5690 11:44:52.020071 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5691 11:44:52.020519 ==
5692 11:44:52.022955 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 11:44:52.026632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 11:44:52.027079 ==
5695 11:44:52.027650
5696 11:44:52.028078
5697 11:44:52.029755 TX Vref Scan disable
5698 11:44:52.032986 == TX Byte 0 ==
5699 11:44:52.036590 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5700 11:44:52.039497 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5701 11:44:52.043331 == TX Byte 1 ==
5702 11:44:52.046257 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5703 11:44:52.049833 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5704 11:44:52.050372
5705 11:44:52.053392 [DATLAT]
5706 11:44:52.053953 Freq=933, CH1 RK0
5707 11:44:52.054442
5708 11:44:52.056399 DATLAT Default: 0xd
5709 11:44:52.057154 0, 0xFFFF, sum = 0
5710 11:44:52.059604 1, 0xFFFF, sum = 0
5711 11:44:52.060046 2, 0xFFFF, sum = 0
5712 11:44:52.063228 3, 0xFFFF, sum = 0
5713 11:44:52.063712 4, 0xFFFF, sum = 0
5714 11:44:52.066266 5, 0xFFFF, sum = 0
5715 11:44:52.066704 6, 0xFFFF, sum = 0
5716 11:44:52.069904 7, 0xFFFF, sum = 0
5717 11:44:52.070343 8, 0xFFFF, sum = 0
5718 11:44:52.072853 9, 0xFFFF, sum = 0
5719 11:44:52.073292 10, 0x0, sum = 1
5720 11:44:52.076334 11, 0x0, sum = 2
5721 11:44:52.076774 12, 0x0, sum = 3
5722 11:44:52.080057 13, 0x0, sum = 4
5723 11:44:52.080495 best_step = 11
5724 11:44:52.080840
5725 11:44:52.081155 ==
5726 11:44:52.082740 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 11:44:52.089492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 11:44:52.090031 ==
5729 11:44:52.090462 RX Vref Scan: 1
5730 11:44:52.090868
5731 11:44:52.092945 RX Vref 0 -> 0, step: 1
5732 11:44:52.093509
5733 11:44:52.096412 RX Delay -69 -> 252, step: 4
5734 11:44:52.096984
5735 11:44:52.099861 Set Vref, RX VrefLevel [Byte0]: 59
5736 11:44:52.102946 [Byte1]: 54
5737 11:44:52.103468
5738 11:44:52.106321 Final RX Vref Byte 0 = 59 to rank0
5739 11:44:52.109700 Final RX Vref Byte 1 = 54 to rank0
5740 11:44:52.112787 Final RX Vref Byte 0 = 59 to rank1
5741 11:44:52.116496 Final RX Vref Byte 1 = 54 to rank1==
5742 11:44:52.119341 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 11:44:52.122879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 11:44:52.123410 ==
5745 11:44:52.126205 DQS Delay:
5746 11:44:52.126638 DQS0 = 0, DQS1 = 0
5747 11:44:52.129059 DQM Delay:
5748 11:44:52.129500 DQM0 = 97, DQM1 = 91
5749 11:44:52.129845 DQ Delay:
5750 11:44:52.132824 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5751 11:44:52.136444 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5752 11:44:52.139426 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =86
5753 11:44:52.142977 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =96
5754 11:44:52.143464
5755 11:44:52.143811
5756 11:44:52.152859 [DQSOSCAuto] RK0, (LSB)MR18= 0x18f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 414 ps
5757 11:44:52.155797 CH1 RK0: MR19=504, MR18=18F5
5758 11:44:52.162438 CH1_RK0: MR19=0x504, MR18=0x18F5, DQSOSC=414, MR23=63, INC=63, DEC=42
5759 11:44:52.162870
5760 11:44:52.166253 ----->DramcWriteLeveling(PI) begin...
5761 11:44:52.166828 ==
5762 11:44:52.169218 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 11:44:52.172700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 11:44:52.173137 ==
5765 11:44:52.175754 Write leveling (Byte 0): 25 => 25
5766 11:44:52.179397 Write leveling (Byte 1): 27 => 27
5767 11:44:52.182779 DramcWriteLeveling(PI) end<-----
5768 11:44:52.183214
5769 11:44:52.183675 ==
5770 11:44:52.185711 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 11:44:52.189155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 11:44:52.189592 ==
5773 11:44:52.192875 [Gating] SW mode calibration
5774 11:44:52.199088 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5775 11:44:52.206174 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5776 11:44:52.209221 0 14 0 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5777 11:44:52.212311 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5778 11:44:52.218862 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 11:44:52.222473 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5780 11:44:52.225949 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 11:44:52.232237 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5782 11:44:52.235941 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 1)
5783 11:44:52.239003 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5784 11:44:52.245645 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 11:44:52.248579 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 11:44:52.252381 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5787 11:44:52.258994 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5788 11:44:52.261858 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 11:44:52.265494 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5790 11:44:52.271739 0 15 24 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5791 11:44:52.275513 0 15 28 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5792 11:44:52.278856 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 11:44:52.285446 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 11:44:52.288343 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 11:44:52.291781 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 11:44:52.298263 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 11:44:52.301796 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5798 11:44:52.305194 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5799 11:44:52.308572 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 11:44:52.315127 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 11:44:52.318329 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 11:44:52.321927 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 11:44:52.328631 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 11:44:52.331752 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 11:44:52.335221 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 11:44:52.341871 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 11:44:52.344954 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 11:44:52.348679 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 11:44:52.355325 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 11:44:52.358407 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 11:44:52.362089 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 11:44:52.368642 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 11:44:52.371655 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 11:44:52.375557 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5815 11:44:52.381883 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 11:44:52.382295 Total UI for P1: 0, mck2ui 16
5817 11:44:52.388235 best dqsien dly found for B0: ( 1, 2, 24)
5818 11:44:52.388762 Total UI for P1: 0, mck2ui 16
5819 11:44:52.394742 best dqsien dly found for B1: ( 1, 2, 24)
5820 11:44:52.398265 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5821 11:44:52.401909 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5822 11:44:52.402304
5823 11:44:52.404783 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5824 11:44:52.408231 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5825 11:44:52.411735 [Gating] SW calibration Done
5826 11:44:52.412138 ==
5827 11:44:52.415050 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 11:44:52.418147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 11:44:52.418547 ==
5830 11:44:52.421751 RX Vref Scan: 0
5831 11:44:52.422284
5832 11:44:52.422732 RX Vref 0 -> 0, step: 1
5833 11:44:52.423154
5834 11:44:52.424731 RX Delay -80 -> 252, step: 8
5835 11:44:52.428413 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5836 11:44:52.432115 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5837 11:44:52.438152 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5838 11:44:52.441680 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5839 11:44:52.444730 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5840 11:44:52.448355 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5841 11:44:52.451454 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5842 11:44:52.455019 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5843 11:44:52.461752 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5844 11:44:52.464814 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5845 11:44:52.467950 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5846 11:44:52.471458 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5847 11:44:52.474677 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5848 11:44:52.481909 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5849 11:44:52.484813 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5850 11:44:52.488290 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5851 11:44:52.488688 ==
5852 11:44:52.491276 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 11:44:52.495071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 11:44:52.495544 ==
5855 11:44:52.498111 DQS Delay:
5856 11:44:52.498468 DQS0 = 0, DQS1 = 0
5857 11:44:52.498773 DQM Delay:
5858 11:44:52.501195 DQM0 = 94, DQM1 = 89
5859 11:44:52.501626 DQ Delay:
5860 11:44:52.504627 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5861 11:44:52.508005 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5862 11:44:52.510875 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5863 11:44:52.514906 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5864 11:44:52.515303
5865 11:44:52.515668
5866 11:44:52.515966 ==
5867 11:44:52.517808 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 11:44:52.524431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 11:44:52.524839 ==
5870 11:44:52.525161
5871 11:44:52.525455
5872 11:44:52.525739 TX Vref Scan disable
5873 11:44:52.528155 == TX Byte 0 ==
5874 11:44:52.531636 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5875 11:44:52.538203 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5876 11:44:52.538602 == TX Byte 1 ==
5877 11:44:52.541410 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5878 11:44:52.548038 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5879 11:44:52.548439 ==
5880 11:44:52.551724 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 11:44:52.554771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 11:44:52.555171 ==
5883 11:44:52.555514
5884 11:44:52.555808
5885 11:44:52.557736 TX Vref Scan disable
5886 11:44:52.561443 == TX Byte 0 ==
5887 11:44:52.564480 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5888 11:44:52.568129 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5889 11:44:52.571190 == TX Byte 1 ==
5890 11:44:52.574308 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5891 11:44:52.577756 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5892 11:44:52.578154
5893 11:44:52.578463 [DATLAT]
5894 11:44:52.580836 Freq=933, CH1 RK1
5895 11:44:52.581273
5896 11:44:52.581799 DATLAT Default: 0xb
5897 11:44:52.584393 0, 0xFFFF, sum = 0
5898 11:44:52.587418 1, 0xFFFF, sum = 0
5899 11:44:52.587819 2, 0xFFFF, sum = 0
5900 11:44:52.590976 3, 0xFFFF, sum = 0
5901 11:44:52.591406 4, 0xFFFF, sum = 0
5902 11:44:52.593931 5, 0xFFFF, sum = 0
5903 11:44:52.594372 6, 0xFFFF, sum = 0
5904 11:44:52.597533 7, 0xFFFF, sum = 0
5905 11:44:52.598078 8, 0xFFFF, sum = 0
5906 11:44:52.601142 9, 0xFFFF, sum = 0
5907 11:44:52.601726 10, 0x0, sum = 1
5908 11:44:52.604271 11, 0x0, sum = 2
5909 11:44:52.604758 12, 0x0, sum = 3
5910 11:44:52.607120 13, 0x0, sum = 4
5911 11:44:52.607697 best_step = 11
5912 11:44:52.608124
5913 11:44:52.608639 ==
5914 11:44:52.610704 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 11:44:52.614089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 11:44:52.614492 ==
5917 11:44:52.617120 RX Vref Scan: 0
5918 11:44:52.617578
5919 11:44:52.620455 RX Vref 0 -> 0, step: 1
5920 11:44:52.621034
5921 11:44:52.621616 RX Delay -61 -> 252, step: 4
5922 11:44:52.628381 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5923 11:44:52.631926 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5924 11:44:52.635440 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5925 11:44:52.638479 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5926 11:44:52.642211 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5927 11:44:52.645277 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5928 11:44:52.651657 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5929 11:44:52.655331 iDelay=195, Bit 7, Center 92 (7 ~ 178) 172
5930 11:44:52.658337 iDelay=195, Bit 8, Center 82 (-9 ~ 174) 184
5931 11:44:52.661443 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5932 11:44:52.664992 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5933 11:44:52.668127 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5934 11:44:52.674694 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5935 11:44:52.678350 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5936 11:44:52.681829 iDelay=195, Bit 14, Center 96 (3 ~ 190) 188
5937 11:44:52.684891 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5938 11:44:52.684997 ==
5939 11:44:52.688543 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 11:44:52.691577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 11:44:52.695129 ==
5942 11:44:52.695234 DQS Delay:
5943 11:44:52.695369 DQS0 = 0, DQS1 = 0
5944 11:44:52.698573 DQM Delay:
5945 11:44:52.698678 DQM0 = 95, DQM1 = 90
5946 11:44:52.701719 DQ Delay:
5947 11:44:52.701824 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5948 11:44:52.704892 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5949 11:44:52.708065 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =84
5950 11:44:52.711542 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5951 11:44:52.714862
5952 11:44:52.715000
5953 11:44:52.721523 [DQSOSCAuto] RK1, (LSB)MR18= 0xb14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5954 11:44:52.724908 CH1 RK1: MR19=505, MR18=B14
5955 11:44:52.731316 CH1_RK1: MR19=0x505, MR18=0xB14, DQSOSC=415, MR23=63, INC=62, DEC=41
5956 11:44:52.731550 [RxdqsGatingPostProcess] freq 933
5957 11:44:52.738189 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5958 11:44:52.741599 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 11:44:52.744639 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 11:44:52.747751 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 11:44:52.751288 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 11:44:52.754895 best DQS0 dly(2T, 0.5T) = (0, 10)
5963 11:44:52.757994 best DQS1 dly(2T, 0.5T) = (0, 10)
5964 11:44:52.761104 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5965 11:44:52.764758 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5966 11:44:52.767678 Pre-setting of DQS Precalculation
5967 11:44:52.771258 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5968 11:44:52.778114 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5969 11:44:52.784720 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5970 11:44:52.787879
5971 11:44:52.788063
5972 11:44:52.788227 [Calibration Summary] 1866 Mbps
5973 11:44:52.791388 CH 0, Rank 0
5974 11:44:52.791583 SW Impedance : PASS
5975 11:44:52.794506 DUTY Scan : NO K
5976 11:44:52.797536 ZQ Calibration : PASS
5977 11:44:52.797772 Jitter Meter : NO K
5978 11:44:52.801085 CBT Training : PASS
5979 11:44:52.805012 Write leveling : PASS
5980 11:44:52.805410 RX DQS gating : PASS
5981 11:44:52.807902 RX DQ/DQS(RDDQC) : PASS
5982 11:44:52.811608 TX DQ/DQS : PASS
5983 11:44:52.812082 RX DATLAT : PASS
5984 11:44:52.814668 RX DQ/DQS(Engine): PASS
5985 11:44:52.818365 TX OE : NO K
5986 11:44:52.818794 All Pass.
5987 11:44:52.819136
5988 11:44:52.819504 CH 0, Rank 1
5989 11:44:52.821322 SW Impedance : PASS
5990 11:44:52.824593 DUTY Scan : NO K
5991 11:44:52.825371 ZQ Calibration : PASS
5992 11:44:52.827915 Jitter Meter : NO K
5993 11:44:52.831344 CBT Training : PASS
5994 11:44:52.831852 Write leveling : PASS
5995 11:44:52.834786 RX DQS gating : PASS
5996 11:44:52.835382 RX DQ/DQS(RDDQC) : PASS
5997 11:44:52.838152 TX DQ/DQS : PASS
5998 11:44:52.841340 RX DATLAT : PASS
5999 11:44:52.841819 RX DQ/DQS(Engine): PASS
6000 11:44:52.844674 TX OE : NO K
6001 11:44:52.845110 All Pass.
6002 11:44:52.845632
6003 11:44:52.848087 CH 1, Rank 0
6004 11:44:52.848608 SW Impedance : PASS
6005 11:44:52.851340 DUTY Scan : NO K
6006 11:44:52.854414 ZQ Calibration : PASS
6007 11:44:52.855029 Jitter Meter : NO K
6008 11:44:52.857804 CBT Training : PASS
6009 11:44:52.861507 Write leveling : PASS
6010 11:44:52.862086 RX DQS gating : PASS
6011 11:44:52.864578 RX DQ/DQS(RDDQC) : PASS
6012 11:44:52.867593 TX DQ/DQS : PASS
6013 11:44:52.868178 RX DATLAT : PASS
6014 11:44:52.871335 RX DQ/DQS(Engine): PASS
6015 11:44:52.874339 TX OE : NO K
6016 11:44:52.874819 All Pass.
6017 11:44:52.875185
6018 11:44:52.875594 CH 1, Rank 1
6019 11:44:52.878067 SW Impedance : PASS
6020 11:44:52.881036 DUTY Scan : NO K
6021 11:44:52.881492 ZQ Calibration : PASS
6022 11:44:52.884246 Jitter Meter : NO K
6023 11:44:52.887791 CBT Training : PASS
6024 11:44:52.888289 Write leveling : PASS
6025 11:44:52.890739 RX DQS gating : PASS
6026 11:44:52.891399 RX DQ/DQS(RDDQC) : PASS
6027 11:44:52.894358 TX DQ/DQS : PASS
6028 11:44:52.897422 RX DATLAT : PASS
6029 11:44:52.897943 RX DQ/DQS(Engine): PASS
6030 11:44:52.901190 TX OE : NO K
6031 11:44:52.901693 All Pass.
6032 11:44:52.902152
6033 11:44:52.904147 DramC Write-DBI off
6034 11:44:52.907820 PER_BANK_REFRESH: Hybrid Mode
6035 11:44:52.908251 TX_TRACKING: ON
6036 11:44:52.917647 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6037 11:44:52.920623 [FAST_K] Save calibration result to emmc
6038 11:44:52.924196 dramc_set_vcore_voltage set vcore to 650000
6039 11:44:52.927248 Read voltage for 400, 6
6040 11:44:52.927704 Vio18 = 0
6041 11:44:52.930543 Vcore = 650000
6042 11:44:52.931139 Vdram = 0
6043 11:44:52.931690 Vddq = 0
6044 11:44:52.932182 Vmddr = 0
6045 11:44:52.937678 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6046 11:44:52.940731 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6047 11:44:52.943631 MEM_TYPE=3, freq_sel=20
6048 11:44:52.947136 sv_algorithm_assistance_LP4_800
6049 11:44:52.950903 ============ PULL DRAM RESETB DOWN ============
6050 11:44:52.957138 ========== PULL DRAM RESETB DOWN end =========
6051 11:44:52.960461 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6052 11:44:52.963962 ===================================
6053 11:44:52.966945 LPDDR4 DRAM CONFIGURATION
6054 11:44:52.970645 ===================================
6055 11:44:52.971072 EX_ROW_EN[0] = 0x0
6056 11:44:52.973715 EX_ROW_EN[1] = 0x0
6057 11:44:52.974140 LP4Y_EN = 0x0
6058 11:44:52.977256 WORK_FSP = 0x0
6059 11:44:52.977685 WL = 0x2
6060 11:44:52.980403 RL = 0x2
6061 11:44:52.980830 BL = 0x2
6062 11:44:52.983388 RPST = 0x0
6063 11:44:52.987303 RD_PRE = 0x0
6064 11:44:52.987795 WR_PRE = 0x1
6065 11:44:52.990168 WR_PST = 0x0
6066 11:44:52.990592 DBI_WR = 0x0
6067 11:44:52.993606 DBI_RD = 0x0
6068 11:44:52.994207 OTF = 0x1
6069 11:44:52.996726 ===================================
6070 11:44:53.000421 ===================================
6071 11:44:53.003339 ANA top config
6072 11:44:53.003787 ===================================
6073 11:44:53.006475 DLL_ASYNC_EN = 0
6074 11:44:53.009945 ALL_SLAVE_EN = 1
6075 11:44:53.013572 NEW_RANK_MODE = 1
6076 11:44:53.016665 DLL_IDLE_MODE = 1
6077 11:44:53.017093 LP45_APHY_COMB_EN = 1
6078 11:44:53.020269 TX_ODT_DIS = 1
6079 11:44:53.023287 NEW_8X_MODE = 1
6080 11:44:53.026912 ===================================
6081 11:44:53.030021 ===================================
6082 11:44:53.032934 data_rate = 800
6083 11:44:53.036554 CKR = 1
6084 11:44:53.037001 DQ_P2S_RATIO = 4
6085 11:44:53.040046 ===================================
6086 11:44:53.043405 CA_P2S_RATIO = 4
6087 11:44:53.046614 DQ_CA_OPEN = 0
6088 11:44:53.050206 DQ_SEMI_OPEN = 1
6089 11:44:53.053487 CA_SEMI_OPEN = 1
6090 11:44:53.056418 CA_FULL_RATE = 0
6091 11:44:53.056905 DQ_CKDIV4_EN = 0
6092 11:44:53.059676 CA_CKDIV4_EN = 1
6093 11:44:53.063098 CA_PREDIV_EN = 0
6094 11:44:53.066382 PH8_DLY = 0
6095 11:44:53.069740 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6096 11:44:53.073179 DQ_AAMCK_DIV = 0
6097 11:44:53.073605 CA_AAMCK_DIV = 0
6098 11:44:53.076766 CA_ADMCK_DIV = 4
6099 11:44:53.079807 DQ_TRACK_CA_EN = 0
6100 11:44:53.083194 CA_PICK = 800
6101 11:44:53.086394 CA_MCKIO = 400
6102 11:44:53.089449 MCKIO_SEMI = 400
6103 11:44:53.093322 PLL_FREQ = 3016
6104 11:44:53.096207 DQ_UI_PI_RATIO = 32
6105 11:44:53.096707 CA_UI_PI_RATIO = 32
6106 11:44:53.099853 ===================================
6107 11:44:53.102872 ===================================
6108 11:44:53.105992 memory_type:LPDDR4
6109 11:44:53.109837 GP_NUM : 10
6110 11:44:53.110265 SRAM_EN : 1
6111 11:44:53.112649 MD32_EN : 0
6112 11:44:53.116180 ===================================
6113 11:44:53.119940 [ANA_INIT] >>>>>>>>>>>>>>
6114 11:44:53.122825 <<<<<< [CONFIGURE PHASE]: ANA_TX
6115 11:44:53.126023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6116 11:44:53.129610 ===================================
6117 11:44:53.130036 data_rate = 800,PCW = 0X7400
6118 11:44:53.132768 ===================================
6119 11:44:53.136423 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6120 11:44:53.142921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 11:44:53.155938 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 11:44:53.159399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6123 11:44:53.162203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6124 11:44:53.165698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6125 11:44:53.169166 [ANA_INIT] flow start
6126 11:44:53.169601 [ANA_INIT] PLL >>>>>>>>
6127 11:44:53.172669 [ANA_INIT] PLL <<<<<<<<
6128 11:44:53.175893 [ANA_INIT] MIDPI >>>>>>>>
6129 11:44:53.176325 [ANA_INIT] MIDPI <<<<<<<<
6130 11:44:53.179221 [ANA_INIT] DLL >>>>>>>>
6131 11:44:53.182739 [ANA_INIT] flow end
6132 11:44:53.185702 ============ LP4 DIFF to SE enter ============
6133 11:44:53.189346 ============ LP4 DIFF to SE exit ============
6134 11:44:53.192338 [ANA_INIT] <<<<<<<<<<<<<
6135 11:44:53.195404 [Flow] Enable top DCM control >>>>>
6136 11:44:53.199081 [Flow] Enable top DCM control <<<<<
6137 11:44:53.202084 Enable DLL master slave shuffle
6138 11:44:53.205467 ==============================================================
6139 11:44:53.208340 Gating Mode config
6140 11:44:53.215011 ==============================================================
6141 11:44:53.215129 Config description:
6142 11:44:53.225495 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6143 11:44:53.231555 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6144 11:44:53.235188 SELPH_MODE 0: By rank 1: By Phase
6145 11:44:53.241534 ==============================================================
6146 11:44:53.245261 GAT_TRACK_EN = 0
6147 11:44:53.248302 RX_GATING_MODE = 2
6148 11:44:53.251956 RX_GATING_TRACK_MODE = 2
6149 11:44:53.254864 SELPH_MODE = 1
6150 11:44:53.258289 PICG_EARLY_EN = 1
6151 11:44:53.261576 VALID_LAT_VALUE = 1
6152 11:44:53.264984 ==============================================================
6153 11:44:53.268313 Enter into Gating configuration >>>>
6154 11:44:53.271651 Exit from Gating configuration <<<<
6155 11:44:53.274910 Enter into DVFS_PRE_config >>>>>
6156 11:44:53.288322 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6157 11:44:53.291189 Exit from DVFS_PRE_config <<<<<
6158 11:44:53.291270 Enter into PICG configuration >>>>
6159 11:44:53.294919 Exit from PICG configuration <<<<
6160 11:44:53.298099 [RX_INPUT] configuration >>>>>
6161 11:44:53.301282 [RX_INPUT] configuration <<<<<
6162 11:44:53.307746 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6163 11:44:53.311325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6164 11:44:53.318143 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 11:44:53.324704 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 11:44:53.331444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6167 11:44:53.337452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6168 11:44:53.341042 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6169 11:44:53.344204 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6170 11:44:53.347856 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6171 11:44:53.354087 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6172 11:44:53.357716 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6173 11:44:53.360877 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 11:44:53.363773 ===================================
6175 11:44:53.367340 LPDDR4 DRAM CONFIGURATION
6176 11:44:53.370758 ===================================
6177 11:44:53.373944 EX_ROW_EN[0] = 0x0
6178 11:44:53.374093 EX_ROW_EN[1] = 0x0
6179 11:44:53.377449 LP4Y_EN = 0x0
6180 11:44:53.377534 WORK_FSP = 0x0
6181 11:44:53.380804 WL = 0x2
6182 11:44:53.380933 RL = 0x2
6183 11:44:53.383782 BL = 0x2
6184 11:44:53.383882 RPST = 0x0
6185 11:44:53.386972 RD_PRE = 0x0
6186 11:44:53.387056 WR_PRE = 0x1
6187 11:44:53.390314 WR_PST = 0x0
6188 11:44:53.390398 DBI_WR = 0x0
6189 11:44:53.393552 DBI_RD = 0x0
6190 11:44:53.397034 OTF = 0x1
6191 11:44:53.400397 ===================================
6192 11:44:53.403493 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6193 11:44:53.407180 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6194 11:44:53.410706 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 11:44:53.413844 ===================================
6196 11:44:53.417350 LPDDR4 DRAM CONFIGURATION
6197 11:44:53.420438 ===================================
6198 11:44:53.423567 EX_ROW_EN[0] = 0x10
6199 11:44:53.423651 EX_ROW_EN[1] = 0x0
6200 11:44:53.427021 LP4Y_EN = 0x0
6201 11:44:53.427105 WORK_FSP = 0x0
6202 11:44:53.429976 WL = 0x2
6203 11:44:53.430103 RL = 0x2
6204 11:44:53.433614 BL = 0x2
6205 11:44:53.433715 RPST = 0x0
6206 11:44:53.436715 RD_PRE = 0x0
6207 11:44:53.436815 WR_PRE = 0x1
6208 11:44:53.440358 WR_PST = 0x0
6209 11:44:53.440455 DBI_WR = 0x0
6210 11:44:53.443442 DBI_RD = 0x0
6211 11:44:53.443526 OTF = 0x1
6212 11:44:53.447120 ===================================
6213 11:44:53.453144 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6214 11:44:53.458709 nWR fixed to 30
6215 11:44:53.461710 [ModeRegInit_LP4] CH0 RK0
6216 11:44:53.461817 [ModeRegInit_LP4] CH0 RK1
6217 11:44:53.464837 [ModeRegInit_LP4] CH1 RK0
6218 11:44:53.468532 [ModeRegInit_LP4] CH1 RK1
6219 11:44:53.468635 match AC timing 19
6220 11:44:53.475064 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6221 11:44:53.478534 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6222 11:44:53.481744 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6223 11:44:53.488482 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6224 11:44:53.491508 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6225 11:44:53.491593 ==
6226 11:44:53.494825 Dram Type= 6, Freq= 0, CH_0, rank 0
6227 11:44:53.498336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 11:44:53.498445 ==
6229 11:44:53.504802 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 11:44:53.511835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6231 11:44:53.514767 [CA 0] Center 36 (8~64) winsize 57
6232 11:44:53.518611 [CA 1] Center 36 (8~64) winsize 57
6233 11:44:53.521658 [CA 2] Center 36 (8~64) winsize 57
6234 11:44:53.521759 [CA 3] Center 36 (8~64) winsize 57
6235 11:44:53.524741 [CA 4] Center 36 (8~64) winsize 57
6236 11:44:53.528421 [CA 5] Center 36 (8~64) winsize 57
6237 11:44:53.528521
6238 11:44:53.531773 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6239 11:44:53.534851
6240 11:44:53.538681 [CATrainingPosCal] consider 1 rank data
6241 11:44:53.538779 u2DelayCellTimex100 = 270/100 ps
6242 11:44:53.544559 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:44:53.548054 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:44:53.551173 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:44:53.554780 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:44:53.557996 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 11:44:53.561628 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 11:44:53.561741
6249 11:44:53.564686 CA PerBit enable=1, Macro0, CA PI delay=36
6250 11:44:53.564786
6251 11:44:53.568339 [CBTSetCACLKResult] CA Dly = 36
6252 11:44:53.571455 CS Dly: 1 (0~32)
6253 11:44:53.571528 ==
6254 11:44:53.575040 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 11:44:53.578214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 11:44:53.578313 ==
6257 11:44:53.584668 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 11:44:53.588138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6259 11:44:53.591499 [CA 0] Center 36 (8~64) winsize 57
6260 11:44:53.594473 [CA 1] Center 36 (8~64) winsize 57
6261 11:44:53.598051 [CA 2] Center 36 (8~64) winsize 57
6262 11:44:53.601169 [CA 3] Center 36 (8~64) winsize 57
6263 11:44:53.604535 [CA 4] Center 36 (8~64) winsize 57
6264 11:44:53.608025 [CA 5] Center 36 (8~64) winsize 57
6265 11:44:53.608108
6266 11:44:53.610960 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6267 11:44:53.611042
6268 11:44:53.614438 [CATrainingPosCal] consider 2 rank data
6269 11:44:53.617960 u2DelayCellTimex100 = 270/100 ps
6270 11:44:53.621336 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 11:44:53.624962 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 11:44:53.627929 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 11:44:53.634506 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 11:44:53.638115 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 11:44:53.640982 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 11:44:53.641066
6277 11:44:53.644680 CA PerBit enable=1, Macro0, CA PI delay=36
6278 11:44:53.644764
6279 11:44:53.647669 [CBTSetCACLKResult] CA Dly = 36
6280 11:44:53.647752 CS Dly: 1 (0~32)
6281 11:44:53.647817
6282 11:44:53.651330 ----->DramcWriteLeveling(PI) begin...
6283 11:44:53.651456 ==
6284 11:44:53.654448 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 11:44:53.661166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 11:44:53.661249 ==
6287 11:44:53.664183 Write leveling (Byte 0): 40 => 8
6288 11:44:53.667935 Write leveling (Byte 1): 32 => 0
6289 11:44:53.668018 DramcWriteLeveling(PI) end<-----
6290 11:44:53.668083
6291 11:44:53.670998 ==
6292 11:44:53.674653 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 11:44:53.677783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 11:44:53.677865 ==
6295 11:44:53.680939 [Gating] SW mode calibration
6296 11:44:53.687565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6297 11:44:53.691133 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6298 11:44:53.697358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 11:44:53.701000 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 11:44:53.704066 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 11:44:53.711040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 11:44:53.714084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 11:44:53.717633 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 11:44:53.723824 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 11:44:53.727217 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 11:44:53.730982 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 11:44:53.733956 Total UI for P1: 0, mck2ui 16
6308 11:44:53.737512 best dqsien dly found for B0: ( 0, 14, 24)
6309 11:44:53.740506 Total UI for P1: 0, mck2ui 16
6310 11:44:53.744175 best dqsien dly found for B1: ( 0, 14, 24)
6311 11:44:53.747085 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6312 11:44:53.750654 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6313 11:44:53.750737
6314 11:44:53.757362 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 11:44:53.760380 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 11:44:53.764028 [Gating] SW calibration Done
6317 11:44:53.764134 ==
6318 11:44:53.767185 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 11:44:53.770745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 11:44:53.770827 ==
6321 11:44:53.770891 RX Vref Scan: 0
6322 11:44:53.770950
6323 11:44:53.773936 RX Vref 0 -> 0, step: 1
6324 11:44:53.774019
6325 11:44:53.776905 RX Delay -410 -> 252, step: 16
6326 11:44:53.780546 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6327 11:44:53.786733 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6328 11:44:53.790370 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6329 11:44:53.793776 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6330 11:44:53.796663 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6331 11:44:53.803650 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6332 11:44:53.806672 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6333 11:44:53.810169 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6334 11:44:53.813547 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6335 11:44:53.820280 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6336 11:44:53.823654 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6337 11:44:53.826701 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6338 11:44:53.830134 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6339 11:44:53.836711 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6340 11:44:53.840386 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6341 11:44:53.843262 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6342 11:44:53.843415 ==
6343 11:44:53.846747 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 11:44:53.850346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 11:44:53.853352 ==
6346 11:44:53.853531 DQS Delay:
6347 11:44:53.853658 DQS0 = 35, DQS1 = 51
6348 11:44:53.856857 DQM Delay:
6349 11:44:53.857057 DQM0 = 8, DQM1 = 10
6350 11:44:53.859971 DQ Delay:
6351 11:44:53.860203 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6352 11:44:53.863854 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6353 11:44:53.866824 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6354 11:44:53.870544 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6355 11:44:53.870951
6356 11:44:53.871338
6357 11:44:53.871744 ==
6358 11:44:53.873588 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 11:44:53.880592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 11:44:53.881307 ==
6361 11:44:53.881922
6362 11:44:53.882461
6363 11:44:53.883014 TX Vref Scan disable
6364 11:44:53.883931 == TX Byte 0 ==
6365 11:44:53.886655 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 11:44:53.890248 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 11:44:53.893309 == TX Byte 1 ==
6368 11:44:53.896816 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6369 11:44:53.900226 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6370 11:44:53.903746 ==
6371 11:44:53.907174 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 11:44:53.910110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 11:44:53.910546 ==
6374 11:44:53.910888
6375 11:44:53.911204
6376 11:44:53.913592 TX Vref Scan disable
6377 11:44:53.914239 == TX Byte 0 ==
6378 11:44:53.916958 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 11:44:53.923420 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 11:44:53.924171 == TX Byte 1 ==
6381 11:44:53.926786 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6382 11:44:53.933576 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6383 11:44:53.934057
6384 11:44:53.934408 [DATLAT]
6385 11:44:53.934769 Freq=400, CH0 RK0
6386 11:44:53.935104
6387 11:44:53.937014 DATLAT Default: 0xf
6388 11:44:53.937551 0, 0xFFFF, sum = 0
6389 11:44:53.939834 1, 0xFFFF, sum = 0
6390 11:44:53.943610 2, 0xFFFF, sum = 0
6391 11:44:53.944340 3, 0xFFFF, sum = 0
6392 11:44:53.946536 4, 0xFFFF, sum = 0
6393 11:44:53.947068 5, 0xFFFF, sum = 0
6394 11:44:53.949885 6, 0xFFFF, sum = 0
6395 11:44:53.950545 7, 0xFFFF, sum = 0
6396 11:44:53.953435 8, 0xFFFF, sum = 0
6397 11:44:53.953883 9, 0xFFFF, sum = 0
6398 11:44:53.956475 10, 0xFFFF, sum = 0
6399 11:44:53.956995 11, 0xFFFF, sum = 0
6400 11:44:53.960203 12, 0xFFFF, sum = 0
6401 11:44:53.960698 13, 0x0, sum = 1
6402 11:44:53.963070 14, 0x0, sum = 2
6403 11:44:53.963540 15, 0x0, sum = 3
6404 11:44:53.966930 16, 0x0, sum = 4
6405 11:44:53.967502 best_step = 14
6406 11:44:53.967883
6407 11:44:53.968232 ==
6408 11:44:53.970034 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 11:44:53.973044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 11:44:53.976722 ==
6411 11:44:53.977167 RX Vref Scan: 1
6412 11:44:53.977608
6413 11:44:53.979671 RX Vref 0 -> 0, step: 1
6414 11:44:53.980158
6415 11:44:53.983420 RX Delay -343 -> 252, step: 8
6416 11:44:53.983928
6417 11:44:53.986407 Set Vref, RX VrefLevel [Byte0]: 51
6418 11:44:53.990079 [Byte1]: 51
6419 11:44:53.990717
6420 11:44:53.993092 Final RX Vref Byte 0 = 51 to rank0
6421 11:44:53.996118 Final RX Vref Byte 1 = 51 to rank0
6422 11:44:53.999801 Final RX Vref Byte 0 = 51 to rank1
6423 11:44:54.003567 Final RX Vref Byte 1 = 51 to rank1==
6424 11:44:54.006062 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 11:44:54.009544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 11:44:54.010132 ==
6427 11:44:54.013163 DQS Delay:
6428 11:44:54.013790 DQS0 = 44, DQS1 = 60
6429 11:44:54.016118 DQM Delay:
6430 11:44:54.016698 DQM0 = 11, DQM1 = 14
6431 11:44:54.019494 DQ Delay:
6432 11:44:54.020127 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6433 11:44:54.022859 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6434 11:44:54.026272 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6435 11:44:54.029904 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6436 11:44:54.030580
6437 11:44:54.031195
6438 11:44:54.039877 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e4b, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6439 11:44:54.042728 CH0 RK0: MR19=C0C, MR18=7E4B
6440 11:44:54.046365 CH0_RK0: MR19=0xC0C, MR18=0x7E4B, DQSOSC=393, MR23=63, INC=382, DEC=254
6441 11:44:54.049404 ==
6442 11:44:54.052960 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 11:44:54.055937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 11:44:54.056460 ==
6445 11:44:54.059435 [Gating] SW mode calibration
6446 11:44:54.066122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6447 11:44:54.069832 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6448 11:44:54.075810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 11:44:54.079535 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 11:44:54.082712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 11:44:54.089431 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 11:44:54.092722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 11:44:54.096178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 11:44:54.102951 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 11:44:54.106080 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 11:44:54.109627 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 11:44:54.112507 Total UI for P1: 0, mck2ui 16
6458 11:44:54.115853 best dqsien dly found for B0: ( 0, 14, 24)
6459 11:44:54.119168 Total UI for P1: 0, mck2ui 16
6460 11:44:54.122787 best dqsien dly found for B1: ( 0, 14, 24)
6461 11:44:54.125686 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6462 11:44:54.129413 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6463 11:44:54.129876
6464 11:44:54.135724 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 11:44:54.139316 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 11:44:54.139914 [Gating] SW calibration Done
6467 11:44:54.142592 ==
6468 11:44:54.145493 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 11:44:54.148987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 11:44:54.149461 ==
6471 11:44:54.149800 RX Vref Scan: 0
6472 11:44:54.150118
6473 11:44:54.152666 RX Vref 0 -> 0, step: 1
6474 11:44:54.153242
6475 11:44:54.155587 RX Delay -410 -> 252, step: 16
6476 11:44:54.159078 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6477 11:44:54.165588 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6478 11:44:54.168682 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6479 11:44:54.178014 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6480 11:44:54.178674 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6481 11:44:54.181908 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6482 11:44:54.185526 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6483 11:44:54.188735 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6484 11:44:54.192308 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6485 11:44:54.198711 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6486 11:44:54.202201 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6487 11:44:54.205302 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6488 11:44:54.208430 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6489 11:44:54.215101 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6490 11:44:54.218255 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6491 11:44:54.221721 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6492 11:44:54.222148 ==
6493 11:44:54.225293 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 11:44:54.228654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 11:44:54.231947 ==
6496 11:44:54.232443 DQS Delay:
6497 11:44:54.232786 DQS0 = 43, DQS1 = 51
6498 11:44:54.235319 DQM Delay:
6499 11:44:54.235725 DQM0 = 12, DQM1 = 10
6500 11:44:54.238705 DQ Delay:
6501 11:44:54.239268 DQ0 =16, DQ1 =8, DQ2 =8, DQ3 =8
6502 11:44:54.242028 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6503 11:44:54.245217 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6504 11:44:54.248241 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6505 11:44:54.249010
6506 11:44:54.249582
6507 11:44:54.251769 ==
6508 11:44:54.252200 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 11:44:54.258390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 11:44:54.258821 ==
6511 11:44:54.259162
6512 11:44:54.259525
6513 11:44:54.261486 TX Vref Scan disable
6514 11:44:54.261940 == TX Byte 0 ==
6515 11:44:54.265028 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6516 11:44:54.271502 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6517 11:44:54.271933 == TX Byte 1 ==
6518 11:44:54.275203 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6519 11:44:54.278254 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6520 11:44:54.281996 ==
6521 11:44:54.284985 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 11:44:54.288602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 11:44:54.289040 ==
6524 11:44:54.289403
6525 11:44:54.289739
6526 11:44:54.291486 TX Vref Scan disable
6527 11:44:54.291943 == TX Byte 0 ==
6528 11:44:54.295065 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6529 11:44:54.301344 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6530 11:44:54.301914 == TX Byte 1 ==
6531 11:44:54.304964 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6532 11:44:54.311649 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6533 11:44:54.312212
6534 11:44:54.312699 [DATLAT]
6535 11:44:54.313163 Freq=400, CH0 RK1
6536 11:44:54.313616
6537 11:44:54.314657 DATLAT Default: 0xe
6538 11:44:54.315094 0, 0xFFFF, sum = 0
6539 11:44:54.318185 1, 0xFFFF, sum = 0
6540 11:44:54.318798 2, 0xFFFF, sum = 0
6541 11:44:54.321316 3, 0xFFFF, sum = 0
6542 11:44:54.321752 4, 0xFFFF, sum = 0
6543 11:44:54.324364 5, 0xFFFF, sum = 0
6544 11:44:54.327986 6, 0xFFFF, sum = 0
6545 11:44:54.328417 7, 0xFFFF, sum = 0
6546 11:44:54.331436 8, 0xFFFF, sum = 0
6547 11:44:54.331867 9, 0xFFFF, sum = 0
6548 11:44:54.335129 10, 0xFFFF, sum = 0
6549 11:44:54.335668 11, 0xFFFF, sum = 0
6550 11:44:54.338381 12, 0xFFFF, sum = 0
6551 11:44:54.338945 13, 0x0, sum = 1
6552 11:44:54.341211 14, 0x0, sum = 2
6553 11:44:54.341639 15, 0x0, sum = 3
6554 11:44:54.344540 16, 0x0, sum = 4
6555 11:44:54.345333 best_step = 14
6556 11:44:54.345734
6557 11:44:54.346051 ==
6558 11:44:54.347877 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 11:44:54.351131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 11:44:54.351605 ==
6561 11:44:54.354482 RX Vref Scan: 0
6562 11:44:54.354904
6563 11:44:54.357846 RX Vref 0 -> 0, step: 1
6564 11:44:54.358272
6565 11:44:54.358608 RX Delay -343 -> 252, step: 8
6566 11:44:54.367019 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6567 11:44:54.370402 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6568 11:44:54.373923 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6569 11:44:54.376898 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6570 11:44:54.383638 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6571 11:44:54.386728 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6572 11:44:54.390404 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6573 11:44:54.393436 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6574 11:44:54.400131 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6575 11:44:54.403282 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6576 11:44:54.406983 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6577 11:44:54.410076 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6578 11:44:54.416798 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6579 11:44:54.420360 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6580 11:44:54.423534 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6581 11:44:54.430199 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6582 11:44:54.430760 ==
6583 11:44:54.433268 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 11:44:54.436813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 11:44:54.437242 ==
6586 11:44:54.437581 DQS Delay:
6587 11:44:54.439843 DQS0 = 48, DQS1 = 60
6588 11:44:54.440272 DQM Delay:
6589 11:44:54.443168 DQM0 = 13, DQM1 = 13
6590 11:44:54.443647 DQ Delay:
6591 11:44:54.446332 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6592 11:44:54.449733 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6593 11:44:54.453008 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6594 11:44:54.456458 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6595 11:44:54.456886
6596 11:44:54.457225
6597 11:44:54.463064 [DQSOSCAuto] RK1, (LSB)MR18= 0x9265, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6598 11:44:54.466652 CH0 RK1: MR19=C0C, MR18=9265
6599 11:44:54.472958 CH0_RK1: MR19=0xC0C, MR18=0x9265, DQSOSC=391, MR23=63, INC=386, DEC=257
6600 11:44:54.476462 [RxdqsGatingPostProcess] freq 400
6601 11:44:54.482912 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6602 11:44:54.483344 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 11:44:54.486616 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 11:44:54.489781 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 11:44:54.492824 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 11:44:54.496348 best DQS0 dly(2T, 0.5T) = (0, 10)
6607 11:44:54.499279 best DQS1 dly(2T, 0.5T) = (0, 10)
6608 11:44:54.503106 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6609 11:44:54.506243 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6610 11:44:54.509631 Pre-setting of DQS Precalculation
6611 11:44:54.516029 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6612 11:44:54.516489 ==
6613 11:44:54.519704 Dram Type= 6, Freq= 0, CH_1, rank 0
6614 11:44:54.522670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 11:44:54.523152 ==
6616 11:44:54.529502 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 11:44:54.532548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6618 11:44:54.536216 [CA 0] Center 36 (8~64) winsize 57
6619 11:44:54.539775 [CA 1] Center 36 (8~64) winsize 57
6620 11:44:54.542637 [CA 2] Center 36 (8~64) winsize 57
6621 11:44:54.546245 [CA 3] Center 36 (8~64) winsize 57
6622 11:44:54.549381 [CA 4] Center 36 (8~64) winsize 57
6623 11:44:54.552414 [CA 5] Center 36 (8~64) winsize 57
6624 11:44:54.552841
6625 11:44:54.555938 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6626 11:44:54.556364
6627 11:44:54.559188 [CATrainingPosCal] consider 1 rank data
6628 11:44:54.562556 u2DelayCellTimex100 = 270/100 ps
6629 11:44:54.566049 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:44:54.569196 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:44:54.572628 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:44:54.579705 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:44:54.582459 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 11:44:54.586083 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 11:44:54.586511
6636 11:44:54.589436 CA PerBit enable=1, Macro0, CA PI delay=36
6637 11:44:54.589872
6638 11:44:54.592589 [CBTSetCACLKResult] CA Dly = 36
6639 11:44:54.593019 CS Dly: 1 (0~32)
6640 11:44:54.593362 ==
6641 11:44:54.595555 Dram Type= 6, Freq= 0, CH_1, rank 1
6642 11:44:54.602773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 11:44:54.603263 ==
6644 11:44:54.605736 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 11:44:54.612496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6646 11:44:54.615440 [CA 0] Center 36 (8~64) winsize 57
6647 11:44:54.618503 [CA 1] Center 36 (8~64) winsize 57
6648 11:44:54.622103 [CA 2] Center 36 (8~64) winsize 57
6649 11:44:54.625248 [CA 3] Center 36 (8~64) winsize 57
6650 11:44:54.628885 [CA 4] Center 36 (8~64) winsize 57
6651 11:44:54.631864 [CA 5] Center 36 (8~64) winsize 57
6652 11:44:54.631951
6653 11:44:54.635504 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6654 11:44:54.635594
6655 11:44:54.638509 [CATrainingPosCal] consider 2 rank data
6656 11:44:54.641548 u2DelayCellTimex100 = 270/100 ps
6657 11:44:54.645241 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 11:44:54.648517 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 11:44:54.651515 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 11:44:54.655167 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 11:44:54.658226 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 11:44:54.665127 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 11:44:54.665231
6664 11:44:54.668518 CA PerBit enable=1, Macro0, CA PI delay=36
6665 11:44:54.668601
6666 11:44:54.671440 [CBTSetCACLKResult] CA Dly = 36
6667 11:44:54.671523 CS Dly: 1 (0~32)
6668 11:44:54.671588
6669 11:44:54.674824 ----->DramcWriteLeveling(PI) begin...
6670 11:44:54.674908 ==
6671 11:44:54.678016 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 11:44:54.681462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 11:44:54.684921 ==
6674 11:44:54.685006 Write leveling (Byte 0): 40 => 8
6675 11:44:54.688291 Write leveling (Byte 1): 40 => 8
6676 11:44:54.691770 DramcWriteLeveling(PI) end<-----
6677 11:44:54.691852
6678 11:44:54.691923 ==
6679 11:44:54.694951 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 11:44:54.701652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 11:44:54.701761 ==
6682 11:44:54.701830 [Gating] SW mode calibration
6683 11:44:54.711316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6684 11:44:54.714434 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6685 11:44:54.721115 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6686 11:44:54.724798 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6687 11:44:54.727919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 11:44:54.734605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 11:44:54.737764 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 11:44:54.741502 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 11:44:54.744535 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 11:44:54.751396 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 11:44:54.754409 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 11:44:54.757980 Total UI for P1: 0, mck2ui 16
6695 11:44:54.761168 best dqsien dly found for B0: ( 0, 14, 24)
6696 11:44:54.764877 Total UI for P1: 0, mck2ui 16
6697 11:44:54.767587 best dqsien dly found for B1: ( 0, 14, 24)
6698 11:44:54.770970 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6699 11:44:54.774457 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6700 11:44:54.774542
6701 11:44:54.777920 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 11:44:54.784297 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 11:44:54.784383 [Gating] SW calibration Done
6704 11:44:54.784450 ==
6705 11:44:54.787804 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 11:44:54.794137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 11:44:54.794239 ==
6708 11:44:54.794308 RX Vref Scan: 0
6709 11:44:54.794370
6710 11:44:54.797657 RX Vref 0 -> 0, step: 1
6711 11:44:54.797742
6712 11:44:54.801170 RX Delay -410 -> 252, step: 16
6713 11:44:54.804538 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6714 11:44:54.807618 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6715 11:44:54.814377 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6716 11:44:54.817493 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6717 11:44:54.821112 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6718 11:44:54.824152 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6719 11:44:54.830860 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6720 11:44:54.833944 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6721 11:44:54.837596 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6722 11:44:54.840643 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6723 11:44:54.847436 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6724 11:44:54.850991 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6725 11:44:54.854478 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6726 11:44:54.857478 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6727 11:44:54.864186 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6728 11:44:54.867234 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6729 11:44:54.867319 ==
6730 11:44:54.870867 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 11:44:54.874208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 11:44:54.874297 ==
6733 11:44:54.877484 DQS Delay:
6734 11:44:54.877571 DQS0 = 51, DQS1 = 59
6735 11:44:54.880919 DQM Delay:
6736 11:44:54.881005 DQM0 = 19, DQM1 = 16
6737 11:44:54.881090 DQ Delay:
6738 11:44:54.884299 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6739 11:44:54.887745 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6740 11:44:54.890592 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6741 11:44:54.894344 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6742 11:44:54.894447
6743 11:44:54.894540
6744 11:44:54.894636 ==
6745 11:44:54.897445 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 11:44:54.904320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 11:44:54.904403 ==
6748 11:44:54.904469
6749 11:44:54.904538
6750 11:44:54.904598 TX Vref Scan disable
6751 11:44:54.907184 == TX Byte 0 ==
6752 11:44:54.910690 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 11:44:54.914188 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 11:44:54.917330 == TX Byte 1 ==
6755 11:44:54.920829 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 11:44:54.923856 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 11:44:54.923932 ==
6758 11:44:54.926939 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 11:44:54.933681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 11:44:54.933758 ==
6761 11:44:54.933822
6762 11:44:54.933880
6763 11:44:54.933945 TX Vref Scan disable
6764 11:44:54.937440 == TX Byte 0 ==
6765 11:44:54.940684 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 11:44:54.943710 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 11:44:54.947426 == TX Byte 1 ==
6768 11:44:54.950440 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 11:44:54.953562 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 11:44:54.953634
6771 11:44:54.957076 [DATLAT]
6772 11:44:54.957162 Freq=400, CH1 RK0
6773 11:44:54.957233
6774 11:44:54.960566 DATLAT Default: 0xf
6775 11:44:54.960641 0, 0xFFFF, sum = 0
6776 11:44:54.963518 1, 0xFFFF, sum = 0
6777 11:44:54.963593 2, 0xFFFF, sum = 0
6778 11:44:54.967233 3, 0xFFFF, sum = 0
6779 11:44:54.967331 4, 0xFFFF, sum = 0
6780 11:44:54.970317 5, 0xFFFF, sum = 0
6781 11:44:54.970388 6, 0xFFFF, sum = 0
6782 11:44:54.973409 7, 0xFFFF, sum = 0
6783 11:44:54.973482 8, 0xFFFF, sum = 0
6784 11:44:54.977002 9, 0xFFFF, sum = 0
6785 11:44:54.980446 10, 0xFFFF, sum = 0
6786 11:44:54.980550 11, 0xFFFF, sum = 0
6787 11:44:54.983409 12, 0xFFFF, sum = 0
6788 11:44:54.983499 13, 0x0, sum = 1
6789 11:44:54.987275 14, 0x0, sum = 2
6790 11:44:54.987435 15, 0x0, sum = 3
6791 11:44:54.990273 16, 0x0, sum = 4
6792 11:44:54.990385 best_step = 14
6793 11:44:54.990483
6794 11:44:54.990571 ==
6795 11:44:54.993549 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 11:44:54.996958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 11:44:54.997059 ==
6798 11:44:55.000582 RX Vref Scan: 1
6799 11:44:55.000741
6800 11:44:55.000850 RX Vref 0 -> 0, step: 1
6801 11:44:55.003483
6802 11:44:55.003561 RX Delay -359 -> 252, step: 8
6803 11:44:55.003623
6804 11:44:55.006764 Set Vref, RX VrefLevel [Byte0]: 59
6805 11:44:55.010311 [Byte1]: 54
6806 11:44:55.015501
6807 11:44:55.015618 Final RX Vref Byte 0 = 59 to rank0
6808 11:44:55.018838 Final RX Vref Byte 1 = 54 to rank0
6809 11:44:55.022009 Final RX Vref Byte 0 = 59 to rank1
6810 11:44:55.025599 Final RX Vref Byte 1 = 54 to rank1==
6811 11:44:55.028680 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 11:44:55.035448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 11:44:55.035593 ==
6814 11:44:55.035730 DQS Delay:
6815 11:44:55.038474 DQS0 = 48, DQS1 = 60
6816 11:44:55.038575 DQM Delay:
6817 11:44:55.038665 DQM0 = 12, DQM1 = 13
6818 11:44:55.042037 DQ Delay:
6819 11:44:55.045109 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6820 11:44:55.045185 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6821 11:44:55.048722 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6822 11:44:55.051873 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6823 11:44:55.055571
6824 11:44:55.055644
6825 11:44:55.061995 [DQSOSCAuto] RK0, (LSB)MR18= 0x8229, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6826 11:44:55.065611 CH1 RK0: MR19=C0C, MR18=8229
6827 11:44:55.071675 CH1_RK0: MR19=0xC0C, MR18=0x8229, DQSOSC=393, MR23=63, INC=382, DEC=254
6828 11:44:55.071759 ==
6829 11:44:55.075314 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 11:44:55.078410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 11:44:55.078511 ==
6832 11:44:55.081538 [Gating] SW mode calibration
6833 11:44:55.088323 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6834 11:44:55.095500 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6835 11:44:55.098287 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 11:44:55.101688 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6837 11:44:55.108442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 11:44:55.111819 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 11:44:55.115267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 11:44:55.121600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 11:44:55.125005 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 11:44:55.128562 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 11:44:55.135339 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 11:44:55.135478 Total UI for P1: 0, mck2ui 16
6845 11:44:55.138468 best dqsien dly found for B0: ( 0, 14, 24)
6846 11:44:55.141561 Total UI for P1: 0, mck2ui 16
6847 11:44:55.145196 best dqsien dly found for B1: ( 0, 14, 24)
6848 11:44:55.148179 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6849 11:44:55.154919 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6850 11:44:55.155005
6851 11:44:55.158639 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 11:44:55.161651 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 11:44:55.164673 [Gating] SW calibration Done
6854 11:44:55.164757 ==
6855 11:44:55.168185 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 11:44:55.171868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 11:44:55.171972 ==
6858 11:44:55.174887 RX Vref Scan: 0
6859 11:44:55.174987
6860 11:44:55.175076 RX Vref 0 -> 0, step: 1
6861 11:44:55.175162
6862 11:44:55.178018 RX Delay -410 -> 252, step: 16
6863 11:44:55.181660 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6864 11:44:55.188223 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6865 11:44:55.191200 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6866 11:44:55.194659 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6867 11:44:55.197777 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6868 11:44:55.205025 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6869 11:44:55.207835 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6870 11:44:55.211453 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6871 11:44:55.214959 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6872 11:44:55.221375 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6873 11:44:55.224794 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6874 11:44:55.228177 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6875 11:44:55.231616 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6876 11:44:55.238302 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6877 11:44:55.241437 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6878 11:44:55.244465 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6879 11:44:55.244549 ==
6880 11:44:55.248181 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 11:44:55.254309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 11:44:55.254395 ==
6883 11:44:55.254462 DQS Delay:
6884 11:44:55.257912 DQS0 = 43, DQS1 = 59
6885 11:44:55.257994 DQM Delay:
6886 11:44:55.258060 DQM0 = 9, DQM1 = 20
6887 11:44:55.261041 DQ Delay:
6888 11:44:55.264623 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6889 11:44:55.264706 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6890 11:44:55.267667 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6891 11:44:55.271068 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6892 11:44:55.271150
6893 11:44:55.274727
6894 11:44:55.274809 ==
6895 11:44:55.277731 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 11:44:55.281428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 11:44:55.281537 ==
6898 11:44:55.281630
6899 11:44:55.281718
6900 11:44:55.284787 TX Vref Scan disable
6901 11:44:55.284870 == TX Byte 0 ==
6902 11:44:55.287542 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6903 11:44:55.294721 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6904 11:44:55.294805 == TX Byte 1 ==
6905 11:44:55.297637 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6906 11:44:55.304572 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6907 11:44:55.304656 ==
6908 11:44:55.307517 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 11:44:55.311052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 11:44:55.311153 ==
6911 11:44:55.311279
6912 11:44:55.311393
6913 11:44:55.314139 TX Vref Scan disable
6914 11:44:55.314234 == TX Byte 0 ==
6915 11:44:55.317608 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6916 11:44:55.324186 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6917 11:44:55.324273 == TX Byte 1 ==
6918 11:44:55.327902 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6919 11:44:55.334151 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6920 11:44:55.334236
6921 11:44:55.334302 [DATLAT]
6922 11:44:55.334363 Freq=400, CH1 RK1
6923 11:44:55.334422
6924 11:44:55.337701 DATLAT Default: 0xe
6925 11:44:55.340784 0, 0xFFFF, sum = 0
6926 11:44:55.340868 1, 0xFFFF, sum = 0
6927 11:44:55.343833 2, 0xFFFF, sum = 0
6928 11:44:55.343917 3, 0xFFFF, sum = 0
6929 11:44:55.347466 4, 0xFFFF, sum = 0
6930 11:44:55.347550 5, 0xFFFF, sum = 0
6931 11:44:55.351037 6, 0xFFFF, sum = 0
6932 11:44:55.351123 7, 0xFFFF, sum = 0
6933 11:44:55.354183 8, 0xFFFF, sum = 0
6934 11:44:55.354268 9, 0xFFFF, sum = 0
6935 11:44:55.357179 10, 0xFFFF, sum = 0
6936 11:44:55.357265 11, 0xFFFF, sum = 0
6937 11:44:55.360872 12, 0xFFFF, sum = 0
6938 11:44:55.360956 13, 0x0, sum = 1
6939 11:44:55.363930 14, 0x0, sum = 2
6940 11:44:55.364014 15, 0x0, sum = 3
6941 11:44:55.367506 16, 0x0, sum = 4
6942 11:44:55.367637 best_step = 14
6943 11:44:55.367704
6944 11:44:55.367805 ==
6945 11:44:55.370586 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 11:44:55.374170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 11:44:55.377140 ==
6948 11:44:55.377264 RX Vref Scan: 0
6949 11:44:55.377386
6950 11:44:55.380850 RX Vref 0 -> 0, step: 1
6951 11:44:55.380958
6952 11:44:55.383764 RX Delay -359 -> 252, step: 8
6953 11:44:55.390531 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6954 11:44:55.393975 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6955 11:44:55.396982 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6956 11:44:55.400498 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6957 11:44:55.406828 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6958 11:44:55.410344 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6959 11:44:55.413797 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6960 11:44:55.416719 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6961 11:44:55.423983 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6962 11:44:55.426834 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6963 11:44:55.430105 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6964 11:44:55.433605 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6965 11:44:55.440080 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6966 11:44:55.443680 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6967 11:44:55.446823 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6968 11:44:55.449862 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6969 11:44:55.453545 ==
6970 11:44:55.456683 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 11:44:55.460376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 11:44:55.460461 ==
6973 11:44:55.460527 DQS Delay:
6974 11:44:55.463346 DQS0 = 52, DQS1 = 56
6975 11:44:55.463467 DQM Delay:
6976 11:44:55.467062 DQM0 = 14, DQM1 = 9
6977 11:44:55.467145 DQ Delay:
6978 11:44:55.469972 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6979 11:44:55.473688 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6980 11:44:55.476675 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6981 11:44:55.480162 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6982 11:44:55.480246
6983 11:44:55.480310
6984 11:44:55.486379 [DQSOSCAuto] RK1, (LSB)MR18= 0x7b90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6985 11:44:55.490084 CH1 RK1: MR19=C0C, MR18=7B90
6986 11:44:55.496778 CH1_RK1: MR19=0xC0C, MR18=0x7B90, DQSOSC=391, MR23=63, INC=386, DEC=257
6987 11:44:55.499847 [RxdqsGatingPostProcess] freq 400
6988 11:44:55.503279 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6989 11:44:55.506178 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 11:44:55.509569 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 11:44:55.513069 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 11:44:55.516415 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 11:44:55.520030 best DQS0 dly(2T, 0.5T) = (0, 10)
6994 11:44:55.522994 best DQS1 dly(2T, 0.5T) = (0, 10)
6995 11:44:55.526493 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6996 11:44:55.529419 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6997 11:44:55.533025 Pre-setting of DQS Precalculation
6998 11:44:55.536682 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6999 11:44:55.545980 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7000 11:44:55.553316 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7001 11:44:55.553404
7002 11:44:55.553491
7003 11:44:55.556470 [Calibration Summary] 800 Mbps
7004 11:44:55.556558 CH 0, Rank 0
7005 11:44:55.559460 SW Impedance : PASS
7006 11:44:55.559547 DUTY Scan : NO K
7007 11:44:55.563060 ZQ Calibration : PASS
7008 11:44:55.566120 Jitter Meter : NO K
7009 11:44:55.566207 CBT Training : PASS
7010 11:44:55.569856 Write leveling : PASS
7011 11:44:55.572923 RX DQS gating : PASS
7012 11:44:55.573010 RX DQ/DQS(RDDQC) : PASS
7013 11:44:55.576027 TX DQ/DQS : PASS
7014 11:44:55.579767 RX DATLAT : PASS
7015 11:44:55.579853 RX DQ/DQS(Engine): PASS
7016 11:44:55.582568 TX OE : NO K
7017 11:44:55.582655 All Pass.
7018 11:44:55.582742
7019 11:44:55.586161 CH 0, Rank 1
7020 11:44:55.586247 SW Impedance : PASS
7021 11:44:55.589269 DUTY Scan : NO K
7022 11:44:55.592660 ZQ Calibration : PASS
7023 11:44:55.592746 Jitter Meter : NO K
7024 11:44:55.596172 CBT Training : PASS
7025 11:44:55.596258 Write leveling : NO K
7026 11:44:55.599796 RX DQS gating : PASS
7027 11:44:55.602855 RX DQ/DQS(RDDQC) : PASS
7028 11:44:55.602941 TX DQ/DQS : PASS
7029 11:44:55.605857 RX DATLAT : PASS
7030 11:44:55.609343 RX DQ/DQS(Engine): PASS
7031 11:44:55.609429 TX OE : NO K
7032 11:44:55.612764 All Pass.
7033 11:44:55.612850
7034 11:44:55.612936 CH 1, Rank 0
7035 11:44:55.616168 SW Impedance : PASS
7036 11:44:55.616255 DUTY Scan : NO K
7037 11:44:55.619085 ZQ Calibration : PASS
7038 11:44:55.622628 Jitter Meter : NO K
7039 11:44:55.622713 CBT Training : PASS
7040 11:44:55.625587 Write leveling : PASS
7041 11:44:55.629240 RX DQS gating : PASS
7042 11:44:55.629349 RX DQ/DQS(RDDQC) : PASS
7043 11:44:55.632752 TX DQ/DQS : PASS
7044 11:44:55.635609 RX DATLAT : PASS
7045 11:44:55.635694 RX DQ/DQS(Engine): PASS
7046 11:44:55.639256 TX OE : NO K
7047 11:44:55.639405 All Pass.
7048 11:44:55.639521
7049 11:44:55.642523 CH 1, Rank 1
7050 11:44:55.642637 SW Impedance : PASS
7051 11:44:55.645843 DUTY Scan : NO K
7052 11:44:55.649188 ZQ Calibration : PASS
7053 11:44:55.649289 Jitter Meter : NO K
7054 11:44:55.652282 CBT Training : PASS
7055 11:44:55.655292 Write leveling : NO K
7056 11:44:55.655420 RX DQS gating : PASS
7057 11:44:55.659127 RX DQ/DQS(RDDQC) : PASS
7058 11:44:55.659211 TX DQ/DQS : PASS
7059 11:44:55.661996 RX DATLAT : PASS
7060 11:44:55.665634 RX DQ/DQS(Engine): PASS
7061 11:44:55.665718 TX OE : NO K
7062 11:44:55.668702 All Pass.
7063 11:44:55.668786
7064 11:44:55.668852 DramC Write-DBI off
7065 11:44:55.672430 PER_BANK_REFRESH: Hybrid Mode
7066 11:44:55.675512 TX_TRACKING: ON
7067 11:44:55.682230 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7068 11:44:55.685325 [FAST_K] Save calibration result to emmc
7069 11:44:55.688766 dramc_set_vcore_voltage set vcore to 725000
7070 11:44:55.691837 Read voltage for 1600, 0
7071 11:44:55.691936 Vio18 = 0
7072 11:44:55.695400 Vcore = 725000
7073 11:44:55.695484 Vdram = 0
7074 11:44:55.695550 Vddq = 0
7075 11:44:55.698877 Vmddr = 0
7076 11:44:55.702297 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7077 11:44:55.708437 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7078 11:44:55.708522 MEM_TYPE=3, freq_sel=13
7079 11:44:55.711937 sv_algorithm_assistance_LP4_3733
7080 11:44:55.718615 ============ PULL DRAM RESETB DOWN ============
7081 11:44:55.722189 ========== PULL DRAM RESETB DOWN end =========
7082 11:44:55.725010 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7083 11:44:55.728583 ===================================
7084 11:44:55.731588 LPDDR4 DRAM CONFIGURATION
7085 11:44:55.735115 ===================================
7086 11:44:55.738462 EX_ROW_EN[0] = 0x0
7087 11:44:55.738546 EX_ROW_EN[1] = 0x0
7088 11:44:55.741949 LP4Y_EN = 0x0
7089 11:44:55.742027 WORK_FSP = 0x1
7090 11:44:55.745050 WL = 0x5
7091 11:44:55.745129 RL = 0x5
7092 11:44:55.748704 BL = 0x2
7093 11:44:55.748777 RPST = 0x0
7094 11:44:55.751539 RD_PRE = 0x0
7095 11:44:55.751627 WR_PRE = 0x1
7096 11:44:55.755163 WR_PST = 0x1
7097 11:44:55.755276 DBI_WR = 0x0
7098 11:44:55.758222 DBI_RD = 0x0
7099 11:44:55.758300 OTF = 0x1
7100 11:44:55.761277 ===================================
7101 11:44:55.764934 ===================================
7102 11:44:55.768555 ANA top config
7103 11:44:55.771584 ===================================
7104 11:44:55.774694 DLL_ASYNC_EN = 0
7105 11:44:55.774799 ALL_SLAVE_EN = 0
7106 11:44:55.778424 NEW_RANK_MODE = 1
7107 11:44:55.781516 DLL_IDLE_MODE = 1
7108 11:44:55.784559 LP45_APHY_COMB_EN = 1
7109 11:44:55.784636 TX_ODT_DIS = 0
7110 11:44:55.788117 NEW_8X_MODE = 1
7111 11:44:55.791597 ===================================
7112 11:44:55.794751 ===================================
7113 11:44:55.797857 data_rate = 3200
7114 11:44:55.801428 CKR = 1
7115 11:44:55.804640 DQ_P2S_RATIO = 8
7116 11:44:55.807847 ===================================
7117 11:44:55.810946 CA_P2S_RATIO = 8
7118 11:44:55.814563 DQ_CA_OPEN = 0
7119 11:44:55.814638 DQ_SEMI_OPEN = 0
7120 11:44:55.818013 CA_SEMI_OPEN = 0
7121 11:44:55.821487 CA_FULL_RATE = 0
7122 11:44:55.824810 DQ_CKDIV4_EN = 0
7123 11:44:55.827661 CA_CKDIV4_EN = 0
7124 11:44:55.827777 CA_PREDIV_EN = 0
7125 11:44:55.831232 PH8_DLY = 12
7126 11:44:55.834698 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7127 11:44:55.837719 DQ_AAMCK_DIV = 4
7128 11:44:55.841087 CA_AAMCK_DIV = 4
7129 11:44:55.844289 CA_ADMCK_DIV = 4
7130 11:44:55.844380 DQ_TRACK_CA_EN = 0
7131 11:44:55.847730 CA_PICK = 1600
7132 11:44:55.851273 CA_MCKIO = 1600
7133 11:44:55.854845 MCKIO_SEMI = 0
7134 11:44:55.857612 PLL_FREQ = 3068
7135 11:44:55.861379 DQ_UI_PI_RATIO = 32
7136 11:44:55.864401 CA_UI_PI_RATIO = 0
7137 11:44:55.867465 ===================================
7138 11:44:55.871049 ===================================
7139 11:44:55.871132 memory_type:LPDDR4
7140 11:44:55.874164 GP_NUM : 10
7141 11:44:55.877891 SRAM_EN : 1
7142 11:44:55.877974 MD32_EN : 0
7143 11:44:55.880968 ===================================
7144 11:44:55.883991 [ANA_INIT] >>>>>>>>>>>>>>
7145 11:44:55.887673 <<<<<< [CONFIGURE PHASE]: ANA_TX
7146 11:44:55.890747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7147 11:44:55.894347 ===================================
7148 11:44:55.897203 data_rate = 3200,PCW = 0X7600
7149 11:44:55.900927 ===================================
7150 11:44:55.903745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7151 11:44:55.907103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 11:44:55.914163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 11:44:55.917249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7154 11:44:55.923890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7155 11:44:55.927344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7156 11:44:55.927470 [ANA_INIT] flow start
7157 11:44:55.930269 [ANA_INIT] PLL >>>>>>>>
7158 11:44:55.933666 [ANA_INIT] PLL <<<<<<<<
7159 11:44:55.933778 [ANA_INIT] MIDPI >>>>>>>>
7160 11:44:55.937214 [ANA_INIT] MIDPI <<<<<<<<
7161 11:44:55.940261 [ANA_INIT] DLL >>>>>>>>
7162 11:44:55.940344 [ANA_INIT] DLL <<<<<<<<
7163 11:44:55.943713 [ANA_INIT] flow end
7164 11:44:55.947263 ============ LP4 DIFF to SE enter ============
7165 11:44:55.950645 ============ LP4 DIFF to SE exit ============
7166 11:44:55.953789 [ANA_INIT] <<<<<<<<<<<<<
7167 11:44:55.957294 [Flow] Enable top DCM control >>>>>
7168 11:44:55.960377 [Flow] Enable top DCM control <<<<<
7169 11:44:55.963972 Enable DLL master slave shuffle
7170 11:44:55.970799 ==============================================================
7171 11:44:55.970883 Gating Mode config
7172 11:44:55.976974 ==============================================================
7173 11:44:55.977058 Config description:
7174 11:44:55.987391 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7175 11:44:55.994182 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7176 11:44:56.000218 SELPH_MODE 0: By rank 1: By Phase
7177 11:44:56.003867 ==============================================================
7178 11:44:56.007265 GAT_TRACK_EN = 1
7179 11:44:56.010397 RX_GATING_MODE = 2
7180 11:44:56.014134 RX_GATING_TRACK_MODE = 2
7181 11:44:56.017111 SELPH_MODE = 1
7182 11:44:56.020635 PICG_EARLY_EN = 1
7183 11:44:56.023582 VALID_LAT_VALUE = 1
7184 11:44:56.027024 ==============================================================
7185 11:44:56.030143 Enter into Gating configuration >>>>
7186 11:44:56.033520 Exit from Gating configuration <<<<
7187 11:44:56.036979 Enter into DVFS_PRE_config >>>>>
7188 11:44:56.050435 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7189 11:44:56.053967 Exit from DVFS_PRE_config <<<<<
7190 11:44:56.056815 Enter into PICG configuration >>>>
7191 11:44:56.060479 Exit from PICG configuration <<<<
7192 11:44:56.060563 [RX_INPUT] configuration >>>>>
7193 11:44:56.063318 [RX_INPUT] configuration <<<<<
7194 11:44:56.069955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7195 11:44:56.073593 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7196 11:44:56.080248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 11:44:56.087214 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 11:44:56.093656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7199 11:44:56.100368 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7200 11:44:56.103219 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7201 11:44:56.106703 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7202 11:44:56.113525 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7203 11:44:56.116549 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7204 11:44:56.120138 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7205 11:44:56.123136 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 11:44:56.126981 ===================================
7207 11:44:56.130124 LPDDR4 DRAM CONFIGURATION
7208 11:44:56.133040 ===================================
7209 11:44:56.136344 EX_ROW_EN[0] = 0x0
7210 11:44:56.136428 EX_ROW_EN[1] = 0x0
7211 11:44:56.139812 LP4Y_EN = 0x0
7212 11:44:56.139895 WORK_FSP = 0x1
7213 11:44:56.143180 WL = 0x5
7214 11:44:56.143287 RL = 0x5
7215 11:44:56.146635 BL = 0x2
7216 11:44:56.146720 RPST = 0x0
7217 11:44:56.149827 RD_PRE = 0x0
7218 11:44:56.149949 WR_PRE = 0x1
7219 11:44:56.153412 WR_PST = 0x1
7220 11:44:56.153513 DBI_WR = 0x0
7221 11:44:56.156834 DBI_RD = 0x0
7222 11:44:56.156947 OTF = 0x1
7223 11:44:56.160262 ===================================
7224 11:44:56.166840 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7225 11:44:56.169681 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7226 11:44:56.173372 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 11:44:56.176372 ===================================
7228 11:44:56.180073 LPDDR4 DRAM CONFIGURATION
7229 11:44:56.183135 ===================================
7230 11:44:56.186351 EX_ROW_EN[0] = 0x10
7231 11:44:56.186434 EX_ROW_EN[1] = 0x0
7232 11:44:56.189886 LP4Y_EN = 0x0
7233 11:44:56.189999 WORK_FSP = 0x1
7234 11:44:56.193015 WL = 0x5
7235 11:44:56.193119 RL = 0x5
7236 11:44:56.196151 BL = 0x2
7237 11:44:56.196234 RPST = 0x0
7238 11:44:56.199748 RD_PRE = 0x0
7239 11:44:56.199846 WR_PRE = 0x1
7240 11:44:56.202860 WR_PST = 0x1
7241 11:44:56.202943 DBI_WR = 0x0
7242 11:44:56.206495 DBI_RD = 0x0
7243 11:44:56.206577 OTF = 0x1
7244 11:44:56.210020 ===================================
7245 11:44:56.216484 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7246 11:44:56.216568 ==
7247 11:44:56.219586 Dram Type= 6, Freq= 0, CH_0, rank 0
7248 11:44:56.226282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7249 11:44:56.226383 ==
7250 11:44:56.226463 [Duty_Offset_Calibration]
7251 11:44:56.229324 B0:3 B1:-1 CA:1
7252 11:44:56.229407
7253 11:44:56.232881 [DutyScan_Calibration_Flow] k_type=0
7254 11:44:56.241554
7255 11:44:56.241654 ==CLK 0==
7256 11:44:56.244953 Final CLK duty delay cell = -4
7257 11:44:56.247816 [-4] MAX Duty = 5031%(X100), DQS PI = 6
7258 11:44:56.251202 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7259 11:44:56.254444 [-4] AVG Duty = 4937%(X100)
7260 11:44:56.254529
7261 11:44:56.257972 CH0 CLK Duty spec in!! Max-Min= 187%
7262 11:44:56.261330 [DutyScan_Calibration_Flow] ====Done====
7263 11:44:56.261414
7264 11:44:56.264215 [DutyScan_Calibration_Flow] k_type=1
7265 11:44:56.280787
7266 11:44:56.280875 ==DQS 0 ==
7267 11:44:56.284413 Final DQS duty delay cell = 0
7268 11:44:56.287523 [0] MAX Duty = 5124%(X100), DQS PI = 20
7269 11:44:56.290555 [0] MIN Duty = 5000%(X100), DQS PI = 14
7270 11:44:56.294346 [0] AVG Duty = 5062%(X100)
7271 11:44:56.294429
7272 11:44:56.294495 ==DQS 1 ==
7273 11:44:56.297451 Final DQS duty delay cell = -4
7274 11:44:56.301093 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7275 11:44:56.304233 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7276 11:44:56.307254 [-4] AVG Duty = 5046%(X100)
7277 11:44:56.307339
7278 11:44:56.310819 CH0 DQS 0 Duty spec in!! Max-Min= 124%
7279 11:44:56.310917
7280 11:44:56.313849 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7281 11:44:56.317273 [DutyScan_Calibration_Flow] ====Done====
7282 11:44:56.317358
7283 11:44:56.320452 [DutyScan_Calibration_Flow] k_type=3
7284 11:44:56.337950
7285 11:44:56.338064 ==DQM 0 ==
7286 11:44:56.341485 Final DQM duty delay cell = 0
7287 11:44:56.344953 [0] MAX Duty = 5000%(X100), DQS PI = 38
7288 11:44:56.348441 [0] MIN Duty = 4875%(X100), DQS PI = 6
7289 11:44:56.348578 [0] AVG Duty = 4937%(X100)
7290 11:44:56.351868
7291 11:44:56.351981 ==DQM 1 ==
7292 11:44:56.354608 Final DQM duty delay cell = 0
7293 11:44:56.358064 [0] MAX Duty = 5218%(X100), DQS PI = 58
7294 11:44:56.361525 [0] MIN Duty = 4969%(X100), DQS PI = 18
7295 11:44:56.361607 [0] AVG Duty = 5093%(X100)
7296 11:44:56.364792
7297 11:44:56.368334 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7298 11:44:56.368423
7299 11:44:56.371748 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7300 11:44:56.374748 [DutyScan_Calibration_Flow] ====Done====
7301 11:44:56.374881
7302 11:44:56.378173 [DutyScan_Calibration_Flow] k_type=2
7303 11:44:56.394443
7304 11:44:56.394574 ==DQ 0 ==
7305 11:44:56.398159 Final DQ duty delay cell = -4
7306 11:44:56.401251 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7307 11:44:56.404251 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7308 11:44:56.407926 [-4] AVG Duty = 4937%(X100)
7309 11:44:56.408007
7310 11:44:56.408070 ==DQ 1 ==
7311 11:44:56.410945 Final DQ duty delay cell = 0
7312 11:44:56.414537 [0] MAX Duty = 5031%(X100), DQS PI = 30
7313 11:44:56.417687 [0] MIN Duty = 4938%(X100), DQS PI = 2
7314 11:44:56.421202 [0] AVG Duty = 4984%(X100)
7315 11:44:56.421292
7316 11:44:56.424288 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7317 11:44:56.424376
7318 11:44:56.427980 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7319 11:44:56.430931 [DutyScan_Calibration_Flow] ====Done====
7320 11:44:56.431034 ==
7321 11:44:56.434609 Dram Type= 6, Freq= 0, CH_1, rank 0
7322 11:44:56.437640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7323 11:44:56.437752 ==
7324 11:44:56.440728 [Duty_Offset_Calibration]
7325 11:44:56.440849 B0:1 B1:1 CA:2
7326 11:44:56.440944
7327 11:44:56.444204 [DutyScan_Calibration_Flow] k_type=0
7328 11:44:56.454954
7329 11:44:56.455041 ==CLK 0==
7330 11:44:56.458664 Final CLK duty delay cell = 0
7331 11:44:56.461897 [0] MAX Duty = 5125%(X100), DQS PI = 40
7332 11:44:56.464769 [0] MIN Duty = 4938%(X100), DQS PI = 10
7333 11:44:56.464871 [0] AVG Duty = 5031%(X100)
7334 11:44:56.468308
7335 11:44:56.471601 CH1 CLK Duty spec in!! Max-Min= 187%
7336 11:44:56.475127 [DutyScan_Calibration_Flow] ====Done====
7337 11:44:56.475250
7338 11:44:56.477998 [DutyScan_Calibration_Flow] k_type=1
7339 11:44:56.495087
7340 11:44:56.495289 ==DQS 0 ==
7341 11:44:56.498192 Final DQS duty delay cell = 0
7342 11:44:56.501428 [0] MAX Duty = 5000%(X100), DQS PI = 52
7343 11:44:56.505029 [0] MIN Duty = 4875%(X100), DQS PI = 0
7344 11:44:56.508074 [0] AVG Duty = 4937%(X100)
7345 11:44:56.508372
7346 11:44:56.508607 ==DQS 1 ==
7347 11:44:56.511814 Final DQS duty delay cell = 0
7348 11:44:56.514930 [0] MAX Duty = 5093%(X100), DQS PI = 24
7349 11:44:56.518570 [0] MIN Duty = 4907%(X100), DQS PI = 62
7350 11:44:56.521563 [0] AVG Duty = 5000%(X100)
7351 11:44:56.521984
7352 11:44:56.524935 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7353 11:44:56.525357
7354 11:44:56.528148 CH1 DQS 1 Duty spec in!! Max-Min= 186%
7355 11:44:56.531699 [DutyScan_Calibration_Flow] ====Done====
7356 11:44:56.532123
7357 11:44:56.534669 [DutyScan_Calibration_Flow] k_type=3
7358 11:44:56.551741
7359 11:44:56.552203 ==DQM 0 ==
7360 11:44:56.555272 Final DQM duty delay cell = 0
7361 11:44:56.558223 [0] MAX Duty = 5124%(X100), DQS PI = 52
7362 11:44:56.561773 [0] MIN Duty = 4876%(X100), DQS PI = 18
7363 11:44:56.565051 [0] AVG Duty = 5000%(X100)
7364 11:44:56.565602
7365 11:44:56.565954 ==DQM 1 ==
7366 11:44:56.568474 Final DQM duty delay cell = 0
7367 11:44:56.572121 [0] MAX Duty = 5156%(X100), DQS PI = 24
7368 11:44:56.575596 [0] MIN Duty = 4875%(X100), DQS PI = 52
7369 11:44:56.578239 [0] AVG Duty = 5015%(X100)
7370 11:44:56.578819
7371 11:44:56.581581 CH1 DQM 0 Duty spec in!! Max-Min= 248%
7372 11:44:56.582127
7373 11:44:56.585259 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7374 11:44:56.588632 [DutyScan_Calibration_Flow] ====Done====
7375 11:44:56.589204
7376 11:44:56.591586 [DutyScan_Calibration_Flow] k_type=2
7377 11:44:56.607999
7378 11:44:56.608564 ==DQ 0 ==
7379 11:44:56.611674 Final DQ duty delay cell = 0
7380 11:44:56.614624 [0] MAX Duty = 5125%(X100), DQS PI = 52
7381 11:44:56.617740 [0] MIN Duty = 4969%(X100), DQS PI = 2
7382 11:44:56.618279 [0] AVG Duty = 5047%(X100)
7383 11:44:56.621239
7384 11:44:56.621834 ==DQ 1 ==
7385 11:44:56.624472 Final DQ duty delay cell = -4
7386 11:44:56.628283 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7387 11:44:56.631147 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7388 11:44:56.634599 [-4] AVG Duty = 4938%(X100)
7389 11:44:56.635192
7390 11:44:56.637872 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7391 11:44:56.638411
7392 11:44:56.640788 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7393 11:44:56.644370 [DutyScan_Calibration_Flow] ====Done====
7394 11:44:56.647574 nWR fixed to 30
7395 11:44:56.651216 [ModeRegInit_LP4] CH0 RK0
7396 11:44:56.651692 [ModeRegInit_LP4] CH0 RK1
7397 11:44:56.654228 [ModeRegInit_LP4] CH1 RK0
7398 11:44:56.657858 [ModeRegInit_LP4] CH1 RK1
7399 11:44:56.658291 match AC timing 5
7400 11:44:56.664394 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7401 11:44:56.667988 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7402 11:44:56.670922 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7403 11:44:56.677915 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7404 11:44:56.680849 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7405 11:44:56.681284 [MiockJmeterHQA]
7406 11:44:56.681629
7407 11:44:56.684320 [DramcMiockJmeter] u1RxGatingPI = 0
7408 11:44:56.687804 0 : 4255, 4027
7409 11:44:56.688286 4 : 4255, 4027
7410 11:44:56.691140 8 : 4252, 4027
7411 11:44:56.691599 12 : 4366, 4140
7412 11:44:56.691959 16 : 4253, 4026
7413 11:44:56.694136 20 : 4252, 4027
7414 11:44:56.694593 24 : 4252, 4027
7415 11:44:56.697608 28 : 4363, 4137
7416 11:44:56.698131 32 : 4253, 4026
7417 11:44:56.701148 36 : 4363, 4138
7418 11:44:56.701703 40 : 4252, 4027
7419 11:44:56.704320 44 : 4252, 4027
7420 11:44:56.704726 48 : 4253, 4027
7421 11:44:56.705058 52 : 4255, 4029
7422 11:44:56.707225 56 : 4363, 4137
7423 11:44:56.707675 60 : 4250, 4027
7424 11:44:56.711081 64 : 4360, 4137
7425 11:44:56.711622 68 : 4250, 4027
7426 11:44:56.714144 72 : 4250, 4027
7427 11:44:56.714526 76 : 4250, 4026
7428 11:44:56.717346 80 : 4361, 4137
7429 11:44:56.717870 84 : 4250, 4027
7430 11:44:56.718330 88 : 4361, 4137
7431 11:44:56.721018 92 : 4250, 4027
7432 11:44:56.721731 96 : 4250, 3364
7433 11:44:56.724051 100 : 4250, 0
7434 11:44:56.724500 104 : 4250, 0
7435 11:44:56.727159 108 : 4363, 0
7436 11:44:56.727682 112 : 4253, 0
7437 11:44:56.728055 116 : 4250, 0
7438 11:44:56.730790 120 : 4250, 0
7439 11:44:56.731196 124 : 4253, 0
7440 11:44:56.731648 128 : 4361, 0
7441 11:44:56.733676 132 : 4360, 0
7442 11:44:56.734068 136 : 4250, 0
7443 11:44:56.737308 140 : 4360, 0
7444 11:44:56.737711 144 : 4361, 0
7445 11:44:56.738066 148 : 4250, 0
7446 11:44:56.740342 152 : 4250, 0
7447 11:44:56.740772 156 : 4250, 0
7448 11:44:56.743461 160 : 4250, 0
7449 11:44:56.743861 164 : 4361, 0
7450 11:44:56.744215 168 : 4250, 0
7451 11:44:56.747067 172 : 4250, 0
7452 11:44:56.747500 176 : 4250, 0
7453 11:44:56.750222 180 : 4250, 0
7454 11:44:56.750755 184 : 4250, 0
7455 11:44:56.751137 188 : 4250, 0
7456 11:44:56.753601 192 : 4360, 0
7457 11:44:56.754082 196 : 4250, 0
7458 11:44:56.754437 200 : 4250, 0
7459 11:44:56.756973 204 : 4250, 0
7460 11:44:56.757379 208 : 4250, 0
7461 11:44:56.760229 212 : 4250, 59
7462 11:44:56.760617 216 : 4250, 3761
7463 11:44:56.763690 220 : 4365, 4140
7464 11:44:56.764074 224 : 4250, 4027
7465 11:44:56.767176 228 : 4250, 4027
7466 11:44:56.767653 232 : 4360, 4138
7467 11:44:56.768001 236 : 4361, 4137
7468 11:44:56.770165 240 : 4250, 4026
7469 11:44:56.770600 244 : 4363, 4139
7470 11:44:56.773473 248 : 4250, 4027
7471 11:44:56.773906 252 : 4253, 4027
7472 11:44:56.776975 256 : 4250, 4027
7473 11:44:56.777486 260 : 4253, 4029
7474 11:44:56.780003 264 : 4250, 4027
7475 11:44:56.780438 268 : 4250, 4027
7476 11:44:56.783438 272 : 4250, 4027
7477 11:44:56.784010 276 : 4253, 4029
7478 11:44:56.786939 280 : 4250, 4027
7479 11:44:56.787415 284 : 4360, 4138
7480 11:44:56.789778 288 : 4361, 4137
7481 11:44:56.790210 292 : 4250, 4027
7482 11:44:56.793234 296 : 4363, 4139
7483 11:44:56.793714 300 : 4250, 4027
7484 11:44:56.794059 304 : 4250, 4027
7485 11:44:56.796808 308 : 4250, 4027
7486 11:44:56.797241 312 : 4253, 4029
7487 11:44:56.800117 316 : 4250, 4027
7488 11:44:56.800908 320 : 4250, 4027
7489 11:44:56.803756 324 : 4250, 4026
7490 11:44:56.804352 328 : 4253, 4029
7491 11:44:56.806649 332 : 4250, 2799
7492 11:44:56.807229 336 : 4360, 23
7493 11:44:56.807788
7494 11:44:56.809745 MIOCK jitter meter ch=0
7495 11:44:56.810263
7496 11:44:56.813394 1T = (336-100) = 236 dly cells
7497 11:44:56.816573 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7498 11:44:56.819642 ==
7499 11:44:56.823318 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 11:44:56.826524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 11:44:56.827195 ==
7502 11:44:56.829725 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 11:44:56.836307 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 11:44:56.839826 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 11:44:56.846332 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 11:44:56.854967 [CA 0] Center 44 (14~75) winsize 62
7507 11:44:56.858083 [CA 1] Center 44 (14~74) winsize 61
7508 11:44:56.861174 [CA 2] Center 39 (10~68) winsize 59
7509 11:44:56.864848 [CA 3] Center 39 (10~68) winsize 59
7510 11:44:56.867818 [CA 4] Center 37 (8~67) winsize 60
7511 11:44:56.871187 [CA 5] Center 37 (7~67) winsize 61
7512 11:44:56.871770
7513 11:44:56.874628 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 11:44:56.875145
7515 11:44:56.880915 [CATrainingPosCal] consider 1 rank data
7516 11:44:56.881370 u2DelayCellTimex100 = 275/100 ps
7517 11:44:56.888138 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7518 11:44:56.890804 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7519 11:44:56.894105 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7520 11:44:56.897765 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7521 11:44:56.900666 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7522 11:44:56.904241 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7523 11:44:56.904838
7524 11:44:56.907727 CA PerBit enable=1, Macro0, CA PI delay=37
7525 11:44:56.908207
7526 11:44:56.911116 [CBTSetCACLKResult] CA Dly = 37
7527 11:44:56.914099 CS Dly: 10 (0~41)
7528 11:44:56.917907 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 11:44:56.920917 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 11:44:56.921315 ==
7531 11:44:56.924667 Dram Type= 6, Freq= 0, CH_0, rank 1
7532 11:44:56.930806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 11:44:56.931279 ==
7534 11:44:56.934017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 11:44:56.940629 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 11:44:56.944127 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 11:44:56.950710 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 11:44:56.958849 [CA 0] Center 44 (14~75) winsize 62
7539 11:44:56.961850 [CA 1] Center 44 (14~75) winsize 62
7540 11:44:56.965539 [CA 2] Center 40 (11~69) winsize 59
7541 11:44:56.968700 [CA 3] Center 39 (10~69) winsize 60
7542 11:44:56.972043 [CA 4] Center 38 (8~68) winsize 61
7543 11:44:56.975174 [CA 5] Center 37 (7~67) winsize 61
7544 11:44:56.975615
7545 11:44:56.978869 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 11:44:56.979290
7547 11:44:56.981677 [CATrainingPosCal] consider 2 rank data
7548 11:44:56.985317 u2DelayCellTimex100 = 275/100 ps
7549 11:44:56.991728 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7550 11:44:56.995226 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7551 11:44:56.998230 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7552 11:44:57.001653 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7553 11:44:57.005227 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7554 11:44:57.008646 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7555 11:44:57.009198
7556 11:44:57.011639 CA PerBit enable=1, Macro0, CA PI delay=37
7557 11:44:57.011733
7558 11:44:57.014732 [CBTSetCACLKResult] CA Dly = 37
7559 11:44:57.017858 CS Dly: 11 (0~44)
7560 11:44:57.021574 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 11:44:57.024568 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 11:44:57.024673
7563 11:44:57.028270 ----->DramcWriteLeveling(PI) begin...
7564 11:44:57.028372 ==
7565 11:44:57.031345 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 11:44:57.038146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 11:44:57.038256 ==
7568 11:44:57.041225 Write leveling (Byte 0): 36 => 36
7569 11:44:57.041301 Write leveling (Byte 1): 29 => 29
7570 11:44:57.044880 DramcWriteLeveling(PI) end<-----
7571 11:44:57.044956
7572 11:44:57.045019 ==
7573 11:44:57.048186 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 11:44:57.054692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 11:44:57.054764 ==
7576 11:44:57.057813 [Gating] SW mode calibration
7577 11:44:57.064576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7578 11:44:57.068346 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7579 11:44:57.074887 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 11:44:57.077961 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 11:44:57.081582 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 11:44:57.088168 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 11:44:57.091031 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
7584 11:44:57.094469 1 4 20 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
7585 11:44:57.101289 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
7586 11:44:57.104716 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 11:44:57.107667 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 11:44:57.111115 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 11:44:57.118106 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 11:44:57.121216 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7591 11:44:57.124301 1 5 16 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
7592 11:44:57.131143 1 5 20 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
7593 11:44:57.134164 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7594 11:44:57.137806 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 11:44:57.144702 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 11:44:57.147655 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 11:44:57.151410 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 11:44:57.157857 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 11:44:57.160842 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
7600 11:44:57.163998 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7601 11:44:57.170736 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7602 11:44:57.174507 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 11:44:57.177605 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 11:44:57.184346 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 11:44:57.187302 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 11:44:57.190747 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 11:44:57.197269 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 11:44:57.200692 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7609 11:44:57.204289 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7610 11:44:57.210722 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 11:44:57.214305 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 11:44:57.217266 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 11:44:57.223758 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 11:44:57.227540 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 11:44:57.230683 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 11:44:57.237047 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 11:44:57.240864 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 11:44:57.243852 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 11:44:57.250425 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 11:44:57.253996 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 11:44:57.257131 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 11:44:57.263661 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 11:44:57.266762 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7624 11:44:57.270361 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7625 11:44:57.277046 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7626 11:44:57.277152 Total UI for P1: 0, mck2ui 16
7627 11:44:57.280238 best dqsien dly found for B0: ( 1, 9, 18)
7628 11:44:57.286957 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 11:44:57.290499 Total UI for P1: 0, mck2ui 16
7630 11:44:57.293336 best dqsien dly found for B1: ( 1, 9, 22)
7631 11:44:57.297098 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7632 11:44:57.299985 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7633 11:44:57.300117
7634 11:44:57.303456 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7635 11:44:57.306483 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7636 11:44:57.309918 [Gating] SW calibration Done
7637 11:44:57.310008 ==
7638 11:44:57.313453 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 11:44:57.317091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 11:44:57.317208 ==
7641 11:44:57.319968 RX Vref Scan: 0
7642 11:44:57.320070
7643 11:44:57.323509 RX Vref 0 -> 0, step: 1
7644 11:44:57.323593
7645 11:44:57.323659 RX Delay 0 -> 252, step: 8
7646 11:44:57.329813 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7647 11:44:57.333450 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7648 11:44:57.336573 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7649 11:44:57.339613 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7650 11:44:57.343407 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7651 11:44:57.349667 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7652 11:44:57.353208 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7653 11:44:57.356182 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7654 11:44:57.359903 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7655 11:44:57.362827 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7656 11:44:57.369686 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7657 11:44:57.372710 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7658 11:44:57.376402 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7659 11:44:57.379505 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7660 11:44:57.383175 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7661 11:44:57.389646 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7662 11:44:57.389750 ==
7663 11:44:57.393122 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 11:44:57.396171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 11:44:57.396275 ==
7666 11:44:57.396366 DQS Delay:
7667 11:44:57.399535 DQS0 = 0, DQS1 = 0
7668 11:44:57.399634 DQM Delay:
7669 11:44:57.402895 DQM0 = 132, DQM1 = 125
7670 11:44:57.402991 DQ Delay:
7671 11:44:57.405826 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7672 11:44:57.409280 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7673 11:44:57.412721 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7674 11:44:57.416259 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7675 11:44:57.419692
7676 11:44:57.419789
7677 11:44:57.419882 ==
7678 11:44:57.422656 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 11:44:57.426204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 11:44:57.426318 ==
7681 11:44:57.426413
7682 11:44:57.426504
7683 11:44:57.429605 TX Vref Scan disable
7684 11:44:57.429703 == TX Byte 0 ==
7685 11:44:57.436319 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7686 11:44:57.439393 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7687 11:44:57.439494 == TX Byte 1 ==
7688 11:44:57.445869 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7689 11:44:57.449569 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7690 11:44:57.449675 ==
7691 11:44:57.452610 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 11:44:57.456126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 11:44:57.456202 ==
7694 11:44:57.471318
7695 11:44:57.474931 TX Vref early break, caculate TX vref
7696 11:44:57.478092 TX Vref=16, minBit 7, minWin=20, winSum=366
7697 11:44:57.481714 TX Vref=18, minBit 7, minWin=22, winSum=376
7698 11:44:57.484748 TX Vref=20, minBit 1, minWin=23, winSum=388
7699 11:44:57.488352 TX Vref=22, minBit 0, minWin=23, winSum=394
7700 11:44:57.491325 TX Vref=24, minBit 4, minWin=24, winSum=413
7701 11:44:57.498335 TX Vref=26, minBit 4, minWin=24, winSum=420
7702 11:44:57.501357 TX Vref=28, minBit 4, minWin=25, winSum=424
7703 11:44:57.504793 TX Vref=30, minBit 4, minWin=25, winSum=424
7704 11:44:57.507870 TX Vref=32, minBit 4, minWin=24, winSum=419
7705 11:44:57.511493 TX Vref=34, minBit 4, minWin=24, winSum=410
7706 11:44:57.514794 TX Vref=36, minBit 0, minWin=24, winSum=399
7707 11:44:57.521300 [TxChooseVref] Worse bit 4, Min win 25, Win sum 424, Final Vref 28
7708 11:44:57.521403
7709 11:44:57.524886 Final TX Range 0 Vref 28
7710 11:44:57.524992
7711 11:44:57.525084 ==
7712 11:44:57.527810 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 11:44:57.531319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 11:44:57.531464 ==
7715 11:44:57.531556
7716 11:44:57.531642
7717 11:44:57.534778 TX Vref Scan disable
7718 11:44:57.541514 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7719 11:44:57.541622 == TX Byte 0 ==
7720 11:44:57.544492 u2DelayCellOfst[0]=14 cells (4 PI)
7721 11:44:57.548160 u2DelayCellOfst[1]=17 cells (5 PI)
7722 11:44:57.551219 u2DelayCellOfst[2]=10 cells (3 PI)
7723 11:44:57.554344 u2DelayCellOfst[3]=14 cells (4 PI)
7724 11:44:57.557896 u2DelayCellOfst[4]=7 cells (2 PI)
7725 11:44:57.561456 u2DelayCellOfst[5]=0 cells (0 PI)
7726 11:44:57.564472 u2DelayCellOfst[6]=17 cells (5 PI)
7727 11:44:57.568138 u2DelayCellOfst[7]=21 cells (6 PI)
7728 11:44:57.571071 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7729 11:44:57.574668 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7730 11:44:57.577793 == TX Byte 1 ==
7731 11:44:57.580974 u2DelayCellOfst[8]=0 cells (0 PI)
7732 11:44:57.584533 u2DelayCellOfst[9]=3 cells (1 PI)
7733 11:44:57.587616 u2DelayCellOfst[10]=10 cells (3 PI)
7734 11:44:57.587718 u2DelayCellOfst[11]=3 cells (1 PI)
7735 11:44:57.591223 u2DelayCellOfst[12]=14 cells (4 PI)
7736 11:44:57.594298 u2DelayCellOfst[13]=10 cells (3 PI)
7737 11:44:57.597924 u2DelayCellOfst[14]=14 cells (4 PI)
7738 11:44:57.600829 u2DelayCellOfst[15]=14 cells (4 PI)
7739 11:44:57.607500 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7740 11:44:57.611103 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7741 11:44:57.611211 DramC Write-DBI on
7742 11:44:57.611321 ==
7743 11:44:57.614652 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 11:44:57.621076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 11:44:57.621192 ==
7746 11:44:57.621273
7747 11:44:57.621346
7748 11:44:57.621405 TX Vref Scan disable
7749 11:44:57.625087 == TX Byte 0 ==
7750 11:44:57.628582 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7751 11:44:57.631619 == TX Byte 1 ==
7752 11:44:57.635202 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7753 11:44:57.638193 DramC Write-DBI off
7754 11:44:57.638290
7755 11:44:57.638379 [DATLAT]
7756 11:44:57.638466 Freq=1600, CH0 RK0
7757 11:44:57.638552
7758 11:44:57.641550 DATLAT Default: 0xf
7759 11:44:57.644781 0, 0xFFFF, sum = 0
7760 11:44:57.644867 1, 0xFFFF, sum = 0
7761 11:44:57.648380 2, 0xFFFF, sum = 0
7762 11:44:57.648479 3, 0xFFFF, sum = 0
7763 11:44:57.651448 4, 0xFFFF, sum = 0
7764 11:44:57.651533 5, 0xFFFF, sum = 0
7765 11:44:57.655118 6, 0xFFFF, sum = 0
7766 11:44:57.655203 7, 0xFFFF, sum = 0
7767 11:44:57.658138 8, 0xFFFF, sum = 0
7768 11:44:57.658235 9, 0xFFFF, sum = 0
7769 11:44:57.661926 10, 0xFFFF, sum = 0
7770 11:44:57.662011 11, 0xFFFF, sum = 0
7771 11:44:57.664805 12, 0xFFFF, sum = 0
7772 11:44:57.664890 13, 0xFFFF, sum = 0
7773 11:44:57.668513 14, 0x0, sum = 1
7774 11:44:57.668597 15, 0x0, sum = 2
7775 11:44:57.671561 16, 0x0, sum = 3
7776 11:44:57.671645 17, 0x0, sum = 4
7777 11:44:57.675076 best_step = 15
7778 11:44:57.675159
7779 11:44:57.675224 ==
7780 11:44:57.678166 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 11:44:57.681262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 11:44:57.681362 ==
7783 11:44:57.684891 RX Vref Scan: 1
7784 11:44:57.684974
7785 11:44:57.685039 Set Vref Range= 24 -> 127
7786 11:44:57.685130
7787 11:44:57.688515 RX Vref 24 -> 127, step: 1
7788 11:44:57.688613
7789 11:44:57.691600 RX Delay 11 -> 252, step: 4
7790 11:44:57.691698
7791 11:44:57.694621 Set Vref, RX VrefLevel [Byte0]: 24
7792 11:44:57.698106 [Byte1]: 24
7793 11:44:57.698189
7794 11:44:57.701156 Set Vref, RX VrefLevel [Byte0]: 25
7795 11:44:57.704800 [Byte1]: 25
7796 11:44:57.707675
7797 11:44:57.707757 Set Vref, RX VrefLevel [Byte0]: 26
7798 11:44:57.711226 [Byte1]: 26
7799 11:44:57.715291
7800 11:44:57.715414 Set Vref, RX VrefLevel [Byte0]: 27
7801 11:44:57.718621 [Byte1]: 27
7802 11:44:57.722978
7803 11:44:57.723091 Set Vref, RX VrefLevel [Byte0]: 28
7804 11:44:57.726453 [Byte1]: 28
7805 11:44:57.730528
7806 11:44:57.730614 Set Vref, RX VrefLevel [Byte0]: 29
7807 11:44:57.734026 [Byte1]: 29
7808 11:44:57.738084
7809 11:44:57.738208 Set Vref, RX VrefLevel [Byte0]: 30
7810 11:44:57.741633 [Byte1]: 30
7811 11:44:57.745749
7812 11:44:57.745858 Set Vref, RX VrefLevel [Byte0]: 31
7813 11:44:57.749320 [Byte1]: 31
7814 11:44:57.753560
7815 11:44:57.753688 Set Vref, RX VrefLevel [Byte0]: 32
7816 11:44:57.756644 [Byte1]: 32
7817 11:44:57.760870
7818 11:44:57.760954 Set Vref, RX VrefLevel [Byte0]: 33
7819 11:44:57.764369 [Byte1]: 33
7820 11:44:57.768741
7821 11:44:57.768823 Set Vref, RX VrefLevel [Byte0]: 34
7822 11:44:57.772389 [Byte1]: 34
7823 11:44:57.776666
7824 11:44:57.776789 Set Vref, RX VrefLevel [Byte0]: 35
7825 11:44:57.779664 [Byte1]: 35
7826 11:44:57.783951
7827 11:44:57.784063 Set Vref, RX VrefLevel [Byte0]: 36
7828 11:44:57.787581 [Byte1]: 36
7829 11:44:57.791758
7830 11:44:57.791841 Set Vref, RX VrefLevel [Byte0]: 37
7831 11:44:57.794805 [Byte1]: 37
7832 11:44:57.798950
7833 11:44:57.799035 Set Vref, RX VrefLevel [Byte0]: 38
7834 11:44:57.802733 [Byte1]: 38
7835 11:44:57.806988
7836 11:44:57.807125 Set Vref, RX VrefLevel [Byte0]: 39
7837 11:44:57.810429 [Byte1]: 39
7838 11:44:57.814711
7839 11:44:57.814841 Set Vref, RX VrefLevel [Byte0]: 40
7840 11:44:57.817662 [Byte1]: 40
7841 11:44:57.821930
7842 11:44:57.822087 Set Vref, RX VrefLevel [Byte0]: 41
7843 11:44:57.825336 [Byte1]: 41
7844 11:44:57.829437
7845 11:44:57.829521 Set Vref, RX VrefLevel [Byte0]: 42
7846 11:44:57.832878 [Byte1]: 42
7847 11:44:57.837395
7848 11:44:57.837480 Set Vref, RX VrefLevel [Byte0]: 43
7849 11:44:57.840430 [Byte1]: 43
7850 11:44:57.844531
7851 11:44:57.844634 Set Vref, RX VrefLevel [Byte0]: 44
7852 11:44:57.847976 [Byte1]: 44
7853 11:44:57.852688
7854 11:44:57.852787 Set Vref, RX VrefLevel [Byte0]: 45
7855 11:44:57.855842 [Byte1]: 45
7856 11:44:57.860133
7857 11:44:57.860216 Set Vref, RX VrefLevel [Byte0]: 46
7858 11:44:57.863089 [Byte1]: 46
7859 11:44:57.867900
7860 11:44:57.867983 Set Vref, RX VrefLevel [Byte0]: 47
7861 11:44:57.870878 [Byte1]: 47
7862 11:44:57.875736
7863 11:44:57.875819 Set Vref, RX VrefLevel [Byte0]: 48
7864 11:44:57.878727 [Byte1]: 48
7865 11:44:57.882935
7866 11:44:57.883028 Set Vref, RX VrefLevel [Byte0]: 49
7867 11:44:57.886322 [Byte1]: 49
7868 11:44:57.890616
7869 11:44:57.890702 Set Vref, RX VrefLevel [Byte0]: 50
7870 11:44:57.894095 [Byte1]: 50
7871 11:44:57.898377
7872 11:44:57.898460 Set Vref, RX VrefLevel [Byte0]: 51
7873 11:44:57.901383 [Byte1]: 51
7874 11:44:57.905720
7875 11:44:57.905804 Set Vref, RX VrefLevel [Byte0]: 52
7876 11:44:57.909273 [Byte1]: 52
7877 11:44:57.913515
7878 11:44:57.913599 Set Vref, RX VrefLevel [Byte0]: 53
7879 11:44:57.916514 [Byte1]: 53
7880 11:44:57.920753
7881 11:44:57.920836 Set Vref, RX VrefLevel [Byte0]: 54
7882 11:44:57.924262 [Byte1]: 54
7883 11:44:57.928407
7884 11:44:57.928506 Set Vref, RX VrefLevel [Byte0]: 55
7885 11:44:57.931871 [Byte1]: 55
7886 11:44:57.936468
7887 11:44:57.936577 Set Vref, RX VrefLevel [Byte0]: 56
7888 11:44:57.939252 [Byte1]: 56
7889 11:44:57.944056
7890 11:44:57.944140 Set Vref, RX VrefLevel [Byte0]: 57
7891 11:44:57.947080 [Byte1]: 57
7892 11:44:57.951715
7893 11:44:57.951799 Set Vref, RX VrefLevel [Byte0]: 58
7894 11:44:57.954627 [Byte1]: 58
7895 11:44:57.959020
7896 11:44:57.959129 Set Vref, RX VrefLevel [Byte0]: 59
7897 11:44:57.962187 [Byte1]: 59
7898 11:44:57.966895
7899 11:44:57.967017 Set Vref, RX VrefLevel [Byte0]: 60
7900 11:44:57.969945 [Byte1]: 60
7901 11:44:57.974274
7902 11:44:57.974357 Set Vref, RX VrefLevel [Byte0]: 61
7903 11:44:57.977978 [Byte1]: 61
7904 11:44:57.982223
7905 11:44:57.982307 Set Vref, RX VrefLevel [Byte0]: 62
7906 11:44:57.985236 [Byte1]: 62
7907 11:44:57.989731
7908 11:44:57.989840 Set Vref, RX VrefLevel [Byte0]: 63
7909 11:44:57.992737 [Byte1]: 63
7910 11:44:57.997159
7911 11:44:57.997289 Set Vref, RX VrefLevel [Byte0]: 64
7912 11:44:58.000708 [Byte1]: 64
7913 11:44:58.005014
7914 11:44:58.005098 Set Vref, RX VrefLevel [Byte0]: 65
7915 11:44:58.008110 [Byte1]: 65
7916 11:44:58.012325
7917 11:44:58.012434 Set Vref, RX VrefLevel [Byte0]: 66
7918 11:44:58.015294 [Byte1]: 66
7919 11:44:58.020219
7920 11:44:58.020302 Set Vref, RX VrefLevel [Byte0]: 67
7921 11:44:58.023295 [Byte1]: 67
7922 11:44:58.027513
7923 11:44:58.030546 Set Vref, RX VrefLevel [Byte0]: 68
7924 11:44:58.033942 [Byte1]: 68
7925 11:44:58.034051
7926 11:44:58.037515 Set Vref, RX VrefLevel [Byte0]: 69
7927 11:44:58.040485 [Byte1]: 69
7928 11:44:58.040570
7929 11:44:58.044034 Set Vref, RX VrefLevel [Byte0]: 70
7930 11:44:58.047644 [Byte1]: 70
7931 11:44:58.047728
7932 11:44:58.050586 Set Vref, RX VrefLevel [Byte0]: 71
7933 11:44:58.053972 [Byte1]: 71
7934 11:44:58.057948
7935 11:44:58.058060 Set Vref, RX VrefLevel [Byte0]: 72
7936 11:44:58.061669 [Byte1]: 72
7937 11:44:58.065874
7938 11:44:58.065983 Set Vref, RX VrefLevel [Byte0]: 73
7939 11:44:58.068940 [Byte1]: 73
7940 11:44:58.073149
7941 11:44:58.073258 Set Vref, RX VrefLevel [Byte0]: 74
7942 11:44:58.076380 [Byte1]: 74
7943 11:44:58.080594
7944 11:44:58.080677 Set Vref, RX VrefLevel [Byte0]: 75
7945 11:44:58.084207 [Byte1]: 75
7946 11:44:58.088484
7947 11:44:58.088567 Set Vref, RX VrefLevel [Byte0]: 76
7948 11:44:58.091948 [Byte1]: 76
7949 11:44:58.096005
7950 11:44:58.096105 Final RX Vref Byte 0 = 57 to rank0
7951 11:44:58.099576 Final RX Vref Byte 1 = 63 to rank0
7952 11:44:58.102599 Final RX Vref Byte 0 = 57 to rank1
7953 11:44:58.106319 Final RX Vref Byte 1 = 63 to rank1==
7954 11:44:58.109399 Dram Type= 6, Freq= 0, CH_0, rank 0
7955 11:44:58.115995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7956 11:44:58.116081 ==
7957 11:44:58.116148 DQS Delay:
7958 11:44:58.116210 DQS0 = 0, DQS1 = 0
7959 11:44:58.119170 DQM Delay:
7960 11:44:58.119268 DQM0 = 129, DQM1 = 122
7961 11:44:58.122821 DQ Delay:
7962 11:44:58.125940 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7963 11:44:58.129297 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7964 11:44:58.132327 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7965 11:44:58.135947 DQ12 =128, DQ13 =126, DQ14 =130, DQ15 =132
7966 11:44:58.136099
7967 11:44:58.136170
7968 11:44:58.136232
7969 11:44:58.139432 [DramC_TX_OE_Calibration] TA2
7970 11:44:58.142297 Original DQ_B0 (3 6) =30, OEN = 27
7971 11:44:58.145806 Original DQ_B1 (3 6) =30, OEN = 27
7972 11:44:58.149526 24, 0x0, End_B0=24 End_B1=24
7973 11:44:58.149612 25, 0x0, End_B0=25 End_B1=25
7974 11:44:58.152379 26, 0x0, End_B0=26 End_B1=26
7975 11:44:58.155500 27, 0x0, End_B0=27 End_B1=27
7976 11:44:58.158791 28, 0x0, End_B0=28 End_B1=28
7977 11:44:58.162489 29, 0x0, End_B0=29 End_B1=29
7978 11:44:58.162575 30, 0x0, End_B0=30 End_B1=30
7979 11:44:58.165959 31, 0x4141, End_B0=30 End_B1=30
7980 11:44:58.169025 Byte0 end_step=30 best_step=27
7981 11:44:58.172521 Byte1 end_step=30 best_step=27
7982 11:44:58.175522 Byte0 TX OE(2T, 0.5T) = (3, 3)
7983 11:44:58.178650 Byte1 TX OE(2T, 0.5T) = (3, 3)
7984 11:44:58.178734
7985 11:44:58.178800
7986 11:44:58.185325 [DQSOSCAuto] RK0, (LSB)MR18= 0x1104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 401 ps
7987 11:44:58.188996 CH0 RK0: MR19=303, MR18=1104
7988 11:44:58.195720 CH0_RK0: MR19=0x303, MR18=0x1104, DQSOSC=401, MR23=63, INC=22, DEC=15
7989 11:44:58.195805
7990 11:44:58.198719 ----->DramcWriteLeveling(PI) begin...
7991 11:44:58.198805 ==
7992 11:44:58.202155 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 11:44:58.205836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 11:44:58.205921 ==
7995 11:44:58.208725 Write leveling (Byte 0): 35 => 35
7996 11:44:58.211941 Write leveling (Byte 1): 24 => 24
7997 11:44:58.215513 DramcWriteLeveling(PI) end<-----
7998 11:44:58.215597
7999 11:44:58.215663 ==
8000 11:44:58.218493 Dram Type= 6, Freq= 0, CH_0, rank 1
8001 11:44:58.222121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 11:44:58.222206 ==
8003 11:44:58.225783 [Gating] SW mode calibration
8004 11:44:58.231859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8005 11:44:58.238619 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8006 11:44:58.242039 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 11:44:58.245595 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 11:44:58.251935 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8009 11:44:58.255364 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8010 11:44:58.258858 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8011 11:44:58.265360 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8012 11:44:58.268421 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 11:44:58.271924 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 11:44:58.278698 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 11:44:58.281802 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 11:44:58.285573 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8017 11:44:58.291700 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8018 11:44:58.295283 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8019 11:44:58.298410 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8020 11:44:58.304847 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 11:44:58.308508 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 11:44:58.311473 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 11:44:58.318125 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 11:44:58.321592 1 6 8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
8025 11:44:58.324727 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8026 11:44:58.331272 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8027 11:44:58.334806 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8028 11:44:58.337821 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 11:44:58.345105 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 11:44:58.347939 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 11:44:58.351273 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 11:44:58.358319 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8033 11:44:58.361326 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8034 11:44:58.364663 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8035 11:44:58.371248 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8036 11:44:58.374819 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 11:44:58.378416 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 11:44:58.384453 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 11:44:58.388122 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 11:44:58.391452 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 11:44:58.398163 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 11:44:58.401170 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 11:44:58.404847 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 11:44:58.410940 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 11:44:58.414555 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 11:44:58.417587 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 11:44:58.421197 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 11:44:58.427956 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8049 11:44:58.431221 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8050 11:44:58.434179 Total UI for P1: 0, mck2ui 16
8051 11:44:58.437868 best dqsien dly found for B0: ( 1, 9, 8)
8052 11:44:58.441253 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8053 11:44:58.447918 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8054 11:44:58.450727 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 11:44:58.454412 Total UI for P1: 0, mck2ui 16
8056 11:44:58.457325 best dqsien dly found for B1: ( 1, 9, 20)
8057 11:44:58.460643 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8058 11:44:58.464279 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8059 11:44:58.464373
8060 11:44:58.467195 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8061 11:44:58.474233 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8062 11:44:58.474317 [Gating] SW calibration Done
8063 11:44:58.474385 ==
8064 11:44:58.477641 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 11:44:58.484233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 11:44:58.484319 ==
8067 11:44:58.484385 RX Vref Scan: 0
8068 11:44:58.484447
8069 11:44:58.487329 RX Vref 0 -> 0, step: 1
8070 11:44:58.487418
8071 11:44:58.490865 RX Delay 0 -> 252, step: 8
8072 11:44:58.494007 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8073 11:44:58.497610 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8074 11:44:58.500671 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8075 11:44:58.504302 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8076 11:44:58.510506 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8077 11:44:58.513892 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8078 11:44:58.517443 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8079 11:44:58.520546 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8080 11:44:58.523542 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8081 11:44:58.530204 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8082 11:44:58.533764 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8083 11:44:58.536722 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8084 11:44:58.540482 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8085 11:44:58.546959 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8086 11:44:58.549945 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8087 11:44:58.553478 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8088 11:44:58.553554 ==
8089 11:44:58.556974 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 11:44:58.560356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 11:44:58.560453 ==
8092 11:44:58.563595 DQS Delay:
8093 11:44:58.563690 DQS0 = 0, DQS1 = 0
8094 11:44:58.566471 DQM Delay:
8095 11:44:58.566574 DQM0 = 131, DQM1 = 124
8096 11:44:58.570435 DQ Delay:
8097 11:44:58.573933 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8098 11:44:58.576794 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8099 11:44:58.580130 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8100 11:44:58.583601 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8101 11:44:58.584029
8102 11:44:58.584367
8103 11:44:58.584675 ==
8104 11:44:58.586771 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 11:44:58.590763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 11:44:58.591197 ==
8107 11:44:58.591620
8108 11:44:58.591950
8109 11:44:58.593465 TX Vref Scan disable
8110 11:44:58.596675 == TX Byte 0 ==
8111 11:44:58.600341 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8112 11:44:58.603433 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8113 11:44:58.606521 == TX Byte 1 ==
8114 11:44:58.610145 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8115 11:44:58.613376 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8116 11:44:58.613809 ==
8117 11:44:58.617124 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 11:44:58.623236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 11:44:58.623900 ==
8120 11:44:58.637570
8121 11:44:58.640620 TX Vref early break, caculate TX vref
8122 11:44:58.643593 TX Vref=16, minBit 4, minWin=22, winSum=372
8123 11:44:58.647182 TX Vref=18, minBit 8, minWin=22, winSum=379
8124 11:44:58.650184 TX Vref=20, minBit 8, minWin=23, winSum=391
8125 11:44:58.653562 TX Vref=22, minBit 9, minWin=23, winSum=395
8126 11:44:58.656802 TX Vref=24, minBit 4, minWin=24, winSum=405
8127 11:44:58.663936 TX Vref=26, minBit 2, minWin=25, winSum=414
8128 11:44:58.667161 TX Vref=28, minBit 1, minWin=24, winSum=418
8129 11:44:58.670299 TX Vref=30, minBit 0, minWin=25, winSum=415
8130 11:44:58.673665 TX Vref=32, minBit 0, minWin=25, winSum=412
8131 11:44:58.676730 TX Vref=34, minBit 1, minWin=24, winSum=405
8132 11:44:58.680225 TX Vref=36, minBit 4, minWin=23, winSum=392
8133 11:44:58.686609 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 30
8134 11:44:58.687040
8135 11:44:58.690008 Final TX Range 0 Vref 30
8136 11:44:58.690436
8137 11:44:58.690704 ==
8138 11:44:58.693722 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 11:44:58.696706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 11:44:58.696920 ==
8141 11:44:58.697096
8142 11:44:58.699829
8143 11:44:58.700057 TX Vref Scan disable
8144 11:44:58.706416 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8145 11:44:58.706569 == TX Byte 0 ==
8146 11:44:58.709612 u2DelayCellOfst[0]=14 cells (4 PI)
8147 11:44:58.713247 u2DelayCellOfst[1]=21 cells (6 PI)
8148 11:44:58.716259 u2DelayCellOfst[2]=10 cells (3 PI)
8149 11:44:58.719975 u2DelayCellOfst[3]=10 cells (3 PI)
8150 11:44:58.722805 u2DelayCellOfst[4]=10 cells (3 PI)
8151 11:44:58.726220 u2DelayCellOfst[5]=0 cells (0 PI)
8152 11:44:58.729255 u2DelayCellOfst[6]=17 cells (5 PI)
8153 11:44:58.733041 u2DelayCellOfst[7]=17 cells (5 PI)
8154 11:44:58.736134 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8155 11:44:58.739766 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8156 11:44:58.742899 == TX Byte 1 ==
8157 11:44:58.746089 u2DelayCellOfst[8]=3 cells (1 PI)
8158 11:44:58.749726 u2DelayCellOfst[9]=0 cells (0 PI)
8159 11:44:58.753149 u2DelayCellOfst[10]=7 cells (2 PI)
8160 11:44:58.756717 u2DelayCellOfst[11]=3 cells (1 PI)
8161 11:44:58.759735 u2DelayCellOfst[12]=14 cells (4 PI)
8162 11:44:58.759988 u2DelayCellOfst[13]=14 cells (4 PI)
8163 11:44:58.762661 u2DelayCellOfst[14]=17 cells (5 PI)
8164 11:44:58.766331 u2DelayCellOfst[15]=10 cells (3 PI)
8165 11:44:58.772892 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8166 11:44:58.775766 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8167 11:44:58.776075 DramC Write-DBI on
8168 11:44:58.779306 ==
8169 11:44:58.782885 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 11:44:58.785774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 11:44:58.786094 ==
8172 11:44:58.786371
8173 11:44:58.786646
8174 11:44:58.789172 TX Vref Scan disable
8175 11:44:58.789454 == TX Byte 0 ==
8176 11:44:58.795626 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8177 11:44:58.795967 == TX Byte 1 ==
8178 11:44:58.799379 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8179 11:44:58.802426 DramC Write-DBI off
8180 11:44:58.802620
8181 11:44:58.802796 [DATLAT]
8182 11:44:58.805492 Freq=1600, CH0 RK1
8183 11:44:58.805692
8184 11:44:58.805847 DATLAT Default: 0xf
8185 11:44:58.809123 0, 0xFFFF, sum = 0
8186 11:44:58.809310 1, 0xFFFF, sum = 0
8187 11:44:58.812767 2, 0xFFFF, sum = 0
8188 11:44:58.812928 3, 0xFFFF, sum = 0
8189 11:44:58.815654 4, 0xFFFF, sum = 0
8190 11:44:58.815759 5, 0xFFFF, sum = 0
8191 11:44:58.818777 6, 0xFFFF, sum = 0
8192 11:44:58.822543 7, 0xFFFF, sum = 0
8193 11:44:58.822691 8, 0xFFFF, sum = 0
8194 11:44:58.825516 9, 0xFFFF, sum = 0
8195 11:44:58.825659 10, 0xFFFF, sum = 0
8196 11:44:58.829045 11, 0xFFFF, sum = 0
8197 11:44:58.829186 12, 0xFFFF, sum = 0
8198 11:44:58.832181 13, 0xFFFF, sum = 0
8199 11:44:58.832325 14, 0x0, sum = 1
8200 11:44:58.835651 15, 0x0, sum = 2
8201 11:44:58.835791 16, 0x0, sum = 3
8202 11:44:58.838718 17, 0x0, sum = 4
8203 11:44:58.838856 best_step = 15
8204 11:44:58.838981
8205 11:44:58.839103 ==
8206 11:44:58.842425 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 11:44:58.845459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 11:44:58.845543 ==
8209 11:44:58.849213 RX Vref Scan: 0
8210 11:44:58.849296
8211 11:44:58.852217 RX Vref 0 -> 0, step: 1
8212 11:44:58.852300
8213 11:44:58.852365 RX Delay 11 -> 252, step: 4
8214 11:44:58.859413 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8215 11:44:58.862372 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8216 11:44:58.866090 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8217 11:44:58.869487 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8218 11:44:58.875914 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8219 11:44:58.879309 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8220 11:44:58.882283 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8221 11:44:58.885904 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8222 11:44:58.889270 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8223 11:44:58.895543 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8224 11:44:58.899102 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8225 11:44:58.902242 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8226 11:44:58.905865 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8227 11:44:58.908939 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8228 11:44:58.915563 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8229 11:44:58.919184 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8230 11:44:58.919292 ==
8231 11:44:58.922191 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 11:44:58.925758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 11:44:58.925867 ==
8234 11:44:58.928927 DQS Delay:
8235 11:44:58.929028 DQS0 = 0, DQS1 = 0
8236 11:44:58.929118 DQM Delay:
8237 11:44:58.932647 DQM0 = 126, DQM1 = 122
8238 11:44:58.932755 DQ Delay:
8239 11:44:58.935305 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8240 11:44:58.938963 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8241 11:44:58.942001 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8242 11:44:58.948798 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8243 11:44:58.948954
8244 11:44:58.949026
8245 11:44:58.949090
8246 11:44:58.952310 [DramC_TX_OE_Calibration] TA2
8247 11:44:58.952458 Original DQ_B0 (3 6) =30, OEN = 27
8248 11:44:58.955345 Original DQ_B1 (3 6) =30, OEN = 27
8249 11:44:58.958976 24, 0x0, End_B0=24 End_B1=24
8250 11:44:58.962452 25, 0x0, End_B0=25 End_B1=25
8251 11:44:58.965327 26, 0x0, End_B0=26 End_B1=26
8252 11:44:58.968940 27, 0x0, End_B0=27 End_B1=27
8253 11:44:58.969024 28, 0x0, End_B0=28 End_B1=28
8254 11:44:58.971995 29, 0x0, End_B0=29 End_B1=29
8255 11:44:58.975363 30, 0x0, End_B0=30 End_B1=30
8256 11:44:58.978934 31, 0x4141, End_B0=30 End_B1=30
8257 11:44:58.982336 Byte0 end_step=30 best_step=27
8258 11:44:58.982420 Byte1 end_step=30 best_step=27
8259 11:44:58.985230 Byte0 TX OE(2T, 0.5T) = (3, 3)
8260 11:44:58.988737 Byte1 TX OE(2T, 0.5T) = (3, 3)
8261 11:44:58.988823
8262 11:44:58.988891
8263 11:44:58.998194 [DQSOSCAuto] RK1, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8264 11:44:58.998307 CH0 RK1: MR19=303, MR18=160B
8265 11:44:59.004877 CH0_RK1: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8266 11:44:59.008603 [RxdqsGatingPostProcess] freq 1600
8267 11:44:59.015239 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8268 11:44:59.018340 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 11:44:59.021474 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 11:44:59.024957 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 11:44:59.028587 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 11:44:59.031629 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 11:44:59.031714 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 11:44:59.035245 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 11:44:59.038092 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 11:44:59.041593 Pre-setting of DQS Precalculation
8277 11:44:59.047897 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8278 11:44:59.048047 ==
8279 11:44:59.051461 Dram Type= 6, Freq= 0, CH_1, rank 0
8280 11:44:59.054455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 11:44:59.054540 ==
8282 11:44:59.061216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8283 11:44:59.064930 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8284 11:44:59.067987 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8285 11:44:59.074679 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8286 11:44:59.083872 [CA 0] Center 43 (15~72) winsize 58
8287 11:44:59.086879 [CA 1] Center 43 (14~72) winsize 59
8288 11:44:59.090493 [CA 2] Center 38 (10~67) winsize 58
8289 11:44:59.094279 [CA 3] Center 37 (8~67) winsize 60
8290 11:44:59.097021 [CA 4] Center 38 (9~68) winsize 60
8291 11:44:59.100472 [CA 5] Center 37 (8~66) winsize 59
8292 11:44:59.100556
8293 11:44:59.103256 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8294 11:44:59.103391
8295 11:44:59.106689 [CATrainingPosCal] consider 1 rank data
8296 11:44:59.110551 u2DelayCellTimex100 = 275/100 ps
8297 11:44:59.113559 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8298 11:44:59.120361 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8299 11:44:59.123390 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8300 11:44:59.126885 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8301 11:44:59.130556 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8302 11:44:59.133619 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8303 11:44:59.133727
8304 11:44:59.137138 CA PerBit enable=1, Macro0, CA PI delay=37
8305 11:44:59.137563
8306 11:44:59.140622 [CBTSetCACLKResult] CA Dly = 37
8307 11:44:59.143503 CS Dly: 8 (0~39)
8308 11:44:59.147156 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8309 11:44:59.150711 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8310 11:44:59.151262 ==
8311 11:44:59.153729 Dram Type= 6, Freq= 0, CH_1, rank 1
8312 11:44:59.156883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 11:44:59.160666 ==
8314 11:44:59.163444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8315 11:44:59.167031 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8316 11:44:59.173531 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8317 11:44:59.180260 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8318 11:44:59.187307 [CA 0] Center 43 (15~72) winsize 58
8319 11:44:59.190672 [CA 1] Center 43 (14~72) winsize 59
8320 11:44:59.194187 [CA 2] Center 38 (9~67) winsize 59
8321 11:44:59.197234 [CA 3] Center 37 (8~67) winsize 60
8322 11:44:59.200675 [CA 4] Center 38 (9~68) winsize 60
8323 11:44:59.204221 [CA 5] Center 36 (7~66) winsize 60
8324 11:44:59.204644
8325 11:44:59.207555 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8326 11:44:59.207978
8327 11:44:59.210601 [CATrainingPosCal] consider 2 rank data
8328 11:44:59.214105 u2DelayCellTimex100 = 275/100 ps
8329 11:44:59.217278 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8330 11:44:59.223948 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8331 11:44:59.226957 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8332 11:44:59.230706 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8333 11:44:59.233735 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8334 11:44:59.237489 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8335 11:44:59.237911
8336 11:44:59.240460 CA PerBit enable=1, Macro0, CA PI delay=37
8337 11:44:59.241229
8338 11:44:59.243590 [CBTSetCACLKResult] CA Dly = 37
8339 11:44:59.247155 CS Dly: 11 (0~45)
8340 11:44:59.250270 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8341 11:44:59.253470 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8342 11:44:59.253889
8343 11:44:59.256780 ----->DramcWriteLeveling(PI) begin...
8344 11:44:59.257210 ==
8345 11:44:59.260471 Dram Type= 6, Freq= 0, CH_1, rank 0
8346 11:44:59.267486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 11:44:59.268014 ==
8348 11:44:59.270217 Write leveling (Byte 0): 23 => 23
8349 11:44:59.270641 Write leveling (Byte 1): 27 => 27
8350 11:44:59.273801 DramcWriteLeveling(PI) end<-----
8351 11:44:59.274241
8352 11:44:59.276945 ==
8353 11:44:59.277364 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 11:44:59.283439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 11:44:59.283865 ==
8356 11:44:59.286898 [Gating] SW mode calibration
8357 11:44:59.293340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8358 11:44:59.296769 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8359 11:44:59.303398 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 11:44:59.306754 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 11:44:59.309722 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 11:44:59.316592 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 11:44:59.319738 1 4 16 | B1->B0 | 2626 2323 | 1 0 | (1 1) (0 0)
8364 11:44:59.323280 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 11:44:59.329983 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 11:44:59.333328 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 11:44:59.336755 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 11:44:59.342897 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 11:44:59.346561 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 11:44:59.349549 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8371 11:44:59.356697 1 5 16 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (1 0)
8372 11:44:59.359720 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8373 11:44:59.363294 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 11:44:59.369805 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 11:44:59.373093 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 11:44:59.376765 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 11:44:59.383111 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 11:44:59.386722 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8379 11:44:59.389859 1 6 16 | B1->B0 | 3737 2727 | 0 0 | (0 0) (0 0)
8380 11:44:59.392907 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 11:44:59.399810 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 11:44:59.402590 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 11:44:59.406211 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 11:44:59.412524 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 11:44:59.415885 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 11:44:59.419295 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8387 11:44:59.425841 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8388 11:44:59.428896 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 11:44:59.432489 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 11:44:59.439323 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 11:44:59.442181 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 11:44:59.445898 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 11:44:59.452607 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 11:44:59.455451 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 11:44:59.458987 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:44:59.465615 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:44:59.469177 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:44:59.472305 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:44:59.478968 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:44:59.482200 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 11:44:59.485560 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 11:44:59.492338 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8403 11:44:59.495315 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8404 11:44:59.498696 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 11:44:59.502096 Total UI for P1: 0, mck2ui 16
8406 11:44:59.505658 best dqsien dly found for B0: ( 1, 9, 14)
8407 11:44:59.508594 Total UI for P1: 0, mck2ui 16
8408 11:44:59.512344 best dqsien dly found for B1: ( 1, 9, 16)
8409 11:44:59.515742 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8410 11:44:59.518683 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8411 11:44:59.518770
8412 11:44:59.522253 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8413 11:44:59.528739 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8414 11:44:59.528827 [Gating] SW calibration Done
8415 11:44:59.532386 ==
8416 11:44:59.532496 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 11:44:59.539166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 11:44:59.539250 ==
8419 11:44:59.539316 RX Vref Scan: 0
8420 11:44:59.539409
8421 11:44:59.542238 RX Vref 0 -> 0, step: 1
8422 11:44:59.542321
8423 11:44:59.545237 RX Delay 0 -> 252, step: 8
8424 11:44:59.549247 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8425 11:44:59.551995 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8426 11:44:59.556056 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8427 11:44:59.562494 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8428 11:44:59.565997 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8429 11:44:59.568991 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8430 11:44:59.572680 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8431 11:44:59.575632 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8432 11:44:59.579302 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8433 11:44:59.586087 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8434 11:44:59.589126 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8435 11:44:59.592458 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8436 11:44:59.595561 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8437 11:44:59.601974 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8438 11:44:59.605282 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8439 11:44:59.608650 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8440 11:44:59.609088 ==
8441 11:44:59.612157 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 11:44:59.615853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 11:44:59.616289 ==
8444 11:44:59.618525 DQS Delay:
8445 11:44:59.618955 DQS0 = 0, DQS1 = 0
8446 11:44:59.622064 DQM Delay:
8447 11:44:59.622496 DQM0 = 134, DQM1 = 127
8448 11:44:59.622842 DQ Delay:
8449 11:44:59.625354 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8450 11:44:59.631973 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8451 11:44:59.635448 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8452 11:44:59.638485 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8453 11:44:59.638916
8454 11:44:59.639257
8455 11:44:59.639624 ==
8456 11:44:59.641653 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 11:44:59.645470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 11:44:59.645907 ==
8459 11:44:59.646247
8460 11:44:59.646680
8461 11:44:59.648436 TX Vref Scan disable
8462 11:44:59.652118 == TX Byte 0 ==
8463 11:44:59.655165 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8464 11:44:59.658852 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8465 11:44:59.661696 == TX Byte 1 ==
8466 11:44:59.664992 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8467 11:44:59.668755 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8468 11:44:59.669297 ==
8469 11:44:59.672096 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 11:44:59.675084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 11:44:59.678070 ==
8472 11:44:59.691059
8473 11:44:59.694367 TX Vref early break, caculate TX vref
8474 11:44:59.697127 TX Vref=16, minBit 8, minWin=21, winSum=364
8475 11:44:59.700798 TX Vref=18, minBit 11, minWin=21, winSum=377
8476 11:44:59.704257 TX Vref=20, minBit 8, minWin=21, winSum=381
8477 11:44:59.707181 TX Vref=22, minBit 8, minWin=23, winSum=393
8478 11:44:59.710728 TX Vref=24, minBit 8, minWin=23, winSum=403
8479 11:44:59.717615 TX Vref=26, minBit 8, minWin=24, winSum=414
8480 11:44:59.720846 TX Vref=28, minBit 0, minWin=25, winSum=419
8481 11:44:59.724015 TX Vref=30, minBit 1, minWin=25, winSum=420
8482 11:44:59.727437 TX Vref=32, minBit 8, minWin=24, winSum=409
8483 11:44:59.730355 TX Vref=34, minBit 9, minWin=23, winSum=401
8484 11:44:59.733888 TX Vref=36, minBit 8, minWin=23, winSum=393
8485 11:44:59.740465 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 30
8486 11:44:59.740894
8487 11:44:59.743442 Final TX Range 0 Vref 30
8488 11:44:59.743843
8489 11:44:59.744163 ==
8490 11:44:59.747137 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 11:44:59.750250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 11:44:59.750756 ==
8493 11:44:59.751127
8494 11:44:59.753960
8495 11:44:59.754382 TX Vref Scan disable
8496 11:44:59.761120 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8497 11:44:59.761548 == TX Byte 0 ==
8498 11:44:59.763590 u2DelayCellOfst[0]=17 cells (5 PI)
8499 11:44:59.766915 u2DelayCellOfst[1]=10 cells (3 PI)
8500 11:44:59.770665 u2DelayCellOfst[2]=0 cells (0 PI)
8501 11:44:59.773481 u2DelayCellOfst[3]=7 cells (2 PI)
8502 11:44:59.777069 u2DelayCellOfst[4]=7 cells (2 PI)
8503 11:44:59.780028 u2DelayCellOfst[5]=21 cells (6 PI)
8504 11:44:59.783757 u2DelayCellOfst[6]=17 cells (5 PI)
8505 11:44:59.786662 u2DelayCellOfst[7]=7 cells (2 PI)
8506 11:44:59.790334 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8507 11:44:59.793472 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8508 11:44:59.796931 == TX Byte 1 ==
8509 11:44:59.800338 u2DelayCellOfst[8]=0 cells (0 PI)
8510 11:44:59.800771 u2DelayCellOfst[9]=7 cells (2 PI)
8511 11:44:59.803279 u2DelayCellOfst[10]=14 cells (4 PI)
8512 11:44:59.807161 u2DelayCellOfst[11]=10 cells (3 PI)
8513 11:44:59.810068 u2DelayCellOfst[12]=14 cells (4 PI)
8514 11:44:59.813451 u2DelayCellOfst[13]=17 cells (5 PI)
8515 11:44:59.816704 u2DelayCellOfst[14]=17 cells (5 PI)
8516 11:44:59.820363 u2DelayCellOfst[15]=21 cells (6 PI)
8517 11:44:59.826723 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8518 11:44:59.829795 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8519 11:44:59.830123 DramC Write-DBI on
8520 11:44:59.830372 ==
8521 11:44:59.833351 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 11:44:59.839595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 11:44:59.839832 ==
8524 11:44:59.840017
8525 11:44:59.840192
8526 11:44:59.840366 TX Vref Scan disable
8527 11:44:59.843866 == TX Byte 0 ==
8528 11:44:59.846795 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8529 11:44:59.850368 == TX Byte 1 ==
8530 11:44:59.853492 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8531 11:44:59.856653 DramC Write-DBI off
8532 11:44:59.856774
8533 11:44:59.856873 [DATLAT]
8534 11:44:59.856973 Freq=1600, CH1 RK0
8535 11:44:59.857074
8536 11:44:59.860436 DATLAT Default: 0xf
8537 11:44:59.860561 0, 0xFFFF, sum = 0
8538 11:44:59.863648 1, 0xFFFF, sum = 0
8539 11:44:59.866699 2, 0xFFFF, sum = 0
8540 11:44:59.866940 3, 0xFFFF, sum = 0
8541 11:44:59.870416 4, 0xFFFF, sum = 0
8542 11:44:59.870605 5, 0xFFFF, sum = 0
8543 11:44:59.873615 6, 0xFFFF, sum = 0
8544 11:44:59.873739 7, 0xFFFF, sum = 0
8545 11:44:59.876648 8, 0xFFFF, sum = 0
8546 11:44:59.876799 9, 0xFFFF, sum = 0
8547 11:44:59.880200 10, 0xFFFF, sum = 0
8548 11:44:59.880328 11, 0xFFFF, sum = 0
8549 11:44:59.883287 12, 0xFFFF, sum = 0
8550 11:44:59.883416 13, 0xFFFF, sum = 0
8551 11:44:59.887084 14, 0x0, sum = 1
8552 11:44:59.887215 15, 0x0, sum = 2
8553 11:44:59.890280 16, 0x0, sum = 3
8554 11:44:59.890423 17, 0x0, sum = 4
8555 11:44:59.893450 best_step = 15
8556 11:44:59.893565
8557 11:44:59.893634 ==
8558 11:44:59.896607 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 11:44:59.900292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 11:44:59.900372 ==
8561 11:44:59.903451 RX Vref Scan: 1
8562 11:44:59.903524
8563 11:44:59.903587 Set Vref Range= 24 -> 127
8564 11:44:59.903646
8565 11:44:59.907237 RX Vref 24 -> 127, step: 1
8566 11:44:59.907764
8567 11:44:59.910391 RX Delay 19 -> 252, step: 4
8568 11:44:59.910962
8569 11:44:59.913456 Set Vref, RX VrefLevel [Byte0]: 24
8570 11:44:59.917251 [Byte1]: 24
8571 11:44:59.917686
8572 11:44:59.920173 Set Vref, RX VrefLevel [Byte0]: 25
8573 11:44:59.923707 [Byte1]: 25
8574 11:44:59.926905
8575 11:44:59.927470 Set Vref, RX VrefLevel [Byte0]: 26
8576 11:44:59.930090 [Byte1]: 26
8577 11:44:59.934437
8578 11:44:59.935002 Set Vref, RX VrefLevel [Byte0]: 27
8579 11:44:59.937594 [Byte1]: 27
8580 11:45:00.037687
8581 11:45:00.038213 Set Vref, RX VrefLevel [Byte0]: 28
8582 11:45:00.038560 [Byte1]: 28
8583 11:45:00.038881
8584 11:45:00.039185 Set Vref, RX VrefLevel [Byte0]: 29
8585 11:45:00.039556 [Byte1]: 29
8586 11:45:00.039865
8587 11:45:00.040155 Set Vref, RX VrefLevel [Byte0]: 30
8588 11:45:00.040445 [Byte1]: 30
8589 11:45:00.040732
8590 11:45:00.041015 Set Vref, RX VrefLevel [Byte0]: 31
8591 11:45:00.041301 [Byte1]: 31
8592 11:45:00.041585
8593 11:45:00.041878 Set Vref, RX VrefLevel [Byte0]: 32
8594 11:45:00.042186 [Byte1]: 32
8595 11:45:00.042485
8596 11:45:00.042762 Set Vref, RX VrefLevel [Byte0]: 33
8597 11:45:00.043039 [Byte1]: 33
8598 11:45:00.043326
8599 11:45:00.043656 Set Vref, RX VrefLevel [Byte0]: 34
8600 11:45:00.043974 [Byte1]: 34
8601 11:45:00.044344
8602 11:45:00.044629 Set Vref, RX VrefLevel [Byte0]: 35
8603 11:45:00.044907 [Byte1]: 35
8604 11:45:00.045188
8605 11:45:00.045462 Set Vref, RX VrefLevel [Byte0]: 36
8606 11:45:00.045741 [Byte1]: 36
8607 11:45:00.046013
8608 11:45:00.046286 Set Vref, RX VrefLevel [Byte0]: 37
8609 11:45:00.046563 [Byte1]: 37
8610 11:45:00.046840
8611 11:45:00.047113 Set Vref, RX VrefLevel [Byte0]: 38
8612 11:45:00.047443 [Byte1]: 38
8613 11:45:00.047779
8614 11:45:00.048060 Set Vref, RX VrefLevel [Byte0]: 39
8615 11:45:00.048339 [Byte1]: 39
8616 11:45:00.048623
8617 11:45:00.048897 Set Vref, RX VrefLevel [Byte0]: 40
8618 11:45:00.049176 [Byte1]: 40
8619 11:45:00.049768
8620 11:45:00.050091 Set Vref, RX VrefLevel [Byte0]: 41
8621 11:45:00.050372 [Byte1]: 41
8622 11:45:00.050652
8623 11:45:00.050926 Set Vref, RX VrefLevel [Byte0]: 42
8624 11:45:00.051513 [Byte1]: 42
8625 11:45:00.055186
8626 11:45:00.055599 Set Vref, RX VrefLevel [Byte0]: 43
8627 11:45:00.058918 [Byte1]: 43
8628 11:45:00.062734
8629 11:45:00.063291 Set Vref, RX VrefLevel [Byte0]: 44
8630 11:45:00.066513 [Byte1]: 44
8631 11:45:00.070450
8632 11:45:00.071187 Set Vref, RX VrefLevel [Byte0]: 45
8633 11:45:00.074090 [Byte1]: 45
8634 11:45:00.078030
8635 11:45:00.078460 Set Vref, RX VrefLevel [Byte0]: 46
8636 11:45:00.081783 [Byte1]: 46
8637 11:45:00.085629
8638 11:45:00.086058 Set Vref, RX VrefLevel [Byte0]: 47
8639 11:45:00.089309 [Byte1]: 47
8640 11:45:00.093633
8641 11:45:00.094062 Set Vref, RX VrefLevel [Byte0]: 48
8642 11:45:00.096742 [Byte1]: 48
8643 11:45:00.101141
8644 11:45:00.101699 Set Vref, RX VrefLevel [Byte0]: 49
8645 11:45:00.104390 [Byte1]: 49
8646 11:45:00.108255
8647 11:45:00.108717 Set Vref, RX VrefLevel [Byte0]: 50
8648 11:45:00.112022 [Byte1]: 50
8649 11:45:00.116208
8650 11:45:00.116848 Set Vref, RX VrefLevel [Byte0]: 51
8651 11:45:00.119314 [Byte1]: 51
8652 11:45:00.123548
8653 11:45:00.124131 Set Vref, RX VrefLevel [Byte0]: 52
8654 11:45:00.126614 [Byte1]: 52
8655 11:45:00.138132
8656 11:45:00.139015 Set Vref, RX VrefLevel [Byte0]: 53
8657 11:45:00.139600 [Byte1]: 53
8658 11:45:00.140237
8659 11:45:00.140635 Set Vref, RX VrefLevel [Byte0]: 54
8660 11:45:00.142359 [Byte1]: 54
8661 11:45:00.146029
8662 11:45:00.146847 Set Vref, RX VrefLevel [Byte0]: 55
8663 11:45:00.149582 [Byte1]: 55
8664 11:45:00.153806
8665 11:45:00.154261 Set Vref, RX VrefLevel [Byte0]: 56
8666 11:45:00.157024 [Byte1]: 56
8667 11:45:00.161357
8668 11:45:00.161806 Set Vref, RX VrefLevel [Byte0]: 57
8669 11:45:00.164676 [Byte1]: 57
8670 11:45:00.168896
8671 11:45:00.169198 Set Vref, RX VrefLevel [Byte0]: 58
8672 11:45:00.171951 [Byte1]: 58
8673 11:45:00.176431
8674 11:45:00.176720 Set Vref, RX VrefLevel [Byte0]: 59
8675 11:45:00.179650 [Byte1]: 59
8676 11:45:00.184016
8677 11:45:00.184219 Set Vref, RX VrefLevel [Byte0]: 60
8678 11:45:00.187273 [Byte1]: 60
8679 11:45:00.191581
8680 11:45:00.191827 Set Vref, RX VrefLevel [Byte0]: 61
8681 11:45:00.194678 [Byte1]: 61
8682 11:45:00.198827
8683 11:45:00.199017 Set Vref, RX VrefLevel [Byte0]: 62
8684 11:45:00.202256 [Byte1]: 62
8685 11:45:00.206462
8686 11:45:00.206666 Set Vref, RX VrefLevel [Byte0]: 63
8687 11:45:00.210283 [Byte1]: 63
8688 11:45:00.214073
8689 11:45:00.214262 Set Vref, RX VrefLevel [Byte0]: 64
8690 11:45:00.217245 [Byte1]: 64
8691 11:45:00.221518
8692 11:45:00.221768 Set Vref, RX VrefLevel [Byte0]: 65
8693 11:45:00.225351 [Byte1]: 65
8694 11:45:00.229638
8695 11:45:00.229912 Set Vref, RX VrefLevel [Byte0]: 66
8696 11:45:00.232499 [Byte1]: 66
8697 11:45:00.236874
8698 11:45:00.237065 Set Vref, RX VrefLevel [Byte0]: 67
8699 11:45:00.240219 [Byte1]: 67
8700 11:45:00.252808
8701 11:45:00.253264 Set Vref, RX VrefLevel [Byte0]: 68
8702 11:45:00.253710 [Byte1]: 68
8703 11:45:00.254123
8704 11:45:00.254526 Set Vref, RX VrefLevel [Byte0]: 69
8705 11:45:00.255873 [Byte1]: 69
8706 11:45:00.259949
8707 11:45:00.260378 Set Vref, RX VrefLevel [Byte0]: 70
8708 11:45:00.263062 [Byte1]: 70
8709 11:45:00.267596
8710 11:45:00.268184 Set Vref, RX VrefLevel [Byte0]: 71
8711 11:45:00.270739 [Byte1]: 71
8712 11:45:00.274990
8713 11:45:00.275606 Set Vref, RX VrefLevel [Byte0]: 72
8714 11:45:00.278121 [Byte1]: 72
8715 11:45:00.282580
8716 11:45:00.282975 Final RX Vref Byte 0 = 64 to rank0
8717 11:45:00.285631 Final RX Vref Byte 1 = 57 to rank0
8718 11:45:00.288848 Final RX Vref Byte 0 = 64 to rank1
8719 11:45:00.305355 Final RX Vref Byte 1 = 57 to rank1==
8720 11:45:00.305715 Dram Type= 6, Freq= 0, CH_1, rank 0
8721 11:45:00.305840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 11:45:00.305943 ==
8723 11:45:00.306040 DQS Delay:
8724 11:45:00.306134 DQS0 = 0, DQS1 = 0
8725 11:45:00.306224 DQM Delay:
8726 11:45:00.306312 DQM0 = 132, DQM1 = 125
8727 11:45:00.308783 DQ Delay:
8728 11:45:00.312629 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =132
8729 11:45:00.315254 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8730 11:45:00.318806 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
8731 11:45:00.322475 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =132
8732 11:45:00.322609
8733 11:45:00.322713
8734 11:45:00.322811
8735 11:45:00.325639 [DramC_TX_OE_Calibration] TA2
8736 11:45:00.328658 Original DQ_B0 (3 6) =30, OEN = 27
8737 11:45:00.331863 Original DQ_B1 (3 6) =30, OEN = 27
8738 11:45:00.335591 24, 0x0, End_B0=24 End_B1=24
8739 11:45:00.335730 25, 0x0, End_B0=25 End_B1=25
8740 11:45:00.338504 26, 0x0, End_B0=26 End_B1=26
8741 11:45:00.342036 27, 0x0, End_B0=27 End_B1=27
8742 11:45:00.345327 28, 0x0, End_B0=28 End_B1=28
8743 11:45:00.348675 29, 0x0, End_B0=29 End_B1=29
8744 11:45:00.348828 30, 0x0, End_B0=30 End_B1=30
8745 11:45:00.351706 31, 0x4141, End_B0=30 End_B1=30
8746 11:45:00.354854 Byte0 end_step=30 best_step=27
8747 11:45:00.358583 Byte1 end_step=30 best_step=27
8748 11:45:00.361616 Byte0 TX OE(2T, 0.5T) = (3, 3)
8749 11:45:00.365269 Byte1 TX OE(2T, 0.5T) = (3, 3)
8750 11:45:00.365412
8751 11:45:00.365517
8752 11:45:00.372054 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8753 11:45:00.375216 CH1 RK0: MR19=302, MR18=12FE
8754 11:45:00.424980 CH1_RK0: MR19=0x302, MR18=0x12FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8755 11:45:00.425584
8756 11:45:00.426114 ----->DramcWriteLeveling(PI) begin...
8757 11:45:00.426501 ==
8758 11:45:00.426936 Dram Type= 6, Freq= 0, CH_1, rank 1
8759 11:45:00.427457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 11:45:00.427938 ==
8761 11:45:00.428405 Write leveling (Byte 0): 26 => 26
8762 11:45:00.428843 Write leveling (Byte 1): 26 => 26
8763 11:45:00.429412 DramcWriteLeveling(PI) end<-----
8764 11:45:00.429847
8765 11:45:00.430401 ==
8766 11:45:00.430794 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 11:45:00.431311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 11:45:00.431849 ==
8769 11:45:00.432411 [Gating] SW mode calibration
8770 11:45:00.432979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8771 11:45:00.433523 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8772 11:45:00.434188 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 11:45:00.435121 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 11:45:00.437990 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8775 11:45:00.441489 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8776 11:45:00.447972 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 11:45:00.451024 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 11:45:00.454472 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 11:45:00.461081 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 11:45:00.464223 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 11:45:00.467881 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8782 11:45:00.474386 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
8783 11:45:00.510304 1 5 12 | B1->B0 | 3232 2424 | 1 0 | (0 1) (1 0)
8784 11:45:00.510736 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8785 11:45:00.511009 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 11:45:00.511409 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 11:45:00.511764 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 11:45:00.512111 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 11:45:00.512416 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 11:45:00.512714 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8791 11:45:00.513681 1 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8792 11:45:00.516929 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 11:45:00.520602 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 11:45:00.527027 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 11:45:00.530074 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 11:45:00.533645 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 11:45:00.540539 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8798 11:45:00.543600 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8799 11:45:00.547106 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8800 11:45:00.553634 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8801 11:45:00.556792 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 11:45:00.560410 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 11:45:00.563871 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 11:45:00.570241 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 11:45:00.573413 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 11:45:00.577092 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 11:45:00.583298 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 11:45:00.586493 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 11:45:00.590330 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 11:45:00.596483 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 11:45:00.600255 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 11:45:00.603416 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 11:45:00.609663 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8814 11:45:00.613408 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8815 11:45:00.616645 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8816 11:45:00.619784 Total UI for P1: 0, mck2ui 16
8817 11:45:00.622895 best dqsien dly found for B0: ( 1, 9, 6)
8818 11:45:00.629849 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 11:45:00.629973 Total UI for P1: 0, mck2ui 16
8820 11:45:00.636106 best dqsien dly found for B1: ( 1, 9, 12)
8821 11:45:00.639730 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8822 11:45:00.642852 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8823 11:45:00.642980
8824 11:45:00.646448 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8825 11:45:00.649443 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8826 11:45:00.652564 [Gating] SW calibration Done
8827 11:45:00.652688 ==
8828 11:45:00.656285 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 11:45:00.659714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 11:45:00.659815 ==
8831 11:45:00.662777 RX Vref Scan: 0
8832 11:45:00.662861
8833 11:45:00.662945 RX Vref 0 -> 0, step: 1
8834 11:45:00.663010
8835 11:45:00.665816 RX Delay 0 -> 252, step: 8
8836 11:45:00.669393 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8837 11:45:00.676145 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8838 11:45:00.679098 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8839 11:45:00.682720 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8840 11:45:00.685861 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8841 11:45:00.689080 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8842 11:45:00.696222 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8843 11:45:00.699267 iDelay=200, Bit 7, Center 123 (72 ~ 175) 104
8844 11:45:00.702575 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8845 11:45:00.705718 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8846 11:45:00.708941 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8847 11:45:00.716187 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8848 11:45:00.719188 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8849 11:45:00.722410 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8850 11:45:00.725547 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8851 11:45:00.732693 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8852 11:45:00.732815 ==
8853 11:45:00.735841 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 11:45:00.738897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 11:45:00.738984 ==
8856 11:45:00.739051 DQS Delay:
8857 11:45:00.742562 DQS0 = 0, DQS1 = 0
8858 11:45:00.742681 DQM Delay:
8859 11:45:00.745729 DQM0 = 132, DQM1 = 127
8860 11:45:00.745827 DQ Delay:
8861 11:45:00.748821 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8862 11:45:00.752492 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =123
8863 11:45:00.755321 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8864 11:45:00.758933 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8865 11:45:00.759010
8866 11:45:00.759075
8867 11:45:00.761915 ==
8868 11:45:00.765492 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 11:45:00.769178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 11:45:00.769272 ==
8871 11:45:00.769384
8872 11:45:00.769492
8873 11:45:00.771885 TX Vref Scan disable
8874 11:45:00.772057 == TX Byte 0 ==
8875 11:45:00.775507 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8876 11:45:00.781756 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8877 11:45:00.781873 == TX Byte 1 ==
8878 11:45:00.785326 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8879 11:45:00.791631 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8880 11:45:00.791774 ==
8881 11:45:00.795322 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 11:45:00.798630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 11:45:00.798833 ==
8884 11:45:00.812743
8885 11:45:00.815977 TX Vref early break, caculate TX vref
8886 11:45:00.819333 TX Vref=16, minBit 9, minWin=22, winSum=384
8887 11:45:00.822627 TX Vref=18, minBit 6, minWin=23, winSum=387
8888 11:45:00.825756 TX Vref=20, minBit 8, minWin=23, winSum=396
8889 11:45:00.829718 TX Vref=22, minBit 8, minWin=24, winSum=403
8890 11:45:00.832859 TX Vref=24, minBit 6, minWin=25, winSum=416
8891 11:45:00.839106 TX Vref=26, minBit 6, minWin=25, winSum=417
8892 11:45:00.842800 TX Vref=28, minBit 8, minWin=25, winSum=422
8893 11:45:00.846407 TX Vref=30, minBit 0, minWin=25, winSum=420
8894 11:45:00.849335 TX Vref=32, minBit 8, minWin=24, winSum=414
8895 11:45:00.852367 TX Vref=34, minBit 0, minWin=24, winSum=408
8896 11:45:00.856156 TX Vref=36, minBit 9, minWin=23, winSum=394
8897 11:45:00.862733 [TxChooseVref] Worse bit 8, Min win 25, Win sum 422, Final Vref 28
8898 11:45:00.863172
8899 11:45:00.865657 Final TX Range 0 Vref 28
8900 11:45:00.866101
8901 11:45:00.866439 ==
8902 11:45:00.869363 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 11:45:00.872959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 11:45:00.873396 ==
8905 11:45:00.873740
8906 11:45:00.874059
8907 11:45:00.875883 TX Vref Scan disable
8908 11:45:00.882453 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8909 11:45:00.883034 == TX Byte 0 ==
8910 11:45:00.886015 u2DelayCellOfst[0]=17 cells (5 PI)
8911 11:45:00.889131 u2DelayCellOfst[1]=10 cells (3 PI)
8912 11:45:00.892198 u2DelayCellOfst[2]=0 cells (0 PI)
8913 11:45:00.895984 u2DelayCellOfst[3]=7 cells (2 PI)
8914 11:45:00.899150 u2DelayCellOfst[4]=10 cells (3 PI)
8915 11:45:00.902257 u2DelayCellOfst[5]=17 cells (5 PI)
8916 11:45:00.905347 u2DelayCellOfst[6]=17 cells (5 PI)
8917 11:45:00.909136 u2DelayCellOfst[7]=7 cells (2 PI)
8918 11:45:00.911749 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8919 11:45:00.915503 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 11:45:00.918628 == TX Byte 1 ==
8921 11:45:00.921626 u2DelayCellOfst[8]=0 cells (0 PI)
8922 11:45:00.925263 u2DelayCellOfst[9]=7 cells (2 PI)
8923 11:45:00.928321 u2DelayCellOfst[10]=14 cells (4 PI)
8924 11:45:00.928477 u2DelayCellOfst[11]=7 cells (2 PI)
8925 11:45:00.931680 u2DelayCellOfst[12]=14 cells (4 PI)
8926 11:45:00.935392 u2DelayCellOfst[13]=17 cells (5 PI)
8927 11:45:00.938591 u2DelayCellOfst[14]=17 cells (5 PI)
8928 11:45:00.941758 u2DelayCellOfst[15]=17 cells (5 PI)
8929 11:45:00.948143 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8930 11:45:00.951774 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8931 11:45:00.951956 DramC Write-DBI on
8932 11:45:00.952061 ==
8933 11:45:00.954698 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 11:45:00.961539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 11:45:00.961709 ==
8936 11:45:00.961809
8937 11:45:00.961901
8938 11:45:00.964740 TX Vref Scan disable
8939 11:45:00.964886 == TX Byte 0 ==
8940 11:45:00.971186 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8941 11:45:00.971309 == TX Byte 1 ==
8942 11:45:00.974838 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8943 11:45:00.977942 DramC Write-DBI off
8944 11:45:00.978022
8945 11:45:00.978089 [DATLAT]
8946 11:45:00.981608 Freq=1600, CH1 RK1
8947 11:45:00.981700
8948 11:45:00.981772 DATLAT Default: 0xf
8949 11:45:00.984568 0, 0xFFFF, sum = 0
8950 11:45:00.984690 1, 0xFFFF, sum = 0
8951 11:45:00.988268 2, 0xFFFF, sum = 0
8952 11:45:00.988392 3, 0xFFFF, sum = 0
8953 11:45:00.991289 4, 0xFFFF, sum = 0
8954 11:45:00.991448 5, 0xFFFF, sum = 0
8955 11:45:00.994417 6, 0xFFFF, sum = 0
8956 11:45:00.994548 7, 0xFFFF, sum = 0
8957 11:45:00.997969 8, 0xFFFF, sum = 0
8958 11:45:00.998117 9, 0xFFFF, sum = 0
8959 11:45:01.001126 10, 0xFFFF, sum = 0
8960 11:45:01.004505 11, 0xFFFF, sum = 0
8961 11:45:01.004679 12, 0xFFFF, sum = 0
8962 11:45:01.008217 13, 0xFFFF, sum = 0
8963 11:45:01.008397 14, 0x0, sum = 1
8964 11:45:01.010734 15, 0x0, sum = 2
8965 11:45:01.010969 16, 0x0, sum = 3
8966 11:45:01.014475 17, 0x0, sum = 4
8967 11:45:01.014677 best_step = 15
8968 11:45:01.014854
8969 11:45:01.015023 ==
8970 11:45:01.017620 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 11:45:01.021015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 11:45:01.021290 ==
8973 11:45:01.024651 RX Vref Scan: 0
8974 11:45:01.024918
8975 11:45:01.027682 RX Vref 0 -> 0, step: 1
8976 11:45:01.027989
8977 11:45:01.028269 RX Delay 11 -> 252, step: 4
8978 11:45:01.034725 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8979 11:45:01.038481 iDelay=191, Bit 1, Center 124 (75 ~ 174) 100
8980 11:45:01.041706 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8981 11:45:01.045034 iDelay=191, Bit 3, Center 130 (79 ~ 182) 104
8982 11:45:01.048119 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8983 11:45:01.054711 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8984 11:45:01.057697 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8985 11:45:01.061371 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
8986 11:45:01.064540 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8987 11:45:01.068247 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8988 11:45:01.074756 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8989 11:45:01.077807 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8990 11:45:01.081240 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8991 11:45:01.085293 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8992 11:45:01.091312 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8993 11:45:01.094263 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
8994 11:45:01.094643 ==
8995 11:45:01.097996 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 11:45:01.100971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 11:45:01.101322 ==
8998 11:45:01.101726 DQS Delay:
8999 11:45:01.104561 DQS0 = 0, DQS1 = 0
9000 11:45:01.104912 DQM Delay:
9001 11:45:01.107742 DQM0 = 130, DQM1 = 126
9002 11:45:01.108012 DQ Delay:
9003 11:45:01.110875 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
9004 11:45:01.113905 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9005 11:45:01.117703 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120
9006 11:45:01.124137 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9007 11:45:01.124225
9008 11:45:01.124324
9009 11:45:01.124418
9010 11:45:01.124507 [DramC_TX_OE_Calibration] TA2
9011 11:45:01.127295 Original DQ_B0 (3 6) =30, OEN = 27
9012 11:45:01.131110 Original DQ_B1 (3 6) =30, OEN = 27
9013 11:45:01.134238 24, 0x0, End_B0=24 End_B1=24
9014 11:45:01.137502 25, 0x0, End_B0=25 End_B1=25
9015 11:45:01.140711 26, 0x0, End_B0=26 End_B1=26
9016 11:45:01.140837 27, 0x0, End_B0=27 End_B1=27
9017 11:45:01.144077 28, 0x0, End_B0=28 End_B1=28
9018 11:45:01.147118 29, 0x0, End_B0=29 End_B1=29
9019 11:45:01.150906 30, 0x0, End_B0=30 End_B1=30
9020 11:45:01.154022 31, 0x5151, End_B0=30 End_B1=30
9021 11:45:01.157229 Byte0 end_step=30 best_step=27
9022 11:45:01.157338 Byte1 end_step=30 best_step=27
9023 11:45:01.160691 Byte0 TX OE(2T, 0.5T) = (3, 3)
9024 11:45:01.163681 Byte1 TX OE(2T, 0.5T) = (3, 3)
9025 11:45:01.163761
9026 11:45:01.163827
9027 11:45:01.173696 [DQSOSCAuto] RK1, (LSB)MR18= 0xe15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9028 11:45:01.173801 CH1 RK1: MR19=303, MR18=E15
9029 11:45:01.180450 CH1_RK1: MR19=0x303, MR18=0xE15, DQSOSC=399, MR23=63, INC=23, DEC=15
9030 11:45:01.183384 [RxdqsGatingPostProcess] freq 1600
9031 11:45:01.189923 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9032 11:45:01.193643 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 11:45:01.196503 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 11:45:01.200261 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 11:45:01.203186 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 11:45:01.203311 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 11:45:01.206883 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 11:45:01.210067 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 11:45:01.213281 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 11:45:01.216455 Pre-setting of DQS Precalculation
9041 11:45:01.223545 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9042 11:45:01.229782 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9043 11:45:01.236737 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9044 11:45:01.236841
9045 11:45:01.236911
9046 11:45:01.239842 [Calibration Summary] 3200 Mbps
9047 11:45:01.239930 CH 0, Rank 0
9048 11:45:01.243030 SW Impedance : PASS
9049 11:45:01.246835 DUTY Scan : NO K
9050 11:45:01.246982 ZQ Calibration : PASS
9051 11:45:01.249936 Jitter Meter : NO K
9052 11:45:01.253171 CBT Training : PASS
9053 11:45:01.253258 Write leveling : PASS
9054 11:45:01.256367 RX DQS gating : PASS
9055 11:45:01.260146 RX DQ/DQS(RDDQC) : PASS
9056 11:45:01.260236 TX DQ/DQS : PASS
9057 11:45:01.263072 RX DATLAT : PASS
9058 11:45:01.263162 RX DQ/DQS(Engine): PASS
9059 11:45:01.266695 TX OE : PASS
9060 11:45:01.266818 All Pass.
9061 11:45:01.266914
9062 11:45:01.269918 CH 0, Rank 1
9063 11:45:01.270004 SW Impedance : PASS
9064 11:45:01.273561 DUTY Scan : NO K
9065 11:45:01.276576 ZQ Calibration : PASS
9066 11:45:01.276679 Jitter Meter : NO K
9067 11:45:01.279808 CBT Training : PASS
9068 11:45:01.282760 Write leveling : PASS
9069 11:45:01.282887 RX DQS gating : PASS
9070 11:45:01.286164 RX DQ/DQS(RDDQC) : PASS
9071 11:45:01.289860 TX DQ/DQS : PASS
9072 11:45:01.289991 RX DATLAT : PASS
9073 11:45:01.292902 RX DQ/DQS(Engine): PASS
9074 11:45:01.296551 TX OE : PASS
9075 11:45:01.296662 All Pass.
9076 11:45:01.296760
9077 11:45:01.296824 CH 1, Rank 0
9078 11:45:01.300224 SW Impedance : PASS
9079 11:45:01.303081 DUTY Scan : NO K
9080 11:45:01.303180 ZQ Calibration : PASS
9081 11:45:01.306677 Jitter Meter : NO K
9082 11:45:01.309856 CBT Training : PASS
9083 11:45:01.309959 Write leveling : PASS
9084 11:45:01.313049 RX DQS gating : PASS
9085 11:45:01.313159 RX DQ/DQS(RDDQC) : PASS
9086 11:45:01.316215 TX DQ/DQS : PASS
9087 11:45:01.319908 RX DATLAT : PASS
9088 11:45:01.320027 RX DQ/DQS(Engine): PASS
9089 11:45:01.323118 TX OE : PASS
9090 11:45:01.323193 All Pass.
9091 11:45:01.323292
9092 11:45:01.326412 CH 1, Rank 1
9093 11:45:01.326534 SW Impedance : PASS
9094 11:45:01.329510 DUTY Scan : NO K
9095 11:45:01.333156 ZQ Calibration : PASS
9096 11:45:01.333275 Jitter Meter : NO K
9097 11:45:01.336442 CBT Training : PASS
9098 11:45:01.339571 Write leveling : PASS
9099 11:45:01.339664 RX DQS gating : PASS
9100 11:45:01.343221 RX DQ/DQS(RDDQC) : PASS
9101 11:45:01.346414 TX DQ/DQS : PASS
9102 11:45:01.346511 RX DATLAT : PASS
9103 11:45:01.349541 RX DQ/DQS(Engine): PASS
9104 11:45:01.352757 TX OE : PASS
9105 11:45:01.352834 All Pass.
9106 11:45:01.352906
9107 11:45:01.352966 DramC Write-DBI on
9108 11:45:01.356485 PER_BANK_REFRESH: Hybrid Mode
9109 11:45:01.359650 TX_TRACKING: ON
9110 11:45:01.366050 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9111 11:45:01.375875 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9112 11:45:01.382595 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9113 11:45:01.386269 [FAST_K] Save calibration result to emmc
9114 11:45:01.389190 sync common calibartion params.
9115 11:45:01.392842 sync cbt_mode0:1, 1:1
9116 11:45:01.392936 dram_init: ddr_geometry: 2
9117 11:45:01.396101 dram_init: ddr_geometry: 2
9118 11:45:01.399563 dram_init: ddr_geometry: 2
9119 11:45:01.399649 0:dram_rank_size:100000000
9120 11:45:01.402645 1:dram_rank_size:100000000
9121 11:45:01.409320 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9122 11:45:01.409407 DFS_SHUFFLE_HW_MODE: ON
9123 11:45:01.416058 dramc_set_vcore_voltage set vcore to 725000
9124 11:45:01.416206 Read voltage for 1600, 0
9125 11:45:01.419166 Vio18 = 0
9126 11:45:01.419252 Vcore = 725000
9127 11:45:01.419318 Vdram = 0
9128 11:45:01.422217 Vddq = 0
9129 11:45:01.422326 Vmddr = 0
9130 11:45:01.426077 switch to 3200 Mbps bootup
9131 11:45:01.426165 [DramcRunTimeConfig]
9132 11:45:01.426231 PHYPLL
9133 11:45:01.429374 DPM_CONTROL_AFTERK: ON
9134 11:45:01.432512 PER_BANK_REFRESH: ON
9135 11:45:01.432641 REFRESH_OVERHEAD_REDUCTION: ON
9136 11:45:01.435598 CMD_PICG_NEW_MODE: OFF
9137 11:45:01.438795 XRTWTW_NEW_MODE: ON
9138 11:45:01.438875 XRTRTR_NEW_MODE: ON
9139 11:45:01.442454 TX_TRACKING: ON
9140 11:45:01.442591 RDSEL_TRACKING: OFF
9141 11:45:01.445462 DQS Precalculation for DVFS: ON
9142 11:45:01.445584 RX_TRACKING: OFF
9143 11:45:01.449180 HW_GATING DBG: ON
9144 11:45:01.449293 ZQCS_ENABLE_LP4: ON
9145 11:45:01.452273 RX_PICG_NEW_MODE: ON
9146 11:45:01.455426 TX_PICG_NEW_MODE: ON
9147 11:45:01.455502 ENABLE_RX_DCM_DPHY: ON
9148 11:45:01.458629 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9149 11:45:01.462452 DUMMY_READ_FOR_TRACKING: OFF
9150 11:45:01.465462 !!! SPM_CONTROL_AFTERK: OFF
9151 11:45:01.469142 !!! SPM could not control APHY
9152 11:45:01.469249 IMPEDANCE_TRACKING: ON
9153 11:45:01.472118 TEMP_SENSOR: ON
9154 11:45:01.472221 HW_SAVE_FOR_SR: OFF
9155 11:45:01.475329 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9156 11:45:01.478957 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9157 11:45:01.481996 Read ODT Tracking: ON
9158 11:45:01.482083 Refresh Rate DeBounce: ON
9159 11:45:01.485114 DFS_NO_QUEUE_FLUSH: ON
9160 11:45:01.488869 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9161 11:45:01.491961 ENABLE_DFS_RUNTIME_MRW: OFF
9162 11:45:01.495646 DDR_RESERVE_NEW_MODE: ON
9163 11:45:01.495729 MR_CBT_SWITCH_FREQ: ON
9164 11:45:01.498629 =========================
9165 11:45:01.516938 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9166 11:45:01.519964 dram_init: ddr_geometry: 2
9167 11:45:01.538148 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9168 11:45:01.541914 dram_init: dram init end (result: 0)
9169 11:45:01.548289 DRAM-K: Full calibration passed in 24569 msecs
9170 11:45:01.551942 MRC: failed to locate region type 0.
9171 11:45:01.552028 DRAM rank0 size:0x100000000,
9172 11:45:01.555137 DRAM rank1 size=0x100000000
9173 11:45:01.565356 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9174 11:45:01.571535 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9175 11:45:01.578473 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9176 11:45:01.585219 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9177 11:45:01.588388 DRAM rank0 size:0x100000000,
9178 11:45:01.591514 DRAM rank1 size=0x100000000
9179 11:45:01.591609 CBMEM:
9180 11:45:01.595220 IMD: root @ 0xfffff000 254 entries.
9181 11:45:01.598339 IMD: root @ 0xffffec00 62 entries.
9182 11:45:01.601488 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9183 11:45:01.604566 WARNING: RO_VPD is uninitialized or empty.
9184 11:45:01.611234 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9185 11:45:01.618593 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9186 11:45:01.631119 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9187 11:45:01.642636 BS: romstage times (exec / console): total (unknown) / 24075 ms
9188 11:45:01.642756
9189 11:45:01.642855
9190 11:45:01.652653 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9191 11:45:01.655687 ARM64: Exception handlers installed.
9192 11:45:01.658816 ARM64: Testing exception
9193 11:45:01.662707 ARM64: Done test exception
9194 11:45:01.662810 Enumerating buses...
9195 11:45:01.665842 Show all devs... Before device enumeration.
9196 11:45:01.669097 Root Device: enabled 1
9197 11:45:01.672209 CPU_CLUSTER: 0: enabled 1
9198 11:45:01.672383 CPU: 00: enabled 1
9199 11:45:01.676189 Compare with tree...
9200 11:45:01.676289 Root Device: enabled 1
9201 11:45:01.679223 CPU_CLUSTER: 0: enabled 1
9202 11:45:01.682276 CPU: 00: enabled 1
9203 11:45:01.682399 Root Device scanning...
9204 11:45:01.685757 scan_static_bus for Root Device
9205 11:45:01.689506 CPU_CLUSTER: 0 enabled
9206 11:45:01.692488 scan_static_bus for Root Device done
9207 11:45:01.695436 scan_bus: bus Root Device finished in 8 msecs
9208 11:45:01.695642 done
9209 11:45:01.702264 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9210 11:45:01.705765 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9211 11:45:01.712556 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9212 11:45:01.715779 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9213 11:45:01.718858 Allocating resources...
9214 11:45:01.722581 Reading resources...
9215 11:45:01.725794 Root Device read_resources bus 0 link: 0
9216 11:45:01.725956 DRAM rank0 size:0x100000000,
9217 11:45:01.729297 DRAM rank1 size=0x100000000
9218 11:45:01.732556 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9219 11:45:01.735848 CPU: 00 missing read_resources
9220 11:45:01.741985 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9221 11:45:01.745209 Root Device read_resources bus 0 link: 0 done
9222 11:45:01.745289 Done reading resources.
9223 11:45:01.752268 Show resources in subtree (Root Device)...After reading.
9224 11:45:01.755265 Root Device child on link 0 CPU_CLUSTER: 0
9225 11:45:01.759018 CPU_CLUSTER: 0 child on link 0 CPU: 00
9226 11:45:01.768627 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9227 11:45:01.768716 CPU: 00
9228 11:45:01.772308 Root Device assign_resources, bus 0 link: 0
9229 11:45:01.775231 CPU_CLUSTER: 0 missing set_resources
9230 11:45:01.781716 Root Device assign_resources, bus 0 link: 0 done
9231 11:45:01.781808 Done setting resources.
9232 11:45:01.788613 Show resources in subtree (Root Device)...After assigning values.
9233 11:45:01.791550 Root Device child on link 0 CPU_CLUSTER: 0
9234 11:45:01.795298 CPU_CLUSTER: 0 child on link 0 CPU: 00
9235 11:45:01.805217 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9236 11:45:01.805349 CPU: 00
9237 11:45:01.808265 Done allocating resources.
9238 11:45:01.815371 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9239 11:45:01.815561 Enabling resources...
9240 11:45:01.815706 done.
9241 11:45:01.821915 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9242 11:45:01.822163 Initializing devices...
9243 11:45:01.825050 Root Device init
9244 11:45:01.825258 init hardware done!
9245 11:45:01.828303 0x00000018: ctrlr->caps
9246 11:45:01.831961 52.000 MHz: ctrlr->f_max
9247 11:45:01.832247 0.400 MHz: ctrlr->f_min
9248 11:45:01.835050 0x40ff8080: ctrlr->voltages
9249 11:45:01.835268 sclk: 390625
9250 11:45:01.838327 Bus Width = 1
9251 11:45:01.838532 sclk: 390625
9252 11:45:01.841413 Bus Width = 1
9253 11:45:01.841621 Early init status = 3
9254 11:45:01.848375 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9255 11:45:01.851580 in-header: 03 fc 00 00 01 00 00 00
9256 11:45:01.851728 in-data: 00
9257 11:45:01.858039 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9258 11:45:01.861690 in-header: 03 fd 00 00 00 00 00 00
9259 11:45:01.864812 in-data:
9260 11:45:01.867979 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9261 11:45:01.871804 in-header: 03 fc 00 00 01 00 00 00
9262 11:45:01.874938 in-data: 00
9263 11:45:01.877912 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9264 11:45:01.883025 in-header: 03 fd 00 00 00 00 00 00
9265 11:45:01.886240 in-data:
9266 11:45:01.889802 [SSUSB] Setting up USB HOST controller...
9267 11:45:01.892745 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9268 11:45:01.896526 [SSUSB] phy power-on done.
9269 11:45:01.899539 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9270 11:45:01.906273 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9271 11:45:01.909418 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9272 11:45:01.916196 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9273 11:45:01.922687 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9274 11:45:01.929422 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9275 11:45:01.936211 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9276 11:45:01.942571 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9277 11:45:01.945807 SPM: binary array size = 0x9dc
9278 11:45:01.949647 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9279 11:45:01.956078 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9280 11:45:01.962408 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9281 11:45:01.969294 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9282 11:45:01.972373 configure_display: Starting display init
9283 11:45:02.006488 anx7625_power_on_init: Init interface.
9284 11:45:02.009870 anx7625_disable_pd_protocol: Disabled PD feature.
9285 11:45:02.013105 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9286 11:45:02.041256 anx7625_start_dp_work: Secure OCM version=00
9287 11:45:02.044389 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9288 11:45:02.058919 sp_tx_get_edid_block: EDID Block = 1
9289 11:45:02.161695 Extracted contents:
9290 11:45:02.164826 header: 00 ff ff ff ff ff ff 00
9291 11:45:02.168046 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9292 11:45:02.171241 version: 01 04
9293 11:45:02.174882 basic params: 95 1f 11 78 0a
9294 11:45:02.178499 chroma info: 76 90 94 55 54 90 27 21 50 54
9295 11:45:02.181610 established: 00 00 00
9296 11:45:02.188256 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9297 11:45:02.191368 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9298 11:45:02.197754 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9299 11:45:02.204663 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9300 11:45:02.210815 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9301 11:45:02.214631 extensions: 00
9302 11:45:02.214731 checksum: fb
9303 11:45:02.214795
9304 11:45:02.217670 Manufacturer: IVO Model 57d Serial Number 0
9305 11:45:02.221279 Made week 0 of 2020
9306 11:45:02.221359 EDID version: 1.4
9307 11:45:02.224558 Digital display
9308 11:45:02.227659 6 bits per primary color channel
9309 11:45:02.227741 DisplayPort interface
9310 11:45:02.231090 Maximum image size: 31 cm x 17 cm
9311 11:45:02.234834 Gamma: 220%
9312 11:45:02.235526 Check DPMS levels
9313 11:45:02.237749 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9314 11:45:02.244376 First detailed timing is preferred timing
9315 11:45:02.244955 Established timings supported:
9316 11:45:02.247990 Standard timings supported:
9317 11:45:02.251010 Detailed timings
9318 11:45:02.254705 Hex of detail: 383680a07038204018303c0035ae10000019
9319 11:45:02.257971 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9320 11:45:02.264283 0780 0798 07c8 0820 hborder 0
9321 11:45:02.268175 0438 043b 0447 0458 vborder 0
9322 11:45:02.271264 -hsync -vsync
9323 11:45:02.271726 Did detailed timing
9324 11:45:02.277638 Hex of detail: 000000000000000000000000000000000000
9325 11:45:02.278060 Manufacturer-specified data, tag 0
9326 11:45:02.284406 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9327 11:45:02.287995 ASCII string: InfoVision
9328 11:45:02.291162 Hex of detail: 000000fe00523134304e574635205248200a
9329 11:45:02.294430 ASCII string: R140NWF5 RH
9330 11:45:02.294980 Checksum
9331 11:45:02.297522 Checksum: 0xfb (valid)
9332 11:45:02.300834 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9333 11:45:02.304601 DSI data_rate: 832800000 bps
9334 11:45:02.310737 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9335 11:45:02.313964 anx7625_parse_edid: pixelclock(138800).
9336 11:45:02.317746 hactive(1920), hsync(48), hfp(24), hbp(88)
9337 11:45:02.320550 vactive(1080), vsync(12), vfp(3), vbp(17)
9338 11:45:02.324190 anx7625_dsi_config: config dsi.
9339 11:45:02.330778 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9340 11:45:02.343098 anx7625_dsi_config: success to config DSI
9341 11:45:02.346675 anx7625_dp_start: MIPI phy setup OK.
9342 11:45:02.350433 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9343 11:45:02.353485 mtk_ddp_mode_set invalid vrefresh 60
9344 11:45:02.356621 main_disp_path_setup
9345 11:45:02.356752 ovl_layer_smi_id_en
9346 11:45:02.359993 ovl_layer_smi_id_en
9347 11:45:02.360087 ccorr_config
9348 11:45:02.360162 aal_config
9349 11:45:02.363195 gamma_config
9350 11:45:02.363294 postmask_config
9351 11:45:02.366540 dither_config
9352 11:45:02.370401 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9353 11:45:02.376836 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9354 11:45:02.379865 Root Device init finished in 551 msecs
9355 11:45:02.383544 CPU_CLUSTER: 0 init
9356 11:45:02.389941 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9357 11:45:02.393351 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9358 11:45:02.396504 APU_MBOX 0x190000b0 = 0x10001
9359 11:45:02.399520 APU_MBOX 0x190001b0 = 0x10001
9360 11:45:02.403314 APU_MBOX 0x190005b0 = 0x10001
9361 11:45:02.406466 APU_MBOX 0x190006b0 = 0x10001
9362 11:45:02.409718 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9363 11:45:02.422546 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9364 11:45:02.434649 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9365 11:45:02.441924 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9366 11:45:02.453179 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9367 11:45:02.462373 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9368 11:45:02.465536 CPU_CLUSTER: 0 init finished in 81 msecs
9369 11:45:02.469023 Devices initialized
9370 11:45:02.472816 Show all devs... After init.
9371 11:45:02.473097 Root Device: enabled 1
9372 11:45:02.476099 CPU_CLUSTER: 0: enabled 1
9373 11:45:02.479094 CPU: 00: enabled 1
9374 11:45:02.482412 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9375 11:45:02.486133 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9376 11:45:02.488918 ELOG: NV offset 0x57f000 size 0x1000
9377 11:45:02.495650 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9378 11:45:02.502491 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9379 11:45:02.506090 ELOG: Event(17) added with size 13 at 2023-06-15 11:45:02 UTC
9380 11:45:02.511947 out: cmd=0x121: 03 db 21 01 00 00 00 00
9381 11:45:02.515701 in-header: 03 db 00 00 2c 00 00 00
9382 11:45:02.529078 in-data: 84 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9383 11:45:02.531848 ELOG: Event(A1) added with size 10 at 2023-06-15 11:45:02 UTC
9384 11:45:02.538689 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9385 11:45:02.545487 ELOG: Event(A0) added with size 9 at 2023-06-15 11:45:02 UTC
9386 11:45:02.548550 elog_add_boot_reason: Logged dev mode boot
9387 11:45:02.555322 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9388 11:45:02.555917 Finalize devices...
9389 11:45:02.558826 Devices finalized
9390 11:45:02.562426 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9391 11:45:02.565647 Writing coreboot table at 0xffe64000
9392 11:45:02.571948 0. 000000000010a000-0000000000113fff: RAMSTAGE
9393 11:45:02.575668 1. 0000000040000000-00000000400fffff: RAM
9394 11:45:02.578876 2. 0000000040100000-000000004032afff: RAMSTAGE
9395 11:45:02.582065 3. 000000004032b000-00000000545fffff: RAM
9396 11:45:02.585221 4. 0000000054600000-000000005465ffff: BL31
9397 11:45:02.588728 5. 0000000054660000-00000000ffe63fff: RAM
9398 11:45:02.595531 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9399 11:45:02.598837 7. 0000000100000000-000000023fffffff: RAM
9400 11:45:02.601899 Passing 5 GPIOs to payload:
9401 11:45:02.605140 NAME | PORT | POLARITY | VALUE
9402 11:45:02.612061 EC in RW | 0x000000aa | low | undefined
9403 11:45:02.615259 EC interrupt | 0x00000005 | low | undefined
9404 11:45:02.618516 TPM interrupt | 0x000000ab | high | undefined
9405 11:45:02.625279 SD card detect | 0x00000011 | high | undefined
9406 11:45:02.628672 speaker enable | 0x00000093 | high | undefined
9407 11:45:02.631717 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9408 11:45:02.635247 in-header: 03 f9 00 00 02 00 00 00
9409 11:45:02.638278 in-data: 02 00
9410 11:45:02.641513 ADC[4]: Raw value=899852 ID=7
9411 11:45:02.642009 ADC[3]: Raw value=213336 ID=1
9412 11:45:02.645296 RAM Code: 0x71
9413 11:45:02.648375 ADC[6]: Raw value=74187 ID=0
9414 11:45:02.648804 ADC[5]: Raw value=212598 ID=1
9415 11:45:02.651429 SKU Code: 0x1
9416 11:45:02.658511 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9417 11:45:02.659068 coreboot table: 964 bytes.
9418 11:45:02.661689 IMD ROOT 0. 0xfffff000 0x00001000
9419 11:45:02.665273 IMD SMALL 1. 0xffffe000 0x00001000
9420 11:45:02.668589 RO MCACHE 2. 0xffffc000 0x00001104
9421 11:45:02.671634 CONSOLE 3. 0xfff7c000 0x00080000
9422 11:45:02.675296 FMAP 4. 0xfff7b000 0x00000452
9423 11:45:02.678498 TIME STAMP 5. 0xfff7a000 0x00000910
9424 11:45:02.681779 VBOOT WORK 6. 0xfff66000 0x00014000
9425 11:45:02.684830 RAMOOPS 7. 0xffe66000 0x00100000
9426 11:45:02.688621 COREBOOT 8. 0xffe64000 0x00002000
9427 11:45:02.691852 IMD small region:
9428 11:45:02.694817 IMD ROOT 0. 0xffffec00 0x00000400
9429 11:45:02.698698 VPD 1. 0xffffeba0 0x0000004c
9430 11:45:02.701610 MMC STATUS 2. 0xffffeb80 0x00000004
9431 11:45:02.705308 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9432 11:45:02.708223 Probing TPM: done!
9433 11:45:02.711430 Connected to device vid:did:rid of 1ae0:0028:00
9434 11:45:02.722379 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9435 11:45:02.725540 Initialized TPM device CR50 revision 0
9436 11:45:02.729302 Checking cr50 for pending updates
9437 11:45:02.733213 Reading cr50 TPM mode
9438 11:45:02.741423 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9439 11:45:02.748027 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9440 11:45:02.788600 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9441 11:45:02.791659 Checking segment from ROM address 0x40100000
9442 11:45:02.794963 Checking segment from ROM address 0x4010001c
9443 11:45:02.801709 Loading segment from ROM address 0x40100000
9444 11:45:02.802104 code (compression=0)
9445 11:45:02.811370 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9446 11:45:02.818345 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9447 11:45:02.818501 it's not compressed!
9448 11:45:02.825136 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9449 11:45:02.828272 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9450 11:45:02.849087 Loading segment from ROM address 0x4010001c
9451 11:45:02.849677 Entry Point 0x80000000
9452 11:45:02.851976 Loaded segments
9453 11:45:02.855656 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9454 11:45:02.861847 Jumping to boot code at 0x80000000(0xffe64000)
9455 11:45:02.868383 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9456 11:45:02.874969 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9457 11:45:02.883003 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9458 11:45:02.886175 Checking segment from ROM address 0x40100000
9459 11:45:02.889397 Checking segment from ROM address 0x4010001c
9460 11:45:02.896408 Loading segment from ROM address 0x40100000
9461 11:45:02.896533 code (compression=1)
9462 11:45:02.903157 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9463 11:45:02.913165 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9464 11:45:02.913333 using LZMA
9465 11:45:02.921104 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9466 11:45:02.928024 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9467 11:45:02.931184 Loading segment from ROM address 0x4010001c
9468 11:45:02.931268 Entry Point 0x54601000
9469 11:45:02.934970 Loaded segments
9470 11:45:02.937935 NOTICE: MT8192 bl31_setup
9471 11:45:02.944937 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9472 11:45:02.948090 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9473 11:45:02.951641 WARNING: region 0:
9474 11:45:02.954789 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 11:45:02.954872 WARNING: region 1:
9476 11:45:02.961621 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9477 11:45:02.964780 WARNING: region 2:
9478 11:45:02.968365 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9479 11:45:02.971437 WARNING: region 3:
9480 11:45:02.975204 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 11:45:02.978218 WARNING: region 4:
9482 11:45:02.981936 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 11:45:02.985175 WARNING: region 5:
9484 11:45:02.988286 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 11:45:02.991437 WARNING: region 6:
9486 11:45:02.995254 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 11:45:02.995399 WARNING: region 7:
9488 11:45:03.001453 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 11:45:03.008261 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9490 11:45:03.011507 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9491 11:45:03.015209 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9492 11:45:03.022102 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9493 11:45:03.025434 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9494 11:45:03.028917 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9495 11:45:03.035524 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9496 11:45:03.038691 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9497 11:45:03.044986 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9498 11:45:03.048876 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9499 11:45:03.051764 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9500 11:45:03.058200 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9501 11:45:03.061497 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9502 11:45:03.065223 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9503 11:45:03.072007 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9504 11:45:03.075006 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9505 11:45:03.082342 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9506 11:45:03.085207 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9507 11:45:03.088415 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9508 11:45:03.095471 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9509 11:45:03.098660 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9510 11:45:03.101954 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9511 11:45:03.108509 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9512 11:45:03.111748 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9513 11:45:03.118722 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9514 11:45:03.121850 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9515 11:45:03.124876 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9516 11:45:03.131903 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9517 11:45:03.135246 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9518 11:45:03.141630 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9519 11:45:03.144864 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9520 11:45:03.147914 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9521 11:45:03.154614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9522 11:45:03.158485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9523 11:45:03.161665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9524 11:45:03.164824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9525 11:45:03.171608 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9526 11:45:03.174695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9527 11:45:03.178210 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9528 11:45:03.181362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9529 11:45:03.188336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9530 11:45:03.191885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9531 11:45:03.194833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9532 11:45:03.198146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9533 11:45:03.205073 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9534 11:45:03.208109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9535 11:45:03.211235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9536 11:45:03.215072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9537 11:45:03.221273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9538 11:45:03.225077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9539 11:45:03.231812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9540 11:45:03.234820 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9541 11:45:03.241337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9542 11:45:03.245080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9543 11:45:03.248148 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9544 11:45:03.254936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9545 11:45:03.258257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9546 11:45:03.265466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9547 11:45:03.268162 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9548 11:45:03.274899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9549 11:45:03.278091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9550 11:45:03.281622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9551 11:45:03.288094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9552 11:45:03.291908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9553 11:45:03.298273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9554 11:45:03.301347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9555 11:45:03.307837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9556 11:45:03.311459 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9557 11:45:03.314577 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9558 11:45:03.321677 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9559 11:45:03.324808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9560 11:45:03.331696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9561 11:45:03.334640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9562 11:45:03.341352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9563 11:45:03.344497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9564 11:45:03.347515 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9565 11:45:03.354563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9566 11:45:03.357583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9567 11:45:03.364046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9568 11:45:03.367839 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9569 11:45:03.374019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9570 11:45:03.377803 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9571 11:45:03.384086 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9572 11:45:03.387904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9573 11:45:03.390875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9574 11:45:03.397788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9575 11:45:03.400809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9576 11:45:03.407705 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9577 11:45:03.410659 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9578 11:45:03.417685 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9579 11:45:03.420853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9580 11:45:03.424095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9581 11:45:03.430962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9582 11:45:03.434072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9583 11:45:03.441072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9584 11:45:03.444280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9585 11:45:03.447450 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9586 11:45:03.454424 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9587 11:45:03.457642 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9588 11:45:03.460830 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9589 11:45:03.464809 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9590 11:45:03.471697 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9591 11:45:03.474689 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9592 11:45:03.481265 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9593 11:45:03.485074 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9594 11:45:03.488104 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9595 11:45:03.494687 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9596 11:45:03.497739 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9597 11:45:03.504428 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9598 11:45:03.508135 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9599 11:45:03.511219 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9600 11:45:03.518489 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9601 11:45:03.521643 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9602 11:45:03.527903 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9603 11:45:03.531723 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9604 11:45:03.535246 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9605 11:45:03.541158 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9606 11:45:03.544992 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9607 11:45:03.548283 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9608 11:45:03.551486 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9609 11:45:03.558618 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9610 11:45:03.561526 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9611 11:45:03.564579 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9612 11:45:03.567723 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9613 11:45:03.574914 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9614 11:45:03.578228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9615 11:45:03.584592 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9616 11:45:03.588208 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9617 11:45:03.591218 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9618 11:45:03.598066 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9619 11:45:03.601585 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9620 11:45:03.607771 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9621 11:45:03.611238 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9622 11:45:03.614407 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9623 11:45:03.621202 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9624 11:45:03.624496 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9625 11:45:03.631535 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9626 11:45:03.634885 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9627 11:45:03.637923 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9628 11:45:03.644750 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9629 11:45:03.647913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9630 11:45:03.650839 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9631 11:45:03.657699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9632 11:45:03.661357 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9633 11:45:03.668294 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9634 11:45:03.671236 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9635 11:45:03.674548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9636 11:45:03.681770 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9637 11:45:03.684616 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9638 11:45:03.691712 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9639 11:45:03.694714 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9640 11:45:03.698053 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9641 11:45:03.704717 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9642 11:45:03.707858 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9643 11:45:03.711456 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9644 11:45:03.718066 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9645 11:45:03.721540 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9646 11:45:03.728066 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9647 11:45:03.731266 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9648 11:45:03.734645 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9649 11:45:03.740812 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9650 11:45:03.744678 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9651 11:45:03.750869 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9652 11:45:03.754155 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9653 11:45:03.758030 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9654 11:45:03.764176 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9655 11:45:03.767764 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9656 11:45:03.771049 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9657 11:45:03.778206 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9658 11:45:03.781364 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9659 11:45:03.788126 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9660 11:45:03.791288 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9661 11:45:03.794743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9662 11:45:03.800956 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9663 11:45:03.804402 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9664 11:45:03.811081 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9665 11:45:03.814237 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9666 11:45:03.817332 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9667 11:45:03.823867 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9668 11:45:03.827409 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9669 11:45:03.833870 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9670 11:45:03.837643 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9671 11:45:03.840955 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9672 11:45:03.847254 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9673 11:45:03.851206 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9674 11:45:03.857369 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9675 11:45:03.860454 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9676 11:45:03.864019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9677 11:45:03.870532 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9678 11:45:03.873842 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9679 11:45:03.880260 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9680 11:45:03.883404 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9681 11:45:03.887239 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9682 11:45:03.893731 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9683 11:45:03.896866 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9684 11:45:03.903779 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9685 11:45:03.906887 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9686 11:45:03.913513 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9687 11:45:03.917187 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9688 11:45:03.920064 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9689 11:45:03.926788 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9690 11:45:03.930427 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9691 11:45:03.937166 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9692 11:45:03.940235 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9693 11:45:03.943409 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9694 11:45:03.950034 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9695 11:45:03.953368 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9696 11:45:03.960297 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9697 11:45:03.963397 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9698 11:45:03.969595 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9699 11:45:03.973315 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9700 11:45:03.976503 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9701 11:45:03.983382 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9702 11:45:03.986539 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9703 11:45:03.992946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9704 11:45:03.996183 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9705 11:45:04.002966 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9706 11:45:04.006118 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9707 11:45:04.009512 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9708 11:45:04.016381 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9709 11:45:04.019424 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9710 11:45:04.026036 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9711 11:45:04.029553 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9712 11:45:04.032817 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9713 11:45:04.039456 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9714 11:45:04.042509 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9715 11:45:04.049435 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9716 11:45:04.053119 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9717 11:45:04.056271 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9718 11:45:04.062320 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9719 11:45:04.066102 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9720 11:45:04.069396 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9721 11:45:04.072690 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9722 11:45:04.079139 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9723 11:45:04.082697 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9724 11:45:04.086020 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9725 11:45:04.092533 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9726 11:45:04.095794 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9727 11:45:04.099155 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9728 11:45:04.105756 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9729 11:45:04.108851 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9730 11:45:04.115602 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9731 11:45:04.119175 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9732 11:45:04.122460 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9733 11:45:04.128970 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9734 11:45:04.132073 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9735 11:45:04.139111 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9736 11:45:04.142093 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9737 11:45:04.145720 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9738 11:45:04.152099 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9739 11:45:04.155036 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9740 11:45:04.158379 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9741 11:45:04.165316 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9742 11:45:04.169025 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9743 11:45:04.172222 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9744 11:45:04.178618 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9745 11:45:04.182316 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9746 11:45:04.188763 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9747 11:45:04.191808 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9748 11:45:04.195263 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9749 11:45:04.201933 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9750 11:45:04.205120 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9751 11:45:04.208248 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9752 11:45:04.215112 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9753 11:45:04.218742 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9754 11:45:04.221765 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9755 11:45:04.228159 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9756 11:45:04.231682 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9757 11:45:04.234805 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9758 11:45:04.241556 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9759 11:45:04.244705 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9760 11:45:04.248237 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9761 11:45:04.251343 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9762 11:45:04.254647 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9763 11:45:04.261840 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9764 11:45:04.264742 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9765 11:45:04.267999 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9766 11:45:04.271265 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9767 11:45:04.278230 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9768 11:45:04.281603 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9769 11:45:04.284749 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9770 11:45:04.291754 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9771 11:45:04.295002 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9772 11:45:04.298136 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9773 11:45:04.304775 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9774 11:45:04.307978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9775 11:45:04.314620 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9776 11:45:04.318017 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9777 11:45:04.324287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9778 11:45:04.327662 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9779 11:45:04.331329 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9780 11:45:04.338034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9781 11:45:04.341196 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9782 11:45:04.348127 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9783 11:45:04.351312 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9784 11:45:04.354379 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9785 11:45:04.361144 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9786 11:45:04.365027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9787 11:45:04.371808 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9788 11:45:04.374954 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9789 11:45:04.378410 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9790 11:45:04.384590 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9791 11:45:04.387861 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9792 11:45:04.394984 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9793 11:45:04.398349 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9794 11:45:04.401650 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9795 11:45:04.407844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9796 11:45:04.411098 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9797 11:45:04.418303 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9798 11:45:04.421371 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9799 11:45:04.427422 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9800 11:45:04.431204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9801 11:45:04.434554 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9802 11:45:04.441069 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9803 11:45:04.443955 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9804 11:45:04.451214 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9805 11:45:04.454400 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9806 11:45:04.457782 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9807 11:45:04.463969 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9808 11:45:04.467821 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9809 11:45:04.474488 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9810 11:45:04.477678 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9811 11:45:04.480711 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9812 11:45:04.487390 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9813 11:45:04.490853 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9814 11:45:04.497395 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9815 11:45:04.501318 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9816 11:45:04.507956 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9817 11:45:04.511139 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9818 11:45:04.514266 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9819 11:45:04.520688 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9820 11:45:04.523881 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9821 11:45:04.530886 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9822 11:45:04.534082 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9823 11:45:04.537278 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9824 11:45:04.543581 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9825 11:45:04.547127 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9826 11:45:04.554029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9827 11:45:04.557038 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9828 11:45:04.560431 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9829 11:45:04.567170 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9830 11:45:04.570370 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9831 11:45:04.576827 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9832 11:45:04.580925 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9833 11:45:04.587243 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9834 11:45:04.590246 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9835 11:45:04.593445 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9836 11:45:04.599915 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9837 11:45:04.603705 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9838 11:45:04.610038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9839 11:45:04.613257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9840 11:45:04.616538 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9841 11:45:04.623290 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9842 11:45:04.626494 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9843 11:45:04.633566 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9844 11:45:04.636596 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9845 11:45:04.639983 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9846 11:45:04.646739 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9847 11:45:04.649788 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9848 11:45:04.656313 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9849 11:45:04.659919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9850 11:45:04.666077 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9851 11:45:04.669918 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9852 11:45:04.676228 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9853 11:45:04.679666 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9854 11:45:04.682707 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9855 11:45:04.689882 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9856 11:45:04.692876 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9857 11:45:04.699603 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9858 11:45:04.702839 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9859 11:45:04.709166 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9860 11:45:04.712913 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9861 11:45:04.719210 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9862 11:45:04.722618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9863 11:45:04.725782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9864 11:45:04.732272 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9865 11:45:04.735786 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9866 11:45:04.742747 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9867 11:45:04.745533 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9868 11:45:04.752056 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9869 11:45:04.755561 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9870 11:45:04.761839 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9871 11:45:04.765635 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9872 11:45:04.768811 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9873 11:45:04.774963 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9874 11:45:04.779074 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9875 11:45:04.785573 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9876 11:45:04.788600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9877 11:45:04.795031 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9878 11:45:04.798973 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9879 11:45:04.802319 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9880 11:45:04.808282 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9881 11:45:04.811954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9882 11:45:04.819125 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9883 11:45:04.821700 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9884 11:45:04.828718 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9885 11:45:04.832329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9886 11:45:04.835545 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9887 11:45:04.842185 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9888 11:45:04.845037 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9889 11:45:04.851767 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9890 11:45:04.854919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9891 11:45:04.858084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9892 11:45:04.864797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9893 11:45:04.868063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9894 11:45:04.874921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9895 11:45:04.877957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9896 11:45:04.884967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9897 11:45:04.888118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9898 11:45:04.894559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9899 11:45:04.897876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9900 11:45:04.904198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9901 11:45:04.908298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9902 11:45:04.914720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9903 11:45:04.917795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9904 11:45:04.924786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9905 11:45:04.928068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9906 11:45:04.934810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9907 11:45:04.938016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9908 11:45:04.944603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9909 11:45:04.947687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9910 11:45:04.954093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9911 11:45:04.957779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9912 11:45:04.964304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9913 11:45:04.967178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9914 11:45:04.973956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9915 11:45:04.977805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9916 11:45:04.984051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9917 11:45:04.987150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9918 11:45:04.994014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9919 11:45:04.997192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9920 11:45:05.003953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9921 11:45:05.007482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9922 11:45:05.014296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9923 11:45:05.017630 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9924 11:45:05.021029 INFO: [APUAPC] vio 0
9925 11:45:05.024019 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9926 11:45:05.027333 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9927 11:45:05.030680 INFO: [APUAPC] D0_APC_0: 0x400510
9928 11:45:05.034014 INFO: [APUAPC] D0_APC_1: 0x0
9929 11:45:05.037195 INFO: [APUAPC] D0_APC_2: 0x1540
9930 11:45:05.040414 INFO: [APUAPC] D0_APC_3: 0x0
9931 11:45:05.043709 INFO: [APUAPC] D1_APC_0: 0xffffffff
9932 11:45:05.047003 INFO: [APUAPC] D1_APC_1: 0xffffffff
9933 11:45:05.050160 INFO: [APUAPC] D1_APC_2: 0x3fffff
9934 11:45:05.054084 INFO: [APUAPC] D1_APC_3: 0x0
9935 11:45:05.057400 INFO: [APUAPC] D2_APC_0: 0xffffffff
9936 11:45:05.060625 INFO: [APUAPC] D2_APC_1: 0xffffffff
9937 11:45:05.063618 INFO: [APUAPC] D2_APC_2: 0x3fffff
9938 11:45:05.066988 INFO: [APUAPC] D2_APC_3: 0x0
9939 11:45:05.070717 INFO: [APUAPC] D3_APC_0: 0xffffffff
9940 11:45:05.073808 INFO: [APUAPC] D3_APC_1: 0xffffffff
9941 11:45:05.076898 INFO: [APUAPC] D3_APC_2: 0x3fffff
9942 11:45:05.080637 INFO: [APUAPC] D3_APC_3: 0x0
9943 11:45:05.083855 INFO: [APUAPC] D4_APC_0: 0xffffffff
9944 11:45:05.086852 INFO: [APUAPC] D4_APC_1: 0xffffffff
9945 11:45:05.090205 INFO: [APUAPC] D4_APC_2: 0x3fffff
9946 11:45:05.093396 INFO: [APUAPC] D4_APC_3: 0x0
9947 11:45:05.097101 INFO: [APUAPC] D5_APC_0: 0xffffffff
9948 11:45:05.100247 INFO: [APUAPC] D5_APC_1: 0xffffffff
9949 11:45:05.103436 INFO: [APUAPC] D5_APC_2: 0x3fffff
9950 11:45:05.106880 INFO: [APUAPC] D5_APC_3: 0x0
9951 11:45:05.110073 INFO: [APUAPC] D6_APC_0: 0xffffffff
9952 11:45:05.113411 INFO: [APUAPC] D6_APC_1: 0xffffffff
9953 11:45:05.116604 INFO: [APUAPC] D6_APC_2: 0x3fffff
9954 11:45:05.119926 INFO: [APUAPC] D6_APC_3: 0x0
9955 11:45:05.123677 INFO: [APUAPC] D7_APC_0: 0xffffffff
9956 11:45:05.126832 INFO: [APUAPC] D7_APC_1: 0xffffffff
9957 11:45:05.130459 INFO: [APUAPC] D7_APC_2: 0x3fffff
9958 11:45:05.133609 INFO: [APUAPC] D7_APC_3: 0x0
9959 11:45:05.137066 INFO: [APUAPC] D8_APC_0: 0xffffffff
9960 11:45:05.140124 INFO: [APUAPC] D8_APC_1: 0xffffffff
9961 11:45:05.143572 INFO: [APUAPC] D8_APC_2: 0x3fffff
9962 11:45:05.144035 INFO: [APUAPC] D8_APC_3: 0x0
9963 11:45:05.146880 INFO: [APUAPC] D9_APC_0: 0xffffffff
9964 11:45:05.153245 INFO: [APUAPC] D9_APC_1: 0xffffffff
9965 11:45:05.156514 INFO: [APUAPC] D9_APC_2: 0x3fffff
9966 11:45:05.156980 INFO: [APUAPC] D9_APC_3: 0x0
9967 11:45:05.160414 INFO: [APUAPC] D10_APC_0: 0xffffffff
9968 11:45:05.166561 INFO: [APUAPC] D10_APC_1: 0xffffffff
9969 11:45:05.169750 INFO: [APUAPC] D10_APC_2: 0x3fffff
9970 11:45:05.170191 INFO: [APUAPC] D10_APC_3: 0x0
9971 11:45:05.173690 INFO: [APUAPC] D11_APC_0: 0xffffffff
9972 11:45:05.179988 INFO: [APUAPC] D11_APC_1: 0xffffffff
9973 11:45:05.183190 INFO: [APUAPC] D11_APC_2: 0x3fffff
9974 11:45:05.183695 INFO: [APUAPC] D11_APC_3: 0x0
9975 11:45:05.186836 INFO: [APUAPC] D12_APC_0: 0xffffffff
9976 11:45:05.193606 INFO: [APUAPC] D12_APC_1: 0xffffffff
9977 11:45:05.196836 INFO: [APUAPC] D12_APC_2: 0x3fffff
9978 11:45:05.197266 INFO: [APUAPC] D12_APC_3: 0x0
9979 11:45:05.199943 INFO: [APUAPC] D13_APC_0: 0xffffffff
9980 11:45:05.206297 INFO: [APUAPC] D13_APC_1: 0xffffffff
9981 11:45:05.209628 INFO: [APUAPC] D13_APC_2: 0x3fffff
9982 11:45:05.210073 INFO: [APUAPC] D13_APC_3: 0x0
9983 11:45:05.216305 INFO: [APUAPC] D14_APC_0: 0xffffffff
9984 11:45:05.220203 INFO: [APUAPC] D14_APC_1: 0xffffffff
9985 11:45:05.223447 INFO: [APUAPC] D14_APC_2: 0x3fffff
9986 11:45:05.223876 INFO: [APUAPC] D14_APC_3: 0x0
9987 11:45:05.229950 INFO: [APUAPC] D15_APC_0: 0xffffffff
9988 11:45:05.233015 INFO: [APUAPC] D15_APC_1: 0xffffffff
9989 11:45:05.236889 INFO: [APUAPC] D15_APC_2: 0x3fffff
9990 11:45:05.237352 INFO: [APUAPC] D15_APC_3: 0x0
9991 11:45:05.240347 INFO: [APUAPC] APC_CON: 0x4
9992 11:45:05.243414 INFO: [NOCDAPC] D0_APC_0: 0x0
9993 11:45:05.246668 INFO: [NOCDAPC] D0_APC_1: 0x0
9994 11:45:05.250067 INFO: [NOCDAPC] D1_APC_0: 0x0
9995 11:45:05.253269 INFO: [NOCDAPC] D1_APC_1: 0xfff
9996 11:45:05.256658 INFO: [NOCDAPC] D2_APC_0: 0x0
9997 11:45:05.260122 INFO: [NOCDAPC] D2_APC_1: 0xfff
9998 11:45:05.263253 INFO: [NOCDAPC] D3_APC_0: 0x0
9999 11:45:05.266609 INFO: [NOCDAPC] D3_APC_1: 0xfff
10000 11:45:05.267039 INFO: [NOCDAPC] D4_APC_0: 0x0
10001 11:45:05.269637 INFO: [NOCDAPC] D4_APC_1: 0xfff
10002 11:45:05.273510 INFO: [NOCDAPC] D5_APC_0: 0x0
10003 11:45:05.276693 INFO: [NOCDAPC] D5_APC_1: 0xfff
10004 11:45:05.280038 INFO: [NOCDAPC] D6_APC_0: 0x0
10005 11:45:05.283203 INFO: [NOCDAPC] D6_APC_1: 0xfff
10006 11:45:05.286266 INFO: [NOCDAPC] D7_APC_0: 0x0
10007 11:45:05.289976 INFO: [NOCDAPC] D7_APC_1: 0xfff
10008 11:45:05.293131 INFO: [NOCDAPC] D8_APC_0: 0x0
10009 11:45:05.296280 INFO: [NOCDAPC] D8_APC_1: 0xfff
10010 11:45:05.296994 INFO: [NOCDAPC] D9_APC_0: 0x0
10011 11:45:05.299784 INFO: [NOCDAPC] D9_APC_1: 0xfff
10012 11:45:05.302725 INFO: [NOCDAPC] D10_APC_0: 0x0
10013 11:45:05.306596 INFO: [NOCDAPC] D10_APC_1: 0xfff
10014 11:45:05.309869 INFO: [NOCDAPC] D11_APC_0: 0x0
10015 11:45:05.312932 INFO: [NOCDAPC] D11_APC_1: 0xfff
10016 11:45:05.316096 INFO: [NOCDAPC] D12_APC_0: 0x0
10017 11:45:05.320173 INFO: [NOCDAPC] D12_APC_1: 0xfff
10018 11:45:05.323265 INFO: [NOCDAPC] D13_APC_0: 0x0
10019 11:45:05.325953 INFO: [NOCDAPC] D13_APC_1: 0xfff
10020 11:45:05.329987 INFO: [NOCDAPC] D14_APC_0: 0x0
10021 11:45:05.333299 INFO: [NOCDAPC] D14_APC_1: 0xfff
10022 11:45:05.336547 INFO: [NOCDAPC] D15_APC_0: 0x0
10023 11:45:05.339496 INFO: [NOCDAPC] D15_APC_1: 0xfff
10024 11:45:05.339950 INFO: [NOCDAPC] APC_CON: 0x4
10025 11:45:05.342743 INFO: [APUAPC] set_apusys_apc done
10026 11:45:05.346083 INFO: [DEVAPC] devapc_init done
10027 11:45:05.352958 INFO: GICv3 without legacy support detected.
10028 11:45:05.356149 INFO: ARM GICv3 driver initialized in EL3
10029 11:45:05.359619 INFO: Maximum SPI INTID supported: 639
10030 11:45:05.362949 INFO: BL31: Initializing runtime services
10031 11:45:05.369363 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10032 11:45:05.372656 INFO: SPM: enable CPC mode
10033 11:45:05.376353 INFO: mcdi ready for mcusys-off-idle and system suspend
10034 11:45:05.382909 INFO: BL31: Preparing for EL3 exit to normal world
10035 11:45:05.386309 INFO: Entry point address = 0x80000000
10036 11:45:05.386750 INFO: SPSR = 0x8
10037 11:45:05.393215
10038 11:45:05.393748
10039 11:45:05.394094
10040 11:45:05.396324 Starting depthcharge on Spherion...
10041 11:45:05.396916
10042 11:45:05.397291 Wipe memory regions:
10043 11:45:05.397606
10044 11:45:05.400082 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10045 11:45:05.400638 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10046 11:45:05.401179 Setting prompt string to ['asurada:']
10047 11:45:05.401573 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10048 11:45:05.402239 [0x00000040000000, 0x00000054600000)
10049 11:45:05.522303
10050 11:45:05.525220 [0x00000054660000, 0x00000080000000)
10051 11:45:05.782010
10052 11:45:05.782646 [0x000000821a7280, 0x000000ffe64000)
10053 11:45:06.526589
10054 11:45:06.527243 [0x00000100000000, 0x00000240000000)
10055 11:45:08.415415
10056 11:45:08.418464 Initializing XHCI USB controller at 0x11200000.
10057 11:45:09.456154
10058 11:45:09.459249 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10059 11:45:09.459527
10060 11:45:09.459704
10061 11:45:09.459867
10062 11:45:09.460321 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 11:45:09.561036 asurada: tftpboot 192.168.201.1 10742249/tftp-deploy-_g234_cb/kernel/image.itb 10742249/tftp-deploy-_g234_cb/kernel/cmdline
10065 11:45:09.561874 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 11:45:09.562579 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10067 11:45:09.568914 tftpboot 192.168.201.1 10742249/tftp-deploy-_g234_cb/kernel/image.itp-deploy-_g234_cb/kernel/cmdline
10068 11:45:09.569526
10069 11:45:09.570042 Waiting for link
10070 11:45:09.727223
10071 11:45:09.727851 R8152: Initializing
10072 11:45:09.728555
10073 11:45:09.730528 Version 6 (ocp_data = 5c30)
10074 11:45:09.731159
10075 11:45:09.733928 R8152: Done initializing
10076 11:45:09.734380
10077 11:45:09.734724 Adding net device
10078 11:45:11.776140
10079 11:45:11.776719 done.
10080 11:45:11.777351
10081 11:45:11.778123 MAC: 00:24:32:30:78:52
10082 11:45:11.778824
10083 11:45:11.779580 Sending DHCP discover... done.
10084 11:45:11.779989
10085 11:45:11.782698 Waiting for reply... done.
10086 11:45:11.783309
10087 11:45:11.785876 Sending DHCP request... done.
10088 11:45:11.786300
10089 11:45:12.460877 Waiting for reply... done.
10090 11:45:12.461574
10091 11:45:12.462224 My ip is 192.168.201.14
10092 11:45:12.462843
10093 11:45:12.463899 The DHCP server ip is 192.168.201.1
10094 11:45:12.464447
10095 11:45:12.470162 TFTP server IP predefined by user: 192.168.201.1
10096 11:45:12.470717
10097 11:45:12.476731 Bootfile predefined by user: 10742249/tftp-deploy-_g234_cb/kernel/image.itb
10098 11:45:12.477385
10099 11:45:12.480105 Sending tftp read request... done.
10100 11:45:12.480821
10101 11:45:12.487439 Waiting for the transfer...
10102 11:45:12.488060
10103 11:45:13.110098 00000000 ################################################################
10104 11:45:13.110599
10105 11:45:13.718496 00080000 ################################################################
10106 11:45:13.718759
10107 11:45:14.278777 00100000 ################################################################
10108 11:45:14.278911
10109 11:45:14.841559 00180000 ################################################################
10110 11:45:14.841703
10111 11:45:15.381515 00200000 ################################################################
10112 11:45:15.381677
10113 11:45:15.913234 00280000 ################################################################
10114 11:45:15.913399
10115 11:45:16.445700 00300000 ################################################################
10116 11:45:16.445875
10117 11:45:16.979820 00380000 ################################################################
10118 11:45:16.979973
10119 11:45:17.497257 00400000 ################################################################
10120 11:45:17.497424
10121 11:45:18.016993 00480000 ################################################################
10122 11:45:18.017158
10123 11:45:18.551239 00500000 ################################################################
10124 11:45:18.551416
10125 11:45:19.070921 00580000 ################################################################
10126 11:45:19.071057
10127 11:45:19.602673 00600000 ################################################################
10128 11:45:19.603434
10129 11:45:20.187303 00680000 ################################################################
10130 11:45:20.187821
10131 11:45:20.786029 00700000 ################################################################
10132 11:45:20.786624
10133 11:45:21.354224 00780000 ################################################################
10134 11:45:21.354388
10135 11:45:21.867244 00800000 ################################################################
10136 11:45:21.867427
10137 11:45:22.383220 00880000 ################################################################
10138 11:45:22.383369
10139 11:45:22.896852 00900000 ################################################################
10140 11:45:22.897026
10141 11:45:23.414968 00980000 ################################################################
10142 11:45:23.415104
10143 11:45:23.935250 00a00000 ################################################################
10144 11:45:23.935392
10145 11:45:24.449514 00a80000 ################################################################
10146 11:45:24.449650
10147 11:45:24.974373 00b00000 ################################################################
10148 11:45:24.974519
10149 11:45:25.491487 00b80000 ################################################################
10150 11:45:25.491642
10151 11:45:26.009334 00c00000 ################################################################
10152 11:45:26.009509
10153 11:45:29.853425 00c80000 ################################################################
10154 11:45:29.853609
10155 11:45:29.853710 00d00000 ################################################################
10156 11:45:29.853813
10157 11:45:29.853916 00d80000 ################################################################
10158 11:45:29.854017
10159 11:45:29.854135 00e00000 ################################################################
10160 11:45:29.854236
10161 11:45:29.854334 00e80000 ################################################################
10162 11:45:29.854441
10163 11:45:29.854538 00f00000 ################################################################
10164 11:45:29.854652
10165 11:45:29.854743 00f80000 ################################################################
10166 11:45:29.854807
10167 11:45:30.243752 01000000 ################################################################
10168 11:45:30.243889
10169 11:45:30.807763 01080000 ################################################################
10170 11:45:30.807943
10171 11:45:31.372698 01100000 ################################################################
10172 11:45:31.372862
10173 11:45:31.910785 01180000 ################################################################
10174 11:45:31.910930
10175 11:45:32.455070 01200000 ################################################################
10176 11:45:32.455213
10177 11:45:32.984501 01280000 ################################################################
10178 11:45:32.984645
10179 11:45:33.542949 01300000 ################################################################
10180 11:45:33.543087
10181 11:45:34.117488 01380000 ################################################################
10182 11:45:34.117631
10183 11:45:34.736867 01400000 ################################################################
10184 11:45:34.737391
10185 11:45:38.067654 01480000 ################################################################
10186 11:45:38.071658
10187 11:45:38.071815 01500000 ################################################################
10188 11:45:38.071929
10189 11:45:38.072034 01580000 ################################################################
10190 11:45:38.072135
10191 11:45:38.072237 01600000 ################################################################
10192 11:45:38.072347
10193 11:45:38.072449 01680000 ################################################################
10194 11:45:38.072564
10195 11:45:38.419753 01700000 ################################################################
10196 11:45:38.419897
10197 11:45:38.995060 01780000 ################################################################
10198 11:45:38.995199
10199 11:45:39.565145 01800000 ################################################################
10200 11:45:39.565309
10201 11:45:40.173256 01880000 ################################################################
10202 11:45:40.173991
10203 11:45:40.821234 01900000 ################################################################
10204 11:45:40.821757
10205 11:45:41.481197 01980000 ################################################################
10206 11:45:41.481777
10207 11:45:42.154540 01a00000 ################################################################
10208 11:45:42.155273
10209 11:45:42.811913 01a80000 ################################################################
10210 11:45:42.812731
10211 11:45:43.382501 01b00000 ################################################################
10212 11:45:43.383007
10213 11:45:43.989339 01b80000 ################################################################
10214 11:45:43.990125
10215 11:45:44.615165 01c00000 ################################################################
10216 11:45:44.615741
10217 11:45:45.216685 01c80000 ################################################################
10218 11:45:45.217214
10219 11:45:45.867657 01d00000 ################################################################
10220 11:45:45.868355
10221 11:45:46.554192 01d80000 ################################################################
10222 11:45:46.554730
10223 11:45:47.239444 01e00000 ################################################################
10224 11:45:47.240057
10225 11:45:47.882390 01e80000 ################################################################
10226 11:45:47.882751
10227 11:45:48.515703 01f00000 ################################################################
10228 11:45:48.516289
10229 11:45:49.163941 01f80000 ################################################################
10230 11:45:49.164519
10231 11:45:52.391677 02000000 ################################################################
10232 11:45:52.392504
10233 11:45:52.393163 02080000 ################################################################
10234 11:45:52.393821
10235 11:45:52.394264 02100000 ################################################################
10236 11:45:52.394384
10237 11:45:52.394503 02180000 ################################################################
10238 11:45:52.394625
10239 11:45:52.394740 02200000 ################################################################
10240 11:45:52.394860
10241 11:45:52.896936 02280000 ################################################################
10242 11:45:52.897107
10243 11:45:53.458605 02300000 ################################################################
10244 11:45:53.459110
10245 11:45:54.078471 02380000 ################################################################
10246 11:45:54.078974
10247 11:45:54.719341 02400000 ################################################################
10248 11:45:54.720028
10249 11:45:55.349350 02480000 ################################################################
10250 11:45:55.350006
10251 11:45:56.018175 02500000 ################################################################
10252 11:45:56.018703
10253 11:45:56.652213 02580000 ################################################################
10254 11:45:56.652731
10255 11:45:57.278104 02600000 ################################################################
10256 11:45:57.278653
10257 11:45:57.918606 02680000 ################################################################
10258 11:45:57.919421
10259 11:45:58.579756 02700000 ################################################################
10260 11:45:58.580493
10261 11:45:59.181132 02780000 ################################################################
10262 11:45:59.181790
10263 11:45:59.783829 02800000 ################################################################
10264 11:45:59.783987
10265 11:46:00.429660 02880000 ################################################################
10266 11:46:00.430207
10267 11:46:01.116833 02900000 ################################################################
10268 11:46:01.117516
10269 11:46:01.832645 02980000 ################################################################
10270 11:46:01.833175
10271 11:46:02.453474 02a00000 ################################################################
10272 11:46:02.453819
10273 11:46:02.972418 02a80000 ################################################################
10274 11:46:02.972574
10275 11:46:03.493589 02b00000 ################################################################
10276 11:46:03.493761
10277 11:46:04.086696 02b80000 ################################################################
10278 11:46:04.087268
10279 11:46:04.700743 02c00000 ################################################################
10280 11:46:04.701261
10281 11:46:05.312103 02c80000 ################################################################
10282 11:46:05.312297
10283 11:46:05.895084 02d00000 ################################################################
10284 11:46:05.895795
10285 11:46:06.548999 02d80000 ################################################################
10286 11:46:06.549517
10287 11:46:07.189292 02e00000 ################################################################
10288 11:46:07.189703
10289 11:46:07.826156 02e80000 ################################################################
10290 11:46:07.826832
10291 11:46:08.441260 02f00000 ################################################################
10292 11:46:08.441931
10293 11:46:09.069745 02f80000 ################################################################
10294 11:46:09.070417
10295 11:46:09.456696 03000000 ##################################### done.
10296 11:46:09.457344
10297 11:46:09.459874 The bootfile was 50631510 bytes long.
10298 11:46:09.460363
10299 11:46:09.463060 Sending tftp read request... done.
10300 11:46:09.463627
10301 11:46:09.466366 Waiting for the transfer...
10302 11:46:09.466842
10303 11:46:09.467218 00000000 # done.
10304 11:46:09.467613
10305 11:46:09.472997 Command line loaded dynamically from TFTP file: 10742249/tftp-deploy-_g234_cb/kernel/cmdline
10306 11:46:09.476745
10307 11:46:09.486329 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10308 11:46:09.486666
10309 11:46:09.486914 Loading FIT.
10310 11:46:09.487145
10311 11:46:09.489482 Image ramdisk-1 has 40139190 bytes.
10312 11:46:09.489719
10313 11:46:09.492621 Image fdt-1 has 46924 bytes.
10314 11:46:09.492862
10315 11:46:09.496495 Image kernel-1 has 10443363 bytes.
10316 11:46:09.496686
10317 11:46:09.505812 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10318 11:46:09.505990
10319 11:46:09.522707 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10320 11:46:09.522901
10321 11:46:09.526137 Choosing best match conf-1 for compat google,spherion-rev2.
10322 11:46:09.532333
10323 11:46:09.536187 Connected to device vid:did:rid of 1ae0:0028:00
10324 11:46:09.543113
10325 11:46:09.547112 tpm_get_response: command 0x17b, return code 0x0
10326 11:46:09.547700
10327 11:46:09.550269 ec_init: CrosEC protocol v3 supported (256, 248)
10328 11:46:09.554359
10329 11:46:09.557522 tpm_cleanup: add release locality here.
10330 11:46:09.558014
10331 11:46:09.558398 Shutting down all USB controllers.
10332 11:46:09.560621
10333 11:46:09.561093 Removing current net device
10334 11:46:09.561472
10335 11:46:09.567449 Exiting depthcharge with code 4 at timestamp: 93564065
10336 11:46:09.568029
10337 11:46:09.570466 LZMA decompressing kernel-1 to 0x821a6718
10338 11:46:09.570946
10339 11:46:09.573625 LZMA decompressing kernel-1 to 0x40000000
10340 11:46:10.885155
10341 11:46:10.885712 jumping to kernel
10342 11:46:10.887105 end: 2.2.4 bootloader-commands (duration 00:01:05) [common]
10343 11:46:10.887637 start: 2.2.5 auto-login-action (timeout 00:03:20) [common]
10344 11:46:10.888030 Setting prompt string to ['Linux version [0-9]']
10345 11:46:10.888374 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10346 11:46:10.888746 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10347 11:46:10.966684
10348 11:46:10.969821 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10349 11:46:10.973439 start: 2.2.5.1 login-action (timeout 00:03:20) [common]
10350 11:46:10.973901 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10351 11:46:10.974346 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10352 11:46:10.974752 Using line separator: #'\n'#
10353 11:46:10.975105 No login prompt set.
10354 11:46:10.975471 Parsing kernel messages
10355 11:46:10.975816 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10356 11:46:10.976562 [login-action] Waiting for messages, (timeout 00:03:20)
10357 11:46:10.993021 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10358 11:46:10.996170 [ 0.000000] random: crng init done
10359 11:46:10.999503 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10360 11:46:11.002718 [ 0.000000] efi: UEFI not found.
10361 11:46:11.013150 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10362 11:46:11.019836 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10363 11:46:11.029606 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10364 11:46:11.039663 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10365 11:46:11.045858 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10366 11:46:11.049180 [ 0.000000] printk: bootconsole [mtk8250] enabled
10367 11:46:11.057958 [ 0.000000] NUMA: No NUMA configuration found
10368 11:46:11.064974 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10369 11:46:11.071284 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10370 11:46:11.071796 [ 0.000000] Zone ranges:
10371 11:46:11.077736 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10372 11:46:11.081413 [ 0.000000] DMA32 empty
10373 11:46:11.087618 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10374 11:46:11.091021 [ 0.000000] Movable zone start for each node
10375 11:46:11.094228 [ 0.000000] Early memory node ranges
10376 11:46:11.101178 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10377 11:46:11.107935 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10378 11:46:11.114763 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10379 11:46:11.121085 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10380 11:46:11.128082 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10381 11:46:11.134761 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10382 11:46:11.190985 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10383 11:46:11.197084 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10384 11:46:11.203585 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10385 11:46:11.207444 [ 0.000000] psci: probing for conduit method from DT.
10386 11:46:11.214154 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10387 11:46:11.217748 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10388 11:46:11.223740 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10389 11:46:11.227044 [ 0.000000] psci: SMC Calling Convention v1.2
10390 11:46:11.233435 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10391 11:46:11.237607 [ 0.000000] Detected VIPT I-cache on CPU0
10392 11:46:11.243937 [ 0.000000] CPU features: detected: GIC system register CPU interface
10393 11:46:11.250577 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10394 11:46:11.257236 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10395 11:46:11.263537 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10396 11:46:11.269871 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10397 11:46:11.279776 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10398 11:46:11.283038 [ 0.000000] alternatives: applying boot alternatives
10399 11:46:11.289834 [ 0.000000] Fallback order for Node 0: 0
10400 11:46:11.296764 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10401 11:46:11.299908 [ 0.000000] Policy zone: Normal
10402 11:46:11.309426 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10403 11:46:11.322568 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10404 11:46:11.332441 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10405 11:46:11.342188 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10406 11:46:11.348543 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10407 11:46:11.351774 <6>[ 0.000000] software IO TLB: area num 8.
10408 11:46:11.409089 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10409 11:46:11.557917 <6>[ 0.000000] Memory: 7931960K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 420808K reserved, 32768K cma-reserved)
10410 11:46:11.564513 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10411 11:46:11.571426 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10412 11:46:11.574597 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10413 11:46:11.581204 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10414 11:46:11.587665 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10415 11:46:11.591308 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10416 11:46:11.601043 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10417 11:46:11.608035 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10418 11:46:11.614157 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10419 11:46:11.620579 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10420 11:46:11.624464 <6>[ 0.000000] GICv3: 608 SPIs implemented
10421 11:46:11.627602 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10422 11:46:11.634091 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10423 11:46:11.637515 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10424 11:46:11.644045 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10425 11:46:11.657463 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10426 11:46:11.668795 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10427 11:46:11.677500 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10428 11:46:11.684515 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10429 11:46:11.697602 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10430 11:46:11.703887 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10431 11:46:11.711077 <6>[ 0.009226] Console: colour dummy device 80x25
10432 11:46:11.720804 <6>[ 0.013972] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10433 11:46:11.724550 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10434 11:46:11.730841 <6>[ 0.029287] LSM: Security Framework initializing
10435 11:46:11.737499 <6>[ 0.034229] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10436 11:46:11.747109 <6>[ 0.042043] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10437 11:46:11.754200 <6>[ 0.051524] cblist_init_generic: Setting adjustable number of callback queues.
10438 11:46:11.760771 <6>[ 0.058977] cblist_init_generic: Setting shift to 3 and lim to 1.
10439 11:46:11.767147 <6>[ 0.065355] cblist_init_generic: Setting shift to 3 and lim to 1.
10440 11:46:11.774357 <6>[ 0.071764] rcu: Hierarchical SRCU implementation.
10441 11:46:11.777619 <6>[ 0.076808] rcu: Max phase no-delay instances is 1000.
10442 11:46:11.785461 <6>[ 0.083856] EFI services will not be available.
10443 11:46:11.789251 <6>[ 0.088830] smp: Bringing up secondary CPUs ...
10444 11:46:11.798153 <6>[ 0.093882] Detected VIPT I-cache on CPU1
10445 11:46:11.804209 <6>[ 0.093956] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10446 11:46:11.810903 <6>[ 0.093987] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10447 11:46:11.814674 <6>[ 0.094325] Detected VIPT I-cache on CPU2
10448 11:46:11.820967 <6>[ 0.094379] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10449 11:46:11.827317 <6>[ 0.094396] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10450 11:46:11.834274 <6>[ 0.094659] Detected VIPT I-cache on CPU3
10451 11:46:11.840924 <6>[ 0.094707] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10452 11:46:11.847368 <6>[ 0.094722] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10453 11:46:11.850667 <6>[ 0.095031] CPU features: detected: Spectre-v4
10454 11:46:11.857113 <6>[ 0.095038] CPU features: detected: Spectre-BHB
10455 11:46:11.860877 <6>[ 0.095044] Detected PIPT I-cache on CPU4
10456 11:46:11.867535 <6>[ 0.095103] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10457 11:46:11.873985 <6>[ 0.095119] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10458 11:46:11.880366 <6>[ 0.095415] Detected PIPT I-cache on CPU5
10459 11:46:11.886828 <6>[ 0.095477] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10460 11:46:11.894076 <6>[ 0.095494] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10461 11:46:11.897304 <6>[ 0.095778] Detected PIPT I-cache on CPU6
10462 11:46:11.903651 <6>[ 0.095845] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10463 11:46:11.909982 <6>[ 0.095861] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10464 11:46:11.917016 <6>[ 0.096161] Detected PIPT I-cache on CPU7
10465 11:46:11.923454 <6>[ 0.096227] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10466 11:46:11.929852 <6>[ 0.096244] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10467 11:46:11.933612 <6>[ 0.096292] smp: Brought up 1 node, 8 CPUs
10468 11:46:11.940015 <6>[ 0.237554] SMP: Total of 8 processors activated.
10469 11:46:11.943187 <6>[ 0.242475] CPU features: detected: 32-bit EL0 Support
10470 11:46:11.953201 <6>[ 0.247837] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10471 11:46:11.959653 <6>[ 0.256692] CPU features: detected: Common not Private translations
10472 11:46:11.966192 <6>[ 0.263168] CPU features: detected: CRC32 instructions
10473 11:46:11.969887 <6>[ 0.268519] CPU features: detected: RCpc load-acquire (LDAPR)
10474 11:46:11.976670 <6>[ 0.274478] CPU features: detected: LSE atomic instructions
10475 11:46:11.982967 <6>[ 0.280259] CPU features: detected: Privileged Access Never
10476 11:46:11.989394 <6>[ 0.286074] CPU features: detected: RAS Extension Support
10477 11:46:11.996517 <6>[ 0.291683] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10478 11:46:11.999869 <6>[ 0.298895] CPU: All CPU(s) started at EL2
10479 11:46:12.006345 <6>[ 0.303211] alternatives: applying system-wide alternatives
10480 11:46:12.015690 <6>[ 0.313956] devtmpfs: initialized
10481 11:46:12.031060 <6>[ 0.322877] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10482 11:46:12.037223 <6>[ 0.332842] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10483 11:46:12.044357 <6>[ 0.341057] pinctrl core: initialized pinctrl subsystem
10484 11:46:12.047292 <6>[ 0.347730] DMI not present or invalid.
10485 11:46:12.053924 <6>[ 0.352146] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10486 11:46:12.064176 <6>[ 0.359032] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10487 11:46:12.070714 <6>[ 0.366614] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10488 11:46:12.080681 <6>[ 0.374840] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10489 11:46:12.083814 <6>[ 0.383091] audit: initializing netlink subsys (disabled)
10490 11:46:12.093663 <5>[ 0.388791] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10491 11:46:12.100736 <6>[ 0.389520] thermal_sys: Registered thermal governor 'step_wise'
10492 11:46:12.107256 <6>[ 0.396757] thermal_sys: Registered thermal governor 'power_allocator'
10493 11:46:12.110417 <6>[ 0.403012] cpuidle: using governor menu
10494 11:46:12.116874 <6>[ 0.413973] NET: Registered PF_QIPCRTR protocol family
10495 11:46:12.123810 <6>[ 0.419483] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10496 11:46:12.130297 <6>[ 0.426589] ASID allocator initialised with 32768 entries
10497 11:46:12.133474 <6>[ 0.433153] Serial: AMBA PL011 UART driver
10498 11:46:12.143050 <4>[ 0.441902] Trying to register duplicate clock ID: 134
10499 11:46:12.197511 <6>[ 0.499364] KASLR enabled
10500 11:46:12.212287 <6>[ 0.507160] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10501 11:46:12.219094 <6>[ 0.514173] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10502 11:46:12.225436 <6>[ 0.520664] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10503 11:46:12.232498 <6>[ 0.527668] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10504 11:46:12.238552 <6>[ 0.534153] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10505 11:46:12.245529 <6>[ 0.541159] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10506 11:46:12.251957 <6>[ 0.547642] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10507 11:46:12.258783 <6>[ 0.554645] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10508 11:46:12.262091 <6>[ 0.562155] ACPI: Interpreter disabled.
10509 11:46:12.270354 <6>[ 0.568536] iommu: Default domain type: Translated
10510 11:46:12.276983 <6>[ 0.573651] iommu: DMA domain TLB invalidation policy: strict mode
10511 11:46:12.280209 <5>[ 0.580310] SCSI subsystem initialized
10512 11:46:12.286866 <6>[ 0.584478] usbcore: registered new interface driver usbfs
10513 11:46:12.294170 <6>[ 0.590211] usbcore: registered new interface driver hub
10514 11:46:12.297299 <6>[ 0.595764] usbcore: registered new device driver usb
10515 11:46:12.303584 <6>[ 0.601847] pps_core: LinuxPPS API ver. 1 registered
10516 11:46:12.313632 <6>[ 0.607040] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10517 11:46:12.316776 <6>[ 0.616387] PTP clock support registered
10518 11:46:12.320210 <6>[ 0.620627] EDAC MC: Ver: 3.0.0
10519 11:46:12.327466 <6>[ 0.625773] FPGA manager framework
10520 11:46:12.334074 <6>[ 0.629455] Advanced Linux Sound Architecture Driver Initialized.
10521 11:46:12.337278 <6>[ 0.636233] vgaarb: loaded
10522 11:46:12.344234 <6>[ 0.639394] clocksource: Switched to clocksource arch_sys_counter
10523 11:46:12.347447 <5>[ 0.645839] VFS: Disk quotas dquot_6.6.0
10524 11:46:12.354489 <6>[ 0.650021] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10525 11:46:12.357541 <6>[ 0.657210] pnp: PnP ACPI: disabled
10526 11:46:12.366047 <6>[ 0.663934] NET: Registered PF_INET protocol family
10527 11:46:12.376009 <6>[ 0.669518] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10528 11:46:12.387011 <6>[ 0.681836] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10529 11:46:12.397158 <6>[ 0.690648] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10530 11:46:12.404037 <6>[ 0.698620] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10531 11:46:12.410459 <6>[ 0.707320] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10532 11:46:12.421834 <6>[ 0.717070] TCP: Hash tables configured (established 65536 bind 65536)
10533 11:46:12.428823 <6>[ 0.723926] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10534 11:46:12.435292 <6>[ 0.731125] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10535 11:46:12.441662 <6>[ 0.738824] NET: Registered PF_UNIX/PF_LOCAL protocol family
10536 11:46:12.448712 <6>[ 0.744974] RPC: Registered named UNIX socket transport module.
10537 11:46:12.452016 <6>[ 0.751128] RPC: Registered udp transport module.
10538 11:46:12.458651 <6>[ 0.756061] RPC: Registered tcp transport module.
10539 11:46:12.465538 <6>[ 0.760990] RPC: Registered tcp NFSv4.1 backchannel transport module.
10540 11:46:12.468783 <6>[ 0.767653] PCI: CLS 0 bytes, default 64
10541 11:46:12.472019 <6>[ 0.771948] Unpacking initramfs...
10542 11:46:12.489377 <6>[ 0.783978] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10543 11:46:12.499055 <6>[ 0.792615] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10544 11:46:12.502132 <6>[ 0.801394] kvm [1]: IPA Size Limit: 40 bits
10545 11:46:12.509216 <6>[ 0.805920] kvm [1]: GICv3: no GICV resource entry
10546 11:46:12.512464 <6>[ 0.810940] kvm [1]: disabling GICv2 emulation
10547 11:46:12.518756 <6>[ 0.815625] kvm [1]: GIC system register CPU interface enabled
10548 11:46:12.522023 <6>[ 0.821787] kvm [1]: vgic interrupt IRQ18
10549 11:46:12.528435 <6>[ 0.826167] kvm [1]: VHE mode initialized successfully
10550 11:46:12.534926 <5>[ 0.832629] Initialise system trusted keyrings
10551 11:46:12.542023 <6>[ 0.837417] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10552 11:46:12.549060 <6>[ 0.847516] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10553 11:46:12.555872 <5>[ 0.853893] NFS: Registering the id_resolver key type
10554 11:46:12.559051 <5>[ 0.859197] Key type id_resolver registered
10555 11:46:12.566215 <5>[ 0.863613] Key type id_legacy registered
10556 11:46:12.572270 <6>[ 0.867891] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10557 11:46:12.578747 <6>[ 0.874814] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10558 11:46:12.585628 <6>[ 0.882537] 9p: Installing v9fs 9p2000 file system support
10559 11:46:12.622528 <5>[ 0.920678] Key type asymmetric registered
10560 11:46:12.625653 <5>[ 0.925009] Asymmetric key parser 'x509' registered
10561 11:46:12.635459 <6>[ 0.930144] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10562 11:46:12.638698 <6>[ 0.937759] io scheduler mq-deadline registered
10563 11:46:12.642605 <6>[ 0.942516] io scheduler kyber registered
10564 11:46:12.660719 <6>[ 0.959356] EINJ: ACPI disabled.
10565 11:46:12.693022 <4>[ 0.984646] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 11:46:12.702614 <4>[ 0.995268] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 11:46:12.717542 <6>[ 1.015954] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10568 11:46:12.725628 <6>[ 1.023919] printk: console [ttyS0] disabled
10569 11:46:12.753149 <6>[ 1.048587] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10570 11:46:12.760426 <6>[ 1.058064] printk: console [ttyS0] enabled
10571 11:46:12.763588 <6>[ 1.058064] printk: console [ttyS0] enabled
10572 11:46:12.770282 <6>[ 1.066957] printk: bootconsole [mtk8250] disabled
10573 11:46:12.773704 <6>[ 1.066957] printk: bootconsole [mtk8250] disabled
10574 11:46:12.780030 <6>[ 1.078149] SuperH (H)SCI(F) driver initialized
10575 11:46:12.783157 <6>[ 1.083434] msm_serial: driver initialized
10576 11:46:12.797791 <6>[ 1.092369] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10577 11:46:12.807472 <6>[ 1.100914] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10578 11:46:12.813738 <6>[ 1.109459] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10579 11:46:12.823867 <6>[ 1.118087] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10580 11:46:12.833822 <6>[ 1.126793] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10581 11:46:12.840894 <6>[ 1.135505] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10582 11:46:12.850572 <6>[ 1.144046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10583 11:46:12.857644 <6>[ 1.152856] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10584 11:46:12.867465 <6>[ 1.161402] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10585 11:46:12.878509 <6>[ 1.176906] loop: module loaded
10586 11:46:12.885026 <6>[ 1.182944] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10587 11:46:12.908206 <4>[ 1.206375] mtk-pmic-keys: Failed to locate of_node [id: -1]
10588 11:46:12.914631 <6>[ 1.213156] megasas: 07.719.03.00-rc1
10589 11:46:12.924617 <6>[ 1.222586] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10590 11:46:12.933031 <6>[ 1.230807] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10591 11:46:12.949151 <6>[ 1.247437] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10592 11:46:13.010098 <6>[ 1.301463] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10593 11:46:14.091748 <6>[ 2.390119] Freeing initrd memory: 39192K
10594 11:46:14.102116 <6>[ 2.400633] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10595 11:46:14.112739 <6>[ 2.411329] tun: Universal TUN/TAP device driver, 1.6
10596 11:46:14.116008 <6>[ 2.417379] thunder_xcv, ver 1.0
10597 11:46:14.119787 <6>[ 2.420884] thunder_bgx, ver 1.0
10598 11:46:14.123443 <6>[ 2.424378] nicpf, ver 1.0
10599 11:46:14.133488 <6>[ 2.428384] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10600 11:46:14.136470 <6>[ 2.435860] hns3: Copyright (c) 2017 Huawei Corporation.
10601 11:46:14.143188 <6>[ 2.441445] hclge is initializing
10602 11:46:14.146841 <6>[ 2.445024] e1000: Intel(R) PRO/1000 Network Driver
10603 11:46:14.153032 <6>[ 2.450153] e1000: Copyright (c) 1999-2006 Intel Corporation.
10604 11:46:14.156811 <6>[ 2.456166] e1000e: Intel(R) PRO/1000 Network Driver
10605 11:46:14.163313 <6>[ 2.461381] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10606 11:46:14.170097 <6>[ 2.467570] igb: Intel(R) Gigabit Ethernet Network Driver
10607 11:46:14.176709 <6>[ 2.473220] igb: Copyright (c) 2007-2014 Intel Corporation.
10608 11:46:14.183254 <6>[ 2.479056] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10609 11:46:14.189680 <6>[ 2.485574] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10610 11:46:14.193121 <6>[ 2.492031] sky2: driver version 1.30
10611 11:46:14.199661 <6>[ 2.496993] VFIO - User Level meta-driver version: 0.3
10612 11:46:14.206664 <6>[ 2.505217] usbcore: registered new interface driver usb-storage
10613 11:46:14.213218 <6>[ 2.511657] usbcore: registered new device driver onboard-usb-hub
10614 11:46:14.222724 <6>[ 2.520736] mt6397-rtc mt6359-rtc: registered as rtc0
10615 11:46:14.232476 <6>[ 2.526231] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:46:14 UTC (1686829574)
10616 11:46:14.235880 <6>[ 2.535850] i2c_dev: i2c /dev entries driver
10617 11:46:14.252485 <6>[ 2.547482] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10618 11:46:14.259860 <6>[ 2.557647] sdhci: Secure Digital Host Controller Interface driver
10619 11:46:14.265970 <6>[ 2.564085] sdhci: Copyright(c) Pierre Ossman
10620 11:46:14.272594 <6>[ 2.569469] Synopsys Designware Multimedia Card Interface Driver
10621 11:46:14.275604 <6>[ 2.576089] mmc0: CQHCI version 5.10
10622 11:46:14.282676 <6>[ 2.576610] sdhci-pltfm: SDHCI platform and OF driver helper
10623 11:46:14.289833 <6>[ 2.588171] ledtrig-cpu: registered to indicate activity on CPUs
10624 11:46:14.300280 <6>[ 2.595376] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10625 11:46:14.306601 <6>[ 2.602793] usbcore: registered new interface driver usbhid
10626 11:46:14.309859 <6>[ 2.608628] usbhid: USB HID core driver
10627 11:46:14.316351 <6>[ 2.612883] spi_master spi0: will run message pump with realtime priority
10628 11:46:14.365882 <6>[ 2.657550] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10629 11:46:14.384550 <6>[ 2.672801] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10630 11:46:14.387718 <6>[ 2.686356] mmc0: Command Queue Engine enabled
10631 11:46:14.395042 <6>[ 2.688590] cros-ec-spi spi0.0: Chrome EC device registered
10632 11:46:14.401830 <6>[ 2.691084] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10633 11:46:14.405020 <6>[ 2.704409] mmcblk0: mmc0:0001 DA4128 116 GiB
10634 11:46:14.421598 <6>[ 2.716084] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10635 11:46:14.427944 <6>[ 2.718476] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10636 11:46:14.434792 <6>[ 2.727622] NET: Registered PF_PACKET protocol family
10637 11:46:14.438063 <6>[ 2.732898] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10638 11:46:14.444783 <6>[ 2.736730] 9pnet: Installing 9P2000 support
10639 11:46:14.447925 <6>[ 2.742513] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10640 11:46:14.454261 <5>[ 2.746423] Key type dns_resolver registered
10641 11:46:14.461192 <6>[ 2.752256] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10642 11:46:14.464360 <6>[ 2.756645] registered taskstats version 1
10643 11:46:14.467416 <5>[ 2.767037] Loading compiled-in X.509 certificates
10644 11:46:14.502449 <4>[ 2.794173] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 11:46:14.512014 <4>[ 2.804898] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 11:46:14.523065 <3>[ 2.817893] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10647 11:46:14.535027 <6>[ 2.833547] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10648 11:46:14.542057 <6>[ 2.840303] xhci-mtk 11200000.usb: xHCI Host Controller
10649 11:46:14.548775 <6>[ 2.845805] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10650 11:46:14.558363 <6>[ 2.853651] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10651 11:46:14.564886 <6>[ 2.863074] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10652 11:46:14.571794 <6>[ 2.869260] xhci-mtk 11200000.usb: xHCI Host Controller
10653 11:46:14.578191 <6>[ 2.874755] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10654 11:46:14.585101 <6>[ 2.882421] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10655 11:46:14.592212 <6>[ 2.890311] hub 1-0:1.0: USB hub found
10656 11:46:14.595445 <6>[ 2.894346] hub 1-0:1.0: 1 port detected
10657 11:46:14.605453 <6>[ 2.898702] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10658 11:46:14.608744 <6>[ 2.907602] hub 2-0:1.0: USB hub found
10659 11:46:14.611834 <6>[ 2.911643] hub 2-0:1.0: 1 port detected
10660 11:46:14.620286 <6>[ 2.918777] mtk-msdc 11f70000.mmc: Got CD GPIO
10661 11:46:14.637973 <6>[ 2.932826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10662 11:46:14.644217 <6>[ 2.940860] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10663 11:46:14.654321 <4>[ 2.948842] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10664 11:46:14.664118 <6>[ 2.958500] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10665 11:46:14.670719 <6>[ 2.966581] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10666 11:46:14.680768 <6>[ 2.974604] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10667 11:46:14.687052 <6>[ 2.982522] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10668 11:46:14.693979 <6>[ 2.990343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10669 11:46:14.703789 <6>[ 2.998170] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10670 11:46:14.713530 <6>[ 3.008867] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10671 11:46:14.723212 <6>[ 3.017242] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10672 11:46:14.730659 <6>[ 3.025597] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10673 11:46:14.739855 <6>[ 3.033941] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10674 11:46:14.746544 <6>[ 3.042285] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10675 11:46:14.757186 <6>[ 3.050628] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10676 11:46:14.763491 <6>[ 3.058971] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10677 11:46:14.773425 <6>[ 3.067314] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10678 11:46:14.779710 <6>[ 3.075658] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10679 11:46:14.789851 <6>[ 3.084001] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10680 11:46:14.796129 <6>[ 3.092344] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10681 11:46:14.806580 <6>[ 3.100688] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10682 11:46:14.813207 <6>[ 3.109031] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10683 11:46:14.823311 <6>[ 3.117375] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10684 11:46:14.829596 <6>[ 3.125722] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10685 11:46:14.836032 <6>[ 3.134631] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10686 11:46:14.843788 <6>[ 3.142101] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10687 11:46:14.850699 <6>[ 3.149204] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10688 11:46:14.860842 <6>[ 3.156362] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10689 11:46:14.868035 <6>[ 3.163697] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10690 11:46:14.877642 <6>[ 3.170634] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10691 11:46:14.884075 <6>[ 3.179788] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10692 11:46:14.893993 <6>[ 3.188918] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10693 11:46:14.904309 <6>[ 3.198218] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10694 11:46:14.914699 <6>[ 3.207693] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10695 11:46:14.924192 <6>[ 3.217167] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10696 11:46:14.930927 <6>[ 3.226296] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10697 11:46:14.940513 <6>[ 3.235774] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10698 11:46:14.951037 <6>[ 3.244907] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10699 11:46:14.960637 <6>[ 3.254225] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10700 11:46:14.970649 <6>[ 3.264391] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10701 11:46:14.980755 <6>[ 3.275808] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10702 11:46:15.012087 <6>[ 3.307671] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10703 11:46:15.166549 <6>[ 3.465091] hub 1-1:1.0: USB hub found
10704 11:46:15.169618 <6>[ 3.469571] hub 1-1:1.0: 4 ports detected
10705 11:46:15.378602 <6>[ 3.587799] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10706 11:46:15.379470 <6>[ 3.616051] hub 2-1:1.0: USB hub found
10707 11:46:15.380116 <6>[ 3.620443] hub 2-1:1.0: 3 ports detected
10708 11:46:15.492149 <6>[ 3.787668] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10709 11:46:15.625358 <6>[ 3.923786] hub 1-1.4:1.0: USB hub found
10710 11:46:15.628350 <6>[ 3.928468] hub 1-1.4:1.0: 2 ports detected
10711 11:46:15.704304 <6>[ 3.999908] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10712 11:46:15.924231 <6>[ 4.219677] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10713 11:46:16.116445 <6>[ 4.411672] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10714 11:46:27.260830 <6>[ 15.564227] ALSA device list:
10715 11:46:27.267184 <6>[ 15.567485] No soundcards found.
10716 11:46:27.279864 <6>[ 15.579911] Freeing unused kernel memory: 8384K
10717 11:46:27.283113 <6>[ 15.584830] Run /init as init process
10718 11:46:27.313703 <6>[ 15.613703] NET: Registered PF_INET6 protocol family
10719 11:46:27.320225 <6>[ 15.620167] Segment Routing with IPv6
10720 11:46:27.323874 <6>[ 15.624111] In-situ OAM (IOAM) with IPv6
10721 11:46:27.358735 <30>[ 15.638766] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10722 11:46:27.361787 <30>[ 15.662737] systemd[1]: Detected architecture arm64.
10723 11:46:27.364812
10724 11:46:27.368039 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10725 11:46:27.368352
10726 11:46:27.383670 <30>[ 15.683818] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10727 11:46:27.514966 <30>[ 15.811587] systemd[1]: Queued start job for default target Graphical Interface.
10728 11:46:27.549196 <30>[ 15.849007] systemd[1]: Created slice system-getty.slice.
10729 11:46:27.555647 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10730 11:46:27.572626 <30>[ 15.872354] systemd[1]: Created slice system-modprobe.slice.
10731 11:46:27.578634 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10732 11:46:27.596374 <30>[ 15.896181] systemd[1]: Created slice system-serial\x2dgetty.slice.
10733 11:46:27.606306 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10734 11:46:27.620706 <30>[ 15.920699] systemd[1]: Created slice User and Session Slice.
10735 11:46:27.627041 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10736 11:46:27.647759 <30>[ 15.944204] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10737 11:46:27.657230 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10738 11:46:27.675263 <30>[ 15.972192] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10739 11:46:27.682113 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10740 11:46:27.702541 <30>[ 15.995771] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10741 11:46:27.709019 <30>[ 16.007806] systemd[1]: Reached target Local Encrypted Volumes.
10742 11:46:27.715317 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10743 11:46:27.732235 <30>[ 16.032036] systemd[1]: Reached target Paths.
10744 11:46:27.735430 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10745 11:46:27.751506 <30>[ 16.051725] systemd[1]: Reached target Remote File Systems.
10746 11:46:27.758174 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10747 11:46:27.775502 <30>[ 16.075950] systemd[1]: Reached target Slices.
10748 11:46:27.778969 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10749 11:46:27.795211 <30>[ 16.095728] systemd[1]: Reached target Swap.
10750 11:46:27.798736 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10751 11:46:27.819152 <30>[ 16.116056] systemd[1]: Listening on initctl Compatibility Named Pipe.
10752 11:46:27.825709 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10753 11:46:27.832288 <30>[ 16.130758] systemd[1]: Listening on Journal Audit Socket.
10754 11:46:27.838808 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10755 11:46:27.852154 <30>[ 16.151990] systemd[1]: Listening on Journal Socket (/dev/log).
10756 11:46:27.858335 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10757 11:46:27.876606 <30>[ 16.176466] systemd[1]: Listening on Journal Socket.
10758 11:46:27.883298 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10759 11:46:27.899813 <30>[ 16.196103] systemd[1]: Listening on Network Service Netlink Socket.
10760 11:46:27.906435 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10761 11:46:27.920388 <30>[ 16.220456] systemd[1]: Listening on udev Control Socket.
10762 11:46:27.926744 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10763 11:46:27.944618 <30>[ 16.244383] systemd[1]: Listening on udev Kernel Socket.
10764 11:46:27.950951 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10765 11:46:27.988057 <30>[ 16.288050] systemd[1]: Mounting Huge Pages File System...
10766 11:46:27.994856 Mounting [0;1;39mHuge Pages File System[0m...
10767 11:46:28.009977 <30>[ 16.309838] systemd[1]: Mounting POSIX Message Queue File System...
10768 11:46:28.017105 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10769 11:46:28.033900 <30>[ 16.333877] systemd[1]: Mounting Kernel Debug File System...
10770 11:46:28.040596 Mounting [0;1;39mKernel Debug File System[0m...
10771 11:46:28.059311 <30>[ 16.356166] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10772 11:46:28.083563 <30>[ 16.380079] systemd[1]: Starting Create list of static device nodes for the current kernel...
10773 11:46:28.090003 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10774 11:46:28.110568 <30>[ 16.410262] systemd[1]: Starting Load Kernel Module configfs...
10775 11:46:28.117120 Starting [0;1;39mLoad Kernel Module configfs[0m...
10776 11:46:28.134122 <30>[ 16.434240] systemd[1]: Starting Load Kernel Module drm...
10777 11:46:28.140935 Starting [0;1;39mLoad Kernel Module drm[0m...
10778 11:46:28.159173 <30>[ 16.455949] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10779 11:46:28.169440 <30>[ 16.469657] systemd[1]: Starting Journal Service...
10780 11:46:28.173029 Starting [0;1;39mJournal Service[0m...
10781 11:46:28.190260 <30>[ 16.490538] systemd[1]: Starting Load Kernel Modules...
10782 11:46:28.196879 Starting [0;1;39mLoad Kernel Modules[0m...
10783 11:46:28.217319 <30>[ 16.514447] systemd[1]: Starting Remount Root and Kernel File Systems...
10784 11:46:28.223905 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10785 11:46:28.237739 <30>[ 16.538276] systemd[1]: Starting Coldplug All udev Devices...
10786 11:46:28.244238 Starting [0;1;39mColdplug All udev Devices[0m...
10787 11:46:28.261861 <30>[ 16.562271] systemd[1]: Mounted Huge Pages File System.
10788 11:46:28.268327 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10789 11:46:28.284315 <30>[ 16.584136] systemd[1]: Started Journal Service.
10790 11:46:28.290683 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10791 11:46:28.305190 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10792 11:46:28.321213 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10793 11:46:28.343799 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10794 11:46:28.361685 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10795 11:46:28.381365 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10796 11:46:28.396910 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10797 11:46:28.416828 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10798 11:46:28.435382 See 'systemctl status systemd-remount-fs.service' for details.
10799 11:46:28.508576 Mounting [0;1;39mKernel Configuration File System[0m...
10800 11:46:28.526321 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10801 11:46:28.543806 <46>[ 16.840384] systemd-journald[175]: Received client request to flush runtime journal.
10802 11:46:28.552105 Starting [0;1;39mLoad/Save Random Seed[0m...
10803 11:46:28.570560 Starting [0;1;39mApply Kernel Variables[0m...
10804 11:46:28.586743 Starting [0;1;39mCreate System Users[0m...
10805 11:46:28.605332 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10806 11:46:28.624579 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10807 11:46:28.636626 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10808 11:46:28.652475 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10809 11:46:28.672989 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10810 11:46:28.692373 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10811 11:46:28.727805 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10812 11:46:28.752138 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10813 11:46:28.763575 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10814 11:46:28.783629 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10815 11:46:28.840204 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10816 11:46:28.863257 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10817 11:46:28.880944 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10818 11:46:28.900386 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10819 11:46:28.949199 Starting [0;1;39mNetwork Service[0m...
10820 11:46:28.973242 Starting [0;1;39mNetwork Time Synchronization[0m...
10821 11:46:28.996077 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10822 11:46:29.049465 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10823 11:46:29.065109 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10824 11:46:29.100689 <6>[ 17.397767] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10825 11:46:29.121146 Starting [0;1;39mNetwork Name Resolution[0m...
10826 11:46:29.131295 <6>[ 17.431438] remoteproc remoteproc0: scp is available
10827 11:46:29.138388 <6>[ 17.438345] remoteproc remoteproc0: powering up scp
10828 11:46:29.148283 <6>[ 17.443805] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10829 11:46:29.155009 [[0;32m OK [<6>[ 17.452418] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10830 11:46:29.158137 0m] Started [0;1;39mNetwork Time Synchronization[0m.
10831 11:46:29.175304 <3>[ 17.471978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10832 11:46:29.181882 <3>[ 17.480192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 11:46:29.191976 <3>[ 17.488333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 11:46:29.201687 [[0;32m OK [0m] Found device [0;1;39m/dev/t<6>[ 17.499656] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10835 11:46:29.204766 tyS0[0m.
10836 11:46:29.211850 <6>[ 17.508562] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10837 11:46:29.221435 <6>[ 17.518158] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10838 11:46:29.228416 <3>[ 17.525006] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 11:46:29.238131 <3>[ 17.535088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 11:46:29.244623 <3>[ 17.543290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 11:46:29.254315 <3>[ 17.551407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 11:46:29.261508 <3>[ 17.551418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 11:46:29.271200 <3>[ 17.566893] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 11:46:29.277923 [[0;32m OK [0m] Created slic<6>[ 17.577467] usbcore: registered new interface driver r8152
10845 11:46:29.287678 e [0;1;39msyste<6>[ 17.580400] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10846 11:46:29.297995 m-systemd\x2dbac<6>[ 17.580403] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10847 11:46:29.307462 klight.slice[0m<3>[ 17.580659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10848 11:46:29.313890 <3>[ 17.580675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 11:46:29.324354 <3>[ 17.580683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10850 11:46:29.330491 <3>[ 17.580759] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 11:46:29.330934 .
10852 11:46:29.340977 <3>[ 17.580767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 11:46:29.346899 <3>[ 17.580773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 11:46:29.356962 <3>[ 17.580781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10855 11:46:29.363645 <3>[ 17.580788] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10856 11:46:29.370065 <3>[ 17.580831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10857 11:46:29.379853 <6>[ 17.648874] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10858 11:46:29.386531 <6>[ 17.653723] remoteproc remoteproc0: remote processor scp is now up
10859 11:46:29.389897 <6>[ 17.661363] pci_bus 0000:00: root bus resource [bus 00-ff]
10860 11:46:29.396907 <6>[ 17.696245] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10861 11:46:29.406773 <6>[ 17.696255] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10862 11:46:29.413170 <6>[ 17.696317] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10863 11:46:29.422997 <6>[ 17.696347] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10864 11:46:29.426244 [[0;32m OK [<6>[ 17.696497] pci 0000:00:00.0: supports D1 D2
10865 11:46:29.436313 <6>[ 17.699157] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10866 11:46:29.442830 0m] Reached targ<6>[ 17.701672] mc: Linux media interface: v0.10
10867 11:46:29.452713 et [0;1;39mSyst<4>[ 17.701781] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10868 11:46:29.462625 <6>[ 17.703908] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10869 11:46:29.469347 em Time Set[0m.<4>[ 17.703936] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10870 11:46:29.469898
10871 11:46:29.475893 <6>[ 17.713444] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10872 11:46:29.485847 <6>[ 17.733869] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10873 11:46:29.495890 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 17.795230] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10874 11:46:29.502255 em Time Synchron<6>[ 17.797418] videodev: Linux video capture interface: v2.00
10875 11:46:29.506174 ized[0m.
10876 11:46:29.512492 <6>[ 17.799731] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10877 11:46:29.519179 <6>[ 17.803312] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10878 11:46:29.528822 <6>[ 17.825694] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10879 11:46:29.535176 <6>[ 17.827294] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10880 11:46:29.545363 <6>[ 17.831680] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10881 11:46:29.551857 <4>[ 17.841620] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10882 11:46:29.558426 <4>[ 17.841620] Fallback method does not support PEC.
10883 11:46:29.564979 <6>[ 17.850473] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10884 11:46:29.571507 <6>[ 17.871247] pci 0000:01:00.0: supports D1 D2
10885 11:46:29.578884 <6>[ 17.876385] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10886 11:46:29.585482 <4>[ 17.881133] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10887 11:46:29.596543 Startin<4>[ 17.893688] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10888 11:46:29.606344 g [0;1;39mLoad/<6>[ 17.896233] usbcore: registered new interface driver cdc_ether
10889 11:46:29.609972 Save Screen …o<6>[ 17.900677] Bluetooth: Core ver 2.22
10890 11:46:29.616499 f leds:white:kbd<6>[ 17.901233] NET: Registered PF_BLUETOOTH protocol family
10891 11:46:29.626247 _backlight[0m..<6>[ 17.901239] Bluetooth: HCI device and connection manager initialized
10892 11:46:29.626680 .
10893 11:46:29.629452 <6>[ 17.901267] Bluetooth: HCI socket layer initialized
10894 11:46:29.635901 <6>[ 17.901275] Bluetooth: L2CAP socket layer initialized
10895 11:46:29.642379 <6>[ 17.901298] Bluetooth: SCO socket layer initialized
10896 11:46:29.649301 <3>[ 17.902917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 11:46:29.659171 <6>[ 17.904764] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10898 11:46:29.665749 <6>[ 17.916019] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10899 11:46:29.672352 <6>[ 17.916101] usbcore: registered new interface driver r8153_ecm
10900 11:46:29.678749 <6>[ 17.923821] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10901 11:46:29.685670 <6>[ 17.930730] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10902 11:46:29.695991 <6>[ 17.932986] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10903 11:46:29.705899 <6>[ 17.938209] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10904 11:46:29.715955 <6>[ 17.941160] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10905 11:46:29.722981 <6>[ 17.941185] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10906 11:46:29.730315 <6>[ 17.941205] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10907 11:46:29.737527 <6>[ 17.941222] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10908 11:46:29.744105 <6>[ 17.941238] pci 0000:00:00.0: PCI bridge to [bus 01]
10909 11:46:29.750920 <6>[ 17.946654] usbcore: registered new interface driver uvcvideo
10910 11:46:29.757447 <6>[ 17.955161] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10911 11:46:29.763935 <6>[ 17.956354] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10912 11:46:29.771080 <6>[ 17.956668] usbcore: registered new interface driver btusb
10913 11:46:29.780966 <4>[ 17.957659] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10914 11:46:29.787565 <3>[ 17.957677] Bluetooth: hci0: Failed to load firmware file (-2)
10915 11:46:29.794421 <3>[ 17.957681] Bluetooth: hci0: Failed to set up firmware (-2)
10916 11:46:29.804277 <4>[ 17.957685] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10917 11:46:29.807607 <6>[ 17.999535] r8152 2-1.3:1.0 eth0: v1.12.13
10918 11:46:29.813699 <6>[ 17.999923] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10919 11:46:29.820685 <6>[ 18.024376] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10920 11:46:29.827083 <6>[ 18.029046] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10921 11:46:29.834028 <3>[ 18.031974] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 11:46:29.843839 <3>[ 18.032832] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10923 11:46:29.853922 <3>[ 18.033614] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 11:46:29.860204 <3>[ 18.036192] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10925 11:46:29.866670 <6>[ 18.044527] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10926 11:46:29.876837 <3>[ 18.061074] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 11:46:29.890063 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m<5>[ 18.187049] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10928 11:46:29.890501 .
10929 11:46:29.912740 [[0;32m OK [<5>[ 18.210355] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10930 11:46:29.922788 <3>[ 18.212109] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 11:46:29.932912 0m] Finished [0<4>[ 18.226945] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10932 11:46:29.936206 <6>[ 18.236852] cfg80211: failed to load regulatory.db
10933 11:46:29.942259 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10934 11:46:29.959795 <3>[ 18.256433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 11:46:29.992686 <3>[ 18.289250] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 11:46:29.999241 <6>[ 18.296023] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10937 11:46:30.005643 <6>[ 18.305712] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10938 11:46:30.031319 <6>[ 18.331532] mt7921e 0000:01:00.0: ASIC revision: 79610010
10939 11:46:30.041084 <3>[ 18.334494] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 11:46:30.112991 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10941 11:46:30.139772 [[0;32m OK [0m] Reached targ<4>[ 18.432345] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10942 11:46:30.140319 et [0;1;39mNetwork[0m.
10943 11:46:30.160372 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10944 11:46:30.175683 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10945 11:46:30.195406 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10946 11:46:30.210525 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10947 11:46:30.223642 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10948 11:46:30.243572 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10949 11:46:30.260994 <4>[ 18.554744] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10950 11:46:30.267241 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10951 11:46:30.280801 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10952 11:46:30.299183 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10953 11:46:30.339902 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10954 11:46:30.382072 Starting [0;1;39mUser Login Management<4>[ 18.676352] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10955 11:46:30.382533 [0m...
10956 11:46:30.405096 Starting [0;1;39mPermit User Sessions[0m...
10957 11:46:30.421405 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10958 11:46:30.438251 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10959 11:46:30.454941 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10960 11:46:30.461493 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10961 11:46:30.478522 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10962 11:46:30.490879 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10963 11:46:30.505878 [[0;32m OK [<4>[ 18.800806] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10964 11:46:30.512210 0m] Reached target [0;1;39mMulti-User System[0m.
10965 11:46:30.528828 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10966 11:46:30.580018 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10967 11:46:30.592625 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10968 11:46:30.632390 [[0;32m OK [0m] Finished [0<4>[ 18.923961] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 11:46:30.635406 ;1;39mUpdate UTMP about System Runlevel Changes[0m.
10970 11:46:30.704253
10971 11:46:30.704716
10972 11:46:30.707479 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10973 11:46:30.707911
10974 11:46:30.710321 debian-bullseye-arm64 login: root (automatic login)
10975 11:46:30.710899
10976 11:46:30.711444
10977 11:46:30.727413 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
10978 11:46:30.727849
10979 11:46:30.734055 The programs included with the Debian GNU/Linux system are free software;
10980 11:46:30.740645 the exact distribution terms for each program are described in the
10981 11:46:30.753829 individual files in /usr/share/doc/*/co<4>[ 19.046885] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 11:46:30.754272 pyright.
10983 11:46:30.754722
10984 11:46:30.760231 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10985 11:46:30.763344 permitted by applicable law.
10986 11:46:30.764557 Matched prompt #10: / #
10988 11:46:30.765676 Setting prompt string to ['/ #']
10989 11:46:30.766120 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10991 11:46:30.767123 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10992 11:46:30.767738 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
10993 11:46:30.768179 Setting prompt string to ['/ #']
10994 11:46:30.768511 Forcing a shell prompt, looking for ['/ #']
10996 11:46:30.819269 / #
10997 11:46:30.819973 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 11:46:30.820575 Waiting using forced prompt support (timeout 00:02:30)
10999 11:46:30.825995
11000 11:46:30.826754 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11001 11:46:30.827238 start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11002 11:46:30.827785 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11003 11:46:30.828235 end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11004 11:46:30.828659 end: 2 depthcharge-action (duration 00:02:00) [common]
11005 11:46:30.829097 start: 3 lava-test-retry (timeout 00:07:22) [common]
11006 11:46:30.829534 start: 3.1 lava-test-shell (timeout 00:07:22) [common]
11007 11:46:30.829906 Using namespace: common
11009 11:46:30.930930 / # #
11010 11:46:30.931606 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11011 11:46:30.932128 <4>[ 19.169746] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11012 11:46:30.937300 #
11013 11:46:30.938043 Using /lava-10742249
11015 11:46:31.039024 / # export SHELL=/bin/sh
11016 11:46:31.039805 <4>[ 19.289662] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11017 11:46:31.044977 export SHELL=/bin/sh
11019 11:46:31.146350 / # . /lava-10742249/environment
11020 11:46:31.147264 . /lava-10742249/environment<4>[ 19.409640] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11021 11:46:31.151936
11023 11:46:31.253640 / # /lava-10742249/bin/lava-test-runner /lava-10742249/0
11024 11:46:31.254162 Test shell timeout: 10s (minimum of the action and connection timeout)
11025 11:46:31.255834 /lava-10742249/bin/lava-test-runner /lava-10742249/0<4>[ 19.529886] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11026 11:46:31.259159
11027 11:46:31.299645 + export TESTRUN_ID=0_v4l2-compliance-uvc
11028 11:46:31.300243 + cd /lava-10742249/0/tests/0_v4l2-compliance-uvc
11029 11:46:31.300735 + cat uuid
11030 11:46:31.301209 + UUID=10742249_1.5.2.3.1
11031 11:46:31.301744 + set +x
11032 11:46:31.302511 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10742249_1.5.2.3.1>
11033 11:46:31.302983 + /usr/bin/v4l2-parser.sh -d uvcvideo
11034 11:46:31.303755 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10742249_1.5.2.3.1
11035 11:46:31.304101 Starting test lava.0_v4l2-compliance-uvc (10742249_1.5.2.3.1)
11036 11:46:31.304491 Skipping test definition patterns.
11037 11:46:31.305078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11038 11:46:31.305429 device: /dev/video0
11039 11:46:31.306004 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11041 11:46:31.347657 <3>[ 19.648047] mt7921e 0000:01:00.0: hardware init failed
11042 11:46:31.443781 <6>[ 19.740873] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11043 11:46:31.450263 <6>[ 19.748961] r8152 2-1.3:1.0 enx002432307852: carrier on
11044 11:46:35.363754 <4>[ 23.664822] ------------[ cut here ]------------
11045 11:46:35.370472 <4>[ 23.669734] get_vaddr_frames() cannot follow VM_IO mapping
11046 11:46:35.383651 <4>[ 23.669882] WARNING: CPU: 2 PID: 309 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11047 11:46:35.430291 <4>[ 23.687984] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb mtk_vcodec_enc btintel mtk_vcodec_common btmtk mtk_vpu uvcvideo v4l2_mem2mem btrtl videobuf2_dma_contig videobuf2_vmalloc r8153_ecm btbcm videobuf2_memops cros_ec_rpmsg cdc_ether videobuf2_v4l2 bluetooth videobuf2_common usbnet ecdh_generic videodev ecc rfkill elants_i2c crct10dif_ce mc sbs_battery elan_i2c r8152 hid_google_hammer pcie_mediatek_gen3 cros_ec_typec hid_vivaldi_common cros_ec_chardev mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11048 11:46:35.440015 <4>[ 23.737370] CPU: 2 PID: 309 Comm: v4l2-compliance Not tainted 6.1.31 #1
11049 11:46:35.443227 <4>[ 23.744234] Hardware name: Google Spherion (rev0 - 3) (DT)
11050 11:46:35.449842 <4>[ 23.749968] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11051 11:46:35.456380 <4>[ 23.757179] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11052 11:46:35.462768 <4>[ 23.763270] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11053 11:46:35.466728 <4>[ 23.769361] sp : ffff800009213810
11054 11:46:35.472705 <4>[ 23.772924] x29: ffff800009213810 x28: ffffd5b123130000 x27: ffffd5b12312c238
11055 11:46:35.482467 <4>[ 23.780311] x26: 0000000000000000 x25: ffffd5b1231304c0 x24: ffff32f18dac8538
11056 11:46:35.489251 <4>[ 23.787698] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11057 11:46:35.496335 <4>[ 23.795085] x20: 00000000fffffff2 x19: ffff32f18b951000 x18: fffffffffffe9538
11058 11:46:35.502753 <4>[ 23.802472] x17: 0000000000000000 x16: ffffd5b197c8bb60 x15: 0000000000000038
11059 11:46:35.512669 <4>[ 23.809859] x14: ffffd5b19a5834a8 x13: 0000000000000636 x12: 0000000000000212
11060 11:46:35.519106 <4>[ 23.817245] x11: fffffffffffe9538 x10: fffffffffffe9500 x9 : 00000000fffff212
11061 11:46:35.525582 <4>[ 23.824633] x8 : ffffd5b19a5834a8 x7 : ffffd5b19a5db4a8 x6 : 00000000000018d8
11062 11:46:35.532309 <4>[ 23.832020] x5 : ffff32f2bef3ea18 x4 : 00000000fffff212 x3 : ffff5d412507b000
11063 11:46:35.542673 <4>[ 23.839406] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff32f18d9a3b00
11064 11:46:35.543207 <4>[ 23.846794] Call trace:
11065 11:46:35.548631 <4>[ 23.849491] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11066 11:46:35.555232 <4>[ 23.855236] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11067 11:46:35.562306 <4>[ 23.861238] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11068 11:46:35.568875 <4>[ 23.867761] __prepare_userptr+0x280/0x410 [videobuf2_common]
11069 11:46:35.572016 <4>[ 23.873765] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11070 11:46:35.578619 <4>[ 23.879421] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11071 11:46:35.585008 <4>[ 23.885079] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11072 11:46:35.588863 <4>[ 23.889972] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11073 11:46:35.595189 <4>[ 23.895038] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11074 11:46:35.598370 <4>[ 23.899914] v4l_qbuf+0x48/0x60 [videodev]
11075 11:46:35.605290 <4>[ 23.904334] __video_do_ioctl+0x184/0x3d0 [videodev]
11076 11:46:35.608426 <4>[ 23.909578] video_usercopy+0x358/0x680 [videodev]
11077 11:46:35.611908 <4>[ 23.914649] video_ioctl2+0x18/0x30 [videodev]
11078 11:46:35.618561 <4>[ 23.919372] v4l2_ioctl+0x40/0x60 [videodev]
11079 11:46:35.621942 <4>[ 23.923923] __arm64_sys_ioctl+0xa8/0xf0
11080 11:46:35.625287 <4>[ 23.928105] invoke_syscall+0x48/0x114
11081 11:46:35.631541 <4>[ 23.932110] el0_svc_common.constprop.0+0x44/0xec
11082 11:46:35.634963 <4>[ 23.937065] do_el0_svc+0x2c/0xd0
11083 11:46:35.637999 <4>[ 23.940631] el0_svc+0x2c/0x84
11084 11:46:35.641392 <4>[ 23.943942] el0t_64_sync_handler+0xb8/0xc0
11085 11:46:35.644738 <4>[ 23.948375] el0t_64_sync+0x18c/0x190
11086 11:46:35.651263 <4>[ 23.952288] ---[ end trace 0000000000000000 ]---
11087 11:46:38.069535 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11088 11:46:38.079389 v4l2-compliance SHA: 57b6b2492f4a 2023-06-07 12:27:03
11089 11:46:38.085280
11090 11:46:38.097369 Compliance test for uvcvideo device /dev/video0:
11091 11:46:38.103945
11092 11:46:38.113202 Driver Info:
11093 11:46:38.123902 Driver name : uvcvideo
11094 11:46:38.136217 Card type : HD User Facing: HD User Facing
11095 11:46:38.145864 Bus info : usb-11200000.usb-1.4.1
11096 11:46:38.152121 Driver version : 6.1.31
11097 11:46:38.161136 Capabilities : 0x84a00001
11098 11:46:38.173431 Metadata Capture
11099 11:46:38.182910 Streaming
11100 11:46:38.192427 Extended Pix Format
11101 11:46:38.202304 Device Capabilities
11102 11:46:38.212387 Device Caps : 0x04200001
11103 11:46:38.224099 Streaming
11104 11:46:38.234469 Extended Pix Format
11105 11:46:38.244227 Media Driver Info:
11106 11:46:38.254520 Driver name : uvcvideo
11107 11:46:38.268104 Model : HD User Facing: HD User Facing
11108 11:46:38.274607 Serial : 200901010001
11109 11:46:38.288754 Bus info : usb-11200000.usb-1.4.1
11110 11:46:38.295838 Media version : 6.1.31
11111 11:46:38.310016 Hardware revision: 0x00009758 (38744)
11112 11:46:38.317235 Driver version : 6.1.31
11113 11:46:38.327919 Interface Info:
11114 11:46:38.342905 <LAVA_SIGNAL_TESTSET START Interface-Info>
11115 11:46:38.343092 ID : 0x03000002
11116 11:46:38.343426 Received signal: <TESTSET> START Interface-Info
11117 11:46:38.343550 Starting test_set Interface-Info
11118 11:46:38.353359 Type : V4L Video
11119 11:46:38.364608 Entity Info:
11120 11:46:38.371485 <LAVA_SIGNAL_TESTSET STOP>
11121 11:46:38.371814 Received signal: <TESTSET> STOP
11122 11:46:38.371894 Closing test_set Interface-Info
11123 11:46:38.381252 <LAVA_SIGNAL_TESTSET START Entity-Info>
11124 11:46:38.381535 Received signal: <TESTSET> START Entity-Info
11125 11:46:38.381609 Starting test_set Entity-Info
11126 11:46:38.384264 ID : 0x00000001 (1)
11127 11:46:38.393527 Name : HD User Facing: HD User Facing
11128 11:46:38.401070 Function : V4L2 I/O
11129 11:46:38.411636 Flags : default
11130 11:46:38.422374 Pad 0x01000007 : 0: Sink
11131 11:46:38.443216 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11132 11:46:38.443389
11133 11:46:38.454294 Required ioctls:
11134 11:46:38.460625 <LAVA_SIGNAL_TESTSET STOP>
11135 11:46:38.460970 Received signal: <TESTSET> STOP
11136 11:46:38.461071 Closing test_set Entity-Info
11137 11:46:38.469562 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11138 11:46:38.469902 Received signal: <TESTSET> START Required-ioctls
11139 11:46:38.470008 Starting test_set Required-ioctls
11140 11:46:38.472911 test MC information (see 'Media Driver Info' above): OK
11141 11:46:38.498269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11142 11:46:38.498634 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11144 11:46:38.501462 test VIDIOC_QUERYCAP: OK
11145 11:46:38.521006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11146 11:46:38.521400 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11148 11:46:38.524317 test invalid ioctls: OK
11149 11:46:38.545646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11150 11:46:38.545874
11151 11:46:38.546196 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11153 11:46:38.556884 Allow for multiple opens:
11154 11:46:38.564483 <LAVA_SIGNAL_TESTSET STOP>
11155 11:46:38.564860 Received signal: <TESTSET> STOP
11156 11:46:38.564979 Closing test_set Required-ioctls
11157 11:46:38.574054 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11158 11:46:38.574431 Received signal: <TESTSET> START Allow-for-multiple-opens
11159 11:46:38.574556 Starting test_set Allow-for-multiple-opens
11160 11:46:38.577133 test second /dev/video0 open: OK
11161 11:46:38.600191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11162 11:46:38.600513 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11164 11:46:38.603421 test VIDIOC_QUERYCAP: OK
11165 11:46:38.624561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11166 11:46:38.624820 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11168 11:46:38.627834 test VIDIOC_G/S_PRIORITY: OK
11169 11:46:38.649439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11170 11:46:38.649751 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11172 11:46:38.652803 test for unlimited opens: OK
11173 11:46:38.672998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11174 11:46:38.673141
11175 11:46:38.673390 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11177 11:46:38.683624 Debug ioctls:
11178 11:46:38.691281 <LAVA_SIGNAL_TESTSET STOP>
11179 11:46:38.691600 Received signal: <TESTSET> STOP
11180 11:46:38.691713 Closing test_set Allow-for-multiple-opens
11181 11:46:38.700929 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11182 11:46:38.701282 Received signal: <TESTSET> START Debug-ioctls
11183 11:46:38.701409 Starting test_set Debug-ioctls
11184 11:46:38.704240 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11185 11:46:38.726292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11186 11:46:38.726832 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11188 11:46:38.732321 test VIDIOC_LOG_STATUS: OK (Not Supported)
11189 11:46:38.750632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11190 11:46:38.750874
11191 11:46:38.751224 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11193 11:46:38.760663 Input ioctls:
11194 11:46:38.768340 <LAVA_SIGNAL_TESTSET STOP>
11195 11:46:38.768783 Received signal: <TESTSET> STOP
11196 11:46:38.768910 Closing test_set Debug-ioctls
11197 11:46:38.777642 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11198 11:46:38.778105 Received signal: <TESTSET> START Input-ioctls
11199 11:46:38.778287 Starting test_set Input-ioctls
11200 11:46:38.780657 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11201 11:46:38.804716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11202 11:46:38.805079 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11204 11:46:38.807776 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11205 11:46:38.826309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11206 11:46:38.826671 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11208 11:46:38.832804 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11209 11:46:38.852086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11210 11:46:38.852401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11212 11:46:38.858044 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11213 11:46:38.875598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11214 11:46:38.875859 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11216 11:46:38.878884 test VIDIOC_G/S/ENUMINPUT: OK
11217 11:46:38.899582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11218 11:46:38.899871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11220 11:46:38.906047 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11221 11:46:38.925279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11222 11:46:38.925538 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11224 11:46:38.928606 Inputs: 1 Audio Inputs: 0 Tuners: 0
11225 11:46:38.936683
11226 11:46:38.954609 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11227 11:46:38.976523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11228 11:46:38.976812 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11230 11:46:38.982972 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11231 11:46:39.001319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11232 11:46:39.001700 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11234 11:46:39.007617 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11235 11:46:39.027536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11236 11:46:39.027993 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11238 11:46:39.033682 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11239 11:46:39.052187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11240 11:46:39.052563 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11242 11:46:39.058721 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11243 11:46:39.077026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11244 11:46:39.077119
11245 11:46:39.077358 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11247 11:46:39.095845 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11248 11:46:39.117520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11249 11:46:39.117890 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11251 11:46:39.123957 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11252 11:46:39.146424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11253 11:46:39.147128 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11255 11:46:39.150282 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11256 11:46:39.168241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11257 11:46:39.168919 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11259 11:46:39.171681 test VIDIOC_G/S_EDID: OK (Not Supported)
11260 11:46:39.192465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11261 11:46:39.193038
11262 11:46:39.193808 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11264 11:46:39.203194 Control ioctls (Input 0):
11265 11:46:39.209923 <LAVA_SIGNAL_TESTSET STOP>
11266 11:46:39.210635 Received signal: <TESTSET> STOP
11267 11:46:39.210990 Closing test_set Input-ioctls
11268 11:46:39.219455 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11269 11:46:39.220127 Received signal: <TESTSET> START Control-ioctls-Input-0
11270 11:46:39.220542 Starting test_set Control-ioctls-Input-0
11271 11:46:39.222704 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11272 11:46:39.247554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11273 11:46:39.248145 test VIDIOC_QUERYCTRL: OK
11274 11:46:39.248765 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11276 11:46:39.268545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11277 11:46:39.269227 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11279 11:46:39.271910 test VIDIOC_G/S_CTRL: OK
11280 11:46:39.292720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11281 11:46:39.293477 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11283 11:46:39.296394 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11284 11:46:39.317670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11285 11:46:39.318367 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11287 11:46:39.324230 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11288 11:46:39.345357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11289 11:46:39.346104 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11291 11:46:39.348508 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11292 11:46:39.367635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11293 11:46:39.368398 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11295 11:46:39.370942 Standard Controls: 16 Private Controls: 0
11296 11:46:39.376671
11297 11:46:39.385965 Format ioctls (Input 0):
11298 11:46:39.392596 <LAVA_SIGNAL_TESTSET STOP>
11299 11:46:39.393353 Received signal: <TESTSET> STOP
11300 11:46:39.393731 Closing test_set Control-ioctls-Input-0
11301 11:46:39.402395 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11302 11:46:39.403186 Received signal: <TESTSET> START Format-ioctls-Input-0
11303 11:46:39.403698 Starting test_set Format-ioctls-Input-0
11304 11:46:39.405624 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11305 11:46:39.430872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11306 11:46:39.431706 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11308 11:46:39.433998 test VIDIOC_G/S_PARM: OK
11309 11:46:39.451267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11310 11:46:39.452008 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11312 11:46:39.454528 test VIDIOC_G_FBUF: OK (Not Supported)
11313 11:46:39.475908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11314 11:46:39.476778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11316 11:46:39.479313 test VIDIOC_G_FMT: OK
11317 11:46:39.500033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11318 11:46:39.500448 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11320 11:46:39.503198 test VIDIOC_TRY_FMT: OK
11321 11:46:39.523965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11322 11:46:39.524286 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11324 11:46:39.530504 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11325 11:46:39.534911 test VIDIOC_S_FMT: OK
11326 11:46:39.560958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11327 11:46:39.561222 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11329 11:46:39.563429 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11330 11:46:39.586696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11331 11:46:39.587040 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11333 11:46:39.589867 test Cropping: OK (Not Supported)
11334 11:46:39.612047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11335 11:46:39.612781 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11337 11:46:39.615150 test Composing: OK (Not Supported)
11338 11:46:39.636935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11339 11:46:39.637821 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11341 11:46:39.640349 test Scaling: OK (Not Supported)
11342 11:46:39.661038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11343 11:46:39.661646
11344 11:46:39.662446 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11346 11:46:39.671593 Codec ioctls (Input 0):
11347 11:46:39.678979 <LAVA_SIGNAL_TESTSET STOP>
11348 11:46:39.679869 Received signal: <TESTSET> STOP
11349 11:46:39.680398 Closing test_set Format-ioctls-Input-0
11350 11:46:39.689497 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11351 11:46:39.690395 Received signal: <TESTSET> START Codec-ioctls-Input-0
11352 11:46:39.690884 Starting test_set Codec-ioctls-Input-0
11353 11:46:39.692166 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11354 11:46:39.725152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11355 11:46:39.726008 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11357 11:46:39.731870 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11358 11:46:39.751595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11359 11:46:39.752292 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11361 11:46:39.757999 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11362 11:46:39.776105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11363 11:46:39.776570
11364 11:46:39.777163 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11366 11:46:39.786354 Buffer ioctls (Input 0):
11367 11:46:39.793047 <LAVA_SIGNAL_TESTSET STOP>
11368 11:46:39.793874 Received signal: <TESTSET> STOP
11369 11:46:39.794432 Closing test_set Codec-ioctls-Input-0
11370 11:46:39.802867 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11371 11:46:39.803739 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11372 11:46:39.804207 Starting test_set Buffer-ioctls-Input-0
11373 11:46:39.806181 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11374 11:46:39.828955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11375 11:46:39.829555 test VIDIOC_EXPBUF: OK
11376 11:46:39.830306 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11378 11:46:39.850581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11379 11:46:39.851522 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11381 11:46:39.853931 test Requests: OK (Not Supported)
11382 11:46:39.874885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11383 11:46:39.875248
11384 11:46:39.875717 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11386 11:46:39.884908 Test input 0:
11387 11:46:39.894359
11388 11:46:39.903882 Streaming ioctls:
11389 11:46:39.909724 <LAVA_SIGNAL_TESTSET STOP>
11390 11:46:39.910094 Received signal: <TESTSET> STOP
11391 11:46:39.910199 Closing test_set Buffer-ioctls-Input-0
11392 11:46:39.919228 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11393 11:46:39.919650 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11394 11:46:39.919784 Starting test_set Streaming-ioctls_Test-input-0
11395 11:46:39.922477 test read/write: OK (Not Supported)
11396 11:46:39.945300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11397 11:46:39.945680 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11399 11:46:39.948124 test blocking wait: OK
11400 11:46:39.968128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11401 11:46:39.968595 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11403 11:46:39.978080 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11404 11:46:39.981619 test MMAP (no poll): FAIL
11405 11:46:40.003215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11406 11:46:40.004172 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11408 11:46:40.013132 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11409 11:46:40.013564 test MMAP (select): FAIL
11410 11:46:40.037492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11411 11:46:40.038200 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11413 11:46:40.046993 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11414 11:46:40.050887 test MMAP (epoll): FAIL
11415 11:46:40.072221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11416 11:46:40.072313
11417 11:46:40.072546 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11419 11:46:40.084095
11420 11:46:40.235571
11421 11:46:40.240569 test USERPTR (no poll): OK
11422 11:46:40.263814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11423 11:46:40.263932
11424 11:46:40.264178 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11426 11:46:40.277395
11427 11:46:40.445486
11428 11:46:40.452520 test USERPTR (select): OK
11429 11:46:40.476926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11430 11:46:40.477222 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11432 11:46:40.483197 test DMABUF: Cannot test, specify --expbuf-device
11433 11:46:40.488397
11434 11:46:40.505986 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11435 11:46:40.509191 <LAVA_TEST_RUNNER EXIT>
11436 11:46:40.509469 ok: lava_test_shell seems to have completed
11437 11:46:40.509543 Marking unfinished test run as failed
11439 11:46:40.511223 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11440 11:46:40.511415 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11441 11:46:40.511530 end: 3 lava-test-retry (duration 00:00:10) [common]
11442 11:46:40.511648 start: 4 finalize (timeout 00:07:12) [common]
11443 11:46:40.511766 start: 4.1 power-off (timeout 00:00:30) [common]
11444 11:46:40.511923 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11445 11:46:40.588917 >> Command sent successfully.
11446 11:46:40.592116 Returned 0 in 0 seconds
11447 11:46:40.692578 end: 4.1 power-off (duration 00:00:00) [common]
11449 11:46:40.693143 start: 4.2 read-feedback (timeout 00:07:12) [common]
11450 11:46:40.693543 Listened to connection for namespace 'common' for up to 1s
11451 11:46:41.694261 Finalising connection for namespace 'common'
11452 11:46:41.694616 Disconnecting from shell: Finalise
11453 11:46:41.694704 / #
11454 11:46:41.795014 end: 4.2 read-feedback (duration 00:00:01) [common]
11455 11:46:41.795193 end: 4 finalize (duration 00:00:01) [common]
11456 11:46:41.795361 Cleaning after the job
11457 11:46:41.795529 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/ramdisk
11458 11:46:41.801187 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/kernel
11459 11:46:41.816896 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/dtb
11460 11:46:41.817155 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742249/tftp-deploy-_g234_cb/modules
11461 11:46:41.824686 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742249
11462 11:46:41.883437 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742249
11463 11:46:41.883608 Job finished correctly