Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 40
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
- Errors: 0
1 11:39:42.700462 lava-dispatcher, installed at version: 2023.05.1
2 11:39:42.700671 start: 0 validate
3 11:39:42.700798 Start time: 2023-06-15 11:39:42.700788+00:00 (UTC)
4 11:39:42.700916 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:39:42.701122 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 11:39:42.979269 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:39:42.980081 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:39:43.242159 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:39:43.242954 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:39:59.496292 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:39:59.497078 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:40:00.017172 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:40:00.017845 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:40:00.286943 validate duration: 17.59
16 11:40:00.288227 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:40:00.288760 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:40:00.289317 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:40:00.289922 Not decompressing ramdisk as can be used compressed.
20 11:40:00.290396 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/initrd.cpio.gz
21 11:40:00.290766 saving as /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/ramdisk/initrd.cpio.gz
22 11:40:00.291104 total size: 4665397 (4MB)
23 11:40:03.600086 progress 0% (0MB)
24 11:40:03.604604 progress 5% (0MB)
25 11:40:03.605849 progress 10% (0MB)
26 11:40:03.607037 progress 15% (0MB)
27 11:40:03.608224 progress 20% (0MB)
28 11:40:03.609437 progress 25% (1MB)
29 11:40:03.610605 progress 30% (1MB)
30 11:40:03.611776 progress 35% (1MB)
31 11:40:03.613121 progress 40% (1MB)
32 11:40:03.614495 progress 45% (2MB)
33 11:40:03.615664 progress 50% (2MB)
34 11:40:03.616834 progress 55% (2MB)
35 11:40:03.618077 progress 60% (2MB)
36 11:40:03.619249 progress 65% (2MB)
37 11:40:03.620415 progress 70% (3MB)
38 11:40:03.621653 progress 75% (3MB)
39 11:40:03.622820 progress 80% (3MB)
40 11:40:03.624231 progress 85% (3MB)
41 11:40:03.625490 progress 90% (4MB)
42 11:40:03.626661 progress 95% (4MB)
43 11:40:03.627852 progress 100% (4MB)
44 11:40:03.628001 4MB downloaded in 3.34s (1.33MB/s)
45 11:40:03.628147 end: 1.1.1 http-download (duration 00:00:03) [common]
47 11:40:03.628385 end: 1.1 download-retry (duration 00:00:03) [common]
48 11:40:03.628470 start: 1.2 download-retry (timeout 00:09:57) [common]
49 11:40:03.628553 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 11:40:03.628679 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:40:03.628748 saving as /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/kernel/Image
52 11:40:03.628809 total size: 47581696 (45MB)
53 11:40:03.628868 No compression specified
54 11:40:03.630062 progress 0% (0MB)
55 11:40:03.641956 progress 5% (2MB)
56 11:40:03.653801 progress 10% (4MB)
57 11:40:03.665385 progress 15% (6MB)
58 11:40:03.677047 progress 20% (9MB)
59 11:40:03.688717 progress 25% (11MB)
60 11:40:03.700215 progress 30% (13MB)
61 11:40:03.711976 progress 35% (15MB)
62 11:40:03.723828 progress 40% (18MB)
63 11:40:03.735975 progress 45% (20MB)
64 11:40:03.747865 progress 50% (22MB)
65 11:40:03.759516 progress 55% (24MB)
66 11:40:03.771284 progress 60% (27MB)
67 11:40:03.782752 progress 65% (29MB)
68 11:40:03.794375 progress 70% (31MB)
69 11:40:03.806110 progress 75% (34MB)
70 11:40:03.817894 progress 80% (36MB)
71 11:40:03.829776 progress 85% (38MB)
72 11:40:03.841527 progress 90% (40MB)
73 11:40:03.853320 progress 95% (43MB)
74 11:40:03.864932 progress 100% (45MB)
75 11:40:03.865058 45MB downloaded in 0.24s (192.08MB/s)
76 11:40:03.865203 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:40:03.865435 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:40:03.865522 start: 1.3 download-retry (timeout 00:09:56) [common]
80 11:40:03.865608 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 11:40:03.865757 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:40:03.865882 saving as /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/dtb/mt8192-asurada-spherion-r0.dtb
83 11:40:03.865977 total size: 46924 (0MB)
84 11:40:03.866035 No compression specified
85 11:40:03.867118 progress 69% (0MB)
86 11:40:03.867379 progress 100% (0MB)
87 11:40:03.867529 0MB downloaded in 0.00s (28.86MB/s)
88 11:40:03.867648 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:40:03.867869 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:40:03.867969 start: 1.4 download-retry (timeout 00:09:56) [common]
92 11:40:03.868052 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 11:40:03.868158 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/full.rootfs.tar.xz
94 11:40:03.868224 saving as /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/nfsrootfs/full.rootfs.tar
95 11:40:03.868283 total size: 200816996 (191MB)
96 11:40:03.868340 Using unxz to decompress xz
97 11:40:03.871798 progress 0% (0MB)
98 11:40:04.393420 progress 5% (9MB)
99 11:40:04.889276 progress 10% (19MB)
100 11:40:05.458459 progress 15% (28MB)
101 11:40:05.832903 progress 20% (38MB)
102 11:40:06.154221 progress 25% (47MB)
103 11:40:06.730443 progress 30% (57MB)
104 11:40:07.264759 progress 35% (67MB)
105 11:40:07.842242 progress 40% (76MB)
106 11:40:08.386067 progress 45% (86MB)
107 11:40:08.955207 progress 50% (95MB)
108 11:40:09.565172 progress 55% (105MB)
109 11:40:10.210056 progress 60% (114MB)
110 11:40:10.326392 progress 65% (124MB)
111 11:40:10.460646 progress 70% (134MB)
112 11:40:10.542632 progress 75% (143MB)
113 11:40:10.612202 progress 80% (153MB)
114 11:40:10.684728 progress 85% (162MB)
115 11:40:10.786144 progress 90% (172MB)
116 11:40:11.059624 progress 95% (181MB)
117 11:40:11.617550 progress 100% (191MB)
118 11:40:11.623086 191MB downloaded in 7.75s (24.70MB/s)
119 11:40:11.623377 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:40:11.623670 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:40:11.623760 start: 1.5 download-retry (timeout 00:09:49) [common]
123 11:40:11.623891 start: 1.5.1 http-download (timeout 00:09:49) [common]
124 11:40:11.624139 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:40:11.624210 saving as /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/modules/modules.tar
126 11:40:11.624271 total size: 8555256 (8MB)
127 11:40:11.624378 Using unxz to decompress xz
128 11:40:11.885964 progress 0% (0MB)
129 11:40:11.912377 progress 5% (0MB)
130 11:40:11.937600 progress 10% (0MB)
131 11:40:11.961168 progress 15% (1MB)
132 11:40:11.985148 progress 20% (1MB)
133 11:40:12.009664 progress 25% (2MB)
134 11:40:12.031859 progress 30% (2MB)
135 11:40:12.056872 progress 35% (2MB)
136 11:40:12.080554 progress 40% (3MB)
137 11:40:12.103529 progress 45% (3MB)
138 11:40:12.130147 progress 50% (4MB)
139 11:40:12.154483 progress 55% (4MB)
140 11:40:12.179542 progress 60% (4MB)
141 11:40:12.204362 progress 65% (5MB)
142 11:40:12.228700 progress 70% (5MB)
143 11:40:12.251991 progress 75% (6MB)
144 11:40:12.274923 progress 80% (6MB)
145 11:40:12.298267 progress 85% (6MB)
146 11:40:12.326285 progress 90% (7MB)
147 11:40:12.352864 progress 95% (7MB)
148 11:40:12.377225 progress 100% (8MB)
149 11:40:12.381509 8MB downloaded in 0.76s (10.77MB/s)
150 11:40:12.381772 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:40:12.382093 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:40:12.382197 start: 1.6 prepare-tftp-overlay (timeout 00:09:48) [common]
154 11:40:12.382306 start: 1.6.1 extract-nfsrootfs (timeout 00:09:48) [common]
155 11:40:15.564815 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10742235/extract-nfsrootfs-_bg7toz5
156 11:40:15.565029 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:40:15.565139 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
158 11:40:15.565303 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63
159 11:40:15.565428 makedir: /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin
160 11:40:15.565531 makedir: /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/tests
161 11:40:15.565626 makedir: /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/results
162 11:40:15.565724 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-add-keys
163 11:40:15.565861 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-add-sources
164 11:40:15.565990 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-background-process-start
165 11:40:15.566112 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-background-process-stop
166 11:40:15.566231 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-common-functions
167 11:40:15.566348 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-echo-ipv4
168 11:40:15.566468 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-install-packages
169 11:40:15.566584 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-installed-packages
170 11:40:15.566703 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-os-build
171 11:40:15.566820 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-probe-channel
172 11:40:15.566936 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-probe-ip
173 11:40:15.567052 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-target-ip
174 11:40:15.567168 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-target-mac
175 11:40:15.567284 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-target-storage
176 11:40:15.567403 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-test-case
177 11:40:15.567524 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-test-event
178 11:40:15.567642 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-test-feedback
179 11:40:15.567760 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-test-raise
180 11:40:15.567876 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-test-reference
181 11:40:15.567993 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-test-runner
182 11:40:15.568109 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-test-set
183 11:40:15.568225 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-test-shell
184 11:40:15.568342 Updating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-add-keys (debian)
185 11:40:15.568492 Updating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-add-sources (debian)
186 11:40:15.568624 Updating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-install-packages (debian)
187 11:40:15.568755 Updating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-installed-packages (debian)
188 11:40:15.568884 Updating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/bin/lava-os-build (debian)
189 11:40:15.569024 Creating /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/environment
190 11:40:15.569127 LAVA metadata
191 11:40:15.569195 - LAVA_JOB_ID=10742235
192 11:40:15.569256 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:40:15.569352 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:45) [common]
194 11:40:15.569427 skipped lava-vland-overlay
195 11:40:15.569498 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:40:15.569574 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:45) [common]
197 11:40:15.569633 skipped lava-multinode-overlay
198 11:40:15.569702 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:40:15.569777 start: 1.6.2.3 test-definition (timeout 00:09:45) [common]
200 11:40:15.569847 Loading test definitions
201 11:40:15.569936 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:45) [common]
202 11:40:15.570008 Using /lava-10742235 at stage 0
203 11:40:15.570283 uuid=10742235_1.6.2.3.1 testdef=None
204 11:40:15.570368 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:40:15.570454 start: 1.6.2.3.2 test-overlay (timeout 00:09:45) [common]
206 11:40:15.570886 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:40:15.571107 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:45) [common]
209 11:40:15.571640 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:40:15.571867 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:45) [common]
212 11:40:15.572382 runner path: /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/0/tests/0_timesync-off test_uuid 10742235_1.6.2.3.1
213 11:40:15.572529 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:40:15.572745 start: 1.6.2.3.5 git-repo-action (timeout 00:09:45) [common]
216 11:40:15.572815 Using /lava-10742235 at stage 0
217 11:40:15.572907 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:40:15.573121 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/0/tests/1_kselftest-arm64'
219 11:40:27.243778 Running '/usr/bin/git checkout kernelci.org
220 11:40:27.385209 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 11:40:27.385888 uuid=10742235_1.6.2.3.5 testdef=None
222 11:40:27.386044 end: 1.6.2.3.5 git-repo-action (duration 00:00:12) [common]
224 11:40:27.386292 start: 1.6.2.3.6 test-overlay (timeout 00:09:33) [common]
225 11:40:27.387036 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:40:27.387269 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:33) [common]
228 11:40:27.388219 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:40:27.388454 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:33) [common]
231 11:40:27.389400 runner path: /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/0/tests/1_kselftest-arm64 test_uuid 10742235_1.6.2.3.5
232 11:40:27.389494 BOARD='mt8192-asurada-spherion-r0'
233 11:40:27.389559 BRANCH='cip'
234 11:40:27.389617 SKIPFILE='/dev/null'
235 11:40:27.389675 SKIP_INSTALL='True'
236 11:40:27.389729 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:40:27.389786 TST_CASENAME=''
238 11:40:27.389840 TST_CMDFILES='arm64'
239 11:40:27.389981 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:40:27.390187 Creating lava-test-runner.conf files
242 11:40:27.390250 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742235/lava-overlay-so7b2f63/lava-10742235/0 for stage 0
243 11:40:27.390345 - 0_timesync-off
244 11:40:27.390415 - 1_kselftest-arm64
245 11:40:27.390510 end: 1.6.2.3 test-definition (duration 00:00:12) [common]
246 11:40:27.390600 start: 1.6.2.4 compress-overlay (timeout 00:09:33) [common]
247 11:40:34.727123 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:40:34.727272 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:26) [common]
249 11:40:34.727364 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:40:34.727464 end: 1.6.2 lava-overlay (duration 00:00:19) [common]
251 11:40:34.727554 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:26) [common]
252 11:40:34.838289 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:40:34.838632 start: 1.6.4 extract-modules (timeout 00:09:25) [common]
254 11:40:34.838741 extracting modules file /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742235/extract-nfsrootfs-_bg7toz5
255 11:40:35.038970 extracting modules file /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742235/extract-overlay-ramdisk-qawnwe8w/ramdisk
256 11:40:35.242411 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:40:35.242579 start: 1.6.5 apply-overlay-tftp (timeout 00:09:25) [common]
258 11:40:35.242675 [common] Applying overlay to NFS
259 11:40:35.242741 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742235/compress-overlay-cxs52jsb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742235/extract-nfsrootfs-_bg7toz5
260 11:40:36.123719 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:40:36.123880 start: 1.6.6 configure-preseed-file (timeout 00:09:24) [common]
262 11:40:36.123976 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:40:36.124070 start: 1.6.7 compress-ramdisk (timeout 00:09:24) [common]
264 11:40:36.124154 Building ramdisk /var/lib/lava/dispatcher/tmp/10742235/extract-overlay-ramdisk-qawnwe8w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742235/extract-overlay-ramdisk-qawnwe8w/ramdisk
265 11:40:36.418085 >> 117806 blocks
266 11:40:38.320864 rename /var/lib/lava/dispatcher/tmp/10742235/extract-overlay-ramdisk-qawnwe8w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/ramdisk/ramdisk.cpio.gz
267 11:40:38.321323 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:40:38.321442 start: 1.6.8 prepare-kernel (timeout 00:09:22) [common]
269 11:40:38.321538 start: 1.6.8.1 prepare-fit (timeout 00:09:22) [common]
270 11:40:38.321642 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/kernel/Image'
271 11:40:49.992185 Returned 0 in 11 seconds
272 11:40:50.092774 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/kernel/image.itb
273 11:40:50.398192 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:40:50.398536 output: Created: Thu Jun 15 12:40:50 2023
275 11:40:50.398613 output: Image 0 (kernel-1)
276 11:40:50.398679 output: Description:
277 11:40:50.398745 output: Created: Thu Jun 15 12:40:50 2023
278 11:40:50.398804 output: Type: Kernel Image
279 11:40:50.398863 output: Compression: lzma compressed
280 11:40:50.398922 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
281 11:40:50.398980 output: Architecture: AArch64
282 11:40:50.399037 output: OS: Linux
283 11:40:50.399092 output: Load Address: 0x00000000
284 11:40:50.399148 output: Entry Point: 0x00000000
285 11:40:50.399203 output: Hash algo: crc32
286 11:40:50.399256 output: Hash value: cd22d0e5
287 11:40:50.399309 output: Image 1 (fdt-1)
288 11:40:50.399362 output: Description: mt8192-asurada-spherion-r0
289 11:40:50.399415 output: Created: Thu Jun 15 12:40:50 2023
290 11:40:50.399469 output: Type: Flat Device Tree
291 11:40:50.399522 output: Compression: uncompressed
292 11:40:50.399575 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 11:40:50.399628 output: Architecture: AArch64
294 11:40:50.399680 output: Hash algo: crc32
295 11:40:50.399733 output: Hash value: 1df858fa
296 11:40:50.399786 output: Image 2 (ramdisk-1)
297 11:40:50.399838 output: Description: unavailable
298 11:40:50.399891 output: Created: Thu Jun 15 12:40:50 2023
299 11:40:50.399944 output: Type: RAMDisk Image
300 11:40:50.399997 output: Compression: Unknown Compression
301 11:40:50.400049 output: Data Size: 17646201 Bytes = 17232.62 KiB = 16.83 MiB
302 11:40:50.400102 output: Architecture: AArch64
303 11:40:50.400154 output: OS: Linux
304 11:40:50.400207 output: Load Address: unavailable
305 11:40:50.400259 output: Entry Point: unavailable
306 11:40:50.400311 output: Hash algo: crc32
307 11:40:50.400364 output: Hash value: abf0935a
308 11:40:50.400416 output: Default Configuration: 'conf-1'
309 11:40:50.400470 output: Configuration 0 (conf-1)
310 11:40:50.400522 output: Description: mt8192-asurada-spherion-r0
311 11:40:50.400574 output: Kernel: kernel-1
312 11:40:50.400625 output: Init Ramdisk: ramdisk-1
313 11:40:50.400678 output: FDT: fdt-1
314 11:40:50.400730 output: Loadables: kernel-1
315 11:40:50.400782 output:
316 11:40:50.400981 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 11:40:50.401122 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 11:40:50.401224 end: 1.6 prepare-tftp-overlay (duration 00:00:38) [common]
319 11:40:50.401321 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:10) [common]
320 11:40:50.401403 No LXC device requested
321 11:40:50.401481 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:40:50.401568 start: 1.8 deploy-device-env (timeout 00:09:10) [common]
323 11:40:50.401645 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:40:50.401714 Checking files for TFTP limit of 4294967296 bytes.
325 11:40:50.402192 end: 1 tftp-deploy (duration 00:00:50) [common]
326 11:40:50.402303 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:40:50.402396 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:40:50.402599 substitutions:
329 11:40:50.402669 - {DTB}: 10742235/tftp-deploy-b86my2hz/dtb/mt8192-asurada-spherion-r0.dtb
330 11:40:50.402734 - {INITRD}: 10742235/tftp-deploy-b86my2hz/ramdisk/ramdisk.cpio.gz
331 11:40:50.402793 - {KERNEL}: 10742235/tftp-deploy-b86my2hz/kernel/Image
332 11:40:50.402850 - {LAVA_MAC}: None
333 11:40:50.402906 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10742235/extract-nfsrootfs-_bg7toz5
334 11:40:50.402962 - {NFS_SERVER_IP}: 192.168.201.1
335 11:40:50.403016 - {PRESEED_CONFIG}: None
336 11:40:50.403070 - {PRESEED_LOCAL}: None
337 11:40:50.403124 - {RAMDISK}: 10742235/tftp-deploy-b86my2hz/ramdisk/ramdisk.cpio.gz
338 11:40:50.403179 - {ROOT_PART}: None
339 11:40:50.403234 - {ROOT}: None
340 11:40:50.403288 - {SERVER_IP}: 192.168.201.1
341 11:40:50.403341 - {TEE}: None
342 11:40:50.403396 Parsed boot commands:
343 11:40:50.403450 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:40:50.403623 Parsed boot commands: tftpboot 192.168.201.1 10742235/tftp-deploy-b86my2hz/kernel/image.itb 10742235/tftp-deploy-b86my2hz/kernel/cmdline
345 11:40:50.403719 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:40:50.403807 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:40:50.403900 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:40:50.403990 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:40:50.404060 Not connected, no need to disconnect.
350 11:40:50.404134 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:40:50.404217 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:40:50.404287 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
353 11:40:50.407735 Setting prompt string to ['lava-test: # ']
354 11:40:50.408084 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:40:50.408195 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:40:50.408299 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:40:50.408403 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:40:50.408610 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 11:40:55.546804 >> Command sent successfully.
360 11:40:55.549407 Returned 0 in 5 seconds
361 11:40:55.649801 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:40:55.650117 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:40:55.650219 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:40:55.650309 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:40:55.650381 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:40:55.650453 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:40:55.650751 [Enter `^Ec?' for help]
369 11:40:55.822452
370 11:40:55.822584
371 11:40:55.822654 F0: 102B 0000
372 11:40:55.822718
373 11:40:55.822777 F3: 1001 0000 [0200]
374 11:40:55.826227
375 11:40:55.826310 F3: 1001 0000
376 11:40:55.826377
377 11:40:55.826438 F7: 102D 0000
378 11:40:55.826498
379 11:40:55.826557 F1: 0000 0000
380 11:40:55.830061
381 11:40:55.830144 V0: 0000 0000 [0001]
382 11:40:55.830216
383 11:40:55.830277 00: 0007 8000
384 11:40:55.830341
385 11:40:55.834168 01: 0000 0000
386 11:40:55.834255
387 11:40:55.834321 BP: 0C00 0209 [0000]
388 11:40:55.834382
389 11:40:55.837669 G0: 1182 0000
390 11:40:55.837752
391 11:40:55.837818 EC: 0000 0021 [4000]
392 11:40:55.837879
393 11:40:55.841360 S7: 0000 0000 [0000]
394 11:40:55.841443
395 11:40:55.841509 CC: 0000 0000 [0001]
396 11:40:55.841578
397 11:40:55.844858 T0: 0000 0040 [010F]
398 11:40:55.844970
399 11:40:55.845062 Jump to BL
400 11:40:55.845125
401 11:40:55.869239
402 11:40:55.869327
403 11:40:55.869394
404 11:40:55.876231 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:40:55.880154 ARM64: Exception handlers installed.
406 11:40:55.883002 ARM64: Testing exception
407 11:40:55.886671 ARM64: Done test exception
408 11:40:55.894047 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:40:55.904333 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:40:55.911343 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:40:55.921526 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:40:55.928292 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:40:55.935009 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:40:55.946697 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:40:55.952908 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:40:55.972306 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:40:55.975776 WDT: Last reset was cold boot
418 11:40:55.978804 SPI1(PAD0) initialized at 2873684 Hz
419 11:40:55.982412 SPI5(PAD0) initialized at 992727 Hz
420 11:40:55.985908 VBOOT: Loading verstage.
421 11:40:55.992344 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:40:55.995579 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:40:55.998968 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:40:56.002332 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:40:56.009967 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:40:56.016270 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:40:56.027161 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 11:40:56.027245
429 11:40:56.027310
430 11:40:56.037691 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:40:56.040632 ARM64: Exception handlers installed.
432 11:40:56.043956 ARM64: Testing exception
433 11:40:56.044042 ARM64: Done test exception
434 11:40:56.050760 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:40:56.054007 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:40:56.068469 Probing TPM: . done!
437 11:40:56.068552 TPM ready after 0 ms
438 11:40:56.075074 Connected to device vid:did:rid of 1ae0:0028:00
439 11:40:56.081857 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 11:40:56.085849 Initialized TPM device CR50 revision 0
441 11:40:56.152339 tlcl_send_startup: Startup return code is 0
442 11:40:56.152434 TPM: setup succeeded
443 11:40:56.163850 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:40:56.172614 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:40:56.182761 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:40:56.191925 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:40:56.195463 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:40:56.203065 in-header: 03 07 00 00 08 00 00 00
449 11:40:56.206873 in-data: aa e4 47 04 13 02 00 00
450 11:40:56.210244 Chrome EC: UHEPI supported
451 11:40:56.217396 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:40:56.220925 in-header: 03 ad 00 00 08 00 00 00
453 11:40:56.224920 in-data: 00 20 20 08 00 00 00 00
454 11:40:56.225037 Phase 1
455 11:40:56.228439 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:40:56.235903 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:40:56.239793 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:40:56.243507 Recovery requested (1009000e)
459 11:40:56.252786 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:40:56.259345 tlcl_extend: response is 0
461 11:40:56.269115 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:40:56.274858 tlcl_extend: response is 0
463 11:40:56.282088 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:40:56.302549 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:40:56.309341 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:40:56.309426
467 11:40:56.309491
468 11:40:56.319000 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:40:56.322307 ARM64: Exception handlers installed.
470 11:40:56.322390 ARM64: Testing exception
471 11:40:56.325719 ARM64: Done test exception
472 11:40:56.347659 pmic_efuse_setting: Set efuses in 11 msecs
473 11:40:56.351171 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:40:56.358396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:40:56.361258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:40:56.367840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:40:56.371262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:40:56.374731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:40:56.382150 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:40:56.385607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:40:56.389395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:40:56.396836 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:40:56.400180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:40:56.403964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:40:56.411075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:40:56.414126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:40:56.420491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:40:56.423810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:40:56.430988 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:40:56.438775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:40:56.442169 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:40:56.449106 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:40:56.452291 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:40:56.459611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:40:56.466733 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:40:56.469862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:40:56.476391 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:40:56.479778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:40:56.486247 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:40:56.493205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:40:56.496521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:40:56.503056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:40:56.506637 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:40:56.513077 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:40:56.516270 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:40:56.523205 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:40:56.526228 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:40:56.532912 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:40:56.536287 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:40:56.542887 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:40:56.546298 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:40:56.549488 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:40:56.556162 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:40:56.559409 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:40:56.563078 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:40:56.570387 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:40:56.573254 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:40:56.576547 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:40:56.583376 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:40:56.586870 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:40:56.589963 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:40:56.593386 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:40:56.599794 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:40:56.603409 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:40:56.609782 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:40:56.619813 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:40:56.623026 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:40:56.633230 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:40:56.639547 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:40:56.646496 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:40:56.649633 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:40:56.652958 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:40:56.660550 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2
534 11:40:56.666685 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:40:56.670366 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:40:56.676722 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:40:56.684752 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 11:40:56.694175 [RTC]rtc_get_frequency_meter,154: input=23, output=956
539 11:40:56.703857 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 11:40:56.713029 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 11:40:56.722785 [RTC]rtc_get_frequency_meter,154: input=16, output=795
542 11:40:56.726031 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 11:40:56.732499 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 11:40:56.736210 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 11:40:56.739272 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 11:40:56.742400 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 11:40:56.745992 ADC[4]: Raw value=902507 ID=7
548 11:40:56.749349 ADC[3]: Raw value=213179 ID=1
549 11:40:56.752934 RAM Code: 0x71
550 11:40:56.756250 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 11:40:56.759632 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 11:40:56.769377 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 11:40:56.776236 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:40:56.779628 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 11:40:56.782767 in-header: 03 07 00 00 08 00 00 00
556 11:40:56.785994 in-data: aa e4 47 04 13 02 00 00
557 11:40:56.789486 Chrome EC: UHEPI supported
558 11:40:56.796034 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 11:40:56.799373 in-header: 03 ed 00 00 08 00 00 00
560 11:40:56.802867 in-data: 80 20 60 08 00 00 00 00
561 11:40:56.806007 MRC: failed to locate region type 0.
562 11:40:56.813219 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 11:40:56.813336 DRAM-K: Running full calibration
564 11:40:56.820769 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 11:40:56.824113 header.status = 0x0
566 11:40:56.824196 header.version = 0x6 (expected: 0x6)
567 11:40:56.828195 header.size = 0xd00 (expected: 0xd00)
568 11:40:56.831404 header.flags = 0x0
569 11:40:56.838451 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 11:40:56.855313 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 11:40:56.862996 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 11:40:56.866240 dram_init: ddr_geometry: 2
573 11:40:56.866323 [EMI] MDL number = 2
574 11:40:56.869682 [EMI] Get MDL freq = 0
575 11:40:56.869764 dram_init: ddr_type: 0
576 11:40:56.872965 is_discrete_lpddr4: 1
577 11:40:56.876515 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 11:40:56.876598
579 11:40:56.876664
580 11:40:56.879846 [Bian_co] ETT version 0.0.0.1
581 11:40:56.882893 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 11:40:56.882976
583 11:40:56.886538 dramc_set_vcore_voltage set vcore to 650000
584 11:40:56.889879 Read voltage for 800, 4
585 11:40:56.889962 Vio18 = 0
586 11:40:56.892887 Vcore = 650000
587 11:40:56.893018 Vdram = 0
588 11:40:56.893113 Vddq = 0
589 11:40:56.893202 Vmddr = 0
590 11:40:56.896686 dram_init: config_dvfs: 1
591 11:40:56.903019 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 11:40:56.906538 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 11:40:56.909916 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 11:40:56.916365 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 11:40:56.919703 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 11:40:56.923699 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 11:40:56.923782 MEM_TYPE=3, freq_sel=18
598 11:40:56.927166 sv_algorithm_assistance_LP4_1600
599 11:40:56.930860 ============ PULL DRAM RESETB DOWN ============
600 11:40:56.934787 ========== PULL DRAM RESETB DOWN end =========
601 11:40:56.942137 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 11:40:56.945962 ===================================
603 11:40:56.946045 LPDDR4 DRAM CONFIGURATION
604 11:40:56.949814 ===================================
605 11:40:56.953468 EX_ROW_EN[0] = 0x0
606 11:40:56.953552 EX_ROW_EN[1] = 0x0
607 11:40:56.956621 LP4Y_EN = 0x0
608 11:40:56.956703 WORK_FSP = 0x0
609 11:40:56.960323 WL = 0x2
610 11:40:56.960406 RL = 0x2
611 11:40:56.963259 BL = 0x2
612 11:40:56.963342 RPST = 0x0
613 11:40:56.966696 RD_PRE = 0x0
614 11:40:56.966778 WR_PRE = 0x1
615 11:40:56.969516 WR_PST = 0x0
616 11:40:56.969598 DBI_WR = 0x0
617 11:40:56.972920 DBI_RD = 0x0
618 11:40:56.973039 OTF = 0x1
619 11:40:56.976625 ===================================
620 11:40:56.979619 ===================================
621 11:40:56.983161 ANA top config
622 11:40:56.986916 ===================================
623 11:40:56.989921 DLL_ASYNC_EN = 0
624 11:40:56.990004 ALL_SLAVE_EN = 1
625 11:40:56.993339 NEW_RANK_MODE = 1
626 11:40:56.996668 DLL_IDLE_MODE = 1
627 11:40:56.999709 LP45_APHY_COMB_EN = 1
628 11:40:56.999792 TX_ODT_DIS = 1
629 11:40:57.003264 NEW_8X_MODE = 1
630 11:40:57.006590 ===================================
631 11:40:57.010025 ===================================
632 11:40:57.013170 data_rate = 1600
633 11:40:57.016458 CKR = 1
634 11:40:57.019876 DQ_P2S_RATIO = 8
635 11:40:57.023240 ===================================
636 11:40:57.023323 CA_P2S_RATIO = 8
637 11:40:57.026603 DQ_CA_OPEN = 0
638 11:40:57.030140 DQ_SEMI_OPEN = 0
639 11:40:57.033126 CA_SEMI_OPEN = 0
640 11:40:57.036339 CA_FULL_RATE = 0
641 11:40:57.039723 DQ_CKDIV4_EN = 1
642 11:40:57.039808 CA_CKDIV4_EN = 1
643 11:40:57.043188 CA_PREDIV_EN = 0
644 11:40:57.046490 PH8_DLY = 0
645 11:40:57.049585 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 11:40:57.052936 DQ_AAMCK_DIV = 4
647 11:40:57.056596 CA_AAMCK_DIV = 4
648 11:40:57.056679 CA_ADMCK_DIV = 4
649 11:40:57.059757 DQ_TRACK_CA_EN = 0
650 11:40:57.063038 CA_PICK = 800
651 11:40:57.066913 CA_MCKIO = 800
652 11:40:57.069754 MCKIO_SEMI = 0
653 11:40:57.073038 PLL_FREQ = 3068
654 11:40:57.076537 DQ_UI_PI_RATIO = 32
655 11:40:57.076619 CA_UI_PI_RATIO = 0
656 11:40:57.079631 ===================================
657 11:40:57.083334 ===================================
658 11:40:57.086341 memory_type:LPDDR4
659 11:40:57.089965 GP_NUM : 10
660 11:40:57.090048 SRAM_EN : 1
661 11:40:57.093384 MD32_EN : 0
662 11:40:57.096872 ===================================
663 11:40:57.100606 [ANA_INIT] >>>>>>>>>>>>>>
664 11:40:57.100689 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 11:40:57.104341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:40:57.108311 ===================================
667 11:40:57.111483 data_rate = 1600,PCW = 0X7600
668 11:40:57.114871 ===================================
669 11:40:57.118460 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 11:40:57.122045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 11:40:57.129121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 11:40:57.132823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 11:40:57.136346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 11:40:57.139400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 11:40:57.142966 [ANA_INIT] flow start
676 11:40:57.143049 [ANA_INIT] PLL >>>>>>>>
677 11:40:57.146194 [ANA_INIT] PLL <<<<<<<<
678 11:40:57.149519 [ANA_INIT] MIDPI >>>>>>>>
679 11:40:57.152876 [ANA_INIT] MIDPI <<<<<<<<
680 11:40:57.152959 [ANA_INIT] DLL >>>>>>>>
681 11:40:57.156354 [ANA_INIT] flow end
682 11:40:57.159748 ============ LP4 DIFF to SE enter ============
683 11:40:57.163157 ============ LP4 DIFF to SE exit ============
684 11:40:57.166633 [ANA_INIT] <<<<<<<<<<<<<
685 11:40:57.169792 [Flow] Enable top DCM control >>>>>
686 11:40:57.172871 [Flow] Enable top DCM control <<<<<
687 11:40:57.176123 Enable DLL master slave shuffle
688 11:40:57.182733 ==============================================================
689 11:40:57.182817 Gating Mode config
690 11:40:57.189884 ==============================================================
691 11:40:57.189968 Config description:
692 11:40:57.199582 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 11:40:57.206159 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 11:40:57.213110 SELPH_MODE 0: By rank 1: By Phase
695 11:40:57.216083 ==============================================================
696 11:40:57.219720 GAT_TRACK_EN = 1
697 11:40:57.223164 RX_GATING_MODE = 2
698 11:40:57.226752 RX_GATING_TRACK_MODE = 2
699 11:40:57.230105 SELPH_MODE = 1
700 11:40:57.233763 PICG_EARLY_EN = 1
701 11:40:57.233873 VALID_LAT_VALUE = 1
702 11:40:57.240933 ==============================================================
703 11:40:57.244467 Enter into Gating configuration >>>>
704 11:40:57.247538 Exit from Gating configuration <<<<
705 11:40:57.251263 Enter into DVFS_PRE_config >>>>>
706 11:40:57.261936 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 11:40:57.265926 Exit from DVFS_PRE_config <<<<<
708 11:40:57.269366 Enter into PICG configuration >>>>
709 11:40:57.269450 Exit from PICG configuration <<<<
710 11:40:57.272853 [RX_INPUT] configuration >>>>>
711 11:40:57.276645 [RX_INPUT] configuration <<<<<
712 11:40:57.280407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 11:40:57.287414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 11:40:57.294897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 11:40:57.298431 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 11:40:57.305937 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 11:40:57.313450 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 11:40:57.316920 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 11:40:57.320651 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 11:40:57.324178 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 11:40:57.327981 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 11:40:57.331584 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 11:40:57.335175 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 11:40:57.338810 ===================================
725 11:40:57.342748 LPDDR4 DRAM CONFIGURATION
726 11:40:57.346284 ===================================
727 11:40:57.346367 EX_ROW_EN[0] = 0x0
728 11:40:57.349829 EX_ROW_EN[1] = 0x0
729 11:40:57.349912 LP4Y_EN = 0x0
730 11:40:57.353485 WORK_FSP = 0x0
731 11:40:57.353572 WL = 0x2
732 11:40:57.357113 RL = 0x2
733 11:40:57.357196 BL = 0x2
734 11:40:57.361005 RPST = 0x0
735 11:40:57.361105 RD_PRE = 0x0
736 11:40:57.364671 WR_PRE = 0x1
737 11:40:57.364753 WR_PST = 0x0
738 11:40:57.368382 DBI_WR = 0x0
739 11:40:57.368465 DBI_RD = 0x0
740 11:40:57.371708 OTF = 0x1
741 11:40:57.375425 ===================================
742 11:40:57.379034 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 11:40:57.382711 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 11:40:57.386617 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 11:40:57.389871 ===================================
746 11:40:57.393560 LPDDR4 DRAM CONFIGURATION
747 11:40:57.393643 ===================================
748 11:40:57.397317 EX_ROW_EN[0] = 0x10
749 11:40:57.401134 EX_ROW_EN[1] = 0x0
750 11:40:57.401217 LP4Y_EN = 0x0
751 11:40:57.401283 WORK_FSP = 0x0
752 11:40:57.405100 WL = 0x2
753 11:40:57.405182 RL = 0x2
754 11:40:57.409103 BL = 0x2
755 11:40:57.409186 RPST = 0x0
756 11:40:57.412458 RD_PRE = 0x0
757 11:40:57.412540 WR_PRE = 0x1
758 11:40:57.416662 WR_PST = 0x0
759 11:40:57.416752 DBI_WR = 0x0
760 11:40:57.416847 DBI_RD = 0x0
761 11:40:57.420489 OTF = 0x1
762 11:40:57.424083 ===================================
763 11:40:57.427755 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 11:40:57.433509 nWR fixed to 40
765 11:40:57.433593 [ModeRegInit_LP4] CH0 RK0
766 11:40:57.437508 [ModeRegInit_LP4] CH0 RK1
767 11:40:57.441016 [ModeRegInit_LP4] CH1 RK0
768 11:40:57.441114 [ModeRegInit_LP4] CH1 RK1
769 11:40:57.444912 match AC timing 13
770 11:40:57.448170 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 11:40:57.452014 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 11:40:57.455884 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 11:40:57.463170 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 11:40:57.466822 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 11:40:57.466904 [EMI DOE] emi_dcm 0
776 11:40:57.474445 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 11:40:57.474528 ==
778 11:40:57.474593 Dram Type= 6, Freq= 0, CH_0, rank 0
779 11:40:57.482201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:40:57.482285 ==
781 11:40:57.485533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 11:40:57.492646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 11:40:57.501005 [CA 0] Center 38 (7~69) winsize 63
784 11:40:57.504239 [CA 1] Center 38 (7~69) winsize 63
785 11:40:57.507960 [CA 2] Center 35 (5~66) winsize 62
786 11:40:57.511514 [CA 3] Center 35 (4~66) winsize 63
787 11:40:57.515234 [CA 4] Center 34 (4~65) winsize 62
788 11:40:57.518492 [CA 5] Center 33 (3~64) winsize 62
789 11:40:57.518575
790 11:40:57.521946 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 11:40:57.522071
792 11:40:57.525020 [CATrainingPosCal] consider 1 rank data
793 11:40:57.528629 u2DelayCellTimex100 = 270/100 ps
794 11:40:57.532221 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 11:40:57.535550 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 11:40:57.538284 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 11:40:57.541591 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
798 11:40:57.544854 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 11:40:57.551552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 11:40:57.551635
801 11:40:57.554910 CA PerBit enable=1, Macro0, CA PI delay=33
802 11:40:57.554994
803 11:40:57.558157 [CBTSetCACLKResult] CA Dly = 33
804 11:40:57.558240 CS Dly: 6 (0~37)
805 11:40:57.558305 ==
806 11:40:57.561765 Dram Type= 6, Freq= 0, CH_0, rank 1
807 11:40:57.565121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 11:40:57.568182 ==
809 11:40:57.571395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 11:40:57.578104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 11:40:57.586969 [CA 0] Center 38 (7~69) winsize 63
812 11:40:57.590756 [CA 1] Center 38 (8~69) winsize 62
813 11:40:57.593829 [CA 2] Center 36 (6~67) winsize 62
814 11:40:57.597093 [CA 3] Center 36 (6~66) winsize 61
815 11:40:57.600276 [CA 4] Center 35 (4~66) winsize 63
816 11:40:57.603523 [CA 5] Center 34 (4~65) winsize 62
817 11:40:57.603608
818 11:40:57.607134 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 11:40:57.607218
820 11:40:57.610575 [CATrainingPosCal] consider 2 rank data
821 11:40:57.613676 u2DelayCellTimex100 = 270/100 ps
822 11:40:57.616887 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 11:40:57.623488 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
824 11:40:57.627029 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 11:40:57.630209 CA3 delay=36 (6~66),Diff = 2 PI (14 cell)
826 11:40:57.633319 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 11:40:57.636779 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 11:40:57.636863
829 11:40:57.640075 CA PerBit enable=1, Macro0, CA PI delay=34
830 11:40:57.640160
831 11:40:57.643554 [CBTSetCACLKResult] CA Dly = 34
832 11:40:57.646833 CS Dly: 6 (0~38)
833 11:40:57.646917
834 11:40:57.650163 ----->DramcWriteLeveling(PI) begin...
835 11:40:57.650249 ==
836 11:40:57.653344 Dram Type= 6, Freq= 0, CH_0, rank 0
837 11:40:57.656885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 11:40:57.657033 ==
839 11:40:57.660078 Write leveling (Byte 0): 34 => 34
840 11:40:57.664006 Write leveling (Byte 1): 29 => 29
841 11:40:57.666837 DramcWriteLeveling(PI) end<-----
842 11:40:57.666921
843 11:40:57.666987 ==
844 11:40:57.670215 Dram Type= 6, Freq= 0, CH_0, rank 0
845 11:40:57.673577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 11:40:57.673661 ==
847 11:40:57.677114 [Gating] SW mode calibration
848 11:40:57.684068 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 11:40:57.687592 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 11:40:57.694931 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 11:40:57.698496 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 11:40:57.702271 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:40:57.704934 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:40:57.712258 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:40:57.715765 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:40:57.719263 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:40:57.722491 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:40:57.728899 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:40:57.732675 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:40:57.735647 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:40:57.742494 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:40:57.745633 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:40:57.749452 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:40:57.755936 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:40:57.758838 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:40:57.762570 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 11:40:57.769363 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
868 11:40:57.772365 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
869 11:40:57.775413 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:40:57.782157 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:40:57.785945 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:40:57.788912 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:40:57.795495 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:40:57.799111 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:40:57.802175 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:40:57.809032 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 11:40:57.811916 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
878 11:40:57.815570 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:40:57.822045 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:40:57.825190 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:40:57.828869 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:40:57.835273 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:40:57.838767 0 10 4 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
884 11:40:57.841876 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
885 11:40:57.845609 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
886 11:40:57.852073 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:40:57.855267 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:40:57.859149 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 11:40:57.865454 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:40:57.868687 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
891 11:40:57.871941 0 11 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
892 11:40:57.878962 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
893 11:40:57.881847 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
894 11:40:57.885384 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:40:57.891814 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:40:57.895329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 11:40:57.898468 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:40:57.905093 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
899 11:40:57.908627 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 11:40:57.912013 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:40:57.918527 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:40:57.922305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:40:57.925150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:40:57.931856 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:40:57.934957 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:40:57.938590 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:40:57.944850 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:40:57.948490 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:40:57.951730 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:40:57.958358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:40:57.961690 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:40:57.965894 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:40:57.971742 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:40:57.974960 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:40:57.978275 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 11:40:57.981596 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 11:40:57.984974 Total UI for P1: 0, mck2ui 16
918 11:40:57.988365 best dqsien dly found for B0: ( 0, 14, 4)
919 11:40:57.995021 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 11:40:57.998433 Total UI for P1: 0, mck2ui 16
921 11:40:58.001363 best dqsien dly found for B1: ( 0, 14, 8)
922 11:40:58.004677 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 11:40:58.008297 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 11:40:58.008379
925 11:40:58.011465 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 11:40:58.014798 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 11:40:58.018222 [Gating] SW calibration Done
928 11:40:58.018303 ==
929 11:40:58.021702 Dram Type= 6, Freq= 0, CH_0, rank 0
930 11:40:58.024773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 11:40:58.024855 ==
932 11:40:58.028173 RX Vref Scan: 0
933 11:40:58.028254
934 11:40:58.028318 RX Vref 0 -> 0, step: 1
935 11:40:58.028378
936 11:40:58.031323 RX Delay -130 -> 252, step: 16
937 11:40:58.038040 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
938 11:40:58.041593 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 11:40:58.044638 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 11:40:58.047930 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 11:40:58.051407 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 11:40:58.057992 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 11:40:58.061138 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 11:40:58.064403 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 11:40:58.067875 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 11:40:58.071229 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 11:40:58.077762 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 11:40:58.081335 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 11:40:58.084344 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 11:40:58.088151 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 11:40:58.090925 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 11:40:58.097722 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 11:40:58.097805 ==
954 11:40:58.101560 Dram Type= 6, Freq= 0, CH_0, rank 0
955 11:40:58.104448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 11:40:58.104531 ==
957 11:40:58.104596 DQS Delay:
958 11:40:58.107724 DQS0 = 0, DQS1 = 0
959 11:40:58.107805 DQM Delay:
960 11:40:58.110734 DQM0 = 90, DQM1 = 80
961 11:40:58.110816 DQ Delay:
962 11:40:58.114249 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
963 11:40:58.118453 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
964 11:40:58.121198 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 11:40:58.124243 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 11:40:58.124325
967 11:40:58.124389
968 11:40:58.124449 ==
969 11:40:58.127629 Dram Type= 6, Freq= 0, CH_0, rank 0
970 11:40:58.130880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 11:40:58.134681 ==
972 11:40:58.134763
973 11:40:58.134827
974 11:40:58.134886 TX Vref Scan disable
975 11:40:58.137464 == TX Byte 0 ==
976 11:40:58.140769 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
977 11:40:58.144008 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
978 11:40:58.147334 == TX Byte 1 ==
979 11:40:58.150781 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 11:40:58.154145 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 11:40:58.157337 ==
982 11:40:58.160773 Dram Type= 6, Freq= 0, CH_0, rank 0
983 11:40:58.163927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 11:40:58.164010 ==
985 11:40:58.176873 TX Vref=22, minBit 8, minWin=26, winSum=438
986 11:40:58.180175 TX Vref=24, minBit 11, minWin=26, winSum=442
987 11:40:58.183590 TX Vref=26, minBit 8, minWin=27, winSum=447
988 11:40:58.186969 TX Vref=28, minBit 8, minWin=27, winSum=453
989 11:40:58.190038 TX Vref=30, minBit 8, minWin=28, winSum=458
990 11:40:58.196726 TX Vref=32, minBit 3, minWin=28, winSum=455
991 11:40:58.200389 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
992 11:40:58.200472
993 11:40:58.203494 Final TX Range 1 Vref 30
994 11:40:58.203577
995 11:40:58.203640 ==
996 11:40:58.207008 Dram Type= 6, Freq= 0, CH_0, rank 0
997 11:40:58.210600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 11:40:58.210683 ==
999 11:40:58.210748
1000 11:40:58.213481
1001 11:40:58.213562 TX Vref Scan disable
1002 11:40:58.216852 == TX Byte 0 ==
1003 11:40:58.220194 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1004 11:40:58.227110 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1005 11:40:58.227195 == TX Byte 1 ==
1006 11:40:58.230520 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1007 11:40:58.236847 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1008 11:40:58.236955
1009 11:40:58.237065 [DATLAT]
1010 11:40:58.237126 Freq=800, CH0 RK0
1011 11:40:58.237186
1012 11:40:58.240195 DATLAT Default: 0xa
1013 11:40:58.240278 0, 0xFFFF, sum = 0
1014 11:40:58.243353 1, 0xFFFF, sum = 0
1015 11:40:58.243437 2, 0xFFFF, sum = 0
1016 11:40:58.247055 3, 0xFFFF, sum = 0
1017 11:40:58.249980 4, 0xFFFF, sum = 0
1018 11:40:58.250063 5, 0xFFFF, sum = 0
1019 11:40:58.253470 6, 0xFFFF, sum = 0
1020 11:40:58.253553 7, 0xFFFF, sum = 0
1021 11:40:58.256740 8, 0xFFFF, sum = 0
1022 11:40:58.256823 9, 0x0, sum = 1
1023 11:40:58.260230 10, 0x0, sum = 2
1024 11:40:58.260314 11, 0x0, sum = 3
1025 11:40:58.260387 12, 0x0, sum = 4
1026 11:40:58.263186 best_step = 10
1027 11:40:58.263267
1028 11:40:58.263330 ==
1029 11:40:58.266447 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 11:40:58.269812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 11:40:58.269893 ==
1032 11:40:58.273270 RX Vref Scan: 1
1033 11:40:58.273350
1034 11:40:58.276616 Set Vref Range= 32 -> 127
1035 11:40:58.276697
1036 11:40:58.276761 RX Vref 32 -> 127, step: 1
1037 11:40:58.276820
1038 11:40:58.279742 RX Delay -95 -> 252, step: 8
1039 11:40:58.279823
1040 11:40:58.283406 Set Vref, RX VrefLevel [Byte0]: 32
1041 11:40:58.286592 [Byte1]: 32
1042 11:40:58.286673
1043 11:40:58.289781 Set Vref, RX VrefLevel [Byte0]: 33
1044 11:40:58.293458 [Byte1]: 33
1045 11:40:58.297195
1046 11:40:58.297276 Set Vref, RX VrefLevel [Byte0]: 34
1047 11:40:58.300445 [Byte1]: 34
1048 11:40:58.304753
1049 11:40:58.304834 Set Vref, RX VrefLevel [Byte0]: 35
1050 11:40:58.307988 [Byte1]: 35
1051 11:40:58.312400
1052 11:40:58.312480 Set Vref, RX VrefLevel [Byte0]: 36
1053 11:40:58.315929 [Byte1]: 36
1054 11:40:58.320054
1055 11:40:58.320135 Set Vref, RX VrefLevel [Byte0]: 37
1056 11:40:58.323519 [Byte1]: 37
1057 11:40:58.328237
1058 11:40:58.328318 Set Vref, RX VrefLevel [Byte0]: 38
1059 11:40:58.331643 [Byte1]: 38
1060 11:40:58.335295
1061 11:40:58.335375 Set Vref, RX VrefLevel [Byte0]: 39
1062 11:40:58.338566 [Byte1]: 39
1063 11:40:58.342826
1064 11:40:58.342906 Set Vref, RX VrefLevel [Byte0]: 40
1065 11:40:58.346279 [Byte1]: 40
1066 11:40:58.351175
1067 11:40:58.351256 Set Vref, RX VrefLevel [Byte0]: 41
1068 11:40:58.354173 [Byte1]: 41
1069 11:40:58.358212
1070 11:40:58.358293 Set Vref, RX VrefLevel [Byte0]: 42
1071 11:40:58.361577 [Byte1]: 42
1072 11:40:58.365971
1073 11:40:58.366052 Set Vref, RX VrefLevel [Byte0]: 43
1074 11:40:58.369519 [Byte1]: 43
1075 11:40:58.374011
1076 11:40:58.374091 Set Vref, RX VrefLevel [Byte0]: 44
1077 11:40:58.376852 [Byte1]: 44
1078 11:40:58.381416
1079 11:40:58.381496 Set Vref, RX VrefLevel [Byte0]: 45
1080 11:40:58.384575 [Byte1]: 45
1081 11:40:58.388345
1082 11:40:58.388426 Set Vref, RX VrefLevel [Byte0]: 46
1083 11:40:58.391781 [Byte1]: 46
1084 11:40:58.396004
1085 11:40:58.399412 Set Vref, RX VrefLevel [Byte0]: 47
1086 11:40:58.399493 [Byte1]: 47
1087 11:40:58.403932
1088 11:40:58.404012 Set Vref, RX VrefLevel [Byte0]: 48
1089 11:40:58.407044 [Byte1]: 48
1090 11:40:58.411162
1091 11:40:58.411243 Set Vref, RX VrefLevel [Byte0]: 49
1092 11:40:58.414502 [Byte1]: 49
1093 11:40:58.418653
1094 11:40:58.418734 Set Vref, RX VrefLevel [Byte0]: 50
1095 11:40:58.422096 [Byte1]: 50
1096 11:40:58.426275
1097 11:40:58.426355 Set Vref, RX VrefLevel [Byte0]: 51
1098 11:40:58.429942 [Byte1]: 51
1099 11:40:58.433930
1100 11:40:58.434010 Set Vref, RX VrefLevel [Byte0]: 52
1101 11:40:58.437792 [Byte1]: 52
1102 11:40:58.441672
1103 11:40:58.441753 Set Vref, RX VrefLevel [Byte0]: 53
1104 11:40:58.444968 [Byte1]: 53
1105 11:40:58.449342
1106 11:40:58.449423 Set Vref, RX VrefLevel [Byte0]: 54
1107 11:40:58.452779 [Byte1]: 54
1108 11:40:58.456728
1109 11:40:58.456809 Set Vref, RX VrefLevel [Byte0]: 55
1110 11:40:58.460178 [Byte1]: 55
1111 11:40:58.464338
1112 11:40:58.464419 Set Vref, RX VrefLevel [Byte0]: 56
1113 11:40:58.467690 [Byte1]: 56
1114 11:40:58.471976
1115 11:40:58.472057 Set Vref, RX VrefLevel [Byte0]: 57
1116 11:40:58.475127 [Byte1]: 57
1117 11:40:58.479673
1118 11:40:58.479754 Set Vref, RX VrefLevel [Byte0]: 58
1119 11:40:58.482886 [Byte1]: 58
1120 11:40:58.487201
1121 11:40:58.487280 Set Vref, RX VrefLevel [Byte0]: 59
1122 11:40:58.491005 [Byte1]: 59
1123 11:40:58.494836
1124 11:40:58.494915 Set Vref, RX VrefLevel [Byte0]: 60
1125 11:40:58.498150 [Byte1]: 60
1126 11:40:58.502365
1127 11:40:58.502444 Set Vref, RX VrefLevel [Byte0]: 61
1128 11:40:58.505590 [Byte1]: 61
1129 11:40:58.510106
1130 11:40:58.510185 Set Vref, RX VrefLevel [Byte0]: 62
1131 11:40:58.513120 [Byte1]: 62
1132 11:40:58.517704
1133 11:40:58.517783 Set Vref, RX VrefLevel [Byte0]: 63
1134 11:40:58.520938 [Byte1]: 63
1135 11:40:58.525296
1136 11:40:58.525375 Set Vref, RX VrefLevel [Byte0]: 64
1137 11:40:58.528451 [Byte1]: 64
1138 11:40:58.532672
1139 11:40:58.532751 Set Vref, RX VrefLevel [Byte0]: 65
1140 11:40:58.536108 [Byte1]: 65
1141 11:40:58.540807
1142 11:40:58.540887 Set Vref, RX VrefLevel [Byte0]: 66
1143 11:40:58.543562 [Byte1]: 66
1144 11:40:58.547824
1145 11:40:58.547903 Set Vref, RX VrefLevel [Byte0]: 67
1146 11:40:58.551498 [Byte1]: 67
1147 11:40:58.555425
1148 11:40:58.555521 Set Vref, RX VrefLevel [Byte0]: 68
1149 11:40:58.559004 [Byte1]: 68
1150 11:40:58.563204
1151 11:40:58.563283 Set Vref, RX VrefLevel [Byte0]: 69
1152 11:40:58.566513 [Byte1]: 69
1153 11:40:58.570613
1154 11:40:58.570692 Set Vref, RX VrefLevel [Byte0]: 70
1155 11:40:58.574146 [Byte1]: 70
1156 11:40:58.578448
1157 11:40:58.578527 Set Vref, RX VrefLevel [Byte0]: 71
1158 11:40:58.581918 [Byte1]: 71
1159 11:40:58.585905
1160 11:40:58.585984 Set Vref, RX VrefLevel [Byte0]: 72
1161 11:40:58.589507 [Byte1]: 72
1162 11:40:58.593485
1163 11:40:58.593564 Set Vref, RX VrefLevel [Byte0]: 73
1164 11:40:58.596936 [Byte1]: 73
1165 11:40:58.601035
1166 11:40:58.601114 Set Vref, RX VrefLevel [Byte0]: 74
1167 11:40:58.604693 [Byte1]: 74
1168 11:40:58.608709
1169 11:40:58.608788 Set Vref, RX VrefLevel [Byte0]: 75
1170 11:40:58.612373 [Byte1]: 75
1171 11:40:58.616527
1172 11:40:58.616693 Set Vref, RX VrefLevel [Byte0]: 76
1173 11:40:58.619665 [Byte1]: 76
1174 11:40:58.624086
1175 11:40:58.624219 Set Vref, RX VrefLevel [Byte0]: 77
1176 11:40:58.627440 [Byte1]: 77
1177 11:40:58.631535
1178 11:40:58.634657 Set Vref, RX VrefLevel [Byte0]: 78
1179 11:40:58.637897 [Byte1]: 78
1180 11:40:58.637992
1181 11:40:58.641849 Set Vref, RX VrefLevel [Byte0]: 79
1182 11:40:58.644731 [Byte1]: 79
1183 11:40:58.644811
1184 11:40:58.648020 Final RX Vref Byte 0 = 63 to rank0
1185 11:40:58.651372 Final RX Vref Byte 1 = 53 to rank0
1186 11:40:58.654563 Final RX Vref Byte 0 = 63 to rank1
1187 11:40:58.658378 Final RX Vref Byte 1 = 53 to rank1==
1188 11:40:58.661623 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 11:40:58.664532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 11:40:58.664613 ==
1191 11:40:58.667767 DQS Delay:
1192 11:40:58.667847 DQS0 = 0, DQS1 = 0
1193 11:40:58.667910 DQM Delay:
1194 11:40:58.670930 DQM0 = 93, DQM1 = 81
1195 11:40:58.671010 DQ Delay:
1196 11:40:58.674376 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1197 11:40:58.677705 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1198 11:40:58.681027 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1199 11:40:58.684419 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1200 11:40:58.684499
1201 11:40:58.684562
1202 11:40:58.694497 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 393 ps
1203 11:40:58.697484 CH0 RK0: MR19=606, MR18=3F3A
1204 11:40:58.700806 CH0_RK0: MR19=0x606, MR18=0x3F3A, DQSOSC=393, MR23=63, INC=95, DEC=63
1205 11:40:58.700889
1206 11:40:58.704374 ----->DramcWriteLeveling(PI) begin...
1207 11:40:58.707427 ==
1208 11:40:58.710845 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 11:40:58.714560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 11:40:58.714642 ==
1211 11:40:58.717687 Write leveling (Byte 0): 31 => 31
1212 11:40:58.721193 Write leveling (Byte 1): 31 => 31
1213 11:40:58.724222 DramcWriteLeveling(PI) end<-----
1214 11:40:58.724303
1215 11:40:58.724367 ==
1216 11:40:58.727496 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 11:40:58.730980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 11:40:58.731063 ==
1219 11:40:58.734204 [Gating] SW mode calibration
1220 11:40:58.741117 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 11:40:58.747563 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 11:40:58.791604 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 11:40:58.791876 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1224 11:40:58.791948 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1225 11:40:58.792023 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:40:58.792099 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:40:58.792345 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:40:58.792766 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:40:58.792874 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:40:58.793253 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:40:58.793693 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:40:58.804377 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:40:58.804638 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:40:58.804707 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:40:58.807202 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:40:58.810836 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:40:58.817146 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:40:58.820564 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:40:58.824067 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1240 11:40:58.830501 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1241 11:40:58.833993 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:40:58.837121 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:40:58.843783 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:40:58.847506 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:40:58.850964 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:40:58.857123 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:40:58.860428 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:40:58.863769 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (1 1) (1 1)
1249 11:40:58.870713 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:40:58.873861 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:40:58.877091 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:40:58.880253 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 11:40:58.887427 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 11:40:58.890197 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 11:40:58.893773 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
1256 11:40:58.900126 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
1257 11:40:58.903780 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:40:58.907116 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:40:58.913648 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:40:58.916792 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:40:58.920113 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 11:40:58.926996 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 11:40:58.930417 0 11 4 | B1->B0 | 2626 2f2f | 1 1 | (0 0) (0 0)
1264 11:40:58.933874 0 11 8 | B1->B0 | 3e3e 4545 | 1 0 | (0 0) (0 0)
1265 11:40:58.937702 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:40:58.944584 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:40:58.947729 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:40:58.951151 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:40:58.958244 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 11:40:58.961952 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 11:40:58.965235 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1272 11:40:58.968180 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1273 11:40:58.974864 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:40:58.977984 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:40:58.984926 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:40:58.987932 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:40:58.991524 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:40:58.994923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:40:59.001565 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:40:59.004548 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:40:59.008132 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:40:59.014731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:40:59.017944 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:40:59.021361 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:40:59.027844 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:40:59.031286 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 11:40:59.034514 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 11:40:59.041390 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 11:40:59.044535 Total UI for P1: 0, mck2ui 16
1290 11:40:59.047852 best dqsien dly found for B0: ( 0, 14, 6)
1291 11:40:59.047934 Total UI for P1: 0, mck2ui 16
1292 11:40:59.054573 best dqsien dly found for B1: ( 0, 14, 6)
1293 11:40:59.057968 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1294 11:40:59.061216 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1295 11:40:59.061296
1296 11:40:59.064492 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1297 11:40:59.067854 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1298 11:40:59.071140 [Gating] SW calibration Done
1299 11:40:59.071219 ==
1300 11:40:59.074479 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 11:40:59.077748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 11:40:59.077828 ==
1303 11:40:59.081325 RX Vref Scan: 0
1304 11:40:59.081404
1305 11:40:59.081466 RX Vref 0 -> 0, step: 1
1306 11:40:59.081523
1307 11:40:59.084209 RX Delay -130 -> 252, step: 16
1308 11:40:59.087526 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1309 11:40:59.094508 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1310 11:40:59.097633 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1311 11:40:59.101144 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1312 11:40:59.104285 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1313 11:40:59.107748 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1314 11:40:59.114296 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1315 11:40:59.117658 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1316 11:40:59.120982 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1317 11:40:59.124139 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1318 11:40:59.127406 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1319 11:40:59.134107 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1320 11:40:59.137325 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1321 11:40:59.140531 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1322 11:40:59.144107 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1323 11:40:59.150738 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1324 11:40:59.150818 ==
1325 11:40:59.154021 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 11:40:59.157195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 11:40:59.157276 ==
1328 11:40:59.157339 DQS Delay:
1329 11:40:59.160582 DQS0 = 0, DQS1 = 0
1330 11:40:59.160720 DQM Delay:
1331 11:40:59.163986 DQM0 = 91, DQM1 = 81
1332 11:40:59.164066 DQ Delay:
1333 11:40:59.167044 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1334 11:40:59.170464 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1335 11:40:59.173869 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1336 11:40:59.177141 DQ12 =93, DQ13 =77, DQ14 =93, DQ15 =85
1337 11:40:59.177221
1338 11:40:59.177284
1339 11:40:59.177341 ==
1340 11:40:59.180338 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 11:40:59.183868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 11:40:59.183949 ==
1343 11:40:59.187142
1344 11:40:59.187223
1345 11:40:59.187288 TX Vref Scan disable
1346 11:40:59.190283 == TX Byte 0 ==
1347 11:40:59.193815 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1348 11:40:59.196884 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1349 11:40:59.200541 == TX Byte 1 ==
1350 11:40:59.203765 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1351 11:40:59.206860 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1352 11:40:59.206943 ==
1353 11:40:59.210580 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 11:40:59.216952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 11:40:59.217073 ==
1356 11:40:59.228659 TX Vref=22, minBit 8, minWin=27, winSum=444
1357 11:40:59.232217 TX Vref=24, minBit 8, minWin=27, winSum=451
1358 11:40:59.235648 TX Vref=26, minBit 8, minWin=27, winSum=449
1359 11:40:59.238576 TX Vref=28, minBit 8, minWin=27, winSum=454
1360 11:40:59.242117 TX Vref=30, minBit 6, minWin=28, winSum=457
1361 11:40:59.245587 TX Vref=32, minBit 8, minWin=27, winSum=456
1362 11:40:59.252225 [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 30
1363 11:40:59.252308
1364 11:40:59.255331 Final TX Range 1 Vref 30
1365 11:40:59.255412
1366 11:40:59.255476 ==
1367 11:40:59.258654 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 11:40:59.262102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 11:40:59.262183 ==
1370 11:40:59.262247
1371 11:40:59.265321
1372 11:40:59.265401 TX Vref Scan disable
1373 11:40:59.268865 == TX Byte 0 ==
1374 11:40:59.271924 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1375 11:40:59.275268 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1376 11:40:59.278506 == TX Byte 1 ==
1377 11:40:59.281903 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1378 11:40:59.285413 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1379 11:40:59.289135
1380 11:40:59.289215 [DATLAT]
1381 11:40:59.289277 Freq=800, CH0 RK1
1382 11:40:59.289336
1383 11:40:59.292010 DATLAT Default: 0xa
1384 11:40:59.292089 0, 0xFFFF, sum = 0
1385 11:40:59.295276 1, 0xFFFF, sum = 0
1386 11:40:59.295361 2, 0xFFFF, sum = 0
1387 11:40:59.298931 3, 0xFFFF, sum = 0
1388 11:40:59.299013 4, 0xFFFF, sum = 0
1389 11:40:59.301998 5, 0xFFFF, sum = 0
1390 11:40:59.305221 6, 0xFFFF, sum = 0
1391 11:40:59.305302 7, 0xFFFF, sum = 0
1392 11:40:59.308866 8, 0xFFFF, sum = 0
1393 11:40:59.308974 9, 0x0, sum = 1
1394 11:40:59.309080 10, 0x0, sum = 2
1395 11:40:59.312262 11, 0x0, sum = 3
1396 11:40:59.312343 12, 0x0, sum = 4
1397 11:40:59.315093 best_step = 10
1398 11:40:59.315173
1399 11:40:59.315235 ==
1400 11:40:59.318483 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 11:40:59.321921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 11:40:59.322002 ==
1403 11:40:59.325342 RX Vref Scan: 0
1404 11:40:59.325425
1405 11:40:59.325488 RX Vref 0 -> 0, step: 1
1406 11:40:59.325546
1407 11:40:59.328550 RX Delay -79 -> 252, step: 8
1408 11:40:59.335147 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1409 11:40:59.338659 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1410 11:40:59.342110 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1411 11:40:59.345446 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1412 11:40:59.348420 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1413 11:40:59.354945 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1414 11:40:59.358563 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1415 11:40:59.361880 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1416 11:40:59.364903 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1417 11:40:59.368730 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1418 11:40:59.375902 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1419 11:40:59.378403 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1420 11:40:59.381638 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1421 11:40:59.384944 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1422 11:40:59.388563 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1423 11:40:59.394972 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1424 11:40:59.395062 ==
1425 11:40:59.398934 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 11:40:59.401676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 11:40:59.401761 ==
1428 11:40:59.401825 DQS Delay:
1429 11:40:59.405458 DQS0 = 0, DQS1 = 0
1430 11:40:59.405540 DQM Delay:
1431 11:40:59.408381 DQM0 = 91, DQM1 = 82
1432 11:40:59.408464 DQ Delay:
1433 11:40:59.411757 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1434 11:40:59.414858 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1435 11:40:59.418503 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
1436 11:40:59.421630 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1437 11:40:59.421714
1438 11:40:59.421779
1439 11:40:59.431756 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f1a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1440 11:40:59.431850 CH0 RK1: MR19=606, MR18=3F1A
1441 11:40:59.438159 CH0_RK1: MR19=0x606, MR18=0x3F1A, DQSOSC=393, MR23=63, INC=95, DEC=63
1442 11:40:59.441404 [RxdqsGatingPostProcess] freq 800
1443 11:40:59.448316 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 11:40:59.451915 Pre-setting of DQS Precalculation
1445 11:40:59.454631 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 11:40:59.454715 ==
1447 11:40:59.458035 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 11:40:59.464856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 11:40:59.464984 ==
1450 11:40:59.468005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 11:40:59.474669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 11:40:59.483811 [CA 0] Center 36 (6~67) winsize 62
1453 11:40:59.486988 [CA 1] Center 36 (6~67) winsize 62
1454 11:40:59.490691 [CA 2] Center 35 (5~65) winsize 61
1455 11:40:59.493964 [CA 3] Center 34 (3~65) winsize 63
1456 11:40:59.497198 [CA 4] Center 34 (4~65) winsize 62
1457 11:40:59.500365 [CA 5] Center 33 (3~64) winsize 62
1458 11:40:59.500450
1459 11:40:59.503781 [CmdBusTrainingLP45] Vref(ca) range 1: 28
1460 11:40:59.503863
1461 11:40:59.507240 [CATrainingPosCal] consider 1 rank data
1462 11:40:59.510618 u2DelayCellTimex100 = 270/100 ps
1463 11:40:59.513884 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1464 11:40:59.516857 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1465 11:40:59.523576 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1466 11:40:59.527021 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1467 11:40:59.530307 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1468 11:40:59.533638 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1469 11:40:59.533722
1470 11:40:59.536845 CA PerBit enable=1, Macro0, CA PI delay=33
1471 11:40:59.536967
1472 11:40:59.540228 [CBTSetCACLKResult] CA Dly = 33
1473 11:40:59.540309 CS Dly: 5 (0~36)
1474 11:40:59.543706 ==
1475 11:40:59.543787 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 11:40:59.550345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 11:40:59.550431 ==
1478 11:40:59.553601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 11:40:59.560146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 11:40:59.570271 [CA 0] Center 36 (6~67) winsize 62
1481 11:40:59.573421 [CA 1] Center 37 (6~68) winsize 63
1482 11:40:59.576498 [CA 2] Center 35 (5~66) winsize 62
1483 11:40:59.580328 [CA 3] Center 34 (4~65) winsize 62
1484 11:40:59.583216 [CA 4] Center 34 (4~65) winsize 62
1485 11:40:59.586472 [CA 5] Center 34 (4~64) winsize 61
1486 11:40:59.586559
1487 11:40:59.589996 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1488 11:40:59.590079
1489 11:40:59.593790 [CATrainingPosCal] consider 2 rank data
1490 11:40:59.596787 u2DelayCellTimex100 = 270/100 ps
1491 11:40:59.600073 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 11:40:59.604180 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 11:40:59.607459 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1494 11:40:59.610988 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 11:40:59.614451 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 11:40:59.618399 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1497 11:40:59.618546
1498 11:40:59.621840 CA PerBit enable=1, Macro0, CA PI delay=34
1499 11:40:59.621970
1500 11:40:59.625509 [CBTSetCACLKResult] CA Dly = 34
1501 11:40:59.629158 CS Dly: 6 (0~38)
1502 11:40:59.629246
1503 11:40:59.632958 ----->DramcWriteLeveling(PI) begin...
1504 11:40:59.633076 ==
1505 11:40:59.635842 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 11:40:59.639277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 11:40:59.639361 ==
1508 11:40:59.642742 Write leveling (Byte 0): 26 => 26
1509 11:40:59.645936 Write leveling (Byte 1): 26 => 26
1510 11:40:59.649257 DramcWriteLeveling(PI) end<-----
1511 11:40:59.649341
1512 11:40:59.649406 ==
1513 11:40:59.652571 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 11:40:59.655876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 11:40:59.655964 ==
1516 11:40:59.659326 [Gating] SW mode calibration
1517 11:40:59.665789 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 11:40:59.672888 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 11:40:59.675763 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 11:40:59.679063 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1521 11:40:59.686124 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:40:59.689287 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:40:59.692626 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:40:59.699184 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:40:59.702854 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:40:59.705884 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:40:59.712533 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:40:59.715692 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:40:59.719447 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:40:59.725779 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:40:59.729443 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:40:59.732299 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:40:59.735619 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:40:59.742562 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:40:59.745619 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:40:59.748867 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1537 11:40:59.755614 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:40:59.758883 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:40:59.762195 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:40:59.768890 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:40:59.772447 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:40:59.775427 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:40:59.782256 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:40:59.785724 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1545 11:40:59.788723 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1546 11:40:59.795458 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:40:59.798987 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:40:59.802003 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:40:59.809075 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:40:59.812083 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 11:40:59.815920 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1552 11:40:59.822066 0 10 4 | B1->B0 | 2f2f 2929 | 0 0 | (0 1) (0 1)
1553 11:40:59.825436 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:40:59.828922 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:40:59.835351 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:40:59.838448 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:40:59.841975 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:40:59.848472 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:40:59.851763 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 11:40:59.855273 0 11 4 | B1->B0 | 2c2c 3636 | 0 0 | (0 0) (0 0)
1561 11:40:59.861675 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1562 11:40:59.865103 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:40:59.868137 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:40:59.875053 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:40:59.878339 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:40:59.881496 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 11:40:59.888413 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 11:40:59.891456 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1569 11:40:59.894649 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:40:59.901231 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:40:59.904845 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:40:59.907831 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:40:59.914512 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:40:59.918344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:40:59.921292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:40:59.925004 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:40:59.931499 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:40:59.934748 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:40:59.937755 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:40:59.944560 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:40:59.948084 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:40:59.951213 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 11:40:59.957701 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 11:40:59.960965 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1585 11:40:59.964373 Total UI for P1: 0, mck2ui 16
1586 11:40:59.968160 best dqsien dly found for B0: ( 0, 14, 2)
1587 11:40:59.971649 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1588 11:40:59.974648 Total UI for P1: 0, mck2ui 16
1589 11:40:59.977999 best dqsien dly found for B1: ( 0, 14, 4)
1590 11:40:59.980949 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1591 11:40:59.984800 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1592 11:40:59.984886
1593 11:40:59.991149 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1594 11:40:59.994382 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1595 11:40:59.994472 [Gating] SW calibration Done
1596 11:40:59.997960 ==
1597 11:41:00.000946 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 11:41:00.004126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 11:41:00.004213 ==
1600 11:41:00.004279 RX Vref Scan: 0
1601 11:41:00.004340
1602 11:41:00.007630 RX Vref 0 -> 0, step: 1
1603 11:41:00.007713
1604 11:41:00.010907 RX Delay -130 -> 252, step: 16
1605 11:41:00.014156 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1606 11:41:00.017566 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1607 11:41:00.024242 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1608 11:41:00.027645 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1609 11:41:00.030782 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1610 11:41:00.034227 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1611 11:41:00.037613 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1612 11:41:00.040900 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1613 11:41:00.047421 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1614 11:41:00.050924 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1615 11:41:00.054222 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1616 11:41:00.057538 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1617 11:41:00.064298 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1618 11:41:00.067478 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1619 11:41:00.071084 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1620 11:41:00.074170 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1621 11:41:00.074258 ==
1622 11:41:00.077295 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 11:41:00.083919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 11:41:00.084012 ==
1625 11:41:00.084079 DQS Delay:
1626 11:41:00.084140 DQS0 = 0, DQS1 = 0
1627 11:41:00.087582 DQM Delay:
1628 11:41:00.087665 DQM0 = 88, DQM1 = 82
1629 11:41:00.090667 DQ Delay:
1630 11:41:00.093952 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1631 11:41:00.097719 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1632 11:41:00.100745 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1633 11:41:00.104075 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1634 11:41:00.104177
1635 11:41:00.104242
1636 11:41:00.104301 ==
1637 11:41:00.107532 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 11:41:00.110808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 11:41:00.110960 ==
1640 11:41:00.111056
1641 11:41:00.111170
1642 11:41:00.114458 TX Vref Scan disable
1643 11:41:00.114542 == TX Byte 0 ==
1644 11:41:00.120724 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1645 11:41:00.123991 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1646 11:41:00.124097 == TX Byte 1 ==
1647 11:41:00.130791 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1648 11:41:00.134379 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1649 11:41:00.134469 ==
1650 11:41:00.137132 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 11:41:00.140517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 11:41:00.140606 ==
1653 11:41:00.154233 TX Vref=22, minBit 15, minWin=27, winSum=455
1654 11:41:00.157675 TX Vref=24, minBit 15, minWin=27, winSum=457
1655 11:41:00.161134 TX Vref=26, minBit 0, minWin=28, winSum=461
1656 11:41:00.164243 TX Vref=28, minBit 13, minWin=28, winSum=462
1657 11:41:00.167944 TX Vref=30, minBit 10, minWin=28, winSum=462
1658 11:41:00.174196 TX Vref=32, minBit 9, minWin=28, winSum=463
1659 11:41:00.177871 [TxChooseVref] Worse bit 9, Min win 28, Win sum 463, Final Vref 32
1660 11:41:00.177981
1661 11:41:00.181183 Final TX Range 1 Vref 32
1662 11:41:00.181269
1663 11:41:00.181333 ==
1664 11:41:00.184687 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 11:41:00.188095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 11:41:00.188186 ==
1667 11:41:00.188252
1668 11:41:00.191336
1669 11:41:00.191420 TX Vref Scan disable
1670 11:41:00.195065 == TX Byte 0 ==
1671 11:41:00.197960 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1672 11:41:00.201333 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1673 11:41:00.204534 == TX Byte 1 ==
1674 11:41:00.208080 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1675 11:41:00.211182 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1676 11:41:00.215329
1677 11:41:00.215422 [DATLAT]
1678 11:41:00.215490 Freq=800, CH1 RK0
1679 11:41:00.215554
1680 11:41:00.217889 DATLAT Default: 0xa
1681 11:41:00.217975 0, 0xFFFF, sum = 0
1682 11:41:00.221272 1, 0xFFFF, sum = 0
1683 11:41:00.221363 2, 0xFFFF, sum = 0
1684 11:41:00.224688 3, 0xFFFF, sum = 0
1685 11:41:00.224778 4, 0xFFFF, sum = 0
1686 11:41:00.227933 5, 0xFFFF, sum = 0
1687 11:41:00.228019 6, 0xFFFF, sum = 0
1688 11:41:00.231201 7, 0xFFFF, sum = 0
1689 11:41:00.234454 8, 0xFFFF, sum = 0
1690 11:41:00.234546 9, 0x0, sum = 1
1691 11:41:00.234614 10, 0x0, sum = 2
1692 11:41:00.238015 11, 0x0, sum = 3
1693 11:41:00.238105 12, 0x0, sum = 4
1694 11:41:00.241176 best_step = 10
1695 11:41:00.241262
1696 11:41:00.241329 ==
1697 11:41:00.244726 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 11:41:00.247972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 11:41:00.248058 ==
1700 11:41:00.251157 RX Vref Scan: 1
1701 11:41:00.251242
1702 11:41:00.251308 Set Vref Range= 32 -> 127
1703 11:41:00.254568
1704 11:41:00.254651 RX Vref 32 -> 127, step: 1
1705 11:41:00.254717
1706 11:41:00.257658 RX Delay -79 -> 252, step: 8
1707 11:41:00.257742
1708 11:41:00.260956 Set Vref, RX VrefLevel [Byte0]: 32
1709 11:41:00.264301 [Byte1]: 32
1710 11:41:00.264387
1711 11:41:00.267567 Set Vref, RX VrefLevel [Byte0]: 33
1712 11:41:00.270911 [Byte1]: 33
1713 11:41:00.274740
1714 11:41:00.274827 Set Vref, RX VrefLevel [Byte0]: 34
1715 11:41:00.278049 [Byte1]: 34
1716 11:41:00.282946
1717 11:41:00.283035 Set Vref, RX VrefLevel [Byte0]: 35
1718 11:41:00.285606 [Byte1]: 35
1719 11:41:00.289705
1720 11:41:00.289791 Set Vref, RX VrefLevel [Byte0]: 36
1721 11:41:00.293253 [Byte1]: 36
1722 11:41:00.297529
1723 11:41:00.297655 Set Vref, RX VrefLevel [Byte0]: 37
1724 11:41:00.300716 [Byte1]: 37
1725 11:41:00.304775
1726 11:41:00.304861 Set Vref, RX VrefLevel [Byte0]: 38
1727 11:41:00.308324 [Byte1]: 38
1728 11:41:00.312394
1729 11:41:00.312489 Set Vref, RX VrefLevel [Byte0]: 39
1730 11:41:00.315715 [Byte1]: 39
1731 11:41:00.319980
1732 11:41:00.320066 Set Vref, RX VrefLevel [Byte0]: 40
1733 11:41:00.323330 [Byte1]: 40
1734 11:41:00.327348
1735 11:41:00.327436 Set Vref, RX VrefLevel [Byte0]: 41
1736 11:41:00.331087 [Byte1]: 41
1737 11:41:00.335316
1738 11:41:00.335406 Set Vref, RX VrefLevel [Byte0]: 42
1739 11:41:00.338633 [Byte1]: 42
1740 11:41:00.342744
1741 11:41:00.342836 Set Vref, RX VrefLevel [Byte0]: 43
1742 11:41:00.346144 [Byte1]: 43
1743 11:41:00.350794
1744 11:41:00.350885 Set Vref, RX VrefLevel [Byte0]: 44
1745 11:41:00.353519 [Byte1]: 44
1746 11:41:00.357753
1747 11:41:00.357841 Set Vref, RX VrefLevel [Byte0]: 45
1748 11:41:00.361574 [Byte1]: 45
1749 11:41:00.365225
1750 11:41:00.365377 Set Vref, RX VrefLevel [Byte0]: 46
1751 11:41:00.368618 [Byte1]: 46
1752 11:41:00.373092
1753 11:41:00.373179 Set Vref, RX VrefLevel [Byte0]: 47
1754 11:41:00.376012 [Byte1]: 47
1755 11:41:00.380367
1756 11:41:00.380452 Set Vref, RX VrefLevel [Byte0]: 48
1757 11:41:00.383556 [Byte1]: 48
1758 11:41:00.387880
1759 11:41:00.387968 Set Vref, RX VrefLevel [Byte0]: 49
1760 11:41:00.391691 [Byte1]: 49
1761 11:41:00.395401
1762 11:41:00.395488 Set Vref, RX VrefLevel [Byte0]: 50
1763 11:41:00.398660 [Byte1]: 50
1764 11:41:00.403258
1765 11:41:00.403347 Set Vref, RX VrefLevel [Byte0]: 51
1766 11:41:00.406449 [Byte1]: 51
1767 11:41:00.410699
1768 11:41:00.410788 Set Vref, RX VrefLevel [Byte0]: 52
1769 11:41:00.413854 [Byte1]: 52
1770 11:41:00.418502
1771 11:41:00.418593 Set Vref, RX VrefLevel [Byte0]: 53
1772 11:41:00.421565 [Byte1]: 53
1773 11:41:00.425664
1774 11:41:00.425752 Set Vref, RX VrefLevel [Byte0]: 54
1775 11:41:00.428999 [Byte1]: 54
1776 11:41:00.433194
1777 11:41:00.433283 Set Vref, RX VrefLevel [Byte0]: 55
1778 11:41:00.436382 [Byte1]: 55
1779 11:41:00.440713
1780 11:41:00.440804 Set Vref, RX VrefLevel [Byte0]: 56
1781 11:41:00.444397 [Byte1]: 56
1782 11:41:00.448516
1783 11:41:00.448606 Set Vref, RX VrefLevel [Byte0]: 57
1784 11:41:00.451664 [Byte1]: 57
1785 11:41:00.455663
1786 11:41:00.455751 Set Vref, RX VrefLevel [Byte0]: 58
1787 11:41:00.459099 [Byte1]: 58
1788 11:41:00.463317
1789 11:41:00.463409 Set Vref, RX VrefLevel [Byte0]: 59
1790 11:41:00.466755 [Byte1]: 59
1791 11:41:00.471227
1792 11:41:00.471317 Set Vref, RX VrefLevel [Byte0]: 60
1793 11:41:00.474128 [Byte1]: 60
1794 11:41:00.478395
1795 11:41:00.478484 Set Vref, RX VrefLevel [Byte0]: 61
1796 11:41:00.481736 [Byte1]: 61
1797 11:41:00.486033
1798 11:41:00.486120 Set Vref, RX VrefLevel [Byte0]: 62
1799 11:41:00.489191 [Byte1]: 62
1800 11:41:00.493819
1801 11:41:00.493913 Set Vref, RX VrefLevel [Byte0]: 63
1802 11:41:00.496868 [Byte1]: 63
1803 11:41:00.501164
1804 11:41:00.501254 Set Vref, RX VrefLevel [Byte0]: 64
1805 11:41:00.504403 [Byte1]: 64
1806 11:41:00.508961
1807 11:41:00.509073 Set Vref, RX VrefLevel [Byte0]: 65
1808 11:41:00.512003 [Byte1]: 65
1809 11:41:00.516062
1810 11:41:00.516148 Set Vref, RX VrefLevel [Byte0]: 66
1811 11:41:00.519604 [Byte1]: 66
1812 11:41:00.523640
1813 11:41:00.523727 Set Vref, RX VrefLevel [Byte0]: 67
1814 11:41:00.527020 [Byte1]: 67
1815 11:41:00.531141
1816 11:41:00.531244 Set Vref, RX VrefLevel [Byte0]: 68
1817 11:41:00.534643 [Byte1]: 68
1818 11:41:00.538910
1819 11:41:00.538998 Set Vref, RX VrefLevel [Byte0]: 69
1820 11:41:00.542108 [Byte1]: 69
1821 11:41:00.546447
1822 11:41:00.546539 Set Vref, RX VrefLevel [Byte0]: 70
1823 11:41:00.549602 [Byte1]: 70
1824 11:41:00.553928
1825 11:41:00.554021 Set Vref, RX VrefLevel [Byte0]: 71
1826 11:41:00.557173 [Byte1]: 71
1827 11:41:00.561560
1828 11:41:00.561658 Set Vref, RX VrefLevel [Byte0]: 72
1829 11:41:00.564635 [Byte1]: 72
1830 11:41:00.569290
1831 11:41:00.569383 Set Vref, RX VrefLevel [Byte0]: 73
1832 11:41:00.572221 [Byte1]: 73
1833 11:41:00.576640
1834 11:41:00.576730 Set Vref, RX VrefLevel [Byte0]: 74
1835 11:41:00.580570 [Byte1]: 74
1836 11:41:00.584215
1837 11:41:00.584302 Set Vref, RX VrefLevel [Byte0]: 75
1838 11:41:00.587590 [Byte1]: 75
1839 11:41:00.591536
1840 11:41:00.591647 Set Vref, RX VrefLevel [Byte0]: 76
1841 11:41:00.595141 [Byte1]: 76
1842 11:41:00.599229
1843 11:41:00.599324 Set Vref, RX VrefLevel [Byte0]: 77
1844 11:41:00.602498 [Byte1]: 77
1845 11:41:00.606914
1846 11:41:00.607005 Set Vref, RX VrefLevel [Byte0]: 78
1847 11:41:00.610097 [Byte1]: 78
1848 11:41:00.614264
1849 11:41:00.614352 Final RX Vref Byte 0 = 51 to rank0
1850 11:41:00.617799 Final RX Vref Byte 1 = 63 to rank0
1851 11:41:00.620671 Final RX Vref Byte 0 = 51 to rank1
1852 11:41:00.624385 Final RX Vref Byte 1 = 63 to rank1==
1853 11:41:00.627311 Dram Type= 6, Freq= 0, CH_1, rank 0
1854 11:41:00.634286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 11:41:00.634390 ==
1856 11:41:00.634462 DQS Delay:
1857 11:41:00.637454 DQS0 = 0, DQS1 = 0
1858 11:41:00.637541 DQM Delay:
1859 11:41:00.637608 DQM0 = 92, DQM1 = 82
1860 11:41:00.640663 DQ Delay:
1861 11:41:00.643993 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1862 11:41:00.647597 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1863 11:41:00.650737 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1864 11:41:00.654275 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1865 11:41:00.654366
1866 11:41:00.654434
1867 11:41:00.660490 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1868 11:41:00.664137 CH1 RK0: MR19=606, MR18=314E
1869 11:41:00.670651 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1870 11:41:00.670784
1871 11:41:00.673864 ----->DramcWriteLeveling(PI) begin...
1872 11:41:00.673961 ==
1873 11:41:00.677170 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 11:41:00.680594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 11:41:00.680686 ==
1876 11:41:00.683965 Write leveling (Byte 0): 27 => 27
1877 11:41:00.687459 Write leveling (Byte 1): 28 => 28
1878 11:41:00.690815 DramcWriteLeveling(PI) end<-----
1879 11:41:00.690905
1880 11:41:00.690971 ==
1881 11:41:00.693406 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 11:41:00.696837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 11:41:00.700333 ==
1884 11:41:00.700426 [Gating] SW mode calibration
1885 11:41:00.706844 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1886 11:41:00.713806 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1887 11:41:00.717027 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1888 11:41:00.723641 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1889 11:41:00.727035 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1890 11:41:00.729947 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:41:00.736579 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:41:00.740197 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:41:00.743544 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:41:00.749991 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:41:00.753376 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:41:00.756632 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:41:00.763469 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:41:00.766401 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:41:00.769591 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:41:00.776396 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:41:00.779831 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:41:00.783007 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:41:00.789727 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1904 11:41:00.793388 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1905 11:41:00.796432 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:41:00.802828 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:41:00.806290 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:41:00.809399 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:41:00.813177 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:41:00.819424 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:41:00.823209 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:41:00.829688 0 9 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1913 11:41:00.832694 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1914 11:41:00.835763 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 11:41:00.842664 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 11:41:00.845714 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 11:41:00.849048 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 11:41:00.852783 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 11:41:00.859143 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 11:41:00.862508 0 10 4 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (0 1)
1921 11:41:00.866073 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1922 11:41:00.872895 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:41:00.875932 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:41:00.879221 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:41:00.885819 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 11:41:00.888940 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 11:41:00.892056 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 11:41:00.898874 0 11 4 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
1929 11:41:00.901982 0 11 8 | B1->B0 | 4040 4343 | 0 0 | (0 0) (0 0)
1930 11:41:00.905565 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 11:41:00.911892 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 11:41:00.915532 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 11:41:00.918845 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 11:41:00.925296 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 11:41:00.929268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 11:41:00.931877 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 11:41:00.938749 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1938 11:41:00.941816 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:41:00.945525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:41:00.952206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:41:00.955276 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:41:00.958477 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:41:00.964932 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:41:00.968911 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:41:00.971541 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:41:00.978647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:41:00.981491 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:41:00.984898 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:41:00.991337 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:41:00.994767 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:41:00.997962 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 11:41:01.004874 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1953 11:41:01.008041 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1954 11:41:01.011561 Total UI for P1: 0, mck2ui 16
1955 11:41:01.014874 best dqsien dly found for B1: ( 0, 14, 4)
1956 11:41:01.017985 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1957 11:41:01.021322 Total UI for P1: 0, mck2ui 16
1958 11:41:01.024456 best dqsien dly found for B0: ( 0, 14, 8)
1959 11:41:01.028111 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1960 11:41:01.031181 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1961 11:41:01.031267
1962 11:41:01.034554 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1963 11:41:01.041280 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1964 11:41:01.041395 [Gating] SW calibration Done
1965 11:41:01.041462 ==
1966 11:41:01.044510 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 11:41:01.051019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 11:41:01.051115 ==
1969 11:41:01.051181 RX Vref Scan: 0
1970 11:41:01.051241
1971 11:41:01.054284 RX Vref 0 -> 0, step: 1
1972 11:41:01.054366
1973 11:41:01.057662 RX Delay -130 -> 252, step: 16
1974 11:41:01.061539 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1975 11:41:01.064362 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1976 11:41:01.067831 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1977 11:41:01.074207 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1978 11:41:01.078443 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1979 11:41:01.080999 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1980 11:41:01.084228 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1981 11:41:01.087631 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1982 11:41:01.093973 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1983 11:41:01.097481 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1984 11:41:01.100467 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1985 11:41:01.104213 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1986 11:41:01.110593 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1987 11:41:01.113881 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1988 11:41:01.117651 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1989 11:41:01.120275 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1990 11:41:01.120360 ==
1991 11:41:01.123768 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 11:41:01.130159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 11:41:01.130259 ==
1994 11:41:01.130325 DQS Delay:
1995 11:41:01.133423 DQS0 = 0, DQS1 = 0
1996 11:41:01.133509 DQM Delay:
1997 11:41:01.133574 DQM0 = 90, DQM1 = 83
1998 11:41:01.136887 DQ Delay:
1999 11:41:01.140200 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
2000 11:41:01.144000 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
2001 11:41:01.146695 DQ8 =61, DQ9 =69, DQ10 =93, DQ11 =69
2002 11:41:01.149966 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
2003 11:41:01.150053
2004 11:41:01.150118
2005 11:41:01.150179 ==
2006 11:41:01.153414 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 11:41:01.156805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 11:41:01.156893 ==
2009 11:41:01.156958
2010 11:41:01.157078
2011 11:41:01.160376 TX Vref Scan disable
2012 11:41:01.160461 == TX Byte 0 ==
2013 11:41:01.166628 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2014 11:41:01.169941 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2015 11:41:01.170032 == TX Byte 1 ==
2016 11:41:01.176601 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2017 11:41:01.179967 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2018 11:41:01.180057 ==
2019 11:41:01.183340 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 11:41:01.186594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 11:41:01.186683 ==
2022 11:41:01.200316 TX Vref=22, minBit 13, minWin=27, winSum=457
2023 11:41:01.203795 TX Vref=24, minBit 9, minWin=28, winSum=458
2024 11:41:01.207362 TX Vref=26, minBit 13, minWin=27, winSum=456
2025 11:41:01.210816 TX Vref=28, minBit 8, minWin=28, winSum=458
2026 11:41:01.213839 TX Vref=30, minBit 8, minWin=28, winSum=459
2027 11:41:01.220378 TX Vref=32, minBit 9, minWin=27, winSum=457
2028 11:41:01.223966 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
2029 11:41:01.224065
2030 11:41:01.227249 Final TX Range 1 Vref 30
2031 11:41:01.227335
2032 11:41:01.227399 ==
2033 11:41:01.230336 Dram Type= 6, Freq= 0, CH_1, rank 1
2034 11:41:01.234224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2035 11:41:01.237177 ==
2036 11:41:01.237267
2037 11:41:01.237332
2038 11:41:01.237392 TX Vref Scan disable
2039 11:41:01.240583 == TX Byte 0 ==
2040 11:41:01.243769 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2041 11:41:01.250760 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2042 11:41:01.250863 == TX Byte 1 ==
2043 11:41:01.253853 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2044 11:41:01.260418 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2045 11:41:01.260525
2046 11:41:01.260593 [DATLAT]
2047 11:41:01.260654 Freq=800, CH1 RK1
2048 11:41:01.260713
2049 11:41:01.263832 DATLAT Default: 0xa
2050 11:41:01.263915 0, 0xFFFF, sum = 0
2051 11:41:01.267221 1, 0xFFFF, sum = 0
2052 11:41:01.267306 2, 0xFFFF, sum = 0
2053 11:41:01.270929 3, 0xFFFF, sum = 0
2054 11:41:01.273591 4, 0xFFFF, sum = 0
2055 11:41:01.273676 5, 0xFFFF, sum = 0
2056 11:41:01.277207 6, 0xFFFF, sum = 0
2057 11:41:01.277294 7, 0xFFFF, sum = 0
2058 11:41:01.280619 8, 0xFFFF, sum = 0
2059 11:41:01.280704 9, 0x0, sum = 1
2060 11:41:01.284087 10, 0x0, sum = 2
2061 11:41:01.284172 11, 0x0, sum = 3
2062 11:41:01.284279 12, 0x0, sum = 4
2063 11:41:01.286893 best_step = 10
2064 11:41:01.286986
2065 11:41:01.287051 ==
2066 11:41:01.290236 Dram Type= 6, Freq= 0, CH_1, rank 1
2067 11:41:01.293506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2068 11:41:01.293618 ==
2069 11:41:01.296765 RX Vref Scan: 0
2070 11:41:01.296851
2071 11:41:01.296916 RX Vref 0 -> 0, step: 1
2072 11:41:01.300063
2073 11:41:01.300172 RX Delay -95 -> 252, step: 8
2074 11:41:01.307194 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2075 11:41:01.310324 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2076 11:41:01.313890 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2077 11:41:01.316940 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2078 11:41:01.320432 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2079 11:41:01.327162 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2080 11:41:01.330511 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2081 11:41:01.333724 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2082 11:41:01.337132 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2083 11:41:01.340694 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2084 11:41:01.346944 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2085 11:41:01.350477 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2086 11:41:01.353675 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2087 11:41:01.357123 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2088 11:41:01.360486 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2089 11:41:01.366898 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2090 11:41:01.367004 ==
2091 11:41:01.370572 Dram Type= 6, Freq= 0, CH_1, rank 1
2092 11:41:01.373647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2093 11:41:01.373736 ==
2094 11:41:01.373803 DQS Delay:
2095 11:41:01.377418 DQS0 = 0, DQS1 = 0
2096 11:41:01.377505 DQM Delay:
2097 11:41:01.380670 DQM0 = 90, DQM1 = 83
2098 11:41:01.380754 DQ Delay:
2099 11:41:01.383664 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2100 11:41:01.386955 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2101 11:41:01.390258 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2102 11:41:01.393433 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2103 11:41:01.393521
2104 11:41:01.393586
2105 11:41:01.403323 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2106 11:41:01.403440 CH1 RK1: MR19=606, MR18=3B10
2107 11:41:01.409997 CH1_RK1: MR19=0x606, MR18=0x3B10, DQSOSC=394, MR23=63, INC=95, DEC=63
2108 11:41:01.413560 [RxdqsGatingPostProcess] freq 800
2109 11:41:01.420107 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2110 11:41:01.423512 Pre-setting of DQS Precalculation
2111 11:41:01.426662 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2112 11:41:01.433491 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2113 11:41:01.440196 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2114 11:41:01.443504
2115 11:41:01.443606
2116 11:41:01.443672 [Calibration Summary] 1600 Mbps
2117 11:41:01.446954 CH 0, Rank 0
2118 11:41:01.447039 SW Impedance : PASS
2119 11:41:01.449769 DUTY Scan : NO K
2120 11:41:01.453089 ZQ Calibration : PASS
2121 11:41:01.453174 Jitter Meter : NO K
2122 11:41:01.456982 CBT Training : PASS
2123 11:41:01.459987 Write leveling : PASS
2124 11:41:01.460075 RX DQS gating : PASS
2125 11:41:01.463237 RX DQ/DQS(RDDQC) : PASS
2126 11:41:01.466473 TX DQ/DQS : PASS
2127 11:41:01.466559 RX DATLAT : PASS
2128 11:41:01.470101 RX DQ/DQS(Engine): PASS
2129 11:41:01.473441 TX OE : NO K
2130 11:41:01.473526 All Pass.
2131 11:41:01.473592
2132 11:41:01.473653 CH 0, Rank 1
2133 11:41:01.476441 SW Impedance : PASS
2134 11:41:01.479821 DUTY Scan : NO K
2135 11:41:01.479904 ZQ Calibration : PASS
2136 11:41:01.483341 Jitter Meter : NO K
2137 11:41:01.486482 CBT Training : PASS
2138 11:41:01.486565 Write leveling : PASS
2139 11:41:01.489779 RX DQS gating : PASS
2140 11:41:01.492897 RX DQ/DQS(RDDQC) : PASS
2141 11:41:01.493029 TX DQ/DQS : PASS
2142 11:41:01.496693 RX DATLAT : PASS
2143 11:41:01.496777 RX DQ/DQS(Engine): PASS
2144 11:41:01.499619 TX OE : NO K
2145 11:41:01.499701 All Pass.
2146 11:41:01.499766
2147 11:41:01.503096 CH 1, Rank 0
2148 11:41:01.503180 SW Impedance : PASS
2149 11:41:01.506518 DUTY Scan : NO K
2150 11:41:01.509486 ZQ Calibration : PASS
2151 11:41:01.509572 Jitter Meter : NO K
2152 11:41:01.513161 CBT Training : PASS
2153 11:41:01.516288 Write leveling : PASS
2154 11:41:01.516398 RX DQS gating : PASS
2155 11:41:01.519518 RX DQ/DQS(RDDQC) : PASS
2156 11:41:01.522828 TX DQ/DQS : PASS
2157 11:41:01.522916 RX DATLAT : PASS
2158 11:41:01.526334 RX DQ/DQS(Engine): PASS
2159 11:41:01.529629 TX OE : NO K
2160 11:41:01.529719 All Pass.
2161 11:41:01.529784
2162 11:41:01.529842 CH 1, Rank 1
2163 11:41:01.533396 SW Impedance : PASS
2164 11:41:01.536261 DUTY Scan : NO K
2165 11:41:01.536344 ZQ Calibration : PASS
2166 11:41:01.539356 Jitter Meter : NO K
2167 11:41:01.542813 CBT Training : PASS
2168 11:41:01.542900 Write leveling : PASS
2169 11:41:01.546285 RX DQS gating : PASS
2170 11:41:01.546368 RX DQ/DQS(RDDQC) : PASS
2171 11:41:01.549351 TX DQ/DQS : PASS
2172 11:41:01.552643 RX DATLAT : PASS
2173 11:41:01.552726 RX DQ/DQS(Engine): PASS
2174 11:41:01.556239 TX OE : NO K
2175 11:41:01.556323 All Pass.
2176 11:41:01.556388
2177 11:41:01.559542 DramC Write-DBI off
2178 11:41:01.562820 PER_BANK_REFRESH: Hybrid Mode
2179 11:41:01.562907 TX_TRACKING: ON
2180 11:41:01.566122 [GetDramInforAfterCalByMRR] Vendor 6.
2181 11:41:01.569452 [GetDramInforAfterCalByMRR] Revision 606.
2182 11:41:01.572890 [GetDramInforAfterCalByMRR] Revision 2 0.
2183 11:41:01.576602 MR0 0x3b3b
2184 11:41:01.576689 MR8 0x5151
2185 11:41:01.579530 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 11:41:01.579613
2187 11:41:01.582807 MR0 0x3b3b
2188 11:41:01.582890 MR8 0x5151
2189 11:41:01.585891 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2190 11:41:01.585975
2191 11:41:01.596274 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2192 11:41:01.599538 [FAST_K] Save calibration result to emmc
2193 11:41:01.602623 [FAST_K] Save calibration result to emmc
2194 11:41:01.606154 dram_init: config_dvfs: 1
2195 11:41:01.609282 dramc_set_vcore_voltage set vcore to 662500
2196 11:41:01.609401 Read voltage for 1200, 2
2197 11:41:01.612856 Vio18 = 0
2198 11:41:01.612968 Vcore = 662500
2199 11:41:01.613077 Vdram = 0
2200 11:41:01.615717 Vddq = 0
2201 11:41:01.615799 Vmddr = 0
2202 11:41:01.619214 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2203 11:41:01.625888 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2204 11:41:01.629136 MEM_TYPE=3, freq_sel=15
2205 11:41:01.632890 sv_algorithm_assistance_LP4_1600
2206 11:41:01.635901 ============ PULL DRAM RESETB DOWN ============
2207 11:41:01.639134 ========== PULL DRAM RESETB DOWN end =========
2208 11:41:01.645773 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2209 11:41:01.649004 ===================================
2210 11:41:01.649110 LPDDR4 DRAM CONFIGURATION
2211 11:41:01.652361 ===================================
2212 11:41:01.655914 EX_ROW_EN[0] = 0x0
2213 11:41:01.656001 EX_ROW_EN[1] = 0x0
2214 11:41:01.658987 LP4Y_EN = 0x0
2215 11:41:01.662514 WORK_FSP = 0x0
2216 11:41:01.662605 WL = 0x4
2217 11:41:01.665545 RL = 0x4
2218 11:41:01.665630 BL = 0x2
2219 11:41:01.668814 RPST = 0x0
2220 11:41:01.668898 RD_PRE = 0x0
2221 11:41:01.672193 WR_PRE = 0x1
2222 11:41:01.672276 WR_PST = 0x0
2223 11:41:01.675629 DBI_WR = 0x0
2224 11:41:01.675713 DBI_RD = 0x0
2225 11:41:01.678933 OTF = 0x1
2226 11:41:01.682306 ===================================
2227 11:41:01.685292 ===================================
2228 11:41:01.685379 ANA top config
2229 11:41:01.689334 ===================================
2230 11:41:01.692220 DLL_ASYNC_EN = 0
2231 11:41:01.695421 ALL_SLAVE_EN = 0
2232 11:41:01.695506 NEW_RANK_MODE = 1
2233 11:41:01.698821 DLL_IDLE_MODE = 1
2234 11:41:01.702153 LP45_APHY_COMB_EN = 1
2235 11:41:01.705453 TX_ODT_DIS = 1
2236 11:41:01.709203 NEW_8X_MODE = 1
2237 11:41:01.712014 ===================================
2238 11:41:01.715191 ===================================
2239 11:41:01.715306 data_rate = 2400
2240 11:41:01.718698 CKR = 1
2241 11:41:01.722268 DQ_P2S_RATIO = 8
2242 11:41:01.725413 ===================================
2243 11:41:01.728708 CA_P2S_RATIO = 8
2244 11:41:01.732217 DQ_CA_OPEN = 0
2245 11:41:01.735439 DQ_SEMI_OPEN = 0
2246 11:41:01.735527 CA_SEMI_OPEN = 0
2247 11:41:01.739101 CA_FULL_RATE = 0
2248 11:41:01.741787 DQ_CKDIV4_EN = 0
2249 11:41:01.745276 CA_CKDIV4_EN = 0
2250 11:41:01.749172 CA_PREDIV_EN = 0
2251 11:41:01.751957 PH8_DLY = 17
2252 11:41:01.752045 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2253 11:41:01.755186 DQ_AAMCK_DIV = 4
2254 11:41:01.758830 CA_AAMCK_DIV = 4
2255 11:41:01.761872 CA_ADMCK_DIV = 4
2256 11:41:01.765579 DQ_TRACK_CA_EN = 0
2257 11:41:01.768333 CA_PICK = 1200
2258 11:41:01.772045 CA_MCKIO = 1200
2259 11:41:01.772135 MCKIO_SEMI = 0
2260 11:41:01.774982 PLL_FREQ = 2366
2261 11:41:01.778314 DQ_UI_PI_RATIO = 32
2262 11:41:01.781643 CA_UI_PI_RATIO = 0
2263 11:41:01.784973 ===================================
2264 11:41:01.788349 ===================================
2265 11:41:01.791571 memory_type:LPDDR4
2266 11:41:01.791658 GP_NUM : 10
2267 11:41:01.795199 SRAM_EN : 1
2268 11:41:01.798694 MD32_EN : 0
2269 11:41:01.801580 ===================================
2270 11:41:01.801667 [ANA_INIT] >>>>>>>>>>>>>>
2271 11:41:01.805290 <<<<<< [CONFIGURE PHASE]: ANA_TX
2272 11:41:01.808149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2273 11:41:01.811736 ===================================
2274 11:41:01.814922 data_rate = 2400,PCW = 0X5b00
2275 11:41:01.818047 ===================================
2276 11:41:01.821397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2277 11:41:01.828015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2278 11:41:01.831401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2279 11:41:01.838432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2280 11:41:01.841577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2281 11:41:01.844673 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2282 11:41:01.844761 [ANA_INIT] flow start
2283 11:41:01.847968 [ANA_INIT] PLL >>>>>>>>
2284 11:41:01.851605 [ANA_INIT] PLL <<<<<<<<
2285 11:41:01.851694 [ANA_INIT] MIDPI >>>>>>>>
2286 11:41:01.854630 [ANA_INIT] MIDPI <<<<<<<<
2287 11:41:01.857964 [ANA_INIT] DLL >>>>>>>>
2288 11:41:01.861362 [ANA_INIT] DLL <<<<<<<<
2289 11:41:01.861452 [ANA_INIT] flow end
2290 11:41:01.864881 ============ LP4 DIFF to SE enter ============
2291 11:41:01.871331 ============ LP4 DIFF to SE exit ============
2292 11:41:01.871437 [ANA_INIT] <<<<<<<<<<<<<
2293 11:41:01.874967 [Flow] Enable top DCM control >>>>>
2294 11:41:01.877873 [Flow] Enable top DCM control <<<<<
2295 11:41:01.881300 Enable DLL master slave shuffle
2296 11:41:01.887846 ==============================================================
2297 11:41:01.887950 Gating Mode config
2298 11:41:01.894568 ==============================================================
2299 11:41:01.898074 Config description:
2300 11:41:01.904685 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2301 11:41:01.911085 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2302 11:41:01.917897 SELPH_MODE 0: By rank 1: By Phase
2303 11:41:01.924646 ==============================================================
2304 11:41:01.927848 GAT_TRACK_EN = 1
2305 11:41:01.927949 RX_GATING_MODE = 2
2306 11:41:01.930777 RX_GATING_TRACK_MODE = 2
2307 11:41:01.934449 SELPH_MODE = 1
2308 11:41:01.937822 PICG_EARLY_EN = 1
2309 11:41:01.940895 VALID_LAT_VALUE = 1
2310 11:41:01.947440 ==============================================================
2311 11:41:01.951236 Enter into Gating configuration >>>>
2312 11:41:01.954300 Exit from Gating configuration <<<<
2313 11:41:01.957357 Enter into DVFS_PRE_config >>>>>
2314 11:41:01.967810 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2315 11:41:01.970699 Exit from DVFS_PRE_config <<<<<
2316 11:41:01.974287 Enter into PICG configuration >>>>
2317 11:41:01.977455 Exit from PICG configuration <<<<
2318 11:41:01.980655 [RX_INPUT] configuration >>>>>
2319 11:41:01.984114 [RX_INPUT] configuration <<<<<
2320 11:41:01.987282 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2321 11:41:01.994394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2322 11:41:02.000604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 11:41:02.004008 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 11:41:02.010553 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2325 11:41:02.017182 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2326 11:41:02.020654 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2327 11:41:02.023986 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2328 11:41:02.030774 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2329 11:41:02.033907 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2330 11:41:02.037228 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2331 11:41:02.044137 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2332 11:41:02.046970 ===================================
2333 11:41:02.047070 LPDDR4 DRAM CONFIGURATION
2334 11:41:02.050512 ===================================
2335 11:41:02.053638 EX_ROW_EN[0] = 0x0
2336 11:41:02.057374 EX_ROW_EN[1] = 0x0
2337 11:41:02.057464 LP4Y_EN = 0x0
2338 11:41:02.060593 WORK_FSP = 0x0
2339 11:41:02.060682 WL = 0x4
2340 11:41:02.063497 RL = 0x4
2341 11:41:02.063584 BL = 0x2
2342 11:41:02.067154 RPST = 0x0
2343 11:41:02.067241 RD_PRE = 0x0
2344 11:41:02.070356 WR_PRE = 0x1
2345 11:41:02.070441 WR_PST = 0x0
2346 11:41:02.073790 DBI_WR = 0x0
2347 11:41:02.073875 DBI_RD = 0x0
2348 11:41:02.076859 OTF = 0x1
2349 11:41:02.080424 ===================================
2350 11:41:02.083744 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2351 11:41:02.087329 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2352 11:41:02.093630 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2353 11:41:02.096943 ===================================
2354 11:41:02.097096 LPDDR4 DRAM CONFIGURATION
2355 11:41:02.100485 ===================================
2356 11:41:02.103783 EX_ROW_EN[0] = 0x10
2357 11:41:02.103872 EX_ROW_EN[1] = 0x0
2358 11:41:02.106980 LP4Y_EN = 0x0
2359 11:41:02.107065 WORK_FSP = 0x0
2360 11:41:02.110176 WL = 0x4
2361 11:41:02.110260 RL = 0x4
2362 11:41:02.114097 BL = 0x2
2363 11:41:02.116950 RPST = 0x0
2364 11:41:02.117096 RD_PRE = 0x0
2365 11:41:02.120448 WR_PRE = 0x1
2366 11:41:02.120529 WR_PST = 0x0
2367 11:41:02.123647 DBI_WR = 0x0
2368 11:41:02.123728 DBI_RD = 0x0
2369 11:41:02.126850 OTF = 0x1
2370 11:41:02.130243 ===================================
2371 11:41:02.133777 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2372 11:41:02.136706 ==
2373 11:41:02.140136 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 11:41:02.143621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 11:41:02.143708 ==
2376 11:41:02.146783 [Duty_Offset_Calibration]
2377 11:41:02.146865 B0:2 B1:0 CA:1
2378 11:41:02.146928
2379 11:41:02.150392 [DutyScan_Calibration_Flow] k_type=0
2380 11:41:02.158926
2381 11:41:02.159033 ==CLK 0==
2382 11:41:02.162296 Final CLK duty delay cell = -4
2383 11:41:02.166100 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2384 11:41:02.169196 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2385 11:41:02.172565 [-4] AVG Duty = 4953%(X100)
2386 11:41:02.172651
2387 11:41:02.175755 CH0 CLK Duty spec in!! Max-Min= 156%
2388 11:41:02.179144 [DutyScan_Calibration_Flow] ====Done====
2389 11:41:02.179229
2390 11:41:02.182608 [DutyScan_Calibration_Flow] k_type=1
2391 11:41:02.197917
2392 11:41:02.198050 ==DQS 0 ==
2393 11:41:02.201048 Final DQS duty delay cell = 0
2394 11:41:02.204424 [0] MAX Duty = 5187%(X100), DQS PI = 32
2395 11:41:02.207845 [0] MIN Duty = 4938%(X100), DQS PI = 0
2396 11:41:02.207935 [0] AVG Duty = 5062%(X100)
2397 11:41:02.211135
2398 11:41:02.211219 ==DQS 1 ==
2399 11:41:02.214343 Final DQS duty delay cell = -4
2400 11:41:02.218182 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2401 11:41:02.221111 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2402 11:41:02.224250 [-4] AVG Duty = 5031%(X100)
2403 11:41:02.224337
2404 11:41:02.227681 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2405 11:41:02.227764
2406 11:41:02.231047 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2407 11:41:02.234208 [DutyScan_Calibration_Flow] ====Done====
2408 11:41:02.234293
2409 11:41:02.237583 [DutyScan_Calibration_Flow] k_type=3
2410 11:41:02.254617
2411 11:41:02.254769 ==DQM 0 ==
2412 11:41:02.257896 Final DQM duty delay cell = 0
2413 11:41:02.261138 [0] MAX Duty = 5062%(X100), DQS PI = 24
2414 11:41:02.264437 [0] MIN Duty = 4844%(X100), DQS PI = 2
2415 11:41:02.264529 [0] AVG Duty = 4953%(X100)
2416 11:41:02.268218
2417 11:41:02.268303 ==DQM 1 ==
2418 11:41:02.271648 Final DQM duty delay cell = 0
2419 11:41:02.274848 [0] MAX Duty = 5218%(X100), DQS PI = 50
2420 11:41:02.277930 [0] MIN Duty = 5000%(X100), DQS PI = 22
2421 11:41:02.278020 [0] AVG Duty = 5109%(X100)
2422 11:41:02.281410
2423 11:41:02.284803 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2424 11:41:02.284889
2425 11:41:02.287986 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2426 11:41:02.291160 [DutyScan_Calibration_Flow] ====Done====
2427 11:41:02.291248
2428 11:41:02.294662 [DutyScan_Calibration_Flow] k_type=2
2429 11:41:02.311129
2430 11:41:02.311278 ==DQ 0 ==
2431 11:41:02.314323 Final DQ duty delay cell = -4
2432 11:41:02.317581 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2433 11:41:02.320916 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2434 11:41:02.324553 [-4] AVG Duty = 4953%(X100)
2435 11:41:02.324641
2436 11:41:02.324706 ==DQ 1 ==
2437 11:41:02.327711 Final DQ duty delay cell = 4
2438 11:41:02.330864 [4] MAX Duty = 5093%(X100), DQS PI = 4
2439 11:41:02.334386 [4] MIN Duty = 5031%(X100), DQS PI = 16
2440 11:41:02.337640 [4] AVG Duty = 5062%(X100)
2441 11:41:02.337740
2442 11:41:02.340866 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2443 11:41:02.340951
2444 11:41:02.343959 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2445 11:41:02.347464 [DutyScan_Calibration_Flow] ====Done====
2446 11:41:02.347549 ==
2447 11:41:02.350904 Dram Type= 6, Freq= 0, CH_1, rank 0
2448 11:41:02.353966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 11:41:02.354053 ==
2450 11:41:02.357779 [Duty_Offset_Calibration]
2451 11:41:02.357880 B0:0 B1:-1 CA:2
2452 11:41:02.357959
2453 11:41:02.360952 [DutyScan_Calibration_Flow] k_type=0
2454 11:41:02.371337
2455 11:41:02.371465 ==CLK 0==
2456 11:41:02.375045 Final CLK duty delay cell = 0
2457 11:41:02.378131 [0] MAX Duty = 5156%(X100), DQS PI = 16
2458 11:41:02.381460 [0] MIN Duty = 4938%(X100), DQS PI = 46
2459 11:41:02.381554 [0] AVG Duty = 5047%(X100)
2460 11:41:02.384762
2461 11:41:02.388133 CH1 CLK Duty spec in!! Max-Min= 218%
2462 11:41:02.391275 [DutyScan_Calibration_Flow] ====Done====
2463 11:41:02.391364
2464 11:41:02.394730 [DutyScan_Calibration_Flow] k_type=1
2465 11:41:02.411063
2466 11:41:02.411211 ==DQS 0 ==
2467 11:41:02.414149 Final DQS duty delay cell = 0
2468 11:41:02.417328 [0] MAX Duty = 5093%(X100), DQS PI = 24
2469 11:41:02.420530 [0] MIN Duty = 4969%(X100), DQS PI = 48
2470 11:41:02.424122 [0] AVG Duty = 5031%(X100)
2471 11:41:02.424211
2472 11:41:02.424278 ==DQS 1 ==
2473 11:41:02.427394 Final DQS duty delay cell = 0
2474 11:41:02.430564 [0] MAX Duty = 5156%(X100), DQS PI = 0
2475 11:41:02.434099 [0] MIN Duty = 4844%(X100), DQS PI = 36
2476 11:41:02.434187 [0] AVG Duty = 5000%(X100)
2477 11:41:02.437602
2478 11:41:02.440794 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2479 11:41:02.440880
2480 11:41:02.443971 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2481 11:41:02.447367 [DutyScan_Calibration_Flow] ====Done====
2482 11:41:02.447457
2483 11:41:02.450551 [DutyScan_Calibration_Flow] k_type=3
2484 11:41:02.467423
2485 11:41:02.467572 ==DQM 0 ==
2486 11:41:02.470568 Final DQM duty delay cell = 4
2487 11:41:02.474059 [4] MAX Duty = 5093%(X100), DQS PI = 6
2488 11:41:02.477241 [4] MIN Duty = 4969%(X100), DQS PI = 28
2489 11:41:02.477329 [4] AVG Duty = 5031%(X100)
2490 11:41:02.480771
2491 11:41:02.480857 ==DQM 1 ==
2492 11:41:02.484156 Final DQM duty delay cell = -4
2493 11:41:02.487359 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2494 11:41:02.490540 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2495 11:41:02.493890 [-4] AVG Duty = 4875%(X100)
2496 11:41:02.493980
2497 11:41:02.497328 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2498 11:41:02.497414
2499 11:41:02.500444 CH1 DQM 1 Duty spec in!! Max-Min= 311%
2500 11:41:02.503773 [DutyScan_Calibration_Flow] ====Done====
2501 11:41:02.503861
2502 11:41:02.507534 [DutyScan_Calibration_Flow] k_type=2
2503 11:41:02.524628
2504 11:41:02.524780 ==DQ 0 ==
2505 11:41:02.527337 Final DQ duty delay cell = 0
2506 11:41:02.530746 [0] MAX Duty = 5062%(X100), DQS PI = 20
2507 11:41:02.534837 [0] MIN Duty = 4938%(X100), DQS PI = 44
2508 11:41:02.534927 [0] AVG Duty = 5000%(X100)
2509 11:41:02.537445
2510 11:41:02.537529 ==DQ 1 ==
2511 11:41:02.540685 Final DQ duty delay cell = 0
2512 11:41:02.544120 [0] MAX Duty = 5031%(X100), DQS PI = 2
2513 11:41:02.547030 [0] MIN Duty = 4813%(X100), DQS PI = 36
2514 11:41:02.547118 [0] AVG Duty = 4922%(X100)
2515 11:41:02.550332
2516 11:41:02.553809 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2517 11:41:02.553896
2518 11:41:02.556959 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2519 11:41:02.560595 [DutyScan_Calibration_Flow] ====Done====
2520 11:41:02.563679 nWR fixed to 30
2521 11:41:02.563772 [ModeRegInit_LP4] CH0 RK0
2522 11:41:02.567176 [ModeRegInit_LP4] CH0 RK1
2523 11:41:02.570535 [ModeRegInit_LP4] CH1 RK0
2524 11:41:02.573771 [ModeRegInit_LP4] CH1 RK1
2525 11:41:02.573861 match AC timing 7
2526 11:41:02.580196 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2527 11:41:02.583497 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2528 11:41:02.586673 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2529 11:41:02.593615 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2530 11:41:02.597115 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2531 11:41:02.597210 ==
2532 11:41:02.600266 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 11:41:02.603649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 11:41:02.603738 ==
2535 11:41:02.610262 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 11:41:02.616587 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2537 11:41:02.624071 [CA 0] Center 38 (8~69) winsize 62
2538 11:41:02.627409 [CA 1] Center 38 (7~69) winsize 63
2539 11:41:02.630735 [CA 2] Center 35 (5~66) winsize 62
2540 11:41:02.634309 [CA 3] Center 34 (4~65) winsize 62
2541 11:41:02.637579 [CA 4] Center 34 (4~65) winsize 62
2542 11:41:02.640524 [CA 5] Center 33 (3~63) winsize 61
2543 11:41:02.640611
2544 11:41:02.643869 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2545 11:41:02.643953
2546 11:41:02.647185 [CATrainingPosCal] consider 1 rank data
2547 11:41:02.650573 u2DelayCellTimex100 = 270/100 ps
2548 11:41:02.654084 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2549 11:41:02.657255 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2550 11:41:02.663795 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2551 11:41:02.667466 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2552 11:41:02.670637 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2553 11:41:02.673792 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2554 11:41:02.673880
2555 11:41:02.677222 CA PerBit enable=1, Macro0, CA PI delay=33
2556 11:41:02.677305
2557 11:41:02.680420 [CBTSetCACLKResult] CA Dly = 33
2558 11:41:02.680503 CS Dly: 6 (0~37)
2559 11:41:02.684150 ==
2560 11:41:02.684235 Dram Type= 6, Freq= 0, CH_0, rank 1
2561 11:41:02.690656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 11:41:02.690754 ==
2563 11:41:02.693837 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2564 11:41:02.701146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2565 11:41:02.709852 [CA 0] Center 39 (8~70) winsize 63
2566 11:41:02.712859 [CA 1] Center 38 (8~69) winsize 62
2567 11:41:02.716034 [CA 2] Center 35 (5~66) winsize 62
2568 11:41:02.719543 [CA 3] Center 35 (5~66) winsize 62
2569 11:41:02.722834 [CA 4] Center 34 (4~65) winsize 62
2570 11:41:02.726233 [CA 5] Center 33 (3~64) winsize 62
2571 11:41:02.726319
2572 11:41:02.729423 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2573 11:41:02.729508
2574 11:41:02.732736 [CATrainingPosCal] consider 2 rank data
2575 11:41:02.736304 u2DelayCellTimex100 = 270/100 ps
2576 11:41:02.739212 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2577 11:41:02.745725 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2578 11:41:02.749104 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2579 11:41:02.752446 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2580 11:41:02.755899 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2581 11:41:02.759089 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2582 11:41:02.759179
2583 11:41:02.762513 CA PerBit enable=1, Macro0, CA PI delay=33
2584 11:41:02.762600
2585 11:41:02.765817 [CBTSetCACLKResult] CA Dly = 33
2586 11:41:02.768961 CS Dly: 7 (0~39)
2587 11:41:02.769086
2588 11:41:02.772412 ----->DramcWriteLeveling(PI) begin...
2589 11:41:02.772497 ==
2590 11:41:02.775733 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 11:41:02.779136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 11:41:02.779223 ==
2593 11:41:02.782249 Write leveling (Byte 0): 34 => 34
2594 11:41:02.785492 Write leveling (Byte 1): 31 => 31
2595 11:41:02.789179 DramcWriteLeveling(PI) end<-----
2596 11:41:02.789265
2597 11:41:02.789329 ==
2598 11:41:02.792233 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 11:41:02.795534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2600 11:41:02.795618 ==
2601 11:41:02.799023 [Gating] SW mode calibration
2602 11:41:02.805601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2603 11:41:02.811819 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2604 11:41:02.815383 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2605 11:41:02.818634 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2606 11:41:02.825265 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 11:41:02.829007 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 11:41:02.832174 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 11:41:02.838733 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 11:41:02.842160 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2611 11:41:02.844950 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2612 11:41:02.851541 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
2613 11:41:02.854846 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2614 11:41:02.858390 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 11:41:02.864957 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 11:41:02.868173 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 11:41:02.871775 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 11:41:02.878103 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2619 11:41:02.881436 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2620 11:41:02.884820 1 1 0 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
2621 11:41:02.891574 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 11:41:02.894894 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 11:41:02.898110 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 11:41:02.904666 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 11:41:02.908040 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 11:41:02.911434 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 11:41:02.918051 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2628 11:41:02.921369 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2629 11:41:02.924890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2630 11:41:02.931623 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:41:02.934865 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:41:02.938252 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:41:02.941360 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:41:02.948572 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:41:02.951281 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:41:02.954932 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:41:02.961236 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:41:02.964771 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:41:02.968486 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:41:02.974721 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 11:41:02.977817 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 11:41:02.981122 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2643 11:41:02.987852 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2644 11:41:02.991294 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2645 11:41:02.994653 Total UI for P1: 0, mck2ui 16
2646 11:41:02.998112 best dqsien dly found for B0: ( 1, 3, 26)
2647 11:41:03.001092 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2648 11:41:03.004376 Total UI for P1: 0, mck2ui 16
2649 11:41:03.007964 best dqsien dly found for B1: ( 1, 4, 0)
2650 11:41:03.011009 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2651 11:41:03.014569 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2652 11:41:03.014656
2653 11:41:03.020813 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2654 11:41:03.024406 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2655 11:41:03.024513 [Gating] SW calibration Done
2656 11:41:03.027812 ==
2657 11:41:03.031326 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 11:41:03.034519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 11:41:03.034611 ==
2660 11:41:03.034675 RX Vref Scan: 0
2661 11:41:03.034734
2662 11:41:03.037532 RX Vref 0 -> 0, step: 1
2663 11:41:03.037614
2664 11:41:03.040767 RX Delay -40 -> 252, step: 8
2665 11:41:03.044199 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2666 11:41:03.047368 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2667 11:41:03.054029 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2668 11:41:03.057542 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2669 11:41:03.060800 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2670 11:41:03.064410 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2671 11:41:03.067561 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2672 11:41:03.070891 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2673 11:41:03.077333 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2674 11:41:03.080923 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2675 11:41:03.084158 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2676 11:41:03.087586 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2677 11:41:03.090718 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2678 11:41:03.097402 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2679 11:41:03.101098 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2680 11:41:03.104249 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2681 11:41:03.104342 ==
2682 11:41:03.107639 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 11:41:03.110933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 11:41:03.111021 ==
2685 11:41:03.114315 DQS Delay:
2686 11:41:03.114406 DQS0 = 0, DQS1 = 0
2687 11:41:03.117437 DQM Delay:
2688 11:41:03.117522 DQM0 = 122, DQM1 = 110
2689 11:41:03.120827 DQ Delay:
2690 11:41:03.124165 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2691 11:41:03.127400 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2692 11:41:03.130639 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2693 11:41:03.134053 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2694 11:41:03.134145
2695 11:41:03.134213
2696 11:41:03.134274 ==
2697 11:41:03.137256 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 11:41:03.140660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 11:41:03.140749 ==
2700 11:41:03.140816
2701 11:41:03.140878
2702 11:41:03.144158 TX Vref Scan disable
2703 11:41:03.147281 == TX Byte 0 ==
2704 11:41:03.150720 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2705 11:41:03.153927 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2706 11:41:03.157674 == TX Byte 1 ==
2707 11:41:03.160441 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2708 11:41:03.164148 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2709 11:41:03.164271 ==
2710 11:41:03.167103 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 11:41:03.170360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 11:41:03.174000 ==
2713 11:41:03.184142 TX Vref=22, minBit 5, minWin=23, winSum=403
2714 11:41:03.187610 TX Vref=24, minBit 0, minWin=24, winSum=409
2715 11:41:03.190859 TX Vref=26, minBit 1, minWin=24, winSum=410
2716 11:41:03.194012 TX Vref=28, minBit 4, minWin=25, winSum=420
2717 11:41:03.197453 TX Vref=30, minBit 1, minWin=25, winSum=419
2718 11:41:03.204125 TX Vref=32, minBit 0, minWin=25, winSum=416
2719 11:41:03.207520 [TxChooseVref] Worse bit 4, Min win 25, Win sum 420, Final Vref 28
2720 11:41:03.207617
2721 11:41:03.211299 Final TX Range 1 Vref 28
2722 11:41:03.211386
2723 11:41:03.211453 ==
2724 11:41:03.213847 Dram Type= 6, Freq= 0, CH_0, rank 0
2725 11:41:03.217297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2726 11:41:03.217384 ==
2727 11:41:03.220548
2728 11:41:03.220633
2729 11:41:03.220698 TX Vref Scan disable
2730 11:41:03.223995 == TX Byte 0 ==
2731 11:41:03.227383 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2732 11:41:03.230710 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2733 11:41:03.233952 == TX Byte 1 ==
2734 11:41:03.237313 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2735 11:41:03.240524 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2736 11:41:03.243984
2737 11:41:03.244075 [DATLAT]
2738 11:41:03.244142 Freq=1200, CH0 RK0
2739 11:41:03.244204
2740 11:41:03.246990 DATLAT Default: 0xd
2741 11:41:03.247074 0, 0xFFFF, sum = 0
2742 11:41:03.250551 1, 0xFFFF, sum = 0
2743 11:41:03.250639 2, 0xFFFF, sum = 0
2744 11:41:03.253800 3, 0xFFFF, sum = 0
2745 11:41:03.257334 4, 0xFFFF, sum = 0
2746 11:41:03.257423 5, 0xFFFF, sum = 0
2747 11:41:03.260324 6, 0xFFFF, sum = 0
2748 11:41:03.260411 7, 0xFFFF, sum = 0
2749 11:41:03.263698 8, 0xFFFF, sum = 0
2750 11:41:03.263787 9, 0xFFFF, sum = 0
2751 11:41:03.266889 10, 0xFFFF, sum = 0
2752 11:41:03.266976 11, 0xFFFF, sum = 0
2753 11:41:03.270492 12, 0x0, sum = 1
2754 11:41:03.270579 13, 0x0, sum = 2
2755 11:41:03.273418 14, 0x0, sum = 3
2756 11:41:03.273505 15, 0x0, sum = 4
2757 11:41:03.277088 best_step = 13
2758 11:41:03.277201
2759 11:41:03.277319 ==
2760 11:41:03.280097 Dram Type= 6, Freq= 0, CH_0, rank 0
2761 11:41:03.283349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2762 11:41:03.283435 ==
2763 11:41:03.283502 RX Vref Scan: 1
2764 11:41:03.283563
2765 11:41:03.286624 Set Vref Range= 32 -> 127
2766 11:41:03.286709
2767 11:41:03.290197 RX Vref 32 -> 127, step: 1
2768 11:41:03.290281
2769 11:41:03.293559 RX Delay -13 -> 252, step: 4
2770 11:41:03.293643
2771 11:41:03.296756 Set Vref, RX VrefLevel [Byte0]: 32
2772 11:41:03.300521 [Byte1]: 32
2773 11:41:03.300610
2774 11:41:03.303421 Set Vref, RX VrefLevel [Byte0]: 33
2775 11:41:03.306709 [Byte1]: 33
2776 11:41:03.310477
2777 11:41:03.310565 Set Vref, RX VrefLevel [Byte0]: 34
2778 11:41:03.313551 [Byte1]: 34
2779 11:41:03.318455
2780 11:41:03.318545 Set Vref, RX VrefLevel [Byte0]: 35
2781 11:41:03.321511 [Byte1]: 35
2782 11:41:03.325957
2783 11:41:03.326045 Set Vref, RX VrefLevel [Byte0]: 36
2784 11:41:03.329136 [Byte1]: 36
2785 11:41:03.333822
2786 11:41:03.333911 Set Vref, RX VrefLevel [Byte0]: 37
2787 11:41:03.337567 [Byte1]: 37
2788 11:41:03.342144
2789 11:41:03.342235 Set Vref, RX VrefLevel [Byte0]: 38
2790 11:41:03.345194 [Byte1]: 38
2791 11:41:03.349599
2792 11:41:03.349692 Set Vref, RX VrefLevel [Byte0]: 39
2793 11:41:03.352905 [Byte1]: 39
2794 11:41:03.357686
2795 11:41:03.357783 Set Vref, RX VrefLevel [Byte0]: 40
2796 11:41:03.360972 [Byte1]: 40
2797 11:41:03.365403
2798 11:41:03.365501 Set Vref, RX VrefLevel [Byte0]: 41
2799 11:41:03.368614 [Byte1]: 41
2800 11:41:03.373472
2801 11:41:03.373565 Set Vref, RX VrefLevel [Byte0]: 42
2802 11:41:03.376728 [Byte1]: 42
2803 11:41:03.381092
2804 11:41:03.381186 Set Vref, RX VrefLevel [Byte0]: 43
2805 11:41:03.384565 [Byte1]: 43
2806 11:41:03.389214
2807 11:41:03.389308 Set Vref, RX VrefLevel [Byte0]: 44
2808 11:41:03.392503 [Byte1]: 44
2809 11:41:03.396956
2810 11:41:03.397053 Set Vref, RX VrefLevel [Byte0]: 45
2811 11:41:03.400375 [Byte1]: 45
2812 11:41:03.405115
2813 11:41:03.405210 Set Vref, RX VrefLevel [Byte0]: 46
2814 11:41:03.408195 [Byte1]: 46
2815 11:41:03.412859
2816 11:41:03.412946 Set Vref, RX VrefLevel [Byte0]: 47
2817 11:41:03.416228 [Byte1]: 47
2818 11:41:03.420629
2819 11:41:03.420716 Set Vref, RX VrefLevel [Byte0]: 48
2820 11:41:03.424123 [Byte1]: 48
2821 11:41:03.428946
2822 11:41:03.429060 Set Vref, RX VrefLevel [Byte0]: 49
2823 11:41:03.431767 [Byte1]: 49
2824 11:41:03.436489
2825 11:41:03.436577 Set Vref, RX VrefLevel [Byte0]: 50
2826 11:41:03.440025 [Byte1]: 50
2827 11:41:03.444129
2828 11:41:03.444220 Set Vref, RX VrefLevel [Byte0]: 51
2829 11:41:03.447508 [Byte1]: 51
2830 11:41:03.452000
2831 11:41:03.452092 Set Vref, RX VrefLevel [Byte0]: 52
2832 11:41:03.455405 [Byte1]: 52
2833 11:41:03.460372
2834 11:41:03.460465 Set Vref, RX VrefLevel [Byte0]: 53
2835 11:41:03.463410 [Byte1]: 53
2836 11:41:03.468142
2837 11:41:03.468237 Set Vref, RX VrefLevel [Byte0]: 54
2838 11:41:03.471670 [Byte1]: 54
2839 11:41:03.475827
2840 11:41:03.475914 Set Vref, RX VrefLevel [Byte0]: 55
2841 11:41:03.479036 [Byte1]: 55
2842 11:41:03.483654
2843 11:41:03.483742 Set Vref, RX VrefLevel [Byte0]: 56
2844 11:41:03.487188 [Byte1]: 56
2845 11:41:03.491486
2846 11:41:03.491574 Set Vref, RX VrefLevel [Byte0]: 57
2847 11:41:03.495149 [Byte1]: 57
2848 11:41:03.499545
2849 11:41:03.499633 Set Vref, RX VrefLevel [Byte0]: 58
2850 11:41:03.502992 [Byte1]: 58
2851 11:41:03.507394
2852 11:41:03.507484 Set Vref, RX VrefLevel [Byte0]: 59
2853 11:41:03.510628 [Byte1]: 59
2854 11:41:03.515351
2855 11:41:03.515439 Set Vref, RX VrefLevel [Byte0]: 60
2856 11:41:03.518872 [Byte1]: 60
2857 11:41:03.523373
2858 11:41:03.523460 Set Vref, RX VrefLevel [Byte0]: 61
2859 11:41:03.526702 [Byte1]: 61
2860 11:41:03.531276
2861 11:41:03.531364 Set Vref, RX VrefLevel [Byte0]: 62
2862 11:41:03.534530 [Byte1]: 62
2863 11:41:03.538991
2864 11:41:03.539078 Set Vref, RX VrefLevel [Byte0]: 63
2865 11:41:03.542374 [Byte1]: 63
2866 11:41:03.546830
2867 11:41:03.546919 Set Vref, RX VrefLevel [Byte0]: 64
2868 11:41:03.550177 [Byte1]: 64
2869 11:41:03.554746
2870 11:41:03.554834 Set Vref, RX VrefLevel [Byte0]: 65
2871 11:41:03.557978 [Byte1]: 65
2872 11:41:03.562888
2873 11:41:03.562980 Set Vref, RX VrefLevel [Byte0]: 66
2874 11:41:03.566248 [Byte1]: 66
2875 11:41:03.570414
2876 11:41:03.570504 Set Vref, RX VrefLevel [Byte0]: 67
2877 11:41:03.574000 [Byte1]: 67
2878 11:41:03.578634
2879 11:41:03.578726 Set Vref, RX VrefLevel [Byte0]: 68
2880 11:41:03.581735 [Byte1]: 68
2881 11:41:03.586434
2882 11:41:03.586525 Set Vref, RX VrefLevel [Byte0]: 69
2883 11:41:03.589533 [Byte1]: 69
2884 11:41:03.594281
2885 11:41:03.594376 Set Vref, RX VrefLevel [Byte0]: 70
2886 11:41:03.597448 [Byte1]: 70
2887 11:41:03.602009
2888 11:41:03.602100 Final RX Vref Byte 0 = 61 to rank0
2889 11:41:03.605356 Final RX Vref Byte 1 = 51 to rank0
2890 11:41:03.608570 Final RX Vref Byte 0 = 61 to rank1
2891 11:41:03.611864 Final RX Vref Byte 1 = 51 to rank1==
2892 11:41:03.615278 Dram Type= 6, Freq= 0, CH_0, rank 0
2893 11:41:03.622358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 11:41:03.622464 ==
2895 11:41:03.622555 DQS Delay:
2896 11:41:03.622636 DQS0 = 0, DQS1 = 0
2897 11:41:03.625467 DQM Delay:
2898 11:41:03.625552 DQM0 = 123, DQM1 = 109
2899 11:41:03.628616 DQ Delay:
2900 11:41:03.632046 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2901 11:41:03.635214 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2902 11:41:03.638682 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2903 11:41:03.641994 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2904 11:41:03.642082
2905 11:41:03.642168
2906 11:41:03.651980 [DQSOSCAuto] RK0, (LSB)MR18= 0x704, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2907 11:41:03.652095 CH0 RK0: MR19=404, MR18=704
2908 11:41:03.658320 CH0_RK0: MR19=0x404, MR18=0x704, DQSOSC=407, MR23=63, INC=39, DEC=26
2909 11:41:03.658417
2910 11:41:03.661658 ----->DramcWriteLeveling(PI) begin...
2911 11:41:03.661747 ==
2912 11:41:03.665146 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 11:41:03.668763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 11:41:03.671815 ==
2915 11:41:03.671920 Write leveling (Byte 0): 34 => 34
2916 11:41:03.675394 Write leveling (Byte 1): 30 => 30
2917 11:41:03.678401 DramcWriteLeveling(PI) end<-----
2918 11:41:03.678490
2919 11:41:03.678573 ==
2920 11:41:03.681630 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 11:41:03.688276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 11:41:03.688383 ==
2923 11:41:03.691932 [Gating] SW mode calibration
2924 11:41:03.698661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2925 11:41:03.702274 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2926 11:41:03.708517 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2927 11:41:03.711626 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 11:41:03.714833 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 11:41:03.721911 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 11:41:03.725009 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 11:41:03.728354 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 11:41:03.731529 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 11:41:03.738270 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2934 11:41:03.741551 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 11:41:03.744833 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 11:41:03.751688 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 11:41:03.754789 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 11:41:03.757992 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 11:41:03.764646 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 11:41:03.768216 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 11:41:03.771139 1 0 28 | B1->B0 | 3636 3b3b | 0 1 | (0 0) (0 0)
2942 11:41:03.778216 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 11:41:03.781312 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:41:03.784688 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 11:41:03.791296 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:41:03.794948 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:41:03.797895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 11:41:03.804640 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 11:41:03.807756 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 11:41:03.811417 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:41:03.817949 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:41:03.821712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:41:03.824290 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:41:03.830929 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:41:03.834338 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:41:03.837554 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:41:03.844300 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:41:03.847509 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:41:03.850828 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:41:03.857574 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:41:03.860895 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:41:03.864152 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:41:03.870878 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:41:03.874134 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 11:41:03.877498 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2966 11:41:03.884298 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2967 11:41:03.884467 Total UI for P1: 0, mck2ui 16
2968 11:41:03.887400 best dqsien dly found for B1: ( 1, 3, 28)
2969 11:41:03.894273 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 11:41:03.897614 Total UI for P1: 0, mck2ui 16
2971 11:41:03.901120 best dqsien dly found for B0: ( 1, 3, 30)
2972 11:41:03.904257 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2973 11:41:03.907426 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2974 11:41:03.907518
2975 11:41:03.910536 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2976 11:41:03.913937 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2977 11:41:03.917255 [Gating] SW calibration Done
2978 11:41:03.917344 ==
2979 11:41:03.921248 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 11:41:03.924094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 11:41:03.924187 ==
2982 11:41:03.927929 RX Vref Scan: 0
2983 11:41:03.928015
2984 11:41:03.928085 RX Vref 0 -> 0, step: 1
2985 11:41:03.930670
2986 11:41:03.930755 RX Delay -40 -> 252, step: 8
2987 11:41:03.937399 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2988 11:41:03.940666 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2989 11:41:03.944175 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2990 11:41:03.947522 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2991 11:41:03.950585 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2992 11:41:03.957134 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2993 11:41:03.960448 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2994 11:41:03.963774 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2995 11:41:03.967117 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2996 11:41:03.970604 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2997 11:41:03.973852 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2998 11:41:03.980283 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2999 11:41:03.983686 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3000 11:41:03.986861 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3001 11:41:03.990699 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3002 11:41:03.997395 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3003 11:41:03.997514 ==
3004 11:41:04.000306 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 11:41:04.003529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 11:41:04.003646 ==
3007 11:41:04.003712 DQS Delay:
3008 11:41:04.006953 DQS0 = 0, DQS1 = 0
3009 11:41:04.007057 DQM Delay:
3010 11:41:04.010111 DQM0 = 120, DQM1 = 109
3011 11:41:04.010219 DQ Delay:
3012 11:41:04.013885 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3013 11:41:04.016876 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3014 11:41:04.020102 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3015 11:41:04.023498 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
3016 11:41:04.023585
3017 11:41:04.023650
3018 11:41:04.026948 ==
3019 11:41:04.030152 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 11:41:04.033426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 11:41:04.033512 ==
3022 11:41:04.033578
3023 11:41:04.033637
3024 11:41:04.036754 TX Vref Scan disable
3025 11:41:04.036838 == TX Byte 0 ==
3026 11:41:04.040128 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3027 11:41:04.047075 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3028 11:41:04.047175 == TX Byte 1 ==
3029 11:41:04.050159 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3030 11:41:04.056834 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3031 11:41:04.056932 ==
3032 11:41:04.059898 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 11:41:04.063219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 11:41:04.063307 ==
3035 11:41:04.075569 TX Vref=22, minBit 3, minWin=23, winSum=411
3036 11:41:04.078822 TX Vref=24, minBit 1, minWin=24, winSum=418
3037 11:41:04.082295 TX Vref=26, minBit 4, minWin=24, winSum=419
3038 11:41:04.085386 TX Vref=28, minBit 0, minWin=24, winSum=415
3039 11:41:04.089011 TX Vref=30, minBit 1, minWin=24, winSum=423
3040 11:41:04.096039 TX Vref=32, minBit 1, minWin=24, winSum=418
3041 11:41:04.099910 [TxChooseVref] Worse bit 1, Min win 24, Win sum 423, Final Vref 30
3042 11:41:04.100012
3043 11:41:04.102020 Final TX Range 1 Vref 30
3044 11:41:04.102108
3045 11:41:04.102175 ==
3046 11:41:04.105520 Dram Type= 6, Freq= 0, CH_0, rank 1
3047 11:41:04.109139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 11:41:04.109229 ==
3049 11:41:04.109297
3050 11:41:04.112140
3051 11:41:04.112244 TX Vref Scan disable
3052 11:41:04.115401 == TX Byte 0 ==
3053 11:41:04.118911 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3054 11:41:04.121944 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3055 11:41:04.125507 == TX Byte 1 ==
3056 11:41:04.128635 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3057 11:41:04.132448 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3058 11:41:04.135562
3059 11:41:04.135651 [DATLAT]
3060 11:41:04.135716 Freq=1200, CH0 RK1
3061 11:41:04.135778
3062 11:41:04.138738 DATLAT Default: 0xd
3063 11:41:04.138824 0, 0xFFFF, sum = 0
3064 11:41:04.142035 1, 0xFFFF, sum = 0
3065 11:41:04.142122 2, 0xFFFF, sum = 0
3066 11:41:04.145651 3, 0xFFFF, sum = 0
3067 11:41:04.145739 4, 0xFFFF, sum = 0
3068 11:41:04.148677 5, 0xFFFF, sum = 0
3069 11:41:04.151855 6, 0xFFFF, sum = 0
3070 11:41:04.151943 7, 0xFFFF, sum = 0
3071 11:41:04.155642 8, 0xFFFF, sum = 0
3072 11:41:04.155730 9, 0xFFFF, sum = 0
3073 11:41:04.158863 10, 0xFFFF, sum = 0
3074 11:41:04.158948 11, 0xFFFF, sum = 0
3075 11:41:04.161923 12, 0x0, sum = 1
3076 11:41:04.162009 13, 0x0, sum = 2
3077 11:41:04.165104 14, 0x0, sum = 3
3078 11:41:04.165193 15, 0x0, sum = 4
3079 11:41:04.165261 best_step = 13
3080 11:41:04.168803
3081 11:41:04.168912 ==
3082 11:41:04.171688 Dram Type= 6, Freq= 0, CH_0, rank 1
3083 11:41:04.175101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 11:41:04.175188 ==
3085 11:41:04.175256 RX Vref Scan: 0
3086 11:41:04.175317
3087 11:41:04.178338 RX Vref 0 -> 0, step: 1
3088 11:41:04.178422
3089 11:41:04.182024 RX Delay -21 -> 252, step: 4
3090 11:41:04.185284 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3091 11:41:04.191667 iDelay=199, Bit 1, Center 122 (55 ~ 190) 136
3092 11:41:04.195282 iDelay=199, Bit 2, Center 118 (51 ~ 186) 136
3093 11:41:04.198722 iDelay=199, Bit 3, Center 116 (51 ~ 182) 132
3094 11:41:04.201703 iDelay=199, Bit 4, Center 120 (51 ~ 190) 140
3095 11:41:04.205231 iDelay=199, Bit 5, Center 114 (51 ~ 178) 128
3096 11:41:04.211673 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3097 11:41:04.215515 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3098 11:41:04.218573 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3099 11:41:04.221808 iDelay=199, Bit 9, Center 96 (31 ~ 162) 132
3100 11:41:04.225375 iDelay=199, Bit 10, Center 108 (47 ~ 170) 124
3101 11:41:04.231745 iDelay=199, Bit 11, Center 104 (43 ~ 166) 124
3102 11:41:04.235056 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3103 11:41:04.238916 iDelay=199, Bit 13, Center 110 (47 ~ 174) 128
3104 11:41:04.241961 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3105 11:41:04.245297 iDelay=199, Bit 15, Center 116 (55 ~ 178) 124
3106 11:41:04.248490 ==
3107 11:41:04.248581 Dram Type= 6, Freq= 0, CH_0, rank 1
3108 11:41:04.255155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 11:41:04.255259 ==
3110 11:41:04.255329 DQS Delay:
3111 11:41:04.258177 DQS0 = 0, DQS1 = 0
3112 11:41:04.258262 DQM Delay:
3113 11:41:04.261661 DQM0 = 120, DQM1 = 107
3114 11:41:04.261747 DQ Delay:
3115 11:41:04.265339 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =116
3116 11:41:04.268383 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =124
3117 11:41:04.271907 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3118 11:41:04.274831 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
3119 11:41:04.274919
3120 11:41:04.274986
3121 11:41:04.285215 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3122 11:41:04.285334 CH0 RK1: MR19=403, MR18=CF4
3123 11:41:04.291384 CH0_RK1: MR19=0x403, MR18=0xCF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3124 11:41:04.294743 [RxdqsGatingPostProcess] freq 1200
3125 11:41:04.301482 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3126 11:41:04.304798 best DQS0 dly(2T, 0.5T) = (0, 11)
3127 11:41:04.308294 best DQS1 dly(2T, 0.5T) = (0, 12)
3128 11:41:04.311352 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3129 11:41:04.315065 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3130 11:41:04.318043 best DQS0 dly(2T, 0.5T) = (0, 11)
3131 11:41:04.318134 best DQS1 dly(2T, 0.5T) = (0, 11)
3132 11:41:04.321441 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3133 11:41:04.324671 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3134 11:41:04.328146 Pre-setting of DQS Precalculation
3135 11:41:04.334956 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3136 11:41:04.335068 ==
3137 11:41:04.337992 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 11:41:04.341758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 11:41:04.341849 ==
3140 11:41:04.347892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3141 11:41:04.354377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
3142 11:41:04.361433 [CA 0] Center 38 (8~68) winsize 61
3143 11:41:04.364636 [CA 1] Center 37 (7~68) winsize 62
3144 11:41:04.368026 [CA 2] Center 35 (5~65) winsize 61
3145 11:41:04.371201 [CA 3] Center 34 (4~65) winsize 62
3146 11:41:04.374861 [CA 4] Center 34 (4~65) winsize 62
3147 11:41:04.377747 [CA 5] Center 33 (3~64) winsize 62
3148 11:41:04.377833
3149 11:41:04.381287 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3150 11:41:04.381373
3151 11:41:04.384371 [CATrainingPosCal] consider 1 rank data
3152 11:41:04.387623 u2DelayCellTimex100 = 270/100 ps
3153 11:41:04.391086 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3154 11:41:04.397521 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3155 11:41:04.400868 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3156 11:41:04.404280 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3157 11:41:04.407879 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3158 11:41:04.411031 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3159 11:41:04.411124
3160 11:41:04.414344 CA PerBit enable=1, Macro0, CA PI delay=33
3161 11:41:04.414431
3162 11:41:04.417543 [CBTSetCACLKResult] CA Dly = 33
3163 11:41:04.420741 CS Dly: 5 (0~36)
3164 11:41:04.420830 ==
3165 11:41:04.424313 Dram Type= 6, Freq= 0, CH_1, rank 1
3166 11:41:04.427506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 11:41:04.427595 ==
3168 11:41:04.434464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3169 11:41:04.437461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3170 11:41:04.447056 [CA 0] Center 38 (8~68) winsize 61
3171 11:41:04.450499 [CA 1] Center 38 (7~69) winsize 63
3172 11:41:04.453909 [CA 2] Center 35 (5~66) winsize 62
3173 11:41:04.457309 [CA 3] Center 35 (5~65) winsize 61
3174 11:41:04.460365 [CA 4] Center 34 (4~64) winsize 61
3175 11:41:04.463817 [CA 5] Center 34 (4~64) winsize 61
3176 11:41:04.463908
3177 11:41:04.467361 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3178 11:41:04.467451
3179 11:41:04.470490 [CATrainingPosCal] consider 2 rank data
3180 11:41:04.474211 u2DelayCellTimex100 = 270/100 ps
3181 11:41:04.477562 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3182 11:41:04.480532 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3183 11:41:04.487217 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3184 11:41:04.490599 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3185 11:41:04.494290 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3186 11:41:04.497747 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3187 11:41:04.497852
3188 11:41:04.500294 CA PerBit enable=1, Macro0, CA PI delay=34
3189 11:41:04.500377
3190 11:41:04.503640 [CBTSetCACLKResult] CA Dly = 34
3191 11:41:04.503754 CS Dly: 6 (0~39)
3192 11:41:04.503820
3193 11:41:04.506838 ----->DramcWriteLeveling(PI) begin...
3194 11:41:04.510389 ==
3195 11:41:04.513890 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 11:41:04.517279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 11:41:04.517368 ==
3198 11:41:04.520454 Write leveling (Byte 0): 24 => 24
3199 11:41:04.523811 Write leveling (Byte 1): 27 => 27
3200 11:41:04.527057 DramcWriteLeveling(PI) end<-----
3201 11:41:04.527141
3202 11:41:04.527206 ==
3203 11:41:04.530184 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 11:41:04.533861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 11:41:04.533952 ==
3206 11:41:04.536947 [Gating] SW mode calibration
3207 11:41:04.543522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3208 11:41:04.550348 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3209 11:41:04.553464 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 11:41:04.556889 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 11:41:04.560627 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 11:41:04.566800 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 11:41:04.570103 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 11:41:04.573387 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3215 11:41:04.580288 0 15 24 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (1 0)
3216 11:41:04.583405 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 11:41:04.586970 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 11:41:04.593530 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 11:41:04.596714 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 11:41:04.600208 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 11:41:04.606907 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 11:41:04.610292 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3223 11:41:04.613353 1 0 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3224 11:41:04.619795 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 11:41:04.623102 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:41:04.626592 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:41:04.633205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 11:41:04.636585 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:41:04.639690 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 11:41:04.646412 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3231 11:41:04.649883 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3232 11:41:04.653014 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:41:04.659556 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:41:04.663245 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:41:04.666131 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:41:04.672792 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:41:04.676275 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:41:04.679809 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:41:04.686279 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:41:04.689285 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:41:04.693051 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:41:04.699475 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:41:04.702995 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:41:04.706320 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:41:04.713124 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 11:41:04.716610 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3247 11:41:04.719507 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3248 11:41:04.722800 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3249 11:41:04.726247 Total UI for P1: 0, mck2ui 16
3250 11:41:04.729483 best dqsien dly found for B0: ( 1, 3, 22)
3251 11:41:04.736089 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 11:41:04.740162 Total UI for P1: 0, mck2ui 16
3253 11:41:04.742943 best dqsien dly found for B1: ( 1, 3, 26)
3254 11:41:04.745862 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3255 11:41:04.749376 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3256 11:41:04.749470
3257 11:41:04.752786 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3258 11:41:04.755865 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3259 11:41:04.759995 [Gating] SW calibration Done
3260 11:41:04.760093 ==
3261 11:41:04.762673 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 11:41:04.766434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 11:41:04.766526 ==
3264 11:41:04.769286 RX Vref Scan: 0
3265 11:41:04.769373
3266 11:41:04.769440 RX Vref 0 -> 0, step: 1
3267 11:41:04.772907
3268 11:41:04.773032 RX Delay -40 -> 252, step: 8
3269 11:41:04.779460 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3270 11:41:04.782692 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3271 11:41:04.786405 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3272 11:41:04.789380 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3273 11:41:04.792917 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3274 11:41:04.796086 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3275 11:41:04.802441 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3276 11:41:04.805716 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3277 11:41:04.809416 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3278 11:41:04.812326 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3279 11:41:04.815856 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3280 11:41:04.822456 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3281 11:41:04.825817 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3282 11:41:04.829147 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3283 11:41:04.832641 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3284 11:41:04.839262 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3285 11:41:04.839366 ==
3286 11:41:04.842628 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 11:41:04.845657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 11:41:04.845762 ==
3289 11:41:04.845830 DQS Delay:
3290 11:41:04.849236 DQS0 = 0, DQS1 = 0
3291 11:41:04.849320 DQM Delay:
3292 11:41:04.852154 DQM0 = 119, DQM1 = 112
3293 11:41:04.852261 DQ Delay:
3294 11:41:04.855752 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3295 11:41:04.858712 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3296 11:41:04.862342 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3297 11:41:04.865415 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3298 11:41:04.865503
3299 11:41:04.865568
3300 11:41:04.868949 ==
3301 11:41:04.869078 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 11:41:04.875440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 11:41:04.875539 ==
3304 11:41:04.875612
3305 11:41:04.875672
3306 11:41:04.878778 TX Vref Scan disable
3307 11:41:04.878861 == TX Byte 0 ==
3308 11:41:04.882141 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3309 11:41:04.888842 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3310 11:41:04.888937 == TX Byte 1 ==
3311 11:41:04.892667 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3312 11:41:04.898834 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3313 11:41:04.898931 ==
3314 11:41:04.901936 Dram Type= 6, Freq= 0, CH_1, rank 0
3315 11:41:04.905458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3316 11:41:04.905546 ==
3317 11:41:04.917311 TX Vref=22, minBit 1, minWin=24, winSum=405
3318 11:41:04.920275 TX Vref=24, minBit 8, minWin=25, winSum=410
3319 11:41:04.923947 TX Vref=26, minBit 8, minWin=25, winSum=417
3320 11:41:04.927351 TX Vref=28, minBit 10, minWin=25, winSum=422
3321 11:41:04.930658 TX Vref=30, minBit 11, minWin=25, winSum=424
3322 11:41:04.937239 TX Vref=32, minBit 12, minWin=25, winSum=423
3323 11:41:04.940511 [TxChooseVref] Worse bit 11, Min win 25, Win sum 424, Final Vref 30
3324 11:41:04.940607
3325 11:41:04.943515 Final TX Range 1 Vref 30
3326 11:41:04.943600
3327 11:41:04.943665 ==
3328 11:41:04.947124 Dram Type= 6, Freq= 0, CH_1, rank 0
3329 11:41:04.950255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3330 11:41:04.953645 ==
3331 11:41:04.953736
3332 11:41:04.953802
3333 11:41:04.953861 TX Vref Scan disable
3334 11:41:04.957356 == TX Byte 0 ==
3335 11:41:04.960299 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3336 11:41:04.963898 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3337 11:41:04.967165 == TX Byte 1 ==
3338 11:41:04.970527 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3339 11:41:04.973893 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3340 11:41:04.973983
3341 11:41:04.977344 [DATLAT]
3342 11:41:04.977429 Freq=1200, CH1 RK0
3343 11:41:04.977495
3344 11:41:04.980686 DATLAT Default: 0xd
3345 11:41:04.980769 0, 0xFFFF, sum = 0
3346 11:41:04.984125 1, 0xFFFF, sum = 0
3347 11:41:04.984210 2, 0xFFFF, sum = 0
3348 11:41:04.987400 3, 0xFFFF, sum = 0
3349 11:41:04.987484 4, 0xFFFF, sum = 0
3350 11:41:04.990510 5, 0xFFFF, sum = 0
3351 11:41:04.994077 6, 0xFFFF, sum = 0
3352 11:41:04.994163 7, 0xFFFF, sum = 0
3353 11:41:04.997434 8, 0xFFFF, sum = 0
3354 11:41:04.997519 9, 0xFFFF, sum = 0
3355 11:41:05.000543 10, 0xFFFF, sum = 0
3356 11:41:05.000628 11, 0xFFFF, sum = 0
3357 11:41:05.003708 12, 0x0, sum = 1
3358 11:41:05.003796 13, 0x0, sum = 2
3359 11:41:05.007041 14, 0x0, sum = 3
3360 11:41:05.007125 15, 0x0, sum = 4
3361 11:41:05.007190 best_step = 13
3362 11:41:05.007248
3363 11:41:05.010446 ==
3364 11:41:05.013676 Dram Type= 6, Freq= 0, CH_1, rank 0
3365 11:41:05.017595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3366 11:41:05.017684 ==
3367 11:41:05.017748 RX Vref Scan: 1
3368 11:41:05.017807
3369 11:41:05.020413 Set Vref Range= 32 -> 127
3370 11:41:05.020493
3371 11:41:05.023791 RX Vref 32 -> 127, step: 1
3372 11:41:05.023872
3373 11:41:05.027369 RX Delay -13 -> 252, step: 4
3374 11:41:05.027451
3375 11:41:05.030460 Set Vref, RX VrefLevel [Byte0]: 32
3376 11:41:05.033719 [Byte1]: 32
3377 11:41:05.033802
3378 11:41:05.037109 Set Vref, RX VrefLevel [Byte0]: 33
3379 11:41:05.040489 [Byte1]: 33
3380 11:41:05.043743
3381 11:41:05.043827 Set Vref, RX VrefLevel [Byte0]: 34
3382 11:41:05.046935 [Byte1]: 34
3383 11:41:05.051311
3384 11:41:05.051395 Set Vref, RX VrefLevel [Byte0]: 35
3385 11:41:05.054656 [Byte1]: 35
3386 11:41:05.059445
3387 11:41:05.059534 Set Vref, RX VrefLevel [Byte0]: 36
3388 11:41:05.062822 [Byte1]: 36
3389 11:41:05.067270
3390 11:41:05.067362 Set Vref, RX VrefLevel [Byte0]: 37
3391 11:41:05.070526 [Byte1]: 37
3392 11:41:05.075100
3393 11:41:05.075191 Set Vref, RX VrefLevel [Byte0]: 38
3394 11:41:05.078236 [Byte1]: 38
3395 11:41:05.082843
3396 11:41:05.082932 Set Vref, RX VrefLevel [Byte0]: 39
3397 11:41:05.086100 [Byte1]: 39
3398 11:41:05.090910
3399 11:41:05.090998 Set Vref, RX VrefLevel [Byte0]: 40
3400 11:41:05.094515 [Byte1]: 40
3401 11:41:05.098810
3402 11:41:05.098895 Set Vref, RX VrefLevel [Byte0]: 41
3403 11:41:05.102338 [Byte1]: 41
3404 11:41:05.106584
3405 11:41:05.106670 Set Vref, RX VrefLevel [Byte0]: 42
3406 11:41:05.110071 [Byte1]: 42
3407 11:41:05.114359
3408 11:41:05.114444 Set Vref, RX VrefLevel [Byte0]: 43
3409 11:41:05.117733 [Byte1]: 43
3410 11:41:05.122457
3411 11:41:05.122545 Set Vref, RX VrefLevel [Byte0]: 44
3412 11:41:05.126534 [Byte1]: 44
3413 11:41:05.130435
3414 11:41:05.130524 Set Vref, RX VrefLevel [Byte0]: 45
3415 11:41:05.133356 [Byte1]: 45
3416 11:41:05.138156
3417 11:41:05.138242 Set Vref, RX VrefLevel [Byte0]: 46
3418 11:41:05.141608 [Byte1]: 46
3419 11:41:05.146077
3420 11:41:05.146165 Set Vref, RX VrefLevel [Byte0]: 47
3421 11:41:05.149684 [Byte1]: 47
3422 11:41:05.154096
3423 11:41:05.154182 Set Vref, RX VrefLevel [Byte0]: 48
3424 11:41:05.157272 [Byte1]: 48
3425 11:41:05.161877
3426 11:41:05.161961 Set Vref, RX VrefLevel [Byte0]: 49
3427 11:41:05.165126 [Byte1]: 49
3428 11:41:05.169630
3429 11:41:05.169721 Set Vref, RX VrefLevel [Byte0]: 50
3430 11:41:05.173056 [Byte1]: 50
3431 11:41:05.177445
3432 11:41:05.177531 Set Vref, RX VrefLevel [Byte0]: 51
3433 11:41:05.180809 [Byte1]: 51
3434 11:41:05.185923
3435 11:41:05.186013 Set Vref, RX VrefLevel [Byte0]: 52
3436 11:41:05.188971 [Byte1]: 52
3437 11:41:05.193652
3438 11:41:05.193740 Set Vref, RX VrefLevel [Byte0]: 53
3439 11:41:05.196676 [Byte1]: 53
3440 11:41:05.201316
3441 11:41:05.201406 Set Vref, RX VrefLevel [Byte0]: 54
3442 11:41:05.204507 [Byte1]: 54
3443 11:41:05.209287
3444 11:41:05.209370 Set Vref, RX VrefLevel [Byte0]: 55
3445 11:41:05.212310 [Byte1]: 55
3446 11:41:05.216890
3447 11:41:05.216981 Set Vref, RX VrefLevel [Byte0]: 56
3448 11:41:05.220298 [Byte1]: 56
3449 11:41:05.224728
3450 11:41:05.224814 Set Vref, RX VrefLevel [Byte0]: 57
3451 11:41:05.228237 [Byte1]: 57
3452 11:41:05.232940
3453 11:41:05.233058 Set Vref, RX VrefLevel [Byte0]: 58
3454 11:41:05.235943 [Byte1]: 58
3455 11:41:05.240483
3456 11:41:05.240567 Set Vref, RX VrefLevel [Byte0]: 59
3457 11:41:05.244792 [Byte1]: 59
3458 11:41:05.248710
3459 11:41:05.248795 Set Vref, RX VrefLevel [Byte0]: 60
3460 11:41:05.251807 [Byte1]: 60
3461 11:41:05.256251
3462 11:41:05.256366 Set Vref, RX VrefLevel [Byte0]: 61
3463 11:41:05.259762 [Byte1]: 61
3464 11:41:05.264727
3465 11:41:05.264813 Set Vref, RX VrefLevel [Byte0]: 62
3466 11:41:05.267424 [Byte1]: 62
3467 11:41:05.272174
3468 11:41:05.272264 Set Vref, RX VrefLevel [Byte0]: 63
3469 11:41:05.275439 [Byte1]: 63
3470 11:41:05.280206
3471 11:41:05.280320 Set Vref, RX VrefLevel [Byte0]: 64
3472 11:41:05.283342 [Byte1]: 64
3473 11:41:05.288133
3474 11:41:05.288221 Set Vref, RX VrefLevel [Byte0]: 65
3475 11:41:05.291588 [Byte1]: 65
3476 11:41:05.296053
3477 11:41:05.296143 Set Vref, RX VrefLevel [Byte0]: 66
3478 11:41:05.299150 [Byte1]: 66
3479 11:41:05.303822
3480 11:41:05.303915 Final RX Vref Byte 0 = 52 to rank0
3481 11:41:05.307112 Final RX Vref Byte 1 = 54 to rank0
3482 11:41:05.310379 Final RX Vref Byte 0 = 52 to rank1
3483 11:41:05.313881 Final RX Vref Byte 1 = 54 to rank1==
3484 11:41:05.317250 Dram Type= 6, Freq= 0, CH_1, rank 0
3485 11:41:05.323793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 11:41:05.323896 ==
3487 11:41:05.323967 DQS Delay:
3488 11:41:05.324027 DQS0 = 0, DQS1 = 0
3489 11:41:05.327165 DQM Delay:
3490 11:41:05.327248 DQM0 = 119, DQM1 = 112
3491 11:41:05.330559 DQ Delay:
3492 11:41:05.333867 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3493 11:41:05.336998 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3494 11:41:05.340598 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3495 11:41:05.343880 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3496 11:41:05.343966
3497 11:41:05.344029
3498 11:41:05.350575 [DQSOSCAuto] RK0, (LSB)MR18= 0x115, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3499 11:41:05.353862 CH1 RK0: MR19=404, MR18=115
3500 11:41:05.360492 CH1_RK0: MR19=0x404, MR18=0x115, DQSOSC=401, MR23=63, INC=40, DEC=27
3501 11:41:05.360595
3502 11:41:05.363832 ----->DramcWriteLeveling(PI) begin...
3503 11:41:05.363916 ==
3504 11:41:05.367268 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 11:41:05.370554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 11:41:05.370645 ==
3507 11:41:05.373710 Write leveling (Byte 0): 24 => 24
3508 11:41:05.376961 Write leveling (Byte 1): 29 => 29
3509 11:41:05.380501 DramcWriteLeveling(PI) end<-----
3510 11:41:05.380602
3511 11:41:05.380700 ==
3512 11:41:05.383917 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 11:41:05.390582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 11:41:05.390683 ==
3515 11:41:05.390750 [Gating] SW mode calibration
3516 11:41:05.400419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3517 11:41:05.403945 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3518 11:41:05.407168 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 11:41:05.414021 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 11:41:05.417407 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 11:41:05.420587 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 11:41:05.427210 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 11:41:05.430222 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 11:41:05.433851 0 15 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 0)
3525 11:41:05.440332 0 15 28 | B1->B0 | 2323 2b2b | 0 1 | (1 0) (1 0)
3526 11:41:05.443646 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 11:41:05.447032 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 11:41:05.453532 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 11:41:05.456985 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 11:41:05.460151 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 11:41:05.467106 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 11:41:05.470307 1 0 24 | B1->B0 | 3232 2424 | 0 0 | (0 0) (0 0)
3533 11:41:05.473563 1 0 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
3534 11:41:05.480148 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:41:05.483396 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 11:41:05.486767 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 11:41:05.493356 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 11:41:05.496825 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 11:41:05.499874 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 11:41:05.506396 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3541 11:41:05.509915 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3542 11:41:05.513372 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:41:05.520121 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:41:05.523290 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:41:05.526539 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:41:05.533264 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:41:05.536496 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:41:05.539727 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:41:05.546312 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:41:05.549488 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:41:05.552886 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:41:05.559490 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:41:05.562870 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:41:05.566066 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:41:05.572927 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 11:41:05.576132 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3557 11:41:05.579221 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3558 11:41:05.585805 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 11:41:05.585908 Total UI for P1: 0, mck2ui 16
3560 11:41:05.588941 best dqsien dly found for B0: ( 1, 3, 26)
3561 11:41:05.592613 Total UI for P1: 0, mck2ui 16
3562 11:41:05.595801 best dqsien dly found for B1: ( 1, 3, 26)
3563 11:41:05.602377 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3564 11:41:05.605783 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3565 11:41:05.605905
3566 11:41:05.608934 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3567 11:41:05.612267 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3568 11:41:05.615596 [Gating] SW calibration Done
3569 11:41:05.615685 ==
3570 11:41:05.619283 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 11:41:05.622117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 11:41:05.622203 ==
3573 11:41:05.625659 RX Vref Scan: 0
3574 11:41:05.625745
3575 11:41:05.625810 RX Vref 0 -> 0, step: 1
3576 11:41:05.625871
3577 11:41:05.628879 RX Delay -40 -> 252, step: 8
3578 11:41:05.632569 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3579 11:41:05.639163 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3580 11:41:05.642043 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3581 11:41:05.645381 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3582 11:41:05.648613 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3583 11:41:05.652149 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3584 11:41:05.658734 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3585 11:41:05.661902 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3586 11:41:05.665385 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3587 11:41:05.668359 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3588 11:41:05.671971 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3589 11:41:05.678394 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3590 11:41:05.681991 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3591 11:41:05.685317 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3592 11:41:05.688413 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3593 11:41:05.692613 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3594 11:41:05.694959 ==
3595 11:41:05.698356 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 11:41:05.701823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 11:41:05.701914 ==
3598 11:41:05.701982 DQS Delay:
3599 11:41:05.704921 DQS0 = 0, DQS1 = 0
3600 11:41:05.705056 DQM Delay:
3601 11:41:05.708533 DQM0 = 120, DQM1 = 113
3602 11:41:05.708618 DQ Delay:
3603 11:41:05.711408 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3604 11:41:05.714910 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3605 11:41:05.718127 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3606 11:41:05.721441 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3607 11:41:05.721529
3608 11:41:05.721593
3609 11:41:05.721653 ==
3610 11:41:05.724547 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 11:41:05.731523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 11:41:05.731620 ==
3613 11:41:05.731688
3614 11:41:05.731748
3615 11:41:05.731805 TX Vref Scan disable
3616 11:41:05.735290 == TX Byte 0 ==
3617 11:41:05.738531 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3618 11:41:05.744712 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3619 11:41:05.744838 == TX Byte 1 ==
3620 11:41:05.748382 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3621 11:41:05.754744 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3622 11:41:05.754844 ==
3623 11:41:05.758118 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 11:41:05.761668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 11:41:05.761754 ==
3626 11:41:05.772952 TX Vref=22, minBit 1, minWin=25, winSum=415
3627 11:41:05.776380 TX Vref=24, minBit 1, minWin=25, winSum=419
3628 11:41:05.779626 TX Vref=26, minBit 1, minWin=26, winSum=425
3629 11:41:05.783270 TX Vref=28, minBit 1, minWin=26, winSum=427
3630 11:41:05.786427 TX Vref=30, minBit 0, minWin=26, winSum=429
3631 11:41:05.792778 TX Vref=32, minBit 1, minWin=26, winSum=430
3632 11:41:05.796057 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 32
3633 11:41:05.796178
3634 11:41:05.799120 Final TX Range 1 Vref 32
3635 11:41:05.799233
3636 11:41:05.799324 ==
3637 11:41:05.802424 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 11:41:05.805755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 11:41:05.809117 ==
3640 11:41:05.809273
3641 11:41:05.809402
3642 11:41:05.809526 TX Vref Scan disable
3643 11:41:05.812749 == TX Byte 0 ==
3644 11:41:05.815956 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3645 11:41:05.823041 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3646 11:41:05.823161 == TX Byte 1 ==
3647 11:41:05.825898 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3648 11:41:05.832855 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3649 11:41:05.833076
3650 11:41:05.833206 [DATLAT]
3651 11:41:05.833328 Freq=1200, CH1 RK1
3652 11:41:05.833432
3653 11:41:05.835937 DATLAT Default: 0xd
3654 11:41:05.839253 0, 0xFFFF, sum = 0
3655 11:41:05.839363 1, 0xFFFF, sum = 0
3656 11:41:05.842368 2, 0xFFFF, sum = 0
3657 11:41:05.842459 3, 0xFFFF, sum = 0
3658 11:41:05.845571 4, 0xFFFF, sum = 0
3659 11:41:05.845717 5, 0xFFFF, sum = 0
3660 11:41:05.849079 6, 0xFFFF, sum = 0
3661 11:41:05.849234 7, 0xFFFF, sum = 0
3662 11:41:05.852275 8, 0xFFFF, sum = 0
3663 11:41:05.852385 9, 0xFFFF, sum = 0
3664 11:41:05.855834 10, 0xFFFF, sum = 0
3665 11:41:05.855943 11, 0xFFFF, sum = 0
3666 11:41:05.858817 12, 0x0, sum = 1
3667 11:41:05.858923 13, 0x0, sum = 2
3668 11:41:05.862288 14, 0x0, sum = 3
3669 11:41:05.862374 15, 0x0, sum = 4
3670 11:41:05.865379 best_step = 13
3671 11:41:05.865464
3672 11:41:05.865583 ==
3673 11:41:05.868809 Dram Type= 6, Freq= 0, CH_1, rank 1
3674 11:41:05.872084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3675 11:41:05.872215 ==
3676 11:41:05.875260 RX Vref Scan: 0
3677 11:41:05.875342
3678 11:41:05.875407 RX Vref 0 -> 0, step: 1
3679 11:41:05.875465
3680 11:41:05.878682 RX Delay -13 -> 252, step: 4
3681 11:41:05.885761 iDelay=195, Bit 0, Center 120 (63 ~ 178) 116
3682 11:41:05.888484 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3683 11:41:05.891628 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3684 11:41:05.895067 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3685 11:41:05.898489 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3686 11:41:05.904958 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3687 11:41:05.908146 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3688 11:41:05.911579 iDelay=195, Bit 7, Center 118 (59 ~ 178) 120
3689 11:41:05.914736 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3690 11:41:05.918149 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3691 11:41:05.924772 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3692 11:41:05.928280 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3693 11:41:05.931559 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3694 11:41:05.934772 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3695 11:41:05.941159 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3696 11:41:05.944398 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3697 11:41:05.944479 ==
3698 11:41:05.947672 Dram Type= 6, Freq= 0, CH_1, rank 1
3699 11:41:05.951112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3700 11:41:05.951194 ==
3701 11:41:05.954498 DQS Delay:
3702 11:41:05.954579 DQS0 = 0, DQS1 = 0
3703 11:41:05.954643 DQM Delay:
3704 11:41:05.957682 DQM0 = 119, DQM1 = 113
3705 11:41:05.957762 DQ Delay:
3706 11:41:05.961336 DQ0 =120, DQ1 =114, DQ2 =108, DQ3 =118
3707 11:41:05.964544 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =118
3708 11:41:05.967778 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3709 11:41:05.974155 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3710 11:41:05.974237
3711 11:41:05.974301
3712 11:41:05.980936 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3713 11:41:05.984181 CH1 RK1: MR19=403, MR18=7EC
3714 11:41:05.990607 CH1_RK1: MR19=0x403, MR18=0x7EC, DQSOSC=407, MR23=63, INC=39, DEC=26
3715 11:41:05.994218 [RxdqsGatingPostProcess] freq 1200
3716 11:41:05.997377 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3717 11:41:06.000612 best DQS0 dly(2T, 0.5T) = (0, 11)
3718 11:41:06.004082 best DQS1 dly(2T, 0.5T) = (0, 11)
3719 11:41:06.007051 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3720 11:41:06.010431 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3721 11:41:06.013730 best DQS0 dly(2T, 0.5T) = (0, 11)
3722 11:41:06.017470 best DQS1 dly(2T, 0.5T) = (0, 11)
3723 11:41:06.020348 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3724 11:41:06.023913 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3725 11:41:06.027190 Pre-setting of DQS Precalculation
3726 11:41:06.030385 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3727 11:41:06.040297 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3728 11:41:06.046832 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3729 11:41:06.046915
3730 11:41:06.046980
3731 11:41:06.050367 [Calibration Summary] 2400 Mbps
3732 11:41:06.050449 CH 0, Rank 0
3733 11:41:06.053567 SW Impedance : PASS
3734 11:41:06.053649 DUTY Scan : NO K
3735 11:41:06.056899 ZQ Calibration : PASS
3736 11:41:06.060017 Jitter Meter : NO K
3737 11:41:06.060098 CBT Training : PASS
3738 11:41:06.063514 Write leveling : PASS
3739 11:41:06.066769 RX DQS gating : PASS
3740 11:41:06.066851 RX DQ/DQS(RDDQC) : PASS
3741 11:41:06.070063 TX DQ/DQS : PASS
3742 11:41:06.073457 RX DATLAT : PASS
3743 11:41:06.073540 RX DQ/DQS(Engine): PASS
3744 11:41:06.076730 TX OE : NO K
3745 11:41:06.076813 All Pass.
3746 11:41:06.076877
3747 11:41:06.079930 CH 0, Rank 1
3748 11:41:06.080013 SW Impedance : PASS
3749 11:41:06.082981 DUTY Scan : NO K
3750 11:41:06.086653 ZQ Calibration : PASS
3751 11:41:06.086734 Jitter Meter : NO K
3752 11:41:06.089832 CBT Training : PASS
3753 11:41:06.092957 Write leveling : PASS
3754 11:41:06.093092 RX DQS gating : PASS
3755 11:41:06.096394 RX DQ/DQS(RDDQC) : PASS
3756 11:41:06.099666 TX DQ/DQS : PASS
3757 11:41:06.099747 RX DATLAT : PASS
3758 11:41:06.102755 RX DQ/DQS(Engine): PASS
3759 11:41:06.106633 TX OE : NO K
3760 11:41:06.106715 All Pass.
3761 11:41:06.106779
3762 11:41:06.106839 CH 1, Rank 0
3763 11:41:06.109425 SW Impedance : PASS
3764 11:41:06.112900 DUTY Scan : NO K
3765 11:41:06.113001 ZQ Calibration : PASS
3766 11:41:06.116159 Jitter Meter : NO K
3767 11:41:06.119323 CBT Training : PASS
3768 11:41:06.119404 Write leveling : PASS
3769 11:41:06.122727 RX DQS gating : PASS
3770 11:41:06.122808 RX DQ/DQS(RDDQC) : PASS
3771 11:41:06.126072 TX DQ/DQS : PASS
3772 11:41:06.129631 RX DATLAT : PASS
3773 11:41:06.129713 RX DQ/DQS(Engine): PASS
3774 11:41:06.132811 TX OE : NO K
3775 11:41:06.132893 All Pass.
3776 11:41:06.132958
3777 11:41:06.136193 CH 1, Rank 1
3778 11:41:06.136274 SW Impedance : PASS
3779 11:41:06.139492 DUTY Scan : NO K
3780 11:41:06.142707 ZQ Calibration : PASS
3781 11:41:06.142789 Jitter Meter : NO K
3782 11:41:06.146206 CBT Training : PASS
3783 11:41:06.149183 Write leveling : PASS
3784 11:41:06.149266 RX DQS gating : PASS
3785 11:41:06.152433 RX DQ/DQS(RDDQC) : PASS
3786 11:41:06.155896 TX DQ/DQS : PASS
3787 11:41:06.155978 RX DATLAT : PASS
3788 11:41:06.159095 RX DQ/DQS(Engine): PASS
3789 11:41:06.162845 TX OE : NO K
3790 11:41:06.162926 All Pass.
3791 11:41:06.162990
3792 11:41:06.163049 DramC Write-DBI off
3793 11:41:06.165965 PER_BANK_REFRESH: Hybrid Mode
3794 11:41:06.169190 TX_TRACKING: ON
3795 11:41:06.176092 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3796 11:41:06.182058 [FAST_K] Save calibration result to emmc
3797 11:41:06.185483 dramc_set_vcore_voltage set vcore to 650000
3798 11:41:06.185565 Read voltage for 600, 5
3799 11:41:06.188918 Vio18 = 0
3800 11:41:06.189054 Vcore = 650000
3801 11:41:06.189121 Vdram = 0
3802 11:41:06.192418 Vddq = 0
3803 11:41:06.192501 Vmddr = 0
3804 11:41:06.195386 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3805 11:41:06.201992 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3806 11:41:06.205376 MEM_TYPE=3, freq_sel=19
3807 11:41:06.208562 sv_algorithm_assistance_LP4_1600
3808 11:41:06.211940 ============ PULL DRAM RESETB DOWN ============
3809 11:41:06.215492 ========== PULL DRAM RESETB DOWN end =========
3810 11:41:06.222301 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3811 11:41:06.225673 ===================================
3812 11:41:06.225756 LPDDR4 DRAM CONFIGURATION
3813 11:41:06.228416 ===================================
3814 11:41:06.231656 EX_ROW_EN[0] = 0x0
3815 11:41:06.231738 EX_ROW_EN[1] = 0x0
3816 11:41:06.235173 LP4Y_EN = 0x0
3817 11:41:06.235254 WORK_FSP = 0x0
3818 11:41:06.238469 WL = 0x2
3819 11:41:06.238550 RL = 0x2
3820 11:41:06.241755 BL = 0x2
3821 11:41:06.244931 RPST = 0x0
3822 11:41:06.245020 RD_PRE = 0x0
3823 11:41:06.248412 WR_PRE = 0x1
3824 11:41:06.248493 WR_PST = 0x0
3825 11:41:06.251708 DBI_WR = 0x0
3826 11:41:06.251790 DBI_RD = 0x0
3827 11:41:06.254952 OTF = 0x1
3828 11:41:06.258380 ===================================
3829 11:41:06.261808 ===================================
3830 11:41:06.261890 ANA top config
3831 11:41:06.264765 ===================================
3832 11:41:06.268201 DLL_ASYNC_EN = 0
3833 11:41:06.271337 ALL_SLAVE_EN = 1
3834 11:41:06.271418 NEW_RANK_MODE = 1
3835 11:41:06.275046 DLL_IDLE_MODE = 1
3836 11:41:06.277911 LP45_APHY_COMB_EN = 1
3837 11:41:06.281559 TX_ODT_DIS = 1
3838 11:41:06.284531 NEW_8X_MODE = 1
3839 11:41:06.288128 ===================================
3840 11:41:06.291464 ===================================
3841 11:41:06.291546 data_rate = 1200
3842 11:41:06.294787 CKR = 1
3843 11:41:06.297907 DQ_P2S_RATIO = 8
3844 11:41:06.301067 ===================================
3845 11:41:06.304531 CA_P2S_RATIO = 8
3846 11:41:06.307883 DQ_CA_OPEN = 0
3847 11:41:06.310976 DQ_SEMI_OPEN = 0
3848 11:41:06.311057 CA_SEMI_OPEN = 0
3849 11:41:06.314614 CA_FULL_RATE = 0
3850 11:41:06.317699 DQ_CKDIV4_EN = 1
3851 11:41:06.321109 CA_CKDIV4_EN = 1
3852 11:41:06.324408 CA_PREDIV_EN = 0
3853 11:41:06.327498 PH8_DLY = 0
3854 11:41:06.327580 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3855 11:41:06.330983 DQ_AAMCK_DIV = 4
3856 11:41:06.334313 CA_AAMCK_DIV = 4
3857 11:41:06.337368 CA_ADMCK_DIV = 4
3858 11:41:06.340615 DQ_TRACK_CA_EN = 0
3859 11:41:06.344060 CA_PICK = 600
3860 11:41:06.347433 CA_MCKIO = 600
3861 11:41:06.347515 MCKIO_SEMI = 0
3862 11:41:06.350747 PLL_FREQ = 2288
3863 11:41:06.354087 DQ_UI_PI_RATIO = 32
3864 11:41:06.357605 CA_UI_PI_RATIO = 0
3865 11:41:06.360685 ===================================
3866 11:41:06.364385 ===================================
3867 11:41:06.367242 memory_type:LPDDR4
3868 11:41:06.367323 GP_NUM : 10
3869 11:41:06.370491 SRAM_EN : 1
3870 11:41:06.373964 MD32_EN : 0
3871 11:41:06.377085 ===================================
3872 11:41:06.377166 [ANA_INIT] >>>>>>>>>>>>>>
3873 11:41:06.380433 <<<<<< [CONFIGURE PHASE]: ANA_TX
3874 11:41:06.383681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3875 11:41:06.387142 ===================================
3876 11:41:06.390332 data_rate = 1200,PCW = 0X5800
3877 11:41:06.393670 ===================================
3878 11:41:06.397668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3879 11:41:06.403833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3880 11:41:06.406918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 11:41:06.413454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3882 11:41:06.416842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3883 11:41:06.420104 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3884 11:41:06.420186 [ANA_INIT] flow start
3885 11:41:06.423225 [ANA_INIT] PLL >>>>>>>>
3886 11:41:06.427216 [ANA_INIT] PLL <<<<<<<<
3887 11:41:06.430307 [ANA_INIT] MIDPI >>>>>>>>
3888 11:41:06.430390 [ANA_INIT] MIDPI <<<<<<<<
3889 11:41:06.433596 [ANA_INIT] DLL >>>>>>>>
3890 11:41:06.436899 [ANA_INIT] flow end
3891 11:41:06.439855 ============ LP4 DIFF to SE enter ============
3892 11:41:06.443249 ============ LP4 DIFF to SE exit ============
3893 11:41:06.446708 [ANA_INIT] <<<<<<<<<<<<<
3894 11:41:06.449869 [Flow] Enable top DCM control >>>>>
3895 11:41:06.453126 [Flow] Enable top DCM control <<<<<
3896 11:41:06.456569 Enable DLL master slave shuffle
3897 11:41:06.459704 ==============================================================
3898 11:41:06.463245 Gating Mode config
3899 11:41:06.469672 ==============================================================
3900 11:41:06.469759 Config description:
3901 11:41:06.479819 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3902 11:41:06.486149 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3903 11:41:06.489649 SELPH_MODE 0: By rank 1: By Phase
3904 11:41:06.496220 ==============================================================
3905 11:41:06.499250 GAT_TRACK_EN = 1
3906 11:41:06.502623 RX_GATING_MODE = 2
3907 11:41:06.506112 RX_GATING_TRACK_MODE = 2
3908 11:41:06.509393 SELPH_MODE = 1
3909 11:41:06.512497 PICG_EARLY_EN = 1
3910 11:41:06.515812 VALID_LAT_VALUE = 1
3911 11:41:06.519075 ==============================================================
3912 11:41:06.522730 Enter into Gating configuration >>>>
3913 11:41:06.525902 Exit from Gating configuration <<<<
3914 11:41:06.529602 Enter into DVFS_PRE_config >>>>>
3915 11:41:06.542609 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3916 11:41:06.545492 Exit from DVFS_PRE_config <<<<<
3917 11:41:06.548887 Enter into PICG configuration >>>>
3918 11:41:06.549036 Exit from PICG configuration <<<<
3919 11:41:06.552028 [RX_INPUT] configuration >>>>>
3920 11:41:06.555594 [RX_INPUT] configuration <<<<<
3921 11:41:06.562064 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3922 11:41:06.565255 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3923 11:41:06.572152 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 11:41:06.578832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 11:41:06.585169 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3926 11:41:06.591709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3927 11:41:06.594851 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3928 11:41:06.598230 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3929 11:41:06.605379 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3930 11:41:06.608151 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3931 11:41:06.611454 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3932 11:41:06.615048 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 11:41:06.618117 ===================================
3934 11:41:06.621295 LPDDR4 DRAM CONFIGURATION
3935 11:41:06.624666 ===================================
3936 11:41:06.627945 EX_ROW_EN[0] = 0x0
3937 11:41:06.628027 EX_ROW_EN[1] = 0x0
3938 11:41:06.631279 LP4Y_EN = 0x0
3939 11:41:06.631361 WORK_FSP = 0x0
3940 11:41:06.634621 WL = 0x2
3941 11:41:06.634703 RL = 0x2
3942 11:41:06.638084 BL = 0x2
3943 11:41:06.638165 RPST = 0x0
3944 11:41:06.641309 RD_PRE = 0x0
3945 11:41:06.641390 WR_PRE = 0x1
3946 11:41:06.644849 WR_PST = 0x0
3947 11:41:06.647924 DBI_WR = 0x0
3948 11:41:06.648006 DBI_RD = 0x0
3949 11:41:06.651080 OTF = 0x1
3950 11:41:06.654428 ===================================
3951 11:41:06.657774 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3952 11:41:06.661427 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3953 11:41:06.664207 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3954 11:41:06.667754 ===================================
3955 11:41:06.671065 LPDDR4 DRAM CONFIGURATION
3956 11:41:06.674167 ===================================
3957 11:41:06.677743 EX_ROW_EN[0] = 0x10
3958 11:41:06.677833 EX_ROW_EN[1] = 0x0
3959 11:41:06.680960 LP4Y_EN = 0x0
3960 11:41:06.681084 WORK_FSP = 0x0
3961 11:41:06.684185 WL = 0x2
3962 11:41:06.684272 RL = 0x2
3963 11:41:06.687584 BL = 0x2
3964 11:41:06.687670 RPST = 0x0
3965 11:41:06.691147 RD_PRE = 0x0
3966 11:41:06.691233 WR_PRE = 0x1
3967 11:41:06.694225 WR_PST = 0x0
3968 11:41:06.694311 DBI_WR = 0x0
3969 11:41:06.697522 DBI_RD = 0x0
3970 11:41:06.700655 OTF = 0x1
3971 11:41:06.704333 ===================================
3972 11:41:06.707220 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3973 11:41:06.712587 nWR fixed to 30
3974 11:41:06.715814 [ModeRegInit_LP4] CH0 RK0
3975 11:41:06.715909 [ModeRegInit_LP4] CH0 RK1
3976 11:41:06.719119 [ModeRegInit_LP4] CH1 RK0
3977 11:41:06.722577 [ModeRegInit_LP4] CH1 RK1
3978 11:41:06.722672 match AC timing 17
3979 11:41:06.729172 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3980 11:41:06.732476 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3981 11:41:06.735493 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3982 11:41:06.742196 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3983 11:41:06.745407 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3984 11:41:06.745509 ==
3985 11:41:06.748795 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 11:41:06.752108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 11:41:06.752206 ==
3988 11:41:06.758653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 11:41:06.765105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3990 11:41:06.768650 [CA 0] Center 36 (6~67) winsize 62
3991 11:41:06.771994 [CA 1] Center 36 (6~67) winsize 62
3992 11:41:06.775325 [CA 2] Center 34 (4~65) winsize 62
3993 11:41:06.778535 [CA 3] Center 34 (4~65) winsize 62
3994 11:41:06.781812 [CA 4] Center 34 (3~65) winsize 63
3995 11:41:06.785157 [CA 5] Center 33 (2~64) winsize 63
3996 11:41:06.785254
3997 11:41:06.788282 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3998 11:41:06.788372
3999 11:41:06.791633 [CATrainingPosCal] consider 1 rank data
4000 11:41:06.794918 u2DelayCellTimex100 = 270/100 ps
4001 11:41:06.798328 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4002 11:41:06.801627 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4003 11:41:06.804943 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 11:41:06.811493 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4005 11:41:06.815213 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4006 11:41:06.818094 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4007 11:41:06.818177
4008 11:41:06.821377 CA PerBit enable=1, Macro0, CA PI delay=33
4009 11:41:06.821461
4010 11:41:06.824734 [CBTSetCACLKResult] CA Dly = 33
4011 11:41:06.824817 CS Dly: 4 (0~35)
4012 11:41:06.824883 ==
4013 11:41:06.828362 Dram Type= 6, Freq= 0, CH_0, rank 1
4014 11:41:06.835145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 11:41:06.835231 ==
4016 11:41:06.837732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4017 11:41:06.844345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4018 11:41:06.847870 [CA 0] Center 36 (6~67) winsize 62
4019 11:41:06.851126 [CA 1] Center 36 (6~67) winsize 62
4020 11:41:06.854504 [CA 2] Center 34 (4~65) winsize 62
4021 11:41:06.857684 [CA 3] Center 34 (4~65) winsize 62
4022 11:41:06.861158 [CA 4] Center 33 (3~64) winsize 62
4023 11:41:06.864454 [CA 5] Center 33 (3~64) winsize 62
4024 11:41:06.864537
4025 11:41:06.867554 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4026 11:41:06.867638
4027 11:41:06.870849 [CATrainingPosCal] consider 2 rank data
4028 11:41:06.874135 u2DelayCellTimex100 = 270/100 ps
4029 11:41:06.877627 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4030 11:41:06.884124 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4031 11:41:06.887633 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4032 11:41:06.891110 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4033 11:41:06.894058 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4034 11:41:06.897224 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 11:41:06.897308
4036 11:41:06.900727 CA PerBit enable=1, Macro0, CA PI delay=33
4037 11:41:06.900811
4038 11:41:06.903940 [CBTSetCACLKResult] CA Dly = 33
4039 11:41:06.907308 CS Dly: 4 (0~36)
4040 11:41:06.907391
4041 11:41:06.910469 ----->DramcWriteLeveling(PI) begin...
4042 11:41:06.910554 ==
4043 11:41:06.913779 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 11:41:06.916864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 11:41:06.916947 ==
4046 11:41:06.920481 Write leveling (Byte 0): 35 => 35
4047 11:41:06.923739 Write leveling (Byte 1): 31 => 31
4048 11:41:06.927239 DramcWriteLeveling(PI) end<-----
4049 11:41:06.927322
4050 11:41:06.927387 ==
4051 11:41:06.930258 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 11:41:06.933640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 11:41:06.933724 ==
4054 11:41:06.936909 [Gating] SW mode calibration
4055 11:41:06.943401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4056 11:41:06.949928 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4057 11:41:06.953258 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 11:41:06.956694 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 11:41:06.963318 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 11:41:06.966647 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4061 11:41:06.969757 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4062 11:41:06.976270 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 11:41:06.979990 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 11:41:06.982811 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 11:41:06.989871 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 11:41:06.992921 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 11:41:06.996128 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4068 11:41:07.002686 0 10 12 | B1->B0 | 2929 3c3c | 0 0 | (0 0) (1 1)
4069 11:41:07.006005 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
4070 11:41:07.009273 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 11:41:07.015934 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 11:41:07.019303 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 11:41:07.025738 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 11:41:07.029098 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:41:07.032811 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:41:07.036133 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4077 11:41:07.042180 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4078 11:41:07.045399 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:41:07.049426 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:41:07.055599 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:41:07.058719 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:41:07.062293 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:41:07.068650 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:41:07.072167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:41:07.075352 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:41:07.081857 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:41:07.085274 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:41:07.088385 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:41:07.095326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:41:07.098244 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:41:07.101644 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:41:07.108373 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4093 11:41:07.111443 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4094 11:41:07.114955 Total UI for P1: 0, mck2ui 16
4095 11:41:07.118074 best dqsien dly found for B0: ( 0, 13, 12)
4096 11:41:07.121660 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 11:41:07.124529 Total UI for P1: 0, mck2ui 16
4098 11:41:07.128332 best dqsien dly found for B1: ( 0, 13, 16)
4099 11:41:07.131420 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4100 11:41:07.137853 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4101 11:41:07.137937
4102 11:41:07.141368 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4103 11:41:07.144748 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4104 11:41:07.147723 [Gating] SW calibration Done
4105 11:41:07.147806 ==
4106 11:41:07.150968 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 11:41:07.154231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 11:41:07.154314 ==
4109 11:41:07.157593 RX Vref Scan: 0
4110 11:41:07.157675
4111 11:41:07.157739 RX Vref 0 -> 0, step: 1
4112 11:41:07.157802
4113 11:41:07.161186 RX Delay -230 -> 252, step: 16
4114 11:41:07.164428 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4115 11:41:07.170779 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4116 11:41:07.174051 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4117 11:41:07.177635 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4118 11:41:07.180908 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4119 11:41:07.187536 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4120 11:41:07.190905 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4121 11:41:07.194557 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4122 11:41:07.197451 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4123 11:41:07.200590 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4124 11:41:07.207425 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4125 11:41:07.210533 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4126 11:41:07.213988 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4127 11:41:07.216943 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4128 11:41:07.223761 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4129 11:41:07.227163 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4130 11:41:07.227247 ==
4131 11:41:07.230406 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 11:41:07.233746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 11:41:07.233831 ==
4134 11:41:07.237368 DQS Delay:
4135 11:41:07.237450 DQS0 = 0, DQS1 = 0
4136 11:41:07.240321 DQM Delay:
4137 11:41:07.240403 DQM0 = 54, DQM1 = 42
4138 11:41:07.240468 DQ Delay:
4139 11:41:07.243670 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4140 11:41:07.247031 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =57
4141 11:41:07.250211 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4142 11:41:07.253638 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4143 11:41:07.253721
4144 11:41:07.253785
4145 11:41:07.253844 ==
4146 11:41:07.257136 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 11:41:07.263532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 11:41:07.263616 ==
4149 11:41:07.263681
4150 11:41:07.263740
4151 11:41:07.266743 TX Vref Scan disable
4152 11:41:07.266825 == TX Byte 0 ==
4153 11:41:07.269939 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4154 11:41:07.276880 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4155 11:41:07.276968 == TX Byte 1 ==
4156 11:41:07.279993 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4157 11:41:07.286491 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4158 11:41:07.286579 ==
4159 11:41:07.290164 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 11:41:07.293283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 11:41:07.293367 ==
4162 11:41:07.293433
4163 11:41:07.293495
4164 11:41:07.296775 TX Vref Scan disable
4165 11:41:07.300372 == TX Byte 0 ==
4166 11:41:07.303146 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4167 11:41:07.306312 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4168 11:41:07.309752 == TX Byte 1 ==
4169 11:41:07.313373 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4170 11:41:07.316515 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4171 11:41:07.316599
4172 11:41:07.319557 [DATLAT]
4173 11:41:07.319640 Freq=600, CH0 RK0
4174 11:41:07.319707
4175 11:41:07.322972 DATLAT Default: 0x9
4176 11:41:07.323057 0, 0xFFFF, sum = 0
4177 11:41:07.326383 1, 0xFFFF, sum = 0
4178 11:41:07.326468 2, 0xFFFF, sum = 0
4179 11:41:07.329539 3, 0xFFFF, sum = 0
4180 11:41:07.329624 4, 0xFFFF, sum = 0
4181 11:41:07.333245 5, 0xFFFF, sum = 0
4182 11:41:07.333330 6, 0xFFFF, sum = 0
4183 11:41:07.336216 7, 0xFFFF, sum = 0
4184 11:41:07.336302 8, 0x0, sum = 1
4185 11:41:07.339948 9, 0x0, sum = 2
4186 11:41:07.340034 10, 0x0, sum = 3
4187 11:41:07.342964 11, 0x0, sum = 4
4188 11:41:07.343048 best_step = 9
4189 11:41:07.343113
4190 11:41:07.343173 ==
4191 11:41:07.346072 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 11:41:07.349453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 11:41:07.353352 ==
4194 11:41:07.353436 RX Vref Scan: 1
4195 11:41:07.353502
4196 11:41:07.356348 RX Vref 0 -> 0, step: 1
4197 11:41:07.356431
4198 11:41:07.359722 RX Delay -179 -> 252, step: 8
4199 11:41:07.359805
4200 11:41:07.362907 Set Vref, RX VrefLevel [Byte0]: 61
4201 11:41:07.366000 [Byte1]: 51
4202 11:41:07.366084
4203 11:41:07.369299 Final RX Vref Byte 0 = 61 to rank0
4204 11:41:07.372710 Final RX Vref Byte 1 = 51 to rank0
4205 11:41:07.376047 Final RX Vref Byte 0 = 61 to rank1
4206 11:41:07.379381 Final RX Vref Byte 1 = 51 to rank1==
4207 11:41:07.382733 Dram Type= 6, Freq= 0, CH_0, rank 0
4208 11:41:07.385982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 11:41:07.386067 ==
4210 11:41:07.389138 DQS Delay:
4211 11:41:07.389221 DQS0 = 0, DQS1 = 0
4212 11:41:07.389287 DQM Delay:
4213 11:41:07.392744 DQM0 = 49, DQM1 = 37
4214 11:41:07.392828 DQ Delay:
4215 11:41:07.395700 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4216 11:41:07.399204 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4217 11:41:07.402402 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4218 11:41:07.405689 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4219 11:41:07.405774
4220 11:41:07.405840
4221 11:41:07.415672 [DQSOSCAuto] RK0, (LSB)MR18= 0x554f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4222 11:41:07.418814 CH0 RK0: MR19=808, MR18=554F
4223 11:41:07.422190 CH0_RK0: MR19=0x808, MR18=0x554F, DQSOSC=393, MR23=63, INC=169, DEC=113
4224 11:41:07.425232
4225 11:41:07.428544 ----->DramcWriteLeveling(PI) begin...
4226 11:41:07.428633 ==
4227 11:41:07.431890 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 11:41:07.435479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 11:41:07.435565 ==
4230 11:41:07.438666 Write leveling (Byte 0): 35 => 35
4231 11:41:07.442086 Write leveling (Byte 1): 31 => 31
4232 11:41:07.445343 DramcWriteLeveling(PI) end<-----
4233 11:41:07.445430
4234 11:41:07.445498 ==
4235 11:41:07.448576 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 11:41:07.452087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 11:41:07.452170 ==
4238 11:41:07.455200 [Gating] SW mode calibration
4239 11:41:07.461949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4240 11:41:07.468334 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4241 11:41:07.471822 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 11:41:07.474993 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 11:41:07.481709 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 11:41:07.484830 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 1)
4245 11:41:07.488302 0 9 16 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4246 11:41:07.494863 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 11:41:07.498131 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 11:41:07.501346 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 11:41:07.508102 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 11:41:07.511372 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 11:41:07.514558 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4252 11:41:07.521162 0 10 12 | B1->B0 | 3030 3232 | 1 1 | (0 0) (1 1)
4253 11:41:07.524459 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4254 11:41:07.527649 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 11:41:07.534337 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:41:07.537989 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 11:41:07.541004 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 11:41:07.547425 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 11:41:07.550816 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 11:41:07.554161 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4261 11:41:07.560549 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4262 11:41:07.564186 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:41:07.567118 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:41:07.573950 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:41:07.577242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:41:07.580468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:41:07.587289 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:41:07.590228 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:41:07.593642 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:41:07.600091 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:41:07.603839 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:41:07.607022 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:41:07.613537 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:41:07.616921 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:41:07.620164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4276 11:41:07.626684 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 11:41:07.630119 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4278 11:41:07.633385 Total UI for P1: 0, mck2ui 16
4279 11:41:07.636818 best dqsien dly found for B0: ( 0, 13, 14)
4280 11:41:07.639874 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 11:41:07.643207 Total UI for P1: 0, mck2ui 16
4282 11:41:07.646924 best dqsien dly found for B1: ( 0, 13, 16)
4283 11:41:07.650256 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4284 11:41:07.653367 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4285 11:41:07.653451
4286 11:41:07.660173 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4287 11:41:07.663200 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4288 11:41:07.663285 [Gating] SW calibration Done
4289 11:41:07.666581 ==
4290 11:41:07.669506 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 11:41:07.673256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 11:41:07.673344 ==
4293 11:41:07.673410 RX Vref Scan: 0
4294 11:41:07.673470
4295 11:41:07.676548 RX Vref 0 -> 0, step: 1
4296 11:41:07.676630
4297 11:41:07.679846 RX Delay -230 -> 252, step: 16
4298 11:41:07.682784 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4299 11:41:07.686239 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4300 11:41:07.693289 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4301 11:41:07.696356 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4302 11:41:07.699594 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4303 11:41:07.702934 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4304 11:41:07.706005 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4305 11:41:07.712575 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4306 11:41:07.716052 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4307 11:41:07.719463 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4308 11:41:07.722546 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4309 11:41:07.729500 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4310 11:41:07.732704 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4311 11:41:07.735770 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4312 11:41:07.739194 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4313 11:41:07.746018 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4314 11:41:07.746108 ==
4315 11:41:07.749290 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 11:41:07.752726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 11:41:07.752811 ==
4318 11:41:07.752906 DQS Delay:
4319 11:41:07.755836 DQS0 = 0, DQS1 = 0
4320 11:41:07.755918 DQM Delay:
4321 11:41:07.759827 DQM0 = 51, DQM1 = 41
4322 11:41:07.759910 DQ Delay:
4323 11:41:07.762421 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4324 11:41:07.765796 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4325 11:41:07.769015 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4326 11:41:07.772191 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4327 11:41:07.772276
4328 11:41:07.772341
4329 11:41:07.772402 ==
4330 11:41:07.775598 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 11:41:07.778849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 11:41:07.782181 ==
4333 11:41:07.782265
4334 11:41:07.782328
4335 11:41:07.782387 TX Vref Scan disable
4336 11:41:07.785534 == TX Byte 0 ==
4337 11:41:07.789125 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4338 11:41:07.791934 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4339 11:41:07.795471 == TX Byte 1 ==
4340 11:41:07.798746 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4341 11:41:07.802332 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4342 11:41:07.805397 ==
4343 11:41:07.808442 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 11:41:07.811767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 11:41:07.811852 ==
4346 11:41:07.811918
4347 11:41:07.811977
4348 11:41:07.815163 TX Vref Scan disable
4349 11:41:07.818526 == TX Byte 0 ==
4350 11:41:07.821663 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4351 11:41:07.825167 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4352 11:41:07.828341 == TX Byte 1 ==
4353 11:41:07.831876 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4354 11:41:07.835342 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4355 11:41:07.835428
4356 11:41:07.835494 [DATLAT]
4357 11:41:07.838193 Freq=600, CH0 RK1
4358 11:41:07.838276
4359 11:41:07.841925 DATLAT Default: 0x9
4360 11:41:07.842007 0, 0xFFFF, sum = 0
4361 11:41:07.844697 1, 0xFFFF, sum = 0
4362 11:41:07.844782 2, 0xFFFF, sum = 0
4363 11:41:07.848476 3, 0xFFFF, sum = 0
4364 11:41:07.848559 4, 0xFFFF, sum = 0
4365 11:41:07.851302 5, 0xFFFF, sum = 0
4366 11:41:07.851420 6, 0xFFFF, sum = 0
4367 11:41:07.854638 7, 0xFFFF, sum = 0
4368 11:41:07.854720 8, 0x0, sum = 1
4369 11:41:07.858075 9, 0x0, sum = 2
4370 11:41:07.858156 10, 0x0, sum = 3
4371 11:41:07.861433 11, 0x0, sum = 4
4372 11:41:07.861516 best_step = 9
4373 11:41:07.861579
4374 11:41:07.861638 ==
4375 11:41:07.864633 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 11:41:07.868057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 11:41:07.868139 ==
4378 11:41:07.871076 RX Vref Scan: 0
4379 11:41:07.871156
4380 11:41:07.874420 RX Vref 0 -> 0, step: 1
4381 11:41:07.874504
4382 11:41:07.874568 RX Delay -179 -> 252, step: 8
4383 11:41:07.882744 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4384 11:41:07.886212 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4385 11:41:07.888865 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4386 11:41:07.892552 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4387 11:41:07.899241 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4388 11:41:07.902162 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4389 11:41:07.905669 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4390 11:41:07.908622 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4391 11:41:07.911902 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4392 11:41:07.918560 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4393 11:41:07.921917 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4394 11:41:07.925408 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4395 11:41:07.928489 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4396 11:41:07.935167 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4397 11:41:07.938354 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4398 11:41:07.941281 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4399 11:41:07.941364 ==
4400 11:41:07.944652 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 11:41:07.948148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 11:41:07.951499 ==
4403 11:41:07.951620 DQS Delay:
4404 11:41:07.951688 DQS0 = 0, DQS1 = 0
4405 11:41:07.954677 DQM Delay:
4406 11:41:07.954758 DQM0 = 48, DQM1 = 41
4407 11:41:07.957784 DQ Delay:
4408 11:41:07.961308 DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44
4409 11:41:07.961392 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4410 11:41:07.964778 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4411 11:41:07.967844 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =52
4412 11:41:07.970930
4413 11:41:07.971014
4414 11:41:07.977630 [DQSOSCAuto] RK1, (LSB)MR18= 0x6230, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4415 11:41:07.980849 CH0 RK1: MR19=808, MR18=6230
4416 11:41:07.987612 CH0_RK1: MR19=0x808, MR18=0x6230, DQSOSC=391, MR23=63, INC=171, DEC=114
4417 11:41:07.990722 [RxdqsGatingPostProcess] freq 600
4418 11:41:07.994012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4419 11:41:07.997447 Pre-setting of DQS Precalculation
4420 11:41:08.003960 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4421 11:41:08.004053 ==
4422 11:41:08.007087 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 11:41:08.010574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 11:41:08.010657 ==
4425 11:41:08.017136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 11:41:08.023611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4427 11:41:08.027390 [CA 0] Center 35 (5~66) winsize 62
4428 11:41:08.030233 [CA 1] Center 35 (5~66) winsize 62
4429 11:41:08.033775 [CA 2] Center 34 (4~65) winsize 62
4430 11:41:08.037192 [CA 3] Center 33 (3~64) winsize 62
4431 11:41:08.040126 [CA 4] Center 33 (3~64) winsize 62
4432 11:41:08.043366 [CA 5] Center 33 (3~64) winsize 62
4433 11:41:08.043445
4434 11:41:08.046876 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4435 11:41:08.046955
4436 11:41:08.050098 [CATrainingPosCal] consider 1 rank data
4437 11:41:08.053757 u2DelayCellTimex100 = 270/100 ps
4438 11:41:08.056812 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 11:41:08.060011 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 11:41:08.063416 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 11:41:08.067332 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 11:41:08.069889 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4443 11:41:08.073510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 11:41:08.073606
4445 11:41:08.080117 CA PerBit enable=1, Macro0, CA PI delay=33
4446 11:41:08.080199
4447 11:41:08.080261 [CBTSetCACLKResult] CA Dly = 33
4448 11:41:08.083081 CS Dly: 4 (0~35)
4449 11:41:08.083162 ==
4450 11:41:08.086340 Dram Type= 6, Freq= 0, CH_1, rank 1
4451 11:41:08.089654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 11:41:08.089734 ==
4453 11:41:08.096549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 11:41:08.102933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4455 11:41:08.106289 [CA 0] Center 36 (6~66) winsize 61
4456 11:41:08.109439 [CA 1] Center 35 (5~66) winsize 62
4457 11:41:08.112927 [CA 2] Center 34 (4~65) winsize 62
4458 11:41:08.116174 [CA 3] Center 34 (4~65) winsize 62
4459 11:41:08.119441 [CA 4] Center 34 (4~65) winsize 62
4460 11:41:08.122706 [CA 5] Center 34 (4~65) winsize 62
4461 11:41:08.122787
4462 11:41:08.126233 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4463 11:41:08.126312
4464 11:41:08.129903 [CATrainingPosCal] consider 2 rank data
4465 11:41:08.132856 u2DelayCellTimex100 = 270/100 ps
4466 11:41:08.136009 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4467 11:41:08.139509 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4468 11:41:08.142796 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4469 11:41:08.146071 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4470 11:41:08.149383 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4471 11:41:08.155940 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4472 11:41:08.156024
4473 11:41:08.159146 CA PerBit enable=1, Macro0, CA PI delay=34
4474 11:41:08.159227
4475 11:41:08.162582 [CBTSetCACLKResult] CA Dly = 34
4476 11:41:08.162664 CS Dly: 5 (0~37)
4477 11:41:08.162728
4478 11:41:08.165765 ----->DramcWriteLeveling(PI) begin...
4479 11:41:08.165846 ==
4480 11:41:08.169503 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 11:41:08.175786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 11:41:08.175869 ==
4483 11:41:08.179382 Write leveling (Byte 0): 31 => 31
4484 11:41:08.179557 Write leveling (Byte 1): 29 => 29
4485 11:41:08.182338 DramcWriteLeveling(PI) end<-----
4486 11:41:08.182418
4487 11:41:08.182481 ==
4488 11:41:08.185741 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 11:41:08.192580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 11:41:08.192690 ==
4491 11:41:08.195710 [Gating] SW mode calibration
4492 11:41:08.202325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4493 11:41:08.205980 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4494 11:41:08.212354 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 11:41:08.215415 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 11:41:08.218949 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4497 11:41:08.225299 0 9 12 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
4498 11:41:08.229119 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 11:41:08.232002 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 11:41:08.238540 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 11:41:08.242115 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 11:41:08.245062 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 11:41:08.252231 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:41:08.255239 0 10 8 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4505 11:41:08.259000 0 10 12 | B1->B0 | 3838 3e3e | 0 0 | (0 0) (0 0)
4506 11:41:08.264830 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 11:41:08.268217 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 11:41:08.271320 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 11:41:08.278177 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:41:08.281641 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 11:41:08.284472 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:41:08.291079 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:41:08.294490 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4514 11:41:08.297874 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:41:08.304504 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:41:08.307753 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:41:08.311039 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:41:08.317542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:41:08.320881 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:41:08.324317 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:41:08.330900 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:41:08.334161 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:41:08.337707 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:41:08.343941 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:41:08.347377 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:41:08.350808 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:41:08.357454 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:41:08.360739 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 11:41:08.363964 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 11:41:08.367156 Total UI for P1: 0, mck2ui 16
4531 11:41:08.370688 best dqsien dly found for B0: ( 0, 13, 10)
4532 11:41:08.373701 Total UI for P1: 0, mck2ui 16
4533 11:41:08.377232 best dqsien dly found for B1: ( 0, 13, 10)
4534 11:41:08.380605 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4535 11:41:08.383627 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4536 11:41:08.383711
4537 11:41:08.390424 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4538 11:41:08.393564 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4539 11:41:08.393647 [Gating] SW calibration Done
4540 11:41:08.396967 ==
4541 11:41:08.400488 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 11:41:08.403496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 11:41:08.403579 ==
4544 11:41:08.403645 RX Vref Scan: 0
4545 11:41:08.403705
4546 11:41:08.406907 RX Vref 0 -> 0, step: 1
4547 11:41:08.406990
4548 11:41:08.410092 RX Delay -230 -> 252, step: 16
4549 11:41:08.413368 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4550 11:41:08.416677 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4551 11:41:08.423400 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4552 11:41:08.426601 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4553 11:41:08.430023 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4554 11:41:08.433521 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4555 11:41:08.440293 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4556 11:41:08.443340 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4557 11:41:08.446415 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4558 11:41:08.449807 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4559 11:41:08.453160 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4560 11:41:08.459977 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4561 11:41:08.463286 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4562 11:41:08.466152 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4563 11:41:08.472909 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4564 11:41:08.476126 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4565 11:41:08.476209 ==
4566 11:41:08.479995 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 11:41:08.482746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 11:41:08.482830 ==
4569 11:41:08.486092 DQS Delay:
4570 11:41:08.486175 DQS0 = 0, DQS1 = 0
4571 11:41:08.486241 DQM Delay:
4572 11:41:08.489422 DQM0 = 48, DQM1 = 39
4573 11:41:08.489502 DQ Delay:
4574 11:41:08.492576 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4575 11:41:08.496350 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4576 11:41:08.499388 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4577 11:41:08.502767 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4578 11:41:08.502848
4579 11:41:08.502911
4580 11:41:08.502968 ==
4581 11:41:08.505884 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 11:41:08.512587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 11:41:08.512670 ==
4584 11:41:08.512735
4585 11:41:08.512792
4586 11:41:08.512849 TX Vref Scan disable
4587 11:41:08.516143 == TX Byte 0 ==
4588 11:41:08.519517 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4589 11:41:08.523272 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4590 11:41:08.526099 == TX Byte 1 ==
4591 11:41:08.529328 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4592 11:41:08.536131 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4593 11:41:08.536231 ==
4594 11:41:08.539150 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 11:41:08.542412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 11:41:08.542493 ==
4597 11:41:08.542555
4598 11:41:08.542613
4599 11:41:08.546369 TX Vref Scan disable
4600 11:41:08.549262 == TX Byte 0 ==
4601 11:41:08.552323 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4602 11:41:08.555861 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4603 11:41:08.559202 == TX Byte 1 ==
4604 11:41:08.562455 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4605 11:41:08.565561 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4606 11:41:08.565642
4607 11:41:08.565704 [DATLAT]
4608 11:41:08.568922 Freq=600, CH1 RK0
4609 11:41:08.569030
4610 11:41:08.572264 DATLAT Default: 0x9
4611 11:41:08.572348 0, 0xFFFF, sum = 0
4612 11:41:08.575380 1, 0xFFFF, sum = 0
4613 11:41:08.575463 2, 0xFFFF, sum = 0
4614 11:41:08.579148 3, 0xFFFF, sum = 0
4615 11:41:08.579230 4, 0xFFFF, sum = 0
4616 11:41:08.581987 5, 0xFFFF, sum = 0
4617 11:41:08.582069 6, 0xFFFF, sum = 0
4618 11:41:08.585853 7, 0xFFFF, sum = 0
4619 11:41:08.585934 8, 0x0, sum = 1
4620 11:41:08.588687 9, 0x0, sum = 2
4621 11:41:08.588770 10, 0x0, sum = 3
4622 11:41:08.592274 11, 0x0, sum = 4
4623 11:41:08.592357 best_step = 9
4624 11:41:08.592423
4625 11:41:08.592481 ==
4626 11:41:08.595340 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 11:41:08.598594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 11:41:08.598676 ==
4629 11:41:08.601965 RX Vref Scan: 1
4630 11:41:08.602045
4631 11:41:08.605283 RX Vref 0 -> 0, step: 1
4632 11:41:08.605364
4633 11:41:08.605428 RX Delay -179 -> 252, step: 8
4634 11:41:08.605488
4635 11:41:08.608786 Set Vref, RX VrefLevel [Byte0]: 52
4636 11:41:08.611850 [Byte1]: 54
4637 11:41:08.616843
4638 11:41:08.616924 Final RX Vref Byte 0 = 52 to rank0
4639 11:41:08.619861 Final RX Vref Byte 1 = 54 to rank0
4640 11:41:08.623027 Final RX Vref Byte 0 = 52 to rank1
4641 11:41:08.626228 Final RX Vref Byte 1 = 54 to rank1==
4642 11:41:08.629876 Dram Type= 6, Freq= 0, CH_1, rank 0
4643 11:41:08.636310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 11:41:08.636393 ==
4645 11:41:08.636459 DQS Delay:
4646 11:41:08.639243 DQS0 = 0, DQS1 = 0
4647 11:41:08.639325 DQM Delay:
4648 11:41:08.639390 DQM0 = 48, DQM1 = 40
4649 11:41:08.642507 DQ Delay:
4650 11:41:08.645875 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4651 11:41:08.649193 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4652 11:41:08.652735 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4653 11:41:08.655928 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =44
4654 11:41:08.656010
4655 11:41:08.656074
4656 11:41:08.662373 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4657 11:41:08.665696 CH1 RK0: MR19=808, MR18=4C72
4658 11:41:08.672073 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4659 11:41:08.672155
4660 11:41:08.675464 ----->DramcWriteLeveling(PI) begin...
4661 11:41:08.675548 ==
4662 11:41:08.679047 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 11:41:08.682085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 11:41:08.682167 ==
4665 11:41:08.685323 Write leveling (Byte 0): 31 => 31
4666 11:41:08.688851 Write leveling (Byte 1): 31 => 31
4667 11:41:08.691789 DramcWriteLeveling(PI) end<-----
4668 11:41:08.691870
4669 11:41:08.691935 ==
4670 11:41:08.695325 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 11:41:08.701638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 11:41:08.701720 ==
4673 11:41:08.701785 [Gating] SW mode calibration
4674 11:41:08.711811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4675 11:41:08.714992 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4676 11:41:08.718353 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4677 11:41:08.725221 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4678 11:41:08.728368 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
4679 11:41:08.731601 0 9 12 | B1->B0 | 2c2c 3232 | 0 1 | (1 0) (1 0)
4680 11:41:08.738057 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4681 11:41:08.741483 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 11:41:08.744497 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 11:41:08.751340 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 11:41:08.754647 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 11:41:08.757971 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 11:41:08.764558 0 10 8 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
4687 11:41:08.767821 0 10 12 | B1->B0 | 4242 3434 | 0 0 | (0 0) (0 0)
4688 11:41:08.771271 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 11:41:08.777677 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 11:41:08.780998 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 11:41:08.784398 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 11:41:08.791133 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 11:41:08.794162 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 11:41:08.797797 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4695 11:41:08.804307 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4696 11:41:08.807360 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:41:08.810690 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:41:08.817405 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:41:08.820876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:41:08.823980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:41:08.830642 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:41:08.833830 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:41:08.837234 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:41:08.843666 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:41:08.847112 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:41:08.850350 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:41:08.857152 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:41:08.860516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:41:08.863837 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:41:08.870264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:41:08.873232 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4712 11:41:08.876648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 11:41:08.880078 Total UI for P1: 0, mck2ui 16
4714 11:41:08.883126 best dqsien dly found for B0: ( 0, 13, 12)
4715 11:41:08.886564 Total UI for P1: 0, mck2ui 16
4716 11:41:08.889756 best dqsien dly found for B1: ( 0, 13, 12)
4717 11:41:08.893313 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4718 11:41:08.899685 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4719 11:41:08.899768
4720 11:41:08.903129 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4721 11:41:08.906093 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4722 11:41:08.909366 [Gating] SW calibration Done
4723 11:41:08.909447 ==
4724 11:41:08.912884 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 11:41:08.916308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 11:41:08.916391 ==
4727 11:41:08.919618 RX Vref Scan: 0
4728 11:41:08.919700
4729 11:41:08.919764 RX Vref 0 -> 0, step: 1
4730 11:41:08.919824
4731 11:41:08.922769 RX Delay -230 -> 252, step: 16
4732 11:41:08.926090 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4733 11:41:08.932711 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4734 11:41:08.935939 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4735 11:41:08.939131 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4736 11:41:08.943093 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4737 11:41:08.949303 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4738 11:41:08.952416 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4739 11:41:08.955662 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4740 11:41:08.959154 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4741 11:41:08.962343 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4742 11:41:08.968932 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4743 11:41:08.972221 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4744 11:41:08.975632 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4745 11:41:08.979031 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4746 11:41:08.985487 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4747 11:41:08.988854 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4748 11:41:08.988937 ==
4749 11:41:08.992214 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 11:41:08.995501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 11:41:08.995583 ==
4752 11:41:08.998900 DQS Delay:
4753 11:41:08.998982 DQS0 = 0, DQS1 = 0
4754 11:41:08.999047 DQM Delay:
4755 11:41:09.002129 DQM0 = 52, DQM1 = 46
4756 11:41:09.002211 DQ Delay:
4757 11:41:09.005446 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4758 11:41:09.009134 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4759 11:41:09.012400 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4760 11:41:09.015509 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4761 11:41:09.015591
4762 11:41:09.015654
4763 11:41:09.015713 ==
4764 11:41:09.018542 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 11:41:09.025367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 11:41:09.025449 ==
4767 11:41:09.025513
4768 11:41:09.025571
4769 11:41:09.025628 TX Vref Scan disable
4770 11:41:09.029137 == TX Byte 0 ==
4771 11:41:09.032359 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4772 11:41:09.035703 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4773 11:41:09.039212 == TX Byte 1 ==
4774 11:41:09.042738 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4775 11:41:09.049106 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4776 11:41:09.049189 ==
4777 11:41:09.052213 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 11:41:09.055549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 11:41:09.055631 ==
4780 11:41:09.055696
4781 11:41:09.055754
4782 11:41:09.058691 TX Vref Scan disable
4783 11:41:09.062448 == TX Byte 0 ==
4784 11:41:09.065346 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4785 11:41:09.068929 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4786 11:41:09.071650 == TX Byte 1 ==
4787 11:41:09.075015 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4788 11:41:09.078608 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4789 11:41:09.078690
4790 11:41:09.081674 [DATLAT]
4791 11:41:09.081755 Freq=600, CH1 RK1
4792 11:41:09.081820
4793 11:41:09.085015 DATLAT Default: 0x9
4794 11:41:09.085097 0, 0xFFFF, sum = 0
4795 11:41:09.088324 1, 0xFFFF, sum = 0
4796 11:41:09.088407 2, 0xFFFF, sum = 0
4797 11:41:09.091626 3, 0xFFFF, sum = 0
4798 11:41:09.091709 4, 0xFFFF, sum = 0
4799 11:41:09.095366 5, 0xFFFF, sum = 0
4800 11:41:09.095449 6, 0xFFFF, sum = 0
4801 11:41:09.098885 7, 0xFFFF, sum = 0
4802 11:41:09.098967 8, 0x0, sum = 1
4803 11:41:09.101798 9, 0x0, sum = 2
4804 11:41:09.101880 10, 0x0, sum = 3
4805 11:41:09.104949 11, 0x0, sum = 4
4806 11:41:09.105067 best_step = 9
4807 11:41:09.105132
4808 11:41:09.105192 ==
4809 11:41:09.108344 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 11:41:09.111744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 11:41:09.111827 ==
4812 11:41:09.115074 RX Vref Scan: 0
4813 11:41:09.115155
4814 11:41:09.118336 RX Vref 0 -> 0, step: 1
4815 11:41:09.118418
4816 11:41:09.118483 RX Delay -179 -> 252, step: 8
4817 11:41:09.126077 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4818 11:41:09.129447 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4819 11:41:09.132691 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4820 11:41:09.136201 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4821 11:41:09.139357 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4822 11:41:09.145775 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4823 11:41:09.149108 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4824 11:41:09.152390 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4825 11:41:09.155913 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4826 11:41:09.162231 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4827 11:41:09.165732 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4828 11:41:09.168904 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4829 11:41:09.172181 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4830 11:41:09.175741 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4831 11:41:09.182206 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4832 11:41:09.185377 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4833 11:41:09.185459 ==
4834 11:41:09.188734 Dram Type= 6, Freq= 0, CH_1, rank 1
4835 11:41:09.192447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4836 11:41:09.192530 ==
4837 11:41:09.195744 DQS Delay:
4838 11:41:09.195825 DQS0 = 0, DQS1 = 0
4839 11:41:09.195889 DQM Delay:
4840 11:41:09.198984 DQM0 = 49, DQM1 = 43
4841 11:41:09.199065 DQ Delay:
4842 11:41:09.202249 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4843 11:41:09.205820 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4844 11:41:09.208823 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4845 11:41:09.212176 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4846 11:41:09.212258
4847 11:41:09.212321
4848 11:41:09.221877 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4849 11:41:09.225254 CH1 RK1: MR19=808, MR18=5B21
4850 11:41:09.231716 CH1_RK1: MR19=0x808, MR18=0x5B21, DQSOSC=392, MR23=63, INC=170, DEC=113
4851 11:41:09.231799 [RxdqsGatingPostProcess] freq 600
4852 11:41:09.238431 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4853 11:41:09.241635 Pre-setting of DQS Precalculation
4854 11:41:09.244954 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4855 11:41:09.254627 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4856 11:41:09.261367 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4857 11:41:09.261451
4858 11:41:09.261515
4859 11:41:09.264593 [Calibration Summary] 1200 Mbps
4860 11:41:09.264676 CH 0, Rank 0
4861 11:41:09.268028 SW Impedance : PASS
4862 11:41:09.268109 DUTY Scan : NO K
4863 11:41:09.271529 ZQ Calibration : PASS
4864 11:41:09.274685 Jitter Meter : NO K
4865 11:41:09.274766 CBT Training : PASS
4866 11:41:09.278098 Write leveling : PASS
4867 11:41:09.281200 RX DQS gating : PASS
4868 11:41:09.281283 RX DQ/DQS(RDDQC) : PASS
4869 11:41:09.285334 TX DQ/DQS : PASS
4870 11:41:09.287824 RX DATLAT : PASS
4871 11:41:09.287904 RX DQ/DQS(Engine): PASS
4872 11:41:09.291074 TX OE : NO K
4873 11:41:09.291154 All Pass.
4874 11:41:09.291217
4875 11:41:09.294622 CH 0, Rank 1
4876 11:41:09.294702 SW Impedance : PASS
4877 11:41:09.297734 DUTY Scan : NO K
4878 11:41:09.301216 ZQ Calibration : PASS
4879 11:41:09.301296 Jitter Meter : NO K
4880 11:41:09.304541 CBT Training : PASS
4881 11:41:09.307773 Write leveling : PASS
4882 11:41:09.307854 RX DQS gating : PASS
4883 11:41:09.310976 RX DQ/DQS(RDDQC) : PASS
4884 11:41:09.314096 TX DQ/DQS : PASS
4885 11:41:09.314178 RX DATLAT : PASS
4886 11:41:09.317794 RX DQ/DQS(Engine): PASS
4887 11:41:09.320913 TX OE : NO K
4888 11:41:09.321017 All Pass.
4889 11:41:09.321108
4890 11:41:09.321166 CH 1, Rank 0
4891 11:41:09.324052 SW Impedance : PASS
4892 11:41:09.327510 DUTY Scan : NO K
4893 11:41:09.327590 ZQ Calibration : PASS
4894 11:41:09.330746 Jitter Meter : NO K
4895 11:41:09.334014 CBT Training : PASS
4896 11:41:09.334094 Write leveling : PASS
4897 11:41:09.337629 RX DQS gating : PASS
4898 11:41:09.337709 RX DQ/DQS(RDDQC) : PASS
4899 11:41:09.340584 TX DQ/DQS : PASS
4900 11:41:09.344437 RX DATLAT : PASS
4901 11:41:09.344530 RX DQ/DQS(Engine): PASS
4902 11:41:09.347395 TX OE : NO K
4903 11:41:09.347491 All Pass.
4904 11:41:09.347577
4905 11:41:09.350656 CH 1, Rank 1
4906 11:41:09.350737 SW Impedance : PASS
4907 11:41:09.354301 DUTY Scan : NO K
4908 11:41:09.357033 ZQ Calibration : PASS
4909 11:41:09.357114 Jitter Meter : NO K
4910 11:41:09.360788 CBT Training : PASS
4911 11:41:09.363985 Write leveling : PASS
4912 11:41:09.364065 RX DQS gating : PASS
4913 11:41:09.367165 RX DQ/DQS(RDDQC) : PASS
4914 11:41:09.370101 TX DQ/DQS : PASS
4915 11:41:09.370181 RX DATLAT : PASS
4916 11:41:09.373700 RX DQ/DQS(Engine): PASS
4917 11:41:09.376888 TX OE : NO K
4918 11:41:09.377035 All Pass.
4919 11:41:09.377162
4920 11:41:09.380070 DramC Write-DBI off
4921 11:41:09.380149 PER_BANK_REFRESH: Hybrid Mode
4922 11:41:09.383624 TX_TRACKING: ON
4923 11:41:09.390067 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4924 11:41:09.396413 [FAST_K] Save calibration result to emmc
4925 11:41:09.400068 dramc_set_vcore_voltage set vcore to 662500
4926 11:41:09.400150 Read voltage for 933, 3
4927 11:41:09.403304 Vio18 = 0
4928 11:41:09.403385 Vcore = 662500
4929 11:41:09.403450 Vdram = 0
4930 11:41:09.406881 Vddq = 0
4931 11:41:09.406963 Vmddr = 0
4932 11:41:09.409782 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4933 11:41:09.416474 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4934 11:41:09.419606 MEM_TYPE=3, freq_sel=17
4935 11:41:09.422972 sv_algorithm_assistance_LP4_1600
4936 11:41:09.426391 ============ PULL DRAM RESETB DOWN ============
4937 11:41:09.429684 ========== PULL DRAM RESETB DOWN end =========
4938 11:41:09.436116 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4939 11:41:09.439972 ===================================
4940 11:41:09.440056 LPDDR4 DRAM CONFIGURATION
4941 11:41:09.444124 ===================================
4942 11:41:09.446301 EX_ROW_EN[0] = 0x0
4943 11:41:09.446383 EX_ROW_EN[1] = 0x0
4944 11:41:09.449418 LP4Y_EN = 0x0
4945 11:41:09.452900 WORK_FSP = 0x0
4946 11:41:09.452986 WL = 0x3
4947 11:41:09.455998 RL = 0x3
4948 11:41:09.456080 BL = 0x2
4949 11:41:09.459315 RPST = 0x0
4950 11:41:09.459396 RD_PRE = 0x0
4951 11:41:09.462619 WR_PRE = 0x1
4952 11:41:09.462700 WR_PST = 0x0
4953 11:41:09.465683 DBI_WR = 0x0
4954 11:41:09.465765 DBI_RD = 0x0
4955 11:41:09.469196 OTF = 0x1
4956 11:41:09.472440 ===================================
4957 11:41:09.475583 ===================================
4958 11:41:09.475700 ANA top config
4959 11:41:09.479035 ===================================
4960 11:41:09.482728 DLL_ASYNC_EN = 0
4961 11:41:09.485869 ALL_SLAVE_EN = 1
4962 11:41:09.485949 NEW_RANK_MODE = 1
4963 11:41:09.489185 DLL_IDLE_MODE = 1
4964 11:41:09.492217 LP45_APHY_COMB_EN = 1
4965 11:41:09.495392 TX_ODT_DIS = 1
4966 11:41:09.498970 NEW_8X_MODE = 1
4967 11:41:09.501904 ===================================
4968 11:41:09.505267 ===================================
4969 11:41:09.508715 data_rate = 1866
4970 11:41:09.508815 CKR = 1
4971 11:41:09.511880 DQ_P2S_RATIO = 8
4972 11:41:09.515393 ===================================
4973 11:41:09.518297 CA_P2S_RATIO = 8
4974 11:41:09.521758 DQ_CA_OPEN = 0
4975 11:41:09.524957 DQ_SEMI_OPEN = 0
4976 11:41:09.528372 CA_SEMI_OPEN = 0
4977 11:41:09.528452 CA_FULL_RATE = 0
4978 11:41:09.531823 DQ_CKDIV4_EN = 1
4979 11:41:09.534821 CA_CKDIV4_EN = 1
4980 11:41:09.538423 CA_PREDIV_EN = 0
4981 11:41:09.542114 PH8_DLY = 0
4982 11:41:09.544742 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4983 11:41:09.544823 DQ_AAMCK_DIV = 4
4984 11:41:09.548111 CA_AAMCK_DIV = 4
4985 11:41:09.551368 CA_ADMCK_DIV = 4
4986 11:41:09.554751 DQ_TRACK_CA_EN = 0
4987 11:41:09.558196 CA_PICK = 933
4988 11:41:09.561316 CA_MCKIO = 933
4989 11:41:09.564706 MCKIO_SEMI = 0
4990 11:41:09.564787 PLL_FREQ = 3732
4991 11:41:09.568244 DQ_UI_PI_RATIO = 32
4992 11:41:09.571094 CA_UI_PI_RATIO = 0
4993 11:41:09.574554 ===================================
4994 11:41:09.577924 ===================================
4995 11:41:09.581123 memory_type:LPDDR4
4996 11:41:09.584450 GP_NUM : 10
4997 11:41:09.584531 SRAM_EN : 1
4998 11:41:09.587589 MD32_EN : 0
4999 11:41:09.591455 ===================================
5000 11:41:09.591541 [ANA_INIT] >>>>>>>>>>>>>>
5001 11:41:09.594774 <<<<<< [CONFIGURE PHASE]: ANA_TX
5002 11:41:09.597835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5003 11:41:09.600928 ===================================
5004 11:41:09.604283 data_rate = 1866,PCW = 0X8f00
5005 11:41:09.607430 ===================================
5006 11:41:09.610862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5007 11:41:09.617335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5008 11:41:09.624379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 11:41:09.627531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5010 11:41:09.631056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5011 11:41:09.634371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5012 11:41:09.637794 [ANA_INIT] flow start
5013 11:41:09.637881 [ANA_INIT] PLL >>>>>>>>
5014 11:41:09.640836 [ANA_INIT] PLL <<<<<<<<
5015 11:41:09.644054 [ANA_INIT] MIDPI >>>>>>>>
5016 11:41:09.644139 [ANA_INIT] MIDPI <<<<<<<<
5017 11:41:09.647660 [ANA_INIT] DLL >>>>>>>>
5018 11:41:09.650559 [ANA_INIT] flow end
5019 11:41:09.654002 ============ LP4 DIFF to SE enter ============
5020 11:41:09.656990 ============ LP4 DIFF to SE exit ============
5021 11:41:09.660449 [ANA_INIT] <<<<<<<<<<<<<
5022 11:41:09.663675 [Flow] Enable top DCM control >>>>>
5023 11:41:09.666981 [Flow] Enable top DCM control <<<<<
5024 11:41:09.670413 Enable DLL master slave shuffle
5025 11:41:09.673610 ==============================================================
5026 11:41:09.677361 Gating Mode config
5027 11:41:09.683595 ==============================================================
5028 11:41:09.683682 Config description:
5029 11:41:09.693581 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5030 11:41:09.700145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5031 11:41:09.706985 SELPH_MODE 0: By rank 1: By Phase
5032 11:41:09.710122 ==============================================================
5033 11:41:09.713418 GAT_TRACK_EN = 1
5034 11:41:09.716824 RX_GATING_MODE = 2
5035 11:41:09.720022 RX_GATING_TRACK_MODE = 2
5036 11:41:09.723517 SELPH_MODE = 1
5037 11:41:09.726605 PICG_EARLY_EN = 1
5038 11:41:09.729945 VALID_LAT_VALUE = 1
5039 11:41:09.733479 ==============================================================
5040 11:41:09.736884 Enter into Gating configuration >>>>
5041 11:41:09.740083 Exit from Gating configuration <<<<
5042 11:41:09.743098 Enter into DVFS_PRE_config >>>>>
5043 11:41:09.757085 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5044 11:41:09.759674 Exit from DVFS_PRE_config <<<<<
5045 11:41:09.763128 Enter into PICG configuration >>>>
5046 11:41:09.766403 Exit from PICG configuration <<<<
5047 11:41:09.766487 [RX_INPUT] configuration >>>>>
5048 11:41:09.769736 [RX_INPUT] configuration <<<<<
5049 11:41:09.776183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5050 11:41:09.779535 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5051 11:41:09.786181 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 11:41:09.792808 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 11:41:09.799297 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5054 11:41:09.806257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5055 11:41:09.808973 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5056 11:41:09.812523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5057 11:41:09.819169 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5058 11:41:09.822456 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5059 11:41:09.826155 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5060 11:41:09.828956 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 11:41:09.832591 ===================================
5062 11:41:09.835756 LPDDR4 DRAM CONFIGURATION
5063 11:41:09.838942 ===================================
5064 11:41:09.842342 EX_ROW_EN[0] = 0x0
5065 11:41:09.842424 EX_ROW_EN[1] = 0x0
5066 11:41:09.845987 LP4Y_EN = 0x0
5067 11:41:09.846068 WORK_FSP = 0x0
5068 11:41:09.848825 WL = 0x3
5069 11:41:09.848906 RL = 0x3
5070 11:41:09.852215 BL = 0x2
5071 11:41:09.852295 RPST = 0x0
5072 11:41:09.855682 RD_PRE = 0x0
5073 11:41:09.859434 WR_PRE = 0x1
5074 11:41:09.859516 WR_PST = 0x0
5075 11:41:09.862139 DBI_WR = 0x0
5076 11:41:09.862219 DBI_RD = 0x0
5077 11:41:09.865572 OTF = 0x1
5078 11:41:09.868599 ===================================
5079 11:41:09.872150 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5080 11:41:09.875521 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5081 11:41:09.878780 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5082 11:41:09.881786 ===================================
5083 11:41:09.885283 LPDDR4 DRAM CONFIGURATION
5084 11:41:09.888538 ===================================
5085 11:41:09.891735 EX_ROW_EN[0] = 0x10
5086 11:41:09.891818 EX_ROW_EN[1] = 0x0
5087 11:41:09.895338 LP4Y_EN = 0x0
5088 11:41:09.895420 WORK_FSP = 0x0
5089 11:41:09.898393 WL = 0x3
5090 11:41:09.898475 RL = 0x3
5091 11:41:09.901775 BL = 0x2
5092 11:41:09.901856 RPST = 0x0
5093 11:41:09.904920 RD_PRE = 0x0
5094 11:41:09.908392 WR_PRE = 0x1
5095 11:41:09.908473 WR_PST = 0x0
5096 11:41:09.911594 DBI_WR = 0x0
5097 11:41:09.911675 DBI_RD = 0x0
5098 11:41:09.914976 OTF = 0x1
5099 11:41:09.918196 ===================================
5100 11:41:09.921750 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5101 11:41:09.926880 nWR fixed to 30
5102 11:41:09.930375 [ModeRegInit_LP4] CH0 RK0
5103 11:41:09.930458 [ModeRegInit_LP4] CH0 RK1
5104 11:41:09.933542 [ModeRegInit_LP4] CH1 RK0
5105 11:41:09.936789 [ModeRegInit_LP4] CH1 RK1
5106 11:41:09.936871 match AC timing 9
5107 11:41:09.943473 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5108 11:41:09.947048 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5109 11:41:09.950426 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5110 11:41:09.956760 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5111 11:41:09.960028 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5112 11:41:09.960109 ==
5113 11:41:09.963586 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 11:41:09.966612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 11:41:09.966695 ==
5116 11:41:09.973183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5117 11:41:09.980113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5118 11:41:09.983317 [CA 0] Center 38 (7~69) winsize 63
5119 11:41:09.986310 [CA 1] Center 38 (7~69) winsize 63
5120 11:41:09.989508 [CA 2] Center 35 (5~66) winsize 62
5121 11:41:09.993145 [CA 3] Center 35 (5~66) winsize 62
5122 11:41:09.996629 [CA 4] Center 34 (4~65) winsize 62
5123 11:41:09.999623 [CA 5] Center 33 (3~64) winsize 62
5124 11:41:09.999706
5125 11:41:10.003098 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5126 11:41:10.003181
5127 11:41:10.006300 [CATrainingPosCal] consider 1 rank data
5128 11:41:10.009586 u2DelayCellTimex100 = 270/100 ps
5129 11:41:10.012786 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5130 11:41:10.016451 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5131 11:41:10.019390 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5132 11:41:10.022834 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5133 11:41:10.029338 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5134 11:41:10.032550 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5135 11:41:10.032632
5136 11:41:10.035774 CA PerBit enable=1, Macro0, CA PI delay=33
5137 11:41:10.035856
5138 11:41:10.039262 [CBTSetCACLKResult] CA Dly = 33
5139 11:41:10.039344 CS Dly: 7 (0~38)
5140 11:41:10.039409 ==
5141 11:41:10.042673 Dram Type= 6, Freq= 0, CH_0, rank 1
5142 11:41:10.049310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 11:41:10.049395 ==
5144 11:41:10.052372 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5145 11:41:10.059047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5146 11:41:10.062391 [CA 0] Center 38 (8~69) winsize 62
5147 11:41:10.065674 [CA 1] Center 38 (8~69) winsize 62
5148 11:41:10.068880 [CA 2] Center 36 (6~66) winsize 61
5149 11:41:10.072395 [CA 3] Center 35 (5~66) winsize 62
5150 11:41:10.075423 [CA 4] Center 35 (5~65) winsize 61
5151 11:41:10.078776 [CA 5] Center 34 (4~64) winsize 61
5152 11:41:10.078859
5153 11:41:10.081966 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5154 11:41:10.082047
5155 11:41:10.085468 [CATrainingPosCal] consider 2 rank data
5156 11:41:10.088803 u2DelayCellTimex100 = 270/100 ps
5157 11:41:10.091992 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5158 11:41:10.098864 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5159 11:41:10.101962 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5160 11:41:10.105509 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5161 11:41:10.108994 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5162 11:41:10.111679 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5163 11:41:10.111760
5164 11:41:10.115371 CA PerBit enable=1, Macro0, CA PI delay=34
5165 11:41:10.115453
5166 11:41:10.118579 [CBTSetCACLKResult] CA Dly = 34
5167 11:41:10.121886 CS Dly: 7 (0~39)
5168 11:41:10.121968
5169 11:41:10.125094 ----->DramcWriteLeveling(PI) begin...
5170 11:41:10.125177 ==
5171 11:41:10.128531 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 11:41:10.131394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 11:41:10.131480 ==
5174 11:41:10.134910 Write leveling (Byte 0): 34 => 34
5175 11:41:10.138127 Write leveling (Byte 1): 28 => 28
5176 11:41:10.141586 DramcWriteLeveling(PI) end<-----
5177 11:41:10.141669
5178 11:41:10.141734 ==
5179 11:41:10.144901 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 11:41:10.148048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 11:41:10.148131 ==
5182 11:41:10.151924 [Gating] SW mode calibration
5183 11:41:10.158143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5184 11:41:10.164508 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5185 11:41:10.167963 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
5186 11:41:10.171145 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 11:41:10.177626 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 11:41:10.181286 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 11:41:10.184567 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 11:41:10.191203 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 11:41:10.194374 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5192 11:41:10.198096 0 14 28 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
5193 11:41:10.204193 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5194 11:41:10.207560 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 11:41:10.210753 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 11:41:10.217486 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 11:41:10.220788 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 11:41:10.224638 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 11:41:10.230557 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5200 11:41:10.233757 0 15 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
5201 11:41:10.237108 1 0 0 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5202 11:41:10.243899 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 11:41:10.247424 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 11:41:10.250501 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 11:41:10.256932 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 11:41:10.260335 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 11:41:10.263813 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5208 11:41:10.270278 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5209 11:41:10.273622 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5210 11:41:10.276804 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:41:10.283313 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:41:10.286776 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:41:10.289911 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:41:10.296754 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:41:10.300245 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:41:10.303298 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:41:10.310114 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:41:10.313254 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:41:10.316504 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:41:10.323075 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:41:10.326365 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:41:10.329890 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:41:10.336130 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5224 11:41:10.339616 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5225 11:41:10.343131 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5226 11:41:10.345917 Total UI for P1: 0, mck2ui 16
5227 11:41:10.349286 best dqsien dly found for B0: ( 1, 2, 26)
5228 11:41:10.355994 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 11:41:10.356090 Total UI for P1: 0, mck2ui 16
5230 11:41:10.362286 best dqsien dly found for B1: ( 1, 2, 30)
5231 11:41:10.365701 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5232 11:41:10.369157 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5233 11:41:10.369238
5234 11:41:10.372281 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5235 11:41:10.376055 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5236 11:41:10.379132 [Gating] SW calibration Done
5237 11:41:10.379215 ==
5238 11:41:10.382298 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 11:41:10.385614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 11:41:10.385696 ==
5241 11:41:10.388969 RX Vref Scan: 0
5242 11:41:10.389085
5243 11:41:10.389149 RX Vref 0 -> 0, step: 1
5244 11:41:10.392071
5245 11:41:10.392152 RX Delay -80 -> 252, step: 8
5246 11:41:10.399273 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5247 11:41:10.402158 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5248 11:41:10.405696 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5249 11:41:10.408630 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5250 11:41:10.412013 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5251 11:41:10.415450 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5252 11:41:10.421968 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5253 11:41:10.425297 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5254 11:41:10.428517 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5255 11:41:10.431685 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5256 11:41:10.435133 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5257 11:41:10.441947 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5258 11:41:10.444924 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5259 11:41:10.448208 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5260 11:41:10.451385 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5261 11:41:10.454516 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5262 11:41:10.454597 ==
5263 11:41:10.457873 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 11:41:10.464475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 11:41:10.464561 ==
5266 11:41:10.464627 DQS Delay:
5267 11:41:10.467696 DQS0 = 0, DQS1 = 0
5268 11:41:10.467777 DQM Delay:
5269 11:41:10.471173 DQM0 = 106, DQM1 = 90
5270 11:41:10.471255 DQ Delay:
5271 11:41:10.474475 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5272 11:41:10.477476 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5273 11:41:10.480998 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5274 11:41:10.484437 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5275 11:41:10.484519
5276 11:41:10.484584
5277 11:41:10.484649 ==
5278 11:41:10.487285 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 11:41:10.490753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 11:41:10.494109 ==
5281 11:41:10.494190
5282 11:41:10.494253
5283 11:41:10.494312 TX Vref Scan disable
5284 11:41:10.497438 == TX Byte 0 ==
5285 11:41:10.500744 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5286 11:41:10.504054 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5287 11:41:10.507435 == TX Byte 1 ==
5288 11:41:10.510450 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5289 11:41:10.513693 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5290 11:41:10.517126 ==
5291 11:41:10.517207 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 11:41:10.523902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 11:41:10.523985 ==
5294 11:41:10.524050
5295 11:41:10.524109
5296 11:41:10.526916 TX Vref Scan disable
5297 11:41:10.526997 == TX Byte 0 ==
5298 11:41:10.533689 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5299 11:41:10.536784 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5300 11:41:10.536894 == TX Byte 1 ==
5301 11:41:10.543757 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5302 11:41:10.546712 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5303 11:41:10.546824
5304 11:41:10.546891 [DATLAT]
5305 11:41:10.550060 Freq=933, CH0 RK0
5306 11:41:10.550142
5307 11:41:10.550206 DATLAT Default: 0xd
5308 11:41:10.553135 0, 0xFFFF, sum = 0
5309 11:41:10.553218 1, 0xFFFF, sum = 0
5310 11:41:10.556453 2, 0xFFFF, sum = 0
5311 11:41:10.556567 3, 0xFFFF, sum = 0
5312 11:41:10.560050 4, 0xFFFF, sum = 0
5313 11:41:10.563396 5, 0xFFFF, sum = 0
5314 11:41:10.563479 6, 0xFFFF, sum = 0
5315 11:41:10.566662 7, 0xFFFF, sum = 0
5316 11:41:10.566744 8, 0xFFFF, sum = 0
5317 11:41:10.569787 9, 0xFFFF, sum = 0
5318 11:41:10.569869 10, 0x0, sum = 1
5319 11:41:10.573141 11, 0x0, sum = 2
5320 11:41:10.573249 12, 0x0, sum = 3
5321 11:41:10.573317 13, 0x0, sum = 4
5322 11:41:10.576628 best_step = 11
5323 11:41:10.576709
5324 11:41:10.576772 ==
5325 11:41:10.580378 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 11:41:10.583251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 11:41:10.583333 ==
5328 11:41:10.586353 RX Vref Scan: 1
5329 11:41:10.586434
5330 11:41:10.589759 RX Vref 0 -> 0, step: 1
5331 11:41:10.589839
5332 11:41:10.589903 RX Delay -53 -> 252, step: 4
5333 11:41:10.589963
5334 11:41:10.592944 Set Vref, RX VrefLevel [Byte0]: 61
5335 11:41:10.596315 [Byte1]: 51
5336 11:41:10.600795
5337 11:41:10.600875 Final RX Vref Byte 0 = 61 to rank0
5338 11:41:10.604066 Final RX Vref Byte 1 = 51 to rank0
5339 11:41:10.607559 Final RX Vref Byte 0 = 61 to rank1
5340 11:41:10.610652 Final RX Vref Byte 1 = 51 to rank1==
5341 11:41:10.613877 Dram Type= 6, Freq= 0, CH_0, rank 0
5342 11:41:10.620333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 11:41:10.620414 ==
5344 11:41:10.620478 DQS Delay:
5345 11:41:10.623903 DQS0 = 0, DQS1 = 0
5346 11:41:10.623985 DQM Delay:
5347 11:41:10.626924 DQM0 = 107, DQM1 = 92
5348 11:41:10.627005 DQ Delay:
5349 11:41:10.630487 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5350 11:41:10.633762 DQ4 =108, DQ5 =100, DQ6 =118, DQ7 =114
5351 11:41:10.636902 DQ8 =88, DQ9 =76, DQ10 =94, DQ11 =90
5352 11:41:10.640318 DQ12 =98, DQ13 =92, DQ14 =102, DQ15 =100
5353 11:41:10.640399
5354 11:41:10.640462
5355 11:41:10.647198 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5356 11:41:10.650131 CH0 RK0: MR19=505, MR18=231F
5357 11:41:10.656728 CH0_RK0: MR19=0x505, MR18=0x231F, DQSOSC=410, MR23=63, INC=64, DEC=42
5358 11:41:10.656840
5359 11:41:10.660741 ----->DramcWriteLeveling(PI) begin...
5360 11:41:10.660821 ==
5361 11:41:10.663299 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 11:41:10.670034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 11:41:10.670114 ==
5364 11:41:10.673179 Write leveling (Byte 0): 31 => 31
5365 11:41:10.673282 Write leveling (Byte 1): 27 => 27
5366 11:41:10.676494 DramcWriteLeveling(PI) end<-----
5367 11:41:10.676573
5368 11:41:10.680078 ==
5369 11:41:10.680158 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 11:41:10.686238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 11:41:10.686318 ==
5372 11:41:10.689642 [Gating] SW mode calibration
5373 11:41:10.696364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5374 11:41:10.699868 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5375 11:41:10.706246 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 11:41:10.709880 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 11:41:10.712753 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 11:41:10.719213 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 11:41:10.722577 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 11:41:10.725965 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 11:41:10.732861 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5382 11:41:10.735929 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5383 11:41:10.739094 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 11:41:10.745601 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 11:41:10.749330 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 11:41:10.752555 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 11:41:10.759335 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 11:41:10.762100 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 11:41:10.765829 0 15 24 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
5390 11:41:10.771983 0 15 28 | B1->B0 | 3939 4343 | 1 0 | (0 0) (0 0)
5391 11:41:10.775227 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 11:41:10.778613 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 11:41:10.785338 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 11:41:10.788668 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 11:41:10.792066 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 11:41:10.798367 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 11:41:10.801822 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 11:41:10.805204 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5399 11:41:10.811878 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:41:10.815069 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:41:10.818150 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:41:10.824851 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:41:10.827957 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:41:10.831460 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:41:10.837981 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:41:10.841346 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:41:10.844642 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:41:10.851543 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:41:10.854616 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:41:10.857799 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:41:10.864293 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:41:10.868131 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:41:10.871337 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 11:41:10.877683 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5415 11:41:10.877764 Total UI for P1: 0, mck2ui 16
5416 11:41:10.884272 best dqsien dly found for B0: ( 1, 2, 26)
5417 11:41:10.887818 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 11:41:10.891280 Total UI for P1: 0, mck2ui 16
5419 11:41:10.894521 best dqsien dly found for B1: ( 1, 2, 28)
5420 11:41:10.897761 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5421 11:41:10.900958 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5422 11:41:10.901114
5423 11:41:10.904517 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5424 11:41:10.907666 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5425 11:41:10.910628 [Gating] SW calibration Done
5426 11:41:10.910723 ==
5427 11:41:10.914011 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 11:41:10.917830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 11:41:10.920452 ==
5430 11:41:10.920532 RX Vref Scan: 0
5431 11:41:10.920596
5432 11:41:10.924317 RX Vref 0 -> 0, step: 1
5433 11:41:10.924412
5434 11:41:10.927096 RX Delay -80 -> 252, step: 8
5435 11:41:10.930579 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5436 11:41:10.933869 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5437 11:41:10.937429 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5438 11:41:10.940656 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5439 11:41:10.946981 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5440 11:41:10.950243 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5441 11:41:10.953610 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5442 11:41:10.956891 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5443 11:41:10.960385 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5444 11:41:10.963645 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5445 11:41:10.970441 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5446 11:41:10.973538 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5447 11:41:10.976781 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5448 11:41:10.980225 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5449 11:41:10.983523 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5450 11:41:10.986815 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5451 11:41:10.990053 ==
5452 11:41:10.990190 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 11:41:10.996873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 11:41:10.997072 ==
5455 11:41:10.997159 DQS Delay:
5456 11:41:10.999838 DQS0 = 0, DQS1 = 0
5457 11:41:10.999943 DQM Delay:
5458 11:41:11.003584 DQM0 = 104, DQM1 = 92
5459 11:41:11.003744 DQ Delay:
5460 11:41:11.007003 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5461 11:41:11.010059 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5462 11:41:11.012942 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =87
5463 11:41:11.016572 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5464 11:41:11.016659
5465 11:41:11.016727
5466 11:41:11.016791 ==
5467 11:41:11.019803 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 11:41:11.022884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 11:41:11.023032 ==
5470 11:41:11.026823
5471 11:41:11.027009
5472 11:41:11.027138 TX Vref Scan disable
5473 11:41:11.029912 == TX Byte 0 ==
5474 11:41:11.033118 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5475 11:41:11.036425 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5476 11:41:11.039935 == TX Byte 1 ==
5477 11:41:11.043338 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5478 11:41:11.046577 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5479 11:41:11.046811 ==
5480 11:41:11.049556 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 11:41:11.056285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 11:41:11.056572 ==
5483 11:41:11.056742
5484 11:41:11.056897
5485 11:41:11.059504 TX Vref Scan disable
5486 11:41:11.059743 == TX Byte 0 ==
5487 11:41:11.066749 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5488 11:41:11.069684 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5489 11:41:11.070070 == TX Byte 1 ==
5490 11:41:11.076071 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5491 11:41:11.079362 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5492 11:41:11.079970
5493 11:41:11.080554 [DATLAT]
5494 11:41:11.082649 Freq=933, CH0 RK1
5495 11:41:11.083029
5496 11:41:11.083386 DATLAT Default: 0xb
5497 11:41:11.085979 0, 0xFFFF, sum = 0
5498 11:41:11.086063 1, 0xFFFF, sum = 0
5499 11:41:11.089064 2, 0xFFFF, sum = 0
5500 11:41:11.089236 3, 0xFFFF, sum = 0
5501 11:41:11.092435 4, 0xFFFF, sum = 0
5502 11:41:11.092611 5, 0xFFFF, sum = 0
5503 11:41:11.095924 6, 0xFFFF, sum = 0
5504 11:41:11.096101 7, 0xFFFF, sum = 0
5505 11:41:11.098950 8, 0xFFFF, sum = 0
5506 11:41:11.102307 9, 0xFFFF, sum = 0
5507 11:41:11.102493 10, 0x0, sum = 1
5508 11:41:11.102581 11, 0x0, sum = 2
5509 11:41:11.105622 12, 0x0, sum = 3
5510 11:41:11.105833 13, 0x0, sum = 4
5511 11:41:11.108937 best_step = 11
5512 11:41:11.109142
5513 11:41:11.109208 ==
5514 11:41:11.112079 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 11:41:11.115533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 11:41:11.115701 ==
5517 11:41:11.118852 RX Vref Scan: 0
5518 11:41:11.118948
5519 11:41:11.119013 RX Vref 0 -> 0, step: 1
5520 11:41:11.119074
5521 11:41:11.122116 RX Delay -45 -> 252, step: 4
5522 11:41:11.129646 iDelay=203, Bit 0, Center 104 (15 ~ 194) 180
5523 11:41:11.132646 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5524 11:41:11.136085 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5525 11:41:11.139396 iDelay=203, Bit 3, Center 98 (11 ~ 186) 176
5526 11:41:11.142454 iDelay=203, Bit 4, Center 106 (19 ~ 194) 176
5527 11:41:11.149365 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5528 11:41:11.152327 iDelay=203, Bit 6, Center 116 (31 ~ 202) 172
5529 11:41:11.155585 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5530 11:41:11.159522 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5531 11:41:11.162195 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5532 11:41:11.168821 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5533 11:41:11.172014 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5534 11:41:11.175421 iDelay=203, Bit 12, Center 100 (15 ~ 186) 172
5535 11:41:11.178911 iDelay=203, Bit 13, Center 96 (15 ~ 178) 164
5536 11:41:11.182056 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5537 11:41:11.188650 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5538 11:41:11.188760 ==
5539 11:41:11.191878 Dram Type= 6, Freq= 0, CH_0, rank 1
5540 11:41:11.195384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 11:41:11.195467 ==
5542 11:41:11.195531 DQS Delay:
5543 11:41:11.198959 DQS0 = 0, DQS1 = 0
5544 11:41:11.199040 DQM Delay:
5545 11:41:11.201744 DQM0 = 105, DQM1 = 93
5546 11:41:11.201841 DQ Delay:
5547 11:41:11.204962 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5548 11:41:11.208352 DQ4 =106, DQ5 =96, DQ6 =116, DQ7 =112
5549 11:41:11.211486 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5550 11:41:11.214759 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =98
5551 11:41:11.214867
5552 11:41:11.214931
5553 11:41:11.224963 [DQSOSCAuto] RK1, (LSB)MR18= 0x290b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5554 11:41:11.228485 CH0 RK1: MR19=505, MR18=290B
5555 11:41:11.234738 CH0_RK1: MR19=0x505, MR18=0x290B, DQSOSC=408, MR23=63, INC=65, DEC=43
5556 11:41:11.234875 [RxdqsGatingPostProcess] freq 933
5557 11:41:11.241309 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5558 11:41:11.244676 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 11:41:11.248070 best DQS1 dly(2T, 0.5T) = (0, 10)
5560 11:41:11.251316 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 11:41:11.254842 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5562 11:41:11.258644 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 11:41:11.261301 best DQS1 dly(2T, 0.5T) = (0, 10)
5564 11:41:11.264510 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 11:41:11.268101 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5566 11:41:11.271125 Pre-setting of DQS Precalculation
5567 11:41:11.274486 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5568 11:41:11.274847 ==
5569 11:41:11.277979 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 11:41:11.281377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 11:41:11.284722 ==
5572 11:41:11.287861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 11:41:11.294312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5574 11:41:11.297907 [CA 0] Center 37 (7~68) winsize 62
5575 11:41:11.301408 [CA 1] Center 37 (7~68) winsize 62
5576 11:41:11.304448 [CA 2] Center 35 (5~66) winsize 62
5577 11:41:11.307751 [CA 3] Center 34 (4~65) winsize 62
5578 11:41:11.311009 [CA 4] Center 34 (4~65) winsize 62
5579 11:41:11.314482 [CA 5] Center 34 (4~64) winsize 61
5580 11:41:11.314801
5581 11:41:11.317455 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5582 11:41:11.317816
5583 11:41:11.320589 [CATrainingPosCal] consider 1 rank data
5584 11:41:11.323870 u2DelayCellTimex100 = 270/100 ps
5585 11:41:11.327477 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5586 11:41:11.331505 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5587 11:41:11.333926 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5588 11:41:11.340381 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5589 11:41:11.343706 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5590 11:41:11.347314 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5591 11:41:11.347417
5592 11:41:11.350606 CA PerBit enable=1, Macro0, CA PI delay=34
5593 11:41:11.350711
5594 11:41:11.353928 [CBTSetCACLKResult] CA Dly = 34
5595 11:41:11.354023 CS Dly: 7 (0~38)
5596 11:41:11.354097 ==
5597 11:41:11.356909 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 11:41:11.363666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 11:41:11.363749 ==
5600 11:41:11.366952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 11:41:11.373577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5602 11:41:11.376837 [CA 0] Center 37 (7~68) winsize 62
5603 11:41:11.380093 [CA 1] Center 38 (8~69) winsize 62
5604 11:41:11.383344 [CA 2] Center 36 (6~66) winsize 61
5605 11:41:11.386729 [CA 3] Center 35 (6~65) winsize 60
5606 11:41:11.389863 [CA 4] Center 35 (5~65) winsize 61
5607 11:41:11.393545 [CA 5] Center 35 (5~65) winsize 61
5608 11:41:11.393627
5609 11:41:11.396465 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5610 11:41:11.396546
5611 11:41:11.400307 [CATrainingPosCal] consider 2 rank data
5612 11:41:11.403367 u2DelayCellTimex100 = 270/100 ps
5613 11:41:11.406651 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5614 11:41:11.412917 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5615 11:41:11.416522 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5616 11:41:11.419865 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5617 11:41:11.422902 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5618 11:41:11.426170 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5619 11:41:11.426251
5620 11:41:11.429397 CA PerBit enable=1, Macro0, CA PI delay=34
5621 11:41:11.429479
5622 11:41:11.432881 [CBTSetCACLKResult] CA Dly = 34
5623 11:41:11.436047 CS Dly: 7 (0~39)
5624 11:41:11.436128
5625 11:41:11.439380 ----->DramcWriteLeveling(PI) begin...
5626 11:41:11.439463 ==
5627 11:41:11.442723 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 11:41:11.445980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 11:41:11.446063 ==
5630 11:41:11.449360 Write leveling (Byte 0): 24 => 24
5631 11:41:11.452685 Write leveling (Byte 1): 28 => 28
5632 11:41:11.455779 DramcWriteLeveling(PI) end<-----
5633 11:41:11.455860
5634 11:41:11.455924 ==
5635 11:41:11.459861 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 11:41:11.462521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 11:41:11.462603 ==
5638 11:41:11.465854 [Gating] SW mode calibration
5639 11:41:11.472391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5640 11:41:11.478893 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5641 11:41:11.482257 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 11:41:11.488594 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 11:41:11.492297 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 11:41:11.495496 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 11:41:11.498840 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 11:41:11.505202 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 11:41:11.508536 0 14 24 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
5648 11:41:11.515166 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5649 11:41:11.518831 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 11:41:11.521864 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 11:41:11.525200 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 11:41:11.531844 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 11:41:11.535316 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 11:41:11.538660 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 11:41:11.544759 0 15 24 | B1->B0 | 2929 2d2d | 0 0 | (1 1) (0 0)
5656 11:41:11.548211 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5657 11:41:11.551380 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 11:41:11.558317 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 11:41:11.561416 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 11:41:11.564982 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 11:41:11.571545 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 11:41:11.574782 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5663 11:41:11.577825 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5664 11:41:11.584660 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5665 11:41:11.587951 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:41:11.591459 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:41:11.597927 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:41:11.601776 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:41:11.604892 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:41:11.611113 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:41:11.614341 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:41:11.617946 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:41:11.624654 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:41:11.627660 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:41:11.631398 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:41:11.637999 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:41:11.641013 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:41:11.644313 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:41:11.650652 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5680 11:41:11.650734 Total UI for P1: 0, mck2ui 16
5681 11:41:11.657488 best dqsien dly found for B0: ( 1, 2, 22)
5682 11:41:11.660791 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 11:41:11.664292 Total UI for P1: 0, mck2ui 16
5684 11:41:11.667104 best dqsien dly found for B1: ( 1, 2, 24)
5685 11:41:11.670367 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5686 11:41:11.673845 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5687 11:41:11.673927
5688 11:41:11.676944 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5689 11:41:11.680350 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5690 11:41:11.684084 [Gating] SW calibration Done
5691 11:41:11.684167 ==
5692 11:41:11.687555 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 11:41:11.693407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 11:41:11.693488 ==
5695 11:41:11.693551 RX Vref Scan: 0
5696 11:41:11.693609
5697 11:41:11.697125 RX Vref 0 -> 0, step: 1
5698 11:41:11.697205
5699 11:41:11.700138 RX Delay -80 -> 252, step: 8
5700 11:41:11.703389 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5701 11:41:11.706709 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5702 11:41:11.710447 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5703 11:41:11.713106 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5704 11:41:11.719670 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5705 11:41:11.723282 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5706 11:41:11.726632 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5707 11:41:11.730103 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5708 11:41:11.732992 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5709 11:41:11.739822 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5710 11:41:11.743280 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5711 11:41:11.746285 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5712 11:41:11.749553 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5713 11:41:11.752894 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5714 11:41:11.756203 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5715 11:41:11.762750 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5716 11:41:11.762831 ==
5717 11:41:11.766311 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 11:41:11.769485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 11:41:11.769566 ==
5720 11:41:11.769629 DQS Delay:
5721 11:41:11.772706 DQS0 = 0, DQS1 = 0
5722 11:41:11.772830 DQM Delay:
5723 11:41:11.775907 DQM0 = 103, DQM1 = 95
5724 11:41:11.775987 DQ Delay:
5725 11:41:11.779349 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =103
5726 11:41:11.782764 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =99
5727 11:41:11.786039 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5728 11:41:11.788887 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5729 11:41:11.788968
5730 11:41:11.789083
5731 11:41:11.792795 ==
5732 11:41:11.792875 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 11:41:11.798856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 11:41:11.798936 ==
5735 11:41:11.798999
5736 11:41:11.799057
5737 11:41:11.802291 TX Vref Scan disable
5738 11:41:11.802372 == TX Byte 0 ==
5739 11:41:11.805470 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5740 11:41:11.812091 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5741 11:41:11.812171 == TX Byte 1 ==
5742 11:41:11.815230 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5743 11:41:11.822345 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5744 11:41:11.822426 ==
5745 11:41:11.825291 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 11:41:11.828768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 11:41:11.828849 ==
5748 11:41:11.828911
5749 11:41:11.828970
5750 11:41:11.832053 TX Vref Scan disable
5751 11:41:11.835433 == TX Byte 0 ==
5752 11:41:11.838381 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5753 11:41:11.841952 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5754 11:41:11.845040 == TX Byte 1 ==
5755 11:41:11.848260 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5756 11:41:11.851567 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5757 11:41:11.851651
5758 11:41:11.854761 [DATLAT]
5759 11:41:11.854844 Freq=933, CH1 RK0
5760 11:41:11.854928
5761 11:41:11.858266 DATLAT Default: 0xd
5762 11:41:11.858350 0, 0xFFFF, sum = 0
5763 11:41:11.862013 1, 0xFFFF, sum = 0
5764 11:41:11.862099 2, 0xFFFF, sum = 0
5765 11:41:11.864841 3, 0xFFFF, sum = 0
5766 11:41:11.864925 4, 0xFFFF, sum = 0
5767 11:41:11.868092 5, 0xFFFF, sum = 0
5768 11:41:11.868177 6, 0xFFFF, sum = 0
5769 11:41:11.871369 7, 0xFFFF, sum = 0
5770 11:41:11.871453 8, 0xFFFF, sum = 0
5771 11:41:11.874790 9, 0xFFFF, sum = 0
5772 11:41:11.874874 10, 0x0, sum = 1
5773 11:41:11.878567 11, 0x0, sum = 2
5774 11:41:11.878651 12, 0x0, sum = 3
5775 11:41:11.881297 13, 0x0, sum = 4
5776 11:41:11.881382 best_step = 11
5777 11:41:11.881466
5778 11:41:11.881544 ==
5779 11:41:11.884822 Dram Type= 6, Freq= 0, CH_1, rank 0
5780 11:41:11.891393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 11:41:11.891479 ==
5782 11:41:11.891565 RX Vref Scan: 1
5783 11:41:11.891646
5784 11:41:11.894755 RX Vref 0 -> 0, step: 1
5785 11:41:11.894840
5786 11:41:11.897965 RX Delay -53 -> 252, step: 4
5787 11:41:11.898051
5788 11:41:11.901498 Set Vref, RX VrefLevel [Byte0]: 52
5789 11:41:11.904651 [Byte1]: 54
5790 11:41:11.904764
5791 11:41:11.908048 Final RX Vref Byte 0 = 52 to rank0
5792 11:41:11.911317 Final RX Vref Byte 1 = 54 to rank0
5793 11:41:11.914734 Final RX Vref Byte 0 = 52 to rank1
5794 11:41:11.917865 Final RX Vref Byte 1 = 54 to rank1==
5795 11:41:11.921126 Dram Type= 6, Freq= 0, CH_1, rank 0
5796 11:41:11.924721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 11:41:11.924806 ==
5798 11:41:11.927702 DQS Delay:
5799 11:41:11.927778 DQS0 = 0, DQS1 = 0
5800 11:41:11.927859 DQM Delay:
5801 11:41:11.931307 DQM0 = 104, DQM1 = 97
5802 11:41:11.931392 DQ Delay:
5803 11:41:11.934411 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5804 11:41:11.937862 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102
5805 11:41:11.940939 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =92
5806 11:41:11.947690 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =104
5807 11:41:11.947775
5808 11:41:11.947860
5809 11:41:11.954500 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5810 11:41:11.957325 CH1 RK0: MR19=505, MR18=1830
5811 11:41:11.964178 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5812 11:41:11.964263
5813 11:41:11.967514 ----->DramcWriteLeveling(PI) begin...
5814 11:41:11.967601 ==
5815 11:41:11.970931 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 11:41:11.973976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 11:41:11.974061 ==
5818 11:41:11.977658 Write leveling (Byte 0): 27 => 27
5819 11:41:11.980864 Write leveling (Byte 1): 28 => 28
5820 11:41:11.983942 DramcWriteLeveling(PI) end<-----
5821 11:41:11.984028
5822 11:41:11.984113 ==
5823 11:41:11.987434 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 11:41:11.990336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 11:41:11.990422 ==
5826 11:41:11.994215 [Gating] SW mode calibration
5827 11:41:12.000203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5828 11:41:12.007273 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5829 11:41:12.010515 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 11:41:12.017006 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 11:41:12.020164 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 11:41:12.023659 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 11:41:12.030464 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 11:41:12.033400 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 11:41:12.037078 0 14 24 | B1->B0 | 3131 3434 | 1 0 | (1 0) (0 0)
5836 11:41:12.043326 0 14 28 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
5837 11:41:12.046716 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5838 11:41:12.049882 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 11:41:12.056588 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 11:41:12.060050 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 11:41:12.063378 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 11:41:12.069908 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 11:41:12.073286 0 15 24 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
5844 11:41:12.076620 0 15 28 | B1->B0 | 4040 3b3b | 0 0 | (0 0) (0 0)
5845 11:41:12.083004 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5846 11:41:12.086587 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 11:41:12.089482 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 11:41:12.096025 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 11:41:12.099318 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 11:41:12.102894 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 11:41:12.109301 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 11:41:12.112953 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5853 11:41:12.116081 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:41:12.122509 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:41:12.125958 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:41:12.129349 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:41:12.135914 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:41:12.139015 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:41:12.142276 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:41:12.148823 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:41:12.152372 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:41:12.155879 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:41:12.162417 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:41:12.165928 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:41:12.169205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:41:12.175379 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:41:12.178879 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5868 11:41:12.182223 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5869 11:41:12.189125 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 11:41:12.189206 Total UI for P1: 0, mck2ui 16
5871 11:41:12.192037 best dqsien dly found for B0: ( 1, 2, 26)
5872 11:41:12.195225 Total UI for P1: 0, mck2ui 16
5873 11:41:12.198478 best dqsien dly found for B1: ( 1, 2, 26)
5874 11:41:12.201739 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5875 11:41:12.208666 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5876 11:41:12.208746
5877 11:41:12.211734 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5878 11:41:12.215129 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5879 11:41:12.218397 [Gating] SW calibration Done
5880 11:41:12.218476 ==
5881 11:41:12.221804 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 11:41:12.225172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 11:41:12.225252 ==
5884 11:41:12.228221 RX Vref Scan: 0
5885 11:41:12.228301
5886 11:41:12.228363 RX Vref 0 -> 0, step: 1
5887 11:41:12.228421
5888 11:41:12.231462 RX Delay -80 -> 252, step: 8
5889 11:41:12.235063 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5890 11:41:12.241459 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5891 11:41:12.244827 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5892 11:41:12.248074 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5893 11:41:12.251310 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5894 11:41:12.254894 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5895 11:41:12.257895 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5896 11:41:12.264921 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5897 11:41:12.268209 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5898 11:41:12.271434 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5899 11:41:12.274516 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5900 11:41:12.278079 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5901 11:41:12.281175 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5902 11:41:12.287770 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5903 11:41:12.291026 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5904 11:41:12.294236 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5905 11:41:12.294317 ==
5906 11:41:12.297670 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 11:41:12.300910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 11:41:12.301031 ==
5909 11:41:12.304283 DQS Delay:
5910 11:41:12.304363 DQS0 = 0, DQS1 = 0
5911 11:41:12.307794 DQM Delay:
5912 11:41:12.307875 DQM0 = 101, DQM1 = 95
5913 11:41:12.307939 DQ Delay:
5914 11:41:12.311025 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5915 11:41:12.314318 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5916 11:41:12.317700 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5917 11:41:12.324262 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5918 11:41:12.324370
5919 11:41:12.324471
5920 11:41:12.324571 ==
5921 11:41:12.327842 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 11:41:12.331108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 11:41:12.331239 ==
5924 11:41:12.331348
5925 11:41:12.331459
5926 11:41:12.334439 TX Vref Scan disable
5927 11:41:12.334533 == TX Byte 0 ==
5928 11:41:12.341134 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5929 11:41:12.344180 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5930 11:41:12.344271 == TX Byte 1 ==
5931 11:41:12.350850 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5932 11:41:12.354239 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5933 11:41:12.354400 ==
5934 11:41:12.357394 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 11:41:12.360726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 11:41:12.360809 ==
5937 11:41:12.364117
5938 11:41:12.364273
5939 11:41:12.364347 TX Vref Scan disable
5940 11:41:12.367667 == TX Byte 0 ==
5941 11:41:12.370699 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5942 11:41:12.377204 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5943 11:41:12.377383 == TX Byte 1 ==
5944 11:41:12.380615 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5945 11:41:12.387262 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5946 11:41:12.387465
5947 11:41:12.387581 [DATLAT]
5948 11:41:12.387684 Freq=933, CH1 RK1
5949 11:41:12.387783
5950 11:41:12.390696 DATLAT Default: 0xb
5951 11:41:12.390894 0, 0xFFFF, sum = 0
5952 11:41:12.393805 1, 0xFFFF, sum = 0
5953 11:41:12.397162 2, 0xFFFF, sum = 0
5954 11:41:12.397397 3, 0xFFFF, sum = 0
5955 11:41:12.400903 4, 0xFFFF, sum = 0
5956 11:41:12.401160 5, 0xFFFF, sum = 0
5957 11:41:12.403748 6, 0xFFFF, sum = 0
5958 11:41:12.403928 7, 0xFFFF, sum = 0
5959 11:41:12.406838 8, 0xFFFF, sum = 0
5960 11:41:12.407029 9, 0xFFFF, sum = 0
5961 11:41:12.410511 10, 0x0, sum = 1
5962 11:41:12.410799 11, 0x0, sum = 2
5963 11:41:12.413947 12, 0x0, sum = 3
5964 11:41:12.414194 13, 0x0, sum = 4
5965 11:41:12.414430 best_step = 11
5966 11:41:12.414612
5967 11:41:12.417346 ==
5968 11:41:12.420504 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 11:41:12.424159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 11:41:12.424649 ==
5971 11:41:12.424956 RX Vref Scan: 0
5972 11:41:12.425271
5973 11:41:12.427517 RX Vref 0 -> 0, step: 1
5974 11:41:12.428030
5975 11:41:12.430659 RX Delay -53 -> 252, step: 4
5976 11:41:12.437356 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5977 11:41:12.440409 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5978 11:41:12.444114 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5979 11:41:12.447591 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5980 11:41:12.450607 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5981 11:41:12.453733 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5982 11:41:12.460719 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5983 11:41:12.464020 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5984 11:41:12.467075 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5985 11:41:12.470429 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5986 11:41:12.473610 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5987 11:41:12.477102 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5988 11:41:12.483773 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5989 11:41:12.486951 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5990 11:41:12.490394 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5991 11:41:12.493324 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5992 11:41:12.493741 ==
5993 11:41:12.497190 Dram Type= 6, Freq= 0, CH_1, rank 1
5994 11:41:12.503585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5995 11:41:12.504121 ==
5996 11:41:12.504473 DQS Delay:
5997 11:41:12.507138 DQS0 = 0, DQS1 = 0
5998 11:41:12.507650 DQM Delay:
5999 11:41:12.510273 DQM0 = 104, DQM1 = 97
6000 11:41:12.510796 DQ Delay:
6001 11:41:12.513129 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
6002 11:41:12.516576 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
6003 11:41:12.520113 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
6004 11:41:12.523076 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =106
6005 11:41:12.523493
6006 11:41:12.523820
6007 11:41:12.533663 [DQSOSCAuto] RK1, (LSB)MR18= 0x2401, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
6008 11:41:12.534189 CH1 RK1: MR19=505, MR18=2401
6009 11:41:12.540003 CH1_RK1: MR19=0x505, MR18=0x2401, DQSOSC=410, MR23=63, INC=64, DEC=42
6010 11:41:12.543430 [RxdqsGatingPostProcess] freq 933
6011 11:41:12.549674 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6012 11:41:12.553138 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 11:41:12.556696 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 11:41:12.559929 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 11:41:12.563124 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 11:41:12.566055 best DQS0 dly(2T, 0.5T) = (0, 10)
6017 11:41:12.566477 best DQS1 dly(2T, 0.5T) = (0, 10)
6018 11:41:12.569384 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6019 11:41:12.572885 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6020 11:41:12.576216 Pre-setting of DQS Precalculation
6021 11:41:12.582492 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6022 11:41:12.589322 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6023 11:41:12.596201 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6024 11:41:12.596720
6025 11:41:12.597097
6026 11:41:12.599164 [Calibration Summary] 1866 Mbps
6027 11:41:12.602889 CH 0, Rank 0
6028 11:41:12.603404 SW Impedance : PASS
6029 11:41:12.605651 DUTY Scan : NO K
6030 11:41:12.609536 ZQ Calibration : PASS
6031 11:41:12.610053 Jitter Meter : NO K
6032 11:41:12.612785 CBT Training : PASS
6033 11:41:12.613333 Write leveling : PASS
6034 11:41:12.615485 RX DQS gating : PASS
6035 11:41:12.619213 RX DQ/DQS(RDDQC) : PASS
6036 11:41:12.619728 TX DQ/DQS : PASS
6037 11:41:12.622245 RX DATLAT : PASS
6038 11:41:12.625605 RX DQ/DQS(Engine): PASS
6039 11:41:12.626134 TX OE : NO K
6040 11:41:12.628572 All Pass.
6041 11:41:12.629022
6042 11:41:12.629384 CH 0, Rank 1
6043 11:41:12.632486 SW Impedance : PASS
6044 11:41:12.633028 DUTY Scan : NO K
6045 11:41:12.635457 ZQ Calibration : PASS
6046 11:41:12.638678 Jitter Meter : NO K
6047 11:41:12.639144 CBT Training : PASS
6048 11:41:12.641820 Write leveling : PASS
6049 11:41:12.645504 RX DQS gating : PASS
6050 11:41:12.645993 RX DQ/DQS(RDDQC) : PASS
6051 11:41:12.648791 TX DQ/DQS : PASS
6052 11:41:12.651876 RX DATLAT : PASS
6053 11:41:12.652298 RX DQ/DQS(Engine): PASS
6054 11:41:12.655395 TX OE : NO K
6055 11:41:12.655917 All Pass.
6056 11:41:12.656246
6057 11:41:12.658538 CH 1, Rank 0
6058 11:41:12.659053 SW Impedance : PASS
6059 11:41:12.661780 DUTY Scan : NO K
6060 11:41:12.665088 ZQ Calibration : PASS
6061 11:41:12.665507 Jitter Meter : NO K
6062 11:41:12.668514 CBT Training : PASS
6063 11:41:12.671663 Write leveling : PASS
6064 11:41:12.672178 RX DQS gating : PASS
6065 11:41:12.675104 RX DQ/DQS(RDDQC) : PASS
6066 11:41:12.678231 TX DQ/DQS : PASS
6067 11:41:12.678650 RX DATLAT : PASS
6068 11:41:12.681840 RX DQ/DQS(Engine): PASS
6069 11:41:12.684961 TX OE : NO K
6070 11:41:12.685426 All Pass.
6071 11:41:12.685755
6072 11:41:12.686058 CH 1, Rank 1
6073 11:41:12.688070 SW Impedance : PASS
6074 11:41:12.691780 DUTY Scan : NO K
6075 11:41:12.692337 ZQ Calibration : PASS
6076 11:41:12.694893 Jitter Meter : NO K
6077 11:41:12.695405 CBT Training : PASS
6078 11:41:12.698348 Write leveling : PASS
6079 11:41:12.701506 RX DQS gating : PASS
6080 11:41:12.702024 RX DQ/DQS(RDDQC) : PASS
6081 11:41:12.704381 TX DQ/DQS : PASS
6082 11:41:12.708003 RX DATLAT : PASS
6083 11:41:12.708495 RX DQ/DQS(Engine): PASS
6084 11:41:12.711159 TX OE : NO K
6085 11:41:12.711576 All Pass.
6086 11:41:12.711899
6087 11:41:12.714530 DramC Write-DBI off
6088 11:41:12.717624 PER_BANK_REFRESH: Hybrid Mode
6089 11:41:12.718039 TX_TRACKING: ON
6090 11:41:12.727979 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6091 11:41:12.731287 [FAST_K] Save calibration result to emmc
6092 11:41:12.734391 dramc_set_vcore_voltage set vcore to 650000
6093 11:41:12.737527 Read voltage for 400, 6
6094 11:41:12.737946 Vio18 = 0
6095 11:41:12.740842 Vcore = 650000
6096 11:41:12.741286 Vdram = 0
6097 11:41:12.741617 Vddq = 0
6098 11:41:12.741956 Vmddr = 0
6099 11:41:12.747913 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6100 11:41:12.750725 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6101 11:41:12.754658 MEM_TYPE=3, freq_sel=20
6102 11:41:12.757291 sv_algorithm_assistance_LP4_800
6103 11:41:12.761050 ============ PULL DRAM RESETB DOWN ============
6104 11:41:12.767624 ========== PULL DRAM RESETB DOWN end =========
6105 11:41:12.770666 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6106 11:41:12.773773 ===================================
6107 11:41:12.777199 LPDDR4 DRAM CONFIGURATION
6108 11:41:12.780587 ===================================
6109 11:41:12.781131 EX_ROW_EN[0] = 0x0
6110 11:41:12.783683 EX_ROW_EN[1] = 0x0
6111 11:41:12.784237 LP4Y_EN = 0x0
6112 11:41:12.787262 WORK_FSP = 0x0
6113 11:41:12.787779 WL = 0x2
6114 11:41:12.790474 RL = 0x2
6115 11:41:12.793535 BL = 0x2
6116 11:41:12.794049 RPST = 0x0
6117 11:41:12.796940 RD_PRE = 0x0
6118 11:41:12.797393 WR_PRE = 0x1
6119 11:41:12.800638 WR_PST = 0x0
6120 11:41:12.801203 DBI_WR = 0x0
6121 11:41:12.803925 DBI_RD = 0x0
6122 11:41:12.804440 OTF = 0x1
6123 11:41:12.807184 ===================================
6124 11:41:12.810335 ===================================
6125 11:41:12.813397 ANA top config
6126 11:41:12.816648 ===================================
6127 11:41:12.817104 DLL_ASYNC_EN = 0
6128 11:41:12.820204 ALL_SLAVE_EN = 1
6129 11:41:12.823268 NEW_RANK_MODE = 1
6130 11:41:12.826482 DLL_IDLE_MODE = 1
6131 11:41:12.827007 LP45_APHY_COMB_EN = 1
6132 11:41:12.829695 TX_ODT_DIS = 1
6133 11:41:12.833686 NEW_8X_MODE = 1
6134 11:41:12.836595 ===================================
6135 11:41:12.840010 ===================================
6136 11:41:12.842853 data_rate = 800
6137 11:41:12.846648 CKR = 1
6138 11:41:12.849763 DQ_P2S_RATIO = 4
6139 11:41:12.853034 ===================================
6140 11:41:12.853453 CA_P2S_RATIO = 4
6141 11:41:12.856267 DQ_CA_OPEN = 0
6142 11:41:12.859906 DQ_SEMI_OPEN = 1
6143 11:41:12.862674 CA_SEMI_OPEN = 1
6144 11:41:12.866483 CA_FULL_RATE = 0
6145 11:41:12.869322 DQ_CKDIV4_EN = 0
6146 11:41:12.869749 CA_CKDIV4_EN = 1
6147 11:41:12.873185 CA_PREDIV_EN = 0
6148 11:41:12.876191 PH8_DLY = 0
6149 11:41:12.879645 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6150 11:41:12.882918 DQ_AAMCK_DIV = 0
6151 11:41:12.885980 CA_AAMCK_DIV = 0
6152 11:41:12.889338 CA_ADMCK_DIV = 4
6153 11:41:12.889764 DQ_TRACK_CA_EN = 0
6154 11:41:12.892646 CA_PICK = 800
6155 11:41:12.895950 CA_MCKIO = 400
6156 11:41:12.899362 MCKIO_SEMI = 400
6157 11:41:12.902311 PLL_FREQ = 3016
6158 11:41:12.905544 DQ_UI_PI_RATIO = 32
6159 11:41:12.909150 CA_UI_PI_RATIO = 32
6160 11:41:12.912589 ===================================
6161 11:41:12.915799 ===================================
6162 11:41:12.916222 memory_type:LPDDR4
6163 11:41:12.918828 GP_NUM : 10
6164 11:41:12.922155 SRAM_EN : 1
6165 11:41:12.922673 MD32_EN : 0
6166 11:41:12.925555 ===================================
6167 11:41:12.928859 [ANA_INIT] >>>>>>>>>>>>>>
6168 11:41:12.932142 <<<<<< [CONFIGURE PHASE]: ANA_TX
6169 11:41:12.935280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6170 11:41:12.938755 ===================================
6171 11:41:12.941548 data_rate = 800,PCW = 0X7400
6172 11:41:12.945510 ===================================
6173 11:41:12.948343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6174 11:41:12.951657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6175 11:41:12.964965 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6176 11:41:12.968290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6177 11:41:12.971770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6178 11:41:12.974985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6179 11:41:12.978324 [ANA_INIT] flow start
6180 11:41:12.981413 [ANA_INIT] PLL >>>>>>>>
6181 11:41:12.981931 [ANA_INIT] PLL <<<<<<<<
6182 11:41:12.984972 [ANA_INIT] MIDPI >>>>>>>>
6183 11:41:12.988233 [ANA_INIT] MIDPI <<<<<<<<
6184 11:41:12.991294 [ANA_INIT] DLL >>>>>>>>
6185 11:41:12.991809 [ANA_INIT] flow end
6186 11:41:12.994653 ============ LP4 DIFF to SE enter ============
6187 11:41:13.001184 ============ LP4 DIFF to SE exit ============
6188 11:41:13.001704 [ANA_INIT] <<<<<<<<<<<<<
6189 11:41:13.004341 [Flow] Enable top DCM control >>>>>
6190 11:41:13.007411 [Flow] Enable top DCM control <<<<<
6191 11:41:13.010895 Enable DLL master slave shuffle
6192 11:41:13.017319 ==============================================================
6193 11:41:13.017740 Gating Mode config
6194 11:41:13.024192 ==============================================================
6195 11:41:13.027398 Config description:
6196 11:41:13.037498 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6197 11:41:13.043885 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6198 11:41:13.047168 SELPH_MODE 0: By rank 1: By Phase
6199 11:41:13.053956 ==============================================================
6200 11:41:13.057053 GAT_TRACK_EN = 0
6201 11:41:13.060634 RX_GATING_MODE = 2
6202 11:41:13.061183 RX_GATING_TRACK_MODE = 2
6203 11:41:13.063669 SELPH_MODE = 1
6204 11:41:13.067085 PICG_EARLY_EN = 1
6205 11:41:13.070522 VALID_LAT_VALUE = 1
6206 11:41:13.076718 ==============================================================
6207 11:41:13.080353 Enter into Gating configuration >>>>
6208 11:41:13.083492 Exit from Gating configuration <<<<
6209 11:41:13.086779 Enter into DVFS_PRE_config >>>>>
6210 11:41:13.096665 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6211 11:41:13.100066 Exit from DVFS_PRE_config <<<<<
6212 11:41:13.103013 Enter into PICG configuration >>>>
6213 11:41:13.106337 Exit from PICG configuration <<<<
6214 11:41:13.110019 [RX_INPUT] configuration >>>>>
6215 11:41:13.113004 [RX_INPUT] configuration <<<<<
6216 11:41:13.116487 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6217 11:41:13.122986 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6218 11:41:13.129872 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6219 11:41:13.136081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6220 11:41:13.142884 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6221 11:41:13.149257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6222 11:41:13.152933 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6223 11:41:13.155808 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6224 11:41:13.159013 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6225 11:41:13.165717 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6226 11:41:13.169317 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6227 11:41:13.172533 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6228 11:41:13.175479 ===================================
6229 11:41:13.178874 LPDDR4 DRAM CONFIGURATION
6230 11:41:13.182145 ===================================
6231 11:41:13.182685 EX_ROW_EN[0] = 0x0
6232 11:41:13.185443 EX_ROW_EN[1] = 0x0
6233 11:41:13.185859 LP4Y_EN = 0x0
6234 11:41:13.189082 WORK_FSP = 0x0
6235 11:41:13.192073 WL = 0x2
6236 11:41:13.192492 RL = 0x2
6237 11:41:13.195391 BL = 0x2
6238 11:41:13.195910 RPST = 0x0
6239 11:41:13.198793 RD_PRE = 0x0
6240 11:41:13.199284 WR_PRE = 0x1
6241 11:41:13.201986 WR_PST = 0x0
6242 11:41:13.202398 DBI_WR = 0x0
6243 11:41:13.205584 DBI_RD = 0x0
6244 11:41:13.206121 OTF = 0x1
6245 11:41:13.208860 ===================================
6246 11:41:13.212197 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6247 11:41:13.218949 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6248 11:41:13.222107 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 11:41:13.225389 ===================================
6250 11:41:13.228923 LPDDR4 DRAM CONFIGURATION
6251 11:41:13.231821 ===================================
6252 11:41:13.232238 EX_ROW_EN[0] = 0x10
6253 11:41:13.235529 EX_ROW_EN[1] = 0x0
6254 11:41:13.236048 LP4Y_EN = 0x0
6255 11:41:13.238454 WORK_FSP = 0x0
6256 11:41:13.241826 WL = 0x2
6257 11:41:13.242344 RL = 0x2
6258 11:41:13.245187 BL = 0x2
6259 11:41:13.245702 RPST = 0x0
6260 11:41:13.248494 RD_PRE = 0x0
6261 11:41:13.249029 WR_PRE = 0x1
6262 11:41:13.251440 WR_PST = 0x0
6263 11:41:13.251880 DBI_WR = 0x0
6264 11:41:13.254862 DBI_RD = 0x0
6265 11:41:13.255275 OTF = 0x1
6266 11:41:13.258837 ===================================
6267 11:41:13.264907 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6268 11:41:13.269163 nWR fixed to 30
6269 11:41:13.272402 [ModeRegInit_LP4] CH0 RK0
6270 11:41:13.272916 [ModeRegInit_LP4] CH0 RK1
6271 11:41:13.275498 [ModeRegInit_LP4] CH1 RK0
6272 11:41:13.278683 [ModeRegInit_LP4] CH1 RK1
6273 11:41:13.279096 match AC timing 19
6274 11:41:13.285374 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6275 11:41:13.288630 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6276 11:41:13.292023 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6277 11:41:13.298864 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6278 11:41:13.302277 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6279 11:41:13.302791 ==
6280 11:41:13.305143 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 11:41:13.308553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 11:41:13.308965 ==
6283 11:41:13.315558 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 11:41:13.321865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6285 11:41:13.325381 [CA 0] Center 36 (8~64) winsize 57
6286 11:41:13.328526 [CA 1] Center 36 (8~64) winsize 57
6287 11:41:13.331800 [CA 2] Center 36 (8~64) winsize 57
6288 11:41:13.335091 [CA 3] Center 36 (8~64) winsize 57
6289 11:41:13.338418 [CA 4] Center 36 (8~64) winsize 57
6290 11:41:13.338938 [CA 5] Center 36 (8~64) winsize 57
6291 11:41:13.341667
6292 11:41:13.344865 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6293 11:41:13.345333
6294 11:41:13.348420 [CATrainingPosCal] consider 1 rank data
6295 11:41:13.351874 u2DelayCellTimex100 = 270/100 ps
6296 11:41:13.355096 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 11:41:13.358651 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 11:41:13.361379 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 11:41:13.364787 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:41:13.368230 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:41:13.371314 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:41:13.371853
6303 11:41:13.374406 CA PerBit enable=1, Macro0, CA PI delay=36
6304 11:41:13.378273
6305 11:41:13.378796 [CBTSetCACLKResult] CA Dly = 36
6306 11:41:13.381315 CS Dly: 1 (0~32)
6307 11:41:13.381727 ==
6308 11:41:13.384195 Dram Type= 6, Freq= 0, CH_0, rank 1
6309 11:41:13.387721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 11:41:13.388138 ==
6311 11:41:13.394506 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6312 11:41:13.400966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6313 11:41:13.404226 [CA 0] Center 36 (8~64) winsize 57
6314 11:41:13.407555 [CA 1] Center 36 (8~64) winsize 57
6315 11:41:13.410833 [CA 2] Center 36 (8~64) winsize 57
6316 11:41:13.414144 [CA 3] Center 36 (8~64) winsize 57
6317 11:41:13.414661 [CA 4] Center 36 (8~64) winsize 57
6318 11:41:13.417110 [CA 5] Center 36 (8~64) winsize 57
6319 11:41:13.417632
6320 11:41:13.424130 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6321 11:41:13.424643
6322 11:41:13.427181 [CATrainingPosCal] consider 2 rank data
6323 11:41:13.430168 u2DelayCellTimex100 = 270/100 ps
6324 11:41:13.433415 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 11:41:13.437007 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 11:41:13.440518 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 11:41:13.443778 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 11:41:13.447108 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 11:41:13.450174 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 11:41:13.450690
6331 11:41:13.453528 CA PerBit enable=1, Macro0, CA PI delay=36
6332 11:41:13.454040
6333 11:41:13.456969 [CBTSetCACLKResult] CA Dly = 36
6334 11:41:13.460570 CS Dly: 1 (0~32)
6335 11:41:13.461123
6336 11:41:13.463669 ----->DramcWriteLeveling(PI) begin...
6337 11:41:13.464192 ==
6338 11:41:13.466702 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 11:41:13.470041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 11:41:13.470560 ==
6341 11:41:13.473551 Write leveling (Byte 0): 40 => 8
6342 11:41:13.476893 Write leveling (Byte 1): 32 => 0
6343 11:41:13.480043 DramcWriteLeveling(PI) end<-----
6344 11:41:13.480572
6345 11:41:13.480907 ==
6346 11:41:13.483306 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 11:41:13.486480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 11:41:13.486899 ==
6349 11:41:13.489730 [Gating] SW mode calibration
6350 11:41:13.496310 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6351 11:41:13.503197 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6352 11:41:13.506760 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6353 11:41:13.513192 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6354 11:41:13.516410 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 11:41:13.519898 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 11:41:13.526387 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 11:41:13.529764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 11:41:13.532970 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 11:41:13.539474 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 11:41:13.542635 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 11:41:13.545981 Total UI for P1: 0, mck2ui 16
6362 11:41:13.549105 best dqsien dly found for B0: ( 0, 14, 24)
6363 11:41:13.552724 Total UI for P1: 0, mck2ui 16
6364 11:41:13.556017 best dqsien dly found for B1: ( 0, 14, 24)
6365 11:41:13.559209 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6366 11:41:13.562738 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6367 11:41:13.563250
6368 11:41:13.565590 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6369 11:41:13.569014 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6370 11:41:13.572222 [Gating] SW calibration Done
6371 11:41:13.572625 ==
6372 11:41:13.575463 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 11:41:13.582208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 11:41:13.582615 ==
6375 11:41:13.582933 RX Vref Scan: 0
6376 11:41:13.583231
6377 11:41:13.585133 RX Vref 0 -> 0, step: 1
6378 11:41:13.585540
6379 11:41:13.588535 RX Delay -410 -> 252, step: 16
6380 11:41:13.591834 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6381 11:41:13.595073 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6382 11:41:13.601522 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6383 11:41:13.604853 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6384 11:41:13.608335 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6385 11:41:13.611479 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6386 11:41:13.618295 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6387 11:41:13.621540 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6388 11:41:13.624917 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6389 11:41:13.628294 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6390 11:41:13.635057 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6391 11:41:13.638151 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6392 11:41:13.641417 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6393 11:41:13.644748 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6394 11:41:13.651320 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6395 11:41:13.654537 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6396 11:41:13.655137 ==
6397 11:41:13.658468 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 11:41:13.660921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 11:41:13.661382 ==
6400 11:41:13.664754 DQS Delay:
6401 11:41:13.665387 DQS0 = 19, DQS1 = 43
6402 11:41:13.667640 DQM Delay:
6403 11:41:13.668040 DQM0 = 5, DQM1 = 14
6404 11:41:13.668361 DQ Delay:
6405 11:41:13.671222 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6406 11:41:13.674837 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6407 11:41:13.677785 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6408 11:41:13.680882 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6409 11:41:13.681337
6410 11:41:13.681658
6411 11:41:13.681951 ==
6412 11:41:13.684229 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 11:41:13.690649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 11:41:13.691223 ==
6415 11:41:13.691548
6416 11:41:13.691845
6417 11:41:13.692124 TX Vref Scan disable
6418 11:41:13.693971 == TX Byte 0 ==
6419 11:41:13.697337 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 11:41:13.700682 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 11:41:13.704114 == TX Byte 1 ==
6422 11:41:13.707090 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6423 11:41:13.710864 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6424 11:41:13.711271 ==
6425 11:41:13.713834 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 11:41:13.720458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 11:41:13.721047 ==
6428 11:41:13.721399
6429 11:41:13.721709
6430 11:41:13.723968 TX Vref Scan disable
6431 11:41:13.724488 == TX Byte 0 ==
6432 11:41:13.727216 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 11:41:13.733621 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 11:41:13.734139 == TX Byte 1 ==
6435 11:41:13.737358 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6436 11:41:13.743526 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6437 11:41:13.744065
6438 11:41:13.744404 [DATLAT]
6439 11:41:13.744715 Freq=400, CH0 RK0
6440 11:41:13.745044
6441 11:41:13.746749 DATLAT Default: 0xf
6442 11:41:13.750204 0, 0xFFFF, sum = 0
6443 11:41:13.750724 1, 0xFFFF, sum = 0
6444 11:41:13.753402 2, 0xFFFF, sum = 0
6445 11:41:13.753921 3, 0xFFFF, sum = 0
6446 11:41:13.756922 4, 0xFFFF, sum = 0
6447 11:41:13.757481 5, 0xFFFF, sum = 0
6448 11:41:13.760024 6, 0xFFFF, sum = 0
6449 11:41:13.760545 7, 0xFFFF, sum = 0
6450 11:41:13.763297 8, 0xFFFF, sum = 0
6451 11:41:13.763815 9, 0xFFFF, sum = 0
6452 11:41:13.766630 10, 0xFFFF, sum = 0
6453 11:41:13.767195 11, 0xFFFF, sum = 0
6454 11:41:13.770304 12, 0xFFFF, sum = 0
6455 11:41:13.770828 13, 0x0, sum = 1
6456 11:41:13.773183 14, 0x0, sum = 2
6457 11:41:13.773694 15, 0x0, sum = 3
6458 11:41:13.776536 16, 0x0, sum = 4
6459 11:41:13.776971 best_step = 14
6460 11:41:13.777507
6461 11:41:13.778013 ==
6462 11:41:13.779632 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 11:41:13.786437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 11:41:13.786953 ==
6465 11:41:13.787289 RX Vref Scan: 1
6466 11:41:13.787602
6467 11:41:13.789771 RX Vref 0 -> 0, step: 1
6468 11:41:13.790190
6469 11:41:13.793070 RX Delay -327 -> 252, step: 8
6470 11:41:13.793581
6471 11:41:13.796374 Set Vref, RX VrefLevel [Byte0]: 61
6472 11:41:13.799718 [Byte1]: 51
6473 11:41:13.800370
6474 11:41:13.803062 Final RX Vref Byte 0 = 61 to rank0
6475 11:41:13.806107 Final RX Vref Byte 1 = 51 to rank0
6476 11:41:13.809224 Final RX Vref Byte 0 = 61 to rank1
6477 11:41:13.812582 Final RX Vref Byte 1 = 51 to rank1==
6478 11:41:13.816219 Dram Type= 6, Freq= 0, CH_0, rank 0
6479 11:41:13.819420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 11:41:13.822486 ==
6481 11:41:13.823069 DQS Delay:
6482 11:41:13.823579 DQS0 = 28, DQS1 = 48
6483 11:41:13.826132 DQM Delay:
6484 11:41:13.826651 DQM0 = 12, DQM1 = 15
6485 11:41:13.829092 DQ Delay:
6486 11:41:13.829512 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6487 11:41:13.832680 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6488 11:41:13.836051 DQ8 =12, DQ9 =0, DQ10 =16, DQ11 =8
6489 11:41:13.839610 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6490 11:41:13.840209
6491 11:41:13.840544
6492 11:41:13.849052 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6493 11:41:13.852360 CH0 RK0: MR19=C0C, MR18=A9A1
6494 11:41:13.859302 CH0_RK0: MR19=0xC0C, MR18=0xA9A1, DQSOSC=388, MR23=63, INC=392, DEC=261
6495 11:41:13.859820 ==
6496 11:41:13.862263 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 11:41:13.865553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 11:41:13.866115 ==
6499 11:41:13.868736 [Gating] SW mode calibration
6500 11:41:13.875499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6501 11:41:13.882098 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6502 11:41:13.885419 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 11:41:13.888816 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 11:41:13.895596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 11:41:13.898632 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 11:41:13.901763 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 11:41:13.908698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 11:41:13.912284 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 11:41:13.915710 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 11:41:13.921816 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 11:41:13.922375 Total UI for P1: 0, mck2ui 16
6512 11:41:13.925118 best dqsien dly found for B0: ( 0, 14, 24)
6513 11:41:13.928440 Total UI for P1: 0, mck2ui 16
6514 11:41:13.931778 best dqsien dly found for B1: ( 0, 14, 24)
6515 11:41:13.938381 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6516 11:41:13.941812 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6517 11:41:13.942293
6518 11:41:13.945068 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6519 11:41:13.948204 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6520 11:41:13.951687 [Gating] SW calibration Done
6521 11:41:13.952205 ==
6522 11:41:13.954864 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 11:41:13.958484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 11:41:13.959005 ==
6525 11:41:13.961710 RX Vref Scan: 0
6526 11:41:13.962227
6527 11:41:13.962557 RX Vref 0 -> 0, step: 1
6528 11:41:13.962866
6529 11:41:13.964824 RX Delay -410 -> 252, step: 16
6530 11:41:13.971939 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6531 11:41:13.975002 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6532 11:41:13.978475 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6533 11:41:13.981229 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6534 11:41:13.984703 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6535 11:41:13.991338 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6536 11:41:13.994739 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6537 11:41:13.997722 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6538 11:41:14.001459 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6539 11:41:14.007962 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6540 11:41:14.011170 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6541 11:41:14.015062 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6542 11:41:14.021062 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6543 11:41:14.024637 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6544 11:41:14.027663 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6545 11:41:14.030823 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6546 11:41:14.034146 ==
6547 11:41:14.034605 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 11:41:14.040734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 11:41:14.041361 ==
6550 11:41:14.041721 DQS Delay:
6551 11:41:14.044263 DQS0 = 27, DQS1 = 43
6552 11:41:14.044678 DQM Delay:
6553 11:41:14.047479 DQM0 = 9, DQM1 = 14
6554 11:41:14.047902 DQ Delay:
6555 11:41:14.050832 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6556 11:41:14.054081 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6557 11:41:14.057382 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6558 11:41:14.060828 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6559 11:41:14.061395
6560 11:41:14.061730
6561 11:41:14.062038 ==
6562 11:41:14.064307 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 11:41:14.067175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 11:41:14.067699 ==
6565 11:41:14.068034
6566 11:41:14.068345
6567 11:41:14.070667 TX Vref Scan disable
6568 11:41:14.071189 == TX Byte 0 ==
6569 11:41:14.077317 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6570 11:41:14.080510 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6571 11:41:14.081061 == TX Byte 1 ==
6572 11:41:14.087106 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6573 11:41:14.090220 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6574 11:41:14.090756 ==
6575 11:41:14.093821 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 11:41:14.097240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 11:41:14.097769 ==
6578 11:41:14.098103
6579 11:41:14.098409
6580 11:41:14.100365 TX Vref Scan disable
6581 11:41:14.100889 == TX Byte 0 ==
6582 11:41:14.106837 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6583 11:41:14.109974 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6584 11:41:14.110399 == TX Byte 1 ==
6585 11:41:14.116862 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6586 11:41:14.119721 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6587 11:41:14.120148
6588 11:41:14.120479 [DATLAT]
6589 11:41:14.123272 Freq=400, CH0 RK1
6590 11:41:14.123772
6591 11:41:14.124109 DATLAT Default: 0xe
6592 11:41:14.126662 0, 0xFFFF, sum = 0
6593 11:41:14.127199 1, 0xFFFF, sum = 0
6594 11:41:14.129692 2, 0xFFFF, sum = 0
6595 11:41:14.130119 3, 0xFFFF, sum = 0
6596 11:41:14.133197 4, 0xFFFF, sum = 0
6597 11:41:14.133628 5, 0xFFFF, sum = 0
6598 11:41:14.136570 6, 0xFFFF, sum = 0
6599 11:41:14.137136 7, 0xFFFF, sum = 0
6600 11:41:14.139867 8, 0xFFFF, sum = 0
6601 11:41:14.143217 9, 0xFFFF, sum = 0
6602 11:41:14.143829 10, 0xFFFF, sum = 0
6603 11:41:14.146195 11, 0xFFFF, sum = 0
6604 11:41:14.146773 12, 0xFFFF, sum = 0
6605 11:41:14.149449 13, 0x0, sum = 1
6606 11:41:14.149891 14, 0x0, sum = 2
6607 11:41:14.153119 15, 0x0, sum = 3
6608 11:41:14.153645 16, 0x0, sum = 4
6609 11:41:14.154026 best_step = 14
6610 11:41:14.154347
6611 11:41:14.156452 ==
6612 11:41:14.159880 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 11:41:14.163219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 11:41:14.163742 ==
6615 11:41:14.164095 RX Vref Scan: 0
6616 11:41:14.164526
6617 11:41:14.166362 RX Vref 0 -> 0, step: 1
6618 11:41:14.166881
6619 11:41:14.169772 RX Delay -327 -> 252, step: 8
6620 11:41:14.176523 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6621 11:41:14.179965 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6622 11:41:14.183524 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6623 11:41:14.189640 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6624 11:41:14.193011 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6625 11:41:14.196399 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6626 11:41:14.199823 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6627 11:41:14.203142 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6628 11:41:14.209684 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6629 11:41:14.213283 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6630 11:41:14.216262 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6631 11:41:14.222902 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6632 11:41:14.226413 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6633 11:41:14.229534 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6634 11:41:14.232704 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6635 11:41:14.239301 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6636 11:41:14.239875 ==
6637 11:41:14.243105 Dram Type= 6, Freq= 0, CH_0, rank 1
6638 11:41:14.245609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 11:41:14.246086 ==
6640 11:41:14.246693 DQS Delay:
6641 11:41:14.249573 DQS0 = 28, DQS1 = 40
6642 11:41:14.250121 DQM Delay:
6643 11:41:14.252517 DQM0 = 10, DQM1 = 12
6644 11:41:14.252974 DQ Delay:
6645 11:41:14.255528 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6646 11:41:14.258875 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6647 11:41:14.262361 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6648 11:41:14.266141 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6649 11:41:14.266704
6650 11:41:14.267074
6651 11:41:14.272259 [DQSOSCAuto] RK1, (LSB)MR18= 0xb56a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6652 11:41:14.275649 CH0 RK1: MR19=C0C, MR18=B56A
6653 11:41:14.282194 CH0_RK1: MR19=0xC0C, MR18=0xB56A, DQSOSC=387, MR23=63, INC=394, DEC=262
6654 11:41:14.285772 [RxdqsGatingPostProcess] freq 400
6655 11:41:14.292297 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6656 11:41:14.295518 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 11:41:14.299048 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 11:41:14.302186 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 11:41:14.305220 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 11:41:14.305782 best DQS0 dly(2T, 0.5T) = (0, 10)
6661 11:41:14.308910 best DQS1 dly(2T, 0.5T) = (0, 10)
6662 11:41:14.312192 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6663 11:41:14.315935 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6664 11:41:14.318678 Pre-setting of DQS Precalculation
6665 11:41:14.325373 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6666 11:41:14.325944 ==
6667 11:41:14.328571 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 11:41:14.332099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 11:41:14.332679 ==
6670 11:41:14.338449 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 11:41:14.345471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6672 11:41:14.348225 [CA 0] Center 36 (8~64) winsize 57
6673 11:41:14.351522 [CA 1] Center 36 (8~64) winsize 57
6674 11:41:14.352091 [CA 2] Center 36 (8~64) winsize 57
6675 11:41:14.355011 [CA 3] Center 36 (8~64) winsize 57
6676 11:41:14.358090 [CA 4] Center 36 (8~64) winsize 57
6677 11:41:14.361645 [CA 5] Center 36 (8~64) winsize 57
6678 11:41:14.362209
6679 11:41:14.364573 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6680 11:41:14.368020
6681 11:41:14.371116 [CATrainingPosCal] consider 1 rank data
6682 11:41:14.371626 u2DelayCellTimex100 = 270/100 ps
6683 11:41:14.377787 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 11:41:14.380940 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 11:41:14.384522 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 11:41:14.388155 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:41:14.391138 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:41:14.395087 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:41:14.395650
6690 11:41:14.397520 CA PerBit enable=1, Macro0, CA PI delay=36
6691 11:41:14.397986
6692 11:41:14.401176 [CBTSetCACLKResult] CA Dly = 36
6693 11:41:14.404282 CS Dly: 1 (0~32)
6694 11:41:14.404839 ==
6695 11:41:14.407513 Dram Type= 6, Freq= 0, CH_1, rank 1
6696 11:41:14.411109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 11:41:14.411677 ==
6698 11:41:14.417582 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6699 11:41:14.420632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6700 11:41:14.423984 [CA 0] Center 36 (8~64) winsize 57
6701 11:41:14.427499 [CA 1] Center 36 (8~64) winsize 57
6702 11:41:14.430786 [CA 2] Center 36 (8~64) winsize 57
6703 11:41:14.433761 [CA 3] Center 36 (8~64) winsize 57
6704 11:41:14.437488 [CA 4] Center 36 (8~64) winsize 57
6705 11:41:14.440811 [CA 5] Center 36 (8~64) winsize 57
6706 11:41:14.441417
6707 11:41:14.443868 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6708 11:41:14.444425
6709 11:41:14.447311 [CATrainingPosCal] consider 2 rank data
6710 11:41:14.450458 u2DelayCellTimex100 = 270/100 ps
6711 11:41:14.453848 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 11:41:14.460592 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 11:41:14.464183 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 11:41:14.466951 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 11:41:14.470333 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 11:41:14.473645 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 11:41:14.474128
6718 11:41:14.476934 CA PerBit enable=1, Macro0, CA PI delay=36
6719 11:41:14.477512
6720 11:41:14.480520 [CBTSetCACLKResult] CA Dly = 36
6721 11:41:14.481019 CS Dly: 1 (0~32)
6722 11:41:14.483595
6723 11:41:14.487312 ----->DramcWriteLeveling(PI) begin...
6724 11:41:14.487852 ==
6725 11:41:14.490525 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 11:41:14.493801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 11:41:14.494276 ==
6728 11:41:14.496838 Write leveling (Byte 0): 40 => 8
6729 11:41:14.500608 Write leveling (Byte 1): 32 => 0
6730 11:41:14.503633 DramcWriteLeveling(PI) end<-----
6731 11:41:14.504197
6732 11:41:14.504669 ==
6733 11:41:14.507146 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 11:41:14.510341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 11:41:14.510819 ==
6736 11:41:14.513163 [Gating] SW mode calibration
6737 11:41:14.520106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6738 11:41:14.526822 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6739 11:41:14.529730 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6740 11:41:14.533079 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6741 11:41:14.540137 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 11:41:14.543475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 11:41:14.547191 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 11:41:14.553415 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 11:41:14.556207 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 11:41:14.559972 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 11:41:14.566381 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 11:41:14.566942 Total UI for P1: 0, mck2ui 16
6749 11:41:14.572971 best dqsien dly found for B0: ( 0, 14, 24)
6750 11:41:14.573574 Total UI for P1: 0, mck2ui 16
6751 11:41:14.576468 best dqsien dly found for B1: ( 0, 14, 24)
6752 11:41:14.582788 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6753 11:41:14.586318 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6754 11:41:14.586887
6755 11:41:14.589100 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6756 11:41:14.592419 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6757 11:41:14.595747 [Gating] SW calibration Done
6758 11:41:14.596203 ==
6759 11:41:14.599210 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 11:41:14.602723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 11:41:14.603280 ==
6762 11:41:14.606001 RX Vref Scan: 0
6763 11:41:14.606560
6764 11:41:14.606925 RX Vref 0 -> 0, step: 1
6765 11:41:14.607261
6766 11:41:14.609670 RX Delay -410 -> 252, step: 16
6767 11:41:14.616084 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6768 11:41:14.618949 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6769 11:41:14.622015 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6770 11:41:14.625363 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6771 11:41:14.632319 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6772 11:41:14.635662 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6773 11:41:14.638732 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6774 11:41:14.642545 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6775 11:41:14.648801 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6776 11:41:14.652093 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6777 11:41:14.655425 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6778 11:41:14.658657 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6779 11:41:14.665627 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6780 11:41:14.668689 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6781 11:41:14.671672 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6782 11:41:14.679114 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6783 11:41:14.679686 ==
6784 11:41:14.681746 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 11:41:14.685045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 11:41:14.685517 ==
6787 11:41:14.685889 DQS Delay:
6788 11:41:14.688177 DQS0 = 27, DQS1 = 43
6789 11:41:14.688639 DQM Delay:
6790 11:41:14.691895 DQM0 = 9, DQM1 = 16
6791 11:41:14.692465 DQ Delay:
6792 11:41:14.695213 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6793 11:41:14.698392 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6794 11:41:14.701786 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6795 11:41:14.704709 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6796 11:41:14.705318
6797 11:41:14.705703
6798 11:41:14.706050 ==
6799 11:41:14.708625 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 11:41:14.711496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 11:41:14.711970 ==
6802 11:41:14.712337
6803 11:41:14.712677
6804 11:41:14.715078 TX Vref Scan disable
6805 11:41:14.715649 == TX Byte 0 ==
6806 11:41:14.721471 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 11:41:14.724842 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 11:41:14.725337 == TX Byte 1 ==
6809 11:41:14.731693 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6810 11:41:14.734908 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6811 11:41:14.735483 ==
6812 11:41:14.737921 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 11:41:14.741651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 11:41:14.742229 ==
6815 11:41:14.742605
6816 11:41:14.742947
6817 11:41:14.744689 TX Vref Scan disable
6818 11:41:14.747989 == TX Byte 0 ==
6819 11:41:14.751475 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 11:41:14.754725 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 11:41:14.757678 == TX Byte 1 ==
6822 11:41:14.761169 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6823 11:41:14.764747 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6824 11:41:14.765353
6825 11:41:14.765728 [DATLAT]
6826 11:41:14.768132 Freq=400, CH1 RK0
6827 11:41:14.768598
6828 11:41:14.770890 DATLAT Default: 0xf
6829 11:41:14.771353 0, 0xFFFF, sum = 0
6830 11:41:14.774291 1, 0xFFFF, sum = 0
6831 11:41:14.774763 2, 0xFFFF, sum = 0
6832 11:41:14.777728 3, 0xFFFF, sum = 0
6833 11:41:14.778198 4, 0xFFFF, sum = 0
6834 11:41:14.781021 5, 0xFFFF, sum = 0
6835 11:41:14.781493 6, 0xFFFF, sum = 0
6836 11:41:14.784244 7, 0xFFFF, sum = 0
6837 11:41:14.784712 8, 0xFFFF, sum = 0
6838 11:41:14.787863 9, 0xFFFF, sum = 0
6839 11:41:14.788393 10, 0xFFFF, sum = 0
6840 11:41:14.791504 11, 0xFFFF, sum = 0
6841 11:41:14.792085 12, 0xFFFF, sum = 0
6842 11:41:14.794236 13, 0x0, sum = 1
6843 11:41:14.794740 14, 0x0, sum = 2
6844 11:41:14.797552 15, 0x0, sum = 3
6845 11:41:14.798027 16, 0x0, sum = 4
6846 11:41:14.800898 best_step = 14
6847 11:41:14.801403
6848 11:41:14.801831 ==
6849 11:41:14.804075 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 11:41:14.807298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 11:41:14.807724 ==
6852 11:41:14.810860 RX Vref Scan: 1
6853 11:41:14.811281
6854 11:41:14.811613 RX Vref 0 -> 0, step: 1
6855 11:41:14.811927
6856 11:41:14.814580 RX Delay -327 -> 252, step: 8
6857 11:41:14.815002
6858 11:41:14.817504 Set Vref, RX VrefLevel [Byte0]: 52
6859 11:41:14.820695 [Byte1]: 54
6860 11:41:14.825332
6861 11:41:14.825855 Final RX Vref Byte 0 = 52 to rank0
6862 11:41:14.828603 Final RX Vref Byte 1 = 54 to rank0
6863 11:41:14.831815 Final RX Vref Byte 0 = 52 to rank1
6864 11:41:14.834986 Final RX Vref Byte 1 = 54 to rank1==
6865 11:41:14.838850 Dram Type= 6, Freq= 0, CH_1, rank 0
6866 11:41:14.844942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 11:41:14.845505 ==
6868 11:41:14.845850 DQS Delay:
6869 11:41:14.848236 DQS0 = 32, DQS1 = 40
6870 11:41:14.848658 DQM Delay:
6871 11:41:14.849015 DQM0 = 12, DQM1 = 12
6872 11:41:14.851163 DQ Delay:
6873 11:41:14.854480 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6874 11:41:14.857929 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6875 11:41:14.858368 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6876 11:41:14.864755 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6877 11:41:14.865317
6878 11:41:14.865657
6879 11:41:14.871392 [DQSOSCAuto] RK0, (LSB)MR18= 0x98d2, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6880 11:41:14.874673 CH1 RK0: MR19=C0C, MR18=98D2
6881 11:41:14.881343 CH1_RK0: MR19=0xC0C, MR18=0x98D2, DQSOSC=383, MR23=63, INC=402, DEC=268
6882 11:41:14.881898 ==
6883 11:41:14.884577 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 11:41:14.888109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 11:41:14.888676 ==
6886 11:41:14.891019 [Gating] SW mode calibration
6887 11:41:14.897608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6888 11:41:14.904448 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6889 11:41:14.907414 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6890 11:41:14.910823 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6891 11:41:14.917099 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 11:41:14.920662 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 11:41:14.923695 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 11:41:14.930615 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 11:41:14.933678 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 11:41:14.937263 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 11:41:14.943609 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 11:41:14.946960 Total UI for P1: 0, mck2ui 16
6899 11:41:14.950040 best dqsien dly found for B0: ( 0, 14, 24)
6900 11:41:14.953671 Total UI for P1: 0, mck2ui 16
6901 11:41:14.956408 best dqsien dly found for B1: ( 0, 14, 24)
6902 11:41:14.960084 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6903 11:41:14.963448 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6904 11:41:14.964005
6905 11:41:14.966566 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6906 11:41:14.969871 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6907 11:41:14.973233 [Gating] SW calibration Done
6908 11:41:14.973802 ==
6909 11:41:14.976321 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 11:41:14.979853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 11:41:14.980411 ==
6912 11:41:14.982801 RX Vref Scan: 0
6913 11:41:14.983261
6914 11:41:14.986579 RX Vref 0 -> 0, step: 1
6915 11:41:14.987140
6916 11:41:14.989704 RX Delay -410 -> 252, step: 16
6917 11:41:14.993123 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6918 11:41:14.996050 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6919 11:41:14.999540 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6920 11:41:15.006177 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6921 11:41:15.009565 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6922 11:41:15.012725 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6923 11:41:15.016233 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6924 11:41:15.023024 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6925 11:41:15.025855 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6926 11:41:15.029533 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6927 11:41:15.032436 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6928 11:41:15.039444 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6929 11:41:15.042773 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6930 11:41:15.046188 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6931 11:41:15.049311 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6932 11:41:15.055872 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6933 11:41:15.056428 ==
6934 11:41:15.059614 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 11:41:15.062748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 11:41:15.063312 ==
6937 11:41:15.063684 DQS Delay:
6938 11:41:15.065840 DQS0 = 35, DQS1 = 43
6939 11:41:15.066298 DQM Delay:
6940 11:41:15.069107 DQM0 = 16, DQM1 = 18
6941 11:41:15.069570 DQ Delay:
6942 11:41:15.072552 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6943 11:41:15.075642 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6944 11:41:15.079173 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6945 11:41:15.082443 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6946 11:41:15.083006
6947 11:41:15.083374
6948 11:41:15.083711 ==
6949 11:41:15.085468 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 11:41:15.089070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 11:41:15.092147 ==
6952 11:41:15.092605
6953 11:41:15.092965
6954 11:41:15.093359 TX Vref Scan disable
6955 11:41:15.095212 == TX Byte 0 ==
6956 11:41:15.098635 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6957 11:41:15.102374 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6958 11:41:15.105340 == TX Byte 1 ==
6959 11:41:15.108808 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6960 11:41:15.111841 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6961 11:41:15.112305 ==
6962 11:41:15.115440 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 11:41:15.121597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 11:41:15.122060 ==
6965 11:41:15.122453
6966 11:41:15.122796
6967 11:41:15.123121 TX Vref Scan disable
6968 11:41:15.125254 == TX Byte 0 ==
6969 11:41:15.128529 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6970 11:41:15.131520 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6971 11:41:15.134712 == TX Byte 1 ==
6972 11:41:15.138680 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6973 11:41:15.141644 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6974 11:41:15.142109
6975 11:41:15.144671 [DATLAT]
6976 11:41:15.145169 Freq=400, CH1 RK1
6977 11:41:15.145543
6978 11:41:15.148217 DATLAT Default: 0xe
6979 11:41:15.148702 0, 0xFFFF, sum = 0
6980 11:41:15.151768 1, 0xFFFF, sum = 0
6981 11:41:15.152359 2, 0xFFFF, sum = 0
6982 11:41:15.154623 3, 0xFFFF, sum = 0
6983 11:41:15.155089 4, 0xFFFF, sum = 0
6984 11:41:15.158145 5, 0xFFFF, sum = 0
6985 11:41:15.158614 6, 0xFFFF, sum = 0
6986 11:41:15.161189 7, 0xFFFF, sum = 0
6987 11:41:15.161656 8, 0xFFFF, sum = 0
6988 11:41:15.164779 9, 0xFFFF, sum = 0
6989 11:41:15.168074 10, 0xFFFF, sum = 0
6990 11:41:15.168638 11, 0xFFFF, sum = 0
6991 11:41:15.171697 12, 0xFFFF, sum = 0
6992 11:41:15.172256 13, 0x0, sum = 1
6993 11:41:15.174629 14, 0x0, sum = 2
6994 11:41:15.175100 15, 0x0, sum = 3
6995 11:41:15.177892 16, 0x0, sum = 4
6996 11:41:15.178461 best_step = 14
6997 11:41:15.178830
6998 11:41:15.179167 ==
6999 11:41:15.181337 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 11:41:15.184502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 11:41:15.185129 ==
7002 11:41:15.187453 RX Vref Scan: 0
7003 11:41:15.187913
7004 11:41:15.191415 RX Vref 0 -> 0, step: 1
7005 11:41:15.191975
7006 11:41:15.192347 RX Delay -327 -> 252, step: 8
7007 11:41:15.199794 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7008 11:41:15.203171 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7009 11:41:15.206701 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7010 11:41:15.212734 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
7011 11:41:15.216409 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7012 11:41:15.219859 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7013 11:41:15.222832 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7014 11:41:15.229416 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7015 11:41:15.232696 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7016 11:41:15.235816 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7017 11:41:15.239415 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7018 11:41:15.246104 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7019 11:41:15.249085 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7020 11:41:15.252281 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7021 11:41:15.255588 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7022 11:41:15.262233 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7023 11:41:15.262655 ==
7024 11:41:15.265790 Dram Type= 6, Freq= 0, CH_1, rank 1
7025 11:41:15.269056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7026 11:41:15.269476 ==
7027 11:41:15.269807 DQS Delay:
7028 11:41:15.272485 DQS0 = 32, DQS1 = 36
7029 11:41:15.273038 DQM Delay:
7030 11:41:15.275693 DQM0 = 12, DQM1 = 11
7031 11:41:15.276108 DQ Delay:
7032 11:41:15.279222 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
7033 11:41:15.282344 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
7034 11:41:15.285538 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7035 11:41:15.289264 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7036 11:41:15.289782
7037 11:41:15.290117
7038 11:41:15.299075 [DQSOSCAuto] RK1, (LSB)MR18= 0xa851, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7039 11:41:15.299643 CH1 RK1: MR19=C0C, MR18=A851
7040 11:41:15.305579 CH1_RK1: MR19=0xC0C, MR18=0xA851, DQSOSC=388, MR23=63, INC=392, DEC=261
7041 11:41:15.308586 [RxdqsGatingPostProcess] freq 400
7042 11:41:15.315534 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7043 11:41:15.318664 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 11:41:15.322062 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 11:41:15.325375 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 11:41:15.328718 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 11:41:15.332306 best DQS0 dly(2T, 0.5T) = (0, 10)
7048 11:41:15.332873 best DQS1 dly(2T, 0.5T) = (0, 10)
7049 11:41:15.335067 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7050 11:41:15.338172 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7051 11:41:15.341889 Pre-setting of DQS Precalculation
7052 11:41:15.348023 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7053 11:41:15.354700 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7054 11:41:15.361750 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7055 11:41:15.362321
7056 11:41:15.362688
7057 11:41:15.365252 [Calibration Summary] 800 Mbps
7058 11:41:15.368385 CH 0, Rank 0
7059 11:41:15.368958 SW Impedance : PASS
7060 11:41:15.371692 DUTY Scan : NO K
7061 11:41:15.372248 ZQ Calibration : PASS
7062 11:41:15.375182 Jitter Meter : NO K
7063 11:41:15.377995 CBT Training : PASS
7064 11:41:15.378547 Write leveling : PASS
7065 11:41:15.381754 RX DQS gating : PASS
7066 11:41:15.384536 RX DQ/DQS(RDDQC) : PASS
7067 11:41:15.385104 TX DQ/DQS : PASS
7068 11:41:15.388231 RX DATLAT : PASS
7069 11:41:15.391386 RX DQ/DQS(Engine): PASS
7070 11:41:15.391950 TX OE : NO K
7071 11:41:15.395054 All Pass.
7072 11:41:15.395609
7073 11:41:15.395972 CH 0, Rank 1
7074 11:41:15.397960 SW Impedance : PASS
7075 11:41:15.398419 DUTY Scan : NO K
7076 11:41:15.401097 ZQ Calibration : PASS
7077 11:41:15.405255 Jitter Meter : NO K
7078 11:41:15.405837 CBT Training : PASS
7079 11:41:15.407982 Write leveling : NO K
7080 11:41:15.411400 RX DQS gating : PASS
7081 11:41:15.411959 RX DQ/DQS(RDDQC) : PASS
7082 11:41:15.414212 TX DQ/DQS : PASS
7083 11:41:15.417797 RX DATLAT : PASS
7084 11:41:15.418378 RX DQ/DQS(Engine): PASS
7085 11:41:15.421045 TX OE : NO K
7086 11:41:15.421525 All Pass.
7087 11:41:15.422017
7088 11:41:15.424125 CH 1, Rank 0
7089 11:41:15.424579 SW Impedance : PASS
7090 11:41:15.427710 DUTY Scan : NO K
7091 11:41:15.431064 ZQ Calibration : PASS
7092 11:41:15.431623 Jitter Meter : NO K
7093 11:41:15.434530 CBT Training : PASS
7094 11:41:15.434988 Write leveling : PASS
7095 11:41:15.437449 RX DQS gating : PASS
7096 11:41:15.440860 RX DQ/DQS(RDDQC) : PASS
7097 11:41:15.441473 TX DQ/DQS : PASS
7098 11:41:15.444217 RX DATLAT : PASS
7099 11:41:15.447364 RX DQ/DQS(Engine): PASS
7100 11:41:15.447930 TX OE : NO K
7101 11:41:15.450643 All Pass.
7102 11:41:15.451100
7103 11:41:15.451459 CH 1, Rank 1
7104 11:41:15.454501 SW Impedance : PASS
7105 11:41:15.455061 DUTY Scan : NO K
7106 11:41:15.457145 ZQ Calibration : PASS
7107 11:41:15.460695 Jitter Meter : NO K
7108 11:41:15.461316 CBT Training : PASS
7109 11:41:15.463725 Write leveling : NO K
7110 11:41:15.467455 RX DQS gating : PASS
7111 11:41:15.468022 RX DQ/DQS(RDDQC) : PASS
7112 11:41:15.470635 TX DQ/DQS : PASS
7113 11:41:15.473978 RX DATLAT : PASS
7114 11:41:15.474541 RX DQ/DQS(Engine): PASS
7115 11:41:15.477171 TX OE : NO K
7116 11:41:15.477636 All Pass.
7117 11:41:15.477998
7118 11:41:15.480431 DramC Write-DBI off
7119 11:41:15.483947 PER_BANK_REFRESH: Hybrid Mode
7120 11:41:15.484513 TX_TRACKING: ON
7121 11:41:15.493874 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7122 11:41:15.497143 [FAST_K] Save calibration result to emmc
7123 11:41:15.500122 dramc_set_vcore_voltage set vcore to 725000
7124 11:41:15.503818 Read voltage for 1600, 0
7125 11:41:15.504383 Vio18 = 0
7126 11:41:15.504755 Vcore = 725000
7127 11:41:15.507232 Vdram = 0
7128 11:41:15.507794 Vddq = 0
7129 11:41:15.508158 Vmddr = 0
7130 11:41:15.513737 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7131 11:41:15.516841 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7132 11:41:15.520082 MEM_TYPE=3, freq_sel=13
7133 11:41:15.523882 sv_algorithm_assistance_LP4_3733
7134 11:41:15.527153 ============ PULL DRAM RESETB DOWN ============
7135 11:41:15.530704 ========== PULL DRAM RESETB DOWN end =========
7136 11:41:15.537049 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7137 11:41:15.540264 ===================================
7138 11:41:15.543758 LPDDR4 DRAM CONFIGURATION
7139 11:41:15.546848 ===================================
7140 11:41:15.547415 EX_ROW_EN[0] = 0x0
7141 11:41:15.550028 EX_ROW_EN[1] = 0x0
7142 11:41:15.550596 LP4Y_EN = 0x0
7143 11:41:15.553667 WORK_FSP = 0x1
7144 11:41:15.554234 WL = 0x5
7145 11:41:15.556491 RL = 0x5
7146 11:41:15.556956 BL = 0x2
7147 11:41:15.560075 RPST = 0x0
7148 11:41:15.560640 RD_PRE = 0x0
7149 11:41:15.563138 WR_PRE = 0x1
7150 11:41:15.563690 WR_PST = 0x1
7151 11:41:15.566491 DBI_WR = 0x0
7152 11:41:15.566967 DBI_RD = 0x0
7153 11:41:15.569715 OTF = 0x1
7154 11:41:15.573207 ===================================
7155 11:41:15.576276 ===================================
7156 11:41:15.576743 ANA top config
7157 11:41:15.579650 ===================================
7158 11:41:15.583608 DLL_ASYNC_EN = 0
7159 11:41:15.586120 ALL_SLAVE_EN = 0
7160 11:41:15.589883 NEW_RANK_MODE = 1
7161 11:41:15.593091 DLL_IDLE_MODE = 1
7162 11:41:15.593650 LP45_APHY_COMB_EN = 1
7163 11:41:15.596075 TX_ODT_DIS = 0
7164 11:41:15.599382 NEW_8X_MODE = 1
7165 11:41:15.603033 ===================================
7166 11:41:15.606208 ===================================
7167 11:41:15.609689 data_rate = 3200
7168 11:41:15.612996 CKR = 1
7169 11:41:15.613568 DQ_P2S_RATIO = 8
7170 11:41:15.616058 ===================================
7171 11:41:15.619067 CA_P2S_RATIO = 8
7172 11:41:15.622501 DQ_CA_OPEN = 0
7173 11:41:15.625570 DQ_SEMI_OPEN = 0
7174 11:41:15.628774 CA_SEMI_OPEN = 0
7175 11:41:15.632442 CA_FULL_RATE = 0
7176 11:41:15.633046 DQ_CKDIV4_EN = 0
7177 11:41:15.635438 CA_CKDIV4_EN = 0
7178 11:41:15.638723 CA_PREDIV_EN = 0
7179 11:41:15.642372 PH8_DLY = 12
7180 11:41:15.645314 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7181 11:41:15.649154 DQ_AAMCK_DIV = 4
7182 11:41:15.652686 CA_AAMCK_DIV = 4
7183 11:41:15.653305 CA_ADMCK_DIV = 4
7184 11:41:15.655420 DQ_TRACK_CA_EN = 0
7185 11:41:15.658682 CA_PICK = 1600
7186 11:41:15.662228 CA_MCKIO = 1600
7187 11:41:15.665235 MCKIO_SEMI = 0
7188 11:41:15.669378 PLL_FREQ = 3068
7189 11:41:15.672172 DQ_UI_PI_RATIO = 32
7190 11:41:15.672731 CA_UI_PI_RATIO = 0
7191 11:41:15.675261 ===================================
7192 11:41:15.678896 ===================================
7193 11:41:15.681906 memory_type:LPDDR4
7194 11:41:15.685013 GP_NUM : 10
7195 11:41:15.685482 SRAM_EN : 1
7196 11:41:15.688586 MD32_EN : 0
7197 11:41:15.691775 ===================================
7198 11:41:15.695047 [ANA_INIT] >>>>>>>>>>>>>>
7199 11:41:15.698686 <<<<<< [CONFIGURE PHASE]: ANA_TX
7200 11:41:15.701890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7201 11:41:15.705223 ===================================
7202 11:41:15.705778 data_rate = 3200,PCW = 0X7600
7203 11:41:15.708505 ===================================
7204 11:41:15.715435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7205 11:41:15.718446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7206 11:41:15.724679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7207 11:41:15.728361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7208 11:41:15.731495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7209 11:41:15.734731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7210 11:41:15.737785 [ANA_INIT] flow start
7211 11:41:15.741849 [ANA_INIT] PLL >>>>>>>>
7212 11:41:15.742424 [ANA_INIT] PLL <<<<<<<<
7213 11:41:15.745399 [ANA_INIT] MIDPI >>>>>>>>
7214 11:41:15.748340 [ANA_INIT] MIDPI <<<<<<<<
7215 11:41:15.748897 [ANA_INIT] DLL >>>>>>>>
7216 11:41:15.751164 [ANA_INIT] DLL <<<<<<<<
7217 11:41:15.754607 [ANA_INIT] flow end
7218 11:41:15.757657 ============ LP4 DIFF to SE enter ============
7219 11:41:15.761420 ============ LP4 DIFF to SE exit ============
7220 11:41:15.764595 [ANA_INIT] <<<<<<<<<<<<<
7221 11:41:15.768195 [Flow] Enable top DCM control >>>>>
7222 11:41:15.771367 [Flow] Enable top DCM control <<<<<
7223 11:41:15.774496 Enable DLL master slave shuffle
7224 11:41:15.781055 ==============================================================
7225 11:41:15.781647 Gating Mode config
7226 11:41:15.787183 ==============================================================
7227 11:41:15.787751 Config description:
7228 11:41:15.797645 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7229 11:41:15.803858 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7230 11:41:15.810905 SELPH_MODE 0: By rank 1: By Phase
7231 11:41:15.813491 ==============================================================
7232 11:41:15.816892 GAT_TRACK_EN = 1
7233 11:41:15.820889 RX_GATING_MODE = 2
7234 11:41:15.824177 RX_GATING_TRACK_MODE = 2
7235 11:41:15.826914 SELPH_MODE = 1
7236 11:41:15.830141 PICG_EARLY_EN = 1
7237 11:41:15.833478 VALID_LAT_VALUE = 1
7238 11:41:15.839979 ==============================================================
7239 11:41:15.843555 Enter into Gating configuration >>>>
7240 11:41:15.846740 Exit from Gating configuration <<<<
7241 11:41:15.850056 Enter into DVFS_PRE_config >>>>>
7242 11:41:15.859806 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7243 11:41:15.863324 Exit from DVFS_PRE_config <<<<<
7244 11:41:15.866704 Enter into PICG configuration >>>>
7245 11:41:15.869954 Exit from PICG configuration <<<<
7246 11:41:15.873213 [RX_INPUT] configuration >>>>>
7247 11:41:15.873767 [RX_INPUT] configuration <<<<<
7248 11:41:15.879795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7249 11:41:15.886041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7250 11:41:15.889326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7251 11:41:15.896804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7252 11:41:15.902857 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7253 11:41:15.909284 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7254 11:41:15.912222 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7255 11:41:15.919498 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7256 11:41:15.922415 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7257 11:41:15.925908 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7258 11:41:15.928962 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7259 11:41:15.936124 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7260 11:41:15.938744 ===================================
7261 11:41:15.939207 LPDDR4 DRAM CONFIGURATION
7262 11:41:15.942300 ===================================
7263 11:41:15.945779 EX_ROW_EN[0] = 0x0
7264 11:41:15.948558 EX_ROW_EN[1] = 0x0
7265 11:41:15.949158 LP4Y_EN = 0x0
7266 11:41:15.952214 WORK_FSP = 0x1
7267 11:41:15.952770 WL = 0x5
7268 11:41:15.955655 RL = 0x5
7269 11:41:15.956210 BL = 0x2
7270 11:41:15.958639 RPST = 0x0
7271 11:41:15.959276 RD_PRE = 0x0
7272 11:41:15.962107 WR_PRE = 0x1
7273 11:41:15.962840 WR_PST = 0x1
7274 11:41:15.965351 DBI_WR = 0x0
7275 11:41:15.965910 DBI_RD = 0x0
7276 11:41:15.968551 OTF = 0x1
7277 11:41:15.971889 ===================================
7278 11:41:15.975101 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7279 11:41:15.978626 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7280 11:41:15.984852 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 11:41:15.988514 ===================================
7282 11:41:15.989252 LPDDR4 DRAM CONFIGURATION
7283 11:41:15.991726 ===================================
7284 11:41:15.995095 EX_ROW_EN[0] = 0x10
7285 11:41:15.998148 EX_ROW_EN[1] = 0x0
7286 11:41:15.998609 LP4Y_EN = 0x0
7287 11:41:16.001268 WORK_FSP = 0x1
7288 11:41:16.001863 WL = 0x5
7289 11:41:16.005279 RL = 0x5
7290 11:41:16.005850 BL = 0x2
7291 11:41:16.008194 RPST = 0x0
7292 11:41:16.008748 RD_PRE = 0x0
7293 11:41:16.011075 WR_PRE = 0x1
7294 11:41:16.011536 WR_PST = 0x1
7295 11:41:16.014542 DBI_WR = 0x0
7296 11:41:16.015000 DBI_RD = 0x0
7297 11:41:16.017748 OTF = 0x1
7298 11:41:16.021341 ===================================
7299 11:41:16.027587 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7300 11:41:16.028050 ==
7301 11:41:16.030939 Dram Type= 6, Freq= 0, CH_0, rank 0
7302 11:41:16.034265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 11:41:16.034848 ==
7304 11:41:16.037628 [Duty_Offset_Calibration]
7305 11:41:16.038085 B0:2 B1:0 CA:1
7306 11:41:16.038449
7307 11:41:16.040899 [DutyScan_Calibration_Flow] k_type=0
7308 11:41:16.051195
7309 11:41:16.051493 ==CLK 0==
7310 11:41:16.054349 Final CLK duty delay cell = -4
7311 11:41:16.057386 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7312 11:41:16.060706 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7313 11:41:16.064281 [-4] AVG Duty = 4906%(X100)
7314 11:41:16.064600
7315 11:41:16.067567 CH0 CLK Duty spec in!! Max-Min= 187%
7316 11:41:16.071090 [DutyScan_Calibration_Flow] ====Done====
7317 11:41:16.071422
7318 11:41:16.074201 [DutyScan_Calibration_Flow] k_type=1
7319 11:41:16.090381
7320 11:41:16.090719 ==DQS 0 ==
7321 11:41:16.093790 Final DQS duty delay cell = 0
7322 11:41:16.097341 [0] MAX Duty = 5249%(X100), DQS PI = 32
7323 11:41:16.100774 [0] MIN Duty = 4969%(X100), DQS PI = 0
7324 11:41:16.103837 [0] AVG Duty = 5109%(X100)
7325 11:41:16.104168
7326 11:41:16.104426 ==DQS 1 ==
7327 11:41:16.107454 Final DQS duty delay cell = -4
7328 11:41:16.110243 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7329 11:41:16.113850 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7330 11:41:16.117092 [-4] AVG Duty = 4984%(X100)
7331 11:41:16.117514
7332 11:41:16.120136 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7333 11:41:16.120463
7334 11:41:16.123379 CH0 DQS 1 Duty spec in!! Max-Min= 219%
7335 11:41:16.126763 [DutyScan_Calibration_Flow] ====Done====
7336 11:41:16.127191
7337 11:41:16.130018 [DutyScan_Calibration_Flow] k_type=3
7338 11:41:16.147402
7339 11:41:16.147961 ==DQM 0 ==
7340 11:41:16.150736 Final DQM duty delay cell = 0
7341 11:41:16.154119 [0] MAX Duty = 5124%(X100), DQS PI = 26
7342 11:41:16.157331 [0] MIN Duty = 4844%(X100), DQS PI = 0
7343 11:41:16.160467 [0] AVG Duty = 4984%(X100)
7344 11:41:16.160933
7345 11:41:16.161357 ==DQM 1 ==
7346 11:41:16.163937 Final DQM duty delay cell = -4
7347 11:41:16.167068 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7348 11:41:16.170529 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7349 11:41:16.173717 [-4] AVG Duty = 4891%(X100)
7350 11:41:16.174287
7351 11:41:16.176862 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7352 11:41:16.177449
7353 11:41:16.180128 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7354 11:41:16.183802 [DutyScan_Calibration_Flow] ====Done====
7355 11:41:16.184372
7356 11:41:16.186963 [DutyScan_Calibration_Flow] k_type=2
7357 11:41:16.204804
7358 11:41:16.205425 ==DQ 0 ==
7359 11:41:16.207903 Final DQ duty delay cell = 0
7360 11:41:16.211042 [0] MAX Duty = 5124%(X100), DQS PI = 32
7361 11:41:16.214588 [0] MIN Duty = 5000%(X100), DQS PI = 16
7362 11:41:16.217704 [0] AVG Duty = 5062%(X100)
7363 11:41:16.218155
7364 11:41:16.218507 ==DQ 1 ==
7365 11:41:16.220817 Final DQ duty delay cell = 0
7366 11:41:16.224332 [0] MAX Duty = 4969%(X100), DQS PI = 42
7367 11:41:16.227753 [0] MIN Duty = 4875%(X100), DQS PI = 10
7368 11:41:16.231353 [0] AVG Duty = 4922%(X100)
7369 11:41:16.231820
7370 11:41:16.234521 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7371 11:41:16.234932
7372 11:41:16.237502 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7373 11:41:16.240825 [DutyScan_Calibration_Flow] ====Done====
7374 11:41:16.241263 ==
7375 11:41:16.244248 Dram Type= 6, Freq= 0, CH_1, rank 0
7376 11:41:16.247490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7377 11:41:16.247915 ==
7378 11:41:16.250631 [Duty_Offset_Calibration]
7379 11:41:16.251082 B0:0 B1:-1 CA:2
7380 11:41:16.251425
7381 11:41:16.254073 [DutyScan_Calibration_Flow] k_type=0
7382 11:41:16.264997
7383 11:41:16.265404 ==CLK 0==
7384 11:41:16.268337 Final CLK duty delay cell = 0
7385 11:41:16.271393 [0] MAX Duty = 5187%(X100), DQS PI = 14
7386 11:41:16.274912 [0] MIN Duty = 4938%(X100), DQS PI = 44
7387 11:41:16.278088 [0] AVG Duty = 5062%(X100)
7388 11:41:16.278495
7389 11:41:16.281503 CH1 CLK Duty spec in!! Max-Min= 249%
7390 11:41:16.284854 [DutyScan_Calibration_Flow] ====Done====
7391 11:41:16.285386
7392 11:41:16.287898 [DutyScan_Calibration_Flow] k_type=1
7393 11:41:16.305210
7394 11:41:16.305750 ==DQS 0 ==
7395 11:41:16.308285 Final DQS duty delay cell = 0
7396 11:41:16.311374 [0] MAX Duty = 5124%(X100), DQS PI = 26
7397 11:41:16.314732 [0] MIN Duty = 5000%(X100), DQS PI = 0
7398 11:41:16.317834 [0] AVG Duty = 5062%(X100)
7399 11:41:16.318382
7400 11:41:16.318739 ==DQS 1 ==
7401 11:41:16.321021 Final DQS duty delay cell = 0
7402 11:41:16.324676 [0] MAX Duty = 5187%(X100), DQS PI = 0
7403 11:41:16.327929 [0] MIN Duty = 4844%(X100), DQS PI = 32
7404 11:41:16.331240 [0] AVG Duty = 5015%(X100)
7405 11:41:16.331796
7406 11:41:16.334395 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7407 11:41:16.334848
7408 11:41:16.337848 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7409 11:41:16.340820 [DutyScan_Calibration_Flow] ====Done====
7410 11:41:16.341318
7411 11:41:16.344211 [DutyScan_Calibration_Flow] k_type=3
7412 11:41:16.362239
7413 11:41:16.362783 ==DQM 0 ==
7414 11:41:16.365667 Final DQM duty delay cell = 4
7415 11:41:16.369181 [4] MAX Duty = 5125%(X100), DQS PI = 6
7416 11:41:16.372073 [4] MIN Duty = 5000%(X100), DQS PI = 30
7417 11:41:16.375364 [4] AVG Duty = 5062%(X100)
7418 11:41:16.375905
7419 11:41:16.376261 ==DQM 1 ==
7420 11:41:16.378667 Final DQM duty delay cell = 0
7421 11:41:16.382088 [0] MAX Duty = 5281%(X100), DQS PI = 58
7422 11:41:16.385630 [0] MIN Duty = 4876%(X100), DQS PI = 34
7423 11:41:16.388805 [0] AVG Duty = 5078%(X100)
7424 11:41:16.389420
7425 11:41:16.392027 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7426 11:41:16.392584
7427 11:41:16.395385 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7428 11:41:16.398492 [DutyScan_Calibration_Flow] ====Done====
7429 11:41:16.399049
7430 11:41:16.401464 [DutyScan_Calibration_Flow] k_type=2
7431 11:41:16.419724
7432 11:41:16.420275 ==DQ 0 ==
7433 11:41:16.422333 Final DQ duty delay cell = 0
7434 11:41:16.425885 [0] MAX Duty = 5093%(X100), DQS PI = 20
7435 11:41:16.429803 [0] MIN Duty = 4969%(X100), DQS PI = 46
7436 11:41:16.430377 [0] AVG Duty = 5031%(X100)
7437 11:41:16.432657
7438 11:41:16.433259 ==DQ 1 ==
7439 11:41:16.436165 Final DQ duty delay cell = 0
7440 11:41:16.438990 [0] MAX Duty = 5062%(X100), DQS PI = 2
7441 11:41:16.442458 [0] MIN Duty = 4813%(X100), DQS PI = 34
7442 11:41:16.443036 [0] AVG Duty = 4937%(X100)
7443 11:41:16.443434
7444 11:41:16.445798 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7445 11:41:16.449164
7446 11:41:16.452166 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7447 11:41:16.455721 [DutyScan_Calibration_Flow] ====Done====
7448 11:41:16.459073 nWR fixed to 30
7449 11:41:16.459542 [ModeRegInit_LP4] CH0 RK0
7450 11:41:16.462352 [ModeRegInit_LP4] CH0 RK1
7451 11:41:16.465597 [ModeRegInit_LP4] CH1 RK0
7452 11:41:16.469021 [ModeRegInit_LP4] CH1 RK1
7453 11:41:16.469578 match AC timing 5
7454 11:41:16.475647 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7455 11:41:16.478993 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7456 11:41:16.482468 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7457 11:41:16.488558 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7458 11:41:16.491964 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7459 11:41:16.492521 [MiockJmeterHQA]
7460 11:41:16.492891
7461 11:41:16.495379 [DramcMiockJmeter] u1RxGatingPI = 0
7462 11:41:16.498641 0 : 4363, 4138
7463 11:41:16.499202 4 : 4260, 4032
7464 11:41:16.501853 8 : 4363, 4138
7465 11:41:16.502416 12 : 4253, 4026
7466 11:41:16.502798 16 : 4254, 4029
7467 11:41:16.504910 20 : 4368, 4140
7468 11:41:16.505448 24 : 4252, 4027
7469 11:41:16.508362 28 : 4253, 4027
7470 11:41:16.508831 32 : 4252, 4026
7471 11:41:16.511935 36 : 4255, 4029
7472 11:41:16.512527 40 : 4253, 4027
7473 11:41:16.514888 44 : 4249, 4027
7474 11:41:16.515359 48 : 4365, 4140
7475 11:41:16.515732 52 : 4252, 4027
7476 11:41:16.518403 56 : 4252, 4029
7477 11:41:16.518971 60 : 4250, 4027
7478 11:41:16.521642 64 : 4361, 4138
7479 11:41:16.522144 68 : 4250, 4027
7480 11:41:16.524806 72 : 4360, 4138
7481 11:41:16.525333 76 : 4249, 4027
7482 11:41:16.528780 80 : 4250, 4027
7483 11:41:16.529412 84 : 4250, 4027
7484 11:41:16.529794 88 : 4253, 3707
7485 11:41:16.531717 92 : 4360, 0
7486 11:41:16.532285 96 : 4250, 0
7487 11:41:16.535053 100 : 4252, 0
7488 11:41:16.535617 104 : 4363, 0
7489 11:41:16.535995 108 : 4360, 0
7490 11:41:16.538147 112 : 4363, 0
7491 11:41:16.538686 116 : 4253, 0
7492 11:41:16.541581 120 : 4360, 0
7493 11:41:16.542147 124 : 4360, 0
7494 11:41:16.542526 128 : 4253, 0
7495 11:41:16.544813 132 : 4252, 0
7496 11:41:16.545406 136 : 4250, 0
7497 11:41:16.545785 140 : 4253, 0
7498 11:41:16.548206 144 : 4252, 0
7499 11:41:16.548777 148 : 4250, 0
7500 11:41:16.551558 152 : 4253, 0
7501 11:41:16.552130 156 : 4363, 0
7502 11:41:16.552620 160 : 4360, 0
7503 11:41:16.554533 164 : 4250, 0
7504 11:41:16.555002 168 : 4253, 0
7505 11:41:16.557962 172 : 4360, 0
7506 11:41:16.558433 176 : 4361, 0
7507 11:41:16.558812 180 : 4250, 0
7508 11:41:16.561151 184 : 4252, 0
7509 11:41:16.561688 188 : 4250, 0
7510 11:41:16.564649 192 : 4252, 0
7511 11:41:16.565145 196 : 4254, 0
7512 11:41:16.565524 200 : 4250, 1
7513 11:41:16.568022 204 : 4253, 2501
7514 11:41:16.568492 208 : 4250, 4027
7515 11:41:16.571163 212 : 4250, 4027
7516 11:41:16.571750 216 : 4360, 4138
7517 11:41:16.574687 220 : 4250, 4027
7518 11:41:16.575295 224 : 4250, 4027
7519 11:41:16.577753 228 : 4361, 4137
7520 11:41:16.578220 232 : 4361, 4138
7521 11:41:16.581338 236 : 4250, 4027
7522 11:41:16.581911 240 : 4363, 4140
7523 11:41:16.584412 244 : 4360, 4138
7524 11:41:16.584875 248 : 4252, 4027
7525 11:41:16.585304 252 : 4249, 4027
7526 11:41:16.587495 256 : 4252, 4029
7527 11:41:16.588218 260 : 4250, 4027
7528 11:41:16.591277 264 : 4250, 4027
7529 11:41:16.591841 268 : 4250, 4027
7530 11:41:16.594470 272 : 4252, 4029
7531 11:41:16.595036 276 : 4250, 4027
7532 11:41:16.597859 280 : 4360, 4138
7533 11:41:16.598424 284 : 4360, 4138
7534 11:41:16.601237 288 : 4250, 4027
7535 11:41:16.601800 292 : 4363, 4140
7536 11:41:16.604267 296 : 4360, 4138
7537 11:41:16.604955 300 : 4250, 4027
7538 11:41:16.607459 304 : 4250, 4027
7539 11:41:16.608022 308 : 4250, 4027
7540 11:41:16.611139 312 : 4250, 3978
7541 11:41:16.611710 316 : 4250, 2233
7542 11:41:16.612082 320 : 4249, 14
7543 11:41:16.612423
7544 11:41:16.614157 MIOCK jitter meter ch=0
7545 11:41:16.614751
7546 11:41:16.617258 1T = (320-92) = 228 dly cells
7547 11:41:16.624038 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7548 11:41:16.624499 ==
7549 11:41:16.627416 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 11:41:16.630724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 11:41:16.631459 ==
7552 11:41:16.637280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7553 11:41:16.640619 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7554 11:41:16.643923 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7555 11:41:16.650843 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7556 11:41:16.659320 [CA 0] Center 42 (12~72) winsize 61
7557 11:41:16.662812 [CA 1] Center 42 (12~72) winsize 61
7558 11:41:16.666206 [CA 2] Center 37 (7~67) winsize 61
7559 11:41:16.669263 [CA 3] Center 37 (7~67) winsize 61
7560 11:41:16.672805 [CA 4] Center 36 (6~66) winsize 61
7561 11:41:16.676023 [CA 5] Center 35 (5~65) winsize 61
7562 11:41:16.676596
7563 11:41:16.679418 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7564 11:41:16.680016
7565 11:41:16.682524 [CATrainingPosCal] consider 1 rank data
7566 11:41:16.685469 u2DelayCellTimex100 = 285/100 ps
7567 11:41:16.692155 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7568 11:41:16.695573 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7569 11:41:16.698944 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7570 11:41:16.702173 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7571 11:41:16.705343 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7572 11:41:16.708603 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7573 11:41:16.709201
7574 11:41:16.712156 CA PerBit enable=1, Macro0, CA PI delay=35
7575 11:41:16.712717
7576 11:41:16.715427 [CBTSetCACLKResult] CA Dly = 35
7577 11:41:16.718856 CS Dly: 9 (0~40)
7578 11:41:16.721794 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7579 11:41:16.724956 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7580 11:41:16.725458 ==
7581 11:41:16.728710 Dram Type= 6, Freq= 0, CH_0, rank 1
7582 11:41:16.735531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 11:41:16.736092 ==
7584 11:41:16.738657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7585 11:41:16.745100 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7586 11:41:16.748342 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7587 11:41:16.754987 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7588 11:41:16.762931 [CA 0] Center 43 (13~74) winsize 62
7589 11:41:16.765773 [CA 1] Center 43 (13~73) winsize 61
7590 11:41:16.769601 [CA 2] Center 38 (9~68) winsize 60
7591 11:41:16.772397 [CA 3] Center 38 (9~68) winsize 60
7592 11:41:16.775641 [CA 4] Center 37 (7~67) winsize 61
7593 11:41:16.778950 [CA 5] Center 36 (6~66) winsize 61
7594 11:41:16.779515
7595 11:41:16.782518 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7596 11:41:16.782983
7597 11:41:16.789011 [CATrainingPosCal] consider 2 rank data
7598 11:41:16.789572 u2DelayCellTimex100 = 285/100 ps
7599 11:41:16.795442 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7600 11:41:16.798790 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7601 11:41:16.801912 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7602 11:41:16.805460 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7603 11:41:16.808795 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7604 11:41:16.811778 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7605 11:41:16.812339
7606 11:41:16.815266 CA PerBit enable=1, Macro0, CA PI delay=35
7607 11:41:16.815726
7608 11:41:16.818600 [CBTSetCACLKResult] CA Dly = 35
7609 11:41:16.821813 CS Dly: 10 (0~43)
7610 11:41:16.825114 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7611 11:41:16.828360 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7612 11:41:16.828916
7613 11:41:16.831951 ----->DramcWriteLeveling(PI) begin...
7614 11:41:16.835319 ==
7615 11:41:16.837997 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 11:41:16.841494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 11:41:16.841952 ==
7618 11:41:16.844509 Write leveling (Byte 0): 37 => 37
7619 11:41:16.847861 Write leveling (Byte 1): 33 => 33
7620 11:41:16.851546 DramcWriteLeveling(PI) end<-----
7621 11:41:16.852164
7622 11:41:16.852537 ==
7623 11:41:16.854934 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 11:41:16.857688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 11:41:16.858151 ==
7626 11:41:16.861105 [Gating] SW mode calibration
7627 11:41:16.867812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7628 11:41:16.874284 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7629 11:41:16.878044 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 11:41:16.881048 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 11:41:16.887453 1 4 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7632 11:41:16.891047 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7633 11:41:16.894620 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7634 11:41:16.900715 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7635 11:41:16.903876 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 11:41:16.907194 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 11:41:16.913829 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 11:41:16.917322 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 11:41:16.920571 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7640 11:41:16.927316 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7641 11:41:16.930324 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7642 11:41:16.934262 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7643 11:41:16.940597 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 11:41:16.944192 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 11:41:16.947358 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 11:41:16.953757 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7647 11:41:16.957057 1 6 8 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
7648 11:41:16.960701 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7649 11:41:16.966976 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7650 11:41:16.970222 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7651 11:41:16.973378 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 11:41:16.980219 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 11:41:16.983235 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 11:41:16.986925 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 11:41:16.993292 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7656 11:41:16.996931 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7657 11:41:17.000148 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7658 11:41:17.006525 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7659 11:41:17.009577 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:41:17.013252 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:41:17.019942 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:41:17.022887 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:41:17.026130 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:41:17.033067 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:41:17.036295 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 11:41:17.039664 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 11:41:17.046274 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:41:17.049152 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 11:41:17.052700 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:41:17.059725 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:41:17.062379 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7672 11:41:17.066208 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7673 11:41:17.069347 Total UI for P1: 0, mck2ui 16
7674 11:41:17.072536 best dqsien dly found for B0: ( 1, 9, 8)
7675 11:41:17.075894 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7676 11:41:17.082801 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7677 11:41:17.085481 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 11:41:17.089138 Total UI for P1: 0, mck2ui 16
7679 11:41:17.092642 best dqsien dly found for B1: ( 1, 9, 20)
7680 11:41:17.095588 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7681 11:41:17.098788 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7682 11:41:17.099260
7683 11:41:17.102195 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7684 11:41:17.108680 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7685 11:41:17.109367 [Gating] SW calibration Done
7686 11:41:17.109778 ==
7687 11:41:17.112189 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 11:41:17.118836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 11:41:17.119538 ==
7690 11:41:17.119985 RX Vref Scan: 0
7691 11:41:17.120345
7692 11:41:17.121852 RX Vref 0 -> 0, step: 1
7693 11:41:17.122319
7694 11:41:17.125397 RX Delay 0 -> 252, step: 8
7695 11:41:17.128843 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7696 11:41:17.132015 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7697 11:41:17.135875 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7698 11:41:17.138672 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7699 11:41:17.145337 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7700 11:41:17.148699 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7701 11:41:17.151946 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7702 11:41:17.155006 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7703 11:41:17.158466 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7704 11:41:17.165143 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7705 11:41:17.168572 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7706 11:41:17.171760 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7707 11:41:17.175101 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7708 11:41:17.182012 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7709 11:41:17.185079 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7710 11:41:17.188716 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7711 11:41:17.189347 ==
7712 11:41:17.191874 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 11:41:17.195025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 11:41:17.195589 ==
7715 11:41:17.198152 DQS Delay:
7716 11:41:17.198711 DQS0 = 0, DQS1 = 0
7717 11:41:17.201246 DQM Delay:
7718 11:41:17.201712 DQM0 = 138, DQM1 = 125
7719 11:41:17.202082 DQ Delay:
7720 11:41:17.204733 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7721 11:41:17.211301 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7722 11:41:17.214608 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
7723 11:41:17.217940 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7724 11:41:17.218404
7725 11:41:17.218767
7726 11:41:17.219106 ==
7727 11:41:17.221044 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 11:41:17.224247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 11:41:17.224715 ==
7730 11:41:17.225200
7731 11:41:17.225611
7732 11:41:17.227584 TX Vref Scan disable
7733 11:41:17.231032 == TX Byte 0 ==
7734 11:41:17.234589 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7735 11:41:17.237847 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7736 11:41:17.240854 == TX Byte 1 ==
7737 11:41:17.244337 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7738 11:41:17.247798 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7739 11:41:17.248355 ==
7740 11:41:17.251147 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 11:41:17.257430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 11:41:17.257991 ==
7743 11:41:17.269336
7744 11:41:17.272470 TX Vref early break, caculate TX vref
7745 11:41:17.275930 TX Vref=16, minBit 8, minWin=22, winSum=375
7746 11:41:17.279188 TX Vref=18, minBit 4, minWin=23, winSum=388
7747 11:41:17.282286 TX Vref=20, minBit 0, minWin=24, winSum=394
7748 11:41:17.285684 TX Vref=22, minBit 8, minWin=24, winSum=405
7749 11:41:17.289071 TX Vref=24, minBit 2, minWin=25, winSum=415
7750 11:41:17.295260 TX Vref=26, minBit 0, minWin=26, winSum=421
7751 11:41:17.298826 TX Vref=28, minBit 1, minWin=26, winSum=431
7752 11:41:17.302291 TX Vref=30, minBit 0, minWin=25, winSum=423
7753 11:41:17.305587 TX Vref=32, minBit 1, minWin=25, winSum=415
7754 11:41:17.308477 TX Vref=34, minBit 2, minWin=24, winSum=407
7755 11:41:17.315235 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
7756 11:41:17.315798
7757 11:41:17.318881 Final TX Range 0 Vref 28
7758 11:41:17.319342
7759 11:41:17.319707 ==
7760 11:41:17.321665 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 11:41:17.325167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 11:41:17.325630 ==
7763 11:41:17.326039
7764 11:41:17.326407
7765 11:41:17.328413 TX Vref Scan disable
7766 11:41:17.335033 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7767 11:41:17.335576 == TX Byte 0 ==
7768 11:41:17.338301 u2DelayCellOfst[0]=10 cells (3 PI)
7769 11:41:17.341534 u2DelayCellOfst[1]=17 cells (5 PI)
7770 11:41:17.344772 u2DelayCellOfst[2]=10 cells (3 PI)
7771 11:41:17.348257 u2DelayCellOfst[3]=10 cells (3 PI)
7772 11:41:17.352033 u2DelayCellOfst[4]=6 cells (2 PI)
7773 11:41:17.354635 u2DelayCellOfst[5]=0 cells (0 PI)
7774 11:41:17.358049 u2DelayCellOfst[6]=17 cells (5 PI)
7775 11:41:17.361297 u2DelayCellOfst[7]=13 cells (4 PI)
7776 11:41:17.364546 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7777 11:41:17.368103 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7778 11:41:17.371521 == TX Byte 1 ==
7779 11:41:17.374633 u2DelayCellOfst[8]=3 cells (1 PI)
7780 11:41:17.375104 u2DelayCellOfst[9]=0 cells (0 PI)
7781 11:41:17.378313 u2DelayCellOfst[10]=6 cells (2 PI)
7782 11:41:17.381350 u2DelayCellOfst[11]=3 cells (1 PI)
7783 11:41:17.384906 u2DelayCellOfst[12]=13 cells (4 PI)
7784 11:41:17.387834 u2DelayCellOfst[13]=13 cells (4 PI)
7785 11:41:17.391069 u2DelayCellOfst[14]=17 cells (5 PI)
7786 11:41:17.394637 u2DelayCellOfst[15]=10 cells (3 PI)
7787 11:41:17.401031 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7788 11:41:17.404337 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7789 11:41:17.404758 DramC Write-DBI on
7790 11:41:17.405139 ==
7791 11:41:17.407431 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 11:41:17.414481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 11:41:17.414905 ==
7794 11:41:17.415237
7795 11:41:17.415541
7796 11:41:17.415835 TX Vref Scan disable
7797 11:41:17.418040 == TX Byte 0 ==
7798 11:41:17.421447 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7799 11:41:17.424723 == TX Byte 1 ==
7800 11:41:17.427909 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7801 11:41:17.431538 DramC Write-DBI off
7802 11:41:17.432079
7803 11:41:17.432422 [DATLAT]
7804 11:41:17.432805 Freq=1600, CH0 RK0
7805 11:41:17.433172
7806 11:41:17.434850 DATLAT Default: 0xf
7807 11:41:17.437876 0, 0xFFFF, sum = 0
7808 11:41:17.438335 1, 0xFFFF, sum = 0
7809 11:41:17.441736 2, 0xFFFF, sum = 0
7810 11:41:17.442163 3, 0xFFFF, sum = 0
7811 11:41:17.444483 4, 0xFFFF, sum = 0
7812 11:41:17.444907 5, 0xFFFF, sum = 0
7813 11:41:17.447925 6, 0xFFFF, sum = 0
7814 11:41:17.448349 7, 0xFFFF, sum = 0
7815 11:41:17.451027 8, 0xFFFF, sum = 0
7816 11:41:17.451453 9, 0xFFFF, sum = 0
7817 11:41:17.454455 10, 0xFFFF, sum = 0
7818 11:41:17.454958 11, 0xFFFF, sum = 0
7819 11:41:17.457702 12, 0xFFFF, sum = 0
7820 11:41:17.458127 13, 0xFFFF, sum = 0
7821 11:41:17.461183 14, 0x0, sum = 1
7822 11:41:17.461605 15, 0x0, sum = 2
7823 11:41:17.464547 16, 0x0, sum = 3
7824 11:41:17.465163 17, 0x0, sum = 4
7825 11:41:17.467579 best_step = 15
7826 11:41:17.468081
7827 11:41:17.468534 ==
7828 11:41:17.471165 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 11:41:17.474583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 11:41:17.475184 ==
7831 11:41:17.477717 RX Vref Scan: 1
7832 11:41:17.478263
7833 11:41:17.478799 Set Vref Range= 24 -> 127
7834 11:41:17.479346
7835 11:41:17.481042 RX Vref 24 -> 127, step: 1
7836 11:41:17.481600
7837 11:41:17.484288 RX Delay 19 -> 252, step: 4
7838 11:41:17.484880
7839 11:41:17.487716 Set Vref, RX VrefLevel [Byte0]: 24
7840 11:41:17.491023 [Byte1]: 24
7841 11:41:17.491450
7842 11:41:17.494280 Set Vref, RX VrefLevel [Byte0]: 25
7843 11:41:17.497411 [Byte1]: 25
7844 11:41:17.500871
7845 11:41:17.501340 Set Vref, RX VrefLevel [Byte0]: 26
7846 11:41:17.504083 [Byte1]: 26
7847 11:41:17.508233
7848 11:41:17.508658 Set Vref, RX VrefLevel [Byte0]: 27
7849 11:41:17.511652 [Byte1]: 27
7850 11:41:17.515884
7851 11:41:17.516305 Set Vref, RX VrefLevel [Byte0]: 28
7852 11:41:17.519325 [Byte1]: 28
7853 11:41:17.523617
7854 11:41:17.524041 Set Vref, RX VrefLevel [Byte0]: 29
7855 11:41:17.527319 [Byte1]: 29
7856 11:41:17.531276
7857 11:41:17.531696 Set Vref, RX VrefLevel [Byte0]: 30
7858 11:41:17.534559 [Byte1]: 30
7859 11:41:17.538767
7860 11:41:17.539191 Set Vref, RX VrefLevel [Byte0]: 31
7861 11:41:17.542201 [Byte1]: 31
7862 11:41:17.546142
7863 11:41:17.546630 Set Vref, RX VrefLevel [Byte0]: 32
7864 11:41:17.549801 [Byte1]: 32
7865 11:41:17.553970
7866 11:41:17.554382 Set Vref, RX VrefLevel [Byte0]: 33
7867 11:41:17.557362 [Byte1]: 33
7868 11:41:17.562049
7869 11:41:17.562562 Set Vref, RX VrefLevel [Byte0]: 34
7870 11:41:17.564734 [Byte1]: 34
7871 11:41:17.569327
7872 11:41:17.569838 Set Vref, RX VrefLevel [Byte0]: 35
7873 11:41:17.572547 [Byte1]: 35
7874 11:41:17.577239
7875 11:41:17.577758 Set Vref, RX VrefLevel [Byte0]: 36
7876 11:41:17.580124 [Byte1]: 36
7877 11:41:17.584487
7878 11:41:17.585037 Set Vref, RX VrefLevel [Byte0]: 37
7879 11:41:17.587646 [Byte1]: 37
7880 11:41:17.592050
7881 11:41:17.592565 Set Vref, RX VrefLevel [Byte0]: 38
7882 11:41:17.598612 [Byte1]: 38
7883 11:41:17.599181
7884 11:41:17.601336 Set Vref, RX VrefLevel [Byte0]: 39
7885 11:41:17.604654 [Byte1]: 39
7886 11:41:17.605233
7887 11:41:17.607932 Set Vref, RX VrefLevel [Byte0]: 40
7888 11:41:17.611107 [Byte1]: 40
7889 11:41:17.614278
7890 11:41:17.614695 Set Vref, RX VrefLevel [Byte0]: 41
7891 11:41:17.617874 [Byte1]: 41
7892 11:41:17.622026
7893 11:41:17.622437 Set Vref, RX VrefLevel [Byte0]: 42
7894 11:41:17.625436 [Byte1]: 42
7895 11:41:17.629674
7896 11:41:17.630191 Set Vref, RX VrefLevel [Byte0]: 43
7897 11:41:17.632712 [Byte1]: 43
7898 11:41:17.637083
7899 11:41:17.637497 Set Vref, RX VrefLevel [Byte0]: 44
7900 11:41:17.640437 [Byte1]: 44
7901 11:41:17.644857
7902 11:41:17.645437 Set Vref, RX VrefLevel [Byte0]: 45
7903 11:41:17.647803 [Byte1]: 45
7904 11:41:17.652600
7905 11:41:17.653219 Set Vref, RX VrefLevel [Byte0]: 46
7906 11:41:17.655717 [Byte1]: 46
7907 11:41:17.660519
7908 11:41:17.661076 Set Vref, RX VrefLevel [Byte0]: 47
7909 11:41:17.663220 [Byte1]: 47
7910 11:41:17.667910
7911 11:41:17.668428 Set Vref, RX VrefLevel [Byte0]: 48
7912 11:41:17.671231 [Byte1]: 48
7913 11:41:17.675498
7914 11:41:17.676018 Set Vref, RX VrefLevel [Byte0]: 49
7915 11:41:17.678489 [Byte1]: 49
7916 11:41:17.683432
7917 11:41:17.683998 Set Vref, RX VrefLevel [Byte0]: 50
7918 11:41:17.686125 [Byte1]: 50
7919 11:41:17.690325
7920 11:41:17.690942 Set Vref, RX VrefLevel [Byte0]: 51
7921 11:41:17.693436 [Byte1]: 51
7922 11:41:17.697748
7923 11:41:17.698378 Set Vref, RX VrefLevel [Byte0]: 52
7924 11:41:17.701020 [Byte1]: 52
7925 11:41:17.705249
7926 11:41:17.705830 Set Vref, RX VrefLevel [Byte0]: 53
7927 11:41:17.708478 [Byte1]: 53
7928 11:41:17.712715
7929 11:41:17.712824 Set Vref, RX VrefLevel [Byte0]: 54
7930 11:41:17.715691 [Byte1]: 54
7931 11:41:17.719945
7932 11:41:17.720044 Set Vref, RX VrefLevel [Byte0]: 55
7933 11:41:17.723591 [Byte1]: 55
7934 11:41:17.727818
7935 11:41:17.727901 Set Vref, RX VrefLevel [Byte0]: 56
7936 11:41:17.731087 [Byte1]: 56
7937 11:41:17.735847
7938 11:41:17.736028 Set Vref, RX VrefLevel [Byte0]: 57
7939 11:41:17.738666 [Byte1]: 57
7940 11:41:17.743036
7941 11:41:17.743217 Set Vref, RX VrefLevel [Byte0]: 58
7942 11:41:17.746408 [Byte1]: 58
7943 11:41:17.750908
7944 11:41:17.751115 Set Vref, RX VrefLevel [Byte0]: 59
7945 11:41:17.753916 [Byte1]: 59
7946 11:41:17.758831
7947 11:41:17.759333 Set Vref, RX VrefLevel [Byte0]: 60
7948 11:41:17.762187 [Byte1]: 60
7949 11:41:17.765805
7950 11:41:17.766263 Set Vref, RX VrefLevel [Byte0]: 61
7951 11:41:17.769144 [Byte1]: 61
7952 11:41:17.773934
7953 11:41:17.774488 Set Vref, RX VrefLevel [Byte0]: 62
7954 11:41:17.776827 [Byte1]: 62
7955 11:41:17.781482
7956 11:41:17.782037 Set Vref, RX VrefLevel [Byte0]: 63
7957 11:41:17.784707 [Byte1]: 63
7958 11:41:17.788915
7959 11:41:17.789500 Set Vref, RX VrefLevel [Byte0]: 64
7960 11:41:17.792030 [Byte1]: 64
7961 11:41:17.796608
7962 11:41:17.797198 Set Vref, RX VrefLevel [Byte0]: 65
7963 11:41:17.799661 [Byte1]: 65
7964 11:41:17.803942
7965 11:41:17.804494 Set Vref, RX VrefLevel [Byte0]: 66
7966 11:41:17.807248 [Byte1]: 66
7967 11:41:17.811501
7968 11:41:17.811963 Set Vref, RX VrefLevel [Byte0]: 67
7969 11:41:17.815107 [Byte1]: 67
7970 11:41:17.818996
7971 11:41:17.819455 Set Vref, RX VrefLevel [Byte0]: 68
7972 11:41:17.822429 [Byte1]: 68
7973 11:41:17.826370
7974 11:41:17.830113 Set Vref, RX VrefLevel [Byte0]: 69
7975 11:41:17.830645 [Byte1]: 69
7976 11:41:17.834215
7977 11:41:17.834770 Set Vref, RX VrefLevel [Byte0]: 70
7978 11:41:17.837836 [Byte1]: 70
7979 11:41:17.841843
7980 11:41:17.842391 Set Vref, RX VrefLevel [Byte0]: 71
7981 11:41:17.845126 [Byte1]: 71
7982 11:41:17.849704
7983 11:41:17.850256 Set Vref, RX VrefLevel [Byte0]: 72
7984 11:41:17.852644 [Byte1]: 72
7985 11:41:17.857020
7986 11:41:17.857481 Set Vref, RX VrefLevel [Byte0]: 73
7987 11:41:17.860235 [Byte1]: 73
7988 11:41:17.864306
7989 11:41:17.864884 Set Vref, RX VrefLevel [Byte0]: 74
7990 11:41:17.867747 [Byte1]: 74
7991 11:41:17.872610
7992 11:41:17.873117 Set Vref, RX VrefLevel [Byte0]: 75
7993 11:41:17.875294 [Byte1]: 75
7994 11:41:17.879738
7995 11:41:17.880316 Set Vref, RX VrefLevel [Byte0]: 76
7996 11:41:17.882868 [Byte1]: 76
7997 11:41:17.887587
7998 11:41:17.888173 Set Vref, RX VrefLevel [Byte0]: 77
7999 11:41:17.890527 [Byte1]: 77
8000 11:41:17.894594
8001 11:41:17.895070 Set Vref, RX VrefLevel [Byte0]: 78
8002 11:41:17.897883 [Byte1]: 78
8003 11:41:17.902395
8004 11:41:17.902977 Set Vref, RX VrefLevel [Byte0]: 79
8005 11:41:17.905846 [Byte1]: 79
8006 11:41:17.910033
8007 11:41:17.910823 Final RX Vref Byte 0 = 57 to rank0
8008 11:41:17.913401 Final RX Vref Byte 1 = 61 to rank0
8009 11:41:17.916841 Final RX Vref Byte 0 = 57 to rank1
8010 11:41:17.919784 Final RX Vref Byte 1 = 61 to rank1==
8011 11:41:17.923177 Dram Type= 6, Freq= 0, CH_0, rank 0
8012 11:41:17.929648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 11:41:17.930124 ==
8014 11:41:17.930493 DQS Delay:
8015 11:41:17.932868 DQS0 = 0, DQS1 = 0
8016 11:41:17.933653 DQM Delay:
8017 11:41:17.934299 DQM0 = 135, DQM1 = 123
8018 11:41:17.935985 DQ Delay:
8019 11:41:17.939619 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
8020 11:41:17.942956 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
8021 11:41:17.945994 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8022 11:41:17.949397 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8023 11:41:17.949864
8024 11:41:17.950235
8025 11:41:17.950575
8026 11:41:17.952581 [DramC_TX_OE_Calibration] TA2
8027 11:41:17.955702 Original DQ_B0 (3 6) =30, OEN = 27
8028 11:41:17.958810 Original DQ_B1 (3 6) =30, OEN = 27
8029 11:41:17.962711 24, 0x0, End_B0=24 End_B1=24
8030 11:41:17.965804 25, 0x0, End_B0=25 End_B1=25
8031 11:41:17.966410 26, 0x0, End_B0=26 End_B1=26
8032 11:41:17.969297 27, 0x0, End_B0=27 End_B1=27
8033 11:41:17.972173 28, 0x0, End_B0=28 End_B1=28
8034 11:41:17.975457 29, 0x0, End_B0=29 End_B1=29
8035 11:41:17.975949 30, 0x0, End_B0=30 End_B1=30
8036 11:41:17.979512 31, 0x4545, End_B0=30 End_B1=30
8037 11:41:17.982507 Byte0 end_step=30 best_step=27
8038 11:41:17.985551 Byte1 end_step=30 best_step=27
8039 11:41:17.988844 Byte0 TX OE(2T, 0.5T) = (3, 3)
8040 11:41:17.992173 Byte1 TX OE(2T, 0.5T) = (3, 3)
8041 11:41:17.992597
8042 11:41:17.992930
8043 11:41:17.998938 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
8044 11:41:18.002135 CH0 RK0: MR19=303, MR18=1A18
8045 11:41:18.008350 CH0_RK0: MR19=0x303, MR18=0x1A18, DQSOSC=396, MR23=63, INC=23, DEC=15
8046 11:41:18.008434
8047 11:41:18.011771 ----->DramcWriteLeveling(PI) begin...
8048 11:41:18.011856 ==
8049 11:41:18.015215 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 11:41:18.018549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 11:41:18.018633 ==
8052 11:41:18.021535 Write leveling (Byte 0): 38 => 38
8053 11:41:18.024665 Write leveling (Byte 1): 29 => 29
8054 11:41:18.028059 DramcWriteLeveling(PI) end<-----
8055 11:41:18.028142
8056 11:41:18.028208 ==
8057 11:41:18.031530 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 11:41:18.034714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 11:41:18.038244 ==
8060 11:41:18.038333 [Gating] SW mode calibration
8061 11:41:18.048250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8062 11:41:18.051211 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8063 11:41:18.054584 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 11:41:18.061466 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 11:41:18.064486 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 11:41:18.068265 1 4 12 | B1->B0 | 2a2a 3030 | 1 0 | (1 1) (0 0)
8067 11:41:18.074572 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 11:41:18.077737 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 11:41:18.080877 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 11:41:18.087561 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 11:41:18.090669 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 11:41:18.094137 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 11:41:18.100537 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8074 11:41:18.103921 1 5 12 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (0 0)
8075 11:41:18.106940 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8076 11:41:18.113918 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 11:41:18.116965 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 11:41:18.120473 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 11:41:18.127089 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 11:41:18.130285 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 11:41:18.133648 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8082 11:41:18.140072 1 6 12 | B1->B0 | 2f2f 4646 | 0 0 | (1 1) (0 0)
8083 11:41:18.143314 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8084 11:41:18.147205 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 11:41:18.153235 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 11:41:18.156412 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 11:41:18.163293 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 11:41:18.166502 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 11:41:18.170023 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 11:41:18.176308 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 11:41:18.179726 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 11:41:18.182941 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:41:18.189698 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:41:18.192954 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:41:18.196419 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:41:18.203017 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:41:18.206403 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:41:18.209586 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:41:18.216441 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 11:41:18.219460 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 11:41:18.222911 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:41:18.229524 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:41:18.232890 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:41:18.236350 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:41:18.242490 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:41:18.246097 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 11:41:18.249346 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 11:41:18.252690 Total UI for P1: 0, mck2ui 16
8109 11:41:18.255784 best dqsien dly found for B0: ( 1, 9, 12)
8110 11:41:18.259291 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 11:41:18.262458 Total UI for P1: 0, mck2ui 16
8112 11:41:18.265759 best dqsien dly found for B1: ( 1, 9, 16)
8113 11:41:18.269085 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8114 11:41:18.275514 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8115 11:41:18.276000
8116 11:41:18.278957 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8117 11:41:18.282113 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8118 11:41:18.285216 [Gating] SW calibration Done
8119 11:41:18.285682 ==
8120 11:41:18.288758 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 11:41:18.292420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 11:41:18.292887 ==
8123 11:41:18.295666 RX Vref Scan: 0
8124 11:41:18.296133
8125 11:41:18.296498 RX Vref 0 -> 0, step: 1
8126 11:41:18.296844
8127 11:41:18.298853 RX Delay 0 -> 252, step: 8
8128 11:41:18.302080 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8129 11:41:18.305483 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8130 11:41:18.312051 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8131 11:41:18.315216 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8132 11:41:18.318511 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8133 11:41:18.322163 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8134 11:41:18.325050 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8135 11:41:18.331838 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8136 11:41:18.335344 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8137 11:41:18.338467 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8138 11:41:18.341735 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8139 11:41:18.348336 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8140 11:41:18.351621 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8141 11:41:18.354756 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8142 11:41:18.358067 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8143 11:41:18.361702 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8144 11:41:18.365023 ==
8145 11:41:18.368123 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 11:41:18.371443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 11:41:18.371893 ==
8148 11:41:18.372327 DQS Delay:
8149 11:41:18.374791 DQS0 = 0, DQS1 = 0
8150 11:41:18.375226 DQM Delay:
8151 11:41:18.378413 DQM0 = 136, DQM1 = 125
8152 11:41:18.378958 DQ Delay:
8153 11:41:18.381444 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8154 11:41:18.384607 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8155 11:41:18.387854 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8156 11:41:18.391474 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8157 11:41:18.391959
8158 11:41:18.392330
8159 11:41:18.392670 ==
8160 11:41:18.394731 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 11:41:18.401404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 11:41:18.401958 ==
8163 11:41:18.402328
8164 11:41:18.402671
8165 11:41:18.402995 TX Vref Scan disable
8166 11:41:18.404863 == TX Byte 0 ==
8167 11:41:18.408166 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8168 11:41:18.415023 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8169 11:41:18.415584 == TX Byte 1 ==
8170 11:41:18.418520 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8171 11:41:18.424777 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8172 11:41:18.425512 ==
8173 11:41:18.428173 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 11:41:18.431211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 11:41:18.431678 ==
8176 11:41:18.445309
8177 11:41:18.448372 TX Vref early break, caculate TX vref
8178 11:41:18.451691 TX Vref=16, minBit 0, minWin=23, winSum=390
8179 11:41:18.455044 TX Vref=18, minBit 0, minWin=24, winSum=401
8180 11:41:18.458139 TX Vref=20, minBit 8, minWin=24, winSum=408
8181 11:41:18.461749 TX Vref=22, minBit 0, minWin=25, winSum=414
8182 11:41:18.465031 TX Vref=24, minBit 0, minWin=26, winSum=425
8183 11:41:18.471689 TX Vref=26, minBit 0, minWin=26, winSum=432
8184 11:41:18.474998 TX Vref=28, minBit 0, minWin=26, winSum=432
8185 11:41:18.477788 TX Vref=30, minBit 0, minWin=25, winSum=428
8186 11:41:18.481329 TX Vref=32, minBit 0, minWin=25, winSum=419
8187 11:41:18.485147 TX Vref=34, minBit 0, minWin=25, winSum=409
8188 11:41:18.491001 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 26
8189 11:41:18.491702
8190 11:41:18.494473 Final TX Range 0 Vref 26
8191 11:41:18.494939
8192 11:41:18.495302 ==
8193 11:41:18.497758 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 11:41:18.500911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 11:41:18.501417 ==
8196 11:41:18.501784
8197 11:41:18.502121
8198 11:41:18.504320 TX Vref Scan disable
8199 11:41:18.510788 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8200 11:41:18.511251 == TX Byte 0 ==
8201 11:41:18.514200 u2DelayCellOfst[0]=13 cells (4 PI)
8202 11:41:18.517622 u2DelayCellOfst[1]=17 cells (5 PI)
8203 11:41:18.520703 u2DelayCellOfst[2]=13 cells (4 PI)
8204 11:41:18.523716 u2DelayCellOfst[3]=13 cells (4 PI)
8205 11:41:18.526861 u2DelayCellOfst[4]=10 cells (3 PI)
8206 11:41:18.530213 u2DelayCellOfst[5]=0 cells (0 PI)
8207 11:41:18.533577 u2DelayCellOfst[6]=20 cells (6 PI)
8208 11:41:18.536869 u2DelayCellOfst[7]=17 cells (5 PI)
8209 11:41:18.540379 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8210 11:41:18.543743 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8211 11:41:18.547200 == TX Byte 1 ==
8212 11:41:18.550302 u2DelayCellOfst[8]=0 cells (0 PI)
8213 11:41:18.553595 u2DelayCellOfst[9]=3 cells (1 PI)
8214 11:41:18.557027 u2DelayCellOfst[10]=6 cells (2 PI)
8215 11:41:18.560353 u2DelayCellOfst[11]=3 cells (1 PI)
8216 11:41:18.560822 u2DelayCellOfst[12]=13 cells (4 PI)
8217 11:41:18.563477 u2DelayCellOfst[13]=13 cells (4 PI)
8218 11:41:18.567089 u2DelayCellOfst[14]=13 cells (4 PI)
8219 11:41:18.570393 u2DelayCellOfst[15]=10 cells (3 PI)
8220 11:41:18.576546 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8221 11:41:18.579887 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8222 11:41:18.580328 DramC Write-DBI on
8223 11:41:18.583412 ==
8224 11:41:18.586506 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 11:41:18.589734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 11:41:18.590340 ==
8227 11:41:18.590870
8228 11:41:18.591385
8229 11:41:18.593027 TX Vref Scan disable
8230 11:41:18.593579 == TX Byte 0 ==
8231 11:41:18.599486 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8232 11:41:18.599947 == TX Byte 1 ==
8233 11:41:18.603244 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8234 11:41:18.606599 DramC Write-DBI off
8235 11:41:18.607024
8236 11:41:18.607396 [DATLAT]
8237 11:41:18.609577 Freq=1600, CH0 RK1
8238 11:41:18.610002
8239 11:41:18.610339 DATLAT Default: 0xf
8240 11:41:18.612676 0, 0xFFFF, sum = 0
8241 11:41:18.613155 1, 0xFFFF, sum = 0
8242 11:41:18.616424 2, 0xFFFF, sum = 0
8243 11:41:18.616856 3, 0xFFFF, sum = 0
8244 11:41:18.619701 4, 0xFFFF, sum = 0
8245 11:41:18.620132 5, 0xFFFF, sum = 0
8246 11:41:18.623055 6, 0xFFFF, sum = 0
8247 11:41:18.626110 7, 0xFFFF, sum = 0
8248 11:41:18.626542 8, 0xFFFF, sum = 0
8249 11:41:18.629688 9, 0xFFFF, sum = 0
8250 11:41:18.630239 10, 0xFFFF, sum = 0
8251 11:41:18.632844 11, 0xFFFF, sum = 0
8252 11:41:18.633325 12, 0xFFFF, sum = 0
8253 11:41:18.635915 13, 0xFFFF, sum = 0
8254 11:41:18.636343 14, 0x0, sum = 1
8255 11:41:18.639381 15, 0x0, sum = 2
8256 11:41:18.639813 16, 0x0, sum = 3
8257 11:41:18.642614 17, 0x0, sum = 4
8258 11:41:18.643045 best_step = 15
8259 11:41:18.643399
8260 11:41:18.643710 ==
8261 11:41:18.645991 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 11:41:18.649398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 11:41:18.652558 ==
8264 11:41:18.653004 RX Vref Scan: 0
8265 11:41:18.653350
8266 11:41:18.655987 RX Vref 0 -> 0, step: 1
8267 11:41:18.656409
8268 11:41:18.659220 RX Delay 11 -> 252, step: 4
8269 11:41:18.662508 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8270 11:41:18.665620 iDelay=191, Bit 1, Center 134 (87 ~ 182) 96
8271 11:41:18.668947 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8272 11:41:18.672234 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8273 11:41:18.678818 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8274 11:41:18.682137 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8275 11:41:18.685816 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8276 11:41:18.688714 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8277 11:41:18.695363 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8278 11:41:18.698724 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8279 11:41:18.701921 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8280 11:41:18.705542 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8281 11:41:18.708703 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8282 11:41:18.714947 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8283 11:41:18.718298 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8284 11:41:18.721640 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8285 11:41:18.722061 ==
8286 11:41:18.724955 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 11:41:18.728483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 11:41:18.731418 ==
8289 11:41:18.731838 DQS Delay:
8290 11:41:18.732168 DQS0 = 0, DQS1 = 0
8291 11:41:18.734756 DQM Delay:
8292 11:41:18.735173 DQM0 = 133, DQM1 = 123
8293 11:41:18.737935 DQ Delay:
8294 11:41:18.741170 DQ0 =132, DQ1 =134, DQ2 =130, DQ3 =130
8295 11:41:18.744473 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8296 11:41:18.747762 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8297 11:41:18.751172 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8298 11:41:18.751643
8299 11:41:18.751981
8300 11:41:18.752289
8301 11:41:18.754770 [DramC_TX_OE_Calibration] TA2
8302 11:41:18.757642 Original DQ_B0 (3 6) =30, OEN = 27
8303 11:41:18.761196 Original DQ_B1 (3 6) =30, OEN = 27
8304 11:41:18.764461 24, 0x0, End_B0=24 End_B1=24
8305 11:41:18.764888 25, 0x0, End_B0=25 End_B1=25
8306 11:41:18.767898 26, 0x0, End_B0=26 End_B1=26
8307 11:41:18.770949 27, 0x0, End_B0=27 End_B1=27
8308 11:41:18.774400 28, 0x0, End_B0=28 End_B1=28
8309 11:41:18.774827 29, 0x0, End_B0=29 End_B1=29
8310 11:41:18.777826 30, 0x0, End_B0=30 End_B1=30
8311 11:41:18.781043 31, 0x5151, End_B0=30 End_B1=30
8312 11:41:18.784017 Byte0 end_step=30 best_step=27
8313 11:41:18.787163 Byte1 end_step=30 best_step=27
8314 11:41:18.790468 Byte0 TX OE(2T, 0.5T) = (3, 3)
8315 11:41:18.793598 Byte1 TX OE(2T, 0.5T) = (3, 3)
8316 11:41:18.793681
8317 11:41:18.793745
8318 11:41:18.800116 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8319 11:41:18.803450 CH0 RK1: MR19=303, MR18=200D
8320 11:41:18.810416 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8321 11:41:18.813711 [RxdqsGatingPostProcess] freq 1600
8322 11:41:18.816879 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8323 11:41:18.820463 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 11:41:18.823717 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 11:41:18.826831 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 11:41:18.830493 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 11:41:18.833565 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 11:41:18.836757 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 11:41:18.840320 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 11:41:18.843633 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 11:41:18.846509 Pre-setting of DQS Precalculation
8332 11:41:18.849791 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8333 11:41:18.850354 ==
8334 11:41:18.853595 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 11:41:18.860037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 11:41:18.860524 ==
8337 11:41:18.863030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 11:41:18.869471 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 11:41:18.873071 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 11:41:18.879564 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 11:41:18.886938 [CA 0] Center 42 (12~72) winsize 61
8342 11:41:18.890925 [CA 1] Center 42 (12~72) winsize 61
8343 11:41:18.893728 [CA 2] Center 38 (9~68) winsize 60
8344 11:41:18.897011 [CA 3] Center 37 (8~67) winsize 60
8345 11:41:18.900230 [CA 4] Center 37 (8~67) winsize 60
8346 11:41:18.903716 [CA 5] Center 37 (7~67) winsize 61
8347 11:41:18.904259
8348 11:41:18.906931 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8349 11:41:18.907508
8350 11:41:18.913590 [CATrainingPosCal] consider 1 rank data
8351 11:41:18.914011 u2DelayCellTimex100 = 285/100 ps
8352 11:41:18.920318 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8353 11:41:18.923778 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8354 11:41:18.927122 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8355 11:41:18.930442 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8356 11:41:18.933515 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8357 11:41:18.936851 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8358 11:41:18.937300
8359 11:41:18.939949 CA PerBit enable=1, Macro0, CA PI delay=37
8360 11:41:18.940357
8361 11:41:18.943490 [CBTSetCACLKResult] CA Dly = 37
8362 11:41:18.946894 CS Dly: 9 (0~40)
8363 11:41:18.949921 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 11:41:18.953187 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 11:41:18.953624 ==
8366 11:41:18.956300 Dram Type= 6, Freq= 0, CH_1, rank 1
8367 11:41:18.963314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 11:41:18.963728 ==
8369 11:41:18.966889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 11:41:18.970003 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 11:41:18.976533 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 11:41:18.982897 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 11:41:18.990664 [CA 0] Center 42 (13~72) winsize 60
8374 11:41:18.993616 [CA 1] Center 42 (12~72) winsize 61
8375 11:41:18.997071 [CA 2] Center 38 (9~68) winsize 60
8376 11:41:19.000480 [CA 3] Center 37 (8~67) winsize 60
8377 11:41:19.003735 [CA 4] Center 38 (9~68) winsize 60
8378 11:41:19.007029 [CA 5] Center 37 (8~67) winsize 60
8379 11:41:19.007576
8380 11:41:19.010361 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8381 11:41:19.011043
8382 11:41:19.013641 [CATrainingPosCal] consider 2 rank data
8383 11:41:19.017073 u2DelayCellTimex100 = 285/100 ps
8384 11:41:19.020285 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8385 11:41:19.026733 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8386 11:41:19.030922 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8387 11:41:19.033496 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8388 11:41:19.036665 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8389 11:41:19.040112 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8390 11:41:19.040565
8391 11:41:19.043410 CA PerBit enable=1, Macro0, CA PI delay=37
8392 11:41:19.043861
8393 11:41:19.046669 [CBTSetCACLKResult] CA Dly = 37
8394 11:41:19.049813 CS Dly: 10 (0~43)
8395 11:41:19.053603 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 11:41:19.056658 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 11:41:19.057256
8398 11:41:19.059683 ----->DramcWriteLeveling(PI) begin...
8399 11:41:19.060152 ==
8400 11:41:19.063300 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 11:41:19.069871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 11:41:19.070435 ==
8403 11:41:19.073070 Write leveling (Byte 0): 25 => 25
8404 11:41:19.076305 Write leveling (Byte 1): 27 => 27
8405 11:41:19.076762 DramcWriteLeveling(PI) end<-----
8406 11:41:19.077158
8407 11:41:19.079545 ==
8408 11:41:19.082843 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 11:41:19.085859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 11:41:19.086314 ==
8411 11:41:19.089487 [Gating] SW mode calibration
8412 11:41:19.095960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8413 11:41:19.099109 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8414 11:41:19.105852 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 11:41:19.109365 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 11:41:19.112520 1 4 8 | B1->B0 | 2b2b 3030 | 1 1 | (0 0) (1 1)
8417 11:41:19.119082 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 11:41:19.122177 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 11:41:19.125679 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 11:41:19.132190 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 11:41:19.135441 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 11:41:19.138543 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 11:41:19.145322 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8424 11:41:19.148860 1 5 8 | B1->B0 | 2626 2525 | 0 0 | (1 0) (1 0)
8425 11:41:19.151879 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8426 11:41:19.158671 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 11:41:19.161790 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 11:41:19.165009 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 11:41:19.171729 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 11:41:19.174859 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 11:41:19.178721 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8432 11:41:19.185274 1 6 8 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
8433 11:41:19.189021 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 11:41:19.191961 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 11:41:19.197973 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 11:41:19.201507 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 11:41:19.204590 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 11:41:19.211062 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 11:41:19.214375 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 11:41:19.218306 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 11:41:19.224331 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 11:41:19.227749 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:41:19.231119 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:41:19.237869 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:41:19.241048 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:41:19.244084 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:41:19.250846 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:41:19.254100 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 11:41:19.257670 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 11:41:19.263832 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:41:19.267197 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:41:19.270431 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 11:41:19.277118 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:41:19.280317 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 11:41:19.283891 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8456 11:41:19.290724 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8457 11:41:19.293603 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8458 11:41:19.296802 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 11:41:19.300227 Total UI for P1: 0, mck2ui 16
8460 11:41:19.303900 best dqsien dly found for B0: ( 1, 9, 8)
8461 11:41:19.306922 Total UI for P1: 0, mck2ui 16
8462 11:41:19.310239 best dqsien dly found for B1: ( 1, 9, 10)
8463 11:41:19.313476 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8464 11:41:19.316436 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8465 11:41:19.316535
8466 11:41:19.323387 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8467 11:41:19.326499 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8468 11:41:19.329767 [Gating] SW calibration Done
8469 11:41:19.329856 ==
8470 11:41:19.333239 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 11:41:19.336641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 11:41:19.336731 ==
8473 11:41:19.336821 RX Vref Scan: 0
8474 11:41:19.336926
8475 11:41:19.339594 RX Vref 0 -> 0, step: 1
8476 11:41:19.339681
8477 11:41:19.343120 RX Delay 0 -> 252, step: 8
8478 11:41:19.346352 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8479 11:41:19.350042 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8480 11:41:19.352913 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8481 11:41:19.359754 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8482 11:41:19.363330 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8483 11:41:19.366498 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8484 11:41:19.369760 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8485 11:41:19.372664 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8486 11:41:19.379434 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8487 11:41:19.382999 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8488 11:41:19.386240 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8489 11:41:19.389467 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8490 11:41:19.392598 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8491 11:41:19.399191 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8492 11:41:19.402796 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8493 11:41:19.406537 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8494 11:41:19.406619 ==
8495 11:41:19.409251 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 11:41:19.412852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 11:41:19.416085 ==
8498 11:41:19.416218 DQS Delay:
8499 11:41:19.416313 DQS0 = 0, DQS1 = 0
8500 11:41:19.419324 DQM Delay:
8501 11:41:19.419405 DQM0 = 138, DQM1 = 129
8502 11:41:19.422352 DQ Delay:
8503 11:41:19.426044 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8504 11:41:19.428825 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8505 11:41:19.432499 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8506 11:41:19.435751 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8507 11:41:19.435833
8508 11:41:19.435927
8509 11:41:19.436050 ==
8510 11:41:19.439106 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 11:41:19.442186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 11:41:19.442267 ==
8513 11:41:19.445734
8514 11:41:19.445824
8515 11:41:19.445916 TX Vref Scan disable
8516 11:41:19.448992 == TX Byte 0 ==
8517 11:41:19.451913 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8518 11:41:19.455804 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 11:41:19.458688 == TX Byte 1 ==
8520 11:41:19.462073 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8521 11:41:19.465477 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8522 11:41:19.465582 ==
8523 11:41:19.468689 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 11:41:19.475286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 11:41:19.475390 ==
8526 11:41:19.486960
8527 11:41:19.490202 TX Vref early break, caculate TX vref
8528 11:41:19.493439 TX Vref=16, minBit 10, minWin=22, winSum=373
8529 11:41:19.496956 TX Vref=18, minBit 10, minWin=22, winSum=384
8530 11:41:19.499973 TX Vref=20, minBit 10, minWin=23, winSum=392
8531 11:41:19.503392 TX Vref=22, minBit 10, minWin=23, winSum=402
8532 11:41:19.509781 TX Vref=24, minBit 10, minWin=23, winSum=412
8533 11:41:19.513731 TX Vref=26, minBit 10, minWin=25, winSum=421
8534 11:41:19.516313 TX Vref=28, minBit 12, minWin=25, winSum=425
8535 11:41:19.519829 TX Vref=30, minBit 10, minWin=25, winSum=421
8536 11:41:19.523075 TX Vref=32, minBit 13, minWin=24, winSum=410
8537 11:41:19.529760 TX Vref=34, minBit 0, minWin=24, winSum=400
8538 11:41:19.532878 [TxChooseVref] Worse bit 12, Min win 25, Win sum 425, Final Vref 28
8539 11:41:19.532985
8540 11:41:19.536325 Final TX Range 0 Vref 28
8541 11:41:19.536408
8542 11:41:19.536473 ==
8543 11:41:19.539562 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 11:41:19.546104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 11:41:19.546212 ==
8546 11:41:19.546310
8547 11:41:19.546403
8548 11:41:19.546476 TX Vref Scan disable
8549 11:41:19.553159 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8550 11:41:19.553242 == TX Byte 0 ==
8551 11:41:19.556200 u2DelayCellOfst[0]=17 cells (5 PI)
8552 11:41:19.559600 u2DelayCellOfst[1]=10 cells (3 PI)
8553 11:41:19.562990 u2DelayCellOfst[2]=0 cells (0 PI)
8554 11:41:19.566567 u2DelayCellOfst[3]=6 cells (2 PI)
8555 11:41:19.570052 u2DelayCellOfst[4]=6 cells (2 PI)
8556 11:41:19.573257 u2DelayCellOfst[5]=17 cells (5 PI)
8557 11:41:19.576609 u2DelayCellOfst[6]=17 cells (5 PI)
8558 11:41:19.579978 u2DelayCellOfst[7]=6 cells (2 PI)
8559 11:41:19.583331 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8560 11:41:19.586259 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8561 11:41:19.589537 == TX Byte 1 ==
8562 11:41:19.592747 u2DelayCellOfst[8]=0 cells (0 PI)
8563 11:41:19.596145 u2DelayCellOfst[9]=3 cells (1 PI)
8564 11:41:19.599578 u2DelayCellOfst[10]=10 cells (3 PI)
8565 11:41:19.602784 u2DelayCellOfst[11]=3 cells (1 PI)
8566 11:41:19.606296 u2DelayCellOfst[12]=13 cells (4 PI)
8567 11:41:19.606384 u2DelayCellOfst[13]=17 cells (5 PI)
8568 11:41:19.609420 u2DelayCellOfst[14]=20 cells (6 PI)
8569 11:41:19.613720 u2DelayCellOfst[15]=17 cells (5 PI)
8570 11:41:19.619981 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8571 11:41:19.623045 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8572 11:41:19.623516 DramC Write-DBI on
8573 11:41:19.626637 ==
8574 11:41:19.629507 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 11:41:19.632957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 11:41:19.633502 ==
8577 11:41:19.633874
8578 11:41:19.634217
8579 11:41:19.636476 TX Vref Scan disable
8580 11:41:19.637127 == TX Byte 0 ==
8581 11:41:19.642709 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8582 11:41:19.643135 == TX Byte 1 ==
8583 11:41:19.646100 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8584 11:41:19.649565 DramC Write-DBI off
8585 11:41:19.650088
8586 11:41:19.650538 [DATLAT]
8587 11:41:19.652661 Freq=1600, CH1 RK0
8588 11:41:19.653401
8589 11:41:19.653881 DATLAT Default: 0xf
8590 11:41:19.656273 0, 0xFFFF, sum = 0
8591 11:41:19.656846 1, 0xFFFF, sum = 0
8592 11:41:19.659288 2, 0xFFFF, sum = 0
8593 11:41:19.659845 3, 0xFFFF, sum = 0
8594 11:41:19.662617 4, 0xFFFF, sum = 0
8595 11:41:19.663073 5, 0xFFFF, sum = 0
8596 11:41:19.665854 6, 0xFFFF, sum = 0
8597 11:41:19.669264 7, 0xFFFF, sum = 0
8598 11:41:19.669689 8, 0xFFFF, sum = 0
8599 11:41:19.672476 9, 0xFFFF, sum = 0
8600 11:41:19.672910 10, 0xFFFF, sum = 0
8601 11:41:19.675620 11, 0xFFFF, sum = 0
8602 11:41:19.676048 12, 0xFFFF, sum = 0
8603 11:41:19.679214 13, 0xFFFF, sum = 0
8604 11:41:19.679640 14, 0x0, sum = 1
8605 11:41:19.682459 15, 0x0, sum = 2
8606 11:41:19.682886 16, 0x0, sum = 3
8607 11:41:19.686225 17, 0x0, sum = 4
8608 11:41:19.686759 best_step = 15
8609 11:41:19.687095
8610 11:41:19.687400 ==
8611 11:41:19.689268 Dram Type= 6, Freq= 0, CH_1, rank 0
8612 11:41:19.692409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8613 11:41:19.692832 ==
8614 11:41:19.696100 RX Vref Scan: 1
8615 11:41:19.696518
8616 11:41:19.699113 Set Vref Range= 24 -> 127
8617 11:41:19.699537
8618 11:41:19.699869 RX Vref 24 -> 127, step: 1
8619 11:41:19.702312
8620 11:41:19.702731 RX Delay 19 -> 252, step: 4
8621 11:41:19.703066
8622 11:41:19.705811 Set Vref, RX VrefLevel [Byte0]: 24
8623 11:41:19.709254 [Byte1]: 24
8624 11:41:19.712363
8625 11:41:19.712777 Set Vref, RX VrefLevel [Byte0]: 25
8626 11:41:19.715679 [Byte1]: 25
8627 11:41:19.719752
8628 11:41:19.719855 Set Vref, RX VrefLevel [Byte0]: 26
8629 11:41:19.723137 [Byte1]: 26
8630 11:41:19.727451
8631 11:41:19.727533 Set Vref, RX VrefLevel [Byte0]: 27
8632 11:41:19.730625 [Byte1]: 27
8633 11:41:19.735009
8634 11:41:19.735091 Set Vref, RX VrefLevel [Byte0]: 28
8635 11:41:19.738341 [Byte1]: 28
8636 11:41:19.742278
8637 11:41:19.742360 Set Vref, RX VrefLevel [Byte0]: 29
8638 11:41:19.745954 [Byte1]: 29
8639 11:41:19.750350
8640 11:41:19.750432 Set Vref, RX VrefLevel [Byte0]: 30
8641 11:41:19.753906 [Byte1]: 30
8642 11:41:19.758116
8643 11:41:19.758538 Set Vref, RX VrefLevel [Byte0]: 31
8644 11:41:19.761282 [Byte1]: 31
8645 11:41:19.765697
8646 11:41:19.766196 Set Vref, RX VrefLevel [Byte0]: 32
8647 11:41:19.768510 [Byte1]: 32
8648 11:41:19.773305
8649 11:41:19.773859 Set Vref, RX VrefLevel [Byte0]: 33
8650 11:41:19.776137 [Byte1]: 33
8651 11:41:19.780306
8652 11:41:19.780387 Set Vref, RX VrefLevel [Byte0]: 34
8653 11:41:19.784040 [Byte1]: 34
8654 11:41:19.788021
8655 11:41:19.788456 Set Vref, RX VrefLevel [Byte0]: 35
8656 11:41:19.791669 [Byte1]: 35
8657 11:41:19.795845
8658 11:41:19.796393 Set Vref, RX VrefLevel [Byte0]: 36
8659 11:41:19.798915 [Byte1]: 36
8660 11:41:19.803309
8661 11:41:19.803722 Set Vref, RX VrefLevel [Byte0]: 37
8662 11:41:19.806533 [Byte1]: 37
8663 11:41:19.810845
8664 11:41:19.811274 Set Vref, RX VrefLevel [Byte0]: 38
8665 11:41:19.814458 [Byte1]: 38
8666 11:41:19.818368
8667 11:41:19.818799 Set Vref, RX VrefLevel [Byte0]: 39
8668 11:41:19.821725 [Byte1]: 39
8669 11:41:19.826023
8670 11:41:19.826438 Set Vref, RX VrefLevel [Byte0]: 40
8671 11:41:19.829354 [Byte1]: 40
8672 11:41:19.833849
8673 11:41:19.834402 Set Vref, RX VrefLevel [Byte0]: 41
8674 11:41:19.837158 [Byte1]: 41
8675 11:41:19.841537
8676 11:41:19.842091 Set Vref, RX VrefLevel [Byte0]: 42
8677 11:41:19.844519 [Byte1]: 42
8678 11:41:19.849243
8679 11:41:19.849820 Set Vref, RX VrefLevel [Byte0]: 43
8680 11:41:19.852478 [Byte1]: 43
8681 11:41:19.856381
8682 11:41:19.856844 Set Vref, RX VrefLevel [Byte0]: 44
8683 11:41:19.859569 [Byte1]: 44
8684 11:41:19.864056
8685 11:41:19.864512 Set Vref, RX VrefLevel [Byte0]: 45
8686 11:41:19.867595 [Byte1]: 45
8687 11:41:19.871562
8688 11:41:19.872039 Set Vref, RX VrefLevel [Byte0]: 46
8689 11:41:19.875159 [Byte1]: 46
8690 11:41:19.879366
8691 11:41:19.879825 Set Vref, RX VrefLevel [Byte0]: 47
8692 11:41:19.882554 [Byte1]: 47
8693 11:41:19.887106
8694 11:41:19.887661 Set Vref, RX VrefLevel [Byte0]: 48
8695 11:41:19.890430 [Byte1]: 48
8696 11:41:19.894420
8697 11:41:19.894984 Set Vref, RX VrefLevel [Byte0]: 49
8698 11:41:19.897743 [Byte1]: 49
8699 11:41:19.902172
8700 11:41:19.902771 Set Vref, RX VrefLevel [Byte0]: 50
8701 11:41:19.905100 [Byte1]: 50
8702 11:41:19.909407
8703 11:41:19.909865 Set Vref, RX VrefLevel [Byte0]: 51
8704 11:41:19.912712 [Byte1]: 51
8705 11:41:19.917101
8706 11:41:19.917649 Set Vref, RX VrefLevel [Byte0]: 52
8707 11:41:19.920385 [Byte1]: 52
8708 11:41:19.924536
8709 11:41:19.925032 Set Vref, RX VrefLevel [Byte0]: 53
8710 11:41:19.927728 [Byte1]: 53
8711 11:41:19.932271
8712 11:41:19.932728 Set Vref, RX VrefLevel [Byte0]: 54
8713 11:41:19.935489 [Byte1]: 54
8714 11:41:19.939879
8715 11:41:19.940371 Set Vref, RX VrefLevel [Byte0]: 55
8716 11:41:19.942900 [Byte1]: 55
8717 11:41:19.947275
8718 11:41:19.947736 Set Vref, RX VrefLevel [Byte0]: 56
8719 11:41:19.950911 [Byte1]: 56
8720 11:41:19.955082
8721 11:41:19.955543 Set Vref, RX VrefLevel [Byte0]: 57
8722 11:41:19.958079 [Byte1]: 57
8723 11:41:19.962712
8724 11:41:19.963174 Set Vref, RX VrefLevel [Byte0]: 58
8725 11:41:19.966030 [Byte1]: 58
8726 11:41:19.970212
8727 11:41:19.970683 Set Vref, RX VrefLevel [Byte0]: 59
8728 11:41:19.973304 [Byte1]: 59
8729 11:41:19.977475
8730 11:41:19.977935 Set Vref, RX VrefLevel [Byte0]: 60
8731 11:41:19.981078 [Byte1]: 60
8732 11:41:19.985211
8733 11:41:19.985669 Set Vref, RX VrefLevel [Byte0]: 61
8734 11:41:19.988477 [Byte1]: 61
8735 11:41:19.992680
8736 11:41:19.993119 Set Vref, RX VrefLevel [Byte0]: 62
8737 11:41:19.996318 [Byte1]: 62
8738 11:41:20.000440
8739 11:41:20.000855 Set Vref, RX VrefLevel [Byte0]: 63
8740 11:41:20.003909 [Byte1]: 63
8741 11:41:20.007900
8742 11:41:20.008317 Set Vref, RX VrefLevel [Byte0]: 64
8743 11:41:20.011002 [Byte1]: 64
8744 11:41:20.015445
8745 11:41:20.015861 Set Vref, RX VrefLevel [Byte0]: 65
8746 11:41:20.018821 [Byte1]: 65
8747 11:41:20.022856
8748 11:41:20.023273 Set Vref, RX VrefLevel [Byte0]: 66
8749 11:41:20.026329 [Byte1]: 66
8750 11:41:20.030619
8751 11:41:20.031035 Set Vref, RX VrefLevel [Byte0]: 67
8752 11:41:20.033989 [Byte1]: 67
8753 11:41:20.038473
8754 11:41:20.038890 Set Vref, RX VrefLevel [Byte0]: 68
8755 11:41:20.044556 [Byte1]: 68
8756 11:41:20.044998
8757 11:41:20.048240 Set Vref, RX VrefLevel [Byte0]: 69
8758 11:41:20.051761 [Byte1]: 69
8759 11:41:20.052182
8760 11:41:20.054756 Set Vref, RX VrefLevel [Byte0]: 70
8761 11:41:20.057936 [Byte1]: 70
8762 11:41:20.058447
8763 11:41:20.061073 Set Vref, RX VrefLevel [Byte0]: 71
8764 11:41:20.064543 [Byte1]: 71
8765 11:41:20.068577
8766 11:41:20.069156 Set Vref, RX VrefLevel [Byte0]: 72
8767 11:41:20.071652 [Byte1]: 72
8768 11:41:20.076219
8769 11:41:20.076635 Set Vref, RX VrefLevel [Byte0]: 73
8770 11:41:20.079132 [Byte1]: 73
8771 11:41:20.083627
8772 11:41:20.084041 Set Vref, RX VrefLevel [Byte0]: 74
8773 11:41:20.086950 [Byte1]: 74
8774 11:41:20.091209
8775 11:41:20.091622 Set Vref, RX VrefLevel [Byte0]: 75
8776 11:41:20.094760 [Byte1]: 75
8777 11:41:20.098774
8778 11:41:20.099191 Final RX Vref Byte 0 = 53 to rank0
8779 11:41:20.101952 Final RX Vref Byte 1 = 62 to rank0
8780 11:41:20.105229 Final RX Vref Byte 0 = 53 to rank1
8781 11:41:20.108513 Final RX Vref Byte 1 = 62 to rank1==
8782 11:41:20.112049 Dram Type= 6, Freq= 0, CH_1, rank 0
8783 11:41:20.118284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 11:41:20.118708 ==
8785 11:41:20.119039 DQS Delay:
8786 11:41:20.121659 DQS0 = 0, DQS1 = 0
8787 11:41:20.122074 DQM Delay:
8788 11:41:20.122404 DQM0 = 133, DQM1 = 129
8789 11:41:20.125314 DQ Delay:
8790 11:41:20.128217 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8791 11:41:20.131634 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8792 11:41:20.134901 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8793 11:41:20.138177 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8794 11:41:20.138595
8795 11:41:20.138922
8796 11:41:20.139229
8797 11:41:20.141723 [DramC_TX_OE_Calibration] TA2
8798 11:41:20.144759 Original DQ_B0 (3 6) =30, OEN = 27
8799 11:41:20.148365 Original DQ_B1 (3 6) =30, OEN = 27
8800 11:41:20.151758 24, 0x0, End_B0=24 End_B1=24
8801 11:41:20.154626 25, 0x0, End_B0=25 End_B1=25
8802 11:41:20.155050 26, 0x0, End_B0=26 End_B1=26
8803 11:41:20.157925 27, 0x0, End_B0=27 End_B1=27
8804 11:41:20.161211 28, 0x0, End_B0=28 End_B1=28
8805 11:41:20.164323 29, 0x0, End_B0=29 End_B1=29
8806 11:41:20.164748 30, 0x0, End_B0=30 End_B1=30
8807 11:41:20.167876 31, 0x4141, End_B0=30 End_B1=30
8808 11:41:20.171148 Byte0 end_step=30 best_step=27
8809 11:41:20.174928 Byte1 end_step=30 best_step=27
8810 11:41:20.178030 Byte0 TX OE(2T, 0.5T) = (3, 3)
8811 11:41:20.181169 Byte1 TX OE(2T, 0.5T) = (3, 3)
8812 11:41:20.181583
8813 11:41:20.181907
8814 11:41:20.187979 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8815 11:41:20.191076 CH1 RK0: MR19=303, MR18=1927
8816 11:41:20.197614 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8817 11:41:20.198031
8818 11:41:20.201160 ----->DramcWriteLeveling(PI) begin...
8819 11:41:20.201580 ==
8820 11:41:20.204215 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 11:41:20.207597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 11:41:20.208036 ==
8823 11:41:20.210769 Write leveling (Byte 0): 23 => 23
8824 11:41:20.214342 Write leveling (Byte 1): 29 => 29
8825 11:41:20.217639 DramcWriteLeveling(PI) end<-----
8826 11:41:20.218053
8827 11:41:20.218417 ==
8828 11:41:20.220841 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 11:41:20.224177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 11:41:20.227366 ==
8831 11:41:20.227924 [Gating] SW mode calibration
8832 11:41:20.234225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8833 11:41:20.240665 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8834 11:41:20.244044 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:41:20.250429 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:41:20.253717 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8837 11:41:20.257010 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8838 11:41:20.263683 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 11:41:20.267055 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 11:41:20.270370 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 11:41:20.277070 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 11:41:20.280290 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 11:41:20.283577 1 5 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8844 11:41:20.290374 1 5 8 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 0)
8845 11:41:20.293525 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8846 11:41:20.296680 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 11:41:20.303487 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 11:41:20.306646 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 11:41:20.310233 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 11:41:20.316316 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 11:41:20.319844 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 11:41:20.323315 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8853 11:41:20.330007 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8854 11:41:20.333045 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 11:41:20.336548 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 11:41:20.342966 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 11:41:20.346097 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 11:41:20.349593 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 11:41:20.356065 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 11:41:20.359474 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8861 11:41:20.362710 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8862 11:41:20.369495 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:41:20.372499 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:41:20.375751 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:41:20.382382 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:41:20.385669 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:41:20.389247 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:41:20.395715 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:41:20.399078 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:41:20.402157 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:41:20.408872 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 11:41:20.412245 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 11:41:20.415561 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 11:41:20.422003 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 11:41:20.425483 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 11:41:20.428843 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8877 11:41:20.435495 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 11:41:20.435921 Total UI for P1: 0, mck2ui 16
8879 11:41:20.441956 best dqsien dly found for B0: ( 1, 9, 8)
8880 11:41:20.442379 Total UI for P1: 0, mck2ui 16
8881 11:41:20.448355 best dqsien dly found for B1: ( 1, 9, 8)
8882 11:41:20.451871 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8883 11:41:20.455155 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8884 11:41:20.455578
8885 11:41:20.458322 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8886 11:41:20.461900 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8887 11:41:20.465058 [Gating] SW calibration Done
8888 11:41:20.465476 ==
8889 11:41:20.468250 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 11:41:20.471354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 11:41:20.471792 ==
8892 11:41:20.475067 RX Vref Scan: 0
8893 11:41:20.475486
8894 11:41:20.475858 RX Vref 0 -> 0, step: 1
8895 11:41:20.476183
8896 11:41:20.478634 RX Delay 0 -> 252, step: 8
8897 11:41:20.481531 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8898 11:41:20.487979 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8899 11:41:20.491476 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8900 11:41:20.494650 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8901 11:41:20.497851 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8902 11:41:20.501374 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8903 11:41:20.507804 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8904 11:41:20.511210 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8905 11:41:20.514365 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8906 11:41:20.517653 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8907 11:41:20.520921 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8908 11:41:20.527723 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8909 11:41:20.531169 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8910 11:41:20.534218 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8911 11:41:20.537649 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8912 11:41:20.544143 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8913 11:41:20.544558 ==
8914 11:41:20.547706 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 11:41:20.551059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 11:41:20.551477 ==
8917 11:41:20.551807 DQS Delay:
8918 11:41:20.554124 DQS0 = 0, DQS1 = 0
8919 11:41:20.554537 DQM Delay:
8920 11:41:20.557687 DQM0 = 136, DQM1 = 133
8921 11:41:20.558101 DQ Delay:
8922 11:41:20.560753 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8923 11:41:20.564011 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =139
8924 11:41:20.567430 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8925 11:41:20.570629 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8926 11:41:20.571243
8927 11:41:20.571591
8928 11:41:20.574236 ==
8929 11:41:20.577674 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 11:41:20.580722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 11:41:20.581176 ==
8932 11:41:20.581519
8933 11:41:20.581848
8934 11:41:20.584195 TX Vref Scan disable
8935 11:41:20.584611 == TX Byte 0 ==
8936 11:41:20.587210 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8937 11:41:20.593679 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8938 11:41:20.594095 == TX Byte 1 ==
8939 11:41:20.600362 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8940 11:41:20.603327 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8941 11:41:20.603717 ==
8942 11:41:20.607111 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 11:41:20.610125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 11:41:20.610604 ==
8945 11:41:20.624867
8946 11:41:20.628206 TX Vref early break, caculate TX vref
8947 11:41:20.631395 TX Vref=16, minBit 9, minWin=22, winSum=378
8948 11:41:20.634824 TX Vref=18, minBit 13, minWin=22, winSum=384
8949 11:41:20.638366 TX Vref=20, minBit 9, minWin=22, winSum=393
8950 11:41:20.641483 TX Vref=22, minBit 9, minWin=23, winSum=405
8951 11:41:20.644803 TX Vref=24, minBit 8, minWin=24, winSum=414
8952 11:41:20.651369 TX Vref=26, minBit 9, minWin=24, winSum=414
8953 11:41:20.655118 TX Vref=28, minBit 8, minWin=25, winSum=417
8954 11:41:20.657945 TX Vref=30, minBit 10, minWin=24, winSum=411
8955 11:41:20.661395 TX Vref=32, minBit 8, minWin=24, winSum=401
8956 11:41:20.664886 TX Vref=34, minBit 8, minWin=24, winSum=399
8957 11:41:20.671315 TX Vref=36, minBit 15, minWin=22, winSum=386
8958 11:41:20.674837 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8959 11:41:20.675197
8960 11:41:20.678017 Final TX Range 0 Vref 28
8961 11:41:20.678371
8962 11:41:20.678672 ==
8963 11:41:20.681157 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 11:41:20.684552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 11:41:20.687717 ==
8966 11:41:20.688132
8967 11:41:20.688457
8968 11:41:20.688761 TX Vref Scan disable
8969 11:41:20.694484 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8970 11:41:20.694918 == TX Byte 0 ==
8971 11:41:20.698048 u2DelayCellOfst[0]=17 cells (5 PI)
8972 11:41:20.701659 u2DelayCellOfst[1]=10 cells (3 PI)
8973 11:41:20.704564 u2DelayCellOfst[2]=0 cells (0 PI)
8974 11:41:20.707694 u2DelayCellOfst[3]=3 cells (1 PI)
8975 11:41:20.711775 u2DelayCellOfst[4]=6 cells (2 PI)
8976 11:41:20.714204 u2DelayCellOfst[5]=17 cells (5 PI)
8977 11:41:20.717781 u2DelayCellOfst[6]=17 cells (5 PI)
8978 11:41:20.721144 u2DelayCellOfst[7]=3 cells (1 PI)
8979 11:41:20.724233 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8980 11:41:20.727562 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8981 11:41:20.730636 == TX Byte 1 ==
8982 11:41:20.734309 u2DelayCellOfst[8]=0 cells (0 PI)
8983 11:41:20.737455 u2DelayCellOfst[9]=3 cells (1 PI)
8984 11:41:20.740933 u2DelayCellOfst[10]=10 cells (3 PI)
8985 11:41:20.744036 u2DelayCellOfst[11]=3 cells (1 PI)
8986 11:41:20.747548 u2DelayCellOfst[12]=13 cells (4 PI)
8987 11:41:20.747982 u2DelayCellOfst[13]=13 cells (4 PI)
8988 11:41:20.751011 u2DelayCellOfst[14]=17 cells (5 PI)
8989 11:41:20.753981 u2DelayCellOfst[15]=17 cells (5 PI)
8990 11:41:20.760268 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8991 11:41:20.763703 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8992 11:41:20.766896 DramC Write-DBI on
8993 11:41:20.767335 ==
8994 11:41:20.770206 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 11:41:20.773494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 11:41:20.773577 ==
8997 11:41:20.773642
8998 11:41:20.773701
8999 11:41:20.776913 TX Vref Scan disable
9000 11:41:20.777002 == TX Byte 0 ==
9001 11:41:20.783173 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9002 11:41:20.783256 == TX Byte 1 ==
9003 11:41:20.786496 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9004 11:41:20.789691 DramC Write-DBI off
9005 11:41:20.789774
9006 11:41:20.789839 [DATLAT]
9007 11:41:20.793011 Freq=1600, CH1 RK1
9008 11:41:20.793094
9009 11:41:20.793159 DATLAT Default: 0xf
9010 11:41:20.796477 0, 0xFFFF, sum = 0
9011 11:41:20.796562 1, 0xFFFF, sum = 0
9012 11:41:20.799598 2, 0xFFFF, sum = 0
9013 11:41:20.803038 3, 0xFFFF, sum = 0
9014 11:41:20.803122 4, 0xFFFF, sum = 0
9015 11:41:20.806090 5, 0xFFFF, sum = 0
9016 11:41:20.806180 6, 0xFFFF, sum = 0
9017 11:41:20.809573 7, 0xFFFF, sum = 0
9018 11:41:20.809656 8, 0xFFFF, sum = 0
9019 11:41:20.812553 9, 0xFFFF, sum = 0
9020 11:41:20.812637 10, 0xFFFF, sum = 0
9021 11:41:20.816186 11, 0xFFFF, sum = 0
9022 11:41:20.816269 12, 0xFFFF, sum = 0
9023 11:41:20.819750 13, 0xFFFF, sum = 0
9024 11:41:20.819832 14, 0x0, sum = 1
9025 11:41:20.822822 15, 0x0, sum = 2
9026 11:41:20.822905 16, 0x0, sum = 3
9027 11:41:20.825946 17, 0x0, sum = 4
9028 11:41:20.826031 best_step = 15
9029 11:41:20.826123
9030 11:41:20.826212 ==
9031 11:41:20.829458 Dram Type= 6, Freq= 0, CH_1, rank 1
9032 11:41:20.835820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9033 11:41:20.835928 ==
9034 11:41:20.836022 RX Vref Scan: 0
9035 11:41:20.836110
9036 11:41:20.839367 RX Vref 0 -> 0, step: 1
9037 11:41:20.839448
9038 11:41:20.842667 RX Delay 19 -> 252, step: 4
9039 11:41:20.845973 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9040 11:41:20.849220 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
9041 11:41:20.852437 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9042 11:41:20.858864 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9043 11:41:20.862124 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9044 11:41:20.865720 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9045 11:41:20.868757 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9046 11:41:20.871987 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
9047 11:41:20.875316 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9048 11:41:20.882240 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9049 11:41:20.885339 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9050 11:41:20.888642 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9051 11:41:20.892146 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9052 11:41:20.898424 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9053 11:41:20.902025 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9054 11:41:20.904963 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9055 11:41:20.905085 ==
9056 11:41:20.908795 Dram Type= 6, Freq= 0, CH_1, rank 1
9057 11:41:20.911947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9058 11:41:20.912054 ==
9059 11:41:20.915075 DQS Delay:
9060 11:41:20.915156 DQS0 = 0, DQS1 = 0
9061 11:41:20.918245 DQM Delay:
9062 11:41:20.918326 DQM0 = 134, DQM1 = 130
9063 11:41:20.918390 DQ Delay:
9064 11:41:20.924903 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
9065 11:41:20.928680 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
9066 11:41:20.931560 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9067 11:41:20.934826 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9068 11:41:20.934901
9069 11:41:20.934963
9070 11:41:20.935021
9071 11:41:20.938344 [DramC_TX_OE_Calibration] TA2
9072 11:41:20.941453 Original DQ_B0 (3 6) =30, OEN = 27
9073 11:41:20.944947 Original DQ_B1 (3 6) =30, OEN = 27
9074 11:41:20.945069 24, 0x0, End_B0=24 End_B1=24
9075 11:41:20.948025 25, 0x0, End_B0=25 End_B1=25
9076 11:41:20.951513 26, 0x0, End_B0=26 End_B1=26
9077 11:41:20.954976 27, 0x0, End_B0=27 End_B1=27
9078 11:41:20.958075 28, 0x0, End_B0=28 End_B1=28
9079 11:41:20.958149 29, 0x0, End_B0=29 End_B1=29
9080 11:41:20.961469 30, 0x0, End_B0=30 End_B1=30
9081 11:41:20.964671 31, 0x4141, End_B0=30 End_B1=30
9082 11:41:20.968008 Byte0 end_step=30 best_step=27
9083 11:41:20.971205 Byte1 end_step=30 best_step=27
9084 11:41:20.974662 Byte0 TX OE(2T, 0.5T) = (3, 3)
9085 11:41:20.974733 Byte1 TX OE(2T, 0.5T) = (3, 3)
9086 11:41:20.974797
9087 11:41:20.974853
9088 11:41:20.984465 [DQSOSCAuto] RK1, (LSB)MR18= 0x1904, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
9089 11:41:20.987706 CH1 RK1: MR19=303, MR18=1904
9090 11:41:20.994361 CH1_RK1: MR19=0x303, MR18=0x1904, DQSOSC=397, MR23=63, INC=23, DEC=15
9091 11:41:20.994548 [RxdqsGatingPostProcess] freq 1600
9092 11:41:21.000896 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9093 11:41:21.004523 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 11:41:21.007602 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 11:41:21.010907 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 11:41:21.014363 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 11:41:21.017788 best DQS0 dly(2T, 0.5T) = (1, 1)
9098 11:41:21.020808 best DQS1 dly(2T, 0.5T) = (1, 1)
9099 11:41:21.024271 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9100 11:41:21.027480 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9101 11:41:21.027657 Pre-setting of DQS Precalculation
9102 11:41:21.034201 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9103 11:41:21.041112 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9104 11:41:21.047739 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9105 11:41:21.048151
9106 11:41:21.048549
9107 11:41:21.051241 [Calibration Summary] 3200 Mbps
9108 11:41:21.054476 CH 0, Rank 0
9109 11:41:21.055019 SW Impedance : PASS
9110 11:41:21.057582 DUTY Scan : NO K
9111 11:41:21.060886 ZQ Calibration : PASS
9112 11:41:21.061336 Jitter Meter : NO K
9113 11:41:21.064399 CBT Training : PASS
9114 11:41:21.067428 Write leveling : PASS
9115 11:41:21.067915 RX DQS gating : PASS
9116 11:41:21.070906 RX DQ/DQS(RDDQC) : PASS
9117 11:41:21.074506 TX DQ/DQS : PASS
9118 11:41:21.074924 RX DATLAT : PASS
9119 11:41:21.077674 RX DQ/DQS(Engine): PASS
9120 11:41:21.080671 TX OE : PASS
9121 11:41:21.081177 All Pass.
9122 11:41:21.081548
9123 11:41:21.082001 CH 0, Rank 1
9124 11:41:21.084386 SW Impedance : PASS
9125 11:41:21.087494 DUTY Scan : NO K
9126 11:41:21.087912 ZQ Calibration : PASS
9127 11:41:21.090664 Jitter Meter : NO K
9128 11:41:21.091080 CBT Training : PASS
9129 11:41:21.094072 Write leveling : PASS
9130 11:41:21.097078 RX DQS gating : PASS
9131 11:41:21.097461 RX DQ/DQS(RDDQC) : PASS
9132 11:41:21.100391 TX DQ/DQS : PASS
9133 11:41:21.104353 RX DATLAT : PASS
9134 11:41:21.104861 RX DQ/DQS(Engine): PASS
9135 11:41:21.107243 TX OE : PASS
9136 11:41:21.107659 All Pass.
9137 11:41:21.107984
9138 11:41:21.110366 CH 1, Rank 0
9139 11:41:21.110783 SW Impedance : PASS
9140 11:41:21.113920 DUTY Scan : NO K
9141 11:41:21.117233 ZQ Calibration : PASS
9142 11:41:21.117646 Jitter Meter : NO K
9143 11:41:21.120719 CBT Training : PASS
9144 11:41:21.124043 Write leveling : PASS
9145 11:41:21.124551 RX DQS gating : PASS
9146 11:41:21.127239 RX DQ/DQS(RDDQC) : PASS
9147 11:41:21.130514 TX DQ/DQS : PASS
9148 11:41:21.131040 RX DATLAT : PASS
9149 11:41:21.133544 RX DQ/DQS(Engine): PASS
9150 11:41:21.136966 TX OE : PASS
9151 11:41:21.137415 All Pass.
9152 11:41:21.137739
9153 11:41:21.138042 CH 1, Rank 1
9154 11:41:21.140316 SW Impedance : PASS
9155 11:41:21.143521 DUTY Scan : NO K
9156 11:41:21.143937 ZQ Calibration : PASS
9157 11:41:21.146725 Jitter Meter : NO K
9158 11:41:21.150271 CBT Training : PASS
9159 11:41:21.150976 Write leveling : PASS
9160 11:41:21.153434 RX DQS gating : PASS
9161 11:41:21.154111 RX DQ/DQS(RDDQC) : PASS
9162 11:41:21.156670 TX DQ/DQS : PASS
9163 11:41:21.160161 RX DATLAT : PASS
9164 11:41:21.160849 RX DQ/DQS(Engine): PASS
9165 11:41:21.163138 TX OE : PASS
9166 11:41:21.163623 All Pass.
9167 11:41:21.164073
9168 11:41:21.166544 DramC Write-DBI on
9169 11:41:21.169658 PER_BANK_REFRESH: Hybrid Mode
9170 11:41:21.170029 TX_TRACKING: ON
9171 11:41:21.179900 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9172 11:41:21.186181 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9173 11:41:21.196194 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9174 11:41:21.199312 [FAST_K] Save calibration result to emmc
9175 11:41:21.199422 sync common calibartion params.
9176 11:41:21.202974 sync cbt_mode0:1, 1:1
9177 11:41:21.206000 dram_init: ddr_geometry: 2
9178 11:41:21.209386 dram_init: ddr_geometry: 2
9179 11:41:21.209522 dram_init: ddr_geometry: 2
9180 11:41:21.212533 0:dram_rank_size:100000000
9181 11:41:21.215661 1:dram_rank_size:100000000
9182 11:41:21.219369 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9183 11:41:21.222421 DFS_SHUFFLE_HW_MODE: ON
9184 11:41:21.225729 dramc_set_vcore_voltage set vcore to 725000
9185 11:41:21.228872 Read voltage for 1600, 0
9186 11:41:21.228979 Vio18 = 0
9187 11:41:21.232182 Vcore = 725000
9188 11:41:21.232280 Vdram = 0
9189 11:41:21.232368 Vddq = 0
9190 11:41:21.232456 Vmddr = 0
9191 11:41:21.235460 switch to 3200 Mbps bootup
9192 11:41:21.238750 [DramcRunTimeConfig]
9193 11:41:21.238855 PHYPLL
9194 11:41:21.242146 DPM_CONTROL_AFTERK: ON
9195 11:41:21.242243 PER_BANK_REFRESH: ON
9196 11:41:21.245611 REFRESH_OVERHEAD_REDUCTION: ON
9197 11:41:21.248959 CMD_PICG_NEW_MODE: OFF
9198 11:41:21.249068 XRTWTW_NEW_MODE: ON
9199 11:41:21.252129 XRTRTR_NEW_MODE: ON
9200 11:41:21.252231 TX_TRACKING: ON
9201 11:41:21.255535 RDSEL_TRACKING: OFF
9202 11:41:21.258999 DQS Precalculation for DVFS: ON
9203 11:41:21.259099 RX_TRACKING: OFF
9204 11:41:21.261966 HW_GATING DBG: ON
9205 11:41:21.262072 ZQCS_ENABLE_LP4: ON
9206 11:41:21.265562 RX_PICG_NEW_MODE: ON
9207 11:41:21.265643 TX_PICG_NEW_MODE: ON
9208 11:41:21.268779 ENABLE_RX_DCM_DPHY: ON
9209 11:41:21.272104 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9210 11:41:21.275304 DUMMY_READ_FOR_TRACKING: OFF
9211 11:41:21.275405 !!! SPM_CONTROL_AFTERK: OFF
9212 11:41:21.278759 !!! SPM could not control APHY
9213 11:41:21.282002 IMPEDANCE_TRACKING: ON
9214 11:41:21.282089 TEMP_SENSOR: ON
9215 11:41:21.285466 HW_SAVE_FOR_SR: OFF
9216 11:41:21.288694 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9217 11:41:21.292004 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9218 11:41:21.292104 Read ODT Tracking: ON
9219 11:41:21.295470 Refresh Rate DeBounce: ON
9220 11:41:21.298394 DFS_NO_QUEUE_FLUSH: ON
9221 11:41:21.301803 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9222 11:41:21.301952 ENABLE_DFS_RUNTIME_MRW: OFF
9223 11:41:21.305350 DDR_RESERVE_NEW_MODE: ON
9224 11:41:21.308375 MR_CBT_SWITCH_FREQ: ON
9225 11:41:21.308476 =========================
9226 11:41:21.328758 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9227 11:41:21.331850 dram_init: ddr_geometry: 2
9228 11:41:21.350407 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9229 11:41:21.353526 dram_init: dram init end (result: 0)
9230 11:41:21.360221 DRAM-K: Full calibration passed in 24534 msecs
9231 11:41:21.363579 MRC: failed to locate region type 0.
9232 11:41:21.363679 DRAM rank0 size:0x100000000,
9233 11:41:21.366832 DRAM rank1 size=0x100000000
9234 11:41:21.376682 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9235 11:41:21.383605 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9236 11:41:21.390040 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9237 11:41:21.399957 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9238 11:41:21.400045 DRAM rank0 size:0x100000000,
9239 11:41:21.403059 DRAM rank1 size=0x100000000
9240 11:41:21.403141 CBMEM:
9241 11:41:21.406521 IMD: root @ 0xfffff000 254 entries.
9242 11:41:21.409784 IMD: root @ 0xffffec00 62 entries.
9243 11:41:21.413230 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9244 11:41:21.419418 WARNING: RO_VPD is uninitialized or empty.
9245 11:41:21.423026 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9246 11:41:21.430599 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9247 11:41:21.443060 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9248 11:41:21.454403 BS: romstage times (exec / console): total (unknown) / 24032 ms
9249 11:41:21.454491
9250 11:41:21.454556
9251 11:41:21.464442 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9252 11:41:21.467814 ARM64: Exception handlers installed.
9253 11:41:21.471187 ARM64: Testing exception
9254 11:41:21.474229 ARM64: Done test exception
9255 11:41:21.474326 Enumerating buses...
9256 11:41:21.477629 Show all devs... Before device enumeration.
9257 11:41:21.480812 Root Device: enabled 1
9258 11:41:21.484153 CPU_CLUSTER: 0: enabled 1
9259 11:41:21.484260 CPU: 00: enabled 1
9260 11:41:21.487641 Compare with tree...
9261 11:41:21.487723 Root Device: enabled 1
9262 11:41:21.490743 CPU_CLUSTER: 0: enabled 1
9263 11:41:21.493962 CPU: 00: enabled 1
9264 11:41:21.494044 Root Device scanning...
9265 11:41:21.497392 scan_static_bus for Root Device
9266 11:41:21.500957 CPU_CLUSTER: 0 enabled
9267 11:41:21.504545 scan_static_bus for Root Device done
9268 11:41:21.507759 scan_bus: bus Root Device finished in 8 msecs
9269 11:41:21.507931 done
9270 11:41:21.514322 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9271 11:41:21.517580 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9272 11:41:21.524344 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9273 11:41:21.527526 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9274 11:41:21.530938 Allocating resources...
9275 11:41:21.534270 Reading resources...
9276 11:41:21.537610 Root Device read_resources bus 0 link: 0
9277 11:41:21.540792 DRAM rank0 size:0x100000000,
9278 11:41:21.541448 DRAM rank1 size=0x100000000
9279 11:41:21.544294 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9280 11:41:21.547454 CPU: 00 missing read_resources
9281 11:41:21.554011 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9282 11:41:21.557185 Root Device read_resources bus 0 link: 0 done
9283 11:41:21.557644 Done reading resources.
9284 11:41:21.563992 Show resources in subtree (Root Device)...After reading.
9285 11:41:21.567277 Root Device child on link 0 CPU_CLUSTER: 0
9286 11:41:21.570469 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 11:41:21.580437 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 11:41:21.581067 CPU: 00
9289 11:41:21.583671 Root Device assign_resources, bus 0 link: 0
9290 11:41:21.586862 CPU_CLUSTER: 0 missing set_resources
9291 11:41:21.593616 Root Device assign_resources, bus 0 link: 0 done
9292 11:41:21.594032 Done setting resources.
9293 11:41:21.600054 Show resources in subtree (Root Device)...After assigning values.
9294 11:41:21.603280 Root Device child on link 0 CPU_CLUSTER: 0
9295 11:41:21.606604 CPU_CLUSTER: 0 child on link 0 CPU: 00
9296 11:41:21.616596 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9297 11:41:21.617109 CPU: 00
9298 11:41:21.620093 Done allocating resources.
9299 11:41:21.626269 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9300 11:41:21.626352 Enabling resources...
9301 11:41:21.626454 done.
9302 11:41:21.632839 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9303 11:41:21.636131 Initializing devices...
9304 11:41:21.636242 Root Device init
9305 11:41:21.639526 init hardware done!
9306 11:41:21.639615 0x00000018: ctrlr->caps
9307 11:41:21.642791 52.000 MHz: ctrlr->f_max
9308 11:41:21.646254 0.400 MHz: ctrlr->f_min
9309 11:41:21.646338 0x40ff8080: ctrlr->voltages
9310 11:41:21.649619 sclk: 390625
9311 11:41:21.649694 Bus Width = 1
9312 11:41:21.649758 sclk: 390625
9313 11:41:21.652952 Bus Width = 1
9314 11:41:21.653080 Early init status = 3
9315 11:41:21.659916 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9316 11:41:21.662877 in-header: 03 fc 00 00 01 00 00 00
9317 11:41:21.666332 in-data: 00
9318 11:41:21.669615 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9319 11:41:21.673290 in-header: 03 fd 00 00 00 00 00 00
9320 11:41:21.676586 in-data:
9321 11:41:21.680124 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9322 11:41:21.683279 in-header: 03 fc 00 00 01 00 00 00
9323 11:41:21.686613 in-data: 00
9324 11:41:21.690137 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9325 11:41:21.694905 in-header: 03 fd 00 00 00 00 00 00
9326 11:41:21.697673 in-data:
9327 11:41:21.701246 [SSUSB] Setting up USB HOST controller...
9328 11:41:21.704658 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9329 11:41:21.707670 [SSUSB] phy power-on done.
9330 11:41:21.711037 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9331 11:41:21.717696 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9332 11:41:21.720971 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9333 11:41:21.727485 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9334 11:41:21.734413 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9335 11:41:21.740869 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9336 11:41:21.747221 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9337 11:41:21.754140 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9338 11:41:21.757350 SPM: binary array size = 0x9dc
9339 11:41:21.760252 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9340 11:41:21.766984 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9341 11:41:21.773327 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9342 11:41:21.780164 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9343 11:41:21.783165 configure_display: Starting display init
9344 11:41:21.817544 anx7625_power_on_init: Init interface.
9345 11:41:21.821084 anx7625_disable_pd_protocol: Disabled PD feature.
9346 11:41:21.824457 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9347 11:41:21.852305 anx7625_start_dp_work: Secure OCM version=00
9348 11:41:21.855479 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9349 11:41:21.870022 sp_tx_get_edid_block: EDID Block = 1
9350 11:41:21.972897 Extracted contents:
9351 11:41:21.976326 header: 00 ff ff ff ff ff ff 00
9352 11:41:21.979406 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9353 11:41:21.983080 version: 01 04
9354 11:41:21.985989 basic params: 95 1f 11 78 0a
9355 11:41:21.989456 chroma info: 76 90 94 55 54 90 27 21 50 54
9356 11:41:21.992350 established: 00 00 00
9357 11:41:21.999056 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9358 11:41:22.002348 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9359 11:41:22.009086 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9360 11:41:22.015825 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9361 11:41:22.022551 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9362 11:41:22.025631 extensions: 00
9363 11:41:22.025701 checksum: fb
9364 11:41:22.025763
9365 11:41:22.029077 Manufacturer: IVO Model 57d Serial Number 0
9366 11:41:22.032247 Made week 0 of 2020
9367 11:41:22.035678 EDID version: 1.4
9368 11:41:22.035749 Digital display
9369 11:41:22.038609 6 bits per primary color channel
9370 11:41:22.038680 DisplayPort interface
9371 11:41:22.042282 Maximum image size: 31 cm x 17 cm
9372 11:41:22.045287 Gamma: 220%
9373 11:41:22.045356 Check DPMS levels
9374 11:41:22.051786 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9375 11:41:22.055339 First detailed timing is preferred timing
9376 11:41:22.055414 Established timings supported:
9377 11:41:22.058889 Standard timings supported:
9378 11:41:22.061728 Detailed timings
9379 11:41:22.064991 Hex of detail: 383680a07038204018303c0035ae10000019
9380 11:41:22.071575 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9381 11:41:22.075095 0780 0798 07c8 0820 hborder 0
9382 11:41:22.078571 0438 043b 0447 0458 vborder 0
9383 11:41:22.081584 -hsync -vsync
9384 11:41:22.081654 Did detailed timing
9385 11:41:22.088266 Hex of detail: 000000000000000000000000000000000000
9386 11:41:22.091452 Manufacturer-specified data, tag 0
9387 11:41:22.094845 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9388 11:41:22.098230 ASCII string: InfoVision
9389 11:41:22.101270 Hex of detail: 000000fe00523134304e574635205248200a
9390 11:41:22.105151 ASCII string: R140NWF5 RH
9391 11:41:22.105220 Checksum
9392 11:41:22.108003 Checksum: 0xfb (valid)
9393 11:41:22.111327 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9394 11:41:22.114664 DSI data_rate: 832800000 bps
9395 11:41:22.120958 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9396 11:41:22.124475 anx7625_parse_edid: pixelclock(138800).
9397 11:41:22.127704 hactive(1920), hsync(48), hfp(24), hbp(88)
9398 11:41:22.130874 vactive(1080), vsync(12), vfp(3), vbp(17)
9399 11:41:22.134377 anx7625_dsi_config: config dsi.
9400 11:41:22.141057 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9401 11:41:22.154712 anx7625_dsi_config: success to config DSI
9402 11:41:22.158145 anx7625_dp_start: MIPI phy setup OK.
9403 11:41:22.161271 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9404 11:41:22.164909 mtk_ddp_mode_set invalid vrefresh 60
9405 11:41:22.168195 main_disp_path_setup
9406 11:41:22.168318 ovl_layer_smi_id_en
9407 11:41:22.171426 ovl_layer_smi_id_en
9408 11:41:22.171501 ccorr_config
9409 11:41:22.171570 aal_config
9410 11:41:22.174634 gamma_config
9411 11:41:22.174703 postmask_config
9412 11:41:22.178112 dither_config
9413 11:41:22.181123 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9414 11:41:22.188086 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9415 11:41:22.191149 Root Device init finished in 551 msecs
9416 11:41:22.194463 CPU_CLUSTER: 0 init
9417 11:41:22.201182 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9418 11:41:22.207760 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9419 11:41:22.207834 APU_MBOX 0x190000b0 = 0x10001
9420 11:41:22.211011 APU_MBOX 0x190001b0 = 0x10001
9421 11:41:22.214485 APU_MBOX 0x190005b0 = 0x10001
9422 11:41:22.217673 APU_MBOX 0x190006b0 = 0x10001
9423 11:41:22.224236 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9424 11:41:22.234251 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9425 11:41:22.246248 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9426 11:41:22.253009 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9427 11:41:22.264397 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9428 11:41:22.273727 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9429 11:41:22.277136 CPU_CLUSTER: 0 init finished in 81 msecs
9430 11:41:22.280132 Devices initialized
9431 11:41:22.283586 Show all devs... After init.
9432 11:41:22.283662 Root Device: enabled 1
9433 11:41:22.287249 CPU_CLUSTER: 0: enabled 1
9434 11:41:22.290090 CPU: 00: enabled 1
9435 11:41:22.293436 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9436 11:41:22.296911 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9437 11:41:22.300011 ELOG: NV offset 0x57f000 size 0x1000
9438 11:41:22.306632 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9439 11:41:22.313300 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9440 11:41:22.316654 ELOG: Event(17) added with size 13 at 2023-06-15 11:41:17 UTC
9441 11:41:22.323317 out: cmd=0x121: 03 db 21 01 00 00 00 00
9442 11:41:22.326792 in-header: 03 0f 00 00 2c 00 00 00
9443 11:41:22.339527 in-data: 50 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9444 11:41:22.343056 ELOG: Event(A1) added with size 10 at 2023-06-15 11:41:17 UTC
9445 11:41:22.349701 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9446 11:41:22.356240 ELOG: Event(A0) added with size 9 at 2023-06-15 11:41:17 UTC
9447 11:41:22.359599 elog_add_boot_reason: Logged dev mode boot
9448 11:41:22.366141 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9449 11:41:22.366249 Finalize devices...
9450 11:41:22.369465 Devices finalized
9451 11:41:22.373045 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9452 11:41:22.376181 Writing coreboot table at 0xffe64000
9453 11:41:22.382582 0. 000000000010a000-0000000000113fff: RAMSTAGE
9454 11:41:22.385906 1. 0000000040000000-00000000400fffff: RAM
9455 11:41:22.389308 2. 0000000040100000-000000004032afff: RAMSTAGE
9456 11:41:22.393181 3. 000000004032b000-00000000545fffff: RAM
9457 11:41:22.396034 4. 0000000054600000-000000005465ffff: BL31
9458 11:41:22.402495 5. 0000000054660000-00000000ffe63fff: RAM
9459 11:41:22.405994 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9460 11:41:22.409269 7. 0000000100000000-000000023fffffff: RAM
9461 11:41:22.412664 Passing 5 GPIOs to payload:
9462 11:41:22.415938 NAME | PORT | POLARITY | VALUE
9463 11:41:22.422486 EC in RW | 0x000000aa | low | undefined
9464 11:41:22.425694 EC interrupt | 0x00000005 | low | undefined
9465 11:41:22.432175 TPM interrupt | 0x000000ab | high | undefined
9466 11:41:22.435615 SD card detect | 0x00000011 | high | undefined
9467 11:41:22.438775 speaker enable | 0x00000093 | high | undefined
9468 11:41:22.445381 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9469 11:41:22.448668 in-header: 03 f9 00 00 02 00 00 00
9470 11:41:22.448753 in-data: 02 00
9471 11:41:22.451955 ADC[4]: Raw value=901032 ID=7
9472 11:41:22.455398 ADC[3]: Raw value=213179 ID=1
9473 11:41:22.455513 RAM Code: 0x71
9474 11:41:22.458604 ADC[6]: Raw value=74502 ID=0
9475 11:41:22.462074 ADC[5]: Raw value=212072 ID=1
9476 11:41:22.462158 SKU Code: 0x1
9477 11:41:22.468382 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9478 11:41:22.471875 coreboot table: 964 bytes.
9479 11:41:22.475152 IMD ROOT 0. 0xfffff000 0x00001000
9480 11:41:22.478504 IMD SMALL 1. 0xffffe000 0x00001000
9481 11:41:22.481699 RO MCACHE 2. 0xffffc000 0x00001104
9482 11:41:22.484811 CONSOLE 3. 0xfff7c000 0x00080000
9483 11:41:22.488627 FMAP 4. 0xfff7b000 0x00000452
9484 11:41:22.491475 TIME STAMP 5. 0xfff7a000 0x00000910
9485 11:41:22.494966 VBOOT WORK 6. 0xfff66000 0x00014000
9486 11:41:22.498117 RAMOOPS 7. 0xffe66000 0x00100000
9487 11:41:22.498199 COREBOOT 8. 0xffe64000 0x00002000
9488 11:41:22.501437 IMD small region:
9489 11:41:22.504871 IMD ROOT 0. 0xffffec00 0x00000400
9490 11:41:22.508019 VPD 1. 0xffffeba0 0x0000004c
9491 11:41:22.511389 MMC STATUS 2. 0xffffeb80 0x00000004
9492 11:41:22.518355 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9493 11:41:22.518440 Probing TPM: done!
9494 11:41:22.524924 Connected to device vid:did:rid of 1ae0:0028:00
9495 11:41:22.531308 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9496 11:41:22.534868 Initialized TPM device CR50 revision 0
9497 11:41:22.538537 Checking cr50 for pending updates
9498 11:41:22.544254 Reading cr50 TPM mode
9499 11:41:22.553061 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9500 11:41:22.559224 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9501 11:41:22.599551 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9502 11:41:22.603029 Checking segment from ROM address 0x40100000
9503 11:41:22.605961 Checking segment from ROM address 0x4010001c
9504 11:41:22.612727 Loading segment from ROM address 0x40100000
9505 11:41:22.612841 code (compression=0)
9506 11:41:22.622433 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9507 11:41:22.629156 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9508 11:41:22.629238 it's not compressed!
9509 11:41:22.635750 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9510 11:41:22.642440 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9511 11:41:22.659914 Loading segment from ROM address 0x4010001c
9512 11:41:22.660016 Entry Point 0x80000000
9513 11:41:22.663167 Loaded segments
9514 11:41:22.666315 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9515 11:41:22.673011 Jumping to boot code at 0x80000000(0xffe64000)
9516 11:41:22.679746 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9517 11:41:22.686027 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9518 11:41:22.694318 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9519 11:41:22.697523 Checking segment from ROM address 0x40100000
9520 11:41:22.700985 Checking segment from ROM address 0x4010001c
9521 11:41:22.707552 Loading segment from ROM address 0x40100000
9522 11:41:22.707630 code (compression=1)
9523 11:41:22.714457 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9524 11:41:22.724058 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9525 11:41:22.724142 using LZMA
9526 11:41:22.732858 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9527 11:41:22.739351 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9528 11:41:22.742781 Loading segment from ROM address 0x4010001c
9529 11:41:22.742860 Entry Point 0x54601000
9530 11:41:22.746060 Loaded segments
9531 11:41:22.748921 NOTICE: MT8192 bl31_setup
9532 11:41:22.756251 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9533 11:41:22.759727 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9534 11:41:22.762782 WARNING: region 0:
9535 11:41:22.766208 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 11:41:22.766283 WARNING: region 1:
9537 11:41:22.772867 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9538 11:41:22.776082 WARNING: region 2:
9539 11:41:22.779754 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9540 11:41:22.782921 WARNING: region 3:
9541 11:41:22.786167 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9542 11:41:22.789478 WARNING: region 4:
9543 11:41:22.796070 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 11:41:22.796147 WARNING: region 5:
9545 11:41:22.799392 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 11:41:22.803126 WARNING: region 6:
9547 11:41:22.806342 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 11:41:22.809419 WARNING: region 7:
9549 11:41:22.812754 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 11:41:22.819125 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9551 11:41:22.822881 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9552 11:41:22.826266 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9553 11:41:22.832744 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9554 11:41:22.835801 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9555 11:41:22.839077 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9556 11:41:22.846063 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9557 11:41:22.849346 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9558 11:41:22.856022 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9559 11:41:22.859109 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9560 11:41:22.862649 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9561 11:41:22.869329 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9562 11:41:22.872527 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9563 11:41:22.875729 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9564 11:41:22.882641 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9565 11:41:22.886021 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9566 11:41:22.892051 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9567 11:41:22.895895 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9568 11:41:22.898887 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9569 11:41:22.905466 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9570 11:41:22.908969 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9571 11:41:22.916293 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9572 11:41:22.918689 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9573 11:41:22.922003 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9574 11:41:22.929081 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9575 11:41:22.932243 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9576 11:41:22.938622 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9577 11:41:22.942044 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9578 11:41:22.945569 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9579 11:41:22.951948 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9580 11:41:22.955415 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9581 11:41:22.961952 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9582 11:41:22.965619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9583 11:41:22.968868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9584 11:41:22.971930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9585 11:41:22.978632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9586 11:41:22.982256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9587 11:41:22.985342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9588 11:41:22.988704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9589 11:41:22.995429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9590 11:41:22.998683 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9591 11:41:23.002039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9592 11:41:23.005281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9593 11:41:23.012307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9594 11:41:23.015384 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9595 11:41:23.018810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9596 11:41:23.021996 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9597 11:41:23.028852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9598 11:41:23.032032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9599 11:41:23.035781 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9600 11:41:23.041921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9601 11:41:23.045192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9602 11:41:23.051788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9603 11:41:23.055302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9604 11:41:23.061945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9605 11:41:23.065035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9606 11:41:23.068835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9607 11:41:23.074965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9608 11:41:23.078572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9609 11:41:23.085302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9610 11:41:23.088331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9611 11:41:23.095402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9612 11:41:23.098249 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9613 11:41:23.105014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9614 11:41:23.108471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9615 11:41:23.111561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9616 11:41:23.118551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9617 11:41:23.121456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9618 11:41:23.128508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9619 11:41:23.131460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9620 11:41:23.138218 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9621 11:41:23.141414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9622 11:41:23.144766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9623 11:41:23.151529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9624 11:41:23.154826 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9625 11:41:23.161774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9626 11:41:23.164831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9627 11:41:23.171644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9628 11:41:23.174891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9629 11:41:23.181290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9630 11:41:23.184575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9631 11:41:23.187875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9632 11:41:23.194668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9633 11:41:23.198062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9634 11:41:23.204604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9635 11:41:23.208209 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9636 11:41:23.214370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9637 11:41:23.217855 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9638 11:41:23.221012 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9639 11:41:23.228051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9640 11:41:23.231642 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9641 11:41:23.237886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9642 11:41:23.241287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9643 11:41:23.247725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9644 11:41:23.251024 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9645 11:41:23.257640 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9646 11:41:23.260863 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9647 11:41:23.264356 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9648 11:41:23.267616 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9649 11:41:23.274478 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9650 11:41:23.277617 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9651 11:41:23.281087 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9652 11:41:23.287378 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9653 11:41:23.290832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9654 11:41:23.297196 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9655 11:41:23.300935 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9656 11:41:23.304289 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9657 11:41:23.310766 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9658 11:41:23.313899 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9659 11:41:23.320913 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9660 11:41:23.323940 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9661 11:41:23.327455 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9662 11:41:23.333863 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9663 11:41:23.337533 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9664 11:41:23.343843 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9665 11:41:23.347434 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9666 11:41:23.350650 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9667 11:41:23.353775 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9668 11:41:23.360554 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9669 11:41:23.363738 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9670 11:41:23.367138 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9671 11:41:23.370628 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9672 11:41:23.377180 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9673 11:41:23.380320 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9674 11:41:23.383455 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9675 11:41:23.390423 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9676 11:41:23.393523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9677 11:41:23.400487 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9678 11:41:23.403640 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9679 11:41:23.406720 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9680 11:41:23.413341 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9681 11:41:23.416727 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9682 11:41:23.423673 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9683 11:41:23.426753 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9684 11:41:23.429977 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9685 11:41:23.436884 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9686 11:41:23.440377 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9687 11:41:23.443546 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9688 11:41:23.450109 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9689 11:41:23.453349 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9690 11:41:23.459812 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9691 11:41:23.463446 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9692 11:41:23.466758 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9693 11:41:23.473245 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9694 11:41:23.476520 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9695 11:41:23.483302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9696 11:41:23.486549 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9697 11:41:23.489845 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9698 11:41:23.496809 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9699 11:41:23.499777 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9700 11:41:23.506512 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9701 11:41:23.509814 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9702 11:41:23.512953 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9703 11:41:23.519587 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9704 11:41:23.523043 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9705 11:41:23.530057 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9706 11:41:23.532990 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9707 11:41:23.536462 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9708 11:41:23.542971 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9709 11:41:23.546402 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9710 11:41:23.553220 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9711 11:41:23.556345 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9712 11:41:23.559530 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9713 11:41:23.566120 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9714 11:41:23.569348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9715 11:41:23.572906 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9716 11:41:23.579546 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9717 11:41:23.582570 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9718 11:41:23.589369 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9719 11:41:23.592423 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9720 11:41:23.599132 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9721 11:41:23.603091 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9722 11:41:23.606127 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9723 11:41:23.612446 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9724 11:41:23.616160 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9725 11:41:23.619077 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9726 11:41:23.625673 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9727 11:41:23.628840 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9728 11:41:23.635624 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9729 11:41:23.638947 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9730 11:41:23.642297 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9731 11:41:23.648902 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9732 11:41:23.652306 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9733 11:41:23.658802 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9734 11:41:23.662008 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9735 11:41:23.665443 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9736 11:41:23.671785 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9737 11:41:23.675348 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9738 11:41:23.681914 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9739 11:41:23.685144 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9740 11:41:23.691840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9741 11:41:23.694963 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9742 11:41:23.698228 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9743 11:41:23.704948 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9744 11:41:23.708182 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9745 11:41:23.714907 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9746 11:41:23.718176 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9747 11:41:23.721598 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9748 11:41:23.728298 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9749 11:41:23.731541 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9750 11:41:23.737952 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9751 11:41:23.741469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9752 11:41:23.747817 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9753 11:41:23.751264 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9754 11:41:23.754549 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9755 11:41:23.761065 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9756 11:41:23.764664 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9757 11:41:23.770975 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9758 11:41:23.774097 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9759 11:41:23.780915 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9760 11:41:23.784261 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9761 11:41:23.787588 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9762 11:41:23.793945 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9763 11:41:23.797140 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9764 11:41:23.803862 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9765 11:41:23.807062 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9766 11:41:23.813812 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9767 11:41:23.816917 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9768 11:41:23.823442 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9769 11:41:23.826765 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9770 11:41:23.829819 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9771 11:41:23.836909 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9772 11:41:23.839751 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9773 11:41:23.846495 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9774 11:41:23.849841 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9775 11:41:23.853323 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9776 11:41:23.859595 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9777 11:41:23.863369 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9778 11:41:23.869667 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9779 11:41:23.872750 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9780 11:41:23.876330 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9781 11:41:23.879251 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9782 11:41:23.886026 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9783 11:41:23.889381 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9784 11:41:23.892565 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9785 11:41:23.899269 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9786 11:41:23.902823 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9787 11:41:23.906153 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9788 11:41:23.912462 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9789 11:41:23.915972 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9790 11:41:23.922508 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9791 11:41:23.925671 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9792 11:41:23.928996 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9793 11:41:23.935791 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9794 11:41:23.939063 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9795 11:41:23.942503 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9796 11:41:23.948915 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9797 11:41:23.952186 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9798 11:41:23.955855 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9799 11:41:23.961899 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9800 11:41:23.965425 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9801 11:41:23.971843 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9802 11:41:23.975126 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9803 11:41:23.978357 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9804 11:41:23.985224 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9805 11:41:23.988402 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9806 11:41:23.994951 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9807 11:41:23.998635 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9808 11:41:24.001729 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9809 11:41:24.008172 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9810 11:41:24.011330 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9811 11:41:24.014634 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9812 11:41:24.021472 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9813 11:41:24.024884 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9814 11:41:24.028169 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9815 11:41:24.034952 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9816 11:41:24.037850 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9817 11:41:24.044848 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9818 11:41:24.047946 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9819 11:41:24.051325 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9820 11:41:24.054431 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9821 11:41:24.060917 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9822 11:41:24.064300 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9823 11:41:24.067561 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9824 11:41:24.071017 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9825 11:41:24.077480 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9826 11:41:24.080874 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9827 11:41:24.084093 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9828 11:41:24.087346 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9829 11:41:24.094049 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9830 11:41:24.097301 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9831 11:41:24.100447 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9832 11:41:24.107113 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9833 11:41:24.110395 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9834 11:41:24.117296 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9835 11:41:24.120570 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9836 11:41:24.123528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9837 11:41:24.130279 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9838 11:41:24.133386 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9839 11:41:24.140087 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9840 11:41:24.143609 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9841 11:41:24.146775 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9842 11:41:24.153812 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9843 11:41:24.156908 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9844 11:41:24.163546 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9845 11:41:24.166557 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9846 11:41:24.173443 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9847 11:41:24.176902 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9848 11:41:24.179773 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9849 11:41:24.186580 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9850 11:41:24.189840 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9851 11:41:24.196443 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9852 11:41:24.199570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9853 11:41:24.206275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9854 11:41:24.209379 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9855 11:41:24.212865 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9856 11:41:24.219281 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9857 11:41:24.222747 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9858 11:41:24.229255 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9859 11:41:24.232486 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9860 11:41:24.235965 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9861 11:41:24.242502 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9862 11:41:24.245999 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9863 11:41:24.252518 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9864 11:41:24.255713 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9865 11:41:24.259171 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9866 11:41:24.265381 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9867 11:41:24.268889 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9868 11:41:24.275218 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9869 11:41:24.278885 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9870 11:41:24.285357 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9871 11:41:24.288533 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9872 11:41:24.291968 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9873 11:41:24.298611 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9874 11:41:24.301917 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9875 11:41:24.308260 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9876 11:41:24.312013 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9877 11:41:24.318223 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9878 11:41:24.321819 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9879 11:41:24.325060 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9880 11:41:24.331610 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9881 11:41:24.334930 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9882 11:41:24.341241 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9883 11:41:24.344690 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9884 11:41:24.347836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9885 11:41:24.354729 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9886 11:41:24.357804 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9887 11:41:24.364439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9888 11:41:24.367738 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9889 11:41:24.374200 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9890 11:41:24.377591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9891 11:41:24.381256 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9892 11:41:24.387261 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9893 11:41:24.390801 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9894 11:41:24.397339 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9895 11:41:24.400482 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9896 11:41:24.403754 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9897 11:41:24.411480 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9898 11:41:24.413941 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9899 11:41:24.420343 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9900 11:41:24.423824 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9901 11:41:24.430412 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9902 11:41:24.433643 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9903 11:41:24.437034 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9904 11:41:24.443695 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9905 11:41:24.447110 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9906 11:41:24.453794 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9907 11:41:24.456792 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9908 11:41:24.463346 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9909 11:41:24.466834 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9910 11:41:24.470005 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9911 11:41:24.477064 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9912 11:41:24.479956 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9913 11:41:24.486935 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9914 11:41:24.490021 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9915 11:41:24.496884 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9916 11:41:24.499732 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9917 11:41:24.506733 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9918 11:41:24.510067 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9919 11:41:24.513332 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9920 11:41:24.520043 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9921 11:41:24.522968 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9922 11:41:24.529529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9923 11:41:24.532566 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9924 11:41:24.539235 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9925 11:41:24.542590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9926 11:41:24.549379 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9927 11:41:24.552456 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9928 11:41:24.555764 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9929 11:41:24.562570 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9930 11:41:24.565652 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9931 11:41:24.572588 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9932 11:41:24.575819 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9933 11:41:24.582370 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9934 11:41:24.585788 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9935 11:41:24.588862 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9936 11:41:24.595769 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9937 11:41:24.598779 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9938 11:41:24.605371 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9939 11:41:24.608797 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9940 11:41:24.615507 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9941 11:41:24.618544 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9942 11:41:24.625266 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9943 11:41:24.628732 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9944 11:41:24.631759 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9945 11:41:24.638312 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9946 11:41:24.641421 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9947 11:41:24.648349 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9948 11:41:24.651471 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9949 11:41:24.657914 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9950 11:41:24.661479 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9951 11:41:24.667964 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9952 11:41:24.671252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9953 11:41:24.674377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9954 11:41:24.681171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9955 11:41:24.684383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9956 11:41:24.690946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9957 11:41:24.694309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9958 11:41:24.701039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9959 11:41:24.704231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9960 11:41:24.710608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9961 11:41:24.714094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9962 11:41:24.720901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9963 11:41:24.724305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9964 11:41:24.730511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9965 11:41:24.733750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9966 11:41:24.740495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9967 11:41:24.743957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9968 11:41:24.750804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9969 11:41:24.753803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9970 11:41:24.760317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9971 11:41:24.763783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9972 11:41:24.770363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9973 11:41:24.773687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9974 11:41:24.780564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9975 11:41:24.783675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9976 11:41:24.790428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9977 11:41:24.793718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9978 11:41:24.800450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9979 11:41:24.803138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9980 11:41:24.810057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9981 11:41:24.813092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9982 11:41:24.820420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9983 11:41:24.822997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9984 11:41:24.826314 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9985 11:41:24.829632 INFO: [APUAPC] vio 0
9986 11:41:24.836549 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9987 11:41:24.839707 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9988 11:41:24.843015 INFO: [APUAPC] D0_APC_0: 0x400510
9989 11:41:24.846241 INFO: [APUAPC] D0_APC_1: 0x0
9990 11:41:24.849292 INFO: [APUAPC] D0_APC_2: 0x1540
9991 11:41:24.852864 INFO: [APUAPC] D0_APC_3: 0x0
9992 11:41:24.856169 INFO: [APUAPC] D1_APC_0: 0xffffffff
9993 11:41:24.859642 INFO: [APUAPC] D1_APC_1: 0xffffffff
9994 11:41:24.862511 INFO: [APUAPC] D1_APC_2: 0x3fffff
9995 11:41:24.865908 INFO: [APUAPC] D1_APC_3: 0x0
9996 11:41:24.869342 INFO: [APUAPC] D2_APC_0: 0xffffffff
9997 11:41:24.872500 INFO: [APUAPC] D2_APC_1: 0xffffffff
9998 11:41:24.875923 INFO: [APUAPC] D2_APC_2: 0x3fffff
9999 11:41:24.879173 INFO: [APUAPC] D2_APC_3: 0x0
10000 11:41:24.882659 INFO: [APUAPC] D3_APC_0: 0xffffffff
10001 11:41:24.885972 INFO: [APUAPC] D3_APC_1: 0xffffffff
10002 11:41:24.888992 INFO: [APUAPC] D3_APC_2: 0x3fffff
10003 11:41:24.892539 INFO: [APUAPC] D3_APC_3: 0x0
10004 11:41:24.895732 INFO: [APUAPC] D4_APC_0: 0xffffffff
10005 11:41:24.899165 INFO: [APUAPC] D4_APC_1: 0xffffffff
10006 11:41:24.902238 INFO: [APUAPC] D4_APC_2: 0x3fffff
10007 11:41:24.905634 INFO: [APUAPC] D4_APC_3: 0x0
10008 11:41:24.908833 INFO: [APUAPC] D5_APC_0: 0xffffffff
10009 11:41:24.912276 INFO: [APUAPC] D5_APC_1: 0xffffffff
10010 11:41:24.915757 INFO: [APUAPC] D5_APC_2: 0x3fffff
10011 11:41:24.915830 INFO: [APUAPC] D5_APC_3: 0x0
10012 11:41:24.918813 INFO: [APUAPC] D6_APC_0: 0xffffffff
10013 11:41:24.925481 INFO: [APUAPC] D6_APC_1: 0xffffffff
10014 11:41:24.929084 INFO: [APUAPC] D6_APC_2: 0x3fffff
10015 11:41:24.929180 INFO: [APUAPC] D6_APC_3: 0x0
10016 11:41:24.931930 INFO: [APUAPC] D7_APC_0: 0xffffffff
10017 11:41:24.935356 INFO: [APUAPC] D7_APC_1: 0xffffffff
10018 11:41:24.938476 INFO: [APUAPC] D7_APC_2: 0x3fffff
10019 11:41:24.942036 INFO: [APUAPC] D7_APC_3: 0x0
10020 11:41:24.945338 INFO: [APUAPC] D8_APC_0: 0xffffffff
10021 11:41:24.948303 INFO: [APUAPC] D8_APC_1: 0xffffffff
10022 11:41:24.951538 INFO: [APUAPC] D8_APC_2: 0x3fffff
10023 11:41:24.954888 INFO: [APUAPC] D8_APC_3: 0x0
10024 11:41:24.958339 INFO: [APUAPC] D9_APC_0: 0xffffffff
10025 11:41:24.961722 INFO: [APUAPC] D9_APC_1: 0xffffffff
10026 11:41:24.964867 INFO: [APUAPC] D9_APC_2: 0x3fffff
10027 11:41:24.967757 INFO: [APUAPC] D9_APC_3: 0x0
10028 11:41:24.971123 INFO: [APUAPC] D10_APC_0: 0xffffffff
10029 11:41:24.974427 INFO: [APUAPC] D10_APC_1: 0xffffffff
10030 11:41:24.977931 INFO: [APUAPC] D10_APC_2: 0x3fffff
10031 11:41:24.981097 INFO: [APUAPC] D10_APC_3: 0x0
10032 11:41:24.984490 INFO: [APUAPC] D11_APC_0: 0xffffffff
10033 11:41:24.991045 INFO: [APUAPC] D11_APC_1: 0xffffffff
10034 11:41:24.994345 INFO: [APUAPC] D11_APC_2: 0x3fffff
10035 11:41:24.994416 INFO: [APUAPC] D11_APC_3: 0x0
10036 11:41:24.997481 INFO: [APUAPC] D12_APC_0: 0xffffffff
10037 11:41:25.004118 INFO: [APUAPC] D12_APC_1: 0xffffffff
10038 11:41:25.007285 INFO: [APUAPC] D12_APC_2: 0x3fffff
10039 11:41:25.007381 INFO: [APUAPC] D12_APC_3: 0x0
10040 11:41:25.014213 INFO: [APUAPC] D13_APC_0: 0xffffffff
10041 11:41:25.017211 INFO: [APUAPC] D13_APC_1: 0xffffffff
10042 11:41:25.020903 INFO: [APUAPC] D13_APC_2: 0x3fffff
10043 11:41:25.024103 INFO: [APUAPC] D13_APC_3: 0x0
10044 11:41:25.027434 INFO: [APUAPC] D14_APC_0: 0xffffffff
10045 11:41:25.030340 INFO: [APUAPC] D14_APC_1: 0xffffffff
10046 11:41:25.033776 INFO: [APUAPC] D14_APC_2: 0x3fffff
10047 11:41:25.037259 INFO: [APUAPC] D14_APC_3: 0x0
10048 11:41:25.040446 INFO: [APUAPC] D15_APC_0: 0xffffffff
10049 11:41:25.043631 INFO: [APUAPC] D15_APC_1: 0xffffffff
10050 11:41:25.046781 INFO: [APUAPC] D15_APC_2: 0x3fffff
10051 11:41:25.050050 INFO: [APUAPC] D15_APC_3: 0x0
10052 11:41:25.050134 INFO: [APUAPC] APC_CON: 0x4
10053 11:41:25.053543 INFO: [NOCDAPC] D0_APC_0: 0x0
10054 11:41:25.056789 INFO: [NOCDAPC] D0_APC_1: 0x0
10055 11:41:25.059940 INFO: [NOCDAPC] D1_APC_0: 0x0
10056 11:41:25.063143 INFO: [NOCDAPC] D1_APC_1: 0xfff
10057 11:41:25.066546 INFO: [NOCDAPC] D2_APC_0: 0x0
10058 11:41:25.069967 INFO: [NOCDAPC] D2_APC_1: 0xfff
10059 11:41:25.073180 INFO: [NOCDAPC] D3_APC_0: 0x0
10060 11:41:25.076615 INFO: [NOCDAPC] D3_APC_1: 0xfff
10061 11:41:25.079666 INFO: [NOCDAPC] D4_APC_0: 0x0
10062 11:41:25.083129 INFO: [NOCDAPC] D4_APC_1: 0xfff
10063 11:41:25.086615 INFO: [NOCDAPC] D5_APC_0: 0x0
10064 11:41:25.086712 INFO: [NOCDAPC] D5_APC_1: 0xfff
10065 11:41:25.089548 INFO: [NOCDAPC] D6_APC_0: 0x0
10066 11:41:25.092964 INFO: [NOCDAPC] D6_APC_1: 0xfff
10067 11:41:25.096397 INFO: [NOCDAPC] D7_APC_0: 0x0
10068 11:41:25.099481 INFO: [NOCDAPC] D7_APC_1: 0xfff
10069 11:41:25.102926 INFO: [NOCDAPC] D8_APC_0: 0x0
10070 11:41:25.106096 INFO: [NOCDAPC] D8_APC_1: 0xfff
10071 11:41:25.109603 INFO: [NOCDAPC] D9_APC_0: 0x0
10072 11:41:25.112602 INFO: [NOCDAPC] D9_APC_1: 0xfff
10073 11:41:25.116070 INFO: [NOCDAPC] D10_APC_0: 0x0
10074 11:41:25.119307 INFO: [NOCDAPC] D10_APC_1: 0xfff
10075 11:41:25.123025 INFO: [NOCDAPC] D11_APC_0: 0x0
10076 11:41:25.126071 INFO: [NOCDAPC] D11_APC_1: 0xfff
10077 11:41:25.126148 INFO: [NOCDAPC] D12_APC_0: 0x0
10078 11:41:25.128969 INFO: [NOCDAPC] D12_APC_1: 0xfff
10079 11:41:25.132589 INFO: [NOCDAPC] D13_APC_0: 0x0
10080 11:41:25.135666 INFO: [NOCDAPC] D13_APC_1: 0xfff
10081 11:41:25.139091 INFO: [NOCDAPC] D14_APC_0: 0x0
10082 11:41:25.142145 INFO: [NOCDAPC] D14_APC_1: 0xfff
10083 11:41:25.145882 INFO: [NOCDAPC] D15_APC_0: 0x0
10084 11:41:25.148963 INFO: [NOCDAPC] D15_APC_1: 0xfff
10085 11:41:25.152060 INFO: [NOCDAPC] APC_CON: 0x4
10086 11:41:25.155232 INFO: [APUAPC] set_apusys_apc done
10087 11:41:25.158637 INFO: [DEVAPC] devapc_init done
10088 11:41:25.161956 INFO: GICv3 without legacy support detected.
10089 11:41:25.165340 INFO: ARM GICv3 driver initialized in EL3
10090 11:41:25.171782 INFO: Maximum SPI INTID supported: 639
10091 11:41:25.175035 INFO: BL31: Initializing runtime services
10092 11:41:25.181912 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10093 11:41:25.182009 INFO: SPM: enable CPC mode
10094 11:41:25.188373 INFO: mcdi ready for mcusys-off-idle and system suspend
10095 11:41:25.191508 INFO: BL31: Preparing for EL3 exit to normal world
10096 11:41:25.194927 INFO: Entry point address = 0x80000000
10097 11:41:25.198296 INFO: SPSR = 0x8
10098 11:41:25.204314
10099 11:41:25.204414
10100 11:41:25.204502
10101 11:41:25.207308 Starting depthcharge on Spherion...
10102 11:41:25.207402
10103 11:41:25.207489 Wipe memory regions:
10104 11:41:25.207584
10105 11:41:25.208386 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10106 11:41:25.208512 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10107 11:41:25.208636 Setting prompt string to ['asurada:']
10108 11:41:25.208741 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10109 11:41:25.210580 [0x00000040000000, 0x00000054600000)
10110 11:41:25.333070
10111 11:41:25.333198 [0x00000054660000, 0x00000080000000)
10112 11:41:25.593489
10113 11:41:25.593609 [0x000000821a7280, 0x000000ffe64000)
10114 11:41:26.338819
10115 11:41:26.338985 [0x00000100000000, 0x00000240000000)
10116 11:41:28.229111
10117 11:41:28.232197 Initializing XHCI USB controller at 0x11200000.
10118 11:41:29.270102
10119 11:41:29.273169 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10120 11:41:29.273260
10121 11:41:29.273325
10122 11:41:29.273386
10123 11:41:29.273662 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 11:41:29.374003 asurada: tftpboot 192.168.201.1 10742235/tftp-deploy-b86my2hz/kernel/image.itb 10742235/tftp-deploy-b86my2hz/kernel/cmdline
10126 11:41:29.374118 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 11:41:29.374209 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10128 11:41:29.378082 tftpboot 192.168.201.1 10742235/tftp-deploy-b86my2hz/kernel/image.itp-deploy-b86my2hz/kernel/cmdline
10129 11:41:29.378168
10130 11:41:29.378234 Waiting for link
10131 11:41:29.538706
10132 11:41:29.538816 R8152: Initializing
10133 11:41:29.538885
10134 11:41:29.541960 Version 9 (ocp_data = 6010)
10135 11:41:29.542044
10136 11:41:29.544981 R8152: Done initializing
10137 11:41:29.545127
10138 11:41:29.545192 Adding net device
10139 11:41:31.418128
10140 11:41:31.418262 done.
10141 11:41:31.418330
10142 11:41:31.418393 MAC: 00:e0:4c:72:2d:d6
10143 11:41:31.418452
10144 11:41:31.421361 Sending DHCP discover... done.
10145 11:41:31.421445
10146 11:41:31.424822 Waiting for reply... done.
10147 11:41:31.424930
10148 11:41:31.427708 Sending DHCP request... done.
10149 11:41:31.427791
10150 11:41:31.431787 Waiting for reply... done.
10151 11:41:31.431871
10152 11:41:31.431937 My ip is 192.168.201.21
10153 11:41:31.431998
10154 11:41:31.435227 The DHCP server ip is 192.168.201.1
10155 11:41:31.435311
10156 11:41:31.441990 TFTP server IP predefined by user: 192.168.201.1
10157 11:41:31.442074
10158 11:41:31.448478 Bootfile predefined by user: 10742235/tftp-deploy-b86my2hz/kernel/image.itb
10159 11:41:31.448561
10160 11:41:31.451927 Sending tftp read request... done.
10161 11:41:31.452010
10162 11:41:31.452075 Waiting for the transfer...
10163 11:41:31.455149
10164 11:41:31.707216 00000000 ################################################################
10165 11:41:31.707341
10166 11:41:31.957095 00080000 ################################################################
10167 11:41:31.957216
10168 11:41:32.207195 00100000 ################################################################
10169 11:41:32.207326
10170 11:41:32.456207 00180000 ################################################################
10171 11:41:32.456338
10172 11:41:32.705067 00200000 ################################################################
10173 11:41:32.705193
10174 11:41:32.957091 00280000 ################################################################
10175 11:41:32.957225
10176 11:41:33.207950 00300000 ################################################################
10177 11:41:33.208080
10178 11:41:33.457369 00380000 ################################################################
10179 11:41:33.457494
10180 11:41:33.706529 00400000 ################################################################
10181 11:41:33.706655
10182 11:41:33.955452 00480000 ################################################################
10183 11:41:33.955575
10184 11:41:34.205457 00500000 ################################################################
10185 11:41:34.205604
10186 11:41:34.455473 00580000 ################################################################
10187 11:41:34.455618
10188 11:41:34.707054 00600000 ################################################################
10189 11:41:34.707200
10190 11:41:34.955937 00680000 ################################################################
10191 11:41:34.956084
10192 11:41:35.209401 00700000 ################################################################
10193 11:41:35.209562
10194 11:41:35.458883 00780000 ################################################################
10195 11:41:35.459030
10196 11:41:35.708710 00800000 ################################################################
10197 11:41:35.708869
10198 11:41:35.959621 00880000 ################################################################
10199 11:41:35.959750
10200 11:41:36.210819 00900000 ################################################################
10201 11:41:36.210958
10202 11:41:36.461545 00980000 ################################################################
10203 11:41:36.461676
10204 11:41:36.709981 00a00000 ################################################################
10205 11:41:36.710113
10206 11:41:36.957412 00a80000 ################################################################
10207 11:41:36.957580
10208 11:41:37.207010 00b00000 ################################################################
10209 11:41:37.207140
10210 11:41:37.457525 00b80000 ################################################################
10211 11:41:37.457658
10212 11:41:37.706575 00c00000 ################################################################
10213 11:41:37.706705
10214 11:41:37.957162 00c80000 ################################################################
10215 11:41:37.957291
10216 11:41:38.206485 00d00000 ################################################################
10217 11:41:38.206633
10218 11:41:38.456512 00d80000 ################################################################
10219 11:41:38.456643
10220 11:41:38.706384 00e00000 ################################################################
10221 11:41:38.706517
10222 11:41:38.956042 00e80000 ################################################################
10223 11:41:38.956191
10224 11:41:39.205385 00f00000 ################################################################
10225 11:41:39.205508
10226 11:41:39.455127 00f80000 ################################################################
10227 11:41:39.455256
10228 11:41:39.703834 01000000 ################################################################
10229 11:41:39.703961
10230 11:41:39.953288 01080000 ################################################################
10231 11:41:39.953427
10232 11:41:40.201511 01100000 ################################################################
10233 11:41:40.201638
10234 11:41:40.459233 01180000 ################################################################
10235 11:41:40.459368
10236 11:41:40.709630 01200000 ################################################################
10237 11:41:40.709765
10238 11:41:40.961744 01280000 ################################################################
10239 11:41:40.961879
10240 11:41:41.214071 01300000 ################################################################
10241 11:41:41.214192
10242 11:41:41.464330 01380000 ################################################################
10243 11:41:41.464460
10244 11:41:41.712543 01400000 ################################################################
10245 11:41:41.712670
10246 11:41:41.961647 01480000 ################################################################
10247 11:41:41.961789
10248 11:41:42.207313 01500000 ################################################################
10249 11:41:42.207459
10250 11:41:42.458587 01580000 ################################################################
10251 11:41:42.458722
10252 11:41:42.708962 01600000 ################################################################
10253 11:41:42.709097
10254 11:41:42.959803 01680000 ################################################################
10255 11:41:42.959942
10256 11:41:43.210232 01700000 ################################################################
10257 11:41:43.210365
10258 11:41:43.460598 01780000 ################################################################
10259 11:41:43.460731
10260 11:41:43.707940 01800000 ################################################################
10261 11:41:43.708071
10262 11:41:43.958075 01880000 ################################################################
10263 11:41:43.958209
10264 11:41:44.208972 01900000 ################################################################
10265 11:41:44.209130
10266 11:41:44.461091 01980000 ################################################################
10267 11:41:44.461274
10268 11:41:44.710296 01a00000 ################################################################
10269 11:41:44.710422
10270 11:41:44.876961 01a80000 ########################################### done.
10271 11:41:44.877077
10272 11:41:44.879903 The bootfile was 28138522 bytes long.
10273 11:41:44.879987
10274 11:41:44.883303 Sending tftp read request... done.
10275 11:41:44.883387
10276 11:41:44.883452 Waiting for the transfer...
10277 11:41:44.883511
10278 11:41:44.886266 00000000 # done.
10279 11:41:44.886351
10280 11:41:44.892768 Command line loaded dynamically from TFTP file: 10742235/tftp-deploy-b86my2hz/kernel/cmdline
10281 11:41:44.892878
10282 11:41:44.912825 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742235/extract-nfsrootfs-_bg7toz5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10283 11:41:44.912912
10284 11:41:44.916380 Loading FIT.
10285 11:41:44.916462
10286 11:41:44.919673 Image ramdisk-1 has 17646201 bytes.
10287 11:41:44.919756
10288 11:41:44.919821 Image fdt-1 has 46924 bytes.
10289 11:41:44.919881
10290 11:41:44.922876 Image kernel-1 has 10443363 bytes.
10291 11:41:44.922958
10292 11:41:44.932432 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10293 11:41:44.932515
10294 11:41:44.948825 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10295 11:41:44.948912
10296 11:41:44.955585 Choosing best match conf-1 for compat google,spherion-rev2.
10297 11:41:44.959589
10298 11:41:44.964014 Connected to device vid:did:rid of 1ae0:0028:00
10299 11:41:44.971304
10300 11:41:44.974625 tpm_get_response: command 0x17b, return code 0x0
10301 11:41:44.974708
10302 11:41:44.978249 ec_init: CrosEC protocol v3 supported (256, 248)
10303 11:41:44.981707
10304 11:41:44.985184 tpm_cleanup: add release locality here.
10305 11:41:44.985260
10306 11:41:44.985322 Shutting down all USB controllers.
10307 11:41:44.988407
10308 11:41:44.988474 Removing current net device
10309 11:41:44.988534
10310 11:41:44.994879 Exiting depthcharge with code 4 at timestamp: 49122079
10311 11:41:44.994956
10312 11:41:44.998414 LZMA decompressing kernel-1 to 0x821a6718
10313 11:41:44.998484
10314 11:41:45.001397 LZMA decompressing kernel-1 to 0x40000000
10315 11:41:46.312852
10316 11:41:46.312996 jumping to kernel
10317 11:41:46.313401 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10318 11:41:46.313501 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10319 11:41:46.313584 Setting prompt string to ['Linux version [0-9]']
10320 11:41:46.313652 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10321 11:41:46.313721 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10322 11:41:46.395601
10323 11:41:46.398892 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10324 11:41:46.402452 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10325 11:41:46.402550 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10326 11:41:46.402634 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10327 11:41:46.402708 Using line separator: #'\n'#
10328 11:41:46.402768 No login prompt set.
10329 11:41:46.402836 Parsing kernel messages
10330 11:41:46.402893 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10331 11:41:46.402996 [login-action] Waiting for messages, (timeout 00:04:04)
10332 11:41:46.421992 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10333 11:41:46.425642 [ 0.000000] random: crng init done
10334 11:41:46.428626 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10335 11:41:46.432233 [ 0.000000] efi: UEFI not found.
10336 11:41:46.441749 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10337 11:41:46.448484 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10338 11:41:46.458433 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10339 11:41:46.468295 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10340 11:41:46.474983 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10341 11:41:46.478166 [ 0.000000] printk: bootconsole [mtk8250] enabled
10342 11:41:46.486781 [ 0.000000] NUMA: No NUMA configuration found
10343 11:41:46.493692 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10344 11:41:46.500100 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10345 11:41:46.500174 [ 0.000000] Zone ranges:
10346 11:41:46.507150 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10347 11:41:46.509974 [ 0.000000] DMA32 empty
10348 11:41:46.516828 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10349 11:41:46.519859 [ 0.000000] Movable zone start for each node
10350 11:41:46.523358 [ 0.000000] Early memory node ranges
10351 11:41:46.529696 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10352 11:41:46.536084 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10353 11:41:46.542853 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10354 11:41:46.549713 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10355 11:41:46.555929 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10356 11:41:46.562828 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10357 11:41:46.618772 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10358 11:41:46.625565 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10359 11:41:46.632248 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10360 11:41:46.635943 [ 0.000000] psci: probing for conduit method from DT.
10361 11:41:46.641967 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10362 11:41:46.645551 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10363 11:41:46.652036 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10364 11:41:46.655261 [ 0.000000] psci: SMC Calling Convention v1.2
10365 11:41:46.661956 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10366 11:41:46.665162 [ 0.000000] Detected VIPT I-cache on CPU0
10367 11:41:46.671724 [ 0.000000] CPU features: detected: GIC system register CPU interface
10368 11:41:46.678239 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10369 11:41:46.684873 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10370 11:41:46.691413 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10371 11:41:46.701476 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10372 11:41:46.708262 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10373 11:41:46.711319 [ 0.000000] alternatives: applying boot alternatives
10374 11:41:46.718082 [ 0.000000] Fallback order for Node 0: 0
10375 11:41:46.724747 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10376 11:41:46.728057 [ 0.000000] Policy zone: Normal
10377 11:41:46.747814 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742235/extract-nfsrootfs-_bg7toz5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10378 11:41:46.757696 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10379 11:41:46.769525 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10380 11:41:46.779130 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10381 11:41:46.785736 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10382 11:41:46.789203 <6>[ 0.000000] software IO TLB: area num 8.
10383 11:41:46.846045 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10384 11:41:46.994646 <6>[ 0.000000] Memory: 7953928K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398840K reserved, 32768K cma-reserved)
10385 11:41:47.001285 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10386 11:41:47.008003 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10387 11:41:47.011186 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10388 11:41:47.017754 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10389 11:41:47.025252 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10390 11:41:47.027746 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10391 11:41:47.037784 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10392 11:41:47.044224 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10393 11:41:47.050849 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10394 11:41:47.057456 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10395 11:41:47.060737 <6>[ 0.000000] GICv3: 608 SPIs implemented
10396 11:41:47.064122 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10397 11:41:47.070867 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10398 11:41:47.073988 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10399 11:41:47.080589 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10400 11:41:47.093894 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10401 11:41:47.106897 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10402 11:41:47.113950 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10403 11:41:47.121610 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10404 11:41:47.134708 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10405 11:41:47.140883 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10406 11:41:47.147822 <6>[ 0.009231] Console: colour dummy device 80x25
10407 11:41:47.157862 <6>[ 0.013986] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10408 11:41:47.164538 <6>[ 0.024492] pid_max: default: 32768 minimum: 301
10409 11:41:47.167680 <6>[ 0.029366] LSM: Security Framework initializing
10410 11:41:47.174251 <6>[ 0.034334] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10411 11:41:47.184405 <6>[ 0.042147] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10412 11:41:47.194314 <6>[ 0.051637] cblist_init_generic: Setting adjustable number of callback queues.
10413 11:41:47.200783 <6>[ 0.059087] cblist_init_generic: Setting shift to 3 and lim to 1.
10414 11:41:47.204066 <6>[ 0.065426] cblist_init_generic: Setting shift to 3 and lim to 1.
10415 11:41:47.210507 <6>[ 0.071873] rcu: Hierarchical SRCU implementation.
10416 11:41:47.217376 <6>[ 0.076887] rcu: Max phase no-delay instances is 1000.
10417 11:41:47.223807 <6>[ 0.083930] EFI services will not be available.
10418 11:41:47.226895 <6>[ 0.088931] smp: Bringing up secondary CPUs ...
10419 11:41:47.234946 <6>[ 0.094013] Detected VIPT I-cache on CPU1
10420 11:41:47.241679 <6>[ 0.094086] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10421 11:41:47.248335 <6>[ 0.094115] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10422 11:41:47.251565 <6>[ 0.094452] Detected VIPT I-cache on CPU2
10423 11:41:47.258166 <6>[ 0.094506] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10424 11:41:47.268419 <6>[ 0.094523] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10425 11:41:47.271535 <6>[ 0.094782] Detected VIPT I-cache on CPU3
10426 11:41:47.278253 <6>[ 0.094832] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10427 11:41:47.285042 <6>[ 0.094847] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10428 11:41:47.287965 <6>[ 0.095152] CPU features: detected: Spectre-v4
10429 11:41:47.294541 <6>[ 0.095159] CPU features: detected: Spectre-BHB
10430 11:41:47.298007 <6>[ 0.095165] Detected PIPT I-cache on CPU4
10431 11:41:47.304320 <6>[ 0.095222] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10432 11:41:47.310937 <6>[ 0.095239] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10433 11:41:47.318100 <6>[ 0.095531] Detected PIPT I-cache on CPU5
10434 11:41:47.324286 <6>[ 0.095594] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10435 11:41:47.330997 <6>[ 0.095611] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10436 11:41:47.334292 <6>[ 0.095895] Detected PIPT I-cache on CPU6
10437 11:41:47.341072 <6>[ 0.095960] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10438 11:41:47.347551 <6>[ 0.095977] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10439 11:41:47.353958 <6>[ 0.096274] Detected PIPT I-cache on CPU7
10440 11:41:47.360533 <6>[ 0.096341] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10441 11:41:47.367314 <6>[ 0.096357] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10442 11:41:47.370538 <6>[ 0.096404] smp: Brought up 1 node, 8 CPUs
10443 11:41:47.377186 <6>[ 0.237827] SMP: Total of 8 processors activated.
10444 11:41:47.381112 <6>[ 0.242748] CPU features: detected: 32-bit EL0 Support
10445 11:41:47.390571 <6>[ 0.248144] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10446 11:41:47.397099 <6>[ 0.256944] CPU features: detected: Common not Private translations
10447 11:41:47.403683 <6>[ 0.263459] CPU features: detected: CRC32 instructions
10448 11:41:47.407188 <6>[ 0.268810] CPU features: detected: RCpc load-acquire (LDAPR)
10449 11:41:47.413497 <6>[ 0.274770] CPU features: detected: LSE atomic instructions
10450 11:41:47.419956 <6>[ 0.280551] CPU features: detected: Privileged Access Never
10451 11:41:47.426556 <6>[ 0.286366] CPU features: detected: RAS Extension Support
10452 11:41:47.433466 <6>[ 0.291975] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10453 11:41:47.436763 <6>[ 0.299241] CPU: All CPU(s) started at EL2
10454 11:41:47.443309 <6>[ 0.303584] alternatives: applying system-wide alternatives
10455 11:41:47.453081 <6>[ 0.314293] devtmpfs: initialized
10456 11:41:47.468412 <6>[ 0.323067] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10457 11:41:47.474987 <6>[ 0.333027] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10458 11:41:47.481377 <6>[ 0.341209] pinctrl core: initialized pinctrl subsystem
10459 11:41:47.484466 <6>[ 0.347873] DMI not present or invalid.
10460 11:41:47.491034 <6>[ 0.352275] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10461 11:41:47.501136 <6>[ 0.359148] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10462 11:41:47.507933 <6>[ 0.366724] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10463 11:41:47.517539 <6>[ 0.374943] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10464 11:41:47.523969 <6>[ 0.383180] audit: initializing netlink subsys (disabled)
10465 11:41:47.530845 <5>[ 0.388869] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10466 11:41:47.537021 <6>[ 0.389570] thermal_sys: Registered thermal governor 'step_wise'
10467 11:41:47.544008 <6>[ 0.396834] thermal_sys: Registered thermal governor 'power_allocator'
10468 11:41:47.547042 <6>[ 0.403086] cpuidle: using governor menu
10469 11:41:47.553668 <6>[ 0.414045] NET: Registered PF_QIPCRTR protocol family
10470 11:41:47.560307 <6>[ 0.419529] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10471 11:41:47.566902 <6>[ 0.426627] ASID allocator initialised with 32768 entries
10472 11:41:47.570312 <6>[ 0.433189] Serial: AMBA PL011 UART driver
10473 11:41:47.580450 <4>[ 0.441922] Trying to register duplicate clock ID: 134
10474 11:41:47.634599 <6>[ 0.499420] KASLR enabled
10475 11:41:47.649115 <6>[ 0.507149] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10476 11:41:47.655711 <6>[ 0.514162] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10477 11:41:47.662387 <6>[ 0.520651] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10478 11:41:47.669165 <6>[ 0.527654] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10479 11:41:47.675510 <6>[ 0.534143] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10480 11:41:47.682187 <6>[ 0.541148] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10481 11:41:47.688685 <6>[ 0.547634] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10482 11:41:47.695539 <6>[ 0.554639] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10483 11:41:47.698449 <6>[ 0.562159] ACPI: Interpreter disabled.
10484 11:41:47.707300 <6>[ 0.568545] iommu: Default domain type: Translated
10485 11:41:47.713863 <6>[ 0.573655] iommu: DMA domain TLB invalidation policy: strict mode
10486 11:41:47.717216 <5>[ 0.580309] SCSI subsystem initialized
10487 11:41:47.723809 <6>[ 0.584475] usbcore: registered new interface driver usbfs
10488 11:41:47.730284 <6>[ 0.590207] usbcore: registered new interface driver hub
10489 11:41:47.733464 <6>[ 0.595757] usbcore: registered new device driver usb
10490 11:41:47.740423 <6>[ 0.601846] pps_core: LinuxPPS API ver. 1 registered
10491 11:41:47.750552 <6>[ 0.607040] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10492 11:41:47.753760 <6>[ 0.616385] PTP clock support registered
10493 11:41:47.757112 <6>[ 0.620629] EDAC MC: Ver: 3.0.0
10494 11:41:47.764400 <6>[ 0.625781] FPGA manager framework
10495 11:41:47.771268 <6>[ 0.629461] Advanced Linux Sound Architecture Driver Initialized.
10496 11:41:47.774354 <6>[ 0.636239] vgaarb: loaded
10497 11:41:47.780725 <6>[ 0.639409] clocksource: Switched to clocksource arch_sys_counter
10498 11:41:47.784191 <5>[ 0.645849] VFS: Disk quotas dquot_6.6.0
10499 11:41:47.791120 <6>[ 0.650031] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10500 11:41:47.794357 <6>[ 0.657221] pnp: PnP ACPI: disabled
10501 11:41:47.802642 <6>[ 0.663944] NET: Registered PF_INET protocol family
10502 11:41:47.812320 <6>[ 0.669550] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10503 11:41:47.824106 <6>[ 0.681870] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10504 11:41:47.833568 <6>[ 0.690682] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10505 11:41:47.840207 <6>[ 0.698652] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10506 11:41:47.850196 <6>[ 0.707348] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10507 11:41:47.856931 <6>[ 0.717087] TCP: Hash tables configured (established 65536 bind 65536)
10508 11:41:47.863508 <6>[ 0.723945] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10509 11:41:47.873192 <6>[ 0.731142] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10510 11:41:47.879693 <6>[ 0.738839] NET: Registered PF_UNIX/PF_LOCAL protocol family
10511 11:41:47.886527 <6>[ 0.745006] RPC: Registered named UNIX socket transport module.
10512 11:41:47.889501 <6>[ 0.751158] RPC: Registered udp transport module.
10513 11:41:47.896264 <6>[ 0.756092] RPC: Registered tcp transport module.
10514 11:41:47.902658 <6>[ 0.761024] RPC: Registered tcp NFSv4.1 backchannel transport module.
10515 11:41:47.905996 <6>[ 0.767690] PCI: CLS 0 bytes, default 64
10516 11:41:47.909323 <6>[ 0.772074] Unpacking initramfs...
10517 11:41:47.919147 <6>[ 0.775884] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10518 11:41:47.926027 <6>[ 0.784521] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10519 11:41:47.932568 <6>[ 0.793354] kvm [1]: IPA Size Limit: 40 bits
10520 11:41:47.935750 <6>[ 0.797881] kvm [1]: GICv3: no GICV resource entry
10521 11:41:47.942241 <6>[ 0.802901] kvm [1]: disabling GICv2 emulation
10522 11:41:47.945832 <6>[ 0.807590] kvm [1]: GIC system register CPU interface enabled
10523 11:41:47.952439 <6>[ 0.813759] kvm [1]: vgic interrupt IRQ18
10524 11:41:47.955771 <6>[ 0.818113] kvm [1]: VHE mode initialized successfully
10525 11:41:47.963437 <5>[ 0.824488] Initialise system trusted keyrings
10526 11:41:47.969645 <6>[ 0.829276] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10527 11:41:47.977710 <6>[ 0.839228] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10528 11:41:47.984567 <5>[ 0.845611] NFS: Registering the id_resolver key type
10529 11:41:47.987734 <5>[ 0.850911] Key type id_resolver registered
10530 11:41:47.994254 <5>[ 0.855324] Key type id_legacy registered
10531 11:41:48.001122 <6>[ 0.859609] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10532 11:41:48.007283 <6>[ 0.866531] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10533 11:41:48.013994 <6>[ 0.874243] 9p: Installing v9fs 9p2000 file system support
10534 11:41:48.049890 <5>[ 0.911200] Key type asymmetric registered
10535 11:41:48.053230 <5>[ 0.915532] Asymmetric key parser 'x509' registered
10536 11:41:48.063001 <6>[ 0.920678] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10537 11:41:48.066066 <6>[ 0.928294] io scheduler mq-deadline registered
10538 11:41:48.069559 <6>[ 0.933053] io scheduler kyber registered
10539 11:41:48.088301 <6>[ 0.949809] EINJ: ACPI disabled.
10540 11:41:48.120991 <4>[ 0.975771] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 11:41:48.130718 <4>[ 0.986397] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10542 11:41:48.145815 <6>[ 1.007357] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10543 11:41:48.153845 <6>[ 1.015423] printk: console [ttyS0] disabled
10544 11:41:48.182029 <6>[ 1.040075] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10545 11:41:48.188505 <6>[ 1.049552] printk: console [ttyS0] enabled
10546 11:41:48.191856 <6>[ 1.049552] printk: console [ttyS0] enabled
10547 11:41:48.198780 <6>[ 1.058449] printk: bootconsole [mtk8250] disabled
10548 11:41:48.201964 <6>[ 1.058449] printk: bootconsole [mtk8250] disabled
10549 11:41:48.208385 <6>[ 1.069675] SuperH (H)SCI(F) driver initialized
10550 11:41:48.211816 <6>[ 1.074936] msm_serial: driver initialized
10551 11:41:48.226182 <6>[ 1.083866] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10552 11:41:48.235825 <6>[ 1.092418] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10553 11:41:48.242380 <6>[ 1.100960] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10554 11:41:48.252467 <6>[ 1.109588] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10555 11:41:48.262057 <6>[ 1.118296] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10556 11:41:48.268761 <6>[ 1.127019] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10557 11:41:48.278682 <6>[ 1.135560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10558 11:41:48.285256 <6>[ 1.144359] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10559 11:41:48.295017 <6>[ 1.152901] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10560 11:41:48.307229 <6>[ 1.168458] loop: module loaded
10561 11:41:48.313884 <6>[ 1.174270] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10562 11:41:48.336277 <4>[ 1.197831] mtk-pmic-keys: Failed to locate of_node [id: -1]
10563 11:41:48.343249 <6>[ 1.204802] megasas: 07.719.03.00-rc1
10564 11:41:48.353245 <6>[ 1.214538] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10565 11:41:48.361889 <6>[ 1.222801] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10566 11:41:48.377515 <6>[ 1.238653] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10567 11:41:48.437495 <6>[ 1.291885] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10568 11:41:48.634709 <6>[ 1.496168] Freeing initrd memory: 17228K
10569 11:41:48.644925 <6>[ 1.506392] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10570 11:41:48.656144 <6>[ 1.517439] tun: Universal TUN/TAP device driver, 1.6
10571 11:41:48.659241 <6>[ 1.523490] thunder_xcv, ver 1.0
10572 11:41:48.662778 <6>[ 1.526983] thunder_bgx, ver 1.0
10573 11:41:48.666237 <6>[ 1.530480] nicpf, ver 1.0
10574 11:41:48.676413 <6>[ 1.534474] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10575 11:41:48.679860 <6>[ 1.541949] hns3: Copyright (c) 2017 Huawei Corporation.
10576 11:41:48.686389 <6>[ 1.547534] hclge is initializing
10577 11:41:48.689641 <6>[ 1.551112] e1000: Intel(R) PRO/1000 Network Driver
10578 11:41:48.696758 <6>[ 1.556241] e1000: Copyright (c) 1999-2006 Intel Corporation.
10579 11:41:48.699752 <6>[ 1.562257] e1000e: Intel(R) PRO/1000 Network Driver
10580 11:41:48.706296 <6>[ 1.567473] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10581 11:41:48.712835 <6>[ 1.573659] igb: Intel(R) Gigabit Ethernet Network Driver
10582 11:41:48.719582 <6>[ 1.579309] igb: Copyright (c) 2007-2014 Intel Corporation.
10583 11:41:48.726118 <6>[ 1.585145] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10584 11:41:48.732696 <6>[ 1.591663] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10585 11:41:48.736068 <6>[ 1.598122] sky2: driver version 1.30
10586 11:41:48.742906 <6>[ 1.603092] VFIO - User Level meta-driver version: 0.3
10587 11:41:48.749791 <6>[ 1.611223] usbcore: registered new interface driver usb-storage
10588 11:41:48.756412 <6>[ 1.617670] usbcore: registered new device driver onboard-usb-hub
10589 11:41:48.765237 <6>[ 1.626744] mt6397-rtc mt6359-rtc: registered as rtc0
10590 11:41:48.775355 <6>[ 1.632211] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:41:44 UTC (1686829304)
10591 11:41:48.778730 <6>[ 1.641774] i2c_dev: i2c /dev entries driver
10592 11:41:48.795194 <6>[ 1.653364] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10593 11:41:48.802215 <6>[ 1.663573] sdhci: Secure Digital Host Controller Interface driver
10594 11:41:48.808684 <6>[ 1.670009] sdhci: Copyright(c) Pierre Ossman
10595 11:41:48.815447 <6>[ 1.675401] Synopsys Designware Multimedia Card Interface Driver
10596 11:41:48.818756 <6>[ 1.681995] mmc0: CQHCI version 5.10
10597 11:41:48.825222 <6>[ 1.682542] sdhci-pltfm: SDHCI platform and OF driver helper
10598 11:41:48.832554 <6>[ 1.693853] ledtrig-cpu: registered to indicate activity on CPUs
10599 11:41:48.843238 <6>[ 1.701175] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10600 11:41:48.846532 <6>[ 1.708562] usbcore: registered new interface driver usbhid
10601 11:41:48.853003 <6>[ 1.714394] usbhid: USB HID core driver
10602 11:41:48.859919 <6>[ 1.718635] spi_master spi0: will run message pump with realtime priority
10603 11:41:48.906347 <6>[ 1.761176] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10604 11:41:48.925616 <6>[ 1.776581] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10605 11:41:48.929083 <6>[ 1.790158] mmc0: Command Queue Engine enabled
10606 11:41:48.936136 <6>[ 1.791519] cros-ec-spi spi0.0: Chrome EC device registered
10607 11:41:48.942291 <6>[ 1.794898] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10608 11:41:48.945527 <6>[ 1.808031] mmcblk0: mmc0:0001 DA4128 116 GiB
10609 11:41:48.961094 <6>[ 1.819241] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10610 11:41:48.967616 <6>[ 1.819590] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10611 11:41:48.974224 <6>[ 1.830743] NET: Registered PF_PACKET protocol family
10612 11:41:48.977698 <6>[ 1.835542] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10613 11:41:48.984307 <6>[ 1.839903] 9pnet: Installing 9P2000 support
10614 11:41:48.987750 <6>[ 1.845655] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10615 11:41:48.994208 <5>[ 1.849575] Key type dns_resolver registered
10616 11:41:49.000705 <6>[ 1.855366] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10617 11:41:49.004249 <6>[ 1.859795] registered taskstats version 1
10618 11:41:49.007225 <5>[ 1.870163] Loading compiled-in X.509 certificates
10619 11:41:49.041159 <4>[ 1.896199] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 11:41:49.051199 <4>[ 1.906902] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10621 11:41:49.061718 <3>[ 1.919866] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10622 11:41:49.073865 <6>[ 1.935339] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10623 11:41:49.080777 <6>[ 1.942096] xhci-mtk 11200000.usb: xHCI Host Controller
10624 11:41:49.087234 <6>[ 1.947601] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10625 11:41:49.097254 <6>[ 1.955482] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10626 11:41:49.103847 <6>[ 1.964906] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10627 11:41:49.110693 <6>[ 1.971107] xhci-mtk 11200000.usb: xHCI Host Controller
10628 11:41:49.117220 <6>[ 1.976619] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10629 11:41:49.123998 <6>[ 1.984277] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10630 11:41:49.130569 <6>[ 1.992192] hub 1-0:1.0: USB hub found
10631 11:41:49.134109 <6>[ 1.996234] hub 1-0:1.0: 1 port detected
10632 11:41:49.143822 <6>[ 2.000581] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10633 11:41:49.147384 <6>[ 2.009421] hub 2-0:1.0: USB hub found
10634 11:41:49.150391 <6>[ 2.013469] hub 2-0:1.0: 1 port detected
10635 11:41:49.158876 <6>[ 2.020594] mtk-msdc 11f70000.mmc: Got CD GPIO
10636 11:41:49.176639 <6>[ 2.034869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10637 11:41:49.183791 <6>[ 2.042933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10638 11:41:49.193541 <4>[ 2.051053] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10639 11:41:49.203434 <6>[ 2.060717] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10640 11:41:49.209635 <6>[ 2.068851] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10641 11:41:49.219963 <6>[ 2.076888] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10642 11:41:49.226428 <6>[ 2.084851] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10643 11:41:49.233086 <6>[ 2.092675] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10644 11:41:49.243112 <6>[ 2.100524] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10645 11:41:49.252786 <6>[ 2.111139] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10646 11:41:49.262942 <6>[ 2.119568] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10647 11:41:49.269561 <6>[ 2.127920] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10648 11:41:49.279189 <6>[ 2.136289] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10649 11:41:49.285946 <6>[ 2.144634] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10650 11:41:49.296014 <6>[ 2.153002] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10651 11:41:49.302746 <6>[ 2.161349] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10652 11:41:49.312576 <6>[ 2.169717] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10653 11:41:49.319494 <6>[ 2.178062] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10654 11:41:49.329193 <6>[ 2.186425] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10655 11:41:49.335777 <6>[ 2.194769] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10656 11:41:49.345839 <6>[ 2.203113] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10657 11:41:49.352288 <6>[ 2.211458] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10658 11:41:49.362222 <6>[ 2.219801] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10659 11:41:49.368790 <6>[ 2.228145] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10660 11:41:49.375572 <6>[ 2.237083] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10661 11:41:49.382993 <6>[ 2.244580] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10662 11:41:49.390177 <6>[ 2.251669] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10663 11:41:49.400536 <6>[ 2.258796] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10664 11:41:49.407126 <6>[ 2.266090] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10665 11:41:49.417086 <6>[ 2.273001] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10666 11:41:49.423592 <6>[ 2.282142] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10667 11:41:49.433769 <6>[ 2.291275] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10668 11:41:49.443601 <6>[ 2.300608] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10669 11:41:49.453299 <6>[ 2.310094] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10670 11:41:49.463299 <6>[ 2.319568] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10671 11:41:49.470217 <6>[ 2.328694] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10672 11:41:49.480155 <6>[ 2.338167] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10673 11:41:49.489938 <6>[ 2.347295] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10674 11:41:49.499716 <6>[ 2.356597] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10675 11:41:49.509597 <6>[ 2.366763] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10676 11:41:49.520343 <6>[ 2.378700] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10677 11:41:49.527214 <6>[ 2.388544] Trying to probe devices needed for running init ...
10678 11:41:49.541493 <6>[ 2.399707] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10679 11:41:49.568480 <6>[ 2.430151] hub 2-1:1.0: USB hub found
10680 11:41:49.571708 <6>[ 2.434556] hub 2-1:1.0: 3 ports detected
10681 11:41:49.693496 <6>[ 2.551680] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10682 11:41:49.847744 <6>[ 2.709432] hub 1-1:1.0: USB hub found
10683 11:41:49.851233 <6>[ 2.713847] hub 1-1:1.0: 4 ports detected
10684 11:41:49.929671 <6>[ 2.787951] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10685 11:41:50.173313 <6>[ 3.031686] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10686 11:41:50.305701 <6>[ 3.167251] hub 1-1.4:1.0: USB hub found
10687 11:41:50.309295 <6>[ 3.171886] hub 1-1.4:1.0: 2 ports detected
10688 11:41:50.605279 <6>[ 3.463682] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10689 11:41:50.797376 <6>[ 3.655682] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10690 11:42:01.802154 <6>[ 14.668298] ALSA device list:
10691 11:42:01.808532 <6>[ 14.671555] No soundcards found.
10692 11:42:01.820957 <6>[ 14.683933] Freeing unused kernel memory: 8384K
10693 11:42:01.824335 <6>[ 14.688853] Run /init as init process
10694 11:42:01.834895 Loading, please wait...
10695 11:42:01.853988 Starting version 247.3-7+deb11u2
10696 11:42:02.207917 <6>[ 15.067362] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10697 11:42:02.224815 <6>[ 15.087755] remoteproc remoteproc0: scp is available
10698 11:42:02.234697 <3>[ 15.092856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 11:42:02.241197 <4>[ 15.093123] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10700 11:42:02.251245 <3>[ 15.101372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 11:42:02.257807 <6>[ 15.101582] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10702 11:42:02.267998 <6>[ 15.104606] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10703 11:42:02.274353 <6>[ 15.104620] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10704 11:42:02.281172 <6>[ 15.110972] remoteproc remoteproc0: powering up scp
10705 11:42:02.287591 <6>[ 15.117174] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10706 11:42:02.297600 <3>[ 15.119010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 11:42:02.307906 <4>[ 15.126607] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10708 11:42:02.314515 <3>[ 15.136102] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 11:42:02.321326 <6>[ 15.136537] mc: Linux media interface: v0.10
10710 11:42:02.324277 <3>[ 15.143959] remoteproc remoteproc0: request_firmware failed: -2
10711 11:42:02.334502 <4>[ 15.145864] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10712 11:42:02.340983 <4>[ 15.145864] Fallback method does not support PEC.
10713 11:42:02.347506 <4>[ 15.147455] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10714 11:42:02.354082 <3>[ 15.149111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 11:42:02.364235 <3>[ 15.149121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 11:42:02.370870 <3>[ 15.149134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 11:42:02.380761 <3>[ 15.149142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 11:42:02.387867 <4>[ 15.149594] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10719 11:42:02.394409 <3>[ 15.155724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 11:42:02.401327 <3>[ 15.167751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 11:42:02.407549 <6>[ 15.174829] usbcore: registered new interface driver r8152
10722 11:42:02.414464 <6>[ 15.177711] videodev: Linux video capture interface: v2.00
10723 11:42:02.420934 <3>[ 15.182961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 11:42:02.430813 <3>[ 15.182980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 11:42:02.437836 <6>[ 15.228853] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10726 11:42:02.444255 <3>[ 15.231150] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 11:42:02.454319 <3>[ 15.234862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10728 11:42:02.460809 <6>[ 15.239131] pci_bus 0000:00: root bus resource [bus 00-ff]
10729 11:42:02.467377 <3>[ 15.247216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 11:42:02.473858 <6>[ 15.254511] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10731 11:42:02.483788 <3>[ 15.258419] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10732 11:42:02.490551 <3>[ 15.262594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 11:42:02.500228 <6>[ 15.270669] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10734 11:42:02.510101 <6>[ 15.271818] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10735 11:42:02.519947 <6>[ 15.272393] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10736 11:42:02.526725 <6>[ 15.272770] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10737 11:42:02.536683 <3>[ 15.276409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 11:42:02.543097 <6>[ 15.282284] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10739 11:42:02.549871 <3>[ 15.290226] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 11:42:02.559746 <3>[ 15.290277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 11:42:02.566402 <3>[ 15.290522] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10742 11:42:02.573010 <4>[ 15.293185] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10743 11:42:02.582924 <4>[ 15.293195] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10744 11:42:02.589752 <6>[ 15.298357] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10745 11:42:02.592853 <6>[ 15.351622] r8152 2-1.3:1.0 eth0: v1.12.13
10746 11:42:02.599526 <6>[ 15.351860] pci 0000:00:00.0: supports D1 D2
10747 11:42:02.606078 <3>[ 15.395738] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10748 11:42:02.612553 <6>[ 15.395990] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10749 11:42:02.622927 <6>[ 15.481477] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10750 11:42:02.628938 <6>[ 15.489908] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10751 11:42:02.635537 <6>[ 15.496213] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10752 11:42:02.642314 <6>[ 15.503704] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10753 11:42:02.652334 <6>[ 15.511193] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10754 11:42:02.655294 <3>[ 15.511731] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10755 11:42:02.662090 <6>[ 15.518775] pci 0000:01:00.0: supports D1 D2
10756 11:42:02.669006 <3>[ 15.525476] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10757 11:42:02.675250 <6>[ 15.529623] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10758 11:42:02.682049 <6>[ 15.539726] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10759 11:42:02.692093 <6>[ 15.543435] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10760 11:42:02.699254 <6>[ 15.550177] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10761 11:42:02.708506 <6>[ 15.567557] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10762 11:42:02.715052 <6>[ 15.575583] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10763 11:42:02.721930 <6>[ 15.576093] usbcore: registered new interface driver cdc_ether
10764 11:42:02.731651 <6>[ 15.583630] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10765 11:42:02.738279 <6>[ 15.583658] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10766 11:42:02.744927 <6>[ 15.583690] pci 0000:00:00.0: PCI bridge to [bus 01]
10767 11:42:02.751879 <6>[ 15.583719] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10768 11:42:02.757989 <6>[ 15.584733] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10769 11:42:02.764847 <6>[ 15.598605] usbcore: registered new interface driver r8153_ecm
10770 11:42:02.768110 <6>[ 15.598627] Bluetooth: Core ver 2.22
10771 11:42:02.774896 <6>[ 15.598699] NET: Registered PF_BLUETOOTH protocol family
10772 11:42:02.781528 <6>[ 15.598702] Bluetooth: HCI device and connection manager initialized
10773 11:42:02.784516 <6>[ 15.598715] Bluetooth: HCI socket layer initialized
10774 11:42:02.791269 <6>[ 15.598721] Bluetooth: L2CAP socket layer initialized
10775 11:42:02.794643 <6>[ 15.598732] Bluetooth: SCO socket layer initialized
10776 11:42:02.801099 <6>[ 15.607070] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10777 11:42:02.807589 <6>[ 15.612406] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10778 11:42:02.814325 <6>[ 15.619640] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10779 11:42:02.821076 <6>[ 15.621436] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10780 11:42:02.827797 <6>[ 15.626929] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10781 11:42:02.840754 <6>[ 15.627342] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10782 11:42:02.844003 <6>[ 15.627538] usbcore: registered new interface driver uvcvideo
10783 11:42:02.850707 <6>[ 15.641876] usbcore: registered new interface driver btusb
10784 11:42:02.860628 <4>[ 15.642427] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10785 11:42:02.867385 <3>[ 15.642437] Bluetooth: hci0: Failed to load firmware file (-2)
10786 11:42:02.873730 <3>[ 15.642440] Bluetooth: hci0: Failed to set up firmware (-2)
10787 11:42:02.883682 <4>[ 15.642444] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10788 11:42:02.897819 <5>[ 15.757256] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10789 11:42:02.916339 <5>[ 15.775773] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10790 11:42:02.922923 <4>[ 15.782660] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10791 11:42:02.929604 <6>[ 15.791559] cfg80211: failed to load regulatory.db
10792 11:42:02.974915 <6>[ 15.834144] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10793 11:42:02.981411 <6>[ 15.841656] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10794 11:42:03.005392 <6>[ 15.868371] mt7921e 0000:01:00.0: ASIC revision: 79610010
10795 11:42:03.111150 <4>[ 15.967155] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 11:42:03.114348 Begin: Loading essential drivers ... done.
10797 11:42:03.120872 Begin: Running /scripts/init-premount ... done.
10798 11:42:03.127538 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10799 11:42:03.134020 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10800 11:42:03.140906 Device /sys/class/net/enx00e04c722dd6 found
10801 11:42:03.141374 done.
10802 11:42:03.200262 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10803 11:42:03.229905 <4>[ 16.085926] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 11:42:03.349337 <4>[ 16.205403] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 11:42:03.465126 <4>[ 16.321233] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 11:42:03.581231 <4>[ 16.437158] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 11:42:03.696768 <4>[ 16.552991] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 11:42:03.812938 <4>[ 16.669268] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 11:42:03.928573 <4>[ 16.785211] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 11:42:04.044255 <4>[ 16.901110] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 11:42:04.125011 <6>[ 16.988043] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10812 11:42:04.160505 <4>[ 17.017060] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 11:42:04.267871 <3>[ 17.130920] mt7921e 0000:01:00.0: hardware init failed
10814 11:42:04.271160 IP-Config: no response after 2 secs - giving up
10815 11:42:04.323581 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10816 11:42:05.428084 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10817 11:42:05.434640 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10818 11:42:05.441485 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10819 11:42:05.448151 host : mt8192-asurada-spherion-r0-cbg-1
10820 11:42:05.454142 domain : lava-rack
10821 11:42:05.460791 rootserver: 192.168.201.1 rootpath:
10822 11:42:05.460880 filename :
10823 11:42:05.489899 done.
10824 11:42:05.496924 Begin: Running /scripts/nfs-bottom ... done.
10825 11:42:05.515409 Begin: Running /scripts/init-bottom ... done.
10826 11:42:06.586332 <6>[ 19.449764] NET: Registered PF_INET6 protocol family
10827 11:42:06.593417 <6>[ 19.456756] Segment Routing with IPv6
10828 11:42:06.596600 <6>[ 19.460749] In-situ OAM (IOAM) with IPv6
10829 11:42:06.697283 <30>[ 19.540473] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10830 11:42:06.700001 <30>[ 19.564255] systemd[1]: Detected architecture arm64.
10831 11:42:06.718480
10832 11:42:06.721646 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10833 11:42:06.721729
10834 11:42:06.737653 <30>[ 19.601481] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10835 11:42:07.192336 <30>[ 20.052736] systemd[1]: Queued start job for default target Graphical Interface.
10836 11:42:07.221036 <30>[ 20.084715] systemd[1]: Created slice system-getty.slice.
10837 11:42:07.227565 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10838 11:42:07.244840 <30>[ 20.108355] systemd[1]: Created slice system-modprobe.slice.
10839 11:42:07.251147 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10840 11:42:07.269298 <30>[ 20.132864] systemd[1]: Created slice system-serial\x2dgetty.slice.
10841 11:42:07.279260 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10842 11:42:07.292515 <30>[ 20.156176] systemd[1]: Created slice User and Session Slice.
10843 11:42:07.299133 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10844 11:42:07.319832 <30>[ 20.180260] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10845 11:42:07.329793 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10846 11:42:07.347551 <30>[ 20.207859] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10847 11:42:07.354122 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10848 11:42:07.374644 <30>[ 20.231811] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10849 11:42:07.381172 <30>[ 20.243858] systemd[1]: Reached target Local Encrypted Volumes.
10850 11:42:07.387956 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10851 11:42:07.404575 <30>[ 20.268161] systemd[1]: Reached target Paths.
10852 11:42:07.407960 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10853 11:42:07.424293 <30>[ 20.287729] systemd[1]: Reached target Remote File Systems.
10854 11:42:07.430546 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10855 11:42:07.448413 <30>[ 20.311960] systemd[1]: Reached target Slices.
10856 11:42:07.454743 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10857 11:42:07.468310 <30>[ 20.331883] systemd[1]: Reached target Swap.
10858 11:42:07.471320 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10859 11:42:07.491667 <30>[ 20.352045] systemd[1]: Listening on initctl Compatibility Named Pipe.
10860 11:42:07.498421 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10861 11:42:07.504809 <30>[ 20.367390] systemd[1]: Listening on Journal Audit Socket.
10862 11:42:07.511644 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10863 11:42:07.525595 <30>[ 20.388660] systemd[1]: Listening on Journal Socket (/dev/log).
10864 11:42:07.531731 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10865 11:42:07.548765 <30>[ 20.412490] systemd[1]: Listening on Journal Socket.
10866 11:42:07.555505 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10867 11:42:07.572929 <30>[ 20.432960] systemd[1]: Listening on Network Service Netlink Socket.
10868 11:42:07.579127 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10869 11:42:07.594811 <30>[ 20.458234] systemd[1]: Listening on udev Control Socket.
10870 11:42:07.601001 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10871 11:42:07.616578 <30>[ 20.479996] systemd[1]: Listening on udev Kernel Socket.
10872 11:42:07.623275 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10873 11:42:07.672622 <30>[ 20.536120] systemd[1]: Mounting Huge Pages File System...
10874 11:42:07.679282 Mounting [0;1;39mHuge Pages File System[0m...
10875 11:42:07.694711 <30>[ 20.558196] systemd[1]: Mounting POSIX Message Queue File System...
10876 11:42:07.701342 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10877 11:42:07.718698 <30>[ 20.582075] systemd[1]: Mounting Kernel Debug File System...
10878 11:42:07.725580 Mounting [0;1;39mKernel Debug File System[0m...
10879 11:42:07.743730 <30>[ 20.603920] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10880 11:42:07.784053 <30>[ 20.644219] systemd[1]: Starting Create list of static device nodes for the current kernel...
10881 11:42:07.790754 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10882 11:42:07.810959 <30>[ 20.674332] systemd[1]: Starting Load Kernel Module configfs...
10883 11:42:07.817541 Starting [0;1;39mLoad Kernel Module configfs[0m...
10884 11:42:07.834864 <30>[ 20.698271] systemd[1]: Starting Load Kernel Module drm...
10885 11:42:07.841404 Starting [0;1;39mLoad Kernel Module drm[0m...
10886 11:42:07.858960 <30>[ 20.722352] systemd[1]: Starting Load Kernel Module fuse...
10887 11:42:07.865712 Starting [0;1;39mLoad Kernel Module fuse[0m...
10888 11:42:07.894811 <6>[ 20.757999] fuse: init (API version 7.37)
10889 11:42:07.904687 <30>[ 20.759258] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10890 11:42:07.932857 <30>[ 20.796371] systemd[1]: Starting Journal Service...
10891 11:42:07.936382 Starting [0;1;39mJournal Service[0m...
10892 11:42:07.959927 <30>[ 20.823306] systemd[1]: Starting Load Kernel Modules...
10893 11:42:07.966459 Starting [0;1;39mLoad Kernel Modules[0m...
10894 11:42:07.986834 <30>[ 20.846817] systemd[1]: Starting Remount Root and Kernel File Systems...
10895 11:42:07.992839 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10896 11:42:08.011532 <30>[ 20.874886] systemd[1]: Starting Coldplug All udev Devices...
10897 11:42:08.018375 Starting [0;1;39mColdplug All udev Devices[0m...
10898 11:42:08.036241 <30>[ 20.899511] systemd[1]: Mounted Huge Pages File System.
10899 11:42:08.042692 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10900 11:42:08.056345 <30>[ 20.920027] systemd[1]: Mounted POSIX Message Queue File System.
10901 11:42:08.063094 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10902 11:42:08.080915 <30>[ 20.944037] systemd[1]: Mounted Kernel Debug File System.
10903 11:42:08.094231 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0<3>[ 20.954245] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 11:42:08.097458 m.
10905 11:42:08.117470 <30>[ 20.976755] systemd[1]: Finished Create list of static device nodes for the current kernel.
10906 11:42:08.130492 [[0;32m OK [0m] Finished [0<3>[ 20.987786] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 11:42:08.133547 ;1;39mCreate list of st… nodes for the current kernel[0m.
10908 11:42:08.153558 <30>[ 21.017025] systemd[1]: modprobe@configfs.service: Succeeded.
10909 11:42:08.160789 <30>[ 21.024153] systemd[1]: Finished Load Kernel Module configfs.
10910 11:42:08.167718 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10911 11:42:08.177419 <3>[ 21.037059] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 11:42:08.189447 <30>[ 21.053066] systemd[1]: modprobe@drm.service: Succeeded.
10913 11:42:08.196386 <30>[ 21.059542] systemd[1]: Finished Load Kernel Module drm.
10914 11:42:08.202980 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10915 11:42:08.217781 <3>[ 21.077718] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 11:42:08.225289 <30>[ 21.088630] systemd[1]: modprobe@fuse.service: Succeeded.
10917 11:42:08.231637 <30>[ 21.095134] systemd[1]: Finished Load Kernel Module fuse.
10918 11:42:08.238611 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10919 11:42:08.253541 <30>[ 21.116498] systemd[1]: Finished Load Kernel Modules.
10920 11:42:08.263450 <3>[ 21.118597] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 11:42:08.266533 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10922 11:42:08.281832 <30>[ 21.144716] systemd[1]: Finished Remount Root and Kernel File Systems.
10923 11:42:08.291620 <3>[ 21.151196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 11:42:08.298346 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10925 11:42:08.322237 <3>[ 21.182437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 11:42:08.352547 <3>[ 21.212587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 11:42:08.359181 <30>[ 21.219213] systemd[1]: Mounting FUSE Control File System...
10928 11:42:08.365391 Mounting [0;1;39mFUSE Control File System[0m...
10929 11:42:08.386534 <3>[ 21.246890] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 11:42:08.398264 <30>[ 21.258688] systemd[1]: Mounting Kernel Configuration File System...
10931 11:42:08.401721 Mounting [0;1;39mKernel Configuration File System[0m...
10932 11:42:08.416008 <3>[ 21.276287] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 11:42:08.427934 <30>[ 21.288146] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10934 11:42:08.437615 <30>[ 21.298139] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10935 11:42:08.448562 <30>[ 21.311759] systemd[1]: Starting Load/Save Random Seed...
10936 11:42:08.454762 Starting [0;1;39mLoad/Save Random Seed[0m...
10937 11:42:08.508530 <30>[ 21.372100] systemd[1]: Starting Apply Kernel Variables...
10938 11:42:08.515077 Starting [0;1;39mApply Kernel Variables[0m...
10939 11:42:08.537074 <30>[ 21.400565] systemd[1]: Starting Create System Users...
10940 11:42:08.543480 Starting [0;1;39mCreate System Users[0m...
10941 11:42:08.565067 <4>[ 21.418678] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10942 11:42:08.575117 <3>[ 21.434354] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10943 11:42:08.578304 <30>[ 21.435894] systemd[1]: Started Journal Service.
10944 11:42:08.584704 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10945 11:42:08.603125 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10946 11:42:08.620087 See 'systemctl status systemd-udev-trigger.service' for details.
10947 11:42:08.636737 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10948 11:42:08.655581 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10949 11:42:08.672798 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10950 11:42:08.693141 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10951 11:42:08.709035 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10952 11:42:08.745081 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10953 11:42:08.762254 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10954 11:42:08.787024 <46>[ 21.647537] systemd-journald[292]: Received client request to flush runtime journal.
10955 11:42:08.822313 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10956 11:42:08.836175 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10957 11:42:08.852057 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10958 11:42:08.924155 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10959 11:42:10.165466 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10960 11:42:10.200714 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10961 11:42:10.220464 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10962 11:42:10.247802 Starting [0;1;39mNetwork Service[0m...
10963 11:42:10.428279 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10964 11:42:10.540342 Starting [0;1;39mNetwork Time Synchronization[0m...
10965 11:42:10.560317 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10966 11:42:10.629901 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10967 11:42:10.648511 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10968 11:42:10.696328 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10969 11:42:10.849751 <6>[ 23.713914] remoteproc remoteproc0: powering up scp
10970 11:42:10.878869 <4>[ 23.739451] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10971 11:42:10.885382 <3>[ 23.749377] remoteproc remoteproc0: request_firmware failed: -2
10972 11:42:10.895162 <3>[ 23.755563] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10973 11:42:10.972217 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10974 11:42:10.992010 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10975 11:42:11.023609 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10976 11:42:11.073768 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10977 11:42:11.091383 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10978 11:42:11.144641 Starting [0;1;39mNetwork Name Resolution[0m...
10979 11:42:11.160471 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10980 11:42:11.178835 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10981 11:42:11.199408 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10982 11:42:11.205768 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10983 11:42:11.222736 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10984 11:42:11.893477 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10985 11:42:11.917544 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10986 11:42:12.241743 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10987 11:42:12.266310 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10988 11:42:12.279888 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10989 11:42:12.312144 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10990 11:42:12.323728 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10991 11:42:12.339436 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10992 11:42:12.392633 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10993 11:42:12.531993 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10994 11:42:12.668267 Starting [0;1;39mUser Login Management[0m...
10995 11:42:12.686452 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10996 11:42:12.925355 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10997 11:42:12.940238 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10998 11:42:12.959447 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10999 11:42:13.007804 Starting [0;1;39mPermit User Sessions[0m...
11000 11:42:13.024026 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11001 11:42:13.044592 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11002 11:42:13.061124 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11003 11:42:13.096462 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11004 11:42:13.114481 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11005 11:42:13.131702 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11006 11:42:13.147870 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11007 11:42:13.164601 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11008 11:42:13.179501 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11009 11:42:13.220781 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11010 11:42:13.292129 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11011 11:42:13.340365
11012 11:42:13.340466
11013 11:42:13.343848 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11014 11:42:13.343923
11015 11:42:13.346937 debian-bullseye-arm64 login: root (automatic login)
11016 11:42:13.347019
11017 11:42:13.347085
11018 11:42:13.608867 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
11019 11:42:13.609037
11020 11:42:13.615487 The programs included with the Debian GNU/Linux system are free software;
11021 11:42:13.622249 the exact distribution terms for each program are described in the
11022 11:42:13.625677 individual files in /usr/share/doc/*/copyright.
11023 11:42:13.625761
11024 11:42:13.632281 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11025 11:42:13.635182 permitted by applicable law.
11026 11:42:14.317700 Matched prompt #10: / #
11028 11:42:14.317986 Setting prompt string to ['/ #']
11029 11:42:14.318082 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11031 11:42:14.318280 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11032 11:42:14.318370 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11033 11:42:14.318442 Setting prompt string to ['/ #']
11034 11:42:14.318504 Forcing a shell prompt, looking for ['/ #']
11036 11:42:14.368724 / #
11037 11:42:14.368824 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11038 11:42:14.368913 Waiting using forced prompt support (timeout 00:02:30)
11039 11:42:14.373822
11040 11:42:14.374089 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11041 11:42:14.374182 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11043 11:42:14.474497 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742235/extract-nfsrootfs-_bg7toz5'
11044 11:42:14.479410 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742235/extract-nfsrootfs-_bg7toz5'
11046 11:42:14.579926 / # export NFS_SERVER_IP='192.168.201.1'
11047 11:42:14.585097 export NFS_SERVER_IP='192.168.201.1'
11048 11:42:14.585374 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11049 11:42:14.585479 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11050 11:42:14.585576 end: 2 depthcharge-action (duration 00:01:24) [common]
11051 11:42:14.585670 start: 3 lava-test-retry (timeout 00:07:46) [common]
11052 11:42:14.585759 start: 3.1 lava-test-shell (timeout 00:07:46) [common]
11053 11:42:14.585836 Using namespace: common
11055 11:42:14.686172 / # #
11056 11:42:14.686292 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11057 11:42:14.691093 #
11058 11:42:14.691357 Using /lava-10742235
11060 11:42:14.791684 / # export SHELL=/bin/bash
11061 11:42:14.796761 export SHELL=/bin/bash
11063 11:42:14.897282 / # . /lava-10742235/environment
11064 11:42:14.902795 . /lava-10742235/environment
11066 11:42:15.006233 / # /lava-10742235/bin/lava-test-runner /lava-10742235/0
11067 11:42:15.006338 Test shell timeout: 10s (minimum of the action and connection timeout)
11068 11:42:15.011273 /lava-10742235/bin/lava-test-runner /lava-10742235/0
11069 11:42:15.202432 + export TESTRUN_ID=0_timesync-off
11070 11:42:15.205942 + TESTRUN_ID=0_timesync-off
11071 11:42:15.208916 + cd /lava-10742235/0/tests/0_timesync-off
11072 11:42:15.212090 ++ cat uuid
11073 11:42:15.212175 + UUID=10742235_1.6.2.3.1
11074 11:42:15.215860 + set +x
11075 11:42:15.219091 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10742235_1.6.2.3.1>
11076 11:42:15.219355 Received signal: <STARTRUN> 0_timesync-off 10742235_1.6.2.3.1
11077 11:42:15.219434 Starting test lava.0_timesync-off (10742235_1.6.2.3.1)
11078 11:42:15.219522 Skipping test definition patterns.
11079 11:42:15.222229 + systemctl stop systemd-timesyncd
11080 11:42:15.247520 + set +x
11081 11:42:15.250793 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10742235_1.6.2.3.1>
11082 11:42:15.251106 Received signal: <ENDRUN> 0_timesync-off 10742235_1.6.2.3.1
11083 11:42:15.251194 Ending use of test pattern.
11084 11:42:15.251258 Ending test lava.0_timesync-off (10742235_1.6.2.3.1), duration 0.03
11086 11:42:15.292263 + export TESTRUN_ID=1_kselftest-arm64
11087 11:42:15.292350 + TESTRUN_ID=1_kselftest-arm64
11088 11:42:15.298596 + cd /lava-10742235/0/tests/1_kselftest-arm64
11089 11:42:15.298682 ++ cat uuid
11090 11:42:15.302003 + UUID=10742235_1.6.2.3.5
11091 11:42:15.302087 + set +x
11092 11:42:15.305375 Received signal: <STARTRUN> 1_kselftest-arm64 10742235_1.6.2.3.5
11093 11:42:15.305457 Starting test lava.1_kselftest-arm64 (10742235_1.6.2.3.5)
11094 11:42:15.305551 Skipping test definition patterns.
11095 11:42:15.308551 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10742235_1.6.2.3.5>
11096 11:42:15.308650 + cd ./automated/linux/kselftest/
11097 11:42:15.334728 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11098 11:42:15.345795 INFO: install_deps skipped
11099 11:42:15.443582 --2023-06-15 11:42:10-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11100 11:42:15.451911 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11101 11:42:15.584487 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11102 11:42:15.717615 HTTP request sent, awaiting response... 200 OK
11103 11:42:15.720558 Length: 2884276 (2.8M) [application/octet-stream]
11104 11:42:15.723760 Saving to: 'kselftest.tar.xz'
11105 11:42:15.723843
11106 11:42:15.723909
11107 11:42:15.982642 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11108 11:42:16.247884 kselftest.tar.xz 1%[ ] 46.39K 176KB/s
11109 11:42:16.562073 kselftest.tar.xz 7%[> ] 214.67K 405KB/s
11110 11:42:16.843670 kselftest.tar.xz 29%[====> ] 822.71K 975KB/s
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11115 11:42:17.215548
11116 11:42:21.719204 skiplist:
11117 11:42:21.722526 ========================================
11118 11:42:21.725692 ========================================
11119 11:42:21.762010 arm64:tags_test
11120 11:42:21.765079 arm64:run_tags_test.sh
11121 11:42:21.765160 arm64:fake_sigreturn_bad_magic
11122 11:42:21.768554 arm64:fake_sigreturn_bad_size
11123 11:42:21.771553 arm64:fake_sigreturn_bad_size_for_magic0
11124 11:42:21.775550 arm64:fake_sigreturn_duplicated_fpsimd
11125 11:42:21.778135 arm64:fake_sigreturn_misaligned_sp
11126 11:42:21.781625 arm64:fake_sigreturn_missing_fpsimd
11127 11:42:21.784952 arm64:fake_sigreturn_sme_change_vl
11128 11:42:21.788098 arm64:fake_sigreturn_sve_change_vl
11129 11:42:21.791571 arm64:mangle_pstate_invalid_compat_toggle
11130 11:42:21.794880 arm64:mangle_pstate_invalid_daif_bits
11131 11:42:21.798279 arm64:mangle_pstate_invalid_mode_el1h
11132 11:42:21.801657 arm64:mangle_pstate_invalid_mode_el1t
11133 11:42:21.804986 arm64:mangle_pstate_invalid_mode_el2h
11134 11:42:21.808213 arm64:mangle_pstate_invalid_mode_el2t
11135 11:42:21.811339 arm64:mangle_pstate_invalid_mode_el3h
11136 11:42:21.814866 arm64:mangle_pstate_invalid_mode_el3t
11137 11:42:21.818199 arm64:sme_trap_no_sm
11138 11:42:21.822254 arm64:sme_trap_non_streaming
11139 11:42:21.822834 arm64:sme_trap_za
11140 11:42:21.825128 arm64:sme_vl
11141 11:42:21.825614 arm64:ssve_regs
11142 11:42:21.828475 arm64:sve_regs
11143 11:42:21.828941 arm64:sve_vl
11144 11:42:21.829358 arm64:za_no_regs
11145 11:42:21.831496 arm64:za_regs
11146 11:42:21.831955 arm64:pac
11147 11:42:21.834881 arm64:fp-stress
11148 11:42:21.835425 arm64:sve-ptrace
11149 11:42:21.838224 arm64:sve-probe-vls
11150 11:42:21.838689 arm64:vec-syscfg
11151 11:42:21.839059 arm64:za-fork
11152 11:42:21.841744 arm64:za-ptrace
11153 11:42:21.844879 arm64:check_buffer_fill
11154 11:42:21.845424 arm64:check_child_memory
11155 11:42:21.848154 arm64:check_gcr_el1_cswitch
11156 11:42:21.851534 arm64:check_ksm_options
11157 11:42:21.851997 arm64:check_mmap_options
11158 11:42:21.854841 arm64:check_prctl
11159 11:42:21.857920 arm64:check_tags_inclusion
11160 11:42:21.858383 arm64:check_user_mem
11161 11:42:21.861711 arm64:btitest
11162 11:42:21.862175 arm64:nobtitest
11163 11:42:21.862541 arm64:hwcap
11164 11:42:21.864813 arm64:ptrace
11165 11:42:21.865310 arm64:syscall-abi
11166 11:42:21.867948 arm64:tpidr2
11167 11:42:21.871564 ============== Tests to run ===============
11168 11:42:21.872033 arm64:tags_test
11169 11:42:21.874856 arm64:run_tags_test.sh
11170 11:42:21.877799 arm64:fake_sigreturn_bad_magic
11171 11:42:21.878264 arm64:fake_sigreturn_bad_size
11172 11:42:21.884434 arm64:fake_sigreturn_bad_size_for_magic0
11173 11:42:21.887667 arm64:fake_sigreturn_duplicated_fpsimd
11174 11:42:21.890907 arm64:fake_sigreturn_misaligned_sp
11175 11:42:21.894646 arm64:fake_sigreturn_missing_fpsimd
11176 11:42:21.895133 arm64:fake_sigreturn_sme_change_vl
11177 11:42:21.897697 arm64:fake_sigreturn_sve_change_vl
11178 11:42:21.904616 arm64:mangle_pstate_invalid_compat_toggle
11179 11:42:21.907522 arm64:mangle_pstate_invalid_daif_bits
11180 11:42:21.911117 arm64:mangle_pstate_invalid_mode_el1h
11181 11:42:21.914000 arm64:mangle_pstate_invalid_mode_el1t
11182 11:42:21.917574 arm64:mangle_pstate_invalid_mode_el2h
11183 11:42:21.921093 arm64:mangle_pstate_invalid_mode_el2t
11184 11:42:21.924218 arm64:mangle_pstate_invalid_mode_el3h
11185 11:42:21.927753 arm64:mangle_pstate_invalid_mode_el3t
11186 11:42:21.928354 arm64:sme_trap_no_sm
11187 11:42:21.930929 arm64:sme_trap_non_streaming
11188 11:42:21.934213 arm64:sme_trap_za
11189 11:42:21.934731 arm64:sme_vl
11190 11:42:21.935165 arm64:ssve_regs
11191 11:42:21.937198 arm64:sve_regs
11192 11:42:21.937737 arm64:sve_vl
11193 11:42:21.940720 arm64:za_no_regs
11194 11:42:21.941250 arm64:za_regs
11195 11:42:21.941681 arm64:pac
11196 11:42:21.943800 arm64:fp-stress
11197 11:42:21.944319 arm64:sve-ptrace
11198 11:42:21.947051 arm64:sve-probe-vls
11199 11:42:21.947536 arm64:vec-syscfg
11200 11:42:21.950639 arm64:za-fork
11201 11:42:21.951178 arm64:za-ptrace
11202 11:42:21.954230 arm64:check_buffer_fill
11203 11:42:21.954694 arm64:check_child_memory
11204 11:42:21.957267 arm64:check_gcr_el1_cswitch
11205 11:42:21.960630 arm64:check_ksm_options
11206 11:42:21.963963 arm64:check_mmap_options
11207 11:42:21.964562 arm64:check_prctl
11208 11:42:21.967059 arm64:check_tags_inclusion
11209 11:42:21.967522 arm64:check_user_mem
11210 11:42:21.970643 arm64:btitest
11211 11:42:21.971104 arm64:nobtitest
11212 11:42:21.973580 arm64:hwcap
11213 11:42:21.974043 arm64:ptrace
11214 11:42:21.974411 arm64:syscall-abi
11215 11:42:21.976953 arm64:tpidr2
11216 11:42:21.980087 ===========End Tests to run ===============
11217 11:42:22.223664 <12>[ 35.088482] kselftest: Running tests in arm64
11218 11:42:22.232888 TAP version 13
11219 11:42:22.245605 1..48
11220 11:42:22.262618 # selftests: arm64: tags_test
11221 11:42:22.643160 ok 1 selftests: arm64: tags_test
11222 11:42:22.658003 # selftests: arm64: run_tags_test.sh
11223 11:42:22.709171 # --------------------
11224 11:42:22.711969 # running tags test
11225 11:42:22.712436 # --------------------
11226 11:42:22.715863 # [PASS]
11227 11:42:22.718861 ok 2 selftests: arm64: run_tags_test.sh
11228 11:42:22.731459 # selftests: arm64: fake_sigreturn_bad_magic
11229 11:42:22.788325 # Registered handlers for all signals.
11230 11:42:22.789095 # Detected MINSTKSIGSZ:4720
11231 11:42:22.791007 # Testcase initialized.
11232 11:42:22.794588 # uc context validated.
11233 11:42:22.797555 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11234 11:42:22.801217 # Handled SIG_COPYCTX
11235 11:42:22.801702 # Available space:3568
11236 11:42:22.807678 # Using badly built context - ERR: BAD MAGIC !
11237 11:42:22.814530 # SIG_OK -- SP:0xFFFFCFCF7DB0 si_addr@:0xffffcfcf7db0 si_code:2 token@:0xffffcfcf6b50 offset:-4704
11238 11:42:22.817604 # ==>> completed. PASS(1)
11239 11:42:22.824387 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11240 11:42:22.830653 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCFCF6B50
11241 11:42:22.837628 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11242 11:42:22.840845 # selftests: arm64: fake_sigreturn_bad_size
11243 11:42:22.862838 # Registered handlers for all signals.
11244 11:42:22.863391 # Detected MINSTKSIGSZ:4720
11245 11:42:22.866330 # Testcase initialized.
11246 11:42:22.869305 # uc context validated.
11247 11:42:22.872887 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11248 11:42:22.875862 # Handled SIG_COPYCTX
11249 11:42:22.876322 # Available space:3568
11250 11:42:22.879686 # uc context validated.
11251 11:42:22.886162 # Using badly built context - ERR: Bad size for esr_context
11252 11:42:22.892619 # SIG_OK -- SP:0xFFFFDFD24180 si_addr@:0xffffdfd24180 si_code:2 token@:0xffffdfd22f20 offset:-4704
11253 11:42:22.896390 # ==>> completed. PASS(1)
11254 11:42:22.902407 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11255 11:42:22.909403 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDFD22F20
11256 11:42:22.912457 ok 4 selftests: arm64: fake_sigreturn_bad_size
11257 11:42:22.918998 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11258 11:42:22.935266 # Registered handlers for all signals.
11259 11:42:22.935900 # Detected MINSTKSIGSZ:4720
11260 11:42:22.938779 # Testcase initialized.
11261 11:42:22.942045 # uc context validated.
11262 11:42:22.944855 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11263 11:42:22.948499 # Handled SIG_COPYCTX
11264 11:42:22.949037 # Available space:3568
11265 11:42:22.954959 # Using badly built context - ERR: Bad size for terminator
11266 11:42:22.964813 # SIG_OK -- SP:0xFFFFF2789950 si_addr@:0xfffff2789950 si_code:2 token@:0xfffff27886f0 offset:-4704
11267 11:42:22.965400 # ==>> completed. PASS(1)
11268 11:42:22.975264 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11269 11:42:22.981069 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF27886F0
11270 11:42:22.984635 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11271 11:42:22.991262 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11272 11:42:23.004303 # Registered handlers for all signals.
11273 11:42:23.004847 # Detected MINSTKSIGSZ:4720
11274 11:42:23.007470 # Testcase initialized.
11275 11:42:23.010777 # uc context validated.
11276 11:42:23.014061 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11277 11:42:23.017457 # Handled SIG_COPYCTX
11278 11:42:23.017916 # Available space:3568
11279 11:42:23.023634 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11280 11:42:23.033561 # SIG_OK -- SP:0xFFFFDDB3FBE0 si_addr@:0xffffddb3fbe0 si_code:2 token@:0xffffddb3e980 offset:-4704
11281 11:42:23.033650 # ==>> completed. PASS(1)
11282 11:42:23.043568 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11283 11:42:23.049900 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDDB3E980
11284 11:42:23.053459 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11285 11:42:23.056182 # selftests: arm64: fake_sigreturn_misaligned_sp
11286 11:42:23.073596 # Registered handlers for all signals.
11287 11:42:23.073773 # Detected MINSTKSIGSZ:4720
11288 11:42:23.076743 # Testcase initialized.
11289 11:42:23.079703 # uc context validated.
11290 11:42:23.083010 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11291 11:42:23.086447 # Handled SIG_COPYCTX
11292 11:42:23.093026 # SIG_OK -- SP:0xFFFFDA84CA13 si_addr@:0xffffda84ca13 si_code:2 token@:0xffffda84ca13 offset:0
11293 11:42:23.096264 # ==>> completed. PASS(1)
11294 11:42:23.102763 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11295 11:42:23.109678 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDA84CA13
11296 11:42:23.116179 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11297 11:42:23.119408 # selftests: arm64: fake_sigreturn_missing_fpsimd
11298 11:42:23.138943 # Registered handlers for all signals.
11299 11:42:23.139028 # Detected MINSTKSIGSZ:4720
11300 11:42:23.142200 # Testcase initialized.
11301 11:42:23.145160 # uc context validated.
11302 11:42:23.148554 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11303 11:42:23.151875 # Handled SIG_COPYCTX
11304 11:42:23.155044 # Mangling template header. Spare space:4096
11305 11:42:23.158593 # Using badly built context - ERR: Missing FPSIMD
11306 11:42:23.168563 # SIG_OK -- SP:0xFFFFF63EAA70 si_addr@:0xfffff63eaa70 si_code:2 token@:0xfffff63e9810 offset:-4704
11307 11:42:23.171688 # ==>> completed. PASS(1)
11308 11:42:23.178282 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11309 11:42:23.185309 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF63E9810
11310 11:42:23.188472 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11311 11:42:23.195280 # selftests: arm64: fake_sigreturn_sme_change_vl
11312 11:42:23.198587 # Registered handlers for all signals.
11313 11:42:23.201690 # Detected MINSTKSIGSZ:4720
11314 11:42:23.202112 # ==>> completed. SKIP.
11315 11:42:23.208237 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11316 11:42:23.215004 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11317 11:42:23.218098 # selftests: arm64: fake_sigreturn_sve_change_vl
11318 11:42:23.266500 # Registered handlers for all signals.
11319 11:42:23.266952 # Detected MINSTKSIGSZ:4720
11320 11:42:23.269592 # ==>> completed. SKIP.
11321 11:42:23.276037 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11322 11:42:23.279399 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11323 11:42:23.285818 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11324 11:42:23.329898 # Registered handlers for all signals.
11325 11:42:23.329996 # Detected MINSTKSIGSZ:4720
11326 11:42:23.333171 # Testcase initialized.
11327 11:42:23.336351 # uc context validated.
11328 11:42:23.336434 # Handled SIG_TRIG
11329 11:42:23.346541 # SIG_OK -- SP:0xFFFFFB314030 si_addr@:0xfffffb314030 si_code:2 token@:(nil) offset:-281474896052272
11330 11:42:23.349876 # ==>> completed. PASS(1)
11331 11:42:23.356515 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11332 11:42:23.363094 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11333 11:42:23.366072 # selftests: arm64: mangle_pstate_invalid_daif_bits
11334 11:42:23.393735 # Registered handlers for all signals.
11335 11:42:23.393993 # Detected MINSTKSIGSZ:4720
11336 11:42:23.396934 # Testcase initialized.
11337 11:42:23.400327 # uc context validated.
11338 11:42:23.400633 # Handled SIG_TRIG
11339 11:42:23.410178 # SIG_OK -- SP:0xFFFFE6530220 si_addr@:0xffffe6530220 si_code:2 token@:(nil) offset:-281474545943072
11340 11:42:23.413581 # ==>> completed. PASS(1)
11341 11:42:23.419955 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11342 11:42:23.423101 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11343 11:42:23.430146 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11344 11:42:23.458271 # Registered handlers for all signals.
11345 11:42:23.458359 # Detected MINSTKSIGSZ:4720
11346 11:42:23.461222 # Testcase initialized.
11347 11:42:23.464721 # uc context validated.
11348 11:42:23.464847 # Handled SIG_TRIG
11349 11:42:23.474607 # SIG_OK -- SP:0xFFFFFC184420 si_addr@:0xfffffc184420 si_code:2 token@:(nil) offset:-281474911192096
11350 11:42:23.477897 # ==>> completed. PASS(1)
11351 11:42:23.484477 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11352 11:42:23.487794 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11353 11:42:23.494235 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11354 11:42:23.520111 # Registered handlers for all signals.
11355 11:42:23.520302 # Detected MINSTKSIGSZ:4720
11356 11:42:23.523166 # Testcase initialized.
11357 11:42:23.526643 # uc context validated.
11358 11:42:23.526828 # Handled SIG_TRIG
11359 11:42:23.536358 # SIG_OK -- SP:0xFFFFCE789AC0 si_addr@:0xffffce789ac0 si_code:2 token@:(nil) offset:-281474145753792
11360 11:42:23.539383 # ==>> completed. PASS(1)
11361 11:42:23.546124 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11362 11:42:23.549405 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11363 11:42:23.556045 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11364 11:42:23.585196 # Registered handlers for all signals.
11365 11:42:23.585280 # Detected MINSTKSIGSZ:4720
11366 11:42:23.588540 # Testcase initialized.
11367 11:42:23.591769 # uc context validated.
11368 11:42:23.591852 # Handled SIG_TRIG
11369 11:42:23.601569 # SIG_OK -- SP:0xFFFFDF9B6270 si_addr@:0xffffdf9b6270 si_code:2 token@:(nil) offset:-281474433245808
11370 11:42:23.605153 # ==>> completed. PASS(1)
11371 11:42:23.611836 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11372 11:42:23.615099 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11373 11:42:23.621534 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11374 11:42:23.646499 # Registered handlers for all signals.
11375 11:42:23.646618 # Detected MINSTKSIGSZ:4720
11376 11:42:23.650069 # Testcase initialized.
11377 11:42:23.653246 # uc context validated.
11378 11:42:23.653353 # Handled SIG_TRIG
11379 11:42:23.663539 # SIG_OK -- SP:0xFFFFC90190B0 si_addr@:0xffffc90190b0 si_code:2 token@:(nil) offset:-281474054066352
11380 11:42:23.666300 # ==>> completed. PASS(1)
11381 11:42:23.673052 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11382 11:42:23.676360 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11383 11:42:23.683081 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11384 11:42:23.708312 # Registered handlers for all signals.
11385 11:42:23.708778 # Detected MINSTKSIGSZ:4720
11386 11:42:23.711555 # Testcase initialized.
11387 11:42:23.714996 # uc context validated.
11388 11:42:23.715417 # Handled SIG_TRIG
11389 11:42:23.724649 # SIG_OK -- SP:0xFFFFE7B8A740 si_addr@:0xffffe7b8a740 si_code:2 token@:(nil) offset:-281474569381696
11390 11:42:23.727875 # ==>> completed. PASS(1)
11391 11:42:23.734426 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11392 11:42:23.737798 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11393 11:42:23.744318 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11394 11:42:23.772801 # Registered handlers for all signals.
11395 11:42:23.772885 # Detected MINSTKSIGSZ:4720
11396 11:42:23.776122 # Testcase initialized.
11397 11:42:23.779224 # uc context validated.
11398 11:42:23.779306 # Handled SIG_TRIG
11399 11:42:23.788950 # SIG_OK -- SP:0xFFFFFE597320 si_addr@:0xfffffe597320 si_code:2 token@:(nil) offset:-281474949018400
11400 11:42:23.792438 # ==>> completed. PASS(1)
11401 11:42:23.799155 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11402 11:42:23.802633 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11403 11:42:23.805775 # selftests: arm64: sme_trap_no_sm
11404 11:42:23.835568 # Registered handlers for all signals.
11405 11:42:23.835661 # Detected MINSTKSIGSZ:4720
11406 11:42:23.839000 # ==>> completed. SKIP.
11407 11:42:23.849229 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11408 11:42:23.852112 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11409 11:42:23.855326 # selftests: arm64: sme_trap_non_streaming
11410 11:42:23.897544 # Registered handlers for all signals.
11411 11:42:23.897626 # Detected MINSTKSIGSZ:4720
11412 11:42:23.900530 # ==>> completed. SKIP.
11413 11:42:23.910469 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11414 11:42:23.917171 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11415 11:42:23.920455 # selftests: arm64: sme_trap_za
11416 11:42:23.959778 # Registered handlers for all signals.
11417 11:42:23.959964 # Detected MINSTKSIGSZ:4720
11418 11:42:23.963177 # Testcase initialized.
11419 11:42:23.973333 # SIG_OK -- SP:0xFFFFE8FA97D0 si_addr@:0xaaaaced12510 si_code:1 token@:(nil) offset:-187650590975248
11420 11:42:23.973508 # ==>> completed. PASS(1)
11421 11:42:23.982661 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11422 11:42:23.986038 ok 21 selftests: arm64: sme_trap_za
11423 11:42:23.986120 # selftests: arm64: sme_vl
11424 11:42:24.022408 # Registered handlers for all signals.
11425 11:42:24.022560 # Detected MINSTKSIGSZ:4720
11426 11:42:24.025818 # ==>> completed. SKIP.
11427 11:42:24.032357 # # SME VL :: Check that we get the right SME VL reported
11428 11:42:24.035569 ok 22 selftests: arm64: sme_vl # SKIP
11429 11:42:24.035697 # selftests: arm64: ssve_regs
11430 11:42:24.084863 # Registered handlers for all signals.
11431 11:42:24.085089 # Detected MINSTKSIGSZ:4720
11432 11:42:24.088506 # ==>> completed. SKIP.
11433 11:42:24.094990 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11434 11:42:24.098139 ok 23 selftests: arm64: ssve_regs # SKIP
11435 11:42:24.101299 # selftests: arm64: sve_regs
11436 11:42:24.145733 # Registered handlers for all signals.
11437 11:42:24.145852 # Detected MINSTKSIGSZ:4720
11438 11:42:24.148835 # ==>> completed. SKIP.
11439 11:42:24.155307 # # SVE registers :: Check that we get the right SVE registers reported
11440 11:42:24.158691 ok 24 selftests: arm64: sve_regs # SKIP
11441 11:42:24.161881 # selftests: arm64: sve_vl
11442 11:42:24.208869 # Registered handlers for all signals.
11443 11:42:24.208998 # Detected MINSTKSIGSZ:4720
11444 11:42:24.212546 # ==>> completed. SKIP.
11445 11:42:24.218558 # # SVE VL :: Check that we get the right SVE VL reported
11446 11:42:24.221825 ok 25 selftests: arm64: sve_vl # SKIP
11447 11:42:24.221929 # selftests: arm64: za_no_regs
11448 11:42:24.272508 # Registered handlers for all signals.
11449 11:42:24.272649 # Detected MINSTKSIGSZ:4720
11450 11:42:24.275852 # ==>> completed. SKIP.
11451 11:42:24.282690 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11452 11:42:24.285619 ok 26 selftests: arm64: za_no_regs # SKIP
11453 11:42:24.288849 # selftests: arm64: za_regs
11454 11:42:24.331862 # Registered handlers for all signals.
11455 11:42:24.332040 # Detected MINSTKSIGSZ:4720
11456 11:42:24.334955 # ==>> completed. SKIP.
11457 11:42:24.341852 # # ZA register :: Check that we get the right ZA registers reported
11458 11:42:24.345269 ok 27 selftests: arm64: za_regs # SKIP
11459 11:42:24.348429 # selftests: arm64: pac
11460 11:42:24.393964 # TAP version 13
11461 11:42:24.394172 # 1..7
11462 11:42:24.396680 # # Starting 7 tests from 1 test cases.
11463 11:42:24.399846 # # RUN global.corrupt_pac ...
11464 11:42:24.403032 # # SKIP PAUTH not enabled
11465 11:42:24.406537 # # OK global.corrupt_pac
11466 11:42:24.409860 # ok 1 # SKIP PAUTH not enabled
11467 11:42:24.416540 # # RUN global.pac_instructions_not_nop ...
11468 11:42:24.419870 # # SKIP PAUTH not enabled
11469 11:42:24.423193 # # OK global.pac_instructions_not_nop
11470 11:42:24.426785 # ok 2 # SKIP PAUTH not enabled
11471 11:42:24.432993 # # RUN global.pac_instructions_not_nop_generic ...
11472 11:42:24.436407 # # SKIP Generic PAUTH not enabled
11473 11:42:24.439875 # # OK global.pac_instructions_not_nop_generic
11474 11:42:24.446150 # ok 3 # SKIP Generic PAUTH not enabled
11475 11:42:24.449568 # # RUN global.single_thread_different_keys ...
11476 11:42:24.453113 # # SKIP PAUTH not enabled
11477 11:42:24.459261 # # OK global.single_thread_different_keys
11478 11:42:24.459372 # ok 4 # SKIP PAUTH not enabled
11479 11:42:24.466288 # # RUN global.exec_changed_keys ...
11480 11:42:24.469380 # # SKIP PAUTH not enabled
11481 11:42:24.472777 # # OK global.exec_changed_keys
11482 11:42:24.475804 # ok 5 # SKIP PAUTH not enabled
11483 11:42:24.479121 # # RUN global.context_switch_keep_keys ...
11484 11:42:24.482736 # # SKIP PAUTH not enabled
11485 11:42:24.489225 # # OK global.context_switch_keep_keys
11486 11:42:24.492290 # ok 6 # SKIP PAUTH not enabled
11487 11:42:24.495618 # # RUN global.context_switch_keep_keys_generic ...
11488 11:42:24.499446 # # SKIP Generic PAUTH not enabled
11489 11:42:24.505886 # # OK global.context_switch_keep_keys_generic
11490 11:42:24.509310 # ok 7 # SKIP Generic PAUTH not enabled
11491 11:42:24.512231 # # PASSED: 7 / 7 tests passed.
11492 11:42:24.518982 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11493 11:42:24.519455 ok 28 selftests: arm64: pac
11494 11:42:24.522143 # selftests: arm64: fp-stress
11495 11:42:33.286108 <6>[ 46.155493] vpu: disabling
11496 11:42:33.289362 <6>[ 46.158555] vproc2: disabling
11497 11:42:33.292834 <6>[ 46.161830] vproc1: disabling
11498 11:42:33.295908 <6>[ 46.165110] vaud18: disabling
11499 11:42:33.303233 <6>[ 46.168594] vsram_others: disabling
11500 11:42:33.305691 <6>[ 46.172523] va09: disabling
11501 11:42:33.309134 <6>[ 46.175666] vsram_md: disabling
11502 11:42:33.312146 <6>[ 46.179186] Vgpu: disabling
11503 11:42:34.464664 # TAP version 13
11504 11:42:34.465260 # 1..16
11505 11:42:34.467667 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11506 11:42:34.470815 # # Will run for 10s
11507 11:42:34.471279 # # Started FPSIMD-0-0
11508 11:42:34.474197 # # Started FPSIMD-0-1
11509 11:42:34.477618 # # Started FPSIMD-1-0
11510 11:42:34.478080 # # Started FPSIMD-1-1
11511 11:42:34.480815 # # Started FPSIMD-2-0
11512 11:42:34.481346 # # Started FPSIMD-2-1
11513 11:42:34.483791 # # Started FPSIMD-3-0
11514 11:42:34.487226 # # Started FPSIMD-3-1
11515 11:42:34.487686 # # Started FPSIMD-4-0
11516 11:42:34.490651 # # Started FPSIMD-4-1
11517 11:42:34.493654 # # Started FPSIMD-5-0
11518 11:42:34.494113 # # Started FPSIMD-5-1
11519 11:42:34.497116 # # Started FPSIMD-6-0
11520 11:42:34.500521 # # Started FPSIMD-6-1
11521 11:42:34.501011 # # Started FPSIMD-7-0
11522 11:42:34.503580 # # FPSIMD-1-0: Vector length: 128 bits
11523 11:42:34.506857 # # FPSIMD-1-0: PID: 1126
11524 11:42:34.510100 # # FPSIMD-0-1: Vector length: 128 bits
11525 11:42:34.513672 # # FPSIMD-0-1: PID: 1125
11526 11:42:34.514130 # # Started FPSIMD-7-1
11527 11:42:34.517185 # # FPSIMD-2-1: Vector length: 128 bits
11528 11:42:34.520128 # # FPSIMD-2-1: PID: 1129
11529 11:42:34.523561 # # FPSIMD-0-0: Vector length: 128 bits
11530 11:42:34.526936 # # FPSIMD-0-0: PID: 1124
11531 11:42:34.530059 # # FPSIMD-1-1: Vector length: 128 bits
11532 11:42:34.533433 # # FPSIMD-1-1: PID: 1127
11533 11:42:34.536744 # # FPSIMD-2-0: Vector length: 128 bits
11534 11:42:34.537215 # # FPSIMD-2-0: PID: 1128
11535 11:42:34.543678 # # FPSIMD-4-0: Vector length: 128 bits
11536 11:42:34.544227 # # FPSIMD-4-0: PID: 1132
11537 11:42:34.546631 # # FPSIMD-3-1: Vector length: 128 bits
11538 11:42:34.550275 # # FPSIMD-3-1: PID: 1131
11539 11:42:34.553638 # # FPSIMD-5-0: Vector length: 128 bits
11540 11:42:34.556673 # # FPSIMD-5-0: PID: 1134
11541 11:42:34.559807 # # FPSIMD-3-0: Vector length: 128 bits
11542 11:42:34.562993 # # FPSIMD-3-0: PID: 1130
11543 11:42:34.566908 # # FPSIMD-5-1: Vector length: 128 bits
11544 11:42:34.567371 # # FPSIMD-5-1: PID: 1135
11545 11:42:34.573325 # # FPSIMD-6-0: Vector length: 128 bits
11546 11:42:34.573786 # # FPSIMD-6-0: PID: 1136
11547 11:42:34.575945 # # FPSIMD-7-0: Vector length: 128 bits
11548 11:42:34.579410 # # FPSIMD-7-0: PID: 1138
11549 11:42:34.582761 # # FPSIMD-7-1: Vector length: 128 bits
11550 11:42:34.586063 # # FPSIMD-7-1: PID: 1139
11551 11:42:34.589586 # # FPSIMD-6-1: Vector length: 128 bits
11552 11:42:34.592426 # # FPSIMD-6-1: PID: 1137
11553 11:42:34.596222 # # FPSIMD-4-1: Vector length: 128 bits
11554 11:42:34.596401 # # FPSIMD-4-1: PID: 1133
11555 11:42:34.599361 # # Finishing up...
11556 11:42:34.606397 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=683800, signals=10
11557 11:42:34.612571 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=733185, signals=10
11558 11:42:34.618982 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1311518, signals=10
11559 11:42:34.628792 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1200160, signals=10
11560 11:42:34.635388 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1843232, signals=10
11561 11:42:34.642001 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=620278, signals=10
11562 11:42:34.648464 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=349455, signals=10
11563 11:42:34.652028 # ok 1 FPSIMD-0-0
11564 11:42:34.652200 # ok 2 FPSIMD-0-1
11565 11:42:34.655336 # ok 3 FPSIMD-1-0
11566 11:42:34.655507 # ok 4 FPSIMD-1-1
11567 11:42:34.658911 # ok 5 FPSIMD-2-0
11568 11:42:34.659093 # ok 6 FPSIMD-2-1
11569 11:42:34.662153 # ok 7 FPSIMD-3-0
11570 11:42:34.662310 # ok 8 FPSIMD-3-1
11571 11:42:34.665168 # ok 9 FPSIMD-4-0
11572 11:42:34.665321 # ok 10 FPSIMD-4-1
11573 11:42:34.668385 # ok 11 FPSIMD-5-0
11574 11:42:34.668560 # ok 12 FPSIMD-5-1
11575 11:42:34.671504 # ok 13 FPSIMD-6-0
11576 11:42:34.671727 # ok 14 FPSIMD-6-1
11577 11:42:34.675652 # ok 15 FPSIMD-7-0
11578 11:42:34.675868 # ok 16 FPSIMD-7-1
11579 11:42:34.681434 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=973053, signals=9
11580 11:42:34.691774 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=464137, signals=9
11581 11:42:34.698308 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=911974, signals=10
11582 11:42:34.705175 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=638126, signals=10
11583 11:42:34.711695 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=361374, signals=10
11584 11:42:34.717945 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=374802, signals=10
11585 11:42:34.724722 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1113720, signals=10
11586 11:42:34.734727 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=383864, signals=10
11587 11:42:34.741460 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=865217, signals=9
11588 11:42:34.744547 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11589 11:42:34.748004 ok 29 selftests: arm64: fp-stress
11590 11:42:34.751164 # selftests: arm64: sve-ptrace
11591 11:42:34.751710 # TAP version 13
11592 11:42:34.754665 # 1..4104
11593 11:42:34.757730 # ok 2 # SKIP SVE not available
11594 11:42:34.761069 # # Planned tests != run tests (4104 != 1)
11595 11:42:34.764130 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11596 11:42:34.767832 ok 30 selftests: arm64: sve-ptrace # SKIP
11597 11:42:34.771152 # selftests: arm64: sve-probe-vls
11598 11:42:34.773933 # TAP version 13
11599 11:42:34.774448 # 1..2
11600 11:42:34.777747 # ok 2 # SKIP SVE not available
11601 11:42:34.780556 # # Planned tests != run tests (2 != 1)
11602 11:42:34.787680 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11603 11:42:34.790795 ok 31 selftests: arm64: sve-probe-vls # SKIP
11604 11:42:34.793802 # selftests: arm64: vec-syscfg
11605 11:42:34.794262 # TAP version 13
11606 11:42:34.794621 # 1..20
11607 11:42:34.797155 # ok 1 # SKIP SVE not supported
11608 11:42:34.801069 # ok 2 # SKIP SVE not supported
11609 11:42:34.803846 # ok 3 # SKIP SVE not supported
11610 11:42:34.807089 # ok 4 # SKIP SVE not supported
11611 11:42:34.810871 # ok 5 # SKIP SVE not supported
11612 11:42:34.811431 # ok 6 # SKIP SVE not supported
11613 11:42:34.813826 # ok 7 # SKIP SVE not supported
11614 11:42:34.817473 # ok 8 # SKIP SVE not supported
11615 11:42:34.820358 # ok 9 # SKIP SVE not supported
11616 11:42:34.823820 # ok 10 # SKIP SVE not supported
11617 11:42:34.827026 # ok 11 # SKIP SME not supported
11618 11:42:34.830881 # ok 12 # SKIP SME not supported
11619 11:42:34.833422 # ok 13 # SKIP SME not supported
11620 11:42:34.836667 # ok 14 # SKIP SME not supported
11621 11:42:34.837163 # ok 15 # SKIP SME not supported
11622 11:42:34.840190 # ok 16 # SKIP SME not supported
11623 11:42:34.843345 # ok 17 # SKIP SME not supported
11624 11:42:34.846624 # ok 18 # SKIP SME not supported
11625 11:42:34.850082 # ok 19 # SKIP SME not supported
11626 11:42:34.853346 # ok 20 # SKIP SME not supported
11627 11:42:34.856677 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11628 11:42:34.860309 ok 32 selftests: arm64: vec-syscfg
11629 11:42:34.863889 # selftests: arm64: za-fork
11630 11:42:34.866846 # TAP version 13
11631 11:42:34.867303 # 1..1
11632 11:42:34.867673 # # PID: 1209
11633 11:42:34.869939 # # SME support not present
11634 11:42:34.870545 # ok 0 skipped
11635 11:42:34.876884 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11636 11:42:34.879653 ok 33 selftests: arm64: za-fork
11637 11:42:34.883300 # selftests: arm64: za-ptrace
11638 11:42:34.883897 # TAP version 13
11639 11:42:34.884264 # 1..1
11640 11:42:34.887350 # ok 2 # SKIP SME not available
11641 11:42:34.893146 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11642 11:42:34.896345 ok 34 selftests: arm64: za-ptrace # SKIP
11643 11:42:34.899423 # selftests: arm64: check_buffer_fill
11644 11:42:34.902740 # # SKIP: MTE features unavailable
11645 11:42:34.906656 ok 35 selftests: arm64: check_buffer_fill # SKIP
11646 11:42:34.909242 # selftests: arm64: check_child_memory
11647 11:42:34.955012 # # SKIP: MTE features unavailable
11648 11:42:34.961435 ok 36 selftests: arm64: check_child_memory # SKIP
11649 11:42:34.975647 # selftests: arm64: check_gcr_el1_cswitch
11650 11:42:35.022924 # # SKIP: MTE features unavailable
11651 11:42:35.029548 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11652 11:42:35.046191 # selftests: arm64: check_ksm_options
11653 11:42:35.093716 # # SKIP: MTE features unavailable
11654 11:42:35.100419 ok 38 selftests: arm64: check_ksm_options # SKIP
11655 11:42:35.114848 # selftests: arm64: check_mmap_options
11656 11:42:35.164463 # # SKIP: MTE features unavailable
11657 11:42:35.170938 ok 39 selftests: arm64: check_mmap_options # SKIP
11658 11:42:35.184101 # selftests: arm64: check_prctl
11659 11:42:35.236159 # TAP version 13
11660 11:42:35.236420 # 1..5
11661 11:42:35.239044 # ok 1 check_basic_read
11662 11:42:35.239260 # ok 2 NONE
11663 11:42:35.242372 # ok 3 # SKIP SYNC
11664 11:42:35.242573 # ok 4 # SKIP ASYNC
11665 11:42:35.245931 # ok 5 # SKIP SYNC+ASYNC
11666 11:42:35.249283 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11667 11:42:35.252536 ok 40 selftests: arm64: check_prctl
11668 11:42:35.259159 # selftests: arm64: check_tags_inclusion
11669 11:42:35.305946 # # SKIP: MTE features unavailable
11670 11:42:35.312633 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11671 11:42:35.324153 # selftests: arm64: check_user_mem
11672 11:42:35.375677 # # SKIP: MTE features unavailable
11673 11:42:35.382289 ok 42 selftests: arm64: check_user_mem # SKIP
11674 11:42:35.391425 # selftests: arm64: btitest
11675 11:42:35.440570 # TAP version 13
11676 11:42:35.441177 # 1..18
11677 11:42:35.443633 # # HWCAP_PACA not present
11678 11:42:35.447298 # # HWCAP2_BTI not present
11679 11:42:35.447762 # # Test binary built for BTI
11680 11:42:35.453506 # ok 1 nohint_func/call_using_br_x0 # SKIP
11681 11:42:35.457001 # ok 1 nohint_func/call_using_br_x16 # SKIP
11682 11:42:35.460094 # ok 1 nohint_func/call_using_blr # SKIP
11683 11:42:35.463494 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11684 11:42:35.466803 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11685 11:42:35.473323 # ok 1 bti_none_func/call_using_blr # SKIP
11686 11:42:35.476814 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11687 11:42:35.480274 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11688 11:42:35.484085 # ok 1 bti_c_func/call_using_blr # SKIP
11689 11:42:35.486847 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11690 11:42:35.490045 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11691 11:42:35.493212 # ok 1 bti_j_func/call_using_blr # SKIP
11692 11:42:35.496519 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11693 11:42:35.502943 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11694 11:42:35.506494 # ok 1 bti_jc_func/call_using_blr # SKIP
11695 11:42:35.509882 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11696 11:42:35.513116 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11697 11:42:35.516364 # ok 1 paciasp_func/call_using_blr # SKIP
11698 11:42:35.522981 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11699 11:42:35.526518 # # WARNING - EXPECTED TEST COUNT WRONG
11700 11:42:35.529609 ok 43 selftests: arm64: btitest
11701 11:42:35.532786 # selftests: arm64: nobtitest
11702 11:42:35.533384 # TAP version 13
11703 11:42:35.533736 # 1..18
11704 11:42:35.536072 # # HWCAP_PACA not present
11705 11:42:35.539143 # # HWCAP2_BTI not present
11706 11:42:35.542766 # # Test binary not built for BTI
11707 11:42:35.545980 # ok 1 nohint_func/call_using_br_x0 # SKIP
11708 11:42:35.549400 # ok 1 nohint_func/call_using_br_x16 # SKIP
11709 11:42:35.552920 # ok 1 nohint_func/call_using_blr # SKIP
11710 11:42:35.556027 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11711 11:42:35.563042 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11712 11:42:35.566072 # ok 1 bti_none_func/call_using_blr # SKIP
11713 11:42:35.569042 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11714 11:42:35.572623 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11715 11:42:35.575656 # ok 1 bti_c_func/call_using_blr # SKIP
11716 11:42:35.579058 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11717 11:42:35.582656 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11718 11:42:35.585911 # ok 1 bti_j_func/call_using_blr # SKIP
11719 11:42:35.592190 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11720 11:42:35.595274 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11721 11:42:35.599071 # ok 1 bti_jc_func/call_using_blr # SKIP
11722 11:42:35.602274 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11723 11:42:35.605412 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11724 11:42:35.608591 # ok 1 paciasp_func/call_using_blr # SKIP
11725 11:42:35.615337 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11726 11:42:35.618961 # # WARNING - EXPECTED TEST COUNT WRONG
11727 11:42:35.622213 ok 44 selftests: arm64: nobtitest
11728 11:42:35.625363 # selftests: arm64: hwcap
11729 11:42:35.625825 # TAP version 13
11730 11:42:35.626187 # 1..28
11731 11:42:35.628406 # ok 1 cpuinfo_match_RNG
11732 11:42:35.631845 # # SIGILL reported for RNG
11733 11:42:35.635281 # ok 2 # SKIP sigill_RNG
11734 11:42:35.635763 # ok 3 cpuinfo_match_SME
11735 11:42:35.638397 # ok 4 sigill_SME
11736 11:42:35.639001 # ok 5 cpuinfo_match_SVE
11737 11:42:35.641481 # ok 6 sigill_SVE
11738 11:42:35.644838 # ok 7 cpuinfo_match_SVE 2
11739 11:42:35.645421 # # SIGILL reported for SVE 2
11740 11:42:35.648298 # ok 8 # SKIP sigill_SVE 2
11741 11:42:35.651788 # ok 9 cpuinfo_match_SVE AES
11742 11:42:35.654981 # # SIGILL reported for SVE AES
11743 11:42:35.658608 # ok 10 # SKIP sigill_SVE AES
11744 11:42:35.661797 # ok 11 cpuinfo_match_SVE2 PMULL
11745 11:42:35.662263 # # SIGILL reported for SVE2 PMULL
11746 11:42:35.664843 # ok 12 # SKIP sigill_SVE2 PMULL
11747 11:42:35.668034 # ok 13 cpuinfo_match_SVE2 BITPERM
11748 11:42:35.671571 # # SIGILL reported for SVE2 BITPERM
11749 11:42:35.674753 # ok 14 # SKIP sigill_SVE2 BITPERM
11750 11:42:35.678020 # ok 15 cpuinfo_match_SVE2 SHA3
11751 11:42:35.681175 # # SIGILL reported for SVE2 SHA3
11752 11:42:35.684521 # ok 16 # SKIP sigill_SVE2 SHA3
11753 11:42:35.687954 # ok 17 cpuinfo_match_SVE2 SM4
11754 11:42:35.691609 # # SIGILL reported for SVE2 SM4
11755 11:42:35.694748 # ok 18 # SKIP sigill_SVE2 SM4
11756 11:42:35.695258 # ok 19 cpuinfo_match_SVE2 I8MM
11757 11:42:35.697865 # # SIGILL reported for SVE2 I8MM
11758 11:42:35.701202 # ok 20 # SKIP sigill_SVE2 I8MM
11759 11:42:35.704465 # ok 21 cpuinfo_match_SVE2 F32MM
11760 11:42:35.707524 # # SIGILL reported for SVE2 F32MM
11761 11:42:35.711374 # ok 22 # SKIP sigill_SVE2 F32MM
11762 11:42:35.714544 # ok 23 cpuinfo_match_SVE2 F64MM
11763 11:42:35.717630 # # SIGILL reported for SVE2 F64MM
11764 11:42:35.721406 # ok 24 # SKIP sigill_SVE2 F64MM
11765 11:42:35.721866 # ok 25 cpuinfo_match_SVE2 BF16
11766 11:42:35.724375 # # SIGILL reported for SVE2 BF16
11767 11:42:35.727596 # ok 26 # SKIP sigill_SVE2 BF16
11768 11:42:35.730825 # ok 27 cpuinfo_match_SVE2 EBF16
11769 11:42:35.734266 # ok 28 # SKIP sigill_SVE2 EBF16
11770 11:42:35.740831 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11771 11:42:35.741342 ok 45 selftests: arm64: hwcap
11772 11:42:35.744223 # selftests: arm64: ptrace
11773 11:42:35.747459 # TAP version 13
11774 11:42:35.747918 # 1..7
11775 11:42:35.750472 # # Parent is 1438, child is 1439
11776 11:42:35.750975 # ok 1 read_tpidr_one
11777 11:42:35.753615 # ok 2 write_tpidr_one
11778 11:42:35.757353 # ok 3 verify_tpidr_one
11779 11:42:35.757867 # ok 4 count_tpidrs
11780 11:42:35.760613 # ok 5 tpidr2_write
11781 11:42:35.761179 # ok 6 tpidr2_read
11782 11:42:35.764004 # ok 7 write_tpidr_only
11783 11:42:35.770275 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11784 11:42:35.770758 ok 46 selftests: arm64: ptrace
11785 11:42:35.773569 # selftests: arm64: syscall-abi
11786 11:42:35.777273 # TAP version 13
11787 11:42:35.777789 # 1..2
11788 11:42:35.780072 # ok 1 getpid() FPSIMD
11789 11:42:35.780484 # ok 2 sched_yield() FPSIMD
11790 11:42:35.787017 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11791 11:42:35.790129 ok 47 selftests: arm64: syscall-abi
11792 11:42:35.793543 # selftests: arm64: tpidr2
11793 11:42:35.793955 # TAP version 13
11794 11:42:35.794313 # 1..5
11795 11:42:35.796729 # # PID: 1473
11796 11:42:35.797325 # # SME support not present
11797 11:42:35.800098 # ok 0 skipped, TPIDR2 not supported
11798 11:42:35.803214 # ok 1 skipped, TPIDR2 not supported
11799 11:42:35.806728 # ok 2 skipped, TPIDR2 not supported
11800 11:42:35.809786 # ok 3 skipped, TPIDR2 not supported
11801 11:42:35.813098 # ok 4 skipped, TPIDR2 not supported
11802 11:42:35.819592 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11803 11:42:35.823060 ok 48 selftests: arm64: tpidr2
11804 11:42:36.413547 arm64_tags_test pass
11805 11:42:36.416912 arm64_run_tags_test_sh pass
11806 11:42:36.420271 arm64_fake_sigreturn_bad_magic pass
11807 11:42:36.423673 arm64_fake_sigreturn_bad_size pass
11808 11:42:36.427167 arm64_fake_sigreturn_bad_size_for_magic0 pass
11809 11:42:36.430373 arm64_fake_sigreturn_duplicated_fpsimd pass
11810 11:42:36.433045 arm64_fake_sigreturn_misaligned_sp pass
11811 11:42:36.436454 arm64_fake_sigreturn_missing_fpsimd pass
11812 11:42:36.439855 arm64_fake_sigreturn_sme_change_vl skip
11813 11:42:36.446766 arm64_fake_sigreturn_sve_change_vl skip
11814 11:42:36.449922 arm64_mangle_pstate_invalid_compat_toggle pass
11815 11:42:36.453109 arm64_mangle_pstate_invalid_daif_bits pass
11816 11:42:36.456810 arm64_mangle_pstate_invalid_mode_el1h pass
11817 11:42:36.459728 arm64_mangle_pstate_invalid_mode_el1t pass
11818 11:42:36.463029 arm64_mangle_pstate_invalid_mode_el2h pass
11819 11:42:36.469788 arm64_mangle_pstate_invalid_mode_el2t pass
11820 11:42:36.473238 arm64_mangle_pstate_invalid_mode_el3h pass
11821 11:42:36.476008 arm64_mangle_pstate_invalid_mode_el3t pass
11822 11:42:36.479748 arm64_sme_trap_no_sm skip
11823 11:42:36.482443 arm64_sme_trap_non_streaming skip
11824 11:42:36.483042 arm64_sme_trap_za pass
11825 11:42:36.486019 arm64_sme_vl skip
11826 11:42:36.486478 arm64_ssve_regs skip
11827 11:42:36.489081 arm64_sve_regs skip
11828 11:42:36.489540 arm64_sve_vl skip
11829 11:42:36.492469 arm64_za_no_regs skip
11830 11:42:36.492929 arm64_za_regs skip
11831 11:42:36.495794 arm64_pac_PAUTH_not_enabled skip
11832 11:42:36.499409 arm64_pac_PAUTH_not_enabled skip
11833 11:42:36.502588 arm64_pac_Generic_PAUTH_not_enabled skip
11834 11:42:36.505876 arm64_pac_PAUTH_not_enabled skip
11835 11:42:36.509027 arm64_pac_PAUTH_not_enabled skip
11836 11:42:36.512261 arm64_pac_PAUTH_not_enabled skip
11837 11:42:36.515784 arm64_pac_Generic_PAUTH_not_enabled skip
11838 11:42:36.518407 arm64_pac pass
11839 11:42:36.518869 arm64_fp-stress_FPSIMD-0-0 pass
11840 11:42:36.522147 arm64_fp-stress_FPSIMD-0-1 pass
11841 11:42:36.525676 arm64_fp-stress_FPSIMD-1-0 pass
11842 11:42:36.528399 arm64_fp-stress_FPSIMD-1-1 pass
11843 11:42:36.532153 arm64_fp-stress_FPSIMD-2-0 pass
11844 11:42:36.535145 arm64_fp-stress_FPSIMD-2-1 pass
11845 11:42:36.538378 arm64_fp-stress_FPSIMD-3-0 pass
11846 11:42:36.541937 arm64_fp-stress_FPSIMD-3-1 pass
11847 11:42:36.542499 arm64_fp-stress_FPSIMD-4-0 pass
11848 11:42:36.545167 arm64_fp-stress_FPSIMD-4-1 pass
11849 11:42:36.548409 arm64_fp-stress_FPSIMD-5-0 pass
11850 11:42:36.551979 arm64_fp-stress_FPSIMD-5-1 pass
11851 11:42:36.555017 arm64_fp-stress_FPSIMD-6-0 pass
11852 11:42:36.558589 arm64_fp-stress_FPSIMD-6-1 pass
11853 11:42:36.561293 arm64_fp-stress_FPSIMD-7-0 pass
11854 11:42:36.565242 arm64_fp-stress_FPSIMD-7-1 pass
11855 11:42:36.565804 arm64_fp-stress pass
11856 11:42:36.568157 arm64_sve-ptrace_SVE_not_available skip
11857 11:42:36.571254 arm64_sve-ptrace skip
11858 11:42:36.574759 arm64_sve-probe-vls_SVE_not_available skip
11859 11:42:36.578307 arm64_sve-probe-vls skip
11860 11:42:36.581098 arm64_vec-syscfg_SVE_not_supported skip
11861 11:42:36.584645 arm64_vec-syscfg_SVE_not_supported skip
11862 11:42:36.587977 arm64_vec-syscfg_SVE_not_supported skip
11863 11:42:36.591212 arm64_vec-syscfg_SVE_not_supported skip
11864 11:42:36.594967 arm64_vec-syscfg_SVE_not_supported skip
11865 11:42:36.597739 arm64_vec-syscfg_SVE_not_supported skip
11866 11:42:36.601053 arm64_vec-syscfg_SVE_not_supported skip
11867 11:42:36.604652 arm64_vec-syscfg_SVE_not_supported skip
11868 11:42:36.607893 arm64_vec-syscfg_SVE_not_supported skip
11869 11:42:36.611572 arm64_vec-syscfg_SVE_not_supported skip
11870 11:42:36.614471 arm64_vec-syscfg_SME_not_supported skip
11871 11:42:36.621233 arm64_vec-syscfg_SME_not_supported skip
11872 11:42:36.624523 arm64_vec-syscfg_SME_not_supported skip
11873 11:42:36.627833 arm64_vec-syscfg_SME_not_supported skip
11874 11:42:36.631077 arm64_vec-syscfg_SME_not_supported skip
11875 11:42:36.634407 arm64_vec-syscfg_SME_not_supported skip
11876 11:42:36.637184 arm64_vec-syscfg_SME_not_supported skip
11877 11:42:36.640863 arm64_vec-syscfg_SME_not_supported skip
11878 11:42:36.644285 arm64_vec-syscfg_SME_not_supported skip
11879 11:42:36.647540 arm64_vec-syscfg_SME_not_supported skip
11880 11:42:36.650609 arm64_vec-syscfg pass
11881 11:42:36.654219 arm64_za-fork_skipped pass
11882 11:42:36.654828 arm64_za-fork pass
11883 11:42:36.657112 arm64_za-ptrace_SME_not_available skip
11884 11:42:36.660607 arm64_za-ptrace skip
11885 11:42:36.661211 arm64_check_buffer_fill skip
11886 11:42:36.664015 arm64_check_child_memory skip
11887 11:42:36.667606 arm64_check_gcr_el1_cswitch skip
11888 11:42:36.670841 arm64_check_ksm_options skip
11889 11:42:36.673757 arm64_check_mmap_options skip
11890 11:42:36.677132 arm64_check_prctl_check_basic_read pass
11891 11:42:36.680354 arm64_check_prctl_NONE pass
11892 11:42:36.680825 arm64_check_prctl_SYNC skip
11893 11:42:36.683726 arm64_check_prctl_ASYNC skip
11894 11:42:36.686826 arm64_check_prctl_SYNC_ASYNC skip
11895 11:42:36.689971 arm64_check_prctl pass
11896 11:42:36.693581 arm64_check_tags_inclusion skip
11897 11:42:36.694157 arm64_check_user_mem skip
11898 11:42:36.700174 arm64_btitest_nohint_func_call_using_br_x0 skip
11899 11:42:36.703567 arm64_btitest_nohint_func_call_using_br_x16 skip
11900 11:42:36.706761 arm64_btitest_nohint_func_call_using_blr skip
11901 11:42:36.709856 arm64_btitest_bti_none_func_call_using_br_x0 skip
11902 11:42:36.716699 arm64_btitest_bti_none_func_call_using_br_x16 skip
11903 11:42:36.720122 arm64_btitest_bti_none_func_call_using_blr skip
11904 11:42:36.723239 arm64_btitest_bti_c_func_call_using_br_x0 skip
11905 11:42:36.729872 arm64_btitest_bti_c_func_call_using_br_x16 skip
11906 11:42:36.733353 arm64_btitest_bti_c_func_call_using_blr skip
11907 11:42:36.736454 arm64_btitest_bti_j_func_call_using_br_x0 skip
11908 11:42:36.739382 arm64_btitest_bti_j_func_call_using_br_x16 skip
11909 11:42:36.746378 arm64_btitest_bti_j_func_call_using_blr skip
11910 11:42:36.749725 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11911 11:42:36.752594 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11912 11:42:36.759390 arm64_btitest_bti_jc_func_call_using_blr skip
11913 11:42:36.762930 arm64_btitest_paciasp_func_call_using_br_x0 skip
11914 11:42:36.765915 arm64_btitest_paciasp_func_call_using_br_x16 skip
11915 11:42:36.769539 arm64_btitest_paciasp_func_call_using_blr skip
11916 11:42:36.772456 arm64_btitest pass
11917 11:42:36.776019 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11918 11:42:36.782372 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11919 11:42:36.785993 arm64_nobtitest_nohint_func_call_using_blr skip
11920 11:42:36.789086 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11921 11:42:36.795493 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11922 11:42:36.798953 arm64_nobtitest_bti_none_func_call_using_blr skip
11923 11:42:36.802554 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11924 11:42:36.809150 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11925 11:42:36.812259 arm64_nobtitest_bti_c_func_call_using_blr skip
11926 11:42:36.815443 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11927 11:42:36.822296 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11928 11:42:36.825401 arm64_nobtitest_bti_j_func_call_using_blr skip
11929 11:42:36.828503 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11930 11:42:36.835125 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11931 11:42:36.838704 arm64_nobtitest_bti_jc_func_call_using_blr skip
11932 11:42:36.841843 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11933 11:42:36.848871 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11934 11:42:36.851780 arm64_nobtitest_paciasp_func_call_using_blr skip
11935 11:42:36.855082 arm64_nobtitest pass
11936 11:42:36.858822 arm64_hwcap_cpuinfo_match_RNG pass
11937 11:42:36.859338 arm64_hwcap_sigill_RNG skip
11938 11:42:36.861694 arm64_hwcap_cpuinfo_match_SME pass
11939 11:42:36.865025 arm64_hwcap_sigill_SME pass
11940 11:42:36.868181 arm64_hwcap_cpuinfo_match_SVE pass
11941 11:42:36.871532 arm64_hwcap_sigill_SVE pass
11942 11:42:36.875047 arm64_hwcap_cpuinfo_match_SVE_2 pass
11943 11:42:36.878323 arm64_hwcap_sigill_SVE_2 skip
11944 11:42:36.881372 arm64_hwcap_cpuinfo_match_SVE_AES pass
11945 11:42:36.881929 arm64_hwcap_sigill_SVE_AES skip
11946 11:42:36.888098 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11947 11:42:36.891079 arm64_hwcap_sigill_SVE2_PMULL skip
11948 11:42:36.894524 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11949 11:42:36.898259 arm64_hwcap_sigill_SVE2_BITPERM skip
11950 11:42:36.901059 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11951 11:42:36.904080 arm64_hwcap_sigill_SVE2_SHA3 skip
11952 11:42:36.907737 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11953 11:42:36.910726 arm64_hwcap_sigill_SVE2_SM4 skip
11954 11:42:36.913865 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11955 11:42:36.917294 arm64_hwcap_sigill_SVE2_I8MM skip
11956 11:42:36.920753 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11957 11:42:36.924268 arm64_hwcap_sigill_SVE2_F32MM skip
11958 11:42:36.927190 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11959 11:42:36.930470 arm64_hwcap_sigill_SVE2_F64MM skip
11960 11:42:36.933833 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11961 11:42:36.936995 arm64_hwcap_sigill_SVE2_BF16 skip
11962 11:42:36.940710 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11963 11:42:36.943707 arm64_hwcap_sigill_SVE2_EBF16 skip
11964 11:42:36.943822 arm64_hwcap pass
11965 11:42:36.947015 arm64_ptrace_read_tpidr_one pass
11966 11:42:36.950603 arm64_ptrace_write_tpidr_one pass
11967 11:42:36.953998 arm64_ptrace_verify_tpidr_one pass
11968 11:42:36.957125 arm64_ptrace_count_tpidrs pass
11969 11:42:36.960451 arm64_ptrace_tpidr2_write pass
11970 11:42:36.963852 arm64_ptrace_tpidr2_read pass
11971 11:42:36.967128 arm64_ptrace_write_tpidr_only pass
11972 11:42:36.967273 arm64_ptrace pass
11973 11:42:36.970352 arm64_syscall-abi_getpid_FPSIMD pass
11974 11:42:36.973775 arm64_syscall-abi_sched_yield_FPSIMD pass
11975 11:42:36.976884 arm64_syscall-abi pass
11976 11:42:36.980406 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11977 11:42:36.983609 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11978 11:42:36.990223 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11979 11:42:36.993856 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11980 11:42:36.997042 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11981 11:42:37.000170 arm64_tpidr2 pass
11982 11:42:37.003568 + ../../utils/send-to-lava.sh ./output/result.txt
11983 11:42:37.010052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11984 11:42:37.010798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11986 11:42:37.016561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11987 11:42:37.017257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11989 11:42:37.023555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11990 11:42:37.024222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11992 11:42:37.030004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11993 11:42:37.030674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11995 11:42:37.036509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11996 11:42:37.037177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11998 11:42:37.079723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11999 11:42:37.080407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12001 11:42:37.126659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12002 11:42:37.126976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12004 11:42:37.176949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12005 11:42:37.177657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12007 11:42:37.220724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12008 11:42:37.221074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12010 11:42:37.264889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12011 11:42:37.265166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12013 11:42:37.307363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12014 11:42:37.307653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12016 11:42:37.354460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12017 11:42:37.354933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12019 11:42:37.395647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12020 11:42:37.395940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12022 11:42:37.446351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12023 11:42:37.447020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12025 11:42:37.489491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12026 11:42:37.489789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12028 11:42:37.533721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12029 11:42:37.534112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12031 11:42:37.579912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12032 11:42:37.580586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12034 11:42:37.629452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12035 11:42:37.630123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12037 11:42:37.678350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12038 11:42:37.679031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12040 11:42:37.729391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12042 11:42:37.732819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12043 11:42:37.785985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12044 11:42:37.786687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12046 11:42:37.836595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12047 11:42:37.837297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12049 11:42:37.891136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12050 11:42:37.891824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12052 11:42:37.940003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12053 11:42:37.940671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12055 11:42:37.989592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12056 11:42:37.990272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12058 11:42:38.040508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12059 11:42:38.041205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12061 11:42:38.090122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12062 11:42:38.090938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12064 11:42:38.140223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12066 11:42:38.142925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12067 11:42:38.192248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12069 11:42:38.195562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12070 11:42:38.248073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12071 11:42:38.248759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12073 11:42:38.298404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12075 11:42:38.301484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12076 11:42:38.351461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12078 11:42:38.354359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12079 11:42:38.400716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12080 11:42:38.401082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12082 11:42:38.443886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12083 11:42:38.444646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12085 11:42:38.487618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12086 11:42:38.488396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12088 11:42:38.539303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12089 11:42:38.540133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12091 11:42:38.588003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12092 11:42:38.588686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12094 11:42:38.634940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12095 11:42:38.635626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12097 11:42:38.685976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12098 11:42:38.686675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12100 11:42:38.734183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12101 11:42:38.734851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12103 11:42:38.790034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12104 11:42:38.790718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12106 11:42:38.845651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12107 11:42:38.846323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12109 11:42:38.900022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12110 11:42:38.900924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12112 11:42:38.946098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12113 11:42:38.946352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12115 11:42:38.992611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12116 11:42:38.993029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12118 11:42:39.036359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12119 11:42:39.037082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12121 11:42:39.092898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12122 11:42:39.093649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12124 11:42:39.147921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12125 11:42:39.148588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12127 11:42:39.209168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12128 11:42:39.210004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12130 11:42:39.256579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12131 11:42:39.257339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12133 11:42:39.308168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12134 11:42:39.309015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12136 11:42:39.363051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12137 11:42:39.363876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12139 11:42:39.418987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12140 11:42:39.419768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12142 11:42:39.472403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12143 11:42:39.473084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12145 11:42:39.530267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12146 11:42:39.531072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12148 11:42:39.572192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12149 11:42:39.572892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12151 11:42:39.621540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12152 11:42:39.622270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12154 11:42:39.673240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12155 11:42:39.673981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12157 11:42:39.721402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12158 11:42:39.722054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12160 11:42:39.769814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12161 11:42:39.770489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12163 11:42:39.812946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12164 11:42:39.813227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12166 11:42:39.858227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12167 11:42:39.858539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12169 11:42:39.899989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12170 11:42:39.900805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12172 11:42:39.942604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12173 11:42:39.943391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12175 11:42:39.990063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12176 11:42:39.990345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12178 11:42:40.032993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12179 11:42:40.033266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12181 11:42:40.071964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12182 11:42:40.072225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12184 11:42:40.116064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12185 11:42:40.116429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12187 11:42:40.174438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12188 11:42:40.175125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12190 11:42:40.220850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12191 11:42:40.221628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12193 11:42:40.266908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12194 11:42:40.267569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12196 11:42:40.314311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12197 11:42:40.314986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12199 11:42:40.364178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12200 11:42:40.364841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12202 11:42:40.411606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12203 11:42:40.412313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12205 11:42:40.463045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12206 11:42:40.463715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12208 11:42:40.511908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12209 11:42:40.512698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12211 11:42:40.559300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12212 11:42:40.560002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12214 11:42:40.613113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12215 11:42:40.613868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12217 11:42:40.659217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12218 11:42:40.659902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12220 11:42:40.711958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12221 11:42:40.712663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12223 11:42:40.756485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12224 11:42:40.757171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12226 11:42:40.808638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12227 11:42:40.809531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12229 11:42:40.860628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12230 11:42:40.861503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12232 11:42:40.909793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12234 11:42:40.912448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12235 11:42:40.955340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12236 11:42:40.956007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12238 11:42:41.005746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12239 11:42:41.006460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12241 11:42:41.058685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12242 11:42:41.059448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12244 11:42:41.109877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12245 11:42:41.110554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12247 11:42:41.163463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12248 11:42:41.164175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12250 11:42:41.214241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12251 11:42:41.215064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12253 11:42:41.264055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12254 11:42:41.264337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12256 11:42:41.293659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12257 11:42:41.293915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12259 11:42:41.341497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12260 11:42:41.341861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12262 11:42:41.387177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12263 11:42:41.387463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12265 11:42:41.429982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12266 11:42:41.430239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12268 11:42:41.469281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12269 11:42:41.469560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12271 11:42:41.508327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12272 11:42:41.508599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12274 11:42:41.545568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12275 11:42:41.545833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12277 11:42:41.590889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12278 11:42:41.591382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12280 11:42:41.631406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12281 11:42:41.631664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12283 11:42:41.671794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12284 11:42:41.672148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12286 11:42:41.718490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12287 11:42:41.718749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12289 11:42:41.753495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12290 11:42:41.753747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12292 11:42:41.795422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12293 11:42:41.795687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12295 11:42:41.834364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12296 11:42:41.834620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12298 11:42:41.874956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12299 11:42:41.875209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12301 11:42:41.918512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12302 11:42:41.918769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12304 11:42:41.958988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12305 11:42:41.959255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12307 11:42:42.004285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12308 11:42:42.004785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12310 11:42:42.049642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12311 11:42:42.050320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12313 11:42:42.101419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12314 11:42:42.102150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12316 11:42:42.152465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12317 11:42:42.153362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12319 11:42:42.204164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12320 11:42:42.204845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12322 11:42:42.256208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12323 11:42:42.256894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12325 11:42:42.310690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12326 11:42:42.311421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12328 11:42:42.361954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12329 11:42:42.362235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12331 11:42:42.401746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12332 11:42:42.402543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12334 11:42:42.447003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12335 11:42:42.447760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12337 11:42:42.500865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12338 11:42:42.501200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12340 11:42:42.544838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12341 11:42:42.545209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12343 11:42:42.581995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12344 11:42:42.582300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12346 11:42:42.615694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12347 11:42:42.616009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12349 11:42:42.657505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12350 11:42:42.657850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12352 11:42:42.694225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12353 11:42:42.694550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12355 11:42:42.729165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12356 11:42:42.729502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12358 11:42:42.766690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12359 11:42:42.767001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12361 11:42:42.802875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12362 11:42:42.803220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12364 11:42:42.838011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12365 11:42:42.838407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12367 11:42:42.875038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12368 11:42:42.875483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12370 11:42:42.912070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12371 11:42:42.912393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12373 11:42:42.946744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12374 11:42:42.947117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12376 11:42:42.978126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12377 11:42:42.978516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12379 11:42:43.013243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12380 11:42:43.013599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12382 11:42:43.041403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12383 11:42:43.041758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12385 11:42:43.073759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12387 11:42:43.076605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12388 11:42:43.106812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12389 11:42:43.107199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12391 11:42:43.143525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12392 11:42:43.143895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12394 11:42:43.171914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12395 11:42:43.172298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12397 11:42:43.210382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12398 11:42:43.210753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12400 11:42:43.237660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12401 11:42:43.238003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12403 11:42:43.274198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12404 11:42:43.274573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12406 11:42:43.305516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12407 11:42:43.305882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12409 11:42:43.339012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12410 11:42:43.339385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12412 11:42:43.501280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12413 11:42:43.501669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12415 11:42:43.535821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12416 11:42:43.536177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12418 11:42:43.568968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12419 11:42:43.569322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12421 11:42:43.602962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12422 11:42:43.603356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12424 11:42:43.634219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12426 11:42:43.637415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12427 11:42:43.670915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12428 11:42:43.671257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12430 11:42:43.700777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12432 11:42:43.703672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12433 11:42:43.733893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12434 11:42:43.734281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12436 11:42:43.760047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12438 11:42:43.762770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12439 11:42:43.794295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12440 11:42:43.794705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12442 11:42:43.825300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12443 11:42:43.825691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12445 11:42:43.859329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12446 11:42:43.859744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12448 11:42:43.890369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12449 11:42:43.890741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12451 11:42:43.921068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12452 11:42:43.921411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12454 11:42:43.951866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12456 11:42:43.954345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12457 11:42:43.989674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12458 11:42:43.990054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12460 11:42:44.023608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12461 11:42:44.024019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12463 11:42:44.050028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12464 11:42:44.050413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12466 11:42:44.080266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12468 11:42:44.083265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12469 11:42:44.115276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12471 11:42:44.118049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12472 11:42:44.150634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12473 11:42:44.151047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12475 11:42:44.178475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12476 11:42:44.178817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12478 11:42:44.210267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12479 11:42:44.210625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12481 11:42:44.246765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12482 11:42:44.247177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12484 11:42:44.282977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12485 11:42:44.283402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12487 11:42:44.314599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12488 11:42:44.314999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12490 11:42:44.350210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12491 11:42:44.350605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12493 11:42:44.382695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12494 11:42:44.383075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12496 11:42:44.411420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12497 11:42:44.411808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12499 11:42:44.453132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12500 11:42:44.453542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12502 11:42:45.051837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12503 11:42:45.052239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12505 11:42:45.084338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12506 11:42:45.084724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12508 11:42:45.120489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12509 11:42:45.120875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12511 11:42:45.149477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12512 11:42:45.149846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12514 11:42:45.179916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12515 11:42:45.180093 + set +x
12516 11:42:45.180381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12518 11:42:45.186673 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10742235_1.6.2.3.5>
12519 11:42:45.187009 Received signal: <ENDRUN> 1_kselftest-arm64 10742235_1.6.2.3.5
12520 11:42:45.187094 Ending use of test pattern.
12521 11:42:45.187159 Ending test lava.1_kselftest-arm64 (10742235_1.6.2.3.5), duration 29.88
12523 11:42:45.189884 <LAVA_TEST_RUNNER EXIT>
12524 11:42:45.190192 ok: lava_test_shell seems to have completed
12525 11:42:45.191178 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12526 11:42:45.191342 end: 3.1 lava-test-shell (duration 00:00:31) [common]
12527 11:42:45.191439 end: 3 lava-test-retry (duration 00:00:31) [common]
12528 11:42:45.191529 start: 4 finalize (timeout 00:07:15) [common]
12529 11:42:45.191618 start: 4.1 power-off (timeout 00:00:30) [common]
12530 11:42:45.191775 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
12531 11:42:45.270933 >> Command sent successfully.
12532 11:42:45.274289 Returned 0 in 0 seconds
12533 11:42:45.374775 end: 4.1 power-off (duration 00:00:00) [common]
12535 11:42:45.375178 start: 4.2 read-feedback (timeout 00:07:15) [common]
12536 11:42:45.375446 Listened to connection for namespace 'common' for up to 1s
12537 11:42:46.376372 Finalising connection for namespace 'common'
12538 11:42:46.376572 Disconnecting from shell: Finalise
12539 11:42:46.376688 / #
12540 11:42:46.477100 end: 4.2 read-feedback (duration 00:00:01) [common]
12541 11:42:46.477294 end: 4 finalize (duration 00:00:01) [common]
12542 11:42:46.477426 Cleaning after the job
12543 11:42:46.477536 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/ramdisk
12544 11:42:46.480089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/kernel
12545 11:42:46.492634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/dtb
12546 11:42:46.492948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/nfsrootfs
12547 11:42:46.583573 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742235/tftp-deploy-b86my2hz/modules
12548 11:42:46.590789 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742235
12549 11:42:47.281368 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742235
12550 11:42:47.281645 Job finished correctly