Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 21
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 35
- Errors: 1
1 04:37:21.176788 lava-dispatcher, installed at version: 2023.05.1
2 04:37:21.177010 start: 0 validate
3 04:37:21.177144 Start time: 2023-08-09 04:37:21.177135+00:00 (UTC)
4 04:37:21.177287 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:37:21.177424 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:37:21.445105 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:37:21.445351 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:37:27.233561 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:37:27.234229 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:37:27.506778 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:37:27.507483 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:37:31.276814 validate duration: 10.10
14 04:37:31.277189 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:37:31.277321 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:37:31.277455 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:37:31.277630 Not decompressing ramdisk as can be used compressed.
18 04:37:31.277751 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 04:37:31.277846 saving as /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/ramdisk/rootfs.cpio.gz
20 04:37:31.277946 total size: 34390042 (32MB)
21 04:37:31.279422 progress 0% (0MB)
22 04:37:31.294258 progress 5% (1MB)
23 04:37:31.305387 progress 10% (3MB)
24 04:37:31.314532 progress 15% (4MB)
25 04:37:31.323658 progress 20% (6MB)
26 04:37:31.332944 progress 25% (8MB)
27 04:37:31.342121 progress 30% (9MB)
28 04:37:31.351331 progress 35% (11MB)
29 04:37:31.360400 progress 40% (13MB)
30 04:37:31.369647 progress 45% (14MB)
31 04:37:31.378802 progress 50% (16MB)
32 04:37:31.388065 progress 55% (18MB)
33 04:37:31.397234 progress 60% (19MB)
34 04:37:31.406332 progress 65% (21MB)
35 04:37:31.415447 progress 70% (22MB)
36 04:37:31.424673 progress 75% (24MB)
37 04:37:31.433780 progress 80% (26MB)
38 04:37:31.442998 progress 85% (27MB)
39 04:37:31.451928 progress 90% (29MB)
40 04:37:31.460901 progress 95% (31MB)
41 04:37:31.469770 progress 100% (32MB)
42 04:37:31.469968 32MB downloaded in 0.19s (170.80MB/s)
43 04:37:31.470119 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:37:31.470358 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:37:31.470444 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:37:31.470529 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:37:31.470672 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:37:31.470743 saving as /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/kernel/Image
50 04:37:31.470804 total size: 49220096 (46MB)
51 04:37:31.470863 No compression specified
52 04:37:31.472056 progress 0% (0MB)
53 04:37:31.485258 progress 5% (2MB)
54 04:37:31.500196 progress 10% (4MB)
55 04:37:31.514160 progress 15% (7MB)
56 04:37:31.528133 progress 20% (9MB)
57 04:37:31.542576 progress 25% (11MB)
58 04:37:31.556511 progress 30% (14MB)
59 04:37:31.569604 progress 35% (16MB)
60 04:37:31.583316 progress 40% (18MB)
61 04:37:31.597252 progress 45% (21MB)
62 04:37:31.610396 progress 50% (23MB)
63 04:37:31.623509 progress 55% (25MB)
64 04:37:31.636497 progress 60% (28MB)
65 04:37:31.649543 progress 65% (30MB)
66 04:37:31.662504 progress 70% (32MB)
67 04:37:31.675651 progress 75% (35MB)
68 04:37:31.689431 progress 80% (37MB)
69 04:37:31.702895 progress 85% (39MB)
70 04:37:31.716467 progress 90% (42MB)
71 04:37:31.730425 progress 95% (44MB)
72 04:37:31.744256 progress 100% (46MB)
73 04:37:31.744461 46MB downloaded in 0.27s (171.53MB/s)
74 04:37:31.744678 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:37:31.745053 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:37:31.745174 start: 1.3 download-retry (timeout 00:10:00) [common]
78 04:37:31.745285 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 04:37:31.745439 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:37:31.745511 saving as /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/dtb/mt8192-asurada-spherion-r0.dtb
81 04:37:31.745574 total size: 47278 (0MB)
82 04:37:31.745636 No compression specified
83 04:37:31.746864 progress 69% (0MB)
84 04:37:31.747145 progress 100% (0MB)
85 04:37:31.747305 0MB downloaded in 0.00s (26.09MB/s)
86 04:37:31.747428 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:37:31.747737 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:37:31.747827 start: 1.4 download-retry (timeout 00:10:00) [common]
90 04:37:31.747912 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 04:37:31.748044 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:37:31.748137 saving as /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/modules/modules.tar
93 04:37:31.748208 total size: 8557308 (8MB)
94 04:37:31.748271 Using unxz to decompress xz
95 04:37:31.753003 progress 0% (0MB)
96 04:37:31.775587 progress 5% (0MB)
97 04:37:31.799097 progress 10% (0MB)
98 04:37:31.827794 progress 15% (1MB)
99 04:37:31.855085 progress 20% (1MB)
100 04:37:31.883458 progress 25% (2MB)
101 04:37:31.912399 progress 30% (2MB)
102 04:37:31.940092 progress 35% (2MB)
103 04:37:31.967035 progress 40% (3MB)
104 04:37:31.995737 progress 45% (3MB)
105 04:37:32.028269 progress 50% (4MB)
106 04:37:32.059129 progress 55% (4MB)
107 04:37:32.084522 progress 60% (4MB)
108 04:37:32.107856 progress 65% (5MB)
109 04:37:32.133518 progress 70% (5MB)
110 04:37:32.158720 progress 75% (6MB)
111 04:37:32.185698 progress 80% (6MB)
112 04:37:32.216278 progress 85% (6MB)
113 04:37:32.245330 progress 90% (7MB)
114 04:37:32.270349 progress 95% (7MB)
115 04:37:32.294432 progress 100% (8MB)
116 04:37:32.299313 8MB downloaded in 0.55s (14.81MB/s)
117 04:37:32.299699 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:37:32.299981 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:37:32.300083 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:37:32.300178 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:37:32.300299 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:37:32.300384 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:37:32.300619 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6
125 04:37:32.300758 makedir: /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin
126 04:37:32.300864 makedir: /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/tests
127 04:37:32.300965 makedir: /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/results
128 04:37:32.301078 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-add-keys
129 04:37:32.301225 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-add-sources
130 04:37:32.301357 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-background-process-start
131 04:37:32.301490 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-background-process-stop
132 04:37:32.301620 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-common-functions
133 04:37:32.301743 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-echo-ipv4
134 04:37:32.301934 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-install-packages
135 04:37:32.302058 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-installed-packages
136 04:37:32.302181 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-os-build
137 04:37:32.302337 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-probe-channel
138 04:37:32.302461 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-probe-ip
139 04:37:32.302595 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-target-ip
140 04:37:32.302786 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-target-mac
141 04:37:32.302974 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-target-storage
142 04:37:32.303136 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-test-case
143 04:37:32.303262 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-test-event
144 04:37:32.303387 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-test-feedback
145 04:37:32.303512 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-test-raise
146 04:37:32.303680 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-test-reference
147 04:37:32.303807 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-test-runner
148 04:37:32.303931 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-test-set
149 04:37:32.304058 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-test-shell
150 04:37:32.304196 Updating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-install-packages (oe)
151 04:37:32.304378 Updating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/bin/lava-installed-packages (oe)
152 04:37:32.304501 Creating /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/environment
153 04:37:32.304601 LAVA metadata
154 04:37:32.304674 - LAVA_JOB_ID=11241309
155 04:37:32.304739 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:37:32.304846 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:37:32.304912 skipped lava-vland-overlay
158 04:37:32.304987 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:37:32.305068 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:37:32.305129 skipped lava-multinode-overlay
161 04:37:32.305204 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:37:32.305294 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:37:32.305372 Loading test definitions
164 04:37:32.305463 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 04:37:32.305535 Using /lava-11241309 at stage 0
166 04:37:32.305926 uuid=11241309_1.5.2.3.1 testdef=None
167 04:37:32.306057 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 04:37:32.306142 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 04:37:32.306740 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 04:37:32.306956 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 04:37:32.307605 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 04:37:32.307832 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 04:37:32.308431 runner path: /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/0/tests/0_cros-ec test_uuid 11241309_1.5.2.3.1
176 04:37:32.308584 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 04:37:32.308791 Creating lava-test-runner.conf files
179 04:37:32.308853 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11241309/lava-overlay-ahzp_lz6/lava-11241309/0 for stage 0
180 04:37:32.308941 - 0_cros-ec
181 04:37:32.309037 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 04:37:32.309119 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 04:37:32.316098 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 04:37:32.316214 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 04:37:32.316314 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 04:37:32.316413 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 04:37:32.316506 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 04:37:33.348278 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 04:37:33.348656 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 04:37:33.348785 extracting modules file /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11241309/extract-overlay-ramdisk-qd8o1dym/ramdisk
191 04:37:33.578903 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 04:37:33.579057 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 04:37:33.579158 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11241309/compress-overlay-ngy0614p/overlay-1.5.2.4.tar.gz to ramdisk
194 04:37:33.579233 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11241309/compress-overlay-ngy0614p/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11241309/extract-overlay-ramdisk-qd8o1dym/ramdisk
195 04:37:33.586079 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 04:37:33.586196 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 04:37:33.586286 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 04:37:33.586373 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 04:37:33.586452 Building ramdisk /var/lib/lava/dispatcher/tmp/11241309/extract-overlay-ramdisk-qd8o1dym/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11241309/extract-overlay-ramdisk-qd8o1dym/ramdisk
200 04:37:34.305261 >> 269660 blocks
201 04:37:39.331227 rename /var/lib/lava/dispatcher/tmp/11241309/extract-overlay-ramdisk-qd8o1dym/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/ramdisk/ramdisk.cpio.gz
202 04:37:39.331744 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 04:37:39.331952 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 04:37:39.332091 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 04:37:39.332218 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/kernel/Image'
206 04:37:53.591253 Returned 0 in 14 seconds
207 04:37:53.691934 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/kernel/image.itb
208 04:37:54.390638 output: FIT description: Kernel Image image with one or more FDT blobs
209 04:37:54.391024 output: Created: Wed Aug 9 05:37:54 2023
210 04:37:54.391132 output: Image 0 (kernel-1)
211 04:37:54.391223 output: Description:
212 04:37:54.391308 output: Created: Wed Aug 9 05:37:54 2023
213 04:37:54.391413 output: Type: Kernel Image
214 04:37:54.391528 output: Compression: lzma compressed
215 04:37:54.391610 output: Data Size: 11036366 Bytes = 10777.70 KiB = 10.53 MiB
216 04:37:54.391717 output: Architecture: AArch64
217 04:37:54.391818 output: OS: Linux
218 04:37:54.391924 output: Load Address: 0x00000000
219 04:37:54.392024 output: Entry Point: 0x00000000
220 04:37:54.392124 output: Hash algo: crc32
221 04:37:54.392221 output: Hash value: 9e750869
222 04:37:54.392315 output: Image 1 (fdt-1)
223 04:37:54.392414 output: Description: mt8192-asurada-spherion-r0
224 04:37:54.392511 output: Created: Wed Aug 9 05:37:54 2023
225 04:37:54.392608 output: Type: Flat Device Tree
226 04:37:54.392702 output: Compression: uncompressed
227 04:37:54.392795 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 04:37:54.392898 output: Architecture: AArch64
229 04:37:54.392992 output: Hash algo: crc32
230 04:37:54.393090 output: Hash value: cc4352de
231 04:37:54.393184 output: Image 2 (ramdisk-1)
232 04:37:54.393280 output: Description: unavailable
233 04:37:54.393379 output: Created: Wed Aug 9 05:37:54 2023
234 04:37:54.393474 output: Type: RAMDisk Image
235 04:37:54.393573 output: Compression: Unknown Compression
236 04:37:54.393666 output: Data Size: 47409225 Bytes = 46298.07 KiB = 45.21 MiB
237 04:37:54.393763 output: Architecture: AArch64
238 04:37:54.393858 output: OS: Linux
239 04:37:54.393954 output: Load Address: unavailable
240 04:37:54.394048 output: Entry Point: unavailable
241 04:37:54.394141 output: Hash algo: crc32
242 04:37:54.394237 output: Hash value: 7b2dc517
243 04:37:54.394332 output: Default Configuration: 'conf-1'
244 04:37:54.394424 output: Configuration 0 (conf-1)
245 04:37:54.394521 output: Description: mt8192-asurada-spherion-r0
246 04:37:54.394613 output: Kernel: kernel-1
247 04:37:54.394709 output: Init Ramdisk: ramdisk-1
248 04:37:54.394804 output: FDT: fdt-1
249 04:37:54.394899 output: Loadables: kernel-1
250 04:37:54.394992 output:
251 04:37:54.395260 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 04:37:54.395412 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 04:37:54.395576 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 04:37:54.395722 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 04:37:54.395817 No LXC device requested
256 04:37:54.395949 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 04:37:54.396088 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 04:37:54.396209 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 04:37:54.396317 Checking files for TFTP limit of 4294967296 bytes.
260 04:37:54.397017 end: 1 tftp-deploy (duration 00:00:23) [common]
261 04:37:54.397161 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 04:37:54.397297 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 04:37:54.397482 substitutions:
264 04:37:54.397585 - {DTB}: 11241309/tftp-deploy-z0d2ds2g/dtb/mt8192-asurada-spherion-r0.dtb
265 04:37:54.397691 - {INITRD}: 11241309/tftp-deploy-z0d2ds2g/ramdisk/ramdisk.cpio.gz
266 04:37:54.397792 - {KERNEL}: 11241309/tftp-deploy-z0d2ds2g/kernel/Image
267 04:37:54.397890 - {LAVA_MAC}: None
268 04:37:54.397994 - {PRESEED_CONFIG}: None
269 04:37:54.398091 - {PRESEED_LOCAL}: None
270 04:37:54.398187 - {RAMDISK}: 11241309/tftp-deploy-z0d2ds2g/ramdisk/ramdisk.cpio.gz
271 04:37:54.398287 - {ROOT_PART}: None
272 04:37:54.398382 - {ROOT}: None
273 04:37:54.398480 - {SERVER_IP}: 192.168.201.1
274 04:37:54.398577 - {TEE}: None
275 04:37:54.398672 Parsed boot commands:
276 04:37:54.398770 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 04:37:54.399010 Parsed boot commands: tftpboot 192.168.201.1 11241309/tftp-deploy-z0d2ds2g/kernel/image.itb 11241309/tftp-deploy-z0d2ds2g/kernel/cmdline
278 04:37:54.399146 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 04:37:54.399277 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 04:37:54.399421 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 04:37:54.399558 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 04:37:54.399673 Not connected, no need to disconnect.
283 04:37:54.399795 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 04:37:54.399922 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 04:37:54.400029 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 04:37:54.404318 Setting prompt string to ['lava-test: # ']
287 04:37:54.404749 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 04:37:54.404880 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 04:37:54.405001 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 04:37:54.405150 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 04:37:54.405506 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 04:37:59.548162 >> Command sent successfully.
293 04:37:59.551474 Returned 0 in 5 seconds
294 04:37:59.651905 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 04:37:59.652676 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 04:37:59.652819 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 04:37:59.652949 Setting prompt string to 'Starting depthcharge on Spherion...'
299 04:37:59.653048 Changing prompt to 'Starting depthcharge on Spherion...'
300 04:37:59.653152 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 04:37:59.653554 [Enter `^Ec?' for help]
302 04:37:59.824907
303 04:37:59.825095
304 04:37:59.825212 F0: 102B 0000
305 04:37:59.825307
306 04:37:59.825400 F3: 1001 0000 [0200]
307 04:37:59.825489
308 04:37:59.828588 F3: 1001 0000
309 04:37:59.828712
310 04:37:59.828810 F7: 102D 0000
311 04:37:59.828901
312 04:37:59.828991 F1: 0000 0000
313 04:37:59.829098
314 04:37:59.832680 V0: 0000 0000 [0001]
315 04:37:59.832806
316 04:37:59.832915 00: 0007 8000
317 04:37:59.833014
318 04:37:59.836017 01: 0000 0000
319 04:37:59.836122
320 04:37:59.836230 BP: 0C00 0209 [0000]
321 04:37:59.836332
322 04:37:59.836399 G0: 1182 0000
323 04:37:59.836461
324 04:37:59.840137 EC: 0000 0021 [4000]
325 04:37:59.840222
326 04:37:59.840288 S7: 0000 0000 [0000]
327 04:37:59.840350
328 04:37:59.843501 CC: 0000 0000 [0001]
329 04:37:59.843625
330 04:37:59.843696 T0: 0000 0040 [010F]
331 04:37:59.843760
332 04:37:59.846755 Jump to BL
333 04:37:59.846863
334 04:37:59.871294
335 04:37:59.871441
336 04:37:59.871564
337 04:37:59.877933 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 04:37:59.881934 ARM64: Exception handlers installed.
339 04:37:59.885153 ARM64: Testing exception
340 04:37:59.889407 ARM64: Done test exception
341 04:37:59.896606 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 04:37:59.903629 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 04:37:59.911448 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 04:37:59.922048 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 04:37:59.928253 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 04:37:59.938733 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 04:37:59.948992 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 04:37:59.956227 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 04:37:59.974042 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 04:37:59.977433 WDT: Last reset was cold boot
351 04:37:59.980549 SPI1(PAD0) initialized at 2873684 Hz
352 04:37:59.984202 SPI5(PAD0) initialized at 992727 Hz
353 04:37:59.987371 VBOOT: Loading verstage.
354 04:37:59.993975 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 04:37:59.997228 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 04:38:00.000470 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 04:38:00.003757 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 04:38:00.011487 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 04:38:00.018102 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 04:38:00.028691 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 04:38:00.028802
362 04:38:00.028871
363 04:38:00.039969 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 04:38:00.043404 ARM64: Exception handlers installed.
365 04:38:00.043498 ARM64: Testing exception
366 04:38:00.046821 ARM64: Done test exception
367 04:38:00.050014 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 04:38:00.056304 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 04:38:00.070286 Probing TPM: . done!
370 04:38:00.070429 TPM ready after 0 ms
371 04:38:00.077935 Connected to device vid:did:rid of 1ae0:0028:00
372 04:38:00.085005 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 04:38:00.145736 Initialized TPM device CR50 revision 0
374 04:38:00.155803 tlcl_send_startup: Startup return code is 0
375 04:38:00.155957 TPM: setup succeeded
376 04:38:00.166727 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 04:38:00.175330 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 04:38:00.189780 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 04:38:00.196979 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 04:38:00.200086 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 04:38:00.204383 in-header: 03 07 00 00 08 00 00 00
382 04:38:00.207684 in-data: aa e4 47 04 13 02 00 00
383 04:38:00.211097 Chrome EC: UHEPI supported
384 04:38:00.218759 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 04:38:00.222080 in-header: 03 95 00 00 08 00 00 00
386 04:38:00.226006 in-data: 18 20 20 08 00 00 00 00
387 04:38:00.226125 Phase 1
388 04:38:00.229597 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 04:38:00.236748 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 04:38:00.240687 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 04:38:00.244719 Recovery requested (1009000e)
392 04:38:00.252968 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 04:38:00.257713 tlcl_extend: response is 0
394 04:38:00.267349 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 04:38:00.273155 tlcl_extend: response is 0
396 04:38:00.280449 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 04:38:00.299913 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 04:38:00.306743 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 04:38:00.306870
400 04:38:00.306943
401 04:38:00.316582 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 04:38:00.319983 ARM64: Exception handlers installed.
403 04:38:00.323108 ARM64: Testing exception
404 04:38:00.323233 ARM64: Done test exception
405 04:38:00.345161 pmic_efuse_setting: Set efuses in 11 msecs
406 04:38:00.348922 pmwrap_interface_init: Select PMIF_VLD_RDY
407 04:38:00.355279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 04:38:00.358727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 04:38:00.366531 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 04:38:00.369907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 04:38:00.374002 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 04:38:00.377207 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 04:38:00.384473 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 04:38:00.387691 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 04:38:00.391614 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 04:38:00.398735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 04:38:00.402619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 04:38:00.406555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 04:38:00.409867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 04:38:00.417967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 04:38:00.425542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 04:38:00.429081 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 04:38:00.436238 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 04:38:00.440138 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 04:38:00.447306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 04:38:00.450950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 04:38:00.458398 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 04:38:00.462051 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 04:38:00.469461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 04:38:00.472998 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 04:38:00.481000 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 04:38:00.484756 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 04:38:00.489026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 04:38:00.496077 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 04:38:00.499381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 04:38:00.503282 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 04:38:00.510734 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 04:38:00.514076 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 04:38:00.521670 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 04:38:00.524705 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 04:38:00.528752 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 04:38:00.536419 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 04:38:00.540267 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 04:38:00.544239 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 04:38:00.547833 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 04:38:00.554711 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 04:38:00.558531 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 04:38:00.562162 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 04:38:00.566081 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 04:38:00.569982 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 04:38:00.573795 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 04:38:00.581241 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 04:38:00.584550 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 04:38:00.588467 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 04:38:00.591771 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 04:38:00.595767 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 04:38:00.599451 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 04:38:00.610643 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 04:38:00.618111 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 04:38:00.622129 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 04:38:00.628527 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 04:38:00.639864 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 04:38:00.643828 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 04:38:00.647738 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 04:38:00.650975 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 04:38:00.659113 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xb
467 04:38:00.662333 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 04:38:00.669910 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 04:38:00.673583 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 04:38:00.683475 [RTC]rtc_get_frequency_meter,154: input=15, output=761
471 04:38:00.692562 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 04:38:00.701857 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 04:38:00.711871 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 04:38:00.720993 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 04:38:00.730847 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 04:38:00.740286 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 04:38:00.744302 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 04:38:00.748012 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 04:38:00.754847 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 04:38:00.758751 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 04:38:00.762655 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 04:38:00.766287 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 04:38:00.770018 ADC[4]: Raw value=906203 ID=7
484 04:38:00.774039 ADC[3]: Raw value=213441 ID=1
485 04:38:00.774157 RAM Code: 0x71
486 04:38:00.777028 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 04:38:00.781704 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 04:38:00.792007 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 04:38:00.799375 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 04:38:00.799489 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 04:38:00.805266 in-header: 03 07 00 00 08 00 00 00
492 04:38:00.809001 in-data: aa e4 47 04 13 02 00 00
493 04:38:00.813016 Chrome EC: UHEPI supported
494 04:38:00.816746 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 04:38:00.820895 in-header: 03 95 00 00 08 00 00 00
496 04:38:00.824160 in-data: 18 20 20 08 00 00 00 00
497 04:38:00.828046 MRC: failed to locate region type 0.
498 04:38:00.835711 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 04:38:00.839638 DRAM-K: Running full calibration
500 04:38:00.843615 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 04:38:00.847440 header.status = 0x0
502 04:38:00.851184 header.version = 0x6 (expected: 0x6)
503 04:38:00.851272 header.size = 0xd00 (expected: 0xd00)
504 04:38:00.854366 header.flags = 0x0
505 04:38:00.861296 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 04:38:00.878781 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 04:38:00.886359 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 04:38:00.889528 dram_init: ddr_geometry: 2
509 04:38:00.889646 [EMI] MDL number = 2
510 04:38:00.893524 [EMI] Get MDL freq = 0
511 04:38:00.893630 dram_init: ddr_type: 0
512 04:38:00.897441 is_discrete_lpddr4: 1
513 04:38:00.901240 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 04:38:00.901329
515 04:38:00.901396
516 04:38:00.901465 [Bian_co] ETT version 0.0.0.1
517 04:38:00.908670 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 04:38:00.908758
519 04:38:00.912219 dramc_set_vcore_voltage set vcore to 650000
520 04:38:00.912323 Read voltage for 800, 4
521 04:38:00.912392 Vio18 = 0
522 04:38:00.916134 Vcore = 650000
523 04:38:00.916221 Vdram = 0
524 04:38:00.916289 Vddq = 0
525 04:38:00.919853 Vmddr = 0
526 04:38:00.919939 dram_init: config_dvfs: 1
527 04:38:00.927726 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 04:38:00.930691 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 04:38:00.934564 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 04:38:00.938213 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 04:38:00.941949 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 04:38:00.945161 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 04:38:00.948890 MEM_TYPE=3, freq_sel=18
534 04:38:00.952038 sv_algorithm_assistance_LP4_1600
535 04:38:00.955129 ============ PULL DRAM RESETB DOWN ============
536 04:38:00.958966 ========== PULL DRAM RESETB DOWN end =========
537 04:38:00.966261 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 04:38:00.966349 ===================================
539 04:38:00.969858 LPDDR4 DRAM CONFIGURATION
540 04:38:00.973542 ===================================
541 04:38:00.973635 EX_ROW_EN[0] = 0x0
542 04:38:00.977293 EX_ROW_EN[1] = 0x0
543 04:38:00.980582 LP4Y_EN = 0x0
544 04:38:00.980674 WORK_FSP = 0x0
545 04:38:00.980767 WL = 0x2
546 04:38:00.984559 RL = 0x2
547 04:38:00.984649 BL = 0x2
548 04:38:00.987591 RPST = 0x0
549 04:38:00.987673 RD_PRE = 0x0
550 04:38:00.991320 WR_PRE = 0x1
551 04:38:00.991419 WR_PST = 0x0
552 04:38:00.994260 DBI_WR = 0x0
553 04:38:00.998048 DBI_RD = 0x0
554 04:38:00.998117 OTF = 0x1
555 04:38:01.001238 ===================================
556 04:38:01.004574 ===================================
557 04:38:01.004644 ANA top config
558 04:38:01.008242 ===================================
559 04:38:01.012021 DLL_ASYNC_EN = 0
560 04:38:01.015666 ALL_SLAVE_EN = 1
561 04:38:01.015745 NEW_RANK_MODE = 1
562 04:38:01.019280 DLL_IDLE_MODE = 1
563 04:38:01.022054 LP45_APHY_COMB_EN = 1
564 04:38:01.025942 TX_ODT_DIS = 1
565 04:38:01.026018 NEW_8X_MODE = 1
566 04:38:01.029614 ===================================
567 04:38:01.033461 ===================================
568 04:38:01.036534 data_rate = 1600
569 04:38:01.039911 CKR = 1
570 04:38:01.043456 DQ_P2S_RATIO = 8
571 04:38:01.047028 ===================================
572 04:38:01.047107 CA_P2S_RATIO = 8
573 04:38:01.050059 DQ_CA_OPEN = 0
574 04:38:01.053208 DQ_SEMI_OPEN = 0
575 04:38:01.057009 CA_SEMI_OPEN = 0
576 04:38:01.060140 CA_FULL_RATE = 0
577 04:38:01.063216 DQ_CKDIV4_EN = 1
578 04:38:01.063283 CA_CKDIV4_EN = 1
579 04:38:01.066903 CA_PREDIV_EN = 0
580 04:38:01.070058 PH8_DLY = 0
581 04:38:01.073241 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 04:38:01.076863 DQ_AAMCK_DIV = 4
583 04:38:01.080712 CA_AAMCK_DIV = 4
584 04:38:01.080780 CA_ADMCK_DIV = 4
585 04:38:01.083636 DQ_TRACK_CA_EN = 0
586 04:38:01.087032 CA_PICK = 800
587 04:38:01.090321 CA_MCKIO = 800
588 04:38:01.094020 MCKIO_SEMI = 0
589 04:38:01.098361 PLL_FREQ = 3068
590 04:38:01.098434 DQ_UI_PI_RATIO = 32
591 04:38:01.101870 CA_UI_PI_RATIO = 0
592 04:38:01.105583 ===================================
593 04:38:01.110158 ===================================
594 04:38:01.110232 memory_type:LPDDR4
595 04:38:01.113074 GP_NUM : 10
596 04:38:01.113234 SRAM_EN : 1
597 04:38:01.116899 MD32_EN : 0
598 04:38:01.120790 ===================================
599 04:38:01.120880 [ANA_INIT] >>>>>>>>>>>>>>
600 04:38:01.124599 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 04:38:01.128794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 04:38:01.131732 ===================================
603 04:38:01.135431 data_rate = 1600,PCW = 0X7600
604 04:38:01.138382 ===================================
605 04:38:01.142096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 04:38:01.145215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 04:38:01.151916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 04:38:01.154888 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 04:38:01.162145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 04:38:01.165269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 04:38:01.165358 [ANA_INIT] flow start
612 04:38:01.168340 [ANA_INIT] PLL >>>>>>>>
613 04:38:01.168423 [ANA_INIT] PLL <<<<<<<<
614 04:38:01.172002 [ANA_INIT] MIDPI >>>>>>>>
615 04:38:01.175255 [ANA_INIT] MIDPI <<<<<<<<
616 04:38:01.178442 [ANA_INIT] DLL >>>>>>>>
617 04:38:01.178525 [ANA_INIT] flow end
618 04:38:01.182206 ============ LP4 DIFF to SE enter ============
619 04:38:01.188554 ============ LP4 DIFF to SE exit ============
620 04:38:01.188638 [ANA_INIT] <<<<<<<<<<<<<
621 04:38:01.191842 [Flow] Enable top DCM control >>>>>
622 04:38:01.195072 [Flow] Enable top DCM control <<<<<
623 04:38:01.198574 Enable DLL master slave shuffle
624 04:38:01.205284 ==============================================================
625 04:38:01.205394 Gating Mode config
626 04:38:01.212257 ==============================================================
627 04:38:01.215370 Config description:
628 04:38:01.225449 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 04:38:01.231921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 04:38:01.235243 SELPH_MODE 0: By rank 1: By Phase
631 04:38:01.241782 ==============================================================
632 04:38:01.241868 GAT_TRACK_EN = 1
633 04:38:01.245671 RX_GATING_MODE = 2
634 04:38:01.249031 RX_GATING_TRACK_MODE = 2
635 04:38:01.252294 SELPH_MODE = 1
636 04:38:01.255436 PICG_EARLY_EN = 1
637 04:38:01.258543 VALID_LAT_VALUE = 1
638 04:38:01.265597 ==============================================================
639 04:38:01.268841 Enter into Gating configuration >>>>
640 04:38:01.271999 Exit from Gating configuration <<<<
641 04:38:01.275235 Enter into DVFS_PRE_config >>>>>
642 04:38:01.285444 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 04:38:01.288596 Exit from DVFS_PRE_config <<<<<
644 04:38:01.292491 Enter into PICG configuration >>>>
645 04:38:01.295871 Exit from PICG configuration <<<<
646 04:38:01.295959 [RX_INPUT] configuration >>>>>
647 04:38:01.299234 [RX_INPUT] configuration <<<<<
648 04:38:01.305450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 04:38:01.308654 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 04:38:01.315657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 04:38:01.322572 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 04:38:01.328834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 04:38:01.335825 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 04:38:01.338705 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 04:38:01.342335 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 04:38:01.349178 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 04:38:01.352317 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 04:38:01.355735 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 04:38:01.359301 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 04:38:01.362361 ===================================
661 04:38:01.365886 LPDDR4 DRAM CONFIGURATION
662 04:38:01.368889 ===================================
663 04:38:01.372689 EX_ROW_EN[0] = 0x0
664 04:38:01.372776 EX_ROW_EN[1] = 0x0
665 04:38:01.375670 LP4Y_EN = 0x0
666 04:38:01.375755 WORK_FSP = 0x0
667 04:38:01.378830 WL = 0x2
668 04:38:01.378914 RL = 0x2
669 04:38:01.382589 BL = 0x2
670 04:38:01.382673 RPST = 0x0
671 04:38:01.385773 RD_PRE = 0x0
672 04:38:01.385857 WR_PRE = 0x1
673 04:38:01.389176 WR_PST = 0x0
674 04:38:01.389259 DBI_WR = 0x0
675 04:38:01.392507 DBI_RD = 0x0
676 04:38:01.392625 OTF = 0x1
677 04:38:01.395728 ===================================
678 04:38:01.402579 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 04:38:01.405725 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 04:38:01.409187 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 04:38:01.412442 ===================================
682 04:38:01.416092 LPDDR4 DRAM CONFIGURATION
683 04:38:01.419094 ===================================
684 04:38:01.419185 EX_ROW_EN[0] = 0x10
685 04:38:01.422900 EX_ROW_EN[1] = 0x0
686 04:38:01.426150 LP4Y_EN = 0x0
687 04:38:01.426239 WORK_FSP = 0x0
688 04:38:01.429235 WL = 0x2
689 04:38:01.429321 RL = 0x2
690 04:38:01.432418 BL = 0x2
691 04:38:01.432570 RPST = 0x0
692 04:38:01.436037 RD_PRE = 0x0
693 04:38:01.436122 WR_PRE = 0x1
694 04:38:01.439341 WR_PST = 0x0
695 04:38:01.439426 DBI_WR = 0x0
696 04:38:01.442258 DBI_RD = 0x0
697 04:38:01.442344 OTF = 0x1
698 04:38:01.445699 ===================================
699 04:38:01.452624 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 04:38:01.456714 nWR fixed to 40
701 04:38:01.459829 [ModeRegInit_LP4] CH0 RK0
702 04:38:01.459919 [ModeRegInit_LP4] CH0 RK1
703 04:38:01.463714 [ModeRegInit_LP4] CH1 RK0
704 04:38:01.466444 [ModeRegInit_LP4] CH1 RK1
705 04:38:01.466558 match AC timing 13
706 04:38:01.473060 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 04:38:01.476745 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 04:38:01.479808 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 04:38:01.486759 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 04:38:01.490145 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 04:38:01.490263 [EMI DOE] emi_dcm 0
712 04:38:01.496911 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 04:38:01.497024 ==
714 04:38:01.499791 Dram Type= 6, Freq= 0, CH_0, rank 0
715 04:38:01.503785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 04:38:01.503905 ==
717 04:38:01.510466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 04:38:01.513500 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 04:38:01.523898 [CA 0] Center 36 (6~67) winsize 62
720 04:38:01.527664 [CA 1] Center 36 (6~67) winsize 62
721 04:38:01.530924 [CA 2] Center 34 (4~65) winsize 62
722 04:38:01.533933 [CA 3] Center 33 (3~64) winsize 62
723 04:38:01.537600 [CA 4] Center 32 (2~63) winsize 62
724 04:38:01.540794 [CA 5] Center 32 (2~62) winsize 61
725 04:38:01.540965
726 04:38:01.544453 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 04:38:01.544611
728 04:38:01.547588 [CATrainingPosCal] consider 1 rank data
729 04:38:01.551059 u2DelayCellTimex100 = 270/100 ps
730 04:38:01.554162 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 04:38:01.557712 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 04:38:01.561253 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 04:38:01.567764 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 04:38:01.570770 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
735 04:38:01.574217 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 04:38:01.574330
737 04:38:01.577806 CA PerBit enable=1, Macro0, CA PI delay=32
738 04:38:01.577916
739 04:38:01.581098 [CBTSetCACLKResult] CA Dly = 32
740 04:38:01.581214 CS Dly: 4 (0~35)
741 04:38:01.581313 ==
742 04:38:01.584065 Dram Type= 6, Freq= 0, CH_0, rank 1
743 04:38:01.590858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 04:38:01.590980 ==
745 04:38:01.594132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 04:38:01.601209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 04:38:01.609990 [CA 0] Center 36 (6~67) winsize 62
748 04:38:01.613706 [CA 1] Center 36 (6~67) winsize 62
749 04:38:01.616743 [CA 2] Center 34 (3~65) winsize 63
750 04:38:01.620422 [CA 3] Center 34 (3~65) winsize 63
751 04:38:01.623596 [CA 4] Center 33 (3~63) winsize 61
752 04:38:01.626710 [CA 5] Center 32 (2~63) winsize 62
753 04:38:01.626828
754 04:38:01.630421 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 04:38:01.630530
756 04:38:01.633555 [CATrainingPosCal] consider 2 rank data
757 04:38:01.636755 u2DelayCellTimex100 = 270/100 ps
758 04:38:01.640284 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 04:38:01.643465 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 04:38:01.650340 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 04:38:01.653410 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 04:38:01.657264 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 04:38:01.660393 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 04:38:01.660510
765 04:38:01.663406 CA PerBit enable=1, Macro0, CA PI delay=32
766 04:38:01.663514
767 04:38:01.667158 [CBTSetCACLKResult] CA Dly = 32
768 04:38:01.667265 CS Dly: 5 (0~37)
769 04:38:01.667380
770 04:38:01.670227 ----->DramcWriteLeveling(PI) begin...
771 04:38:01.670339 ==
772 04:38:01.674353 Dram Type= 6, Freq= 0, CH_0, rank 0
773 04:38:01.677800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 04:38:01.677934 ==
775 04:38:01.682052 Write leveling (Byte 0): 31 => 31
776 04:38:01.685739 Write leveling (Byte 1): 33 => 33
777 04:38:01.689049 DramcWriteLeveling(PI) end<-----
778 04:38:01.689171
779 04:38:01.689268 ==
780 04:38:01.692561 Dram Type= 6, Freq= 0, CH_0, rank 0
781 04:38:01.695593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 04:38:01.695680 ==
783 04:38:01.699213 [Gating] SW mode calibration
784 04:38:01.705904 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 04:38:01.712599 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 04:38:01.716281 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 04:38:01.719282 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 04:38:01.725977 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 04:38:01.729503 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 04:38:01.732535 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 04:38:01.739279 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 04:38:01.742785 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 04:38:01.746358 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 04:38:01.752518 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 04:38:01.756169 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 04:38:01.759658 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 04:38:01.762636 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 04:38:01.769762 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 04:38:01.773060 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 04:38:01.776477 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 04:38:01.783058 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 04:38:01.786230 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 04:38:01.789810 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 04:38:01.796211 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 04:38:01.799674 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 04:38:01.803199 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:38:01.809954 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:38:01.813216 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 04:38:01.816378 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 04:38:01.822901 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 04:38:01.826430 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 04:38:01.829490 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
813 04:38:01.833089 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 04:38:01.839692 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 04:38:01.843508 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 04:38:01.846450 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 04:38:01.853238 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 04:38:01.856832 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 04:38:01.859855 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
820 04:38:01.866892 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
821 04:38:01.869745 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:38:01.873271 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:38:01.880054 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:38:01.883285 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 04:38:01.886805 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 04:38:01.890439 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 04:38:01.897146 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 04:38:01.900402 0 11 8 | B1->B0 | 3131 4343 | 0 0 | (0 0) (0 0)
829 04:38:01.903406 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
830 04:38:01.910251 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 04:38:01.913779 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 04:38:01.917203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 04:38:01.923912 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 04:38:01.927050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 04:38:01.930662 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 04:38:01.937097 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 04:38:01.940143 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 04:38:01.943914 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 04:38:01.950507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 04:38:01.953478 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 04:38:01.957249 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 04:38:01.963932 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 04:38:01.967260 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 04:38:01.970253 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 04:38:01.977110 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 04:38:01.980132 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 04:38:01.983826 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 04:38:01.986984 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 04:38:01.993765 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 04:38:01.996962 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 04:38:02.000022 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 04:38:02.006751 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 04:38:02.010388 Total UI for P1: 0, mck2ui 16
854 04:38:02.013624 best dqsien dly found for B0: ( 0, 14, 4)
855 04:38:02.017275 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 04:38:02.020263 Total UI for P1: 0, mck2ui 16
857 04:38:02.023374 best dqsien dly found for B1: ( 0, 14, 8)
858 04:38:02.026970 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 04:38:02.031043 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 04:38:02.031114
861 04:38:02.034623 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 04:38:02.037918 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 04:38:02.040804 [Gating] SW calibration Done
864 04:38:02.040887 ==
865 04:38:02.044178 Dram Type= 6, Freq= 0, CH_0, rank 0
866 04:38:02.048014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 04:38:02.048099 ==
868 04:38:02.051005 RX Vref Scan: 0
869 04:38:02.051087
870 04:38:02.051153 RX Vref 0 -> 0, step: 1
871 04:38:02.051214
872 04:38:02.054707 RX Delay -130 -> 252, step: 16
873 04:38:02.061381 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 04:38:02.064339 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 04:38:02.067937 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
876 04:38:02.071009 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 04:38:02.074500 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 04:38:02.077585 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 04:38:02.084439 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 04:38:02.087389 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 04:38:02.091165 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 04:38:02.094536 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 04:38:02.097540 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 04:38:02.104411 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 04:38:02.108064 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 04:38:02.111036 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 04:38:02.114752 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 04:38:02.121252 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 04:38:02.121344 ==
890 04:38:02.124299 Dram Type= 6, Freq= 0, CH_0, rank 0
891 04:38:02.127762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 04:38:02.127845 ==
893 04:38:02.127911 DQS Delay:
894 04:38:02.131249 DQS0 = 0, DQS1 = 0
895 04:38:02.131367 DQM Delay:
896 04:38:02.134261 DQM0 = 93, DQM1 = 84
897 04:38:02.134343 DQ Delay:
898 04:38:02.138034 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 04:38:02.141552 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
900 04:38:02.144471 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
901 04:38:02.148131 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 04:38:02.148240
903 04:38:02.148334
904 04:38:02.148458 ==
905 04:38:02.151229 Dram Type= 6, Freq= 0, CH_0, rank 0
906 04:38:02.154871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 04:38:02.154952 ==
908 04:38:02.155015
909 04:38:02.155074
910 04:38:02.158153 TX Vref Scan disable
911 04:38:02.161518 == TX Byte 0 ==
912 04:38:02.164857 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 04:38:02.167845 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 04:38:02.171324 == TX Byte 1 ==
915 04:38:02.174450 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
916 04:38:02.178141 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
917 04:38:02.178215 ==
918 04:38:02.181161 Dram Type= 6, Freq= 0, CH_0, rank 0
919 04:38:02.184820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 04:38:02.187961 ==
921 04:38:02.199407 TX Vref=22, minBit 8, minWin=27, winSum=446
922 04:38:02.202782 TX Vref=24, minBit 10, minWin=27, winSum=450
923 04:38:02.205921 TX Vref=26, minBit 11, minWin=27, winSum=453
924 04:38:02.209597 TX Vref=28, minBit 0, minWin=28, winSum=455
925 04:38:02.212528 TX Vref=30, minBit 8, minWin=28, winSum=458
926 04:38:02.216192 TX Vref=32, minBit 8, minWin=28, winSum=458
927 04:38:02.222807 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
928 04:38:02.222890
929 04:38:02.225844 Final TX Range 1 Vref 30
930 04:38:02.225928
931 04:38:02.225996 ==
932 04:38:02.229521 Dram Type= 6, Freq= 0, CH_0, rank 0
933 04:38:02.232573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 04:38:02.232682 ==
935 04:38:02.232785
936 04:38:02.235482
937 04:38:02.235589 TX Vref Scan disable
938 04:38:02.239183 == TX Byte 0 ==
939 04:38:02.242570 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 04:38:02.245884 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 04:38:02.249487 == TX Byte 1 ==
942 04:38:02.252878 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
943 04:38:02.255855 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
944 04:38:02.255933
945 04:38:02.259201 [DATLAT]
946 04:38:02.259272 Freq=800, CH0 RK0
947 04:38:02.259333
948 04:38:02.262585 DATLAT Default: 0xa
949 04:38:02.262686 0, 0xFFFF, sum = 0
950 04:38:02.266079 1, 0xFFFF, sum = 0
951 04:38:02.266185 2, 0xFFFF, sum = 0
952 04:38:02.269689 3, 0xFFFF, sum = 0
953 04:38:02.269772 4, 0xFFFF, sum = 0
954 04:38:02.272742 5, 0xFFFF, sum = 0
955 04:38:02.272825 6, 0xFFFF, sum = 0
956 04:38:02.276187 7, 0xFFFF, sum = 0
957 04:38:02.276270 8, 0xFFFF, sum = 0
958 04:38:02.279489 9, 0x0, sum = 1
959 04:38:02.279600 10, 0x0, sum = 2
960 04:38:02.283040 11, 0x0, sum = 3
961 04:38:02.283122 12, 0x0, sum = 4
962 04:38:02.286178 best_step = 10
963 04:38:02.286260
964 04:38:02.286324 ==
965 04:38:02.289376 Dram Type= 6, Freq= 0, CH_0, rank 0
966 04:38:02.292570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 04:38:02.292652 ==
968 04:38:02.296217 RX Vref Scan: 1
969 04:38:02.296299
970 04:38:02.296363 Set Vref Range= 32 -> 127
971 04:38:02.296424
972 04:38:02.299132 RX Vref 32 -> 127, step: 1
973 04:38:02.299214
974 04:38:02.302722 RX Delay -95 -> 252, step: 8
975 04:38:02.302810
976 04:38:02.305758 Set Vref, RX VrefLevel [Byte0]: 32
977 04:38:02.309159 [Byte1]: 32
978 04:38:02.309241
979 04:38:02.312886 Set Vref, RX VrefLevel [Byte0]: 33
980 04:38:02.315941 [Byte1]: 33
981 04:38:02.319623
982 04:38:02.319725 Set Vref, RX VrefLevel [Byte0]: 34
983 04:38:02.322684 [Byte1]: 34
984 04:38:02.327046
985 04:38:02.327128 Set Vref, RX VrefLevel [Byte0]: 35
986 04:38:02.330089 [Byte1]: 35
987 04:38:02.334619
988 04:38:02.334710 Set Vref, RX VrefLevel [Byte0]: 36
989 04:38:02.338267 [Byte1]: 36
990 04:38:02.342553
991 04:38:02.342657 Set Vref, RX VrefLevel [Byte0]: 37
992 04:38:02.345544 [Byte1]: 37
993 04:38:02.350385
994 04:38:02.350464 Set Vref, RX VrefLevel [Byte0]: 38
995 04:38:02.353573 [Byte1]: 38
996 04:38:02.357823
997 04:38:02.357904 Set Vref, RX VrefLevel [Byte0]: 39
998 04:38:02.361322 [Byte1]: 39
999 04:38:02.365664
1000 04:38:02.365746 Set Vref, RX VrefLevel [Byte0]: 40
1001 04:38:02.369019 [Byte1]: 40
1002 04:38:02.373286
1003 04:38:02.373367 Set Vref, RX VrefLevel [Byte0]: 41
1004 04:38:02.376289 [Byte1]: 41
1005 04:38:02.380148
1006 04:38:02.380230 Set Vref, RX VrefLevel [Byte0]: 42
1007 04:38:02.383720 [Byte1]: 42
1008 04:38:02.387960
1009 04:38:02.388048 Set Vref, RX VrefLevel [Byte0]: 43
1010 04:38:02.391256 [Byte1]: 43
1011 04:38:02.395289
1012 04:38:02.395397 Set Vref, RX VrefLevel [Byte0]: 44
1013 04:38:02.398632 [Byte1]: 44
1014 04:38:02.402907
1015 04:38:02.402988 Set Vref, RX VrefLevel [Byte0]: 45
1016 04:38:02.405991 [Byte1]: 45
1017 04:38:02.410677
1018 04:38:02.410759 Set Vref, RX VrefLevel [Byte0]: 46
1019 04:38:02.413621 [Byte1]: 46
1020 04:38:02.418096
1021 04:38:02.418177 Set Vref, RX VrefLevel [Byte0]: 47
1022 04:38:02.421749 [Byte1]: 47
1023 04:38:02.425874
1024 04:38:02.425968 Set Vref, RX VrefLevel [Byte0]: 48
1025 04:38:02.428946 [Byte1]: 48
1026 04:38:02.433223
1027 04:38:02.433317 Set Vref, RX VrefLevel [Byte0]: 49
1028 04:38:02.436815 [Byte1]: 49
1029 04:38:02.441163
1030 04:38:02.441239 Set Vref, RX VrefLevel [Byte0]: 50
1031 04:38:02.444240 [Byte1]: 50
1032 04:38:02.448584
1033 04:38:02.448677 Set Vref, RX VrefLevel [Byte0]: 51
1034 04:38:02.452217 [Byte1]: 51
1035 04:38:02.456026
1036 04:38:02.456109 Set Vref, RX VrefLevel [Byte0]: 52
1037 04:38:02.459649 [Byte1]: 52
1038 04:38:02.463730
1039 04:38:02.463818 Set Vref, RX VrefLevel [Byte0]: 53
1040 04:38:02.466820 [Byte1]: 53
1041 04:38:02.471575
1042 04:38:02.471668 Set Vref, RX VrefLevel [Byte0]: 54
1043 04:38:02.474511 [Byte1]: 54
1044 04:38:02.478800
1045 04:38:02.478906 Set Vref, RX VrefLevel [Byte0]: 55
1046 04:38:02.482178 [Byte1]: 55
1047 04:38:02.486305
1048 04:38:02.486378 Set Vref, RX VrefLevel [Byte0]: 56
1049 04:38:02.489923 [Byte1]: 56
1050 04:38:02.494044
1051 04:38:02.494123 Set Vref, RX VrefLevel [Byte0]: 57
1052 04:38:02.497704 [Byte1]: 57
1053 04:38:02.501783
1054 04:38:02.501860 Set Vref, RX VrefLevel [Byte0]: 58
1055 04:38:02.504977 [Byte1]: 58
1056 04:38:02.509587
1057 04:38:02.509667 Set Vref, RX VrefLevel [Byte0]: 59
1058 04:38:02.512726 [Byte1]: 59
1059 04:38:02.516896
1060 04:38:02.516975 Set Vref, RX VrefLevel [Byte0]: 60
1061 04:38:02.520238 [Byte1]: 60
1062 04:38:02.524773
1063 04:38:02.524854 Set Vref, RX VrefLevel [Byte0]: 61
1064 04:38:02.527786 [Byte1]: 61
1065 04:38:02.532095
1066 04:38:02.532175 Set Vref, RX VrefLevel [Byte0]: 62
1067 04:38:02.535790 [Byte1]: 62
1068 04:38:02.540163
1069 04:38:02.540272 Set Vref, RX VrefLevel [Byte0]: 63
1070 04:38:02.543121 [Byte1]: 63
1071 04:38:02.547514
1072 04:38:02.547594 Set Vref, RX VrefLevel [Byte0]: 64
1073 04:38:02.550472 [Byte1]: 64
1074 04:38:02.555263
1075 04:38:02.555335 Set Vref, RX VrefLevel [Byte0]: 65
1076 04:38:02.558282 [Byte1]: 65
1077 04:38:02.562573
1078 04:38:02.562649 Set Vref, RX VrefLevel [Byte0]: 66
1079 04:38:02.565556 [Byte1]: 66
1080 04:38:02.570505
1081 04:38:02.570605 Set Vref, RX VrefLevel [Byte0]: 67
1082 04:38:02.573439 [Byte1]: 67
1083 04:38:02.577569
1084 04:38:02.577673 Set Vref, RX VrefLevel [Byte0]: 68
1085 04:38:02.581387 [Byte1]: 68
1086 04:38:02.585624
1087 04:38:02.585697 Set Vref, RX VrefLevel [Byte0]: 69
1088 04:38:02.588775 [Byte1]: 69
1089 04:38:02.593314
1090 04:38:02.593386 Set Vref, RX VrefLevel [Byte0]: 70
1091 04:38:02.596178 [Byte1]: 70
1092 04:38:02.600540
1093 04:38:02.600622 Set Vref, RX VrefLevel [Byte0]: 71
1094 04:38:02.604091 [Byte1]: 71
1095 04:38:02.608160
1096 04:38:02.608240 Set Vref, RX VrefLevel [Byte0]: 72
1097 04:38:02.611754 [Byte1]: 72
1098 04:38:02.615771
1099 04:38:02.615881 Set Vref, RX VrefLevel [Byte0]: 73
1100 04:38:02.619040 [Byte1]: 73
1101 04:38:02.623802
1102 04:38:02.623884 Set Vref, RX VrefLevel [Byte0]: 74
1103 04:38:02.627120 [Byte1]: 74
1104 04:38:02.630893
1105 04:38:02.630964 Set Vref, RX VrefLevel [Byte0]: 75
1106 04:38:02.634418 [Byte1]: 75
1107 04:38:02.638317
1108 04:38:02.638386 Set Vref, RX VrefLevel [Byte0]: 76
1109 04:38:02.641950 [Byte1]: 76
1110 04:38:02.646235
1111 04:38:02.646307 Set Vref, RX VrefLevel [Byte0]: 77
1112 04:38:02.649388 [Byte1]: 77
1113 04:38:02.653631
1114 04:38:02.653711 Set Vref, RX VrefLevel [Byte0]: 78
1115 04:38:02.657315 [Byte1]: 78
1116 04:38:02.661587
1117 04:38:02.661667 Set Vref, RX VrefLevel [Byte0]: 79
1118 04:38:02.664777 [Byte1]: 79
1119 04:38:02.669165
1120 04:38:02.669246 Final RX Vref Byte 0 = 51 to rank0
1121 04:38:02.672160 Final RX Vref Byte 1 = 62 to rank0
1122 04:38:02.675702 Final RX Vref Byte 0 = 51 to rank1
1123 04:38:02.678872 Final RX Vref Byte 1 = 62 to rank1==
1124 04:38:02.682738 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 04:38:02.685538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 04:38:02.689304 ==
1127 04:38:02.689386 DQS Delay:
1128 04:38:02.689450 DQS0 = 0, DQS1 = 0
1129 04:38:02.692350 DQM Delay:
1130 04:38:02.692430 DQM0 = 91, DQM1 = 86
1131 04:38:02.696002 DQ Delay:
1132 04:38:02.698992 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1133 04:38:02.699073 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 04:38:02.702513 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1135 04:38:02.705930 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1136 04:38:02.709008
1137 04:38:02.709088
1138 04:38:02.715648 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1139 04:38:02.719449 CH0 RK0: MR19=606, MR18=4D43
1140 04:38:02.725994 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64
1141 04:38:02.726076
1142 04:38:02.729550 ----->DramcWriteLeveling(PI) begin...
1143 04:38:02.729632 ==
1144 04:38:02.732817 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 04:38:02.735866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 04:38:02.735947 ==
1147 04:38:02.739456 Write leveling (Byte 0): 31 => 31
1148 04:38:02.742800 Write leveling (Byte 1): 30 => 30
1149 04:38:02.786917 DramcWriteLeveling(PI) end<-----
1150 04:38:02.787020
1151 04:38:02.787122 ==
1152 04:38:02.787181 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 04:38:02.787426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 04:38:02.787490 ==
1155 04:38:02.787603 [Gating] SW mode calibration
1156 04:38:02.787660 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 04:38:02.787716 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 04:38:02.787953 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 04:38:02.788013 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 04:38:02.788595 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1161 04:38:02.788894 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1162 04:38:02.792984 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 04:38:02.796172 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 04:38:02.799104 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 04:38:02.802770 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 04:38:02.809172 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 04:38:02.812812 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 04:38:02.816290 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 04:38:02.819425 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 04:38:02.826286 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 04:38:02.829374 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 04:38:02.832485 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 04:38:02.839169 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 04:38:02.842532 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 04:38:02.846007 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1176 04:38:02.852837 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1177 04:38:02.856332 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 04:38:02.859320 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 04:38:02.866096 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 04:38:02.869662 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 04:38:02.873102 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 04:38:02.880032 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 04:38:02.883085 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 04:38:02.886550 0 9 8 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (1 1)
1185 04:38:02.893455 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 04:38:02.896487 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 04:38:02.900024 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 04:38:02.903101 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 04:38:02.909719 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 04:38:02.913467 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 04:38:02.916797 0 10 4 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
1192 04:38:02.924105 0 10 8 | B1->B0 | 2727 2828 | 0 0 | (1 0) (0 0)
1193 04:38:02.927385 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1194 04:38:02.930756 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 04:38:02.934272 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 04:38:02.941066 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 04:38:02.944764 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 04:38:02.948652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 04:38:02.952037 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1200 04:38:02.958794 0 11 8 | B1->B0 | 4242 4545 | 0 1 | (1 1) (0 0)
1201 04:38:02.962390 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 04:38:02.965397 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 04:38:02.972105 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 04:38:02.975698 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 04:38:02.978614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 04:38:02.985651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 04:38:02.989154 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 04:38:02.992084 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 04:38:02.995837 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 04:38:03.002194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 04:38:03.005610 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 04:38:03.008654 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 04:38:03.015852 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 04:38:03.018758 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 04:38:03.022308 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 04:38:03.028816 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 04:38:03.032464 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 04:38:03.035482 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 04:38:03.042692 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 04:38:03.045692 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 04:38:03.048847 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 04:38:03.052299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 04:38:03.059052 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 04:38:03.062505 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 04:38:03.065535 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 04:38:03.069416 Total UI for P1: 0, mck2ui 16
1227 04:38:03.072617 best dqsien dly found for B0: ( 0, 14, 8)
1228 04:38:03.076211 Total UI for P1: 0, mck2ui 16
1229 04:38:03.079082 best dqsien dly found for B1: ( 0, 14, 8)
1230 04:38:03.082404 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 04:38:03.085922 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 04:38:03.086439
1233 04:38:03.092491 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 04:38:03.095954 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 04:38:03.096510 [Gating] SW calibration Done
1236 04:38:03.099346 ==
1237 04:38:03.102337 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 04:38:03.105837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 04:38:03.106287 ==
1240 04:38:03.106645 RX Vref Scan: 0
1241 04:38:03.106978
1242 04:38:03.109012 RX Vref 0 -> 0, step: 1
1243 04:38:03.109422
1244 04:38:03.112597 RX Delay -130 -> 252, step: 16
1245 04:38:03.116196 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1246 04:38:03.119295 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1247 04:38:03.122925 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1248 04:38:03.129541 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1249 04:38:03.132963 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1250 04:38:03.136206 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1251 04:38:03.139161 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1252 04:38:03.142861 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1253 04:38:03.149434 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1254 04:38:03.152985 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1255 04:38:03.156275 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1256 04:38:03.159210 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1257 04:38:03.162575 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1258 04:38:03.169446 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1259 04:38:03.172858 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1260 04:38:03.175931 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1261 04:38:03.176345 ==
1262 04:38:03.179140 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 04:38:03.182584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 04:38:03.183002 ==
1265 04:38:03.186173 DQS Delay:
1266 04:38:03.186583 DQS0 = 0, DQS1 = 0
1267 04:38:03.189064 DQM Delay:
1268 04:38:03.189476 DQM0 = 89, DQM1 = 83
1269 04:38:03.192521 DQ Delay:
1270 04:38:03.192931 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1271 04:38:03.195506 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
1272 04:38:03.199210 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1273 04:38:03.201893 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1274 04:38:03.201973
1275 04:38:03.205416
1276 04:38:03.205495 ==
1277 04:38:03.208717 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 04:38:03.212264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 04:38:03.212403 ==
1280 04:38:03.212498
1281 04:38:03.212593
1282 04:38:03.215891 TX Vref Scan disable
1283 04:38:03.215978 == TX Byte 0 ==
1284 04:38:03.218805 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1285 04:38:03.225301 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1286 04:38:03.225383 == TX Byte 1 ==
1287 04:38:03.229052 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1288 04:38:03.235802 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1289 04:38:03.235877 ==
1290 04:38:03.238640 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 04:38:03.242200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 04:38:03.242281 ==
1293 04:38:03.255780 TX Vref=22, minBit 10, minWin=27, winSum=449
1294 04:38:03.258927 TX Vref=24, minBit 10, minWin=27, winSum=452
1295 04:38:03.262638 TX Vref=26, minBit 11, minWin=27, winSum=456
1296 04:38:03.265634 TX Vref=28, minBit 4, minWin=28, winSum=459
1297 04:38:03.269442 TX Vref=30, minBit 7, minWin=28, winSum=460
1298 04:38:03.275500 TX Vref=32, minBit 5, minWin=28, winSum=460
1299 04:38:03.279365 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 30
1300 04:38:03.279530
1301 04:38:03.282227 Final TX Range 1 Vref 30
1302 04:38:03.282308
1303 04:38:03.282372 ==
1304 04:38:03.285837 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 04:38:03.288896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 04:38:03.289006 ==
1307 04:38:03.289069
1308 04:38:03.292655
1309 04:38:03.292735 TX Vref Scan disable
1310 04:38:03.295860 == TX Byte 0 ==
1311 04:38:03.299229 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1312 04:38:03.302189 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1313 04:38:03.305921 == TX Byte 1 ==
1314 04:38:03.309082 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1315 04:38:03.312345 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1316 04:38:03.315622
1317 04:38:03.315702 [DATLAT]
1318 04:38:03.315764 Freq=800, CH0 RK1
1319 04:38:03.315823
1320 04:38:03.319328 DATLAT Default: 0xa
1321 04:38:03.319407 0, 0xFFFF, sum = 0
1322 04:38:03.322813 1, 0xFFFF, sum = 0
1323 04:38:03.322894 2, 0xFFFF, sum = 0
1324 04:38:03.325629 3, 0xFFFF, sum = 0
1325 04:38:03.325711 4, 0xFFFF, sum = 0
1326 04:38:03.329366 5, 0xFFFF, sum = 0
1327 04:38:03.329438 6, 0xFFFF, sum = 0
1328 04:38:03.332641 7, 0xFFFF, sum = 0
1329 04:38:03.332715 8, 0xFFFF, sum = 0
1330 04:38:03.335861 9, 0x0, sum = 1
1331 04:38:03.335933 10, 0x0, sum = 2
1332 04:38:03.339449 11, 0x0, sum = 3
1333 04:38:03.339527 12, 0x0, sum = 4
1334 04:38:03.342461 best_step = 10
1335 04:38:03.342542
1336 04:38:03.342605 ==
1337 04:38:03.345867 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 04:38:03.349402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 04:38:03.349492 ==
1340 04:38:03.352514 RX Vref Scan: 0
1341 04:38:03.352591
1342 04:38:03.352654 RX Vref 0 -> 0, step: 1
1343 04:38:03.352712
1344 04:38:03.356299 RX Delay -79 -> 252, step: 8
1345 04:38:03.362870 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 04:38:03.365854 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1347 04:38:03.368951 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 04:38:03.372550 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1349 04:38:03.375641 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1350 04:38:03.382293 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1351 04:38:03.385862 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1352 04:38:03.389157 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 04:38:03.392794 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1354 04:38:03.396112 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1355 04:38:03.399239 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 04:38:03.406128 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 04:38:03.409015 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1358 04:38:03.412806 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1359 04:38:03.415964 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 04:38:03.422461 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1361 04:38:03.422541 ==
1362 04:38:03.426066 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 04:38:03.429168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 04:38:03.429249 ==
1365 04:38:03.429312 DQS Delay:
1366 04:38:03.432348 DQS0 = 0, DQS1 = 0
1367 04:38:03.432429 DQM Delay:
1368 04:38:03.435830 DQM0 = 92, DQM1 = 84
1369 04:38:03.435910 DQ Delay:
1370 04:38:03.439299 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1371 04:38:03.442317 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1372 04:38:03.445637 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1373 04:38:03.449243 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1374 04:38:03.449324
1375 04:38:03.449388
1376 04:38:03.456348 [DQSOSCAuto] RK1, (LSB)MR18= 0x4112, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1377 04:38:03.459456 CH0 RK1: MR19=606, MR18=4112
1378 04:38:03.466106 CH0_RK1: MR19=0x606, MR18=0x4112, DQSOSC=393, MR23=63, INC=95, DEC=63
1379 04:38:03.469070 [RxdqsGatingPostProcess] freq 800
1380 04:38:03.475747 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 04:38:03.475829 Pre-setting of DQS Precalculation
1382 04:38:03.482467 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 04:38:03.482563 ==
1384 04:38:03.486247 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 04:38:03.489337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 04:38:03.489418 ==
1387 04:38:03.495819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 04:38:03.502191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 04:38:03.510610 [CA 0] Center 36 (6~67) winsize 62
1390 04:38:03.513595 [CA 1] Center 36 (6~67) winsize 62
1391 04:38:03.517259 [CA 2] Center 34 (4~65) winsize 62
1392 04:38:03.520702 [CA 3] Center 35 (5~65) winsize 61
1393 04:38:03.523642 [CA 4] Center 34 (4~65) winsize 62
1394 04:38:03.527342 [CA 5] Center 34 (4~65) winsize 62
1395 04:38:03.527422
1396 04:38:03.530358 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1397 04:38:03.530438
1398 04:38:03.534131 [CATrainingPosCal] consider 1 rank data
1399 04:38:03.537160 u2DelayCellTimex100 = 270/100 ps
1400 04:38:03.540351 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 04:38:03.543567 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 04:38:03.550802 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 04:38:03.553963 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1404 04:38:03.556954 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 04:38:03.560630 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1406 04:38:03.560711
1407 04:38:03.564000 CA PerBit enable=1, Macro0, CA PI delay=34
1408 04:38:03.564080
1409 04:38:03.567579 [CBTSetCACLKResult] CA Dly = 34
1410 04:38:03.567674 CS Dly: 6 (0~37)
1411 04:38:03.567738 ==
1412 04:38:03.570946 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 04:38:03.577268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 04:38:03.577350 ==
1415 04:38:03.581054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 04:38:03.588194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 04:38:03.597723 [CA 0] Center 36 (6~67) winsize 62
1418 04:38:03.601187 [CA 1] Center 37 (6~68) winsize 63
1419 04:38:03.604944 [CA 2] Center 35 (5~66) winsize 62
1420 04:38:03.608484 [CA 3] Center 34 (4~65) winsize 62
1421 04:38:03.612211 [CA 4] Center 35 (5~66) winsize 62
1422 04:38:03.612330 [CA 5] Center 34 (4~65) winsize 62
1423 04:38:03.612426
1424 04:38:03.615832 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1425 04:38:03.615913
1426 04:38:03.622781 [CATrainingPosCal] consider 2 rank data
1427 04:38:03.622882 u2DelayCellTimex100 = 270/100 ps
1428 04:38:03.629153 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 04:38:03.632950 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 04:38:03.635923 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1431 04:38:03.639642 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1432 04:38:03.642597 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1433 04:38:03.646400 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 04:38:03.646481
1435 04:38:03.649341 CA PerBit enable=1, Macro0, CA PI delay=34
1436 04:38:03.649449
1437 04:38:03.652350 [CBTSetCACLKResult] CA Dly = 34
1438 04:38:03.655985 CS Dly: 6 (0~38)
1439 04:38:03.656065
1440 04:38:03.658937 ----->DramcWriteLeveling(PI) begin...
1441 04:38:03.659018 ==
1442 04:38:03.662541 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 04:38:03.666165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 04:38:03.666247 ==
1445 04:38:03.669096 Write leveling (Byte 0): 28 => 28
1446 04:38:03.672846 Write leveling (Byte 1): 28 => 28
1447 04:38:03.676356 DramcWriteLeveling(PI) end<-----
1448 04:38:03.676453
1449 04:38:03.676552 ==
1450 04:38:03.679359 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 04:38:03.683130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 04:38:03.683229 ==
1453 04:38:03.685905 [Gating] SW mode calibration
1454 04:38:03.692543 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 04:38:03.699228 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 04:38:03.702545 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 04:38:03.706199 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1458 04:38:03.712868 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 04:38:03.715892 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 04:38:03.719618 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 04:38:03.723018 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 04:38:03.729966 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 04:38:03.733065 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 04:38:03.736371 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 04:38:03.743091 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 04:38:03.746094 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 04:38:03.749588 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 04:38:03.756192 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 04:38:03.759825 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 04:38:03.762896 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 04:38:03.769755 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 04:38:03.772895 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1473 04:38:03.776645 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1474 04:38:03.783132 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 04:38:03.786159 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 04:38:03.789783 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 04:38:03.796522 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 04:38:03.799309 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 04:38:03.802798 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 04:38:03.809472 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 04:38:03.812803 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1482 04:38:03.816269 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 04:38:03.819759 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 04:38:03.826165 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 04:38:03.829273 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 04:38:03.833117 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 04:38:03.839668 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 04:38:03.842613 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1489 04:38:03.846467 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (1 1) (1 1)
1490 04:38:03.852720 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1491 04:38:03.856177 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 04:38:03.859851 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 04:38:03.866493 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 04:38:03.869536 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 04:38:03.872638 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 04:38:03.879806 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 04:38:03.882862 0 11 4 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
1498 04:38:03.886260 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1499 04:38:03.893085 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 04:38:03.896035 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 04:38:03.899797 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 04:38:03.903418 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 04:38:03.909449 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 04:38:03.912865 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 04:38:03.916548 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1506 04:38:03.923079 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 04:38:03.926719 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 04:38:03.929555 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 04:38:03.936547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 04:38:03.939633 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 04:38:03.943121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 04:38:03.949968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 04:38:03.952927 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 04:38:03.956331 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 04:38:03.963179 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 04:38:03.966024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 04:38:03.969585 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 04:38:03.976182 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 04:38:03.979953 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 04:38:03.983011 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 04:38:03.989833 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1522 04:38:03.989920 Total UI for P1: 0, mck2ui 16
1523 04:38:03.993303 best dqsien dly found for B1: ( 0, 14, 2)
1524 04:38:03.999918 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1525 04:38:04.002904 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 04:38:04.006553 Total UI for P1: 0, mck2ui 16
1527 04:38:04.009563 best dqsien dly found for B0: ( 0, 14, 6)
1528 04:38:04.013134 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1529 04:38:04.016641 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1530 04:38:04.016714
1531 04:38:04.019669 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1532 04:38:04.023094 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1533 04:38:04.026696 [Gating] SW calibration Done
1534 04:38:04.026795 ==
1535 04:38:04.029759 Dram Type= 6, Freq= 0, CH_1, rank 0
1536 04:38:04.033392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1537 04:38:04.036950 ==
1538 04:38:04.037024 RX Vref Scan: 0
1539 04:38:04.037106
1540 04:38:04.039955 RX Vref 0 -> 0, step: 1
1541 04:38:04.040047
1542 04:38:04.043386 RX Delay -130 -> 252, step: 16
1543 04:38:04.046832 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1544 04:38:04.050196 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1545 04:38:04.053376 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1546 04:38:04.056345 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1547 04:38:04.059997 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1548 04:38:04.066700 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1549 04:38:04.069634 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1550 04:38:04.073202 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1551 04:38:04.076704 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1552 04:38:04.083634 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1553 04:38:04.086533 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1554 04:38:04.089578 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1555 04:38:04.093218 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1556 04:38:04.096713 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1557 04:38:04.103347 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1558 04:38:04.106398 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1559 04:38:04.106478 ==
1560 04:38:04.110058 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 04:38:04.112969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 04:38:04.113050 ==
1563 04:38:04.116562 DQS Delay:
1564 04:38:04.116642 DQS0 = 0, DQS1 = 0
1565 04:38:04.116706 DQM Delay:
1566 04:38:04.120047 DQM0 = 94, DQM1 = 89
1567 04:38:04.120128 DQ Delay:
1568 04:38:04.122936 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1569 04:38:04.126540 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1570 04:38:04.130068 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1571 04:38:04.133036 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1572 04:38:04.133116
1573 04:38:04.133179
1574 04:38:04.133237 ==
1575 04:38:04.136098 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 04:38:04.143446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 04:38:04.143537 ==
1578 04:38:04.143630
1579 04:38:04.143705
1580 04:38:04.143763 TX Vref Scan disable
1581 04:38:04.146360 == TX Byte 0 ==
1582 04:38:04.150113 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1583 04:38:04.153181 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1584 04:38:04.156511 == TX Byte 1 ==
1585 04:38:04.160627 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1586 04:38:04.164207 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1587 04:38:04.164319 ==
1588 04:38:04.167282 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 04:38:04.171037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 04:38:04.174196 ==
1591 04:38:04.185246 TX Vref=22, minBit 0, minWin=27, winSum=441
1592 04:38:04.189038 TX Vref=24, minBit 4, minWin=26, winSum=442
1593 04:38:04.192194 TX Vref=26, minBit 2, minWin=27, winSum=446
1594 04:38:04.195061 TX Vref=28, minBit 1, minWin=27, winSum=446
1595 04:38:04.198802 TX Vref=30, minBit 1, minWin=27, winSum=451
1596 04:38:04.201777 TX Vref=32, minBit 1, minWin=27, winSum=450
1597 04:38:04.208641 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1598 04:38:04.208724
1599 04:38:04.212135 Final TX Range 1 Vref 30
1600 04:38:04.212215
1601 04:38:04.212278 ==
1602 04:38:04.215677 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 04:38:04.218559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 04:38:04.218640 ==
1605 04:38:04.218708
1606 04:38:04.218766
1607 04:38:04.222095 TX Vref Scan disable
1608 04:38:04.225645 == TX Byte 0 ==
1609 04:38:04.228971 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1610 04:38:04.232394 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1611 04:38:04.235317 == TX Byte 1 ==
1612 04:38:04.239072 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1613 04:38:04.242131 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1614 04:38:04.242204
1615 04:38:04.245232 [DATLAT]
1616 04:38:04.245306 Freq=800, CH1 RK0
1617 04:38:04.245367
1618 04:38:04.248985 DATLAT Default: 0xa
1619 04:38:04.249061 0, 0xFFFF, sum = 0
1620 04:38:04.252156 1, 0xFFFF, sum = 0
1621 04:38:04.252261 2, 0xFFFF, sum = 0
1622 04:38:04.255719 3, 0xFFFF, sum = 0
1623 04:38:04.255800 4, 0xFFFF, sum = 0
1624 04:38:04.258648 5, 0xFFFF, sum = 0
1625 04:38:04.258731 6, 0xFFFF, sum = 0
1626 04:38:04.262140 7, 0xFFFF, sum = 0
1627 04:38:04.262239 8, 0xFFFF, sum = 0
1628 04:38:04.265469 9, 0x0, sum = 1
1629 04:38:04.265543 10, 0x0, sum = 2
1630 04:38:04.268703 11, 0x0, sum = 3
1631 04:38:04.268784 12, 0x0, sum = 4
1632 04:38:04.272234 best_step = 10
1633 04:38:04.272307
1634 04:38:04.272365 ==
1635 04:38:04.275789 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 04:38:04.278675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 04:38:04.278752 ==
1638 04:38:04.282071 RX Vref Scan: 1
1639 04:38:04.282143
1640 04:38:04.282208 Set Vref Range= 32 -> 127
1641 04:38:04.282282
1642 04:38:04.285716 RX Vref 32 -> 127, step: 1
1643 04:38:04.285782
1644 04:38:04.288751 RX Delay -63 -> 252, step: 8
1645 04:38:04.288820
1646 04:38:04.292374 Set Vref, RX VrefLevel [Byte0]: 32
1647 04:38:04.295458 [Byte1]: 32
1648 04:38:04.295589
1649 04:38:04.299163 Set Vref, RX VrefLevel [Byte0]: 33
1650 04:38:04.302267 [Byte1]: 33
1651 04:38:04.302366
1652 04:38:04.305258 Set Vref, RX VrefLevel [Byte0]: 34
1653 04:38:04.308755 [Byte1]: 34
1654 04:38:04.312951
1655 04:38:04.313026 Set Vref, RX VrefLevel [Byte0]: 35
1656 04:38:04.315973 [Byte1]: 35
1657 04:38:04.320300
1658 04:38:04.320373 Set Vref, RX VrefLevel [Byte0]: 36
1659 04:38:04.323847 [Byte1]: 36
1660 04:38:04.328081
1661 04:38:04.328185 Set Vref, RX VrefLevel [Byte0]: 37
1662 04:38:04.331135 [Byte1]: 37
1663 04:38:04.335108
1664 04:38:04.335177 Set Vref, RX VrefLevel [Byte0]: 38
1665 04:38:04.338574 [Byte1]: 38
1666 04:38:04.343211
1667 04:38:04.343327 Set Vref, RX VrefLevel [Byte0]: 39
1668 04:38:04.346189 [Byte1]: 39
1669 04:38:04.350696
1670 04:38:04.350770 Set Vref, RX VrefLevel [Byte0]: 40
1671 04:38:04.353632 [Byte1]: 40
1672 04:38:04.357991
1673 04:38:04.358066 Set Vref, RX VrefLevel [Byte0]: 41
1674 04:38:04.361430 [Byte1]: 41
1675 04:38:04.365796
1676 04:38:04.365896 Set Vref, RX VrefLevel [Byte0]: 42
1677 04:38:04.368763 [Byte1]: 42
1678 04:38:04.372888
1679 04:38:04.372970 Set Vref, RX VrefLevel [Byte0]: 43
1680 04:38:04.379414 [Byte1]: 43
1681 04:38:04.379540
1682 04:38:04.382808 Set Vref, RX VrefLevel [Byte0]: 44
1683 04:38:04.386294 [Byte1]: 44
1684 04:38:04.386369
1685 04:38:04.389198 Set Vref, RX VrefLevel [Byte0]: 45
1686 04:38:04.392944 [Byte1]: 45
1687 04:38:04.393012
1688 04:38:04.395868 Set Vref, RX VrefLevel [Byte0]: 46
1689 04:38:04.399382 [Byte1]: 46
1690 04:38:04.403137
1691 04:38:04.403210 Set Vref, RX VrefLevel [Byte0]: 47
1692 04:38:04.406083 [Byte1]: 47
1693 04:38:04.410412
1694 04:38:04.410485 Set Vref, RX VrefLevel [Byte0]: 48
1695 04:38:04.413443 [Byte1]: 48
1696 04:38:04.418247
1697 04:38:04.418325 Set Vref, RX VrefLevel [Byte0]: 49
1698 04:38:04.421214 [Byte1]: 49
1699 04:38:04.425517
1700 04:38:04.425596 Set Vref, RX VrefLevel [Byte0]: 50
1701 04:38:04.428565 [Byte1]: 50
1702 04:38:04.432755
1703 04:38:04.432833 Set Vref, RX VrefLevel [Byte0]: 51
1704 04:38:04.436376 [Byte1]: 51
1705 04:38:04.440541
1706 04:38:04.440619 Set Vref, RX VrefLevel [Byte0]: 52
1707 04:38:04.443630 [Byte1]: 52
1708 04:38:04.448032
1709 04:38:04.448158 Set Vref, RX VrefLevel [Byte0]: 53
1710 04:38:04.451123 [Byte1]: 53
1711 04:38:04.455257
1712 04:38:04.455334 Set Vref, RX VrefLevel [Byte0]: 54
1713 04:38:04.458487 [Byte1]: 54
1714 04:38:04.462833
1715 04:38:04.462919 Set Vref, RX VrefLevel [Byte0]: 55
1716 04:38:04.466302 [Byte1]: 55
1717 04:38:04.470509
1718 04:38:04.470586 Set Vref, RX VrefLevel [Byte0]: 56
1719 04:38:04.473320 [Byte1]: 56
1720 04:38:04.478267
1721 04:38:04.478344 Set Vref, RX VrefLevel [Byte0]: 57
1722 04:38:04.481169 [Byte1]: 57
1723 04:38:04.485140
1724 04:38:04.485214 Set Vref, RX VrefLevel [Byte0]: 58
1725 04:38:04.488530 [Byte1]: 58
1726 04:38:04.492640
1727 04:38:04.492715 Set Vref, RX VrefLevel [Byte0]: 59
1728 04:38:04.496317 [Byte1]: 59
1729 04:38:04.500066
1730 04:38:04.500145 Set Vref, RX VrefLevel [Byte0]: 60
1731 04:38:04.503497 [Byte1]: 60
1732 04:38:04.507737
1733 04:38:04.507808 Set Vref, RX VrefLevel [Byte0]: 61
1734 04:38:04.511435 [Byte1]: 61
1735 04:38:04.515140
1736 04:38:04.515209 Set Vref, RX VrefLevel [Byte0]: 62
1737 04:38:04.518955 [Byte1]: 62
1738 04:38:04.522907
1739 04:38:04.522979 Set Vref, RX VrefLevel [Byte0]: 63
1740 04:38:04.525838 [Byte1]: 63
1741 04:38:04.530582
1742 04:38:04.530651 Set Vref, RX VrefLevel [Byte0]: 64
1743 04:38:04.533713 [Byte1]: 64
1744 04:38:04.537871
1745 04:38:04.537940 Set Vref, RX VrefLevel [Byte0]: 65
1746 04:38:04.543883 [Byte1]: 65
1747 04:38:04.543961
1748 04:38:04.547573 Set Vref, RX VrefLevel [Byte0]: 66
1749 04:38:04.551162 [Byte1]: 66
1750 04:38:04.551239
1751 04:38:04.554085 Set Vref, RX VrefLevel [Byte0]: 67
1752 04:38:04.557493 [Byte1]: 67
1753 04:38:04.557569
1754 04:38:04.561191 Set Vref, RX VrefLevel [Byte0]: 68
1755 04:38:04.564262 [Byte1]: 68
1756 04:38:04.567997
1757 04:38:04.568077 Set Vref, RX VrefLevel [Byte0]: 69
1758 04:38:04.571089 [Byte1]: 69
1759 04:38:04.575306
1760 04:38:04.575406 Set Vref, RX VrefLevel [Byte0]: 70
1761 04:38:04.578541 [Byte1]: 70
1762 04:38:04.582563
1763 04:38:04.582639 Set Vref, RX VrefLevel [Byte0]: 71
1764 04:38:04.586304 [Byte1]: 71
1765 04:38:04.590422
1766 04:38:04.590495 Set Vref, RX VrefLevel [Byte0]: 72
1767 04:38:04.593493 [Byte1]: 72
1768 04:38:04.597820
1769 04:38:04.597933 Set Vref, RX VrefLevel [Byte0]: 73
1770 04:38:04.601016 [Byte1]: 73
1771 04:38:04.605759
1772 04:38:04.605835 Final RX Vref Byte 0 = 58 to rank0
1773 04:38:04.608657 Final RX Vref Byte 1 = 56 to rank0
1774 04:38:04.612129 Final RX Vref Byte 0 = 58 to rank1
1775 04:38:04.615240 Final RX Vref Byte 1 = 56 to rank1==
1776 04:38:04.618378 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 04:38:04.625151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 04:38:04.625246 ==
1779 04:38:04.625313 DQS Delay:
1780 04:38:04.625371 DQS0 = 0, DQS1 = 0
1781 04:38:04.628678 DQM Delay:
1782 04:38:04.628766 DQM0 = 95, DQM1 = 90
1783 04:38:04.631706 DQ Delay:
1784 04:38:04.635206 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1785 04:38:04.638933 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1786 04:38:04.639015 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1787 04:38:04.645632 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1788 04:38:04.645707
1789 04:38:04.645768
1790 04:38:04.652175 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1791 04:38:04.655235 CH1 RK0: MR19=606, MR18=2C48
1792 04:38:04.662211 CH1_RK0: MR19=0x606, MR18=0x2C48, DQSOSC=391, MR23=63, INC=96, DEC=64
1793 04:38:04.662290
1794 04:38:04.665086 ----->DramcWriteLeveling(PI) begin...
1795 04:38:04.665160 ==
1796 04:38:04.668852 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 04:38:04.672072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 04:38:04.672174 ==
1799 04:38:04.675147 Write leveling (Byte 0): 28 => 28
1800 04:38:04.679090 Write leveling (Byte 1): 29 => 29
1801 04:38:04.682392 DramcWriteLeveling(PI) end<-----
1802 04:38:04.682497
1803 04:38:04.682586 ==
1804 04:38:04.685495 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 04:38:04.689023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 04:38:04.689104 ==
1807 04:38:04.692111 [Gating] SW mode calibration
1808 04:38:04.698573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 04:38:04.705321 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 04:38:04.708689 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1811 04:38:04.711931 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1812 04:38:04.718989 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 04:38:04.722525 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 04:38:04.725667 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 04:38:04.732121 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 04:38:04.735637 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 04:38:04.738633 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 04:38:04.745548 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 04:38:04.748619 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 04:38:04.752151 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 04:38:04.758789 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 04:38:04.761834 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 04:38:04.765473 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 04:38:04.768415 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 04:38:04.775628 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 04:38:04.778641 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1827 04:38:04.782280 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1828 04:38:04.788511 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 04:38:04.792278 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 04:38:04.795872 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 04:38:04.802066 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 04:38:04.805888 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 04:38:04.808822 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 04:38:04.815478 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 04:38:04.819005 0 9 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1836 04:38:04.822546 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1837 04:38:04.828816 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 04:38:04.832127 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 04:38:04.835660 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 04:38:04.838758 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 04:38:04.845743 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 04:38:04.849176 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1843 04:38:04.852573 0 10 4 | B1->B0 | 2b2b 3030 | 1 0 | (1 0) (0 1)
1844 04:38:04.859268 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 04:38:04.862281 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 04:38:04.866179 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 04:38:04.872663 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 04:38:04.875755 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 04:38:04.879264 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 04:38:04.885943 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1851 04:38:04.888843 0 11 4 | B1->B0 | 3737 2a2a | 0 0 | (1 1) (0 0)
1852 04:38:04.892541 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1853 04:38:04.899348 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 04:38:04.902217 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 04:38:04.905858 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 04:38:04.912608 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 04:38:04.915787 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 04:38:04.919418 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 04:38:04.922394 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1860 04:38:04.929189 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 04:38:04.932671 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 04:38:04.936177 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 04:38:04.942389 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 04:38:04.945949 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 04:38:04.949493 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 04:38:04.956174 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 04:38:04.959818 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 04:38:04.962494 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 04:38:04.969155 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 04:38:04.972864 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 04:38:04.975718 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 04:38:04.982427 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 04:38:04.986043 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 04:38:04.989658 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 04:38:04.995967 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1876 04:38:04.999732 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 04:38:05.002502 Total UI for P1: 0, mck2ui 16
1878 04:38:05.006190 best dqsien dly found for B0: ( 0, 14, 4)
1879 04:38:05.009182 Total UI for P1: 0, mck2ui 16
1880 04:38:05.012915 best dqsien dly found for B1: ( 0, 14, 4)
1881 04:38:05.015949 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1882 04:38:05.019755 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1883 04:38:05.019829
1884 04:38:05.022752 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1885 04:38:05.026430 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1886 04:38:05.029435 [Gating] SW calibration Done
1887 04:38:05.029507 ==
1888 04:38:05.033012 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 04:38:05.035982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 04:38:05.036052 ==
1891 04:38:05.039620 RX Vref Scan: 0
1892 04:38:05.039692
1893 04:38:05.039751 RX Vref 0 -> 0, step: 1
1894 04:38:05.039807
1895 04:38:05.042809 RX Delay -130 -> 252, step: 16
1896 04:38:05.046344 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1897 04:38:05.053149 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1898 04:38:05.056126 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1899 04:38:05.059499 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1900 04:38:05.063158 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1901 04:38:05.066365 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1902 04:38:05.073188 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1903 04:38:05.076681 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1904 04:38:05.079618 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1905 04:38:05.082719 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1906 04:38:05.086243 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1907 04:38:05.092828 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1908 04:38:05.096345 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1909 04:38:05.099613 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1910 04:38:05.103368 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1911 04:38:05.106240 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1912 04:38:05.106313 ==
1913 04:38:05.109713 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 04:38:05.116619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 04:38:05.116710 ==
1916 04:38:05.116833 DQS Delay:
1917 04:38:05.119872 DQS0 = 0, DQS1 = 0
1918 04:38:05.119976 DQM Delay:
1919 04:38:05.120068 DQM0 = 93, DQM1 = 90
1920 04:38:05.123335 DQ Delay:
1921 04:38:05.126345 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1922 04:38:05.130022 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1923 04:38:05.133133 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1924 04:38:05.136589 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1925 04:38:05.136700
1926 04:38:05.136790
1927 04:38:05.136879 ==
1928 04:38:05.139651 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 04:38:05.143267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 04:38:05.143387 ==
1931 04:38:05.143481
1932 04:38:05.143579
1933 04:38:05.146501 TX Vref Scan disable
1934 04:38:05.149973 == TX Byte 0 ==
1935 04:38:05.152953 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1936 04:38:05.156696 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1937 04:38:05.159667 == TX Byte 1 ==
1938 04:38:05.163234 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1939 04:38:05.166424 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1940 04:38:05.166502 ==
1941 04:38:05.169764 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 04:38:05.173209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 04:38:05.173288 ==
1944 04:38:05.187209 TX Vref=22, minBit 2, minWin=26, winSum=443
1945 04:38:05.190833 TX Vref=24, minBit 1, minWin=27, winSum=448
1946 04:38:05.193987 TX Vref=26, minBit 2, minWin=27, winSum=450
1947 04:38:05.197726 TX Vref=28, minBit 2, minWin=27, winSum=450
1948 04:38:05.200637 TX Vref=30, minBit 1, minWin=27, winSum=449
1949 04:38:05.204286 TX Vref=32, minBit 2, minWin=27, winSum=448
1950 04:38:05.211057 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 26
1951 04:38:05.211140
1952 04:38:05.214044 Final TX Range 1 Vref 26
1953 04:38:05.214129
1954 04:38:05.214194 ==
1955 04:38:05.217825 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 04:38:05.221051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 04:38:05.221133 ==
1958 04:38:05.221197
1959 04:38:05.221255
1960 04:38:05.224336 TX Vref Scan disable
1961 04:38:05.227838 == TX Byte 0 ==
1962 04:38:05.230998 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1963 04:38:05.234220 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1964 04:38:05.237597 == TX Byte 1 ==
1965 04:38:05.241037 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1966 04:38:05.244545 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1967 04:38:05.244620
1968 04:38:05.247450 [DATLAT]
1969 04:38:05.247557 Freq=800, CH1 RK1
1970 04:38:05.247623
1971 04:38:05.251263 DATLAT Default: 0xa
1972 04:38:05.251345 0, 0xFFFF, sum = 0
1973 04:38:05.254175 1, 0xFFFF, sum = 0
1974 04:38:05.254258 2, 0xFFFF, sum = 0
1975 04:38:05.257383 3, 0xFFFF, sum = 0
1976 04:38:05.257466 4, 0xFFFF, sum = 0
1977 04:38:05.261088 5, 0xFFFF, sum = 0
1978 04:38:05.261170 6, 0xFFFF, sum = 0
1979 04:38:05.264214 7, 0xFFFF, sum = 0
1980 04:38:05.264296 8, 0xFFFF, sum = 0
1981 04:38:05.267861 9, 0x0, sum = 1
1982 04:38:05.267943 10, 0x0, sum = 2
1983 04:38:05.270945 11, 0x0, sum = 3
1984 04:38:05.271027 12, 0x0, sum = 4
1985 04:38:05.274384 best_step = 10
1986 04:38:05.274465
1987 04:38:05.274528 ==
1988 04:38:05.277788 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 04:38:05.281106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 04:38:05.281188 ==
1991 04:38:05.284488 RX Vref Scan: 0
1992 04:38:05.284569
1993 04:38:05.284633 RX Vref 0 -> 0, step: 1
1994 04:38:05.284692
1995 04:38:05.287789 RX Delay -63 -> 252, step: 8
1996 04:38:05.294290 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1997 04:38:05.297520 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1998 04:38:05.300866 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1999 04:38:05.304103 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2000 04:38:05.307890 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2001 04:38:05.310896 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2002 04:38:05.317606 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2003 04:38:05.321257 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2004 04:38:05.324333 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2005 04:38:05.328342 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2006 04:38:05.331151 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2007 04:38:05.334850 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2008 04:38:05.341246 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2009 04:38:05.344749 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2010 04:38:05.347800 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2011 04:38:05.351395 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2012 04:38:05.351479 ==
2013 04:38:05.354765 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 04:38:05.361389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 04:38:05.361474 ==
2016 04:38:05.361538 DQS Delay:
2017 04:38:05.361598 DQS0 = 0, DQS1 = 0
2018 04:38:05.364401 DQM Delay:
2019 04:38:05.364483 DQM0 = 97, DQM1 = 92
2020 04:38:05.368092 DQ Delay:
2021 04:38:05.371376 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2022 04:38:05.375006 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2023 04:38:05.378029 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2024 04:38:05.381564 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2025 04:38:05.381647
2026 04:38:05.381710
2027 04:38:05.388499 [DQSOSCAuto] RK1, (LSB)MR18= 0x460e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2028 04:38:05.391352 CH1 RK1: MR19=606, MR18=460E
2029 04:38:05.398023 CH1_RK1: MR19=0x606, MR18=0x460E, DQSOSC=392, MR23=63, INC=96, DEC=64
2030 04:38:05.401603 [RxdqsGatingPostProcess] freq 800
2031 04:38:05.404855 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2032 04:38:05.408112 Pre-setting of DQS Precalculation
2033 04:38:05.414564 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2034 04:38:05.421439 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2035 04:38:05.428081 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2036 04:38:05.428211
2037 04:38:05.428279
2038 04:38:05.431037 [Calibration Summary] 1600 Mbps
2039 04:38:05.431144 CH 0, Rank 0
2040 04:38:05.434907 SW Impedance : PASS
2041 04:38:05.437970 DUTY Scan : NO K
2042 04:38:05.438066 ZQ Calibration : PASS
2043 04:38:05.441123 Jitter Meter : NO K
2044 04:38:05.444505 CBT Training : PASS
2045 04:38:05.444635 Write leveling : PASS
2046 04:38:05.448168 RX DQS gating : PASS
2047 04:38:05.451166 RX DQ/DQS(RDDQC) : PASS
2048 04:38:05.451299 TX DQ/DQS : PASS
2049 04:38:05.454993 RX DATLAT : PASS
2050 04:38:05.455138 RX DQ/DQS(Engine): PASS
2051 04:38:05.458072 TX OE : NO K
2052 04:38:05.458146 All Pass.
2053 04:38:05.458207
2054 04:38:05.461479 CH 0, Rank 1
2055 04:38:05.461559 SW Impedance : PASS
2056 04:38:05.464933 DUTY Scan : NO K
2057 04:38:05.467774 ZQ Calibration : PASS
2058 04:38:05.467856 Jitter Meter : NO K
2059 04:38:05.471198 CBT Training : PASS
2060 04:38:05.474695 Write leveling : PASS
2061 04:38:05.474821 RX DQS gating : PASS
2062 04:38:05.477893 RX DQ/DQS(RDDQC) : PASS
2063 04:38:05.481652 TX DQ/DQS : PASS
2064 04:38:05.481755 RX DATLAT : PASS
2065 04:38:05.484621 RX DQ/DQS(Engine): PASS
2066 04:38:05.487948 TX OE : NO K
2067 04:38:05.488067 All Pass.
2068 04:38:05.488178
2069 04:38:05.488238 CH 1, Rank 0
2070 04:38:05.491234 SW Impedance : PASS
2071 04:38:05.494447 DUTY Scan : NO K
2072 04:38:05.494540 ZQ Calibration : PASS
2073 04:38:05.498099 Jitter Meter : NO K
2074 04:38:05.501140 CBT Training : PASS
2075 04:38:05.501261 Write leveling : PASS
2076 04:38:05.504976 RX DQS gating : PASS
2077 04:38:05.505088 RX DQ/DQS(RDDQC) : PASS
2078 04:38:05.507875 TX DQ/DQS : PASS
2079 04:38:05.511480 RX DATLAT : PASS
2080 04:38:05.511602 RX DQ/DQS(Engine): PASS
2081 04:38:05.514514 TX OE : NO K
2082 04:38:05.514601 All Pass.
2083 04:38:05.514665
2084 04:38:05.517936 CH 1, Rank 1
2085 04:38:05.518066 SW Impedance : PASS
2086 04:38:05.521486 DUTY Scan : NO K
2087 04:38:05.524851 ZQ Calibration : PASS
2088 04:38:05.524957 Jitter Meter : NO K
2089 04:38:05.527947 CBT Training : PASS
2090 04:38:05.531674 Write leveling : PASS
2091 04:38:05.531772 RX DQS gating : PASS
2092 04:38:05.534702 RX DQ/DQS(RDDQC) : PASS
2093 04:38:05.537880 TX DQ/DQS : PASS
2094 04:38:05.537985 RX DATLAT : PASS
2095 04:38:05.541626 RX DQ/DQS(Engine): PASS
2096 04:38:05.541737 TX OE : NO K
2097 04:38:05.544421 All Pass.
2098 04:38:05.544505
2099 04:38:05.544570 DramC Write-DBI off
2100 04:38:05.548076 PER_BANK_REFRESH: Hybrid Mode
2101 04:38:05.551362 TX_TRACKING: ON
2102 04:38:05.554758 [GetDramInforAfterCalByMRR] Vendor 6.
2103 04:38:05.557857 [GetDramInforAfterCalByMRR] Revision 606.
2104 04:38:05.561108 [GetDramInforAfterCalByMRR] Revision 2 0.
2105 04:38:05.561189 MR0 0x3b3b
2106 04:38:05.561253 MR8 0x5151
2107 04:38:05.567883 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 04:38:05.567969
2109 04:38:05.568034 MR0 0x3b3b
2110 04:38:05.568094 MR8 0x5151
2111 04:38:05.571320 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 04:38:05.571404
2113 04:38:05.581383 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2114 04:38:05.584947 [FAST_K] Save calibration result to emmc
2115 04:38:05.588032 [FAST_K] Save calibration result to emmc
2116 04:38:05.591002 dram_init: config_dvfs: 1
2117 04:38:05.594592 dramc_set_vcore_voltage set vcore to 662500
2118 04:38:05.598291 Read voltage for 1200, 2
2119 04:38:05.598375 Vio18 = 0
2120 04:38:05.598441 Vcore = 662500
2121 04:38:05.601429 Vdram = 0
2122 04:38:05.601510 Vddq = 0
2123 04:38:05.601575 Vmddr = 0
2124 04:38:05.608179 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2125 04:38:05.611320 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2126 04:38:05.615118 MEM_TYPE=3, freq_sel=15
2127 04:38:05.617923 sv_algorithm_assistance_LP4_1600
2128 04:38:05.621509 ============ PULL DRAM RESETB DOWN ============
2129 04:38:05.624607 ========== PULL DRAM RESETB DOWN end =========
2130 04:38:05.631435 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2131 04:38:05.635022 ===================================
2132 04:38:05.635107 LPDDR4 DRAM CONFIGURATION
2133 04:38:05.638497 ===================================
2134 04:38:05.641488 EX_ROW_EN[0] = 0x0
2135 04:38:05.644922 EX_ROW_EN[1] = 0x0
2136 04:38:05.645000 LP4Y_EN = 0x0
2137 04:38:05.648417 WORK_FSP = 0x0
2138 04:38:05.648494 WL = 0x4
2139 04:38:05.651791 RL = 0x4
2140 04:38:05.651894 BL = 0x2
2141 04:38:05.655297 RPST = 0x0
2142 04:38:05.655373 RD_PRE = 0x0
2143 04:38:05.658228 WR_PRE = 0x1
2144 04:38:05.658307 WR_PST = 0x0
2145 04:38:05.661760 DBI_WR = 0x0
2146 04:38:05.661844 DBI_RD = 0x0
2147 04:38:05.664970 OTF = 0x1
2148 04:38:05.668492 ===================================
2149 04:38:05.671644 ===================================
2150 04:38:05.671733 ANA top config
2151 04:38:05.675051 ===================================
2152 04:38:05.678628 DLL_ASYNC_EN = 0
2153 04:38:05.681583 ALL_SLAVE_EN = 0
2154 04:38:05.681697 NEW_RANK_MODE = 1
2155 04:38:05.685062 DLL_IDLE_MODE = 1
2156 04:38:05.688606 LP45_APHY_COMB_EN = 1
2157 04:38:05.691660 TX_ODT_DIS = 1
2158 04:38:05.695320 NEW_8X_MODE = 1
2159 04:38:05.698360 ===================================
2160 04:38:05.701937 ===================================
2161 04:38:05.702024 data_rate = 2400
2162 04:38:05.704963 CKR = 1
2163 04:38:05.708632 DQ_P2S_RATIO = 8
2164 04:38:05.711761 ===================================
2165 04:38:05.714887 CA_P2S_RATIO = 8
2166 04:38:05.718452 DQ_CA_OPEN = 0
2167 04:38:05.721615 DQ_SEMI_OPEN = 0
2168 04:38:05.721700 CA_SEMI_OPEN = 0
2169 04:38:05.725396 CA_FULL_RATE = 0
2170 04:38:05.728420 DQ_CKDIV4_EN = 0
2171 04:38:05.731507 CA_CKDIV4_EN = 0
2172 04:38:05.735272 CA_PREDIV_EN = 0
2173 04:38:05.738470 PH8_DLY = 17
2174 04:38:05.738555 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2175 04:38:05.741836 DQ_AAMCK_DIV = 4
2176 04:38:05.745254 CA_AAMCK_DIV = 4
2177 04:38:05.748312 CA_ADMCK_DIV = 4
2178 04:38:05.751987 DQ_TRACK_CA_EN = 0
2179 04:38:05.755026 CA_PICK = 1200
2180 04:38:05.755109 CA_MCKIO = 1200
2181 04:38:05.758268 MCKIO_SEMI = 0
2182 04:38:05.761748 PLL_FREQ = 2366
2183 04:38:05.765496 DQ_UI_PI_RATIO = 32
2184 04:38:05.768539 CA_UI_PI_RATIO = 0
2185 04:38:05.771824 ===================================
2186 04:38:05.775234 ===================================
2187 04:38:05.778599 memory_type:LPDDR4
2188 04:38:05.778683 GP_NUM : 10
2189 04:38:05.781796 SRAM_EN : 1
2190 04:38:05.781879 MD32_EN : 0
2191 04:38:05.785055 ===================================
2192 04:38:05.789033 [ANA_INIT] >>>>>>>>>>>>>>
2193 04:38:05.791774 <<<<<< [CONFIGURE PHASE]: ANA_TX
2194 04:38:05.794875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2195 04:38:05.798658 ===================================
2196 04:38:05.801783 data_rate = 2400,PCW = 0X5b00
2197 04:38:05.805394 ===================================
2198 04:38:05.808729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2199 04:38:05.811790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 04:38:05.818557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 04:38:05.821719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2202 04:38:05.825337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2203 04:38:05.832219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2204 04:38:05.832300 [ANA_INIT] flow start
2205 04:38:05.835181 [ANA_INIT] PLL >>>>>>>>
2206 04:38:05.838759 [ANA_INIT] PLL <<<<<<<<
2207 04:38:05.838842 [ANA_INIT] MIDPI >>>>>>>>
2208 04:38:05.841876 [ANA_INIT] MIDPI <<<<<<<<
2209 04:38:05.845624 [ANA_INIT] DLL >>>>>>>>
2210 04:38:05.845707 [ANA_INIT] DLL <<<<<<<<
2211 04:38:05.848463 [ANA_INIT] flow end
2212 04:38:05.851949 ============ LP4 DIFF to SE enter ============
2213 04:38:05.855035 ============ LP4 DIFF to SE exit ============
2214 04:38:05.858661 [ANA_INIT] <<<<<<<<<<<<<
2215 04:38:05.861635 [Flow] Enable top DCM control >>>>>
2216 04:38:05.865241 [Flow] Enable top DCM control <<<<<
2217 04:38:05.869087 Enable DLL master slave shuffle
2218 04:38:05.875047 ==============================================================
2219 04:38:05.875132 Gating Mode config
2220 04:38:05.881726 ==============================================================
2221 04:38:05.881811 Config description:
2222 04:38:05.891873 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2223 04:38:05.898771 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2224 04:38:05.905401 SELPH_MODE 0: By rank 1: By Phase
2225 04:38:05.908985 ==============================================================
2226 04:38:05.912227 GAT_TRACK_EN = 1
2227 04:38:05.915760 RX_GATING_MODE = 2
2228 04:38:05.918888 RX_GATING_TRACK_MODE = 2
2229 04:38:05.921893 SELPH_MODE = 1
2230 04:38:05.925458 PICG_EARLY_EN = 1
2231 04:38:05.929059 VALID_LAT_VALUE = 1
2232 04:38:05.932088 ==============================================================
2233 04:38:05.935982 Enter into Gating configuration >>>>
2234 04:38:05.938904 Exit from Gating configuration <<<<
2235 04:38:05.942580 Enter into DVFS_PRE_config >>>>>
2236 04:38:05.955565 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2237 04:38:05.955669 Exit from DVFS_PRE_config <<<<<
2238 04:38:05.959173 Enter into PICG configuration >>>>
2239 04:38:05.962235 Exit from PICG configuration <<<<
2240 04:38:05.965875 [RX_INPUT] configuration >>>>>
2241 04:38:05.968976 [RX_INPUT] configuration <<<<<
2242 04:38:05.975921 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2243 04:38:05.978858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2244 04:38:05.985590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 04:38:05.992152 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 04:38:05.998772 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 04:38:06.005502 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 04:38:06.009060 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2249 04:38:06.012085 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2250 04:38:06.015665 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2251 04:38:06.022535 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2252 04:38:06.025739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2253 04:38:06.029008 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2254 04:38:06.032336 ===================================
2255 04:38:06.035478 LPDDR4 DRAM CONFIGURATION
2256 04:38:06.039216 ===================================
2257 04:38:06.039302 EX_ROW_EN[0] = 0x0
2258 04:38:06.042510 EX_ROW_EN[1] = 0x0
2259 04:38:06.042665 LP4Y_EN = 0x0
2260 04:38:06.045629 WORK_FSP = 0x0
2261 04:38:06.045728 WL = 0x4
2262 04:38:06.049097 RL = 0x4
2263 04:38:06.049183 BL = 0x2
2264 04:38:06.052220 RPST = 0x0
2265 04:38:06.052342 RD_PRE = 0x0
2266 04:38:06.056061 WR_PRE = 0x1
2267 04:38:06.058799 WR_PST = 0x0
2268 04:38:06.058882 DBI_WR = 0x0
2269 04:38:06.062341 DBI_RD = 0x0
2270 04:38:06.062442 OTF = 0x1
2271 04:38:06.065893 ===================================
2272 04:38:06.069154 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2273 04:38:06.072545 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2274 04:38:06.079122 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 04:38:06.082353 ===================================
2276 04:38:06.086070 LPDDR4 DRAM CONFIGURATION
2277 04:38:06.086155 ===================================
2278 04:38:06.088976 EX_ROW_EN[0] = 0x10
2279 04:38:06.092540 EX_ROW_EN[1] = 0x0
2280 04:38:06.092623 LP4Y_EN = 0x0
2281 04:38:06.095744 WORK_FSP = 0x0
2282 04:38:06.095825 WL = 0x4
2283 04:38:06.099411 RL = 0x4
2284 04:38:06.099508 BL = 0x2
2285 04:38:06.102375 RPST = 0x0
2286 04:38:06.102456 RD_PRE = 0x0
2287 04:38:06.106112 WR_PRE = 0x1
2288 04:38:06.106292 WR_PST = 0x0
2289 04:38:06.109238 DBI_WR = 0x0
2290 04:38:06.109364 DBI_RD = 0x0
2291 04:38:06.112554 OTF = 0x1
2292 04:38:06.116148 ===================================
2293 04:38:06.122734 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2294 04:38:06.122822 ==
2295 04:38:06.126013 Dram Type= 6, Freq= 0, CH_0, rank 0
2296 04:38:06.129584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2297 04:38:06.129671 ==
2298 04:38:06.132642 [Duty_Offset_Calibration]
2299 04:38:06.132748 B0:2 B1:1 CA:1
2300 04:38:06.132842
2301 04:38:06.135751 [DutyScan_Calibration_Flow] k_type=0
2302 04:38:06.146405
2303 04:38:06.146486 ==CLK 0==
2304 04:38:06.149747 Final CLK duty delay cell = 0
2305 04:38:06.153167 [0] MAX Duty = 5187%(X100), DQS PI = 24
2306 04:38:06.156138 [0] MIN Duty = 4875%(X100), DQS PI = 0
2307 04:38:06.156214 [0] AVG Duty = 5031%(X100)
2308 04:38:06.159399
2309 04:38:06.162835 CH0 CLK Duty spec in!! Max-Min= 312%
2310 04:38:06.166070 [DutyScan_Calibration_Flow] ====Done====
2311 04:38:06.166180
2312 04:38:06.169535 [DutyScan_Calibration_Flow] k_type=1
2313 04:38:06.184277
2314 04:38:06.184367 ==DQS 0 ==
2315 04:38:06.187345 Final DQS duty delay cell = -4
2316 04:38:06.190431 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2317 04:38:06.193991 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2318 04:38:06.197602 [-4] AVG Duty = 4937%(X100)
2319 04:38:06.197682
2320 04:38:06.197747 ==DQS 1 ==
2321 04:38:06.200803 Final DQS duty delay cell = -4
2322 04:38:06.203992 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2323 04:38:06.207622 [-4] MIN Duty = 4844%(X100), DQS PI = 30
2324 04:38:06.210478 [-4] AVG Duty = 4906%(X100)
2325 04:38:06.210560
2326 04:38:06.214092 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2327 04:38:06.214166
2328 04:38:06.217216 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2329 04:38:06.220563 [DutyScan_Calibration_Flow] ====Done====
2330 04:38:06.220645
2331 04:38:06.223895 [DutyScan_Calibration_Flow] k_type=3
2332 04:38:06.240827
2333 04:38:06.240908 ==DQM 0 ==
2334 04:38:06.244557 Final DQM duty delay cell = 0
2335 04:38:06.247700 [0] MAX Duty = 5156%(X100), DQS PI = 30
2336 04:38:06.251089 [0] MIN Duty = 4938%(X100), DQS PI = 0
2337 04:38:06.251173 [0] AVG Duty = 5047%(X100)
2338 04:38:06.254748
2339 04:38:06.254829 ==DQM 1 ==
2340 04:38:06.257758 Final DQM duty delay cell = 0
2341 04:38:06.261284 [0] MAX Duty = 5125%(X100), DQS PI = 60
2342 04:38:06.264185 [0] MIN Duty = 5031%(X100), DQS PI = 36
2343 04:38:06.264267 [0] AVG Duty = 5078%(X100)
2344 04:38:06.267736
2345 04:38:06.271206 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2346 04:38:06.271314
2347 04:38:06.274216 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2348 04:38:06.277612 [DutyScan_Calibration_Flow] ====Done====
2349 04:38:06.277694
2350 04:38:06.281109 [DutyScan_Calibration_Flow] k_type=2
2351 04:38:06.297221
2352 04:38:06.297306 ==DQ 0 ==
2353 04:38:06.300909 Final DQ duty delay cell = 0
2354 04:38:06.304495 [0] MAX Duty = 5031%(X100), DQS PI = 24
2355 04:38:06.307717 [0] MIN Duty = 4906%(X100), DQS PI = 0
2356 04:38:06.307800 [0] AVG Duty = 4968%(X100)
2357 04:38:06.307865
2358 04:38:06.310974 ==DQ 1 ==
2359 04:38:06.314323 Final DQ duty delay cell = 0
2360 04:38:06.317354 [0] MAX Duty = 5093%(X100), DQS PI = 10
2361 04:38:06.321029 [0] MIN Duty = 4938%(X100), DQS PI = 36
2362 04:38:06.321112 [0] AVG Duty = 5015%(X100)
2363 04:38:06.321177
2364 04:38:06.324080 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2365 04:38:06.327759
2366 04:38:06.330540 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2367 04:38:06.333825 [DutyScan_Calibration_Flow] ====Done====
2368 04:38:06.333932 ==
2369 04:38:06.337162 Dram Type= 6, Freq= 0, CH_1, rank 0
2370 04:38:06.340923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 04:38:06.341006 ==
2372 04:38:06.343936 [Duty_Offset_Calibration]
2373 04:38:06.344016 B0:1 B1:0 CA:0
2374 04:38:06.344080
2375 04:38:06.347656 [DutyScan_Calibration_Flow] k_type=0
2376 04:38:06.356780
2377 04:38:06.356861 ==CLK 0==
2378 04:38:06.360579 Final CLK duty delay cell = -4
2379 04:38:06.363694 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2380 04:38:06.366586 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2381 04:38:06.370305 [-4] AVG Duty = 4969%(X100)
2382 04:38:06.370385
2383 04:38:06.373546 CH1 CLK Duty spec in!! Max-Min= 124%
2384 04:38:06.377132 [DutyScan_Calibration_Flow] ====Done====
2385 04:38:06.377213
2386 04:38:06.380049 [DutyScan_Calibration_Flow] k_type=1
2387 04:38:06.396271
2388 04:38:06.396360 ==DQS 0 ==
2389 04:38:06.399677 Final DQS duty delay cell = 0
2390 04:38:06.403046 [0] MAX Duty = 5094%(X100), DQS PI = 26
2391 04:38:06.406484 [0] MIN Duty = 4875%(X100), DQS PI = 0
2392 04:38:06.406565 [0] AVG Duty = 4984%(X100)
2393 04:38:06.406628
2394 04:38:06.409863 ==DQS 1 ==
2395 04:38:06.413037 Final DQS duty delay cell = 0
2396 04:38:06.416544 [0] MAX Duty = 5187%(X100), DQS PI = 20
2397 04:38:06.419444 [0] MIN Duty = 4969%(X100), DQS PI = 10
2398 04:38:06.419571 [0] AVG Duty = 5078%(X100)
2399 04:38:06.423267
2400 04:38:06.426337 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2401 04:38:06.426422
2402 04:38:06.430095 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2403 04:38:06.432978 [DutyScan_Calibration_Flow] ====Done====
2404 04:38:06.433060
2405 04:38:06.436662 [DutyScan_Calibration_Flow] k_type=3
2406 04:38:06.453192
2407 04:38:06.453279 ==DQM 0 ==
2408 04:38:06.456193 Final DQM duty delay cell = 0
2409 04:38:06.459837 [0] MAX Duty = 5156%(X100), DQS PI = 6
2410 04:38:06.462972 [0] MIN Duty = 5031%(X100), DQS PI = 46
2411 04:38:06.463055 [0] AVG Duty = 5093%(X100)
2412 04:38:06.466409
2413 04:38:06.466492 ==DQM 1 ==
2414 04:38:06.469590 Final DQM duty delay cell = 0
2415 04:38:06.472603 [0] MAX Duty = 5031%(X100), DQS PI = 16
2416 04:38:06.476216 [0] MIN Duty = 4907%(X100), DQS PI = 36
2417 04:38:06.476299 [0] AVG Duty = 4969%(X100)
2418 04:38:06.479322
2419 04:38:06.482971 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2420 04:38:06.483054
2421 04:38:06.486043 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2422 04:38:06.489866 [DutyScan_Calibration_Flow] ====Done====
2423 04:38:06.489949
2424 04:38:06.492961 [DutyScan_Calibration_Flow] k_type=2
2425 04:38:06.509068
2426 04:38:06.509155 ==DQ 0 ==
2427 04:38:06.512670 Final DQ duty delay cell = -4
2428 04:38:06.515387 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2429 04:38:06.518468 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2430 04:38:06.521979 [-4] AVG Duty = 4984%(X100)
2431 04:38:06.522062
2432 04:38:06.522146 ==DQ 1 ==
2433 04:38:06.525310 Final DQ duty delay cell = 0
2434 04:38:06.528710 [0] MAX Duty = 5125%(X100), DQS PI = 20
2435 04:38:06.532013 [0] MIN Duty = 4969%(X100), DQS PI = 12
2436 04:38:06.535107 [0] AVG Duty = 5047%(X100)
2437 04:38:06.535184
2438 04:38:06.538759 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2439 04:38:06.538871
2440 04:38:06.542383 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2441 04:38:06.545567 [DutyScan_Calibration_Flow] ====Done====
2442 04:38:06.549146 nWR fixed to 30
2443 04:38:06.549273 [ModeRegInit_LP4] CH0 RK0
2444 04:38:06.551927 [ModeRegInit_LP4] CH0 RK1
2445 04:38:06.555370 [ModeRegInit_LP4] CH1 RK0
2446 04:38:06.558742 [ModeRegInit_LP4] CH1 RK1
2447 04:38:06.558843 match AC timing 7
2448 04:38:06.562266 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2449 04:38:06.568787 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2450 04:38:06.572395 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2451 04:38:06.575444 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2452 04:38:06.582065 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2453 04:38:06.582149 ==
2454 04:38:06.585644 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 04:38:06.588661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 04:38:06.588745 ==
2457 04:38:06.595330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2458 04:38:06.598985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2459 04:38:06.608781 [CA 0] Center 39 (8~70) winsize 63
2460 04:38:06.612374 [CA 1] Center 39 (8~70) winsize 63
2461 04:38:06.616008 [CA 2] Center 35 (5~66) winsize 62
2462 04:38:06.619117 [CA 3] Center 34 (4~65) winsize 62
2463 04:38:06.622143 [CA 4] Center 33 (3~64) winsize 62
2464 04:38:06.625591 [CA 5] Center 32 (3~62) winsize 60
2465 04:38:06.625675
2466 04:38:06.629168 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2467 04:38:06.629251
2468 04:38:06.632593 [CATrainingPosCal] consider 1 rank data
2469 04:38:06.635897 u2DelayCellTimex100 = 270/100 ps
2470 04:38:06.639022 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2471 04:38:06.642185 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2472 04:38:06.649123 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2473 04:38:06.652212 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2474 04:38:06.655748 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2475 04:38:06.659224 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2476 04:38:06.659307
2477 04:38:06.662305 CA PerBit enable=1, Macro0, CA PI delay=32
2478 04:38:06.662386
2479 04:38:06.665772 [CBTSetCACLKResult] CA Dly = 32
2480 04:38:06.665854 CS Dly: 6 (0~37)
2481 04:38:06.665919 ==
2482 04:38:06.669086 Dram Type= 6, Freq= 0, CH_0, rank 1
2483 04:38:06.675509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 04:38:06.675633 ==
2485 04:38:06.679006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 04:38:06.685750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2487 04:38:06.694540 [CA 0] Center 38 (8~69) winsize 62
2488 04:38:06.697942 [CA 1] Center 38 (8~69) winsize 62
2489 04:38:06.701594 [CA 2] Center 35 (5~66) winsize 62
2490 04:38:06.704541 [CA 3] Center 34 (4~65) winsize 62
2491 04:38:06.708151 [CA 4] Center 33 (3~64) winsize 62
2492 04:38:06.711249 [CA 5] Center 32 (3~62) winsize 60
2493 04:38:06.711347
2494 04:38:06.714891 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 04:38:06.714973
2496 04:38:06.718006 [CATrainingPosCal] consider 2 rank data
2497 04:38:06.721118 u2DelayCellTimex100 = 270/100 ps
2498 04:38:06.724914 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2499 04:38:06.727985 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2500 04:38:06.734532 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2501 04:38:06.738001 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2502 04:38:06.740986 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2503 04:38:06.744713 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2504 04:38:06.744794
2505 04:38:06.748398 CA PerBit enable=1, Macro0, CA PI delay=32
2506 04:38:06.748477
2507 04:38:06.751355 [CBTSetCACLKResult] CA Dly = 32
2508 04:38:06.751450 CS Dly: 6 (0~38)
2509 04:38:06.751514
2510 04:38:06.755032 ----->DramcWriteLeveling(PI) begin...
2511 04:38:06.758395 ==
2512 04:38:06.761121 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 04:38:06.764860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 04:38:06.764941 ==
2515 04:38:06.768004 Write leveling (Byte 0): 32 => 32
2516 04:38:06.771043 Write leveling (Byte 1): 30 => 30
2517 04:38:06.774708 DramcWriteLeveling(PI) end<-----
2518 04:38:06.774783
2519 04:38:06.774844 ==
2520 04:38:06.777738 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 04:38:06.781160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 04:38:06.781234 ==
2523 04:38:06.784466 [Gating] SW mode calibration
2524 04:38:06.791402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2525 04:38:06.795171 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2526 04:38:06.801437 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2527 04:38:06.805149 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2528 04:38:06.808038 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 04:38:06.814664 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 04:38:06.818441 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 04:38:06.821628 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 04:38:06.828384 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2533 04:38:06.831291 0 15 28 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
2534 04:38:06.834756 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2535 04:38:06.842140 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 04:38:06.845014 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 04:38:06.848150 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 04:38:06.854574 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 04:38:06.858211 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 04:38:06.861172 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2541 04:38:06.868004 1 0 28 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
2542 04:38:06.871691 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
2543 04:38:06.875064 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 04:38:06.878408 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 04:38:06.884867 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 04:38:06.887915 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 04:38:06.891294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 04:38:06.897952 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 04:38:06.901521 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 04:38:06.904610 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 04:38:06.911666 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 04:38:06.914614 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 04:38:06.918304 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 04:38:06.925047 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 04:38:06.928314 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 04:38:06.931832 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 04:38:06.938012 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 04:38:06.941623 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 04:38:06.945166 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 04:38:06.951841 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 04:38:06.954984 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 04:38:06.958441 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 04:38:06.962024 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 04:38:06.968721 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 04:38:06.971682 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 04:38:06.975172 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2567 04:38:06.978192 Total UI for P1: 0, mck2ui 16
2568 04:38:06.981818 best dqsien dly found for B0: ( 1, 3, 28)
2569 04:38:06.988547 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 04:38:06.988650 Total UI for P1: 0, mck2ui 16
2571 04:38:06.994964 best dqsien dly found for B1: ( 1, 4, 0)
2572 04:38:06.998412 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2573 04:38:07.001515 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2574 04:38:07.001596
2575 04:38:07.005117 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2576 04:38:07.008790 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2577 04:38:07.012069 [Gating] SW calibration Done
2578 04:38:07.012150 ==
2579 04:38:07.015361 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 04:38:07.018417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 04:38:07.018499 ==
2582 04:38:07.022037 RX Vref Scan: 0
2583 04:38:07.022118
2584 04:38:07.022181 RX Vref 0 -> 0, step: 1
2585 04:38:07.022244
2586 04:38:07.024829 RX Delay -40 -> 252, step: 8
2587 04:38:07.028438 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2588 04:38:07.035113 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2589 04:38:07.039005 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2590 04:38:07.041841 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2591 04:38:07.045486 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2592 04:38:07.048307 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2593 04:38:07.051995 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2594 04:38:07.058606 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2595 04:38:07.061795 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2596 04:38:07.065243 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2597 04:38:07.068378 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2598 04:38:07.072064 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2599 04:38:07.078890 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2600 04:38:07.081951 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2601 04:38:07.085097 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2602 04:38:07.088616 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2603 04:38:07.088699 ==
2604 04:38:07.091659 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 04:38:07.098359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 04:38:07.098441 ==
2607 04:38:07.098505 DQS Delay:
2608 04:38:07.101842 DQS0 = 0, DQS1 = 0
2609 04:38:07.101923 DQM Delay:
2610 04:38:07.101987 DQM0 = 121, DQM1 = 113
2611 04:38:07.105473 DQ Delay:
2612 04:38:07.108303 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2613 04:38:07.112140 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2614 04:38:07.115089 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2615 04:38:07.118534 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2616 04:38:07.118615
2617 04:38:07.118679
2618 04:38:07.118738 ==
2619 04:38:07.122197 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 04:38:07.125176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 04:38:07.125259 ==
2622 04:38:07.129057
2623 04:38:07.129152
2624 04:38:07.129222 TX Vref Scan disable
2625 04:38:07.131847 == TX Byte 0 ==
2626 04:38:07.135120 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2627 04:38:07.138412 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2628 04:38:07.142227 == TX Byte 1 ==
2629 04:38:07.145255 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2630 04:38:07.148679 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2631 04:38:07.148760 ==
2632 04:38:07.152194 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 04:38:07.158923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 04:38:07.159007 ==
2635 04:38:07.169438 TX Vref=22, minBit 12, minWin=24, winSum=408
2636 04:38:07.173288 TX Vref=24, minBit 13, minWin=24, winSum=410
2637 04:38:07.176087 TX Vref=26, minBit 3, minWin=25, winSum=420
2638 04:38:07.179044 TX Vref=28, minBit 2, minWin=26, winSum=424
2639 04:38:07.182631 TX Vref=30, minBit 12, minWin=25, winSum=425
2640 04:38:07.189336 TX Vref=32, minBit 0, minWin=26, winSum=425
2641 04:38:07.193001 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 32
2642 04:38:07.193082
2643 04:38:07.195813 Final TX Range 1 Vref 32
2644 04:38:07.195894
2645 04:38:07.195957 ==
2646 04:38:07.199546 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 04:38:07.202524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 04:38:07.202633 ==
2649 04:38:07.206146
2650 04:38:07.206227
2651 04:38:07.206291 TX Vref Scan disable
2652 04:38:07.209107 == TX Byte 0 ==
2653 04:38:07.212605 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2654 04:38:07.216305 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2655 04:38:07.219382 == TX Byte 1 ==
2656 04:38:07.223103 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2657 04:38:07.225956 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2658 04:38:07.226045
2659 04:38:07.229330 [DATLAT]
2660 04:38:07.229410 Freq=1200, CH0 RK0
2661 04:38:07.229475
2662 04:38:07.233129 DATLAT Default: 0xd
2663 04:38:07.233210 0, 0xFFFF, sum = 0
2664 04:38:07.236247 1, 0xFFFF, sum = 0
2665 04:38:07.236330 2, 0xFFFF, sum = 0
2666 04:38:07.239457 3, 0xFFFF, sum = 0
2667 04:38:07.239582 4, 0xFFFF, sum = 0
2668 04:38:07.243053 5, 0xFFFF, sum = 0
2669 04:38:07.243134 6, 0xFFFF, sum = 0
2670 04:38:07.245948 7, 0xFFFF, sum = 0
2671 04:38:07.246031 8, 0xFFFF, sum = 0
2672 04:38:07.249442 9, 0xFFFF, sum = 0
2673 04:38:07.252823 10, 0xFFFF, sum = 0
2674 04:38:07.252905 11, 0xFFFF, sum = 0
2675 04:38:07.256163 12, 0x0, sum = 1
2676 04:38:07.256245 13, 0x0, sum = 2
2677 04:38:07.256310 14, 0x0, sum = 3
2678 04:38:07.259745 15, 0x0, sum = 4
2679 04:38:07.259827 best_step = 13
2680 04:38:07.259891
2681 04:38:07.263183 ==
2682 04:38:07.263317 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 04:38:07.269344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 04:38:07.269443 ==
2685 04:38:07.269540 RX Vref Scan: 1
2686 04:38:07.269616
2687 04:38:07.273140 Set Vref Range= 32 -> 127
2688 04:38:07.273237
2689 04:38:07.276093 RX Vref 32 -> 127, step: 1
2690 04:38:07.276191
2691 04:38:07.279765 RX Delay -13 -> 252, step: 4
2692 04:38:07.279879
2693 04:38:07.282854 Set Vref, RX VrefLevel [Byte0]: 32
2694 04:38:07.286587 [Byte1]: 32
2695 04:38:07.286751
2696 04:38:07.289643 Set Vref, RX VrefLevel [Byte0]: 33
2697 04:38:07.293214 [Byte1]: 33
2698 04:38:07.293319
2699 04:38:07.296101 Set Vref, RX VrefLevel [Byte0]: 34
2700 04:38:07.299679 [Byte1]: 34
2701 04:38:07.303197
2702 04:38:07.303298 Set Vref, RX VrefLevel [Byte0]: 35
2703 04:38:07.306433 [Byte1]: 35
2704 04:38:07.311319
2705 04:38:07.311399 Set Vref, RX VrefLevel [Byte0]: 36
2706 04:38:07.314787 [Byte1]: 36
2707 04:38:07.319346
2708 04:38:07.319425 Set Vref, RX VrefLevel [Byte0]: 37
2709 04:38:07.322407 [Byte1]: 37
2710 04:38:07.327239
2711 04:38:07.327312 Set Vref, RX VrefLevel [Byte0]: 38
2712 04:38:07.330200 [Byte1]: 38
2713 04:38:07.335094
2714 04:38:07.335174 Set Vref, RX VrefLevel [Byte0]: 39
2715 04:38:07.338711 [Byte1]: 39
2716 04:38:07.342887
2717 04:38:07.342968 Set Vref, RX VrefLevel [Byte0]: 40
2718 04:38:07.346131 [Byte1]: 40
2719 04:38:07.350803
2720 04:38:07.350883 Set Vref, RX VrefLevel [Byte0]: 41
2721 04:38:07.354388 [Byte1]: 41
2722 04:38:07.358544
2723 04:38:07.358624 Set Vref, RX VrefLevel [Byte0]: 42
2724 04:38:07.362062 [Byte1]: 42
2725 04:38:07.366489
2726 04:38:07.366591 Set Vref, RX VrefLevel [Byte0]: 43
2727 04:38:07.370182 [Byte1]: 43
2728 04:38:07.374327
2729 04:38:07.374408 Set Vref, RX VrefLevel [Byte0]: 44
2730 04:38:07.377753 [Byte1]: 44
2731 04:38:07.382114
2732 04:38:07.382214 Set Vref, RX VrefLevel [Byte0]: 45
2733 04:38:07.385900 [Byte1]: 45
2734 04:38:07.390000
2735 04:38:07.390099 Set Vref, RX VrefLevel [Byte0]: 46
2736 04:38:07.393582 [Byte1]: 46
2737 04:38:07.398103
2738 04:38:07.398184 Set Vref, RX VrefLevel [Byte0]: 47
2739 04:38:07.401667 [Byte1]: 47
2740 04:38:07.406363
2741 04:38:07.406444 Set Vref, RX VrefLevel [Byte0]: 48
2742 04:38:07.409399 [Byte1]: 48
2743 04:38:07.414170
2744 04:38:07.414250 Set Vref, RX VrefLevel [Byte0]: 49
2745 04:38:07.417266 [Byte1]: 49
2746 04:38:07.422172
2747 04:38:07.422269 Set Vref, RX VrefLevel [Byte0]: 50
2748 04:38:07.424974 [Byte1]: 50
2749 04:38:07.430137
2750 04:38:07.430217 Set Vref, RX VrefLevel [Byte0]: 51
2751 04:38:07.433140 [Byte1]: 51
2752 04:38:07.437545
2753 04:38:07.437626 Set Vref, RX VrefLevel [Byte0]: 52
2754 04:38:07.441001 [Byte1]: 52
2755 04:38:07.445395
2756 04:38:07.445475 Set Vref, RX VrefLevel [Byte0]: 53
2757 04:38:07.448974 [Byte1]: 53
2758 04:38:07.453248
2759 04:38:07.453329 Set Vref, RX VrefLevel [Byte0]: 54
2760 04:38:07.457151 [Byte1]: 54
2761 04:38:07.461292
2762 04:38:07.461373 Set Vref, RX VrefLevel [Byte0]: 55
2763 04:38:07.464318 [Byte1]: 55
2764 04:38:07.468995
2765 04:38:07.469079 Set Vref, RX VrefLevel [Byte0]: 56
2766 04:38:07.472691 [Byte1]: 56
2767 04:38:07.476878
2768 04:38:07.476958 Set Vref, RX VrefLevel [Byte0]: 57
2769 04:38:07.480452 [Byte1]: 57
2770 04:38:07.484786
2771 04:38:07.484866 Set Vref, RX VrefLevel [Byte0]: 58
2772 04:38:07.488411 [Byte1]: 58
2773 04:38:07.492738
2774 04:38:07.492819 Set Vref, RX VrefLevel [Byte0]: 59
2775 04:38:07.496233 [Byte1]: 59
2776 04:38:07.500648
2777 04:38:07.500729 Set Vref, RX VrefLevel [Byte0]: 60
2778 04:38:07.503985 [Byte1]: 60
2779 04:38:07.508681
2780 04:38:07.508761 Set Vref, RX VrefLevel [Byte0]: 61
2781 04:38:07.511850 [Byte1]: 61
2782 04:38:07.516863
2783 04:38:07.516944 Set Vref, RX VrefLevel [Byte0]: 62
2784 04:38:07.519874 [Byte1]: 62
2785 04:38:07.524321
2786 04:38:07.524401 Set Vref, RX VrefLevel [Byte0]: 63
2787 04:38:07.527879 [Byte1]: 63
2788 04:38:07.531962
2789 04:38:07.532043 Set Vref, RX VrefLevel [Byte0]: 64
2790 04:38:07.535724 [Byte1]: 64
2791 04:38:07.540541
2792 04:38:07.540621 Set Vref, RX VrefLevel [Byte0]: 65
2793 04:38:07.543463 [Byte1]: 65
2794 04:38:07.548139
2795 04:38:07.548220 Set Vref, RX VrefLevel [Byte0]: 66
2796 04:38:07.551202 [Byte1]: 66
2797 04:38:07.556073
2798 04:38:07.556154 Set Vref, RX VrefLevel [Byte0]: 67
2799 04:38:07.559238 [Byte1]: 67
2800 04:38:07.564057
2801 04:38:07.564138 Set Vref, RX VrefLevel [Byte0]: 68
2802 04:38:07.567139 [Byte1]: 68
2803 04:38:07.571957
2804 04:38:07.572037 Final RX Vref Byte 0 = 55 to rank0
2805 04:38:07.574905 Final RX Vref Byte 1 = 55 to rank0
2806 04:38:07.578617 Final RX Vref Byte 0 = 55 to rank1
2807 04:38:07.581523 Final RX Vref Byte 1 = 55 to rank1==
2808 04:38:07.585269 Dram Type= 6, Freq= 0, CH_0, rank 0
2809 04:38:07.588858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2810 04:38:07.591884 ==
2811 04:38:07.591965 DQS Delay:
2812 04:38:07.592030 DQS0 = 0, DQS1 = 0
2813 04:38:07.595079 DQM Delay:
2814 04:38:07.595159 DQM0 = 120, DQM1 = 114
2815 04:38:07.598791 DQ Delay:
2816 04:38:07.601757 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2817 04:38:07.605417 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2818 04:38:07.608303 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2819 04:38:07.611929 DQ12 =120, DQ13 =118, DQ14 =128, DQ15 =122
2820 04:38:07.612010
2821 04:38:07.612074
2822 04:38:07.618394 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2823 04:38:07.621661 CH0 RK0: MR19=404, MR18=130C
2824 04:38:07.628532 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2825 04:38:07.628613
2826 04:38:07.631791 ----->DramcWriteLeveling(PI) begin...
2827 04:38:07.631872 ==
2828 04:38:07.635103 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 04:38:07.638534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 04:38:07.642012 ==
2831 04:38:07.642092 Write leveling (Byte 0): 35 => 35
2832 04:38:07.645496 Write leveling (Byte 1): 28 => 28
2833 04:38:07.648661 DramcWriteLeveling(PI) end<-----
2834 04:38:07.648740
2835 04:38:07.648803 ==
2836 04:38:07.651712 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 04:38:07.658774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 04:38:07.658856 ==
2839 04:38:07.658919 [Gating] SW mode calibration
2840 04:38:07.668519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2841 04:38:07.672112 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2842 04:38:07.675283 0 15 0 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (0 0)
2843 04:38:07.682507 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 04:38:07.685722 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 04:38:07.688657 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 04:38:07.695458 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 04:38:07.698963 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 04:38:07.702061 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 04:38:07.709130 0 15 28 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
2850 04:38:07.712648 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 04:38:07.715480 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 04:38:07.719040 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 04:38:07.726010 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 04:38:07.729106 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 04:38:07.732309 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 04:38:07.738879 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 04:38:07.742191 1 0 28 | B1->B0 | 3535 3333 | 0 0 | (0 0) (0 0)
2858 04:38:07.745674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 04:38:07.752145 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 04:38:07.755497 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 04:38:07.758979 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 04:38:07.765461 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 04:38:07.769098 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 04:38:07.772579 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2865 04:38:07.779214 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2866 04:38:07.782183 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2867 04:38:07.785918 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 04:38:07.792798 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 04:38:07.795836 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 04:38:07.799211 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 04:38:07.805521 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 04:38:07.809121 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 04:38:07.812309 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 04:38:07.815790 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 04:38:07.822207 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 04:38:07.825690 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 04:38:07.829201 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 04:38:07.835770 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 04:38:07.839109 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 04:38:07.842504 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 04:38:07.849069 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2882 04:38:07.852342 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2883 04:38:07.856051 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 04:38:07.859072 Total UI for P1: 0, mck2ui 16
2885 04:38:07.862555 best dqsien dly found for B0: ( 1, 3, 30)
2886 04:38:07.865984 Total UI for P1: 0, mck2ui 16
2887 04:38:07.869459 best dqsien dly found for B1: ( 1, 3, 30)
2888 04:38:07.872831 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2889 04:38:07.876152 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2890 04:38:07.876251
2891 04:38:07.879022 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2892 04:38:07.885799 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2893 04:38:07.885908 [Gating] SW calibration Done
2894 04:38:07.885999 ==
2895 04:38:07.889349 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 04:38:07.896121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 04:38:07.896204 ==
2898 04:38:07.896268 RX Vref Scan: 0
2899 04:38:07.896326
2900 04:38:07.899711 RX Vref 0 -> 0, step: 1
2901 04:38:07.899791
2902 04:38:07.902895 RX Delay -40 -> 252, step: 8
2903 04:38:07.906578 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2904 04:38:07.909565 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2905 04:38:07.912647 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2906 04:38:07.916323 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2907 04:38:07.923015 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2908 04:38:07.926184 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2909 04:38:07.929545 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2910 04:38:07.932909 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2911 04:38:07.936060 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2912 04:38:07.942783 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2913 04:38:07.946330 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2914 04:38:07.949898 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2915 04:38:07.952982 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2916 04:38:07.956240 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2917 04:38:07.962977 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2918 04:38:07.966644 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2919 04:38:07.966725 ==
2920 04:38:07.969967 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 04:38:07.972941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 04:38:07.973039 ==
2923 04:38:07.976545 DQS Delay:
2924 04:38:07.976629 DQS0 = 0, DQS1 = 0
2925 04:38:07.976692 DQM Delay:
2926 04:38:07.979670 DQM0 = 121, DQM1 = 113
2927 04:38:07.979767 DQ Delay:
2928 04:38:07.983030 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2929 04:38:07.986357 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2930 04:38:07.989751 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
2931 04:38:07.993119 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2932 04:38:07.993200
2933 04:38:07.996616
2934 04:38:07.996697 ==
2935 04:38:07.999855 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 04:38:08.003464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 04:38:08.003588 ==
2938 04:38:08.003653
2939 04:38:08.003713
2940 04:38:08.006585 TX Vref Scan disable
2941 04:38:08.006710 == TX Byte 0 ==
2942 04:38:08.013228 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2943 04:38:08.016775 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2944 04:38:08.016890 == TX Byte 1 ==
2945 04:38:08.019827 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2946 04:38:08.026586 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2947 04:38:08.026693 ==
2948 04:38:08.030195 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 04:38:08.033232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 04:38:08.033333 ==
2951 04:38:08.046043 TX Vref=22, minBit 1, minWin=24, winSum=409
2952 04:38:08.049026 TX Vref=24, minBit 5, minWin=25, winSum=420
2953 04:38:08.052498 TX Vref=26, minBit 0, minWin=26, winSum=420
2954 04:38:08.055881 TX Vref=28, minBit 0, minWin=26, winSum=422
2955 04:38:08.059741 TX Vref=30, minBit 5, minWin=25, winSum=424
2956 04:38:08.062910 TX Vref=32, minBit 5, minWin=25, winSum=425
2957 04:38:08.069211 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
2958 04:38:08.069292
2959 04:38:08.072942 Final TX Range 1 Vref 28
2960 04:38:08.073024
2961 04:38:08.073087 ==
2962 04:38:08.075871 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 04:38:08.079676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 04:38:08.079757 ==
2965 04:38:08.079821
2966 04:38:08.079880
2967 04:38:08.082686 TX Vref Scan disable
2968 04:38:08.086131 == TX Byte 0 ==
2969 04:38:08.089586 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2970 04:38:08.092596 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2971 04:38:08.096104 == TX Byte 1 ==
2972 04:38:08.099326 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2973 04:38:08.102878 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2974 04:38:08.102958
2975 04:38:08.106364 [DATLAT]
2976 04:38:08.106444 Freq=1200, CH0 RK1
2977 04:38:08.106509
2978 04:38:08.109584 DATLAT Default: 0xd
2979 04:38:08.109664 0, 0xFFFF, sum = 0
2980 04:38:08.113098 1, 0xFFFF, sum = 0
2981 04:38:08.113181 2, 0xFFFF, sum = 0
2982 04:38:08.116791 3, 0xFFFF, sum = 0
2983 04:38:08.116873 4, 0xFFFF, sum = 0
2984 04:38:08.119939 5, 0xFFFF, sum = 0
2985 04:38:08.120021 6, 0xFFFF, sum = 0
2986 04:38:08.122888 7, 0xFFFF, sum = 0
2987 04:38:08.122969 8, 0xFFFF, sum = 0
2988 04:38:08.126491 9, 0xFFFF, sum = 0
2989 04:38:08.126572 10, 0xFFFF, sum = 0
2990 04:38:08.129952 11, 0xFFFF, sum = 0
2991 04:38:08.130034 12, 0x0, sum = 1
2992 04:38:08.133149 13, 0x0, sum = 2
2993 04:38:08.133230 14, 0x0, sum = 3
2994 04:38:08.136235 15, 0x0, sum = 4
2995 04:38:08.136337 best_step = 13
2996 04:38:08.136441
2997 04:38:08.136499 ==
2998 04:38:08.139713 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 04:38:08.146539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 04:38:08.146646 ==
3001 04:38:08.146728 RX Vref Scan: 0
3002 04:38:08.146790
3003 04:38:08.149577 RX Vref 0 -> 0, step: 1
3004 04:38:08.149658
3005 04:38:08.153178 RX Delay -13 -> 252, step: 4
3006 04:38:08.156473 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3007 04:38:08.159794 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3008 04:38:08.166100 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3009 04:38:08.169853 iDelay=195, Bit 3, Center 120 (51 ~ 190) 140
3010 04:38:08.173274 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3011 04:38:08.176687 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3012 04:38:08.179992 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3013 04:38:08.186614 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3014 04:38:08.189571 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3015 04:38:08.193132 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3016 04:38:08.196792 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3017 04:38:08.199700 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3018 04:38:08.206634 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3019 04:38:08.210057 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3020 04:38:08.212954 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3021 04:38:08.216411 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3022 04:38:08.216515 ==
3023 04:38:08.219887 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 04:38:08.223135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 04:38:08.226300 ==
3026 04:38:08.226424 DQS Delay:
3027 04:38:08.226519 DQS0 = 0, DQS1 = 0
3028 04:38:08.230123 DQM Delay:
3029 04:38:08.230222 DQM0 = 121, DQM1 = 111
3030 04:38:08.233025 DQ Delay:
3031 04:38:08.236590 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =120
3032 04:38:08.239693 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3033 04:38:08.243212 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3034 04:38:08.246877 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3035 04:38:08.246982
3036 04:38:08.247076
3037 04:38:08.252905 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3038 04:38:08.256257 CH0 RK1: MR19=403, MR18=CED
3039 04:38:08.262898 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3040 04:38:08.266520 [RxdqsGatingPostProcess] freq 1200
3041 04:38:08.273248 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3042 04:38:08.273338 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 04:38:08.276253 best DQS1 dly(2T, 0.5T) = (0, 12)
3044 04:38:08.280044 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 04:38:08.283395 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3046 04:38:08.286825 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 04:38:08.290204 best DQS1 dly(2T, 0.5T) = (0, 11)
3048 04:38:08.293154 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 04:38:08.296629 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3050 04:38:08.300068 Pre-setting of DQS Precalculation
3051 04:38:08.303054 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3052 04:38:08.306236 ==
3053 04:38:08.309738 Dram Type= 6, Freq= 0, CH_1, rank 0
3054 04:38:08.313541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 04:38:08.313652 ==
3056 04:38:08.316499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3057 04:38:08.323274 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3058 04:38:08.332203 [CA 0] Center 37 (7~68) winsize 62
3059 04:38:08.335499 [CA 1] Center 37 (7~68) winsize 62
3060 04:38:08.339035 [CA 2] Center 35 (5~65) winsize 61
3061 04:38:08.342135 [CA 3] Center 34 (4~64) winsize 61
3062 04:38:08.345854 [CA 4] Center 34 (4~64) winsize 61
3063 04:38:08.348899 [CA 5] Center 33 (3~63) winsize 61
3064 04:38:08.348983
3065 04:38:08.352507 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3066 04:38:08.352595
3067 04:38:08.355948 [CATrainingPosCal] consider 1 rank data
3068 04:38:08.359187 u2DelayCellTimex100 = 270/100 ps
3069 04:38:08.362480 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3070 04:38:08.365667 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3071 04:38:08.372489 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3072 04:38:08.375738 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3073 04:38:08.378872 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3074 04:38:08.382621 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3075 04:38:08.382707
3076 04:38:08.385615 CA PerBit enable=1, Macro0, CA PI delay=33
3077 04:38:08.385694
3078 04:38:08.389306 [CBTSetCACLKResult] CA Dly = 33
3079 04:38:08.389405 CS Dly: 7 (0~38)
3080 04:38:08.389469 ==
3081 04:38:08.392308 Dram Type= 6, Freq= 0, CH_1, rank 1
3082 04:38:08.398806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 04:38:08.398894 ==
3084 04:38:08.402514 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3085 04:38:08.408682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3086 04:38:08.418029 [CA 0] Center 37 (7~68) winsize 62
3087 04:38:08.420946 [CA 1] Center 37 (7~68) winsize 62
3088 04:38:08.424882 [CA 2] Center 35 (5~66) winsize 62
3089 04:38:08.427743 [CA 3] Center 35 (5~65) winsize 61
3090 04:38:08.431406 [CA 4] Center 34 (4~65) winsize 62
3091 04:38:08.434653 [CA 5] Center 34 (4~64) winsize 61
3092 04:38:08.434776
3093 04:38:08.438172 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3094 04:38:08.438250
3095 04:38:08.441224 [CATrainingPosCal] consider 2 rank data
3096 04:38:08.444437 u2DelayCellTimex100 = 270/100 ps
3097 04:38:08.448015 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3098 04:38:08.451239 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3099 04:38:08.457878 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3100 04:38:08.461529 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3101 04:38:08.464396 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3102 04:38:08.467982 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3103 04:38:08.468120
3104 04:38:08.470992 CA PerBit enable=1, Macro0, CA PI delay=33
3105 04:38:08.471128
3106 04:38:08.474794 [CBTSetCACLKResult] CA Dly = 33
3107 04:38:08.474932 CS Dly: 8 (0~41)
3108 04:38:08.475059
3109 04:38:08.477745 ----->DramcWriteLeveling(PI) begin...
3110 04:38:08.481082 ==
3111 04:38:08.481222 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 04:38:08.488088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 04:38:08.488235 ==
3114 04:38:08.491532 Write leveling (Byte 0): 25 => 25
3115 04:38:08.494508 Write leveling (Byte 1): 28 => 28
3116 04:38:08.494644 DramcWriteLeveling(PI) end<-----
3117 04:38:08.498172
3118 04:38:08.498305 ==
3119 04:38:08.501309 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 04:38:08.504283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 04:38:08.504422 ==
3122 04:38:08.507636 [Gating] SW mode calibration
3123 04:38:08.514343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3124 04:38:08.517843 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3125 04:38:08.524543 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 04:38:08.527783 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 04:38:08.531235 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 04:38:08.537959 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 04:38:08.541384 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 04:38:08.544586 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 04:38:08.551092 0 15 24 | B1->B0 | 3030 2c2c | 0 0 | (0 1) (0 1)
3132 04:38:08.554723 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 04:38:08.558141 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 04:38:08.564725 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 04:38:08.567992 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 04:38:08.571476 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 04:38:08.578282 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 04:38:08.581334 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3139 04:38:08.584945 1 0 24 | B1->B0 | 3434 4444 | 1 0 | (0 0) (0 0)
3140 04:38:08.588122 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 04:38:08.594593 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 04:38:08.598287 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 04:38:08.601569 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 04:38:08.608459 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 04:38:08.611880 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 04:38:08.615319 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 04:38:08.621631 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3148 04:38:08.624871 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3149 04:38:08.628713 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 04:38:08.635025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 04:38:08.638729 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 04:38:08.641832 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 04:38:08.644998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 04:38:08.652023 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 04:38:08.654991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 04:38:08.658628 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 04:38:08.665535 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 04:38:08.668380 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 04:38:08.672193 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 04:38:08.678385 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 04:38:08.682182 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 04:38:08.684906 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 04:38:08.692049 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3164 04:38:08.695061 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3165 04:38:08.698616 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 04:38:08.701815 Total UI for P1: 0, mck2ui 16
3167 04:38:08.704915 best dqsien dly found for B0: ( 1, 3, 26)
3168 04:38:08.708696 Total UI for P1: 0, mck2ui 16
3169 04:38:08.711579 best dqsien dly found for B1: ( 1, 3, 26)
3170 04:38:08.715191 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3171 04:38:08.718854 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3172 04:38:08.718941
3173 04:38:08.721637 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3174 04:38:08.728525 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3175 04:38:08.728609 [Gating] SW calibration Done
3176 04:38:08.728675 ==
3177 04:38:08.731562 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 04:38:08.738626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 04:38:08.738711 ==
3180 04:38:08.738777 RX Vref Scan: 0
3181 04:38:08.738838
3182 04:38:08.741778 RX Vref 0 -> 0, step: 1
3183 04:38:08.741861
3184 04:38:08.745420 RX Delay -40 -> 252, step: 8
3185 04:38:08.748654 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3186 04:38:08.752309 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3187 04:38:08.755202 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3188 04:38:08.762193 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3189 04:38:08.765406 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3190 04:38:08.768892 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3191 04:38:08.771823 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3192 04:38:08.775214 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3193 04:38:08.778905 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3194 04:38:08.785457 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3195 04:38:08.788456 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3196 04:38:08.792138 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3197 04:38:08.795538 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3198 04:38:08.801947 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3199 04:38:08.805698 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3200 04:38:08.808625 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3201 04:38:08.808741 ==
3202 04:38:08.811837 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 04:38:08.815267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 04:38:08.815349 ==
3205 04:38:08.818480 DQS Delay:
3206 04:38:08.818577 DQS0 = 0, DQS1 = 0
3207 04:38:08.818642 DQM Delay:
3208 04:38:08.821919 DQM0 = 119, DQM1 = 116
3209 04:38:08.822000 DQ Delay:
3210 04:38:08.825504 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3211 04:38:08.828465 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3212 04:38:08.835498 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3213 04:38:08.838411 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3214 04:38:08.838492
3215 04:38:08.838556
3216 04:38:08.838615 ==
3217 04:38:08.842008 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 04:38:08.845066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 04:38:08.845147 ==
3220 04:38:08.845211
3221 04:38:08.845271
3222 04:38:08.848612 TX Vref Scan disable
3223 04:38:08.852143 == TX Byte 0 ==
3224 04:38:08.855318 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3225 04:38:08.858846 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3226 04:38:08.858928 == TX Byte 1 ==
3227 04:38:08.865366 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3228 04:38:08.868775 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3229 04:38:08.868857 ==
3230 04:38:08.871829 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 04:38:08.875468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 04:38:08.875588 ==
3233 04:38:08.888593 TX Vref=22, minBit 1, minWin=25, winSum=412
3234 04:38:08.891642 TX Vref=24, minBit 9, minWin=25, winSum=418
3235 04:38:08.895467 TX Vref=26, minBit 1, minWin=25, winSum=423
3236 04:38:08.898721 TX Vref=28, minBit 1, minWin=26, winSum=428
3237 04:38:08.901476 TX Vref=30, minBit 9, minWin=25, winSum=428
3238 04:38:08.905250 TX Vref=32, minBit 2, minWin=26, winSum=427
3239 04:38:08.911759 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3240 04:38:08.911842
3241 04:38:08.915217 Final TX Range 1 Vref 28
3242 04:38:08.915299
3243 04:38:08.915363 ==
3244 04:38:08.918334 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 04:38:08.921886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 04:38:08.921968 ==
3247 04:38:08.922032
3248 04:38:08.922091
3249 04:38:08.924757 TX Vref Scan disable
3250 04:38:08.928234 == TX Byte 0 ==
3251 04:38:08.931581 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3252 04:38:08.935307 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3253 04:38:08.938633 == TX Byte 1 ==
3254 04:38:08.941625 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3255 04:38:08.945058 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3256 04:38:08.945139
3257 04:38:08.948129 [DATLAT]
3258 04:38:08.948209 Freq=1200, CH1 RK0
3259 04:38:08.948286
3260 04:38:08.951731 DATLAT Default: 0xd
3261 04:38:08.951812 0, 0xFFFF, sum = 0
3262 04:38:08.955380 1, 0xFFFF, sum = 0
3263 04:38:08.955463 2, 0xFFFF, sum = 0
3264 04:38:08.958453 3, 0xFFFF, sum = 0
3265 04:38:08.958537 4, 0xFFFF, sum = 0
3266 04:38:08.962007 5, 0xFFFF, sum = 0
3267 04:38:08.962091 6, 0xFFFF, sum = 0
3268 04:38:08.965051 7, 0xFFFF, sum = 0
3269 04:38:08.965134 8, 0xFFFF, sum = 0
3270 04:38:08.968594 9, 0xFFFF, sum = 0
3271 04:38:08.968677 10, 0xFFFF, sum = 0
3272 04:38:08.971493 11, 0xFFFF, sum = 0
3273 04:38:08.971610 12, 0x0, sum = 1
3274 04:38:08.975165 13, 0x0, sum = 2
3275 04:38:08.975248 14, 0x0, sum = 3
3276 04:38:08.978909 15, 0x0, sum = 4
3277 04:38:08.978991 best_step = 13
3278 04:38:08.979055
3279 04:38:08.979113 ==
3280 04:38:08.981682 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 04:38:08.988892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 04:38:08.988974 ==
3283 04:38:08.989038 RX Vref Scan: 1
3284 04:38:08.989098
3285 04:38:08.992137 Set Vref Range= 32 -> 127
3286 04:38:08.992218
3287 04:38:08.995056 RX Vref 32 -> 127, step: 1
3288 04:38:08.995136
3289 04:38:08.995200 RX Delay -5 -> 252, step: 4
3290 04:38:08.998798
3291 04:38:08.998878 Set Vref, RX VrefLevel [Byte0]: 32
3292 04:38:09.001879 [Byte1]: 32
3293 04:38:09.006845
3294 04:38:09.006930 Set Vref, RX VrefLevel [Byte0]: 33
3295 04:38:09.009617 [Byte1]: 33
3296 04:38:09.014101
3297 04:38:09.014172 Set Vref, RX VrefLevel [Byte0]: 34
3298 04:38:09.017489 [Byte1]: 34
3299 04:38:09.022133
3300 04:38:09.022246 Set Vref, RX VrefLevel [Byte0]: 35
3301 04:38:09.025279 [Byte1]: 35
3302 04:38:09.030135
3303 04:38:09.030215 Set Vref, RX VrefLevel [Byte0]: 36
3304 04:38:09.032998 [Byte1]: 36
3305 04:38:09.037902
3306 04:38:09.037982 Set Vref, RX VrefLevel [Byte0]: 37
3307 04:38:09.041344 [Byte1]: 37
3308 04:38:09.045688
3309 04:38:09.045800 Set Vref, RX VrefLevel [Byte0]: 38
3310 04:38:09.049174 [Byte1]: 38
3311 04:38:09.053747
3312 04:38:09.053827 Set Vref, RX VrefLevel [Byte0]: 39
3313 04:38:09.056751 [Byte1]: 39
3314 04:38:09.061130
3315 04:38:09.061311 Set Vref, RX VrefLevel [Byte0]: 40
3316 04:38:09.064577 [Byte1]: 40
3317 04:38:09.069387
3318 04:38:09.069467 Set Vref, RX VrefLevel [Byte0]: 41
3319 04:38:09.072356 [Byte1]: 41
3320 04:38:09.076842
3321 04:38:09.076949 Set Vref, RX VrefLevel [Byte0]: 42
3322 04:38:09.080166 [Byte1]: 42
3323 04:38:09.084846
3324 04:38:09.084929 Set Vref, RX VrefLevel [Byte0]: 43
3325 04:38:09.088404 [Byte1]: 43
3326 04:38:09.092631
3327 04:38:09.092705 Set Vref, RX VrefLevel [Byte0]: 44
3328 04:38:09.096106 [Byte1]: 44
3329 04:38:09.100366
3330 04:38:09.100437 Set Vref, RX VrefLevel [Byte0]: 45
3331 04:38:09.103917 [Byte1]: 45
3332 04:38:09.108752
3333 04:38:09.108850 Set Vref, RX VrefLevel [Byte0]: 46
3334 04:38:09.111897 [Byte1]: 46
3335 04:38:09.116114
3336 04:38:09.116194 Set Vref, RX VrefLevel [Byte0]: 47
3337 04:38:09.119874 [Byte1]: 47
3338 04:38:09.124040
3339 04:38:09.124121 Set Vref, RX VrefLevel [Byte0]: 48
3340 04:38:09.127767 [Byte1]: 48
3341 04:38:09.132017
3342 04:38:09.132097 Set Vref, RX VrefLevel [Byte0]: 49
3343 04:38:09.135065 [Byte1]: 49
3344 04:38:09.139927
3345 04:38:09.140007 Set Vref, RX VrefLevel [Byte0]: 50
3346 04:38:09.143073 [Byte1]: 50
3347 04:38:09.147806
3348 04:38:09.147887 Set Vref, RX VrefLevel [Byte0]: 51
3349 04:38:09.151323 [Byte1]: 51
3350 04:38:09.155377
3351 04:38:09.155484 Set Vref, RX VrefLevel [Byte0]: 52
3352 04:38:09.158786 [Byte1]: 52
3353 04:38:09.163313
3354 04:38:09.163394 Set Vref, RX VrefLevel [Byte0]: 53
3355 04:38:09.167057 [Byte1]: 53
3356 04:38:09.171310
3357 04:38:09.171418 Set Vref, RX VrefLevel [Byte0]: 54
3358 04:38:09.174772 [Byte1]: 54
3359 04:38:09.179097
3360 04:38:09.179251 Set Vref, RX VrefLevel [Byte0]: 55
3361 04:38:09.182675 [Byte1]: 55
3362 04:38:09.186839
3363 04:38:09.186919 Set Vref, RX VrefLevel [Byte0]: 56
3364 04:38:09.190657 [Byte1]: 56
3365 04:38:09.194844
3366 04:38:09.194925 Set Vref, RX VrefLevel [Byte0]: 57
3367 04:38:09.198127 [Byte1]: 57
3368 04:38:09.202510
3369 04:38:09.202591 Set Vref, RX VrefLevel [Byte0]: 58
3370 04:38:09.205988 [Byte1]: 58
3371 04:38:09.210352
3372 04:38:09.210432 Set Vref, RX VrefLevel [Byte0]: 59
3373 04:38:09.214228 [Byte1]: 59
3374 04:38:09.218400
3375 04:38:09.218481 Set Vref, RX VrefLevel [Byte0]: 60
3376 04:38:09.221335 [Byte1]: 60
3377 04:38:09.226129
3378 04:38:09.226211 Set Vref, RX VrefLevel [Byte0]: 61
3379 04:38:09.229395 [Byte1]: 61
3380 04:38:09.234124
3381 04:38:09.234264 Set Vref, RX VrefLevel [Byte0]: 62
3382 04:38:09.237495 [Byte1]: 62
3383 04:38:09.241888
3384 04:38:09.241971 Set Vref, RX VrefLevel [Byte0]: 63
3385 04:38:09.245351 [Byte1]: 63
3386 04:38:09.249911
3387 04:38:09.250023 Set Vref, RX VrefLevel [Byte0]: 64
3388 04:38:09.253025 [Byte1]: 64
3389 04:38:09.257940
3390 04:38:09.258073 Set Vref, RX VrefLevel [Byte0]: 65
3391 04:38:09.260888 [Byte1]: 65
3392 04:38:09.265662
3393 04:38:09.265748 Set Vref, RX VrefLevel [Byte0]: 66
3394 04:38:09.268905 [Byte1]: 66
3395 04:38:09.273128
3396 04:38:09.273239 Set Vref, RX VrefLevel [Byte0]: 67
3397 04:38:09.276631 [Byte1]: 67
3398 04:38:09.281511
3399 04:38:09.281638 Set Vref, RX VrefLevel [Byte0]: 68
3400 04:38:09.284758 [Byte1]: 68
3401 04:38:09.289174
3402 04:38:09.289269 Set Vref, RX VrefLevel [Byte0]: 69
3403 04:38:09.292417 [Byte1]: 69
3404 04:38:09.296809
3405 04:38:09.296903 Final RX Vref Byte 0 = 56 to rank0
3406 04:38:09.300511 Final RX Vref Byte 1 = 54 to rank0
3407 04:38:09.303677 Final RX Vref Byte 0 = 56 to rank1
3408 04:38:09.306473 Final RX Vref Byte 1 = 54 to rank1==
3409 04:38:09.310146 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 04:38:09.316473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 04:38:09.316564 ==
3412 04:38:09.316630 DQS Delay:
3413 04:38:09.316690 DQS0 = 0, DQS1 = 0
3414 04:38:09.320053 DQM Delay:
3415 04:38:09.320166 DQM0 = 120, DQM1 = 117
3416 04:38:09.323814 DQ Delay:
3417 04:38:09.326862 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3418 04:38:09.330445 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =122
3419 04:38:09.333384 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3420 04:38:09.337062 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3421 04:38:09.337144
3422 04:38:09.337208
3423 04:38:09.343416 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3424 04:38:09.347119 CH1 RK0: MR19=304, MR18=FE10
3425 04:38:09.353500 CH1_RK0: MR19=0x304, MR18=0xFE10, DQSOSC=403, MR23=63, INC=40, DEC=26
3426 04:38:09.353589
3427 04:38:09.356832 ----->DramcWriteLeveling(PI) begin...
3428 04:38:09.356937 ==
3429 04:38:09.360014 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 04:38:09.363634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 04:38:09.367074 ==
3432 04:38:09.367158 Write leveling (Byte 0): 25 => 25
3433 04:38:09.370216 Write leveling (Byte 1): 28 => 28
3434 04:38:09.373311 DramcWriteLeveling(PI) end<-----
3435 04:38:09.373399
3436 04:38:09.373465 ==
3437 04:38:09.376827 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 04:38:09.383527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 04:38:09.383612 ==
3440 04:38:09.383678 [Gating] SW mode calibration
3441 04:38:09.394009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3442 04:38:09.397208 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3443 04:38:09.400978 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 04:38:09.407249 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 04:38:09.410724 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 04:38:09.413723 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 04:38:09.420691 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 04:38:09.423798 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3449 04:38:09.426923 0 15 24 | B1->B0 | 2a2a 3434 | 1 1 | (1 0) (1 0)
3450 04:38:09.433771 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3451 04:38:09.437242 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 04:38:09.440896 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 04:38:09.447436 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 04:38:09.450894 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 04:38:09.454187 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 04:38:09.457516 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3457 04:38:09.464026 1 0 24 | B1->B0 | 4141 2827 | 0 1 | (0 0) (0 0)
3458 04:38:09.467646 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 04:38:09.470739 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 04:38:09.477396 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 04:38:09.480420 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 04:38:09.484006 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 04:38:09.490349 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 04:38:09.493751 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 04:38:09.497097 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3466 04:38:09.503666 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3467 04:38:09.507201 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 04:38:09.510563 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 04:38:09.517099 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 04:38:09.520573 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 04:38:09.523479 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 04:38:09.530188 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 04:38:09.533861 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 04:38:09.536954 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 04:38:09.543510 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 04:38:09.547312 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 04:38:09.550224 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 04:38:09.556734 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 04:38:09.560007 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 04:38:09.563489 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 04:38:09.570175 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 04:38:09.573361 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3483 04:38:09.576635 Total UI for P1: 0, mck2ui 16
3484 04:38:09.580322 best dqsien dly found for B1: ( 1, 3, 24)
3485 04:38:09.583218 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 04:38:09.587022 Total UI for P1: 0, mck2ui 16
3487 04:38:09.590101 best dqsien dly found for B0: ( 1, 3, 26)
3488 04:38:09.593072 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3489 04:38:09.596803 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3490 04:38:09.596922
3491 04:38:09.599783 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3492 04:38:09.606523 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3493 04:38:09.606626 [Gating] SW calibration Done
3494 04:38:09.606732 ==
3495 04:38:09.609925 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 04:38:09.616345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 04:38:09.616491 ==
3498 04:38:09.616619 RX Vref Scan: 0
3499 04:38:09.616740
3500 04:38:09.620138 RX Vref 0 -> 0, step: 1
3501 04:38:09.620219
3502 04:38:09.623357 RX Delay -40 -> 252, step: 8
3503 04:38:09.626686 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3504 04:38:09.629822 iDelay=208, Bit 1, Center 119 (56 ~ 183) 128
3505 04:38:09.633183 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3506 04:38:09.640096 iDelay=208, Bit 3, Center 119 (56 ~ 183) 128
3507 04:38:09.643107 iDelay=208, Bit 4, Center 119 (56 ~ 183) 128
3508 04:38:09.646535 iDelay=208, Bit 5, Center 135 (64 ~ 207) 144
3509 04:38:09.650349 iDelay=208, Bit 6, Center 131 (64 ~ 199) 136
3510 04:38:09.653467 iDelay=208, Bit 7, Center 123 (56 ~ 191) 136
3511 04:38:09.656682 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
3512 04:38:09.663066 iDelay=208, Bit 9, Center 107 (40 ~ 175) 136
3513 04:38:09.666539 iDelay=208, Bit 10, Center 115 (48 ~ 183) 136
3514 04:38:09.669841 iDelay=208, Bit 11, Center 111 (48 ~ 175) 128
3515 04:38:09.673088 iDelay=208, Bit 12, Center 127 (56 ~ 199) 144
3516 04:38:09.680056 iDelay=208, Bit 13, Center 127 (64 ~ 191) 128
3517 04:38:09.683230 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
3518 04:38:09.686221 iDelay=208, Bit 15, Center 123 (56 ~ 191) 136
3519 04:38:09.686302 ==
3520 04:38:09.690183 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 04:38:09.693351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 04:38:09.693433 ==
3523 04:38:09.696642 DQS Delay:
3524 04:38:09.696722 DQS0 = 0, DQS1 = 0
3525 04:38:09.699510 DQM Delay:
3526 04:38:09.699631 DQM0 = 122, DQM1 = 117
3527 04:38:09.699695 DQ Delay:
3528 04:38:09.706304 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3529 04:38:09.710021 DQ4 =119, DQ5 =135, DQ6 =131, DQ7 =123
3530 04:38:09.713165 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3531 04:38:09.716529 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3532 04:38:09.716636
3533 04:38:09.716731
3534 04:38:09.716819 ==
3535 04:38:09.719736 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 04:38:09.723227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 04:38:09.723360 ==
3538 04:38:09.723479
3539 04:38:09.723600
3540 04:38:09.726303 TX Vref Scan disable
3541 04:38:09.729682 == TX Byte 0 ==
3542 04:38:09.733103 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3543 04:38:09.736667 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3544 04:38:09.739348 == TX Byte 1 ==
3545 04:38:09.743056 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3546 04:38:09.746228 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3547 04:38:09.746365 ==
3548 04:38:09.749461 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 04:38:09.755740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 04:38:09.755849 ==
3551 04:38:09.766411 TX Vref=22, minBit 1, minWin=26, winSum=423
3552 04:38:09.769461 TX Vref=24, minBit 10, minWin=25, winSum=425
3553 04:38:09.772979 TX Vref=26, minBit 10, minWin=25, winSum=427
3554 04:38:09.775989 TX Vref=28, minBit 10, minWin=25, winSum=432
3555 04:38:09.779377 TX Vref=30, minBit 9, minWin=26, winSum=433
3556 04:38:09.786148 TX Vref=32, minBit 9, minWin=26, winSum=434
3557 04:38:09.790009 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3558 04:38:09.790138
3559 04:38:09.792960 Final TX Range 1 Vref 32
3560 04:38:09.793060
3561 04:38:09.793155 ==
3562 04:38:09.796082 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 04:38:09.799496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 04:38:09.803116 ==
3565 04:38:09.803195
3566 04:38:09.803258
3567 04:38:09.803317 TX Vref Scan disable
3568 04:38:09.806375 == TX Byte 0 ==
3569 04:38:09.809495 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3570 04:38:09.816041 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3571 04:38:09.816125 == TX Byte 1 ==
3572 04:38:09.819486 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3573 04:38:09.826338 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3574 04:38:09.826424
3575 04:38:09.826488 [DATLAT]
3576 04:38:09.826547 Freq=1200, CH1 RK1
3577 04:38:09.826605
3578 04:38:09.829304 DATLAT Default: 0xd
3579 04:38:09.829386 0, 0xFFFF, sum = 0
3580 04:38:09.832923 1, 0xFFFF, sum = 0
3581 04:38:09.833005 2, 0xFFFF, sum = 0
3582 04:38:09.836600 3, 0xFFFF, sum = 0
3583 04:38:09.839382 4, 0xFFFF, sum = 0
3584 04:38:09.839463 5, 0xFFFF, sum = 0
3585 04:38:09.843040 6, 0xFFFF, sum = 0
3586 04:38:09.843122 7, 0xFFFF, sum = 0
3587 04:38:09.846078 8, 0xFFFF, sum = 0
3588 04:38:09.846161 9, 0xFFFF, sum = 0
3589 04:38:09.849473 10, 0xFFFF, sum = 0
3590 04:38:09.849555 11, 0xFFFF, sum = 0
3591 04:38:09.852589 12, 0x0, sum = 1
3592 04:38:09.852672 13, 0x0, sum = 2
3593 04:38:09.856106 14, 0x0, sum = 3
3594 04:38:09.856189 15, 0x0, sum = 4
3595 04:38:09.859278 best_step = 13
3596 04:38:09.859387
3597 04:38:09.859480 ==
3598 04:38:09.862782 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 04:38:09.865980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 04:38:09.866063 ==
3601 04:38:09.866128 RX Vref Scan: 0
3602 04:38:09.866187
3603 04:38:09.869607 RX Vref 0 -> 0, step: 1
3604 04:38:09.869688
3605 04:38:09.872887 RX Delay -5 -> 252, step: 4
3606 04:38:09.875837 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3607 04:38:09.882477 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3608 04:38:09.885942 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3609 04:38:09.889239 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3610 04:38:09.892579 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3611 04:38:09.895977 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3612 04:38:09.902767 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3613 04:38:09.905924 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3614 04:38:09.908956 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3615 04:38:09.912303 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3616 04:38:09.915838 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3617 04:38:09.922199 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3618 04:38:09.925877 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3619 04:38:09.929189 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3620 04:38:09.932456 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3621 04:38:09.935497 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3622 04:38:09.939030 ==
3623 04:38:09.942551 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 04:38:09.945419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 04:38:09.945501 ==
3626 04:38:09.945565 DQS Delay:
3627 04:38:09.949163 DQS0 = 0, DQS1 = 0
3628 04:38:09.949245 DQM Delay:
3629 04:38:09.952225 DQM0 = 120, DQM1 = 118
3630 04:38:09.952306 DQ Delay:
3631 04:38:09.956129 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3632 04:38:09.958798 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3633 04:38:09.962222 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3634 04:38:09.965835 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3635 04:38:09.965918
3636 04:38:09.965981
3637 04:38:09.975512 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3638 04:38:09.979156 CH1 RK1: MR19=403, MR18=10ED
3639 04:38:09.982058 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3640 04:38:09.985714 [RxdqsGatingPostProcess] freq 1200
3641 04:38:09.992351 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3642 04:38:09.995312 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 04:38:09.998767 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 04:38:10.002040 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 04:38:10.005680 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 04:38:10.008814 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 04:38:10.012483 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 04:38:10.015430 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 04:38:10.019132 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 04:38:10.022028 Pre-setting of DQS Precalculation
3651 04:38:10.025695 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3652 04:38:10.032324 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3653 04:38:10.039068 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3654 04:38:10.039150
3655 04:38:10.039214
3656 04:38:10.041943 [Calibration Summary] 2400 Mbps
3657 04:38:10.045570 CH 0, Rank 0
3658 04:38:10.045651 SW Impedance : PASS
3659 04:38:10.048497 DUTY Scan : NO K
3660 04:38:10.052006 ZQ Calibration : PASS
3661 04:38:10.052089 Jitter Meter : NO K
3662 04:38:10.055568 CBT Training : PASS
3663 04:38:10.058594 Write leveling : PASS
3664 04:38:10.058674 RX DQS gating : PASS
3665 04:38:10.062198 RX DQ/DQS(RDDQC) : PASS
3666 04:38:10.062278 TX DQ/DQS : PASS
3667 04:38:10.065197 RX DATLAT : PASS
3668 04:38:10.068907 RX DQ/DQS(Engine): PASS
3669 04:38:10.068995 TX OE : NO K
3670 04:38:10.072219 All Pass.
3671 04:38:10.072302
3672 04:38:10.072365 CH 0, Rank 1
3673 04:38:10.075396 SW Impedance : PASS
3674 04:38:10.075503 DUTY Scan : NO K
3675 04:38:10.079146 ZQ Calibration : PASS
3676 04:38:10.081862 Jitter Meter : NO K
3677 04:38:10.081960 CBT Training : PASS
3678 04:38:10.085131 Write leveling : PASS
3679 04:38:10.088839 RX DQS gating : PASS
3680 04:38:10.088924 RX DQ/DQS(RDDQC) : PASS
3681 04:38:10.091687 TX DQ/DQS : PASS
3682 04:38:10.095421 RX DATLAT : PASS
3683 04:38:10.095502 RX DQ/DQS(Engine): PASS
3684 04:38:10.098463 TX OE : NO K
3685 04:38:10.098530 All Pass.
3686 04:38:10.098589
3687 04:38:10.101629 CH 1, Rank 0
3688 04:38:10.101709 SW Impedance : PASS
3689 04:38:10.105050 DUTY Scan : NO K
3690 04:38:10.109068 ZQ Calibration : PASS
3691 04:38:10.109148 Jitter Meter : NO K
3692 04:38:10.111799 CBT Training : PASS
3693 04:38:10.111879 Write leveling : PASS
3694 04:38:10.115251 RX DQS gating : PASS
3695 04:38:10.118990 RX DQ/DQS(RDDQC) : PASS
3696 04:38:10.119071 TX DQ/DQS : PASS
3697 04:38:10.121984 RX DATLAT : PASS
3698 04:38:10.125249 RX DQ/DQS(Engine): PASS
3699 04:38:10.125329 TX OE : NO K
3700 04:38:10.128911 All Pass.
3701 04:38:10.128990
3702 04:38:10.129053 CH 1, Rank 1
3703 04:38:10.131983 SW Impedance : PASS
3704 04:38:10.132063 DUTY Scan : NO K
3705 04:38:10.135233 ZQ Calibration : PASS
3706 04:38:10.138953 Jitter Meter : NO K
3707 04:38:10.139033 CBT Training : PASS
3708 04:38:10.141918 Write leveling : PASS
3709 04:38:10.145279 RX DQS gating : PASS
3710 04:38:10.145359 RX DQ/DQS(RDDQC) : PASS
3711 04:38:10.148314 TX DQ/DQS : PASS
3712 04:38:10.151969 RX DATLAT : PASS
3713 04:38:10.152050 RX DQ/DQS(Engine): PASS
3714 04:38:10.154963 TX OE : NO K
3715 04:38:10.155043 All Pass.
3716 04:38:10.155107
3717 04:38:10.158760 DramC Write-DBI off
3718 04:38:10.162184 PER_BANK_REFRESH: Hybrid Mode
3719 04:38:10.162264 TX_TRACKING: ON
3720 04:38:10.171833 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3721 04:38:10.175004 [FAST_K] Save calibration result to emmc
3722 04:38:10.178467 dramc_set_vcore_voltage set vcore to 650000
3723 04:38:10.181506 Read voltage for 600, 5
3724 04:38:10.181586 Vio18 = 0
3725 04:38:10.181649 Vcore = 650000
3726 04:38:10.185246 Vdram = 0
3727 04:38:10.185326 Vddq = 0
3728 04:38:10.185389 Vmddr = 0
3729 04:38:10.191841 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3730 04:38:10.194710 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3731 04:38:10.198371 MEM_TYPE=3, freq_sel=19
3732 04:38:10.201899 sv_algorithm_assistance_LP4_1600
3733 04:38:10.204987 ============ PULL DRAM RESETB DOWN ============
3734 04:38:10.208265 ========== PULL DRAM RESETB DOWN end =========
3735 04:38:10.215019 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3736 04:38:10.218143 ===================================
3737 04:38:10.218224 LPDDR4 DRAM CONFIGURATION
3738 04:38:10.221454 ===================================
3739 04:38:10.224816 EX_ROW_EN[0] = 0x0
3740 04:38:10.228643 EX_ROW_EN[1] = 0x0
3741 04:38:10.228724 LP4Y_EN = 0x0
3742 04:38:10.231364 WORK_FSP = 0x0
3743 04:38:10.231470 WL = 0x2
3744 04:38:10.234996 RL = 0x2
3745 04:38:10.235076 BL = 0x2
3746 04:38:10.238000 RPST = 0x0
3747 04:38:10.238080 RD_PRE = 0x0
3748 04:38:10.241720 WR_PRE = 0x1
3749 04:38:10.241800 WR_PST = 0x0
3750 04:38:10.244667 DBI_WR = 0x0
3751 04:38:10.244748 DBI_RD = 0x0
3752 04:38:10.248215 OTF = 0x1
3753 04:38:10.251077 ===================================
3754 04:38:10.254737 ===================================
3755 04:38:10.254817 ANA top config
3756 04:38:10.258021 ===================================
3757 04:38:10.261170 DLL_ASYNC_EN = 0
3758 04:38:10.264726 ALL_SLAVE_EN = 1
3759 04:38:10.267902 NEW_RANK_MODE = 1
3760 04:38:10.267991 DLL_IDLE_MODE = 1
3761 04:38:10.271392 LP45_APHY_COMB_EN = 1
3762 04:38:10.274284 TX_ODT_DIS = 1
3763 04:38:10.277956 NEW_8X_MODE = 1
3764 04:38:10.281487 ===================================
3765 04:38:10.284503 ===================================
3766 04:38:10.288158 data_rate = 1200
3767 04:38:10.288239 CKR = 1
3768 04:38:10.291103 DQ_P2S_RATIO = 8
3769 04:38:10.294650 ===================================
3770 04:38:10.297612 CA_P2S_RATIO = 8
3771 04:38:10.300825 DQ_CA_OPEN = 0
3772 04:38:10.304615 DQ_SEMI_OPEN = 0
3773 04:38:10.307503 CA_SEMI_OPEN = 0
3774 04:38:10.307621 CA_FULL_RATE = 0
3775 04:38:10.311139 DQ_CKDIV4_EN = 1
3776 04:38:10.314570 CA_CKDIV4_EN = 1
3777 04:38:10.317381 CA_PREDIV_EN = 0
3778 04:38:10.320990 PH8_DLY = 0
3779 04:38:10.324389 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3780 04:38:10.324468 DQ_AAMCK_DIV = 4
3781 04:38:10.327592 CA_AAMCK_DIV = 4
3782 04:38:10.331148 CA_ADMCK_DIV = 4
3783 04:38:10.334125 DQ_TRACK_CA_EN = 0
3784 04:38:10.337857 CA_PICK = 600
3785 04:38:10.341294 CA_MCKIO = 600
3786 04:38:10.341374 MCKIO_SEMI = 0
3787 04:38:10.344193 PLL_FREQ = 2288
3788 04:38:10.347859 DQ_UI_PI_RATIO = 32
3789 04:38:10.350936 CA_UI_PI_RATIO = 0
3790 04:38:10.353882 ===================================
3791 04:38:10.357545 ===================================
3792 04:38:10.360543 memory_type:LPDDR4
3793 04:38:10.360625 GP_NUM : 10
3794 04:38:10.364281 SRAM_EN : 1
3795 04:38:10.367498 MD32_EN : 0
3796 04:38:10.370699 ===================================
3797 04:38:10.370781 [ANA_INIT] >>>>>>>>>>>>>>
3798 04:38:10.373872 <<<<<< [CONFIGURE PHASE]: ANA_TX
3799 04:38:10.377072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3800 04:38:10.381030 ===================================
3801 04:38:10.383728 data_rate = 1200,PCW = 0X5800
3802 04:38:10.387595 ===================================
3803 04:38:10.390568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3804 04:38:10.397247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 04:38:10.400749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 04:38:10.407556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3807 04:38:10.410383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3808 04:38:10.413879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3809 04:38:10.413960 [ANA_INIT] flow start
3810 04:38:10.417571 [ANA_INIT] PLL >>>>>>>>
3811 04:38:10.420484 [ANA_INIT] PLL <<<<<<<<
3812 04:38:10.420564 [ANA_INIT] MIDPI >>>>>>>>
3813 04:38:10.423949 [ANA_INIT] MIDPI <<<<<<<<
3814 04:38:10.427108 [ANA_INIT] DLL >>>>>>>>
3815 04:38:10.427187 [ANA_INIT] flow end
3816 04:38:10.433591 ============ LP4 DIFF to SE enter ============
3817 04:38:10.437001 ============ LP4 DIFF to SE exit ============
3818 04:38:10.440271 [ANA_INIT] <<<<<<<<<<<<<
3819 04:38:10.443714 [Flow] Enable top DCM control >>>>>
3820 04:38:10.446864 [Flow] Enable top DCM control <<<<<
3821 04:38:10.450085 Enable DLL master slave shuffle
3822 04:38:10.453630 ==============================================================
3823 04:38:10.456742 Gating Mode config
3824 04:38:10.466393 ==============================================================
3825 04:38:10.466485 Config description:
3826 04:38:10.473839 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3827 04:38:10.480318 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3828 04:38:10.483726 SELPH_MODE 0: By rank 1: By Phase
3829 04:38:10.490636 ==============================================================
3830 04:38:10.493915 GAT_TRACK_EN = 1
3831 04:38:10.496806 RX_GATING_MODE = 2
3832 04:38:10.500371 RX_GATING_TRACK_MODE = 2
3833 04:38:10.503844 SELPH_MODE = 1
3834 04:38:10.503929 PICG_EARLY_EN = 1
3835 04:38:10.507300 VALID_LAT_VALUE = 1
3836 04:38:10.513844 ==============================================================
3837 04:38:10.516828 Enter into Gating configuration >>>>
3838 04:38:10.520360 Exit from Gating configuration <<<<
3839 04:38:10.523921 Enter into DVFS_PRE_config >>>>>
3840 04:38:10.533282 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3841 04:38:10.536904 Exit from DVFS_PRE_config <<<<<
3842 04:38:10.540381 Enter into PICG configuration >>>>
3843 04:38:10.543391 Exit from PICG configuration <<<<
3844 04:38:10.546908 [RX_INPUT] configuration >>>>>
3845 04:38:10.550307 [RX_INPUT] configuration <<<<<
3846 04:38:10.553292 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3847 04:38:10.560074 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3848 04:38:10.566597 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 04:38:10.573460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 04:38:10.580154 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 04:38:10.583846 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 04:38:10.590601 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3853 04:38:10.593899 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3854 04:38:10.596886 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3855 04:38:10.600486 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3856 04:38:10.603407 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3857 04:38:10.609974 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3858 04:38:10.613114 ===================================
3859 04:38:10.616574 LPDDR4 DRAM CONFIGURATION
3860 04:38:10.619992 ===================================
3861 04:38:10.620070 EX_ROW_EN[0] = 0x0
3862 04:38:10.623642 EX_ROW_EN[1] = 0x0
3863 04:38:10.623715 LP4Y_EN = 0x0
3864 04:38:10.626635 WORK_FSP = 0x0
3865 04:38:10.626707 WL = 0x2
3866 04:38:10.630025 RL = 0x2
3867 04:38:10.630141 BL = 0x2
3868 04:38:10.633271 RPST = 0x0
3869 04:38:10.633349 RD_PRE = 0x0
3870 04:38:10.636813 WR_PRE = 0x1
3871 04:38:10.636918 WR_PST = 0x0
3872 04:38:10.639709 DBI_WR = 0x0
3873 04:38:10.643257 DBI_RD = 0x0
3874 04:38:10.643328 OTF = 0x1
3875 04:38:10.646439 ===================================
3876 04:38:10.649873 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3877 04:38:10.653419 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3878 04:38:10.659704 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 04:38:10.663281 ===================================
3880 04:38:10.666224 LPDDR4 DRAM CONFIGURATION
3881 04:38:10.669774 ===================================
3882 04:38:10.669857 EX_ROW_EN[0] = 0x10
3883 04:38:10.672900 EX_ROW_EN[1] = 0x0
3884 04:38:10.672982 LP4Y_EN = 0x0
3885 04:38:10.676369 WORK_FSP = 0x0
3886 04:38:10.676452 WL = 0x2
3887 04:38:10.679905 RL = 0x2
3888 04:38:10.679987 BL = 0x2
3889 04:38:10.682974 RPST = 0x0
3890 04:38:10.683055 RD_PRE = 0x0
3891 04:38:10.686055 WR_PRE = 0x1
3892 04:38:10.686140 WR_PST = 0x0
3893 04:38:10.689598 DBI_WR = 0x0
3894 04:38:10.689671 DBI_RD = 0x0
3895 04:38:10.692839 OTF = 0x1
3896 04:38:10.696284 ===================================
3897 04:38:10.702812 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3898 04:38:10.706255 nWR fixed to 30
3899 04:38:10.710021 [ModeRegInit_LP4] CH0 RK0
3900 04:38:10.710102 [ModeRegInit_LP4] CH0 RK1
3901 04:38:10.713023 [ModeRegInit_LP4] CH1 RK0
3902 04:38:10.716594 [ModeRegInit_LP4] CH1 RK1
3903 04:38:10.716698 match AC timing 17
3904 04:38:10.722893 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3905 04:38:10.726183 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3906 04:38:10.729768 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3907 04:38:10.736256 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3908 04:38:10.739776 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3909 04:38:10.739859 ==
3910 04:38:10.743120 Dram Type= 6, Freq= 0, CH_0, rank 0
3911 04:38:10.746477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3912 04:38:10.746559 ==
3913 04:38:10.753221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3914 04:38:10.759811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3915 04:38:10.763168 [CA 0] Center 36 (5~67) winsize 63
3916 04:38:10.766614 [CA 1] Center 36 (5~67) winsize 63
3917 04:38:10.769540 [CA 2] Center 33 (3~64) winsize 62
3918 04:38:10.773097 [CA 3] Center 33 (2~64) winsize 63
3919 04:38:10.776719 [CA 4] Center 33 (2~64) winsize 63
3920 04:38:10.779573 [CA 5] Center 32 (2~63) winsize 62
3921 04:38:10.779655
3922 04:38:10.783199 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3923 04:38:10.783281
3924 04:38:10.786147 [CATrainingPosCal] consider 1 rank data
3925 04:38:10.789963 u2DelayCellTimex100 = 270/100 ps
3926 04:38:10.793202 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3927 04:38:10.796690 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3928 04:38:10.799752 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3929 04:38:10.802819 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3930 04:38:10.806433 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3931 04:38:10.809799 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3932 04:38:10.809874
3933 04:38:10.816184 CA PerBit enable=1, Macro0, CA PI delay=32
3934 04:38:10.816269
3935 04:38:10.816333 [CBTSetCACLKResult] CA Dly = 32
3936 04:38:10.819928 CS Dly: 5 (0~36)
3937 04:38:10.820009 ==
3938 04:38:10.822703 Dram Type= 6, Freq= 0, CH_0, rank 1
3939 04:38:10.826453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3940 04:38:10.826528 ==
3941 04:38:10.832944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3942 04:38:10.839402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3943 04:38:10.842633 [CA 0] Center 35 (5~66) winsize 62
3944 04:38:10.846067 [CA 1] Center 35 (5~66) winsize 62
3945 04:38:10.849444 [CA 2] Center 34 (3~65) winsize 63
3946 04:38:10.852846 [CA 3] Center 33 (3~64) winsize 62
3947 04:38:10.856131 [CA 4] Center 32 (2~63) winsize 62
3948 04:38:10.859630 [CA 5] Center 32 (2~63) winsize 62
3949 04:38:10.859731
3950 04:38:10.863016 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3951 04:38:10.863126
3952 04:38:10.865969 [CATrainingPosCal] consider 2 rank data
3953 04:38:10.869512 u2DelayCellTimex100 = 270/100 ps
3954 04:38:10.872471 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3955 04:38:10.875950 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3956 04:38:10.879325 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3957 04:38:10.882760 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3958 04:38:10.885928 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3959 04:38:10.893053 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3960 04:38:10.893291
3961 04:38:10.896008 CA PerBit enable=1, Macro0, CA PI delay=32
3962 04:38:10.896303
3963 04:38:10.899602 [CBTSetCACLKResult] CA Dly = 32
3964 04:38:10.899895 CS Dly: 5 (0~36)
3965 04:38:10.900129
3966 04:38:10.902534 ----->DramcWriteLeveling(PI) begin...
3967 04:38:10.902878 ==
3968 04:38:10.906136 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 04:38:10.909421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 04:38:10.913167 ==
3971 04:38:10.913584 Write leveling (Byte 0): 33 => 33
3972 04:38:10.916188 Write leveling (Byte 1): 31 => 31
3973 04:38:10.919675 DramcWriteLeveling(PI) end<-----
3974 04:38:10.920086
3975 04:38:10.920412 ==
3976 04:38:10.922637 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 04:38:10.929767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 04:38:10.930186 ==
3979 04:38:10.930516 [Gating] SW mode calibration
3980 04:38:10.939377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3981 04:38:10.943045 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3982 04:38:10.946002 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 04:38:10.952707 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 04:38:10.955531 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 04:38:10.959032 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
3986 04:38:10.965816 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
3987 04:38:10.969377 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 04:38:10.972563 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 04:38:10.979019 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 04:38:10.982540 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 04:38:10.985656 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 04:38:10.992269 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 04:38:10.995810 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
3994 04:38:10.999346 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3995 04:38:11.005573 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 04:38:11.008869 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 04:38:11.012463 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 04:38:11.018909 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 04:38:11.022312 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 04:38:11.025803 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 04:38:11.032332 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4002 04:38:11.035499 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4003 04:38:11.039020 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 04:38:11.045636 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 04:38:11.048686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 04:38:11.052247 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 04:38:11.055827 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 04:38:11.062476 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 04:38:11.065571 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 04:38:11.069087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 04:38:11.075474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 04:38:11.079328 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 04:38:11.082292 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 04:38:11.088992 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 04:38:11.092122 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 04:38:11.095419 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 04:38:11.102138 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4018 04:38:11.105340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4019 04:38:11.109051 Total UI for P1: 0, mck2ui 16
4020 04:38:11.111980 best dqsien dly found for B0: ( 0, 13, 12)
4021 04:38:11.115473 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 04:38:11.118898 Total UI for P1: 0, mck2ui 16
4023 04:38:11.122547 best dqsien dly found for B1: ( 0, 13, 16)
4024 04:38:11.125433 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4025 04:38:11.128879 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4026 04:38:11.128960
4027 04:38:11.135309 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4028 04:38:11.138818 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4029 04:38:11.138899 [Gating] SW calibration Done
4030 04:38:11.142165 ==
4031 04:38:11.145775 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 04:38:11.148802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 04:38:11.148884 ==
4034 04:38:11.148947 RX Vref Scan: 0
4035 04:38:11.149006
4036 04:38:11.152392 RX Vref 0 -> 0, step: 1
4037 04:38:11.152471
4038 04:38:11.155379 RX Delay -230 -> 252, step: 16
4039 04:38:11.159012 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4040 04:38:11.162175 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4041 04:38:11.169030 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4042 04:38:11.172295 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4043 04:38:11.175775 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4044 04:38:11.178794 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4045 04:38:11.182375 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4046 04:38:11.188865 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4047 04:38:11.192227 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4048 04:38:11.195291 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4049 04:38:11.198918 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4050 04:38:11.205335 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4051 04:38:11.209007 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4052 04:38:11.211896 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4053 04:38:11.215432 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4054 04:38:11.222015 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4055 04:38:11.222096 ==
4056 04:38:11.225426 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 04:38:11.228753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 04:38:11.228833 ==
4059 04:38:11.228897 DQS Delay:
4060 04:38:11.232094 DQS0 = 0, DQS1 = 0
4061 04:38:11.232174 DQM Delay:
4062 04:38:11.235445 DQM0 = 52, DQM1 = 46
4063 04:38:11.235583 DQ Delay:
4064 04:38:11.238458 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4065 04:38:11.242106 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4066 04:38:11.245230 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4067 04:38:11.248752 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4068 04:38:11.248833
4069 04:38:11.248896
4070 04:38:11.248955 ==
4071 04:38:11.252194 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 04:38:11.255244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 04:38:11.255326 ==
4074 04:38:11.255390
4075 04:38:11.255450
4076 04:38:11.258551 TX Vref Scan disable
4077 04:38:11.261942 == TX Byte 0 ==
4078 04:38:11.265602 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4079 04:38:11.268452 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4080 04:38:11.271945 == TX Byte 1 ==
4081 04:38:11.275735 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4082 04:38:11.278513 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4083 04:38:11.278594 ==
4084 04:38:11.282166 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 04:38:11.288876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 04:38:11.288958 ==
4087 04:38:11.289021
4088 04:38:11.289080
4089 04:38:11.289135 TX Vref Scan disable
4090 04:38:11.292454 == TX Byte 0 ==
4091 04:38:11.295903 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4092 04:38:11.302677 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4093 04:38:11.302758 == TX Byte 1 ==
4094 04:38:11.306321 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4095 04:38:11.312902 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4096 04:38:11.313011
4097 04:38:11.313102 [DATLAT]
4098 04:38:11.313189 Freq=600, CH0 RK0
4099 04:38:11.313275
4100 04:38:11.315732 DATLAT Default: 0x9
4101 04:38:11.315812 0, 0xFFFF, sum = 0
4102 04:38:11.319297 1, 0xFFFF, sum = 0
4103 04:38:11.319379 2, 0xFFFF, sum = 0
4104 04:38:11.322337 3, 0xFFFF, sum = 0
4105 04:38:11.325980 4, 0xFFFF, sum = 0
4106 04:38:11.326062 5, 0xFFFF, sum = 0
4107 04:38:11.329479 6, 0xFFFF, sum = 0
4108 04:38:11.329562 7, 0xFFFF, sum = 0
4109 04:38:11.332486 8, 0x0, sum = 1
4110 04:38:11.332563 9, 0x0, sum = 2
4111 04:38:11.332631 10, 0x0, sum = 3
4112 04:38:11.335719 11, 0x0, sum = 4
4113 04:38:11.335801 best_step = 9
4114 04:38:11.335864
4115 04:38:11.335923 ==
4116 04:38:11.339367 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 04:38:11.345773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 04:38:11.345854 ==
4119 04:38:11.345956 RX Vref Scan: 1
4120 04:38:11.346015
4121 04:38:11.349398 RX Vref 0 -> 0, step: 1
4122 04:38:11.349478
4123 04:38:11.352471 RX Delay -163 -> 252, step: 8
4124 04:38:11.352554
4125 04:38:11.355703 Set Vref, RX VrefLevel [Byte0]: 55
4126 04:38:11.359234 [Byte1]: 55
4127 04:38:11.359314
4128 04:38:11.362719 Final RX Vref Byte 0 = 55 to rank0
4129 04:38:11.365724 Final RX Vref Byte 1 = 55 to rank0
4130 04:38:11.369372 Final RX Vref Byte 0 = 55 to rank1
4131 04:38:11.372786 Final RX Vref Byte 1 = 55 to rank1==
4132 04:38:11.375985 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 04:38:11.379069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 04:38:11.379150 ==
4135 04:38:11.382453 DQS Delay:
4136 04:38:11.382533 DQS0 = 0, DQS1 = 0
4137 04:38:11.382596 DQM Delay:
4138 04:38:11.385973 DQM0 = 53, DQM1 = 46
4139 04:38:11.386053 DQ Delay:
4140 04:38:11.388979 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4141 04:38:11.392314 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4142 04:38:11.395831 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4143 04:38:11.399320 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4144 04:38:11.399424
4145 04:38:11.399515
4146 04:38:11.409038 [DQSOSCAuto] RK0, (LSB)MR18= 0x7367, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4147 04:38:11.412692 CH0 RK0: MR19=808, MR18=7367
4148 04:38:11.415731 CH0_RK0: MR19=0x808, MR18=0x7367, DQSOSC=388, MR23=63, INC=174, DEC=116
4149 04:38:11.415812
4150 04:38:11.419136 ----->DramcWriteLeveling(PI) begin...
4151 04:38:11.422145 ==
4152 04:38:11.425742 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 04:38:11.429246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 04:38:11.429327 ==
4155 04:38:11.432143 Write leveling (Byte 0): 36 => 36
4156 04:38:11.435828 Write leveling (Byte 1): 34 => 34
4157 04:38:11.439397 DramcWriteLeveling(PI) end<-----
4158 04:38:11.439503
4159 04:38:11.439618 ==
4160 04:38:11.442113 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 04:38:11.445946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 04:38:11.446028 ==
4163 04:38:11.448842 [Gating] SW mode calibration
4164 04:38:11.455664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4165 04:38:11.462337 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4166 04:38:11.465436 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 04:38:11.468846 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 04:38:11.471893 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 04:38:11.478983 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4170 04:38:11.482651 0 9 16 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4171 04:38:11.485532 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 04:38:11.492232 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 04:38:11.495226 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 04:38:11.498569 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 04:38:11.505507 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 04:38:11.508796 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 04:38:11.511945 0 10 12 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0)
4178 04:38:11.518550 0 10 16 | B1->B0 | 4141 4141 | 0 0 | (0 0) (0 0)
4179 04:38:11.521870 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 04:38:11.525564 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 04:38:11.532318 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 04:38:11.535336 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 04:38:11.538859 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 04:38:11.545376 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 04:38:11.548344 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4186 04:38:11.551823 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 04:38:11.558346 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 04:38:11.561879 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 04:38:11.564888 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 04:38:11.571721 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 04:38:11.575012 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 04:38:11.578503 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 04:38:11.585116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 04:38:11.588464 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 04:38:11.591489 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 04:38:11.595138 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 04:38:11.601777 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 04:38:11.605452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 04:38:11.608476 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 04:38:11.615469 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 04:38:11.618444 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4202 04:38:11.621999 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 04:38:11.625520 Total UI for P1: 0, mck2ui 16
4204 04:38:11.628795 best dqsien dly found for B0: ( 0, 13, 12)
4205 04:38:11.631676 Total UI for P1: 0, mck2ui 16
4206 04:38:11.635279 best dqsien dly found for B1: ( 0, 13, 12)
4207 04:38:11.638365 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4208 04:38:11.641909 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4209 04:38:11.641990
4210 04:38:11.648249 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4211 04:38:11.651637 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4212 04:38:11.655116 [Gating] SW calibration Done
4213 04:38:11.655197 ==
4214 04:38:11.658202 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 04:38:11.661904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 04:38:11.662002 ==
4217 04:38:11.662066 RX Vref Scan: 0
4218 04:38:11.662126
4219 04:38:11.665440 RX Vref 0 -> 0, step: 1
4220 04:38:11.665521
4221 04:38:11.668428 RX Delay -230 -> 252, step: 16
4222 04:38:11.672100 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4223 04:38:11.675080 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4224 04:38:11.681906 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4225 04:38:11.685095 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4226 04:38:11.688337 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4227 04:38:11.691766 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4228 04:38:11.695586 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4229 04:38:11.701921 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4230 04:38:11.705291 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4231 04:38:11.708656 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4232 04:38:11.711662 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4233 04:38:11.718157 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4234 04:38:11.721948 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4235 04:38:11.724797 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4236 04:38:11.728142 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4237 04:38:11.734848 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4238 04:38:11.734929 ==
4239 04:38:11.738645 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 04:38:11.741825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 04:38:11.741938 ==
4242 04:38:11.742001 DQS Delay:
4243 04:38:11.745192 DQS0 = 0, DQS1 = 0
4244 04:38:11.745272 DQM Delay:
4245 04:38:11.748236 DQM0 = 54, DQM1 = 43
4246 04:38:11.748315 DQ Delay:
4247 04:38:11.752144 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4248 04:38:11.754925 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4249 04:38:11.758217 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4250 04:38:11.761811 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4251 04:38:11.761917
4252 04:38:11.762008
4253 04:38:11.762129 ==
4254 04:38:11.764905 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 04:38:11.768598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 04:38:11.768679 ==
4257 04:38:11.768742
4258 04:38:11.768800
4259 04:38:11.772184 TX Vref Scan disable
4260 04:38:11.775084 == TX Byte 0 ==
4261 04:38:11.778740 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4262 04:38:11.781785 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4263 04:38:11.785404 == TX Byte 1 ==
4264 04:38:11.788379 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4265 04:38:11.791877 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4266 04:38:11.791951 ==
4267 04:38:11.794781 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 04:38:11.801683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 04:38:11.801764 ==
4270 04:38:11.801828
4271 04:38:11.801887
4272 04:38:11.801943 TX Vref Scan disable
4273 04:38:11.805715 == TX Byte 0 ==
4274 04:38:11.809107 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4275 04:38:11.816110 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4276 04:38:11.816191 == TX Byte 1 ==
4277 04:38:11.819366 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4278 04:38:11.825727 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4279 04:38:11.825807
4280 04:38:11.825870 [DATLAT]
4281 04:38:11.825929 Freq=600, CH0 RK1
4282 04:38:11.825986
4283 04:38:11.828802 DATLAT Default: 0x9
4284 04:38:11.828882 0, 0xFFFF, sum = 0
4285 04:38:11.832344 1, 0xFFFF, sum = 0
4286 04:38:11.832426 2, 0xFFFF, sum = 0
4287 04:38:11.835927 3, 0xFFFF, sum = 0
4288 04:38:11.836009 4, 0xFFFF, sum = 0
4289 04:38:11.839203 5, 0xFFFF, sum = 0
4290 04:38:11.842479 6, 0xFFFF, sum = 0
4291 04:38:11.842581 7, 0xFFFF, sum = 0
4292 04:38:11.842647 8, 0x0, sum = 1
4293 04:38:11.845809 9, 0x0, sum = 2
4294 04:38:11.845890 10, 0x0, sum = 3
4295 04:38:11.849102 11, 0x0, sum = 4
4296 04:38:11.849183 best_step = 9
4297 04:38:11.849246
4298 04:38:11.849303 ==
4299 04:38:11.852611 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 04:38:11.858946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 04:38:11.859027 ==
4302 04:38:11.859090 RX Vref Scan: 0
4303 04:38:11.859148
4304 04:38:11.862206 RX Vref 0 -> 0, step: 1
4305 04:38:11.862312
4306 04:38:11.865359 RX Delay -163 -> 252, step: 8
4307 04:38:11.869158 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4308 04:38:11.875377 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4309 04:38:11.879136 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4310 04:38:11.882053 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4311 04:38:11.885870 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4312 04:38:11.888826 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4313 04:38:11.895673 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4314 04:38:11.898837 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4315 04:38:11.902388 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4316 04:38:11.905373 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4317 04:38:11.908925 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4318 04:38:11.915527 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4319 04:38:11.918837 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4320 04:38:11.922188 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4321 04:38:11.925874 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4322 04:38:11.928526 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4323 04:38:11.932209 ==
4324 04:38:11.935185 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 04:38:11.938726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 04:38:11.938805 ==
4327 04:38:11.938868 DQS Delay:
4328 04:38:11.942205 DQS0 = 0, DQS1 = 0
4329 04:38:11.942285 DQM Delay:
4330 04:38:11.945172 DQM0 = 54, DQM1 = 46
4331 04:38:11.945251 DQ Delay:
4332 04:38:11.948602 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4333 04:38:11.952110 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =64
4334 04:38:11.955498 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =36
4335 04:38:11.958636 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4336 04:38:11.958740
4337 04:38:11.958804
4338 04:38:11.965047 [DQSOSCAuto] RK1, (LSB)MR18= 0x6222, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4339 04:38:11.968420 CH0 RK1: MR19=808, MR18=6222
4340 04:38:11.975437 CH0_RK1: MR19=0x808, MR18=0x6222, DQSOSC=391, MR23=63, INC=171, DEC=114
4341 04:38:11.978568 [RxdqsGatingPostProcess] freq 600
4342 04:38:11.985638 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4343 04:38:11.985719 Pre-setting of DQS Precalculation
4344 04:38:11.992131 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4345 04:38:11.992212 ==
4346 04:38:11.995199 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 04:38:11.998673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 04:38:11.998753 ==
4349 04:38:12.005297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 04:38:12.011804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4351 04:38:12.015375 [CA 0] Center 36 (5~67) winsize 63
4352 04:38:12.018247 [CA 1] Center 36 (5~67) winsize 63
4353 04:38:12.021581 [CA 2] Center 35 (4~66) winsize 63
4354 04:38:12.025150 [CA 3] Center 34 (4~65) winsize 62
4355 04:38:12.028315 [CA 4] Center 34 (4~65) winsize 62
4356 04:38:12.031709 [CA 5] Center 34 (3~65) winsize 63
4357 04:38:12.031790
4358 04:38:12.035087 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4359 04:38:12.035168
4360 04:38:12.038312 [CATrainingPosCal] consider 1 rank data
4361 04:38:12.041679 u2DelayCellTimex100 = 270/100 ps
4362 04:38:12.045121 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4363 04:38:12.048795 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4364 04:38:12.051745 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4365 04:38:12.055282 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4366 04:38:12.058370 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4367 04:38:12.061890 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4368 04:38:12.061971
4369 04:38:12.068101 CA PerBit enable=1, Macro0, CA PI delay=34
4370 04:38:12.068182
4371 04:38:12.068247 [CBTSetCACLKResult] CA Dly = 34
4372 04:38:12.071406 CS Dly: 6 (0~37)
4373 04:38:12.071487 ==
4374 04:38:12.074903 Dram Type= 6, Freq= 0, CH_1, rank 1
4375 04:38:12.078520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 04:38:12.078607 ==
4377 04:38:12.085204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 04:38:12.091459 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4379 04:38:12.094908 [CA 0] Center 36 (5~67) winsize 63
4380 04:38:12.098291 [CA 1] Center 36 (5~67) winsize 63
4381 04:38:12.101765 [CA 2] Center 35 (4~66) winsize 63
4382 04:38:12.104989 [CA 3] Center 34 (4~65) winsize 62
4383 04:38:12.107913 [CA 4] Center 35 (4~66) winsize 63
4384 04:38:12.111511 [CA 5] Center 34 (3~65) winsize 63
4385 04:38:12.111630
4386 04:38:12.114485 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4387 04:38:12.114566
4388 04:38:12.117809 [CATrainingPosCal] consider 2 rank data
4389 04:38:12.121450 u2DelayCellTimex100 = 270/100 ps
4390 04:38:12.124841 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4391 04:38:12.127946 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4392 04:38:12.131038 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4393 04:38:12.134383 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4394 04:38:12.137929 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4395 04:38:12.141518 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4396 04:38:12.144334
4397 04:38:12.147717 CA PerBit enable=1, Macro0, CA PI delay=34
4398 04:38:12.147798
4399 04:38:12.150983 [CBTSetCACLKResult] CA Dly = 34
4400 04:38:12.151063 CS Dly: 6 (0~38)
4401 04:38:12.151128
4402 04:38:12.154437 ----->DramcWriteLeveling(PI) begin...
4403 04:38:12.154519 ==
4404 04:38:12.157619 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 04:38:12.161141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 04:38:12.164633 ==
4407 04:38:12.164714 Write leveling (Byte 0): 31 => 31
4408 04:38:12.168182 Write leveling (Byte 1): 31 => 31
4409 04:38:12.171078 DramcWriteLeveling(PI) end<-----
4410 04:38:12.171166
4411 04:38:12.171238 ==
4412 04:38:12.174543 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 04:38:12.181357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 04:38:12.181439 ==
4415 04:38:12.181504 [Gating] SW mode calibration
4416 04:38:12.190777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 04:38:12.194439 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4418 04:38:12.200817 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 04:38:12.204054 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 04:38:12.207317 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 04:38:12.214140 0 9 12 | B1->B0 | 2e2e 2a2a | 0 0 | (1 0) (0 0)
4422 04:38:12.217885 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 04:38:12.221147 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 04:38:12.224161 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 04:38:12.231041 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 04:38:12.234547 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 04:38:12.237431 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 04:38:12.244503 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4429 04:38:12.247520 0 10 12 | B1->B0 | 3636 3a3a | 0 0 | (1 1) (0 0)
4430 04:38:12.251213 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 04:38:12.257379 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 04:38:12.260561 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 04:38:12.264178 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 04:38:12.270487 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 04:38:12.273921 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 04:38:12.277369 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 04:38:12.283645 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4438 04:38:12.287049 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 04:38:12.290587 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 04:38:12.297169 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 04:38:12.300106 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 04:38:12.303875 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 04:38:12.310139 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 04:38:12.313607 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 04:38:12.317038 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 04:38:12.323219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 04:38:12.326957 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 04:38:12.329886 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 04:38:12.336765 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 04:38:12.340416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 04:38:12.343193 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 04:38:12.349927 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 04:38:12.353343 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 04:38:12.356482 Total UI for P1: 0, mck2ui 16
4455 04:38:12.359906 best dqsien dly found for B0: ( 0, 13, 10)
4456 04:38:12.362840 Total UI for P1: 0, mck2ui 16
4457 04:38:12.366430 best dqsien dly found for B1: ( 0, 13, 10)
4458 04:38:12.369903 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4459 04:38:12.372771 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4460 04:38:12.372851
4461 04:38:12.376232 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4462 04:38:12.379972 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4463 04:38:12.383258 [Gating] SW calibration Done
4464 04:38:12.383364 ==
4465 04:38:12.385886 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 04:38:12.392657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 04:38:12.392739 ==
4468 04:38:12.392802 RX Vref Scan: 0
4469 04:38:12.392861
4470 04:38:12.396042 RX Vref 0 -> 0, step: 1
4471 04:38:12.396121
4472 04:38:12.399690 RX Delay -230 -> 252, step: 16
4473 04:38:12.402567 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4474 04:38:12.405998 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4475 04:38:12.409442 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4476 04:38:12.415968 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4477 04:38:12.419012 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4478 04:38:12.422465 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4479 04:38:12.425786 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4480 04:38:12.432565 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4481 04:38:12.435762 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4482 04:38:12.438781 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4483 04:38:12.442285 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4484 04:38:12.449150 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4485 04:38:12.452279 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4486 04:38:12.455394 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4487 04:38:12.458979 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4488 04:38:12.465483 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4489 04:38:12.465565 ==
4490 04:38:12.469022 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 04:38:12.472093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 04:38:12.472174 ==
4493 04:38:12.472238 DQS Delay:
4494 04:38:12.475610 DQS0 = 0, DQS1 = 0
4495 04:38:12.475691 DQM Delay:
4496 04:38:12.478537 DQM0 = 52, DQM1 = 49
4497 04:38:12.478617 DQ Delay:
4498 04:38:12.481974 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4499 04:38:12.485248 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4500 04:38:12.488498 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4501 04:38:12.491907 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4502 04:38:12.491987
4503 04:38:12.492050
4504 04:38:12.492108 ==
4505 04:38:12.495558 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 04:38:12.498426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 04:38:12.498507 ==
4508 04:38:12.498571
4509 04:38:12.498629
4510 04:38:12.501996 TX Vref Scan disable
4511 04:38:12.505415 == TX Byte 0 ==
4512 04:38:12.508731 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4513 04:38:12.511851 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4514 04:38:12.515557 == TX Byte 1 ==
4515 04:38:12.518485 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4516 04:38:12.521562 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4517 04:38:12.521643 ==
4518 04:38:12.525051 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 04:38:12.531874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 04:38:12.531955 ==
4521 04:38:12.532019
4522 04:38:12.532078
4523 04:38:12.532135 TX Vref Scan disable
4524 04:38:12.536420 == TX Byte 0 ==
4525 04:38:12.539494 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4526 04:38:12.545849 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4527 04:38:12.545931 == TX Byte 1 ==
4528 04:38:12.549238 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 04:38:12.555947 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 04:38:12.556029
4531 04:38:12.556094 [DATLAT]
4532 04:38:12.556153 Freq=600, CH1 RK0
4533 04:38:12.556211
4534 04:38:12.559169 DATLAT Default: 0x9
4535 04:38:12.559251 0, 0xFFFF, sum = 0
4536 04:38:12.562905 1, 0xFFFF, sum = 0
4537 04:38:12.562988 2, 0xFFFF, sum = 0
4538 04:38:12.565840 3, 0xFFFF, sum = 0
4539 04:38:12.569573 4, 0xFFFF, sum = 0
4540 04:38:12.569655 5, 0xFFFF, sum = 0
4541 04:38:12.572413 6, 0xFFFF, sum = 0
4542 04:38:12.572495 7, 0xFFFF, sum = 0
4543 04:38:12.575967 8, 0x0, sum = 1
4544 04:38:12.576049 9, 0x0, sum = 2
4545 04:38:12.576115 10, 0x0, sum = 3
4546 04:38:12.578998 11, 0x0, sum = 4
4547 04:38:12.579080 best_step = 9
4548 04:38:12.579144
4549 04:38:12.579203 ==
4550 04:38:12.582720 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 04:38:12.589055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 04:38:12.589137 ==
4553 04:38:12.589201 RX Vref Scan: 1
4554 04:38:12.589260
4555 04:38:12.592442 RX Vref 0 -> 0, step: 1
4556 04:38:12.592523
4557 04:38:12.596019 RX Delay -147 -> 252, step: 8
4558 04:38:12.596100
4559 04:38:12.599031 Set Vref, RX VrefLevel [Byte0]: 56
4560 04:38:12.602542 [Byte1]: 54
4561 04:38:12.602624
4562 04:38:12.605927 Final RX Vref Byte 0 = 56 to rank0
4563 04:38:12.608692 Final RX Vref Byte 1 = 54 to rank0
4564 04:38:12.612367 Final RX Vref Byte 0 = 56 to rank1
4565 04:38:12.615506 Final RX Vref Byte 1 = 54 to rank1==
4566 04:38:12.619351 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 04:38:12.622425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 04:38:12.622507 ==
4569 04:38:12.625829 DQS Delay:
4570 04:38:12.625910 DQS0 = 0, DQS1 = 0
4571 04:38:12.625974 DQM Delay:
4572 04:38:12.629411 DQM0 = 48, DQM1 = 44
4573 04:38:12.629492 DQ Delay:
4574 04:38:12.632425 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4575 04:38:12.636109 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4576 04:38:12.638946 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4577 04:38:12.642654 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4578 04:38:12.642735
4579 04:38:12.642799
4580 04:38:12.652629 [DQSOSCAuto] RK0, (LSB)MR18= 0x456a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4581 04:38:12.656022 CH1 RK0: MR19=808, MR18=456A
4582 04:38:12.659291 CH1_RK0: MR19=0x808, MR18=0x456A, DQSOSC=389, MR23=63, INC=173, DEC=115
4583 04:38:12.659373
4584 04:38:12.662491 ----->DramcWriteLeveling(PI) begin...
4585 04:38:12.665655 ==
4586 04:38:12.669318 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 04:38:12.672381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 04:38:12.672462 ==
4589 04:38:12.675429 Write leveling (Byte 0): 30 => 30
4590 04:38:12.679074 Write leveling (Byte 1): 30 => 30
4591 04:38:12.682113 DramcWriteLeveling(PI) end<-----
4592 04:38:12.682193
4593 04:38:12.682257 ==
4594 04:38:12.685781 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 04:38:12.688942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 04:38:12.689024 ==
4597 04:38:12.692365 [Gating] SW mode calibration
4598 04:38:12.698918 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4599 04:38:12.706037 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4600 04:38:12.708797 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 04:38:12.712548 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 04:38:12.715748 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 04:38:12.721944 0 9 12 | B1->B0 | 2c2c 3030 | 1 0 | (1 0) (0 1)
4604 04:38:12.725173 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 04:38:12.728769 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 04:38:12.735769 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 04:38:12.738730 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 04:38:12.742336 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 04:38:12.748852 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 04:38:12.752501 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 04:38:12.755593 0 10 12 | B1->B0 | 3a3a 3434 | 0 0 | (0 0) (0 0)
4612 04:38:12.761964 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 04:38:12.765443 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 04:38:12.768528 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 04:38:12.775359 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 04:38:12.778907 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 04:38:12.781933 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 04:38:12.788736 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 04:38:12.792004 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4620 04:38:12.795017 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 04:38:12.802082 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 04:38:12.805082 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 04:38:12.808727 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 04:38:12.815079 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 04:38:12.818610 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 04:38:12.821927 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 04:38:12.828456 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 04:38:12.831758 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 04:38:12.834950 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 04:38:12.841864 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 04:38:12.845264 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 04:38:12.848193 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 04:38:12.854779 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 04:38:12.858536 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4635 04:38:12.861571 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4636 04:38:12.864945 Total UI for P1: 0, mck2ui 16
4637 04:38:12.867875 best dqsien dly found for B1: ( 0, 13, 8)
4638 04:38:12.871495 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 04:38:12.874588 Total UI for P1: 0, mck2ui 16
4640 04:38:12.878104 best dqsien dly found for B0: ( 0, 13, 12)
4641 04:38:12.881076 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4642 04:38:12.887705 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4643 04:38:12.887810
4644 04:38:12.891452 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4645 04:38:12.894789 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4646 04:38:12.897994 [Gating] SW calibration Done
4647 04:38:12.898076 ==
4648 04:38:12.901189 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 04:38:12.904369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 04:38:12.904451 ==
4651 04:38:12.908057 RX Vref Scan: 0
4652 04:38:12.908126
4653 04:38:12.908186 RX Vref 0 -> 0, step: 1
4654 04:38:12.908242
4655 04:38:12.910893 RX Delay -230 -> 252, step: 16
4656 04:38:12.914473 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4657 04:38:12.920944 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4658 04:38:12.924475 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4659 04:38:12.928092 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4660 04:38:12.931151 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4661 04:38:12.934697 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4662 04:38:12.940845 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4663 04:38:12.944175 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4664 04:38:12.947670 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4665 04:38:12.950998 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4666 04:38:12.957571 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4667 04:38:12.961076 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4668 04:38:12.964084 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4669 04:38:12.967814 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4670 04:38:12.974173 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4671 04:38:12.977687 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4672 04:38:12.977768 ==
4673 04:38:12.980603 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 04:38:12.984299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 04:38:12.984381 ==
4676 04:38:12.987682 DQS Delay:
4677 04:38:12.987762 DQS0 = 0, DQS1 = 0
4678 04:38:12.987826 DQM Delay:
4679 04:38:12.990779 DQM0 = 51, DQM1 = 48
4680 04:38:12.990860 DQ Delay:
4681 04:38:12.994235 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4682 04:38:12.997633 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4683 04:38:13.000550 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4684 04:38:13.003892 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4685 04:38:13.003973
4686 04:38:13.004037
4687 04:38:13.004096 ==
4688 04:38:13.007259 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 04:38:13.013981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 04:38:13.014063 ==
4691 04:38:13.014127
4692 04:38:13.014185
4693 04:38:13.014241 TX Vref Scan disable
4694 04:38:13.017430 == TX Byte 0 ==
4695 04:38:13.020866 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4696 04:38:13.024044 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4697 04:38:13.027490 == TX Byte 1 ==
4698 04:38:13.031072 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4699 04:38:13.033925 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4700 04:38:13.037798 ==
4701 04:38:13.040738 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 04:38:13.044238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 04:38:13.044320 ==
4704 04:38:13.044384
4705 04:38:13.044442
4706 04:38:13.047595 TX Vref Scan disable
4707 04:38:13.047689 == TX Byte 0 ==
4708 04:38:13.054405 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4709 04:38:13.057670 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4710 04:38:13.057751 == TX Byte 1 ==
4711 04:38:13.064123 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4712 04:38:13.067229 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4713 04:38:13.067311
4714 04:38:13.067374 [DATLAT]
4715 04:38:13.070640 Freq=600, CH1 RK1
4716 04:38:13.070721
4717 04:38:13.070786 DATLAT Default: 0x9
4718 04:38:13.074234 0, 0xFFFF, sum = 0
4719 04:38:13.074316 1, 0xFFFF, sum = 0
4720 04:38:13.077165 2, 0xFFFF, sum = 0
4721 04:38:13.077248 3, 0xFFFF, sum = 0
4722 04:38:13.080951 4, 0xFFFF, sum = 0
4723 04:38:13.081034 5, 0xFFFF, sum = 0
4724 04:38:13.083836 6, 0xFFFF, sum = 0
4725 04:38:13.087299 7, 0xFFFF, sum = 0
4726 04:38:13.087382 8, 0x0, sum = 1
4727 04:38:13.087447 9, 0x0, sum = 2
4728 04:38:13.090535 10, 0x0, sum = 3
4729 04:38:13.090617 11, 0x0, sum = 4
4730 04:38:13.094122 best_step = 9
4731 04:38:13.094203
4732 04:38:13.094267 ==
4733 04:38:13.097147 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 04:38:13.100469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 04:38:13.100552 ==
4736 04:38:13.103901 RX Vref Scan: 0
4737 04:38:13.103982
4738 04:38:13.104045 RX Vref 0 -> 0, step: 1
4739 04:38:13.104104
4740 04:38:13.107302 RX Delay -163 -> 252, step: 8
4741 04:38:13.114141 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4742 04:38:13.117799 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4743 04:38:13.121123 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4744 04:38:13.124738 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4745 04:38:13.127828 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4746 04:38:13.134239 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4747 04:38:13.138084 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4748 04:38:13.140733 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4749 04:38:13.144335 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4750 04:38:13.148026 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4751 04:38:13.154609 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4752 04:38:13.157424 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4753 04:38:13.161092 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4754 04:38:13.164421 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4755 04:38:13.170866 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4756 04:38:13.174468 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4757 04:38:13.174573 ==
4758 04:38:13.177379 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 04:38:13.180922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 04:38:13.181003 ==
4761 04:38:13.183964 DQS Delay:
4762 04:38:13.184045 DQS0 = 0, DQS1 = 0
4763 04:38:13.184108 DQM Delay:
4764 04:38:13.187396 DQM0 = 49, DQM1 = 45
4765 04:38:13.187502 DQ Delay:
4766 04:38:13.191149 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4767 04:38:13.194009 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4768 04:38:13.197524 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4769 04:38:13.201210 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4770 04:38:13.201291
4771 04:38:13.201355
4772 04:38:13.210625 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4773 04:38:13.210708 CH1 RK1: MR19=808, MR18=6D24
4774 04:38:13.217803 CH1_RK1: MR19=0x808, MR18=0x6D24, DQSOSC=389, MR23=63, INC=173, DEC=115
4775 04:38:13.220585 [RxdqsGatingPostProcess] freq 600
4776 04:38:13.227259 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4777 04:38:13.231006 Pre-setting of DQS Precalculation
4778 04:38:13.234019 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4779 04:38:13.240964 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4780 04:38:13.250404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4781 04:38:13.250486
4782 04:38:13.250550
4783 04:38:13.253971 [Calibration Summary] 1200 Mbps
4784 04:38:13.254052 CH 0, Rank 0
4785 04:38:13.257068 SW Impedance : PASS
4786 04:38:13.257150 DUTY Scan : NO K
4787 04:38:13.260542 ZQ Calibration : PASS
4788 04:38:13.264037 Jitter Meter : NO K
4789 04:38:13.264118 CBT Training : PASS
4790 04:38:13.267446 Write leveling : PASS
4791 04:38:13.267584 RX DQS gating : PASS
4792 04:38:13.270854 RX DQ/DQS(RDDQC) : PASS
4793 04:38:13.274024 TX DQ/DQS : PASS
4794 04:38:13.274105 RX DATLAT : PASS
4795 04:38:13.277171 RX DQ/DQS(Engine): PASS
4796 04:38:13.280479 TX OE : NO K
4797 04:38:13.280560 All Pass.
4798 04:38:13.280625
4799 04:38:13.280683 CH 0, Rank 1
4800 04:38:13.283813 SW Impedance : PASS
4801 04:38:13.287163 DUTY Scan : NO K
4802 04:38:13.287270 ZQ Calibration : PASS
4803 04:38:13.290855 Jitter Meter : NO K
4804 04:38:13.293695 CBT Training : PASS
4805 04:38:13.293776 Write leveling : PASS
4806 04:38:13.297328 RX DQS gating : PASS
4807 04:38:13.300197 RX DQ/DQS(RDDQC) : PASS
4808 04:38:13.300279 TX DQ/DQS : PASS
4809 04:38:13.303976 RX DATLAT : PASS
4810 04:38:13.306868 RX DQ/DQS(Engine): PASS
4811 04:38:13.306949 TX OE : NO K
4812 04:38:13.307014 All Pass.
4813 04:38:13.310375
4814 04:38:13.310456 CH 1, Rank 0
4815 04:38:13.313465 SW Impedance : PASS
4816 04:38:13.313546 DUTY Scan : NO K
4817 04:38:13.317111 ZQ Calibration : PASS
4818 04:38:13.317192 Jitter Meter : NO K
4819 04:38:13.320019 CBT Training : PASS
4820 04:38:13.323742 Write leveling : PASS
4821 04:38:13.323869 RX DQS gating : PASS
4822 04:38:13.327095 RX DQ/DQS(RDDQC) : PASS
4823 04:38:13.330261 TX DQ/DQS : PASS
4824 04:38:13.330332 RX DATLAT : PASS
4825 04:38:13.333316 RX DQ/DQS(Engine): PASS
4826 04:38:13.336820 TX OE : NO K
4827 04:38:13.336894 All Pass.
4828 04:38:13.336954
4829 04:38:13.337011 CH 1, Rank 1
4830 04:38:13.340482 SW Impedance : PASS
4831 04:38:13.343562 DUTY Scan : NO K
4832 04:38:13.343643 ZQ Calibration : PASS
4833 04:38:13.346758 Jitter Meter : NO K
4834 04:38:13.350168 CBT Training : PASS
4835 04:38:13.350248 Write leveling : PASS
4836 04:38:13.353403 RX DQS gating : PASS
4837 04:38:13.356848 RX DQ/DQS(RDDQC) : PASS
4838 04:38:13.356929 TX DQ/DQS : PASS
4839 04:38:13.360445 RX DATLAT : PASS
4840 04:38:13.363733 RX DQ/DQS(Engine): PASS
4841 04:38:13.363813 TX OE : NO K
4842 04:38:13.363876 All Pass.
4843 04:38:13.366628
4844 04:38:13.366707 DramC Write-DBI off
4845 04:38:13.370000 PER_BANK_REFRESH: Hybrid Mode
4846 04:38:13.370081 TX_TRACKING: ON
4847 04:38:13.379945 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4848 04:38:13.383254 [FAST_K] Save calibration result to emmc
4849 04:38:13.386733 dramc_set_vcore_voltage set vcore to 662500
4850 04:38:13.389645 Read voltage for 933, 3
4851 04:38:13.389718 Vio18 = 0
4852 04:38:13.393003 Vcore = 662500
4853 04:38:13.393076 Vdram = 0
4854 04:38:13.393136 Vddq = 0
4855 04:38:13.393193 Vmddr = 0
4856 04:38:13.399703 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4857 04:38:13.406763 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4858 04:38:13.406843 MEM_TYPE=3, freq_sel=17
4859 04:38:13.409880 sv_algorithm_assistance_LP4_1600
4860 04:38:13.413406 ============ PULL DRAM RESETB DOWN ============
4861 04:38:13.419983 ========== PULL DRAM RESETB DOWN end =========
4862 04:38:13.422923 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4863 04:38:13.426501 ===================================
4864 04:38:13.430054 LPDDR4 DRAM CONFIGURATION
4865 04:38:13.433043 ===================================
4866 04:38:13.433113 EX_ROW_EN[0] = 0x0
4867 04:38:13.436606 EX_ROW_EN[1] = 0x0
4868 04:38:13.436687 LP4Y_EN = 0x0
4869 04:38:13.439625 WORK_FSP = 0x0
4870 04:38:13.439758 WL = 0x3
4871 04:38:13.442772 RL = 0x3
4872 04:38:13.442852 BL = 0x2
4873 04:38:13.446715 RPST = 0x0
4874 04:38:13.449411 RD_PRE = 0x0
4875 04:38:13.449490 WR_PRE = 0x1
4876 04:38:13.452920 WR_PST = 0x0
4877 04:38:13.453000 DBI_WR = 0x0
4878 04:38:13.456059 DBI_RD = 0x0
4879 04:38:13.456140 OTF = 0x1
4880 04:38:13.459472 ===================================
4881 04:38:13.463061 ===================================
4882 04:38:13.466514 ANA top config
4883 04:38:13.466595 ===================================
4884 04:38:13.469419 DLL_ASYNC_EN = 0
4885 04:38:13.472963 ALL_SLAVE_EN = 1
4886 04:38:13.475868 NEW_RANK_MODE = 1
4887 04:38:13.479241 DLL_IDLE_MODE = 1
4888 04:38:13.479321 LP45_APHY_COMB_EN = 1
4889 04:38:13.482742 TX_ODT_DIS = 1
4890 04:38:13.486383 NEW_8X_MODE = 1
4891 04:38:13.489829 ===================================
4892 04:38:13.492566 ===================================
4893 04:38:13.496123 data_rate = 1866
4894 04:38:13.499555 CKR = 1
4895 04:38:13.499649 DQ_P2S_RATIO = 8
4896 04:38:13.502549 ===================================
4897 04:38:13.505983 CA_P2S_RATIO = 8
4898 04:38:13.509555 DQ_CA_OPEN = 0
4899 04:38:13.512514 DQ_SEMI_OPEN = 0
4900 04:38:13.516101 CA_SEMI_OPEN = 0
4901 04:38:13.519149 CA_FULL_RATE = 0
4902 04:38:13.519230 DQ_CKDIV4_EN = 1
4903 04:38:13.522545 CA_CKDIV4_EN = 1
4904 04:38:13.526176 CA_PREDIV_EN = 0
4905 04:38:13.529268 PH8_DLY = 0
4906 04:38:13.532308 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4907 04:38:13.535617 DQ_AAMCK_DIV = 4
4908 04:38:13.535697 CA_AAMCK_DIV = 4
4909 04:38:13.539146 CA_ADMCK_DIV = 4
4910 04:38:13.542728 DQ_TRACK_CA_EN = 0
4911 04:38:13.545647 CA_PICK = 933
4912 04:38:13.549175 CA_MCKIO = 933
4913 04:38:13.552593 MCKIO_SEMI = 0
4914 04:38:13.555716 PLL_FREQ = 3732
4915 04:38:13.555831 DQ_UI_PI_RATIO = 32
4916 04:38:13.559265 CA_UI_PI_RATIO = 0
4917 04:38:13.562702 ===================================
4918 04:38:13.565675 ===================================
4919 04:38:13.569166 memory_type:LPDDR4
4920 04:38:13.572429 GP_NUM : 10
4921 04:38:13.572510 SRAM_EN : 1
4922 04:38:13.576004 MD32_EN : 0
4923 04:38:13.579010 ===================================
4924 04:38:13.582656 [ANA_INIT] >>>>>>>>>>>>>>
4925 04:38:13.582736 <<<<<< [CONFIGURE PHASE]: ANA_TX
4926 04:38:13.585988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4927 04:38:13.588964 ===================================
4928 04:38:13.592470 data_rate = 1866,PCW = 0X8f00
4929 04:38:13.595731 ===================================
4930 04:38:13.599256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4931 04:38:13.606003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 04:38:13.612209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 04:38:13.615715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4934 04:38:13.619196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4935 04:38:13.622970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4936 04:38:13.625794 [ANA_INIT] flow start
4937 04:38:13.625874 [ANA_INIT] PLL >>>>>>>>
4938 04:38:13.628895 [ANA_INIT] PLL <<<<<<<<
4939 04:38:13.632682 [ANA_INIT] MIDPI >>>>>>>>
4940 04:38:13.632762 [ANA_INIT] MIDPI <<<<<<<<
4941 04:38:13.635497 [ANA_INIT] DLL >>>>>>>>
4942 04:38:13.639252 [ANA_INIT] flow end
4943 04:38:13.642477 ============ LP4 DIFF to SE enter ============
4944 04:38:13.645936 ============ LP4 DIFF to SE exit ============
4945 04:38:13.649310 [ANA_INIT] <<<<<<<<<<<<<
4946 04:38:13.652438 [Flow] Enable top DCM control >>>>>
4947 04:38:13.655552 [Flow] Enable top DCM control <<<<<
4948 04:38:13.659074 Enable DLL master slave shuffle
4949 04:38:13.662712 ==============================================================
4950 04:38:13.665421 Gating Mode config
4951 04:38:13.672215 ==============================================================
4952 04:38:13.672296 Config description:
4953 04:38:13.682208 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4954 04:38:13.688770 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4955 04:38:13.692350 SELPH_MODE 0: By rank 1: By Phase
4956 04:38:13.698967 ==============================================================
4957 04:38:13.701813 GAT_TRACK_EN = 1
4958 04:38:13.705124 RX_GATING_MODE = 2
4959 04:38:13.708862 RX_GATING_TRACK_MODE = 2
4960 04:38:13.712193 SELPH_MODE = 1
4961 04:38:13.715224 PICG_EARLY_EN = 1
4962 04:38:13.718734 VALID_LAT_VALUE = 1
4963 04:38:13.722259 ==============================================================
4964 04:38:13.725226 Enter into Gating configuration >>>>
4965 04:38:13.728876 Exit from Gating configuration <<<<
4966 04:38:13.731572 Enter into DVFS_PRE_config >>>>>
4967 04:38:13.745479 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4968 04:38:13.748317 Exit from DVFS_PRE_config <<<<<
4969 04:38:13.748399 Enter into PICG configuration >>>>
4970 04:38:13.751559 Exit from PICG configuration <<<<
4971 04:38:13.755057 [RX_INPUT] configuration >>>>>
4972 04:38:13.758721 [RX_INPUT] configuration <<<<<
4973 04:38:13.765264 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4974 04:38:13.768397 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4975 04:38:13.774914 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 04:38:13.781695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 04:38:13.788370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 04:38:13.795224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 04:38:13.798284 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4980 04:38:13.801813 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4981 04:38:13.805015 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4982 04:38:13.811469 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4983 04:38:13.815197 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4984 04:38:13.818362 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 04:38:13.821817 ===================================
4986 04:38:13.824771 LPDDR4 DRAM CONFIGURATION
4987 04:38:13.828056 ===================================
4988 04:38:13.831452 EX_ROW_EN[0] = 0x0
4989 04:38:13.831559 EX_ROW_EN[1] = 0x0
4990 04:38:13.835051 LP4Y_EN = 0x0
4991 04:38:13.835133 WORK_FSP = 0x0
4992 04:38:13.838172 WL = 0x3
4993 04:38:13.838253 RL = 0x3
4994 04:38:13.841714 BL = 0x2
4995 04:38:13.841795 RPST = 0x0
4996 04:38:13.844732 RD_PRE = 0x0
4997 04:38:13.844833 WR_PRE = 0x1
4998 04:38:13.848414 WR_PST = 0x0
4999 04:38:13.848494 DBI_WR = 0x0
5000 04:38:13.851427 DBI_RD = 0x0
5001 04:38:13.851508 OTF = 0x1
5002 04:38:13.854945 ===================================
5003 04:38:13.858399 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5004 04:38:13.865158 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5005 04:38:13.868013 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 04:38:13.871652 ===================================
5007 04:38:13.874625 LPDDR4 DRAM CONFIGURATION
5008 04:38:13.878193 ===================================
5009 04:38:13.878274 EX_ROW_EN[0] = 0x10
5010 04:38:13.881281 EX_ROW_EN[1] = 0x0
5011 04:38:13.884974 LP4Y_EN = 0x0
5012 04:38:13.885112 WORK_FSP = 0x0
5013 04:38:13.887842 WL = 0x3
5014 04:38:13.887922 RL = 0x3
5015 04:38:13.891429 BL = 0x2
5016 04:38:13.891512 RPST = 0x0
5017 04:38:13.894412 RD_PRE = 0x0
5018 04:38:13.894493 WR_PRE = 0x1
5019 04:38:13.898040 WR_PST = 0x0
5020 04:38:13.898121 DBI_WR = 0x0
5021 04:38:13.901252 DBI_RD = 0x0
5022 04:38:13.901332 OTF = 0x1
5023 04:38:13.904424 ===================================
5024 04:38:13.911345 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5025 04:38:13.915116 nWR fixed to 30
5026 04:38:13.918482 [ModeRegInit_LP4] CH0 RK0
5027 04:38:13.918564 [ModeRegInit_LP4] CH0 RK1
5028 04:38:13.921823 [ModeRegInit_LP4] CH1 RK0
5029 04:38:13.925236 [ModeRegInit_LP4] CH1 RK1
5030 04:38:13.925317 match AC timing 9
5031 04:38:13.932285 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5032 04:38:13.935244 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5033 04:38:13.938523 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5034 04:38:13.945520 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5035 04:38:13.949134 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5036 04:38:13.949228 ==
5037 04:38:13.952053 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 04:38:13.955579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 04:38:13.955661 ==
5040 04:38:13.962146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 04:38:13.968776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5042 04:38:13.972079 [CA 0] Center 37 (6~68) winsize 63
5043 04:38:13.975556 [CA 1] Center 37 (7~68) winsize 62
5044 04:38:13.978394 [CA 2] Center 34 (4~65) winsize 62
5045 04:38:13.981992 [CA 3] Center 34 (3~65) winsize 63
5046 04:38:13.985737 [CA 4] Center 33 (3~64) winsize 62
5047 04:38:13.988617 [CA 5] Center 32 (2~62) winsize 61
5048 04:38:13.988697
5049 04:38:13.992230 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5050 04:38:13.992310
5051 04:38:13.995238 [CATrainingPosCal] consider 1 rank data
5052 04:38:13.998541 u2DelayCellTimex100 = 270/100 ps
5053 04:38:14.002113 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5054 04:38:14.005250 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5055 04:38:14.008709 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5056 04:38:14.011741 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5057 04:38:14.015565 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5058 04:38:14.018319 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5059 04:38:14.018390
5060 04:38:14.025058 CA PerBit enable=1, Macro0, CA PI delay=32
5061 04:38:14.025139
5062 04:38:14.028425 [CBTSetCACLKResult] CA Dly = 32
5063 04:38:14.028505 CS Dly: 5 (0~36)
5064 04:38:14.028569 ==
5065 04:38:14.031844 Dram Type= 6, Freq= 0, CH_0, rank 1
5066 04:38:14.035199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 04:38:14.035272 ==
5068 04:38:14.041670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 04:38:14.048498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5070 04:38:14.051742 [CA 0] Center 37 (6~68) winsize 63
5071 04:38:14.055186 [CA 1] Center 37 (6~68) winsize 63
5072 04:38:14.058558 [CA 2] Center 34 (4~65) winsize 62
5073 04:38:14.061852 [CA 3] Center 33 (3~64) winsize 62
5074 04:38:14.065285 [CA 4] Center 33 (3~63) winsize 61
5075 04:38:14.068311 [CA 5] Center 32 (2~62) winsize 61
5076 04:38:14.068395
5077 04:38:14.072002 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5078 04:38:14.072083
5079 04:38:14.075217 [CATrainingPosCal] consider 2 rank data
5080 04:38:14.078667 u2DelayCellTimex100 = 270/100 ps
5081 04:38:14.081549 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5082 04:38:14.085137 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5083 04:38:14.088774 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5084 04:38:14.091773 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5085 04:38:14.094879 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5086 04:38:14.101821 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5087 04:38:14.101902
5088 04:38:14.104816 CA PerBit enable=1, Macro0, CA PI delay=32
5089 04:38:14.104898
5090 04:38:14.108415 [CBTSetCACLKResult] CA Dly = 32
5091 04:38:14.108497 CS Dly: 5 (0~37)
5092 04:38:14.108561
5093 04:38:14.111413 ----->DramcWriteLeveling(PI) begin...
5094 04:38:14.111495 ==
5095 04:38:14.115129 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 04:38:14.118053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 04:38:14.121798 ==
5098 04:38:14.124777 Write leveling (Byte 0): 32 => 32
5099 04:38:14.124859 Write leveling (Byte 1): 29 => 29
5100 04:38:14.127784 DramcWriteLeveling(PI) end<-----
5101 04:38:14.127865
5102 04:38:14.127928 ==
5103 04:38:14.131657 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 04:38:14.138345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 04:38:14.138427 ==
5106 04:38:14.141297 [Gating] SW mode calibration
5107 04:38:14.148007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 04:38:14.151103 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5109 04:38:14.157972 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5110 04:38:14.161271 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 04:38:14.164654 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 04:38:14.171496 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 04:38:14.174255 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 04:38:14.177849 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 04:38:14.184153 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5116 04:38:14.187644 0 14 28 | B1->B0 | 3333 2727 | 1 0 | (0 1) (1 0)
5117 04:38:14.191285 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5118 04:38:14.194886 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 04:38:14.201419 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 04:38:14.204732 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 04:38:14.207680 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 04:38:14.214853 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 04:38:14.217771 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5124 04:38:14.221389 0 15 28 | B1->B0 | 2626 3d3d | 0 0 | (0 0) (0 0)
5125 04:38:14.228206 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5126 04:38:14.231007 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 04:38:14.234588 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 04:38:14.241311 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 04:38:14.244739 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 04:38:14.247653 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 04:38:14.254450 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 04:38:14.257584 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5133 04:38:14.261382 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 04:38:14.267551 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 04:38:14.271210 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 04:38:14.274380 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 04:38:14.280766 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 04:38:14.284086 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 04:38:14.287582 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 04:38:14.294539 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 04:38:14.297910 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 04:38:14.300819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 04:38:14.304414 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 04:38:14.310664 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 04:38:14.314338 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 04:38:14.317317 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 04:38:14.324059 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 04:38:14.327710 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5149 04:38:14.330743 Total UI for P1: 0, mck2ui 16
5150 04:38:14.334143 best dqsien dly found for B0: ( 1, 2, 24)
5151 04:38:14.337182 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 04:38:14.340818 Total UI for P1: 0, mck2ui 16
5153 04:38:14.344367 best dqsien dly found for B1: ( 1, 2, 28)
5154 04:38:14.347258 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5155 04:38:14.350939 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5156 04:38:14.353810
5157 04:38:14.357380 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5158 04:38:14.360836 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5159 04:38:14.364191 [Gating] SW calibration Done
5160 04:38:14.364272 ==
5161 04:38:14.367246 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 04:38:14.370524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 04:38:14.370607 ==
5164 04:38:14.370671 RX Vref Scan: 0
5165 04:38:14.370730
5166 04:38:14.373835 RX Vref 0 -> 0, step: 1
5167 04:38:14.373916
5168 04:38:14.377005 RX Delay -80 -> 252, step: 8
5169 04:38:14.380350 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5170 04:38:14.384266 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5171 04:38:14.390516 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5172 04:38:14.394084 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5173 04:38:14.397827 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5174 04:38:14.400483 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5175 04:38:14.404236 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5176 04:38:14.407178 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5177 04:38:14.414214 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5178 04:38:14.417082 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5179 04:38:14.420287 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5180 04:38:14.423795 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5181 04:38:14.427397 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5182 04:38:14.430314 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5183 04:38:14.437030 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5184 04:38:14.440566 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5185 04:38:14.440647 ==
5186 04:38:14.443547 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 04:38:14.447269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 04:38:14.447351 ==
5189 04:38:14.450149 DQS Delay:
5190 04:38:14.450229 DQS0 = 0, DQS1 = 0
5191 04:38:14.450294 DQM Delay:
5192 04:38:14.453888 DQM0 = 104, DQM1 = 96
5193 04:38:14.453969 DQ Delay:
5194 04:38:14.457279 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5195 04:38:14.460208 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5196 04:38:14.464119 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5197 04:38:14.466879 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5198 04:38:14.467016
5199 04:38:14.467082
5200 04:38:14.470157 ==
5201 04:38:14.473768 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 04:38:14.476780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 04:38:14.476861 ==
5204 04:38:14.476924
5205 04:38:14.476984
5206 04:38:14.480234 TX Vref Scan disable
5207 04:38:14.480315 == TX Byte 0 ==
5208 04:38:14.486645 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5209 04:38:14.489988 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5210 04:38:14.490073 == TX Byte 1 ==
5211 04:38:14.497270 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5212 04:38:14.500078 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5213 04:38:14.500160 ==
5214 04:38:14.503707 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 04:38:14.506680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 04:38:14.506761 ==
5217 04:38:14.506825
5218 04:38:14.506884
5219 04:38:14.510294 TX Vref Scan disable
5220 04:38:14.513341 == TX Byte 0 ==
5221 04:38:14.516715 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5222 04:38:14.520041 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5223 04:38:14.523599 == TX Byte 1 ==
5224 04:38:14.526972 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5225 04:38:14.530172 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5226 04:38:14.530253
5227 04:38:14.533352 [DATLAT]
5228 04:38:14.533432 Freq=933, CH0 RK0
5229 04:38:14.533496
5230 04:38:14.537117 DATLAT Default: 0xd
5231 04:38:14.537200 0, 0xFFFF, sum = 0
5232 04:38:14.540533 1, 0xFFFF, sum = 0
5233 04:38:14.540605 2, 0xFFFF, sum = 0
5234 04:38:14.543443 3, 0xFFFF, sum = 0
5235 04:38:14.543511 4, 0xFFFF, sum = 0
5236 04:38:14.546955 5, 0xFFFF, sum = 0
5237 04:38:14.547037 6, 0xFFFF, sum = 0
5238 04:38:14.550589 7, 0xFFFF, sum = 0
5239 04:38:14.550670 8, 0xFFFF, sum = 0
5240 04:38:14.553534 9, 0xFFFF, sum = 0
5241 04:38:14.553616 10, 0x0, sum = 1
5242 04:38:14.557088 11, 0x0, sum = 2
5243 04:38:14.557170 12, 0x0, sum = 3
5244 04:38:14.560114 13, 0x0, sum = 4
5245 04:38:14.560195 best_step = 11
5246 04:38:14.560258
5247 04:38:14.560317 ==
5248 04:38:14.563751 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 04:38:14.567301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 04:38:14.567383 ==
5251 04:38:14.570223 RX Vref Scan: 1
5252 04:38:14.570304
5253 04:38:14.573929 RX Vref 0 -> 0, step: 1
5254 04:38:14.574010
5255 04:38:14.574074 RX Delay -45 -> 252, step: 4
5256 04:38:14.577105
5257 04:38:14.577187 Set Vref, RX VrefLevel [Byte0]: 55
5258 04:38:14.579991 [Byte1]: 55
5259 04:38:14.584837
5260 04:38:14.584917 Final RX Vref Byte 0 = 55 to rank0
5261 04:38:14.588353 Final RX Vref Byte 1 = 55 to rank0
5262 04:38:14.591932 Final RX Vref Byte 0 = 55 to rank1
5263 04:38:14.595362 Final RX Vref Byte 1 = 55 to rank1==
5264 04:38:14.598380 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 04:38:14.604930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 04:38:14.605026 ==
5267 04:38:14.605093 DQS Delay:
5268 04:38:14.605152 DQS0 = 0, DQS1 = 0
5269 04:38:14.608192 DQM Delay:
5270 04:38:14.608274 DQM0 = 104, DQM1 = 97
5271 04:38:14.611418 DQ Delay:
5272 04:38:14.615107 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5273 04:38:14.618494 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5274 04:38:14.621577 DQ8 =88, DQ9 =90, DQ10 =96, DQ11 =92
5275 04:38:14.624992 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5276 04:38:14.625102
5277 04:38:14.625197
5278 04:38:14.631815 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5279 04:38:14.634846 CH0 RK0: MR19=505, MR18=332B
5280 04:38:14.641544 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5281 04:38:14.641642
5282 04:38:14.644997 ----->DramcWriteLeveling(PI) begin...
5283 04:38:14.645094 ==
5284 04:38:14.648518 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 04:38:14.651753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 04:38:14.651835 ==
5287 04:38:14.655059 Write leveling (Byte 0): 31 => 31
5288 04:38:14.658670 Write leveling (Byte 1): 27 => 27
5289 04:38:14.661671 DramcWriteLeveling(PI) end<-----
5290 04:38:14.661752
5291 04:38:14.661853 ==
5292 04:38:14.665206 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 04:38:14.668081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 04:38:14.671687 ==
5295 04:38:14.671768 [Gating] SW mode calibration
5296 04:38:14.681666 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5297 04:38:14.685227 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5298 04:38:14.688048 0 14 0 | B1->B0 | 3232 3333 | 1 0 | (0 0) (0 0)
5299 04:38:14.694785 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 04:38:14.698237 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 04:38:14.701888 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 04:38:14.708313 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 04:38:14.711431 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 04:38:14.715396 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 04:38:14.721371 0 14 28 | B1->B0 | 2929 2c2c | 0 0 | (0 0) (0 0)
5306 04:38:14.724766 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 04:38:14.727980 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 04:38:14.734709 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 04:38:14.737874 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 04:38:14.741361 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 04:38:14.748363 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 04:38:14.751486 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5313 04:38:14.754902 0 15 28 | B1->B0 | 4141 3b3b | 0 0 | (0 0) (0 0)
5314 04:38:14.761097 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 04:38:14.764831 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 04:38:14.767892 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 04:38:14.774622 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 04:38:14.778100 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 04:38:14.781072 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 04:38:14.787673 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 04:38:14.790976 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5322 04:38:14.794784 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 04:38:14.797573 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 04:38:14.804854 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 04:38:14.807529 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 04:38:14.811136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 04:38:14.817581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 04:38:14.821293 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 04:38:14.824232 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 04:38:14.830868 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 04:38:14.834526 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 04:38:14.837567 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 04:38:14.844508 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 04:38:14.848046 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 04:38:14.851059 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 04:38:14.857430 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 04:38:14.860706 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5338 04:38:14.864534 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 04:38:14.867421 Total UI for P1: 0, mck2ui 16
5340 04:38:14.870938 best dqsien dly found for B0: ( 1, 2, 28)
5341 04:38:14.874197 Total UI for P1: 0, mck2ui 16
5342 04:38:14.877683 best dqsien dly found for B1: ( 1, 2, 28)
5343 04:38:14.881016 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5344 04:38:14.884394 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5345 04:38:14.884475
5346 04:38:14.890945 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5347 04:38:14.893902 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5348 04:38:14.893983 [Gating] SW calibration Done
5349 04:38:14.897805 ==
5350 04:38:14.897900 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 04:38:14.903927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 04:38:14.904009 ==
5353 04:38:14.904087 RX Vref Scan: 0
5354 04:38:14.904161
5355 04:38:14.907649 RX Vref 0 -> 0, step: 1
5356 04:38:14.907744
5357 04:38:14.910524 RX Delay -80 -> 252, step: 8
5358 04:38:14.914382 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5359 04:38:14.917573 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5360 04:38:14.920891 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5361 04:38:14.926936 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5362 04:38:14.930522 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5363 04:38:14.934296 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5364 04:38:14.937378 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5365 04:38:14.940331 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5366 04:38:14.943842 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5367 04:38:14.950250 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5368 04:38:14.953923 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5369 04:38:14.956931 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5370 04:38:14.960537 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5371 04:38:14.963932 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5372 04:38:14.966796 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5373 04:38:14.973750 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5374 04:38:14.973831 ==
5375 04:38:14.977271 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 04:38:14.980232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 04:38:14.980314 ==
5378 04:38:14.980378 DQS Delay:
5379 04:38:14.983477 DQS0 = 0, DQS1 = 0
5380 04:38:14.983605 DQM Delay:
5381 04:38:14.987067 DQM0 = 104, DQM1 = 94
5382 04:38:14.987147 DQ Delay:
5383 04:38:14.990085 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5384 04:38:14.993896 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5385 04:38:14.996920 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5386 04:38:15.000681 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5387 04:38:15.000794
5388 04:38:15.000887
5389 04:38:15.000977 ==
5390 04:38:15.003492 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 04:38:15.010271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 04:38:15.010374 ==
5393 04:38:15.010471
5394 04:38:15.010546
5395 04:38:15.010635 TX Vref Scan disable
5396 04:38:15.013270 == TX Byte 0 ==
5397 04:38:15.016697 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5398 04:38:15.023675 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5399 04:38:15.023783 == TX Byte 1 ==
5400 04:38:15.026610 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5401 04:38:15.033202 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5402 04:38:15.033286 ==
5403 04:38:15.036750 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 04:38:15.039813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 04:38:15.039895 ==
5406 04:38:15.039999
5407 04:38:15.040058
5408 04:38:15.043341 TX Vref Scan disable
5409 04:38:15.043422 == TX Byte 0 ==
5410 04:38:15.050109 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5411 04:38:15.053416 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5412 04:38:15.053497 == TX Byte 1 ==
5413 04:38:15.060070 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5414 04:38:15.063755 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5415 04:38:15.063830
5416 04:38:15.063891 [DATLAT]
5417 04:38:15.066605 Freq=933, CH0 RK1
5418 04:38:15.066675
5419 04:38:15.066734 DATLAT Default: 0xb
5420 04:38:15.069985 0, 0xFFFF, sum = 0
5421 04:38:15.070065 1, 0xFFFF, sum = 0
5422 04:38:15.073665 2, 0xFFFF, sum = 0
5423 04:38:15.073747 3, 0xFFFF, sum = 0
5424 04:38:15.076567 4, 0xFFFF, sum = 0
5425 04:38:15.076681 5, 0xFFFF, sum = 0
5426 04:38:15.080114 6, 0xFFFF, sum = 0
5427 04:38:15.080202 7, 0xFFFF, sum = 0
5428 04:38:15.083466 8, 0xFFFF, sum = 0
5429 04:38:15.086972 9, 0xFFFF, sum = 0
5430 04:38:15.087054 10, 0x0, sum = 1
5431 04:38:15.087119 11, 0x0, sum = 2
5432 04:38:15.089908 12, 0x0, sum = 3
5433 04:38:15.089990 13, 0x0, sum = 4
5434 04:38:15.093316 best_step = 11
5435 04:38:15.093398
5436 04:38:15.093462 ==
5437 04:38:15.096874 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 04:38:15.100245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 04:38:15.100326 ==
5440 04:38:15.103274 RX Vref Scan: 0
5441 04:38:15.103355
5442 04:38:15.103419 RX Vref 0 -> 0, step: 1
5443 04:38:15.103478
5444 04:38:15.106742 RX Delay -45 -> 252, step: 4
5445 04:38:15.113936 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5446 04:38:15.117500 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5447 04:38:15.120741 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5448 04:38:15.123872 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5449 04:38:15.127027 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5450 04:38:15.133679 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5451 04:38:15.137127 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5452 04:38:15.140557 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5453 04:38:15.143715 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5454 04:38:15.146730 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5455 04:38:15.153739 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5456 04:38:15.157327 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5457 04:38:15.160471 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5458 04:38:15.163937 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5459 04:38:15.167046 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5460 04:38:15.173452 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5461 04:38:15.173552 ==
5462 04:38:15.177075 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 04:38:15.180057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 04:38:15.180169 ==
5465 04:38:15.180276 DQS Delay:
5466 04:38:15.183398 DQS0 = 0, DQS1 = 0
5467 04:38:15.183479 DQM Delay:
5468 04:38:15.186955 DQM0 = 104, DQM1 = 95
5469 04:38:15.187053 DQ Delay:
5470 04:38:15.190416 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =102
5471 04:38:15.193443 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =112
5472 04:38:15.196889 DQ8 =88, DQ9 =84, DQ10 =94, DQ11 =88
5473 04:38:15.200238 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5474 04:38:15.200319
5475 04:38:15.200383
5476 04:38:15.210262 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5477 04:38:15.210345 CH0 RK1: MR19=505, MR18=2B05
5478 04:38:15.216644 CH0_RK1: MR19=0x505, MR18=0x2B05, DQSOSC=408, MR23=63, INC=65, DEC=43
5479 04:38:15.220375 [RxdqsGatingPostProcess] freq 933
5480 04:38:15.226824 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5481 04:38:15.230347 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 04:38:15.233273 best DQS1 dly(2T, 0.5T) = (0, 10)
5483 04:38:15.236939 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 04:38:15.240222 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5485 04:38:15.243346 best DQS0 dly(2T, 0.5T) = (0, 10)
5486 04:38:15.243426 best DQS1 dly(2T, 0.5T) = (0, 10)
5487 04:38:15.246930 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5488 04:38:15.250069 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5489 04:38:15.253737 Pre-setting of DQS Precalculation
5490 04:38:15.259985 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5491 04:38:15.260149 ==
5492 04:38:15.263709 Dram Type= 6, Freq= 0, CH_1, rank 0
5493 04:38:15.266872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 04:38:15.266954 ==
5495 04:38:15.273366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5496 04:38:15.279924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5497 04:38:15.283525 [CA 0] Center 36 (6~67) winsize 62
5498 04:38:15.286927 [CA 1] Center 36 (6~67) winsize 62
5499 04:38:15.289961 [CA 2] Center 34 (4~65) winsize 62
5500 04:38:15.293462 [CA 3] Center 34 (4~65) winsize 62
5501 04:38:15.296918 [CA 4] Center 34 (4~64) winsize 61
5502 04:38:15.299758 [CA 5] Center 33 (3~64) winsize 62
5503 04:38:15.299839
5504 04:38:15.303005 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5505 04:38:15.303110
5506 04:38:15.306723 [CATrainingPosCal] consider 1 rank data
5507 04:38:15.310161 u2DelayCellTimex100 = 270/100 ps
5508 04:38:15.313103 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5509 04:38:15.316712 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5510 04:38:15.320200 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5511 04:38:15.323100 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5512 04:38:15.326724 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5513 04:38:15.329657 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5514 04:38:15.329738
5515 04:38:15.336758 CA PerBit enable=1, Macro0, CA PI delay=33
5516 04:38:15.336839
5517 04:38:15.336903 [CBTSetCACLKResult] CA Dly = 33
5518 04:38:15.339801 CS Dly: 6 (0~37)
5519 04:38:15.339881 ==
5520 04:38:15.343491 Dram Type= 6, Freq= 0, CH_1, rank 1
5521 04:38:15.347071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 04:38:15.347156 ==
5523 04:38:15.353382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 04:38:15.360278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5525 04:38:15.363552 [CA 0] Center 36 (6~67) winsize 62
5526 04:38:15.366737 [CA 1] Center 37 (7~68) winsize 62
5527 04:38:15.369849 [CA 2] Center 35 (4~66) winsize 63
5528 04:38:15.373414 [CA 3] Center 34 (4~65) winsize 62
5529 04:38:15.376757 [CA 4] Center 34 (4~65) winsize 62
5530 04:38:15.380431 [CA 5] Center 34 (4~64) winsize 61
5531 04:38:15.380526
5532 04:38:15.383287 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5533 04:38:15.383368
5534 04:38:15.386269 [CATrainingPosCal] consider 2 rank data
5535 04:38:15.389738 u2DelayCellTimex100 = 270/100 ps
5536 04:38:15.393553 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5537 04:38:15.396327 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5538 04:38:15.399834 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5539 04:38:15.403387 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5540 04:38:15.406358 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5541 04:38:15.409570 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5542 04:38:15.409651
5543 04:38:15.416610 CA PerBit enable=1, Macro0, CA PI delay=34
5544 04:38:15.416691
5545 04:38:15.416754 [CBTSetCACLKResult] CA Dly = 34
5546 04:38:15.419720 CS Dly: 7 (0~39)
5547 04:38:15.419802
5548 04:38:15.423214 ----->DramcWriteLeveling(PI) begin...
5549 04:38:15.423296 ==
5550 04:38:15.426525 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 04:38:15.429596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 04:38:15.429677 ==
5553 04:38:15.433251 Write leveling (Byte 0): 25 => 25
5554 04:38:15.436122 Write leveling (Byte 1): 29 => 29
5555 04:38:15.439724 DramcWriteLeveling(PI) end<-----
5556 04:38:15.439805
5557 04:38:15.439868 ==
5558 04:38:15.442993 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 04:38:15.446398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 04:38:15.449848 ==
5561 04:38:15.449929 [Gating] SW mode calibration
5562 04:38:15.459166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5563 04:38:15.462737 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5564 04:38:15.466176 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 04:38:15.472642 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 04:38:15.476102 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 04:38:15.479393 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 04:38:15.485875 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 04:38:15.489490 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 04:38:15.493093 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5571 04:38:15.499408 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5572 04:38:15.503042 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 04:38:15.505823 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 04:38:15.512595 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 04:38:15.516030 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 04:38:15.519352 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 04:38:15.526106 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 04:38:15.529681 0 15 24 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (1 1)
5579 04:38:15.532576 0 15 28 | B1->B0 | 3939 4343 | 1 0 | (0 0) (0 0)
5580 04:38:15.536292 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 04:38:15.542887 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 04:38:15.545932 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 04:38:15.549499 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 04:38:15.556192 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 04:38:15.559639 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 04:38:15.562525 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5587 04:38:15.568980 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 04:38:15.572759 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 04:38:15.575729 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 04:38:15.582300 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 04:38:15.585818 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 04:38:15.588893 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 04:38:15.595436 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 04:38:15.598833 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 04:38:15.601959 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 04:38:15.608638 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 04:38:15.611720 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 04:38:15.615410 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 04:38:15.621998 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 04:38:15.625642 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 04:38:15.628485 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 04:38:15.635499 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5603 04:38:15.638598 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 04:38:15.641995 Total UI for P1: 0, mck2ui 16
5605 04:38:15.645379 best dqsien dly found for B0: ( 1, 2, 26)
5606 04:38:15.648415 Total UI for P1: 0, mck2ui 16
5607 04:38:15.652047 best dqsien dly found for B1: ( 1, 2, 24)
5608 04:38:15.655010 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5609 04:38:15.658510 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5610 04:38:15.658592
5611 04:38:15.662211 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5612 04:38:15.665536 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5613 04:38:15.668604 [Gating] SW calibration Done
5614 04:38:15.668685 ==
5615 04:38:15.672077 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 04:38:15.675008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 04:38:15.678600 ==
5618 04:38:15.678681 RX Vref Scan: 0
5619 04:38:15.678745
5620 04:38:15.681560 RX Vref 0 -> 0, step: 1
5621 04:38:15.681640
5622 04:38:15.685344 RX Delay -80 -> 252, step: 8
5623 04:38:15.688104 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5624 04:38:15.691837 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5625 04:38:15.695068 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5626 04:38:15.698370 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5627 04:38:15.701447 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5628 04:38:15.708032 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5629 04:38:15.711627 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5630 04:38:15.714631 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5631 04:38:15.718403 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5632 04:38:15.721620 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5633 04:38:15.724715 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5634 04:38:15.731620 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5635 04:38:15.734709 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5636 04:38:15.738192 iDelay=208, Bit 13, Center 107 (24 ~ 191) 168
5637 04:38:15.741596 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5638 04:38:15.744977 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5639 04:38:15.748332 ==
5640 04:38:15.751508 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 04:38:15.754474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 04:38:15.754594 ==
5643 04:38:15.754658 DQS Delay:
5644 04:38:15.758031 DQS0 = 0, DQS1 = 0
5645 04:38:15.758111 DQM Delay:
5646 04:38:15.761430 DQM0 = 102, DQM1 = 98
5647 04:38:15.761511 DQ Delay:
5648 04:38:15.764519 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5649 04:38:15.768133 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5650 04:38:15.771449 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5651 04:38:15.774480 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =103
5652 04:38:15.774561
5653 04:38:15.774624
5654 04:38:15.774683 ==
5655 04:38:15.778260 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 04:38:15.781192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 04:38:15.784758 ==
5658 04:38:15.784839
5659 04:38:15.784902
5660 04:38:15.784961 TX Vref Scan disable
5661 04:38:15.787696 == TX Byte 0 ==
5662 04:38:15.791217 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5663 04:38:15.794637 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5664 04:38:15.797637 == TX Byte 1 ==
5665 04:38:15.801384 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5666 04:38:15.804349 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5667 04:38:15.807556 ==
5668 04:38:15.811099 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 04:38:15.814549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 04:38:15.814630 ==
5671 04:38:15.814716
5672 04:38:15.814790
5673 04:38:15.817566 TX Vref Scan disable
5674 04:38:15.817646 == TX Byte 0 ==
5675 04:38:15.824131 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 04:38:15.827681 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 04:38:15.827789 == TX Byte 1 ==
5678 04:38:15.834120 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5679 04:38:15.837432 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5680 04:38:15.837514
5681 04:38:15.837578 [DATLAT]
5682 04:38:15.841284 Freq=933, CH1 RK0
5683 04:38:15.841379
5684 04:38:15.841442 DATLAT Default: 0xd
5685 04:38:15.844446 0, 0xFFFF, sum = 0
5686 04:38:15.844528 1, 0xFFFF, sum = 0
5687 04:38:15.847773 2, 0xFFFF, sum = 0
5688 04:38:15.847855 3, 0xFFFF, sum = 0
5689 04:38:15.850970 4, 0xFFFF, sum = 0
5690 04:38:15.851052 5, 0xFFFF, sum = 0
5691 04:38:15.854559 6, 0xFFFF, sum = 0
5692 04:38:15.854642 7, 0xFFFF, sum = 0
5693 04:38:15.857596 8, 0xFFFF, sum = 0
5694 04:38:15.857678 9, 0xFFFF, sum = 0
5695 04:38:15.860737 10, 0x0, sum = 1
5696 04:38:15.860848 11, 0x0, sum = 2
5697 04:38:15.864566 12, 0x0, sum = 3
5698 04:38:15.864655 13, 0x0, sum = 4
5699 04:38:15.867907 best_step = 11
5700 04:38:15.867987
5701 04:38:15.868051 ==
5702 04:38:15.871112 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 04:38:15.874465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 04:38:15.874547 ==
5705 04:38:15.877607 RX Vref Scan: 1
5706 04:38:15.877688
5707 04:38:15.877751 RX Vref 0 -> 0, step: 1
5708 04:38:15.877809
5709 04:38:15.880790 RX Delay -45 -> 252, step: 4
5710 04:38:15.880891
5711 04:38:15.884205 Set Vref, RX VrefLevel [Byte0]: 56
5712 04:38:15.887763 [Byte1]: 54
5713 04:38:15.891357
5714 04:38:15.891436 Final RX Vref Byte 0 = 56 to rank0
5715 04:38:15.894967 Final RX Vref Byte 1 = 54 to rank0
5716 04:38:15.898213 Final RX Vref Byte 0 = 56 to rank1
5717 04:38:15.901920 Final RX Vref Byte 1 = 54 to rank1==
5718 04:38:15.904944 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 04:38:15.911340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 04:38:15.911425 ==
5721 04:38:15.911490 DQS Delay:
5722 04:38:15.911591 DQS0 = 0, DQS1 = 0
5723 04:38:15.914863 DQM Delay:
5724 04:38:15.914943 DQM0 = 104, DQM1 = 100
5725 04:38:15.917964 DQ Delay:
5726 04:38:15.921494 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5727 04:38:15.925064 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =104
5728 04:38:15.928183 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5729 04:38:15.931771 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =108
5730 04:38:15.931852
5731 04:38:15.931915
5732 04:38:15.938418 [DQSOSCAuto] RK0, (LSB)MR18= 0x152c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5733 04:38:15.941341 CH1 RK0: MR19=505, MR18=152C
5734 04:38:15.947951 CH1_RK0: MR19=0x505, MR18=0x152C, DQSOSC=408, MR23=63, INC=65, DEC=43
5735 04:38:15.948034
5736 04:38:15.951637 ----->DramcWriteLeveling(PI) begin...
5737 04:38:15.951722 ==
5738 04:38:15.954636 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 04:38:15.957927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 04:38:15.958008 ==
5741 04:38:15.961231 Write leveling (Byte 0): 28 => 28
5742 04:38:15.964924 Write leveling (Byte 1): 26 => 26
5743 04:38:15.968131 DramcWriteLeveling(PI) end<-----
5744 04:38:15.968211
5745 04:38:15.968275 ==
5746 04:38:15.971610 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 04:38:15.977805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 04:38:15.977887 ==
5749 04:38:15.977951 [Gating] SW mode calibration
5750 04:38:15.987928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5751 04:38:15.991135 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5752 04:38:15.994825 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 04:38:16.000936 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 04:38:16.004565 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 04:38:16.008109 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 04:38:16.014066 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 04:38:16.017615 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5758 04:38:16.021223 0 14 24 | B1->B0 | 2a2a 3030 | 0 1 | (0 0) (1 0)
5759 04:38:16.027954 0 14 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5760 04:38:16.030964 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 04:38:16.034220 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 04:38:16.041153 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 04:38:16.044189 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 04:38:16.047824 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 04:38:16.054740 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 04:38:16.057523 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (0 0) (0 0)
5767 04:38:16.061059 0 15 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5768 04:38:16.067898 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 04:38:16.071040 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 04:38:16.074181 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 04:38:16.080877 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 04:38:16.083899 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 04:38:16.087376 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5774 04:38:16.094493 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5775 04:38:16.097430 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 04:38:16.100901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 04:38:16.107660 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 04:38:16.110755 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 04:38:16.114007 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 04:38:16.120470 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 04:38:16.124138 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 04:38:16.127164 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 04:38:16.130747 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 04:38:16.137175 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 04:38:16.140752 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 04:38:16.143713 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 04:38:16.150221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 04:38:16.153765 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 04:38:16.156953 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 04:38:16.163739 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5791 04:38:16.166732 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5792 04:38:16.170350 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 04:38:16.173972 Total UI for P1: 0, mck2ui 16
5794 04:38:16.176815 best dqsien dly found for B0: ( 1, 2, 28)
5795 04:38:16.180394 Total UI for P1: 0, mck2ui 16
5796 04:38:16.183765 best dqsien dly found for B1: ( 1, 2, 26)
5797 04:38:16.187074 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5798 04:38:16.190410 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5799 04:38:16.190491
5800 04:38:16.197112 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5801 04:38:16.200041 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5802 04:38:16.203348 [Gating] SW calibration Done
5803 04:38:16.203429 ==
5804 04:38:16.206659 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 04:38:16.210302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 04:38:16.210384 ==
5807 04:38:16.210448 RX Vref Scan: 0
5808 04:38:16.210507
5809 04:38:16.213542 RX Vref 0 -> 0, step: 1
5810 04:38:16.213624
5811 04:38:16.217006 RX Delay -80 -> 252, step: 8
5812 04:38:16.220522 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5813 04:38:16.223889 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5814 04:38:16.227011 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5815 04:38:16.233444 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5816 04:38:16.237018 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5817 04:38:16.240156 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5818 04:38:16.243393 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5819 04:38:16.246994 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5820 04:38:16.250045 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5821 04:38:16.256578 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5822 04:38:16.259990 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5823 04:38:16.263228 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5824 04:38:16.266392 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5825 04:38:16.269848 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5826 04:38:16.277052 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5827 04:38:16.280004 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5828 04:38:16.280085 ==
5829 04:38:16.283425 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 04:38:16.286876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 04:38:16.286970 ==
5832 04:38:16.287062 DQS Delay:
5833 04:38:16.290198 DQS0 = 0, DQS1 = 0
5834 04:38:16.290281 DQM Delay:
5835 04:38:16.293786 DQM0 = 102, DQM1 = 98
5836 04:38:16.293935 DQ Delay:
5837 04:38:16.296586 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =95
5838 04:38:16.300010 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5839 04:38:16.303406 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5840 04:38:16.306393 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5841 04:38:16.306516
5842 04:38:16.306585
5843 04:38:16.306659 ==
5844 04:38:16.309955 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 04:38:16.316423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 04:38:16.316553 ==
5847 04:38:16.316647
5848 04:38:16.316735
5849 04:38:16.316821 TX Vref Scan disable
5850 04:38:16.320180 == TX Byte 0 ==
5851 04:38:16.323477 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5852 04:38:16.326977 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5853 04:38:16.330116 == TX Byte 1 ==
5854 04:38:16.333382 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5855 04:38:16.340253 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5856 04:38:16.340336 ==
5857 04:38:16.343411 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 04:38:16.346649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 04:38:16.346731 ==
5860 04:38:16.346795
5861 04:38:16.346855
5862 04:38:16.349980 TX Vref Scan disable
5863 04:38:16.350060 == TX Byte 0 ==
5864 04:38:16.357105 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5865 04:38:16.359960 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5866 04:38:16.360042 == TX Byte 1 ==
5867 04:38:16.366570 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5868 04:38:16.369844 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5869 04:38:16.369936
5870 04:38:16.370040 [DATLAT]
5871 04:38:16.373081 Freq=933, CH1 RK1
5872 04:38:16.373163
5873 04:38:16.373226 DATLAT Default: 0xb
5874 04:38:16.376827 0, 0xFFFF, sum = 0
5875 04:38:16.376937 1, 0xFFFF, sum = 0
5876 04:38:16.379730 2, 0xFFFF, sum = 0
5877 04:38:16.379805 3, 0xFFFF, sum = 0
5878 04:38:16.383108 4, 0xFFFF, sum = 0
5879 04:38:16.383178 5, 0xFFFF, sum = 0
5880 04:38:16.386728 6, 0xFFFF, sum = 0
5881 04:38:16.389617 7, 0xFFFF, sum = 0
5882 04:38:16.389698 8, 0xFFFF, sum = 0
5883 04:38:16.393144 9, 0xFFFF, sum = 0
5884 04:38:16.393227 10, 0x0, sum = 1
5885 04:38:16.393293 11, 0x0, sum = 2
5886 04:38:16.396409 12, 0x0, sum = 3
5887 04:38:16.396491 13, 0x0, sum = 4
5888 04:38:16.399795 best_step = 11
5889 04:38:16.399875
5890 04:38:16.399938 ==
5891 04:38:16.403411 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 04:38:16.406652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 04:38:16.406733 ==
5894 04:38:16.410139 RX Vref Scan: 0
5895 04:38:16.410220
5896 04:38:16.410284 RX Vref 0 -> 0, step: 1
5897 04:38:16.410343
5898 04:38:16.413038 RX Delay -45 -> 252, step: 4
5899 04:38:16.420173 iDelay=203, Bit 0, Center 108 (23 ~ 194) 172
5900 04:38:16.423767 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5901 04:38:16.426714 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5902 04:38:16.430284 iDelay=203, Bit 3, Center 98 (19 ~ 178) 160
5903 04:38:16.433789 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5904 04:38:16.440593 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5905 04:38:16.443372 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5906 04:38:16.447066 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5907 04:38:16.449910 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5908 04:38:16.453409 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5909 04:38:16.460072 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5910 04:38:16.463677 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5911 04:38:16.466864 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5912 04:38:16.470234 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5913 04:38:16.473529 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5914 04:38:16.479989 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5915 04:38:16.480071 ==
5916 04:38:16.483328 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 04:38:16.486953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 04:38:16.487036 ==
5919 04:38:16.487100 DQS Delay:
5920 04:38:16.489808 DQS0 = 0, DQS1 = 0
5921 04:38:16.489878 DQM Delay:
5922 04:38:16.493420 DQM0 = 104, DQM1 = 100
5923 04:38:16.493501 DQ Delay:
5924 04:38:16.496403 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =98
5925 04:38:16.499966 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5926 04:38:16.503164 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =94
5927 04:38:16.506593 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =106
5928 04:38:16.506673
5929 04:38:16.506737
5930 04:38:16.516705 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps
5931 04:38:16.520204 CH1 RK1: MR19=505, MR18=2D00
5932 04:38:16.523197 CH1_RK1: MR19=0x505, MR18=0x2D00, DQSOSC=407, MR23=63, INC=65, DEC=43
5933 04:38:16.526778 [RxdqsGatingPostProcess] freq 933
5934 04:38:16.533244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 04:38:16.536804 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 04:38:16.540093 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 04:38:16.543447 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 04:38:16.546486 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 04:38:16.549802 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 04:38:16.553402 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 04:38:16.556839 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 04:38:16.560164 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 04:38:16.560246 Pre-setting of DQS Precalculation
5944 04:38:16.566467 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 04:38:16.573102 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 04:38:16.579693 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 04:38:16.579775
5948 04:38:16.579838
5949 04:38:16.582855 [Calibration Summary] 1866 Mbps
5950 04:38:16.586228 CH 0, Rank 0
5951 04:38:16.586309 SW Impedance : PASS
5952 04:38:16.589781 DUTY Scan : NO K
5953 04:38:16.592880 ZQ Calibration : PASS
5954 04:38:16.592961 Jitter Meter : NO K
5955 04:38:16.596274 CBT Training : PASS
5956 04:38:16.599748 Write leveling : PASS
5957 04:38:16.599850 RX DQS gating : PASS
5958 04:38:16.602870 RX DQ/DQS(RDDQC) : PASS
5959 04:38:16.602950 TX DQ/DQS : PASS
5960 04:38:16.606219 RX DATLAT : PASS
5961 04:38:16.609471 RX DQ/DQS(Engine): PASS
5962 04:38:16.609552 TX OE : NO K
5963 04:38:16.612751 All Pass.
5964 04:38:16.612832
5965 04:38:16.612896 CH 0, Rank 1
5966 04:38:16.616311 SW Impedance : PASS
5967 04:38:16.616393 DUTY Scan : NO K
5968 04:38:16.619951 ZQ Calibration : PASS
5969 04:38:16.622882 Jitter Meter : NO K
5970 04:38:16.622962 CBT Training : PASS
5971 04:38:16.626287 Write leveling : PASS
5972 04:38:16.629887 RX DQS gating : PASS
5973 04:38:16.630039 RX DQ/DQS(RDDQC) : PASS
5974 04:38:16.632911 TX DQ/DQS : PASS
5975 04:38:16.636457 RX DATLAT : PASS
5976 04:38:16.636538 RX DQ/DQS(Engine): PASS
5977 04:38:16.639498 TX OE : NO K
5978 04:38:16.639605 All Pass.
5979 04:38:16.639669
5980 04:38:16.643012 CH 1, Rank 0
5981 04:38:16.643093 SW Impedance : PASS
5982 04:38:16.645943 DUTY Scan : NO K
5983 04:38:16.649557 ZQ Calibration : PASS
5984 04:38:16.649638 Jitter Meter : NO K
5985 04:38:16.652481 CBT Training : PASS
5986 04:38:16.656134 Write leveling : PASS
5987 04:38:16.656215 RX DQS gating : PASS
5988 04:38:16.659672 RX DQ/DQS(RDDQC) : PASS
5989 04:38:16.659752 TX DQ/DQS : PASS
5990 04:38:16.662553 RX DATLAT : PASS
5991 04:38:16.666030 RX DQ/DQS(Engine): PASS
5992 04:38:16.666111 TX OE : NO K
5993 04:38:16.669518 All Pass.
5994 04:38:16.669598
5995 04:38:16.669662 CH 1, Rank 1
5996 04:38:16.672452 SW Impedance : PASS
5997 04:38:16.672534 DUTY Scan : NO K
5998 04:38:16.676014 ZQ Calibration : PASS
5999 04:38:16.679493 Jitter Meter : NO K
6000 04:38:16.679598 CBT Training : PASS
6001 04:38:16.683049 Write leveling : PASS
6002 04:38:16.686375 RX DQS gating : PASS
6003 04:38:16.686456 RX DQ/DQS(RDDQC) : PASS
6004 04:38:16.689464 TX DQ/DQS : PASS
6005 04:38:16.692871 RX DATLAT : PASS
6006 04:38:16.692983 RX DQ/DQS(Engine): PASS
6007 04:38:16.695908 TX OE : NO K
6008 04:38:16.696001 All Pass.
6009 04:38:16.696067
6010 04:38:16.699475 DramC Write-DBI off
6011 04:38:16.702489 PER_BANK_REFRESH: Hybrid Mode
6012 04:38:16.702569 TX_TRACKING: ON
6013 04:38:16.712374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 04:38:16.715774 [FAST_K] Save calibration result to emmc
6015 04:38:16.719213 dramc_set_vcore_voltage set vcore to 650000
6016 04:38:16.722406 Read voltage for 400, 6
6017 04:38:16.722487 Vio18 = 0
6018 04:38:16.722551 Vcore = 650000
6019 04:38:16.725974 Vdram = 0
6020 04:38:16.726054 Vddq = 0
6021 04:38:16.726119 Vmddr = 0
6022 04:38:16.732694 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 04:38:16.735731 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 04:38:16.739307 MEM_TYPE=3, freq_sel=20
6025 04:38:16.742249 sv_algorithm_assistance_LP4_800
6026 04:38:16.745688 ============ PULL DRAM RESETB DOWN ============
6027 04:38:16.749239 ========== PULL DRAM RESETB DOWN end =========
6028 04:38:16.755530 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 04:38:16.758797 ===================================
6030 04:38:16.758878 LPDDR4 DRAM CONFIGURATION
6031 04:38:16.762290 ===================================
6032 04:38:16.765727 EX_ROW_EN[0] = 0x0
6033 04:38:16.768673 EX_ROW_EN[1] = 0x0
6034 04:38:16.768754 LP4Y_EN = 0x0
6035 04:38:16.772491 WORK_FSP = 0x0
6036 04:38:16.772572 WL = 0x2
6037 04:38:16.776024 RL = 0x2
6038 04:38:16.776105 BL = 0x2
6039 04:38:16.778825 RPST = 0x0
6040 04:38:16.778905 RD_PRE = 0x0
6041 04:38:16.782396 WR_PRE = 0x1
6042 04:38:16.782476 WR_PST = 0x0
6043 04:38:16.785502 DBI_WR = 0x0
6044 04:38:16.785583 DBI_RD = 0x0
6045 04:38:16.788877 OTF = 0x1
6046 04:38:16.792379 ===================================
6047 04:38:16.795285 ===================================
6048 04:38:16.795365 ANA top config
6049 04:38:16.798835 ===================================
6050 04:38:16.802441 DLL_ASYNC_EN = 0
6051 04:38:16.805339 ALL_SLAVE_EN = 1
6052 04:38:16.808787 NEW_RANK_MODE = 1
6053 04:38:16.808869 DLL_IDLE_MODE = 1
6054 04:38:16.812233 LP45_APHY_COMB_EN = 1
6055 04:38:16.815745 TX_ODT_DIS = 1
6056 04:38:16.819096 NEW_8X_MODE = 1
6057 04:38:16.821920 ===================================
6058 04:38:16.825494 ===================================
6059 04:38:16.828613 data_rate = 800
6060 04:38:16.828694 CKR = 1
6061 04:38:16.831847 DQ_P2S_RATIO = 4
6062 04:38:16.835466 ===================================
6063 04:38:16.838880 CA_P2S_RATIO = 4
6064 04:38:16.841887 DQ_CA_OPEN = 0
6065 04:38:16.845309 DQ_SEMI_OPEN = 1
6066 04:38:16.845389 CA_SEMI_OPEN = 1
6067 04:38:16.848837 CA_FULL_RATE = 0
6068 04:38:16.851865 DQ_CKDIV4_EN = 0
6069 04:38:16.855279 CA_CKDIV4_EN = 1
6070 04:38:16.858340 CA_PREDIV_EN = 0
6071 04:38:16.861722 PH8_DLY = 0
6072 04:38:16.864990 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 04:38:16.865071 DQ_AAMCK_DIV = 0
6074 04:38:16.868332 CA_AAMCK_DIV = 0
6075 04:38:16.871934 CA_ADMCK_DIV = 4
6076 04:38:16.875344 DQ_TRACK_CA_EN = 0
6077 04:38:16.878274 CA_PICK = 800
6078 04:38:16.881694 CA_MCKIO = 400
6079 04:38:16.881775 MCKIO_SEMI = 400
6080 04:38:16.885200 PLL_FREQ = 3016
6081 04:38:16.888185 DQ_UI_PI_RATIO = 32
6082 04:38:16.891787 CA_UI_PI_RATIO = 32
6083 04:38:16.895297 ===================================
6084 04:38:16.898659 ===================================
6085 04:38:16.901532 memory_type:LPDDR4
6086 04:38:16.901613 GP_NUM : 10
6087 04:38:16.904949 SRAM_EN : 1
6088 04:38:16.908466 MD32_EN : 0
6089 04:38:16.911365 ===================================
6090 04:38:16.911446 [ANA_INIT] >>>>>>>>>>>>>>
6091 04:38:16.915098 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 04:38:16.918261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 04:38:16.921893 ===================================
6094 04:38:16.925148 data_rate = 800,PCW = 0X7400
6095 04:38:16.928529 ===================================
6096 04:38:16.931447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 04:38:16.938453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 04:38:16.948488 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 04:38:16.955078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 04:38:16.958143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 04:38:16.961823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 04:38:16.961904 [ANA_INIT] flow start
6103 04:38:16.964865 [ANA_INIT] PLL >>>>>>>>
6104 04:38:16.968370 [ANA_INIT] PLL <<<<<<<<
6105 04:38:16.968451 [ANA_INIT] MIDPI >>>>>>>>
6106 04:38:16.971621 [ANA_INIT] MIDPI <<<<<<<<
6107 04:38:16.974804 [ANA_INIT] DLL >>>>>>>>
6108 04:38:16.974885 [ANA_INIT] flow end
6109 04:38:16.978365 ============ LP4 DIFF to SE enter ============
6110 04:38:16.985242 ============ LP4 DIFF to SE exit ============
6111 04:38:16.985324 [ANA_INIT] <<<<<<<<<<<<<
6112 04:38:16.988102 [Flow] Enable top DCM control >>>>>
6113 04:38:16.991552 [Flow] Enable top DCM control <<<<<
6114 04:38:16.995154 Enable DLL master slave shuffle
6115 04:38:17.001475 ==============================================================
6116 04:38:17.001557 Gating Mode config
6117 04:38:17.007830 ==============================================================
6118 04:38:17.011431 Config description:
6119 04:38:17.021324 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 04:38:17.028308 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 04:38:17.031657 SELPH_MODE 0: By rank 1: By Phase
6122 04:38:17.038059 ==============================================================
6123 04:38:17.041619 GAT_TRACK_EN = 0
6124 04:38:17.044513 RX_GATING_MODE = 2
6125 04:38:17.044622 RX_GATING_TRACK_MODE = 2
6126 04:38:17.047931 SELPH_MODE = 1
6127 04:38:17.051427 PICG_EARLY_EN = 1
6128 04:38:17.054912 VALID_LAT_VALUE = 1
6129 04:38:17.061664 ==============================================================
6130 04:38:17.064726 Enter into Gating configuration >>>>
6131 04:38:17.067955 Exit from Gating configuration <<<<
6132 04:38:17.071435 Enter into DVFS_PRE_config >>>>>
6133 04:38:17.081303 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 04:38:17.084985 Exit from DVFS_PRE_config <<<<<
6135 04:38:17.088083 Enter into PICG configuration >>>>
6136 04:38:17.091734 Exit from PICG configuration <<<<
6137 04:38:17.094633 [RX_INPUT] configuration >>>>>
6138 04:38:17.098207 [RX_INPUT] configuration <<<<<
6139 04:38:17.101598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 04:38:17.108227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 04:38:17.114829 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 04:38:17.118214 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 04:38:17.124598 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 04:38:17.131582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 04:38:17.134464 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 04:38:17.137867 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 04:38:17.144830 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 04:38:17.147834 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 04:38:17.151355 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 04:38:17.157948 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 04:38:17.161318 ===================================
6152 04:38:17.161428 LPDDR4 DRAM CONFIGURATION
6153 04:38:17.164616 ===================================
6154 04:38:17.167634 EX_ROW_EN[0] = 0x0
6155 04:38:17.171530 EX_ROW_EN[1] = 0x0
6156 04:38:17.171656 LP4Y_EN = 0x0
6157 04:38:17.174412 WORK_FSP = 0x0
6158 04:38:17.174492 WL = 0x2
6159 04:38:17.177880 RL = 0x2
6160 04:38:17.177988 BL = 0x2
6161 04:38:17.181455 RPST = 0x0
6162 04:38:17.181536 RD_PRE = 0x0
6163 04:38:17.184551 WR_PRE = 0x1
6164 04:38:17.184632 WR_PST = 0x0
6165 04:38:17.188031 DBI_WR = 0x0
6166 04:38:17.188112 DBI_RD = 0x0
6167 04:38:17.191284 OTF = 0x1
6168 04:38:17.194281 ===================================
6169 04:38:17.197449 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 04:38:17.201086 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 04:38:17.207551 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 04:38:17.210975 ===================================
6173 04:38:17.211056 LPDDR4 DRAM CONFIGURATION
6174 04:38:17.214626 ===================================
6175 04:38:17.217886 EX_ROW_EN[0] = 0x10
6176 04:38:17.217966 EX_ROW_EN[1] = 0x0
6177 04:38:17.221429 LP4Y_EN = 0x0
6178 04:38:17.221510 WORK_FSP = 0x0
6179 04:38:17.224551 WL = 0x2
6180 04:38:17.224632 RL = 0x2
6181 04:38:17.228036 BL = 0x2
6182 04:38:17.231536 RPST = 0x0
6183 04:38:17.231617 RD_PRE = 0x0
6184 04:38:17.234496 WR_PRE = 0x1
6185 04:38:17.234577 WR_PST = 0x0
6186 04:38:17.237953 DBI_WR = 0x0
6187 04:38:17.238059 DBI_RD = 0x0
6188 04:38:17.241458 OTF = 0x1
6189 04:38:17.244744 ===================================
6190 04:38:17.247655 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 04:38:17.252941 nWR fixed to 30
6192 04:38:17.256421 [ModeRegInit_LP4] CH0 RK0
6193 04:38:17.256502 [ModeRegInit_LP4] CH0 RK1
6194 04:38:17.260017 [ModeRegInit_LP4] CH1 RK0
6195 04:38:17.262895 [ModeRegInit_LP4] CH1 RK1
6196 04:38:17.262975 match AC timing 19
6197 04:38:17.269466 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 04:38:17.272863 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 04:38:17.276490 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 04:38:17.282812 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 04:38:17.286407 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 04:38:17.286515 ==
6203 04:38:17.289406 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 04:38:17.292987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 04:38:17.293069 ==
6206 04:38:17.299863 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 04:38:17.305945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6208 04:38:17.309573 [CA 0] Center 36 (8~64) winsize 57
6209 04:38:17.313079 [CA 1] Center 36 (8~64) winsize 57
6210 04:38:17.316336 [CA 2] Center 36 (8~64) winsize 57
6211 04:38:17.316417 [CA 3] Center 36 (8~64) winsize 57
6212 04:38:17.319654 [CA 4] Center 36 (8~64) winsize 57
6213 04:38:17.322793 [CA 5] Center 36 (8~64) winsize 57
6214 04:38:17.322874
6215 04:38:17.329876 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6216 04:38:17.329957
6217 04:38:17.332634 [CATrainingPosCal] consider 1 rank data
6218 04:38:17.336115 u2DelayCellTimex100 = 270/100 ps
6219 04:38:17.339287 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 04:38:17.342671 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 04:38:17.346395 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 04:38:17.349694 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 04:38:17.353036 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 04:38:17.356116 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 04:38:17.356198
6226 04:38:17.359401 CA PerBit enable=1, Macro0, CA PI delay=36
6227 04:38:17.359481
6228 04:38:17.362939 [CBTSetCACLKResult] CA Dly = 36
6229 04:38:17.366489 CS Dly: 1 (0~32)
6230 04:38:17.366569 ==
6231 04:38:17.369394 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 04:38:17.372897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 04:38:17.372979 ==
6234 04:38:17.379417 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 04:38:17.382807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 04:38:17.386003 [CA 0] Center 36 (8~64) winsize 57
6237 04:38:17.389096 [CA 1] Center 36 (8~64) winsize 57
6238 04:38:17.392877 [CA 2] Center 36 (8~64) winsize 57
6239 04:38:17.396079 [CA 3] Center 36 (8~64) winsize 57
6240 04:38:17.399339 [CA 4] Center 36 (8~64) winsize 57
6241 04:38:17.402792 [CA 5] Center 36 (8~64) winsize 57
6242 04:38:17.402899
6243 04:38:17.406281 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 04:38:17.406362
6245 04:38:17.409243 [CATrainingPosCal] consider 2 rank data
6246 04:38:17.412899 u2DelayCellTimex100 = 270/100 ps
6247 04:38:17.415997 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 04:38:17.419431 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 04:38:17.422949 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 04:38:17.438266 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 04:38:17.438378 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 04:38:17.438474 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 04:38:17.438563
6254 04:38:17.439562 CA PerBit enable=1, Macro0, CA PI delay=36
6255 04:38:17.439674
6256 04:38:17.442963 [CBTSetCACLKResult] CA Dly = 36
6257 04:38:17.443043 CS Dly: 1 (0~32)
6258 04:38:17.443107
6259 04:38:17.446181 ----->DramcWriteLeveling(PI) begin...
6260 04:38:17.446262 ==
6261 04:38:17.449108 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 04:38:17.456294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 04:38:17.456376 ==
6264 04:38:17.459164 Write leveling (Byte 0): 40 => 8
6265 04:38:17.459245 Write leveling (Byte 1): 40 => 8
6266 04:38:17.462928 DramcWriteLeveling(PI) end<-----
6267 04:38:17.463009
6268 04:38:17.466000 ==
6269 04:38:17.466081 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 04:38:17.473006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 04:38:17.473088 ==
6272 04:38:17.476035 [Gating] SW mode calibration
6273 04:38:17.483018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 04:38:17.485954 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 04:38:17.492421 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 04:38:17.496353 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 04:38:17.499188 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 04:38:17.506084 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 04:38:17.509134 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 04:38:17.512602 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 04:38:17.518920 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 04:38:17.522551 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 04:38:17.525856 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 04:38:17.529172 Total UI for P1: 0, mck2ui 16
6285 04:38:17.532200 best dqsien dly found for B0: ( 0, 14, 24)
6286 04:38:17.535676 Total UI for P1: 0, mck2ui 16
6287 04:38:17.539141 best dqsien dly found for B1: ( 0, 14, 24)
6288 04:38:17.542148 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 04:38:17.545872 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 04:38:17.545954
6291 04:38:17.551964 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 04:38:17.555285 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 04:38:17.555367 [Gating] SW calibration Done
6294 04:38:17.558665 ==
6295 04:38:17.562280 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 04:38:17.565415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 04:38:17.565506 ==
6298 04:38:17.565573 RX Vref Scan: 0
6299 04:38:17.565633
6300 04:38:17.568873 RX Vref 0 -> 0, step: 1
6301 04:38:17.568955
6302 04:38:17.571898 RX Delay -410 -> 252, step: 16
6303 04:38:17.575241 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6304 04:38:17.581843 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6305 04:38:17.585359 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6306 04:38:17.588788 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6307 04:38:17.591559 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6308 04:38:17.598398 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6309 04:38:17.601640 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6310 04:38:17.605061 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6311 04:38:17.608241 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6312 04:38:17.614993 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6313 04:38:17.618279 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6314 04:38:17.621190 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6315 04:38:17.624693 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6316 04:38:17.631464 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6317 04:38:17.634372 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6318 04:38:17.637877 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6319 04:38:17.637958 ==
6320 04:38:17.641298 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 04:38:17.647733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 04:38:17.647817 ==
6323 04:38:17.647883 DQS Delay:
6324 04:38:17.651244 DQS0 = 27, DQS1 = 35
6325 04:38:17.651325 DQM Delay:
6326 04:38:17.651389 DQM0 = 10, DQM1 = 11
6327 04:38:17.654507 DQ Delay:
6328 04:38:17.658072 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6329 04:38:17.658153 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6330 04:38:17.660824 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6331 04:38:17.664208 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6332 04:38:17.664290
6333 04:38:17.667632
6334 04:38:17.667712 ==
6335 04:38:17.671378 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 04:38:17.674305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 04:38:17.674388 ==
6338 04:38:17.674452
6339 04:38:17.674510
6340 04:38:17.677423 TX Vref Scan disable
6341 04:38:17.677505 == TX Byte 0 ==
6342 04:38:17.681208 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 04:38:17.687726 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 04:38:17.687808 == TX Byte 1 ==
6345 04:38:17.690838 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 04:38:17.697394 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 04:38:17.697477 ==
6348 04:38:17.700979 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 04:38:17.704132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 04:38:17.704214 ==
6351 04:38:17.704277
6352 04:38:17.704354
6353 04:38:17.707713 TX Vref Scan disable
6354 04:38:17.707794 == TX Byte 0 ==
6355 04:38:17.710487 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 04:38:17.717272 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 04:38:17.717358 == TX Byte 1 ==
6358 04:38:17.720932 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 04:38:17.727461 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 04:38:17.727593
6361 04:38:17.727659 [DATLAT]
6362 04:38:17.727719 Freq=400, CH0 RK0
6363 04:38:17.730776
6364 04:38:17.730856 DATLAT Default: 0xf
6365 04:38:17.734163 0, 0xFFFF, sum = 0
6366 04:38:17.734246 1, 0xFFFF, sum = 0
6367 04:38:17.737526 2, 0xFFFF, sum = 0
6368 04:38:17.737608 3, 0xFFFF, sum = 0
6369 04:38:17.740418 4, 0xFFFF, sum = 0
6370 04:38:17.740530 5, 0xFFFF, sum = 0
6371 04:38:17.743736 6, 0xFFFF, sum = 0
6372 04:38:17.743817 7, 0xFFFF, sum = 0
6373 04:38:17.747205 8, 0xFFFF, sum = 0
6374 04:38:17.747286 9, 0xFFFF, sum = 0
6375 04:38:17.750846 10, 0xFFFF, sum = 0
6376 04:38:17.750929 11, 0xFFFF, sum = 0
6377 04:38:17.753827 12, 0xFFFF, sum = 0
6378 04:38:17.753908 13, 0x0, sum = 1
6379 04:38:17.757402 14, 0x0, sum = 2
6380 04:38:17.757484 15, 0x0, sum = 3
6381 04:38:17.760679 16, 0x0, sum = 4
6382 04:38:17.760762 best_step = 14
6383 04:38:17.760826
6384 04:38:17.760884 ==
6385 04:38:17.764014 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 04:38:17.770286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 04:38:17.770368 ==
6388 04:38:17.770432 RX Vref Scan: 1
6389 04:38:17.770491
6390 04:38:17.773673 RX Vref 0 -> 0, step: 1
6391 04:38:17.773755
6392 04:38:17.777099 RX Delay -311 -> 252, step: 8
6393 04:38:17.777181
6394 04:38:17.780480 Set Vref, RX VrefLevel [Byte0]: 55
6395 04:38:17.783976 [Byte1]: 55
6396 04:38:17.784074
6397 04:38:17.786867 Final RX Vref Byte 0 = 55 to rank0
6398 04:38:17.790341 Final RX Vref Byte 1 = 55 to rank0
6399 04:38:17.793604 Final RX Vref Byte 0 = 55 to rank1
6400 04:38:17.797446 Final RX Vref Byte 1 = 55 to rank1==
6401 04:38:17.800485 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 04:38:17.803644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 04:38:17.803757 ==
6404 04:38:17.806903 DQS Delay:
6405 04:38:17.807014 DQS0 = 28, DQS1 = 36
6406 04:38:17.810344 DQM Delay:
6407 04:38:17.810454 DQM0 = 10, DQM1 = 12
6408 04:38:17.813743 DQ Delay:
6409 04:38:17.813854 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6410 04:38:17.817174 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6411 04:38:17.820382 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6412 04:38:17.823799 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6413 04:38:17.823881
6414 04:38:17.823944
6415 04:38:17.833455 [DQSOSCAuto] RK0, (LSB)MR18= 0xcab8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6416 04:38:17.836719 CH0 RK0: MR19=C0C, MR18=CAB8
6417 04:38:17.840499 CH0_RK0: MR19=0xC0C, MR18=0xCAB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6418 04:38:17.843372 ==
6419 04:38:17.843454 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 04:38:17.850498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 04:38:17.850582 ==
6422 04:38:17.853434 [Gating] SW mode calibration
6423 04:38:17.860403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 04:38:17.863685 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 04:38:17.870592 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 04:38:17.874117 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 04:38:17.876873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 04:38:17.884028 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 04:38:17.887152 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 04:38:17.890055 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 04:38:17.897167 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 04:38:17.900054 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 04:38:17.903406 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 04:38:17.907025 Total UI for P1: 0, mck2ui 16
6435 04:38:17.910035 best dqsien dly found for B0: ( 0, 14, 24)
6436 04:38:17.913287 Total UI for P1: 0, mck2ui 16
6437 04:38:17.916974 best dqsien dly found for B1: ( 0, 14, 24)
6438 04:38:17.919980 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 04:38:17.923290 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 04:38:17.923372
6441 04:38:17.930115 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 04:38:17.933253 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 04:38:17.933338 [Gating] SW calibration Done
6444 04:38:17.936721 ==
6445 04:38:17.936804 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 04:38:17.942922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 04:38:17.943004 ==
6448 04:38:17.943069 RX Vref Scan: 0
6449 04:38:17.943130
6450 04:38:17.946370 RX Vref 0 -> 0, step: 1
6451 04:38:17.946452
6452 04:38:17.949868 RX Delay -410 -> 252, step: 16
6453 04:38:17.953395 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6454 04:38:17.956070 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6455 04:38:17.962974 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6456 04:38:17.966351 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6457 04:38:17.969751 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6458 04:38:17.972673 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6459 04:38:17.979469 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6460 04:38:17.982608 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6461 04:38:17.985937 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6462 04:38:17.989147 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6463 04:38:17.996103 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6464 04:38:17.999645 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6465 04:38:18.002866 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6466 04:38:18.009318 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6467 04:38:18.012464 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6468 04:38:18.016081 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6469 04:38:18.016162 ==
6470 04:38:18.019145 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 04:38:18.022614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 04:38:18.022699 ==
6473 04:38:18.026065 DQS Delay:
6474 04:38:18.026145 DQS0 = 27, DQS1 = 35
6475 04:38:18.029093 DQM Delay:
6476 04:38:18.029174 DQM0 = 12, DQM1 = 10
6477 04:38:18.032303 DQ Delay:
6478 04:38:18.032384 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6479 04:38:18.035437 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6480 04:38:18.038978 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6481 04:38:18.042389 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6482 04:38:18.042470
6483 04:38:18.042534
6484 04:38:18.042593 ==
6485 04:38:18.045873 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 04:38:18.052172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 04:38:18.052254 ==
6488 04:38:18.052318
6489 04:38:18.052376
6490 04:38:18.052433 TX Vref Scan disable
6491 04:38:18.055451 == TX Byte 0 ==
6492 04:38:18.059168 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6493 04:38:18.062312 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6494 04:38:18.065416 == TX Byte 1 ==
6495 04:38:18.068809 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6496 04:38:18.072156 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6497 04:38:18.072238 ==
6498 04:38:18.075823 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 04:38:18.082083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 04:38:18.082165 ==
6501 04:38:18.082229
6502 04:38:18.082288
6503 04:38:18.082345 TX Vref Scan disable
6504 04:38:18.085608 == TX Byte 0 ==
6505 04:38:18.089028 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6506 04:38:18.092688 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6507 04:38:18.095464 == TX Byte 1 ==
6508 04:38:18.098812 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6509 04:38:18.102357 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6510 04:38:18.102438
6511 04:38:18.105687 [DATLAT]
6512 04:38:18.105767 Freq=400, CH0 RK1
6513 04:38:18.105832
6514 04:38:18.109212 DATLAT Default: 0xe
6515 04:38:18.109293 0, 0xFFFF, sum = 0
6516 04:38:18.112364 1, 0xFFFF, sum = 0
6517 04:38:18.112446 2, 0xFFFF, sum = 0
6518 04:38:18.115659 3, 0xFFFF, sum = 0
6519 04:38:18.115742 4, 0xFFFF, sum = 0
6520 04:38:18.118978 5, 0xFFFF, sum = 0
6521 04:38:18.119060 6, 0xFFFF, sum = 0
6522 04:38:18.122164 7, 0xFFFF, sum = 0
6523 04:38:18.125465 8, 0xFFFF, sum = 0
6524 04:38:18.125547 9, 0xFFFF, sum = 0
6525 04:38:18.128614 10, 0xFFFF, sum = 0
6526 04:38:18.128696 11, 0xFFFF, sum = 0
6527 04:38:18.132105 12, 0xFFFF, sum = 0
6528 04:38:18.132187 13, 0x0, sum = 1
6529 04:38:18.135167 14, 0x0, sum = 2
6530 04:38:18.135248 15, 0x0, sum = 3
6531 04:38:18.138757 16, 0x0, sum = 4
6532 04:38:18.138838 best_step = 14
6533 04:38:18.138902
6534 04:38:18.138961 ==
6535 04:38:18.141935 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 04:38:18.145217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 04:38:18.145303 ==
6538 04:38:18.148458 RX Vref Scan: 0
6539 04:38:18.148539
6540 04:38:18.152004 RX Vref 0 -> 0, step: 1
6541 04:38:18.152085
6542 04:38:18.152149 RX Delay -311 -> 252, step: 8
6543 04:38:18.160377 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6544 04:38:18.163767 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6545 04:38:18.167129 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6546 04:38:18.170231 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6547 04:38:18.176837 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6548 04:38:18.180151 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6549 04:38:18.183715 iDelay=217, Bit 6, Center -8 (-223 ~ 208) 432
6550 04:38:18.187034 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6551 04:38:18.193597 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6552 04:38:18.196862 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6553 04:38:18.200292 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6554 04:38:18.203816 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6555 04:38:18.210119 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6556 04:38:18.213512 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6557 04:38:18.217049 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6558 04:38:18.223492 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6559 04:38:18.223671 ==
6560 04:38:18.226744 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 04:38:18.230373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 04:38:18.230456 ==
6563 04:38:18.230534 DQS Delay:
6564 04:38:18.233553 DQS0 = 24, DQS1 = 32
6565 04:38:18.233635 DQM Delay:
6566 04:38:18.236744 DQM0 = 8, DQM1 = 10
6567 04:38:18.236826 DQ Delay:
6568 04:38:18.240270 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6569 04:38:18.243663 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6570 04:38:18.246621 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6571 04:38:18.250023 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6572 04:38:18.250104
6573 04:38:18.250168
6574 04:38:18.256465 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6575 04:38:18.259871 CH0 RK1: MR19=C0C, MR18=BC5D
6576 04:38:18.266607 CH0_RK1: MR19=0xC0C, MR18=0xBC5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6577 04:38:18.270162 [RxdqsGatingPostProcess] freq 400
6578 04:38:18.273581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 04:38:18.276335 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 04:38:18.279755 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 04:38:18.283130 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 04:38:18.286887 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 04:38:18.289676 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 04:38:18.292869 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 04:38:18.296694 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 04:38:18.299908 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 04:38:18.303236 Pre-setting of DQS Precalculation
6588 04:38:18.306397 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 04:38:18.309511 ==
6590 04:38:18.309596 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 04:38:18.316449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 04:38:18.316531 ==
6593 04:38:18.319907 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 04:38:18.326261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6595 04:38:18.329575 [CA 0] Center 36 (8~64) winsize 57
6596 04:38:18.333066 [CA 1] Center 36 (8~64) winsize 57
6597 04:38:18.336693 [CA 2] Center 36 (8~64) winsize 57
6598 04:38:18.339635 [CA 3] Center 36 (8~64) winsize 57
6599 04:38:18.344926 [CA 4] Center 36 (8~64) winsize 57
6600 04:38:18.346611 [CA 5] Center 36 (8~64) winsize 57
6601 04:38:18.346710
6602 04:38:18.350037 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6603 04:38:18.350139
6604 04:38:18.352908 [CATrainingPosCal] consider 1 rank data
6605 04:38:18.356263 u2DelayCellTimex100 = 270/100 ps
6606 04:38:18.359653 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 04:38:18.363090 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 04:38:18.366372 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 04:38:18.369846 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 04:38:18.373141 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 04:38:18.379475 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 04:38:18.379619
6613 04:38:18.382948 CA PerBit enable=1, Macro0, CA PI delay=36
6614 04:38:18.383028
6615 04:38:18.386339 [CBTSetCACLKResult] CA Dly = 36
6616 04:38:18.386421 CS Dly: 1 (0~32)
6617 04:38:18.386485 ==
6618 04:38:18.389353 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 04:38:18.392901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 04:38:18.396282 ==
6621 04:38:18.399753 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 04:38:18.406061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 04:38:18.409318 [CA 0] Center 36 (8~64) winsize 57
6624 04:38:18.412979 [CA 1] Center 36 (8~64) winsize 57
6625 04:38:18.416100 [CA 2] Center 36 (8~64) winsize 57
6626 04:38:18.419147 [CA 3] Center 36 (8~64) winsize 57
6627 04:38:18.422450 [CA 4] Center 36 (8~64) winsize 57
6628 04:38:18.425895 [CA 5] Center 36 (8~64) winsize 57
6629 04:38:18.426002
6630 04:38:18.429635 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 04:38:18.429717
6632 04:38:18.432604 [CATrainingPosCal] consider 2 rank data
6633 04:38:18.436022 u2DelayCellTimex100 = 270/100 ps
6634 04:38:18.439643 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 04:38:18.442510 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 04:38:18.445859 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 04:38:18.449262 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 04:38:18.452390 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 04:38:18.455704 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 04:38:18.455784
6641 04:38:18.462474 CA PerBit enable=1, Macro0, CA PI delay=36
6642 04:38:18.462555
6643 04:38:18.462618 [CBTSetCACLKResult] CA Dly = 36
6644 04:38:18.465741 CS Dly: 1 (0~32)
6645 04:38:18.465822
6646 04:38:18.469059 ----->DramcWriteLeveling(PI) begin...
6647 04:38:18.469142 ==
6648 04:38:18.472002 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 04:38:18.475647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 04:38:18.475728 ==
6651 04:38:18.478753 Write leveling (Byte 0): 40 => 8
6652 04:38:18.482183 Write leveling (Byte 1): 40 => 8
6653 04:38:18.485530 DramcWriteLeveling(PI) end<-----
6654 04:38:18.485611
6655 04:38:18.485675 ==
6656 04:38:18.489051 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 04:38:18.492302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 04:38:18.492383 ==
6659 04:38:18.495783 [Gating] SW mode calibration
6660 04:38:18.502146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 04:38:18.509139 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 04:38:18.512618 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 04:38:18.519094 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 04:38:18.522497 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 04:38:18.525760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 04:38:18.529525 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 04:38:18.535803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 04:38:18.539288 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 04:38:18.542523 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 04:38:18.549290 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 04:38:18.552266 Total UI for P1: 0, mck2ui 16
6672 04:38:18.555634 best dqsien dly found for B0: ( 0, 14, 24)
6673 04:38:18.558775 Total UI for P1: 0, mck2ui 16
6674 04:38:18.562666 best dqsien dly found for B1: ( 0, 14, 24)
6675 04:38:18.566005 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 04:38:18.568810 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 04:38:18.568892
6678 04:38:18.572358 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 04:38:18.575800 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 04:38:18.578745 [Gating] SW calibration Done
6681 04:38:18.578826 ==
6682 04:38:18.582104 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 04:38:18.585335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 04:38:18.585416 ==
6685 04:38:18.588899 RX Vref Scan: 0
6686 04:38:18.588979
6687 04:38:18.592123 RX Vref 0 -> 0, step: 1
6688 04:38:18.592204
6689 04:38:18.592271 RX Delay -410 -> 252, step: 16
6690 04:38:18.598592 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6691 04:38:18.602027 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6692 04:38:18.605544 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6693 04:38:18.608970 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6694 04:38:18.615339 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6695 04:38:18.618826 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6696 04:38:18.621854 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6697 04:38:18.625342 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6698 04:38:18.631830 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6699 04:38:18.635302 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6700 04:38:18.638550 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6701 04:38:18.641778 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6702 04:38:18.648556 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6703 04:38:18.652297 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6704 04:38:18.655248 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6705 04:38:18.658833 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6706 04:38:18.662140 ==
6707 04:38:18.665663 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 04:38:18.668931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 04:38:18.669013 ==
6710 04:38:18.669078 DQS Delay:
6711 04:38:18.672287 DQS0 = 27, DQS1 = 35
6712 04:38:18.672367 DQM Delay:
6713 04:38:18.675444 DQM0 = 10, DQM1 = 13
6714 04:38:18.675589 DQ Delay:
6715 04:38:18.678703 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6716 04:38:18.682177 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6717 04:38:18.685484 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6718 04:38:18.688556 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6719 04:38:18.688637
6720 04:38:18.688701
6721 04:38:18.688804 ==
6722 04:38:18.691775 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 04:38:18.695055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 04:38:18.695136 ==
6725 04:38:18.695200
6726 04:38:18.695259
6727 04:38:18.698547 TX Vref Scan disable
6728 04:38:18.698628 == TX Byte 0 ==
6729 04:38:18.704948 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 04:38:18.708304 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 04:38:18.708385 == TX Byte 1 ==
6732 04:38:18.715314 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 04:38:18.718369 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 04:38:18.718476 ==
6735 04:38:18.721671 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 04:38:18.725053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 04:38:18.725135 ==
6738 04:38:18.725199
6739 04:38:18.725258
6740 04:38:18.728452 TX Vref Scan disable
6741 04:38:18.728533 == TX Byte 0 ==
6742 04:38:18.734980 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 04:38:18.738714 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 04:38:18.738795 == TX Byte 1 ==
6745 04:38:18.744810 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 04:38:18.748079 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 04:38:18.748160
6748 04:38:18.748223 [DATLAT]
6749 04:38:18.751463 Freq=400, CH1 RK0
6750 04:38:18.751597
6751 04:38:18.751663 DATLAT Default: 0xf
6752 04:38:18.754853 0, 0xFFFF, sum = 0
6753 04:38:18.754951 1, 0xFFFF, sum = 0
6754 04:38:18.758375 2, 0xFFFF, sum = 0
6755 04:38:18.758457 3, 0xFFFF, sum = 0
6756 04:38:18.761331 4, 0xFFFF, sum = 0
6757 04:38:18.761415 5, 0xFFFF, sum = 0
6758 04:38:18.765120 6, 0xFFFF, sum = 0
6759 04:38:18.765202 7, 0xFFFF, sum = 0
6760 04:38:18.768280 8, 0xFFFF, sum = 0
6761 04:38:18.768362 9, 0xFFFF, sum = 0
6762 04:38:18.771379 10, 0xFFFF, sum = 0
6763 04:38:18.775172 11, 0xFFFF, sum = 0
6764 04:38:18.775254 12, 0xFFFF, sum = 0
6765 04:38:18.777996 13, 0x0, sum = 1
6766 04:38:18.778078 14, 0x0, sum = 2
6767 04:38:18.781786 15, 0x0, sum = 3
6768 04:38:18.781869 16, 0x0, sum = 4
6769 04:38:18.781934 best_step = 14
6770 04:38:18.782027
6771 04:38:18.784788 ==
6772 04:38:18.787933 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 04:38:18.791226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 04:38:18.791310 ==
6775 04:38:18.791376 RX Vref Scan: 1
6776 04:38:18.791437
6777 04:38:18.794968 RX Vref 0 -> 0, step: 1
6778 04:38:18.795051
6779 04:38:18.798237 RX Delay -311 -> 252, step: 8
6780 04:38:18.798319
6781 04:38:18.801569 Set Vref, RX VrefLevel [Byte0]: 56
6782 04:38:18.804390 [Byte1]: 54
6783 04:38:18.808190
6784 04:38:18.808272 Final RX Vref Byte 0 = 56 to rank0
6785 04:38:18.811467 Final RX Vref Byte 1 = 54 to rank0
6786 04:38:18.814904 Final RX Vref Byte 0 = 56 to rank1
6787 04:38:18.817761 Final RX Vref Byte 1 = 54 to rank1==
6788 04:38:18.821246 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 04:38:18.828234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 04:38:18.828316 ==
6791 04:38:18.828381 DQS Delay:
6792 04:38:18.831124 DQS0 = 28, DQS1 = 32
6793 04:38:18.831205 DQM Delay:
6794 04:38:18.831269 DQM0 = 9, DQM1 = 10
6795 04:38:18.834587 DQ Delay:
6796 04:38:18.838223 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6797 04:38:18.838304 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6798 04:38:18.841181 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6799 04:38:18.844702 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6800 04:38:18.844783
6801 04:38:18.844848
6802 04:38:18.854532 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6803 04:38:18.858021 CH1 RK0: MR19=C0C, MR18=93CB
6804 04:38:18.864793 CH1_RK0: MR19=0xC0C, MR18=0x93CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6805 04:38:18.864876 ==
6806 04:38:18.868070 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 04:38:18.871154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 04:38:18.871236 ==
6809 04:38:18.874449 [Gating] SW mode calibration
6810 04:38:18.881083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 04:38:18.884819 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 04:38:18.891107 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 04:38:18.894657 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 04:38:18.897668 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 04:38:18.904470 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 04:38:18.908041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 04:38:18.911038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 04:38:18.918035 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 04:38:18.921084 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 04:38:18.924666 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 04:38:18.927663 Total UI for P1: 0, mck2ui 16
6822 04:38:18.931246 best dqsien dly found for B0: ( 0, 14, 24)
6823 04:38:18.934698 Total UI for P1: 0, mck2ui 16
6824 04:38:18.937689 best dqsien dly found for B1: ( 0, 14, 24)
6825 04:38:18.941085 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 04:38:18.944621 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 04:38:18.944702
6828 04:38:18.951370 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 04:38:18.954185 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 04:38:18.954266 [Gating] SW calibration Done
6831 04:38:18.957678 ==
6832 04:38:18.961165 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 04:38:18.964615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 04:38:18.964697 ==
6835 04:38:18.964784 RX Vref Scan: 0
6836 04:38:18.964857
6837 04:38:18.967810 RX Vref 0 -> 0, step: 1
6838 04:38:18.967891
6839 04:38:18.971111 RX Delay -410 -> 252, step: 16
6840 04:38:18.974312 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6841 04:38:18.977985 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6842 04:38:18.984075 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6843 04:38:18.987452 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6844 04:38:18.991025 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6845 04:38:18.994521 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6846 04:38:19.001009 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6847 04:38:19.004498 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6848 04:38:19.007904 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6849 04:38:19.011147 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6850 04:38:19.018049 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6851 04:38:19.021073 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6852 04:38:19.024293 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6853 04:38:19.027802 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6854 04:38:19.034669 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6855 04:38:19.037901 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6856 04:38:19.037982 ==
6857 04:38:19.041231 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 04:38:19.044602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 04:38:19.044684 ==
6860 04:38:19.048141 DQS Delay:
6861 04:38:19.048222 DQS0 = 27, DQS1 = 35
6862 04:38:19.050993 DQM Delay:
6863 04:38:19.051074 DQM0 = 11, DQM1 = 15
6864 04:38:19.051137 DQ Delay:
6865 04:38:19.054339 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6866 04:38:19.057785 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6867 04:38:19.061273 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6868 04:38:19.064243 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6869 04:38:19.064324
6870 04:38:19.064387
6871 04:38:19.064447 ==
6872 04:38:19.067711 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 04:38:19.071444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 04:38:19.074268 ==
6875 04:38:19.074349
6876 04:38:19.074412
6877 04:38:19.074470 TX Vref Scan disable
6878 04:38:19.078040 == TX Byte 0 ==
6879 04:38:19.081454 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6880 04:38:19.084948 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6881 04:38:19.087632 == TX Byte 1 ==
6882 04:38:19.091204 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6883 04:38:19.094444 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6884 04:38:19.094526 ==
6885 04:38:19.097606 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 04:38:19.100923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 04:38:19.104462 ==
6888 04:38:19.104544
6889 04:38:19.104608
6890 04:38:19.104667 TX Vref Scan disable
6891 04:38:19.107739 == TX Byte 0 ==
6892 04:38:19.111251 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6893 04:38:19.114028 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6894 04:38:19.117882 == TX Byte 1 ==
6895 04:38:19.120675 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6896 04:38:19.124304 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6897 04:38:19.124385
6898 04:38:19.127564 [DATLAT]
6899 04:38:19.127659 Freq=400, CH1 RK1
6900 04:38:19.127723
6901 04:38:19.130977 DATLAT Default: 0xe
6902 04:38:19.131057 0, 0xFFFF, sum = 0
6903 04:38:19.133798 1, 0xFFFF, sum = 0
6904 04:38:19.133881 2, 0xFFFF, sum = 0
6905 04:38:19.137095 3, 0xFFFF, sum = 0
6906 04:38:19.137178 4, 0xFFFF, sum = 0
6907 04:38:19.140908 5, 0xFFFF, sum = 0
6908 04:38:19.140990 6, 0xFFFF, sum = 0
6909 04:38:19.143818 7, 0xFFFF, sum = 0
6910 04:38:19.143900 8, 0xFFFF, sum = 0
6911 04:38:19.147273 9, 0xFFFF, sum = 0
6912 04:38:19.147356 10, 0xFFFF, sum = 0
6913 04:38:19.150756 11, 0xFFFF, sum = 0
6914 04:38:19.154054 12, 0xFFFF, sum = 0
6915 04:38:19.154137 13, 0x0, sum = 1
6916 04:38:19.154202 14, 0x0, sum = 2
6917 04:38:19.157002 15, 0x0, sum = 3
6918 04:38:19.157084 16, 0x0, sum = 4
6919 04:38:19.160344 best_step = 14
6920 04:38:19.160425
6921 04:38:19.160489 ==
6922 04:38:19.163987 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 04:38:19.166795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 04:38:19.166876 ==
6925 04:38:19.170285 RX Vref Scan: 0
6926 04:38:19.170365
6927 04:38:19.170429 RX Vref 0 -> 0, step: 1
6928 04:38:19.173315
6929 04:38:19.173396 RX Delay -311 -> 252, step: 8
6930 04:38:19.181595 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6931 04:38:19.184836 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6932 04:38:19.188718 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6933 04:38:19.191541 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6934 04:38:19.198474 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6935 04:38:19.201256 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6936 04:38:19.205088 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6937 04:38:19.208206 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6938 04:38:19.214666 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6939 04:38:19.218553 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6940 04:38:19.221488 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6941 04:38:19.225048 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6942 04:38:19.231697 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6943 04:38:19.234457 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6944 04:38:19.238123 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6945 04:38:19.245207 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6946 04:38:19.245288 ==
6947 04:38:19.247885 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 04:38:19.251121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 04:38:19.251202 ==
6950 04:38:19.251266 DQS Delay:
6951 04:38:19.254741 DQS0 = 32, DQS1 = 32
6952 04:38:19.254821 DQM Delay:
6953 04:38:19.258151 DQM0 = 14, DQM1 = 11
6954 04:38:19.258232 DQ Delay:
6955 04:38:19.261511 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6956 04:38:19.264672 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =16
6957 04:38:19.267813 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6958 04:38:19.271014 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6959 04:38:19.271095
6960 04:38:19.271173
6961 04:38:19.278065 [DQSOSCAuto] RK1, (LSB)MR18= 0xc456, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6962 04:38:19.281008 CH1 RK1: MR19=C0C, MR18=C456
6963 04:38:19.288045 CH1_RK1: MR19=0xC0C, MR18=0xC456, DQSOSC=385, MR23=63, INC=398, DEC=265
6964 04:38:19.291130 [RxdqsGatingPostProcess] freq 400
6965 04:38:19.297877 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 04:38:19.297965 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 04:38:19.301042 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 04:38:19.304577 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 04:38:19.308035 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 04:38:19.310820 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 04:38:19.314485 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 04:38:19.317923 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 04:38:19.321312 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 04:38:19.324463 Pre-setting of DQS Precalculation
6975 04:38:19.331201 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 04:38:19.337712 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 04:38:19.344637 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 04:38:19.344718
6979 04:38:19.344816
6980 04:38:19.347681 [Calibration Summary] 800 Mbps
6981 04:38:19.347762 CH 0, Rank 0
6982 04:38:19.351095 SW Impedance : PASS
6983 04:38:19.351176 DUTY Scan : NO K
6984 04:38:19.354551 ZQ Calibration : PASS
6985 04:38:19.357577 Jitter Meter : NO K
6986 04:38:19.357658 CBT Training : PASS
6987 04:38:19.361090 Write leveling : PASS
6988 04:38:19.364194 RX DQS gating : PASS
6989 04:38:19.364275 RX DQ/DQS(RDDQC) : PASS
6990 04:38:19.367838 TX DQ/DQS : PASS
6991 04:38:19.370841 RX DATLAT : PASS
6992 04:38:19.370921 RX DQ/DQS(Engine): PASS
6993 04:38:19.374458 TX OE : NO K
6994 04:38:19.374540 All Pass.
6995 04:38:19.374648
6996 04:38:19.377962 CH 0, Rank 1
6997 04:38:19.378042 SW Impedance : PASS
6998 04:38:19.381089 DUTY Scan : NO K
6999 04:38:19.384558 ZQ Calibration : PASS
7000 04:38:19.384639 Jitter Meter : NO K
7001 04:38:19.388014 CBT Training : PASS
7002 04:38:19.390922 Write leveling : NO K
7003 04:38:19.391003 RX DQS gating : PASS
7004 04:38:19.394547 RX DQ/DQS(RDDQC) : PASS
7005 04:38:19.394628 TX DQ/DQS : PASS
7006 04:38:19.397954 RX DATLAT : PASS
7007 04:38:19.400725 RX DQ/DQS(Engine): PASS
7008 04:38:19.400806 TX OE : NO K
7009 04:38:19.404549 All Pass.
7010 04:38:19.404630
7011 04:38:19.404694 CH 1, Rank 0
7012 04:38:19.407365 SW Impedance : PASS
7013 04:38:19.407446 DUTY Scan : NO K
7014 04:38:19.410825 ZQ Calibration : PASS
7015 04:38:19.414201 Jitter Meter : NO K
7016 04:38:19.414282 CBT Training : PASS
7017 04:38:19.417857 Write leveling : PASS
7018 04:38:19.420671 RX DQS gating : PASS
7019 04:38:19.420752 RX DQ/DQS(RDDQC) : PASS
7020 04:38:19.424210 TX DQ/DQS : PASS
7021 04:38:19.427682 RX DATLAT : PASS
7022 04:38:19.427764 RX DQ/DQS(Engine): PASS
7023 04:38:19.430595 TX OE : NO K
7024 04:38:19.430676 All Pass.
7025 04:38:19.430739
7026 04:38:19.434081 CH 1, Rank 1
7027 04:38:19.434191 SW Impedance : PASS
7028 04:38:19.437233 DUTY Scan : NO K
7029 04:38:19.440756 ZQ Calibration : PASS
7030 04:38:19.440837 Jitter Meter : NO K
7031 04:38:19.444035 CBT Training : PASS
7032 04:38:19.447451 Write leveling : NO K
7033 04:38:19.447569 RX DQS gating : PASS
7034 04:38:19.450710 RX DQ/DQS(RDDQC) : PASS
7035 04:38:19.450790 TX DQ/DQS : PASS
7036 04:38:19.453969 RX DATLAT : PASS
7037 04:38:19.457541 RX DQ/DQS(Engine): PASS
7038 04:38:19.457622 TX OE : NO K
7039 04:38:19.460517 All Pass.
7040 04:38:19.460597
7041 04:38:19.460661 DramC Write-DBI off
7042 04:38:19.464025 PER_BANK_REFRESH: Hybrid Mode
7043 04:38:19.467425 TX_TRACKING: ON
7044 04:38:19.473762 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 04:38:19.477040 [FAST_K] Save calibration result to emmc
7046 04:38:19.483911 dramc_set_vcore_voltage set vcore to 725000
7047 04:38:19.484004 Read voltage for 1600, 0
7048 04:38:19.484069 Vio18 = 0
7049 04:38:19.487174 Vcore = 725000
7050 04:38:19.487254 Vdram = 0
7051 04:38:19.487318 Vddq = 0
7052 04:38:19.490282 Vmddr = 0
7053 04:38:19.493623 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 04:38:19.500276 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 04:38:19.503528 MEM_TYPE=3, freq_sel=13
7056 04:38:19.503640 sv_algorithm_assistance_LP4_3733
7057 04:38:19.510028 ============ PULL DRAM RESETB DOWN ============
7058 04:38:19.513498 ========== PULL DRAM RESETB DOWN end =========
7059 04:38:19.516446 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 04:38:19.519878 ===================================
7061 04:38:19.523485 LPDDR4 DRAM CONFIGURATION
7062 04:38:19.526884 ===================================
7063 04:38:19.529719 EX_ROW_EN[0] = 0x0
7064 04:38:19.529800 EX_ROW_EN[1] = 0x0
7065 04:38:19.533180 LP4Y_EN = 0x0
7066 04:38:19.533260 WORK_FSP = 0x1
7067 04:38:19.536592 WL = 0x5
7068 04:38:19.536672 RL = 0x5
7069 04:38:19.539559 BL = 0x2
7070 04:38:19.539639 RPST = 0x0
7071 04:38:19.543024 RD_PRE = 0x0
7072 04:38:19.543104 WR_PRE = 0x1
7073 04:38:19.546496 WR_PST = 0x1
7074 04:38:19.549727 DBI_WR = 0x0
7075 04:38:19.549808 DBI_RD = 0x0
7076 04:38:19.552838 OTF = 0x1
7077 04:38:19.556221 ===================================
7078 04:38:19.559503 ===================================
7079 04:38:19.559592 ANA top config
7080 04:38:19.562757 ===================================
7081 04:38:19.566322 DLL_ASYNC_EN = 0
7082 04:38:19.566402 ALL_SLAVE_EN = 0
7083 04:38:19.569901 NEW_RANK_MODE = 1
7084 04:38:19.572865 DLL_IDLE_MODE = 1
7085 04:38:19.576488 LP45_APHY_COMB_EN = 1
7086 04:38:19.579405 TX_ODT_DIS = 0
7087 04:38:19.579487 NEW_8X_MODE = 1
7088 04:38:19.582948 ===================================
7089 04:38:19.586370 ===================================
7090 04:38:19.589411 data_rate = 3200
7091 04:38:19.593094 CKR = 1
7092 04:38:19.596091 DQ_P2S_RATIO = 8
7093 04:38:19.599796 ===================================
7094 04:38:19.603026 CA_P2S_RATIO = 8
7095 04:38:19.606609 DQ_CA_OPEN = 0
7096 04:38:19.606689 DQ_SEMI_OPEN = 0
7097 04:38:19.609425 CA_SEMI_OPEN = 0
7098 04:38:19.612855 CA_FULL_RATE = 0
7099 04:38:19.616044 DQ_CKDIV4_EN = 0
7100 04:38:19.619410 CA_CKDIV4_EN = 0
7101 04:38:19.619491 CA_PREDIV_EN = 0
7102 04:38:19.623164 PH8_DLY = 12
7103 04:38:19.626077 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 04:38:19.629320 DQ_AAMCK_DIV = 4
7105 04:38:19.632774 CA_AAMCK_DIV = 4
7106 04:38:19.636134 CA_ADMCK_DIV = 4
7107 04:38:19.639288 DQ_TRACK_CA_EN = 0
7108 04:38:19.639375 CA_PICK = 1600
7109 04:38:19.642710 CA_MCKIO = 1600
7110 04:38:19.646192 MCKIO_SEMI = 0
7111 04:38:19.649824 PLL_FREQ = 3068
7112 04:38:19.653116 DQ_UI_PI_RATIO = 32
7113 04:38:19.656377 CA_UI_PI_RATIO = 0
7114 04:38:19.659785 ===================================
7115 04:38:19.662669 ===================================
7116 04:38:19.662765 memory_type:LPDDR4
7117 04:38:19.665890 GP_NUM : 10
7118 04:38:19.669621 SRAM_EN : 1
7119 04:38:19.669702 MD32_EN : 0
7120 04:38:19.672914 ===================================
7121 04:38:19.676460 [ANA_INIT] >>>>>>>>>>>>>>
7122 04:38:19.679783 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 04:38:19.682697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 04:38:19.686023 ===================================
7125 04:38:19.689567 data_rate = 3200,PCW = 0X7600
7126 04:38:19.692964 ===================================
7127 04:38:19.696284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 04:38:19.699272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 04:38:19.705980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 04:38:19.709230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 04:38:19.712486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 04:38:19.716115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 04:38:19.719646 [ANA_INIT] flow start
7134 04:38:19.722814 [ANA_INIT] PLL >>>>>>>>
7135 04:38:19.722896 [ANA_INIT] PLL <<<<<<<<
7136 04:38:19.726044 [ANA_INIT] MIDPI >>>>>>>>
7137 04:38:19.729141 [ANA_INIT] MIDPI <<<<<<<<
7138 04:38:19.732543 [ANA_INIT] DLL >>>>>>>>
7139 04:38:19.732623 [ANA_INIT] DLL <<<<<<<<
7140 04:38:19.736138 [ANA_INIT] flow end
7141 04:38:19.739113 ============ LP4 DIFF to SE enter ============
7142 04:38:19.742374 ============ LP4 DIFF to SE exit ============
7143 04:38:19.745919 [ANA_INIT] <<<<<<<<<<<<<
7144 04:38:19.749161 [Flow] Enable top DCM control >>>>>
7145 04:38:19.752853 [Flow] Enable top DCM control <<<<<
7146 04:38:19.755732 Enable DLL master slave shuffle
7147 04:38:19.762249 ==============================================================
7148 04:38:19.762330 Gating Mode config
7149 04:38:19.769379 ==============================================================
7150 04:38:19.769461 Config description:
7151 04:38:19.778801 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 04:38:19.785893 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 04:38:19.792322 SELPH_MODE 0: By rank 1: By Phase
7154 04:38:19.795756 ==============================================================
7155 04:38:19.799155 GAT_TRACK_EN = 1
7156 04:38:19.802515 RX_GATING_MODE = 2
7157 04:38:19.805807 RX_GATING_TRACK_MODE = 2
7158 04:38:19.809024 SELPH_MODE = 1
7159 04:38:19.812335 PICG_EARLY_EN = 1
7160 04:38:19.815743 VALID_LAT_VALUE = 1
7161 04:38:19.819223 ==============================================================
7162 04:38:19.822484 Enter into Gating configuration >>>>
7163 04:38:19.825516 Exit from Gating configuration <<<<
7164 04:38:19.829360 Enter into DVFS_PRE_config >>>>>
7165 04:38:19.842272 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 04:38:19.845228 Exit from DVFS_PRE_config <<<<<
7167 04:38:19.848624 Enter into PICG configuration >>>>
7168 04:38:19.851942 Exit from PICG configuration <<<<
7169 04:38:19.852022 [RX_INPUT] configuration >>>>>
7170 04:38:19.855473 [RX_INPUT] configuration <<<<<
7171 04:38:19.861884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 04:38:19.865288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 04:38:19.872405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 04:38:19.879060 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 04:38:19.885783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 04:38:19.891920 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 04:38:19.895556 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 04:38:19.898939 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 04:38:19.902019 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 04:38:19.908490 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 04:38:19.911910 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 04:38:19.915133 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 04:38:19.918374 ===================================
7184 04:38:19.921935 LPDDR4 DRAM CONFIGURATION
7185 04:38:19.925441 ===================================
7186 04:38:19.928826 EX_ROW_EN[0] = 0x0
7187 04:38:19.928908 EX_ROW_EN[1] = 0x0
7188 04:38:19.931992 LP4Y_EN = 0x0
7189 04:38:19.932072 WORK_FSP = 0x1
7190 04:38:19.935124 WL = 0x5
7191 04:38:19.935205 RL = 0x5
7192 04:38:19.938922 BL = 0x2
7193 04:38:19.939003 RPST = 0x0
7194 04:38:19.942192 RD_PRE = 0x0
7195 04:38:19.942273 WR_PRE = 0x1
7196 04:38:19.945110 WR_PST = 0x1
7197 04:38:19.945191 DBI_WR = 0x0
7198 04:38:19.948607 DBI_RD = 0x0
7199 04:38:19.948688 OTF = 0x1
7200 04:38:19.951633 ===================================
7201 04:38:19.958393 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 04:38:19.961596 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 04:38:19.965241 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 04:38:19.968810 ===================================
7205 04:38:19.971664 LPDDR4 DRAM CONFIGURATION
7206 04:38:19.975204 ===================================
7207 04:38:19.975286 EX_ROW_EN[0] = 0x10
7208 04:38:19.978596 EX_ROW_EN[1] = 0x0
7209 04:38:19.982419 LP4Y_EN = 0x0
7210 04:38:19.982500 WORK_FSP = 0x1
7211 04:38:19.985176 WL = 0x5
7212 04:38:19.985257 RL = 0x5
7213 04:38:19.988524 BL = 0x2
7214 04:38:19.988605 RPST = 0x0
7215 04:38:19.991740 RD_PRE = 0x0
7216 04:38:19.991821 WR_PRE = 0x1
7217 04:38:19.995060 WR_PST = 0x1
7218 04:38:19.995141 DBI_WR = 0x0
7219 04:38:19.998642 DBI_RD = 0x0
7220 04:38:19.998760 OTF = 0x1
7221 04:38:20.002007 ===================================
7222 04:38:20.008432 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 04:38:20.008515 ==
7224 04:38:20.011784 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 04:38:20.015251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 04:38:20.018639 ==
7227 04:38:20.018720 [Duty_Offset_Calibration]
7228 04:38:20.021942 B0:2 B1:1 CA:1
7229 04:38:20.022023
7230 04:38:20.025168 [DutyScan_Calibration_Flow] k_type=0
7231 04:38:20.033933
7232 04:38:20.034043 ==CLK 0==
7233 04:38:20.037275 Final CLK duty delay cell = 0
7234 04:38:20.040709 [0] MAX Duty = 5156%(X100), DQS PI = 22
7235 04:38:20.043854 [0] MIN Duty = 4876%(X100), DQS PI = 48
7236 04:38:20.043935 [0] AVG Duty = 5016%(X100)
7237 04:38:20.047061
7238 04:38:20.050709 CH0 CLK Duty spec in!! Max-Min= 280%
7239 04:38:20.053782 [DutyScan_Calibration_Flow] ====Done====
7240 04:38:20.053863
7241 04:38:20.056979 [DutyScan_Calibration_Flow] k_type=1
7242 04:38:20.073150
7243 04:38:20.073230 ==DQS 0 ==
7244 04:38:20.076421 Final DQS duty delay cell = -4
7245 04:38:20.079726 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7246 04:38:20.083092 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7247 04:38:20.086339 [-4] AVG Duty = 4891%(X100)
7248 04:38:20.086420
7249 04:38:20.086484 ==DQS 1 ==
7250 04:38:20.089639 Final DQS duty delay cell = 0
7251 04:38:20.092792 [0] MAX Duty = 5218%(X100), DQS PI = 22
7252 04:38:20.096279 [0] MIN Duty = 5062%(X100), DQS PI = 32
7253 04:38:20.099460 [0] AVG Duty = 5140%(X100)
7254 04:38:20.099593
7255 04:38:20.102873 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7256 04:38:20.102970
7257 04:38:20.106437 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7258 04:38:20.109333 [DutyScan_Calibration_Flow] ====Done====
7259 04:38:20.109399
7260 04:38:20.112685 [DutyScan_Calibration_Flow] k_type=3
7261 04:38:20.129514
7262 04:38:20.129621 ==DQM 0 ==
7263 04:38:20.133061 Final DQM duty delay cell = 0
7264 04:38:20.136514 [0] MAX Duty = 5218%(X100), DQS PI = 34
7265 04:38:20.139882 [0] MIN Duty = 4907%(X100), DQS PI = 54
7266 04:38:20.142796 [0] AVG Duty = 5062%(X100)
7267 04:38:20.142866
7268 04:38:20.142925 ==DQM 1 ==
7269 04:38:20.146252 Final DQM duty delay cell = -4
7270 04:38:20.149734 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7271 04:38:20.153004 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7272 04:38:20.156609 [-4] AVG Duty = 4906%(X100)
7273 04:38:20.156709
7274 04:38:20.159754 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7275 04:38:20.159826
7276 04:38:20.163214 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7277 04:38:20.166121 [DutyScan_Calibration_Flow] ====Done====
7278 04:38:20.166203
7279 04:38:20.169579 [DutyScan_Calibration_Flow] k_type=2
7280 04:38:20.187219
7281 04:38:20.187302 ==DQ 0 ==
7282 04:38:20.190468 Final DQ duty delay cell = 0
7283 04:38:20.193566 [0] MAX Duty = 5062%(X100), DQS PI = 24
7284 04:38:20.197007 [0] MIN Duty = 4907%(X100), DQS PI = 0
7285 04:38:20.197089 [0] AVG Duty = 4984%(X100)
7286 04:38:20.197153
7287 04:38:20.200405 ==DQ 1 ==
7288 04:38:20.203669 Final DQ duty delay cell = 0
7289 04:38:20.206859 [0] MAX Duty = 5125%(X100), DQS PI = 4
7290 04:38:20.210580 [0] MIN Duty = 4907%(X100), DQS PI = 34
7291 04:38:20.210681 [0] AVG Duty = 5016%(X100)
7292 04:38:20.210770
7293 04:38:20.213429 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7294 04:38:20.217140
7295 04:38:20.220251 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7296 04:38:20.223713 [DutyScan_Calibration_Flow] ====Done====
7297 04:38:20.223783 ==
7298 04:38:20.226664 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 04:38:20.230282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 04:38:20.230377 ==
7301 04:38:20.233493 [Duty_Offset_Calibration]
7302 04:38:20.233561 B0:1 B1:0 CA:0
7303 04:38:20.233619
7304 04:38:20.236605 [DutyScan_Calibration_Flow] k_type=0
7305 04:38:20.246497
7306 04:38:20.246577 ==CLK 0==
7307 04:38:20.249975 Final CLK duty delay cell = -4
7308 04:38:20.252918 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7309 04:38:20.256436 [-4] MIN Duty = 4875%(X100), DQS PI = 2
7310 04:38:20.259939 [-4] AVG Duty = 4937%(X100)
7311 04:38:20.260020
7312 04:38:20.263366 CH1 CLK Duty spec in!! Max-Min= 125%
7313 04:38:20.266572 [DutyScan_Calibration_Flow] ====Done====
7314 04:38:20.266653
7315 04:38:20.269412 [DutyScan_Calibration_Flow] k_type=1
7316 04:38:20.286593
7317 04:38:20.286675 ==DQS 0 ==
7318 04:38:20.289600 Final DQS duty delay cell = 0
7319 04:38:20.292840 [0] MAX Duty = 5094%(X100), DQS PI = 12
7320 04:38:20.296493 [0] MIN Duty = 4844%(X100), DQS PI = 48
7321 04:38:20.299942 [0] AVG Duty = 4969%(X100)
7322 04:38:20.300023
7323 04:38:20.300086 ==DQS 1 ==
7324 04:38:20.303272 Final DQS duty delay cell = 0
7325 04:38:20.306737 [0] MAX Duty = 5249%(X100), DQS PI = 16
7326 04:38:20.309528 [0] MIN Duty = 4969%(X100), DQS PI = 6
7327 04:38:20.309609 [0] AVG Duty = 5109%(X100)
7328 04:38:20.312915
7329 04:38:20.316152 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7330 04:38:20.316233
7331 04:38:20.319946 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7332 04:38:20.323119 [DutyScan_Calibration_Flow] ====Done====
7333 04:38:20.323200
7334 04:38:20.326466 [DutyScan_Calibration_Flow] k_type=3
7335 04:38:20.343366
7336 04:38:20.343448 ==DQM 0 ==
7337 04:38:20.346750 Final DQM duty delay cell = 0
7338 04:38:20.350208 [0] MAX Duty = 5218%(X100), DQS PI = 18
7339 04:38:20.353595 [0] MIN Duty = 4969%(X100), DQS PI = 48
7340 04:38:20.356463 [0] AVG Duty = 5093%(X100)
7341 04:38:20.356544
7342 04:38:20.356608 ==DQM 1 ==
7343 04:38:20.359933 Final DQM duty delay cell = 0
7344 04:38:20.363318 [0] MAX Duty = 5093%(X100), DQS PI = 16
7345 04:38:20.366311 [0] MIN Duty = 4907%(X100), DQS PI = 34
7346 04:38:20.369794 [0] AVG Duty = 5000%(X100)
7347 04:38:20.369874
7348 04:38:20.372956 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7349 04:38:20.373037
7350 04:38:20.376223 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7351 04:38:20.379788 [DutyScan_Calibration_Flow] ====Done====
7352 04:38:20.379868
7353 04:38:20.383146 [DutyScan_Calibration_Flow] k_type=2
7354 04:38:20.399122
7355 04:38:20.399229 ==DQ 0 ==
7356 04:38:20.402875 Final DQ duty delay cell = -4
7357 04:38:20.406027 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7358 04:38:20.409265 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7359 04:38:20.412716 [-4] AVG Duty = 4953%(X100)
7360 04:38:20.412797
7361 04:38:20.412860 ==DQ 1 ==
7362 04:38:20.416335 Final DQ duty delay cell = 0
7363 04:38:20.419323 [0] MAX Duty = 5156%(X100), DQS PI = 18
7364 04:38:20.422560 [0] MIN Duty = 4938%(X100), DQS PI = 8
7365 04:38:20.422642 [0] AVG Duty = 5047%(X100)
7366 04:38:20.425965
7367 04:38:20.429226 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7368 04:38:20.429307
7369 04:38:20.432816 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7370 04:38:20.435864 [DutyScan_Calibration_Flow] ====Done====
7371 04:38:20.439455 nWR fixed to 30
7372 04:38:20.439572 [ModeRegInit_LP4] CH0 RK0
7373 04:38:20.442862 [ModeRegInit_LP4] CH0 RK1
7374 04:38:20.446069 [ModeRegInit_LP4] CH1 RK0
7375 04:38:20.449240 [ModeRegInit_LP4] CH1 RK1
7376 04:38:20.449320 match AC timing 5
7377 04:38:20.455959 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 04:38:20.459527 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 04:38:20.462543 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 04:38:20.469414 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 04:38:20.472410 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 04:38:20.472491 [MiockJmeterHQA]
7383 04:38:20.472554
7384 04:38:20.475877 [DramcMiockJmeter] u1RxGatingPI = 0
7385 04:38:20.479428 0 : 4252, 4027
7386 04:38:20.479509 4 : 4253, 4026
7387 04:38:20.482535 8 : 4252, 4027
7388 04:38:20.482616 12 : 4363, 4137
7389 04:38:20.482680 16 : 4252, 4027
7390 04:38:20.485716 20 : 4253, 4027
7391 04:38:20.485798 24 : 4253, 4026
7392 04:38:20.488804 28 : 4252, 4027
7393 04:38:20.488886 32 : 4363, 4137
7394 04:38:20.492163 36 : 4252, 4027
7395 04:38:20.492245 40 : 4253, 4026
7396 04:38:20.495510 44 : 4252, 4027
7397 04:38:20.495627 48 : 4255, 4029
7398 04:38:20.495692 52 : 4254, 4029
7399 04:38:20.499150 56 : 4365, 4140
7400 04:38:20.499232 60 : 4361, 4138
7401 04:38:20.502293 64 : 4361, 4138
7402 04:38:20.502375 68 : 4252, 4029
7403 04:38:20.505959 72 : 4252, 4029
7404 04:38:20.506042 76 : 4252, 4029
7405 04:38:20.506107 80 : 4252, 4030
7406 04:38:20.509179 84 : 4361, 4138
7407 04:38:20.509260 88 : 4250, 229
7408 04:38:20.512510 92 : 4252, 0
7409 04:38:20.512591 96 : 4361, 0
7410 04:38:20.512655 100 : 4253, 0
7411 04:38:20.516119 104 : 4250, 0
7412 04:38:20.516201 108 : 4250, 0
7413 04:38:20.519048 112 : 4252, 0
7414 04:38:20.519130 116 : 4360, 0
7415 04:38:20.519209 120 : 4361, 0
7416 04:38:20.522482 124 : 4249, 0
7417 04:38:20.522564 128 : 4253, 0
7418 04:38:20.525441 132 : 4250, 0
7419 04:38:20.525526 136 : 4361, 0
7420 04:38:20.525590 140 : 4255, 0
7421 04:38:20.528842 144 : 4252, 0
7422 04:38:20.528923 148 : 4361, 0
7423 04:38:20.532156 152 : 4250, 0
7424 04:38:20.532238 156 : 4250, 0
7425 04:38:20.532303 160 : 4250, 0
7426 04:38:20.535896 164 : 4252, 0
7427 04:38:20.535978 168 : 4360, 0
7428 04:38:20.536043 172 : 4250, 0
7429 04:38:20.538981 176 : 4360, 0
7430 04:38:20.539077 180 : 4258, 0
7431 04:38:20.542122 184 : 4253, 0
7432 04:38:20.542205 188 : 4363, 0
7433 04:38:20.542270 192 : 4252, 0
7434 04:38:20.545558 196 : 4252, 0
7435 04:38:20.545641 200 : 4361, 0
7436 04:38:20.549003 204 : 4251, 1240
7437 04:38:20.549086 208 : 4250, 4022
7438 04:38:20.552186 212 : 4361, 4137
7439 04:38:20.552269 216 : 4361, 4137
7440 04:38:20.555511 220 : 4250, 4027
7441 04:38:20.555647 224 : 4250, 4027
7442 04:38:20.555725 228 : 4252, 4029
7443 04:38:20.558888 232 : 4250, 4027
7444 04:38:20.558971 236 : 4250, 4027
7445 04:38:20.562424 240 : 4361, 4138
7446 04:38:20.562507 244 : 4249, 4027
7447 04:38:20.565274 248 : 4250, 4026
7448 04:38:20.565357 252 : 4360, 4137
7449 04:38:20.568952 256 : 4250, 4027
7450 04:38:20.569035 260 : 4250, 4027
7451 04:38:20.572337 264 : 4361, 4138
7452 04:38:20.572419 268 : 4361, 4137
7453 04:38:20.575303 272 : 4250, 4027
7454 04:38:20.575386 276 : 4249, 4027
7455 04:38:20.578906 280 : 4252, 4029
7456 04:38:20.579035 284 : 4250, 4026
7457 04:38:20.579100 288 : 4250, 4026
7458 04:38:20.582392 292 : 4361, 4138
7459 04:38:20.582475 296 : 4250, 4026
7460 04:38:20.585457 300 : 4250, 4026
7461 04:38:20.585554 304 : 4363, 4139
7462 04:38:20.588826 308 : 4250, 3961
7463 04:38:20.588909 312 : 4250, 2128
7464 04:38:20.592168 316 : 4361, 1
7465 04:38:20.592251
7466 04:38:20.592315 MIOCK jitter meter ch=0
7467 04:38:20.592374
7468 04:38:20.595752 1T = (316-88) = 228 dly cells
7469 04:38:20.602489 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7470 04:38:20.602570 ==
7471 04:38:20.605699 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 04:38:20.609054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7473 04:38:20.609137 ==
7474 04:38:20.615540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7475 04:38:20.618920 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7476 04:38:20.621839 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7477 04:38:20.628939 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7478 04:38:20.638196 [CA 0] Center 43 (13~74) winsize 62
7479 04:38:20.641670 [CA 1] Center 43 (13~74) winsize 62
7480 04:38:20.645338 [CA 2] Center 38 (9~68) winsize 60
7481 04:38:20.648262 [CA 3] Center 38 (8~68) winsize 61
7482 04:38:20.651592 [CA 4] Center 37 (7~67) winsize 61
7483 04:38:20.654938 [CA 5] Center 35 (6~65) winsize 60
7484 04:38:20.655020
7485 04:38:20.658223 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7486 04:38:20.658304
7487 04:38:20.661529 [CATrainingPosCal] consider 1 rank data
7488 04:38:20.664782 u2DelayCellTimex100 = 285/100 ps
7489 04:38:20.668216 CA0 delay=43 (13~74),Diff = 8 PI (27 cell)
7490 04:38:20.674711 CA1 delay=43 (13~74),Diff = 8 PI (27 cell)
7491 04:38:20.678246 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7492 04:38:20.681751 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7493 04:38:20.684686 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7494 04:38:20.688245 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7495 04:38:20.688328
7496 04:38:20.691819 CA PerBit enable=1, Macro0, CA PI delay=35
7497 04:38:20.691901
7498 04:38:20.694688 [CBTSetCACLKResult] CA Dly = 35
7499 04:38:20.698133 CS Dly: 9 (0~40)
7500 04:38:20.701732 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7501 04:38:20.704802 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7502 04:38:20.704883 ==
7503 04:38:20.708074 Dram Type= 6, Freq= 0, CH_0, rank 1
7504 04:38:20.711304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 04:38:20.714754 ==
7506 04:38:20.718168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 04:38:20.721476 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 04:38:20.727984 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 04:38:20.731318 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 04:38:20.741488 [CA 0] Center 43 (13~73) winsize 61
7511 04:38:20.745360 [CA 1] Center 43 (13~73) winsize 61
7512 04:38:20.748358 [CA 2] Center 38 (8~68) winsize 61
7513 04:38:20.751963 [CA 3] Center 38 (8~68) winsize 61
7514 04:38:20.755168 [CA 4] Center 36 (6~66) winsize 61
7515 04:38:20.758523 [CA 5] Center 35 (6~65) winsize 60
7516 04:38:20.758604
7517 04:38:20.762026 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7518 04:38:20.762107
7519 04:38:20.765129 [CATrainingPosCal] consider 2 rank data
7520 04:38:20.768347 u2DelayCellTimex100 = 285/100 ps
7521 04:38:20.772136 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7522 04:38:20.778444 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7523 04:38:20.781885 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7524 04:38:20.785455 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7525 04:38:20.788321 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7526 04:38:20.792079 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7527 04:38:20.792160
7528 04:38:20.795609 CA PerBit enable=1, Macro0, CA PI delay=35
7529 04:38:20.795691
7530 04:38:20.798508 [CBTSetCACLKResult] CA Dly = 35
7531 04:38:20.798590 CS Dly: 10 (0~42)
7532 04:38:20.805356 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 04:38:20.808874 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 04:38:20.808955
7535 04:38:20.811753 ----->DramcWriteLeveling(PI) begin...
7536 04:38:20.811835 ==
7537 04:38:20.815359 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 04:38:20.818307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 04:38:20.822127 ==
7540 04:38:20.822209 Write leveling (Byte 0): 34 => 34
7541 04:38:20.825065 Write leveling (Byte 1): 28 => 28
7542 04:38:20.828547 DramcWriteLeveling(PI) end<-----
7543 04:38:20.828629
7544 04:38:20.828692 ==
7545 04:38:20.831617 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 04:38:20.838216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 04:38:20.838298 ==
7548 04:38:20.838363 [Gating] SW mode calibration
7549 04:38:20.848747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7550 04:38:20.851772 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7551 04:38:20.855234 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 04:38:20.861752 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 04:38:20.864915 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7554 04:38:20.868171 1 4 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7555 04:38:20.875178 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7556 04:38:20.878346 1 4 20 | B1->B0 | 3232 3535 | 0 0 | (0 0) (0 0)
7557 04:38:20.881652 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 04:38:20.888190 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 04:38:20.891620 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7560 04:38:20.894576 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 04:38:20.901613 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7562 04:38:20.905039 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7563 04:38:20.907993 1 5 16 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
7564 04:38:20.914460 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7565 04:38:20.917937 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7566 04:38:20.921512 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 04:38:20.927735 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7568 04:38:20.931279 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7569 04:38:20.934411 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7570 04:38:20.941555 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7571 04:38:20.945032 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7572 04:38:20.947879 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7573 04:38:20.954415 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 04:38:20.958125 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 04:38:20.961216 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 04:38:20.967670 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 04:38:20.971051 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 04:38:20.974329 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 04:38:20.981024 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 04:38:20.984598 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7581 04:38:20.987669 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 04:38:20.994081 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 04:38:20.997665 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 04:38:21.001224 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 04:38:21.007694 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 04:38:21.011162 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 04:38:21.014189 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 04:38:21.021245 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 04:38:21.024045 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 04:38:21.027612 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 04:38:21.031108 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 04:38:21.037509 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 04:38:21.040886 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 04:38:21.044182 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 04:38:21.050990 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 04:38:21.054536 Total UI for P1: 0, mck2ui 16
7597 04:38:21.057555 best dqsien dly found for B0: ( 1, 9, 10)
7598 04:38:21.060574 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 04:38:21.064061 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 04:38:21.067320 Total UI for P1: 0, mck2ui 16
7601 04:38:21.070483 best dqsien dly found for B1: ( 1, 9, 18)
7602 04:38:21.073860 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7603 04:38:21.077289 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7604 04:38:21.080577
7605 04:38:21.083778 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7606 04:38:21.087455 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7607 04:38:21.090474 [Gating] SW calibration Done
7608 04:38:21.090555 ==
7609 04:38:21.093871 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 04:38:21.097659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 04:38:21.097742 ==
7612 04:38:21.097807 RX Vref Scan: 0
7613 04:38:21.100455
7614 04:38:21.100570 RX Vref 0 -> 0, step: 1
7615 04:38:21.100664
7616 04:38:21.103830 RX Delay 0 -> 252, step: 8
7617 04:38:21.107194 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7618 04:38:21.110749 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7619 04:38:21.117432 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7620 04:38:21.120395 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7621 04:38:21.123616 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7622 04:38:21.127173 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7623 04:38:21.130584 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7624 04:38:21.136923 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7625 04:38:21.140306 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7626 04:38:21.143877 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7627 04:38:21.147011 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7628 04:38:21.150486 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7629 04:38:21.157000 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7630 04:38:21.159889 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7631 04:38:21.163287 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7632 04:38:21.167050 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7633 04:38:21.167132 ==
7634 04:38:21.170205 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 04:38:21.177058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 04:38:21.177140 ==
7637 04:38:21.177204 DQS Delay:
7638 04:38:21.177268 DQS0 = 0, DQS1 = 0
7639 04:38:21.180300 DQM Delay:
7640 04:38:21.180397 DQM0 = 137, DQM1 = 130
7641 04:38:21.183629 DQ Delay:
7642 04:38:21.186527 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7643 04:38:21.190131 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7644 04:38:21.193535 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7645 04:38:21.196913 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7646 04:38:21.197008
7647 04:38:21.197103
7648 04:38:21.197187 ==
7649 04:38:21.200116 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 04:38:21.203303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 04:38:21.206796 ==
7652 04:38:21.206892
7653 04:38:21.206978
7654 04:38:21.207072 TX Vref Scan disable
7655 04:38:21.209822 == TX Byte 0 ==
7656 04:38:21.213424 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7657 04:38:21.216609 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7658 04:38:21.220202 == TX Byte 1 ==
7659 04:38:21.223120 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7660 04:38:21.226604 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7661 04:38:21.226699 ==
7662 04:38:21.230176 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 04:38:21.236549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 04:38:21.236647 ==
7665 04:38:21.247566
7666 04:38:21.251091 TX Vref early break, caculate TX vref
7667 04:38:21.254424 TX Vref=16, minBit 0, minWin=23, winSum=380
7668 04:38:21.257577 TX Vref=18, minBit 0, minWin=24, winSum=391
7669 04:38:21.260976 TX Vref=20, minBit 0, minWin=24, winSum=402
7670 04:38:21.264389 TX Vref=22, minBit 0, minWin=25, winSum=407
7671 04:38:21.267852 TX Vref=24, minBit 1, minWin=25, winSum=417
7672 04:38:21.274516 TX Vref=26, minBit 1, minWin=25, winSum=428
7673 04:38:21.277913 TX Vref=28, minBit 6, minWin=25, winSum=428
7674 04:38:21.281118 TX Vref=30, minBit 6, minWin=24, winSum=411
7675 04:38:21.284773 TX Vref=32, minBit 1, minWin=23, winSum=404
7676 04:38:21.291135 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
7677 04:38:21.291237
7678 04:38:21.294481 Final TX Range 0 Vref 26
7679 04:38:21.294578
7680 04:38:21.294672 ==
7681 04:38:21.297416 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 04:38:21.300931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 04:38:21.301034 ==
7684 04:38:21.301123
7685 04:38:21.301207
7686 04:38:21.304488 TX Vref Scan disable
7687 04:38:21.307314 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7688 04:38:21.311390 == TX Byte 0 ==
7689 04:38:21.314044 u2DelayCellOfst[0]=10 cells (3 PI)
7690 04:38:21.317446 u2DelayCellOfst[1]=13 cells (4 PI)
7691 04:38:21.320892 u2DelayCellOfst[2]=10 cells (3 PI)
7692 04:38:21.323924 u2DelayCellOfst[3]=10 cells (3 PI)
7693 04:38:21.327235 u2DelayCellOfst[4]=6 cells (2 PI)
7694 04:38:21.327331 u2DelayCellOfst[5]=0 cells (0 PI)
7695 04:38:21.330602 u2DelayCellOfst[6]=17 cells (5 PI)
7696 04:38:21.334236 u2DelayCellOfst[7]=17 cells (5 PI)
7697 04:38:21.340736 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7698 04:38:21.343703 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7699 04:38:21.343784 == TX Byte 1 ==
7700 04:38:21.347109 u2DelayCellOfst[8]=0 cells (0 PI)
7701 04:38:21.350715 u2DelayCellOfst[9]=0 cells (0 PI)
7702 04:38:21.353672 u2DelayCellOfst[10]=6 cells (2 PI)
7703 04:38:21.357072 u2DelayCellOfst[11]=6 cells (2 PI)
7704 04:38:21.360569 u2DelayCellOfst[12]=10 cells (3 PI)
7705 04:38:21.364059 u2DelayCellOfst[13]=10 cells (3 PI)
7706 04:38:21.367279 u2DelayCellOfst[14]=17 cells (5 PI)
7707 04:38:21.370379 u2DelayCellOfst[15]=10 cells (3 PI)
7708 04:38:21.373839 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7709 04:38:21.377031 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7710 04:38:21.380230 DramC Write-DBI on
7711 04:38:21.380333 ==
7712 04:38:21.383768 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 04:38:21.387189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 04:38:21.387266 ==
7715 04:38:21.387332
7716 04:38:21.390101
7717 04:38:21.390182 TX Vref Scan disable
7718 04:38:21.393881 == TX Byte 0 ==
7719 04:38:21.397278 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7720 04:38:21.400550 == TX Byte 1 ==
7721 04:38:21.404079 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7722 04:38:21.404161 DramC Write-DBI off
7723 04:38:21.404225
7724 04:38:21.406971 [DATLAT]
7725 04:38:21.407052 Freq=1600, CH0 RK0
7726 04:38:21.407117
7727 04:38:21.410008 DATLAT Default: 0xf
7728 04:38:21.410089 0, 0xFFFF, sum = 0
7729 04:38:21.413726 1, 0xFFFF, sum = 0
7730 04:38:21.413809 2, 0xFFFF, sum = 0
7731 04:38:21.416556 3, 0xFFFF, sum = 0
7732 04:38:21.416639 4, 0xFFFF, sum = 0
7733 04:38:21.420068 5, 0xFFFF, sum = 0
7734 04:38:21.423718 6, 0xFFFF, sum = 0
7735 04:38:21.423800 7, 0xFFFF, sum = 0
7736 04:38:21.427075 8, 0xFFFF, sum = 0
7737 04:38:21.427157 9, 0xFFFF, sum = 0
7738 04:38:21.429933 10, 0xFFFF, sum = 0
7739 04:38:21.430015 11, 0xFFFF, sum = 0
7740 04:38:21.433469 12, 0xFFFF, sum = 0
7741 04:38:21.433552 13, 0xFFFF, sum = 0
7742 04:38:21.437019 14, 0x0, sum = 1
7743 04:38:21.437101 15, 0x0, sum = 2
7744 04:38:21.440374 16, 0x0, sum = 3
7745 04:38:21.440457 17, 0x0, sum = 4
7746 04:38:21.443307 best_step = 15
7747 04:38:21.443387
7748 04:38:21.443451 ==
7749 04:38:21.446845 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 04:38:21.450394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 04:38:21.450476 ==
7752 04:38:21.450540 RX Vref Scan: 1
7753 04:38:21.450599
7754 04:38:21.453819 Set Vref Range= 24 -> 127
7755 04:38:21.453901
7756 04:38:21.456898 RX Vref 24 -> 127, step: 1
7757 04:38:21.456979
7758 04:38:21.460242 RX Delay 27 -> 252, step: 4
7759 04:38:21.460323
7760 04:38:21.463814 Set Vref, RX VrefLevel [Byte0]: 24
7761 04:38:21.466772 [Byte1]: 24
7762 04:38:21.466854
7763 04:38:21.470471 Set Vref, RX VrefLevel [Byte0]: 25
7764 04:38:21.473237 [Byte1]: 25
7765 04:38:21.473318
7766 04:38:21.476975 Set Vref, RX VrefLevel [Byte0]: 26
7767 04:38:21.480103 [Byte1]: 26
7768 04:38:21.483317
7769 04:38:21.483398 Set Vref, RX VrefLevel [Byte0]: 27
7770 04:38:21.486730 [Byte1]: 27
7771 04:38:21.491231
7772 04:38:21.491312 Set Vref, RX VrefLevel [Byte0]: 28
7773 04:38:21.494156 [Byte1]: 28
7774 04:38:21.498848
7775 04:38:21.498929 Set Vref, RX VrefLevel [Byte0]: 29
7776 04:38:21.501685 [Byte1]: 29
7777 04:38:21.506094
7778 04:38:21.506175 Set Vref, RX VrefLevel [Byte0]: 30
7779 04:38:21.509510 [Byte1]: 30
7780 04:38:21.513743
7781 04:38:21.513823 Set Vref, RX VrefLevel [Byte0]: 31
7782 04:38:21.516907 [Byte1]: 31
7783 04:38:21.520915
7784 04:38:21.520996 Set Vref, RX VrefLevel [Byte0]: 32
7785 04:38:21.524287 [Byte1]: 32
7786 04:38:21.528893
7787 04:38:21.528974 Set Vref, RX VrefLevel [Byte0]: 33
7788 04:38:21.531795 [Byte1]: 33
7789 04:38:21.536100
7790 04:38:21.536180 Set Vref, RX VrefLevel [Byte0]: 34
7791 04:38:21.539346 [Byte1]: 34
7792 04:38:21.543512
7793 04:38:21.543629 Set Vref, RX VrefLevel [Byte0]: 35
7794 04:38:21.547281 [Byte1]: 35
7795 04:38:21.551237
7796 04:38:21.551318 Set Vref, RX VrefLevel [Byte0]: 36
7797 04:38:21.554735 [Byte1]: 36
7798 04:38:21.558651
7799 04:38:21.558746 Set Vref, RX VrefLevel [Byte0]: 37
7800 04:38:21.562217 [Byte1]: 37
7801 04:38:21.566349
7802 04:38:21.566462 Set Vref, RX VrefLevel [Byte0]: 38
7803 04:38:21.569921 [Byte1]: 38
7804 04:38:21.574044
7805 04:38:21.574124 Set Vref, RX VrefLevel [Byte0]: 39
7806 04:38:21.577478 [Byte1]: 39
7807 04:38:21.581553
7808 04:38:21.581634 Set Vref, RX VrefLevel [Byte0]: 40
7809 04:38:21.584982 [Byte1]: 40
7810 04:38:21.588931
7811 04:38:21.589012 Set Vref, RX VrefLevel [Byte0]: 41
7812 04:38:21.592331 [Byte1]: 41
7813 04:38:21.596675
7814 04:38:21.596755 Set Vref, RX VrefLevel [Byte0]: 42
7815 04:38:21.599737 [Byte1]: 42
7816 04:38:21.604100
7817 04:38:21.604182 Set Vref, RX VrefLevel [Byte0]: 43
7818 04:38:21.607821 [Byte1]: 43
7819 04:38:21.611649
7820 04:38:21.611730 Set Vref, RX VrefLevel [Byte0]: 44
7821 04:38:21.614998 [Byte1]: 44
7822 04:38:21.618954
7823 04:38:21.619034 Set Vref, RX VrefLevel [Byte0]: 45
7824 04:38:21.622551 [Byte1]: 45
7825 04:38:21.626561
7826 04:38:21.626642 Set Vref, RX VrefLevel [Byte0]: 46
7827 04:38:21.629789 [Byte1]: 46
7828 04:38:21.634063
7829 04:38:21.634166 Set Vref, RX VrefLevel [Byte0]: 47
7830 04:38:21.637708 [Byte1]: 47
7831 04:38:21.641632
7832 04:38:21.641711 Set Vref, RX VrefLevel [Byte0]: 48
7833 04:38:21.645373 [Byte1]: 48
7834 04:38:21.649114
7835 04:38:21.649195 Set Vref, RX VrefLevel [Byte0]: 49
7836 04:38:21.652402 [Byte1]: 49
7837 04:38:21.657086
7838 04:38:21.657167 Set Vref, RX VrefLevel [Byte0]: 50
7839 04:38:21.659881 [Byte1]: 50
7840 04:38:21.664656
7841 04:38:21.664737 Set Vref, RX VrefLevel [Byte0]: 51
7842 04:38:21.667473 [Byte1]: 51
7843 04:38:21.672217
7844 04:38:21.672298 Set Vref, RX VrefLevel [Byte0]: 52
7845 04:38:21.675017 [Byte1]: 52
7846 04:38:21.679130
7847 04:38:21.679252 Set Vref, RX VrefLevel [Byte0]: 53
7848 04:38:21.682557 [Byte1]: 53
7849 04:38:21.687251
7850 04:38:21.687337 Set Vref, RX VrefLevel [Byte0]: 54
7851 04:38:21.690072 [Byte1]: 54
7852 04:38:21.694168
7853 04:38:21.694266 Set Vref, RX VrefLevel [Byte0]: 55
7854 04:38:21.697772 [Byte1]: 55
7855 04:38:21.701790
7856 04:38:21.701888 Set Vref, RX VrefLevel [Byte0]: 56
7857 04:38:21.705469 [Byte1]: 56
7858 04:38:21.709547
7859 04:38:21.709648 Set Vref, RX VrefLevel [Byte0]: 57
7860 04:38:21.712791 [Byte1]: 57
7861 04:38:21.717401
7862 04:38:21.717522 Set Vref, RX VrefLevel [Byte0]: 58
7863 04:38:21.720908 [Byte1]: 58
7864 04:38:21.724647
7865 04:38:21.724781 Set Vref, RX VrefLevel [Byte0]: 59
7866 04:38:21.728029 [Byte1]: 59
7867 04:38:21.732097
7868 04:38:21.732269 Set Vref, RX VrefLevel [Byte0]: 60
7869 04:38:21.735444 [Byte1]: 60
7870 04:38:21.739915
7871 04:38:21.740116 Set Vref, RX VrefLevel [Byte0]: 61
7872 04:38:21.743173 [Byte1]: 61
7873 04:38:21.747352
7874 04:38:21.747684 Set Vref, RX VrefLevel [Byte0]: 62
7875 04:38:21.751053 [Byte1]: 62
7876 04:38:21.755040
7877 04:38:21.755484 Set Vref, RX VrefLevel [Byte0]: 63
7878 04:38:21.758626 [Byte1]: 63
7879 04:38:21.762827
7880 04:38:21.763240 Set Vref, RX VrefLevel [Byte0]: 64
7881 04:38:21.766020 [Byte1]: 64
7882 04:38:21.769950
7883 04:38:21.770366 Set Vref, RX VrefLevel [Byte0]: 65
7884 04:38:21.773273 [Byte1]: 65
7885 04:38:21.777995
7886 04:38:21.778412 Set Vref, RX VrefLevel [Byte0]: 66
7887 04:38:21.780844 [Byte1]: 66
7888 04:38:21.785278
7889 04:38:21.785696 Set Vref, RX VrefLevel [Byte0]: 67
7890 04:38:21.788614 [Byte1]: 67
7891 04:38:21.792943
7892 04:38:21.793361 Set Vref, RX VrefLevel [Byte0]: 68
7893 04:38:21.796309 [Byte1]: 68
7894 04:38:21.800355
7895 04:38:21.800772 Set Vref, RX VrefLevel [Byte0]: 69
7896 04:38:21.803303 [Byte1]: 69
7897 04:38:21.807612
7898 04:38:21.808037 Set Vref, RX VrefLevel [Byte0]: 70
7899 04:38:21.811148 [Byte1]: 70
7900 04:38:21.815068
7901 04:38:21.815483 Set Vref, RX VrefLevel [Byte0]: 71
7902 04:38:21.818737 [Byte1]: 71
7903 04:38:21.822786
7904 04:38:21.823202 Set Vref, RX VrefLevel [Byte0]: 72
7905 04:38:21.825921 [Byte1]: 72
7906 04:38:21.830659
7907 04:38:21.831085 Set Vref, RX VrefLevel [Byte0]: 73
7908 04:38:21.833569 [Byte1]: 73
7909 04:38:21.837797
7910 04:38:21.838214 Set Vref, RX VrefLevel [Byte0]: 74
7911 04:38:21.841297 [Byte1]: 74
7912 04:38:21.845268
7913 04:38:21.845684 Set Vref, RX VrefLevel [Byte0]: 75
7914 04:38:21.848840 [Byte1]: 75
7915 04:38:21.852945
7916 04:38:21.853359 Set Vref, RX VrefLevel [Byte0]: 76
7917 04:38:21.856148 [Byte1]: 76
7918 04:38:21.860257
7919 04:38:21.860673 Set Vref, RX VrefLevel [Byte0]: 77
7920 04:38:21.863800 [Byte1]: 77
7921 04:38:21.868029
7922 04:38:21.868443 Set Vref, RX VrefLevel [Byte0]: 78
7923 04:38:21.871147 [Byte1]: 78
7924 04:38:21.875309
7925 04:38:21.875760 Final RX Vref Byte 0 = 54 to rank0
7926 04:38:21.879070 Final RX Vref Byte 1 = 62 to rank0
7927 04:38:21.882329 Final RX Vref Byte 0 = 54 to rank1
7928 04:38:21.885258 Final RX Vref Byte 1 = 62 to rank1==
7929 04:38:21.888692 Dram Type= 6, Freq= 0, CH_0, rank 0
7930 04:38:21.895164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7931 04:38:21.895246 ==
7932 04:38:21.895310 DQS Delay:
7933 04:38:21.895370 DQS0 = 0, DQS1 = 0
7934 04:38:21.898447 DQM Delay:
7935 04:38:21.898529 DQM0 = 133, DQM1 = 127
7936 04:38:21.902007 DQ Delay:
7937 04:38:21.904998 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7938 04:38:21.908349 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7939 04:38:21.911732 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7940 04:38:21.914905 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7941 04:38:21.914986
7942 04:38:21.915050
7943 04:38:21.915109
7944 04:38:21.918293 [DramC_TX_OE_Calibration] TA2
7945 04:38:21.921682 Original DQ_B0 (3 6) =30, OEN = 27
7946 04:38:21.924897 Original DQ_B1 (3 6) =30, OEN = 27
7947 04:38:21.928349 24, 0x0, End_B0=24 End_B1=24
7948 04:38:21.928432 25, 0x0, End_B0=25 End_B1=25
7949 04:38:21.931464 26, 0x0, End_B0=26 End_B1=26
7950 04:38:21.934919 27, 0x0, End_B0=27 End_B1=27
7951 04:38:21.938456 28, 0x0, End_B0=28 End_B1=28
7952 04:38:21.941525 29, 0x0, End_B0=29 End_B1=29
7953 04:38:21.941608 30, 0x0, End_B0=30 End_B1=30
7954 04:38:21.944801 31, 0x4141, End_B0=30 End_B1=30
7955 04:38:21.948062 Byte0 end_step=30 best_step=27
7956 04:38:21.951631 Byte1 end_step=30 best_step=27
7957 04:38:21.954915 Byte0 TX OE(2T, 0.5T) = (3, 3)
7958 04:38:21.958300 Byte1 TX OE(2T, 0.5T) = (3, 3)
7959 04:38:21.958381
7960 04:38:21.958445
7961 04:38:21.964563 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7962 04:38:21.968047 CH0 RK0: MR19=303, MR18=2622
7963 04:38:21.974521 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7964 04:38:21.974603
7965 04:38:21.978055 ----->DramcWriteLeveling(PI) begin...
7966 04:38:21.978137 ==
7967 04:38:21.981886 Dram Type= 6, Freq= 0, CH_0, rank 1
7968 04:38:21.984553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 04:38:21.984658 ==
7970 04:38:21.987930 Write leveling (Byte 0): 35 => 35
7971 04:38:21.991698 Write leveling (Byte 1): 29 => 29
7972 04:38:21.994570 DramcWriteLeveling(PI) end<-----
7973 04:38:21.994652
7974 04:38:21.994716 ==
7975 04:38:21.998189 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 04:38:22.001431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 04:38:22.001537 ==
7978 04:38:22.004955 [Gating] SW mode calibration
7979 04:38:22.011447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7980 04:38:22.017682 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7981 04:38:22.021101 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 04:38:22.024508 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 04:38:22.031090 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 04:38:22.034671 1 4 12 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7985 04:38:22.037658 1 4 16 | B1->B0 | 3333 3736 | 0 1 | (0 0) (0 0)
7986 04:38:22.044229 1 4 20 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7987 04:38:22.047736 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7988 04:38:22.051257 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7989 04:38:22.057943 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7990 04:38:22.061420 1 5 4 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7991 04:38:22.064609 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7992 04:38:22.071007 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
7993 04:38:22.074510 1 5 16 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 0)
7994 04:38:22.077556 1 5 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7995 04:38:22.084460 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7996 04:38:22.087436 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 04:38:22.090849 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7998 04:38:22.097650 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7999 04:38:22.100947 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8000 04:38:22.104706 1 6 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
8001 04:38:22.110941 1 6 16 | B1->B0 | 3d3d 4645 | 0 1 | (0 0) (0 0)
8002 04:38:22.114432 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 04:38:22.118020 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 04:38:22.124075 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 04:38:22.127699 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 04:38:22.130874 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 04:38:22.137674 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 04:38:22.140986 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8009 04:38:22.143916 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8010 04:38:22.151004 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 04:38:22.153910 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 04:38:22.157313 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 04:38:22.160436 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 04:38:22.167327 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 04:38:22.170989 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 04:38:22.174090 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 04:38:22.180292 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 04:38:22.183871 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 04:38:22.187134 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 04:38:22.194125 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 04:38:22.197052 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 04:38:22.200820 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 04:38:22.207078 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 04:38:22.210906 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8025 04:38:22.214133 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8026 04:38:22.217403 Total UI for P1: 0, mck2ui 16
8027 04:38:22.220292 best dqsien dly found for B0: ( 1, 9, 12)
8028 04:38:22.226998 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 04:38:22.227079 Total UI for P1: 0, mck2ui 16
8030 04:38:22.233990 best dqsien dly found for B1: ( 1, 9, 14)
8031 04:38:22.237330 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8032 04:38:22.240673 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8033 04:38:22.240754
8034 04:38:22.244161 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8035 04:38:22.247194 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8036 04:38:22.250574 [Gating] SW calibration Done
8037 04:38:22.250655 ==
8038 04:38:22.254048 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 04:38:22.256997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 04:38:22.257079 ==
8041 04:38:22.260429 RX Vref Scan: 0
8042 04:38:22.260509
8043 04:38:22.260573 RX Vref 0 -> 0, step: 1
8044 04:38:22.260632
8045 04:38:22.263911 RX Delay 0 -> 252, step: 8
8046 04:38:22.267558 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8047 04:38:22.273696 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8048 04:38:22.277231 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8049 04:38:22.280637 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8050 04:38:22.284142 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8051 04:38:22.287005 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8052 04:38:22.293635 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8053 04:38:22.297142 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
8054 04:38:22.300171 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8055 04:38:22.303424 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8056 04:38:22.307287 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8057 04:38:22.313634 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8058 04:38:22.316900 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8059 04:38:22.320146 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8060 04:38:22.323477 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8061 04:38:22.326835 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8062 04:38:22.330189 ==
8063 04:38:22.333695 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 04:38:22.336671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 04:38:22.336753 ==
8066 04:38:22.336817 DQS Delay:
8067 04:38:22.340106 DQS0 = 0, DQS1 = 0
8068 04:38:22.340197 DQM Delay:
8069 04:38:22.344069 DQM0 = 137, DQM1 = 128
8070 04:38:22.344166 DQ Delay:
8071 04:38:22.346641 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8072 04:38:22.350320 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =147
8073 04:38:22.353826 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8074 04:38:22.356757 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8075 04:38:22.356839
8076 04:38:22.356902
8077 04:38:22.356962 ==
8078 04:38:22.360144 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 04:38:22.366691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 04:38:22.366788 ==
8081 04:38:22.366855
8082 04:38:22.366914
8083 04:38:22.366971 TX Vref Scan disable
8084 04:38:22.370181 == TX Byte 0 ==
8085 04:38:22.373650 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8086 04:38:22.376962 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8087 04:38:22.380499 == TX Byte 1 ==
8088 04:38:22.383937 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8089 04:38:22.386928 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8090 04:38:22.390401 ==
8091 04:38:22.393851 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 04:38:22.396865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 04:38:22.396948 ==
8094 04:38:22.410083
8095 04:38:22.412962 TX Vref early break, caculate TX vref
8096 04:38:22.416391 TX Vref=16, minBit 1, minWin=22, winSum=390
8097 04:38:22.419722 TX Vref=18, minBit 1, minWin=23, winSum=395
8098 04:38:22.423488 TX Vref=20, minBit 1, minWin=24, winSum=406
8099 04:38:22.426623 TX Vref=22, minBit 0, minWin=24, winSum=408
8100 04:38:22.430127 TX Vref=24, minBit 0, minWin=26, winSum=425
8101 04:38:22.436364 TX Vref=26, minBit 7, minWin=25, winSum=428
8102 04:38:22.439584 TX Vref=28, minBit 0, minWin=25, winSum=427
8103 04:38:22.443142 TX Vref=30, minBit 0, minWin=25, winSum=416
8104 04:38:22.446508 TX Vref=32, minBit 0, minWin=24, winSum=407
8105 04:38:22.449756 TX Vref=34, minBit 1, minWin=24, winSum=399
8106 04:38:22.456227 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 24
8107 04:38:22.456311
8108 04:38:22.459756 Final TX Range 0 Vref 24
8109 04:38:22.459838
8110 04:38:22.459901 ==
8111 04:38:22.463197 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 04:38:22.466174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 04:38:22.466256 ==
8114 04:38:22.466321
8115 04:38:22.466379
8116 04:38:22.469592 TX Vref Scan disable
8117 04:38:22.476256 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8118 04:38:22.476338 == TX Byte 0 ==
8119 04:38:22.479715 u2DelayCellOfst[0]=10 cells (3 PI)
8120 04:38:22.482640 u2DelayCellOfst[1]=13 cells (4 PI)
8121 04:38:22.486088 u2DelayCellOfst[2]=10 cells (3 PI)
8122 04:38:22.489669 u2DelayCellOfst[3]=10 cells (3 PI)
8123 04:38:22.492520 u2DelayCellOfst[4]=6 cells (2 PI)
8124 04:38:22.496116 u2DelayCellOfst[5]=0 cells (0 PI)
8125 04:38:22.499474 u2DelayCellOfst[6]=13 cells (4 PI)
8126 04:38:22.502928 u2DelayCellOfst[7]=13 cells (4 PI)
8127 04:38:22.505984 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8128 04:38:22.509252 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8129 04:38:22.512208 == TX Byte 1 ==
8130 04:38:22.515575 u2DelayCellOfst[8]=3 cells (1 PI)
8131 04:38:22.515656 u2DelayCellOfst[9]=0 cells (0 PI)
8132 04:38:22.519206 u2DelayCellOfst[10]=6 cells (2 PI)
8133 04:38:22.522681 u2DelayCellOfst[11]=3 cells (1 PI)
8134 04:38:22.525493 u2DelayCellOfst[12]=10 cells (3 PI)
8135 04:38:22.529266 u2DelayCellOfst[13]=13 cells (4 PI)
8136 04:38:22.532641 u2DelayCellOfst[14]=13 cells (4 PI)
8137 04:38:22.535573 u2DelayCellOfst[15]=10 cells (3 PI)
8138 04:38:22.539109 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8139 04:38:22.546108 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8140 04:38:22.546190 DramC Write-DBI on
8141 04:38:22.546255 ==
8142 04:38:22.548945 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 04:38:22.556166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 04:38:22.556248 ==
8145 04:38:22.556312
8146 04:38:22.556371
8147 04:38:22.556428 TX Vref Scan disable
8148 04:38:22.559496 == TX Byte 0 ==
8149 04:38:22.562955 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8150 04:38:22.566038 == TX Byte 1 ==
8151 04:38:22.569221 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8152 04:38:22.572740 DramC Write-DBI off
8153 04:38:22.572821
8154 04:38:22.572884 [DATLAT]
8155 04:38:22.572943 Freq=1600, CH0 RK1
8156 04:38:22.573001
8157 04:38:22.576438 DATLAT Default: 0xf
8158 04:38:22.576520 0, 0xFFFF, sum = 0
8159 04:38:22.579286 1, 0xFFFF, sum = 0
8160 04:38:22.579367 2, 0xFFFF, sum = 0
8161 04:38:22.582707 3, 0xFFFF, sum = 0
8162 04:38:22.585870 4, 0xFFFF, sum = 0
8163 04:38:22.585952 5, 0xFFFF, sum = 0
8164 04:38:22.589298 6, 0xFFFF, sum = 0
8165 04:38:22.589381 7, 0xFFFF, sum = 0
8166 04:38:22.592470 8, 0xFFFF, sum = 0
8167 04:38:22.592553 9, 0xFFFF, sum = 0
8168 04:38:22.595835 10, 0xFFFF, sum = 0
8169 04:38:22.595921 11, 0xFFFF, sum = 0
8170 04:38:22.599703 12, 0xFFFF, sum = 0
8171 04:38:22.599786 13, 0xFFFF, sum = 0
8172 04:38:22.602830 14, 0x0, sum = 1
8173 04:38:22.602912 15, 0x0, sum = 2
8174 04:38:22.605766 16, 0x0, sum = 3
8175 04:38:22.605848 17, 0x0, sum = 4
8176 04:38:22.609118 best_step = 15
8177 04:38:22.609198
8178 04:38:22.609263 ==
8179 04:38:22.612658 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 04:38:22.616127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 04:38:22.616209 ==
8182 04:38:22.616273 RX Vref Scan: 0
8183 04:38:22.619036
8184 04:38:22.619117 RX Vref 0 -> 0, step: 1
8185 04:38:22.619181
8186 04:38:22.622371 RX Delay 19 -> 252, step: 4
8187 04:38:22.625833 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8188 04:38:22.632542 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8189 04:38:22.635792 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8190 04:38:22.639169 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8191 04:38:22.642234 iDelay=191, Bit 4, Center 136 (83 ~ 190) 108
8192 04:38:22.645645 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8193 04:38:22.652720 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8194 04:38:22.656330 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8195 04:38:22.659141 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8196 04:38:22.662500 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8197 04:38:22.665715 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8198 04:38:22.672413 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8199 04:38:22.675608 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8200 04:38:22.679463 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8201 04:38:22.682192 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8202 04:38:22.685600 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8203 04:38:22.689614 ==
8204 04:38:22.689695 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 04:38:22.695862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 04:38:22.695945 ==
8207 04:38:22.696010 DQS Delay:
8208 04:38:22.698858 DQS0 = 0, DQS1 = 0
8209 04:38:22.698970 DQM Delay:
8210 04:38:22.702436 DQM0 = 134, DQM1 = 127
8211 04:38:22.702517 DQ Delay:
8212 04:38:22.705755 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8213 04:38:22.708861 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8214 04:38:22.712750 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8215 04:38:22.715672 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8216 04:38:22.715754
8217 04:38:22.715817
8218 04:38:22.715876
8219 04:38:22.719119 [DramC_TX_OE_Calibration] TA2
8220 04:38:22.722516 Original DQ_B0 (3 6) =30, OEN = 27
8221 04:38:22.725301 Original DQ_B1 (3 6) =30, OEN = 27
8222 04:38:22.728822 24, 0x0, End_B0=24 End_B1=24
8223 04:38:22.732340 25, 0x0, End_B0=25 End_B1=25
8224 04:38:22.732422 26, 0x0, End_B0=26 End_B1=26
8225 04:38:22.735391 27, 0x0, End_B0=27 End_B1=27
8226 04:38:22.738645 28, 0x0, End_B0=28 End_B1=28
8227 04:38:22.742055 29, 0x0, End_B0=29 End_B1=29
8228 04:38:22.742167 30, 0x0, End_B0=30 End_B1=30
8229 04:38:22.745409 31, 0x4141, End_B0=30 End_B1=30
8230 04:38:22.749106 Byte0 end_step=30 best_step=27
8231 04:38:22.752365 Byte1 end_step=30 best_step=27
8232 04:38:22.755733 Byte0 TX OE(2T, 0.5T) = (3, 3)
8233 04:38:22.758736 Byte1 TX OE(2T, 0.5T) = (3, 3)
8234 04:38:22.758836
8235 04:38:22.758930
8236 04:38:22.765857 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8237 04:38:22.768721 CH0 RK1: MR19=303, MR18=2008
8238 04:38:22.775660 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8239 04:38:22.779085 [RxdqsGatingPostProcess] freq 1600
8240 04:38:22.781746 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8241 04:38:22.785497 best DQS0 dly(2T, 0.5T) = (1, 1)
8242 04:38:22.788809 best DQS1 dly(2T, 0.5T) = (1, 1)
8243 04:38:22.792188 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8244 04:38:22.795134 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8245 04:38:22.798667 best DQS0 dly(2T, 0.5T) = (1, 1)
8246 04:38:22.801987 best DQS1 dly(2T, 0.5T) = (1, 1)
8247 04:38:22.805612 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8248 04:38:22.808840 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8249 04:38:22.811779 Pre-setting of DQS Precalculation
8250 04:38:22.815507 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8251 04:38:22.815621 ==
8252 04:38:22.818533 Dram Type= 6, Freq= 0, CH_1, rank 0
8253 04:38:22.825222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 04:38:22.825298 ==
8255 04:38:22.829157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8256 04:38:22.831676 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8257 04:38:22.838259 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8258 04:38:22.844952 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8259 04:38:22.852249 [CA 0] Center 42 (13~72) winsize 60
8260 04:38:22.855660 [CA 1] Center 42 (12~72) winsize 61
8261 04:38:22.859130 [CA 2] Center 38 (9~68) winsize 60
8262 04:38:22.862137 [CA 3] Center 38 (9~67) winsize 59
8263 04:38:22.865563 [CA 4] Center 38 (9~68) winsize 60
8264 04:38:22.869241 [CA 5] Center 37 (8~67) winsize 60
8265 04:38:22.869312
8266 04:38:22.872156 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8267 04:38:22.872226
8268 04:38:22.875496 [CATrainingPosCal] consider 1 rank data
8269 04:38:22.878859 u2DelayCellTimex100 = 285/100 ps
8270 04:38:22.882001 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8271 04:38:22.888898 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8272 04:38:22.892165 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8273 04:38:22.895691 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8274 04:38:22.898752 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8275 04:38:22.902030 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8276 04:38:22.902099
8277 04:38:22.905454 CA PerBit enable=1, Macro0, CA PI delay=37
8278 04:38:22.905525
8279 04:38:22.908979 [CBTSetCACLKResult] CA Dly = 37
8280 04:38:22.912593 CS Dly: 10 (0~41)
8281 04:38:22.915342 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8282 04:38:22.918810 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8283 04:38:22.918906 ==
8284 04:38:22.922253 Dram Type= 6, Freq= 0, CH_1, rank 1
8285 04:38:22.925639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 04:38:22.928617 ==
8287 04:38:22.932002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 04:38:22.935095 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 04:38:22.942126 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 04:38:22.945091 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 04:38:22.955707 [CA 0] Center 42 (12~72) winsize 61
8292 04:38:22.958780 [CA 1] Center 42 (12~72) winsize 61
8293 04:38:22.962725 [CA 2] Center 38 (9~68) winsize 60
8294 04:38:22.965627 [CA 3] Center 38 (8~68) winsize 61
8295 04:38:22.969183 [CA 4] Center 38 (8~68) winsize 61
8296 04:38:22.972316 [CA 5] Center 37 (7~67) winsize 61
8297 04:38:22.972401
8298 04:38:22.975782 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8299 04:38:22.975855
8300 04:38:22.978742 [CATrainingPosCal] consider 2 rank data
8301 04:38:22.981967 u2DelayCellTimex100 = 285/100 ps
8302 04:38:22.985361 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8303 04:38:22.992162 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8304 04:38:22.995552 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8305 04:38:22.999021 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8306 04:38:23.002530 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8307 04:38:23.005369 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8308 04:38:23.005456
8309 04:38:23.008872 CA PerBit enable=1, Macro0, CA PI delay=37
8310 04:38:23.008945
8311 04:38:23.012504 [CBTSetCACLKResult] CA Dly = 37
8312 04:38:23.015339 CS Dly: 11 (0~44)
8313 04:38:23.018695 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 04:38:23.022200 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 04:38:23.022300
8316 04:38:23.025569 ----->DramcWriteLeveling(PI) begin...
8317 04:38:23.025666 ==
8318 04:38:23.028881 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 04:38:23.032194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 04:38:23.032278 ==
8321 04:38:23.035659 Write leveling (Byte 0): 26 => 26
8322 04:38:23.039261 Write leveling (Byte 1): 28 => 28
8323 04:38:23.042126 DramcWriteLeveling(PI) end<-----
8324 04:38:23.042224
8325 04:38:23.042315 ==
8326 04:38:23.045368 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 04:38:23.052376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 04:38:23.052450 ==
8329 04:38:23.052510 [Gating] SW mode calibration
8330 04:38:23.062241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8331 04:38:23.065716 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8332 04:38:23.068888 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 04:38:23.075299 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 04:38:23.078839 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8335 04:38:23.082389 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8336 04:38:23.088703 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 04:38:23.091844 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 04:38:23.095486 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 04:38:23.101938 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 04:38:23.105674 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 04:38:23.109010 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 04:38:23.115449 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8343 04:38:23.118929 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8344 04:38:23.122306 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 04:38:23.128629 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 04:38:23.132124 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 04:38:23.135618 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 04:38:23.141782 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 04:38:23.145193 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 04:38:23.148501 1 6 8 | B1->B0 | 2424 3b3b | 0 1 | (0 0) (0 0)
8351 04:38:23.155012 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 04:38:23.158437 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 04:38:23.161785 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 04:38:23.168538 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 04:38:23.171943 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 04:38:23.175001 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 04:38:23.181686 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 04:38:23.184788 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8359 04:38:23.188285 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8360 04:38:23.195326 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 04:38:23.198632 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 04:38:23.201918 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 04:38:23.205011 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 04:38:23.212066 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 04:38:23.215196 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 04:38:23.218702 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 04:38:23.224979 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 04:38:23.228886 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 04:38:23.231585 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 04:38:23.238327 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 04:38:23.241758 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 04:38:23.245251 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 04:38:23.251785 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 04:38:23.254944 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8375 04:38:23.258494 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8376 04:38:23.261643 Total UI for P1: 0, mck2ui 16
8377 04:38:23.264965 best dqsien dly found for B0: ( 1, 9, 8)
8378 04:38:23.272051 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 04:38:23.272151 Total UI for P1: 0, mck2ui 16
8380 04:38:23.274921 best dqsien dly found for B1: ( 1, 9, 10)
8381 04:38:23.278386 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8382 04:38:23.285013 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8383 04:38:23.285112
8384 04:38:23.288429 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8385 04:38:23.291678 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8386 04:38:23.295093 [Gating] SW calibration Done
8387 04:38:23.295190 ==
8388 04:38:23.298516 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 04:38:23.301949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 04:38:23.302032 ==
8391 04:38:23.305206 RX Vref Scan: 0
8392 04:38:23.305309
8393 04:38:23.305397 RX Vref 0 -> 0, step: 1
8394 04:38:23.305490
8395 04:38:23.308425 RX Delay 0 -> 252, step: 8
8396 04:38:23.311683 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8397 04:38:23.315008 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8398 04:38:23.321665 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8399 04:38:23.324984 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8400 04:38:23.328257 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8401 04:38:23.331428 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8402 04:38:23.335345 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8403 04:38:23.341634 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8404 04:38:23.344817 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8405 04:38:23.348342 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8406 04:38:23.351814 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8407 04:38:23.354881 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8408 04:38:23.361642 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8409 04:38:23.364946 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8410 04:38:23.368496 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8411 04:38:23.371701 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8412 04:38:23.371776 ==
8413 04:38:23.375281 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 04:38:23.378069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 04:38:23.381645 ==
8416 04:38:23.381726 DQS Delay:
8417 04:38:23.381790 DQS0 = 0, DQS1 = 0
8418 04:38:23.385400 DQM Delay:
8419 04:38:23.385481 DQM0 = 137, DQM1 = 133
8420 04:38:23.388129 DQ Delay:
8421 04:38:23.391683 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8422 04:38:23.395021 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8423 04:38:23.398356 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8424 04:38:23.401680 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8425 04:38:23.401762
8426 04:38:23.401826
8427 04:38:23.401885 ==
8428 04:38:23.405188 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 04:38:23.408791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 04:38:23.408875 ==
8431 04:38:23.408942
8432 04:38:23.409002
8433 04:38:23.411685 TX Vref Scan disable
8434 04:38:23.415167 == TX Byte 0 ==
8435 04:38:23.418293 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8436 04:38:23.421783 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8437 04:38:23.425122 == TX Byte 1 ==
8438 04:38:23.428403 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8439 04:38:23.431506 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8440 04:38:23.431628 ==
8441 04:38:23.434728 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 04:38:23.441284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 04:38:23.441362 ==
8444 04:38:23.454030
8445 04:38:23.457630 TX Vref early break, caculate TX vref
8446 04:38:23.460582 TX Vref=16, minBit 0, minWin=22, winSum=374
8447 04:38:23.463654 TX Vref=18, minBit 1, minWin=23, winSum=381
8448 04:38:23.467239 TX Vref=20, minBit 0, minWin=24, winSum=397
8449 04:38:23.470424 TX Vref=22, minBit 3, minWin=24, winSum=405
8450 04:38:23.473721 TX Vref=24, minBit 0, minWin=25, winSum=414
8451 04:38:23.480446 TX Vref=26, minBit 0, minWin=26, winSum=426
8452 04:38:23.483508 TX Vref=28, minBit 0, minWin=25, winSum=426
8453 04:38:23.487036 TX Vref=30, minBit 0, minWin=25, winSum=422
8454 04:38:23.490630 TX Vref=32, minBit 6, minWin=24, winSum=415
8455 04:38:23.494157 TX Vref=34, minBit 0, minWin=24, winSum=404
8456 04:38:23.497538 TX Vref=36, minBit 0, minWin=23, winSum=392
8457 04:38:23.503711 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8458 04:38:23.503814
8459 04:38:23.507269 Final TX Range 0 Vref 26
8460 04:38:23.507350
8461 04:38:23.507451 ==
8462 04:38:23.510744 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 04:38:23.513747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 04:38:23.513855 ==
8465 04:38:23.513947
8466 04:38:23.514039
8467 04:38:23.517072 TX Vref Scan disable
8468 04:38:23.524095 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8469 04:38:23.524177 == TX Byte 0 ==
8470 04:38:23.526919 u2DelayCellOfst[0]=17 cells (5 PI)
8471 04:38:23.530482 u2DelayCellOfst[1]=10 cells (3 PI)
8472 04:38:23.533822 u2DelayCellOfst[2]=0 cells (0 PI)
8473 04:38:23.537241 u2DelayCellOfst[3]=6 cells (2 PI)
8474 04:38:23.540945 u2DelayCellOfst[4]=6 cells (2 PI)
8475 04:38:23.543937 u2DelayCellOfst[5]=17 cells (5 PI)
8476 04:38:23.547117 u2DelayCellOfst[6]=17 cells (5 PI)
8477 04:38:23.550410 u2DelayCellOfst[7]=3 cells (1 PI)
8478 04:38:23.553501 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8479 04:38:23.556956 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8480 04:38:23.560735 == TX Byte 1 ==
8481 04:38:23.560816 u2DelayCellOfst[8]=0 cells (0 PI)
8482 04:38:23.564063 u2DelayCellOfst[9]=3 cells (1 PI)
8483 04:38:23.567497 u2DelayCellOfst[10]=13 cells (4 PI)
8484 04:38:23.570430 u2DelayCellOfst[11]=3 cells (1 PI)
8485 04:38:23.573757 u2DelayCellOfst[12]=17 cells (5 PI)
8486 04:38:23.577005 u2DelayCellOfst[13]=17 cells (5 PI)
8487 04:38:23.580717 u2DelayCellOfst[14]=17 cells (5 PI)
8488 04:38:23.584108 u2DelayCellOfst[15]=17 cells (5 PI)
8489 04:38:23.586849 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8490 04:38:23.593921 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8491 04:38:23.594004 DramC Write-DBI on
8492 04:38:23.594069 ==
8493 04:38:23.597342 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 04:38:23.600248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 04:38:23.603591 ==
8496 04:38:23.603673
8497 04:38:23.603737
8498 04:38:23.603797 TX Vref Scan disable
8499 04:38:23.606950 == TX Byte 0 ==
8500 04:38:23.610315 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8501 04:38:23.613793 == TX Byte 1 ==
8502 04:38:23.616855 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8503 04:38:23.620319 DramC Write-DBI off
8504 04:38:23.620399
8505 04:38:23.620463 [DATLAT]
8506 04:38:23.620522 Freq=1600, CH1 RK0
8507 04:38:23.620580
8508 04:38:23.623698 DATLAT Default: 0xf
8509 04:38:23.623780 0, 0xFFFF, sum = 0
8510 04:38:23.626651 1, 0xFFFF, sum = 0
8511 04:38:23.630168 2, 0xFFFF, sum = 0
8512 04:38:23.630278 3, 0xFFFF, sum = 0
8513 04:38:23.633723 4, 0xFFFF, sum = 0
8514 04:38:23.633798 5, 0xFFFF, sum = 0
8515 04:38:23.636671 6, 0xFFFF, sum = 0
8516 04:38:23.636743 7, 0xFFFF, sum = 0
8517 04:38:23.640011 8, 0xFFFF, sum = 0
8518 04:38:23.640085 9, 0xFFFF, sum = 0
8519 04:38:23.643714 10, 0xFFFF, sum = 0
8520 04:38:23.643786 11, 0xFFFF, sum = 0
8521 04:38:23.646976 12, 0xFFFF, sum = 0
8522 04:38:23.647047 13, 0xFFFF, sum = 0
8523 04:38:23.650583 14, 0x0, sum = 1
8524 04:38:23.650654 15, 0x0, sum = 2
8525 04:38:23.653146 16, 0x0, sum = 3
8526 04:38:23.653244 17, 0x0, sum = 4
8527 04:38:23.657067 best_step = 15
8528 04:38:23.657163
8529 04:38:23.657240 ==
8530 04:38:23.660199 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 04:38:23.663350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 04:38:23.663448 ==
8533 04:38:23.666648 RX Vref Scan: 1
8534 04:38:23.666744
8535 04:38:23.666832 Set Vref Range= 24 -> 127
8536 04:38:23.666918
8537 04:38:23.669847 RX Vref 24 -> 127, step: 1
8538 04:38:23.669915
8539 04:38:23.673220 RX Delay 27 -> 252, step: 4
8540 04:38:23.673290
8541 04:38:23.676780 Set Vref, RX VrefLevel [Byte0]: 24
8542 04:38:23.680124 [Byte1]: 24
8543 04:38:23.680221
8544 04:38:23.683549 Set Vref, RX VrefLevel [Byte0]: 25
8545 04:38:23.687068 [Byte1]: 25
8546 04:38:23.687148
8547 04:38:23.690029 Set Vref, RX VrefLevel [Byte0]: 26
8548 04:38:23.693007 [Byte1]: 26
8549 04:38:23.696853
8550 04:38:23.696934 Set Vref, RX VrefLevel [Byte0]: 27
8551 04:38:23.700427 [Byte1]: 27
8552 04:38:23.704786
8553 04:38:23.704867 Set Vref, RX VrefLevel [Byte0]: 28
8554 04:38:23.708014 [Byte1]: 28
8555 04:38:23.712394
8556 04:38:23.712476 Set Vref, RX VrefLevel [Byte0]: 29
8557 04:38:23.715274 [Byte1]: 29
8558 04:38:23.720030
8559 04:38:23.720111 Set Vref, RX VrefLevel [Byte0]: 30
8560 04:38:23.722972 [Byte1]: 30
8561 04:38:23.727006
8562 04:38:23.727086 Set Vref, RX VrefLevel [Byte0]: 31
8563 04:38:23.730381 [Byte1]: 31
8564 04:38:23.735097
8565 04:38:23.735178 Set Vref, RX VrefLevel [Byte0]: 32
8566 04:38:23.737982 [Byte1]: 32
8567 04:38:23.742548
8568 04:38:23.742629 Set Vref, RX VrefLevel [Byte0]: 33
8569 04:38:23.745346 [Byte1]: 33
8570 04:38:23.750048
8571 04:38:23.750129 Set Vref, RX VrefLevel [Byte0]: 34
8572 04:38:23.753515 [Byte1]: 34
8573 04:38:23.757541
8574 04:38:23.757621 Set Vref, RX VrefLevel [Byte0]: 35
8575 04:38:23.760884 [Byte1]: 35
8576 04:38:23.764687
8577 04:38:23.764768 Set Vref, RX VrefLevel [Byte0]: 36
8578 04:38:23.768156 [Byte1]: 36
8579 04:38:23.772392
8580 04:38:23.772472 Set Vref, RX VrefLevel [Byte0]: 37
8581 04:38:23.775899 [Byte1]: 37
8582 04:38:23.780198
8583 04:38:23.780278 Set Vref, RX VrefLevel [Byte0]: 38
8584 04:38:23.783667 [Byte1]: 38
8585 04:38:23.787744
8586 04:38:23.787884 Set Vref, RX VrefLevel [Byte0]: 39
8587 04:38:23.794098 [Byte1]: 39
8588 04:38:23.794193
8589 04:38:23.797057 Set Vref, RX VrefLevel [Byte0]: 40
8590 04:38:23.800672 [Byte1]: 40
8591 04:38:23.800754
8592 04:38:23.804151 Set Vref, RX VrefLevel [Byte0]: 41
8593 04:38:23.807185 [Byte1]: 41
8594 04:38:23.807292
8595 04:38:23.810601 Set Vref, RX VrefLevel [Byte0]: 42
8596 04:38:23.813945 [Byte1]: 42
8597 04:38:23.817447
8598 04:38:23.817548 Set Vref, RX VrefLevel [Byte0]: 43
8599 04:38:23.820889 [Byte1]: 43
8600 04:38:23.824958
8601 04:38:23.825035 Set Vref, RX VrefLevel [Byte0]: 44
8602 04:38:23.828463 [Byte1]: 44
8603 04:38:23.833097
8604 04:38:23.833177 Set Vref, RX VrefLevel [Byte0]: 45
8605 04:38:23.835919 [Byte1]: 45
8606 04:38:23.840168
8607 04:38:23.840249 Set Vref, RX VrefLevel [Byte0]: 46
8608 04:38:23.843495 [Byte1]: 46
8609 04:38:23.847558
8610 04:38:23.847652 Set Vref, RX VrefLevel [Byte0]: 47
8611 04:38:23.851027 [Byte1]: 47
8612 04:38:23.855156
8613 04:38:23.855237 Set Vref, RX VrefLevel [Byte0]: 48
8614 04:38:23.858603 [Byte1]: 48
8615 04:38:23.862666
8616 04:38:23.862747 Set Vref, RX VrefLevel [Byte0]: 49
8617 04:38:23.866240 [Byte1]: 49
8618 04:38:23.870260
8619 04:38:23.870341 Set Vref, RX VrefLevel [Byte0]: 50
8620 04:38:23.873625 [Byte1]: 50
8621 04:38:23.877725
8622 04:38:23.877806 Set Vref, RX VrefLevel [Byte0]: 51
8623 04:38:23.881241 [Byte1]: 51
8624 04:38:23.885446
8625 04:38:23.885527 Set Vref, RX VrefLevel [Byte0]: 52
8626 04:38:23.888826 [Byte1]: 52
8627 04:38:23.893089
8628 04:38:23.893170 Set Vref, RX VrefLevel [Byte0]: 53
8629 04:38:23.896007 [Byte1]: 53
8630 04:38:23.900553
8631 04:38:23.900634 Set Vref, RX VrefLevel [Byte0]: 54
8632 04:38:23.903966 [Byte1]: 54
8633 04:38:23.908074
8634 04:38:23.908155 Set Vref, RX VrefLevel [Byte0]: 55
8635 04:38:23.911462 [Byte1]: 55
8636 04:38:23.915413
8637 04:38:23.915494 Set Vref, RX VrefLevel [Byte0]: 56
8638 04:38:23.918940 [Byte1]: 56
8639 04:38:23.923102
8640 04:38:23.923184 Set Vref, RX VrefLevel [Byte0]: 57
8641 04:38:23.926248 [Byte1]: 57
8642 04:38:23.930456
8643 04:38:23.930540 Set Vref, RX VrefLevel [Byte0]: 58
8644 04:38:23.934008 [Byte1]: 58
8645 04:38:23.938394
8646 04:38:23.938475 Set Vref, RX VrefLevel [Byte0]: 59
8647 04:38:23.941286 [Byte1]: 59
8648 04:38:23.945671
8649 04:38:23.945752 Set Vref, RX VrefLevel [Byte0]: 60
8650 04:38:23.949030 [Byte1]: 60
8651 04:38:23.953125
8652 04:38:23.953206 Set Vref, RX VrefLevel [Byte0]: 61
8653 04:38:23.956655 [Byte1]: 61
8654 04:38:23.961184
8655 04:38:23.961264 Set Vref, RX VrefLevel [Byte0]: 62
8656 04:38:23.963950 [Byte1]: 62
8657 04:38:23.968654
8658 04:38:23.968735 Set Vref, RX VrefLevel [Byte0]: 63
8659 04:38:23.971435 [Byte1]: 63
8660 04:38:23.976063
8661 04:38:23.976144 Set Vref, RX VrefLevel [Byte0]: 64
8662 04:38:23.978925 [Byte1]: 64
8663 04:38:23.983561
8664 04:38:23.983656 Set Vref, RX VrefLevel [Byte0]: 65
8665 04:38:23.986908 [Byte1]: 65
8666 04:38:23.990768
8667 04:38:23.990850 Set Vref, RX VrefLevel [Byte0]: 66
8668 04:38:23.994010 [Byte1]: 66
8669 04:38:23.998260
8670 04:38:23.998364 Set Vref, RX VrefLevel [Byte0]: 67
8671 04:38:24.001852 [Byte1]: 67
8672 04:38:24.006147
8673 04:38:24.006228 Set Vref, RX VrefLevel [Byte0]: 68
8674 04:38:24.009110 [Byte1]: 68
8675 04:38:24.013513
8676 04:38:24.013593 Set Vref, RX VrefLevel [Byte0]: 69
8677 04:38:24.016813 [Byte1]: 69
8678 04:38:24.021429
8679 04:38:24.021509 Set Vref, RX VrefLevel [Byte0]: 70
8680 04:38:24.024405 [Byte1]: 70
8681 04:38:24.028542
8682 04:38:24.028622 Set Vref, RX VrefLevel [Byte0]: 71
8683 04:38:24.031932 [Byte1]: 71
8684 04:38:24.035947
8685 04:38:24.036028 Set Vref, RX VrefLevel [Byte0]: 72
8686 04:38:24.039441 [Byte1]: 72
8687 04:38:24.043335
8688 04:38:24.043415 Set Vref, RX VrefLevel [Byte0]: 73
8689 04:38:24.047136 [Byte1]: 73
8690 04:38:24.050927
8691 04:38:24.051008 Set Vref, RX VrefLevel [Byte0]: 74
8692 04:38:24.054443 [Byte1]: 74
8693 04:38:24.058748
8694 04:38:24.058828 Set Vref, RX VrefLevel [Byte0]: 75
8695 04:38:24.061971 [Byte1]: 75
8696 04:38:24.066414
8697 04:38:24.066495 Final RX Vref Byte 0 = 59 to rank0
8698 04:38:24.069812 Final RX Vref Byte 1 = 55 to rank0
8699 04:38:24.072769 Final RX Vref Byte 0 = 59 to rank1
8700 04:38:24.076065 Final RX Vref Byte 1 = 55 to rank1==
8701 04:38:24.079753 Dram Type= 6, Freq= 0, CH_1, rank 0
8702 04:38:24.085936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8703 04:38:24.086022 ==
8704 04:38:24.086101 DQS Delay:
8705 04:38:24.086161 DQS0 = 0, DQS1 = 0
8706 04:38:24.089439 DQM Delay:
8707 04:38:24.089521 DQM0 = 134, DQM1 = 131
8708 04:38:24.092661 DQ Delay:
8709 04:38:24.095979 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8710 04:38:24.099470 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8711 04:38:24.102846 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8712 04:38:24.106092 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8713 04:38:24.106174
8714 04:38:24.106237
8715 04:38:24.106296
8716 04:38:24.109929 [DramC_TX_OE_Calibration] TA2
8717 04:38:24.112765 Original DQ_B0 (3 6) =30, OEN = 27
8718 04:38:24.115890 Original DQ_B1 (3 6) =30, OEN = 27
8719 04:38:24.119235 24, 0x0, End_B0=24 End_B1=24
8720 04:38:24.119317 25, 0x0, End_B0=25 End_B1=25
8721 04:38:24.122451 26, 0x0, End_B0=26 End_B1=26
8722 04:38:24.125981 27, 0x0, End_B0=27 End_B1=27
8723 04:38:24.129523 28, 0x0, End_B0=28 End_B1=28
8724 04:38:24.129606 29, 0x0, End_B0=29 End_B1=29
8725 04:38:24.132350 30, 0x0, End_B0=30 End_B1=30
8726 04:38:24.135840 31, 0x4141, End_B0=30 End_B1=30
8727 04:38:24.139330 Byte0 end_step=30 best_step=27
8728 04:38:24.142314 Byte1 end_step=30 best_step=27
8729 04:38:24.145880 Byte0 TX OE(2T, 0.5T) = (3, 3)
8730 04:38:24.149452 Byte1 TX OE(2T, 0.5T) = (3, 3)
8731 04:38:24.149534
8732 04:38:24.149598
8733 04:38:24.155935 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8734 04:38:24.159376 CH1 RK0: MR19=303, MR18=1725
8735 04:38:24.165731 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8736 04:38:24.165817
8737 04:38:24.169486 ----->DramcWriteLeveling(PI) begin...
8738 04:38:24.169568 ==
8739 04:38:24.172208 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 04:38:24.175910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 04:38:24.175993 ==
8742 04:38:24.179086 Write leveling (Byte 0): 25 => 25
8743 04:38:24.182330 Write leveling (Byte 1): 28 => 28
8744 04:38:24.186242 DramcWriteLeveling(PI) end<-----
8745 04:38:24.186323
8746 04:38:24.186387 ==
8747 04:38:24.189287 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 04:38:24.192456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 04:38:24.192540 ==
8750 04:38:24.195674 [Gating] SW mode calibration
8751 04:38:24.202690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8752 04:38:24.209242 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8753 04:38:24.212211 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 04:38:24.215591 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 04:38:24.222507 1 4 8 | B1->B0 | 2b2b 2424 | 1 0 | (0 0) (0 0)
8756 04:38:24.225615 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8757 04:38:24.229065 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 04:38:24.235899 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 04:38:24.238915 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 04:38:24.242384 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 04:38:24.248847 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 04:38:24.252288 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8763 04:38:24.255700 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8764 04:38:24.262108 1 5 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 0)
8765 04:38:24.265360 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 04:38:24.269005 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 04:38:24.275708 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 04:38:24.278605 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 04:38:24.281993 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 04:38:24.288845 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 04:38:24.291937 1 6 8 | B1->B0 | 3e3e 2626 | 0 0 | (0 0) (0 0)
8772 04:38:24.295625 1 6 12 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
8773 04:38:24.302116 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 04:38:24.305392 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 04:38:24.308396 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 04:38:24.315381 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 04:38:24.318376 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 04:38:24.321754 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 04:38:24.328093 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8780 04:38:24.331356 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8781 04:38:24.335142 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8782 04:38:24.341737 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 04:38:24.344900 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 04:38:24.348440 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 04:38:24.354797 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 04:38:24.358139 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 04:38:24.361210 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 04:38:24.368028 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 04:38:24.371773 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 04:38:24.374405 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 04:38:24.381491 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 04:38:24.384798 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 04:38:24.388103 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 04:38:24.391008 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 04:38:24.398033 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8796 04:38:24.401027 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8797 04:38:24.404562 Total UI for P1: 0, mck2ui 16
8798 04:38:24.408015 best dqsien dly found for B1: ( 1, 9, 8)
8799 04:38:24.411323 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 04:38:24.414412 Total UI for P1: 0, mck2ui 16
8801 04:38:24.417932 best dqsien dly found for B0: ( 1, 9, 12)
8802 04:38:24.421160 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8803 04:38:24.424330 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8804 04:38:24.428187
8805 04:38:24.430954 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8806 04:38:24.434646 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8807 04:38:24.438152 [Gating] SW calibration Done
8808 04:38:24.438258 ==
8809 04:38:24.440855 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 04:38:24.444283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 04:38:24.444365 ==
8812 04:38:24.444429 RX Vref Scan: 0
8813 04:38:24.447738
8814 04:38:24.447819 RX Vref 0 -> 0, step: 1
8815 04:38:24.447883
8816 04:38:24.450783 RX Delay 0 -> 252, step: 8
8817 04:38:24.454231 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8818 04:38:24.457695 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8819 04:38:24.464551 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8820 04:38:24.467464 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8821 04:38:24.470897 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8822 04:38:24.474492 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8823 04:38:24.477350 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8824 04:38:24.484019 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8825 04:38:24.487537 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8826 04:38:24.490914 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8827 04:38:24.494242 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8828 04:38:24.497769 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8829 04:38:24.504069 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8830 04:38:24.507642 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8831 04:38:24.510710 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8832 04:38:24.513984 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8833 04:38:24.514065 ==
8834 04:38:24.517545 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 04:38:24.523696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 04:38:24.523777 ==
8837 04:38:24.523842 DQS Delay:
8838 04:38:24.527622 DQS0 = 0, DQS1 = 0
8839 04:38:24.527703 DQM Delay:
8840 04:38:24.527800 DQM0 = 136, DQM1 = 133
8841 04:38:24.530332 DQ Delay:
8842 04:38:24.533759 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8843 04:38:24.536963 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8844 04:38:24.540550 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8845 04:38:24.544221 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8846 04:38:24.544305
8847 04:38:24.544369
8848 04:38:24.544428 ==
8849 04:38:24.547075 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 04:38:24.550509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 04:38:24.554142 ==
8852 04:38:24.554223
8853 04:38:24.554286
8854 04:38:24.554345 TX Vref Scan disable
8855 04:38:24.557203 == TX Byte 0 ==
8856 04:38:24.560575 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8857 04:38:24.563447 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8858 04:38:24.566931 == TX Byte 1 ==
8859 04:38:24.570520 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8860 04:38:24.573684 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8861 04:38:24.577039 ==
8862 04:38:24.577120 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 04:38:24.583858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 04:38:24.583940 ==
8865 04:38:24.596699
8866 04:38:24.600133 TX Vref early break, caculate TX vref
8867 04:38:24.603138 TX Vref=16, minBit 0, minWin=23, winSum=382
8868 04:38:24.606587 TX Vref=18, minBit 0, minWin=23, winSum=395
8869 04:38:24.610048 TX Vref=20, minBit 1, minWin=24, winSum=402
8870 04:38:24.613050 TX Vref=22, minBit 1, minWin=24, winSum=409
8871 04:38:24.616717 TX Vref=24, minBit 0, minWin=25, winSum=421
8872 04:38:24.623044 TX Vref=26, minBit 0, minWin=25, winSum=425
8873 04:38:24.626504 TX Vref=28, minBit 0, minWin=24, winSum=429
8874 04:38:24.629929 TX Vref=30, minBit 0, minWin=25, winSum=420
8875 04:38:24.633326 TX Vref=32, minBit 0, minWin=24, winSum=409
8876 04:38:24.636303 TX Vref=34, minBit 0, minWin=24, winSum=409
8877 04:38:24.639556 TX Vref=36, minBit 0, minWin=23, winSum=398
8878 04:38:24.646266 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8879 04:38:24.646348
8880 04:38:24.649701 Final TX Range 0 Vref 26
8881 04:38:24.649783
8882 04:38:24.649846 ==
8883 04:38:24.653002 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 04:38:24.656314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 04:38:24.656400 ==
8886 04:38:24.656465
8887 04:38:24.659566
8888 04:38:24.659651 TX Vref Scan disable
8889 04:38:24.666087 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8890 04:38:24.666167 == TX Byte 0 ==
8891 04:38:24.669401 u2DelayCellOfst[0]=17 cells (5 PI)
8892 04:38:24.673125 u2DelayCellOfst[1]=10 cells (3 PI)
8893 04:38:24.676396 u2DelayCellOfst[2]=0 cells (0 PI)
8894 04:38:24.679678 u2DelayCellOfst[3]=6 cells (2 PI)
8895 04:38:24.683088 u2DelayCellOfst[4]=10 cells (3 PI)
8896 04:38:24.685993 u2DelayCellOfst[5]=17 cells (5 PI)
8897 04:38:24.689831 u2DelayCellOfst[6]=17 cells (5 PI)
8898 04:38:24.693275 u2DelayCellOfst[7]=6 cells (2 PI)
8899 04:38:24.696351 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8900 04:38:24.699552 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8901 04:38:24.702911 == TX Byte 1 ==
8902 04:38:24.706342 u2DelayCellOfst[8]=0 cells (0 PI)
8903 04:38:24.706439 u2DelayCellOfst[9]=3 cells (1 PI)
8904 04:38:24.709333 u2DelayCellOfst[10]=10 cells (3 PI)
8905 04:38:24.712777 u2DelayCellOfst[11]=3 cells (1 PI)
8906 04:38:24.716332 u2DelayCellOfst[12]=13 cells (4 PI)
8907 04:38:24.719722 u2DelayCellOfst[13]=13 cells (4 PI)
8908 04:38:24.722621 u2DelayCellOfst[14]=13 cells (4 PI)
8909 04:38:24.726090 u2DelayCellOfst[15]=17 cells (5 PI)
8910 04:38:24.729521 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8911 04:38:24.736007 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8912 04:38:24.736112 DramC Write-DBI on
8913 04:38:24.736201 ==
8914 04:38:24.739429 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 04:38:24.746159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 04:38:24.746247 ==
8917 04:38:24.746310
8918 04:38:24.746367
8919 04:38:24.746423 TX Vref Scan disable
8920 04:38:24.749794 == TX Byte 0 ==
8921 04:38:24.753240 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8922 04:38:24.756434 == TX Byte 1 ==
8923 04:38:24.759805 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8924 04:38:24.763224 DramC Write-DBI off
8925 04:38:24.763319
8926 04:38:24.763405 [DATLAT]
8927 04:38:24.763498 Freq=1600, CH1 RK1
8928 04:38:24.763628
8929 04:38:24.766108 DATLAT Default: 0xf
8930 04:38:24.769930 0, 0xFFFF, sum = 0
8931 04:38:24.770035 1, 0xFFFF, sum = 0
8932 04:38:24.772977 2, 0xFFFF, sum = 0
8933 04:38:24.773072 3, 0xFFFF, sum = 0
8934 04:38:24.776533 4, 0xFFFF, sum = 0
8935 04:38:24.776629 5, 0xFFFF, sum = 0
8936 04:38:24.779837 6, 0xFFFF, sum = 0
8937 04:38:24.779933 7, 0xFFFF, sum = 0
8938 04:38:24.783234 8, 0xFFFF, sum = 0
8939 04:38:24.783304 9, 0xFFFF, sum = 0
8940 04:38:24.786656 10, 0xFFFF, sum = 0
8941 04:38:24.786760 11, 0xFFFF, sum = 0
8942 04:38:24.789731 12, 0xFFFF, sum = 0
8943 04:38:24.789828 13, 0xFFFF, sum = 0
8944 04:38:24.793384 14, 0x0, sum = 1
8945 04:38:24.793488 15, 0x0, sum = 2
8946 04:38:24.796233 16, 0x0, sum = 3
8947 04:38:24.796307 17, 0x0, sum = 4
8948 04:38:24.799604 best_step = 15
8949 04:38:24.799706
8950 04:38:24.799795 ==
8951 04:38:24.802664 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 04:38:24.806378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 04:38:24.806458 ==
8954 04:38:24.809518 RX Vref Scan: 0
8955 04:38:24.809599
8956 04:38:24.809663 RX Vref 0 -> 0, step: 1
8957 04:38:24.809722
8958 04:38:24.813008 RX Delay 19 -> 252, step: 4
8959 04:38:24.816645 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8960 04:38:24.823247 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8961 04:38:24.826312 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8962 04:38:24.829570 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8963 04:38:24.833129 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8964 04:38:24.836672 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8965 04:38:24.839593 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8966 04:38:24.846687 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8967 04:38:24.849505 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8968 04:38:24.853403 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8969 04:38:24.856524 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8970 04:38:24.859503 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8971 04:38:24.866409 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8972 04:38:24.869829 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8973 04:38:24.873256 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8974 04:38:24.876724 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8975 04:38:24.876806 ==
8976 04:38:24.879566 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 04:38:24.886335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 04:38:24.886417 ==
8979 04:38:24.886481 DQS Delay:
8980 04:38:24.889413 DQS0 = 0, DQS1 = 0
8981 04:38:24.889524 DQM Delay:
8982 04:38:24.889588 DQM0 = 134, DQM1 = 130
8983 04:38:24.892970 DQ Delay:
8984 04:38:24.896353 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8985 04:38:24.899644 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8986 04:38:24.902919 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =126
8987 04:38:24.906431 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8988 04:38:24.906512
8989 04:38:24.906576
8990 04:38:24.906634
8991 04:38:24.909782 [DramC_TX_OE_Calibration] TA2
8992 04:38:24.912654 Original DQ_B0 (3 6) =30, OEN = 27
8993 04:38:24.915993 Original DQ_B1 (3 6) =30, OEN = 27
8994 04:38:24.919350 24, 0x0, End_B0=24 End_B1=24
8995 04:38:24.919463 25, 0x0, End_B0=25 End_B1=25
8996 04:38:24.922807 26, 0x0, End_B0=26 End_B1=26
8997 04:38:24.926515 27, 0x0, End_B0=27 End_B1=27
8998 04:38:24.929368 28, 0x0, End_B0=28 End_B1=28
8999 04:38:24.932868 29, 0x0, End_B0=29 End_B1=29
9000 04:38:24.932951 30, 0x0, End_B0=30 End_B1=30
9001 04:38:24.936390 31, 0x5151, End_B0=30 End_B1=30
9002 04:38:24.939962 Byte0 end_step=30 best_step=27
9003 04:38:24.942853 Byte1 end_step=30 best_step=27
9004 04:38:24.946194 Byte0 TX OE(2T, 0.5T) = (3, 3)
9005 04:38:24.949674 Byte1 TX OE(2T, 0.5T) = (3, 3)
9006 04:38:24.949755
9007 04:38:24.949819
9008 04:38:24.955995 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9009 04:38:24.959406 CH1 RK1: MR19=303, MR18=2409
9010 04:38:24.966157 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9011 04:38:24.969574 [RxdqsGatingPostProcess] freq 1600
9012 04:38:24.972861 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9013 04:38:24.976095 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 04:38:24.979467 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 04:38:24.983009 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 04:38:24.985900 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 04:38:24.989350 best DQS0 dly(2T, 0.5T) = (1, 1)
9018 04:38:24.992788 best DQS1 dly(2T, 0.5T) = (1, 1)
9019 04:38:24.995715 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9020 04:38:24.999432 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9021 04:38:25.002770 Pre-setting of DQS Precalculation
9022 04:38:25.005954 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9023 04:38:25.012522 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9024 04:38:25.019088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9025 04:38:25.022416
9026 04:38:25.022524
9027 04:38:25.022616 [Calibration Summary] 3200 Mbps
9028 04:38:25.025670 CH 0, Rank 0
9029 04:38:25.025766 SW Impedance : PASS
9030 04:38:25.029127 DUTY Scan : NO K
9031 04:38:25.032677 ZQ Calibration : PASS
9032 04:38:25.032758 Jitter Meter : NO K
9033 04:38:25.035893 CBT Training : PASS
9034 04:38:25.039165 Write leveling : PASS
9035 04:38:25.039246 RX DQS gating : PASS
9036 04:38:25.042676 RX DQ/DQS(RDDQC) : PASS
9037 04:38:25.045624 TX DQ/DQS : PASS
9038 04:38:25.045705 RX DATLAT : PASS
9039 04:38:25.049138 RX DQ/DQS(Engine): PASS
9040 04:38:25.052679 TX OE : PASS
9041 04:38:25.052760 All Pass.
9042 04:38:25.052824
9043 04:38:25.052884 CH 0, Rank 1
9044 04:38:25.055588 SW Impedance : PASS
9045 04:38:25.059132 DUTY Scan : NO K
9046 04:38:25.059212 ZQ Calibration : PASS
9047 04:38:25.062707 Jitter Meter : NO K
9048 04:38:25.065877 CBT Training : PASS
9049 04:38:25.065958 Write leveling : PASS
9050 04:38:25.068889 RX DQS gating : PASS
9051 04:38:25.068970 RX DQ/DQS(RDDQC) : PASS
9052 04:38:25.072370 TX DQ/DQS : PASS
9053 04:38:25.075787 RX DATLAT : PASS
9054 04:38:25.075883 RX DQ/DQS(Engine): PASS
9055 04:38:25.078631 TX OE : PASS
9056 04:38:25.078754 All Pass.
9057 04:38:25.078868
9058 04:38:25.082174 CH 1, Rank 0
9059 04:38:25.082270 SW Impedance : PASS
9060 04:38:25.085603 DUTY Scan : NO K
9061 04:38:25.088809 ZQ Calibration : PASS
9062 04:38:25.088891 Jitter Meter : NO K
9063 04:38:25.092406 CBT Training : PASS
9064 04:38:25.095411 Write leveling : PASS
9065 04:38:25.095492 RX DQS gating : PASS
9066 04:38:25.098839 RX DQ/DQS(RDDQC) : PASS
9067 04:38:25.101837 TX DQ/DQS : PASS
9068 04:38:25.101919 RX DATLAT : PASS
9069 04:38:25.105292 RX DQ/DQS(Engine): PASS
9070 04:38:25.108586 TX OE : PASS
9071 04:38:25.108668 All Pass.
9072 04:38:25.108731
9073 04:38:25.108790 CH 1, Rank 1
9074 04:38:25.111781 SW Impedance : PASS
9075 04:38:25.115504 DUTY Scan : NO K
9076 04:38:25.115624 ZQ Calibration : PASS
9077 04:38:25.119051 Jitter Meter : NO K
9078 04:38:25.122087 CBT Training : PASS
9079 04:38:25.122169 Write leveling : PASS
9080 04:38:25.125529 RX DQS gating : PASS
9081 04:38:25.125611 RX DQ/DQS(RDDQC) : PASS
9082 04:38:25.128408 TX DQ/DQS : PASS
9083 04:38:25.131915 RX DATLAT : PASS
9084 04:38:25.132012 RX DQ/DQS(Engine): PASS
9085 04:38:25.135454 TX OE : PASS
9086 04:38:25.135575 All Pass.
9087 04:38:25.135640
9088 04:38:25.138178 DramC Write-DBI on
9089 04:38:25.141536 PER_BANK_REFRESH: Hybrid Mode
9090 04:38:25.141617 TX_TRACKING: ON
9091 04:38:25.151652 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9092 04:38:25.158137 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9093 04:38:25.168524 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9094 04:38:25.171336 [FAST_K] Save calibration result to emmc
9095 04:38:25.171418 sync common calibartion params.
9096 04:38:25.174853 sync cbt_mode0:1, 1:1
9097 04:38:25.178337 dram_init: ddr_geometry: 2
9098 04:38:25.181373 dram_init: ddr_geometry: 2
9099 04:38:25.181453 dram_init: ddr_geometry: 2
9100 04:38:25.184941 0:dram_rank_size:100000000
9101 04:38:25.188303 1:dram_rank_size:100000000
9102 04:38:25.191926 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9103 04:38:25.194877 DFS_SHUFFLE_HW_MODE: ON
9104 04:38:25.198366 dramc_set_vcore_voltage set vcore to 725000
9105 04:38:25.201551 Read voltage for 1600, 0
9106 04:38:25.201631 Vio18 = 0
9107 04:38:25.204747 Vcore = 725000
9108 04:38:25.204828 Vdram = 0
9109 04:38:25.204891 Vddq = 0
9110 04:38:25.204954 Vmddr = 0
9111 04:38:25.208018 switch to 3200 Mbps bootup
9112 04:38:25.211359 [DramcRunTimeConfig]
9113 04:38:25.211439 PHYPLL
9114 04:38:25.214786 DPM_CONTROL_AFTERK: ON
9115 04:38:25.214867 PER_BANK_REFRESH: ON
9116 04:38:25.218148 REFRESH_OVERHEAD_REDUCTION: ON
9117 04:38:25.221370 CMD_PICG_NEW_MODE: OFF
9118 04:38:25.221450 XRTWTW_NEW_MODE: ON
9119 04:38:25.224904 XRTRTR_NEW_MODE: ON
9120 04:38:25.224985 TX_TRACKING: ON
9121 04:38:25.228023 RDSEL_TRACKING: OFF
9122 04:38:25.228124 DQS Precalculation for DVFS: ON
9123 04:38:25.231051 RX_TRACKING: OFF
9124 04:38:25.231159 HW_GATING DBG: ON
9125 04:38:25.234599 ZQCS_ENABLE_LP4: ON
9126 04:38:25.238134 RX_PICG_NEW_MODE: ON
9127 04:38:25.238215 TX_PICG_NEW_MODE: ON
9128 04:38:25.241509 ENABLE_RX_DCM_DPHY: ON
9129 04:38:25.244915 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9130 04:38:25.244996 DUMMY_READ_FOR_TRACKING: OFF
9131 04:38:25.247842 !!! SPM_CONTROL_AFTERK: OFF
9132 04:38:25.251222 !!! SPM could not control APHY
9133 04:38:25.254771 IMPEDANCE_TRACKING: ON
9134 04:38:25.254852 TEMP_SENSOR: ON
9135 04:38:25.257988 HW_SAVE_FOR_SR: OFF
9136 04:38:25.258083 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9137 04:38:25.264828 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9138 04:38:25.264910 Read ODT Tracking: ON
9139 04:38:25.268130 Refresh Rate DeBounce: ON
9140 04:38:25.271441 DFS_NO_QUEUE_FLUSH: ON
9141 04:38:25.274904 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9142 04:38:25.274985 ENABLE_DFS_RUNTIME_MRW: OFF
9143 04:38:25.277843 DDR_RESERVE_NEW_MODE: ON
9144 04:38:25.281258 MR_CBT_SWITCH_FREQ: ON
9145 04:38:25.281339 =========================
9146 04:38:25.301046 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9147 04:38:25.304273 dram_init: ddr_geometry: 2
9148 04:38:25.322672 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9149 04:38:25.326020 dram_init: dram init end (result: 0)
9150 04:38:25.332799 DRAM-K: Full calibration passed in 24482 msecs
9151 04:38:25.335769 MRC: failed to locate region type 0.
9152 04:38:25.335849 DRAM rank0 size:0x100000000,
9153 04:38:25.339678 DRAM rank1 size=0x100000000
9154 04:38:25.349197 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9155 04:38:25.356014 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9156 04:38:25.362408 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9157 04:38:25.369313 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9158 04:38:25.372569 DRAM rank0 size:0x100000000,
9159 04:38:25.376393 DRAM rank1 size=0x100000000
9160 04:38:25.376473 CBMEM:
9161 04:38:25.379149 IMD: root @ 0xfffff000 254 entries.
9162 04:38:25.382345 IMD: root @ 0xffffec00 62 entries.
9163 04:38:25.385698 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9164 04:38:25.389206 WARNING: RO_VPD is uninitialized or empty.
9165 04:38:25.395701 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9166 04:38:25.402500 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9167 04:38:25.415163 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9168 04:38:25.426937 BS: romstage times (exec / console): total (unknown) / 24013 ms
9169 04:38:25.427028
9170 04:38:25.427092
9171 04:38:25.436735 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9172 04:38:25.440240 ARM64: Exception handlers installed.
9173 04:38:25.443591 ARM64: Testing exception
9174 04:38:25.446670 ARM64: Done test exception
9175 04:38:25.446751 Enumerating buses...
9176 04:38:25.449871 Show all devs... Before device enumeration.
9177 04:38:25.453564 Root Device: enabled 1
9178 04:38:25.456408 CPU_CLUSTER: 0: enabled 1
9179 04:38:25.456489 CPU: 00: enabled 1
9180 04:38:25.459697 Compare with tree...
9181 04:38:25.459778 Root Device: enabled 1
9182 04:38:25.463048 CPU_CLUSTER: 0: enabled 1
9183 04:38:25.466532 CPU: 00: enabled 1
9184 04:38:25.466613 Root Device scanning...
9185 04:38:25.470160 scan_static_bus for Root Device
9186 04:38:25.472987 CPU_CLUSTER: 0 enabled
9187 04:38:25.476579 scan_static_bus for Root Device done
9188 04:38:25.480015 scan_bus: bus Root Device finished in 8 msecs
9189 04:38:25.480097 done
9190 04:38:25.486384 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9191 04:38:25.489533 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9192 04:38:25.496326 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9193 04:38:25.499658 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9194 04:38:25.503136 Allocating resources...
9195 04:38:25.506199 Reading resources...
9196 04:38:25.509587 Root Device read_resources bus 0 link: 0
9197 04:38:25.509668 DRAM rank0 size:0x100000000,
9198 04:38:25.513290 DRAM rank1 size=0x100000000
9199 04:38:25.516159 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9200 04:38:25.519702 CPU: 00 missing read_resources
9201 04:38:25.523277 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9202 04:38:25.529686 Root Device read_resources bus 0 link: 0 done
9203 04:38:25.529767 Done reading resources.
9204 04:38:25.536423 Show resources in subtree (Root Device)...After reading.
9205 04:38:25.539497 Root Device child on link 0 CPU_CLUSTER: 0
9206 04:38:25.542883 CPU_CLUSTER: 0 child on link 0 CPU: 00
9207 04:38:25.552898 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9208 04:38:25.552980 CPU: 00
9209 04:38:25.556312 Root Device assign_resources, bus 0 link: 0
9210 04:38:25.559430 CPU_CLUSTER: 0 missing set_resources
9211 04:38:25.566132 Root Device assign_resources, bus 0 link: 0 done
9212 04:38:25.566213 Done setting resources.
9213 04:38:25.572978 Show resources in subtree (Root Device)...After assigning values.
9214 04:38:25.575925 Root Device child on link 0 CPU_CLUSTER: 0
9215 04:38:25.579424 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 04:38:25.589306 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 04:38:25.589389 CPU: 00
9218 04:38:25.592792 Done allocating resources.
9219 04:38:25.596119 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9220 04:38:25.599419 Enabling resources...
9221 04:38:25.599500 done.
9222 04:38:25.606066 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9223 04:38:25.606148 Initializing devices...
9224 04:38:25.609280 Root Device init
9225 04:38:25.609361 init hardware done!
9226 04:38:25.612681 0x00000018: ctrlr->caps
9227 04:38:25.615825 52.000 MHz: ctrlr->f_max
9228 04:38:25.615908 0.400 MHz: ctrlr->f_min
9229 04:38:25.619234 0x40ff8080: ctrlr->voltages
9230 04:38:25.619316 sclk: 390625
9231 04:38:25.622636 Bus Width = 1
9232 04:38:25.622745 sclk: 390625
9233 04:38:25.626258 Bus Width = 1
9234 04:38:25.626339 Early init status = 3
9235 04:38:25.632592 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9236 04:38:25.636088 in-header: 03 fc 00 00 01 00 00 00
9237 04:38:25.639150 in-data: 00
9238 04:38:25.642477 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9239 04:38:25.647073 in-header: 03 fd 00 00 00 00 00 00
9240 04:38:25.650865 in-data:
9241 04:38:25.654002 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9242 04:38:25.658233 in-header: 03 fc 00 00 01 00 00 00
9243 04:38:25.662001 in-data: 00
9244 04:38:25.664894 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9245 04:38:25.670314 in-header: 03 fd 00 00 00 00 00 00
9246 04:38:25.673333 in-data:
9247 04:38:25.676945 [SSUSB] Setting up USB HOST controller...
9248 04:38:25.680517 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9249 04:38:25.683564 [SSUSB] phy power-on done.
9250 04:38:25.686727 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9251 04:38:25.693777 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9252 04:38:25.696642 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9253 04:38:25.703657 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9254 04:38:25.710015 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9255 04:38:25.716854 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9256 04:38:25.723156 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9257 04:38:25.729892 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9258 04:38:25.733520 SPM: binary array size = 0x9dc
9259 04:38:25.736980 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9260 04:38:25.743569 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9261 04:38:25.749889 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9262 04:38:25.753341 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9263 04:38:25.759814 configure_display: Starting display init
9264 04:38:25.793350 anx7625_power_on_init: Init interface.
9265 04:38:25.796722 anx7625_disable_pd_protocol: Disabled PD feature.
9266 04:38:25.800201 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9267 04:38:25.828150 anx7625_start_dp_work: Secure OCM version=00
9268 04:38:25.831419 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9269 04:38:25.846125 sp_tx_get_edid_block: EDID Block = 1
9270 04:38:25.948738 Extracted contents:
9271 04:38:25.952085 header: 00 ff ff ff ff ff ff 00
9272 04:38:25.955089 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9273 04:38:25.958759 version: 01 04
9274 04:38:25.962090 basic params: 95 1f 11 78 0a
9275 04:38:25.965232 chroma info: 76 90 94 55 54 90 27 21 50 54
9276 04:38:25.968592 established: 00 00 00
9277 04:38:25.974816 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9278 04:38:25.981598 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9279 04:38:25.984495 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9280 04:38:25.991413 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9281 04:38:25.998269 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9282 04:38:26.001395 extensions: 00
9283 04:38:26.001476 checksum: fb
9284 04:38:26.001540
9285 04:38:26.004720 Manufacturer: IVO Model 57d Serial Number 0
9286 04:38:26.008273 Made week 0 of 2020
9287 04:38:26.011338 EDID version: 1.4
9288 04:38:26.011419 Digital display
9289 04:38:26.014776 6 bits per primary color channel
9290 04:38:26.014859 DisplayPort interface
9291 04:38:26.018155 Maximum image size: 31 cm x 17 cm
9292 04:38:26.021352 Gamma: 220%
9293 04:38:26.021432 Check DPMS levels
9294 04:38:26.025122 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9295 04:38:26.031485 First detailed timing is preferred timing
9296 04:38:26.031606 Established timings supported:
9297 04:38:26.034730 Standard timings supported:
9298 04:38:26.038102 Detailed timings
9299 04:38:26.041839 Hex of detail: 383680a07038204018303c0035ae10000019
9300 04:38:26.044524 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9301 04:38:26.051368 0780 0798 07c8 0820 hborder 0
9302 04:38:26.054369 0438 043b 0447 0458 vborder 0
9303 04:38:26.057899 -hsync -vsync
9304 04:38:26.057979 Did detailed timing
9305 04:38:26.064684 Hex of detail: 000000000000000000000000000000000000
9306 04:38:26.067803 Manufacturer-specified data, tag 0
9307 04:38:26.071173 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9308 04:38:26.074699 ASCII string: InfoVision
9309 04:38:26.078042 Hex of detail: 000000fe00523134304e574635205248200a
9310 04:38:26.081501 ASCII string: R140NWF5 RH
9311 04:38:26.081582 Checksum
9312 04:38:26.085101 Checksum: 0xfb (valid)
9313 04:38:26.087692 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9314 04:38:26.091193 DSI data_rate: 832800000 bps
9315 04:38:26.098026 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9316 04:38:26.101512 anx7625_parse_edid: pixelclock(138800).
9317 04:38:26.104445 hactive(1920), hsync(48), hfp(24), hbp(88)
9318 04:38:26.107833 vactive(1080), vsync(12), vfp(3), vbp(17)
9319 04:38:26.111553 anx7625_dsi_config: config dsi.
9320 04:38:26.118228 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9321 04:38:26.130509 anx7625_dsi_config: success to config DSI
9322 04:38:26.134115 anx7625_dp_start: MIPI phy setup OK.
9323 04:38:26.137278 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9324 04:38:26.140868 mtk_ddp_mode_set invalid vrefresh 60
9325 04:38:26.144089 main_disp_path_setup
9326 04:38:26.144170 ovl_layer_smi_id_en
9327 04:38:26.147396 ovl_layer_smi_id_en
9328 04:38:26.147502 ccorr_config
9329 04:38:26.147610 aal_config
9330 04:38:26.150722 gamma_config
9331 04:38:26.150805 postmask_config
9332 04:38:26.154384 dither_config
9333 04:38:26.157041 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9334 04:38:26.164056 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9335 04:38:26.167057 Root Device init finished in 555 msecs
9336 04:38:26.167138 CPU_CLUSTER: 0 init
9337 04:38:26.177312 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9338 04:38:26.180399 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9339 04:38:26.183870 APU_MBOX 0x190000b0 = 0x10001
9340 04:38:26.187150 APU_MBOX 0x190001b0 = 0x10001
9341 04:38:26.190651 APU_MBOX 0x190005b0 = 0x10001
9342 04:38:26.193730 APU_MBOX 0x190006b0 = 0x10001
9343 04:38:26.197215 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9344 04:38:26.209625 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9345 04:38:26.222267 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9346 04:38:26.228526 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9347 04:38:26.240437 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9348 04:38:26.249785 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9349 04:38:26.252808 CPU_CLUSTER: 0 init finished in 81 msecs
9350 04:38:26.256723 Devices initialized
9351 04:38:26.259426 Show all devs... After init.
9352 04:38:26.259506 Root Device: enabled 1
9353 04:38:26.262515 CPU_CLUSTER: 0: enabled 1
9354 04:38:26.266120 CPU: 00: enabled 1
9355 04:38:26.269485 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9356 04:38:26.273001 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9357 04:38:26.275879 ELOG: NV offset 0x57f000 size 0x1000
9358 04:38:26.282857 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9359 04:38:26.289180 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9360 04:38:26.292665 ELOG: Event(17) added with size 13 at 2023-08-09 04:37:51 UTC
9361 04:38:26.295880 out: cmd=0x121: 03 db 21 01 00 00 00 00
9362 04:38:26.300218 in-header: 03 c0 00 00 2c 00 00 00
9363 04:38:26.312872 in-data: 9f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9364 04:38:26.319753 ELOG: Event(A1) added with size 10 at 2023-08-09 04:37:51 UTC
9365 04:38:26.326790 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9366 04:38:26.333107 ELOG: Event(A0) added with size 9 at 2023-08-09 04:37:51 UTC
9367 04:38:26.336025 elog_add_boot_reason: Logged dev mode boot
9368 04:38:26.339699 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9369 04:38:26.342913 Finalize devices...
9370 04:38:26.342993 Devices finalized
9371 04:38:26.349306 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9372 04:38:26.352841 Writing coreboot table at 0xffe64000
9373 04:38:26.356160 0. 000000000010a000-0000000000113fff: RAMSTAGE
9374 04:38:26.359361 1. 0000000040000000-00000000400fffff: RAM
9375 04:38:26.366165 2. 0000000040100000-000000004032afff: RAMSTAGE
9376 04:38:26.369535 3. 000000004032b000-00000000545fffff: RAM
9377 04:38:26.372737 4. 0000000054600000-000000005465ffff: BL31
9378 04:38:26.376138 5. 0000000054660000-00000000ffe63fff: RAM
9379 04:38:26.382693 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9380 04:38:26.386240 7. 0000000100000000-000000023fffffff: RAM
9381 04:38:26.386321 Passing 5 GPIOs to payload:
9382 04:38:26.392669 NAME | PORT | POLARITY | VALUE
9383 04:38:26.396215 EC in RW | 0x000000aa | low | undefined
9384 04:38:26.403004 EC interrupt | 0x00000005 | low | undefined
9385 04:38:26.406508 TPM interrupt | 0x000000ab | high | undefined
9386 04:38:26.409159 SD card detect | 0x00000011 | high | undefined
9387 04:38:26.416324 speaker enable | 0x00000093 | high | undefined
9388 04:38:26.419430 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9389 04:38:26.422575 in-header: 03 f9 00 00 02 00 00 00
9390 04:38:26.422657 in-data: 02 00
9391 04:38:26.426286 ADC[4]: Raw value=903618 ID=7
9392 04:38:26.429637 ADC[3]: Raw value=213810 ID=1
9393 04:38:26.429719 RAM Code: 0x71
9394 04:38:26.432683 ADC[6]: Raw value=75332 ID=0
9395 04:38:26.436820 ADC[5]: Raw value=212703 ID=1
9396 04:38:26.436900 SKU Code: 0x1
9397 04:38:26.442912 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2f90
9398 04:38:26.446380 coreboot table: 964 bytes.
9399 04:38:26.449269 IMD ROOT 0. 0xfffff000 0x00001000
9400 04:38:26.452647 IMD SMALL 1. 0xffffe000 0x00001000
9401 04:38:26.456123 RO MCACHE 2. 0xffffc000 0x00001104
9402 04:38:26.459046 CONSOLE 3. 0xfff7c000 0x00080000
9403 04:38:26.462675 FMAP 4. 0xfff7b000 0x00000452
9404 04:38:26.465927 TIME STAMP 5. 0xfff7a000 0x00000910
9405 04:38:26.469038 VBOOT WORK 6. 0xfff66000 0x00014000
9406 04:38:26.472981 RAMOOPS 7. 0xffe66000 0x00100000
9407 04:38:26.475905 COREBOOT 8. 0xffe64000 0x00002000
9408 04:38:26.475985 IMD small region:
9409 04:38:26.479134 IMD ROOT 0. 0xffffec00 0x00000400
9410 04:38:26.483069 VPD 1. 0xffffeba0 0x0000004c
9411 04:38:26.485926 MMC STATUS 2. 0xffffeb80 0x00000004
9412 04:38:26.492475 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9413 04:38:26.495941 Probing TPM: done!
9414 04:38:26.499489 Connected to device vid:did:rid of 1ae0:0028:00
9415 04:38:26.509043 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9416 04:38:26.512682 Initialized TPM device CR50 revision 0
9417 04:38:26.516922 Checking cr50 for pending updates
9418 04:38:26.520263 Reading cr50 TPM mode
9419 04:38:26.528765 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9420 04:38:26.534735 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9421 04:38:26.575230 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9422 04:38:26.578357 Checking segment from ROM address 0x40100000
9423 04:38:26.581632 Checking segment from ROM address 0x4010001c
9424 04:38:26.588177 Loading segment from ROM address 0x40100000
9425 04:38:26.588260 code (compression=0)
9426 04:38:26.598286 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9427 04:38:26.605250 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9428 04:38:26.605331 it's not compressed!
9429 04:38:26.611546 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9430 04:38:26.614888 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9431 04:38:26.635312 Loading segment from ROM address 0x4010001c
9432 04:38:26.635420 Entry Point 0x80000000
9433 04:38:26.638597 Loaded segments
9434 04:38:26.642116 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9435 04:38:26.648972 Jumping to boot code at 0x80000000(0xffe64000)
9436 04:38:26.655395 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9437 04:38:26.662238 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9438 04:38:26.669851 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9439 04:38:26.672974 Checking segment from ROM address 0x40100000
9440 04:38:26.676855 Checking segment from ROM address 0x4010001c
9441 04:38:26.683196 Loading segment from ROM address 0x40100000
9442 04:38:26.683295 code (compression=1)
9443 04:38:26.689483 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9444 04:38:26.699696 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9445 04:38:26.699775 using LZMA
9446 04:38:26.707996 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9447 04:38:26.714972 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9448 04:38:26.718326 Loading segment from ROM address 0x4010001c
9449 04:38:26.718423 Entry Point 0x54601000
9450 04:38:26.721829 Loaded segments
9451 04:38:26.724612 NOTICE: MT8192 bl31_setup
9452 04:38:26.732147 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9453 04:38:26.734946 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9454 04:38:26.738506 WARNING: region 0:
9455 04:38:26.741894 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 04:38:26.741965 WARNING: region 1:
9457 04:38:26.748175 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9458 04:38:26.751741 WARNING: region 2:
9459 04:38:26.755093 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9460 04:38:26.758523 WARNING: region 3:
9461 04:38:26.761934 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 04:38:26.765399 WARNING: region 4:
9463 04:38:26.768816 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 04:38:26.772149 WARNING: region 5:
9465 04:38:26.775696 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 04:38:26.778621 WARNING: region 6:
9467 04:38:26.781919 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 04:38:26.782000 WARNING: region 7:
9469 04:38:26.788739 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 04:38:26.795457 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9471 04:38:26.798837 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9472 04:38:26.802047 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9473 04:38:26.805342 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9474 04:38:26.812143 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9475 04:38:26.815609 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9476 04:38:26.822452 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9477 04:38:26.825479 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9478 04:38:26.828780 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9479 04:38:26.835428 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9480 04:38:26.839404 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9481 04:38:26.842199 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9482 04:38:26.849296 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9483 04:38:26.852279 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9484 04:38:26.859308 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9485 04:38:26.862498 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9486 04:38:26.865950 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9487 04:38:26.872518 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9488 04:38:26.875950 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9489 04:38:26.878930 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9490 04:38:26.885637 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9491 04:38:26.889219 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9492 04:38:26.895859 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9493 04:38:26.898988 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9494 04:38:26.902369 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9495 04:38:26.909094 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9496 04:38:26.912514 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9497 04:38:26.915978 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9498 04:38:26.922563 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9499 04:38:26.925943 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9500 04:38:26.932606 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9501 04:38:26.935649 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9502 04:38:26.939444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9503 04:38:26.945981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9504 04:38:26.949074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9505 04:38:26.953001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9506 04:38:26.956262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9507 04:38:26.959661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9508 04:38:26.965893 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9509 04:38:26.969315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9510 04:38:26.972678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9511 04:38:26.976455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9512 04:38:26.982803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9513 04:38:26.986510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9514 04:38:26.989726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9515 04:38:26.993188 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9516 04:38:26.999562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9517 04:38:27.003062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9518 04:38:27.005909 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9519 04:38:27.012995 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9520 04:38:27.016418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9521 04:38:27.022818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9522 04:38:27.026279 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9523 04:38:27.029917 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9524 04:38:27.036224 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9525 04:38:27.039772 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9526 04:38:27.046614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9527 04:38:27.049520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9528 04:38:27.056315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9529 04:38:27.059919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9530 04:38:27.062794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9531 04:38:27.070257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9532 04:38:27.073187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9533 04:38:27.080193 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9534 04:38:27.083181 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9535 04:38:27.089873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9536 04:38:27.093080 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9537 04:38:27.096692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9538 04:38:27.103053 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9539 04:38:27.106645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9540 04:38:27.113199 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9541 04:38:27.116501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9542 04:38:27.123036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9543 04:38:27.126597 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9544 04:38:27.130134 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9545 04:38:27.136681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9546 04:38:27.139686 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9547 04:38:27.146555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9548 04:38:27.149891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9549 04:38:27.156510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9550 04:38:27.159757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9551 04:38:27.166794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9552 04:38:27.169669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9553 04:38:27.172978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9554 04:38:27.180124 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9555 04:38:27.183447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9556 04:38:27.190410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9557 04:38:27.193795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9558 04:38:27.196725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9559 04:38:27.203521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9560 04:38:27.206854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9561 04:38:27.213209 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9562 04:38:27.216626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9563 04:38:27.223295 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9564 04:38:27.227118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9565 04:38:27.230067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9566 04:38:27.236651 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9567 04:38:27.240112 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9568 04:38:27.243630 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9569 04:38:27.247495 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9570 04:38:27.253597 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9571 04:38:27.257122 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9572 04:38:27.260112 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9573 04:38:27.267057 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9574 04:38:27.270601 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9575 04:38:27.276943 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9576 04:38:27.280449 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9577 04:38:27.283426 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9578 04:38:27.290314 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9579 04:38:27.293806 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9580 04:38:27.300417 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9581 04:38:27.303714 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9582 04:38:27.307575 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9583 04:38:27.313908 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9584 04:38:27.317297 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9585 04:38:27.323659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9586 04:38:27.327090 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9587 04:38:27.330449 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9588 04:38:27.333559 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9589 04:38:27.340322 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9590 04:38:27.343712 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9591 04:38:27.346842 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9592 04:38:27.350817 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9593 04:38:27.357546 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9594 04:38:27.360303 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9595 04:38:27.363926 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9596 04:38:27.370570 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9597 04:38:27.373845 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9598 04:38:27.380855 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9599 04:38:27.383633 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9600 04:38:27.387221 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9601 04:38:27.394020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9602 04:38:27.397465 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9603 04:38:27.400907 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9604 04:38:27.407247 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9605 04:38:27.410698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9606 04:38:27.417893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9607 04:38:27.421247 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9608 04:38:27.424371 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9609 04:38:27.430836 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9610 04:38:27.434077 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9611 04:38:27.440938 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9612 04:38:27.443959 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9613 04:38:27.447435 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9614 04:38:27.453793 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9615 04:38:27.457656 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9616 04:38:27.460942 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9617 04:38:27.467355 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9618 04:38:27.470723 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9619 04:38:27.477709 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9620 04:38:27.480371 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9621 04:38:27.483668 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9622 04:38:27.490754 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9623 04:38:27.494355 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9624 04:38:27.500739 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9625 04:38:27.504201 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9626 04:38:27.507092 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9627 04:38:27.514292 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9628 04:38:27.517028 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9629 04:38:27.520501 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9630 04:38:27.527061 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9631 04:38:27.530808 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9632 04:38:27.537567 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9633 04:38:27.540239 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9634 04:38:27.543734 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9635 04:38:27.550720 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9636 04:38:27.553648 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9637 04:38:27.560615 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9638 04:38:27.563629 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9639 04:38:27.567112 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9640 04:38:27.573840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9641 04:38:27.577254 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9642 04:38:27.583463 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9643 04:38:27.587226 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9644 04:38:27.590112 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9645 04:38:27.596617 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9646 04:38:27.600373 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9647 04:38:27.606933 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9648 04:38:27.610324 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9649 04:38:27.613564 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9650 04:38:27.620148 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9651 04:38:27.623177 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9652 04:38:27.626646 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9653 04:38:27.633189 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9654 04:38:27.636983 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9655 04:38:27.643114 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9656 04:38:27.646528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9657 04:38:27.649822 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9658 04:38:27.656866 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9659 04:38:27.659804 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9660 04:38:27.666893 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9661 04:38:27.669734 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9662 04:38:27.676832 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9663 04:38:27.679867 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9664 04:38:27.683206 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9665 04:38:27.689886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9666 04:38:27.693291 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9667 04:38:27.699628 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9668 04:38:27.703121 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9669 04:38:27.710094 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9670 04:38:27.713102 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9671 04:38:27.716313 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9672 04:38:27.723250 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9673 04:38:27.726403 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9674 04:38:27.732640 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9675 04:38:27.736274 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9676 04:38:27.739397 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9677 04:38:27.746146 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9678 04:38:27.749708 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9679 04:38:27.756128 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9680 04:38:27.759759 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9681 04:38:27.762722 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9682 04:38:27.769640 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9683 04:38:27.772726 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9684 04:38:27.779783 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9685 04:38:27.782662 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9686 04:38:27.789574 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9687 04:38:27.792496 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9688 04:38:27.795892 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9689 04:38:27.802634 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9690 04:38:27.806096 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9691 04:38:27.812649 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9692 04:38:27.815997 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9693 04:38:27.819292 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9694 04:38:27.825627 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9695 04:38:27.829140 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9696 04:38:27.835836 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9697 04:38:27.839128 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9698 04:38:27.842507 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9699 04:38:27.849070 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9700 04:38:27.852227 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9701 04:38:27.855818 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9702 04:38:27.859096 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9703 04:38:27.865872 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9704 04:38:27.869544 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9705 04:38:27.872780 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9706 04:38:27.879188 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9707 04:38:27.882168 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9708 04:38:27.885710 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9709 04:38:27.892660 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9710 04:38:27.895719 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9711 04:38:27.902583 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9712 04:38:27.905464 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9713 04:38:27.908940 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9714 04:38:27.915458 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9715 04:38:27.918697 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9716 04:38:27.922220 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9717 04:38:27.929009 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9718 04:38:27.932590 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9719 04:38:27.935923 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9720 04:38:27.942194 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9721 04:38:27.945708 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9722 04:38:27.952058 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9723 04:38:27.955359 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9724 04:38:27.958358 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9725 04:38:27.965208 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9726 04:38:27.968352 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9727 04:38:27.975153 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9728 04:38:27.978578 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9729 04:38:27.981852 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9730 04:38:27.988829 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9731 04:38:27.991812 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9732 04:38:27.995121 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9733 04:38:28.001928 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9734 04:38:28.005174 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9735 04:38:28.008622 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9736 04:38:28.014839 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9737 04:38:28.018401 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9738 04:38:28.021848 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9739 04:38:28.028266 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9740 04:38:28.031708 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9741 04:38:28.034995 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9742 04:38:28.038510 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9743 04:38:28.041773 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9744 04:38:28.048297 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9745 04:38:28.051871 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9746 04:38:28.054731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9747 04:38:28.058299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9748 04:38:28.064780 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9749 04:38:28.068282 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9750 04:38:28.071596 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9751 04:38:28.078249 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9752 04:38:28.081918 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9753 04:38:28.084700 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9754 04:38:28.091992 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9755 04:38:28.094992 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9756 04:38:28.101632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9757 04:38:28.104771 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9758 04:38:28.111785 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9759 04:38:28.114662 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9760 04:38:28.117989 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9761 04:38:28.124988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9762 04:38:28.127843 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9763 04:38:28.134810 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9764 04:38:28.138146 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9765 04:38:28.141505 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9766 04:38:28.147893 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9767 04:38:28.151316 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9768 04:38:28.157693 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9769 04:38:28.161176 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9770 04:38:28.164647 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9771 04:38:28.170955 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9772 04:38:28.174647 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9773 04:38:28.181390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9774 04:38:28.184242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9775 04:38:28.188145 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9776 04:38:28.194433 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9777 04:38:28.197998 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9778 04:38:28.204429 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9779 04:38:28.208173 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9780 04:38:28.214592 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9781 04:38:28.217778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9782 04:38:28.220865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9783 04:38:28.227921 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9784 04:38:28.230866 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9785 04:38:28.234243 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9786 04:38:28.241057 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9787 04:38:28.244382 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9788 04:38:28.251345 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9789 04:38:28.254397 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9790 04:38:28.261251 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9791 04:38:28.264773 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9792 04:38:28.267642 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9793 04:38:28.274330 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9794 04:38:28.277653 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9795 04:38:28.284496 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9796 04:38:28.287792 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9797 04:38:28.290900 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9798 04:38:28.298043 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9799 04:38:28.301301 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9800 04:38:28.307553 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9801 04:38:28.311026 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9802 04:38:28.314307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9803 04:38:28.320801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9804 04:38:28.324089 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9805 04:38:28.330595 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9806 04:38:28.333936 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9807 04:38:28.337024 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9808 04:38:28.343698 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9809 04:38:28.347234 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9810 04:38:28.353915 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9811 04:38:28.357325 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9812 04:38:28.363985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9813 04:38:28.367437 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9814 04:38:28.370464 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9815 04:38:28.377240 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9816 04:38:28.380048 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9817 04:38:28.387027 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9818 04:38:28.390531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9819 04:38:28.393391 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9820 04:38:28.399930 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9821 04:38:28.403713 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9822 04:38:28.410206 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9823 04:38:28.413622 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9824 04:38:28.416504 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9825 04:38:28.423736 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9826 04:38:28.426852 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9827 04:38:28.433534 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9828 04:38:28.436522 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9829 04:38:28.443550 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9830 04:38:28.446807 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9831 04:38:28.453168 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9832 04:38:28.456549 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9833 04:38:28.460090 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9834 04:38:28.466555 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9835 04:38:28.470094 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9836 04:38:28.476848 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9837 04:38:28.479899 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9838 04:38:28.486762 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9839 04:38:28.489774 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9840 04:38:28.492994 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9841 04:38:28.499862 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9842 04:38:28.502817 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9843 04:38:28.509740 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9844 04:38:28.512799 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9845 04:38:28.519635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9846 04:38:28.523036 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9847 04:38:28.526478 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9848 04:38:28.532587 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9849 04:38:28.536310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9850 04:38:28.542618 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9851 04:38:28.546030 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9852 04:38:28.552939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9853 04:38:28.555954 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9854 04:38:28.562634 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9855 04:38:28.566087 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9856 04:38:28.569106 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9857 04:38:28.575768 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9858 04:38:28.579085 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9859 04:38:28.585720 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9860 04:38:28.589268 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9861 04:38:28.595786 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9862 04:38:28.599163 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9863 04:38:28.602299 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9864 04:38:28.609288 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9865 04:38:28.612098 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9866 04:38:28.619009 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9867 04:38:28.622369 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9868 04:38:28.629451 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9869 04:38:28.632130 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9870 04:38:28.638784 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9871 04:38:28.642449 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9872 04:38:28.645485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9873 04:38:28.652066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9874 04:38:28.655509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9875 04:38:28.662030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9876 04:38:28.665403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9877 04:38:28.672002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9878 04:38:28.675701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9879 04:38:28.682446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9880 04:38:28.685317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9881 04:38:28.688624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9882 04:38:28.695416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9883 04:38:28.698687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9884 04:38:28.705373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9885 04:38:28.708698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9886 04:38:28.715497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9887 04:38:28.718951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9888 04:38:28.725170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9889 04:38:28.728534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9890 04:38:28.735357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9891 04:38:28.738514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9892 04:38:28.745371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9893 04:38:28.749132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9894 04:38:28.755387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9895 04:38:28.758581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9896 04:38:28.765649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9897 04:38:28.768642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9898 04:38:28.775134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9899 04:38:28.778897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9900 04:38:28.785209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9901 04:38:28.788589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9902 04:38:28.795669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9903 04:38:28.798504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9904 04:38:28.802024 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9905 04:38:28.805579 INFO: [APUAPC] vio 0
9906 04:38:28.811780 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9907 04:38:28.815196 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9908 04:38:28.818455 INFO: [APUAPC] D0_APC_0: 0x400510
9909 04:38:28.821824 INFO: [APUAPC] D0_APC_1: 0x0
9910 04:38:28.825303 INFO: [APUAPC] D0_APC_2: 0x1540
9911 04:38:28.828904 INFO: [APUAPC] D0_APC_3: 0x0
9912 04:38:28.831760 INFO: [APUAPC] D1_APC_0: 0xffffffff
9913 04:38:28.835153 INFO: [APUAPC] D1_APC_1: 0xffffffff
9914 04:38:28.838804 INFO: [APUAPC] D1_APC_2: 0x3fffff
9915 04:38:28.841907 INFO: [APUAPC] D1_APC_3: 0x0
9916 04:38:28.845271 INFO: [APUAPC] D2_APC_0: 0xffffffff
9917 04:38:28.848310 INFO: [APUAPC] D2_APC_1: 0xffffffff
9918 04:38:28.851578 INFO: [APUAPC] D2_APC_2: 0x3fffff
9919 04:38:28.855065 INFO: [APUAPC] D2_APC_3: 0x0
9920 04:38:28.858783 INFO: [APUAPC] D3_APC_0: 0xffffffff
9921 04:38:28.861964 INFO: [APUAPC] D3_APC_1: 0xffffffff
9922 04:38:28.865182 INFO: [APUAPC] D3_APC_2: 0x3fffff
9923 04:38:28.865309 INFO: [APUAPC] D3_APC_3: 0x0
9924 04:38:28.871588 INFO: [APUAPC] D4_APC_0: 0xffffffff
9925 04:38:28.875077 INFO: [APUAPC] D4_APC_1: 0xffffffff
9926 04:38:28.878489 INFO: [APUAPC] D4_APC_2: 0x3fffff
9927 04:38:28.878570 INFO: [APUAPC] D4_APC_3: 0x0
9928 04:38:28.881747 INFO: [APUAPC] D5_APC_0: 0xffffffff
9929 04:38:28.885188 INFO: [APUAPC] D5_APC_1: 0xffffffff
9930 04:38:28.888288 INFO: [APUAPC] D5_APC_2: 0x3fffff
9931 04:38:28.891973 INFO: [APUAPC] D5_APC_3: 0x0
9932 04:38:28.894766 INFO: [APUAPC] D6_APC_0: 0xffffffff
9933 04:38:28.898055 INFO: [APUAPC] D6_APC_1: 0xffffffff
9934 04:38:28.901307 INFO: [APUAPC] D6_APC_2: 0x3fffff
9935 04:38:28.905111 INFO: [APUAPC] D6_APC_3: 0x0
9936 04:38:28.908003 INFO: [APUAPC] D7_APC_0: 0xffffffff
9937 04:38:28.911595 INFO: [APUAPC] D7_APC_1: 0xffffffff
9938 04:38:28.915227 INFO: [APUAPC] D7_APC_2: 0x3fffff
9939 04:38:28.917956 INFO: [APUAPC] D7_APC_3: 0x0
9940 04:38:28.921349 INFO: [APUAPC] D8_APC_0: 0xffffffff
9941 04:38:28.924919 INFO: [APUAPC] D8_APC_1: 0xffffffff
9942 04:38:28.928119 INFO: [APUAPC] D8_APC_2: 0x3fffff
9943 04:38:28.931175 INFO: [APUAPC] D8_APC_3: 0x0
9944 04:38:28.934531 INFO: [APUAPC] D9_APC_0: 0xffffffff
9945 04:38:28.938000 INFO: [APUAPC] D9_APC_1: 0xffffffff
9946 04:38:28.941446 INFO: [APUAPC] D9_APC_2: 0x3fffff
9947 04:38:28.944550 INFO: [APUAPC] D9_APC_3: 0x0
9948 04:38:28.947960 INFO: [APUAPC] D10_APC_0: 0xffffffff
9949 04:38:28.951281 INFO: [APUAPC] D10_APC_1: 0xffffffff
9950 04:38:28.954612 INFO: [APUAPC] D10_APC_2: 0x3fffff
9951 04:38:28.957972 INFO: [APUAPC] D10_APC_3: 0x0
9952 04:38:28.961208 INFO: [APUAPC] D11_APC_0: 0xffffffff
9953 04:38:28.964798 INFO: [APUAPC] D11_APC_1: 0xffffffff
9954 04:38:28.967755 INFO: [APUAPC] D11_APC_2: 0x3fffff
9955 04:38:28.971434 INFO: [APUAPC] D11_APC_3: 0x0
9956 04:38:28.974480 INFO: [APUAPC] D12_APC_0: 0xffffffff
9957 04:38:28.977988 INFO: [APUAPC] D12_APC_1: 0xffffffff
9958 04:38:28.981467 INFO: [APUAPC] D12_APC_2: 0x3fffff
9959 04:38:28.984388 INFO: [APUAPC] D12_APC_3: 0x0
9960 04:38:28.987752 INFO: [APUAPC] D13_APC_0: 0xffffffff
9961 04:38:28.991111 INFO: [APUAPC] D13_APC_1: 0xffffffff
9962 04:38:28.994402 INFO: [APUAPC] D13_APC_2: 0x3fffff
9963 04:38:28.997779 INFO: [APUAPC] D13_APC_3: 0x0
9964 04:38:29.001302 INFO: [APUAPC] D14_APC_0: 0xffffffff
9965 04:38:29.004751 INFO: [APUAPC] D14_APC_1: 0xffffffff
9966 04:38:29.008112 INFO: [APUAPC] D14_APC_2: 0x3fffff
9967 04:38:29.011132 INFO: [APUAPC] D14_APC_3: 0x0
9968 04:38:29.014596 INFO: [APUAPC] D15_APC_0: 0xffffffff
9969 04:38:29.017966 INFO: [APUAPC] D15_APC_1: 0xffffffff
9970 04:38:29.021418 INFO: [APUAPC] D15_APC_2: 0x3fffff
9971 04:38:29.024441 INFO: [APUAPC] D15_APC_3: 0x0
9972 04:38:29.027859 INFO: [APUAPC] APC_CON: 0x4
9973 04:38:29.031275 INFO: [NOCDAPC] D0_APC_0: 0x0
9974 04:38:29.034544 INFO: [NOCDAPC] D0_APC_1: 0x0
9975 04:38:29.037452 INFO: [NOCDAPC] D1_APC_0: 0x0
9976 04:38:29.041005 INFO: [NOCDAPC] D1_APC_1: 0xfff
9977 04:38:29.041075 INFO: [NOCDAPC] D2_APC_0: 0x0
9978 04:38:29.044327 INFO: [NOCDAPC] D2_APC_1: 0xfff
9979 04:38:29.047448 INFO: [NOCDAPC] D3_APC_0: 0x0
9980 04:38:29.051112 INFO: [NOCDAPC] D3_APC_1: 0xfff
9981 04:38:29.054217 INFO: [NOCDAPC] D4_APC_0: 0x0
9982 04:38:29.057868 INFO: [NOCDAPC] D4_APC_1: 0xfff
9983 04:38:29.061152 INFO: [NOCDAPC] D5_APC_0: 0x0
9984 04:38:29.064158 INFO: [NOCDAPC] D5_APC_1: 0xfff
9985 04:38:29.067803 INFO: [NOCDAPC] D6_APC_0: 0x0
9986 04:38:29.070923 INFO: [NOCDAPC] D6_APC_1: 0xfff
9987 04:38:29.070993 INFO: [NOCDAPC] D7_APC_0: 0x0
9988 04:38:29.074162 INFO: [NOCDAPC] D7_APC_1: 0xfff
9989 04:38:29.077555 INFO: [NOCDAPC] D8_APC_0: 0x0
9990 04:38:29.081135 INFO: [NOCDAPC] D8_APC_1: 0xfff
9991 04:38:29.083926 INFO: [NOCDAPC] D9_APC_0: 0x0
9992 04:38:29.087456 INFO: [NOCDAPC] D9_APC_1: 0xfff
9993 04:38:29.090986 INFO: [NOCDAPC] D10_APC_0: 0x0
9994 04:38:29.093775 INFO: [NOCDAPC] D10_APC_1: 0xfff
9995 04:38:29.097271 INFO: [NOCDAPC] D11_APC_0: 0x0
9996 04:38:29.100426 INFO: [NOCDAPC] D11_APC_1: 0xfff
9997 04:38:29.103768 INFO: [NOCDAPC] D12_APC_0: 0x0
9998 04:38:29.107400 INFO: [NOCDAPC] D12_APC_1: 0xfff
9999 04:38:29.110878 INFO: [NOCDAPC] D13_APC_0: 0x0
10000 04:38:29.113816 INFO: [NOCDAPC] D13_APC_1: 0xfff
10001 04:38:29.113890 INFO: [NOCDAPC] D14_APC_0: 0x0
10002 04:38:29.117412 INFO: [NOCDAPC] D14_APC_1: 0xfff
10003 04:38:29.120736 INFO: [NOCDAPC] D15_APC_0: 0x0
10004 04:38:29.124276 INFO: [NOCDAPC] D15_APC_1: 0xfff
10005 04:38:29.127174 INFO: [NOCDAPC] APC_CON: 0x4
10006 04:38:29.130848 INFO: [APUAPC] set_apusys_apc done
10007 04:38:29.133829 INFO: [DEVAPC] devapc_init done
10008 04:38:29.137117 INFO: GICv3 without legacy support detected.
10009 04:38:29.144023 INFO: ARM GICv3 driver initialized in EL3
10010 04:38:29.147086 INFO: Maximum SPI INTID supported: 639
10011 04:38:29.150482 INFO: BL31: Initializing runtime services
10012 04:38:29.157214 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10013 04:38:29.157296 INFO: SPM: enable CPC mode
10014 04:38:29.163626 INFO: mcdi ready for mcusys-off-idle and system suspend
10015 04:38:29.166932 INFO: BL31: Preparing for EL3 exit to normal world
10016 04:38:29.173871 INFO: Entry point address = 0x80000000
10017 04:38:29.173953 INFO: SPSR = 0x8
10018 04:38:29.179966
10019 04:38:29.180046
10020 04:38:29.180109
10021 04:38:29.180775 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10022 04:38:29.180873 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10023 04:38:29.180953 Setting prompt string to ['asurada:']
10024 04:38:29.181028 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10025 04:38:29.183194 Starting depthcharge on Spherion...
10026 04:38:29.183274
10027 04:38:29.183337 Wipe memory regions:
10028 04:38:29.183397
10029 04:38:29.186332 [0x00000040000000, 0x00000054600000)
10030 04:38:29.308810
10031 04:38:29.308933 [0x00000054660000, 0x00000080000000)
10032 04:38:29.569018
10033 04:38:29.569167 [0x000000821a7280, 0x000000ffe64000)
10034 04:38:30.312742
10035 04:38:30.312888 [0x00000100000000, 0x00000240000000)
10036 04:38:32.199181
10037 04:38:32.201960 Initializing XHCI USB controller at 0x11200000.
10038 04:38:33.240921
10039 04:38:33.244483 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10040 04:38:33.244915
10041 04:38:33.245248
10042 04:38:33.245557
10043 04:38:33.246283 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 04:38:33.347277 asurada: tftpboot 192.168.201.1 11241309/tftp-deploy-z0d2ds2g/kernel/image.itb 11241309/tftp-deploy-z0d2ds2g/kernel/cmdline
10046 04:38:33.347729 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 04:38:33.347956 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10048 04:38:33.353037 tftpboot 192.168.201.1 11241309/tftp-deploy-z0d2ds2g/kernel/image.ittp-deploy-z0d2ds2g/kernel/cmdline
10049 04:38:33.353340
10050 04:38:33.353573 Waiting for link
10051 04:38:33.511397
10052 04:38:33.511991 R8152: Initializing
10053 04:38:33.512417
10054 04:38:33.514055 Version 9 (ocp_data = 6010)
10055 04:38:33.514474
10056 04:38:33.517471 R8152: Done initializing
10057 04:38:33.517892
10058 04:38:33.518219 Adding net device
10059 04:38:35.462358
10060 04:38:35.462950 done.
10061 04:38:35.463388
10062 04:38:35.463933 MAC: 00:e0:4c:78:7a:aa
10063 04:38:35.464253
10064 04:38:35.465748 Sending DHCP discover... done.
10065 04:38:35.466240
10066 04:38:39.397051 Waiting for reply... done.
10067 04:38:39.397625
10068 04:38:39.397995 Sending DHCP request... done.
10069 04:38:39.400343
10070 04:38:39.400795 Waiting for reply... done.
10071 04:38:39.401150
10072 04:38:39.403811 My ip is 192.168.201.12
10073 04:38:39.404257
10074 04:38:39.406864 The DHCP server ip is 192.168.201.1
10075 04:38:39.407318
10076 04:38:39.410448 TFTP server IP predefined by user: 192.168.201.1
10077 04:38:39.411005
10078 04:38:39.417236 Bootfile predefined by user: 11241309/tftp-deploy-z0d2ds2g/kernel/image.itb
10079 04:38:39.417703
10080 04:38:39.420073 Sending tftp read request... done.
10081 04:38:39.420526
10082 04:38:39.428158 Waiting for the transfer...
10083 04:38:39.428614
10084 04:38:39.748154 00000000 ################################################################
10085 04:38:39.748301
10086 04:38:40.040412 00080000 ################################################################
10087 04:38:40.040558
10088 04:38:40.338726 00100000 ################################################################
10089 04:38:40.338870
10090 04:38:40.638480 00180000 ################################################################
10091 04:38:40.638617
10092 04:38:40.938188 00200000 ################################################################
10093 04:38:40.938333
10094 04:38:41.214980 00280000 ################################################################
10095 04:38:41.215121
10096 04:38:41.466775 00300000 ################################################################
10097 04:38:41.466919
10098 04:38:41.733509 00380000 ################################################################
10099 04:38:41.733646
10100 04:38:42.012955 00400000 ################################################################
10101 04:38:42.013092
10102 04:38:42.277501 00480000 ################################################################
10103 04:38:42.277652
10104 04:38:42.540559 00500000 ################################################################
10105 04:38:42.540737
10106 04:38:42.811253 00580000 ################################################################
10107 04:38:42.811450
10108 04:38:43.074921 00600000 ################################################################
10109 04:38:43.075102
10110 04:38:43.340911 00680000 ################################################################
10111 04:38:43.341056
10112 04:38:43.611489 00700000 ################################################################
10113 04:38:43.611663
10114 04:38:43.875872 00780000 ################################################################
10115 04:38:43.876070
10116 04:38:44.134945 00800000 ################################################################
10117 04:38:44.135148
10118 04:38:44.394348 00880000 ################################################################
10119 04:38:44.394526
10120 04:38:44.651236 00900000 ################################################################
10121 04:38:44.651426
10122 04:38:44.907241 00980000 ################################################################
10123 04:38:44.907429
10124 04:38:45.155508 00a00000 ################################################################
10125 04:38:45.155688
10126 04:38:45.409212 00a80000 ################################################################
10127 04:38:45.409398
10128 04:38:45.664002 00b00000 ################################################################
10129 04:38:45.664268
10130 04:38:45.917381 00b80000 ################################################################
10131 04:38:45.917535
10132 04:38:46.195439 00c00000 ################################################################
10133 04:38:46.195608
10134 04:38:46.464774 00c80000 ################################################################
10135 04:38:46.464925
10136 04:38:46.723324 00d00000 ################################################################
10137 04:38:46.723506
10138 04:38:46.984318 00d80000 ################################################################
10139 04:38:46.984492
10140 04:38:47.252294 00e00000 ################################################################
10141 04:38:47.252445
10142 04:38:47.535297 00e80000 ################################################################
10143 04:38:47.535443
10144 04:38:47.809314 00f00000 ################################################################
10145 04:38:47.809489
10146 04:38:48.057734 00f80000 ################################################################
10147 04:38:48.057909
10148 04:38:48.312237 01000000 ################################################################
10149 04:38:48.312383
10150 04:38:48.578908 01080000 ################################################################
10151 04:38:48.579093
10152 04:38:48.833623 01100000 ################################################################
10153 04:38:48.833769
10154 04:38:49.088549 01180000 ################################################################
10155 04:38:49.088746
10156 04:38:49.340106 01200000 ################################################################
10157 04:38:49.340285
10158 04:38:49.590069 01280000 ################################################################
10159 04:38:49.590274
10160 04:38:49.853672 01300000 ################################################################
10161 04:38:49.853872
10162 04:38:50.105845 01380000 ################################################################
10163 04:38:50.105993
10164 04:38:50.353924 01400000 ################################################################
10165 04:38:50.354075
10166 04:38:50.598016 01480000 ################################################################
10167 04:38:50.598164
10168 04:38:50.857770 01500000 ################################################################
10169 04:38:50.857928
10170 04:38:51.130662 01580000 ################################################################
10171 04:38:51.130811
10172 04:38:51.417732 01600000 ################################################################
10173 04:38:51.417873
10174 04:38:51.692436 01680000 ################################################################
10175 04:38:51.692580
10176 04:38:51.984085 01700000 ################################################################
10177 04:38:51.984234
10178 04:38:52.267194 01780000 ################################################################
10179 04:38:52.267339
10180 04:38:52.536436 01800000 ################################################################
10181 04:38:52.536584
10182 04:38:52.805412 01880000 ################################################################
10183 04:38:52.805565
10184 04:38:53.082753 01900000 ################################################################
10185 04:38:53.082900
10186 04:38:53.345731 01980000 ################################################################
10187 04:38:53.345868
10188 04:38:53.605463 01a00000 ################################################################
10189 04:38:53.605616
10190 04:38:53.864849 01a80000 ################################################################
10191 04:38:53.864999
10192 04:38:54.134690 01b00000 ################################################################
10193 04:38:54.134852
10194 04:38:54.396683 01b80000 ################################################################
10195 04:38:54.396832
10196 04:38:54.649256 01c00000 ################################################################
10197 04:38:54.649446
10198 04:38:54.914508 01c80000 ################################################################
10199 04:38:54.914682
10200 04:38:55.176790 01d00000 ################################################################
10201 04:38:55.176942
10202 04:38:55.426514 01d80000 ################################################################
10203 04:38:55.426666
10204 04:38:55.682406 01e00000 ################################################################
10205 04:38:55.682553
10206 04:38:55.931997 01e80000 ################################################################
10207 04:38:55.932170
10208 04:38:56.189596 01f00000 ################################################################
10209 04:38:56.189739
10210 04:38:56.443378 01f80000 ################################################################
10211 04:38:56.443539
10212 04:38:56.701354 02000000 ################################################################
10213 04:38:56.701530
10214 04:38:56.952177 02080000 ################################################################
10215 04:38:56.952373
10216 04:38:57.200720 02100000 ################################################################
10217 04:38:57.200912
10218 04:38:57.466213 02180000 ################################################################
10219 04:38:57.466366
10220 04:38:57.750834 02200000 ################################################################
10221 04:38:57.750985
10222 04:38:58.039336 02280000 ################################################################
10223 04:38:58.039501
10224 04:38:58.306341 02300000 ################################################################
10225 04:38:58.306522
10226 04:38:58.559610 02380000 ################################################################
10227 04:38:58.559753
10228 04:38:58.807583 02400000 ################################################################
10229 04:38:58.807724
10230 04:38:59.066981 02480000 ################################################################
10231 04:38:59.067128
10232 04:38:59.330865 02500000 ################################################################
10233 04:38:59.331009
10234 04:38:59.582469 02580000 ################################################################
10235 04:38:59.582610
10236 04:38:59.836280 02600000 ################################################################
10237 04:38:59.836413
10238 04:39:00.096451 02680000 ################################################################
10239 04:39:00.096587
10240 04:39:00.358447 02700000 ################################################################
10241 04:39:00.358575
10242 04:39:00.619544 02780000 ################################################################
10243 04:39:00.619686
10244 04:39:00.885678 02800000 ################################################################
10245 04:39:00.885808
10246 04:39:01.150228 02880000 ################################################################
10247 04:39:01.150363
10248 04:39:01.409932 02900000 ################################################################
10249 04:39:01.410089
10250 04:39:01.661854 02980000 ################################################################
10251 04:39:01.661989
10252 04:39:01.915490 02a00000 ################################################################
10253 04:39:01.915661
10254 04:39:02.186411 02a80000 ################################################################
10255 04:39:02.186547
10256 04:39:02.453700 02b00000 ################################################################
10257 04:39:02.453835
10258 04:39:02.706503 02b80000 ################################################################
10259 04:39:02.706634
10260 04:39:02.959095 02c00000 ################################################################
10261 04:39:02.959230
10262 04:39:03.225733 02c80000 ################################################################
10263 04:39:03.225868
10264 04:39:03.481109 02d00000 ################################################################
10265 04:39:03.481241
10266 04:39:03.734147 02d80000 ################################################################
10267 04:39:03.734278
10268 04:39:03.986106 02e00000 ################################################################
10269 04:39:03.986252
10270 04:39:04.233616 02e80000 ################################################################
10271 04:39:04.233787
10272 04:39:04.495789 02f00000 ################################################################
10273 04:39:04.495922
10274 04:39:04.748152 02f80000 ################################################################
10275 04:39:04.748287
10276 04:39:04.997352 03000000 ################################################################
10277 04:39:04.997489
10278 04:39:05.258198 03080000 ################################################################
10279 04:39:05.258361
10280 04:39:05.510182 03100000 ################################################################
10281 04:39:05.510320
10282 04:39:05.770291 03180000 ################################################################
10283 04:39:05.770431
10284 04:39:06.025330 03200000 ################################################################
10285 04:39:06.025482
10286 04:39:06.282101 03280000 ################################################################
10287 04:39:06.282238
10288 04:39:06.545529 03300000 ################################################################
10289 04:39:06.545675
10290 04:39:06.826802 03380000 ################################################################
10291 04:39:06.826974
10292 04:39:07.102740 03400000 ################################################################
10293 04:39:07.102872
10294 04:39:07.359139 03480000 ################################################################
10295 04:39:07.359274
10296 04:39:07.606864 03500000 ################################################################
10297 04:39:07.606997
10298 04:39:07.855786 03580000 ################################################################
10299 04:39:07.855958
10300 04:39:08.106145 03600000 ################################################################
10301 04:39:08.106294
10302 04:39:08.373288 03680000 ################################################################
10303 04:39:08.373459
10304 04:39:08.619791 03700000 ################################################################
10305 04:39:08.619928
10306 04:39:08.763614 03780000 ##################################### done.
10307 04:39:08.763805
10308 04:39:08.767209 The bootfile was 58494906 bytes long.
10309 04:39:08.767309
10310 04:39:08.770363 Sending tftp read request... done.
10311 04:39:08.770446
10312 04:39:08.773397 Waiting for the transfer...
10313 04:39:08.773480
10314 04:39:08.773543 00000000 # done.
10315 04:39:08.773604
10316 04:39:08.783839 Command line loaded dynamically from TFTP file: 11241309/tftp-deploy-z0d2ds2g/kernel/cmdline
10317 04:39:08.783934
10318 04:39:08.796659 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10319 04:39:08.796755
10320 04:39:08.796819 Loading FIT.
10321 04:39:08.796879
10322 04:39:08.800187 Image ramdisk-1 has 47409225 bytes.
10323 04:39:08.800270
10324 04:39:08.803684 Image fdt-1 has 47278 bytes.
10325 04:39:08.803765
10326 04:39:08.807053 Image kernel-1 has 11036366 bytes.
10327 04:39:08.807134
10328 04:39:08.817060 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10329 04:39:08.817218
10330 04:39:08.833763 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10331 04:39:08.833928
10332 04:39:08.837080 Choosing best match conf-1 for compat google,spherion-rev2.
10333 04:39:08.842621
10334 04:39:08.847591 Connected to device vid:did:rid of 1ae0:0028:00
10335 04:39:08.855290
10336 04:39:08.858587 tpm_get_response: command 0x17b, return code 0x0
10337 04:39:08.858748
10338 04:39:08.862161 ec_init: CrosEC protocol v3 supported (256, 248)
10339 04:39:08.865804
10340 04:39:08.869376 tpm_cleanup: add release locality here.
10341 04:39:08.869516
10342 04:39:08.869606 Shutting down all USB controllers.
10343 04:39:08.872427
10344 04:39:08.872571 Removing current net device
10345 04:39:08.872669
10346 04:39:08.879442 Exiting depthcharge with code 4 at timestamp: 69004220
10347 04:39:08.879672
10348 04:39:08.882748 LZMA decompressing kernel-1 to 0x821a6718
10349 04:39:08.883254
10350 04:39:08.885768 LZMA decompressing kernel-1 to 0x40000000
10351 04:39:10.275226
10352 04:39:10.275725 jumping to kernel
10353 04:39:10.277160 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10354 04:39:10.277636 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10355 04:39:10.278002 Setting prompt string to ['Linux version [0-9]']
10356 04:39:10.278334 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10357 04:39:10.278684 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10358 04:39:10.356646
10359 04:39:10.359932 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10360 04:39:10.363589 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10361 04:39:10.364155 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10362 04:39:10.364578 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10363 04:39:10.364945 Using line separator: #'\n'#
10364 04:39:10.365245 No login prompt set.
10365 04:39:10.365554 Parsing kernel messages
10366 04:39:10.365831 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10367 04:39:10.366332 [login-action] Waiting for messages, (timeout 00:03:44)
10368 04:39:10.382784 [ 0.000000] Linux version 6.1.42-cip2 (KernelCI@build-j7071-arm64-gcc-10-defconfig-arm64-chromebook-7p24g) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 9 04:18:34 UTC 2023
10369 04:39:10.386238 [ 0.000000] random: crng init done
10370 04:39:10.389652 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10371 04:39:10.393249 [ 0.000000] efi: UEFI not found.
10372 04:39:10.402617 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10373 04:39:10.409255 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10374 04:39:10.419654 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10375 04:39:10.429641 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10376 04:39:10.436103 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10377 04:39:10.439275 [ 0.000000] printk: bootconsole [mtk8250] enabled
10378 04:39:10.448247 [ 0.000000] NUMA: No NUMA configuration found
10379 04:39:10.454930 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10380 04:39:10.461091 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10381 04:39:10.461528 [ 0.000000] Zone ranges:
10382 04:39:10.467729 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10383 04:39:10.471332 [ 0.000000] DMA32 empty
10384 04:39:10.478041 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10385 04:39:10.481127 [ 0.000000] Movable zone start for each node
10386 04:39:10.484523 [ 0.000000] Early memory node ranges
10387 04:39:10.491443 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10388 04:39:10.498063 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10389 04:39:10.504772 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10390 04:39:10.511862 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10391 04:39:10.518019 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10392 04:39:10.524428 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10393 04:39:10.580617 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10394 04:39:10.587050 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10395 04:39:10.593509 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10396 04:39:10.597238 [ 0.000000] psci: probing for conduit method from DT.
10397 04:39:10.604034 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10398 04:39:10.606930 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10399 04:39:10.613459 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10400 04:39:10.617333 [ 0.000000] psci: SMC Calling Convention v1.2
10401 04:39:10.623329 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10402 04:39:10.626967 [ 0.000000] Detected VIPT I-cache on CPU0
10403 04:39:10.633255 [ 0.000000] CPU features: detected: GIC system register CPU interface
10404 04:39:10.640420 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10405 04:39:10.646620 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10406 04:39:10.653387 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10407 04:39:10.662887 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10408 04:39:10.669937 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10409 04:39:10.673178 [ 0.000000] alternatives: applying boot alternatives
10410 04:39:10.680015 [ 0.000000] Fallback order for Node 0: 0
10411 04:39:10.686497 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10412 04:39:10.689679 [ 0.000000] Policy zone: Normal
10413 04:39:10.702775 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10414 04:39:10.712761 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10415 04:39:10.723819 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10416 04:39:10.734025 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10417 04:39:10.740648 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10418 04:39:10.743756 <6>[ 0.000000] software IO TLB: area num 8.
10419 04:39:10.799785 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10420 04:39:10.949078 <6>[ 0.000000] Memory: 7923260K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 429508K reserved, 32768K cma-reserved)
10421 04:39:10.955869 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10422 04:39:10.962364 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10423 04:39:10.965500 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10424 04:39:10.972649 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10425 04:39:10.978636 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10426 04:39:10.982716 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10427 04:39:10.992513 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10428 04:39:10.998678 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10429 04:39:11.002657 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10430 04:39:11.010118 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10431 04:39:11.013920 <6>[ 0.000000] GICv3: 608 SPIs implemented
10432 04:39:11.020099 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10433 04:39:11.024020 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10434 04:39:11.026741 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10435 04:39:11.037062 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10436 04:39:11.046801 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10437 04:39:11.060210 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10438 04:39:11.067077 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10439 04:39:11.076171 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10440 04:39:11.089292 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10441 04:39:11.095651 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10442 04:39:11.102775 <6>[ 0.009180] Console: colour dummy device 80x25
10443 04:39:11.112489 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10444 04:39:11.118875 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10445 04:39:11.122539 <6>[ 0.029213] LSM: Security Framework initializing
10446 04:39:11.129002 <6>[ 0.034153] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10447 04:39:11.138919 <6>[ 0.041967] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10448 04:39:11.146117 <6>[ 0.051395] cblist_init_generic: Setting adjustable number of callback queues.
10449 04:39:11.152394 <6>[ 0.058841] cblist_init_generic: Setting shift to 3 and lim to 1.
10450 04:39:11.163018 <6>[ 0.065178] cblist_init_generic: Setting adjustable number of callback queues.
10451 04:39:11.166069 <6>[ 0.072650] cblist_init_generic: Setting shift to 3 and lim to 1.
10452 04:39:11.172528 <6>[ 0.079089] rcu: Hierarchical SRCU implementation.
10453 04:39:11.179489 <6>[ 0.084103] rcu: Max phase no-delay instances is 1000.
10454 04:39:11.185504 <6>[ 0.091135] EFI services will not be available.
10455 04:39:11.189035 <6>[ 0.096088] smp: Bringing up secondary CPUs ...
10456 04:39:11.197059 <6>[ 0.101139] Detected VIPT I-cache on CPU1
10457 04:39:11.203619 <6>[ 0.101209] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10458 04:39:11.210062 <6>[ 0.101238] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10459 04:39:11.213405 <6>[ 0.101578] Detected VIPT I-cache on CPU2
10460 04:39:11.223598 <6>[ 0.101631] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10461 04:39:11.230255 <6>[ 0.101649] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10462 04:39:11.233255 <6>[ 0.101908] Detected VIPT I-cache on CPU3
10463 04:39:11.239725 <6>[ 0.101956] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10464 04:39:11.246374 <6>[ 0.101970] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10465 04:39:11.249743 <6>[ 0.102273] CPU features: detected: Spectre-v4
10466 04:39:11.256645 <6>[ 0.102280] CPU features: detected: Spectre-BHB
10467 04:39:11.259615 <6>[ 0.102286] Detected PIPT I-cache on CPU4
10468 04:39:11.266193 <6>[ 0.102343] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10469 04:39:11.273069 <6>[ 0.102359] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10470 04:39:11.279499 <6>[ 0.102649] Detected PIPT I-cache on CPU5
10471 04:39:11.286262 <6>[ 0.102712] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10472 04:39:11.292994 <6>[ 0.102728] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10473 04:39:11.296222 <6>[ 0.103009] Detected PIPT I-cache on CPU6
10474 04:39:11.302864 <6>[ 0.103073] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10475 04:39:11.309410 <6>[ 0.103089] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10476 04:39:11.315924 <6>[ 0.103385] Detected PIPT I-cache on CPU7
10477 04:39:11.322513 <6>[ 0.103450] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10478 04:39:11.329312 <6>[ 0.103466] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10479 04:39:11.332465 <6>[ 0.103514] smp: Brought up 1 node, 8 CPUs
10480 04:39:11.338620 <6>[ 0.244907] SMP: Total of 8 processors activated.
10481 04:39:11.342316 <6>[ 0.249859] CPU features: detected: 32-bit EL0 Support
10482 04:39:11.352027 <6>[ 0.255254] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10483 04:39:11.358870 <6>[ 0.264097] CPU features: detected: Common not Private translations
10484 04:39:11.365761 <6>[ 0.270573] CPU features: detected: CRC32 instructions
10485 04:39:11.368631 <6>[ 0.275924] CPU features: detected: RCpc load-acquire (LDAPR)
10486 04:39:11.375179 <6>[ 0.281920] CPU features: detected: LSE atomic instructions
10487 04:39:11.382111 <6>[ 0.287701] CPU features: detected: Privileged Access Never
10488 04:39:11.388769 <6>[ 0.293517] CPU features: detected: RAS Extension Support
10489 04:39:11.395414 <6>[ 0.299125] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10490 04:39:11.398541 <6>[ 0.306347] CPU: All CPU(s) started at EL2
10491 04:39:11.405320 <6>[ 0.310664] alternatives: applying system-wide alternatives
10492 04:39:11.414571 <6>[ 0.321362] devtmpfs: initialized
10493 04:39:11.426317 <6>[ 0.330227] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10494 04:39:11.436710 <6>[ 0.340189] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10495 04:39:11.440007 <6>[ 0.347782] pinctrl core: initialized pinctrl subsystem
10496 04:39:11.448022 <6>[ 0.354429] DMI not present or invalid.
10497 04:39:11.454537 <6>[ 0.358836] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10498 04:39:11.461013 <6>[ 0.365688] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10499 04:39:11.471004 <6>[ 0.373274] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10500 04:39:11.477312 <6>[ 0.381483] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10501 04:39:11.483923 <6>[ 0.389724] audit: initializing netlink subsys (disabled)
10502 04:39:11.491127 <5>[ 0.395416] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10503 04:39:11.497285 <6>[ 0.396122] thermal_sys: Registered thermal governor 'step_wise'
10504 04:39:11.504040 <6>[ 0.403382] thermal_sys: Registered thermal governor 'power_allocator'
10505 04:39:11.507699 <6>[ 0.409637] cpuidle: using governor menu
10506 04:39:11.514243 <6>[ 0.420599] NET: Registered PF_QIPCRTR protocol family
10507 04:39:11.521215 <6>[ 0.426081] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10508 04:39:11.527208 <6>[ 0.433184] ASID allocator initialised with 32768 entries
10509 04:39:11.530648 <6>[ 0.439747] Serial: AMBA PL011 UART driver
10510 04:39:11.541733 <4>[ 0.448478] Trying to register duplicate clock ID: 134
10511 04:39:11.595593 <6>[ 0.506207] KASLR enabled
10512 04:39:11.610051 <6>[ 0.513938] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10513 04:39:11.616787 <6>[ 0.520952] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10514 04:39:11.623372 <6>[ 0.527441] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10515 04:39:11.629967 <6>[ 0.534448] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10516 04:39:11.636689 <6>[ 0.540937] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10517 04:39:11.643163 <6>[ 0.547941] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10518 04:39:11.650257 <6>[ 0.554425] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10519 04:39:11.656459 <6>[ 0.561434] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10520 04:39:11.659697 <6>[ 0.568936] ACPI: Interpreter disabled.
10521 04:39:11.668481 <6>[ 0.575342] iommu: Default domain type: Translated
10522 04:39:11.675171 <6>[ 0.580453] iommu: DMA domain TLB invalidation policy: strict mode
10523 04:39:11.678484 <5>[ 0.587105] SCSI subsystem initialized
10524 04:39:11.684991 <6>[ 0.591280] usbcore: registered new interface driver usbfs
10525 04:39:11.691355 <6>[ 0.597012] usbcore: registered new interface driver hub
10526 04:39:11.694360 <6>[ 0.602564] usbcore: registered new device driver usb
10527 04:39:11.701434 <6>[ 0.608657] pps_core: LinuxPPS API ver. 1 registered
10528 04:39:11.711667 <6>[ 0.613848] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10529 04:39:11.714651 <6>[ 0.623195] PTP clock support registered
10530 04:39:11.717734 <6>[ 0.627438] EDAC MC: Ver: 3.0.0
10531 04:39:11.725407 <6>[ 0.632576] FPGA manager framework
10532 04:39:11.728887 <6>[ 0.636256] Advanced Linux Sound Architecture Driver Initialized.
10533 04:39:11.732554 <6>[ 0.643033] vgaarb: loaded
10534 04:39:11.739259 <6>[ 0.646209] clocksource: Switched to clocksource arch_sys_counter
10535 04:39:11.746034 <5>[ 0.652645] VFS: Disk quotas dquot_6.6.0
10536 04:39:11.752718 <6>[ 0.656829] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10537 04:39:11.755758 <6>[ 0.664015] pnp: PnP ACPI: disabled
10538 04:39:11.763358 <6>[ 0.670749] NET: Registered PF_INET protocol family
10539 04:39:11.773681 <6>[ 0.676347] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10540 04:39:11.784672 <6>[ 0.688652] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10541 04:39:11.794586 <6>[ 0.697467] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10542 04:39:11.801648 <6>[ 0.705438] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10543 04:39:11.808085 <6>[ 0.714140] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10544 04:39:11.819857 <6>[ 0.723882] TCP: Hash tables configured (established 65536 bind 65536)
10545 04:39:11.826691 <6>[ 0.730741] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10546 04:39:11.833794 <6>[ 0.737936] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10547 04:39:11.839829 <6>[ 0.745638] NET: Registered PF_UNIX/PF_LOCAL protocol family
10548 04:39:11.846540 <6>[ 0.751804] RPC: Registered named UNIX socket transport module.
10549 04:39:11.849587 <6>[ 0.757957] RPC: Registered udp transport module.
10550 04:39:11.856844 <6>[ 0.762889] RPC: Registered tcp transport module.
10551 04:39:11.863038 <6>[ 0.767819] RPC: Registered tcp NFSv4.1 backchannel transport module.
10552 04:39:11.866374 <6>[ 0.774485] PCI: CLS 0 bytes, default 64
10553 04:39:11.869933 <6>[ 0.778875] Unpacking initramfs...
10554 04:39:11.894570 <6>[ 0.798316] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10555 04:39:11.904071 <6>[ 0.806976] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10556 04:39:11.907711 <6>[ 0.815825] kvm [1]: IPA Size Limit: 40 bits
10557 04:39:11.914223 <6>[ 0.820355] kvm [1]: GICv3: no GICV resource entry
10558 04:39:11.917208 <6>[ 0.825375] kvm [1]: disabling GICv2 emulation
10559 04:39:11.923810 <6>[ 0.830064] kvm [1]: GIC system register CPU interface enabled
10560 04:39:11.927308 <6>[ 0.836243] kvm [1]: vgic interrupt IRQ18
10561 04:39:11.934087 <6>[ 0.840595] kvm [1]: VHE mode initialized successfully
10562 04:39:11.940457 <5>[ 0.847003] Initialise system trusted keyrings
10563 04:39:11.947095 <6>[ 0.851817] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10564 04:39:11.954352 <6>[ 0.861759] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10565 04:39:11.960960 <5>[ 0.868205] NFS: Registering the id_resolver key type
10566 04:39:11.964671 <5>[ 0.873518] Key type id_resolver registered
10567 04:39:11.971013 <5>[ 0.877934] Key type id_legacy registered
10568 04:39:11.977583 <6>[ 0.882220] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10569 04:39:11.984455 <6>[ 0.889140] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10570 04:39:11.990964 <6>[ 0.896852] 9p: Installing v9fs 9p2000 file system support
10571 04:39:12.028312 <5>[ 0.935125] Key type asymmetric registered
10572 04:39:12.031428 <5>[ 0.939456] Asymmetric key parser 'x509' registered
10573 04:39:12.041220 <6>[ 0.944601] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10574 04:39:12.044387 <6>[ 0.952237] io scheduler mq-deadline registered
10575 04:39:12.048036 <6>[ 0.956999] io scheduler kyber registered
10576 04:39:12.067403 <6>[ 0.974008] EINJ: ACPI disabled.
10577 04:39:12.099379 <4>[ 0.999424] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 04:39:12.108975 <4>[ 1.010047] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 04:39:12.123421 <6>[ 1.030812] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10580 04:39:12.131892 <6>[ 1.038866] printk: console [ttyS0] disabled
10581 04:39:12.159801 <6>[ 1.063517] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10582 04:39:12.166078 <6>[ 1.072992] printk: console [ttyS0] enabled
10583 04:39:12.169631 <6>[ 1.072992] printk: console [ttyS0] enabled
10584 04:39:12.176199 <6>[ 1.081886] printk: bootconsole [mtk8250] disabled
10585 04:39:12.179837 <6>[ 1.081886] printk: bootconsole [mtk8250] disabled
10586 04:39:12.186549 <6>[ 1.093277] SuperH (H)SCI(F) driver initialized
10587 04:39:12.189617 <6>[ 1.098582] msm_serial: driver initialized
10588 04:39:12.203947 <6>[ 1.107651] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10589 04:39:12.213651 <6>[ 1.116204] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10590 04:39:12.220419 <6>[ 1.124746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10591 04:39:12.230323 <6>[ 1.133377] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10592 04:39:12.236963 <6>[ 1.142086] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10593 04:39:12.246950 <6>[ 1.150801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10594 04:39:12.257112 <6>[ 1.159342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10595 04:39:12.263442 <6>[ 1.168152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10596 04:39:12.273560 <6>[ 1.176710] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10597 04:39:12.285235 <6>[ 1.192400] loop: module loaded
10598 04:39:12.291946 <6>[ 1.198375] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10599 04:39:12.314239 <4>[ 1.221717] mtk-pmic-keys: Failed to locate of_node [id: -1]
10600 04:39:12.321538 <6>[ 1.228719] megasas: 07.719.03.00-rc1
10601 04:39:12.331067 <6>[ 1.238350] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10602 04:39:12.338754 <6>[ 1.245592] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10603 04:39:12.354944 <6>[ 1.262142] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10604 04:39:12.412561 <6>[ 1.312475] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10605 04:39:13.842997 <6>[ 2.750634] Freeing initrd memory: 46292K
10606 04:39:13.853807 <6>[ 2.761039] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10607 04:39:13.864941 <6>[ 2.772217] tun: Universal TUN/TAP device driver, 1.6
10608 04:39:13.868568 <6>[ 2.778285] thunder_xcv, ver 1.0
10609 04:39:13.871526 <6>[ 2.781781] thunder_bgx, ver 1.0
10610 04:39:13.875114 <6>[ 2.785279] nicpf, ver 1.0
10611 04:39:13.885011 <6>[ 2.789307] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10612 04:39:13.888696 <6>[ 2.796783] hns3: Copyright (c) 2017 Huawei Corporation.
10613 04:39:13.895060 <6>[ 2.802371] hclge is initializing
10614 04:39:13.898556 <6>[ 2.805948] e1000: Intel(R) PRO/1000 Network Driver
10615 04:39:13.904836 <6>[ 2.811077] e1000: Copyright (c) 1999-2006 Intel Corporation.
10616 04:39:13.908184 <6>[ 2.817093] e1000e: Intel(R) PRO/1000 Network Driver
10617 04:39:13.914966 <6>[ 2.822309] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10618 04:39:13.921823 <6>[ 2.828494] igb: Intel(R) Gigabit Ethernet Network Driver
10619 04:39:13.928413 <6>[ 2.834143] igb: Copyright (c) 2007-2014 Intel Corporation.
10620 04:39:13.935052 <6>[ 2.839980] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10621 04:39:13.941790 <6>[ 2.846498] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10622 04:39:13.945312 <6>[ 2.852965] sky2: driver version 1.30
10623 04:39:13.951698 <6>[ 2.857967] VFIO - User Level meta-driver version: 0.3
10624 04:39:13.958922 <6>[ 2.866242] usbcore: registered new interface driver usb-storage
10625 04:39:13.965432 <6>[ 2.872687] usbcore: registered new device driver onboard-usb-hub
10626 04:39:13.974303 <6>[ 2.881813] mt6397-rtc mt6359-rtc: registered as rtc0
10627 04:39:13.984359 <6>[ 2.887279] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-09T04:38:38 UTC (1691555918)
10628 04:39:13.987487 <6>[ 2.896866] i2c_dev: i2c /dev entries driver
10629 04:39:14.004803 <6>[ 2.908697] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10630 04:39:14.025099 <6>[ 2.932704] cpu cpu0: EM: created perf domain
10631 04:39:14.028274 <6>[ 2.937698] cpu cpu4: EM: created perf domain
10632 04:39:14.036144 <6>[ 2.943321] sdhci: Secure Digital Host Controller Interface driver
10633 04:39:14.042408 <6>[ 2.949752] sdhci: Copyright(c) Pierre Ossman
10634 04:39:14.049403 <6>[ 2.954696] Synopsys Designware Multimedia Card Interface Driver
10635 04:39:14.056051 <6>[ 2.961325] sdhci-pltfm: SDHCI platform and OF driver helper
10636 04:39:14.059014 <6>[ 2.961355] mmc0: CQHCI version 5.10
10637 04:39:14.065833 <6>[ 2.971471] ledtrig-cpu: registered to indicate activity on CPUs
10638 04:39:14.072743 <6>[ 2.978571] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10639 04:39:14.078733 <6>[ 2.985630] usbcore: registered new interface driver usbhid
10640 04:39:14.081648 <6>[ 2.991452] usbhid: USB HID core driver
10641 04:39:14.091786 <6>[ 2.995618] spi_master spi0: will run message pump with realtime priority
10642 04:39:14.133162 <6>[ 3.034309] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10643 04:39:14.153116 <6>[ 3.050419] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10644 04:39:14.156180 <6>[ 3.064038] mmc0: Command Queue Engine enabled
10645 04:39:14.162834 <6>[ 3.068817] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10646 04:39:14.169723 <6>[ 3.076101] mmcblk0: mmc0:0001 DA4128 116 GiB
10647 04:39:14.172822 <6>[ 3.081020] cros-ec-spi spi0.0: Chrome EC device registered
10648 04:39:14.179438 <6>[ 3.084839] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10649 04:39:14.187351 <6>[ 3.094644] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10650 04:39:14.194004 <6>[ 3.100533] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10651 04:39:14.200312 <6>[ 3.106632] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10652 04:39:14.219865 <6>[ 3.123836] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10653 04:39:14.227140 <6>[ 3.134704] NET: Registered PF_PACKET protocol family
10654 04:39:14.230908 <6>[ 3.140118] 9pnet: Installing 9P2000 support
10655 04:39:14.237577 <5>[ 3.144684] Key type dns_resolver registered
10656 04:39:14.240627 <6>[ 3.149676] registered taskstats version 1
10657 04:39:14.247188 <5>[ 3.154062] Loading compiled-in X.509 certificates
10658 04:39:14.278593 <4>[ 3.179297] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10659 04:39:14.288520 <4>[ 3.190027] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10660 04:39:14.295032 <3>[ 3.200564] debugfs: File 'uA_load' in directory '/' already present!
10661 04:39:14.301821 <3>[ 3.207265] debugfs: File 'min_uV' in directory '/' already present!
10662 04:39:14.308329 <3>[ 3.213874] debugfs: File 'max_uV' in directory '/' already present!
10663 04:39:14.315165 <3>[ 3.220481] debugfs: File 'constraint_flags' in directory '/' already present!
10664 04:39:14.326267 <3>[ 3.230189] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10665 04:39:14.338175 <6>[ 3.245595] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10666 04:39:14.344944 <6>[ 3.252417] xhci-mtk 11200000.usb: xHCI Host Controller
10667 04:39:14.351689 <6>[ 3.257919] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10668 04:39:14.361941 <6>[ 3.265792] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10669 04:39:14.368611 <6>[ 3.275225] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10670 04:39:14.374690 <6>[ 3.281441] xhci-mtk 11200000.usb: xHCI Host Controller
10671 04:39:14.381754 <6>[ 3.286958] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10672 04:39:14.388169 <6>[ 3.294614] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10673 04:39:14.395031 <6>[ 3.302597] hub 1-0:1.0: USB hub found
10674 04:39:14.398839 <6>[ 3.306645] hub 1-0:1.0: 1 port detected
10675 04:39:14.408525 <6>[ 3.310973] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10676 04:39:14.411692 <6>[ 3.319761] hub 2-0:1.0: USB hub found
10677 04:39:14.415237 <6>[ 3.323803] hub 2-0:1.0: 1 port detected
10678 04:39:14.424847 <6>[ 3.332429] mtk-msdc 11f70000.mmc: Got CD GPIO
10679 04:39:14.437022 <6>[ 3.341342] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10680 04:39:14.443774 <6>[ 3.349395] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10681 04:39:14.453795 <4>[ 3.357321] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10682 04:39:14.463690 <6>[ 3.366884] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10683 04:39:14.470584 <6>[ 3.374967] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10684 04:39:14.477015 <6>[ 3.382984] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10685 04:39:14.487223 <6>[ 3.390910] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10686 04:39:14.493486 <6>[ 3.398727] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10687 04:39:14.503294 <6>[ 3.406543] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10688 04:39:14.513585 <6>[ 3.416923] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10689 04:39:14.519725 <6>[ 3.425301] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10690 04:39:14.529763 <6>[ 3.433640] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10691 04:39:14.536459 <6>[ 3.441978] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10692 04:39:14.546659 <6>[ 3.450316] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10693 04:39:14.553317 <6>[ 3.458656] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10694 04:39:14.563293 <6>[ 3.466994] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10695 04:39:14.570090 <6>[ 3.475333] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10696 04:39:14.579485 <6>[ 3.483670] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10697 04:39:14.586456 <6>[ 3.492015] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10698 04:39:14.596628 <6>[ 3.500354] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10699 04:39:14.602801 <6>[ 3.508691] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10700 04:39:14.612783 <6>[ 3.517029] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10701 04:39:14.622572 <6>[ 3.525369] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10702 04:39:14.629337 <6>[ 3.533708] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10703 04:39:14.636116 <6>[ 3.542465] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10704 04:39:14.642874 <6>[ 3.549636] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10705 04:39:14.649386 <6>[ 3.556403] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10706 04:39:14.656220 <6>[ 3.563170] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10707 04:39:14.665921 <6>[ 3.570099] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10708 04:39:14.672848 <6>[ 3.576949] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10709 04:39:14.682237 <6>[ 3.586085] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10710 04:39:14.692589 <6>[ 3.595204] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10711 04:39:14.702692 <6>[ 3.604498] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10712 04:39:14.712507 <6>[ 3.613966] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10713 04:39:14.718913 <6>[ 3.623433] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10714 04:39:14.728810 <6>[ 3.632554] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10715 04:39:14.738556 <6>[ 3.642022] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10716 04:39:14.748969 <6>[ 3.651141] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10717 04:39:14.758519 <6>[ 3.660435] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10718 04:39:14.768518 <6>[ 3.670595] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10719 04:39:14.778834 <6>[ 3.682155] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10720 04:39:14.806160 <6>[ 3.710730] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10721 04:39:14.834281 <6>[ 3.741805] hub 2-1:1.0: USB hub found
10722 04:39:14.837419 <6>[ 3.746275] hub 2-1:1.0: 3 ports detected
10723 04:39:14.958273 <6>[ 3.862476] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10724 04:39:15.113055 <6>[ 4.020549] hub 1-1:1.0: USB hub found
10725 04:39:15.116112 <6>[ 4.025064] hub 1-1:1.0: 4 ports detected
10726 04:39:15.190542 <6>[ 4.094808] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10727 04:39:15.438060 <6>[ 4.342530] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10728 04:39:15.570574 <6>[ 4.477778] hub 1-1.4:1.0: USB hub found
10729 04:39:15.573642 <6>[ 4.482314] hub 1-1.4:1.0: 2 ports detected
10730 04:39:15.870020 <6>[ 4.774477] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10731 04:39:16.062407 <6>[ 4.966589] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10732 04:39:27.071337 <6>[ 15.983499] ALSA device list:
10733 04:39:27.078182 <6>[ 15.986795] No soundcards found.
10734 04:39:27.086009 <6>[ 15.994802] Freeing unused kernel memory: 8384K
10735 04:39:27.089110 <6>[ 15.999842] Run /init as init process
10736 04:39:27.138551 <6>[ 16.047020] NET: Registered PF_INET6 protocol family
10737 04:39:27.144958 <6>[ 16.053383] Segment Routing with IPv6
10738 04:39:27.148032 <6>[ 16.057341] In-situ OAM (IOAM) with IPv6
10739 04:39:27.182596 <30>[ 16.071452] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10740 04:39:27.185416 <30>[ 16.095298] systemd[1]: Detected architecture arm64.
10741 04:39:27.185554
10742 04:39:27.192029 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10743 04:39:27.192151
10744 04:39:27.205402 <30>[ 16.114492] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10745 04:39:27.363508 <30>[ 16.269449] systemd[1]: Queued start job for default target Graphical Interface.
10746 04:39:27.406256 <30>[ 16.315295] systemd[1]: Created slice system-getty.slice.
10747 04:39:27.412985 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10748 04:39:27.430011 <30>[ 16.338976] systemd[1]: Created slice system-modprobe.slice.
10749 04:39:27.436385 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10750 04:39:27.453968 <30>[ 16.363127] systemd[1]: Created slice system-serial\x2dgetty.slice.
10751 04:39:27.463940 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10752 04:39:27.477813 <30>[ 16.386864] systemd[1]: Created slice User and Session Slice.
10753 04:39:27.484315 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10754 04:39:27.504837 <30>[ 16.410628] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10755 04:39:27.514644 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10756 04:39:27.528994 <30>[ 16.434556] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10757 04:39:27.535434 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10758 04:39:27.556233 <30>[ 16.458556] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10759 04:39:27.562751 <30>[ 16.470692] systemd[1]: Reached target Local Encrypted Volumes.
10760 04:39:27.569528 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10761 04:39:27.586499 <30>[ 16.495025] systemd[1]: Reached target Paths.
10762 04:39:27.589591 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10763 04:39:27.605636 <30>[ 16.514497] systemd[1]: Reached target Remote File Systems.
10764 04:39:27.612264 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10765 04:39:27.630041 <30>[ 16.538878] systemd[1]: Reached target Slices.
10766 04:39:27.636298 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10767 04:39:27.649700 <30>[ 16.558517] systemd[1]: Reached target Swap.
10768 04:39:27.652976 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10769 04:39:27.673331 <30>[ 16.579013] systemd[1]: Listening on initctl Compatibility Named Pipe.
10770 04:39:27.679962 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10771 04:39:27.686498 <30>[ 16.594197] systemd[1]: Listening on Journal Audit Socket.
10772 04:39:27.692909 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10773 04:39:27.705704 <30>[ 16.614980] systemd[1]: Listening on Journal Socket (/dev/log).
10774 04:39:27.712416 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10775 04:39:27.730789 <30>[ 16.639728] systemd[1]: Listening on Journal Socket.
10776 04:39:27.737481 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10777 04:39:27.753554 <30>[ 16.659190] systemd[1]: Listening on Network Service Netlink Socket.
10778 04:39:27.760209 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10779 04:39:27.774929 <30>[ 16.683713] systemd[1]: Listening on udev Control Socket.
10780 04:39:27.781479 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10781 04:39:27.798878 <30>[ 16.707585] systemd[1]: Listening on udev Kernel Socket.
10782 04:39:27.805265 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10783 04:39:27.861911 <30>[ 16.770768] systemd[1]: Mounting Huge Pages File System...
10784 04:39:27.868351 Mounting [0;1;39mHuge Pages File System[0m...
10785 04:39:27.883765 <30>[ 16.792703] systemd[1]: Mounting POSIX Message Queue File System...
10786 04:39:27.890492 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10787 04:39:27.911514 <30>[ 16.820447] systemd[1]: Mounting Kernel Debug File System...
10788 04:39:27.918100 Mounting [0;1;39mKernel Debug File System[0m...
10789 04:39:27.940766 <30>[ 16.846811] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10790 04:39:27.954112 <30>[ 16.859496] systemd[1]: Starting Create list of static device nodes for the current kernel...
10791 04:39:27.960132 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10792 04:39:27.981986 <30>[ 16.891246] systemd[1]: Starting Load Kernel Module configfs...
10793 04:39:27.988700 Starting [0;1;39mLoad Kernel Module configfs[0m...
10794 04:39:28.042076 <30>[ 16.951257] systemd[1]: Starting Load Kernel Module drm...
10795 04:39:28.048864 Starting [0;1;39mLoad Kernel Module drm[0m...
10796 04:39:28.065041 <30>[ 16.971008] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10797 04:39:28.080019 <30>[ 16.989188] systemd[1]: Starting Journal Service...
10798 04:39:28.083741 Starting [0;1;39mJournal Service[0m...
10799 04:39:28.106665 <30>[ 17.015527] systemd[1]: Starting Load Kernel Modules...
10800 04:39:28.112958 Starting [0;1;39mLoad Kernel Modules[0m...
10801 04:39:28.133066 <30>[ 17.038815] systemd[1]: Starting Remount Root and Kernel File Systems...
10802 04:39:28.139629 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10803 04:39:28.158166 <30>[ 17.067123] systemd[1]: Starting Coldplug All udev Devices...
10804 04:39:28.164856 Starting [0;1;39mColdplug All udev Devices[0m...
10805 04:39:28.180561 <30>[ 17.089729] systemd[1]: Started Journal Service.
10806 04:39:28.187214 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10807 04:39:28.203701 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10808 04:39:28.222502 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10809 04:39:28.238245 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10810 04:39:28.258152 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10811 04:39:28.275732 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10812 04:39:28.301157 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10813 04:39:28.320020 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10814 04:39:28.343767 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10815 04:39:28.357268 See 'systemctl status systemd-remount-fs.service' for details.
10816 04:39:28.417652 Mounting [0;1;39mKernel Configuration File System[0m...
10817 04:39:28.442455 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10818 04:39:28.463049 <46>[ 17.368788] systemd-journald[177]: Received client request to flush runtime journal.
10819 04:39:28.469720 Starting [0;1;39mLoad/Save Random Seed[0m...
10820 04:39:28.488549 Starting [0;1;39mApply Kernel Variables[0m...
10821 04:39:28.506541 Starting [0;1;39mCreate System Users[0m...
10822 04:39:28.530812 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10823 04:39:28.550206 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10824 04:39:28.574261 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10825 04:39:28.587380 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10826 04:39:28.603259 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10827 04:39:28.619326 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10828 04:39:28.665699 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10829 04:39:28.687291 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10830 04:39:28.701510 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10831 04:39:28.721576 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10832 04:39:28.757625 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10833 04:39:28.783026 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10834 04:39:28.802844 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10835 04:39:28.824171 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10836 04:39:28.867101 Starting [0;1;39mNetwork Service[0m...
10837 04:39:28.892199 Starting [0;1;39mNetwork Time Synchronization[0m...
10838 04:39:28.915309 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10839 04:39:28.962249 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10840 04:39:28.978763 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10841 04:39:28.994125 <6>[ 17.899713] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10842 04:39:29.000619 <6>[ 17.907531] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10843 04:39:29.014159 [[0;32m OK [<6>[ 17.916642] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10844 04:39:29.017249 0m] Started [0;1;39mNetwork Service[0m.
10845 04:39:29.039910 [[0;32m OK [0m] Found device<4>[ 17.944604] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10846 04:39:29.040014 [0;1;39m/dev/ttyS0[0m.
10847 04:39:29.051762 <4>[ 17.957766] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10848 04:39:29.058329 <6>[ 17.963485] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10849 04:39:29.080755 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbac<6>[ 17.988049] remoteproc remoteproc0: scp is available
10850 04:39:29.087645 klight.slice[0m<6>[ 17.994526] remoteproc remoteproc0: powering up scp
10851 04:39:29.087816 .
10852 04:39:29.094232 <6>[ 18.000793] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10853 04:39:29.100840 <6>[ 18.005622] usbcore: registered new interface driver r8152
10854 04:39:29.107504 <6>[ 18.009472] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10855 04:39:29.113709 <3>[ 18.011447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 04:39:29.124060 <3>[ 18.011469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 04:39:29.130617 <3>[ 18.011480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 04:39:29.140332 <3>[ 18.033527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 04:39:29.147073 <6>[ 18.047667] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10860 04:39:29.153682 <6>[ 18.047959] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10861 04:39:29.160319 <6>[ 18.047966] pci_bus 0000:00: root bus resource [bus 00-ff]
10862 04:39:29.166921 <6>[ 18.047973] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10863 04:39:29.176745 <6>[ 18.047976] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10864 04:39:29.183775 <6>[ 18.048028] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10865 04:39:29.191065 <6>[ 18.048092] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10866 04:39:29.194097 <6>[ 18.048359] pci 0000:00:00.0: supports D1 D2
10867 04:39:29.200702 <6>[ 18.048361] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10868 04:39:29.207339 <6>[ 18.053373] mc: Linux media interface: v0.10
10869 04:39:29.214174 <3>[ 18.053476] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 04:39:29.224375 <3>[ 18.053481] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 04:39:29.230885 <3>[ 18.053486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 04:39:29.240960 <3>[ 18.053490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 04:39:29.248139 <3>[ 18.057631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 04:39:29.254120 <3>[ 18.061643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 04:39:29.264282 <6>[ 18.065484] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10876 04:39:29.271035 <6>[ 18.070647] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10877 04:39:29.277771 <3>[ 18.074174] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 04:39:29.287277 <4>[ 18.078601] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10879 04:39:29.290655 <4>[ 18.078601] Fallback method does not support PEC.
10880 04:39:29.301096 <6>[ 18.081245] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10881 04:39:29.307141 <3>[ 18.091100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 04:39:29.317350 <6>[ 18.094927] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10883 04:39:29.324437 <6>[ 18.097372] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10884 04:39:29.331638 <6>[ 18.098847] videodev: Linux video capture interface: v2.00
10885 04:39:29.341652 <6>[ 18.099707] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10886 04:39:29.348286 <6>[ 18.099978] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10887 04:39:29.358197 <3>[ 18.105031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 04:39:29.365443 <6>[ 18.110362] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10889 04:39:29.372366 <3>[ 18.111864] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 04:39:29.382214 <3>[ 18.116278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 04:39:29.389012 <3>[ 18.116295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 04:39:29.399144 <3>[ 18.116312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 04:39:29.406553 <3>[ 18.116316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 04:39:29.413210 <3>[ 18.119093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 04:39:29.419703 <6>[ 18.121290] pci 0000:01:00.0: supports D1 D2
10896 04:39:29.423061 <6>[ 18.147286] usbcore: registered new interface driver cdc_ether
10897 04:39:29.430220 <6>[ 18.154173] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10898 04:39:29.437003 <6>[ 18.162575] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10899 04:39:29.443694 <6>[ 18.164092] Bluetooth: Core ver 2.22
10900 04:39:29.447051 <6>[ 18.164193] NET: Registered PF_BLUETOOTH protocol family
10901 04:39:29.454361 <6>[ 18.164198] Bluetooth: HCI device and connection manager initialized
10902 04:39:29.461219 <6>[ 18.164217] Bluetooth: HCI socket layer initialized
10903 04:39:29.464632 <6>[ 18.164222] Bluetooth: L2CAP socket layer initialized
10904 04:39:29.471283 <6>[ 18.164232] Bluetooth: SCO socket layer initialized
10905 04:39:29.477781 <6>[ 18.169931] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10906 04:39:29.484552 <6>[ 18.169955] remoteproc remoteproc0: remote processor scp is now up
10907 04:39:29.491312 <6>[ 18.184876] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10908 04:39:29.498072 <6>[ 18.192733] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10909 04:39:29.508158 <6>[ 18.206336] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10910 04:39:29.514633 <3>[ 18.207972] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 04:39:29.524465 <6>[ 18.214712] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10912 04:39:29.528010 <6>[ 18.215925] usbcore: registered new interface driver r8153_ecm
10913 04:39:29.537587 <6>[ 18.222091] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10914 04:39:29.544542 <3>[ 18.243346] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 04:39:29.554555 <6>[ 18.244448] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10916 04:39:29.567441 <6>[ 18.267095] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10917 04:39:29.574158 <6>[ 18.271647] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10918 04:39:29.580909 <6>[ 18.271660] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10919 04:39:29.587659 <6>[ 18.274728] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10920 04:39:29.601172 <4>[ 18.277164] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10921 04:39:29.604789 <3>[ 18.277176] Bluetooth: hci0: Failed to load firmware file (-2)
10922 04:39:29.610808 <3>[ 18.277183] Bluetooth: hci0: Failed to set up firmware (-2)
10923 04:39:29.620683 <4>[ 18.277187] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10924 04:39:29.627339 <6>[ 18.277582] usbcore: registered new interface driver btusb
10925 04:39:29.634583 <6>[ 18.283155] usbcore: registered new interface driver uvcvideo
10926 04:39:29.641078 <3>[ 18.286603] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 04:39:29.647829 <6>[ 18.287904] pci 0000:00:00.0: PCI bridge to [bus 01]
10928 04:39:29.653836 <6>[ 18.287910] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10929 04:39:29.660581 <6>[ 18.288554] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10930 04:39:29.670635 <6>[ 18.289155] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10931 04:39:29.677032 <6>[ 18.291661] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10932 04:39:29.687259 <3>[ 18.320559] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 04:39:29.697132 <3>[ 18.322979] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10934 04:39:29.703891 <6>[ 18.328438] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10935 04:39:29.706999 <6>[ 18.338473] r8152 2-1.3:1.0 eth0: v1.12.13
10936 04:39:29.713583 <6>[ 18.339371] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10937 04:39:29.720285 <3>[ 18.344126] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 04:39:29.726793 <6>[ 18.354640] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10939 04:39:29.733723 <6>[ 18.356957] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10940 04:39:29.743779 <3>[ 18.371449] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 04:39:29.756803 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.<5>[ 18.662141] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10942 04:39:29.756912
10943 04:39:29.772728 <5>[ 18.678781] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10944 04:39:29.782634 [[0;32m OK [0m] Reached targ<4>[ 18.687557] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10945 04:39:29.789486 et [0;1;39mSyst<6>[ 18.697815] cfg80211: failed to load regulatory.db
10946 04:39:29.792884 em Time Synchronized[0m.
10947 04:39:29.804465 <3>[ 18.710665] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 04:39:29.834147 <3>[ 18.740148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 04:39:29.853806 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m..<6>[ 18.758514] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10950 04:39:29.853939 .
10951 04:39:29.860569 <6>[ 18.767580] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10952 04:39:29.874071 Starting [0;1;39mNetwork Name Resolution[0m...
10953 04:39:29.880854 <6>[ 18.790366] mt7921e 0000:01:00.0: ASIC revision: 79610010
10954 04:39:29.898244 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10955 04:39:29.953853 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10956 04:39:29.988196 <4>[ 18.890628] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 04:39:30.070424 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10958 04:39:30.085460 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10959 04:39:30.106567 <4>[ 19.009335] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10960 04:39:30.113556 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10961 04:39:30.129496 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10962 04:39:30.153445 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10963 04:39:30.168578 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 04:39:30.181368 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10965 04:39:30.200805 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10966 04:39:30.214175 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10967 04:39:30.227934 <4>[ 19.129965] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10968 04:39:30.234398 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10969 04:39:30.253382 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10970 04:39:30.293865 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10971 04:39:30.324660 Starting [0;1;39mUser Login Management[0m...
10972 04:39:30.348667 <4>[ 19.251146] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 04:39:30.355164 Starting [0;1;39mPermit User Sessions[0m...
10974 04:39:30.371539 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10975 04:39:30.447615 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10976 04:39:30.468103 <4>[ 19.370897] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10977 04:39:30.474833 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10978 04:39:30.490520 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10979 04:39:30.559437 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10980 04:39:30.586295 <4>[ 19.488867] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10981 04:39:30.592425 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10982 04:39:30.610919 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10983 04:39:30.628090 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10984 04:39:30.646401 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10985 04:39:30.690623 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10986 04:39:30.712256 <4>[ 19.614963] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10987 04:39:30.722372 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10988 04:39:30.741008
10989 04:39:30.741145
10990 04:39:30.744041 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10991 04:39:30.744156
10992 04:39:30.747551 debian-bullseye-arm64 login: root (automatic login)
10993 04:39:30.747666
10994 04:39:30.747762
10995 04:39:30.765635 Linux debian-bullseye-arm64 6.1.42-cip2 #1 SMP PREEMPT Wed Aug 9 04:18:34 UTC 2023 aarch64
10996 04:39:30.765721
10997 04:39:30.772334 The programs included with the Debian GNU/Linux system are free software;
10998 04:39:30.778631 the exact distribution terms for each program are described in the
10999 04:39:30.782321 individual files in /usr/share/doc/*/copyright.
11000 04:39:30.782432
11001 04:39:30.789016 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11002 04:39:30.791925 permitted by applicable law.
11003 04:39:30.792449 Matched prompt #10: / #
11005 04:39:30.792785 Setting prompt string to ['/ #']
11006 04:39:30.792920 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11008 04:39:30.793246 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11009 04:39:30.793373 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11010 04:39:30.793479 Setting prompt string to ['/ #']
11011 04:39:30.793585 Forcing a shell prompt, looking for ['/ #']
11013 04:39:30.843883 / #
11014 04:39:30.844018 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11015 04:39:30.844117 Waiting using forced prompt support (timeout 00:02:30)
11016 04:39:30.844239 <4>[ 19.739040] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11017 04:39:30.849599
11018 04:39:30.849906 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11019 04:39:30.850037 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11020 04:39:30.850172 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11021 04:39:30.850299 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11022 04:39:30.850420 end: 2 depthcharge-action (duration 00:01:36) [common]
11023 04:39:30.850539 start: 3 lava-test-retry (timeout 00:05:00) [common]
11024 04:39:30.850654 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11025 04:39:30.850754 Using namespace: common
11027 04:39:30.951126 / # #
11028 04:39:30.951320 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11029 04:39:30.999592 #<4>[ 19.863276] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11030 04:39:30.999721
11031 04:39:30.999982 Using /lava-11241309
11033 04:39:31.100322 / # export SHELL=/bin/sh
11034 04:39:31.100547 export SHELL=/bin/sh<6>[ 19.980342] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11035 04:39:31.100628 <4>[ 19.988335] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11036 04:39:31.100740 <6>[ 19.988559] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11037 04:39:31.105828
11039 04:39:31.206357 / # . /lava-11241309/environment
11040 04:39:31.206549 . /lava-11241309/environment<3>[ 20.112986] mt7921e 0000:01:00.0: hardware init failed
11041 04:39:31.211186
11043 04:39:31.311798 / # /lava-11241309/bin/lava-test-runner /lava-11241309/0
11044 04:39:31.311964 Test shell timeout: 10s (minimum of the action and connection timeout)
11045 04:39:31.317062 /lava-11241309/bin/lava-test-runner /lava-11241309/0
11046 04:39:31.335453 + export TESTRUN_ID=0_cros-ec
11047 04:39:31.342152 + c<8>[ 20.250483] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11241309_1.5.2.3.1>
11048 04:39:31.342446 Received signal: <STARTRUN> 0_cros-ec 11241309_1.5.2.3.1
11049 04:39:31.342527 Starting test lava.0_cros-ec (11241309_1.5.2.3.1)
11050 04:39:31.342636 Skipping test definition patterns.
11051 04:39:31.345059 d /lava-11241309/0/tests/0_cros-ec
11052 04:39:31.348750 + cat uuid
11053 04:39:31.348839 + UUID=11241309_1.5.2.3.1
11054 04:39:31.348928 + set +x
11055 04:39:31.354945 + python3 -m cros.runners.lava_runner -v
11056 04:39:31.713781 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11057 04:39:31.723532 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11058 04:39:31.723686
11059 04:39:31.730169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11060 04:39:31.730459 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11062 04:39:31.736731 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11063 04:39:31.743742 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11064 04:39:31.743856
11065 04:39:31.750750 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
11066 04:39:31.750862 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
11067 04:39:31.756621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 20.665027] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11241309_1.5.2.3.1>
11068 04:39:31.756880 Received signal: <ENDRUN> 0_cros-ec 11241309_1.5.2.3.1
11069 04:39:31.756967 Ending use of test pattern.
11070 04:39:31.757030 Ending test lava.0_cros-ec (11241309_1.5.2.3.1), duration 0.41
11072 04:39:31.760299 valid RESULT=skip>
11073 04:39:31.763459 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11074 04:39:31.770284 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11075 04:39:31.770364
11076 04:39:31.776703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11077 04:39:31.776981 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11079 04:39:31.783936 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11080 04:39:31.790043 Checks the standard ABI for the main Embedded Controller. ... ok
11081 04:39:31.790151
11082 04:39:31.793751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11083 04:39:31.794027 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11085 04:39:31.800266 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11086 04:39:31.803295 Checks the main Embedded controller character device. ... ok
11087 04:39:31.806919
11088 04:39:31.809986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11089 04:39:31.810272 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11091 04:39:31.817046 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11092 04:39:31.823621 Checks basic comunication with the main Embedded controller. ... ok
11093 04:39:31.823706
11094 04:39:31.826868 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11096 04:39:31.829768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11097 04:39:31.833419 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11098 04:39:31.840038 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11099 04:39:31.840124
11100 04:39:31.846628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11101 04:39:31.846908 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11103 04:39:31.853104 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11104 04:39:31.860025 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11105 04:39:31.860136
11106 04:39:31.866301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11107 04:39:31.866599 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11109 04:39:31.873244 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11110 04:39:31.880028 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11111 04:39:31.880116
11112 04:39:31.883497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11113 04:39:31.883765 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11115 04:39:31.890007 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11116 04:39:31.896195 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11117 04:39:31.896299
11118 04:39:31.902873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11119 04:39:31.903152 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11121 04:39:31.909445 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11122 04:39:31.916174 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11123 04:39:31.916260
11124 04:39:31.922995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11125 04:39:31.923278 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11127 04:39:31.929090 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11128 04:39:31.935978 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11129 04:39:31.936063
11130 04:39:31.942754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11131 04:39:31.943010 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11133 04:39:31.945917 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11134 04:39:31.955766 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11135 04:39:31.955851
11136 04:39:31.959482 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11138 04:39:31.962741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11139 04:39:31.965882 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11140 04:39:31.975896 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11141 04:39:31.975979
11142 04:39:31.982355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11143 04:39:31.982637 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11145 04:39:31.989124 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11146 04:39:31.992296 Check the cros battery ABI. ... skipped 'No BAT found'
11147 04:39:31.992374
11148 04:39:31.998863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11149 04:39:31.999120 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11151 04:39:32.005651 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11152 04:39:32.012217 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11153 04:39:32.012305
11154 04:39:32.019145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11155 04:39:32.019401 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11157 04:39:32.025566 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11158 04:39:32.031985 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11159 04:39:32.032072
11160 04:39:32.038887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11161 04:39:32.039176 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11163 04:39:32.045598 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11164 04:39:32.051713 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11165 04:39:32.051803
11166 04:39:32.058552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11167 04:39:32.058636
11168 04:39:32.058877 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11170 04:39:32.065332 ----------------------------------------------------------------------
11171 04:39:32.065445 Ran 18 tests in 0.006s
11172 04:39:32.065539
11173 04:39:32.068810 OK (skipped=15)
11174 04:39:32.068897 + set +x
11175 04:39:32.071843 <LAVA_TEST_RUNNER EXIT>
11176 04:39:32.072119 ok: lava_test_shell seems to have completed
11177 04:39:32.072423 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11178 04:39:32.072553 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11179 04:39:32.072666 end: 3 lava-test-retry (duration 00:00:01) [common]
11180 04:39:32.072781 start: 4 finalize (timeout 00:07:59) [common]
11181 04:39:32.072895 start: 4.1 power-off (timeout 00:00:30) [common]
11182 04:39:32.073173 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11183 04:39:32.150736 >> Command sent successfully.
11184 04:39:32.153180 Returned 0 in 0 seconds
11185 04:39:32.253593 end: 4.1 power-off (duration 00:00:00) [common]
11187 04:39:32.253915 start: 4.2 read-feedback (timeout 00:07:59) [common]
11188 04:39:32.254183 Listened to connection for namespace 'common' for up to 1s
11189 04:39:33.255119 Finalising connection for namespace 'common'
11190 04:39:33.255304 Disconnecting from shell: Finalise
11191 04:39:33.255426 / #
11192 04:39:33.355775 end: 4.2 read-feedback (duration 00:00:01) [common]
11193 04:39:33.355949 end: 4 finalize (duration 00:00:01) [common]
11194 04:39:33.356091 Cleaning after the job
11195 04:39:33.356210 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/ramdisk
11196 04:39:33.362945 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/kernel
11197 04:39:33.371297 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/dtb
11198 04:39:33.371543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241309/tftp-deploy-z0d2ds2g/modules
11199 04:39:33.378550 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11241309
11200 04:39:33.505986 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11241309
11201 04:39:33.506184 Job finished correctly