Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 20
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 28
- Errors: 1
1 04:36:59.866428 lava-dispatcher, installed at version: 2023.05.1
2 04:36:59.866634 start: 0 validate
3 04:36:59.866773 Start time: 2023-08-09 04:36:59.866765+00:00 (UTC)
4 04:36:59.866908 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:36:59.867040 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:37:00.127613 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:37:00.127804 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:37:06.892523 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:37:06.892743 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:37:07.158393 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:37:07.158579 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:37:09.923047 validate duration: 10.06
14 04:37:09.923330 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:37:09.923432 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:37:09.923523 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:37:09.923655 Not decompressing ramdisk as can be used compressed.
18 04:37:09.923742 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 04:37:09.923808 saving as /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/ramdisk/rootfs.cpio.gz
20 04:37:09.923871 total size: 8181372 (7MB)
21 04:37:09.924898 progress 0% (0MB)
22 04:37:09.927293 progress 5% (0MB)
23 04:37:09.929633 progress 10% (0MB)
24 04:37:09.931962 progress 15% (1MB)
25 04:37:09.934146 progress 20% (1MB)
26 04:37:09.936481 progress 25% (1MB)
27 04:37:09.938633 progress 30% (2MB)
28 04:37:09.941003 progress 35% (2MB)
29 04:37:09.943145 progress 40% (3MB)
30 04:37:09.945457 progress 45% (3MB)
31 04:37:09.947564 progress 50% (3MB)
32 04:37:09.949844 progress 55% (4MB)
33 04:37:09.951947 progress 60% (4MB)
34 04:37:09.954230 progress 65% (5MB)
35 04:37:09.956325 progress 70% (5MB)
36 04:37:09.958606 progress 75% (5MB)
37 04:37:09.960755 progress 80% (6MB)
38 04:37:09.963032 progress 85% (6MB)
39 04:37:09.965185 progress 90% (7MB)
40 04:37:09.967495 progress 95% (7MB)
41 04:37:09.969691 progress 100% (7MB)
42 04:37:09.969902 7MB downloaded in 0.05s (169.52MB/s)
43 04:37:09.970055 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:37:09.970306 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:37:09.970395 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:37:09.970481 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:37:09.970621 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:37:09.970694 saving as /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/kernel/Image
50 04:37:09.970756 total size: 49220096 (46MB)
51 04:37:09.970818 No compression specified
52 04:37:09.971898 progress 0% (0MB)
53 04:37:09.984919 progress 5% (2MB)
54 04:37:09.998092 progress 10% (4MB)
55 04:37:10.011188 progress 15% (7MB)
56 04:37:10.024493 progress 20% (9MB)
57 04:37:10.037779 progress 25% (11MB)
58 04:37:10.050874 progress 30% (14MB)
59 04:37:10.063977 progress 35% (16MB)
60 04:37:10.077233 progress 40% (18MB)
61 04:37:10.090346 progress 45% (21MB)
62 04:37:10.103663 progress 50% (23MB)
63 04:37:10.116873 progress 55% (25MB)
64 04:37:10.130137 progress 60% (28MB)
65 04:37:10.143205 progress 65% (30MB)
66 04:37:10.156337 progress 70% (32MB)
67 04:37:10.169451 progress 75% (35MB)
68 04:37:10.182575 progress 80% (37MB)
69 04:37:10.195665 progress 85% (39MB)
70 04:37:10.208713 progress 90% (42MB)
71 04:37:10.221587 progress 95% (44MB)
72 04:37:10.234794 progress 100% (46MB)
73 04:37:10.234972 46MB downloaded in 0.26s (177.66MB/s)
74 04:37:10.235133 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:37:10.235368 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:37:10.235462 start: 1.3 download-retry (timeout 00:10:00) [common]
78 04:37:10.235559 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 04:37:10.235735 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:37:10.235813 saving as /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/dtb/mt8192-asurada-spherion-r0.dtb
81 04:37:10.235878 total size: 47278 (0MB)
82 04:37:10.235941 No compression specified
83 04:37:10.237234 progress 69% (0MB)
84 04:37:10.237522 progress 100% (0MB)
85 04:37:10.237686 0MB downloaded in 0.00s (24.99MB/s)
86 04:37:10.237831 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:37:10.238058 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:37:10.238144 start: 1.4 download-retry (timeout 00:10:00) [common]
90 04:37:10.238228 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 04:37:10.238345 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:37:10.238416 saving as /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/modules/modules.tar
93 04:37:10.238477 total size: 8557308 (8MB)
94 04:37:10.238538 Using unxz to decompress xz
95 04:37:10.242627 progress 0% (0MB)
96 04:37:10.264849 progress 5% (0MB)
97 04:37:10.287773 progress 10% (0MB)
98 04:37:10.314855 progress 15% (1MB)
99 04:37:10.341379 progress 20% (1MB)
100 04:37:10.368242 progress 25% (2MB)
101 04:37:10.397539 progress 30% (2MB)
102 04:37:10.425174 progress 35% (2MB)
103 04:37:10.452388 progress 40% (3MB)
104 04:37:10.478880 progress 45% (3MB)
105 04:37:10.506352 progress 50% (4MB)
106 04:37:10.532522 progress 55% (4MB)
107 04:37:10.558407 progress 60% (4MB)
108 04:37:10.582017 progress 65% (5MB)
109 04:37:10.608207 progress 70% (5MB)
110 04:37:10.633371 progress 75% (6MB)
111 04:37:10.660195 progress 80% (6MB)
112 04:37:10.690810 progress 85% (6MB)
113 04:37:10.719878 progress 90% (7MB)
114 04:37:10.744670 progress 95% (7MB)
115 04:37:10.768909 progress 100% (8MB)
116 04:37:10.773792 8MB downloaded in 0.54s (15.25MB/s)
117 04:37:10.774157 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:37:10.774573 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:37:10.774706 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:37:10.774835 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:37:10.774956 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:37:10.775077 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:37:10.775349 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark
125 04:37:10.775534 makedir: /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin
126 04:37:10.775677 makedir: /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/tests
127 04:37:10.775812 makedir: /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/results
128 04:37:10.775935 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-add-keys
129 04:37:10.776095 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-add-sources
130 04:37:10.776267 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-background-process-start
131 04:37:10.776439 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-background-process-stop
132 04:37:10.776606 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-common-functions
133 04:37:10.776784 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-echo-ipv4
134 04:37:10.776970 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-install-packages
135 04:37:10.777141 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-installed-packages
136 04:37:10.777319 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-os-build
137 04:37:10.777517 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-probe-channel
138 04:37:10.777698 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-probe-ip
139 04:37:10.777875 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-target-ip
140 04:37:10.778064 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-target-mac
141 04:37:10.778256 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-target-storage
142 04:37:10.778439 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-test-case
143 04:37:10.778611 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-test-event
144 04:37:10.778786 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-test-feedback
145 04:37:10.778958 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-test-raise
146 04:37:10.779137 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-test-reference
147 04:37:10.779308 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-test-runner
148 04:37:10.779474 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-test-set
149 04:37:10.779654 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-test-shell
150 04:37:10.779803 Updating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-install-packages (oe)
151 04:37:10.779986 Updating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/bin/lava-installed-packages (oe)
152 04:37:10.780130 Creating /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/environment
153 04:37:10.780269 LAVA metadata
154 04:37:10.780386 - LAVA_JOB_ID=11241307
155 04:37:10.780488 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:37:10.780643 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:37:10.780756 skipped lava-vland-overlay
158 04:37:10.780869 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:37:10.780990 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:37:10.781094 skipped lava-multinode-overlay
161 04:37:10.781181 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:37:10.781273 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:37:10.781365 Loading test definitions
164 04:37:10.781471 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 04:37:10.781583 Using /lava-11241307 at stage 0
166 04:37:10.782078 uuid=11241307_1.5.2.3.1 testdef=None
167 04:37:10.782208 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 04:37:10.782350 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 04:37:10.783165 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 04:37:10.783545 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 04:37:10.784423 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 04:37:10.784809 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 04:37:10.785657 runner path: /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/0/tests/0_dmesg test_uuid 11241307_1.5.2.3.1
176 04:37:10.785862 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 04:37:10.786268 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 04:37:10.786400 Using /lava-11241307 at stage 1
180 04:37:10.786865 uuid=11241307_1.5.2.3.5 testdef=None
181 04:37:10.787001 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 04:37:10.787123 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 04:37:10.787838 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 04:37:10.788075 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 04:37:10.789575 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 04:37:10.789959 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 04:37:10.791029 runner path: /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/1/tests/1_bootrr test_uuid 11241307_1.5.2.3.5
190 04:37:10.791235 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 04:37:10.791603 Creating lava-test-runner.conf files
193 04:37:10.791700 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/0 for stage 0
194 04:37:10.791837 - 0_dmesg
195 04:37:10.791927 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11241307/lava-overlay-iyp9aark/lava-11241307/1 for stage 1
196 04:37:10.792067 - 1_bootrr
197 04:37:10.792210 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 04:37:10.792337 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 04:37:10.803177 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 04:37:10.803350 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 04:37:10.803485 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 04:37:10.803608 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 04:37:10.803738 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 04:37:11.062645 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 04:37:11.063077 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 04:37:11.063233 extracting modules file /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11241307/extract-overlay-ramdisk-2p_69ji1/ramdisk
207 04:37:11.368243 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 04:37:11.368447 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
209 04:37:11.368580 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11241307/compress-overlay-2tvassh7/overlay-1.5.2.4.tar.gz to ramdisk
210 04:37:11.368707 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11241307/compress-overlay-2tvassh7/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11241307/extract-overlay-ramdisk-2p_69ji1/ramdisk
211 04:37:11.377978 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 04:37:11.378155 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
213 04:37:11.378287 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 04:37:11.378409 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
215 04:37:11.378534 Building ramdisk /var/lib/lava/dispatcher/tmp/11241307/extract-overlay-ramdisk-2p_69ji1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11241307/extract-overlay-ramdisk-2p_69ji1/ramdisk
216 04:37:11.754953 >> 143904 blocks
217 04:37:14.067359 rename /var/lib/lava/dispatcher/tmp/11241307/extract-overlay-ramdisk-2p_69ji1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/ramdisk/ramdisk.cpio.gz
218 04:37:14.067846 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 04:37:14.068010 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 04:37:14.068143 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 04:37:14.068277 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/kernel/Image'
222 04:37:27.334807 Returned 0 in 13 seconds
223 04:37:27.435487 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/kernel/image.itb
224 04:37:27.834198 output: FIT description: Kernel Image image with one or more FDT blobs
225 04:37:27.834622 output: Created: Wed Aug 9 05:37:27 2023
226 04:37:27.834732 output: Image 0 (kernel-1)
227 04:37:27.834841 output: Description:
228 04:37:27.834936 output: Created: Wed Aug 9 05:37:27 2023
229 04:37:27.835037 output: Type: Kernel Image
230 04:37:27.835134 output: Compression: lzma compressed
231 04:37:27.835225 output: Data Size: 11036366 Bytes = 10777.70 KiB = 10.53 MiB
232 04:37:27.835325 output: Architecture: AArch64
233 04:37:27.835416 output: OS: Linux
234 04:37:27.835505 output: Load Address: 0x00000000
235 04:37:27.835604 output: Entry Point: 0x00000000
236 04:37:27.835695 output: Hash algo: crc32
237 04:37:27.835793 output: Hash value: 9e750869
238 04:37:27.835882 output: Image 1 (fdt-1)
239 04:37:27.835969 output: Description: mt8192-asurada-spherion-r0
240 04:37:27.836063 output: Created: Wed Aug 9 05:37:27 2023
241 04:37:27.836148 output: Type: Flat Device Tree
242 04:37:27.836231 output: Compression: uncompressed
243 04:37:27.836325 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 04:37:27.836409 output: Architecture: AArch64
245 04:37:27.836500 output: Hash algo: crc32
246 04:37:27.836591 output: Hash value: cc4352de
247 04:37:27.836685 output: Image 2 (ramdisk-1)
248 04:37:27.836780 output: Description: unavailable
249 04:37:27.836863 output: Created: Wed Aug 9 05:37:27 2023
250 04:37:27.836954 output: Type: RAMDisk Image
251 04:37:27.837012 output: Compression: Unknown Compression
252 04:37:27.837073 output: Data Size: 21241578 Bytes = 20743.73 KiB = 20.26 MiB
253 04:37:27.837163 output: Architecture: AArch64
254 04:37:27.837254 output: OS: Linux
255 04:37:27.837337 output: Load Address: unavailable
256 04:37:27.837429 output: Entry Point: unavailable
257 04:37:27.837514 output: Hash algo: crc32
258 04:37:27.837597 output: Hash value: 46592023
259 04:37:27.837689 output: Default Configuration: 'conf-1'
260 04:37:27.837773 output: Configuration 0 (conf-1)
261 04:37:27.837856 output: Description: mt8192-asurada-spherion-r0
262 04:37:27.837951 output: Kernel: kernel-1
263 04:37:27.838039 output: Init Ramdisk: ramdisk-1
264 04:37:27.838124 output: FDT: fdt-1
265 04:37:27.838206 output: Loadables: kernel-1
266 04:37:27.838298 output:
267 04:37:27.838550 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 04:37:27.838690 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 04:37:27.838834 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 04:37:27.838963 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 04:37:27.839086 No LXC device requested
272 04:37:27.839202 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 04:37:27.839331 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 04:37:27.839443 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 04:37:27.839550 Checking files for TFTP limit of 4294967296 bytes.
276 04:37:27.840266 end: 1 tftp-deploy (duration 00:00:18) [common]
277 04:37:27.840406 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 04:37:27.840543 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 04:37:27.840726 substitutions:
280 04:37:27.840804 - {DTB}: 11241307/tftp-deploy-a8jao2y4/dtb/mt8192-asurada-spherion-r0.dtb
281 04:37:27.840870 - {INITRD}: 11241307/tftp-deploy-a8jao2y4/ramdisk/ramdisk.cpio.gz
282 04:37:27.840931 - {KERNEL}: 11241307/tftp-deploy-a8jao2y4/kernel/Image
283 04:37:27.841013 - {LAVA_MAC}: None
284 04:37:27.841073 - {PRESEED_CONFIG}: None
285 04:37:27.841130 - {PRESEED_LOCAL}: None
286 04:37:27.841187 - {RAMDISK}: 11241307/tftp-deploy-a8jao2y4/ramdisk/ramdisk.cpio.gz
287 04:37:27.841264 - {ROOT_PART}: None
288 04:37:27.841321 - {ROOT}: None
289 04:37:27.841376 - {SERVER_IP}: 192.168.201.1
290 04:37:27.841433 - {TEE}: None
291 04:37:27.841503 Parsed boot commands:
292 04:37:27.841558 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 04:37:27.841792 Parsed boot commands: tftpboot 192.168.201.1 11241307/tftp-deploy-a8jao2y4/kernel/image.itb 11241307/tftp-deploy-a8jao2y4/kernel/cmdline
294 04:37:27.841919 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 04:37:27.842040 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 04:37:27.842189 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 04:37:27.842310 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 04:37:27.842425 Not connected, no need to disconnect.
299 04:37:27.842532 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 04:37:27.842659 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 04:37:27.842759 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
302 04:37:27.847760 Setting prompt string to ['lava-test: # ']
303 04:37:27.848498 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 04:37:27.848640 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 04:37:27.848795 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 04:37:27.848927 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 04:37:27.849278 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
308 04:37:32.987124 >> Command sent successfully.
309 04:37:32.989523 Returned 0 in 5 seconds
310 04:37:33.089905 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 04:37:33.090256 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 04:37:33.090370 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 04:37:33.090460 Setting prompt string to 'Starting depthcharge on Spherion...'
315 04:37:33.090550 Changing prompt to 'Starting depthcharge on Spherion...'
316 04:37:33.090620 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 04:37:33.090927 [Enter `^Ec?' for help]
318 04:37:33.264530
319 04:37:33.264699
320 04:37:33.264813 F0: 102B 0000
321 04:37:33.264878
322 04:37:33.264937 F3: 1001 0000 [0200]
323 04:37:33.267806
324 04:37:33.267874 F3: 1001 0000
325 04:37:33.267934
326 04:37:33.268020 F7: 102D 0000
327 04:37:33.268077
328 04:37:33.271428 F1: 0000 0000
329 04:37:33.271515
330 04:37:33.271581 V0: 0000 0000 [0001]
331 04:37:33.271644
332 04:37:33.274179 00: 0007 8000
333 04:37:33.274266
334 04:37:33.274332 01: 0000 0000
335 04:37:33.274395
336 04:37:33.277857 BP: 0C00 0209 [0000]
337 04:37:33.277940
338 04:37:33.278005 G0: 1182 0000
339 04:37:33.278066
340 04:37:33.281535 EC: 0000 0021 [4000]
341 04:37:33.281683
342 04:37:33.281790 S7: 0000 0000 [0000]
343 04:37:33.281885
344 04:37:33.284960 CC: 0000 0000 [0001]
345 04:37:33.285076
346 04:37:33.285172 T0: 0000 0040 [010F]
347 04:37:33.285257
348 04:37:33.285317 Jump to BL
349 04:37:33.285374
350 04:37:33.311440
351 04:37:33.311574
352 04:37:33.311642
353 04:37:33.318963 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 04:37:33.321952 ARM64: Exception handlers installed.
355 04:37:33.326175 ARM64: Testing exception
356 04:37:33.329037 ARM64: Done test exception
357 04:37:33.335854 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 04:37:33.346206 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 04:37:33.353068 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 04:37:33.363347 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 04:37:33.370108 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 04:37:33.376408 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 04:37:33.388083 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 04:37:33.395066 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 04:37:33.414676 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 04:37:33.417603 WDT: Last reset was cold boot
367 04:37:33.421208 SPI1(PAD0) initialized at 2873684 Hz
368 04:37:33.423998 SPI5(PAD0) initialized at 992727 Hz
369 04:37:33.427684 VBOOT: Loading verstage.
370 04:37:33.434243 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 04:37:33.437675 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 04:37:33.441147 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 04:37:33.444254 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 04:37:33.451951 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 04:37:33.458295 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 04:37:33.469522 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 04:37:33.469638
378 04:37:33.469745
379 04:37:33.479487 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 04:37:33.483054 ARM64: Exception handlers installed.
381 04:37:33.486221 ARM64: Testing exception
382 04:37:33.486330 ARM64: Done test exception
383 04:37:33.492673 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 04:37:33.496322 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 04:37:33.511191 Probing TPM: . done!
386 04:37:33.511303 TPM ready after 0 ms
387 04:37:33.518315 Connected to device vid:did:rid of 1ae0:0028:00
388 04:37:33.524910 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 04:37:33.582341 Initialized TPM device CR50 revision 0
390 04:37:33.593974 tlcl_send_startup: Startup return code is 0
391 04:37:33.594073 TPM: setup succeeded
392 04:37:33.605560 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 04:37:33.614464 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 04:37:33.626471 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 04:37:33.636400 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 04:37:33.639981 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 04:37:33.644107 in-header: 03 07 00 00 08 00 00 00
398 04:37:33.647755 in-data: aa e4 47 04 13 02 00 00
399 04:37:33.651239 Chrome EC: UHEPI supported
400 04:37:33.659101 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 04:37:33.662469 in-header: 03 ad 00 00 08 00 00 00
402 04:37:33.666158 in-data: 00 20 20 08 00 00 00 00
403 04:37:33.666234 Phase 1
404 04:37:33.670318 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 04:37:33.677324 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 04:37:33.680804 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 04:37:33.684632 Recovery requested (1009000e)
408 04:37:33.693110 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 04:37:33.698656 tlcl_extend: response is 0
410 04:37:33.708152 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 04:37:33.713074 tlcl_extend: response is 0
412 04:37:33.720179 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 04:37:33.739933 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 04:37:33.747233 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 04:37:33.747317
416 04:37:33.747383
417 04:37:33.757250 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 04:37:33.760907 ARM64: Exception handlers installed.
419 04:37:33.760990 ARM64: Testing exception
420 04:37:33.764400 ARM64: Done test exception
421 04:37:33.785775 pmic_efuse_setting: Set efuses in 11 msecs
422 04:37:33.789585 pmwrap_interface_init: Select PMIF_VLD_RDY
423 04:37:33.796253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 04:37:33.799373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 04:37:33.806463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 04:37:33.809864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 04:37:33.813351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 04:37:33.820995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 04:37:33.824382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 04:37:33.828301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 04:37:33.831516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 04:37:33.839171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 04:37:33.842652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 04:37:33.846226 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 04:37:33.850085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 04:37:33.857917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 04:37:33.865049 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 04:37:33.868735 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 04:37:33.876170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 04:37:33.880068 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 04:37:33.887055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 04:37:33.890644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 04:37:33.898232 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 04:37:33.901672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 04:37:33.909431 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 04:37:33.912875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 04:37:33.920486 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 04:37:33.924131 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 04:37:33.931449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 04:37:33.935025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 04:37:33.939160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 04:37:33.946294 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 04:37:33.950162 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 04:37:33.953885 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 04:37:33.961075 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 04:37:33.964642 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 04:37:33.968288 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 04:37:33.976132 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 04:37:33.979504 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 04:37:33.983730 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 04:37:33.991300 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 04:37:33.994794 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 04:37:33.998637 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 04:37:34.002187 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 04:37:34.005789 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 04:37:34.013190 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 04:37:34.017223 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 04:37:34.020366 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 04:37:34.024698 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 04:37:34.028401 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 04:37:34.031901 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 04:37:34.036097 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 04:37:34.039220 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 04:37:34.050533 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 04:37:34.058462 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 04:37:34.062014 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 04:37:34.069261 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 04:37:34.080060 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 04:37:34.084367 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 04:37:34.087920 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 04:37:34.091299 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 04:37:34.099038 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x14
483 04:37:34.102966 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 04:37:34.111056 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
485 04:37:34.114587 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 04:37:34.123780 [RTC]rtc_get_frequency_meter,154: input=15, output=789
487 04:37:34.133019 [RTC]rtc_get_frequency_meter,154: input=23, output=977
488 04:37:34.142250 [RTC]rtc_get_frequency_meter,154: input=19, output=883
489 04:37:34.152208 [RTC]rtc_get_frequency_meter,154: input=17, output=836
490 04:37:34.161659 [RTC]rtc_get_frequency_meter,154: input=16, output=812
491 04:37:34.171171 [RTC]rtc_get_frequency_meter,154: input=15, output=790
492 04:37:34.180962 [RTC]rtc_get_frequency_meter,154: input=16, output=814
493 04:37:34.184048 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
494 04:37:34.191976 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
495 04:37:34.195327 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 04:37:34.198683 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 04:37:34.202287 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 04:37:34.206007 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 04:37:34.210009 ADC[4]: Raw value=902066 ID=7
500 04:37:34.213622 ADC[3]: Raw value=213336 ID=1
501 04:37:34.214193 RAM Code: 0x71
502 04:37:34.217528 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 04:37:34.224931 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 04:37:34.232442 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 04:37:34.239709 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 04:37:34.243257 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 04:37:34.246956 in-header: 03 07 00 00 08 00 00 00
508 04:37:34.250341 in-data: aa e4 47 04 13 02 00 00
509 04:37:34.250730 Chrome EC: UHEPI supported
510 04:37:34.258082 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 04:37:34.261472 in-header: 03 ed 00 00 08 00 00 00
512 04:37:34.265194 in-data: 80 20 60 08 00 00 00 00
513 04:37:34.269085 MRC: failed to locate region type 0.
514 04:37:34.276413 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 04:37:34.279833 DRAM-K: Running full calibration
516 04:37:34.284522 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 04:37:34.287691 header.status = 0x0
518 04:37:34.291660 header.version = 0x6 (expected: 0x6)
519 04:37:34.292451 header.size = 0xd00 (expected: 0xd00)
520 04:37:34.295640 header.flags = 0x0
521 04:37:34.302253 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 04:37:34.319910 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
523 04:37:34.326888 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 04:37:34.327081 dram_init: ddr_geometry: 2
525 04:37:34.330820 [EMI] MDL number = 2
526 04:37:34.330998 [EMI] Get MDL freq = 0
527 04:37:34.334326 dram_init: ddr_type: 0
528 04:37:34.334404 is_discrete_lpddr4: 1
529 04:37:34.337947 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 04:37:34.338030
531 04:37:34.338095
532 04:37:34.341719 [Bian_co] ETT version 0.0.0.1
533 04:37:34.345190 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 04:37:34.345278
535 04:37:34.353014 dramc_set_vcore_voltage set vcore to 650000
536 04:37:34.353101 Read voltage for 800, 4
537 04:37:34.353167 Vio18 = 0
538 04:37:34.356347 Vcore = 650000
539 04:37:34.356457 Vdram = 0
540 04:37:34.356561 Vddq = 0
541 04:37:34.360308 Vmddr = 0
542 04:37:34.360396 dram_init: config_dvfs: 1
543 04:37:34.363949 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 04:37:34.370991 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 04:37:34.374065 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
546 04:37:34.377717 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
547 04:37:34.381226 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
548 04:37:34.387788 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
549 04:37:34.387886 MEM_TYPE=3, freq_sel=18
550 04:37:34.391050 sv_algorithm_assistance_LP4_1600
551 04:37:34.394595 ============ PULL DRAM RESETB DOWN ============
552 04:37:34.401307 ========== PULL DRAM RESETB DOWN end =========
553 04:37:34.404583 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 04:37:34.407742 ===================================
555 04:37:34.411072 LPDDR4 DRAM CONFIGURATION
556 04:37:34.414462 ===================================
557 04:37:34.414581 EX_ROW_EN[0] = 0x0
558 04:37:34.417914 EX_ROW_EN[1] = 0x0
559 04:37:34.418012 LP4Y_EN = 0x0
560 04:37:34.421142 WORK_FSP = 0x0
561 04:37:34.421229 WL = 0x2
562 04:37:34.424934 RL = 0x2
563 04:37:34.425049 BL = 0x2
564 04:37:34.427762 RPST = 0x0
565 04:37:34.427843 RD_PRE = 0x0
566 04:37:34.431668 WR_PRE = 0x1
567 04:37:34.431771 WR_PST = 0x0
568 04:37:34.435352 DBI_WR = 0x0
569 04:37:34.435487 DBI_RD = 0x0
570 04:37:34.438091 OTF = 0x1
571 04:37:34.441431 ===================================
572 04:37:34.444671 ===================================
573 04:37:34.444778 ANA top config
574 04:37:34.448257 ===================================
575 04:37:34.451622 DLL_ASYNC_EN = 0
576 04:37:34.455183 ALL_SLAVE_EN = 1
577 04:37:34.458266 NEW_RANK_MODE = 1
578 04:37:34.458340 DLL_IDLE_MODE = 1
579 04:37:34.461656 LP45_APHY_COMB_EN = 1
580 04:37:34.464731 TX_ODT_DIS = 1
581 04:37:34.468655 NEW_8X_MODE = 1
582 04:37:34.471362 ===================================
583 04:37:34.474878 ===================================
584 04:37:34.478128 data_rate = 1600
585 04:37:34.478244 CKR = 1
586 04:37:34.481906 DQ_P2S_RATIO = 8
587 04:37:34.485163 ===================================
588 04:37:34.488498 CA_P2S_RATIO = 8
589 04:37:34.491918 DQ_CA_OPEN = 0
590 04:37:34.494901 DQ_SEMI_OPEN = 0
591 04:37:34.495023 CA_SEMI_OPEN = 0
592 04:37:34.498340 CA_FULL_RATE = 0
593 04:37:34.502042 DQ_CKDIV4_EN = 1
594 04:37:34.504986 CA_CKDIV4_EN = 1
595 04:37:34.508325 CA_PREDIV_EN = 0
596 04:37:34.512190 PH8_DLY = 0
597 04:37:34.512270 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 04:37:34.515870 DQ_AAMCK_DIV = 4
599 04:37:34.518742 CA_AAMCK_DIV = 4
600 04:37:34.522157 CA_ADMCK_DIV = 4
601 04:37:34.525642 DQ_TRACK_CA_EN = 0
602 04:37:34.525735 CA_PICK = 800
603 04:37:34.528925 CA_MCKIO = 800
604 04:37:34.532403 MCKIO_SEMI = 0
605 04:37:34.535971 PLL_FREQ = 3068
606 04:37:34.539556 DQ_UI_PI_RATIO = 32
607 04:37:34.543791 CA_UI_PI_RATIO = 0
608 04:37:34.543876 ===================================
609 04:37:34.546711 ===================================
610 04:37:34.550397 memory_type:LPDDR4
611 04:37:34.554192 GP_NUM : 10
612 04:37:34.554280 SRAM_EN : 1
613 04:37:34.557533 MD32_EN : 0
614 04:37:34.561064 ===================================
615 04:37:34.561170 [ANA_INIT] >>>>>>>>>>>>>>
616 04:37:34.564566 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 04:37:34.568414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 04:37:34.572061 ===================================
619 04:37:34.575549 data_rate = 1600,PCW = 0X7600
620 04:37:34.578855 ===================================
621 04:37:34.582385 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 04:37:34.585332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 04:37:34.592118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 04:37:34.595435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 04:37:34.598630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 04:37:34.602139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 04:37:34.605659 [ANA_INIT] flow start
628 04:37:34.609298 [ANA_INIT] PLL >>>>>>>>
629 04:37:34.609383 [ANA_INIT] PLL <<<<<<<<
630 04:37:34.612519 [ANA_INIT] MIDPI >>>>>>>>
631 04:37:34.615420 [ANA_INIT] MIDPI <<<<<<<<
632 04:37:34.619141 [ANA_INIT] DLL >>>>>>>>
633 04:37:34.619225 [ANA_INIT] flow end
634 04:37:34.622326 ============ LP4 DIFF to SE enter ============
635 04:37:34.628788 ============ LP4 DIFF to SE exit ============
636 04:37:34.628872 [ANA_INIT] <<<<<<<<<<<<<
637 04:37:34.632247 [Flow] Enable top DCM control >>>>>
638 04:37:34.635966 [Flow] Enable top DCM control <<<<<
639 04:37:34.639283 Enable DLL master slave shuffle
640 04:37:34.646139 ==============================================================
641 04:37:34.646223 Gating Mode config
642 04:37:34.652635 ==============================================================
643 04:37:34.652737 Config description:
644 04:37:34.662456 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 04:37:34.669601 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 04:37:34.676181 SELPH_MODE 0: By rank 1: By Phase
647 04:37:34.679834 ==============================================================
648 04:37:34.682995 GAT_TRACK_EN = 1
649 04:37:34.685940 RX_GATING_MODE = 2
650 04:37:34.689733 RX_GATING_TRACK_MODE = 2
651 04:37:34.692560 SELPH_MODE = 1
652 04:37:34.695996 PICG_EARLY_EN = 1
653 04:37:34.699582 VALID_LAT_VALUE = 1
654 04:37:34.703236 ==============================================================
655 04:37:34.706523 Enter into Gating configuration >>>>
656 04:37:34.709753 Exit from Gating configuration <<<<
657 04:37:34.713039 Enter into DVFS_PRE_config >>>>>
658 04:37:34.726634 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 04:37:34.729717 Exit from DVFS_PRE_config <<<<<
660 04:37:34.729809 Enter into PICG configuration >>>>
661 04:37:34.733321 Exit from PICG configuration <<<<
662 04:37:34.736279 [RX_INPUT] configuration >>>>>
663 04:37:34.739797 [RX_INPUT] configuration <<<<<
664 04:37:34.746426 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 04:37:34.749932 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 04:37:34.756974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 04:37:34.764493 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 04:37:34.767651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 04:37:34.774042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 04:37:34.777791 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 04:37:34.784654 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 04:37:34.787612 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 04:37:34.791309 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 04:37:34.794736 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 04:37:34.801267 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 04:37:34.804336 ===================================
677 04:37:34.804464 LPDDR4 DRAM CONFIGURATION
678 04:37:34.807857 ===================================
679 04:37:34.811480 EX_ROW_EN[0] = 0x0
680 04:37:34.815031 EX_ROW_EN[1] = 0x0
681 04:37:34.815136 LP4Y_EN = 0x0
682 04:37:34.818494 WORK_FSP = 0x0
683 04:37:34.818608 WL = 0x2
684 04:37:34.821587 RL = 0x2
685 04:37:34.821696 BL = 0x2
686 04:37:34.824554 RPST = 0x0
687 04:37:34.824693 RD_PRE = 0x0
688 04:37:34.828514 WR_PRE = 0x1
689 04:37:34.828619 WR_PST = 0x0
690 04:37:34.831438 DBI_WR = 0x0
691 04:37:34.831547 DBI_RD = 0x0
692 04:37:34.835030 OTF = 0x1
693 04:37:34.838135 ===================================
694 04:37:34.842160 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 04:37:34.844833 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 04:37:34.848436 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 04:37:34.851590 ===================================
698 04:37:34.855154 LPDDR4 DRAM CONFIGURATION
699 04:37:34.858301 ===================================
700 04:37:34.861745 EX_ROW_EN[0] = 0x10
701 04:37:34.861940 EX_ROW_EN[1] = 0x0
702 04:37:34.865433 LP4Y_EN = 0x0
703 04:37:34.865576 WORK_FSP = 0x0
704 04:37:34.868356 WL = 0x2
705 04:37:34.868440 RL = 0x2
706 04:37:34.872133 BL = 0x2
707 04:37:34.872254 RPST = 0x0
708 04:37:34.875473 RD_PRE = 0x0
709 04:37:34.875596 WR_PRE = 0x1
710 04:37:34.878617 WR_PST = 0x0
711 04:37:34.878733 DBI_WR = 0x0
712 04:37:34.881806 DBI_RD = 0x0
713 04:37:34.881912 OTF = 0x1
714 04:37:34.885359 ===================================
715 04:37:34.892065 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 04:37:34.896865 nWR fixed to 40
717 04:37:34.900025 [ModeRegInit_LP4] CH0 RK0
718 04:37:34.900142 [ModeRegInit_LP4] CH0 RK1
719 04:37:34.903452 [ModeRegInit_LP4] CH1 RK0
720 04:37:34.906694 [ModeRegInit_LP4] CH1 RK1
721 04:37:34.906802 match AC timing 13
722 04:37:34.914116 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 04:37:34.916846 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 04:37:34.920327 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 04:37:34.926802 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 04:37:34.930349 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 04:37:34.930457 [EMI DOE] emi_dcm 0
728 04:37:34.936961 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 04:37:34.937043 ==
730 04:37:34.940431 Dram Type= 6, Freq= 0, CH_0, rank 0
731 04:37:34.943450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 04:37:34.943564 ==
733 04:37:34.950269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 04:37:34.953984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 04:37:34.964364 [CA 0] Center 37 (7~68) winsize 62
736 04:37:34.967614 [CA 1] Center 37 (6~68) winsize 63
737 04:37:34.970557 [CA 2] Center 35 (5~66) winsize 62
738 04:37:34.974188 [CA 3] Center 34 (4~65) winsize 62
739 04:37:34.977383 [CA 4] Center 34 (3~65) winsize 63
740 04:37:34.980859 [CA 5] Center 33 (3~64) winsize 62
741 04:37:34.980939
742 04:37:34.984531 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 04:37:34.984646
744 04:37:34.987492 [CATrainingPosCal] consider 1 rank data
745 04:37:34.991104 u2DelayCellTimex100 = 270/100 ps
746 04:37:34.994465 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
747 04:37:34.997481 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
748 04:37:35.004639 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
749 04:37:35.007973 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
750 04:37:35.011009 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
751 04:37:35.014583 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 04:37:35.014665
753 04:37:35.017731 CA PerBit enable=1, Macro0, CA PI delay=33
754 04:37:35.017818
755 04:37:35.021413 [CBTSetCACLKResult] CA Dly = 33
756 04:37:35.021492 CS Dly: 5 (0~36)
757 04:37:35.021558 ==
758 04:37:35.024877 Dram Type= 6, Freq= 0, CH_0, rank 1
759 04:37:35.031129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 04:37:35.031215 ==
761 04:37:35.034705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 04:37:35.041424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 04:37:35.050366 [CA 0] Center 37 (7~68) winsize 62
764 04:37:35.053943 [CA 1] Center 37 (6~68) winsize 63
765 04:37:35.056868 [CA 2] Center 35 (5~66) winsize 62
766 04:37:35.060337 [CA 3] Center 35 (4~66) winsize 63
767 04:37:35.063627 [CA 4] Center 34 (4~65) winsize 62
768 04:37:35.067156 [CA 5] Center 33 (3~64) winsize 62
769 04:37:35.067272
770 04:37:35.070246 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 04:37:35.070347
772 04:37:35.073957 [CATrainingPosCal] consider 2 rank data
773 04:37:35.077104 u2DelayCellTimex100 = 270/100 ps
774 04:37:35.080755 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 04:37:35.084350 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
776 04:37:35.090883 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
777 04:37:35.094016 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 04:37:35.097447 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
779 04:37:35.100654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 04:37:35.100759
781 04:37:35.104107 CA PerBit enable=1, Macro0, CA PI delay=33
782 04:37:35.104189
783 04:37:35.107714 [CBTSetCACLKResult] CA Dly = 33
784 04:37:35.107797 CS Dly: 5 (0~37)
785 04:37:35.107863
786 04:37:35.110751 ----->DramcWriteLeveling(PI) begin...
787 04:37:35.110836 ==
788 04:37:35.114429 Dram Type= 6, Freq= 0, CH_0, rank 0
789 04:37:35.117686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 04:37:35.121547 ==
791 04:37:35.121666 Write leveling (Byte 0): 31 => 31
792 04:37:35.125331 Write leveling (Byte 1): 29 => 29
793 04:37:35.129104 DramcWriteLeveling(PI) end<-----
794 04:37:35.129213
795 04:37:35.129336 ==
796 04:37:35.132913 Dram Type= 6, Freq= 0, CH_0, rank 0
797 04:37:35.136394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 04:37:35.136475 ==
799 04:37:35.139407 [Gating] SW mode calibration
800 04:37:35.146943 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 04:37:35.150414 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 04:37:35.157124 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 04:37:35.160513 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 04:37:35.164123 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 04:37:35.170576 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 04:37:35.174127 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:37:35.177519 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:37:35.184234 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 04:37:35.187930 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 04:37:35.190683 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 04:37:35.194152 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 04:37:35.200849 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 04:37:35.204473 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 04:37:35.208234 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 04:37:35.214460 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 04:37:35.218172 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 04:37:35.221765 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 04:37:35.227719 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 04:37:35.231258 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 04:37:35.234700 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
821 04:37:35.241615 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:37:35.244340 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:37:35.248133 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:37:35.251207 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 04:37:35.258148 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 04:37:35.261831 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 04:37:35.264813 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 04:37:35.271359 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 04:37:35.275046 0 9 12 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
830 04:37:35.278029 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 04:37:35.284450 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 04:37:35.288123 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 04:37:35.291386 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 04:37:35.298078 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 04:37:35.301496 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
836 04:37:35.304824 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
837 04:37:35.311758 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
838 04:37:35.315154 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 04:37:35.318199 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 04:37:35.321661 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 04:37:35.328403 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 04:37:35.332070 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 04:37:35.334962 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 04:37:35.341867 0 11 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
845 04:37:35.345017 0 11 12 | B1->B0 | 3636 3f3f | 0 0 | (0 0) (1 1)
846 04:37:35.348447 0 11 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
847 04:37:35.355386 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 04:37:35.358840 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 04:37:35.361932 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 04:37:35.368480 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 04:37:35.372160 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 04:37:35.375294 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
853 04:37:35.382103 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 04:37:35.385616 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 04:37:35.388572 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 04:37:35.392244 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 04:37:35.399133 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 04:37:35.402117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 04:37:35.405334 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 04:37:35.412695 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 04:37:35.415329 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 04:37:35.418888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 04:37:35.425640 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 04:37:35.429359 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 04:37:35.432419 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 04:37:35.439051 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 04:37:35.442640 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 04:37:35.445610 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
869 04:37:35.448913 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 04:37:35.452229 Total UI for P1: 0, mck2ui 16
871 04:37:35.455866 best dqsien dly found for B0: ( 0, 14, 8)
872 04:37:35.459473 Total UI for P1: 0, mck2ui 16
873 04:37:35.462334 best dqsien dly found for B1: ( 0, 14, 10)
874 04:37:35.465842 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
875 04:37:35.469236 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
876 04:37:35.472615
877 04:37:35.475694 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
878 04:37:35.479111 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
879 04:37:35.482692 [Gating] SW calibration Done
880 04:37:35.482799 ==
881 04:37:35.485768 Dram Type= 6, Freq= 0, CH_0, rank 0
882 04:37:35.489338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 04:37:35.489458 ==
884 04:37:35.489555 RX Vref Scan: 0
885 04:37:35.489660
886 04:37:35.492475 RX Vref 0 -> 0, step: 1
887 04:37:35.492560
888 04:37:35.496119 RX Delay -130 -> 252, step: 16
889 04:37:35.499179 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
890 04:37:35.502766 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
891 04:37:35.506228 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
892 04:37:35.513073 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
893 04:37:35.516477 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
894 04:37:35.519517 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
895 04:37:35.523026 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
896 04:37:35.526619 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
897 04:37:35.532936 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
898 04:37:35.536611 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
899 04:37:35.539566 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
900 04:37:35.543152 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
901 04:37:35.546682 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
902 04:37:35.553244 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
903 04:37:35.556576 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
904 04:37:35.559767 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
905 04:37:35.559893 ==
906 04:37:35.563350 Dram Type= 6, Freq= 0, CH_0, rank 0
907 04:37:35.566788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 04:37:35.566868 ==
909 04:37:35.569753 DQS Delay:
910 04:37:35.569834 DQS0 = 0, DQS1 = 0
911 04:37:35.573391 DQM Delay:
912 04:37:35.573467 DQM0 = 85, DQM1 = 79
913 04:37:35.573533 DQ Delay:
914 04:37:35.576705 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
915 04:37:35.579915 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
916 04:37:35.583377 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
917 04:37:35.586918 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
918 04:37:35.587027
919 04:37:35.587122
920 04:37:35.587213 ==
921 04:37:35.590417 Dram Type= 6, Freq= 0, CH_0, rank 0
922 04:37:35.596532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 04:37:35.596617 ==
924 04:37:35.596693
925 04:37:35.596757
926 04:37:35.596817 TX Vref Scan disable
927 04:37:35.600106 == TX Byte 0 ==
928 04:37:35.603669 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
929 04:37:35.607391 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
930 04:37:35.610235 == TX Byte 1 ==
931 04:37:35.613846 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
932 04:37:35.616962 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
933 04:37:35.620581 ==
934 04:37:35.623572 Dram Type= 6, Freq= 0, CH_0, rank 0
935 04:37:35.627233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 04:37:35.627342 ==
937 04:37:35.639408 TX Vref=22, minBit 5, minWin=27, winSum=442
938 04:37:35.643150 TX Vref=24, minBit 7, minWin=27, winSum=444
939 04:37:35.646661 TX Vref=26, minBit 7, minWin=27, winSum=446
940 04:37:35.649748 TX Vref=28, minBit 5, minWin=27, winSum=455
941 04:37:35.653408 TX Vref=30, minBit 3, minWin=28, winSum=457
942 04:37:35.656338 TX Vref=32, minBit 3, minWin=28, winSum=457
943 04:37:35.663364 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 30
944 04:37:35.663449
945 04:37:35.666861 Final TX Range 1 Vref 30
946 04:37:35.666946
947 04:37:35.667014 ==
948 04:37:35.669942 Dram Type= 6, Freq= 0, CH_0, rank 0
949 04:37:35.673115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 04:37:35.673199 ==
951 04:37:35.673266
952 04:37:35.673327
953 04:37:35.676551 TX Vref Scan disable
954 04:37:35.680121 == TX Byte 0 ==
955 04:37:35.683127 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
956 04:37:35.686688 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
957 04:37:35.689816 == TX Byte 1 ==
958 04:37:35.693666 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
959 04:37:35.696441 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
960 04:37:35.696547
961 04:37:35.700102 [DATLAT]
962 04:37:35.700206 Freq=800, CH0 RK0
963 04:37:35.700314
964 04:37:35.703659 DATLAT Default: 0xa
965 04:37:35.703780 0, 0xFFFF, sum = 0
966 04:37:35.706689 1, 0xFFFF, sum = 0
967 04:37:35.706801 2, 0xFFFF, sum = 0
968 04:37:35.710267 3, 0xFFFF, sum = 0
969 04:37:35.710396 4, 0xFFFF, sum = 0
970 04:37:35.713341 5, 0xFFFF, sum = 0
971 04:37:35.713421 6, 0xFFFF, sum = 0
972 04:37:35.716904 7, 0xFFFF, sum = 0
973 04:37:35.717028 8, 0xFFFF, sum = 0
974 04:37:35.719988 9, 0x0, sum = 1
975 04:37:35.720067 10, 0x0, sum = 2
976 04:37:35.723558 11, 0x0, sum = 3
977 04:37:35.723674 12, 0x0, sum = 4
978 04:37:35.727106 best_step = 10
979 04:37:35.727203
980 04:37:35.727267 ==
981 04:37:35.730195 Dram Type= 6, Freq= 0, CH_0, rank 0
982 04:37:35.733655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 04:37:35.733779 ==
984 04:37:35.733875 RX Vref Scan: 1
985 04:37:35.736813
986 04:37:35.736896 Set Vref Range= 32 -> 127
987 04:37:35.736960
988 04:37:35.740332 RX Vref 32 -> 127, step: 1
989 04:37:35.740426
990 04:37:35.744068 RX Delay -95 -> 252, step: 8
991 04:37:35.744143
992 04:37:35.746809 Set Vref, RX VrefLevel [Byte0]: 32
993 04:37:35.750566 [Byte1]: 32
994 04:37:35.750651
995 04:37:35.754351 Set Vref, RX VrefLevel [Byte0]: 33
996 04:37:35.757886 [Byte1]: 33
997 04:37:35.757997
998 04:37:35.761618 Set Vref, RX VrefLevel [Byte0]: 34
999 04:37:35.764495 [Byte1]: 34
1000 04:37:35.764601
1001 04:37:35.768020 Set Vref, RX VrefLevel [Byte0]: 35
1002 04:37:35.770893 [Byte1]: 35
1003 04:37:35.774905
1004 04:37:35.774988 Set Vref, RX VrefLevel [Byte0]: 36
1005 04:37:35.778668 [Byte1]: 36
1006 04:37:35.782493
1007 04:37:35.782571 Set Vref, RX VrefLevel [Byte0]: 37
1008 04:37:35.786492 [Byte1]: 37
1009 04:37:35.790942
1010 04:37:35.791041 Set Vref, RX VrefLevel [Byte0]: 38
1011 04:37:35.794003 [Byte1]: 38
1012 04:37:35.797946
1013 04:37:35.798027 Set Vref, RX VrefLevel [Byte0]: 39
1014 04:37:35.801597 [Byte1]: 39
1015 04:37:35.805688
1016 04:37:35.805796 Set Vref, RX VrefLevel [Byte0]: 40
1017 04:37:35.808905 [Byte1]: 40
1018 04:37:35.813426
1019 04:37:35.813524 Set Vref, RX VrefLevel [Byte0]: 41
1020 04:37:35.816504 [Byte1]: 41
1021 04:37:35.821269
1022 04:37:35.821350 Set Vref, RX VrefLevel [Byte0]: 42
1023 04:37:35.824890 [Byte1]: 42
1024 04:37:35.828423
1025 04:37:35.828508 Set Vref, RX VrefLevel [Byte0]: 43
1026 04:37:35.831384 [Byte1]: 43
1027 04:37:35.836062
1028 04:37:35.836143 Set Vref, RX VrefLevel [Byte0]: 44
1029 04:37:35.839184 [Byte1]: 44
1030 04:37:35.843266
1031 04:37:35.843345 Set Vref, RX VrefLevel [Byte0]: 45
1032 04:37:35.846903 [Byte1]: 45
1033 04:37:35.850962
1034 04:37:35.851059 Set Vref, RX VrefLevel [Byte0]: 46
1035 04:37:35.854700 [Byte1]: 46
1036 04:37:35.858916
1037 04:37:35.859013 Set Vref, RX VrefLevel [Byte0]: 47
1038 04:37:35.861674 [Byte1]: 47
1039 04:37:35.866386
1040 04:37:35.866484 Set Vref, RX VrefLevel [Byte0]: 48
1041 04:37:35.869723 [Byte1]: 48
1042 04:37:35.873827
1043 04:37:35.873936 Set Vref, RX VrefLevel [Byte0]: 49
1044 04:37:35.877359 [Byte1]: 49
1045 04:37:35.881478
1046 04:37:35.881556 Set Vref, RX VrefLevel [Byte0]: 50
1047 04:37:35.884998 [Byte1]: 50
1048 04:37:35.889136
1049 04:37:35.889248 Set Vref, RX VrefLevel [Byte0]: 51
1050 04:37:35.892318 [Byte1]: 51
1051 04:37:35.896470
1052 04:37:35.896579 Set Vref, RX VrefLevel [Byte0]: 52
1053 04:37:35.900156 [Byte1]: 52
1054 04:37:35.904394
1055 04:37:35.904483 Set Vref, RX VrefLevel [Byte0]: 53
1056 04:37:35.907405 [Byte1]: 53
1057 04:37:35.912111
1058 04:37:35.912207 Set Vref, RX VrefLevel [Byte0]: 54
1059 04:37:35.915066 [Byte1]: 54
1060 04:37:35.919529
1061 04:37:35.919609 Set Vref, RX VrefLevel [Byte0]: 55
1062 04:37:35.922486 [Byte1]: 55
1063 04:37:35.927209
1064 04:37:35.927289 Set Vref, RX VrefLevel [Byte0]: 56
1065 04:37:35.930165 [Byte1]: 56
1066 04:37:35.934368
1067 04:37:35.934448 Set Vref, RX VrefLevel [Byte0]: 57
1068 04:37:35.938041 [Byte1]: 57
1069 04:37:35.942086
1070 04:37:35.942164 Set Vref, RX VrefLevel [Byte0]: 58
1071 04:37:35.946026 [Byte1]: 58
1072 04:37:35.950058
1073 04:37:35.950137 Set Vref, RX VrefLevel [Byte0]: 59
1074 04:37:35.952818 [Byte1]: 59
1075 04:37:35.957590
1076 04:37:35.957669 Set Vref, RX VrefLevel [Byte0]: 60
1077 04:37:35.961131 [Byte1]: 60
1078 04:37:35.964777
1079 04:37:35.964885 Set Vref, RX VrefLevel [Byte0]: 61
1080 04:37:35.968141 [Byte1]: 61
1081 04:37:35.972841
1082 04:37:35.972943 Set Vref, RX VrefLevel [Byte0]: 62
1083 04:37:35.975742 [Byte1]: 62
1084 04:37:35.979881
1085 04:37:35.979960 Set Vref, RX VrefLevel [Byte0]: 63
1086 04:37:35.983472 [Byte1]: 63
1087 04:37:35.987553
1088 04:37:35.987652 Set Vref, RX VrefLevel [Byte0]: 64
1089 04:37:35.991319 [Byte1]: 64
1090 04:37:35.995222
1091 04:37:35.995323 Set Vref, RX VrefLevel [Byte0]: 65
1092 04:37:35.998809 [Byte1]: 65
1093 04:37:36.002768
1094 04:37:36.002847 Set Vref, RX VrefLevel [Byte0]: 66
1095 04:37:36.006366 [Byte1]: 66
1096 04:37:36.010877
1097 04:37:36.010962 Set Vref, RX VrefLevel [Byte0]: 67
1098 04:37:36.013819 [Byte1]: 67
1099 04:37:36.018342
1100 04:37:36.018464 Set Vref, RX VrefLevel [Byte0]: 68
1101 04:37:36.021770 [Byte1]: 68
1102 04:37:36.025424
1103 04:37:36.025508 Set Vref, RX VrefLevel [Byte0]: 69
1104 04:37:36.028958 [Byte1]: 69
1105 04:37:36.033230
1106 04:37:36.033348 Set Vref, RX VrefLevel [Byte0]: 70
1107 04:37:36.036512 [Byte1]: 70
1108 04:37:36.040958
1109 04:37:36.041070 Set Vref, RX VrefLevel [Byte0]: 71
1110 04:37:36.043878 [Byte1]: 71
1111 04:37:36.048327
1112 04:37:36.048429 Set Vref, RX VrefLevel [Byte0]: 72
1113 04:37:36.051760 [Byte1]: 72
1114 04:37:36.055769
1115 04:37:36.055857 Set Vref, RX VrefLevel [Byte0]: 73
1116 04:37:36.059430 [Byte1]: 73
1117 04:37:36.063434
1118 04:37:36.063531 Set Vref, RX VrefLevel [Byte0]: 74
1119 04:37:36.067006 [Byte1]: 74
1120 04:37:36.071217
1121 04:37:36.071314 Set Vref, RX VrefLevel [Byte0]: 75
1122 04:37:36.074950 [Byte1]: 75
1123 04:37:36.079097
1124 04:37:36.079186 Final RX Vref Byte 0 = 61 to rank0
1125 04:37:36.082192 Final RX Vref Byte 1 = 59 to rank0
1126 04:37:36.085296 Final RX Vref Byte 0 = 61 to rank1
1127 04:37:36.088792 Final RX Vref Byte 1 = 59 to rank1==
1128 04:37:36.092240 Dram Type= 6, Freq= 0, CH_0, rank 0
1129 04:37:36.095437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 04:37:36.098901 ==
1131 04:37:36.099035 DQS Delay:
1132 04:37:36.099182 DQS0 = 0, DQS1 = 0
1133 04:37:36.102380 DQM Delay:
1134 04:37:36.102454 DQM0 = 86, DQM1 = 79
1135 04:37:36.105757 DQ Delay:
1136 04:37:36.105845 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1137 04:37:36.109010 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1138 04:37:36.112774 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1139 04:37:36.115463 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1140 04:37:36.115579
1141 04:37:36.119543
1142 04:37:36.125578 [DQSOSCAuto] RK0, (LSB)MR18= 0x240a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 400 ps
1143 04:37:36.129345 CH0 RK0: MR19=606, MR18=240A
1144 04:37:36.135944 CH0_RK0: MR19=0x606, MR18=0x240A, DQSOSC=400, MR23=63, INC=92, DEC=61
1145 04:37:36.136027
1146 04:37:36.139425 ----->DramcWriteLeveling(PI) begin...
1147 04:37:36.139509 ==
1148 04:37:36.142985 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 04:37:36.146131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 04:37:36.146214 ==
1151 04:37:36.149767 Write leveling (Byte 0): 29 => 29
1152 04:37:36.152951 Write leveling (Byte 1): 28 => 28
1153 04:37:36.156438 DramcWriteLeveling(PI) end<-----
1154 04:37:36.156519
1155 04:37:36.156584 ==
1156 04:37:36.159579 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 04:37:36.163163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 04:37:36.163247 ==
1159 04:37:36.166340 [Gating] SW mode calibration
1160 04:37:36.173152 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1161 04:37:36.176826 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1162 04:37:36.183393 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 04:37:36.186449 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1164 04:37:36.190159 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1165 04:37:36.197037 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 04:37:36.240369 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 04:37:36.240715 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 04:37:36.240797 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 04:37:36.241103 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 04:37:36.241174 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 04:37:36.241432 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 04:37:36.241494 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 04:37:36.241552 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 04:37:36.241618 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 04:37:36.241702 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 04:37:36.284547 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 04:37:36.285194 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 04:37:36.285307 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1179 04:37:36.285585 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1180 04:37:36.285655 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1181 04:37:36.286256 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1182 04:37:36.286797 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 04:37:36.286900 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 04:37:36.287512 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 04:37:36.287809 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 04:37:36.303835 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 04:37:36.304449 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 04:37:36.304556 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1189 04:37:36.304835 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1190 04:37:36.307735 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 04:37:36.311325 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 04:37:36.314331 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 04:37:36.317807 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 04:37:36.324749 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 04:37:36.327593 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1196 04:37:36.331153 0 10 8 | B1->B0 | 2f2f 2525 | 1 1 | (1 0) (1 0)
1197 04:37:36.334406 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1198 04:37:36.341485 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 04:37:36.344858 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 04:37:36.348025 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 04:37:36.354677 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 04:37:36.358698 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 04:37:36.361633 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1204 04:37:36.368714 0 11 8 | B1->B0 | 2c2c 3e3e | 0 0 | (0 0) (0 0)
1205 04:37:36.372569 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1206 04:37:36.376110 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 04:37:36.380028 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 04:37:36.383751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 04:37:36.387013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 04:37:36.394365 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 04:37:36.397840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1212 04:37:36.400874 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1213 04:37:36.408116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 04:37:36.411077 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 04:37:36.414436 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 04:37:36.417957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 04:37:36.424349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 04:37:36.428000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 04:37:36.431158 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 04:37:36.437821 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 04:37:36.441389 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 04:37:36.444776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 04:37:36.451547 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 04:37:36.454644 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 04:37:36.457924 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 04:37:36.464820 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 04:37:36.468014 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1228 04:37:36.471619 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1229 04:37:36.474595 Total UI for P1: 0, mck2ui 16
1230 04:37:36.478182 best dqsien dly found for B0: ( 0, 14, 4)
1231 04:37:36.481742 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 04:37:36.485177 Total UI for P1: 0, mck2ui 16
1233 04:37:36.488394 best dqsien dly found for B1: ( 0, 14, 10)
1234 04:37:36.491859 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1235 04:37:36.498550 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1236 04:37:36.498632
1237 04:37:36.501550 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1238 04:37:36.504997 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1239 04:37:36.508243 [Gating] SW calibration Done
1240 04:37:36.508378 ==
1241 04:37:36.511843 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 04:37:36.514898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1243 04:37:36.514999 ==
1244 04:37:36.515065 RX Vref Scan: 0
1245 04:37:36.515141
1246 04:37:36.518673 RX Vref 0 -> 0, step: 1
1247 04:37:36.518799
1248 04:37:36.521720 RX Delay -130 -> 252, step: 16
1249 04:37:36.525171 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1250 04:37:36.528549 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1251 04:37:36.535220 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1252 04:37:36.538763 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1253 04:37:36.542369 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1254 04:37:36.545443 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1255 04:37:36.549095 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1256 04:37:36.552193 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1257 04:37:36.558801 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1258 04:37:36.562353 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1259 04:37:36.565748 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1260 04:37:36.568732 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1261 04:37:36.572347 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1262 04:37:36.579184 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1263 04:37:36.582353 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1264 04:37:36.585689 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1265 04:37:36.585796 ==
1266 04:37:36.589320 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 04:37:36.592653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 04:37:36.592750 ==
1269 04:37:36.595732 DQS Delay:
1270 04:37:36.595840 DQS0 = 0, DQS1 = 0
1271 04:37:36.599230 DQM Delay:
1272 04:37:36.599333 DQM0 = 87, DQM1 = 76
1273 04:37:36.599425 DQ Delay:
1274 04:37:36.602712 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1275 04:37:36.605752 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1276 04:37:36.609067 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1277 04:37:36.612793 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1278 04:37:36.612868
1279 04:37:36.612932
1280 04:37:36.615732 ==
1281 04:37:36.615804 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 04:37:36.622718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 04:37:36.622837 ==
1284 04:37:36.622934
1285 04:37:36.623025
1286 04:37:36.623117 TX Vref Scan disable
1287 04:37:36.626606 == TX Byte 0 ==
1288 04:37:36.630147 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1289 04:37:36.633520 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1290 04:37:36.637125 == TX Byte 1 ==
1291 04:37:36.639931 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1292 04:37:36.643706 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1293 04:37:36.646711 ==
1294 04:37:36.649888 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 04:37:36.653410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 04:37:36.653486 ==
1297 04:37:36.665558 TX Vref=22, minBit 2, minWin=27, winSum=441
1298 04:37:36.668972 TX Vref=24, minBit 2, minWin=27, winSum=442
1299 04:37:36.672869 TX Vref=26, minBit 12, minWin=27, winSum=448
1300 04:37:36.676029 TX Vref=28, minBit 0, minWin=28, winSum=453
1301 04:37:36.679543 TX Vref=30, minBit 0, minWin=28, winSum=454
1302 04:37:36.682780 TX Vref=32, minBit 0, minWin=28, winSum=451
1303 04:37:36.689176 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1304 04:37:36.689259
1305 04:37:36.692935 Final TX Range 1 Vref 30
1306 04:37:36.693018
1307 04:37:36.693091 ==
1308 04:37:36.696311 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 04:37:36.699235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 04:37:36.699319 ==
1311 04:37:36.699414
1312 04:37:36.699479
1313 04:37:36.702701 TX Vref Scan disable
1314 04:37:36.705816 == TX Byte 0 ==
1315 04:37:36.709261 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1316 04:37:36.712808 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1317 04:37:36.716005 == TX Byte 1 ==
1318 04:37:36.719538 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1319 04:37:36.723268 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1320 04:37:36.723349
1321 04:37:36.726207 [DATLAT]
1322 04:37:36.726287 Freq=800, CH0 RK1
1323 04:37:36.726351
1324 04:37:36.729623 DATLAT Default: 0xa
1325 04:37:36.729703 0, 0xFFFF, sum = 0
1326 04:37:36.733150 1, 0xFFFF, sum = 0
1327 04:37:36.733232 2, 0xFFFF, sum = 0
1328 04:37:36.736249 3, 0xFFFF, sum = 0
1329 04:37:36.736330 4, 0xFFFF, sum = 0
1330 04:37:36.739666 5, 0xFFFF, sum = 0
1331 04:37:36.739782 6, 0xFFFF, sum = 0
1332 04:37:36.743374 7, 0xFFFF, sum = 0
1333 04:37:36.743455 8, 0xFFFF, sum = 0
1334 04:37:36.746279 9, 0x0, sum = 1
1335 04:37:36.746391 10, 0x0, sum = 2
1336 04:37:36.749708 11, 0x0, sum = 3
1337 04:37:36.749789 12, 0x0, sum = 4
1338 04:37:36.753619 best_step = 10
1339 04:37:36.753699
1340 04:37:36.753772 ==
1341 04:37:36.756406 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 04:37:36.759754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 04:37:36.759834 ==
1344 04:37:36.759897 RX Vref Scan: 0
1345 04:37:36.759956
1346 04:37:36.763095 RX Vref 0 -> 0, step: 1
1347 04:37:36.763175
1348 04:37:36.766926 RX Delay -95 -> 252, step: 8
1349 04:37:36.769908 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1350 04:37:36.776772 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1351 04:37:36.779731 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1352 04:37:36.783537 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1353 04:37:36.786654 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1354 04:37:36.790116 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1355 04:37:36.797199 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1356 04:37:36.800141 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1357 04:37:36.803448 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1358 04:37:36.806536 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1359 04:37:36.810060 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1360 04:37:36.813612 iDelay=209, Bit 11, Center 72 (-31 ~ 176) 208
1361 04:37:36.820465 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1362 04:37:36.823794 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1363 04:37:36.826685 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1364 04:37:36.830458 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1365 04:37:36.830537 ==
1366 04:37:36.833408 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 04:37:36.840488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 04:37:36.840568 ==
1369 04:37:36.840632 DQS Delay:
1370 04:37:36.843811 DQS0 = 0, DQS1 = 0
1371 04:37:36.843890 DQM Delay:
1372 04:37:36.843953 DQM0 = 87, DQM1 = 78
1373 04:37:36.846807 DQ Delay:
1374 04:37:36.850730 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1375 04:37:36.853728 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1376 04:37:36.853808 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1377 04:37:36.860596 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1378 04:37:36.860735
1379 04:37:36.860800
1380 04:37:36.867002 [DQSOSCAuto] RK1, (LSB)MR18= 0x321c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1381 04:37:36.871042 CH0 RK1: MR19=606, MR18=321C
1382 04:37:36.877200 CH0_RK1: MR19=0x606, MR18=0x321C, DQSOSC=397, MR23=63, INC=93, DEC=62
1383 04:37:36.880404 [RxdqsGatingPostProcess] freq 800
1384 04:37:36.883589 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1385 04:37:36.887181 Pre-setting of DQS Precalculation
1386 04:37:36.893861 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1387 04:37:36.893969 ==
1388 04:37:36.897583 Dram Type= 6, Freq= 0, CH_1, rank 0
1389 04:37:36.900897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 04:37:36.900979 ==
1391 04:37:36.907168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 04:37:36.910553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 04:37:36.920797 [CA 0] Center 36 (6~66) winsize 61
1394 04:37:36.924322 [CA 1] Center 36 (6~66) winsize 61
1395 04:37:36.927132 [CA 2] Center 34 (4~65) winsize 62
1396 04:37:36.930704 [CA 3] Center 33 (3~64) winsize 62
1397 04:37:36.933993 [CA 4] Center 34 (4~65) winsize 62
1398 04:37:36.937542 [CA 5] Center 33 (3~64) winsize 62
1399 04:37:36.937621
1400 04:37:36.940475 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1401 04:37:36.940584
1402 04:37:36.944087 [CATrainingPosCal] consider 1 rank data
1403 04:37:36.947366 u2DelayCellTimex100 = 270/100 ps
1404 04:37:36.950388 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1405 04:37:36.953882 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1406 04:37:36.957645 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1407 04:37:36.963787 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1408 04:37:36.967360 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1409 04:37:36.970482 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1410 04:37:36.970596
1411 04:37:36.973731 CA PerBit enable=1, Macro0, CA PI delay=33
1412 04:37:36.973814
1413 04:37:36.977647 [CBTSetCACLKResult] CA Dly = 33
1414 04:37:36.977748 CS Dly: 5 (0~36)
1415 04:37:36.977832 ==
1416 04:37:36.980520 Dram Type= 6, Freq= 0, CH_1, rank 1
1417 04:37:36.987791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 04:37:36.987875 ==
1419 04:37:36.990932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 04:37:36.997317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 04:37:37.006788 [CA 0] Center 36 (6~66) winsize 61
1422 04:37:37.010431 [CA 1] Center 36 (6~66) winsize 61
1423 04:37:37.013702 [CA 2] Center 34 (4~65) winsize 62
1424 04:37:37.016647 [CA 3] Center 34 (3~65) winsize 63
1425 04:37:37.020233 [CA 4] Center 34 (4~65) winsize 62
1426 04:37:37.023387 [CA 5] Center 33 (3~64) winsize 62
1427 04:37:37.023470
1428 04:37:37.026645 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1429 04:37:37.026728
1430 04:37:37.030077 [CATrainingPosCal] consider 2 rank data
1431 04:37:37.033252 u2DelayCellTimex100 = 270/100 ps
1432 04:37:37.037356 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1433 04:37:37.041180 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1434 04:37:37.044325 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1435 04:37:37.048392 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1436 04:37:37.051918 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1437 04:37:37.055519 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1438 04:37:37.055603
1439 04:37:37.059774 CA PerBit enable=1, Macro0, CA PI delay=33
1440 04:37:37.059858
1441 04:37:37.063298 [CBTSetCACLKResult] CA Dly = 33
1442 04:37:37.063381 CS Dly: 5 (0~36)
1443 04:37:37.063466
1444 04:37:37.066774 ----->DramcWriteLeveling(PI) begin...
1445 04:37:37.066859 ==
1446 04:37:37.070190 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 04:37:37.077227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 04:37:37.077312 ==
1449 04:37:37.080221 Write leveling (Byte 0): 28 => 28
1450 04:37:37.080306 Write leveling (Byte 1): 28 => 28
1451 04:37:37.083734 DramcWriteLeveling(PI) end<-----
1452 04:37:37.083817
1453 04:37:37.083900 ==
1454 04:37:37.087349 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 04:37:37.094032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 04:37:37.094116 ==
1457 04:37:37.097075 [Gating] SW mode calibration
1458 04:37:37.104152 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1459 04:37:37.107344 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1460 04:37:37.111014 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1461 04:37:37.117749 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1462 04:37:37.120992 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1463 04:37:37.124043 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 04:37:37.130948 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 04:37:37.134491 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 04:37:37.137515 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 04:37:37.144364 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 04:37:37.147783 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 04:37:37.151297 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1470 04:37:37.157786 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 04:37:37.161286 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 04:37:37.164574 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 04:37:37.171318 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 04:37:37.174802 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 04:37:37.177764 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 04:37:37.181135 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 04:37:37.188371 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 04:37:37.191330 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1479 04:37:37.194360 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 04:37:37.201532 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1481 04:37:37.204820 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 04:37:37.207989 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 04:37:37.214695 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 04:37:37.218265 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 04:37:37.221230 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 04:37:37.228502 0 9 8 | B1->B0 | 2424 2323 | 1 1 | (0 0) (1 1)
1487 04:37:37.231763 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 04:37:37.235224 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 04:37:37.238316 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 04:37:37.245050 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 04:37:37.248385 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 04:37:37.251911 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 04:37:37.258833 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 04:37:37.261758 0 10 8 | B1->B0 | 2c2c 3030 | 1 1 | (0 1) (0 1)
1495 04:37:37.265640 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 04:37:37.271795 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 04:37:37.275360 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1498 04:37:37.278862 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 04:37:37.285105 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 04:37:37.288669 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 04:37:37.292314 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1502 04:37:37.295317 0 11 8 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 0)
1503 04:37:37.302147 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 04:37:37.305318 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 04:37:37.308400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 04:37:37.315555 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 04:37:37.318962 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 04:37:37.322073 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 04:37:37.328964 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 04:37:37.331871 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1511 04:37:37.335611 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 04:37:37.342457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 04:37:37.345573 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 04:37:37.348785 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 04:37:37.355892 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 04:37:37.359130 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 04:37:37.362535 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 04:37:37.365564 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 04:37:37.372075 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 04:37:37.375719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 04:37:37.379102 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 04:37:37.385332 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 04:37:37.388826 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 04:37:37.392185 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 04:37:37.399422 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 04:37:37.402554 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 04:37:37.405799 Total UI for P1: 0, mck2ui 16
1528 04:37:37.409073 best dqsien dly found for B0: ( 0, 14, 6)
1529 04:37:37.412727 Total UI for P1: 0, mck2ui 16
1530 04:37:37.415766 best dqsien dly found for B1: ( 0, 14, 6)
1531 04:37:37.419319 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1532 04:37:37.422739 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1533 04:37:37.422824
1534 04:37:37.426058 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1535 04:37:37.429333 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1536 04:37:37.432940 [Gating] SW calibration Done
1537 04:37:37.433012 ==
1538 04:37:37.436127 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 04:37:37.439418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1540 04:37:37.439515 ==
1541 04:37:37.442905 RX Vref Scan: 0
1542 04:37:37.443002
1543 04:37:37.443096 RX Vref 0 -> 0, step: 1
1544 04:37:37.443185
1545 04:37:37.445989 RX Delay -130 -> 252, step: 16
1546 04:37:37.452932 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1547 04:37:37.456293 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1548 04:37:37.459476 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1549 04:37:37.462957 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1550 04:37:37.466237 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1551 04:37:37.469522 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1552 04:37:37.476395 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1553 04:37:37.479727 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1554 04:37:37.482918 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1555 04:37:37.486921 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1556 04:37:37.489894 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1557 04:37:37.496917 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1558 04:37:37.499868 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1559 04:37:37.503533 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1560 04:37:37.506976 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1561 04:37:37.509977 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1562 04:37:37.510058 ==
1563 04:37:37.513537 Dram Type= 6, Freq= 0, CH_1, rank 0
1564 04:37:37.520283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1565 04:37:37.520364 ==
1566 04:37:37.520428 DQS Delay:
1567 04:37:37.523183 DQS0 = 0, DQS1 = 0
1568 04:37:37.523263 DQM Delay:
1569 04:37:37.523327 DQM0 = 83, DQM1 = 77
1570 04:37:37.527000 DQ Delay:
1571 04:37:37.530310 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1572 04:37:37.533671 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1573 04:37:37.537044 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1574 04:37:37.539926 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1575 04:37:37.540007
1576 04:37:37.540070
1577 04:37:37.540129 ==
1578 04:37:37.543660 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 04:37:37.547269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 04:37:37.547350 ==
1581 04:37:37.547414
1582 04:37:37.547472
1583 04:37:37.550286 TX Vref Scan disable
1584 04:37:37.550366 == TX Byte 0 ==
1585 04:37:37.557125 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1586 04:37:37.560581 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1587 04:37:37.560661 == TX Byte 1 ==
1588 04:37:37.566857 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1589 04:37:37.570836 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1590 04:37:37.570917 ==
1591 04:37:37.573626 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 04:37:37.576902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 04:37:37.576982 ==
1594 04:37:37.590810 TX Vref=22, minBit 1, minWin=27, winSum=439
1595 04:37:37.593963 TX Vref=24, minBit 1, minWin=27, winSum=442
1596 04:37:37.597755 TX Vref=26, minBit 0, minWin=27, winSum=443
1597 04:37:37.600580 TX Vref=28, minBit 1, minWin=28, winSum=452
1598 04:37:37.604091 TX Vref=30, minBit 0, minWin=28, winSum=451
1599 04:37:37.607445 TX Vref=32, minBit 1, minWin=28, winSum=456
1600 04:37:37.614122 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 32
1601 04:37:37.614239
1602 04:37:37.617926 Final TX Range 1 Vref 32
1603 04:37:37.618029
1604 04:37:37.618170 ==
1605 04:37:37.621834 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 04:37:37.625794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 04:37:37.625903 ==
1608 04:37:37.625995
1609 04:37:37.626089
1610 04:37:37.628392 TX Vref Scan disable
1611 04:37:37.631853 == TX Byte 0 ==
1612 04:37:37.634891 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1613 04:37:37.638543 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1614 04:37:37.642043 == TX Byte 1 ==
1615 04:37:37.644997 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1616 04:37:37.648440 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1617 04:37:37.648546
1618 04:37:37.648638 [DATLAT]
1619 04:37:37.651687 Freq=800, CH1 RK0
1620 04:37:37.651783
1621 04:37:37.651871 DATLAT Default: 0xa
1622 04:37:37.655189 0, 0xFFFF, sum = 0
1623 04:37:37.658731 1, 0xFFFF, sum = 0
1624 04:37:37.658834 2, 0xFFFF, sum = 0
1625 04:37:37.661974 3, 0xFFFF, sum = 0
1626 04:37:37.662077 4, 0xFFFF, sum = 0
1627 04:37:37.665318 5, 0xFFFF, sum = 0
1628 04:37:37.665423 6, 0xFFFF, sum = 0
1629 04:37:37.668834 7, 0xFFFF, sum = 0
1630 04:37:37.668933 8, 0xFFFF, sum = 0
1631 04:37:37.672249 9, 0x0, sum = 1
1632 04:37:37.672349 10, 0x0, sum = 2
1633 04:37:37.672440 11, 0x0, sum = 3
1634 04:37:37.675219 12, 0x0, sum = 4
1635 04:37:37.675320 best_step = 10
1636 04:37:37.675409
1637 04:37:37.675494 ==
1638 04:37:37.678950 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 04:37:37.685564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 04:37:37.685645 ==
1641 04:37:37.685709 RX Vref Scan: 1
1642 04:37:37.685769
1643 04:37:37.689081 Set Vref Range= 32 -> 127
1644 04:37:37.689192
1645 04:37:37.692411 RX Vref 32 -> 127, step: 1
1646 04:37:37.692491
1647 04:37:37.692555 RX Delay -95 -> 252, step: 8
1648 04:37:37.695799
1649 04:37:37.695878 Set Vref, RX VrefLevel [Byte0]: 32
1650 04:37:37.699070 [Byte1]: 32
1651 04:37:37.703044
1652 04:37:37.703123 Set Vref, RX VrefLevel [Byte0]: 33
1653 04:37:37.706367 [Byte1]: 33
1654 04:37:37.710953
1655 04:37:37.711032 Set Vref, RX VrefLevel [Byte0]: 34
1656 04:37:37.714306 [Byte1]: 34
1657 04:37:37.718598
1658 04:37:37.718679 Set Vref, RX VrefLevel [Byte0]: 35
1659 04:37:37.722004 [Byte1]: 35
1660 04:37:37.726171
1661 04:37:37.726282 Set Vref, RX VrefLevel [Byte0]: 36
1662 04:37:37.729196 [Byte1]: 36
1663 04:37:37.733897
1664 04:37:37.733970 Set Vref, RX VrefLevel [Byte0]: 37
1665 04:37:37.736947 [Byte1]: 37
1666 04:37:37.741587
1667 04:37:37.741694 Set Vref, RX VrefLevel [Byte0]: 38
1668 04:37:37.744733 [Byte1]: 38
1669 04:37:37.748608
1670 04:37:37.748741 Set Vref, RX VrefLevel [Byte0]: 39
1671 04:37:37.752532 [Byte1]: 39
1672 04:37:37.756430
1673 04:37:37.756500 Set Vref, RX VrefLevel [Byte0]: 40
1674 04:37:37.760106 [Byte1]: 40
1675 04:37:37.764073
1676 04:37:37.764142 Set Vref, RX VrefLevel [Byte0]: 41
1677 04:37:37.767687 [Byte1]: 41
1678 04:37:37.771862
1679 04:37:37.771959 Set Vref, RX VrefLevel [Byte0]: 42
1680 04:37:37.775288 [Byte1]: 42
1681 04:37:37.779376
1682 04:37:37.779449 Set Vref, RX VrefLevel [Byte0]: 43
1683 04:37:37.782385 [Byte1]: 43
1684 04:37:37.787100
1685 04:37:37.787180 Set Vref, RX VrefLevel [Byte0]: 44
1686 04:37:37.790029 [Byte1]: 44
1687 04:37:37.794468
1688 04:37:37.794548 Set Vref, RX VrefLevel [Byte0]: 45
1689 04:37:37.798089 [Byte1]: 45
1690 04:37:37.802576
1691 04:37:37.802660 Set Vref, RX VrefLevel [Byte0]: 46
1692 04:37:37.805657 [Byte1]: 46
1693 04:37:37.809540
1694 04:37:37.809617 Set Vref, RX VrefLevel [Byte0]: 47
1695 04:37:37.812773 [Byte1]: 47
1696 04:37:37.817256
1697 04:37:37.817332 Set Vref, RX VrefLevel [Byte0]: 48
1698 04:37:37.820415 [Byte1]: 48
1699 04:37:37.824864
1700 04:37:37.824944 Set Vref, RX VrefLevel [Byte0]: 49
1701 04:37:37.828431 [Byte1]: 49
1702 04:37:37.832628
1703 04:37:37.832745 Set Vref, RX VrefLevel [Byte0]: 50
1704 04:37:37.836035 [Byte1]: 50
1705 04:37:37.840280
1706 04:37:37.840360 Set Vref, RX VrefLevel [Byte0]: 51
1707 04:37:37.843199 [Byte1]: 51
1708 04:37:37.847854
1709 04:37:37.847934 Set Vref, RX VrefLevel [Byte0]: 52
1710 04:37:37.851069 [Byte1]: 52
1711 04:37:37.855009
1712 04:37:37.855088 Set Vref, RX VrefLevel [Byte0]: 53
1713 04:37:37.858495 [Byte1]: 53
1714 04:37:37.862635
1715 04:37:37.862717 Set Vref, RX VrefLevel [Byte0]: 54
1716 04:37:37.866127 [Byte1]: 54
1717 04:37:37.870404
1718 04:37:37.870484 Set Vref, RX VrefLevel [Byte0]: 55
1719 04:37:37.873836 [Byte1]: 55
1720 04:37:37.878316
1721 04:37:37.878396 Set Vref, RX VrefLevel [Byte0]: 56
1722 04:37:37.881453 [Byte1]: 56
1723 04:37:37.885353
1724 04:37:37.885433 Set Vref, RX VrefLevel [Byte0]: 57
1725 04:37:37.889034 [Byte1]: 57
1726 04:37:37.893173
1727 04:37:37.893253 Set Vref, RX VrefLevel [Byte0]: 58
1728 04:37:37.897032 [Byte1]: 58
1729 04:37:37.901116
1730 04:37:37.901196 Set Vref, RX VrefLevel [Byte0]: 59
1731 04:37:37.904233 [Byte1]: 59
1732 04:37:37.908405
1733 04:37:37.908484 Set Vref, RX VrefLevel [Byte0]: 60
1734 04:37:37.911605 [Byte1]: 60
1735 04:37:37.915866
1736 04:37:37.915951 Set Vref, RX VrefLevel [Byte0]: 61
1737 04:37:37.919348 [Byte1]: 61
1738 04:37:37.923360
1739 04:37:37.923439 Set Vref, RX VrefLevel [Byte0]: 62
1740 04:37:37.927109 [Byte1]: 62
1741 04:37:37.931693
1742 04:37:37.931772 Set Vref, RX VrefLevel [Byte0]: 63
1743 04:37:37.934547 [Byte1]: 63
1744 04:37:37.939111
1745 04:37:37.939190 Set Vref, RX VrefLevel [Byte0]: 64
1746 04:37:37.942476 [Byte1]: 64
1747 04:37:37.946568
1748 04:37:37.946648 Set Vref, RX VrefLevel [Byte0]: 65
1749 04:37:37.949563 [Byte1]: 65
1750 04:37:37.953798
1751 04:37:37.953952 Set Vref, RX VrefLevel [Byte0]: 66
1752 04:37:37.957265 [Byte1]: 66
1753 04:37:37.961420
1754 04:37:37.961500 Set Vref, RX VrefLevel [Byte0]: 67
1755 04:37:37.964810 [Byte1]: 67
1756 04:37:37.968982
1757 04:37:37.969064 Set Vref, RX VrefLevel [Byte0]: 68
1758 04:37:37.972455 [Byte1]: 68
1759 04:37:37.976696
1760 04:37:37.976789 Set Vref, RX VrefLevel [Byte0]: 69
1761 04:37:37.980143 [Byte1]: 69
1762 04:37:37.984582
1763 04:37:37.984661 Set Vref, RX VrefLevel [Byte0]: 70
1764 04:37:37.987464 [Byte1]: 70
1765 04:37:37.991836
1766 04:37:37.991916 Set Vref, RX VrefLevel [Byte0]: 71
1767 04:37:37.995710 [Byte1]: 71
1768 04:37:37.999831
1769 04:37:37.999910 Set Vref, RX VrefLevel [Byte0]: 72
1770 04:37:38.002595 [Byte1]: 72
1771 04:37:38.007474
1772 04:37:38.007553 Set Vref, RX VrefLevel [Byte0]: 73
1773 04:37:38.010537 [Byte1]: 73
1774 04:37:38.014760
1775 04:37:38.014840 Set Vref, RX VrefLevel [Byte0]: 74
1776 04:37:38.018138 [Byte1]: 74
1777 04:37:38.022403
1778 04:37:38.022482 Set Vref, RX VrefLevel [Byte0]: 75
1779 04:37:38.025727 [Byte1]: 75
1780 04:37:38.030089
1781 04:37:38.030168 Set Vref, RX VrefLevel [Byte0]: 76
1782 04:37:38.033106 [Byte1]: 76
1783 04:37:38.037468
1784 04:37:38.037548 Set Vref, RX VrefLevel [Byte0]: 77
1785 04:37:38.040980 [Byte1]: 77
1786 04:37:38.045302
1787 04:37:38.045381 Set Vref, RX VrefLevel [Byte0]: 78
1788 04:37:38.048341 [Byte1]: 78
1789 04:37:38.052620
1790 04:37:38.052736 Final RX Vref Byte 0 = 59 to rank0
1791 04:37:38.056259 Final RX Vref Byte 1 = 58 to rank0
1792 04:37:38.059804 Final RX Vref Byte 0 = 59 to rank1
1793 04:37:38.062904 Final RX Vref Byte 1 = 58 to rank1==
1794 04:37:38.066412 Dram Type= 6, Freq= 0, CH_1, rank 0
1795 04:37:38.069561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 04:37:38.072844 ==
1797 04:37:38.072915 DQS Delay:
1798 04:37:38.072975 DQS0 = 0, DQS1 = 0
1799 04:37:38.076515 DQM Delay:
1800 04:37:38.076594 DQM0 = 83, DQM1 = 73
1801 04:37:38.079346 DQ Delay:
1802 04:37:38.079426 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1803 04:37:38.082811 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1804 04:37:38.086271 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =72
1805 04:37:38.089941 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1806 04:37:38.090021
1807 04:37:38.093386
1808 04:37:38.099760 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1809 04:37:38.103110 CH1 RK0: MR19=605, MR18=26FB
1810 04:37:38.109556 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1811 04:37:38.109637
1812 04:37:38.113283 ----->DramcWriteLeveling(PI) begin...
1813 04:37:38.113365 ==
1814 04:37:38.116781 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 04:37:38.119686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 04:37:38.119767 ==
1817 04:37:38.123151 Write leveling (Byte 0): 29 => 29
1818 04:37:38.126704 Write leveling (Byte 1): 30 => 30
1819 04:37:38.129879 DramcWriteLeveling(PI) end<-----
1820 04:37:38.129959
1821 04:37:38.130023 ==
1822 04:37:38.133182 Dram Type= 6, Freq= 0, CH_1, rank 1
1823 04:37:38.136423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1824 04:37:38.136504 ==
1825 04:37:38.140014 [Gating] SW mode calibration
1826 04:37:38.146750 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1827 04:37:38.153052 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1828 04:37:38.156444 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1829 04:37:38.159884 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1830 04:37:38.163564 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 04:37:38.170141 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 04:37:38.173535 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 04:37:38.176533 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 04:37:38.183385 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 04:37:38.186729 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1836 04:37:38.190200 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 04:37:38.196849 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 04:37:38.200376 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 04:37:38.203649 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 04:37:38.210233 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1841 04:37:38.213659 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 04:37:38.216810 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1843 04:37:38.223670 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 04:37:38.227146 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (1 1)
1845 04:37:38.230096 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1846 04:37:38.233722 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1847 04:37:38.240161 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 04:37:38.243522 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1849 04:37:38.247152 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 04:37:38.254078 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 04:37:38.257345 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 04:37:38.260565 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 04:37:38.267601 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1854 04:37:38.270761 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1855 04:37:38.273724 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1856 04:37:38.277328 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 04:37:38.284371 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 04:37:38.287406 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 04:37:38.290733 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1860 04:37:38.297233 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1861 04:37:38.300801 0 10 4 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)
1862 04:37:38.304249 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 04:37:38.310879 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 04:37:38.314123 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 04:37:38.317404 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 04:37:38.324164 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 04:37:38.327721 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 04:37:38.331232 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 04:37:38.337688 0 11 4 | B1->B0 | 2b2b 3333 | 1 0 | (0 0) (0 0)
1870 04:37:38.340874 0 11 8 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
1871 04:37:38.344869 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 04:37:38.347642 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 04:37:38.354438 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 04:37:38.357870 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 04:37:38.361314 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 04:37:38.368073 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1877 04:37:38.371445 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1878 04:37:38.374511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 04:37:38.381388 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 04:37:38.384909 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 04:37:38.388313 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 04:37:38.394806 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 04:37:38.398276 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 04:37:38.401867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 04:37:38.404676 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 04:37:38.411790 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 04:37:38.415451 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 04:37:38.418285 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 04:37:38.425437 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 04:37:38.428402 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 04:37:38.431684 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 04:37:38.438662 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 04:37:38.442031 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1894 04:37:38.445359 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 04:37:38.448590 Total UI for P1: 0, mck2ui 16
1896 04:37:38.451747 best dqsien dly found for B0: ( 0, 14, 4)
1897 04:37:38.455107 Total UI for P1: 0, mck2ui 16
1898 04:37:38.458559 best dqsien dly found for B1: ( 0, 14, 4)
1899 04:37:38.462082 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1900 04:37:38.465293 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1901 04:37:38.465374
1902 04:37:38.468647 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1903 04:37:38.472296 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1904 04:37:38.475689 [Gating] SW calibration Done
1905 04:37:38.475771 ==
1906 04:37:38.478909 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 04:37:38.485513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 04:37:38.485607 ==
1909 04:37:38.485717 RX Vref Scan: 0
1910 04:37:38.485779
1911 04:37:38.489017 RX Vref 0 -> 0, step: 1
1912 04:37:38.489098
1913 04:37:38.492008 RX Delay -130 -> 252, step: 16
1914 04:37:38.495887 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1915 04:37:38.499300 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1916 04:37:38.502091 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1917 04:37:38.505733 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1918 04:37:38.512671 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1919 04:37:38.515533 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1920 04:37:38.519497 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1921 04:37:38.522448 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1922 04:37:38.526037 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1923 04:37:38.529312 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1924 04:37:38.535739 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1925 04:37:38.539124 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1926 04:37:38.542719 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1927 04:37:38.545749 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1928 04:37:38.549256 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1929 04:37:38.556342 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1930 04:37:38.556424 ==
1931 04:37:38.559502 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 04:37:38.562783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 04:37:38.562865 ==
1934 04:37:38.562929 DQS Delay:
1935 04:37:38.566130 DQS0 = 0, DQS1 = 0
1936 04:37:38.566232 DQM Delay:
1937 04:37:38.569924 DQM0 = 82, DQM1 = 78
1938 04:37:38.570005 DQ Delay:
1939 04:37:38.573082 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1940 04:37:38.576043 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1941 04:37:38.579669 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1942 04:37:38.582970 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1943 04:37:38.583052
1944 04:37:38.583116
1945 04:37:38.583175 ==
1946 04:37:38.586289 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 04:37:38.589676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 04:37:38.589757 ==
1949 04:37:38.589821
1950 04:37:38.592739
1951 04:37:38.592820 TX Vref Scan disable
1952 04:37:38.596135 == TX Byte 0 ==
1953 04:37:38.599947 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1954 04:37:38.602981 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1955 04:37:38.606490 == TX Byte 1 ==
1956 04:37:38.609665 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1957 04:37:38.613131 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1958 04:37:38.613212 ==
1959 04:37:38.616503 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 04:37:38.622899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 04:37:38.622981 ==
1962 04:37:38.634479 TX Vref=22, minBit 1, minWin=27, winSum=443
1963 04:37:38.637901 TX Vref=24, minBit 0, minWin=27, winSum=445
1964 04:37:38.641264 TX Vref=26, minBit 12, minWin=27, winSum=449
1965 04:37:38.644351 TX Vref=28, minBit 10, minWin=27, winSum=451
1966 04:37:38.647665 TX Vref=30, minBit 1, minWin=27, winSum=452
1967 04:37:38.651426 TX Vref=32, minBit 0, minWin=27, winSum=451
1968 04:37:38.658090 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1969 04:37:38.658196
1970 04:37:38.661942 Final TX Range 1 Vref 30
1971 04:37:38.662016
1972 04:37:38.662076 ==
1973 04:37:38.664683 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 04:37:38.668098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 04:37:38.668173 ==
1976 04:37:38.668235
1977 04:37:38.668294
1978 04:37:38.671217 TX Vref Scan disable
1979 04:37:38.674625 == TX Byte 0 ==
1980 04:37:38.678213 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1981 04:37:38.681340 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1982 04:37:38.684852 == TX Byte 1 ==
1983 04:37:38.688183 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1984 04:37:38.691845 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1985 04:37:38.691926
1986 04:37:38.694597 [DATLAT]
1987 04:37:38.694691 Freq=800, CH1 RK1
1988 04:37:38.694779
1989 04:37:38.698522 DATLAT Default: 0xa
1990 04:37:38.698590 0, 0xFFFF, sum = 0
1991 04:37:38.701568 1, 0xFFFF, sum = 0
1992 04:37:38.701669 2, 0xFFFF, sum = 0
1993 04:37:38.705162 3, 0xFFFF, sum = 0
1994 04:37:38.705233 4, 0xFFFF, sum = 0
1995 04:37:38.708231 5, 0xFFFF, sum = 0
1996 04:37:38.708300 6, 0xFFFF, sum = 0
1997 04:37:38.711794 7, 0xFFFF, sum = 0
1998 04:37:38.711864 8, 0xFFFF, sum = 0
1999 04:37:38.714800 9, 0x0, sum = 1
2000 04:37:38.714868 10, 0x0, sum = 2
2001 04:37:38.718373 11, 0x0, sum = 3
2002 04:37:38.718473 12, 0x0, sum = 4
2003 04:37:38.721381 best_step = 10
2004 04:37:38.721452
2005 04:37:38.721514 ==
2006 04:37:38.724757 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 04:37:38.728595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 04:37:38.728677 ==
2009 04:37:38.731894 RX Vref Scan: 0
2010 04:37:38.731975
2011 04:37:38.732038 RX Vref 0 -> 0, step: 1
2012 04:37:38.732098
2013 04:37:38.735590 RX Delay -95 -> 252, step: 8
2014 04:37:38.738201 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2015 04:37:38.744891 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2016 04:37:38.748196 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2017 04:37:38.751823 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2018 04:37:38.755342 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2019 04:37:38.758693 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2020 04:37:38.765348 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2021 04:37:38.768618 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2022 04:37:38.772013 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2023 04:37:38.775352 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2024 04:37:38.778817 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2025 04:37:38.785382 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2026 04:37:38.788453 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2027 04:37:38.792201 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2028 04:37:38.795108 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2029 04:37:38.798675 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2030 04:37:38.798785 ==
2031 04:37:38.802227 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 04:37:38.808817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 04:37:38.808954 ==
2034 04:37:38.809038 DQS Delay:
2035 04:37:38.812338 DQS0 = 0, DQS1 = 0
2036 04:37:38.812417 DQM Delay:
2037 04:37:38.812480 DQM0 = 80, DQM1 = 75
2038 04:37:38.815473 DQ Delay:
2039 04:37:38.818950 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2040 04:37:38.822469 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2041 04:37:38.825714 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2042 04:37:38.828943 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2043 04:37:38.829024
2044 04:37:38.829102
2045 04:37:38.835871 [DQSOSCAuto] RK1, (LSB)MR18= 0x232f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
2046 04:37:38.839348 CH1 RK1: MR19=606, MR18=232F
2047 04:37:38.845579 CH1_RK1: MR19=0x606, MR18=0x232F, DQSOSC=397, MR23=63, INC=93, DEC=62
2048 04:37:38.849179 [RxdqsGatingPostProcess] freq 800
2049 04:37:38.852151 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2050 04:37:38.856146 Pre-setting of DQS Precalculation
2051 04:37:38.862824 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2052 04:37:38.869222 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2053 04:37:38.875796 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2054 04:37:38.875877
2055 04:37:38.875942
2056 04:37:38.879427 [Calibration Summary] 1600 Mbps
2057 04:37:38.879526 CH 0, Rank 0
2058 04:37:38.882934 SW Impedance : PASS
2059 04:37:38.883032 DUTY Scan : NO K
2060 04:37:38.885719 ZQ Calibration : PASS
2061 04:37:38.889291 Jitter Meter : NO K
2062 04:37:38.889404 CBT Training : PASS
2063 04:37:38.892593 Write leveling : PASS
2064 04:37:38.896079 RX DQS gating : PASS
2065 04:37:38.896192 RX DQ/DQS(RDDQC) : PASS
2066 04:37:38.899538 TX DQ/DQS : PASS
2067 04:37:38.903085 RX DATLAT : PASS
2068 04:37:38.903166 RX DQ/DQS(Engine): PASS
2069 04:37:38.906547 TX OE : NO K
2070 04:37:38.906629 All Pass.
2071 04:37:38.906724
2072 04:37:38.909553 CH 0, Rank 1
2073 04:37:38.909633 SW Impedance : PASS
2074 04:37:38.912600 DUTY Scan : NO K
2075 04:37:38.916162 ZQ Calibration : PASS
2076 04:37:38.916273 Jitter Meter : NO K
2077 04:37:38.919371 CBT Training : PASS
2078 04:37:38.919453 Write leveling : PASS
2079 04:37:38.922988 RX DQS gating : PASS
2080 04:37:38.926082 RX DQ/DQS(RDDQC) : PASS
2081 04:37:38.926163 TX DQ/DQS : PASS
2082 04:37:38.929430 RX DATLAT : PASS
2083 04:37:38.933135 RX DQ/DQS(Engine): PASS
2084 04:37:38.933215 TX OE : NO K
2085 04:37:38.936390 All Pass.
2086 04:37:38.936487
2087 04:37:38.936553 CH 1, Rank 0
2088 04:37:38.939870 SW Impedance : PASS
2089 04:37:38.939965 DUTY Scan : NO K
2090 04:37:38.942865 ZQ Calibration : PASS
2091 04:37:38.946770 Jitter Meter : NO K
2092 04:37:38.946864 CBT Training : PASS
2093 04:37:38.949737 Write leveling : PASS
2094 04:37:38.949832 RX DQS gating : PASS
2095 04:37:38.953091 RX DQ/DQS(RDDQC) : PASS
2096 04:37:38.956606 TX DQ/DQS : PASS
2097 04:37:38.956702 RX DATLAT : PASS
2098 04:37:38.960199 RX DQ/DQS(Engine): PASS
2099 04:37:38.963432 TX OE : NO K
2100 04:37:38.963513 All Pass.
2101 04:37:38.963577
2102 04:37:38.963674 CH 1, Rank 1
2103 04:37:38.966722 SW Impedance : PASS
2104 04:37:38.970148 DUTY Scan : NO K
2105 04:37:38.970231 ZQ Calibration : PASS
2106 04:37:38.973224 Jitter Meter : NO K
2107 04:37:38.976751 CBT Training : PASS
2108 04:37:38.976834 Write leveling : PASS
2109 04:37:38.979824 RX DQS gating : PASS
2110 04:37:38.979907 RX DQ/DQS(RDDQC) : PASS
2111 04:37:38.983350 TX DQ/DQS : PASS
2112 04:37:38.986352 RX DATLAT : PASS
2113 04:37:38.986435 RX DQ/DQS(Engine): PASS
2114 04:37:38.989965 TX OE : NO K
2115 04:37:38.990049 All Pass.
2116 04:37:38.990114
2117 04:37:38.993553 DramC Write-DBI off
2118 04:37:38.996441 PER_BANK_REFRESH: Hybrid Mode
2119 04:37:38.996524 TX_TRACKING: ON
2120 04:37:39.000045 [GetDramInforAfterCalByMRR] Vendor 6.
2121 04:37:39.003398 [GetDramInforAfterCalByMRR] Revision 606.
2122 04:37:39.007094 [GetDramInforAfterCalByMRR] Revision 2 0.
2123 04:37:39.010575 MR0 0x3b3b
2124 04:37:39.010657 MR8 0x5151
2125 04:37:39.013599 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 04:37:39.013727
2127 04:37:39.013825 MR0 0x3b3b
2128 04:37:39.017080 MR8 0x5151
2129 04:37:39.020334 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2130 04:37:39.020417
2131 04:37:39.030584 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2132 04:37:39.034087 [FAST_K] Save calibration result to emmc
2133 04:37:39.037087 [FAST_K] Save calibration result to emmc
2134 04:37:39.037233 dram_init: config_dvfs: 1
2135 04:37:39.043899 dramc_set_vcore_voltage set vcore to 662500
2136 04:37:39.043996 Read voltage for 1200, 2
2137 04:37:39.044061 Vio18 = 0
2138 04:37:39.046917 Vcore = 662500
2139 04:37:39.047014 Vdram = 0
2140 04:37:39.047078 Vddq = 0
2141 04:37:39.050615 Vmddr = 0
2142 04:37:39.054059 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2143 04:37:39.060827 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2144 04:37:39.063729 MEM_TYPE=3, freq_sel=15
2145 04:37:39.063803 sv_algorithm_assistance_LP4_1600
2146 04:37:39.070802 ============ PULL DRAM RESETB DOWN ============
2147 04:37:39.074205 ========== PULL DRAM RESETB DOWN end =========
2148 04:37:39.077628 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2149 04:37:39.080928 ===================================
2150 04:37:39.084276 LPDDR4 DRAM CONFIGURATION
2151 04:37:39.087304 ===================================
2152 04:37:39.090754 EX_ROW_EN[0] = 0x0
2153 04:37:39.090837 EX_ROW_EN[1] = 0x0
2154 04:37:39.094463 LP4Y_EN = 0x0
2155 04:37:39.094572 WORK_FSP = 0x0
2156 04:37:39.097569 WL = 0x4
2157 04:37:39.097652 RL = 0x4
2158 04:37:39.101368 BL = 0x2
2159 04:37:39.101457 RPST = 0x0
2160 04:37:39.104457 RD_PRE = 0x0
2161 04:37:39.104535 WR_PRE = 0x1
2162 04:37:39.107384 WR_PST = 0x0
2163 04:37:39.107466 DBI_WR = 0x0
2164 04:37:39.111115 DBI_RD = 0x0
2165 04:37:39.111197 OTF = 0x1
2166 04:37:39.114179 ===================================
2167 04:37:39.117794 ===================================
2168 04:37:39.121060 ANA top config
2169 04:37:39.124364 ===================================
2170 04:37:39.124468 DLL_ASYNC_EN = 0
2171 04:37:39.127442 ALL_SLAVE_EN = 0
2172 04:37:39.131295 NEW_RANK_MODE = 1
2173 04:37:39.134367 DLL_IDLE_MODE = 1
2174 04:37:39.134451 LP45_APHY_COMB_EN = 1
2175 04:37:39.137529 TX_ODT_DIS = 1
2176 04:37:39.141004 NEW_8X_MODE = 1
2177 04:37:39.144654 ===================================
2178 04:37:39.147882 ===================================
2179 04:37:39.151408 data_rate = 2400
2180 04:37:39.154303 CKR = 1
2181 04:37:39.154412 DQ_P2S_RATIO = 8
2182 04:37:39.157961 ===================================
2183 04:37:39.161346 CA_P2S_RATIO = 8
2184 04:37:39.164780 DQ_CA_OPEN = 0
2185 04:37:39.167883 DQ_SEMI_OPEN = 0
2186 04:37:39.171456 CA_SEMI_OPEN = 0
2187 04:37:39.174915 CA_FULL_RATE = 0
2188 04:37:39.174996 DQ_CKDIV4_EN = 0
2189 04:37:39.178386 CA_CKDIV4_EN = 0
2190 04:37:39.181317 CA_PREDIV_EN = 0
2191 04:37:39.185242 PH8_DLY = 17
2192 04:37:39.188602 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2193 04:37:39.188738 DQ_AAMCK_DIV = 4
2194 04:37:39.191817 CA_AAMCK_DIV = 4
2195 04:37:39.195277 CA_ADMCK_DIV = 4
2196 04:37:39.198743 DQ_TRACK_CA_EN = 0
2197 04:37:39.201438 CA_PICK = 1200
2198 04:37:39.204967 CA_MCKIO = 1200
2199 04:37:39.208559 MCKIO_SEMI = 0
2200 04:37:39.208658 PLL_FREQ = 2366
2201 04:37:39.211638 DQ_UI_PI_RATIO = 32
2202 04:37:39.215122 CA_UI_PI_RATIO = 0
2203 04:37:39.218756 ===================================
2204 04:37:39.221619 ===================================
2205 04:37:39.225415 memory_type:LPDDR4
2206 04:37:39.225490 GP_NUM : 10
2207 04:37:39.228249 SRAM_EN : 1
2208 04:37:39.231800 MD32_EN : 0
2209 04:37:39.235137 ===================================
2210 04:37:39.235243 [ANA_INIT] >>>>>>>>>>>>>>
2211 04:37:39.238548 <<<<<< [CONFIGURE PHASE]: ANA_TX
2212 04:37:39.241801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2213 04:37:39.245191 ===================================
2214 04:37:39.248300 data_rate = 2400,PCW = 0X5b00
2215 04:37:39.251707 ===================================
2216 04:37:39.254779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2217 04:37:39.261947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2218 04:37:39.264894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2219 04:37:39.271880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2220 04:37:39.274895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2221 04:37:39.278485 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2222 04:37:39.278587 [ANA_INIT] flow start
2223 04:37:39.281993 [ANA_INIT] PLL >>>>>>>>
2224 04:37:39.285254 [ANA_INIT] PLL <<<<<<<<
2225 04:37:39.285328 [ANA_INIT] MIDPI >>>>>>>>
2226 04:37:39.288472 [ANA_INIT] MIDPI <<<<<<<<
2227 04:37:39.292137 [ANA_INIT] DLL >>>>>>>>
2228 04:37:39.295282 [ANA_INIT] DLL <<<<<<<<
2229 04:37:39.295361 [ANA_INIT] flow end
2230 04:37:39.298733 ============ LP4 DIFF to SE enter ============
2231 04:37:39.305305 ============ LP4 DIFF to SE exit ============
2232 04:37:39.305386 [ANA_INIT] <<<<<<<<<<<<<
2233 04:37:39.309087 [Flow] Enable top DCM control >>>>>
2234 04:37:39.311964 [Flow] Enable top DCM control <<<<<
2235 04:37:39.315365 Enable DLL master slave shuffle
2236 04:37:39.321954 ==============================================================
2237 04:37:39.322035 Gating Mode config
2238 04:37:39.329171 ==============================================================
2239 04:37:39.329251 Config description:
2240 04:37:39.339055 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2241 04:37:39.345594 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2242 04:37:39.352201 SELPH_MODE 0: By rank 1: By Phase
2243 04:37:39.355530 ==============================================================
2244 04:37:39.359039 GAT_TRACK_EN = 1
2245 04:37:39.362585 RX_GATING_MODE = 2
2246 04:37:39.366077 RX_GATING_TRACK_MODE = 2
2247 04:37:39.369008 SELPH_MODE = 1
2248 04:37:39.372596 PICG_EARLY_EN = 1
2249 04:37:39.376033 VALID_LAT_VALUE = 1
2250 04:37:39.379650 ==============================================================
2251 04:37:39.382995 Enter into Gating configuration >>>>
2252 04:37:39.386210 Exit from Gating configuration <<<<
2253 04:37:39.389371 Enter into DVFS_PRE_config >>>>>
2254 04:37:39.402805 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2255 04:37:39.402890 Exit from DVFS_PRE_config <<<<<
2256 04:37:39.406120 Enter into PICG configuration >>>>
2257 04:37:39.409606 Exit from PICG configuration <<<<
2258 04:37:39.412628 [RX_INPUT] configuration >>>>>
2259 04:37:39.416490 [RX_INPUT] configuration <<<<<
2260 04:37:39.423189 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2261 04:37:39.426112 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2262 04:37:39.433278 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2263 04:37:39.439506 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2264 04:37:39.446537 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2265 04:37:39.453202 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2266 04:37:39.456897 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2267 04:37:39.459777 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2268 04:37:39.463299 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2269 04:37:39.466493 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2270 04:37:39.473413 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2271 04:37:39.476579 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 04:37:39.480154 ===================================
2273 04:37:39.483903 LPDDR4 DRAM CONFIGURATION
2274 04:37:39.486617 ===================================
2275 04:37:39.486694 EX_ROW_EN[0] = 0x0
2276 04:37:39.490105 EX_ROW_EN[1] = 0x0
2277 04:37:39.490179 LP4Y_EN = 0x0
2278 04:37:39.493441 WORK_FSP = 0x0
2279 04:37:39.493543 WL = 0x4
2280 04:37:39.496903 RL = 0x4
2281 04:37:39.496981 BL = 0x2
2282 04:37:39.500569 RPST = 0x0
2283 04:37:39.500676 RD_PRE = 0x0
2284 04:37:39.503675 WR_PRE = 0x1
2285 04:37:39.503773 WR_PST = 0x0
2286 04:37:39.507030 DBI_WR = 0x0
2287 04:37:39.507104 DBI_RD = 0x0
2288 04:37:39.510479 OTF = 0x1
2289 04:37:39.513870 ===================================
2290 04:37:39.517376 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2291 04:37:39.520346 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2292 04:37:39.527543 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2293 04:37:39.530231 ===================================
2294 04:37:39.530306 LPDDR4 DRAM CONFIGURATION
2295 04:37:39.533826 ===================================
2296 04:37:39.537017 EX_ROW_EN[0] = 0x10
2297 04:37:39.540342 EX_ROW_EN[1] = 0x0
2298 04:37:39.540443 LP4Y_EN = 0x0
2299 04:37:39.543825 WORK_FSP = 0x0
2300 04:37:39.543902 WL = 0x4
2301 04:37:39.547333 RL = 0x4
2302 04:37:39.547412 BL = 0x2
2303 04:37:39.550438 RPST = 0x0
2304 04:37:39.550510 RD_PRE = 0x0
2305 04:37:39.553877 WR_PRE = 0x1
2306 04:37:39.553959 WR_PST = 0x0
2307 04:37:39.557146 DBI_WR = 0x0
2308 04:37:39.557228 DBI_RD = 0x0
2309 04:37:39.560774 OTF = 0x1
2310 04:37:39.563815 ===================================
2311 04:37:39.570947 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2312 04:37:39.571029 ==
2313 04:37:39.574108 Dram Type= 6, Freq= 0, CH_0, rank 0
2314 04:37:39.577764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2315 04:37:39.577845 ==
2316 04:37:39.580839 [Duty_Offset_Calibration]
2317 04:37:39.580919 B0:2 B1:-1 CA:1
2318 04:37:39.580983
2319 04:37:39.584336 [DutyScan_Calibration_Flow] k_type=0
2320 04:37:39.593144
2321 04:37:39.593224 ==CLK 0==
2322 04:37:39.596770 Final CLK duty delay cell = -4
2323 04:37:39.599926 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2324 04:37:39.603494 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2325 04:37:39.606732 [-4] AVG Duty = 4953%(X100)
2326 04:37:39.606812
2327 04:37:39.610124 CH0 CLK Duty spec in!! Max-Min= 156%
2328 04:37:39.613123 [DutyScan_Calibration_Flow] ====Done====
2329 04:37:39.613203
2330 04:37:39.616534 [DutyScan_Calibration_Flow] k_type=1
2331 04:37:39.631688
2332 04:37:39.631770 ==DQS 0 ==
2333 04:37:39.635076 Final DQS duty delay cell = 0
2334 04:37:39.638612 [0] MAX Duty = 5125%(X100), DQS PI = 48
2335 04:37:39.641817 [0] MIN Duty = 5000%(X100), DQS PI = 14
2336 04:37:39.641905 [0] AVG Duty = 5062%(X100)
2337 04:37:39.645211
2338 04:37:39.645290 ==DQS 1 ==
2339 04:37:39.648848 Final DQS duty delay cell = -4
2340 04:37:39.652317 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2341 04:37:39.655334 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2342 04:37:39.658863 [-4] AVG Duty = 5062%(X100)
2343 04:37:39.658944
2344 04:37:39.661817 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2345 04:37:39.661898
2346 04:37:39.665228 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2347 04:37:39.668629 [DutyScan_Calibration_Flow] ====Done====
2348 04:37:39.668813
2349 04:37:39.672191 [DutyScan_Calibration_Flow] k_type=3
2350 04:37:39.688905
2351 04:37:39.689077 ==DQM 0 ==
2352 04:37:39.692195 Final DQM duty delay cell = 0
2353 04:37:39.695312 [0] MAX Duty = 5031%(X100), DQS PI = 54
2354 04:37:39.698576 [0] MIN Duty = 4875%(X100), DQS PI = 4
2355 04:37:39.698698 [0] AVG Duty = 4953%(X100)
2356 04:37:39.698800
2357 04:37:39.702075 ==DQM 1 ==
2358 04:37:39.705522 Final DQM duty delay cell = 0
2359 04:37:39.708735 [0] MAX Duty = 5156%(X100), DQS PI = 62
2360 04:37:39.712013 [0] MIN Duty = 4969%(X100), DQS PI = 10
2361 04:37:39.712133 [0] AVG Duty = 5062%(X100)
2362 04:37:39.712237
2363 04:37:39.719087 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2364 04:37:39.719214
2365 04:37:39.722100 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2366 04:37:39.725448 [DutyScan_Calibration_Flow] ====Done====
2367 04:37:39.725533
2368 04:37:39.728815 [DutyScan_Calibration_Flow] k_type=2
2369 04:37:39.744676
2370 04:37:39.744870 ==DQ 0 ==
2371 04:37:39.748378 Final DQ duty delay cell = -4
2372 04:37:39.752009 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2373 04:37:39.754702 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2374 04:37:39.754823 [-4] AVG Duty = 4953%(X100)
2375 04:37:39.757819
2376 04:37:39.757896 ==DQ 1 ==
2377 04:37:39.761416 Final DQ duty delay cell = 0
2378 04:37:39.764783 [0] MAX Duty = 5031%(X100), DQS PI = 18
2379 04:37:39.767843 [0] MIN Duty = 4907%(X100), DQS PI = 46
2380 04:37:39.767930 [0] AVG Duty = 4969%(X100)
2381 04:37:39.767997
2382 04:37:39.771588 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2383 04:37:39.771681
2384 04:37:39.774824 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2385 04:37:39.781332 [DutyScan_Calibration_Flow] ====Done====
2386 04:37:39.781427 ==
2387 04:37:39.785147 Dram Type= 6, Freq= 0, CH_1, rank 0
2388 04:37:39.788367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2389 04:37:39.788483 ==
2390 04:37:39.791850 [Duty_Offset_Calibration]
2391 04:37:39.791945 B0:1 B1:1 CA:2
2392 04:37:39.792012
2393 04:37:39.795136 [DutyScan_Calibration_Flow] k_type=0
2394 04:37:39.805133
2395 04:37:39.805270 ==CLK 0==
2396 04:37:39.807732 Final CLK duty delay cell = 0
2397 04:37:39.811212 [0] MAX Duty = 5187%(X100), DQS PI = 24
2398 04:37:39.814360 [0] MIN Duty = 4938%(X100), DQS PI = 48
2399 04:37:39.814469 [0] AVG Duty = 5062%(X100)
2400 04:37:39.818541
2401 04:37:39.818633 CH1 CLK Duty spec in!! Max-Min= 249%
2402 04:37:39.824728 [DutyScan_Calibration_Flow] ====Done====
2403 04:37:39.824902
2404 04:37:39.827825 [DutyScan_Calibration_Flow] k_type=1
2405 04:37:39.844066
2406 04:37:39.844243 ==DQS 0 ==
2407 04:37:39.847408 Final DQS duty delay cell = 0
2408 04:37:39.850500 [0] MAX Duty = 5031%(X100), DQS PI = 18
2409 04:37:39.854010 [0] MIN Duty = 4813%(X100), DQS PI = 50
2410 04:37:39.854125 [0] AVG Duty = 4922%(X100)
2411 04:37:39.857468
2412 04:37:39.857578 ==DQS 1 ==
2413 04:37:39.860456 Final DQS duty delay cell = 0
2414 04:37:39.864100 [0] MAX Duty = 5062%(X100), DQS PI = 36
2415 04:37:39.867517 [0] MIN Duty = 4906%(X100), DQS PI = 16
2416 04:37:39.867625 [0] AVG Duty = 4984%(X100)
2417 04:37:39.867725
2418 04:37:39.874268 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2419 04:37:39.874387
2420 04:37:39.877782 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2421 04:37:39.881022 [DutyScan_Calibration_Flow] ====Done====
2422 04:37:39.881103
2423 04:37:39.884264 [DutyScan_Calibration_Flow] k_type=3
2424 04:37:39.900420
2425 04:37:39.900506 ==DQM 0 ==
2426 04:37:39.903921 Final DQM duty delay cell = 0
2427 04:37:39.906853 [0] MAX Duty = 5093%(X100), DQS PI = 18
2428 04:37:39.910464 [0] MIN Duty = 4907%(X100), DQS PI = 44
2429 04:37:39.910569 [0] AVG Duty = 5000%(X100)
2430 04:37:39.913906
2431 04:37:39.913994 ==DQM 1 ==
2432 04:37:39.917453 Final DQM duty delay cell = 0
2433 04:37:39.920403 [0] MAX Duty = 5156%(X100), DQS PI = 62
2434 04:37:39.924082 [0] MIN Duty = 4938%(X100), DQS PI = 22
2435 04:37:39.924183 [0] AVG Duty = 5047%(X100)
2436 04:37:39.927453
2437 04:37:39.930657 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2438 04:37:39.930761
2439 04:37:39.933942 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2440 04:37:39.937377 [DutyScan_Calibration_Flow] ====Done====
2441 04:37:39.937477
2442 04:37:39.940474 [DutyScan_Calibration_Flow] k_type=2
2443 04:37:39.956803
2444 04:37:39.956914 ==DQ 0 ==
2445 04:37:39.960307 Final DQ duty delay cell = 0
2446 04:37:39.963657 [0] MAX Duty = 5124%(X100), DQS PI = 18
2447 04:37:39.967358 [0] MIN Duty = 4938%(X100), DQS PI = 50
2448 04:37:39.967471 [0] AVG Duty = 5031%(X100)
2449 04:37:39.967733
2450 04:37:39.970296 ==DQ 1 ==
2451 04:37:39.973925 Final DQ duty delay cell = 0
2452 04:37:39.976874 [0] MAX Duty = 5093%(X100), DQS PI = 8
2453 04:37:39.980636 [0] MIN Duty = 5031%(X100), DQS PI = 2
2454 04:37:39.980767 [0] AVG Duty = 5062%(X100)
2455 04:37:39.980858
2456 04:37:39.984067 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2457 04:37:39.984176
2458 04:37:39.987176 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2459 04:37:39.990367 [DutyScan_Calibration_Flow] ====Done====
2460 04:37:39.996015 nWR fixed to 30
2461 04:37:39.999379 [ModeRegInit_LP4] CH0 RK0
2462 04:37:39.999488 [ModeRegInit_LP4] CH0 RK1
2463 04:37:40.002668 [ModeRegInit_LP4] CH1 RK0
2464 04:37:40.005922 [ModeRegInit_LP4] CH1 RK1
2465 04:37:40.006031 match AC timing 7
2466 04:37:40.012952 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2467 04:37:40.015810 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2468 04:37:40.019147 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2469 04:37:40.026388 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2470 04:37:40.029425 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2471 04:37:40.029498 ==
2472 04:37:40.032962 Dram Type= 6, Freq= 0, CH_0, rank 0
2473 04:37:40.036314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 04:37:40.036410 ==
2475 04:37:40.042589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 04:37:40.049032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2477 04:37:40.057085 [CA 0] Center 40 (10~71) winsize 62
2478 04:37:40.060145 [CA 1] Center 39 (9~70) winsize 62
2479 04:37:40.063408 [CA 2] Center 36 (6~67) winsize 62
2480 04:37:40.066788 [CA 3] Center 36 (5~67) winsize 63
2481 04:37:40.070084 [CA 4] Center 35 (5~65) winsize 61
2482 04:37:40.073678 [CA 5] Center 34 (4~64) winsize 61
2483 04:37:40.073759
2484 04:37:40.077345 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2485 04:37:40.077425
2486 04:37:40.080339 [CATrainingPosCal] consider 1 rank data
2487 04:37:40.083706 u2DelayCellTimex100 = 270/100 ps
2488 04:37:40.087051 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2489 04:37:40.090623 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2490 04:37:40.097551 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2491 04:37:40.100600 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2492 04:37:40.103662 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2493 04:37:40.107127 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2494 04:37:40.107228
2495 04:37:40.110406 CA PerBit enable=1, Macro0, CA PI delay=34
2496 04:37:40.110520
2497 04:37:40.113685 [CBTSetCACLKResult] CA Dly = 34
2498 04:37:40.113762 CS Dly: 7 (0~38)
2499 04:37:40.113824 ==
2500 04:37:40.117478 Dram Type= 6, Freq= 0, CH_0, rank 1
2501 04:37:40.123862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 04:37:40.123969 ==
2503 04:37:40.127133 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2504 04:37:40.133884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2505 04:37:40.142705 [CA 0] Center 39 (9~70) winsize 62
2506 04:37:40.145992 [CA 1] Center 39 (9~70) winsize 62
2507 04:37:40.149316 [CA 2] Center 36 (6~67) winsize 62
2508 04:37:40.152595 [CA 3] Center 36 (5~67) winsize 63
2509 04:37:40.156235 [CA 4] Center 34 (4~65) winsize 62
2510 04:37:40.159289 [CA 5] Center 34 (4~64) winsize 61
2511 04:37:40.159398
2512 04:37:40.163120 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2513 04:37:40.163222
2514 04:37:40.166039 [CATrainingPosCal] consider 2 rank data
2515 04:37:40.169441 u2DelayCellTimex100 = 270/100 ps
2516 04:37:40.172753 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2517 04:37:40.176381 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2518 04:37:40.179401 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2519 04:37:40.186689 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2520 04:37:40.189552 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2521 04:37:40.193212 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2522 04:37:40.193282
2523 04:37:40.196601 CA PerBit enable=1, Macro0, CA PI delay=34
2524 04:37:40.196734
2525 04:37:40.199722 [CBTSetCACLKResult] CA Dly = 34
2526 04:37:40.199818 CS Dly: 8 (0~41)
2527 04:37:40.199906
2528 04:37:40.203163 ----->DramcWriteLeveling(PI) begin...
2529 04:37:40.203240 ==
2530 04:37:40.206291 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 04:37:40.213383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 04:37:40.213465 ==
2533 04:37:40.216592 Write leveling (Byte 0): 32 => 32
2534 04:37:40.220192 Write leveling (Byte 1): 30 => 30
2535 04:37:40.220281 DramcWriteLeveling(PI) end<-----
2536 04:37:40.220370
2537 04:37:40.223352 ==
2538 04:37:40.223452 Dram Type= 6, Freq= 0, CH_0, rank 0
2539 04:37:40.229827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 04:37:40.229900 ==
2541 04:37:40.233205 [Gating] SW mode calibration
2542 04:37:40.240020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2543 04:37:40.243502 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2544 04:37:40.250159 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 04:37:40.253590 0 15 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2546 04:37:40.256760 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2547 04:37:40.263470 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 04:37:40.267106 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2549 04:37:40.270517 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 04:37:40.273327 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 04:37:40.280204 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 04:37:40.283666 1 0 0 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
2553 04:37:40.287443 1 0 4 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
2554 04:37:40.293645 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 04:37:40.297232 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 04:37:40.300204 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 04:37:40.307306 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 04:37:40.310730 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 04:37:40.314060 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 04:37:40.320431 1 1 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2561 04:37:40.323860 1 1 4 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
2562 04:37:40.327839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 04:37:40.330860 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 04:37:40.337497 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 04:37:40.340746 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 04:37:40.343957 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 04:37:40.350730 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 04:37:40.353731 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2569 04:37:40.357351 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2570 04:37:40.363985 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2571 04:37:40.367259 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 04:37:40.370758 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 04:37:40.377503 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 04:37:40.381424 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 04:37:40.384526 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 04:37:40.391109 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 04:37:40.394112 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 04:37:40.397750 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 04:37:40.401027 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 04:37:40.407562 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 04:37:40.411232 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 04:37:40.414302 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 04:37:40.421018 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 04:37:40.424787 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2585 04:37:40.427818 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 04:37:40.430890 Total UI for P1: 0, mck2ui 16
2587 04:37:40.434919 best dqsien dly found for B0: ( 1, 4, 0)
2588 04:37:40.437810 Total UI for P1: 0, mck2ui 16
2589 04:37:40.441492 best dqsien dly found for B1: ( 1, 4, 2)
2590 04:37:40.444611 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2591 04:37:40.447854 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2592 04:37:40.447935
2593 04:37:40.451193 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2594 04:37:40.454687 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2595 04:37:40.458372 [Gating] SW calibration Done
2596 04:37:40.458468 ==
2597 04:37:40.461231 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 04:37:40.467893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 04:37:40.467974 ==
2600 04:37:40.468039 RX Vref Scan: 0
2601 04:37:40.468099
2602 04:37:40.471342 RX Vref 0 -> 0, step: 1
2603 04:37:40.471422
2604 04:37:40.474671 RX Delay -40 -> 252, step: 8
2605 04:37:40.478251 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2606 04:37:40.481312 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2607 04:37:40.484480 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2608 04:37:40.488235 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2609 04:37:40.495201 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2610 04:37:40.498284 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2611 04:37:40.501705 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2612 04:37:40.504888 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2613 04:37:40.508284 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2614 04:37:40.511907 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2615 04:37:40.518476 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2616 04:37:40.521544 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2617 04:37:40.524889 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2618 04:37:40.528775 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2619 04:37:40.531506 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2620 04:37:40.538333 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2621 04:37:40.538433 ==
2622 04:37:40.541991 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 04:37:40.544932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 04:37:40.545001 ==
2625 04:37:40.545062 DQS Delay:
2626 04:37:40.548319 DQS0 = 0, DQS1 = 0
2627 04:37:40.548420 DQM Delay:
2628 04:37:40.551801 DQM0 = 116, DQM1 = 107
2629 04:37:40.551894 DQ Delay:
2630 04:37:40.554987 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2631 04:37:40.558251 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2632 04:37:40.561779 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2633 04:37:40.565622 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2634 04:37:40.565717
2635 04:37:40.565805
2636 04:37:40.565898 ==
2637 04:37:40.568294 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 04:37:40.575546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 04:37:40.575648 ==
2640 04:37:40.575736
2641 04:37:40.575820
2642 04:37:40.575912 TX Vref Scan disable
2643 04:37:40.578966 == TX Byte 0 ==
2644 04:37:40.582350 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2645 04:37:40.585829 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2646 04:37:40.589280 == TX Byte 1 ==
2647 04:37:40.592309 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2648 04:37:40.595411 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2649 04:37:40.599208 ==
2650 04:37:40.602608 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 04:37:40.606073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 04:37:40.606144 ==
2653 04:37:40.616931 TX Vref=22, minBit 1, minWin=24, winSum=417
2654 04:37:40.620062 TX Vref=24, minBit 1, minWin=25, winSum=418
2655 04:37:40.623502 TX Vref=26, minBit 7, minWin=25, winSum=425
2656 04:37:40.627108 TX Vref=28, minBit 0, minWin=26, winSum=431
2657 04:37:40.630508 TX Vref=30, minBit 0, minWin=26, winSum=432
2658 04:37:40.633777 TX Vref=32, minBit 0, minWin=26, winSum=431
2659 04:37:40.640498 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
2660 04:37:40.640612
2661 04:37:40.643589 Final TX Range 1 Vref 30
2662 04:37:40.643683
2663 04:37:40.643770 ==
2664 04:37:40.647031 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 04:37:40.650556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 04:37:40.650658 ==
2667 04:37:40.650745
2668 04:37:40.650837
2669 04:37:40.653799 TX Vref Scan disable
2670 04:37:40.657109 == TX Byte 0 ==
2671 04:37:40.660423 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2672 04:37:40.664029 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2673 04:37:40.667503 == TX Byte 1 ==
2674 04:37:40.670617 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2675 04:37:40.673988 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2676 04:37:40.674070
2677 04:37:40.677045 [DATLAT]
2678 04:37:40.677125 Freq=1200, CH0 RK0
2679 04:37:40.677188
2680 04:37:40.680633 DATLAT Default: 0xd
2681 04:37:40.680724 0, 0xFFFF, sum = 0
2682 04:37:40.684100 1, 0xFFFF, sum = 0
2683 04:37:40.684182 2, 0xFFFF, sum = 0
2684 04:37:40.687159 3, 0xFFFF, sum = 0
2685 04:37:40.687288 4, 0xFFFF, sum = 0
2686 04:37:40.690669 5, 0xFFFF, sum = 0
2687 04:37:40.690786 6, 0xFFFF, sum = 0
2688 04:37:40.694123 7, 0xFFFF, sum = 0
2689 04:37:40.694233 8, 0xFFFF, sum = 0
2690 04:37:40.697477 9, 0xFFFF, sum = 0
2691 04:37:40.697562 10, 0xFFFF, sum = 0
2692 04:37:40.700602 11, 0xFFFF, sum = 0
2693 04:37:40.700737 12, 0x0, sum = 1
2694 04:37:40.703914 13, 0x0, sum = 2
2695 04:37:40.704019 14, 0x0, sum = 3
2696 04:37:40.707428 15, 0x0, sum = 4
2697 04:37:40.707542 best_step = 13
2698 04:37:40.707634
2699 04:37:40.707721 ==
2700 04:37:40.711040 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 04:37:40.714164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 04:37:40.717585 ==
2703 04:37:40.717665 RX Vref Scan: 1
2704 04:37:40.717730
2705 04:37:40.720861 Set Vref Range= 32 -> 127
2706 04:37:40.720941
2707 04:37:40.724430 RX Vref 32 -> 127, step: 1
2708 04:37:40.724547
2709 04:37:40.724645 RX Delay -21 -> 252, step: 4
2710 04:37:40.724759
2711 04:37:40.727461 Set Vref, RX VrefLevel [Byte0]: 32
2712 04:37:40.731128 [Byte1]: 32
2713 04:37:40.735037
2714 04:37:40.735148 Set Vref, RX VrefLevel [Byte0]: 33
2715 04:37:40.738770 [Byte1]: 33
2716 04:37:40.743145
2717 04:37:40.743248 Set Vref, RX VrefLevel [Byte0]: 34
2718 04:37:40.746387 [Byte1]: 34
2719 04:37:40.750965
2720 04:37:40.751065 Set Vref, RX VrefLevel [Byte0]: 35
2721 04:37:40.754604 [Byte1]: 35
2722 04:37:40.758788
2723 04:37:40.758888 Set Vref, RX VrefLevel [Byte0]: 36
2724 04:37:40.762138 [Byte1]: 36
2725 04:37:40.766771
2726 04:37:40.766891 Set Vref, RX VrefLevel [Byte0]: 37
2727 04:37:40.769980 [Byte1]: 37
2728 04:37:40.775037
2729 04:37:40.775143 Set Vref, RX VrefLevel [Byte0]: 38
2730 04:37:40.778397 [Byte1]: 38
2731 04:37:40.783078
2732 04:37:40.783178 Set Vref, RX VrefLevel [Byte0]: 39
2733 04:37:40.786016 [Byte1]: 39
2734 04:37:40.790772
2735 04:37:40.790853 Set Vref, RX VrefLevel [Byte0]: 40
2736 04:37:40.794388 [Byte1]: 40
2737 04:37:40.798829
2738 04:37:40.798909 Set Vref, RX VrefLevel [Byte0]: 41
2739 04:37:40.801893 [Byte1]: 41
2740 04:37:40.806586
2741 04:37:40.806667 Set Vref, RX VrefLevel [Byte0]: 42
2742 04:37:40.809926 [Byte1]: 42
2743 04:37:40.814251
2744 04:37:40.814332 Set Vref, RX VrefLevel [Byte0]: 43
2745 04:37:40.818089 [Byte1]: 43
2746 04:37:40.822216
2747 04:37:40.822296 Set Vref, RX VrefLevel [Byte0]: 44
2748 04:37:40.825992 [Byte1]: 44
2749 04:37:40.830053
2750 04:37:40.830132 Set Vref, RX VrefLevel [Byte0]: 45
2751 04:37:40.833466 [Byte1]: 45
2752 04:37:40.838396
2753 04:37:40.838475 Set Vref, RX VrefLevel [Byte0]: 46
2754 04:37:40.841469 [Byte1]: 46
2755 04:37:40.846114
2756 04:37:40.846194 Set Vref, RX VrefLevel [Byte0]: 47
2757 04:37:40.849364 [Byte1]: 47
2758 04:37:40.854595
2759 04:37:40.854670 Set Vref, RX VrefLevel [Byte0]: 48
2760 04:37:40.857113 [Byte1]: 48
2761 04:37:40.861880
2762 04:37:40.861955 Set Vref, RX VrefLevel [Byte0]: 49
2763 04:37:40.865610 [Byte1]: 49
2764 04:37:40.870035
2765 04:37:40.870103 Set Vref, RX VrefLevel [Byte0]: 50
2766 04:37:40.873471 [Byte1]: 50
2767 04:37:40.877814
2768 04:37:40.877881 Set Vref, RX VrefLevel [Byte0]: 51
2769 04:37:40.881082 [Byte1]: 51
2770 04:37:40.885674
2771 04:37:40.885755 Set Vref, RX VrefLevel [Byte0]: 52
2772 04:37:40.889241 [Byte1]: 52
2773 04:37:40.894355
2774 04:37:40.894424 Set Vref, RX VrefLevel [Byte0]: 53
2775 04:37:40.896808 [Byte1]: 53
2776 04:37:40.901693
2777 04:37:40.901794 Set Vref, RX VrefLevel [Byte0]: 54
2778 04:37:40.904969 [Byte1]: 54
2779 04:37:40.909554
2780 04:37:40.909623 Set Vref, RX VrefLevel [Byte0]: 55
2781 04:37:40.912639 [Byte1]: 55
2782 04:37:40.917433
2783 04:37:40.917538 Set Vref, RX VrefLevel [Byte0]: 56
2784 04:37:40.920982 [Byte1]: 56
2785 04:37:40.925105
2786 04:37:40.925185 Set Vref, RX VrefLevel [Byte0]: 57
2787 04:37:40.929065 [Byte1]: 57
2788 04:37:40.933437
2789 04:37:40.933516 Set Vref, RX VrefLevel [Byte0]: 58
2790 04:37:40.936537 [Byte1]: 58
2791 04:37:40.941208
2792 04:37:40.941287 Set Vref, RX VrefLevel [Byte0]: 59
2793 04:37:40.945050 [Byte1]: 59
2794 04:37:40.949058
2795 04:37:40.949137 Set Vref, RX VrefLevel [Byte0]: 60
2796 04:37:40.952834 [Byte1]: 60
2797 04:37:40.957370
2798 04:37:40.957450 Set Vref, RX VrefLevel [Byte0]: 61
2799 04:37:40.960637 [Byte1]: 61
2800 04:37:40.964885
2801 04:37:40.964965 Set Vref, RX VrefLevel [Byte0]: 62
2802 04:37:40.968531 [Byte1]: 62
2803 04:37:40.972618
2804 04:37:40.975877 Set Vref, RX VrefLevel [Byte0]: 63
2805 04:37:40.979544 [Byte1]: 63
2806 04:37:40.979623
2807 04:37:40.983227 Set Vref, RX VrefLevel [Byte0]: 64
2808 04:37:40.985893 [Byte1]: 64
2809 04:37:40.985973
2810 04:37:40.989677 Set Vref, RX VrefLevel [Byte0]: 65
2811 04:37:40.992843 [Byte1]: 65
2812 04:37:40.996554
2813 04:37:40.996634 Set Vref, RX VrefLevel [Byte0]: 66
2814 04:37:41.000071 [Byte1]: 66
2815 04:37:41.004645
2816 04:37:41.004765 Set Vref, RX VrefLevel [Byte0]: 67
2817 04:37:41.008145 [Byte1]: 67
2818 04:37:41.012464
2819 04:37:41.012566 Set Vref, RX VrefLevel [Byte0]: 68
2820 04:37:41.016003 [Byte1]: 68
2821 04:37:41.020572
2822 04:37:41.020694 Final RX Vref Byte 0 = 53 to rank0
2823 04:37:41.023745 Final RX Vref Byte 1 = 52 to rank0
2824 04:37:41.027355 Final RX Vref Byte 0 = 53 to rank1
2825 04:37:41.030751 Final RX Vref Byte 1 = 52 to rank1==
2826 04:37:41.034385 Dram Type= 6, Freq= 0, CH_0, rank 0
2827 04:37:41.037374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 04:37:41.040639 ==
2829 04:37:41.040764 DQS Delay:
2830 04:37:41.040852 DQS0 = 0, DQS1 = 0
2831 04:37:41.044352 DQM Delay:
2832 04:37:41.044438 DQM0 = 115, DQM1 = 105
2833 04:37:41.048035 DQ Delay:
2834 04:37:41.050623 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2835 04:37:41.054122 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2836 04:37:41.057797 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2837 04:37:41.060796 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2838 04:37:41.060870
2839 04:37:41.060930
2840 04:37:41.067823 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2841 04:37:41.070668 CH0 RK0: MR19=303, MR18=FDEC
2842 04:37:41.077646 CH0_RK0: MR19=0x303, MR18=0xFDEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2843 04:37:41.077722
2844 04:37:41.081399 ----->DramcWriteLeveling(PI) begin...
2845 04:37:41.081499 ==
2846 04:37:41.084347 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 04:37:41.087684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 04:37:41.087763 ==
2849 04:37:41.091163 Write leveling (Byte 0): 32 => 32
2850 04:37:41.094237 Write leveling (Byte 1): 28 => 28
2851 04:37:41.097965 DramcWriteLeveling(PI) end<-----
2852 04:37:41.098066
2853 04:37:41.098154 ==
2854 04:37:41.101119 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 04:37:41.104537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 04:37:41.104639 ==
2857 04:37:41.107812 [Gating] SW mode calibration
2858 04:37:41.114349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2859 04:37:41.121145 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2860 04:37:41.124332 0 15 0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
2861 04:37:41.127996 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2862 04:37:41.134461 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 04:37:41.138382 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 04:37:41.141372 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 04:37:41.148343 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 04:37:41.151350 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2867 04:37:41.154912 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2868 04:37:41.161969 1 0 0 | B1->B0 | 3030 2929 | 1 0 | (1 0) (0 0)
2869 04:37:41.164841 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 04:37:41.168392 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 04:37:41.174887 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 04:37:41.178142 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 04:37:41.181481 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 04:37:41.188343 1 0 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
2875 04:37:41.191989 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2876 04:37:41.195370 1 1 0 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (0 0)
2877 04:37:41.198742 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 04:37:41.205123 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 04:37:41.208297 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 04:37:41.211688 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 04:37:41.218995 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 04:37:41.221956 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2883 04:37:41.225411 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2884 04:37:41.232032 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2885 04:37:41.235632 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2886 04:37:41.238937 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 04:37:41.245673 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 04:37:41.248566 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 04:37:41.252097 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 04:37:41.255843 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 04:37:41.262391 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 04:37:41.265714 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 04:37:41.269105 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 04:37:41.275605 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 04:37:41.279131 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 04:37:41.282231 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 04:37:41.289145 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 04:37:41.292952 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 04:37:41.295758 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2900 04:37:41.302517 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2901 04:37:41.302594 Total UI for P1: 0, mck2ui 16
2902 04:37:41.305887 best dqsien dly found for B0: ( 1, 3, 26)
2903 04:37:41.312578 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 04:37:41.316211 Total UI for P1: 0, mck2ui 16
2905 04:37:41.319569 best dqsien dly found for B1: ( 1, 4, 0)
2906 04:37:41.322923 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2907 04:37:41.325748 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2908 04:37:41.325848
2909 04:37:41.329524 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2910 04:37:41.332505 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2911 04:37:41.336296 [Gating] SW calibration Done
2912 04:37:41.336374 ==
2913 04:37:41.339351 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 04:37:41.342883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 04:37:41.342962 ==
2916 04:37:41.346068 RX Vref Scan: 0
2917 04:37:41.346149
2918 04:37:41.346213 RX Vref 0 -> 0, step: 1
2919 04:37:41.346272
2920 04:37:41.349362 RX Delay -40 -> 252, step: 8
2921 04:37:41.353453 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2922 04:37:41.359515 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2923 04:37:41.362901 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2924 04:37:41.366709 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2925 04:37:41.369582 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2926 04:37:41.373091 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2927 04:37:41.376637 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2928 04:37:41.383142 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2929 04:37:41.386545 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2930 04:37:41.389619 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2931 04:37:41.393129 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2932 04:37:41.396865 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2933 04:37:41.403316 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2934 04:37:41.406730 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2935 04:37:41.410108 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2936 04:37:41.413642 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2937 04:37:41.413726 ==
2938 04:37:41.416920 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 04:37:41.420394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 04:37:41.423769 ==
2941 04:37:41.423853 DQS Delay:
2942 04:37:41.423917 DQS0 = 0, DQS1 = 0
2943 04:37:41.427039 DQM Delay:
2944 04:37:41.427120 DQM0 = 115, DQM1 = 105
2945 04:37:41.430237 DQ Delay:
2946 04:37:41.433341 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2947 04:37:41.436929 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2948 04:37:41.440450 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2949 04:37:41.443766 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2950 04:37:41.443861
2951 04:37:41.443925
2952 04:37:41.444021 ==
2953 04:37:41.446857 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 04:37:41.450236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 04:37:41.450341 ==
2956 04:37:41.450419
2957 04:37:41.450497
2958 04:37:41.453759 TX Vref Scan disable
2959 04:37:41.456871 == TX Byte 0 ==
2960 04:37:41.460490 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2961 04:37:41.463629 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2962 04:37:41.463710 == TX Byte 1 ==
2963 04:37:41.470602 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2964 04:37:41.473890 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2965 04:37:41.473987 ==
2966 04:37:41.476993 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 04:37:41.480601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 04:37:41.480691 ==
2969 04:37:41.494277 TX Vref=22, minBit 3, minWin=25, winSum=420
2970 04:37:41.497445 TX Vref=24, minBit 1, minWin=25, winSum=429
2971 04:37:41.500986 TX Vref=26, minBit 0, minWin=26, winSum=433
2972 04:37:41.504113 TX Vref=28, minBit 3, minWin=26, winSum=434
2973 04:37:41.507479 TX Vref=30, minBit 7, minWin=26, winSum=435
2974 04:37:41.510429 TX Vref=32, minBit 12, minWin=26, winSum=437
2975 04:37:41.517588 [TxChooseVref] Worse bit 12, Min win 26, Win sum 437, Final Vref 32
2976 04:37:41.517685
2977 04:37:41.520474 Final TX Range 1 Vref 32
2978 04:37:41.520586
2979 04:37:41.520703 ==
2980 04:37:41.524179 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 04:37:41.527361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 04:37:41.527459 ==
2983 04:37:41.527547
2984 04:37:41.530492
2985 04:37:41.530564 TX Vref Scan disable
2986 04:37:41.533887 == TX Byte 0 ==
2987 04:37:41.537186 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2988 04:37:41.540600 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2989 04:37:41.544238 == TX Byte 1 ==
2990 04:37:41.547907 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2991 04:37:41.550609 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2992 04:37:41.550711
2993 04:37:41.554353 [DATLAT]
2994 04:37:41.554422 Freq=1200, CH0 RK1
2995 04:37:41.554480
2996 04:37:41.557326 DATLAT Default: 0xd
2997 04:37:41.557392 0, 0xFFFF, sum = 0
2998 04:37:41.561032 1, 0xFFFF, sum = 0
2999 04:37:41.561100 2, 0xFFFF, sum = 0
3000 04:37:41.564520 3, 0xFFFF, sum = 0
3001 04:37:41.564603 4, 0xFFFF, sum = 0
3002 04:37:41.567498 5, 0xFFFF, sum = 0
3003 04:37:41.567574 6, 0xFFFF, sum = 0
3004 04:37:41.570819 7, 0xFFFF, sum = 0
3005 04:37:41.570894 8, 0xFFFF, sum = 0
3006 04:37:41.574403 9, 0xFFFF, sum = 0
3007 04:37:41.574486 10, 0xFFFF, sum = 0
3008 04:37:41.577381 11, 0xFFFF, sum = 0
3009 04:37:41.577454 12, 0x0, sum = 1
3010 04:37:41.581170 13, 0x0, sum = 2
3011 04:37:41.581250 14, 0x0, sum = 3
3012 04:37:41.584692 15, 0x0, sum = 4
3013 04:37:41.584786 best_step = 13
3014 04:37:41.584848
3015 04:37:41.584907 ==
3016 04:37:41.587789 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 04:37:41.594813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 04:37:41.594893 ==
3019 04:37:41.594956 RX Vref Scan: 0
3020 04:37:41.595015
3021 04:37:41.597905 RX Vref 0 -> 0, step: 1
3022 04:37:41.597984
3023 04:37:41.601358 RX Delay -21 -> 252, step: 4
3024 04:37:41.604331 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3025 04:37:41.607864 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3026 04:37:41.611450 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3027 04:37:41.617683 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3028 04:37:41.621194 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3029 04:37:41.624641 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3030 04:37:41.627880 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3031 04:37:41.631182 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3032 04:37:41.638224 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3033 04:37:41.641340 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3034 04:37:41.644789 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3035 04:37:41.648358 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3036 04:37:41.651250 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3037 04:37:41.655223 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3038 04:37:41.661817 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3039 04:37:41.665226 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3040 04:37:41.665301 ==
3041 04:37:41.668647 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 04:37:41.671484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 04:37:41.671564 ==
3044 04:37:41.674994 DQS Delay:
3045 04:37:41.675073 DQS0 = 0, DQS1 = 0
3046 04:37:41.675136 DQM Delay:
3047 04:37:41.678209 DQM0 = 114, DQM1 = 104
3048 04:37:41.678288 DQ Delay:
3049 04:37:41.681676 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3050 04:37:41.685304 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3051 04:37:41.688518 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3052 04:37:41.694931 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3053 04:37:41.695011
3054 04:37:41.695091
3055 04:37:41.702006 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3056 04:37:41.705500 CH0 RK1: MR19=403, MR18=F1
3057 04:37:41.708639 CH0_RK1: MR19=0x403, MR18=0xF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3058 04:37:41.711630 [RxdqsGatingPostProcess] freq 1200
3059 04:37:41.718496 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3060 04:37:41.722108 best DQS0 dly(2T, 0.5T) = (0, 12)
3061 04:37:41.725465 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 04:37:41.728472 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3063 04:37:41.732165 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 04:37:41.735573 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 04:37:41.738568 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 04:37:41.741934 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 04:37:41.742051 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 04:37:41.745267 Pre-setting of DQS Precalculation
3069 04:37:41.752077 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3070 04:37:41.752158 ==
3071 04:37:41.755326 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 04:37:41.759310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 04:37:41.759391 ==
3074 04:37:41.765889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 04:37:41.772107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 04:37:41.779404 [CA 0] Center 38 (8~68) winsize 61
3077 04:37:41.782465 [CA 1] Center 38 (8~68) winsize 61
3078 04:37:41.785684 [CA 2] Center 35 (5~65) winsize 61
3079 04:37:41.789292 [CA 3] Center 34 (4~65) winsize 62
3080 04:37:41.792846 [CA 4] Center 34 (4~65) winsize 62
3081 04:37:41.796261 [CA 5] Center 34 (4~64) winsize 61
3082 04:37:41.796340
3083 04:37:41.800049 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3084 04:37:41.800128
3085 04:37:41.802743 [CATrainingPosCal] consider 1 rank data
3086 04:37:41.806264 u2DelayCellTimex100 = 270/100 ps
3087 04:37:41.809645 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3088 04:37:41.812636 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3089 04:37:41.816404 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3090 04:37:41.822764 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3091 04:37:41.826063 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3092 04:37:41.829373 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3093 04:37:41.829477
3094 04:37:41.833231 CA PerBit enable=1, Macro0, CA PI delay=34
3095 04:37:41.833314
3096 04:37:41.836118 [CBTSetCACLKResult] CA Dly = 34
3097 04:37:41.836189 CS Dly: 6 (0~37)
3098 04:37:41.836249 ==
3099 04:37:41.839875 Dram Type= 6, Freq= 0, CH_1, rank 1
3100 04:37:41.846544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 04:37:41.846625 ==
3102 04:37:41.849647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 04:37:41.856466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3104 04:37:41.865001 [CA 0] Center 38 (8~68) winsize 61
3105 04:37:41.867946 [CA 1] Center 38 (8~68) winsize 61
3106 04:37:41.871866 [CA 2] Center 34 (4~65) winsize 62
3107 04:37:41.874763 [CA 3] Center 34 (4~65) winsize 62
3108 04:37:41.878523 [CA 4] Center 34 (4~65) winsize 62
3109 04:37:41.881517 [CA 5] Center 33 (3~64) winsize 62
3110 04:37:41.881589
3111 04:37:41.884948 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 04:37:41.885018
3113 04:37:41.888012 [CATrainingPosCal] consider 2 rank data
3114 04:37:41.891465 u2DelayCellTimex100 = 270/100 ps
3115 04:37:41.895020 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3116 04:37:41.898299 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3117 04:37:41.901553 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3118 04:37:41.908379 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3119 04:37:41.911691 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3120 04:37:41.915558 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3121 04:37:41.915643
3122 04:37:41.918582 CA PerBit enable=1, Macro0, CA PI delay=34
3123 04:37:41.918666
3124 04:37:41.922126 [CBTSetCACLKResult] CA Dly = 34
3125 04:37:41.922211 CS Dly: 7 (0~40)
3126 04:37:41.922297
3127 04:37:41.925560 ----->DramcWriteLeveling(PI) begin...
3128 04:37:41.925645 ==
3129 04:37:41.928422 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 04:37:41.935446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 04:37:41.935540 ==
3132 04:37:41.938848 Write leveling (Byte 0): 26 => 26
3133 04:37:41.938932 Write leveling (Byte 1): 29 => 29
3134 04:37:41.942360 DramcWriteLeveling(PI) end<-----
3135 04:37:41.942444
3136 04:37:41.942529 ==
3137 04:37:41.945907 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 04:37:41.952110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 04:37:41.952195 ==
3140 04:37:41.955519 [Gating] SW mode calibration
3141 04:37:41.962047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3142 04:37:41.965399 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3143 04:37:41.972174 0 15 0 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
3144 04:37:41.975807 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 04:37:41.978911 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 04:37:41.982502 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 04:37:41.989304 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3148 04:37:41.992166 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 04:37:41.995539 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 04:37:42.002444 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3151 04:37:42.005983 1 0 0 | B1->B0 | 2424 2a2a | 0 0 | (1 0) (0 1)
3152 04:37:42.009441 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 04:37:42.015762 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 04:37:42.019542 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 04:37:42.022455 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3156 04:37:42.029506 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 04:37:42.032536 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 04:37:42.036065 1 0 28 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
3159 04:37:42.039271 1 1 0 | B1->B0 | 4242 3535 | 0 0 | (0 0) (1 1)
3160 04:37:42.046192 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 04:37:42.049638 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 04:37:42.052782 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 04:37:42.059331 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 04:37:42.062914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 04:37:42.066411 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 04:37:42.072951 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3167 04:37:42.076526 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3168 04:37:42.080077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 04:37:42.086560 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 04:37:42.089788 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 04:37:42.092827 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 04:37:42.100260 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 04:37:42.102988 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 04:37:42.106633 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 04:37:42.109670 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 04:37:42.116431 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 04:37:42.119833 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 04:37:42.123263 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 04:37:42.130115 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 04:37:42.133320 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 04:37:42.136976 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 04:37:42.143372 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3183 04:37:42.146485 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 04:37:42.149982 Total UI for P1: 0, mck2ui 16
3185 04:37:42.153304 best dqsien dly found for B0: ( 1, 3, 28)
3186 04:37:42.156832 Total UI for P1: 0, mck2ui 16
3187 04:37:42.160062 best dqsien dly found for B1: ( 1, 3, 30)
3188 04:37:42.163330 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3189 04:37:42.166467 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3190 04:37:42.166552
3191 04:37:42.170297 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3192 04:37:42.173187 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3193 04:37:42.176781 [Gating] SW calibration Done
3194 04:37:42.176864 ==
3195 04:37:42.179885 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 04:37:42.183393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 04:37:42.183477 ==
3198 04:37:42.187012 RX Vref Scan: 0
3199 04:37:42.187132
3200 04:37:42.187233 RX Vref 0 -> 0, step: 1
3201 04:37:42.190440
3202 04:37:42.190524 RX Delay -40 -> 252, step: 8
3203 04:37:42.196945 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3204 04:37:42.200656 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3205 04:37:42.203902 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3206 04:37:42.207402 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3207 04:37:42.210456 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 04:37:42.213970 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3209 04:37:42.220962 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3210 04:37:42.223927 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3211 04:37:42.227587 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3212 04:37:42.230516 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3213 04:37:42.234220 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3214 04:37:42.237533 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3215 04:37:42.244022 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3216 04:37:42.247807 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3217 04:37:42.250531 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3218 04:37:42.254064 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3219 04:37:42.254177 ==
3220 04:37:42.257647 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 04:37:42.264085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 04:37:42.264183 ==
3223 04:37:42.264283 DQS Delay:
3224 04:37:42.267497 DQS0 = 0, DQS1 = 0
3225 04:37:42.267583 DQM Delay:
3226 04:37:42.271043 DQM0 = 117, DQM1 = 110
3227 04:37:42.271119 DQ Delay:
3228 04:37:42.274346 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =119
3229 04:37:42.277723 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3230 04:37:42.280768 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3231 04:37:42.284027 DQ12 =123, DQ13 =115, DQ14 =115, DQ15 =115
3232 04:37:42.284132
3233 04:37:42.284234
3234 04:37:42.284334 ==
3235 04:37:42.287780 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 04:37:42.291168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 04:37:42.291270 ==
3238 04:37:42.294154
3239 04:37:42.294240
3240 04:37:42.294327 TX Vref Scan disable
3241 04:37:42.297450 == TX Byte 0 ==
3242 04:37:42.301011 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 04:37:42.304385 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 04:37:42.307845 == TX Byte 1 ==
3245 04:37:42.310630 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3246 04:37:42.314478 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3247 04:37:42.314564 ==
3248 04:37:42.317344 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 04:37:42.324091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 04:37:42.324198 ==
3251 04:37:42.334998 TX Vref=22, minBit 2, minWin=25, winSum=413
3252 04:37:42.338150 TX Vref=24, minBit 4, minWin=25, winSum=417
3253 04:37:42.341461 TX Vref=26, minBit 1, minWin=25, winSum=424
3254 04:37:42.345432 TX Vref=28, minBit 1, minWin=26, winSum=430
3255 04:37:42.348262 TX Vref=30, minBit 1, minWin=26, winSum=429
3256 04:37:42.351778 TX Vref=32, minBit 3, minWin=26, winSum=430
3257 04:37:42.358463 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3258 04:37:42.358571
3259 04:37:42.362061 Final TX Range 1 Vref 28
3260 04:37:42.362161
3261 04:37:42.362261 ==
3262 04:37:42.365023 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 04:37:42.368434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 04:37:42.368530 ==
3265 04:37:42.368622
3266 04:37:42.368722
3267 04:37:42.371954 TX Vref Scan disable
3268 04:37:42.375366 == TX Byte 0 ==
3269 04:37:42.378488 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 04:37:42.381944 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 04:37:42.385476 == TX Byte 1 ==
3272 04:37:42.389134 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3273 04:37:42.392173 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3274 04:37:42.392272
3275 04:37:42.395639 [DATLAT]
3276 04:37:42.395731 Freq=1200, CH1 RK0
3277 04:37:42.395820
3278 04:37:42.398604 DATLAT Default: 0xd
3279 04:37:42.398707 0, 0xFFFF, sum = 0
3280 04:37:42.402099 1, 0xFFFF, sum = 0
3281 04:37:42.402200 2, 0xFFFF, sum = 0
3282 04:37:42.405572 3, 0xFFFF, sum = 0
3283 04:37:42.405679 4, 0xFFFF, sum = 0
3284 04:37:42.409103 5, 0xFFFF, sum = 0
3285 04:37:42.409202 6, 0xFFFF, sum = 0
3286 04:37:42.412395 7, 0xFFFF, sum = 0
3287 04:37:42.412521 8, 0xFFFF, sum = 0
3288 04:37:42.415752 9, 0xFFFF, sum = 0
3289 04:37:42.415859 10, 0xFFFF, sum = 0
3290 04:37:42.418895 11, 0xFFFF, sum = 0
3291 04:37:42.419002 12, 0x0, sum = 1
3292 04:37:42.422772 13, 0x0, sum = 2
3293 04:37:42.422876 14, 0x0, sum = 3
3294 04:37:42.425513 15, 0x0, sum = 4
3295 04:37:42.425610 best_step = 13
3296 04:37:42.425704
3297 04:37:42.425791 ==
3298 04:37:42.429343 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 04:37:42.432634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 04:37:42.435753 ==
3301 04:37:42.435850 RX Vref Scan: 1
3302 04:37:42.435922
3303 04:37:42.439150 Set Vref Range= 32 -> 127
3304 04:37:42.439251
3305 04:37:42.442294 RX Vref 32 -> 127, step: 1
3306 04:37:42.442391
3307 04:37:42.442482 RX Delay -21 -> 252, step: 4
3308 04:37:42.442568
3309 04:37:42.445786 Set Vref, RX VrefLevel [Byte0]: 32
3310 04:37:42.449101 [Byte1]: 32
3311 04:37:42.453947
3312 04:37:42.454049 Set Vref, RX VrefLevel [Byte0]: 33
3313 04:37:42.456300 [Byte1]: 33
3314 04:37:42.461032
3315 04:37:42.461134 Set Vref, RX VrefLevel [Byte0]: 34
3316 04:37:42.464654 [Byte1]: 34
3317 04:37:42.469399
3318 04:37:42.469499 Set Vref, RX VrefLevel [Byte0]: 35
3319 04:37:42.472341 [Byte1]: 35
3320 04:37:42.476994
3321 04:37:42.477066 Set Vref, RX VrefLevel [Byte0]: 36
3322 04:37:42.480741 [Byte1]: 36
3323 04:37:42.484824
3324 04:37:42.484925 Set Vref, RX VrefLevel [Byte0]: 37
3325 04:37:42.488240 [Byte1]: 37
3326 04:37:42.492954
3327 04:37:42.493056 Set Vref, RX VrefLevel [Byte0]: 38
3328 04:37:42.495944 [Byte1]: 38
3329 04:37:42.500512
3330 04:37:42.500611 Set Vref, RX VrefLevel [Byte0]: 39
3331 04:37:42.504289 [Byte1]: 39
3332 04:37:42.508674
3333 04:37:42.508784 Set Vref, RX VrefLevel [Byte0]: 40
3334 04:37:42.511815 [Byte1]: 40
3335 04:37:42.516701
3336 04:37:42.516825 Set Vref, RX VrefLevel [Byte0]: 41
3337 04:37:42.520153 [Byte1]: 41
3338 04:37:42.524430
3339 04:37:42.524593 Set Vref, RX VrefLevel [Byte0]: 42
3340 04:37:42.527829 [Byte1]: 42
3341 04:37:42.532538
3342 04:37:42.532646 Set Vref, RX VrefLevel [Byte0]: 43
3343 04:37:42.536112 [Byte1]: 43
3344 04:37:42.540622
3345 04:37:42.540737 Set Vref, RX VrefLevel [Byte0]: 44
3346 04:37:42.544018 [Byte1]: 44
3347 04:37:42.548387
3348 04:37:42.548465 Set Vref, RX VrefLevel [Byte0]: 45
3349 04:37:42.551435 [Byte1]: 45
3350 04:37:42.555968
3351 04:37:42.556048 Set Vref, RX VrefLevel [Byte0]: 46
3352 04:37:42.559533 [Byte1]: 46
3353 04:37:42.564137
3354 04:37:42.564211 Set Vref, RX VrefLevel [Byte0]: 47
3355 04:37:42.567676 [Byte1]: 47
3356 04:37:42.572065
3357 04:37:42.572165 Set Vref, RX VrefLevel [Byte0]: 48
3358 04:37:42.575032 [Byte1]: 48
3359 04:37:42.579877
3360 04:37:42.580002 Set Vref, RX VrefLevel [Byte0]: 49
3361 04:37:42.583369 [Byte1]: 49
3362 04:37:42.587705
3363 04:37:42.587810 Set Vref, RX VrefLevel [Byte0]: 50
3364 04:37:42.591357 [Byte1]: 50
3365 04:37:42.595471
3366 04:37:42.599018 Set Vref, RX VrefLevel [Byte0]: 51
3367 04:37:42.599124 [Byte1]: 51
3368 04:37:42.603815
3369 04:37:42.603888 Set Vref, RX VrefLevel [Byte0]: 52
3370 04:37:42.607141 [Byte1]: 52
3371 04:37:42.611508
3372 04:37:42.611606 Set Vref, RX VrefLevel [Byte0]: 53
3373 04:37:42.614906 [Byte1]: 53
3374 04:37:42.619613
3375 04:37:42.619717 Set Vref, RX VrefLevel [Byte0]: 54
3376 04:37:42.622860 [Byte1]: 54
3377 04:37:42.627440
3378 04:37:42.627522 Set Vref, RX VrefLevel [Byte0]: 55
3379 04:37:42.630899 [Byte1]: 55
3380 04:37:42.635203
3381 04:37:42.635307 Set Vref, RX VrefLevel [Byte0]: 56
3382 04:37:42.638884 [Byte1]: 56
3383 04:37:42.643665
3384 04:37:42.643746 Set Vref, RX VrefLevel [Byte0]: 57
3385 04:37:42.646532 [Byte1]: 57
3386 04:37:42.650911
3387 04:37:42.651002 Set Vref, RX VrefLevel [Byte0]: 58
3388 04:37:42.654402 [Byte1]: 58
3389 04:37:42.659239
3390 04:37:42.659317 Set Vref, RX VrefLevel [Byte0]: 59
3391 04:37:42.662112 [Byte1]: 59
3392 04:37:42.666691
3393 04:37:42.666782 Set Vref, RX VrefLevel [Byte0]: 60
3394 04:37:42.670038 [Byte1]: 60
3395 04:37:42.675003
3396 04:37:42.675105 Set Vref, RX VrefLevel [Byte0]: 61
3397 04:37:42.677904 [Byte1]: 61
3398 04:37:42.682732
3399 04:37:42.682838 Set Vref, RX VrefLevel [Byte0]: 62
3400 04:37:42.686162 [Byte1]: 62
3401 04:37:42.690802
3402 04:37:42.690922 Set Vref, RX VrefLevel [Byte0]: 63
3403 04:37:42.693819 [Byte1]: 63
3404 04:37:42.698560
3405 04:37:42.698659 Set Vref, RX VrefLevel [Byte0]: 64
3406 04:37:42.702356 [Byte1]: 64
3407 04:37:42.706334
3408 04:37:42.706433 Set Vref, RX VrefLevel [Byte0]: 65
3409 04:37:42.710037 [Byte1]: 65
3410 04:37:42.714444
3411 04:37:42.714543 Set Vref, RX VrefLevel [Byte0]: 66
3412 04:37:42.717511 [Byte1]: 66
3413 04:37:42.722385
3414 04:37:42.722482 Set Vref, RX VrefLevel [Byte0]: 67
3415 04:37:42.725838 [Byte1]: 67
3416 04:37:42.730548
3417 04:37:42.730646 Set Vref, RX VrefLevel [Byte0]: 68
3418 04:37:42.733648 [Byte1]: 68
3419 04:37:42.738332
3420 04:37:42.738432 Set Vref, RX VrefLevel [Byte0]: 69
3421 04:37:42.741937 [Byte1]: 69
3422 04:37:42.745945
3423 04:37:42.746021 Set Vref, RX VrefLevel [Byte0]: 70
3424 04:37:42.749449 [Byte1]: 70
3425 04:37:42.754640
3426 04:37:42.754750 Set Vref, RX VrefLevel [Byte0]: 71
3427 04:37:42.757889 [Byte1]: 71
3428 04:37:42.761972
3429 04:37:42.762077 Final RX Vref Byte 0 = 56 to rank0
3430 04:37:42.765042 Final RX Vref Byte 1 = 55 to rank0
3431 04:37:42.768527 Final RX Vref Byte 0 = 56 to rank1
3432 04:37:42.772181 Final RX Vref Byte 1 = 55 to rank1==
3433 04:37:42.775657 Dram Type= 6, Freq= 0, CH_1, rank 0
3434 04:37:42.778895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 04:37:42.781961 ==
3436 04:37:42.782065 DQS Delay:
3437 04:37:42.782158 DQS0 = 0, DQS1 = 0
3438 04:37:42.785839 DQM Delay:
3439 04:37:42.785934 DQM0 = 116, DQM1 = 110
3440 04:37:42.788874 DQ Delay:
3441 04:37:42.792421 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3442 04:37:42.795328 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3443 04:37:42.799007 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3444 04:37:42.802021 DQ12 =118, DQ13 =114, DQ14 =118, DQ15 =114
3445 04:37:42.802120
3446 04:37:42.802220
3447 04:37:42.809167 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbe0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
3448 04:37:42.812132 CH1 RK0: MR19=303, MR18=FBE0
3449 04:37:42.818874 CH1_RK0: MR19=0x303, MR18=0xFBE0, DQSOSC=412, MR23=63, INC=38, DEC=25
3450 04:37:42.818951
3451 04:37:42.822594 ----->DramcWriteLeveling(PI) begin...
3452 04:37:42.822696 ==
3453 04:37:42.826161 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 04:37:42.829095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 04:37:42.829194 ==
3456 04:37:42.832616 Write leveling (Byte 0): 28 => 28
3457 04:37:42.835879 Write leveling (Byte 1): 28 => 28
3458 04:37:42.839174 DramcWriteLeveling(PI) end<-----
3459 04:37:42.839266
3460 04:37:42.839356 ==
3461 04:37:42.842559 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 04:37:42.846053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 04:37:42.849151 ==
3464 04:37:42.849249 [Gating] SW mode calibration
3465 04:37:42.856092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3466 04:37:42.862679 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3467 04:37:42.866339 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3468 04:37:42.872525 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3469 04:37:42.876031 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 04:37:42.879454 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 04:37:42.885930 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3472 04:37:42.889252 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3473 04:37:42.892830 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
3474 04:37:42.896256 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3475 04:37:42.903356 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 04:37:42.906318 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 04:37:42.909375 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3478 04:37:42.916443 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 04:37:42.919367 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 04:37:42.922941 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3481 04:37:42.930016 1 0 24 | B1->B0 | 2929 4242 | 0 0 | (0 0) (0 0)
3482 04:37:42.932994 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3483 04:37:42.936488 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 04:37:42.942897 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 04:37:42.946569 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 04:37:42.950001 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 04:37:42.953234 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 04:37:42.960192 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3489 04:37:42.963333 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3490 04:37:42.966364 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3491 04:37:42.973590 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 04:37:42.976756 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 04:37:42.980301 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 04:37:42.986989 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 04:37:42.989937 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 04:37:42.993410 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 04:37:43.000535 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 04:37:43.003449 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 04:37:43.006861 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 04:37:43.013400 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 04:37:43.016982 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 04:37:43.020612 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 04:37:43.023434 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 04:37:43.030146 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3505 04:37:43.033843 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3506 04:37:43.036875 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3507 04:37:43.040319 Total UI for P1: 0, mck2ui 16
3508 04:37:43.043816 best dqsien dly found for B0: ( 1, 3, 22)
3509 04:37:43.050130 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 04:37:43.050213 Total UI for P1: 0, mck2ui 16
3511 04:37:43.056827 best dqsien dly found for B1: ( 1, 3, 26)
3512 04:37:43.060325 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3513 04:37:43.063675 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3514 04:37:43.063757
3515 04:37:43.067069 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3516 04:37:43.070415 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3517 04:37:43.073378 [Gating] SW calibration Done
3518 04:37:43.073460 ==
3519 04:37:43.076943 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 04:37:43.080392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 04:37:43.080499 ==
3522 04:37:43.084093 RX Vref Scan: 0
3523 04:37:43.084175
3524 04:37:43.084239 RX Vref 0 -> 0, step: 1
3525 04:37:43.084299
3526 04:37:43.087193 RX Delay -40 -> 252, step: 8
3527 04:37:43.090449 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3528 04:37:43.097055 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3529 04:37:43.100168 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3530 04:37:43.103748 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3531 04:37:43.106936 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3532 04:37:43.110315 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3533 04:37:43.113754 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3534 04:37:43.120111 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3535 04:37:43.123938 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3536 04:37:43.127679 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3537 04:37:43.130437 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3538 04:37:43.133808 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3539 04:37:43.140266 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3540 04:37:43.144016 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3541 04:37:43.147702 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3542 04:37:43.150334 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3543 04:37:43.150407 ==
3544 04:37:43.153800 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 04:37:43.160411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 04:37:43.160489 ==
3547 04:37:43.160553 DQS Delay:
3548 04:37:43.160612 DQS0 = 0, DQS1 = 0
3549 04:37:43.163705 DQM Delay:
3550 04:37:43.163776 DQM0 = 113, DQM1 = 110
3551 04:37:43.167330 DQ Delay:
3552 04:37:43.170945 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3553 04:37:43.174361 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3554 04:37:43.177187 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3555 04:37:43.180401 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3556 04:37:43.180482
3557 04:37:43.180546
3558 04:37:43.180605 ==
3559 04:37:43.183901 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 04:37:43.187506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 04:37:43.187588 ==
3562 04:37:43.187652
3563 04:37:43.187712
3564 04:37:43.190420 TX Vref Scan disable
3565 04:37:43.194184 == TX Byte 0 ==
3566 04:37:43.197455 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3567 04:37:43.200618 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3568 04:37:43.204286 == TX Byte 1 ==
3569 04:37:43.207511 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3570 04:37:43.210629 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3571 04:37:43.210722 ==
3572 04:37:43.214917 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 04:37:43.217580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 04:37:43.220657 ==
3575 04:37:43.231090 TX Vref=22, minBit 2, minWin=25, winSum=419
3576 04:37:43.234368 TX Vref=24, minBit 7, minWin=25, winSum=425
3577 04:37:43.237368 TX Vref=26, minBit 2, minWin=26, winSum=430
3578 04:37:43.241013 TX Vref=28, minBit 0, minWin=27, winSum=433
3579 04:37:43.244713 TX Vref=30, minBit 2, minWin=26, winSum=432
3580 04:37:43.247351 TX Vref=32, minBit 3, minWin=26, winSum=435
3581 04:37:43.254209 [TxChooseVref] Worse bit 0, Min win 27, Win sum 433, Final Vref 28
3582 04:37:43.254290
3583 04:37:43.257796 Final TX Range 1 Vref 28
3584 04:37:43.257878
3585 04:37:43.257942 ==
3586 04:37:43.260892 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 04:37:43.264452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 04:37:43.264534 ==
3589 04:37:43.264598
3590 04:37:43.267841
3591 04:37:43.267924 TX Vref Scan disable
3592 04:37:43.270872 == TX Byte 0 ==
3593 04:37:43.274401 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3594 04:37:43.277305 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3595 04:37:43.280647 == TX Byte 1 ==
3596 04:37:43.284111 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3597 04:37:43.287420 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3598 04:37:43.287528
3599 04:37:43.290744 [DATLAT]
3600 04:37:43.290822 Freq=1200, CH1 RK1
3601 04:37:43.290895
3602 04:37:43.293953 DATLAT Default: 0xd
3603 04:37:43.294034 0, 0xFFFF, sum = 0
3604 04:37:43.297568 1, 0xFFFF, sum = 0
3605 04:37:43.297643 2, 0xFFFF, sum = 0
3606 04:37:43.300793 3, 0xFFFF, sum = 0
3607 04:37:43.300876 4, 0xFFFF, sum = 0
3608 04:37:43.303909 5, 0xFFFF, sum = 0
3609 04:37:43.303983 6, 0xFFFF, sum = 0
3610 04:37:43.307549 7, 0xFFFF, sum = 0
3611 04:37:43.307626 8, 0xFFFF, sum = 0
3612 04:37:43.310786 9, 0xFFFF, sum = 0
3613 04:37:43.313924 10, 0xFFFF, sum = 0
3614 04:37:43.314027 11, 0xFFFF, sum = 0
3615 04:37:43.317801 12, 0x0, sum = 1
3616 04:37:43.317884 13, 0x0, sum = 2
3617 04:37:43.317953 14, 0x0, sum = 3
3618 04:37:43.320623 15, 0x0, sum = 4
3619 04:37:43.320756 best_step = 13
3620 04:37:43.320822
3621 04:37:43.324561 ==
3622 04:37:43.324639 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 04:37:43.330694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 04:37:43.330772 ==
3625 04:37:43.330845 RX Vref Scan: 0
3626 04:37:43.330990
3627 04:37:43.334573 RX Vref 0 -> 0, step: 1
3628 04:37:43.334670
3629 04:37:43.337660 RX Delay -21 -> 252, step: 4
3630 04:37:43.341384 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3631 04:37:43.344135 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3632 04:37:43.350892 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3633 04:37:43.354511 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3634 04:37:43.357521 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3635 04:37:43.360908 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3636 04:37:43.364357 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3637 04:37:43.370931 iDelay=191, Bit 7, Center 110 (43 ~ 178) 136
3638 04:37:43.374483 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3639 04:37:43.377631 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3640 04:37:43.380741 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3641 04:37:43.384247 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3642 04:37:43.390816 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3643 04:37:43.394348 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3644 04:37:43.397381 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3645 04:37:43.400433 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3646 04:37:43.400538 ==
3647 04:37:43.404094 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 04:37:43.410544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 04:37:43.410625 ==
3650 04:37:43.410688 DQS Delay:
3651 04:37:43.410747 DQS0 = 0, DQS1 = 0
3652 04:37:43.414080 DQM Delay:
3653 04:37:43.414185 DQM0 = 113, DQM1 = 110
3654 04:37:43.417723 DQ Delay:
3655 04:37:43.420611 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3656 04:37:43.423804 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3657 04:37:43.427097 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3658 04:37:43.430456 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =120
3659 04:37:43.430536
3660 04:37:43.430598
3661 04:37:43.440402 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3662 04:37:43.440483 CH1 RK1: MR19=304, MR18=FA02
3663 04:37:43.447032 CH1_RK1: MR19=0x304, MR18=0xFA02, DQSOSC=409, MR23=63, INC=39, DEC=26
3664 04:37:43.450449 [RxdqsGatingPostProcess] freq 1200
3665 04:37:43.456984 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3666 04:37:43.460435 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 04:37:43.463838 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 04:37:43.467623 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 04:37:43.470423 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 04:37:43.473656 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 04:37:43.473738 best DQS1 dly(2T, 0.5T) = (0, 11)
3672 04:37:43.476999 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 04:37:43.480618 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3674 04:37:43.483566 Pre-setting of DQS Precalculation
3675 04:37:43.490497 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3676 04:37:43.496965 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3677 04:37:43.503812 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3678 04:37:43.503891
3679 04:37:43.503956
3680 04:37:43.507725 [Calibration Summary] 2400 Mbps
3681 04:37:43.507813 CH 0, Rank 0
3682 04:37:43.510547 SW Impedance : PASS
3683 04:37:43.513983 DUTY Scan : NO K
3684 04:37:43.514056 ZQ Calibration : PASS
3685 04:37:43.517400 Jitter Meter : NO K
3686 04:37:43.521142 CBT Training : PASS
3687 04:37:43.521221 Write leveling : PASS
3688 04:37:43.524349 RX DQS gating : PASS
3689 04:37:43.527412 RX DQ/DQS(RDDQC) : PASS
3690 04:37:43.527516 TX DQ/DQS : PASS
3691 04:37:43.530814 RX DATLAT : PASS
3692 04:37:43.530893 RX DQ/DQS(Engine): PASS
3693 04:37:43.534229 TX OE : NO K
3694 04:37:43.534309 All Pass.
3695 04:37:43.534372
3696 04:37:43.537508 CH 0, Rank 1
3697 04:37:43.537587 SW Impedance : PASS
3698 04:37:43.541250 DUTY Scan : NO K
3699 04:37:43.543802 ZQ Calibration : PASS
3700 04:37:43.543882 Jitter Meter : NO K
3701 04:37:43.547600 CBT Training : PASS
3702 04:37:43.550760 Write leveling : PASS
3703 04:37:43.550841 RX DQS gating : PASS
3704 04:37:43.554080 RX DQ/DQS(RDDQC) : PASS
3705 04:37:43.557334 TX DQ/DQS : PASS
3706 04:37:43.557438 RX DATLAT : PASS
3707 04:37:43.560797 RX DQ/DQS(Engine): PASS
3708 04:37:43.564294 TX OE : NO K
3709 04:37:43.564369 All Pass.
3710 04:37:43.564432
3711 04:37:43.564491 CH 1, Rank 0
3712 04:37:43.567688 SW Impedance : PASS
3713 04:37:43.570878 DUTY Scan : NO K
3714 04:37:43.570953 ZQ Calibration : PASS
3715 04:37:43.574604 Jitter Meter : NO K
3716 04:37:43.574677 CBT Training : PASS
3717 04:37:43.577374 Write leveling : PASS
3718 04:37:43.580696 RX DQS gating : PASS
3719 04:37:43.580810 RX DQ/DQS(RDDQC) : PASS
3720 04:37:43.584372 TX DQ/DQS : PASS
3721 04:37:43.587320 RX DATLAT : PASS
3722 04:37:43.587417 RX DQ/DQS(Engine): PASS
3723 04:37:43.590755 TX OE : NO K
3724 04:37:43.590863 All Pass.
3725 04:37:43.590958
3726 04:37:43.594359 CH 1, Rank 1
3727 04:37:43.594432 SW Impedance : PASS
3728 04:37:43.597753 DUTY Scan : NO K
3729 04:37:43.600891 ZQ Calibration : PASS
3730 04:37:43.600978 Jitter Meter : NO K
3731 04:37:43.604545 CBT Training : PASS
3732 04:37:43.607644 Write leveling : PASS
3733 04:37:43.607810 RX DQS gating : PASS
3734 04:37:43.610803 RX DQ/DQS(RDDQC) : PASS
3735 04:37:43.610954 TX DQ/DQS : PASS
3736 04:37:43.614070 RX DATLAT : PASS
3737 04:37:43.617681 RX DQ/DQS(Engine): PASS
3738 04:37:43.617759 TX OE : NO K
3739 04:37:43.621203 All Pass.
3740 04:37:43.621313
3741 04:37:43.621396 DramC Write-DBI off
3742 04:37:43.624110 PER_BANK_REFRESH: Hybrid Mode
3743 04:37:43.627722 TX_TRACKING: ON
3744 04:37:43.634209 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3745 04:37:43.637776 [FAST_K] Save calibration result to emmc
3746 04:37:43.641266 dramc_set_vcore_voltage set vcore to 650000
3747 04:37:43.644448 Read voltage for 600, 5
3748 04:37:43.644578 Vio18 = 0
3749 04:37:43.647488 Vcore = 650000
3750 04:37:43.647569 Vdram = 0
3751 04:37:43.647634 Vddq = 0
3752 04:37:43.650708 Vmddr = 0
3753 04:37:43.654272 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3754 04:37:43.661128 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3755 04:37:43.661228 MEM_TYPE=3, freq_sel=19
3756 04:37:43.664250 sv_algorithm_assistance_LP4_1600
3757 04:37:43.667616 ============ PULL DRAM RESETB DOWN ============
3758 04:37:43.674318 ========== PULL DRAM RESETB DOWN end =========
3759 04:37:43.677957 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3760 04:37:43.680882 ===================================
3761 04:37:43.684573 LPDDR4 DRAM CONFIGURATION
3762 04:37:43.687494 ===================================
3763 04:37:43.687577 EX_ROW_EN[0] = 0x0
3764 04:37:43.690785 EX_ROW_EN[1] = 0x0
3765 04:37:43.694526 LP4Y_EN = 0x0
3766 04:37:43.694630 WORK_FSP = 0x0
3767 04:37:43.697820 WL = 0x2
3768 04:37:43.697902 RL = 0x2
3769 04:37:43.700887 BL = 0x2
3770 04:37:43.700970 RPST = 0x0
3771 04:37:43.704380 RD_PRE = 0x0
3772 04:37:43.704463 WR_PRE = 0x1
3773 04:37:43.707490 WR_PST = 0x0
3774 04:37:43.707572 DBI_WR = 0x0
3775 04:37:43.710913 DBI_RD = 0x0
3776 04:37:43.710995 OTF = 0x1
3777 04:37:43.714504 ===================================
3778 04:37:43.717715 ===================================
3779 04:37:43.720805 ANA top config
3780 04:37:43.724442 ===================================
3781 04:37:43.724521 DLL_ASYNC_EN = 0
3782 04:37:43.728081 ALL_SLAVE_EN = 1
3783 04:37:43.731137 NEW_RANK_MODE = 1
3784 04:37:43.734472 DLL_IDLE_MODE = 1
3785 04:37:43.734555 LP45_APHY_COMB_EN = 1
3786 04:37:43.738047 TX_ODT_DIS = 1
3787 04:37:43.740965 NEW_8X_MODE = 1
3788 04:37:43.744735 ===================================
3789 04:37:43.748315 ===================================
3790 04:37:43.751014 data_rate = 1200
3791 04:37:43.754926 CKR = 1
3792 04:37:43.755037 DQ_P2S_RATIO = 8
3793 04:37:43.758016 ===================================
3794 04:37:43.761477 CA_P2S_RATIO = 8
3795 04:37:43.764444 DQ_CA_OPEN = 0
3796 04:37:43.768301 DQ_SEMI_OPEN = 0
3797 04:37:43.771207 CA_SEMI_OPEN = 0
3798 04:37:43.774774 CA_FULL_RATE = 0
3799 04:37:43.774874 DQ_CKDIV4_EN = 1
3800 04:37:43.778482 CA_CKDIV4_EN = 1
3801 04:37:43.781333 CA_PREDIV_EN = 0
3802 04:37:43.784565 PH8_DLY = 0
3803 04:37:43.787785 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3804 04:37:43.787875 DQ_AAMCK_DIV = 4
3805 04:37:43.791524 CA_AAMCK_DIV = 4
3806 04:37:43.794477 CA_ADMCK_DIV = 4
3807 04:37:43.797898 DQ_TRACK_CA_EN = 0
3808 04:37:43.801517 CA_PICK = 600
3809 04:37:43.804815 CA_MCKIO = 600
3810 04:37:43.808159 MCKIO_SEMI = 0
3811 04:37:43.808261 PLL_FREQ = 2288
3812 04:37:43.811323 DQ_UI_PI_RATIO = 32
3813 04:37:43.814911 CA_UI_PI_RATIO = 0
3814 04:37:43.818126 ===================================
3815 04:37:43.821524 ===================================
3816 04:37:43.825164 memory_type:LPDDR4
3817 04:37:43.825314 GP_NUM : 10
3818 04:37:43.828149 SRAM_EN : 1
3819 04:37:43.831658 MD32_EN : 0
3820 04:37:43.834792 ===================================
3821 04:37:43.834909 [ANA_INIT] >>>>>>>>>>>>>>
3822 04:37:43.838181 <<<<<< [CONFIGURE PHASE]: ANA_TX
3823 04:37:43.841483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3824 04:37:43.845160 ===================================
3825 04:37:43.848103 data_rate = 1200,PCW = 0X5800
3826 04:37:43.851868 ===================================
3827 04:37:43.855244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3828 04:37:43.861443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 04:37:43.864679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 04:37:43.872150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3831 04:37:43.875004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3832 04:37:43.878362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3833 04:37:43.878484 [ANA_INIT] flow start
3834 04:37:43.881659 [ANA_INIT] PLL >>>>>>>>
3835 04:37:43.885012 [ANA_INIT] PLL <<<<<<<<
3836 04:37:43.885092 [ANA_INIT] MIDPI >>>>>>>>
3837 04:37:43.888689 [ANA_INIT] MIDPI <<<<<<<<
3838 04:37:43.891577 [ANA_INIT] DLL >>>>>>>>
3839 04:37:43.891658 [ANA_INIT] flow end
3840 04:37:43.898172 ============ LP4 DIFF to SE enter ============
3841 04:37:43.901819 ============ LP4 DIFF to SE exit ============
3842 04:37:43.904875 [ANA_INIT] <<<<<<<<<<<<<
3843 04:37:43.908050 [Flow] Enable top DCM control >>>>>
3844 04:37:43.911457 [Flow] Enable top DCM control <<<<<
3845 04:37:43.911533 Enable DLL master slave shuffle
3846 04:37:43.918345 ==============================================================
3847 04:37:43.921548 Gating Mode config
3848 04:37:43.925078 ==============================================================
3849 04:37:43.928483 Config description:
3850 04:37:43.938424 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3851 04:37:43.944894 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3852 04:37:43.948577 SELPH_MODE 0: By rank 1: By Phase
3853 04:37:43.955340 ==============================================================
3854 04:37:43.958786 GAT_TRACK_EN = 1
3855 04:37:43.961886 RX_GATING_MODE = 2
3856 04:37:43.961967 RX_GATING_TRACK_MODE = 2
3857 04:37:43.965535 SELPH_MODE = 1
3858 04:37:43.968970 PICG_EARLY_EN = 1
3859 04:37:43.971900 VALID_LAT_VALUE = 1
3860 04:37:43.978396 ==============================================================
3861 04:37:43.982063 Enter into Gating configuration >>>>
3862 04:37:43.985614 Exit from Gating configuration <<<<
3863 04:37:43.988565 Enter into DVFS_PRE_config >>>>>
3864 04:37:43.998780 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3865 04:37:44.002389 Exit from DVFS_PRE_config <<<<<
3866 04:37:44.004896 Enter into PICG configuration >>>>
3867 04:37:44.008862 Exit from PICG configuration <<<<
3868 04:37:44.011900 [RX_INPUT] configuration >>>>>
3869 04:37:44.015203 [RX_INPUT] configuration <<<<<
3870 04:37:44.018813 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3871 04:37:44.025336 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3872 04:37:44.031995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 04:37:44.035372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 04:37:44.042110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 04:37:44.048839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 04:37:44.052908 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3877 04:37:44.055558 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3878 04:37:44.062206 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3879 04:37:44.065613 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3880 04:37:44.068591 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3881 04:37:44.075476 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 04:37:44.079050 ===================================
3883 04:37:44.079136 LPDDR4 DRAM CONFIGURATION
3884 04:37:44.082191 ===================================
3885 04:37:44.085302 EX_ROW_EN[0] = 0x0
3886 04:37:44.085383 EX_ROW_EN[1] = 0x0
3887 04:37:44.088457 LP4Y_EN = 0x0
3888 04:37:44.092195 WORK_FSP = 0x0
3889 04:37:44.092276 WL = 0x2
3890 04:37:44.095610 RL = 0x2
3891 04:37:44.095691 BL = 0x2
3892 04:37:44.098770 RPST = 0x0
3893 04:37:44.098875 RD_PRE = 0x0
3894 04:37:44.102109 WR_PRE = 0x1
3895 04:37:44.102201 WR_PST = 0x0
3896 04:37:44.105267 DBI_WR = 0x0
3897 04:37:44.105347 DBI_RD = 0x0
3898 04:37:44.108942 OTF = 0x1
3899 04:37:44.112121 ===================================
3900 04:37:44.115585 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3901 04:37:44.118802 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3902 04:37:44.122430 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 04:37:44.125417 ===================================
3904 04:37:44.128892 LPDDR4 DRAM CONFIGURATION
3905 04:37:44.131967 ===================================
3906 04:37:44.135544 EX_ROW_EN[0] = 0x10
3907 04:37:44.135624 EX_ROW_EN[1] = 0x0
3908 04:37:44.138984 LP4Y_EN = 0x0
3909 04:37:44.139064 WORK_FSP = 0x0
3910 04:37:44.142005 WL = 0x2
3911 04:37:44.142085 RL = 0x2
3912 04:37:44.145504 BL = 0x2
3913 04:37:44.145584 RPST = 0x0
3914 04:37:44.148918 RD_PRE = 0x0
3915 04:37:44.148997 WR_PRE = 0x1
3916 04:37:44.151751 WR_PST = 0x0
3917 04:37:44.155387 DBI_WR = 0x0
3918 04:37:44.155467 DBI_RD = 0x0
3919 04:37:44.158587 OTF = 0x1
3920 04:37:44.161898 ===================================
3921 04:37:44.165331 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3922 04:37:44.170398 nWR fixed to 30
3923 04:37:44.173795 [ModeRegInit_LP4] CH0 RK0
3924 04:37:44.173875 [ModeRegInit_LP4] CH0 RK1
3925 04:37:44.177085 [ModeRegInit_LP4] CH1 RK0
3926 04:37:44.180289 [ModeRegInit_LP4] CH1 RK1
3927 04:37:44.180369 match AC timing 17
3928 04:37:44.187131 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3929 04:37:44.190256 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3930 04:37:44.193961 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3931 04:37:44.200359 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3932 04:37:44.204009 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3933 04:37:44.204093 ==
3934 04:37:44.206825 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 04:37:44.210522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 04:37:44.210603 ==
3937 04:37:44.216868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 04:37:44.223690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3939 04:37:44.226840 [CA 0] Center 36 (6~66) winsize 61
3940 04:37:44.230012 [CA 1] Center 36 (6~66) winsize 61
3941 04:37:44.234028 [CA 2] Center 34 (4~65) winsize 62
3942 04:37:44.236739 [CA 3] Center 34 (4~65) winsize 62
3943 04:37:44.240191 [CA 4] Center 34 (4~65) winsize 62
3944 04:37:44.243898 [CA 5] Center 33 (3~64) winsize 62
3945 04:37:44.243978
3946 04:37:44.246942 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3947 04:37:44.247022
3948 04:37:44.250060 [CATrainingPosCal] consider 1 rank data
3949 04:37:44.253502 u2DelayCellTimex100 = 270/100 ps
3950 04:37:44.257047 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3951 04:37:44.260442 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3952 04:37:44.263682 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3953 04:37:44.266983 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3954 04:37:44.270459 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3955 04:37:44.273715 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 04:37:44.273796
3957 04:37:44.280581 CA PerBit enable=1, Macro0, CA PI delay=33
3958 04:37:44.280661
3959 04:37:44.283596 [CBTSetCACLKResult] CA Dly = 33
3960 04:37:44.283676 CS Dly: 4 (0~35)
3961 04:37:44.283740 ==
3962 04:37:44.286912 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 04:37:44.290326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 04:37:44.290407 ==
3965 04:37:44.296926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 04:37:44.303904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3967 04:37:44.307207 [CA 0] Center 36 (6~66) winsize 61
3968 04:37:44.310066 [CA 1] Center 36 (6~66) winsize 61
3969 04:37:44.313849 [CA 2] Center 34 (4~65) winsize 62
3970 04:37:44.316722 [CA 3] Center 34 (4~65) winsize 62
3971 04:37:44.320419 [CA 4] Center 33 (3~64) winsize 62
3972 04:37:44.323465 [CA 5] Center 33 (3~64) winsize 62
3973 04:37:44.323546
3974 04:37:44.327311 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3975 04:37:44.327392
3976 04:37:44.330113 [CATrainingPosCal] consider 2 rank data
3977 04:37:44.333391 u2DelayCellTimex100 = 270/100 ps
3978 04:37:44.337000 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3979 04:37:44.340016 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3980 04:37:44.343579 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3981 04:37:44.347036 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3982 04:37:44.350207 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3983 04:37:44.353997 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 04:37:44.354099
3985 04:37:44.360411 CA PerBit enable=1, Macro0, CA PI delay=33
3986 04:37:44.360518
3987 04:37:44.363827 [CBTSetCACLKResult] CA Dly = 33
3988 04:37:44.363908 CS Dly: 4 (0~36)
3989 04:37:44.363972
3990 04:37:44.366896 ----->DramcWriteLeveling(PI) begin...
3991 04:37:44.366978 ==
3992 04:37:44.370335 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 04:37:44.373603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 04:37:44.373684 ==
3995 04:37:44.376844 Write leveling (Byte 0): 35 => 35
3996 04:37:44.380143 Write leveling (Byte 1): 33 => 33
3997 04:37:44.383707 DramcWriteLeveling(PI) end<-----
3998 04:37:44.383788
3999 04:37:44.383853 ==
4000 04:37:44.386877 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 04:37:44.390366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 04:37:44.393400 ==
4003 04:37:44.393481 [Gating] SW mode calibration
4004 04:37:44.403652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4005 04:37:44.406856 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4006 04:37:44.410497 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 04:37:44.416939 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 04:37:44.419996 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 04:37:44.423711 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4010 04:37:44.430277 0 9 16 | B1->B0 | 3131 2929 | 0 0 | (0 1) (1 1)
4011 04:37:44.433475 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 04:37:44.437275 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 04:37:44.443553 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 04:37:44.446961 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 04:37:44.450033 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 04:37:44.457008 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 04:37:44.460491 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4018 04:37:44.463581 0 10 16 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
4019 04:37:44.470311 0 10 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4020 04:37:44.473274 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 04:37:44.476801 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 04:37:44.480340 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 04:37:44.487185 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 04:37:44.490613 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 04:37:44.493396 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 04:37:44.500177 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4027 04:37:44.503933 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 04:37:44.507232 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 04:37:44.513471 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 04:37:44.517174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 04:37:44.520375 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 04:37:44.527121 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 04:37:44.530168 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 04:37:44.533785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 04:37:44.540158 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 04:37:44.543587 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 04:37:44.546888 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 04:37:44.553927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 04:37:44.557219 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 04:37:44.560280 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 04:37:44.563744 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 04:37:44.570374 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4043 04:37:44.574039 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4044 04:37:44.576925 Total UI for P1: 0, mck2ui 16
4045 04:37:44.580402 best dqsien dly found for B0: ( 0, 13, 16)
4046 04:37:44.583970 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 04:37:44.586977 Total UI for P1: 0, mck2ui 16
4048 04:37:44.590792 best dqsien dly found for B1: ( 0, 13, 18)
4049 04:37:44.594020 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4050 04:37:44.597361 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4051 04:37:44.600823
4052 04:37:44.603814 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4053 04:37:44.607282 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4054 04:37:44.610360 [Gating] SW calibration Done
4055 04:37:44.610441 ==
4056 04:37:44.613598 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 04:37:44.616925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 04:37:44.617007 ==
4059 04:37:44.617071 RX Vref Scan: 0
4060 04:37:44.617131
4061 04:37:44.620404 RX Vref 0 -> 0, step: 1
4062 04:37:44.620485
4063 04:37:44.623749 RX Delay -230 -> 252, step: 16
4064 04:37:44.627260 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4065 04:37:44.630726 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4066 04:37:44.637484 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4067 04:37:44.640484 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4068 04:37:44.643619 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4069 04:37:44.647100 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4070 04:37:44.654019 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4071 04:37:44.657678 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4072 04:37:44.660663 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4073 04:37:44.663807 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4074 04:37:44.667538 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4075 04:37:44.673934 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4076 04:37:44.677129 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4077 04:37:44.680776 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4078 04:37:44.684216 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4079 04:37:44.690460 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4080 04:37:44.690542 ==
4081 04:37:44.693985 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 04:37:44.696985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 04:37:44.697096 ==
4084 04:37:44.697198 DQS Delay:
4085 04:37:44.700761 DQS0 = 0, DQS1 = 0
4086 04:37:44.700849 DQM Delay:
4087 04:37:44.703772 DQM0 = 42, DQM1 = 34
4088 04:37:44.703853 DQ Delay:
4089 04:37:44.707109 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4090 04:37:44.710261 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4091 04:37:44.713816 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4092 04:37:44.717360 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4093 04:37:44.717441
4094 04:37:44.717505
4095 04:37:44.717564 ==
4096 04:37:44.720776 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 04:37:44.723961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 04:37:44.724043 ==
4099 04:37:44.724107
4100 04:37:44.724177
4101 04:37:44.727232 TX Vref Scan disable
4102 04:37:44.730728 == TX Byte 0 ==
4103 04:37:44.734214 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4104 04:37:44.737771 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4105 04:37:44.740509 == TX Byte 1 ==
4106 04:37:44.744154 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4107 04:37:44.747416 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4108 04:37:44.747497 ==
4109 04:37:44.750909 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 04:37:44.757083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 04:37:44.757164 ==
4112 04:37:44.757229
4113 04:37:44.757288
4114 04:37:44.757346 TX Vref Scan disable
4115 04:37:44.761488 == TX Byte 0 ==
4116 04:37:44.764784 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4117 04:37:44.768011 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4118 04:37:44.771921 == TX Byte 1 ==
4119 04:37:44.774963 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4120 04:37:44.778346 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4121 04:37:44.781407
4122 04:37:44.781561 [DATLAT]
4123 04:37:44.781665 Freq=600, CH0 RK0
4124 04:37:44.781742
4125 04:37:44.784968 DATLAT Default: 0x9
4126 04:37:44.785049 0, 0xFFFF, sum = 0
4127 04:37:44.788450 1, 0xFFFF, sum = 0
4128 04:37:44.788532 2, 0xFFFF, sum = 0
4129 04:37:44.791341 3, 0xFFFF, sum = 0
4130 04:37:44.791424 4, 0xFFFF, sum = 0
4131 04:37:44.794996 5, 0xFFFF, sum = 0
4132 04:37:44.795107 6, 0xFFFF, sum = 0
4133 04:37:44.798476 7, 0xFFFF, sum = 0
4134 04:37:44.798575 8, 0x0, sum = 1
4135 04:37:44.801453 9, 0x0, sum = 2
4136 04:37:44.801557 10, 0x0, sum = 3
4137 04:37:44.804959 11, 0x0, sum = 4
4138 04:37:44.805061 best_step = 9
4139 04:37:44.805153
4140 04:37:44.805239 ==
4141 04:37:44.808339 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 04:37:44.814718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 04:37:44.814825 ==
4144 04:37:44.814902 RX Vref Scan: 1
4145 04:37:44.814963
4146 04:37:44.818060 RX Vref 0 -> 0, step: 1
4147 04:37:44.818162
4148 04:37:44.821715 RX Delay -179 -> 252, step: 8
4149 04:37:44.821798
4150 04:37:44.825115 Set Vref, RX VrefLevel [Byte0]: 53
4151 04:37:44.828497 [Byte1]: 52
4152 04:37:44.828578
4153 04:37:44.831765 Final RX Vref Byte 0 = 53 to rank0
4154 04:37:44.835287 Final RX Vref Byte 1 = 52 to rank0
4155 04:37:44.838378 Final RX Vref Byte 0 = 53 to rank1
4156 04:37:44.841865 Final RX Vref Byte 1 = 52 to rank1==
4157 04:37:44.845320 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 04:37:44.848383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 04:37:44.848464 ==
4160 04:37:44.848529 DQS Delay:
4161 04:37:44.852025 DQS0 = 0, DQS1 = 0
4162 04:37:44.852106 DQM Delay:
4163 04:37:44.855005 DQM0 = 43, DQM1 = 33
4164 04:37:44.855086 DQ Delay:
4165 04:37:44.858512 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4166 04:37:44.861948 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4167 04:37:44.865186 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4168 04:37:44.868282 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4169 04:37:44.868362
4170 04:37:44.868426
4171 04:37:44.878774 [DQSOSCAuto] RK0, (LSB)MR18= 0x411f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4172 04:37:44.878857 CH0 RK0: MR19=808, MR18=411F
4173 04:37:44.885609 CH0_RK0: MR19=0x808, MR18=0x411F, DQSOSC=397, MR23=63, INC=166, DEC=110
4174 04:37:44.885690
4175 04:37:44.888603 ----->DramcWriteLeveling(PI) begin...
4176 04:37:44.888707 ==
4177 04:37:44.892026 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 04:37:44.898559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 04:37:44.898641 ==
4180 04:37:44.902285 Write leveling (Byte 0): 32 => 32
4181 04:37:44.902366 Write leveling (Byte 1): 31 => 31
4182 04:37:44.905337 DramcWriteLeveling(PI) end<-----
4183 04:37:44.905444
4184 04:37:44.905536 ==
4185 04:37:44.908792 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 04:37:44.915302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 04:37:44.915387 ==
4188 04:37:44.918736 [Gating] SW mode calibration
4189 04:37:44.925198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4190 04:37:44.929004 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4191 04:37:44.935171 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 04:37:44.938437 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 04:37:44.941800 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 04:37:44.945455 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4195 04:37:44.951853 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4196 04:37:44.955496 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 04:37:44.958793 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 04:37:44.965219 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 04:37:44.968902 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 04:37:44.972252 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 04:37:44.978577 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 04:37:44.982142 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4203 04:37:44.985697 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4204 04:37:44.991918 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 04:37:44.995385 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 04:37:44.999286 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 04:37:45.005525 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 04:37:45.009191 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 04:37:45.012240 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 04:37:45.018745 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4211 04:37:45.022272 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4212 04:37:45.025789 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 04:37:45.029102 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 04:37:45.035623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 04:37:45.039126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 04:37:45.042587 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 04:37:45.049269 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 04:37:45.052326 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 04:37:45.055364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 04:37:45.062055 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 04:37:45.065656 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 04:37:45.069343 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 04:37:45.075889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 04:37:45.079105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 04:37:45.082752 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4226 04:37:45.089042 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4227 04:37:45.092320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4228 04:37:45.095774 Total UI for P1: 0, mck2ui 16
4229 04:37:45.099511 best dqsien dly found for B0: ( 0, 13, 10)
4230 04:37:45.102414 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 04:37:45.106338 Total UI for P1: 0, mck2ui 16
4232 04:37:45.109046 best dqsien dly found for B1: ( 0, 13, 16)
4233 04:37:45.112215 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4234 04:37:45.115968 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4235 04:37:45.116050
4236 04:37:45.118908 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4237 04:37:45.125998 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4238 04:37:45.126079 [Gating] SW calibration Done
4239 04:37:45.126144 ==
4240 04:37:45.128878 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 04:37:45.135915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 04:37:45.135997 ==
4243 04:37:45.136061 RX Vref Scan: 0
4244 04:37:45.136120
4245 04:37:45.138993 RX Vref 0 -> 0, step: 1
4246 04:37:45.139074
4247 04:37:45.142581 RX Delay -230 -> 252, step: 16
4248 04:37:45.146018 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4249 04:37:45.149373 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4250 04:37:45.152150 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4251 04:37:45.159452 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4252 04:37:45.162746 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4253 04:37:45.165575 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4254 04:37:45.168947 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4255 04:37:45.175739 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4256 04:37:45.178530 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4257 04:37:45.182179 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4258 04:37:45.185339 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4259 04:37:45.188875 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4260 04:37:45.195533 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4261 04:37:45.198985 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4262 04:37:45.201873 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4263 04:37:45.205367 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4264 04:37:45.208934 ==
4265 04:37:45.212370 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 04:37:45.215569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 04:37:45.215640 ==
4268 04:37:45.215705 DQS Delay:
4269 04:37:45.219041 DQS0 = 0, DQS1 = 0
4270 04:37:45.219123 DQM Delay:
4271 04:37:45.222889 DQM0 = 39, DQM1 = 31
4272 04:37:45.222969 DQ Delay:
4273 04:37:45.225719 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4274 04:37:45.229159 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4275 04:37:45.232463 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4276 04:37:45.235533 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4277 04:37:45.235614
4278 04:37:45.235678
4279 04:37:45.235738 ==
4280 04:37:45.239220 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 04:37:45.242175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 04:37:45.242257 ==
4283 04:37:45.242321
4284 04:37:45.242380
4285 04:37:45.245443 TX Vref Scan disable
4286 04:37:45.249101 == TX Byte 0 ==
4287 04:37:45.252303 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4288 04:37:45.255783 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4289 04:37:45.259354 == TX Byte 1 ==
4290 04:37:45.262792 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4291 04:37:45.265646 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4292 04:37:45.265727 ==
4293 04:37:45.269069 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 04:37:45.273081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 04:37:45.273162 ==
4296 04:37:45.275783
4297 04:37:45.275863
4298 04:37:45.275927 TX Vref Scan disable
4299 04:37:45.279380 == TX Byte 0 ==
4300 04:37:45.282775 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4301 04:37:45.286229 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4302 04:37:45.289231 == TX Byte 1 ==
4303 04:37:45.292899 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4304 04:37:45.296263 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4305 04:37:45.299562
4306 04:37:45.299643 [DATLAT]
4307 04:37:45.299708 Freq=600, CH0 RK1
4308 04:37:45.299768
4309 04:37:45.302930 DATLAT Default: 0x9
4310 04:37:45.303016 0, 0xFFFF, sum = 0
4311 04:37:45.306426 1, 0xFFFF, sum = 0
4312 04:37:45.306508 2, 0xFFFF, sum = 0
4313 04:37:45.309509 3, 0xFFFF, sum = 0
4314 04:37:45.309591 4, 0xFFFF, sum = 0
4315 04:37:45.312872 5, 0xFFFF, sum = 0
4316 04:37:45.312954 6, 0xFFFF, sum = 0
4317 04:37:45.315887 7, 0xFFFF, sum = 0
4318 04:37:45.315964 8, 0x0, sum = 1
4319 04:37:45.319574 9, 0x0, sum = 2
4320 04:37:45.319655 10, 0x0, sum = 3
4321 04:37:45.323043 11, 0x0, sum = 4
4322 04:37:45.323130 best_step = 9
4323 04:37:45.323198
4324 04:37:45.323261 ==
4325 04:37:45.326202 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 04:37:45.332599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 04:37:45.332713 ==
4328 04:37:45.332796 RX Vref Scan: 0
4329 04:37:45.332871
4330 04:37:45.336215 RX Vref 0 -> 0, step: 1
4331 04:37:45.336324
4332 04:37:45.339122 RX Delay -195 -> 252, step: 8
4333 04:37:45.342863 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4334 04:37:45.349410 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4335 04:37:45.352998 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4336 04:37:45.355925 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4337 04:37:45.359442 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4338 04:37:45.362587 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4339 04:37:45.369821 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4340 04:37:45.372507 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4341 04:37:45.376302 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4342 04:37:45.379101 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4343 04:37:45.386027 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4344 04:37:45.389454 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4345 04:37:45.392865 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4346 04:37:45.395979 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4347 04:37:45.399407 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4348 04:37:45.406289 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4349 04:37:45.406369 ==
4350 04:37:45.409448 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 04:37:45.412885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 04:37:45.412967 ==
4353 04:37:45.413030 DQS Delay:
4354 04:37:45.416185 DQS0 = 0, DQS1 = 0
4355 04:37:45.416294 DQM Delay:
4356 04:37:45.419144 DQM0 = 39, DQM1 = 33
4357 04:37:45.419251 DQ Delay:
4358 04:37:45.422816 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4359 04:37:45.425768 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4360 04:37:45.429632 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4361 04:37:45.432825 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4362 04:37:45.432905
4363 04:37:45.432968
4364 04:37:45.442905 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4365 04:37:45.442987 CH0 RK1: MR19=808, MR18=4B2D
4366 04:37:45.449835 CH0_RK1: MR19=0x808, MR18=0x4B2D, DQSOSC=395, MR23=63, INC=168, DEC=112
4367 04:37:45.452739 [RxdqsGatingPostProcess] freq 600
4368 04:37:45.459135 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4369 04:37:45.463133 Pre-setting of DQS Precalculation
4370 04:37:45.465749 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4371 04:37:45.465855 ==
4372 04:37:45.469226 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 04:37:45.472879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 04:37:45.472987 ==
4375 04:37:45.479353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 04:37:45.485727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 04:37:45.489229 [CA 0] Center 35 (5~65) winsize 61
4378 04:37:45.492683 [CA 1] Center 35 (5~65) winsize 61
4379 04:37:45.496386 [CA 2] Center 34 (4~65) winsize 62
4380 04:37:45.499466 [CA 3] Center 33 (3~64) winsize 62
4381 04:37:45.502860 [CA 4] Center 34 (3~65) winsize 63
4382 04:37:45.505913 [CA 5] Center 33 (3~64) winsize 62
4383 04:37:45.506020
4384 04:37:45.509111 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 04:37:45.509219
4386 04:37:45.512751 [CATrainingPosCal] consider 1 rank data
4387 04:37:45.515552 u2DelayCellTimex100 = 270/100 ps
4388 04:37:45.518998 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4389 04:37:45.522825 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4390 04:37:45.526059 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 04:37:45.529442 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4392 04:37:45.532387 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4393 04:37:45.539309 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 04:37:45.539416
4395 04:37:45.542802 CA PerBit enable=1, Macro0, CA PI delay=33
4396 04:37:45.542907
4397 04:37:45.546190 [CBTSetCACLKResult] CA Dly = 33
4398 04:37:45.546295 CS Dly: 5 (0~36)
4399 04:37:45.546388 ==
4400 04:37:45.549254 Dram Type= 6, Freq= 0, CH_1, rank 1
4401 04:37:45.552578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 04:37:45.552722 ==
4403 04:37:45.559340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 04:37:45.565948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4405 04:37:45.569441 [CA 0] Center 35 (5~66) winsize 62
4406 04:37:45.573140 [CA 1] Center 36 (6~66) winsize 61
4407 04:37:45.575873 [CA 2] Center 34 (4~65) winsize 62
4408 04:37:45.579607 [CA 3] Center 34 (3~65) winsize 63
4409 04:37:45.582567 [CA 4] Center 34 (3~65) winsize 63
4410 04:37:45.586016 [CA 5] Center 33 (3~64) winsize 62
4411 04:37:45.586121
4412 04:37:45.589556 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4413 04:37:45.589654
4414 04:37:45.592880 [CATrainingPosCal] consider 2 rank data
4415 04:37:45.596472 u2DelayCellTimex100 = 270/100 ps
4416 04:37:45.599612 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4417 04:37:45.602610 CA1 delay=35 (6~65),Diff = 2 PI (19 cell)
4418 04:37:45.606404 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 04:37:45.609560 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 04:37:45.612536 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4421 04:37:45.616183 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 04:37:45.619470
4423 04:37:45.622473 CA PerBit enable=1, Macro0, CA PI delay=33
4424 04:37:45.622580
4425 04:37:45.626199 [CBTSetCACLKResult] CA Dly = 33
4426 04:37:45.626312 CS Dly: 5 (0~36)
4427 04:37:45.626404
4428 04:37:45.629883 ----->DramcWriteLeveling(PI) begin...
4429 04:37:45.629993 ==
4430 04:37:45.632822 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 04:37:45.636369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 04:37:45.636480 ==
4433 04:37:45.639346 Write leveling (Byte 0): 30 => 30
4434 04:37:45.642886 Write leveling (Byte 1): 30 => 30
4435 04:37:45.646038 DramcWriteLeveling(PI) end<-----
4436 04:37:45.646148
4437 04:37:45.646240 ==
4438 04:37:45.649611 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 04:37:45.656061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 04:37:45.656193 ==
4441 04:37:45.656308 [Gating] SW mode calibration
4442 04:37:45.666246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4443 04:37:45.669611 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4444 04:37:45.672799 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 04:37:45.679437 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 04:37:45.682818 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4447 04:37:45.686033 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
4448 04:37:45.693117 0 9 16 | B1->B0 | 2727 2525 | 1 0 | (0 0) (0 0)
4449 04:37:45.696454 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4450 04:37:45.699410 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 04:37:45.706243 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 04:37:45.709659 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4453 04:37:45.712972 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 04:37:45.720180 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 04:37:45.722824 0 10 12 | B1->B0 | 2727 2b2b | 0 0 | (0 0) (0 0)
4456 04:37:45.726364 0 10 16 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
4457 04:37:45.733112 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 04:37:45.736505 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 04:37:45.740120 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 04:37:45.746659 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 04:37:45.749695 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 04:37:45.753304 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 04:37:45.756721 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 04:37:45.763467 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 04:37:45.766892 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 04:37:45.770103 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 04:37:45.776533 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 04:37:45.779768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 04:37:45.783508 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 04:37:45.790128 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 04:37:45.793363 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 04:37:45.796753 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 04:37:45.803137 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 04:37:45.806582 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 04:37:45.809985 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 04:37:45.816641 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 04:37:45.820561 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 04:37:45.823303 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4479 04:37:45.826931 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4480 04:37:45.833471 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4481 04:37:45.836807 Total UI for P1: 0, mck2ui 16
4482 04:37:45.840176 best dqsien dly found for B0: ( 0, 13, 10)
4483 04:37:45.843308 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 04:37:45.846998 Total UI for P1: 0, mck2ui 16
4485 04:37:45.850185 best dqsien dly found for B1: ( 0, 13, 14)
4486 04:37:45.853780 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4487 04:37:45.856879 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4488 04:37:45.857286
4489 04:37:45.860355 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4490 04:37:45.863416 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4491 04:37:45.866976 [Gating] SW calibration Done
4492 04:37:45.867384 ==
4493 04:37:45.870330 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 04:37:45.876745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 04:37:45.877221 ==
4496 04:37:45.877697 RX Vref Scan: 0
4497 04:37:45.878018
4498 04:37:45.880482 RX Vref 0 -> 0, step: 1
4499 04:37:45.881241
4500 04:37:45.883326 RX Delay -230 -> 252, step: 16
4501 04:37:45.887141 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4502 04:37:45.890609 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4503 04:37:45.893762 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4504 04:37:45.900783 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4505 04:37:45.903856 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4506 04:37:45.907093 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4507 04:37:45.910499 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4508 04:37:45.913703 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4509 04:37:45.920894 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4510 04:37:45.923408 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4511 04:37:45.927230 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4512 04:37:45.930363 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4513 04:37:45.937132 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4514 04:37:45.940727 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4515 04:37:45.944241 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4516 04:37:45.947479 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4517 04:37:45.947897 ==
4518 04:37:45.950890 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 04:37:45.953987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 04:37:45.957370 ==
4521 04:37:45.957927 DQS Delay:
4522 04:37:45.958403 DQS0 = 0, DQS1 = 0
4523 04:37:45.960477 DQM Delay:
4524 04:37:45.960934 DQM0 = 43, DQM1 = 35
4525 04:37:45.964001 DQ Delay:
4526 04:37:45.964466 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4527 04:37:45.967759 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4528 04:37:45.970676 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4529 04:37:45.974126 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4530 04:37:45.977764
4531 04:37:45.978176
4532 04:37:45.978504 ==
4533 04:37:45.980527 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 04:37:45.983699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 04:37:45.983780 ==
4536 04:37:45.983845
4537 04:37:45.983905
4538 04:37:45.987051 TX Vref Scan disable
4539 04:37:45.987132 == TX Byte 0 ==
4540 04:37:45.993686 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4541 04:37:45.997227 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4542 04:37:45.997309 == TX Byte 1 ==
4543 04:37:46.003393 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 04:37:46.006486 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 04:37:46.006568 ==
4546 04:37:46.010350 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 04:37:46.013529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 04:37:46.013610 ==
4549 04:37:46.013675
4550 04:37:46.013735
4551 04:37:46.016578 TX Vref Scan disable
4552 04:37:46.020075 == TX Byte 0 ==
4553 04:37:46.023658 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4554 04:37:46.026538 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4555 04:37:46.029924 == TX Byte 1 ==
4556 04:37:46.033723 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4557 04:37:46.036560 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4558 04:37:46.036644
4559 04:37:46.040104 [DATLAT]
4560 04:37:46.040185 Freq=600, CH1 RK0
4561 04:37:46.040250
4562 04:37:46.043380 DATLAT Default: 0x9
4563 04:37:46.043461 0, 0xFFFF, sum = 0
4564 04:37:46.046643 1, 0xFFFF, sum = 0
4565 04:37:46.046725 2, 0xFFFF, sum = 0
4566 04:37:46.050179 3, 0xFFFF, sum = 0
4567 04:37:46.050262 4, 0xFFFF, sum = 0
4568 04:37:46.053708 5, 0xFFFF, sum = 0
4569 04:37:46.053790 6, 0xFFFF, sum = 0
4570 04:37:46.056573 7, 0xFFFF, sum = 0
4571 04:37:46.056680 8, 0x0, sum = 1
4572 04:37:46.060608 9, 0x0, sum = 2
4573 04:37:46.060713 10, 0x0, sum = 3
4574 04:37:46.063514 11, 0x0, sum = 4
4575 04:37:46.063597 best_step = 9
4576 04:37:46.063661
4577 04:37:46.063721 ==
4578 04:37:46.066506 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 04:37:46.070231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 04:37:46.073984 ==
4581 04:37:46.074063 RX Vref Scan: 1
4582 04:37:46.074126
4583 04:37:46.076969 RX Vref 0 -> 0, step: 1
4584 04:37:46.077048
4585 04:37:46.079785 RX Delay -195 -> 252, step: 8
4586 04:37:46.079864
4587 04:37:46.083334 Set Vref, RX VrefLevel [Byte0]: 56
4588 04:37:46.086587 [Byte1]: 55
4589 04:37:46.086666
4590 04:37:46.090320 Final RX Vref Byte 0 = 56 to rank0
4591 04:37:46.093256 Final RX Vref Byte 1 = 55 to rank0
4592 04:37:46.096305 Final RX Vref Byte 0 = 56 to rank1
4593 04:37:46.099674 Final RX Vref Byte 1 = 55 to rank1==
4594 04:37:46.103488 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 04:37:46.106657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 04:37:46.106737 ==
4597 04:37:46.106801 DQS Delay:
4598 04:37:46.110111 DQS0 = 0, DQS1 = 0
4599 04:37:46.110203 DQM Delay:
4600 04:37:46.113419 DQM0 = 41, DQM1 = 34
4601 04:37:46.113500 DQ Delay:
4602 04:37:46.116455 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4603 04:37:46.119951 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4604 04:37:46.123244 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4605 04:37:46.126901 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4606 04:37:46.126982
4607 04:37:46.127047
4608 04:37:46.136843 [DQSOSCAuto] RK0, (LSB)MR18= 0x450b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4609 04:37:46.136964 CH1 RK0: MR19=808, MR18=450B
4610 04:37:46.143623 CH1_RK0: MR19=0x808, MR18=0x450B, DQSOSC=396, MR23=63, INC=167, DEC=111
4611 04:37:46.143723
4612 04:37:46.146620 ----->DramcWriteLeveling(PI) begin...
4613 04:37:46.146694 ==
4614 04:37:46.150109 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 04:37:46.156537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 04:37:46.156644 ==
4617 04:37:46.160255 Write leveling (Byte 0): 32 => 32
4618 04:37:46.163014 Write leveling (Byte 1): 30 => 30
4619 04:37:46.163112 DramcWriteLeveling(PI) end<-----
4620 04:37:46.163212
4621 04:37:46.166513 ==
4622 04:37:46.169820 Dram Type= 6, Freq= 0, CH_1, rank 1
4623 04:37:46.173104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 04:37:46.173186 ==
4625 04:37:46.176727 [Gating] SW mode calibration
4626 04:37:46.183404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4627 04:37:46.186399 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4628 04:37:46.193612 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 04:37:46.196455 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4630 04:37:46.200025 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4631 04:37:46.206502 0 9 12 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (1 1)
4632 04:37:46.210158 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4633 04:37:46.213814 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 04:37:46.216739 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 04:37:46.223549 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 04:37:46.226659 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 04:37:46.230011 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4638 04:37:46.236647 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 04:37:46.239860 0 10 12 | B1->B0 | 3131 4141 | 0 1 | (0 0) (0 0)
4640 04:37:46.243365 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4641 04:37:46.250195 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 04:37:46.253238 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 04:37:46.256867 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 04:37:46.263245 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 04:37:46.266349 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 04:37:46.269677 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4647 04:37:46.276769 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4648 04:37:46.280158 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 04:37:46.283540 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 04:37:46.289858 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 04:37:46.293352 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 04:37:46.296957 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 04:37:46.303678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 04:37:46.307196 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 04:37:46.309997 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 04:37:46.313578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 04:37:46.320094 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 04:37:46.323662 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 04:37:46.327124 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 04:37:46.333298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 04:37:46.337140 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 04:37:46.340177 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4663 04:37:46.346689 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4664 04:37:46.349929 Total UI for P1: 0, mck2ui 16
4665 04:37:46.353379 best dqsien dly found for B0: ( 0, 13, 8)
4666 04:37:46.356661 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 04:37:46.360144 Total UI for P1: 0, mck2ui 16
4668 04:37:46.363527 best dqsien dly found for B1: ( 0, 13, 14)
4669 04:37:46.366639 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4670 04:37:46.370236 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4671 04:37:46.370317
4672 04:37:46.373298 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4673 04:37:46.376991 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4674 04:37:46.380001 [Gating] SW calibration Done
4675 04:37:46.380082 ==
4676 04:37:46.383223 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 04:37:46.387045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 04:37:46.390151 ==
4679 04:37:46.390256 RX Vref Scan: 0
4680 04:37:46.390364
4681 04:37:46.393979 RX Vref 0 -> 0, step: 1
4682 04:37:46.394052
4683 04:37:46.396723 RX Delay -230 -> 252, step: 16
4684 04:37:46.399819 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4685 04:37:46.403302 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4686 04:37:46.407047 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4687 04:37:46.410072 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4688 04:37:46.416964 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4689 04:37:46.420038 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4690 04:37:46.423702 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4691 04:37:46.427242 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4692 04:37:46.433681 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4693 04:37:46.436605 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4694 04:37:46.439934 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4695 04:37:46.443706 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4696 04:37:46.447138 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4697 04:37:46.453341 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4698 04:37:46.456879 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4699 04:37:46.460306 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4700 04:37:46.460387 ==
4701 04:37:46.463580 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 04:37:46.466672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 04:37:46.470005 ==
4704 04:37:46.470086 DQS Delay:
4705 04:37:46.470157 DQS0 = 0, DQS1 = 0
4706 04:37:46.473648 DQM Delay:
4707 04:37:46.473729 DQM0 = 40, DQM1 = 38
4708 04:37:46.476501 DQ Delay:
4709 04:37:46.480396 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4710 04:37:46.480481 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4711 04:37:46.483170 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4712 04:37:46.487070 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4713 04:37:46.489943
4714 04:37:46.490024
4715 04:37:46.490088 ==
4716 04:37:46.493739 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 04:37:46.496928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 04:37:46.497010 ==
4719 04:37:46.497075
4720 04:37:46.497134
4721 04:37:46.500297 TX Vref Scan disable
4722 04:37:46.500378 == TX Byte 0 ==
4723 04:37:46.507090 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4724 04:37:46.509777 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4725 04:37:46.509858 == TX Byte 1 ==
4726 04:37:46.516692 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4727 04:37:46.520162 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4728 04:37:46.520243 ==
4729 04:37:46.523263 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 04:37:46.526892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 04:37:46.526963 ==
4732 04:37:46.527024
4733 04:37:46.527081
4734 04:37:46.529836 TX Vref Scan disable
4735 04:37:46.533678 == TX Byte 0 ==
4736 04:37:46.537086 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4737 04:37:46.540024 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4738 04:37:46.543511 == TX Byte 1 ==
4739 04:37:46.546559 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4740 04:37:46.550379 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4741 04:37:46.550459
4742 04:37:46.553529 [DATLAT]
4743 04:37:46.553610 Freq=600, CH1 RK1
4744 04:37:46.553675
4745 04:37:46.556995 DATLAT Default: 0x9
4746 04:37:46.557076 0, 0xFFFF, sum = 0
4747 04:37:46.559997 1, 0xFFFF, sum = 0
4748 04:37:46.560079 2, 0xFFFF, sum = 0
4749 04:37:46.563755 3, 0xFFFF, sum = 0
4750 04:37:46.563837 4, 0xFFFF, sum = 0
4751 04:37:46.566975 5, 0xFFFF, sum = 0
4752 04:37:46.567057 6, 0xFFFF, sum = 0
4753 04:37:46.570393 7, 0xFFFF, sum = 0
4754 04:37:46.570475 8, 0x0, sum = 1
4755 04:37:46.574005 9, 0x0, sum = 2
4756 04:37:46.574087 10, 0x0, sum = 3
4757 04:37:46.577158 11, 0x0, sum = 4
4758 04:37:46.577239 best_step = 9
4759 04:37:46.577304
4760 04:37:46.577364 ==
4761 04:37:46.580459 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 04:37:46.583476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 04:37:46.587000 ==
4764 04:37:46.587080 RX Vref Scan: 0
4765 04:37:46.587144
4766 04:37:46.590359 RX Vref 0 -> 0, step: 1
4767 04:37:46.590445
4768 04:37:46.593250 RX Delay -179 -> 252, step: 8
4769 04:37:46.596936 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4770 04:37:46.599960 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4771 04:37:46.607012 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4772 04:37:46.609900 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4773 04:37:46.613446 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4774 04:37:46.616820 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4775 04:37:46.619958 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4776 04:37:46.627091 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4777 04:37:46.630355 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4778 04:37:46.633502 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4779 04:37:46.636578 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4780 04:37:46.644095 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4781 04:37:46.646844 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4782 04:37:46.650413 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4783 04:37:46.653473 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4784 04:37:46.660560 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4785 04:37:46.660641 ==
4786 04:37:46.663841 Dram Type= 6, Freq= 0, CH_1, rank 1
4787 04:37:46.666849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4788 04:37:46.666923 ==
4789 04:37:46.666991 DQS Delay:
4790 04:37:46.670343 DQS0 = 0, DQS1 = 0
4791 04:37:46.670440 DQM Delay:
4792 04:37:46.673343 DQM0 = 38, DQM1 = 33
4793 04:37:46.673441 DQ Delay:
4794 04:37:46.676776 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4795 04:37:46.680248 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4796 04:37:46.683654 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4797 04:37:46.686966 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4798 04:37:46.687047
4799 04:37:46.687111
4800 04:37:46.693593 [DQSOSCAuto] RK1, (LSB)MR18= 0x3241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4801 04:37:46.696852 CH1 RK1: MR19=808, MR18=3241
4802 04:37:46.703569 CH1_RK1: MR19=0x808, MR18=0x3241, DQSOSC=397, MR23=63, INC=166, DEC=110
4803 04:37:46.707121 [RxdqsGatingPostProcess] freq 600
4804 04:37:46.713709 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4805 04:37:46.713821 Pre-setting of DQS Precalculation
4806 04:37:46.720726 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4807 04:37:46.727128 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4808 04:37:46.733792 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4809 04:37:46.733876
4810 04:37:46.733941
4811 04:37:46.737058 [Calibration Summary] 1200 Mbps
4812 04:37:46.737168 CH 0, Rank 0
4813 04:37:46.740495 SW Impedance : PASS
4814 04:37:46.743954 DUTY Scan : NO K
4815 04:37:46.744064 ZQ Calibration : PASS
4816 04:37:46.747455 Jitter Meter : NO K
4817 04:37:46.750715 CBT Training : PASS
4818 04:37:46.750795 Write leveling : PASS
4819 04:37:46.753503 RX DQS gating : PASS
4820 04:37:46.757089 RX DQ/DQS(RDDQC) : PASS
4821 04:37:46.757170 TX DQ/DQS : PASS
4822 04:37:46.760656 RX DATLAT : PASS
4823 04:37:46.764019 RX DQ/DQS(Engine): PASS
4824 04:37:46.764099 TX OE : NO K
4825 04:37:46.767398 All Pass.
4826 04:37:46.767479
4827 04:37:46.767543 CH 0, Rank 1
4828 04:37:46.770466 SW Impedance : PASS
4829 04:37:46.770547 DUTY Scan : NO K
4830 04:37:46.773780 ZQ Calibration : PASS
4831 04:37:46.777373 Jitter Meter : NO K
4832 04:37:46.777453 CBT Training : PASS
4833 04:37:46.780407 Write leveling : PASS
4834 04:37:46.780488 RX DQS gating : PASS
4835 04:37:46.783899 RX DQ/DQS(RDDQC) : PASS
4836 04:37:46.787139 TX DQ/DQS : PASS
4837 04:37:46.787221 RX DATLAT : PASS
4838 04:37:46.790523 RX DQ/DQS(Engine): PASS
4839 04:37:46.793796 TX OE : NO K
4840 04:37:46.793870 All Pass.
4841 04:37:46.793932
4842 04:37:46.793991 CH 1, Rank 0
4843 04:37:46.796916 SW Impedance : PASS
4844 04:37:46.800545 DUTY Scan : NO K
4845 04:37:46.800644 ZQ Calibration : PASS
4846 04:37:46.803546 Jitter Meter : NO K
4847 04:37:46.807107 CBT Training : PASS
4848 04:37:46.807208 Write leveling : PASS
4849 04:37:46.810331 RX DQS gating : PASS
4850 04:37:46.814124 RX DQ/DQS(RDDQC) : PASS
4851 04:37:46.814205 TX DQ/DQS : PASS
4852 04:37:46.816945 RX DATLAT : PASS
4853 04:37:46.817025 RX DQ/DQS(Engine): PASS
4854 04:37:46.820450 TX OE : NO K
4855 04:37:46.820561 All Pass.
4856 04:37:46.820653
4857 04:37:46.823574 CH 1, Rank 1
4858 04:37:46.823665 SW Impedance : PASS
4859 04:37:46.827206 DUTY Scan : NO K
4860 04:37:46.830353 ZQ Calibration : PASS
4861 04:37:46.830434 Jitter Meter : NO K
4862 04:37:46.833866 CBT Training : PASS
4863 04:37:46.837011 Write leveling : PASS
4864 04:37:46.837092 RX DQS gating : PASS
4865 04:37:46.840502 RX DQ/DQS(RDDQC) : PASS
4866 04:37:46.843933 TX DQ/DQS : PASS
4867 04:37:46.844014 RX DATLAT : PASS
4868 04:37:46.847127 RX DQ/DQS(Engine): PASS
4869 04:37:46.850417 TX OE : NO K
4870 04:37:46.850498 All Pass.
4871 04:37:46.850562
4872 04:37:46.850621 DramC Write-DBI off
4873 04:37:46.854328 PER_BANK_REFRESH: Hybrid Mode
4874 04:37:46.857189 TX_TRACKING: ON
4875 04:37:46.863569 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4876 04:37:46.867184 [FAST_K] Save calibration result to emmc
4877 04:37:46.874085 dramc_set_vcore_voltage set vcore to 662500
4878 04:37:46.874166 Read voltage for 933, 3
4879 04:37:46.876982 Vio18 = 0
4880 04:37:46.877063 Vcore = 662500
4881 04:37:46.877127 Vdram = 0
4882 04:37:46.877187 Vddq = 0
4883 04:37:46.880782 Vmddr = 0
4884 04:37:46.883724 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4885 04:37:46.890896 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4886 04:37:46.890977 MEM_TYPE=3, freq_sel=17
4887 04:37:46.893876 sv_algorithm_assistance_LP4_1600
4888 04:37:46.900828 ============ PULL DRAM RESETB DOWN ============
4889 04:37:46.904174 ========== PULL DRAM RESETB DOWN end =========
4890 04:37:46.907634 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4891 04:37:46.910816 ===================================
4892 04:37:46.913987 LPDDR4 DRAM CONFIGURATION
4893 04:37:46.917576 ===================================
4894 04:37:46.920783 EX_ROW_EN[0] = 0x0
4895 04:37:46.920863 EX_ROW_EN[1] = 0x0
4896 04:37:46.923902 LP4Y_EN = 0x0
4897 04:37:46.923982 WORK_FSP = 0x0
4898 04:37:46.927549 WL = 0x3
4899 04:37:46.927630 RL = 0x3
4900 04:37:46.930542 BL = 0x2
4901 04:37:46.930629 RPST = 0x0
4902 04:37:46.934054 RD_PRE = 0x0
4903 04:37:46.934162 WR_PRE = 0x1
4904 04:37:46.937587 WR_PST = 0x0
4905 04:37:46.937662 DBI_WR = 0x0
4906 04:37:46.940495 DBI_RD = 0x0
4907 04:37:46.940620 OTF = 0x1
4908 04:37:46.944166 ===================================
4909 04:37:46.947829 ===================================
4910 04:37:46.950658 ANA top config
4911 04:37:46.954245 ===================================
4912 04:37:46.954327 DLL_ASYNC_EN = 0
4913 04:37:46.957342 ALL_SLAVE_EN = 1
4914 04:37:46.960889 NEW_RANK_MODE = 1
4915 04:37:46.964061 DLL_IDLE_MODE = 1
4916 04:37:46.967481 LP45_APHY_COMB_EN = 1
4917 04:37:46.967562 TX_ODT_DIS = 1
4918 04:37:46.970783 NEW_8X_MODE = 1
4919 04:37:46.974127 ===================================
4920 04:37:46.977209 ===================================
4921 04:37:46.980523 data_rate = 1866
4922 04:37:46.983825 CKR = 1
4923 04:37:46.987605 DQ_P2S_RATIO = 8
4924 04:37:46.990773 ===================================
4925 04:37:46.990853 CA_P2S_RATIO = 8
4926 04:37:46.994145 DQ_CA_OPEN = 0
4927 04:37:46.997750 DQ_SEMI_OPEN = 0
4928 04:37:47.000802 CA_SEMI_OPEN = 0
4929 04:37:47.004182 CA_FULL_RATE = 0
4930 04:37:47.007934 DQ_CKDIV4_EN = 1
4931 04:37:47.008014 CA_CKDIV4_EN = 1
4932 04:37:47.010998 CA_PREDIV_EN = 0
4933 04:37:47.014046 PH8_DLY = 0
4934 04:37:47.017611 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4935 04:37:47.020586 DQ_AAMCK_DIV = 4
4936 04:37:47.020687 CA_AAMCK_DIV = 4
4937 04:37:47.024922 CA_ADMCK_DIV = 4
4938 04:37:47.027454 DQ_TRACK_CA_EN = 0
4939 04:37:47.030791 CA_PICK = 933
4940 04:37:47.033898 CA_MCKIO = 933
4941 04:37:47.037727 MCKIO_SEMI = 0
4942 04:37:47.041260 PLL_FREQ = 3732
4943 04:37:47.041341 DQ_UI_PI_RATIO = 32
4944 04:37:47.044110 CA_UI_PI_RATIO = 0
4945 04:37:47.047767 ===================================
4946 04:37:47.050806 ===================================
4947 04:37:47.054308 memory_type:LPDDR4
4948 04:37:47.057835 GP_NUM : 10
4949 04:37:47.057916 SRAM_EN : 1
4950 04:37:47.060947 MD32_EN : 0
4951 04:37:47.064547 ===================================
4952 04:37:47.067426 [ANA_INIT] >>>>>>>>>>>>>>
4953 04:37:47.067536 <<<<<< [CONFIGURE PHASE]: ANA_TX
4954 04:37:47.071210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4955 04:37:47.074263 ===================================
4956 04:37:47.077518 data_rate = 1866,PCW = 0X8f00
4957 04:37:47.081104 ===================================
4958 04:37:47.084456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4959 04:37:47.091285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4960 04:37:47.097495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4961 04:37:47.101011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4962 04:37:47.104600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4963 04:37:47.107529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4964 04:37:47.111408 [ANA_INIT] flow start
4965 04:37:47.111490 [ANA_INIT] PLL >>>>>>>>
4966 04:37:47.114205 [ANA_INIT] PLL <<<<<<<<
4967 04:37:47.117924 [ANA_INIT] MIDPI >>>>>>>>
4968 04:37:47.118005 [ANA_INIT] MIDPI <<<<<<<<
4969 04:37:47.121614 [ANA_INIT] DLL >>>>>>>>
4970 04:37:47.124780 [ANA_INIT] flow end
4971 04:37:47.128397 ============ LP4 DIFF to SE enter ============
4972 04:37:47.131233 ============ LP4 DIFF to SE exit ============
4973 04:37:47.134634 [ANA_INIT] <<<<<<<<<<<<<
4974 04:37:47.138221 [Flow] Enable top DCM control >>>>>
4975 04:37:47.141400 [Flow] Enable top DCM control <<<<<
4976 04:37:47.144532 Enable DLL master slave shuffle
4977 04:37:47.148160 ==============================================================
4978 04:37:47.151490 Gating Mode config
4979 04:37:47.154816 ==============================================================
4980 04:37:47.158285 Config description:
4981 04:37:47.167792 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4982 04:37:47.174929 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4983 04:37:47.177923 SELPH_MODE 0: By rank 1: By Phase
4984 04:37:47.184827 ==============================================================
4985 04:37:47.188351 GAT_TRACK_EN = 1
4986 04:37:47.191375 RX_GATING_MODE = 2
4987 04:37:47.195035 RX_GATING_TRACK_MODE = 2
4988 04:37:47.198277 SELPH_MODE = 1
4989 04:37:47.198358 PICG_EARLY_EN = 1
4990 04:37:47.201513 VALID_LAT_VALUE = 1
4991 04:37:47.208250 ==============================================================
4992 04:37:47.211235 Enter into Gating configuration >>>>
4993 04:37:47.214520 Exit from Gating configuration <<<<
4994 04:37:47.218070 Enter into DVFS_PRE_config >>>>>
4995 04:37:47.228205 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4996 04:37:47.231615 Exit from DVFS_PRE_config <<<<<
4997 04:37:47.235050 Enter into PICG configuration >>>>
4998 04:37:47.238606 Exit from PICG configuration <<<<
4999 04:37:47.241491 [RX_INPUT] configuration >>>>>
5000 04:37:47.245292 [RX_INPUT] configuration <<<<<
5001 04:37:47.248107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5002 04:37:47.255172 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5003 04:37:47.261424 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5004 04:37:47.268088 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5005 04:37:47.271776 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5006 04:37:47.278562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5007 04:37:47.281982 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5008 04:37:47.288388 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5009 04:37:47.291512 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5010 04:37:47.294943 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5011 04:37:47.298093 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5012 04:37:47.304969 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5013 04:37:47.308318 ===================================
5014 04:37:47.308403 LPDDR4 DRAM CONFIGURATION
5015 04:37:47.311825 ===================================
5016 04:37:47.314754 EX_ROW_EN[0] = 0x0
5017 04:37:47.318277 EX_ROW_EN[1] = 0x0
5018 04:37:47.318358 LP4Y_EN = 0x0
5019 04:37:47.321535 WORK_FSP = 0x0
5020 04:37:47.321616 WL = 0x3
5021 04:37:47.325103 RL = 0x3
5022 04:37:47.325184 BL = 0x2
5023 04:37:47.328002 RPST = 0x0
5024 04:37:47.328108 RD_PRE = 0x0
5025 04:37:47.331409 WR_PRE = 0x1
5026 04:37:47.331492 WR_PST = 0x0
5027 04:37:47.334830 DBI_WR = 0x0
5028 04:37:47.334936 DBI_RD = 0x0
5029 04:37:47.338184 OTF = 0x1
5030 04:37:47.341435 ===================================
5031 04:37:47.344553 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5032 04:37:47.348112 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5033 04:37:47.354804 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5034 04:37:47.358303 ===================================
5035 04:37:47.358384 LPDDR4 DRAM CONFIGURATION
5036 04:37:47.362091 ===================================
5037 04:37:47.364989 EX_ROW_EN[0] = 0x10
5038 04:37:47.365071 EX_ROW_EN[1] = 0x0
5039 04:37:47.368595 LP4Y_EN = 0x0
5040 04:37:47.371316 WORK_FSP = 0x0
5041 04:37:47.371397 WL = 0x3
5042 04:37:47.375150 RL = 0x3
5043 04:37:47.375231 BL = 0x2
5044 04:37:47.378071 RPST = 0x0
5045 04:37:47.378151 RD_PRE = 0x0
5046 04:37:47.381622 WR_PRE = 0x1
5047 04:37:47.381703 WR_PST = 0x0
5048 04:37:47.384702 DBI_WR = 0x0
5049 04:37:47.384801 DBI_RD = 0x0
5050 04:37:47.388329 OTF = 0x1
5051 04:37:47.391402 ===================================
5052 04:37:47.395098 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5053 04:37:47.400401 nWR fixed to 30
5054 04:37:47.403850 [ModeRegInit_LP4] CH0 RK0
5055 04:37:47.403930 [ModeRegInit_LP4] CH0 RK1
5056 04:37:47.407079 [ModeRegInit_LP4] CH1 RK0
5057 04:37:47.410584 [ModeRegInit_LP4] CH1 RK1
5058 04:37:47.410665 match AC timing 9
5059 04:37:47.416966 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5060 04:37:47.420600 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5061 04:37:47.424249 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5062 04:37:47.430989 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5063 04:37:47.434222 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5064 04:37:47.434303 ==
5065 04:37:47.437550 Dram Type= 6, Freq= 0, CH_0, rank 0
5066 04:37:47.440810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 04:37:47.440891 ==
5068 04:37:47.446919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 04:37:47.454017 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5070 04:37:47.457263 [CA 0] Center 38 (8~69) winsize 62
5071 04:37:47.460565 [CA 1] Center 38 (7~69) winsize 63
5072 04:37:47.464069 [CA 2] Center 35 (5~66) winsize 62
5073 04:37:47.467337 [CA 3] Center 35 (5~66) winsize 62
5074 04:37:47.470401 [CA 4] Center 34 (4~64) winsize 61
5075 04:37:47.473658 [CA 5] Center 34 (4~64) winsize 61
5076 04:37:47.473745
5077 04:37:47.477367 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5078 04:37:47.477523
5079 04:37:47.480285 [CATrainingPosCal] consider 1 rank data
5080 04:37:47.483703 u2DelayCellTimex100 = 270/100 ps
5081 04:37:47.487290 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5082 04:37:47.490443 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5083 04:37:47.493999 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5084 04:37:47.497120 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5085 04:37:47.500596 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5086 04:37:47.503564 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5087 04:37:47.503666
5088 04:37:47.507546 CA PerBit enable=1, Macro0, CA PI delay=34
5089 04:37:47.510346
5090 04:37:47.510447 [CBTSetCACLKResult] CA Dly = 34
5091 04:37:47.514141 CS Dly: 6 (0~37)
5092 04:37:47.514243 ==
5093 04:37:47.517184 Dram Type= 6, Freq= 0, CH_0, rank 1
5094 04:37:47.520313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 04:37:47.520412 ==
5096 04:37:47.527408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5097 04:37:47.533776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5098 04:37:47.537228 [CA 0] Center 38 (8~69) winsize 62
5099 04:37:47.540879 [CA 1] Center 38 (8~69) winsize 62
5100 04:37:47.543759 [CA 2] Center 35 (5~66) winsize 62
5101 04:37:47.547813 [CA 3] Center 35 (5~66) winsize 62
5102 04:37:47.550713 [CA 4] Center 33 (3~64) winsize 62
5103 04:37:47.554346 [CA 5] Center 33 (3~64) winsize 62
5104 04:37:47.554445
5105 04:37:47.557411 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5106 04:37:47.557519
5107 04:37:47.560661 [CATrainingPosCal] consider 2 rank data
5108 04:37:47.563940 u2DelayCellTimex100 = 270/100 ps
5109 04:37:47.567279 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5110 04:37:47.570570 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5111 04:37:47.574180 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5112 04:37:47.577362 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5113 04:37:47.581016 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5114 04:37:47.584305 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5115 04:37:47.584404
5116 04:37:47.587441 CA PerBit enable=1, Macro0, CA PI delay=34
5117 04:37:47.587544
5118 04:37:47.590550 [CBTSetCACLKResult] CA Dly = 34
5119 04:37:47.594386 CS Dly: 7 (0~39)
5120 04:37:47.594490
5121 04:37:47.597488 ----->DramcWriteLeveling(PI) begin...
5122 04:37:47.597594 ==
5123 04:37:47.600485 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 04:37:47.603935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 04:37:47.604034 ==
5126 04:37:47.607102 Write leveling (Byte 0): 30 => 30
5127 04:37:47.610654 Write leveling (Byte 1): 29 => 29
5128 04:37:47.614331 DramcWriteLeveling(PI) end<-----
5129 04:37:47.614438
5130 04:37:47.614529 ==
5131 04:37:47.617313 Dram Type= 6, Freq= 0, CH_0, rank 0
5132 04:37:47.620436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 04:37:47.620537 ==
5134 04:37:47.623850 [Gating] SW mode calibration
5135 04:37:47.630416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5136 04:37:47.637420 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5137 04:37:47.640865 0 14 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5138 04:37:47.647316 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5139 04:37:47.650832 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 04:37:47.654289 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 04:37:47.657124 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 04:37:47.663945 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 04:37:47.667269 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 04:37:47.670761 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5145 04:37:47.677396 0 15 0 | B1->B0 | 3131 2828 | 0 0 | (0 1) (0 0)
5146 04:37:47.680927 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5147 04:37:47.684188 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 04:37:47.690544 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 04:37:47.693914 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 04:37:47.697458 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 04:37:47.704069 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 04:37:47.707386 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5153 04:37:47.710869 1 0 0 | B1->B0 | 2d2d 3a3a | 0 0 | (0 0) (1 1)
5154 04:37:47.717069 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 04:37:47.720839 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 04:37:47.723788 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 04:37:47.730768 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 04:37:47.734115 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 04:37:47.737399 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 04:37:47.741111 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 04:37:47.747674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 04:37:47.750540 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5163 04:37:47.754236 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 04:37:47.760879 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 04:37:47.764143 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 04:37:47.767777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 04:37:47.774312 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 04:37:47.777740 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 04:37:47.780743 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 04:37:47.787857 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 04:37:47.790897 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 04:37:47.794252 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 04:37:47.800792 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 04:37:47.804430 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 04:37:47.807444 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 04:37:47.814438 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5177 04:37:47.817756 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5178 04:37:47.821015 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5179 04:37:47.824021 Total UI for P1: 0, mck2ui 16
5180 04:37:47.827555 best dqsien dly found for B0: ( 1, 2, 30)
5181 04:37:47.831556 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 04:37:47.834322 Total UI for P1: 0, mck2ui 16
5183 04:37:47.837698 best dqsien dly found for B1: ( 1, 3, 0)
5184 04:37:47.840997 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5185 04:37:47.844207 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5186 04:37:47.844308
5187 04:37:47.851402 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5188 04:37:47.854317 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5189 04:37:47.854419 [Gating] SW calibration Done
5190 04:37:47.857788 ==
5191 04:37:47.860824 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 04:37:47.864258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 04:37:47.864367 ==
5194 04:37:47.864459 RX Vref Scan: 0
5195 04:37:47.864563
5196 04:37:47.868171 RX Vref 0 -> 0, step: 1
5197 04:37:47.868331
5198 04:37:47.871034 RX Delay -80 -> 252, step: 8
5199 04:37:47.874568 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5200 04:37:47.877900 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5201 04:37:47.881759 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5202 04:37:47.887966 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5203 04:37:47.890878 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5204 04:37:47.894293 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5205 04:37:47.897974 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5206 04:37:47.900952 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5207 04:37:47.904745 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5208 04:37:47.911006 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5209 04:37:47.914788 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5210 04:37:47.917679 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5211 04:37:47.921253 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5212 04:37:47.924422 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5213 04:37:47.930876 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5214 04:37:47.933947 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5215 04:37:47.934054 ==
5216 04:37:47.937607 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 04:37:47.940629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 04:37:47.940769 ==
5219 04:37:47.940856 DQS Delay:
5220 04:37:47.944460 DQS0 = 0, DQS1 = 0
5221 04:37:47.944562 DQM Delay:
5222 04:37:47.947467 DQM0 = 98, DQM1 = 86
5223 04:37:47.947562 DQ Delay:
5224 04:37:47.950812 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =91
5225 04:37:47.954068 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5226 04:37:47.957252 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5227 04:37:47.960799 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5228 04:37:47.960882
5229 04:37:47.961002
5230 04:37:47.961092 ==
5231 04:37:47.964094 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 04:37:47.970669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 04:37:47.970767 ==
5234 04:37:47.970860
5235 04:37:47.970946
5236 04:37:47.971030 TX Vref Scan disable
5237 04:37:47.974262 == TX Byte 0 ==
5238 04:37:47.977328 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5239 04:37:47.980557 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5240 04:37:47.984300 == TX Byte 1 ==
5241 04:37:47.988018 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5242 04:37:47.990831 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5243 04:37:47.994204 ==
5244 04:37:47.997707 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 04:37:48.001301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 04:37:48.001415 ==
5247 04:37:48.001508
5248 04:37:48.001596
5249 04:37:48.003981 TX Vref Scan disable
5250 04:37:48.004050 == TX Byte 0 ==
5251 04:37:48.010640 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5252 04:37:48.014362 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5253 04:37:48.014463 == TX Byte 1 ==
5254 04:37:48.020610 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5255 04:37:48.024211 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5256 04:37:48.024312
5257 04:37:48.024406 [DATLAT]
5258 04:37:48.027295 Freq=933, CH0 RK0
5259 04:37:48.027390
5260 04:37:48.027483 DATLAT Default: 0xd
5261 04:37:48.030728 0, 0xFFFF, sum = 0
5262 04:37:48.030826 1, 0xFFFF, sum = 0
5263 04:37:48.033976 2, 0xFFFF, sum = 0
5264 04:37:48.034086 3, 0xFFFF, sum = 0
5265 04:37:48.037382 4, 0xFFFF, sum = 0
5266 04:37:48.037486 5, 0xFFFF, sum = 0
5267 04:37:48.041062 6, 0xFFFF, sum = 0
5268 04:37:48.041160 7, 0xFFFF, sum = 0
5269 04:37:48.043965 8, 0xFFFF, sum = 0
5270 04:37:48.044089 9, 0xFFFF, sum = 0
5271 04:37:48.047312 10, 0x0, sum = 1
5272 04:37:48.047419 11, 0x0, sum = 2
5273 04:37:48.051095 12, 0x0, sum = 3
5274 04:37:48.051199 13, 0x0, sum = 4
5275 04:37:48.054423 best_step = 11
5276 04:37:48.054508
5277 04:37:48.054595 ==
5278 04:37:48.057785 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 04:37:48.061015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 04:37:48.061097 ==
5281 04:37:48.064149 RX Vref Scan: 1
5282 04:37:48.064230
5283 04:37:48.064295 RX Vref 0 -> 0, step: 1
5284 04:37:48.064354
5285 04:37:48.067662 RX Delay -61 -> 252, step: 4
5286 04:37:48.067744
5287 04:37:48.071383 Set Vref, RX VrefLevel [Byte0]: 53
5288 04:37:48.074396 [Byte1]: 52
5289 04:37:48.077898
5290 04:37:48.077979 Final RX Vref Byte 0 = 53 to rank0
5291 04:37:48.081527 Final RX Vref Byte 1 = 52 to rank0
5292 04:37:48.084893 Final RX Vref Byte 0 = 53 to rank1
5293 04:37:48.088432 Final RX Vref Byte 1 = 52 to rank1==
5294 04:37:48.091794 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 04:37:48.098051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 04:37:48.098166 ==
5297 04:37:48.098260 DQS Delay:
5298 04:37:48.098352 DQS0 = 0, DQS1 = 0
5299 04:37:48.101448 DQM Delay:
5300 04:37:48.101549 DQM0 = 96, DQM1 = 88
5301 04:37:48.104432 DQ Delay:
5302 04:37:48.108365 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5303 04:37:48.111366 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5304 04:37:48.111468 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =80
5305 04:37:48.118029 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =98
5306 04:37:48.118131
5307 04:37:48.118224
5308 04:37:48.125002 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5309 04:37:48.128345 CH0 RK0: MR19=504, MR18=11FC
5310 04:37:48.134614 CH0_RK0: MR19=0x504, MR18=0x11FC, DQSOSC=416, MR23=63, INC=62, DEC=41
5311 04:37:48.134736
5312 04:37:48.137957 ----->DramcWriteLeveling(PI) begin...
5313 04:37:48.138072 ==
5314 04:37:48.141251 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 04:37:48.145032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 04:37:48.145135 ==
5317 04:37:48.148177 Write leveling (Byte 0): 30 => 30
5318 04:37:48.151941 Write leveling (Byte 1): 29 => 29
5319 04:37:48.155119 DramcWriteLeveling(PI) end<-----
5320 04:37:48.155227
5321 04:37:48.155323 ==
5322 04:37:48.158226 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 04:37:48.161676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 04:37:48.161778 ==
5325 04:37:48.164735 [Gating] SW mode calibration
5326 04:37:48.171348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5327 04:37:48.177963 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5328 04:37:48.181563 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
5329 04:37:48.185112 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5330 04:37:48.191879 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 04:37:48.194733 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 04:37:48.198258 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 04:37:48.205028 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 04:37:48.208191 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5335 04:37:48.211299 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5336 04:37:48.218450 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 1) (1 0)
5337 04:37:48.222126 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5338 04:37:48.225750 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 04:37:48.228475 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 04:37:48.235156 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 04:37:48.238581 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 04:37:48.241815 0 15 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5343 04:37:48.248505 0 15 28 | B1->B0 | 2929 3c3c | 0 0 | (0 0) (0 0)
5344 04:37:48.251871 1 0 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
5345 04:37:48.254948 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 04:37:48.261991 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 04:37:48.265337 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 04:37:48.268286 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 04:37:48.275032 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 04:37:48.278500 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5351 04:37:48.281742 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5352 04:37:48.288516 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5353 04:37:48.291875 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 04:37:48.294899 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 04:37:48.302014 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 04:37:48.304906 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 04:37:48.308495 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 04:37:48.314983 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 04:37:48.318386 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 04:37:48.321774 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 04:37:48.324786 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 04:37:48.331894 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 04:37:48.335404 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 04:37:48.338321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 04:37:48.344746 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 04:37:48.348248 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 04:37:48.351307 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5368 04:37:48.357980 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5369 04:37:48.361797 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5370 04:37:48.364704 Total UI for P1: 0, mck2ui 16
5371 04:37:48.368346 best dqsien dly found for B0: ( 1, 2, 30)
5372 04:37:48.371263 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 04:37:48.375007 Total UI for P1: 0, mck2ui 16
5374 04:37:48.378302 best dqsien dly found for B1: ( 1, 3, 2)
5375 04:37:48.381701 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5376 04:37:48.384899 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5377 04:37:48.384980
5378 04:37:48.391285 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5379 04:37:48.395038 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5380 04:37:48.395130 [Gating] SW calibration Done
5381 04:37:48.398145 ==
5382 04:37:48.398221 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 04:37:48.404886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 04:37:48.404976 ==
5385 04:37:48.405042 RX Vref Scan: 0
5386 04:37:48.405102
5387 04:37:48.408543 RX Vref 0 -> 0, step: 1
5388 04:37:48.408640
5389 04:37:48.411440 RX Delay -80 -> 252, step: 8
5390 04:37:48.414988 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5391 04:37:48.418513 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5392 04:37:48.421479 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5393 04:37:48.425095 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5394 04:37:48.431710 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5395 04:37:48.434836 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5396 04:37:48.438257 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5397 04:37:48.441523 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5398 04:37:48.444906 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5399 04:37:48.448464 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5400 04:37:48.455173 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5401 04:37:48.458790 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5402 04:37:48.461648 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5403 04:37:48.465495 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5404 04:37:48.468345 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5405 04:37:48.475015 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5406 04:37:48.475115 ==
5407 04:37:48.478462 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 04:37:48.481807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 04:37:48.481884 ==
5410 04:37:48.481975 DQS Delay:
5411 04:37:48.485323 DQS0 = 0, DQS1 = 0
5412 04:37:48.485398 DQM Delay:
5413 04:37:48.488273 DQM0 = 96, DQM1 = 87
5414 04:37:48.488355 DQ Delay:
5415 04:37:48.492210 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5416 04:37:48.495059 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5417 04:37:48.498345 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5418 04:37:48.501774 DQ12 =87, DQ13 =95, DQ14 =99, DQ15 =95
5419 04:37:48.501861
5420 04:37:48.501964
5421 04:37:48.502068 ==
5422 04:37:48.504960 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 04:37:48.508561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 04:37:48.508675 ==
5425 04:37:48.508794
5426 04:37:48.508874
5427 04:37:48.511676 TX Vref Scan disable
5428 04:37:48.515359 == TX Byte 0 ==
5429 04:37:48.518134 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5430 04:37:48.522026 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5431 04:37:48.524991 == TX Byte 1 ==
5432 04:37:48.528414 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5433 04:37:48.532339 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5434 04:37:48.532444 ==
5435 04:37:48.535139 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 04:37:48.538537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 04:37:48.541650 ==
5438 04:37:48.541727
5439 04:37:48.541807
5440 04:37:48.541885 TX Vref Scan disable
5441 04:37:48.545490 == TX Byte 0 ==
5442 04:37:48.548767 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5443 04:37:48.552115 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5444 04:37:48.555833 == TX Byte 1 ==
5445 04:37:48.558892 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5446 04:37:48.562332 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5447 04:37:48.565263
5448 04:37:48.565362 [DATLAT]
5449 04:37:48.565461 Freq=933, CH0 RK1
5450 04:37:48.565540
5451 04:37:48.568659 DATLAT Default: 0xb
5452 04:37:48.568778 0, 0xFFFF, sum = 0
5453 04:37:48.571944 1, 0xFFFF, sum = 0
5454 04:37:48.572054 2, 0xFFFF, sum = 0
5455 04:37:48.575979 3, 0xFFFF, sum = 0
5456 04:37:48.576089 4, 0xFFFF, sum = 0
5457 04:37:48.579049 5, 0xFFFF, sum = 0
5458 04:37:48.579155 6, 0xFFFF, sum = 0
5459 04:37:48.582073 7, 0xFFFF, sum = 0
5460 04:37:48.585537 8, 0xFFFF, sum = 0
5461 04:37:48.585619 9, 0xFFFF, sum = 0
5462 04:37:48.588993 10, 0x0, sum = 1
5463 04:37:48.589108 11, 0x0, sum = 2
5464 04:37:48.589199 12, 0x0, sum = 3
5465 04:37:48.592007 13, 0x0, sum = 4
5466 04:37:48.592106 best_step = 11
5467 04:37:48.592202
5468 04:37:48.592297 ==
5469 04:37:48.595670 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 04:37:48.602279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 04:37:48.602359 ==
5472 04:37:48.602441 RX Vref Scan: 0
5473 04:37:48.602517
5474 04:37:48.605346 RX Vref 0 -> 0, step: 1
5475 04:37:48.605418
5476 04:37:48.608889 RX Delay -69 -> 252, step: 4
5477 04:37:48.611982 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5478 04:37:48.615597 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5479 04:37:48.622188 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5480 04:37:48.625199 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5481 04:37:48.629120 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5482 04:37:48.631950 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5483 04:37:48.635660 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5484 04:37:48.638645 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5485 04:37:48.645439 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5486 04:37:48.649073 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5487 04:37:48.651989 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5488 04:37:48.655552 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5489 04:37:48.659157 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5490 04:37:48.662590 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5491 04:37:48.669091 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5492 04:37:48.672237 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5493 04:37:48.672315 ==
5494 04:37:48.675647 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 04:37:48.679176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 04:37:48.679260 ==
5497 04:37:48.682384 DQS Delay:
5498 04:37:48.682465 DQS0 = 0, DQS1 = 0
5499 04:37:48.682548 DQM Delay:
5500 04:37:48.685647 DQM0 = 95, DQM1 = 88
5501 04:37:48.685728 DQ Delay:
5502 04:37:48.689216 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5503 04:37:48.691992 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5504 04:37:48.695495 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
5505 04:37:48.699119 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5506 04:37:48.699200
5507 04:37:48.699264
5508 04:37:48.708817 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a07, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5509 04:37:48.708916 CH0 RK1: MR19=505, MR18=1A07
5510 04:37:48.715387 CH0_RK1: MR19=0x505, MR18=0x1A07, DQSOSC=413, MR23=63, INC=63, DEC=42
5511 04:37:48.719257 [RxdqsGatingPostProcess] freq 933
5512 04:37:48.725712 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5513 04:37:48.728762 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 04:37:48.732238 best DQS1 dly(2T, 0.5T) = (0, 11)
5515 04:37:48.735656 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 04:37:48.739119 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5517 04:37:48.742165 best DQS0 dly(2T, 0.5T) = (0, 10)
5518 04:37:48.742245 best DQS1 dly(2T, 0.5T) = (0, 11)
5519 04:37:48.745601 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5520 04:37:48.749256 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5521 04:37:48.752108 Pre-setting of DQS Precalculation
5522 04:37:48.759403 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5523 04:37:48.759487 ==
5524 04:37:48.761973 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 04:37:48.765816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 04:37:48.765920 ==
5527 04:37:48.772340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5528 04:37:48.779063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5529 04:37:48.782265 [CA 0] Center 36 (6~67) winsize 62
5530 04:37:48.785610 [CA 1] Center 36 (6~67) winsize 62
5531 04:37:48.789329 [CA 2] Center 34 (4~64) winsize 61
5532 04:37:48.792480 [CA 3] Center 33 (2~64) winsize 63
5533 04:37:48.795528 [CA 4] Center 33 (3~64) winsize 62
5534 04:37:48.795605 [CA 5] Center 33 (2~64) winsize 63
5535 04:37:48.799128
5536 04:37:48.802572 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5537 04:37:48.802650
5538 04:37:48.805851 [CATrainingPosCal] consider 1 rank data
5539 04:37:48.809696 u2DelayCellTimex100 = 270/100 ps
5540 04:37:48.812266 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5541 04:37:48.815989 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5542 04:37:48.818892 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5543 04:37:48.822289 CA3 delay=33 (2~64),Diff = 0 PI (0 cell)
5544 04:37:48.825792 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5545 04:37:48.829155 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5546 04:37:48.829234
5547 04:37:48.832395 CA PerBit enable=1, Macro0, CA PI delay=33
5548 04:37:48.832501
5549 04:37:48.835828 [CBTSetCACLKResult] CA Dly = 33
5550 04:37:48.839359 CS Dly: 4 (0~35)
5551 04:37:48.839440 ==
5552 04:37:48.842102 Dram Type= 6, Freq= 0, CH_1, rank 1
5553 04:37:48.845663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 04:37:48.845744 ==
5555 04:37:48.852172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5556 04:37:48.859027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5557 04:37:48.862219 [CA 0] Center 36 (6~67) winsize 62
5558 04:37:48.865544 [CA 1] Center 37 (7~67) winsize 61
5559 04:37:48.868875 [CA 2] Center 33 (3~64) winsize 62
5560 04:37:48.872171 [CA 3] Center 33 (3~64) winsize 62
5561 04:37:48.875691 [CA 4] Center 34 (4~65) winsize 62
5562 04:37:48.875772 [CA 5] Center 33 (3~63) winsize 61
5563 04:37:48.879322
5564 04:37:48.882296 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5565 04:37:48.882377
5566 04:37:48.885472 [CATrainingPosCal] consider 2 rank data
5567 04:37:48.889315 u2DelayCellTimex100 = 270/100 ps
5568 04:37:48.892313 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5569 04:37:48.896060 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5570 04:37:48.898801 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 04:37:48.902529 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 04:37:48.905974 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 04:37:48.909172 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5574 04:37:48.909253
5575 04:37:48.912195 CA PerBit enable=1, Macro0, CA PI delay=33
5576 04:37:48.912277
5577 04:37:48.915762 [CBTSetCACLKResult] CA Dly = 33
5578 04:37:48.918844 CS Dly: 5 (0~38)
5579 04:37:48.918924
5580 04:37:48.922461 ----->DramcWriteLeveling(PI) begin...
5581 04:37:48.922536 ==
5582 04:37:48.926159 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 04:37:48.929390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 04:37:48.929471 ==
5585 04:37:48.932398 Write leveling (Byte 0): 25 => 25
5586 04:37:48.935502 Write leveling (Byte 1): 31 => 31
5587 04:37:48.939204 DramcWriteLeveling(PI) end<-----
5588 04:37:48.939293
5589 04:37:48.939369 ==
5590 04:37:48.942467 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 04:37:48.945983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 04:37:48.946054 ==
5593 04:37:48.949436 [Gating] SW mode calibration
5594 04:37:48.955676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5595 04:37:48.962807 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5596 04:37:48.965675 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5597 04:37:48.969353 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 04:37:48.975875 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 04:37:48.979433 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 04:37:48.982315 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 04:37:48.989496 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 04:37:48.992568 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5603 04:37:48.995923 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (1 0) (1 0)
5604 04:37:49.002544 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 04:37:49.005710 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 04:37:49.009268 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 04:37:49.016116 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 04:37:49.018851 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5609 04:37:49.022806 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 04:37:49.029243 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 04:37:49.033088 0 15 28 | B1->B0 | 2e2e 2c2c | 0 0 | (0 0) (0 0)
5612 04:37:49.035798 1 0 0 | B1->B0 | 3f3f 3e3e | 0 0 | (1 1) (1 1)
5613 04:37:49.039356 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 04:37:49.046060 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 04:37:49.049325 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 04:37:49.052770 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 04:37:49.059602 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 04:37:49.062493 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 04:37:49.066044 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5620 04:37:49.072397 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 04:37:49.075929 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 04:37:49.079146 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 04:37:49.086098 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 04:37:49.089743 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 04:37:49.093185 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 04:37:49.099677 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 04:37:49.102995 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 04:37:49.106544 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 04:37:49.109631 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 04:37:49.116331 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 04:37:49.119376 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 04:37:49.122694 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 04:37:49.129494 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 04:37:49.133056 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5635 04:37:49.136172 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5636 04:37:49.142994 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 04:37:49.143085 Total UI for P1: 0, mck2ui 16
5638 04:37:49.151096 best dqsien dly found for B0: ( 1, 2, 26)
5639 04:37:49.151179 Total UI for P1: 0, mck2ui 16
5640 04:37:49.156677 best dqsien dly found for B1: ( 1, 2, 26)
5641 04:37:49.159813 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5642 04:37:49.163127 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5643 04:37:49.163206
5644 04:37:49.166436 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5645 04:37:49.169735 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5646 04:37:49.173054 [Gating] SW calibration Done
5647 04:37:49.173135 ==
5648 04:37:49.176243 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 04:37:49.180055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 04:37:49.180136 ==
5651 04:37:49.183191 RX Vref Scan: 0
5652 04:37:49.183271
5653 04:37:49.183333 RX Vref 0 -> 0, step: 1
5654 04:37:49.183392
5655 04:37:49.186451 RX Delay -80 -> 252, step: 8
5656 04:37:49.190000 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5657 04:37:49.193161 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5658 04:37:49.199907 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5659 04:37:49.203320 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5660 04:37:49.206340 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5661 04:37:49.209662 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5662 04:37:49.213208 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5663 04:37:49.216617 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5664 04:37:49.223311 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5665 04:37:49.226759 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5666 04:37:49.229706 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5667 04:37:49.233587 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5668 04:37:49.236706 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5669 04:37:49.239807 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5670 04:37:49.246514 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5671 04:37:49.250162 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5672 04:37:49.250245 ==
5673 04:37:49.253690 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 04:37:49.256527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 04:37:49.256609 ==
5676 04:37:49.256699 DQS Delay:
5677 04:37:49.260625 DQS0 = 0, DQS1 = 0
5678 04:37:49.260745 DQM Delay:
5679 04:37:49.263522 DQM0 = 95, DQM1 = 89
5680 04:37:49.263602 DQ Delay:
5681 04:37:49.267039 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5682 04:37:49.270301 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5683 04:37:49.273382 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5684 04:37:49.276875 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5685 04:37:49.276955
5686 04:37:49.277018
5687 04:37:49.277078 ==
5688 04:37:49.280439 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 04:37:49.283870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 04:37:49.287273 ==
5691 04:37:49.287371
5692 04:37:49.287435
5693 04:37:49.287494 TX Vref Scan disable
5694 04:37:49.290234 == TX Byte 0 ==
5695 04:37:49.293606 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5696 04:37:49.296868 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5697 04:37:49.300423 == TX Byte 1 ==
5698 04:37:49.303846 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5699 04:37:49.307253 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5700 04:37:49.307351 ==
5701 04:37:49.310175 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 04:37:49.317221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 04:37:49.317333 ==
5704 04:37:49.317398
5705 04:37:49.317457
5706 04:37:49.319966 TX Vref Scan disable
5707 04:37:49.320045 == TX Byte 0 ==
5708 04:37:49.327027 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5709 04:37:49.330254 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5710 04:37:49.330339 == TX Byte 1 ==
5711 04:37:49.336688 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5712 04:37:49.340087 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5713 04:37:49.340171
5714 04:37:49.340235 [DATLAT]
5715 04:37:49.343510 Freq=933, CH1 RK0
5716 04:37:49.343618
5717 04:37:49.343710 DATLAT Default: 0xd
5718 04:37:49.346912 0, 0xFFFF, sum = 0
5719 04:37:49.346994 1, 0xFFFF, sum = 0
5720 04:37:49.349938 2, 0xFFFF, sum = 0
5721 04:37:49.350020 3, 0xFFFF, sum = 0
5722 04:37:49.353835 4, 0xFFFF, sum = 0
5723 04:37:49.353917 5, 0xFFFF, sum = 0
5724 04:37:49.357410 6, 0xFFFF, sum = 0
5725 04:37:49.357492 7, 0xFFFF, sum = 0
5726 04:37:49.359983 8, 0xFFFF, sum = 0
5727 04:37:49.360065 9, 0xFFFF, sum = 0
5728 04:37:49.363520 10, 0x0, sum = 1
5729 04:37:49.363602 11, 0x0, sum = 2
5730 04:37:49.367089 12, 0x0, sum = 3
5731 04:37:49.367170 13, 0x0, sum = 4
5732 04:37:49.370530 best_step = 11
5733 04:37:49.370610
5734 04:37:49.370673 ==
5735 04:37:49.373219 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 04:37:49.376830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 04:37:49.376911 ==
5738 04:37:49.380221 RX Vref Scan: 1
5739 04:37:49.380302
5740 04:37:49.380366 RX Vref 0 -> 0, step: 1
5741 04:37:49.380425
5742 04:37:49.383640 RX Delay -61 -> 252, step: 4
5743 04:37:49.383721
5744 04:37:49.387042 Set Vref, RX VrefLevel [Byte0]: 56
5745 04:37:49.390320 [Byte1]: 55
5746 04:37:49.393890
5747 04:37:49.393969 Final RX Vref Byte 0 = 56 to rank0
5748 04:37:49.397422 Final RX Vref Byte 1 = 55 to rank0
5749 04:37:49.400651 Final RX Vref Byte 0 = 56 to rank1
5750 04:37:49.403903 Final RX Vref Byte 1 = 55 to rank1==
5751 04:37:49.407138 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 04:37:49.414102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 04:37:49.414183 ==
5754 04:37:49.414247 DQS Delay:
5755 04:37:49.414307 DQS0 = 0, DQS1 = 0
5756 04:37:49.417178 DQM Delay:
5757 04:37:49.417257 DQM0 = 98, DQM1 = 91
5758 04:37:49.420644 DQ Delay:
5759 04:37:49.424116 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =98
5760 04:37:49.427180 DQ4 =98, DQ5 =108, DQ6 =106, DQ7 =94
5761 04:37:49.430618 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
5762 04:37:49.434061 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =94
5763 04:37:49.434143
5764 04:37:49.434207
5765 04:37:49.440580 [DQSOSCAuto] RK0, (LSB)MR18= 0x11ed, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5766 04:37:49.443899 CH1 RK0: MR19=504, MR18=11ED
5767 04:37:49.450348 CH1_RK0: MR19=0x504, MR18=0x11ED, DQSOSC=416, MR23=63, INC=62, DEC=41
5768 04:37:49.450511
5769 04:37:49.453821 ----->DramcWriteLeveling(PI) begin...
5770 04:37:49.453950 ==
5771 04:37:49.457343 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 04:37:49.461130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 04:37:49.461224 ==
5774 04:37:49.463897 Write leveling (Byte 0): 27 => 27
5775 04:37:49.467192 Write leveling (Byte 1): 27 => 27
5776 04:37:49.470515 DramcWriteLeveling(PI) end<-----
5777 04:37:49.470617
5778 04:37:49.470708 ==
5779 04:37:49.474410 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 04:37:49.477162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 04:37:49.477246 ==
5782 04:37:49.480932 [Gating] SW mode calibration
5783 04:37:49.487395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5784 04:37:49.494342 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5785 04:37:49.497712 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 04:37:49.500754 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 04:37:49.507643 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 04:37:49.510496 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 04:37:49.514367 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 04:37:49.520720 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 0) (1 0)
5791 04:37:49.523793 0 14 24 | B1->B0 | 3232 2b2b | 1 1 | (1 1) (1 0)
5792 04:37:49.527287 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5793 04:37:49.533732 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 04:37:49.537284 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 04:37:49.540704 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 04:37:49.547504 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5797 04:37:49.550455 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 04:37:49.553829 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 04:37:49.560601 0 15 24 | B1->B0 | 2929 3838 | 0 0 | (0 0) (1 1)
5800 04:37:49.564116 0 15 28 | B1->B0 | 3737 4242 | 0 0 | (0 0) (0 0)
5801 04:37:49.567603 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 04:37:49.574405 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 04:37:49.577466 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 04:37:49.580536 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 04:37:49.584237 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 04:37:49.590687 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5807 04:37:49.594382 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5808 04:37:49.597293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5809 04:37:49.604221 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 04:37:49.607262 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 04:37:49.611126 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 04:37:49.617854 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 04:37:49.620872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 04:37:49.624121 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 04:37:49.631349 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 04:37:49.634113 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 04:37:49.637535 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 04:37:49.643907 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 04:37:49.647778 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 04:37:49.650848 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 04:37:49.657824 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 04:37:49.660554 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5823 04:37:49.664200 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5824 04:37:49.670699 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 04:37:49.670781 Total UI for P1: 0, mck2ui 16
5826 04:37:49.673904 best dqsien dly found for B0: ( 1, 2, 22)
5827 04:37:49.677356 Total UI for P1: 0, mck2ui 16
5828 04:37:49.680658 best dqsien dly found for B1: ( 1, 2, 24)
5829 04:37:49.684383 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5830 04:37:49.691011 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5831 04:37:49.691102
5832 04:37:49.693856 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5833 04:37:49.697464 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5834 04:37:49.700499 [Gating] SW calibration Done
5835 04:37:49.700580 ==
5836 04:37:49.703933 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 04:37:49.707700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 04:37:49.707807 ==
5839 04:37:49.707901 RX Vref Scan: 0
5840 04:37:49.710542
5841 04:37:49.710623 RX Vref 0 -> 0, step: 1
5842 04:37:49.710689
5843 04:37:49.713870 RX Delay -80 -> 252, step: 8
5844 04:37:49.717297 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5845 04:37:49.720885 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5846 04:37:49.727850 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5847 04:37:49.730565 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5848 04:37:49.734402 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5849 04:37:49.737780 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5850 04:37:49.740544 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5851 04:37:49.743985 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5852 04:37:49.747356 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5853 04:37:49.754106 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5854 04:37:49.757767 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5855 04:37:49.761095 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5856 04:37:49.764404 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5857 04:37:49.768137 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5858 04:37:49.773905 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5859 04:37:49.777410 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5860 04:37:49.777491 ==
5861 04:37:49.780504 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 04:37:49.784512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 04:37:49.784594 ==
5864 04:37:49.784659 DQS Delay:
5865 04:37:49.787349 DQS0 = 0, DQS1 = 0
5866 04:37:49.787430 DQM Delay:
5867 04:37:49.790546 DQM0 = 94, DQM1 = 89
5868 04:37:49.790627 DQ Delay:
5869 04:37:49.794115 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5870 04:37:49.797502 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5871 04:37:49.800812 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5872 04:37:49.803993 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5873 04:37:49.804073
5874 04:37:49.804138
5875 04:37:49.804197 ==
5876 04:37:49.807519 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 04:37:49.811085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 04:37:49.814081 ==
5879 04:37:49.814191
5880 04:37:49.814284
5881 04:37:49.814376 TX Vref Scan disable
5882 04:37:49.817386 == TX Byte 0 ==
5883 04:37:49.821069 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5884 04:37:49.824813 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5885 04:37:49.827225 == TX Byte 1 ==
5886 04:37:49.831095 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5887 04:37:49.834149 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5888 04:37:49.834257 ==
5889 04:37:49.837492 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 04:37:49.844306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 04:37:49.844413 ==
5892 04:37:49.844504
5893 04:37:49.844595
5894 04:37:49.844702 TX Vref Scan disable
5895 04:37:49.848339 == TX Byte 0 ==
5896 04:37:49.851883 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5897 04:37:49.855042 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5898 04:37:49.858543 == TX Byte 1 ==
5899 04:37:49.861933 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5900 04:37:49.865538 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5901 04:37:49.865646
5902 04:37:49.868489 [DATLAT]
5903 04:37:49.868605 Freq=933, CH1 RK1
5904 04:37:49.868716
5905 04:37:49.871791 DATLAT Default: 0xb
5906 04:37:49.871879 0, 0xFFFF, sum = 0
5907 04:37:49.875429 1, 0xFFFF, sum = 0
5908 04:37:49.875536 2, 0xFFFF, sum = 0
5909 04:37:49.878412 3, 0xFFFF, sum = 0
5910 04:37:49.878513 4, 0xFFFF, sum = 0
5911 04:37:49.882472 5, 0xFFFF, sum = 0
5912 04:37:49.882576 6, 0xFFFF, sum = 0
5913 04:37:49.885041 7, 0xFFFF, sum = 0
5914 04:37:49.885116 8, 0xFFFF, sum = 0
5915 04:37:49.888316 9, 0xFFFF, sum = 0
5916 04:37:49.888419 10, 0x0, sum = 1
5917 04:37:49.891645 11, 0x0, sum = 2
5918 04:37:49.891757 12, 0x0, sum = 3
5919 04:37:49.895039 13, 0x0, sum = 4
5920 04:37:49.895139 best_step = 11
5921 04:37:49.895231
5922 04:37:49.895316 ==
5923 04:37:49.898518 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 04:37:49.905337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 04:37:49.905418 ==
5926 04:37:49.905493 RX Vref Scan: 0
5927 04:37:49.905583
5928 04:37:49.908895 RX Vref 0 -> 0, step: 1
5929 04:37:49.909002
5930 04:37:49.911940 RX Delay -61 -> 252, step: 4
5931 04:37:49.915345 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5932 04:37:49.918254 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5933 04:37:49.925123 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5934 04:37:49.928566 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5935 04:37:49.932506 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5936 04:37:49.935100 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5937 04:37:49.938866 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5938 04:37:49.942043 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5939 04:37:49.948206 iDelay=199, Bit 8, Center 84 (-5 ~ 174) 180
5940 04:37:49.952077 iDelay=199, Bit 9, Center 82 (-5 ~ 170) 176
5941 04:37:49.955467 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5942 04:37:49.958622 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5943 04:37:49.961709 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5944 04:37:49.965181 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5945 04:37:49.971825 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5946 04:37:49.974888 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5947 04:37:49.974992 ==
5948 04:37:49.978404 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 04:37:49.981624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 04:37:49.981725 ==
5951 04:37:49.985079 DQS Delay:
5952 04:37:49.985157 DQS0 = 0, DQS1 = 0
5953 04:37:49.985237 DQM Delay:
5954 04:37:49.988410 DQM0 = 95, DQM1 = 92
5955 04:37:49.988511 DQ Delay:
5956 04:37:49.991807 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5957 04:37:49.994949 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5958 04:37:49.998531 DQ8 =84, DQ9 =82, DQ10 =90, DQ11 =86
5959 04:37:50.002217 DQ12 =96, DQ13 =98, DQ14 =102, DQ15 =98
5960 04:37:50.002330
5961 04:37:50.002428
5962 04:37:50.012022 [DQSOSCAuto] RK1, (LSB)MR18= 0xf19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 417 ps
5963 04:37:50.012127 CH1 RK1: MR19=505, MR18=F19
5964 04:37:50.018577 CH1_RK1: MR19=0x505, MR18=0xF19, DQSOSC=413, MR23=63, INC=63, DEC=42
5965 04:37:50.022195 [RxdqsGatingPostProcess] freq 933
5966 04:37:50.029051 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5967 04:37:50.032532 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 04:37:50.035610 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 04:37:50.038684 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 04:37:50.041937 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 04:37:50.042018 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 04:37:50.045932 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 04:37:50.048584 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 04:37:50.052185 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 04:37:50.055813 Pre-setting of DQS Precalculation
5976 04:37:50.062235 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5977 04:37:50.069041 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5978 04:37:50.075783 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5979 04:37:50.075888
5980 04:37:50.075980
5981 04:37:50.079075 [Calibration Summary] 1866 Mbps
5982 04:37:50.079148 CH 0, Rank 0
5983 04:37:50.082262 SW Impedance : PASS
5984 04:37:50.085674 DUTY Scan : NO K
5985 04:37:50.085749 ZQ Calibration : PASS
5986 04:37:50.088857 Jitter Meter : NO K
5987 04:37:50.092268 CBT Training : PASS
5988 04:37:50.092348 Write leveling : PASS
5989 04:37:50.095548 RX DQS gating : PASS
5990 04:37:50.095629 RX DQ/DQS(RDDQC) : PASS
5991 04:37:50.099219 TX DQ/DQS : PASS
5992 04:37:50.102597 RX DATLAT : PASS
5993 04:37:50.102677 RX DQ/DQS(Engine): PASS
5994 04:37:50.105535 TX OE : NO K
5995 04:37:50.105617 All Pass.
5996 04:37:50.105681
5997 04:37:50.109132 CH 0, Rank 1
5998 04:37:50.109203 SW Impedance : PASS
5999 04:37:50.112371 DUTY Scan : NO K
6000 04:37:50.115748 ZQ Calibration : PASS
6001 04:37:50.115819 Jitter Meter : NO K
6002 04:37:50.119362 CBT Training : PASS
6003 04:37:50.122586 Write leveling : PASS
6004 04:37:50.122694 RX DQS gating : PASS
6005 04:37:50.126144 RX DQ/DQS(RDDQC) : PASS
6006 04:37:50.126232 TX DQ/DQS : PASS
6007 04:37:50.129368 RX DATLAT : PASS
6008 04:37:50.132520 RX DQ/DQS(Engine): PASS
6009 04:37:50.132602 TX OE : NO K
6010 04:37:50.135861 All Pass.
6011 04:37:50.135932
6012 04:37:50.135994 CH 1, Rank 0
6013 04:37:50.138918 SW Impedance : PASS
6014 04:37:50.138992 DUTY Scan : NO K
6015 04:37:50.142360 ZQ Calibration : PASS
6016 04:37:50.146217 Jitter Meter : NO K
6017 04:37:50.146291 CBT Training : PASS
6018 04:37:50.148969 Write leveling : PASS
6019 04:37:50.152445 RX DQS gating : PASS
6020 04:37:50.152526 RX DQ/DQS(RDDQC) : PASS
6021 04:37:50.155743 TX DQ/DQS : PASS
6022 04:37:50.158918 RX DATLAT : PASS
6023 04:37:50.158999 RX DQ/DQS(Engine): PASS
6024 04:37:50.162731 TX OE : NO K
6025 04:37:50.162817 All Pass.
6026 04:37:50.162883
6027 04:37:50.165887 CH 1, Rank 1
6028 04:37:50.165968 SW Impedance : PASS
6029 04:37:50.169052 DUTY Scan : NO K
6030 04:37:50.172137 ZQ Calibration : PASS
6031 04:37:50.172218 Jitter Meter : NO K
6032 04:37:50.175699 CBT Training : PASS
6033 04:37:50.175780 Write leveling : PASS
6034 04:37:50.178875 RX DQS gating : PASS
6035 04:37:50.182205 RX DQ/DQS(RDDQC) : PASS
6036 04:37:50.182286 TX DQ/DQS : PASS
6037 04:37:50.185885 RX DATLAT : PASS
6038 04:37:50.189297 RX DQ/DQS(Engine): PASS
6039 04:37:50.189378 TX OE : NO K
6040 04:37:50.192403 All Pass.
6041 04:37:50.192487
6042 04:37:50.192552 DramC Write-DBI off
6043 04:37:50.195682 PER_BANK_REFRESH: Hybrid Mode
6044 04:37:50.199385 TX_TRACKING: ON
6045 04:37:50.206073 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6046 04:37:50.209161 [FAST_K] Save calibration result to emmc
6047 04:37:50.212559 dramc_set_vcore_voltage set vcore to 650000
6048 04:37:50.215904 Read voltage for 400, 6
6049 04:37:50.215989 Vio18 = 0
6050 04:37:50.219513 Vcore = 650000
6051 04:37:50.219593 Vdram = 0
6052 04:37:50.219658 Vddq = 0
6053 04:37:50.222516 Vmddr = 0
6054 04:37:50.225979 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6055 04:37:50.232693 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6056 04:37:50.232789 MEM_TYPE=3, freq_sel=20
6057 04:37:50.235728 sv_algorithm_assistance_LP4_800
6058 04:37:50.239355 ============ PULL DRAM RESETB DOWN ============
6059 04:37:50.246065 ========== PULL DRAM RESETB DOWN end =========
6060 04:37:50.249129 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6061 04:37:50.252408 ===================================
6062 04:37:50.255864 LPDDR4 DRAM CONFIGURATION
6063 04:37:50.259156 ===================================
6064 04:37:50.259230 EX_ROW_EN[0] = 0x0
6065 04:37:50.262260 EX_ROW_EN[1] = 0x0
6066 04:37:50.262357 LP4Y_EN = 0x0
6067 04:37:50.265751 WORK_FSP = 0x0
6068 04:37:50.265822 WL = 0x2
6069 04:37:50.269427 RL = 0x2
6070 04:37:50.272856 BL = 0x2
6071 04:37:50.272926 RPST = 0x0
6072 04:37:50.276019 RD_PRE = 0x0
6073 04:37:50.276099 WR_PRE = 0x1
6074 04:37:50.279453 WR_PST = 0x0
6075 04:37:50.279534 DBI_WR = 0x0
6076 04:37:50.282939 DBI_RD = 0x0
6077 04:37:50.283019 OTF = 0x1
6078 04:37:50.285795 ===================================
6079 04:37:50.289338 ===================================
6080 04:37:50.292677 ANA top config
6081 04:37:50.295628 ===================================
6082 04:37:50.295708 DLL_ASYNC_EN = 0
6083 04:37:50.299572 ALL_SLAVE_EN = 1
6084 04:37:50.302836 NEW_RANK_MODE = 1
6085 04:37:50.305915 DLL_IDLE_MODE = 1
6086 04:37:50.305995 LP45_APHY_COMB_EN = 1
6087 04:37:50.309202 TX_ODT_DIS = 1
6088 04:37:50.312230 NEW_8X_MODE = 1
6089 04:37:50.316054 ===================================
6090 04:37:50.319479 ===================================
6091 04:37:50.322422 data_rate = 800
6092 04:37:50.325601 CKR = 1
6093 04:37:50.325682 DQ_P2S_RATIO = 4
6094 04:37:50.329501 ===================================
6095 04:37:50.332323 CA_P2S_RATIO = 4
6096 04:37:50.335659 DQ_CA_OPEN = 0
6097 04:37:50.339298 DQ_SEMI_OPEN = 1
6098 04:37:50.342962 CA_SEMI_OPEN = 1
6099 04:37:50.345830 CA_FULL_RATE = 0
6100 04:37:50.345910 DQ_CKDIV4_EN = 0
6101 04:37:50.349383 CA_CKDIV4_EN = 1
6102 04:37:50.352551 CA_PREDIV_EN = 0
6103 04:37:50.355873 PH8_DLY = 0
6104 04:37:50.359530 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6105 04:37:50.362359 DQ_AAMCK_DIV = 0
6106 04:37:50.362439 CA_AAMCK_DIV = 0
6107 04:37:50.365905 CA_ADMCK_DIV = 4
6108 04:37:50.369464 DQ_TRACK_CA_EN = 0
6109 04:37:50.372208 CA_PICK = 800
6110 04:37:50.375834 CA_MCKIO = 400
6111 04:37:50.378933 MCKIO_SEMI = 400
6112 04:37:50.382378 PLL_FREQ = 3016
6113 04:37:50.382462 DQ_UI_PI_RATIO = 32
6114 04:37:50.385887 CA_UI_PI_RATIO = 32
6115 04:37:50.388907 ===================================
6116 04:37:50.392637 ===================================
6117 04:37:50.395891 memory_type:LPDDR4
6118 04:37:50.399581 GP_NUM : 10
6119 04:37:50.399664 SRAM_EN : 1
6120 04:37:50.402562 MD32_EN : 0
6121 04:37:50.405862 ===================================
6122 04:37:50.409448 [ANA_INIT] >>>>>>>>>>>>>>
6123 04:37:50.409529 <<<<<< [CONFIGURE PHASE]: ANA_TX
6124 04:37:50.412796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6125 04:37:50.416030 ===================================
6126 04:37:50.419025 data_rate = 800,PCW = 0X7400
6127 04:37:50.422582 ===================================
6128 04:37:50.425710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6129 04:37:50.432937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6130 04:37:50.442765 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 04:37:50.449789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6132 04:37:50.452825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6133 04:37:50.456419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6134 04:37:50.456500 [ANA_INIT] flow start
6135 04:37:50.459815 [ANA_INIT] PLL >>>>>>>>
6136 04:37:50.462669 [ANA_INIT] PLL <<<<<<<<
6137 04:37:50.462749 [ANA_INIT] MIDPI >>>>>>>>
6138 04:37:50.466346 [ANA_INIT] MIDPI <<<<<<<<
6139 04:37:50.469421 [ANA_INIT] DLL >>>>>>>>
6140 04:37:50.469501 [ANA_INIT] flow end
6141 04:37:50.476194 ============ LP4 DIFF to SE enter ============
6142 04:37:50.479621 ============ LP4 DIFF to SE exit ============
6143 04:37:50.479703 [ANA_INIT] <<<<<<<<<<<<<
6144 04:37:50.483137 [Flow] Enable top DCM control >>>>>
6145 04:37:50.486465 [Flow] Enable top DCM control <<<<<
6146 04:37:50.489120 Enable DLL master slave shuffle
6147 04:37:50.496001 ==============================================================
6148 04:37:50.499587 Gating Mode config
6149 04:37:50.503325 ==============================================================
6150 04:37:50.506204 Config description:
6151 04:37:50.516209 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6152 04:37:50.523222 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6153 04:37:50.526289 SELPH_MODE 0: By rank 1: By Phase
6154 04:37:50.532854 ==============================================================
6155 04:37:50.536224 GAT_TRACK_EN = 0
6156 04:37:50.536325 RX_GATING_MODE = 2
6157 04:37:50.539542 RX_GATING_TRACK_MODE = 2
6158 04:37:50.543072 SELPH_MODE = 1
6159 04:37:50.546642 PICG_EARLY_EN = 1
6160 04:37:50.549780 VALID_LAT_VALUE = 1
6161 04:37:50.556225 ==============================================================
6162 04:37:50.559806 Enter into Gating configuration >>>>
6163 04:37:50.563161 Exit from Gating configuration <<<<
6164 04:37:50.566757 Enter into DVFS_PRE_config >>>>>
6165 04:37:50.576313 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6166 04:37:50.579882 Exit from DVFS_PRE_config <<<<<
6167 04:37:50.583054 Enter into PICG configuration >>>>
6168 04:37:50.586677 Exit from PICG configuration <<<<
6169 04:37:50.589719 [RX_INPUT] configuration >>>>>
6170 04:37:50.593195 [RX_INPUT] configuration <<<<<
6171 04:37:50.596039 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6172 04:37:50.602672 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6173 04:37:50.609375 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 04:37:50.612869 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 04:37:50.619234 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 04:37:50.626039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 04:37:50.629445 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6178 04:37:50.632891 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6179 04:37:50.639519 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6180 04:37:50.642569 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6181 04:37:50.645965 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6182 04:37:50.652506 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 04:37:50.656165 ===================================
6184 04:37:50.656241 LPDDR4 DRAM CONFIGURATION
6185 04:37:50.659000 ===================================
6186 04:37:50.662649 EX_ROW_EN[0] = 0x0
6187 04:37:50.665892 EX_ROW_EN[1] = 0x0
6188 04:37:50.665978 LP4Y_EN = 0x0
6189 04:37:50.669572 WORK_FSP = 0x0
6190 04:37:50.669646 WL = 0x2
6191 04:37:50.672624 RL = 0x2
6192 04:37:50.672751 BL = 0x2
6193 04:37:50.676001 RPST = 0x0
6194 04:37:50.676077 RD_PRE = 0x0
6195 04:37:50.679459 WR_PRE = 0x1
6196 04:37:50.679531 WR_PST = 0x0
6197 04:37:50.683197 DBI_WR = 0x0
6198 04:37:50.683304 DBI_RD = 0x0
6199 04:37:50.685895 OTF = 0x1
6200 04:37:50.689233 ===================================
6201 04:37:50.692996 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6202 04:37:50.696436 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6203 04:37:50.699616 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6204 04:37:50.702976 ===================================
6205 04:37:50.706240 LPDDR4 DRAM CONFIGURATION
6206 04:37:50.709833 ===================================
6207 04:37:50.712566 EX_ROW_EN[0] = 0x10
6208 04:37:50.712662 EX_ROW_EN[1] = 0x0
6209 04:37:50.716072 LP4Y_EN = 0x0
6210 04:37:50.716153 WORK_FSP = 0x0
6211 04:37:50.719427 WL = 0x2
6212 04:37:50.719518 RL = 0x2
6213 04:37:50.722920 BL = 0x2
6214 04:37:50.723015 RPST = 0x0
6215 04:37:50.725912 RD_PRE = 0x0
6216 04:37:50.725993 WR_PRE = 0x1
6217 04:37:50.729708 WR_PST = 0x0
6218 04:37:50.729796 DBI_WR = 0x0
6219 04:37:50.732559 DBI_RD = 0x0
6220 04:37:50.736267 OTF = 0x1
6221 04:37:50.739553 ===================================
6222 04:37:50.742469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6223 04:37:50.748247 nWR fixed to 30
6224 04:37:50.751063 [ModeRegInit_LP4] CH0 RK0
6225 04:37:50.751144 [ModeRegInit_LP4] CH0 RK1
6226 04:37:50.754464 [ModeRegInit_LP4] CH1 RK0
6227 04:37:50.757740 [ModeRegInit_LP4] CH1 RK1
6228 04:37:50.757820 match AC timing 19
6229 04:37:50.764703 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6230 04:37:50.768127 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6231 04:37:50.771376 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6232 04:37:50.778110 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6233 04:37:50.781306 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6234 04:37:50.781412 ==
6235 04:37:50.784590 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 04:37:50.788188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 04:37:50.788290 ==
6238 04:37:50.794883 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 04:37:50.801199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6240 04:37:50.804908 [CA 0] Center 36 (8~64) winsize 57
6241 04:37:50.804985 [CA 1] Center 36 (8~64) winsize 57
6242 04:37:50.808021 [CA 2] Center 36 (8~64) winsize 57
6243 04:37:50.811439 [CA 3] Center 36 (8~64) winsize 57
6244 04:37:50.815082 [CA 4] Center 36 (8~64) winsize 57
6245 04:37:50.817837 [CA 5] Center 36 (8~64) winsize 57
6246 04:37:50.817909
6247 04:37:50.821269 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6248 04:37:50.821351
6249 04:37:50.824854 [CATrainingPosCal] consider 1 rank data
6250 04:37:50.828349 u2DelayCellTimex100 = 270/100 ps
6251 04:37:50.831649 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 04:37:50.838142 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 04:37:50.841713 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 04:37:50.844510 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 04:37:50.847866 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 04:37:50.851367 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 04:37:50.851448
6258 04:37:50.855676 CA PerBit enable=1, Macro0, CA PI delay=36
6259 04:37:50.855757
6260 04:37:50.858085 [CBTSetCACLKResult] CA Dly = 36
6261 04:37:50.858188 CS Dly: 1 (0~32)
6262 04:37:50.861540 ==
6263 04:37:50.861620 Dram Type= 6, Freq= 0, CH_0, rank 1
6264 04:37:50.868692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 04:37:50.868788 ==
6266 04:37:50.871617 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 04:37:50.878546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6268 04:37:50.881703 [CA 0] Center 36 (8~64) winsize 57
6269 04:37:50.884997 [CA 1] Center 36 (8~64) winsize 57
6270 04:37:50.888319 [CA 2] Center 36 (8~64) winsize 57
6271 04:37:50.891496 [CA 3] Center 36 (8~64) winsize 57
6272 04:37:50.894856 [CA 4] Center 36 (8~64) winsize 57
6273 04:37:50.898148 [CA 5] Center 36 (8~64) winsize 57
6274 04:37:50.898229
6275 04:37:50.902139 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6276 04:37:50.902221
6277 04:37:50.905144 [CATrainingPosCal] consider 2 rank data
6278 04:37:50.908421 u2DelayCellTimex100 = 270/100 ps
6279 04:37:50.911800 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 04:37:50.915055 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 04:37:50.918258 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 04:37:50.921363 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 04:37:50.925301 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 04:37:50.928298 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 04:37:50.928401
6286 04:37:50.935096 CA PerBit enable=1, Macro0, CA PI delay=36
6287 04:37:50.935199
6288 04:37:50.935339 [CBTSetCACLKResult] CA Dly = 36
6289 04:37:50.938432 CS Dly: 1 (0~32)
6290 04:37:50.938507
6291 04:37:50.941766 ----->DramcWriteLeveling(PI) begin...
6292 04:37:50.941855 ==
6293 04:37:50.945322 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 04:37:50.948160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 04:37:50.948242 ==
6296 04:37:50.951944 Write leveling (Byte 0): 40 => 8
6297 04:37:50.955217 Write leveling (Byte 1): 32 => 0
6298 04:37:50.958319 DramcWriteLeveling(PI) end<-----
6299 04:37:50.958393
6300 04:37:50.958481 ==
6301 04:37:50.961691 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 04:37:50.965335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 04:37:50.968630 ==
6304 04:37:50.968749 [Gating] SW mode calibration
6305 04:37:50.975026 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6306 04:37:50.981798 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6307 04:37:50.985513 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6308 04:37:50.991877 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 04:37:50.995626 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 04:37:50.998371 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 04:37:51.001910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 04:37:51.009007 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 04:37:51.012141 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 04:37:51.015153 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 04:37:51.022244 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 04:37:51.025396 Total UI for P1: 0, mck2ui 16
6317 04:37:51.029036 best dqsien dly found for B0: ( 0, 14, 24)
6318 04:37:51.029112 Total UI for P1: 0, mck2ui 16
6319 04:37:51.035657 best dqsien dly found for B1: ( 0, 14, 24)
6320 04:37:51.038897 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6321 04:37:51.042130 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6322 04:37:51.042208
6323 04:37:51.045616 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6324 04:37:51.048975 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 04:37:51.051958 [Gating] SW calibration Done
6326 04:37:51.052056 ==
6327 04:37:51.055481 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 04:37:51.058829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 04:37:51.058942 ==
6330 04:37:51.062094 RX Vref Scan: 0
6331 04:37:51.062196
6332 04:37:51.062286 RX Vref 0 -> 0, step: 1
6333 04:37:51.062379
6334 04:37:51.065560 RX Delay -410 -> 252, step: 16
6335 04:37:51.072467 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6336 04:37:51.075999 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6337 04:37:51.078864 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6338 04:37:51.082220 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6339 04:37:51.089085 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6340 04:37:51.092536 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6341 04:37:51.095427 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6342 04:37:51.098858 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6343 04:37:51.102235 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6344 04:37:51.108906 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6345 04:37:51.112577 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6346 04:37:51.115908 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6347 04:37:51.122280 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6348 04:37:51.125852 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6349 04:37:51.129049 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6350 04:37:51.132229 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6351 04:37:51.132331 ==
6352 04:37:51.136045 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 04:37:51.142302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 04:37:51.142380 ==
6355 04:37:51.142442 DQS Delay:
6356 04:37:51.145758 DQS0 = 35, DQS1 = 51
6357 04:37:51.145826 DQM Delay:
6358 04:37:51.145885 DQM0 = 8, DQM1 = 10
6359 04:37:51.148858 DQ Delay:
6360 04:37:51.152222 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6361 04:37:51.152320 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6362 04:37:51.155584 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6363 04:37:51.159458 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6364 04:37:51.159528
6365 04:37:51.162510
6366 04:37:51.162615 ==
6367 04:37:51.166013 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 04:37:51.168876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 04:37:51.168975 ==
6370 04:37:51.169067
6371 04:37:51.169157
6372 04:37:51.172064 TX Vref Scan disable
6373 04:37:51.172159 == TX Byte 0 ==
6374 04:37:51.175564 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 04:37:51.182294 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 04:37:51.182409 == TX Byte 1 ==
6377 04:37:51.185549 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6378 04:37:51.191925 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6379 04:37:51.192007 ==
6380 04:37:51.195499 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 04:37:51.198928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 04:37:51.199030 ==
6383 04:37:51.199120
6384 04:37:51.199207
6385 04:37:51.202212 TX Vref Scan disable
6386 04:37:51.202310 == TX Byte 0 ==
6387 04:37:51.208873 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 04:37:51.211883 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 04:37:51.211984 == TX Byte 1 ==
6390 04:37:51.218372 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6391 04:37:51.221892 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6392 04:37:51.221973
6393 04:37:51.222063 [DATLAT]
6394 04:37:51.225290 Freq=400, CH0 RK0
6395 04:37:51.225371
6396 04:37:51.225435 DATLAT Default: 0xf
6397 04:37:51.228853 0, 0xFFFF, sum = 0
6398 04:37:51.228935 1, 0xFFFF, sum = 0
6399 04:37:51.232046 2, 0xFFFF, sum = 0
6400 04:37:51.232135 3, 0xFFFF, sum = 0
6401 04:37:51.235388 4, 0xFFFF, sum = 0
6402 04:37:51.235471 5, 0xFFFF, sum = 0
6403 04:37:51.238603 6, 0xFFFF, sum = 0
6404 04:37:51.238685 7, 0xFFFF, sum = 0
6405 04:37:51.241878 8, 0xFFFF, sum = 0
6406 04:37:51.241961 9, 0xFFFF, sum = 0
6407 04:37:51.244979 10, 0xFFFF, sum = 0
6408 04:37:51.245055 11, 0xFFFF, sum = 0
6409 04:37:51.248362 12, 0xFFFF, sum = 0
6410 04:37:51.248436 13, 0x0, sum = 1
6411 04:37:51.251899 14, 0x0, sum = 2
6412 04:37:51.251990 15, 0x0, sum = 3
6413 04:37:51.255343 16, 0x0, sum = 4
6414 04:37:51.255416 best_step = 14
6415 04:37:51.255476
6416 04:37:51.255533 ==
6417 04:37:51.258353 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 04:37:51.265125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 04:37:51.265200 ==
6420 04:37:51.265263 RX Vref Scan: 1
6421 04:37:51.265322
6422 04:37:51.268775 RX Vref 0 -> 0, step: 1
6423 04:37:51.268855
6424 04:37:51.271556 RX Delay -343 -> 252, step: 8
6425 04:37:51.271636
6426 04:37:51.275215 Set Vref, RX VrefLevel [Byte0]: 53
6427 04:37:51.278268 [Byte1]: 52
6428 04:37:51.278349
6429 04:37:51.281723 Final RX Vref Byte 0 = 53 to rank0
6430 04:37:51.285054 Final RX Vref Byte 1 = 52 to rank0
6431 04:37:51.288570 Final RX Vref Byte 0 = 53 to rank1
6432 04:37:51.291966 Final RX Vref Byte 1 = 52 to rank1==
6433 04:37:51.295572 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 04:37:51.298760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 04:37:51.301840 ==
6436 04:37:51.301921 DQS Delay:
6437 04:37:51.301986 DQS0 = 44, DQS1 = 60
6438 04:37:51.305266 DQM Delay:
6439 04:37:51.305351 DQM0 = 10, DQM1 = 15
6440 04:37:51.308264 DQ Delay:
6441 04:37:51.308345 DQ0 =12, DQ1 =8, DQ2 =4, DQ3 =8
6442 04:37:51.312251 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6443 04:37:51.315420 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6444 04:37:51.318490 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6445 04:37:51.318592
6446 04:37:51.318682
6447 04:37:51.328820 [DQSOSCAuto] RK0, (LSB)MR18= 0x8957, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6448 04:37:51.331758 CH0 RK0: MR19=C0C, MR18=8957
6449 04:37:51.335864 CH0_RK0: MR19=0xC0C, MR18=0x8957, DQSOSC=392, MR23=63, INC=384, DEC=256
6450 04:37:51.338819 ==
6451 04:37:51.341886 Dram Type= 6, Freq= 0, CH_0, rank 1
6452 04:37:51.345186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 04:37:51.345268 ==
6454 04:37:51.348807 [Gating] SW mode calibration
6455 04:37:51.355472 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6456 04:37:51.358842 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6457 04:37:51.365498 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6458 04:37:51.368518 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 04:37:51.372264 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 04:37:51.378659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 04:37:51.382177 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 04:37:51.385661 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 04:37:51.392317 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 04:37:51.395601 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 04:37:51.398625 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 04:37:51.402196 Total UI for P1: 0, mck2ui 16
6467 04:37:51.405371 best dqsien dly found for B0: ( 0, 14, 24)
6468 04:37:51.408656 Total UI for P1: 0, mck2ui 16
6469 04:37:51.412372 best dqsien dly found for B1: ( 0, 14, 24)
6470 04:37:51.415575 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6471 04:37:51.418631 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6472 04:37:51.418719
6473 04:37:51.422107 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6474 04:37:51.429023 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 04:37:51.429131 [Gating] SW calibration Done
6476 04:37:51.429225 ==
6477 04:37:51.432454 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 04:37:51.439198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 04:37:51.439303 ==
6480 04:37:51.439396 RX Vref Scan: 0
6481 04:37:51.439484
6482 04:37:51.442243 RX Vref 0 -> 0, step: 1
6483 04:37:51.442315
6484 04:37:51.445750 RX Delay -410 -> 252, step: 16
6485 04:37:51.448656 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6486 04:37:51.452223 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6487 04:37:51.459331 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6488 04:37:51.462413 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6489 04:37:51.465229 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6490 04:37:51.469140 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6491 04:37:51.472356 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6492 04:37:51.478807 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6493 04:37:51.482253 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6494 04:37:51.485704 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6495 04:37:51.489338 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6496 04:37:51.495902 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6497 04:37:51.498999 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6498 04:37:51.502542 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6499 04:37:51.509062 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6500 04:37:51.512357 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6501 04:37:51.512438 ==
6502 04:37:51.515580 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 04:37:51.519577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 04:37:51.519658 ==
6505 04:37:51.519721 DQS Delay:
6506 04:37:51.522141 DQS0 = 43, DQS1 = 51
6507 04:37:51.522222 DQM Delay:
6508 04:37:51.525588 DQM0 = 11, DQM1 = 10
6509 04:37:51.525668 DQ Delay:
6510 04:37:51.529470 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6511 04:37:51.532590 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6512 04:37:51.535450 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6513 04:37:51.538738 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6514 04:37:51.538819
6515 04:37:51.538883
6516 04:37:51.538942 ==
6517 04:37:51.542265 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 04:37:51.545764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 04:37:51.545845 ==
6520 04:37:51.545909
6521 04:37:51.545969
6522 04:37:51.549032 TX Vref Scan disable
6523 04:37:51.553124 == TX Byte 0 ==
6524 04:37:51.556257 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6525 04:37:51.559255 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6526 04:37:51.559367 == TX Byte 1 ==
6527 04:37:51.566044 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6528 04:37:51.569394 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6529 04:37:51.569475 ==
6530 04:37:51.572379 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 04:37:51.576104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 04:37:51.576207 ==
6533 04:37:51.576287
6534 04:37:51.576348
6535 04:37:51.579559 TX Vref Scan disable
6536 04:37:51.579640 == TX Byte 0 ==
6537 04:37:51.586216 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6538 04:37:51.589328 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6539 04:37:51.589403 == TX Byte 1 ==
6540 04:37:51.595812 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6541 04:37:51.599277 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6542 04:37:51.599359
6543 04:37:51.599423 [DATLAT]
6544 04:37:51.602713 Freq=400, CH0 RK1
6545 04:37:51.602794
6546 04:37:51.602858 DATLAT Default: 0xe
6547 04:37:51.606102 0, 0xFFFF, sum = 0
6548 04:37:51.606185 1, 0xFFFF, sum = 0
6549 04:37:51.609457 2, 0xFFFF, sum = 0
6550 04:37:51.609539 3, 0xFFFF, sum = 0
6551 04:37:51.612827 4, 0xFFFF, sum = 0
6552 04:37:51.612909 5, 0xFFFF, sum = 0
6553 04:37:51.615849 6, 0xFFFF, sum = 0
6554 04:37:51.615932 7, 0xFFFF, sum = 0
6555 04:37:51.619419 8, 0xFFFF, sum = 0
6556 04:37:51.619502 9, 0xFFFF, sum = 0
6557 04:37:51.622738 10, 0xFFFF, sum = 0
6558 04:37:51.626096 11, 0xFFFF, sum = 0
6559 04:37:51.626177 12, 0xFFFF, sum = 0
6560 04:37:51.629239 13, 0x0, sum = 1
6561 04:37:51.629321 14, 0x0, sum = 2
6562 04:37:51.629386 15, 0x0, sum = 3
6563 04:37:51.632512 16, 0x0, sum = 4
6564 04:37:51.632630 best_step = 14
6565 04:37:51.632746
6566 04:37:51.636003 ==
6567 04:37:51.639239 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 04:37:51.642550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 04:37:51.642631 ==
6570 04:37:51.642696 RX Vref Scan: 0
6571 04:37:51.642756
6572 04:37:51.645983 RX Vref 0 -> 0, step: 1
6573 04:37:51.646063
6574 04:37:51.648938 RX Delay -343 -> 252, step: 8
6575 04:37:51.655965 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6576 04:37:51.659489 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6577 04:37:51.662861 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6578 04:37:51.665950 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6579 04:37:51.672614 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6580 04:37:51.675803 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6581 04:37:51.678963 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6582 04:37:51.682634 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6583 04:37:51.689181 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6584 04:37:51.692750 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6585 04:37:51.696058 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6586 04:37:51.699530 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6587 04:37:51.705903 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6588 04:37:51.709044 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6589 04:37:51.712458 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6590 04:37:51.715894 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6591 04:37:51.719091 ==
6592 04:37:51.722340 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 04:37:51.726393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 04:37:51.726495 ==
6595 04:37:51.726585 DQS Delay:
6596 04:37:51.729565 DQS0 = 48, DQS1 = 60
6597 04:37:51.729638 DQM Delay:
6598 04:37:51.732361 DQM0 = 12, DQM1 = 13
6599 04:37:51.732458 DQ Delay:
6600 04:37:51.736027 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6601 04:37:51.739140 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6602 04:37:51.742493 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6603 04:37:51.745955 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6604 04:37:51.746040
6605 04:37:51.746119
6606 04:37:51.752491 [DQSOSCAuto] RK1, (LSB)MR18= 0x9567, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6607 04:37:51.756274 CH0 RK1: MR19=C0C, MR18=9567
6608 04:37:51.762883 CH0_RK1: MR19=0xC0C, MR18=0x9567, DQSOSC=391, MR23=63, INC=386, DEC=257
6609 04:37:51.765709 [RxdqsGatingPostProcess] freq 400
6610 04:37:51.769402 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6611 04:37:51.772744 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 04:37:51.776077 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 04:37:51.779521 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 04:37:51.782720 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 04:37:51.785803 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 04:37:51.789181 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 04:37:51.792760 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 04:37:51.795814 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 04:37:51.799288 Pre-setting of DQS Precalculation
6620 04:37:51.802751 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6621 04:37:51.802832 ==
6622 04:37:51.806412 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 04:37:51.813022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 04:37:51.813108 ==
6625 04:37:51.816222 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 04:37:51.822695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6627 04:37:51.825912 [CA 0] Center 36 (8~64) winsize 57
6628 04:37:51.829122 [CA 1] Center 36 (8~64) winsize 57
6629 04:37:51.832530 [CA 2] Center 36 (8~64) winsize 57
6630 04:37:51.835839 [CA 3] Center 36 (8~64) winsize 57
6631 04:37:51.839483 [CA 4] Center 36 (8~64) winsize 57
6632 04:37:51.843004 [CA 5] Center 36 (8~64) winsize 57
6633 04:37:51.843126
6634 04:37:51.846189 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6635 04:37:51.846273
6636 04:37:51.849535 [CATrainingPosCal] consider 1 rank data
6637 04:37:51.852705 u2DelayCellTimex100 = 270/100 ps
6638 04:37:51.856104 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 04:37:51.859511 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 04:37:51.862786 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 04:37:51.866154 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 04:37:51.869819 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 04:37:51.872936 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 04:37:51.873058
6645 04:37:51.879760 CA PerBit enable=1, Macro0, CA PI delay=36
6646 04:37:51.879844
6647 04:37:51.879929 [CBTSetCACLKResult] CA Dly = 36
6648 04:37:51.882595 CS Dly: 1 (0~32)
6649 04:37:51.882679 ==
6650 04:37:51.886155 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 04:37:51.889419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 04:37:51.889504 ==
6653 04:37:51.896059 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 04:37:51.902604 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6655 04:37:51.906522 [CA 0] Center 36 (8~64) winsize 57
6656 04:37:51.909594 [CA 1] Center 36 (8~64) winsize 57
6657 04:37:51.912785 [CA 2] Center 36 (8~64) winsize 57
6658 04:37:51.912869 [CA 3] Center 36 (8~64) winsize 57
6659 04:37:51.916268 [CA 4] Center 36 (8~64) winsize 57
6660 04:37:51.919319 [CA 5] Center 36 (8~64) winsize 57
6661 04:37:51.919400
6662 04:37:51.926354 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6663 04:37:51.926460
6664 04:37:51.929533 [CATrainingPosCal] consider 2 rank data
6665 04:37:51.929635 u2DelayCellTimex100 = 270/100 ps
6666 04:37:51.936295 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 04:37:51.939249 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 04:37:51.942899 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 04:37:51.945836 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 04:37:51.949341 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 04:37:51.952575 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 04:37:51.952724
6673 04:37:51.956466 CA PerBit enable=1, Macro0, CA PI delay=36
6674 04:37:51.956571
6675 04:37:51.959543 [CBTSetCACLKResult] CA Dly = 36
6676 04:37:51.962896 CS Dly: 1 (0~32)
6677 04:37:51.962985
6678 04:37:51.966244 ----->DramcWriteLeveling(PI) begin...
6679 04:37:51.966334 ==
6680 04:37:51.969621 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 04:37:51.972617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 04:37:51.972759 ==
6683 04:37:51.976396 Write leveling (Byte 0): 40 => 8
6684 04:37:51.979305 Write leveling (Byte 1): 40 => 8
6685 04:37:51.982913 DramcWriteLeveling(PI) end<-----
6686 04:37:51.983026
6687 04:37:51.983119 ==
6688 04:37:51.986430 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 04:37:51.989323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 04:37:51.989461 ==
6691 04:37:51.993168 [Gating] SW mode calibration
6692 04:37:51.999219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6693 04:37:52.006388 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6694 04:37:52.009753 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6695 04:37:52.012932 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6696 04:37:52.016345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 04:37:52.023320 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 04:37:52.026439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 04:37:52.029780 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 04:37:52.036323 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 04:37:52.040073 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 04:37:52.043348 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 04:37:52.046700 Total UI for P1: 0, mck2ui 16
6704 04:37:52.050187 best dqsien dly found for B0: ( 0, 14, 24)
6705 04:37:52.053657 Total UI for P1: 0, mck2ui 16
6706 04:37:52.056438 best dqsien dly found for B1: ( 0, 14, 24)
6707 04:37:52.059718 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6708 04:37:52.063017 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6709 04:37:52.063099
6710 04:37:52.070006 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6711 04:37:52.073464 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 04:37:52.076507 [Gating] SW calibration Done
6713 04:37:52.076588 ==
6714 04:37:52.079892 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 04:37:52.083038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 04:37:52.083120 ==
6717 04:37:52.083185 RX Vref Scan: 0
6718 04:37:52.083293
6719 04:37:52.086845 RX Vref 0 -> 0, step: 1
6720 04:37:52.086926
6721 04:37:52.089593 RX Delay -410 -> 252, step: 16
6722 04:37:52.093018 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6723 04:37:52.096402 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6724 04:37:52.103206 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6725 04:37:52.106585 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6726 04:37:52.109706 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6727 04:37:52.113116 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6728 04:37:52.119439 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6729 04:37:52.123073 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6730 04:37:52.126391 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6731 04:37:52.129767 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6732 04:37:52.136447 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6733 04:37:52.139860 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6734 04:37:52.142691 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6735 04:37:52.149369 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6736 04:37:52.152949 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6737 04:37:52.156259 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6738 04:37:52.156340 ==
6739 04:37:52.159817 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 04:37:52.163307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 04:37:52.163388 ==
6742 04:37:52.166177 DQS Delay:
6743 04:37:52.166257 DQS0 = 51, DQS1 = 59
6744 04:37:52.169976 DQM Delay:
6745 04:37:52.170056 DQM0 = 19, DQM1 = 16
6746 04:37:52.170120 DQ Delay:
6747 04:37:52.173273 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6748 04:37:52.176192 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6749 04:37:52.179656 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6750 04:37:52.183070 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6751 04:37:52.183176
6752 04:37:52.183267
6753 04:37:52.183354 ==
6754 04:37:52.186543 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 04:37:52.193035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 04:37:52.193115 ==
6757 04:37:52.193179
6758 04:37:52.193237
6759 04:37:52.193295 TX Vref Scan disable
6760 04:37:52.196761 == TX Byte 0 ==
6761 04:37:52.199603 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 04:37:52.203404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 04:37:52.206446 == TX Byte 1 ==
6764 04:37:52.209919 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 04:37:52.212842 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 04:37:52.212949 ==
6767 04:37:52.216200 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 04:37:52.223104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 04:37:52.223215 ==
6770 04:37:52.223307
6771 04:37:52.223399
6772 04:37:52.223485 TX Vref Scan disable
6773 04:37:52.226583 == TX Byte 0 ==
6774 04:37:52.230070 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 04:37:52.232820 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 04:37:52.236278 == TX Byte 1 ==
6777 04:37:52.239668 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 04:37:52.243038 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 04:37:52.243140
6780 04:37:52.246623 [DATLAT]
6781 04:37:52.246722 Freq=400, CH1 RK0
6782 04:37:52.246826
6783 04:37:52.250092 DATLAT Default: 0xf
6784 04:37:52.250192 0, 0xFFFF, sum = 0
6785 04:37:52.253473 1, 0xFFFF, sum = 0
6786 04:37:52.253580 2, 0xFFFF, sum = 0
6787 04:37:52.256881 3, 0xFFFF, sum = 0
6788 04:37:52.256973 4, 0xFFFF, sum = 0
6789 04:37:52.259763 5, 0xFFFF, sum = 0
6790 04:37:52.259864 6, 0xFFFF, sum = 0
6791 04:37:52.263060 7, 0xFFFF, sum = 0
6792 04:37:52.263162 8, 0xFFFF, sum = 0
6793 04:37:52.266305 9, 0xFFFF, sum = 0
6794 04:37:52.266406 10, 0xFFFF, sum = 0
6795 04:37:52.269640 11, 0xFFFF, sum = 0
6796 04:37:52.273506 12, 0xFFFF, sum = 0
6797 04:37:52.273609 13, 0x0, sum = 1
6798 04:37:52.273704 14, 0x0, sum = 2
6799 04:37:52.276336 15, 0x0, sum = 3
6800 04:37:52.276434 16, 0x0, sum = 4
6801 04:37:52.279724 best_step = 14
6802 04:37:52.279820
6803 04:37:52.279883 ==
6804 04:37:52.283421 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 04:37:52.286780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 04:37:52.286878 ==
6807 04:37:52.289916 RX Vref Scan: 1
6808 04:37:52.290022
6809 04:37:52.290113 RX Vref 0 -> 0, step: 1
6810 04:37:52.290200
6811 04:37:52.293439 RX Delay -359 -> 252, step: 8
6812 04:37:52.293534
6813 04:37:52.296397 Set Vref, RX VrefLevel [Byte0]: 56
6814 04:37:52.299753 [Byte1]: 55
6815 04:37:52.304808
6816 04:37:52.304912 Final RX Vref Byte 0 = 56 to rank0
6817 04:37:52.308768 Final RX Vref Byte 1 = 55 to rank0
6818 04:37:52.311484 Final RX Vref Byte 0 = 56 to rank1
6819 04:37:52.314924 Final RX Vref Byte 1 = 55 to rank1==
6820 04:37:52.318307 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 04:37:52.324896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 04:37:52.325002 ==
6823 04:37:52.325104 DQS Delay:
6824 04:37:52.328482 DQS0 = 48, DQS1 = 64
6825 04:37:52.328581 DQM Delay:
6826 04:37:52.328708 DQM0 = 13, DQM1 = 16
6827 04:37:52.331291 DQ Delay:
6828 04:37:52.334662 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6829 04:37:52.337867 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6830 04:37:52.337967 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6831 04:37:52.341677 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6832 04:37:52.344989
6833 04:37:52.345089
6834 04:37:52.351779 [DQSOSCAuto] RK0, (LSB)MR18= 0x8830, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6835 04:37:52.354663 CH1 RK0: MR19=C0C, MR18=8830
6836 04:37:52.361344 CH1_RK0: MR19=0xC0C, MR18=0x8830, DQSOSC=392, MR23=63, INC=384, DEC=256
6837 04:37:52.361422 ==
6838 04:37:52.365034 Dram Type= 6, Freq= 0, CH_1, rank 1
6839 04:37:52.367928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 04:37:52.368028 ==
6841 04:37:52.371261 [Gating] SW mode calibration
6842 04:37:52.377833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6843 04:37:52.384563 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6844 04:37:52.387791 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6845 04:37:52.391464 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 04:37:52.394937 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 04:37:52.401351 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 04:37:52.404414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 04:37:52.407776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 04:37:52.414802 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 04:37:52.417768 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 04:37:52.421170 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 04:37:52.424433 Total UI for P1: 0, mck2ui 16
6854 04:37:52.428085 best dqsien dly found for B0: ( 0, 14, 24)
6855 04:37:52.430904 Total UI for P1: 0, mck2ui 16
6856 04:37:52.434340 best dqsien dly found for B1: ( 0, 14, 24)
6857 04:37:52.437745 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6858 04:37:52.444341 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6859 04:37:52.444444
6860 04:37:52.447704 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6861 04:37:52.450950 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 04:37:52.454850 [Gating] SW calibration Done
6863 04:37:52.454948 ==
6864 04:37:52.457687 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 04:37:52.461329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 04:37:52.461427 ==
6867 04:37:52.461521 RX Vref Scan: 0
6868 04:37:52.461608
6869 04:37:52.464456 RX Vref 0 -> 0, step: 1
6870 04:37:52.464550
6871 04:37:52.467878 RX Delay -410 -> 252, step: 16
6872 04:37:52.471349 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6873 04:37:52.477854 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6874 04:37:52.481025 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6875 04:37:52.484343 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6876 04:37:52.487941 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6877 04:37:52.494390 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6878 04:37:52.497822 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6879 04:37:52.501705 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6880 04:37:52.505037 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6881 04:37:52.507744 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6882 04:37:52.514862 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6883 04:37:52.517920 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6884 04:37:52.521155 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6885 04:37:52.527703 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6886 04:37:52.530968 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6887 04:37:52.534683 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6888 04:37:52.534782 ==
6889 04:37:52.537912 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 04:37:52.541691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 04:37:52.541792 ==
6892 04:37:52.544899 DQS Delay:
6893 04:37:52.544998 DQS0 = 43, DQS1 = 59
6894 04:37:52.547938 DQM Delay:
6895 04:37:52.548034 DQM0 = 9, DQM1 = 19
6896 04:37:52.548127 DQ Delay:
6897 04:37:52.551144 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6898 04:37:52.554996 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6899 04:37:52.558144 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6900 04:37:52.561604 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =32
6901 04:37:52.561684
6902 04:37:52.561747
6903 04:37:52.561805 ==
6904 04:37:52.564737 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 04:37:52.571061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 04:37:52.571167 ==
6907 04:37:52.571269
6908 04:37:52.571361
6909 04:37:52.571447 TX Vref Scan disable
6910 04:37:52.574969 == TX Byte 0 ==
6911 04:37:52.577992 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6912 04:37:52.581398 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6913 04:37:52.584958 == TX Byte 1 ==
6914 04:37:52.588342 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6915 04:37:52.591223 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6916 04:37:52.591329 ==
6917 04:37:52.594707 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 04:37:52.601615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 04:37:52.601695 ==
6920 04:37:52.601758
6921 04:37:52.601816
6922 04:37:52.601872 TX Vref Scan disable
6923 04:37:52.604726 == TX Byte 0 ==
6924 04:37:52.607784 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6925 04:37:52.611443 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6926 04:37:52.615003 == TX Byte 1 ==
6927 04:37:52.618427 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6928 04:37:52.621448 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6929 04:37:52.621528
6930 04:37:52.624823 [DATLAT]
6931 04:37:52.624902 Freq=400, CH1 RK1
6932 04:37:52.624966
6933 04:37:52.627948 DATLAT Default: 0xe
6934 04:37:52.628027 0, 0xFFFF, sum = 0
6935 04:37:52.631309 1, 0xFFFF, sum = 0
6936 04:37:52.631404 2, 0xFFFF, sum = 0
6937 04:37:52.634797 3, 0xFFFF, sum = 0
6938 04:37:52.634907 4, 0xFFFF, sum = 0
6939 04:37:52.638189 5, 0xFFFF, sum = 0
6940 04:37:52.638299 6, 0xFFFF, sum = 0
6941 04:37:52.641377 7, 0xFFFF, sum = 0
6942 04:37:52.641482 8, 0xFFFF, sum = 0
6943 04:37:52.644927 9, 0xFFFF, sum = 0
6944 04:37:52.645029 10, 0xFFFF, sum = 0
6945 04:37:52.648129 11, 0xFFFF, sum = 0
6946 04:37:52.648229 12, 0xFFFF, sum = 0
6947 04:37:52.651555 13, 0x0, sum = 1
6948 04:37:52.651681 14, 0x0, sum = 2
6949 04:37:52.655062 15, 0x0, sum = 3
6950 04:37:52.655175 16, 0x0, sum = 4
6951 04:37:52.658219 best_step = 14
6952 04:37:52.658331
6953 04:37:52.658423 ==
6954 04:37:52.661274 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 04:37:52.664827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 04:37:52.664927 ==
6957 04:37:52.668375 RX Vref Scan: 0
6958 04:37:52.668470
6959 04:37:52.668562 RX Vref 0 -> 0, step: 1
6960 04:37:52.668649
6961 04:37:52.671927 RX Delay -359 -> 252, step: 8
6962 04:37:52.679717 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6963 04:37:52.683056 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6964 04:37:52.686107 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6965 04:37:52.689822 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6966 04:37:52.695786 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6967 04:37:52.699123 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6968 04:37:52.702740 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6969 04:37:52.706244 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6970 04:37:52.712527 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6971 04:37:52.715708 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6972 04:37:52.719249 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6973 04:37:52.722655 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6974 04:37:52.729477 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6975 04:37:52.732957 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6976 04:37:52.735982 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6977 04:37:52.739643 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6978 04:37:52.743042 ==
6979 04:37:52.746487 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 04:37:52.749727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 04:37:52.749813 ==
6982 04:37:52.749877 DQS Delay:
6983 04:37:52.753046 DQS0 = 48, DQS1 = 60
6984 04:37:52.753125 DQM Delay:
6985 04:37:52.755931 DQM0 = 9, DQM1 = 13
6986 04:37:52.756010 DQ Delay:
6987 04:37:52.759146 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6988 04:37:52.762903 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6989 04:37:52.765987 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6990 04:37:52.769786 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6991 04:37:52.769866
6992 04:37:52.769929
6993 04:37:52.776306 [DQSOSCAuto] RK1, (LSB)MR18= 0x7086, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6994 04:37:52.779628 CH1 RK1: MR19=C0C, MR18=7086
6995 04:37:52.786025 CH1_RK1: MR19=0xC0C, MR18=0x7086, DQSOSC=393, MR23=63, INC=382, DEC=254
6996 04:37:52.789868 [RxdqsGatingPostProcess] freq 400
6997 04:37:52.792956 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6998 04:37:52.795832 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 04:37:52.799170 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 04:37:52.802953 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 04:37:52.806113 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 04:37:52.809924 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 04:37:52.812757 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 04:37:52.816039 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 04:37:52.819572 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 04:37:52.822914 Pre-setting of DQS Precalculation
7007 04:37:52.826135 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7008 04:37:52.832617 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7009 04:37:52.842775 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7010 04:37:52.842881
7011 04:37:52.842973
7012 04:37:52.843066 [Calibration Summary] 800 Mbps
7013 04:37:52.846495 CH 0, Rank 0
7014 04:37:52.846591 SW Impedance : PASS
7015 04:37:52.849331 DUTY Scan : NO K
7016 04:37:52.852870 ZQ Calibration : PASS
7017 04:37:52.852967 Jitter Meter : NO K
7018 04:37:52.856370 CBT Training : PASS
7019 04:37:52.859493 Write leveling : PASS
7020 04:37:52.859591 RX DQS gating : PASS
7021 04:37:52.862696 RX DQ/DQS(RDDQC) : PASS
7022 04:37:52.866047 TX DQ/DQS : PASS
7023 04:37:52.866146 RX DATLAT : PASS
7024 04:37:52.869536 RX DQ/DQS(Engine): PASS
7025 04:37:52.872853 TX OE : NO K
7026 04:37:52.872949 All Pass.
7027 04:37:52.873041
7028 04:37:52.873133 CH 0, Rank 1
7029 04:37:52.876390 SW Impedance : PASS
7030 04:37:52.879469 DUTY Scan : NO K
7031 04:37:52.879571 ZQ Calibration : PASS
7032 04:37:52.883135 Jitter Meter : NO K
7033 04:37:52.886486 CBT Training : PASS
7034 04:37:52.886588 Write leveling : NO K
7035 04:37:52.889280 RX DQS gating : PASS
7036 04:37:52.889380 RX DQ/DQS(RDDQC) : PASS
7037 04:37:52.892803 TX DQ/DQS : PASS
7038 04:37:52.896362 RX DATLAT : PASS
7039 04:37:52.896434 RX DQ/DQS(Engine): PASS
7040 04:37:52.899840 TX OE : NO K
7041 04:37:52.899910 All Pass.
7042 04:37:52.899969
7043 04:37:52.903214 CH 1, Rank 0
7044 04:37:52.903295 SW Impedance : PASS
7045 04:37:52.906520 DUTY Scan : NO K
7046 04:37:52.909497 ZQ Calibration : PASS
7047 04:37:52.909571 Jitter Meter : NO K
7048 04:37:52.912871 CBT Training : PASS
7049 04:37:52.916480 Write leveling : PASS
7050 04:37:52.916547 RX DQS gating : PASS
7051 04:37:52.919926 RX DQ/DQS(RDDQC) : PASS
7052 04:37:52.923021 TX DQ/DQS : PASS
7053 04:37:52.923105 RX DATLAT : PASS
7054 04:37:52.926667 RX DQ/DQS(Engine): PASS
7055 04:37:52.926773 TX OE : NO K
7056 04:37:52.929720 All Pass.
7057 04:37:52.929800
7058 04:37:52.929914 CH 1, Rank 1
7059 04:37:52.933712 SW Impedance : PASS
7060 04:37:52.933792 DUTY Scan : NO K
7061 04:37:52.936719 ZQ Calibration : PASS
7062 04:37:52.939961 Jitter Meter : NO K
7063 04:37:52.940041 CBT Training : PASS
7064 04:37:52.943130 Write leveling : NO K
7065 04:37:52.946682 RX DQS gating : PASS
7066 04:37:52.946761 RX DQ/DQS(RDDQC) : PASS
7067 04:37:52.949815 TX DQ/DQS : PASS
7068 04:37:52.953344 RX DATLAT : PASS
7069 04:37:52.953423 RX DQ/DQS(Engine): PASS
7070 04:37:52.956521 TX OE : NO K
7071 04:37:52.956600 All Pass.
7072 04:37:52.956663
7073 04:37:52.959806 DramC Write-DBI off
7074 04:37:52.963080 PER_BANK_REFRESH: Hybrid Mode
7075 04:37:52.963160 TX_TRACKING: ON
7076 04:37:52.973368 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7077 04:37:52.976793 [FAST_K] Save calibration result to emmc
7078 04:37:52.980232 dramc_set_vcore_voltage set vcore to 725000
7079 04:37:52.983362 Read voltage for 1600, 0
7080 04:37:52.983441 Vio18 = 0
7081 04:37:52.983506 Vcore = 725000
7082 04:37:52.986507 Vdram = 0
7083 04:37:52.986586 Vddq = 0
7084 04:37:52.986649 Vmddr = 0
7085 04:37:52.993168 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7086 04:37:52.996644 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7087 04:37:52.999860 MEM_TYPE=3, freq_sel=13
7088 04:37:53.003110 sv_algorithm_assistance_LP4_3733
7089 04:37:53.006622 ============ PULL DRAM RESETB DOWN ============
7090 04:37:53.010125 ========== PULL DRAM RESETB DOWN end =========
7091 04:37:53.016639 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7092 04:37:53.020194 ===================================
7093 04:37:53.020275 LPDDR4 DRAM CONFIGURATION
7094 04:37:53.023947 ===================================
7095 04:37:53.026677 EX_ROW_EN[0] = 0x0
7096 04:37:53.026757 EX_ROW_EN[1] = 0x0
7097 04:37:53.030044 LP4Y_EN = 0x0
7098 04:37:53.030124 WORK_FSP = 0x1
7099 04:37:53.033325 WL = 0x5
7100 04:37:53.036616 RL = 0x5
7101 04:37:53.036735 BL = 0x2
7102 04:37:53.040165 RPST = 0x0
7103 04:37:53.040244 RD_PRE = 0x0
7104 04:37:53.043525 WR_PRE = 0x1
7105 04:37:53.043649 WR_PST = 0x1
7106 04:37:53.046631 DBI_WR = 0x0
7107 04:37:53.046729 DBI_RD = 0x0
7108 04:37:53.050568 OTF = 0x1
7109 04:37:53.053362 ===================================
7110 04:37:53.056806 ===================================
7111 04:37:53.056881 ANA top config
7112 04:37:53.059848 ===================================
7113 04:37:53.063755 DLL_ASYNC_EN = 0
7114 04:37:53.067201 ALL_SLAVE_EN = 0
7115 04:37:53.067299 NEW_RANK_MODE = 1
7116 04:37:53.070223 DLL_IDLE_MODE = 1
7117 04:37:53.073708 LP45_APHY_COMB_EN = 1
7118 04:37:53.076946 TX_ODT_DIS = 0
7119 04:37:53.077043 NEW_8X_MODE = 1
7120 04:37:53.079859 ===================================
7121 04:37:53.083248 ===================================
7122 04:37:53.086710 data_rate = 3200
7123 04:37:53.090099 CKR = 1
7124 04:37:53.093780 DQ_P2S_RATIO = 8
7125 04:37:53.096522 ===================================
7126 04:37:53.099908 CA_P2S_RATIO = 8
7127 04:37:53.103662 DQ_CA_OPEN = 0
7128 04:37:53.103742 DQ_SEMI_OPEN = 0
7129 04:37:53.107087 CA_SEMI_OPEN = 0
7130 04:37:53.110539 CA_FULL_RATE = 0
7131 04:37:53.113324 DQ_CKDIV4_EN = 0
7132 04:37:53.116832 CA_CKDIV4_EN = 0
7133 04:37:53.120244 CA_PREDIV_EN = 0
7134 04:37:53.120353 PH8_DLY = 12
7135 04:37:53.123408 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7136 04:37:53.127085 DQ_AAMCK_DIV = 4
7137 04:37:53.129895 CA_AAMCK_DIV = 4
7138 04:37:53.133926 CA_ADMCK_DIV = 4
7139 04:37:53.137097 DQ_TRACK_CA_EN = 0
7140 04:37:53.137201 CA_PICK = 1600
7141 04:37:53.140092 CA_MCKIO = 1600
7142 04:37:53.143669 MCKIO_SEMI = 0
7143 04:37:53.146739 PLL_FREQ = 3068
7144 04:37:53.150331 DQ_UI_PI_RATIO = 32
7145 04:37:53.153558 CA_UI_PI_RATIO = 0
7146 04:37:53.157310 ===================================
7147 04:37:53.160088 ===================================
7148 04:37:53.160192 memory_type:LPDDR4
7149 04:37:53.163433 GP_NUM : 10
7150 04:37:53.167084 SRAM_EN : 1
7151 04:37:53.167184 MD32_EN : 0
7152 04:37:53.170192 ===================================
7153 04:37:53.173920 [ANA_INIT] >>>>>>>>>>>>>>
7154 04:37:53.177051 <<<<<< [CONFIGURE PHASE]: ANA_TX
7155 04:37:53.180602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7156 04:37:53.183650 ===================================
7157 04:37:53.186999 data_rate = 3200,PCW = 0X7600
7158 04:37:53.190321 ===================================
7159 04:37:53.193544 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7160 04:37:53.197118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7161 04:37:53.203362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 04:37:53.206787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7163 04:37:53.209889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7164 04:37:53.213262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7165 04:37:53.216996 [ANA_INIT] flow start
7166 04:37:53.220044 [ANA_INIT] PLL >>>>>>>>
7167 04:37:53.220145 [ANA_INIT] PLL <<<<<<<<
7168 04:37:53.223820 [ANA_INIT] MIDPI >>>>>>>>
7169 04:37:53.226787 [ANA_INIT] MIDPI <<<<<<<<
7170 04:37:53.230363 [ANA_INIT] DLL >>>>>>>>
7171 04:37:53.230462 [ANA_INIT] DLL <<<<<<<<
7172 04:37:53.233668 [ANA_INIT] flow end
7173 04:37:53.236994 ============ LP4 DIFF to SE enter ============
7174 04:37:53.240188 ============ LP4 DIFF to SE exit ============
7175 04:37:53.243422 [ANA_INIT] <<<<<<<<<<<<<
7176 04:37:53.246591 [Flow] Enable top DCM control >>>>>
7177 04:37:53.250423 [Flow] Enable top DCM control <<<<<
7178 04:37:53.253453 Enable DLL master slave shuffle
7179 04:37:53.256840 ==============================================================
7180 04:37:53.260105 Gating Mode config
7181 04:37:53.267219 ==============================================================
7182 04:37:53.267325 Config description:
7183 04:37:53.276693 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7184 04:37:53.283586 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7185 04:37:53.290399 SELPH_MODE 0: By rank 1: By Phase
7186 04:37:53.293425 ==============================================================
7187 04:37:53.297488 GAT_TRACK_EN = 1
7188 04:37:53.300108 RX_GATING_MODE = 2
7189 04:37:53.303426 RX_GATING_TRACK_MODE = 2
7190 04:37:53.306734 SELPH_MODE = 1
7191 04:37:53.310400 PICG_EARLY_EN = 1
7192 04:37:53.313866 VALID_LAT_VALUE = 1
7193 04:37:53.317341 ==============================================================
7194 04:37:53.320272 Enter into Gating configuration >>>>
7195 04:37:53.323716 Exit from Gating configuration <<<<
7196 04:37:53.326894 Enter into DVFS_PRE_config >>>>>
7197 04:37:53.337666 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7198 04:37:53.340573 Exit from DVFS_PRE_config <<<<<
7199 04:37:53.343865 Enter into PICG configuration >>>>
7200 04:37:53.347235 Exit from PICG configuration <<<<
7201 04:37:53.350669 [RX_INPUT] configuration >>>>>
7202 04:37:53.353676 [RX_INPUT] configuration <<<<<
7203 04:37:53.360476 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7204 04:37:53.363727 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7205 04:37:53.370397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 04:37:53.377294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 04:37:53.383945 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 04:37:53.390496 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 04:37:53.393692 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7210 04:37:53.397020 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7211 04:37:53.400537 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7212 04:37:53.403913 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7213 04:37:53.411001 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7214 04:37:53.414029 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 04:37:53.417421 ===================================
7216 04:37:53.420857 LPDDR4 DRAM CONFIGURATION
7217 04:37:53.424984 ===================================
7218 04:37:53.425090 EX_ROW_EN[0] = 0x0
7219 04:37:53.427858 EX_ROW_EN[1] = 0x0
7220 04:37:53.427966 LP4Y_EN = 0x0
7221 04:37:53.431462 WORK_FSP = 0x1
7222 04:37:53.431563 WL = 0x5
7223 04:37:53.434169 RL = 0x5
7224 04:37:53.434270 BL = 0x2
7225 04:37:53.437732 RPST = 0x0
7226 04:37:53.437834 RD_PRE = 0x0
7227 04:37:53.441093 WR_PRE = 0x1
7228 04:37:53.441192 WR_PST = 0x1
7229 04:37:53.444529 DBI_WR = 0x0
7230 04:37:53.444610 DBI_RD = 0x0
7231 04:37:53.447664 OTF = 0x1
7232 04:37:53.451359 ===================================
7233 04:37:53.454288 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7234 04:37:53.457331 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7235 04:37:53.464248 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7236 04:37:53.467359 ===================================
7237 04:37:53.467440 LPDDR4 DRAM CONFIGURATION
7238 04:37:53.470895 ===================================
7239 04:37:53.474612 EX_ROW_EN[0] = 0x10
7240 04:37:53.477575 EX_ROW_EN[1] = 0x0
7241 04:37:53.477647 LP4Y_EN = 0x0
7242 04:37:53.481021 WORK_FSP = 0x1
7243 04:37:53.481089 WL = 0x5
7244 04:37:53.484308 RL = 0x5
7245 04:37:53.484402 BL = 0x2
7246 04:37:53.487651 RPST = 0x0
7247 04:37:53.487748 RD_PRE = 0x0
7248 04:37:53.490882 WR_PRE = 0x1
7249 04:37:53.490977 WR_PST = 0x1
7250 04:37:53.494348 DBI_WR = 0x0
7251 04:37:53.494440 DBI_RD = 0x0
7252 04:37:53.497837 OTF = 0x1
7253 04:37:53.501310 ===================================
7254 04:37:53.507462 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7255 04:37:53.507567 ==
7256 04:37:53.510889 Dram Type= 6, Freq= 0, CH_0, rank 0
7257 04:37:53.514263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7258 04:37:53.514343 ==
7259 04:37:53.517889 [Duty_Offset_Calibration]
7260 04:37:53.517969 B0:2 B1:-1 CA:1
7261 04:37:53.518033
7262 04:37:53.520931 [DutyScan_Calibration_Flow] k_type=0
7263 04:37:53.530301
7264 04:37:53.530382 ==CLK 0==
7265 04:37:53.534086 Final CLK duty delay cell = -4
7266 04:37:53.536908 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7267 04:37:53.540381 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7268 04:37:53.543847 [-4] AVG Duty = 4937%(X100)
7269 04:37:53.543927
7270 04:37:53.547481 CH0 CLK Duty spec in!! Max-Min= 187%
7271 04:37:53.550636 [DutyScan_Calibration_Flow] ====Done====
7272 04:37:53.550716
7273 04:37:53.553614 [DutyScan_Calibration_Flow] k_type=1
7274 04:37:53.570062
7275 04:37:53.570141 ==DQS 0 ==
7276 04:37:53.573492 Final DQS duty delay cell = 0
7277 04:37:53.576897 [0] MAX Duty = 5125%(X100), DQS PI = 20
7278 04:37:53.580278 [0] MIN Duty = 5000%(X100), DQS PI = 14
7279 04:37:53.583569 [0] AVG Duty = 5062%(X100)
7280 04:37:53.583649
7281 04:37:53.583713 ==DQS 1 ==
7282 04:37:53.586470 Final DQS duty delay cell = -4
7283 04:37:53.590108 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7284 04:37:53.593474 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7285 04:37:53.596413 [-4] AVG Duty = 5046%(X100)
7286 04:37:53.596493
7287 04:37:53.599603 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7288 04:37:53.599683
7289 04:37:53.603037 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7290 04:37:53.606684 [DutyScan_Calibration_Flow] ====Done====
7291 04:37:53.606765
7292 04:37:53.609748 [DutyScan_Calibration_Flow] k_type=3
7293 04:37:53.627326
7294 04:37:53.627415 ==DQM 0 ==
7295 04:37:53.631204 Final DQM duty delay cell = 0
7296 04:37:53.633910 [0] MAX Duty = 5000%(X100), DQS PI = 20
7297 04:37:53.637498 [0] MIN Duty = 4875%(X100), DQS PI = 4
7298 04:37:53.637577 [0] AVG Duty = 4937%(X100)
7299 04:37:53.640683
7300 04:37:53.640791 ==DQM 1 ==
7301 04:37:53.644420 Final DQM duty delay cell = 0
7302 04:37:53.647473 [0] MAX Duty = 5187%(X100), DQS PI = 58
7303 04:37:53.650810 [0] MIN Duty = 4969%(X100), DQS PI = 20
7304 04:37:53.650890 [0] AVG Duty = 5078%(X100)
7305 04:37:53.654261
7306 04:37:53.657755 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7307 04:37:53.657836
7308 04:37:53.661134 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7309 04:37:53.664102 [DutyScan_Calibration_Flow] ====Done====
7310 04:37:53.664181
7311 04:37:53.667645 [DutyScan_Calibration_Flow] k_type=2
7312 04:37:53.683900
7313 04:37:53.683979 ==DQ 0 ==
7314 04:37:53.687150 Final DQ duty delay cell = -4
7315 04:37:53.690435 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7316 04:37:53.693974 [-4] MIN Duty = 4844%(X100), DQS PI = 28
7317 04:37:53.697033 [-4] AVG Duty = 4937%(X100)
7318 04:37:53.697113
7319 04:37:53.697176 ==DQ 1 ==
7320 04:37:53.700359 Final DQ duty delay cell = 0
7321 04:37:53.703990 [0] MAX Duty = 5031%(X100), DQS PI = 30
7322 04:37:53.706992 [0] MIN Duty = 4907%(X100), DQS PI = 26
7323 04:37:53.710286 [0] AVG Duty = 4969%(X100)
7324 04:37:53.710365
7325 04:37:53.714023 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7326 04:37:53.714104
7327 04:37:53.717461 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7328 04:37:53.720619 [DutyScan_Calibration_Flow] ====Done====
7329 04:37:53.720761 ==
7330 04:37:53.723751 Dram Type= 6, Freq= 0, CH_1, rank 0
7331 04:37:53.727253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 04:37:53.727357 ==
7333 04:37:53.730578 [Duty_Offset_Calibration]
7334 04:37:53.730674 B0:1 B1:1 CA:2
7335 04:37:53.730765
7336 04:37:53.733742 [DutyScan_Calibration_Flow] k_type=0
7337 04:37:53.744570
7338 04:37:53.744697 ==CLK 0==
7339 04:37:53.747471 Final CLK duty delay cell = 0
7340 04:37:53.750857 [0] MAX Duty = 5125%(X100), DQS PI = 48
7341 04:37:53.754426 [0] MIN Duty = 4938%(X100), DQS PI = 12
7342 04:37:53.754522 [0] AVG Duty = 5031%(X100)
7343 04:37:53.757798
7344 04:37:53.761033 CH1 CLK Duty spec in!! Max-Min= 187%
7345 04:37:53.764066 [DutyScan_Calibration_Flow] ====Done====
7346 04:37:53.764157
7347 04:37:53.767373 [DutyScan_Calibration_Flow] k_type=1
7348 04:37:53.783935
7349 04:37:53.784035 ==DQS 0 ==
7350 04:37:53.787356 Final DQS duty delay cell = 0
7351 04:37:53.790938 [0] MAX Duty = 5031%(X100), DQS PI = 52
7352 04:37:53.794055 [0] MIN Duty = 4844%(X100), DQS PI = 12
7353 04:37:53.797561 [0] AVG Duty = 4937%(X100)
7354 04:37:53.797653
7355 04:37:53.797742 ==DQS 1 ==
7356 04:37:53.800519 Final DQS duty delay cell = 0
7357 04:37:53.803850 [0] MAX Duty = 5093%(X100), DQS PI = 24
7358 04:37:53.807302 [0] MIN Duty = 4907%(X100), DQS PI = 62
7359 04:37:53.811220 [0] AVG Duty = 5000%(X100)
7360 04:37:53.811321
7361 04:37:53.814049 CH1 DQS 0 Duty spec in!! Max-Min= 187%
7362 04:37:53.814143
7363 04:37:53.817244 CH1 DQS 1 Duty spec in!! Max-Min= 186%
7364 04:37:53.820531 [DutyScan_Calibration_Flow] ====Done====
7365 04:37:53.820626
7366 04:37:53.824232 [DutyScan_Calibration_Flow] k_type=3
7367 04:37:53.840961
7368 04:37:53.841089 ==DQM 0 ==
7369 04:37:53.844402 Final DQM duty delay cell = 0
7370 04:37:53.847760 [0] MAX Duty = 5124%(X100), DQS PI = 52
7371 04:37:53.850990 [0] MIN Duty = 4876%(X100), DQS PI = 18
7372 04:37:53.854443 [0] AVG Duty = 5000%(X100)
7373 04:37:53.854547
7374 04:37:53.854640 ==DQM 1 ==
7375 04:37:53.857677 Final DQM duty delay cell = 0
7376 04:37:53.860987 [0] MAX Duty = 5187%(X100), DQS PI = 28
7377 04:37:53.864248 [0] MIN Duty = 4875%(X100), DQS PI = 52
7378 04:37:53.864347 [0] AVG Duty = 5031%(X100)
7379 04:37:53.867851
7380 04:37:53.871286 CH1 DQM 0 Duty spec in!! Max-Min= 248%
7381 04:37:53.871382
7382 04:37:53.874397 CH1 DQM 1 Duty spec in!! Max-Min= 312%
7383 04:37:53.877863 [DutyScan_Calibration_Flow] ====Done====
7384 04:37:53.877958
7385 04:37:53.881331 [DutyScan_Calibration_Flow] k_type=2
7386 04:37:53.896903
7387 04:37:53.897005 ==DQ 0 ==
7388 04:37:53.900720 Final DQ duty delay cell = 0
7389 04:37:53.904183 [0] MAX Duty = 5125%(X100), DQS PI = 52
7390 04:37:53.907335 [0] MIN Duty = 4938%(X100), DQS PI = 20
7391 04:37:53.907436 [0] AVG Duty = 5031%(X100)
7392 04:37:53.907539
7393 04:37:53.910757 ==DQ 1 ==
7394 04:37:53.914444 Final DQ duty delay cell = -4
7395 04:37:53.917216 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7396 04:37:53.920720 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7397 04:37:53.920817 [-4] AVG Duty = 4938%(X100)
7398 04:37:53.920904
7399 04:37:53.923944 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7400 04:37:53.924049
7401 04:37:53.930635 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7402 04:37:53.934385 [DutyScan_Calibration_Flow] ====Done====
7403 04:37:53.937673 nWR fixed to 30
7404 04:37:53.937784 [ModeRegInit_LP4] CH0 RK0
7405 04:37:53.940736 [ModeRegInit_LP4] CH0 RK1
7406 04:37:53.944036 [ModeRegInit_LP4] CH1 RK0
7407 04:37:53.944143 [ModeRegInit_LP4] CH1 RK1
7408 04:37:53.947297 match AC timing 5
7409 04:37:53.950679 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7410 04:37:53.953963 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7411 04:37:53.960967 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7412 04:37:53.964175 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7413 04:37:53.970876 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7414 04:37:53.970953 [MiockJmeterHQA]
7415 04:37:53.971030
7416 04:37:53.974372 [DramcMiockJmeter] u1RxGatingPI = 0
7417 04:37:53.977461 0 : 4253, 4027
7418 04:37:53.977545 4 : 4363, 4137
7419 04:37:53.977640 8 : 4252, 4027
7420 04:37:53.980745 12 : 4252, 4027
7421 04:37:53.980849 16 : 4366, 4142
7422 04:37:53.984541 20 : 4253, 4026
7423 04:37:53.984644 24 : 4255, 4030
7424 04:37:53.987245 28 : 4253, 4026
7425 04:37:53.987347 32 : 4363, 4138
7426 04:37:53.987451 36 : 4363, 4137
7427 04:37:53.990719 40 : 4250, 4027
7428 04:37:53.990817 44 : 4252, 4027
7429 04:37:53.994383 48 : 4253, 4026
7430 04:37:53.994482 52 : 4252, 4027
7431 04:37:53.997489 56 : 4252, 4027
7432 04:37:53.997586 60 : 4361, 4137
7433 04:37:54.001113 64 : 4250, 4027
7434 04:37:54.001211 68 : 4250, 4026
7435 04:37:54.001301 72 : 4250, 4026
7436 04:37:54.004191 76 : 4250, 4027
7437 04:37:54.004286 80 : 4250, 4027
7438 04:37:54.007360 84 : 4360, 4138
7439 04:37:54.007461 88 : 4360, 4137
7440 04:37:54.010919 92 : 4250, 4027
7441 04:37:54.011030 96 : 4250, 3317
7442 04:37:54.011122 100 : 4250, 0
7443 04:37:54.014213 104 : 4253, 0
7444 04:37:54.014316 108 : 4252, 0
7445 04:37:54.017350 112 : 4250, 0
7446 04:37:54.017448 116 : 4252, 0
7447 04:37:54.017552 120 : 4360, 0
7448 04:37:54.020790 124 : 4361, 0
7449 04:37:54.020860 128 : 4360, 0
7450 04:37:54.020962 132 : 4250, 0
7451 04:37:54.024286 136 : 4250, 0
7452 04:37:54.024384 140 : 4250, 0
7453 04:37:54.028240 144 : 4250, 0
7454 04:37:54.028340 148 : 4250, 0
7455 04:37:54.028440 152 : 4250, 0
7456 04:37:54.030815 156 : 4250, 0
7457 04:37:54.030921 160 : 4250, 0
7458 04:37:54.034192 164 : 4250, 0
7459 04:37:54.034299 168 : 4250, 0
7460 04:37:54.034390 172 : 4360, 0
7461 04:37:54.038018 176 : 4361, 0
7462 04:37:54.038127 180 : 4247, 0
7463 04:37:54.040970 184 : 4250, 0
7464 04:37:54.041070 188 : 4250, 0
7465 04:37:54.041159 192 : 4250, 0
7466 04:37:54.044176 196 : 4250, 0
7467 04:37:54.044275 200 : 4250, 0
7468 04:37:54.044378 204 : 4250, 0
7469 04:37:54.047650 208 : 4250, 0
7470 04:37:54.047747 212 : 4249, 66
7471 04:37:54.051475 216 : 4250, 3484
7472 04:37:54.051573 220 : 4360, 4137
7473 04:37:54.054490 224 : 4250, 4026
7474 04:37:54.054596 228 : 4250, 4027
7475 04:37:54.057475 232 : 4366, 4142
7476 04:37:54.057581 236 : 4250, 4026
7477 04:37:54.060678 240 : 4250, 4027
7478 04:37:54.060762 244 : 4250, 4027
7479 04:37:54.060823 248 : 4250, 4027
7480 04:37:54.064440 252 : 4250, 4026
7481 04:37:54.064537 256 : 4250, 4027
7482 04:37:54.067830 260 : 4360, 4138
7483 04:37:54.067928 264 : 4249, 4027
7484 04:37:54.070800 268 : 4250, 4026
7485 04:37:54.070908 272 : 4361, 4137
7486 04:37:54.074267 276 : 4250, 4027
7487 04:37:54.074376 280 : 4250, 4027
7488 04:37:54.077376 284 : 4360, 4137
7489 04:37:54.077472 288 : 4250, 4026
7490 04:37:54.080788 292 : 4250, 4027
7491 04:37:54.080858 296 : 4250, 4027
7492 04:37:54.084832 300 : 4250, 4027
7493 04:37:54.084934 304 : 4250, 4026
7494 04:37:54.085038 308 : 4250, 4027
7495 04:37:54.087957 312 : 4361, 4137
7496 04:37:54.088054 316 : 4250, 4027
7497 04:37:54.090945 320 : 4250, 4026
7498 04:37:54.091041 324 : 4363, 4140
7499 04:37:54.094408 328 : 4250, 4027
7500 04:37:54.094516 332 : 4250, 3016
7501 04:37:54.097517 336 : 4363, 73
7502 04:37:54.097615
7503 04:37:54.097709 MIOCK jitter meter ch=0
7504 04:37:54.097774
7505 04:37:54.101085 1T = (336-100) = 236 dly cells
7506 04:37:54.107559 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7507 04:37:54.107663 ==
7508 04:37:54.110868 Dram Type= 6, Freq= 0, CH_0, rank 0
7509 04:37:54.114364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7510 04:37:54.114473 ==
7511 04:37:54.121475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7512 04:37:54.124562 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7513 04:37:54.127784 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7514 04:37:54.134772 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7515 04:37:54.144044 [CA 0] Center 44 (14~75) winsize 62
7516 04:37:54.147554 [CA 1] Center 43 (13~74) winsize 62
7517 04:37:54.150891 [CA 2] Center 39 (10~68) winsize 59
7518 04:37:54.153912 [CA 3] Center 39 (10~68) winsize 59
7519 04:37:54.157904 [CA 4] Center 37 (7~67) winsize 61
7520 04:37:54.161354 [CA 5] Center 37 (7~67) winsize 61
7521 04:37:54.161451
7522 04:37:54.164063 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7523 04:37:54.164156
7524 04:37:54.167551 [CATrainingPosCal] consider 1 rank data
7525 04:37:54.170987 u2DelayCellTimex100 = 275/100 ps
7526 04:37:54.174565 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7527 04:37:54.181014 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7528 04:37:54.184266 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7529 04:37:54.187725 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7530 04:37:54.190610 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7531 04:37:54.194215 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7532 04:37:54.194321
7533 04:37:54.197529 CA PerBit enable=1, Macro0, CA PI delay=37
7534 04:37:54.197629
7535 04:37:54.200760 [CBTSetCACLKResult] CA Dly = 37
7536 04:37:54.203992 CS Dly: 11 (0~42)
7537 04:37:54.207286 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7538 04:37:54.210754 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7539 04:37:54.210856 ==
7540 04:37:54.213889 Dram Type= 6, Freq= 0, CH_0, rank 1
7541 04:37:54.217370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 04:37:54.220866 ==
7543 04:37:54.223887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7544 04:37:54.227149 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7545 04:37:54.233672 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7546 04:37:54.237182 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7547 04:37:54.247826 [CA 0] Center 44 (14~74) winsize 61
7548 04:37:54.251338 [CA 1] Center 44 (14~74) winsize 61
7549 04:37:54.254309 [CA 2] Center 40 (11~69) winsize 59
7550 04:37:54.257646 [CA 3] Center 39 (10~68) winsize 59
7551 04:37:54.261068 [CA 4] Center 38 (9~67) winsize 59
7552 04:37:54.264431 [CA 5] Center 37 (7~67) winsize 61
7553 04:37:54.264528
7554 04:37:54.267690 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7555 04:37:54.267797
7556 04:37:54.271214 [CATrainingPosCal] consider 2 rank data
7557 04:37:54.274531 u2DelayCellTimex100 = 275/100 ps
7558 04:37:54.277776 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7559 04:37:54.285068 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7560 04:37:54.287980 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7561 04:37:54.291441 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7562 04:37:54.294623 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7563 04:37:54.297892 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7564 04:37:54.297996
7565 04:37:54.301382 CA PerBit enable=1, Macro0, CA PI delay=37
7566 04:37:54.301478
7567 04:37:54.304627 [CBTSetCACLKResult] CA Dly = 37
7568 04:37:54.308173 CS Dly: 12 (0~44)
7569 04:37:54.311495 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7570 04:37:54.314423 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7571 04:37:54.314520
7572 04:37:54.318363 ----->DramcWriteLeveling(PI) begin...
7573 04:37:54.318459 ==
7574 04:37:54.321515 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 04:37:54.324933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 04:37:54.325029 ==
7577 04:37:54.328161 Write leveling (Byte 0): 30 => 30
7578 04:37:54.331643 Write leveling (Byte 1): 28 => 28
7579 04:37:54.334912 DramcWriteLeveling(PI) end<-----
7580 04:37:54.335071
7581 04:37:54.335169 ==
7582 04:37:54.338211 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 04:37:54.344513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 04:37:54.344617 ==
7585 04:37:54.344739 [Gating] SW mode calibration
7586 04:37:54.354797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7587 04:37:54.358371 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7588 04:37:54.361326 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 04:37:54.368603 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 04:37:54.371039 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 04:37:54.375075 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 04:37:54.381753 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7593 04:37:54.384891 1 4 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7594 04:37:54.388185 1 4 24 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
7595 04:37:54.394448 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 04:37:54.398393 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 04:37:54.401367 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 04:37:54.407900 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 04:37:54.411205 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 04:37:54.414604 1 5 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7601 04:37:54.421198 1 5 20 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
7602 04:37:54.424609 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7603 04:37:54.428143 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 04:37:54.434621 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 04:37:54.437771 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 04:37:54.441082 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 04:37:54.447987 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 04:37:54.450708 1 6 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7609 04:37:54.454090 1 6 20 | B1->B0 | 2323 4545 | 1 0 | (0 0) (0 0)
7610 04:37:54.461492 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7611 04:37:54.464193 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 04:37:54.467689 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 04:37:54.474298 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 04:37:54.477491 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 04:37:54.481064 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 04:37:54.484444 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 04:37:54.491515 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7618 04:37:54.494374 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7619 04:37:54.497865 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 04:37:54.504631 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 04:37:54.507973 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 04:37:54.511388 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 04:37:54.517931 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 04:37:54.521098 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 04:37:54.524606 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 04:37:54.531459 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 04:37:54.534792 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 04:37:54.537515 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 04:37:54.544607 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 04:37:54.547386 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 04:37:54.550758 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 04:37:54.557554 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 04:37:54.560932 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7634 04:37:54.564621 Total UI for P1: 0, mck2ui 16
7635 04:37:54.568039 best dqsien dly found for B0: ( 1, 9, 16)
7636 04:37:54.570736 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7637 04:37:54.574172 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 04:37:54.578177 Total UI for P1: 0, mck2ui 16
7639 04:37:54.580703 best dqsien dly found for B1: ( 1, 9, 22)
7640 04:37:54.584400 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7641 04:37:54.591003 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7642 04:37:54.591106
7643 04:37:54.594849 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7644 04:37:54.597532 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7645 04:37:54.600796 [Gating] SW calibration Done
7646 04:37:54.600886 ==
7647 04:37:54.604187 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 04:37:54.607656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 04:37:54.607758 ==
7650 04:37:54.607849 RX Vref Scan: 0
7651 04:37:54.611114
7652 04:37:54.611215 RX Vref 0 -> 0, step: 1
7653 04:37:54.611305
7654 04:37:54.614558 RX Delay 0 -> 252, step: 8
7655 04:37:54.617877 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7656 04:37:54.621096 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7657 04:37:54.628036 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7658 04:37:54.631362 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
7659 04:37:54.634459 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7660 04:37:54.637545 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7661 04:37:54.641508 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7662 04:37:54.644352 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7663 04:37:54.651288 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7664 04:37:54.654590 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7665 04:37:54.658047 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7666 04:37:54.661046 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7667 04:37:54.664625 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7668 04:37:54.671309 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7669 04:37:54.674871 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7670 04:37:54.678013 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7671 04:37:54.678110 ==
7672 04:37:54.681429 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 04:37:54.685009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 04:37:54.685110 ==
7675 04:37:54.687848 DQS Delay:
7676 04:37:54.687940 DQS0 = 0, DQS1 = 0
7677 04:37:54.691240 DQM Delay:
7678 04:37:54.691332 DQM0 = 132, DQM1 = 125
7679 04:37:54.694589 DQ Delay:
7680 04:37:54.697893 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7681 04:37:54.701406 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7682 04:37:54.705034 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7683 04:37:54.708415 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7684 04:37:54.708518
7685 04:37:54.708611
7686 04:37:54.708733 ==
7687 04:37:54.711332 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 04:37:54.714681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 04:37:54.714778 ==
7690 04:37:54.714867
7691 04:37:54.714965
7692 04:37:54.717915 TX Vref Scan disable
7693 04:37:54.721293 == TX Byte 0 ==
7694 04:37:54.724787 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7695 04:37:54.728065 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7696 04:37:54.731277 == TX Byte 1 ==
7697 04:37:54.735131 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7698 04:37:54.737840 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7699 04:37:54.737912 ==
7700 04:37:54.741463 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 04:37:54.744582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 04:37:54.748027 ==
7703 04:37:54.759360
7704 04:37:54.762755 TX Vref early break, caculate TX vref
7705 04:37:54.766141 TX Vref=16, minBit 1, minWin=20, winSum=358
7706 04:37:54.769127 TX Vref=18, minBit 4, minWin=21, winSum=368
7707 04:37:54.772718 TX Vref=20, minBit 1, minWin=21, winSum=378
7708 04:37:54.775897 TX Vref=22, minBit 1, minWin=22, winSum=385
7709 04:37:54.779298 TX Vref=24, minBit 7, minWin=23, winSum=398
7710 04:37:54.786184 TX Vref=26, minBit 7, minWin=22, winSum=408
7711 04:37:54.789443 TX Vref=28, minBit 1, minWin=25, winSum=418
7712 04:37:54.792437 TX Vref=30, minBit 1, minWin=25, winSum=423
7713 04:37:54.796084 TX Vref=32, minBit 0, minWin=24, winSum=405
7714 04:37:54.799330 TX Vref=34, minBit 0, minWin=24, winSum=397
7715 04:37:54.806373 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 30
7716 04:37:54.806449
7717 04:37:54.809441 Final TX Range 0 Vref 30
7718 04:37:54.809513
7719 04:37:54.809574 ==
7720 04:37:54.813015 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 04:37:54.816366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 04:37:54.816479 ==
7723 04:37:54.816573
7724 04:37:54.816687
7725 04:37:54.819291 TX Vref Scan disable
7726 04:37:54.822603 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7727 04:37:54.826182 == TX Byte 0 ==
7728 04:37:54.829484 u2DelayCellOfst[0]=14 cells (4 PI)
7729 04:37:54.833238 u2DelayCellOfst[1]=21 cells (6 PI)
7730 04:37:54.835954 u2DelayCellOfst[2]=10 cells (3 PI)
7731 04:37:54.839501 u2DelayCellOfst[3]=14 cells (4 PI)
7732 04:37:54.842980 u2DelayCellOfst[4]=10 cells (3 PI)
7733 04:37:54.843060 u2DelayCellOfst[5]=0 cells (0 PI)
7734 04:37:54.846421 u2DelayCellOfst[6]=21 cells (6 PI)
7735 04:37:54.849677 u2DelayCellOfst[7]=21 cells (6 PI)
7736 04:37:54.856041 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7737 04:37:54.859697 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7738 04:37:54.859794 == TX Byte 1 ==
7739 04:37:54.862928 u2DelayCellOfst[8]=3 cells (1 PI)
7740 04:37:54.866126 u2DelayCellOfst[9]=0 cells (0 PI)
7741 04:37:54.869495 u2DelayCellOfst[10]=7 cells (2 PI)
7742 04:37:54.873018 u2DelayCellOfst[11]=3 cells (1 PI)
7743 04:37:54.876071 u2DelayCellOfst[12]=14 cells (4 PI)
7744 04:37:54.879425 u2DelayCellOfst[13]=14 cells (4 PI)
7745 04:37:54.882613 u2DelayCellOfst[14]=17 cells (5 PI)
7746 04:37:54.885942 u2DelayCellOfst[15]=14 cells (4 PI)
7747 04:37:54.889434 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7748 04:37:54.892812 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7749 04:37:54.896131 DramC Write-DBI on
7750 04:37:54.896216 ==
7751 04:37:54.899504 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 04:37:54.903098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 04:37:54.903196 ==
7754 04:37:54.903293
7755 04:37:54.903369
7756 04:37:54.906075 TX Vref Scan disable
7757 04:37:54.909685 == TX Byte 0 ==
7758 04:37:54.912741 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7759 04:37:54.912822 == TX Byte 1 ==
7760 04:37:54.919750 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7761 04:37:54.919830 DramC Write-DBI off
7762 04:37:54.919894
7763 04:37:54.923039 [DATLAT]
7764 04:37:54.923118 Freq=1600, CH0 RK0
7765 04:37:54.923182
7766 04:37:54.926340 DATLAT Default: 0xf
7767 04:37:54.926420 0, 0xFFFF, sum = 0
7768 04:37:54.929647 1, 0xFFFF, sum = 0
7769 04:37:54.929735 2, 0xFFFF, sum = 0
7770 04:37:54.933031 3, 0xFFFF, sum = 0
7771 04:37:54.933112 4, 0xFFFF, sum = 0
7772 04:37:54.936484 5, 0xFFFF, sum = 0
7773 04:37:54.936565 6, 0xFFFF, sum = 0
7774 04:37:54.939767 7, 0xFFFF, sum = 0
7775 04:37:54.939869 8, 0xFFFF, sum = 0
7776 04:37:54.943185 9, 0xFFFF, sum = 0
7777 04:37:54.943297 10, 0xFFFF, sum = 0
7778 04:37:54.946201 11, 0xFFFF, sum = 0
7779 04:37:54.946282 12, 0xFFFF, sum = 0
7780 04:37:54.949624 13, 0xFFFF, sum = 0
7781 04:37:54.949695 14, 0x0, sum = 1
7782 04:37:54.952711 15, 0x0, sum = 2
7783 04:37:54.952805 16, 0x0, sum = 3
7784 04:37:54.955989 17, 0x0, sum = 4
7785 04:37:54.956061 best_step = 15
7786 04:37:54.956121
7787 04:37:54.956177 ==
7788 04:37:54.959669 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 04:37:54.966142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 04:37:54.966223 ==
7791 04:37:54.966287 RX Vref Scan: 1
7792 04:37:54.966347
7793 04:37:54.969467 Set Vref Range= 24 -> 127
7794 04:37:54.969547
7795 04:37:54.972856 RX Vref 24 -> 127, step: 1
7796 04:37:54.972942
7797 04:37:54.976419 RX Delay 11 -> 252, step: 4
7798 04:37:54.976558
7799 04:37:54.976657 Set Vref, RX VrefLevel [Byte0]: 24
7800 04:37:54.979697 [Byte1]: 24
7801 04:37:54.984152
7802 04:37:54.984328 Set Vref, RX VrefLevel [Byte0]: 25
7803 04:37:54.987490 [Byte1]: 25
7804 04:37:54.991394
7805 04:37:54.991595 Set Vref, RX VrefLevel [Byte0]: 26
7806 04:37:54.994997 [Byte1]: 26
7807 04:37:54.999896
7808 04:37:55.000028 Set Vref, RX VrefLevel [Byte0]: 27
7809 04:37:55.002282 [Byte1]: 27
7810 04:37:55.006855
7811 04:37:55.006935 Set Vref, RX VrefLevel [Byte0]: 28
7812 04:37:55.010124 [Byte1]: 28
7813 04:37:55.014538
7814 04:37:55.014617 Set Vref, RX VrefLevel [Byte0]: 29
7815 04:37:55.017806 [Byte1]: 29
7816 04:37:55.021956
7817 04:37:55.022064 Set Vref, RX VrefLevel [Byte0]: 30
7818 04:37:55.025431 [Byte1]: 30
7819 04:37:55.030143
7820 04:37:55.030242 Set Vref, RX VrefLevel [Byte0]: 31
7821 04:37:55.032964 [Byte1]: 31
7822 04:37:55.037480
7823 04:37:55.037632 Set Vref, RX VrefLevel [Byte0]: 32
7824 04:37:55.040533 [Byte1]: 32
7825 04:37:55.044609
7826 04:37:55.044744 Set Vref, RX VrefLevel [Byte0]: 33
7827 04:37:55.048160 [Byte1]: 33
7828 04:37:55.053394
7829 04:37:55.053843 Set Vref, RX VrefLevel [Byte0]: 34
7830 04:37:55.056003 [Byte1]: 34
7831 04:37:55.060436
7832 04:37:55.060978 Set Vref, RX VrefLevel [Byte0]: 35
7833 04:37:55.063975 [Byte1]: 35
7834 04:37:55.067978
7835 04:37:55.068419 Set Vref, RX VrefLevel [Byte0]: 36
7836 04:37:55.071495 [Byte1]: 36
7837 04:37:55.075515
7838 04:37:55.075924 Set Vref, RX VrefLevel [Byte0]: 37
7839 04:37:55.078743 [Byte1]: 37
7840 04:37:55.082828
7841 04:37:55.082907 Set Vref, RX VrefLevel [Byte0]: 38
7842 04:37:55.086584 [Byte1]: 38
7843 04:37:55.090334
7844 04:37:55.090414 Set Vref, RX VrefLevel [Byte0]: 39
7845 04:37:55.094236 [Byte1]: 39
7846 04:37:55.098238
7847 04:37:55.098344 Set Vref, RX VrefLevel [Byte0]: 40
7848 04:37:55.101372 [Byte1]: 40
7849 04:37:55.105349
7850 04:37:55.105425 Set Vref, RX VrefLevel [Byte0]: 41
7851 04:37:55.108992 [Byte1]: 41
7852 04:37:55.113247
7853 04:37:55.113326 Set Vref, RX VrefLevel [Byte0]: 42
7854 04:37:55.116557 [Byte1]: 42
7855 04:37:55.121050
7856 04:37:55.121129 Set Vref, RX VrefLevel [Byte0]: 43
7857 04:37:55.124622 [Byte1]: 43
7858 04:37:55.128593
7859 04:37:55.128724 Set Vref, RX VrefLevel [Byte0]: 44
7860 04:37:55.131901 [Byte1]: 44
7861 04:37:55.136022
7862 04:37:55.136102 Set Vref, RX VrefLevel [Byte0]: 45
7863 04:37:55.139848 [Byte1]: 45
7864 04:37:55.144018
7865 04:37:55.144102 Set Vref, RX VrefLevel [Byte0]: 46
7866 04:37:55.150395 [Byte1]: 46
7867 04:37:55.150494
7868 04:37:55.153345 Set Vref, RX VrefLevel [Byte0]: 47
7869 04:37:55.157222 [Byte1]: 47
7870 04:37:55.157302
7871 04:37:55.160985 Set Vref, RX VrefLevel [Byte0]: 48
7872 04:37:55.163668 [Byte1]: 48
7873 04:37:55.163764
7874 04:37:55.167016 Set Vref, RX VrefLevel [Byte0]: 49
7875 04:37:55.170124 [Byte1]: 49
7876 04:37:55.174343
7877 04:37:55.174423 Set Vref, RX VrefLevel [Byte0]: 50
7878 04:37:55.177913 [Byte1]: 50
7879 04:37:55.182027
7880 04:37:55.182107 Set Vref, RX VrefLevel [Byte0]: 51
7881 04:37:55.185363 [Byte1]: 51
7882 04:37:55.189604
7883 04:37:55.189683 Set Vref, RX VrefLevel [Byte0]: 52
7884 04:37:55.192719 [Byte1]: 52
7885 04:37:55.197366
7886 04:37:55.197445 Set Vref, RX VrefLevel [Byte0]: 53
7887 04:37:55.200158 [Byte1]: 53
7888 04:37:55.204965
7889 04:37:55.205046 Set Vref, RX VrefLevel [Byte0]: 54
7890 04:37:55.207982 [Byte1]: 54
7891 04:37:55.212241
7892 04:37:55.212322 Set Vref, RX VrefLevel [Byte0]: 55
7893 04:37:55.215701 [Byte1]: 55
7894 04:37:55.219682
7895 04:37:55.219762 Set Vref, RX VrefLevel [Byte0]: 56
7896 04:37:55.223520 [Byte1]: 56
7897 04:37:55.227629
7898 04:37:55.227708 Set Vref, RX VrefLevel [Byte0]: 57
7899 04:37:55.230537 [Byte1]: 57
7900 04:37:55.234816
7901 04:37:55.234895 Set Vref, RX VrefLevel [Byte0]: 58
7902 04:37:55.238276 [Byte1]: 58
7903 04:37:55.243232
7904 04:37:55.243311 Set Vref, RX VrefLevel [Byte0]: 59
7905 04:37:55.249027 [Byte1]: 59
7906 04:37:55.249108
7907 04:37:55.252415 Set Vref, RX VrefLevel [Byte0]: 60
7908 04:37:55.255608 [Byte1]: 60
7909 04:37:55.255689
7910 04:37:55.259510 Set Vref, RX VrefLevel [Byte0]: 61
7911 04:37:55.262344 [Byte1]: 61
7912 04:37:55.262424
7913 04:37:55.265707 Set Vref, RX VrefLevel [Byte0]: 62
7914 04:37:55.268844 [Byte1]: 62
7915 04:37:55.273303
7916 04:37:55.273385 Set Vref, RX VrefLevel [Byte0]: 63
7917 04:37:55.276111 [Byte1]: 63
7918 04:37:55.280566
7919 04:37:55.280645 Set Vref, RX VrefLevel [Byte0]: 64
7920 04:37:55.283833 [Byte1]: 64
7921 04:37:55.288830
7922 04:37:55.288906 Set Vref, RX VrefLevel [Byte0]: 65
7923 04:37:55.291627 [Byte1]: 65
7924 04:37:55.295918
7925 04:37:55.295994 Set Vref, RX VrefLevel [Byte0]: 66
7926 04:37:55.299240 [Byte1]: 66
7927 04:37:55.303710
7928 04:37:55.303780 Set Vref, RX VrefLevel [Byte0]: 67
7929 04:37:55.307087 [Byte1]: 67
7930 04:37:55.311299
7931 04:37:55.311379 Set Vref, RX VrefLevel [Byte0]: 68
7932 04:37:55.314513 [Byte1]: 68
7933 04:37:55.318661
7934 04:37:55.318745 Set Vref, RX VrefLevel [Byte0]: 69
7935 04:37:55.321804 [Byte1]: 69
7936 04:37:55.326756
7937 04:37:55.326863 Set Vref, RX VrefLevel [Byte0]: 70
7938 04:37:55.330044 [Byte1]: 70
7939 04:37:55.334359
7940 04:37:55.334439 Set Vref, RX VrefLevel [Byte0]: 71
7941 04:37:55.337746 [Byte1]: 71
7942 04:37:55.341611
7943 04:37:55.341690 Set Vref, RX VrefLevel [Byte0]: 72
7944 04:37:55.345323 [Byte1]: 72
7945 04:37:55.349476
7946 04:37:55.349556 Set Vref, RX VrefLevel [Byte0]: 73
7947 04:37:55.352344 [Byte1]: 73
7948 04:37:55.356943
7949 04:37:55.357023 Set Vref, RX VrefLevel [Byte0]: 74
7950 04:37:55.359901 [Byte1]: 74
7951 04:37:55.364506
7952 04:37:55.364585 Set Vref, RX VrefLevel [Byte0]: 75
7953 04:37:55.368145 [Byte1]: 75
7954 04:37:55.372075
7955 04:37:55.372154 Set Vref, RX VrefLevel [Byte0]: 76
7956 04:37:55.375418 [Byte1]: 76
7957 04:37:55.379686
7958 04:37:55.379766 Final RX Vref Byte 0 = 61 to rank0
7959 04:37:55.383365 Final RX Vref Byte 1 = 63 to rank0
7960 04:37:55.386537 Final RX Vref Byte 0 = 61 to rank1
7961 04:37:55.389920 Final RX Vref Byte 1 = 63 to rank1==
7962 04:37:55.393272 Dram Type= 6, Freq= 0, CH_0, rank 0
7963 04:37:55.396492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7964 04:37:55.400032 ==
7965 04:37:55.400112 DQS Delay:
7966 04:37:55.400176 DQS0 = 0, DQS1 = 0
7967 04:37:55.402938 DQM Delay:
7968 04:37:55.403018 DQM0 = 129, DQM1 = 122
7969 04:37:55.406303 DQ Delay:
7970 04:37:55.409900 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7971 04:37:55.413059 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7972 04:37:55.416568 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7973 04:37:55.420133 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =132
7974 04:37:55.420218
7975 04:37:55.420280
7976 04:37:55.420339
7977 04:37:55.423248 [DramC_TX_OE_Calibration] TA2
7978 04:37:55.426448 Original DQ_B0 (3 6) =30, OEN = 27
7979 04:37:55.429630 Original DQ_B1 (3 6) =30, OEN = 27
7980 04:37:55.433377 24, 0x0, End_B0=24 End_B1=24
7981 04:37:55.433459 25, 0x0, End_B0=25 End_B1=25
7982 04:37:55.436439 26, 0x0, End_B0=26 End_B1=26
7983 04:37:55.439615 27, 0x0, End_B0=27 End_B1=27
7984 04:37:55.443412 28, 0x0, End_B0=28 End_B1=28
7985 04:37:55.443495 29, 0x0, End_B0=29 End_B1=29
7986 04:37:55.446413 30, 0x0, End_B0=30 End_B1=30
7987 04:37:55.450066 31, 0x4141, End_B0=30 End_B1=30
7988 04:37:55.453465 Byte0 end_step=30 best_step=27
7989 04:37:55.456595 Byte1 end_step=30 best_step=27
7990 04:37:55.460619 Byte0 TX OE(2T, 0.5T) = (3, 3)
7991 04:37:55.460724 Byte1 TX OE(2T, 0.5T) = (3, 3)
7992 04:37:55.460790
7993 04:37:55.460849
7994 04:37:55.470118 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7995 04:37:55.473505 CH0 RK0: MR19=303, MR18=1509
7996 04:37:55.476827 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7997 04:37:55.479975
7998 04:37:55.483212 ----->DramcWriteLeveling(PI) begin...
7999 04:37:55.483294 ==
8000 04:37:55.486828 Dram Type= 6, Freq= 0, CH_0, rank 1
8001 04:37:55.490197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 04:37:55.490278 ==
8003 04:37:55.493201 Write leveling (Byte 0): 34 => 34
8004 04:37:55.496694 Write leveling (Byte 1): 26 => 26
8005 04:37:55.500074 DramcWriteLeveling(PI) end<-----
8006 04:37:55.500154
8007 04:37:55.500217 ==
8008 04:37:55.503236 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 04:37:55.506951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 04:37:55.507031 ==
8011 04:37:55.510055 [Gating] SW mode calibration
8012 04:37:55.516875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8013 04:37:55.523377 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8014 04:37:55.526536 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 04:37:55.529755 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 04:37:55.536685 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8017 04:37:55.540182 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8018 04:37:55.543333 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8019 04:37:55.546939 1 4 20 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
8020 04:37:55.553707 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 04:37:55.556531 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 04:37:55.560164 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 04:37:55.566493 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 04:37:55.570129 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8025 04:37:55.573691 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8026 04:37:55.580368 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8027 04:37:55.583680 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8028 04:37:55.586620 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8029 04:37:55.593592 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 04:37:55.597238 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 04:37:55.600154 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 04:37:55.607034 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8033 04:37:55.610675 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8034 04:37:55.613924 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8035 04:37:55.620457 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8036 04:37:55.623844 1 6 24 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8037 04:37:55.627044 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 04:37:55.630488 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 04:37:55.637404 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 04:37:55.640463 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8041 04:37:55.643918 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8042 04:37:55.650381 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8043 04:37:55.654672 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 04:37:55.657392 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 04:37:55.664137 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 04:37:55.667036 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 04:37:55.670568 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 04:37:55.677382 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 04:37:55.680638 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 04:37:55.683766 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 04:37:55.690442 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 04:37:55.693735 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 04:37:55.697335 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 04:37:55.704051 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 04:37:55.707534 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 04:37:55.710794 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8057 04:37:55.713758 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8058 04:37:55.720939 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 04:37:55.723977 Total UI for P1: 0, mck2ui 16
8060 04:37:55.727302 best dqsien dly found for B0: ( 1, 9, 10)
8061 04:37:55.730785 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8062 04:37:55.733695 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 04:37:55.737209 Total UI for P1: 0, mck2ui 16
8064 04:37:55.740938 best dqsien dly found for B1: ( 1, 9, 18)
8065 04:37:55.743706 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8066 04:37:55.747347 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8067 04:37:55.747759
8068 04:37:55.754128 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8069 04:37:55.757185 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8070 04:37:55.761038 [Gating] SW calibration Done
8071 04:37:55.761466 ==
8072 04:37:55.764172 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 04:37:55.767710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 04:37:55.768128 ==
8075 04:37:55.768457 RX Vref Scan: 0
8076 04:37:55.768801
8077 04:37:55.770541 RX Vref 0 -> 0, step: 1
8078 04:37:55.770951
8079 04:37:55.774047 RX Delay 0 -> 252, step: 8
8080 04:37:55.777550 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8081 04:37:55.781232 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8082 04:37:55.784173 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8083 04:37:55.791018 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8084 04:37:55.794419 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8085 04:37:55.797688 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8086 04:37:55.800745 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8087 04:37:55.804431 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8088 04:37:55.811151 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8089 04:37:55.814292 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8090 04:37:55.817484 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8091 04:37:55.821268 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8092 04:37:55.824097 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8093 04:37:55.831010 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8094 04:37:55.834005 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8095 04:37:55.837281 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8096 04:37:55.837698 ==
8097 04:37:55.840861 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 04:37:55.844561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 04:37:55.845028 ==
8100 04:37:55.847946 DQS Delay:
8101 04:37:55.848485 DQS0 = 0, DQS1 = 0
8102 04:37:55.851132 DQM Delay:
8103 04:37:55.852073 DQM0 = 131, DQM1 = 124
8104 04:37:55.852651 DQ Delay:
8105 04:37:55.857493 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8106 04:37:55.861131 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8107 04:37:55.864996 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8108 04:37:55.867453 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8109 04:37:55.867866
8110 04:37:55.868193
8111 04:37:55.868492 ==
8112 04:37:55.870870 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 04:37:55.874115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 04:37:55.874534 ==
8115 04:37:55.874865
8116 04:37:55.875299
8117 04:37:55.877572 TX Vref Scan disable
8118 04:37:55.881196 == TX Byte 0 ==
8119 04:37:55.884216 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8120 04:37:55.887683 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8121 04:37:55.891169 == TX Byte 1 ==
8122 04:37:55.894342 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8123 04:37:55.897454 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8124 04:37:55.897904 ==
8125 04:37:55.900784 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 04:37:55.904360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 04:37:55.904905 ==
8128 04:37:55.920803
8129 04:37:55.923822 TX Vref early break, caculate TX vref
8130 04:37:55.927127 TX Vref=16, minBit 5, minWin=22, winSum=369
8131 04:37:55.930689 TX Vref=18, minBit 9, minWin=22, winSum=379
8132 04:37:55.934002 TX Vref=20, minBit 4, minWin=23, winSum=388
8133 04:37:55.937745 TX Vref=22, minBit 2, minWin=23, winSum=396
8134 04:37:55.940890 TX Vref=24, minBit 3, minWin=24, winSum=403
8135 04:37:55.947283 TX Vref=26, minBit 0, minWin=25, winSum=411
8136 04:37:55.950326 TX Vref=28, minBit 0, minWin=25, winSum=416
8137 04:37:55.953973 TX Vref=30, minBit 0, minWin=25, winSum=417
8138 04:37:55.957163 TX Vref=32, minBit 2, minWin=24, winSum=408
8139 04:37:55.960735 TX Vref=34, minBit 0, minWin=24, winSum=398
8140 04:37:55.963964 TX Vref=36, minBit 4, minWin=23, winSum=389
8141 04:37:55.970916 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 30
8142 04:37:55.971331
8143 04:37:55.974366 Final TX Range 0 Vref 30
8144 04:37:55.974857
8145 04:37:55.975191 ==
8146 04:37:55.977295 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 04:37:55.980799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 04:37:55.981216 ==
8149 04:37:55.981631
8150 04:37:55.981952
8151 04:37:55.984452 TX Vref Scan disable
8152 04:37:55.990971 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8153 04:37:55.991383 == TX Byte 0 ==
8154 04:37:55.993972 u2DelayCellOfst[0]=14 cells (4 PI)
8155 04:37:55.997479 u2DelayCellOfst[1]=17 cells (5 PI)
8156 04:37:56.000773 u2DelayCellOfst[2]=10 cells (3 PI)
8157 04:37:56.003963 u2DelayCellOfst[3]=10 cells (3 PI)
8158 04:37:56.007135 u2DelayCellOfst[4]=10 cells (3 PI)
8159 04:37:56.010480 u2DelayCellOfst[5]=0 cells (0 PI)
8160 04:37:56.014010 u2DelayCellOfst[6]=17 cells (5 PI)
8161 04:37:56.017265 u2DelayCellOfst[7]=17 cells (5 PI)
8162 04:37:56.020575 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8163 04:37:56.023727 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8164 04:37:56.027414 == TX Byte 1 ==
8165 04:37:56.027870 u2DelayCellOfst[8]=0 cells (0 PI)
8166 04:37:56.030484 u2DelayCellOfst[9]=0 cells (0 PI)
8167 04:37:56.034018 u2DelayCellOfst[10]=3 cells (1 PI)
8168 04:37:56.037496 u2DelayCellOfst[11]=0 cells (0 PI)
8169 04:37:56.040833 u2DelayCellOfst[12]=10 cells (3 PI)
8170 04:37:56.044467 u2DelayCellOfst[13]=10 cells (3 PI)
8171 04:37:56.047168 u2DelayCellOfst[14]=14 cells (4 PI)
8172 04:37:56.050534 u2DelayCellOfst[15]=10 cells (3 PI)
8173 04:37:56.054055 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8174 04:37:56.060381 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8175 04:37:56.060833 DramC Write-DBI on
8176 04:37:56.061170 ==
8177 04:37:56.063948 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 04:37:56.067446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 04:37:56.070919 ==
8180 04:37:56.071329
8181 04:37:56.071668
8182 04:37:56.072027 TX Vref Scan disable
8183 04:37:56.074148 == TX Byte 0 ==
8184 04:37:56.077247 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8185 04:37:56.080604 == TX Byte 1 ==
8186 04:37:56.083832 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8187 04:37:56.087507 DramC Write-DBI off
8188 04:37:56.087912
8189 04:37:56.088236 [DATLAT]
8190 04:37:56.088542 Freq=1600, CH0 RK1
8191 04:37:56.088903
8192 04:37:56.090790 DATLAT Default: 0xf
8193 04:37:56.091197 0, 0xFFFF, sum = 0
8194 04:37:56.093975 1, 0xFFFF, sum = 0
8195 04:37:56.094390 2, 0xFFFF, sum = 0
8196 04:37:56.097701 3, 0xFFFF, sum = 0
8197 04:37:56.098117 4, 0xFFFF, sum = 0
8198 04:37:56.100566 5, 0xFFFF, sum = 0
8199 04:37:56.104067 6, 0xFFFF, sum = 0
8200 04:37:56.104481 7, 0xFFFF, sum = 0
8201 04:37:56.107406 8, 0xFFFF, sum = 0
8202 04:37:56.107817 9, 0xFFFF, sum = 0
8203 04:37:56.110893 10, 0xFFFF, sum = 0
8204 04:37:56.111358 11, 0xFFFF, sum = 0
8205 04:37:56.114324 12, 0xFFFF, sum = 0
8206 04:37:56.115006 13, 0xFFFF, sum = 0
8207 04:37:56.117315 14, 0x0, sum = 1
8208 04:37:56.117740 15, 0x0, sum = 2
8209 04:37:56.120589 16, 0x0, sum = 3
8210 04:37:56.121034 17, 0x0, sum = 4
8211 04:37:56.124371 best_step = 15
8212 04:37:56.124923
8213 04:37:56.125266 ==
8214 04:37:56.127479 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 04:37:56.131125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 04:37:56.131545 ==
8217 04:37:56.131881 RX Vref Scan: 0
8218 04:37:56.132194
8219 04:37:56.134525 RX Vref 0 -> 0, step: 1
8220 04:37:56.135049
8221 04:37:56.137902 RX Delay 11 -> 252, step: 4
8222 04:37:56.141225 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8223 04:37:56.147786 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8224 04:37:56.151096 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8225 04:37:56.154197 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8226 04:37:56.158003 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8227 04:37:56.160924 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8228 04:37:56.164431 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8229 04:37:56.170804 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8230 04:37:56.174247 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8231 04:37:56.177570 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8232 04:37:56.180915 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8233 04:37:56.184480 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8234 04:37:56.190798 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8235 04:37:56.194849 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8236 04:37:56.197679 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8237 04:37:56.201384 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8238 04:37:56.201795 ==
8239 04:37:56.204386 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 04:37:56.211137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 04:37:56.211550 ==
8242 04:37:56.211873 DQS Delay:
8243 04:37:56.214078 DQS0 = 0, DQS1 = 0
8244 04:37:56.214555 DQM Delay:
8245 04:37:56.214891 DQM0 = 127, DQM1 = 122
8246 04:37:56.217683 DQ Delay:
8247 04:37:56.221106 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8248 04:37:56.224053 DQ4 =126, DQ5 =116, DQ6 =138, DQ7 =134
8249 04:37:56.227333 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8250 04:37:56.230873 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8251 04:37:56.231462
8252 04:37:56.231942
8253 04:37:56.232461
8254 04:37:56.234334 [DramC_TX_OE_Calibration] TA2
8255 04:37:56.237635 Original DQ_B0 (3 6) =30, OEN = 27
8256 04:37:56.240897 Original DQ_B1 (3 6) =30, OEN = 27
8257 04:37:56.244580 24, 0x0, End_B0=24 End_B1=24
8258 04:37:56.245025 25, 0x0, End_B0=25 End_B1=25
8259 04:37:56.247780 26, 0x0, End_B0=26 End_B1=26
8260 04:37:56.250782 27, 0x0, End_B0=27 End_B1=27
8261 04:37:56.254196 28, 0x0, End_B0=28 End_B1=28
8262 04:37:56.254620 29, 0x0, End_B0=29 End_B1=29
8263 04:37:56.257508 30, 0x0, End_B0=30 End_B1=30
8264 04:37:56.260806 31, 0x4141, End_B0=30 End_B1=30
8265 04:37:56.264546 Byte0 end_step=30 best_step=27
8266 04:37:56.267755 Byte1 end_step=30 best_step=27
8267 04:37:56.271217 Byte0 TX OE(2T, 0.5T) = (3, 3)
8268 04:37:56.271634 Byte1 TX OE(2T, 0.5T) = (3, 3)
8269 04:37:56.274482
8270 04:37:56.275124
8271 04:37:56.281012 [DQSOSCAuto] RK1, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8272 04:37:56.284926 CH0 RK1: MR19=303, MR18=160B
8273 04:37:56.290684 CH0_RK1: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8274 04:37:56.294510 [RxdqsGatingPostProcess] freq 1600
8275 04:37:56.297800 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8276 04:37:56.300801 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 04:37:56.304110 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 04:37:56.307532 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 04:37:56.311279 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 04:37:56.314485 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 04:37:56.317772 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 04:37:56.320783 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 04:37:56.323958 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 04:37:56.324032 Pre-setting of DQS Precalculation
8285 04:37:56.330803 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8286 04:37:56.330878 ==
8287 04:37:56.334166 Dram Type= 6, Freq= 0, CH_1, rank 0
8288 04:37:56.337610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 04:37:56.337708 ==
8290 04:37:56.344396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8291 04:37:56.347598 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8292 04:37:56.350777 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8293 04:37:56.357867 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8294 04:37:56.366703 [CA 0] Center 43 (14~72) winsize 59
8295 04:37:56.370155 [CA 1] Center 43 (14~72) winsize 59
8296 04:37:56.373589 [CA 2] Center 38 (10~67) winsize 58
8297 04:37:56.376913 [CA 3] Center 37 (8~66) winsize 59
8298 04:37:56.380375 [CA 4] Center 38 (8~68) winsize 61
8299 04:37:56.383846 [CA 5] Center 37 (8~66) winsize 59
8300 04:37:56.383928
8301 04:37:56.387144 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8302 04:37:56.387251
8303 04:37:56.390647 [CATrainingPosCal] consider 1 rank data
8304 04:37:56.393586 u2DelayCellTimex100 = 275/100 ps
8305 04:37:56.397007 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8306 04:37:56.403649 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8307 04:37:56.407253 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8308 04:37:56.410831 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8309 04:37:56.413692 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8310 04:37:56.417268 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8311 04:37:56.417341
8312 04:37:56.420347 CA PerBit enable=1, Macro0, CA PI delay=37
8313 04:37:56.420443
8314 04:37:56.423826 [CBTSetCACLKResult] CA Dly = 37
8315 04:37:56.423926 CS Dly: 8 (0~39)
8316 04:37:56.430224 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8317 04:37:56.433853 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8318 04:37:56.433951 ==
8319 04:37:56.436998 Dram Type= 6, Freq= 0, CH_1, rank 1
8320 04:37:56.440480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 04:37:56.440579 ==
8322 04:37:56.447217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 04:37:56.450639 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 04:37:56.453806 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 04:37:56.460559 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 04:37:56.470283 [CA 0] Center 42 (13~72) winsize 60
8327 04:37:56.474084 [CA 1] Center 43 (14~72) winsize 59
8328 04:37:56.476996 [CA 2] Center 37 (8~67) winsize 60
8329 04:37:56.480131 [CA 3] Center 36 (7~66) winsize 60
8330 04:37:56.483527 [CA 4] Center 38 (9~67) winsize 59
8331 04:37:56.486764 [CA 5] Center 36 (7~66) winsize 60
8332 04:37:56.486859
8333 04:37:56.490441 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8334 04:37:56.490542
8335 04:37:56.494129 [CATrainingPosCal] consider 2 rank data
8336 04:37:56.496816 u2DelayCellTimex100 = 275/100 ps
8337 04:37:56.500369 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8338 04:37:56.506762 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8339 04:37:56.509906 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8340 04:37:56.513644 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8341 04:37:56.516847 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8342 04:37:56.520375 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8343 04:37:56.520476
8344 04:37:56.523801 CA PerBit enable=1, Macro0, CA PI delay=37
8345 04:37:56.523880
8346 04:37:56.526675 [CBTSetCACLKResult] CA Dly = 37
8347 04:37:56.530264 CS Dly: 10 (0~44)
8348 04:37:56.533865 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 04:37:56.537266 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 04:37:56.537363
8351 04:37:56.540231 ----->DramcWriteLeveling(PI) begin...
8352 04:37:56.540329 ==
8353 04:37:56.544120 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 04:37:56.546886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 04:37:56.546986 ==
8356 04:37:56.550280 Write leveling (Byte 0): 25 => 25
8357 04:37:56.553918 Write leveling (Byte 1): 27 => 27
8358 04:37:56.557269 DramcWriteLeveling(PI) end<-----
8359 04:37:56.557343
8360 04:37:56.557406 ==
8361 04:37:56.560327 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 04:37:56.564218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 04:37:56.567199 ==
8364 04:37:56.567272 [Gating] SW mode calibration
8365 04:37:56.577114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8366 04:37:56.580596 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8367 04:37:56.583839 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 04:37:56.590628 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 04:37:56.594025 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 04:37:56.597097 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 04:37:56.603861 1 4 16 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
8372 04:37:56.607119 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 04:37:56.610529 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 04:37:56.616907 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 04:37:56.620343 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 04:37:56.623992 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 04:37:56.630232 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 04:37:56.633583 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8379 04:37:56.637605 1 5 16 | B1->B0 | 2a2a 3434 | 0 0 | (0 1) (0 1)
8380 04:37:56.644063 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8381 04:37:56.646958 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 04:37:56.650929 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 04:37:56.657486 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 04:37:56.660349 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 04:37:56.664290 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 04:37:56.667517 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8387 04:37:56.673855 1 6 16 | B1->B0 | 4343 3535 | 0 1 | (0 0) (0 0)
8388 04:37:56.677430 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 04:37:56.680322 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 04:37:56.687226 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 04:37:56.690552 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 04:37:56.693824 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 04:37:56.700508 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 04:37:56.703896 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8395 04:37:56.707548 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 04:37:56.714547 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8397 04:37:56.717679 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 04:37:56.721045 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 04:37:56.724451 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 04:37:56.731006 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 04:37:56.734344 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 04:37:56.737729 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 04:37:56.744596 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 04:37:56.747628 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 04:37:56.750940 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 04:37:56.757477 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 04:37:56.760786 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 04:37:56.763936 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 04:37:56.771024 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 04:37:56.774270 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 04:37:56.777459 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 04:37:56.785092 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 04:37:56.785174 Total UI for P1: 0, mck2ui 16
8414 04:37:56.790818 best dqsien dly found for B0: ( 1, 9, 16)
8415 04:37:56.790900 Total UI for P1: 0, mck2ui 16
8416 04:37:56.794118 best dqsien dly found for B1: ( 1, 9, 16)
8417 04:37:56.801244 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8418 04:37:56.804239 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8419 04:37:56.804320
8420 04:37:56.807822 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8421 04:37:56.811085 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8422 04:37:56.814544 [Gating] SW calibration Done
8423 04:37:56.814626 ==
8424 04:37:56.817709 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 04:37:56.821335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 04:37:56.821417 ==
8427 04:37:56.824567 RX Vref Scan: 0
8428 04:37:56.824648
8429 04:37:56.824751 RX Vref 0 -> 0, step: 1
8430 04:37:56.824812
8431 04:37:56.827511 RX Delay 0 -> 252, step: 8
8432 04:37:56.830924 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8433 04:37:56.834168 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8434 04:37:56.841095 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8435 04:37:56.844462 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8436 04:37:56.847749 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8437 04:37:56.851330 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8438 04:37:56.854504 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8439 04:37:56.861000 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8440 04:37:56.864434 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8441 04:37:56.867836 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8442 04:37:56.871062 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8443 04:37:56.874215 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8444 04:37:56.881774 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8445 04:37:56.884391 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8446 04:37:56.887484 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8447 04:37:56.891202 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8448 04:37:56.891300 ==
8449 04:37:56.894603 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 04:37:56.898062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 04:37:56.901063 ==
8452 04:37:56.901144 DQS Delay:
8453 04:37:56.901208 DQS0 = 0, DQS1 = 0
8454 04:37:56.904517 DQM Delay:
8455 04:37:56.904598 DQM0 = 134, DQM1 = 127
8456 04:37:56.907961 DQ Delay:
8457 04:37:56.911395 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8458 04:37:56.914210 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8459 04:37:56.917824 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8460 04:37:56.921276 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8461 04:37:56.921362
8462 04:37:56.921427
8463 04:37:56.921487 ==
8464 04:37:56.924524 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 04:37:56.927493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 04:37:56.927601 ==
8467 04:37:56.927693
8468 04:37:56.930946
8469 04:37:56.931027 TX Vref Scan disable
8470 04:37:56.934579 == TX Byte 0 ==
8471 04:37:56.937744 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8472 04:37:56.941100 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8473 04:37:56.944571 == TX Byte 1 ==
8474 04:37:56.947732 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8475 04:37:56.950678 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8476 04:37:56.950784 ==
8477 04:37:56.954803 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 04:37:56.960543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 04:37:56.960653 ==
8480 04:37:56.973228
8481 04:37:56.976351 TX Vref early break, caculate TX vref
8482 04:37:56.979988 TX Vref=16, minBit 8, minWin=21, winSum=364
8483 04:37:56.983222 TX Vref=18, minBit 9, minWin=20, winSum=373
8484 04:37:56.986879 TX Vref=20, minBit 8, minWin=22, winSum=383
8485 04:37:56.989942 TX Vref=22, minBit 8, minWin=23, winSum=391
8486 04:37:56.993295 TX Vref=24, minBit 5, minWin=24, winSum=401
8487 04:37:57.000095 TX Vref=26, minBit 5, minWin=25, winSum=412
8488 04:37:57.003441 TX Vref=28, minBit 8, minWin=24, winSum=418
8489 04:37:57.006844 TX Vref=30, minBit 1, minWin=25, winSum=419
8490 04:37:57.009979 TX Vref=32, minBit 9, minWin=24, winSum=412
8491 04:37:57.013228 TX Vref=34, minBit 8, minWin=24, winSum=403
8492 04:37:57.016906 TX Vref=36, minBit 8, minWin=23, winSum=392
8493 04:37:57.023696 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 30
8494 04:37:57.023770
8495 04:37:57.026744 Final TX Range 0 Vref 30
8496 04:37:57.026825
8497 04:37:57.026891 ==
8498 04:37:57.030246 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 04:37:57.033624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 04:37:57.033705 ==
8501 04:37:57.033770
8502 04:37:57.033830
8503 04:37:57.036867 TX Vref Scan disable
8504 04:37:57.043427 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8505 04:37:57.043509 == TX Byte 0 ==
8506 04:37:57.046673 u2DelayCellOfst[0]=17 cells (5 PI)
8507 04:37:57.050287 u2DelayCellOfst[1]=14 cells (4 PI)
8508 04:37:57.053412 u2DelayCellOfst[2]=0 cells (0 PI)
8509 04:37:57.056850 u2DelayCellOfst[3]=7 cells (2 PI)
8510 04:37:57.060403 u2DelayCellOfst[4]=7 cells (2 PI)
8511 04:37:57.063821 u2DelayCellOfst[5]=21 cells (6 PI)
8512 04:37:57.067297 u2DelayCellOfst[6]=17 cells (5 PI)
8513 04:37:57.067378 u2DelayCellOfst[7]=7 cells (2 PI)
8514 04:37:57.073561 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8515 04:37:57.076901 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8516 04:37:57.076983 == TX Byte 1 ==
8517 04:37:57.080346 u2DelayCellOfst[8]=0 cells (0 PI)
8518 04:37:57.083842 u2DelayCellOfst[9]=3 cells (1 PI)
8519 04:37:57.087565 u2DelayCellOfst[10]=14 cells (4 PI)
8520 04:37:57.090057 u2DelayCellOfst[11]=7 cells (2 PI)
8521 04:37:57.093764 u2DelayCellOfst[12]=14 cells (4 PI)
8522 04:37:57.096922 u2DelayCellOfst[13]=17 cells (5 PI)
8523 04:37:57.100461 u2DelayCellOfst[14]=17 cells (5 PI)
8524 04:37:57.103768 u2DelayCellOfst[15]=21 cells (6 PI)
8525 04:37:57.107050 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8526 04:37:57.110093 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8527 04:37:57.113943 DramC Write-DBI on
8528 04:37:57.114024 ==
8529 04:37:57.117237 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 04:37:57.120177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 04:37:57.120286 ==
8532 04:37:57.120381
8533 04:37:57.120471
8534 04:37:57.123592 TX Vref Scan disable
8535 04:37:57.127063 == TX Byte 0 ==
8536 04:37:57.130511 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8537 04:37:57.133537 == TX Byte 1 ==
8538 04:37:57.137015 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8539 04:37:57.137092 DramC Write-DBI off
8540 04:37:57.137155
8541 04:37:57.140679 [DATLAT]
8542 04:37:57.140757 Freq=1600, CH1 RK0
8543 04:37:57.140822
8544 04:37:57.144160 DATLAT Default: 0xf
8545 04:37:57.144241 0, 0xFFFF, sum = 0
8546 04:37:57.146866 1, 0xFFFF, sum = 0
8547 04:37:57.146948 2, 0xFFFF, sum = 0
8548 04:37:57.150419 3, 0xFFFF, sum = 0
8549 04:37:57.150501 4, 0xFFFF, sum = 0
8550 04:37:57.153645 5, 0xFFFF, sum = 0
8551 04:37:57.153730 6, 0xFFFF, sum = 0
8552 04:37:57.157028 7, 0xFFFF, sum = 0
8553 04:37:57.157156 8, 0xFFFF, sum = 0
8554 04:37:57.160519 9, 0xFFFF, sum = 0
8555 04:37:57.160632 10, 0xFFFF, sum = 0
8556 04:37:57.164072 11, 0xFFFF, sum = 0
8557 04:37:57.167249 12, 0xFFFF, sum = 0
8558 04:37:57.167362 13, 0xFFFF, sum = 0
8559 04:37:57.170561 14, 0x0, sum = 1
8560 04:37:57.170660 15, 0x0, sum = 2
8561 04:37:57.170727 16, 0x0, sum = 3
8562 04:37:57.174035 17, 0x0, sum = 4
8563 04:37:57.174117 best_step = 15
8564 04:37:57.174187
8565 04:37:57.174250 ==
8566 04:37:57.177677 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 04:37:57.183689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 04:37:57.183797 ==
8569 04:37:57.183891 RX Vref Scan: 1
8570 04:37:57.183980
8571 04:37:57.187280 Set Vref Range= 24 -> 127
8572 04:37:57.187351
8573 04:37:57.190711 RX Vref 24 -> 127, step: 1
8574 04:37:57.190792
8575 04:37:57.193930 RX Delay 19 -> 252, step: 4
8576 04:37:57.194011
8577 04:37:57.197413 Set Vref, RX VrefLevel [Byte0]: 24
8578 04:37:57.200702 [Byte1]: 24
8579 04:37:57.200798
8580 04:37:57.203807 Set Vref, RX VrefLevel [Byte0]: 25
8581 04:37:57.207231 [Byte1]: 25
8582 04:37:57.207313
8583 04:37:57.210528 Set Vref, RX VrefLevel [Byte0]: 26
8584 04:37:57.214273 [Byte1]: 26
8585 04:37:57.214354
8586 04:37:57.217531 Set Vref, RX VrefLevel [Byte0]: 27
8587 04:37:57.220708 [Byte1]: 27
8588 04:37:57.224492
8589 04:37:57.224599 Set Vref, RX VrefLevel [Byte0]: 28
8590 04:37:57.227846 [Byte1]: 28
8591 04:37:57.232420
8592 04:37:57.232527 Set Vref, RX VrefLevel [Byte0]: 29
8593 04:37:57.235269 [Byte1]: 29
8594 04:37:57.239306
8595 04:37:57.239387 Set Vref, RX VrefLevel [Byte0]: 30
8596 04:37:57.243126 [Byte1]: 30
8597 04:37:57.247457
8598 04:37:57.247543 Set Vref, RX VrefLevel [Byte0]: 31
8599 04:37:57.250463 [Byte1]: 31
8600 04:37:57.254871
8601 04:37:57.254965 Set Vref, RX VrefLevel [Byte0]: 32
8602 04:37:57.257755 [Byte1]: 32
8603 04:37:57.262278
8604 04:37:57.262381 Set Vref, RX VrefLevel [Byte0]: 33
8605 04:37:57.265592 [Byte1]: 33
8606 04:37:57.270050
8607 04:37:57.270154 Set Vref, RX VrefLevel [Byte0]: 34
8608 04:37:57.273435 [Byte1]: 34
8609 04:37:57.277445
8610 04:37:57.277519 Set Vref, RX VrefLevel [Byte0]: 35
8611 04:37:57.280977 [Byte1]: 35
8612 04:37:57.284988
8613 04:37:57.285060 Set Vref, RX VrefLevel [Byte0]: 36
8614 04:37:57.288219 [Byte1]: 36
8615 04:37:57.292526
8616 04:37:57.292633 Set Vref, RX VrefLevel [Byte0]: 37
8617 04:37:57.296332 [Byte1]: 37
8618 04:37:57.300135
8619 04:37:57.300257 Set Vref, RX VrefLevel [Byte0]: 38
8620 04:37:57.303586 [Byte1]: 38
8621 04:37:57.307410
8622 04:37:57.307505 Set Vref, RX VrefLevel [Byte0]: 39
8623 04:37:57.310724 [Byte1]: 39
8624 04:37:57.315246
8625 04:37:57.315327 Set Vref, RX VrefLevel [Byte0]: 40
8626 04:37:57.318777 [Byte1]: 40
8627 04:37:57.322758
8628 04:37:57.322837 Set Vref, RX VrefLevel [Byte0]: 41
8629 04:37:57.325960 [Byte1]: 41
8630 04:37:57.330241
8631 04:37:57.330315 Set Vref, RX VrefLevel [Byte0]: 42
8632 04:37:57.333478 [Byte1]: 42
8633 04:37:57.338142
8634 04:37:57.338248 Set Vref, RX VrefLevel [Byte0]: 43
8635 04:37:57.341327 [Byte1]: 43
8636 04:37:57.346205
8637 04:37:57.346286 Set Vref, RX VrefLevel [Byte0]: 44
8638 04:37:57.348691 [Byte1]: 44
8639 04:37:57.353174
8640 04:37:57.353255 Set Vref, RX VrefLevel [Byte0]: 45
8641 04:37:57.356564 [Byte1]: 45
8642 04:37:57.360515
8643 04:37:57.360596 Set Vref, RX VrefLevel [Byte0]: 46
8644 04:37:57.364214 [Byte1]: 46
8645 04:37:57.368014
8646 04:37:57.368086 Set Vref, RX VrefLevel [Byte0]: 47
8647 04:37:57.371729 [Byte1]: 47
8648 04:37:57.375649
8649 04:37:57.375729 Set Vref, RX VrefLevel [Byte0]: 48
8650 04:37:57.379228 [Byte1]: 48
8651 04:37:57.383272
8652 04:37:57.383379 Set Vref, RX VrefLevel [Byte0]: 49
8653 04:37:57.386660 [Byte1]: 49
8654 04:37:57.391396
8655 04:37:57.391477 Set Vref, RX VrefLevel [Byte0]: 50
8656 04:37:57.394584 [Byte1]: 50
8657 04:37:57.398613
8658 04:37:57.398688 Set Vref, RX VrefLevel [Byte0]: 51
8659 04:37:57.401695 [Byte1]: 51
8660 04:37:57.406042
8661 04:37:57.406155 Set Vref, RX VrefLevel [Byte0]: 52
8662 04:37:57.409517 [Byte1]: 52
8663 04:37:57.413502
8664 04:37:57.413583 Set Vref, RX VrefLevel [Byte0]: 53
8665 04:37:57.416739 [Byte1]: 53
8666 04:37:57.421174
8667 04:37:57.421259 Set Vref, RX VrefLevel [Byte0]: 54
8668 04:37:57.424341 [Byte1]: 54
8669 04:37:57.429249
8670 04:37:57.429330 Set Vref, RX VrefLevel [Byte0]: 55
8671 04:37:57.432315 [Byte1]: 55
8672 04:37:57.436502
8673 04:37:57.436627 Set Vref, RX VrefLevel [Byte0]: 56
8674 04:37:57.439468 [Byte1]: 56
8675 04:37:57.443671
8676 04:37:57.443780 Set Vref, RX VrefLevel [Byte0]: 57
8677 04:37:57.447283 [Byte1]: 57
8678 04:37:57.451346
8679 04:37:57.451457 Set Vref, RX VrefLevel [Byte0]: 58
8680 04:37:57.454718 [Byte1]: 58
8681 04:37:57.458781
8682 04:37:57.458862 Set Vref, RX VrefLevel [Byte0]: 59
8683 04:37:57.462539 [Byte1]: 59
8684 04:37:57.466723
8685 04:37:57.466814 Set Vref, RX VrefLevel [Byte0]: 60
8686 04:37:57.469819 [Byte1]: 60
8687 04:37:57.474556
8688 04:37:57.474639 Set Vref, RX VrefLevel [Byte0]: 61
8689 04:37:57.477610 [Byte1]: 61
8690 04:37:57.482052
8691 04:37:57.482163 Set Vref, RX VrefLevel [Byte0]: 62
8692 04:37:57.485246 [Byte1]: 62
8693 04:37:57.489671
8694 04:37:57.489754 Set Vref, RX VrefLevel [Byte0]: 63
8695 04:37:57.492903 [Byte1]: 63
8696 04:37:57.496959
8697 04:37:57.497039 Set Vref, RX VrefLevel [Byte0]: 64
8698 04:37:57.500342 [Byte1]: 64
8699 04:37:57.504196
8700 04:37:57.504294 Set Vref, RX VrefLevel [Byte0]: 65
8701 04:37:57.507591 [Byte1]: 65
8702 04:37:57.511987
8703 04:37:57.512103 Set Vref, RX VrefLevel [Byte0]: 66
8704 04:37:57.515297 [Byte1]: 66
8705 04:37:57.519882
8706 04:37:57.519965 Set Vref, RX VrefLevel [Byte0]: 67
8707 04:37:57.523162 [Byte1]: 67
8708 04:37:57.527261
8709 04:37:57.527342 Set Vref, RX VrefLevel [Byte0]: 68
8710 04:37:57.533662 [Byte1]: 68
8711 04:37:57.533747
8712 04:37:57.537135 Set Vref, RX VrefLevel [Byte0]: 69
8713 04:37:57.540525 [Byte1]: 69
8714 04:37:57.540634
8715 04:37:57.543880 Set Vref, RX VrefLevel [Byte0]: 70
8716 04:37:57.547112 [Byte1]: 70
8717 04:37:57.547195
8718 04:37:57.550517 Set Vref, RX VrefLevel [Byte0]: 71
8719 04:37:57.553574 [Byte1]: 71
8720 04:37:57.557403
8721 04:37:57.557486 Set Vref, RX VrefLevel [Byte0]: 72
8722 04:37:57.561024 [Byte1]: 72
8723 04:37:57.564983
8724 04:37:57.565059 Final RX Vref Byte 0 = 64 to rank0
8725 04:37:57.568391 Final RX Vref Byte 1 = 55 to rank0
8726 04:37:57.571910 Final RX Vref Byte 0 = 64 to rank1
8727 04:37:57.575452 Final RX Vref Byte 1 = 55 to rank1==
8728 04:37:57.578280 Dram Type= 6, Freq= 0, CH_1, rank 0
8729 04:37:57.585291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 04:37:57.585404 ==
8731 04:37:57.585498 DQS Delay:
8732 04:37:57.585589 DQS0 = 0, DQS1 = 0
8733 04:37:57.588494 DQM Delay:
8734 04:37:57.588591 DQM0 = 132, DQM1 = 124
8735 04:37:57.591864 DQ Delay:
8736 04:37:57.594885 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =132
8737 04:37:57.598394 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8738 04:37:57.601885 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8739 04:37:57.605678 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8740 04:37:57.605768
8741 04:37:57.605834
8742 04:37:57.605895
8743 04:37:57.608629 [DramC_TX_OE_Calibration] TA2
8744 04:37:57.611986 Original DQ_B0 (3 6) =30, OEN = 27
8745 04:37:57.615390 Original DQ_B1 (3 6) =30, OEN = 27
8746 04:37:57.618857 24, 0x0, End_B0=24 End_B1=24
8747 04:37:57.618943 25, 0x0, End_B0=25 End_B1=25
8748 04:37:57.621713 26, 0x0, End_B0=26 End_B1=26
8749 04:37:57.625349 27, 0x0, End_B0=27 End_B1=27
8750 04:37:57.628690 28, 0x0, End_B0=28 End_B1=28
8751 04:37:57.628780 29, 0x0, End_B0=29 End_B1=29
8752 04:37:57.632018 30, 0x0, End_B0=30 End_B1=30
8753 04:37:57.635548 31, 0x4141, End_B0=30 End_B1=30
8754 04:37:57.638875 Byte0 end_step=30 best_step=27
8755 04:37:57.641789 Byte1 end_step=30 best_step=27
8756 04:37:57.645552 Byte0 TX OE(2T, 0.5T) = (3, 3)
8757 04:37:57.645638 Byte1 TX OE(2T, 0.5T) = (3, 3)
8758 04:37:57.645708
8759 04:37:57.645770
8760 04:37:57.655355 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8761 04:37:57.658769 CH1 RK0: MR19=303, MR18=1600
8762 04:37:57.665273 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8763 04:37:57.665354
8764 04:37:57.668917 ----->DramcWriteLeveling(PI) begin...
8765 04:37:57.669000 ==
8766 04:37:57.672080 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 04:37:57.675338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 04:37:57.675418 ==
8769 04:37:57.678585 Write leveling (Byte 0): 25 => 25
8770 04:37:57.682004 Write leveling (Byte 1): 27 => 27
8771 04:37:57.685615 DramcWriteLeveling(PI) end<-----
8772 04:37:57.685718
8773 04:37:57.685784 ==
8774 04:37:57.688959 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 04:37:57.691752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 04:37:57.691833 ==
8777 04:37:57.695764 [Gating] SW mode calibration
8778 04:37:57.702138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8779 04:37:57.708915 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8780 04:37:57.712286 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 04:37:57.715640 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 04:37:57.718766 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
8783 04:37:57.725444 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8784 04:37:57.728979 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 04:37:57.731887 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 04:37:57.738382 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 04:37:57.741876 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 04:37:57.745291 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 04:37:57.752382 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8790 04:37:57.755379 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
8791 04:37:57.759038 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8792 04:37:57.765440 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 04:37:57.768368 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 04:37:57.771831 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 04:37:57.778857 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 04:37:57.782114 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 04:37:57.785561 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 04:37:57.791716 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8799 04:37:57.795370 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8800 04:37:57.798682 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 04:37:57.805187 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 04:37:57.808773 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 04:37:57.811739 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 04:37:57.818729 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 04:37:57.821933 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8806 04:37:57.825421 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8807 04:37:57.832138 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8808 04:37:57.835406 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8809 04:37:57.838306 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 04:37:57.844901 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 04:37:57.848272 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 04:37:57.851513 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 04:37:57.854777 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 04:37:57.861466 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 04:37:57.864785 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 04:37:57.868301 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 04:37:57.875103 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 04:37:57.878255 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 04:37:57.881968 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 04:37:57.888202 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 04:37:57.891455 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 04:37:57.895181 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8823 04:37:57.901686 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8824 04:37:57.901797 Total UI for P1: 0, mck2ui 16
8825 04:37:57.908633 best dqsien dly found for B0: ( 1, 9, 8)
8826 04:37:57.911618 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 04:37:57.915189 Total UI for P1: 0, mck2ui 16
8828 04:37:57.918401 best dqsien dly found for B1: ( 1, 9, 10)
8829 04:37:57.921613 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8830 04:37:57.924984 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8831 04:37:57.925095
8832 04:37:57.928506 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8833 04:37:57.932102 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8834 04:37:57.934909 [Gating] SW calibration Done
8835 04:37:57.935020 ==
8836 04:37:57.938252 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 04:37:57.941582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 04:37:57.941661 ==
8839 04:37:57.945058 RX Vref Scan: 0
8840 04:37:57.945141
8841 04:37:57.948449 RX Vref 0 -> 0, step: 1
8842 04:37:57.948559
8843 04:37:57.948660 RX Delay 0 -> 252, step: 8
8844 04:37:57.954872 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8845 04:37:57.958889 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8846 04:37:57.961774 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8847 04:37:57.965277 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8848 04:37:57.968568 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8849 04:37:57.975494 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8850 04:37:57.978826 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8851 04:37:57.981725 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8852 04:37:57.985272 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8853 04:37:57.988505 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8854 04:37:57.994971 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8855 04:37:57.998721 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8856 04:37:58.001900 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8857 04:37:58.005426 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8858 04:37:58.008658 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8859 04:37:58.015046 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8860 04:37:58.015140 ==
8861 04:37:58.018596 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 04:37:58.022637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 04:37:58.022718 ==
8864 04:37:58.022807 DQS Delay:
8865 04:37:58.025177 DQS0 = 0, DQS1 = 0
8866 04:37:58.025281 DQM Delay:
8867 04:37:58.028728 DQM0 = 132, DQM1 = 127
8868 04:37:58.028812 DQ Delay:
8869 04:37:58.032042 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8870 04:37:58.035549 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8871 04:37:58.038731 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8872 04:37:58.041994 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8873 04:37:58.042069
8874 04:37:58.042149
8875 04:37:58.042226 ==
8876 04:37:58.045574 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 04:37:58.051895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 04:37:58.051999 ==
8879 04:37:58.052110
8880 04:37:58.052212
8881 04:37:58.052308 TX Vref Scan disable
8882 04:37:58.055387 == TX Byte 0 ==
8883 04:37:58.058877 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8884 04:37:58.062276 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8885 04:37:58.065417 == TX Byte 1 ==
8886 04:37:58.069027 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8887 04:37:58.072421 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8888 04:37:58.075254 ==
8889 04:37:58.079079 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 04:37:58.082559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 04:37:58.082661 ==
8892 04:37:58.095488
8893 04:37:58.098944 TX Vref early break, caculate TX vref
8894 04:37:58.102116 TX Vref=16, minBit 11, minWin=21, winSum=374
8895 04:37:58.105702 TX Vref=18, minBit 9, minWin=21, winSum=382
8896 04:37:58.108741 TX Vref=20, minBit 8, minWin=23, winSum=392
8897 04:37:58.112354 TX Vref=22, minBit 8, minWin=23, winSum=399
8898 04:37:58.115803 TX Vref=24, minBit 8, minWin=24, winSum=406
8899 04:37:58.122458 TX Vref=26, minBit 8, minWin=24, winSum=415
8900 04:37:58.125574 TX Vref=28, minBit 5, minWin=25, winSum=420
8901 04:37:58.128601 TX Vref=30, minBit 5, minWin=25, winSum=425
8902 04:37:58.132300 TX Vref=32, minBit 0, minWin=25, winSum=411
8903 04:37:58.135318 TX Vref=34, minBit 8, minWin=24, winSum=406
8904 04:37:58.139060 TX Vref=36, minBit 0, minWin=24, winSum=400
8905 04:37:58.145848 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 30
8906 04:37:58.145964
8907 04:37:58.148605 Final TX Range 0 Vref 30
8908 04:37:58.148740
8909 04:37:58.148831 ==
8910 04:37:58.152205 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 04:37:58.155688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 04:37:58.155771 ==
8913 04:37:58.155835
8914 04:37:58.155895
8915 04:37:58.159051 TX Vref Scan disable
8916 04:37:58.165534 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8917 04:37:58.165616 == TX Byte 0 ==
8918 04:37:58.168600 u2DelayCellOfst[0]=17 cells (5 PI)
8919 04:37:58.171962 u2DelayCellOfst[1]=14 cells (4 PI)
8920 04:37:58.175356 u2DelayCellOfst[2]=0 cells (0 PI)
8921 04:37:58.179069 u2DelayCellOfst[3]=7 cells (2 PI)
8922 04:37:58.182009 u2DelayCellOfst[4]=10 cells (3 PI)
8923 04:37:58.185625 u2DelayCellOfst[5]=21 cells (6 PI)
8924 04:37:58.189006 u2DelayCellOfst[6]=17 cells (5 PI)
8925 04:37:58.192051 u2DelayCellOfst[7]=7 cells (2 PI)
8926 04:37:58.195863 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8927 04:37:58.199274 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8928 04:37:58.199357 == TX Byte 1 ==
8929 04:37:58.202242 u2DelayCellOfst[8]=0 cells (0 PI)
8930 04:37:58.205572 u2DelayCellOfst[9]=7 cells (2 PI)
8931 04:37:58.209569 u2DelayCellOfst[10]=10 cells (3 PI)
8932 04:37:58.212312 u2DelayCellOfst[11]=3 cells (1 PI)
8933 04:37:58.215919 u2DelayCellOfst[12]=10 cells (3 PI)
8934 04:37:58.219599 u2DelayCellOfst[13]=14 cells (4 PI)
8935 04:37:58.223104 u2DelayCellOfst[14]=14 cells (4 PI)
8936 04:37:58.225573 u2DelayCellOfst[15]=14 cells (4 PI)
8937 04:37:58.228808 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8938 04:37:58.235689 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8939 04:37:58.235773 DramC Write-DBI on
8940 04:37:58.235840 ==
8941 04:37:58.239000 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 04:37:58.241917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 04:37:58.242006 ==
8944 04:37:58.245403
8945 04:37:58.245485
8946 04:37:58.245550 TX Vref Scan disable
8947 04:37:58.248813 == TX Byte 0 ==
8948 04:37:58.252356 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8949 04:37:58.255936 == TX Byte 1 ==
8950 04:37:58.258826 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8951 04:37:58.261878 DramC Write-DBI off
8952 04:37:58.261959
8953 04:37:58.262032 [DATLAT]
8954 04:37:58.262094 Freq=1600, CH1 RK1
8955 04:37:58.262154
8956 04:37:58.265331 DATLAT Default: 0xf
8957 04:37:58.265401 0, 0xFFFF, sum = 0
8958 04:37:58.268770 1, 0xFFFF, sum = 0
8959 04:37:58.268901 2, 0xFFFF, sum = 0
8960 04:37:58.271900 3, 0xFFFF, sum = 0
8961 04:37:58.275193 4, 0xFFFF, sum = 0
8962 04:37:58.275298 5, 0xFFFF, sum = 0
8963 04:37:58.279003 6, 0xFFFF, sum = 0
8964 04:37:58.279110 7, 0xFFFF, sum = 0
8965 04:37:58.282318 8, 0xFFFF, sum = 0
8966 04:37:58.282399 9, 0xFFFF, sum = 0
8967 04:37:58.285105 10, 0xFFFF, sum = 0
8968 04:37:58.285186 11, 0xFFFF, sum = 0
8969 04:37:58.288943 12, 0xFFFF, sum = 0
8970 04:37:58.289024 13, 0xFFFF, sum = 0
8971 04:37:58.292454 14, 0x0, sum = 1
8972 04:37:58.292553 15, 0x0, sum = 2
8973 04:37:58.295247 16, 0x0, sum = 3
8974 04:37:58.295328 17, 0x0, sum = 4
8975 04:37:58.298719 best_step = 15
8976 04:37:58.298798
8977 04:37:58.298861 ==
8978 04:37:58.302066 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 04:37:58.305233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 04:37:58.305313 ==
8981 04:37:58.305376 RX Vref Scan: 0
8982 04:37:58.308630
8983 04:37:58.308746 RX Vref 0 -> 0, step: 1
8984 04:37:58.308830
8985 04:37:58.312327 RX Delay 11 -> 252, step: 4
8986 04:37:58.315546 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8987 04:37:58.322073 iDelay=191, Bit 1, Center 124 (75 ~ 174) 100
8988 04:37:58.325207 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8989 04:37:58.328598 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8990 04:37:58.331767 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8991 04:37:58.335165 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8992 04:37:58.338791 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8993 04:37:58.345555 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
8994 04:37:58.348673 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8995 04:37:58.352032 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8996 04:37:58.355416 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8997 04:37:58.358846 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8998 04:37:58.365611 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8999 04:37:58.369278 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9000 04:37:58.371957 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9001 04:37:58.375372 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9002 04:37:58.375452 ==
9003 04:37:58.378729 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 04:37:58.385185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 04:37:58.385292 ==
9006 04:37:58.385384 DQS Delay:
9007 04:37:58.389056 DQS0 = 0, DQS1 = 0
9008 04:37:58.389136 DQM Delay:
9009 04:37:58.389229 DQM0 = 129, DQM1 = 125
9010 04:37:58.391964 DQ Delay:
9011 04:37:58.395365 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
9012 04:37:58.398994 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9013 04:37:58.402056 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =116
9014 04:37:58.405573 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9015 04:37:58.405653
9016 04:37:58.405716
9017 04:37:58.405775
9018 04:37:58.408932 [DramC_TX_OE_Calibration] TA2
9019 04:37:58.412112 Original DQ_B0 (3 6) =30, OEN = 27
9020 04:37:58.415517 Original DQ_B1 (3 6) =30, OEN = 27
9021 04:37:58.419397 24, 0x0, End_B0=24 End_B1=24
9022 04:37:58.419479 25, 0x0, End_B0=25 End_B1=25
9023 04:37:58.421973 26, 0x0, End_B0=26 End_B1=26
9024 04:37:58.425258 27, 0x0, End_B0=27 End_B1=27
9025 04:37:58.429214 28, 0x0, End_B0=28 End_B1=28
9026 04:37:58.429324 29, 0x0, End_B0=29 End_B1=29
9027 04:37:58.432393 30, 0x0, End_B0=30 End_B1=30
9028 04:37:58.435324 31, 0x4141, End_B0=30 End_B1=30
9029 04:37:58.438714 Byte0 end_step=30 best_step=27
9030 04:37:58.442226 Byte1 end_step=30 best_step=27
9031 04:37:58.445779 Byte0 TX OE(2T, 0.5T) = (3, 3)
9032 04:37:58.445856 Byte1 TX OE(2T, 0.5T) = (3, 3)
9033 04:37:58.445937
9034 04:37:58.448934
9035 04:37:58.455574 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9036 04:37:58.459061 CH1 RK1: MR19=303, MR18=1016
9037 04:37:58.465462 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9038 04:37:58.465544 [RxdqsGatingPostProcess] freq 1600
9039 04:37:58.472405 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9040 04:37:58.475358 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 04:37:58.478930 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 04:37:58.482155 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 04:37:58.485735 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 04:37:58.488871 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 04:37:58.492594 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 04:37:58.495585 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 04:37:58.495667 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 04:37:58.499386 Pre-setting of DQS Precalculation
9049 04:37:58.505813 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9050 04:37:58.512134 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9051 04:37:58.519185 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 04:37:58.519308
9053 04:37:58.519381
9054 04:37:58.522613 [Calibration Summary] 3200 Mbps
9055 04:37:58.525849 CH 0, Rank 0
9056 04:37:58.525929 SW Impedance : PASS
9057 04:37:58.529546 DUTY Scan : NO K
9058 04:37:58.529625 ZQ Calibration : PASS
9059 04:37:58.532653 Jitter Meter : NO K
9060 04:37:58.535659 CBT Training : PASS
9061 04:37:58.535739 Write leveling : PASS
9062 04:37:58.539118 RX DQS gating : PASS
9063 04:37:58.542766 RX DQ/DQS(RDDQC) : PASS
9064 04:37:58.542845 TX DQ/DQS : PASS
9065 04:37:58.546037 RX DATLAT : PASS
9066 04:37:58.549690 RX DQ/DQS(Engine): PASS
9067 04:37:58.549770 TX OE : PASS
9068 04:37:58.552518 All Pass.
9069 04:37:58.552601
9070 04:37:58.552671 CH 0, Rank 1
9071 04:37:58.555611 SW Impedance : PASS
9072 04:37:58.555691 DUTY Scan : NO K
9073 04:37:58.558944 ZQ Calibration : PASS
9074 04:37:58.562236 Jitter Meter : NO K
9075 04:37:58.562315 CBT Training : PASS
9076 04:37:58.565682 Write leveling : PASS
9077 04:37:58.569026 RX DQS gating : PASS
9078 04:37:58.569106 RX DQ/DQS(RDDQC) : PASS
9079 04:37:58.572398 TX DQ/DQS : PASS
9080 04:37:58.572478 RX DATLAT : PASS
9081 04:37:58.575785 RX DQ/DQS(Engine): PASS
9082 04:37:58.578907 TX OE : PASS
9083 04:37:58.578986 All Pass.
9084 04:37:58.579049
9085 04:37:58.579108 CH 1, Rank 0
9086 04:37:58.582225 SW Impedance : PASS
9087 04:37:58.585595 DUTY Scan : NO K
9088 04:37:58.585676 ZQ Calibration : PASS
9089 04:37:58.588876 Jitter Meter : NO K
9090 04:37:58.592650 CBT Training : PASS
9091 04:37:58.592739 Write leveling : PASS
9092 04:37:58.595815 RX DQS gating : PASS
9093 04:37:58.599527 RX DQ/DQS(RDDQC) : PASS
9094 04:37:58.599626 TX DQ/DQS : PASS
9095 04:37:58.602626 RX DATLAT : PASS
9096 04:37:58.605533 RX DQ/DQS(Engine): PASS
9097 04:37:58.605613 TX OE : PASS
9098 04:37:58.605677 All Pass.
9099 04:37:58.608849
9100 04:37:58.608928 CH 1, Rank 1
9101 04:37:58.612431 SW Impedance : PASS
9102 04:37:58.612510 DUTY Scan : NO K
9103 04:37:58.615867 ZQ Calibration : PASS
9104 04:37:58.615947 Jitter Meter : NO K
9105 04:37:58.618842 CBT Training : PASS
9106 04:37:58.622747 Write leveling : PASS
9107 04:37:58.622827 RX DQS gating : PASS
9108 04:37:58.625639 RX DQ/DQS(RDDQC) : PASS
9109 04:37:58.629035 TX DQ/DQS : PASS
9110 04:37:58.629115 RX DATLAT : PASS
9111 04:37:58.632740 RX DQ/DQS(Engine): PASS
9112 04:37:58.635834 TX OE : PASS
9113 04:37:58.635914 All Pass.
9114 04:37:58.635977
9115 04:37:58.636036 DramC Write-DBI on
9116 04:37:58.639083 PER_BANK_REFRESH: Hybrid Mode
9117 04:37:58.642268 TX_TRACKING: ON
9118 04:37:58.649323 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9119 04:37:58.659042 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9120 04:37:58.666081 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 04:37:58.669043 [FAST_K] Save calibration result to emmc
9122 04:37:58.672909 sync common calibartion params.
9123 04:37:58.675596 sync cbt_mode0:1, 1:1
9124 04:37:58.675675 dram_init: ddr_geometry: 2
9125 04:37:58.679077 dram_init: ddr_geometry: 2
9126 04:37:58.682406 dram_init: ddr_geometry: 2
9127 04:37:58.682485 0:dram_rank_size:100000000
9128 04:37:58.685772 1:dram_rank_size:100000000
9129 04:37:58.692616 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9130 04:37:58.692706 DFS_SHUFFLE_HW_MODE: ON
9131 04:37:58.699191 dramc_set_vcore_voltage set vcore to 725000
9132 04:37:58.699270 Read voltage for 1600, 0
9133 04:37:58.702614 Vio18 = 0
9134 04:37:58.702694 Vcore = 725000
9135 04:37:58.702757 Vdram = 0
9136 04:37:58.702816 Vddq = 0
9137 04:37:58.706167 Vmddr = 0
9138 04:37:58.706246 switch to 3200 Mbps bootup
9139 04:37:58.709133 [DramcRunTimeConfig]
9140 04:37:58.709212 PHYPLL
9141 04:37:58.712585 DPM_CONTROL_AFTERK: ON
9142 04:37:58.712670 PER_BANK_REFRESH: ON
9143 04:37:58.715862 REFRESH_OVERHEAD_REDUCTION: ON
9144 04:37:58.719367 CMD_PICG_NEW_MODE: OFF
9145 04:37:58.719446 XRTWTW_NEW_MODE: ON
9146 04:37:58.722904 XRTRTR_NEW_MODE: ON
9147 04:37:58.722983 TX_TRACKING: ON
9148 04:37:58.726128 RDSEL_TRACKING: OFF
9149 04:37:58.729513 DQS Precalculation for DVFS: ON
9150 04:37:58.729596 RX_TRACKING: OFF
9151 04:37:58.733002 HW_GATING DBG: ON
9152 04:37:58.733081 ZQCS_ENABLE_LP4: ON
9153 04:37:58.736057 RX_PICG_NEW_MODE: ON
9154 04:37:58.736137 TX_PICG_NEW_MODE: ON
9155 04:37:58.739604 ENABLE_RX_DCM_DPHY: ON
9156 04:37:58.742942 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9157 04:37:58.746433 DUMMY_READ_FOR_TRACKING: OFF
9158 04:37:58.749479 !!! SPM_CONTROL_AFTERK: OFF
9159 04:37:58.749568 !!! SPM could not control APHY
9160 04:37:58.752579 IMPEDANCE_TRACKING: ON
9161 04:37:58.752659 TEMP_SENSOR: ON
9162 04:37:58.755743 HW_SAVE_FOR_SR: OFF
9163 04:37:58.759241 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9164 04:37:58.762435 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9165 04:37:58.765664 Read ODT Tracking: ON
9166 04:37:58.765746 Refresh Rate DeBounce: ON
9167 04:37:58.769220 DFS_NO_QUEUE_FLUSH: ON
9168 04:37:58.772299 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9169 04:37:58.775687 ENABLE_DFS_RUNTIME_MRW: OFF
9170 04:37:58.775769 DDR_RESERVE_NEW_MODE: ON
9171 04:37:58.779013 MR_CBT_SWITCH_FREQ: ON
9172 04:37:58.782386 =========================
9173 04:37:58.800183 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9174 04:37:58.803471 dram_init: ddr_geometry: 2
9175 04:37:58.821763 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9176 04:37:58.825396 dram_init: dram init end (result: 0)
9177 04:37:58.832347 DRAM-K: Full calibration passed in 24541 msecs
9178 04:37:58.834956 MRC: failed to locate region type 0.
9179 04:37:58.835067 DRAM rank0 size:0x100000000,
9180 04:37:58.838416 DRAM rank1 size=0x100000000
9181 04:37:58.848656 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9182 04:37:58.854947 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9183 04:37:58.862092 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9184 04:37:58.868646 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9185 04:37:58.871703 DRAM rank0 size:0x100000000,
9186 04:37:58.875598 DRAM rank1 size=0x100000000
9187 04:37:58.875679 CBMEM:
9188 04:37:58.878662 IMD: root @ 0xfffff000 254 entries.
9189 04:37:58.881867 IMD: root @ 0xffffec00 62 entries.
9190 04:37:58.885548 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9191 04:37:58.888573 WARNING: RO_VPD is uninitialized or empty.
9192 04:37:58.895188 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9193 04:37:58.901492 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9194 04:37:58.914671 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9195 04:37:58.926024 BS: romstage times (exec / console): total (unknown) / 24055 ms
9196 04:37:58.926126
9197 04:37:58.926227
9198 04:37:58.935861 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9199 04:37:58.939533 ARM64: Exception handlers installed.
9200 04:37:58.942453 ARM64: Testing exception
9201 04:37:58.945874 ARM64: Done test exception
9202 04:37:58.945979 Enumerating buses...
9203 04:37:58.949609 Show all devs... Before device enumeration.
9204 04:37:58.952684 Root Device: enabled 1
9205 04:37:58.955661 CPU_CLUSTER: 0: enabled 1
9206 04:37:58.955771 CPU: 00: enabled 1
9207 04:37:58.959306 Compare with tree...
9208 04:37:58.959414 Root Device: enabled 1
9209 04:37:58.962500 CPU_CLUSTER: 0: enabled 1
9210 04:37:58.965837 CPU: 00: enabled 1
9211 04:37:58.965958 Root Device scanning...
9212 04:37:58.969329 scan_static_bus for Root Device
9213 04:37:58.972582 CPU_CLUSTER: 0 enabled
9214 04:37:58.975935 scan_static_bus for Root Device done
9215 04:37:58.979575 scan_bus: bus Root Device finished in 8 msecs
9216 04:37:58.979648 done
9217 04:37:58.985779 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9218 04:37:58.989609 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9219 04:37:58.996016 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9220 04:37:58.998989 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9221 04:37:59.002600 Allocating resources...
9222 04:37:59.002681 Reading resources...
9223 04:37:59.009122 Root Device read_resources bus 0 link: 0
9224 04:37:59.009234 DRAM rank0 size:0x100000000,
9225 04:37:59.012503 DRAM rank1 size=0x100000000
9226 04:37:59.015607 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9227 04:37:59.019114 CPU: 00 missing read_resources
9228 04:37:59.022475 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9229 04:37:59.029519 Root Device read_resources bus 0 link: 0 done
9230 04:37:59.029612 Done reading resources.
9231 04:37:59.036339 Show resources in subtree (Root Device)...After reading.
9232 04:37:59.039246 Root Device child on link 0 CPU_CLUSTER: 0
9233 04:37:59.042623 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 04:37:59.052475 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 04:37:59.052563 CPU: 00
9236 04:37:59.055944 Root Device assign_resources, bus 0 link: 0
9237 04:37:59.059271 CPU_CLUSTER: 0 missing set_resources
9238 04:37:59.062476 Root Device assign_resources, bus 0 link: 0 done
9239 04:37:59.065839 Done setting resources.
9240 04:37:59.072582 Show resources in subtree (Root Device)...After assigning values.
9241 04:37:59.075880 Root Device child on link 0 CPU_CLUSTER: 0
9242 04:37:59.079450 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 04:37:59.089467 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 04:37:59.089552 CPU: 00
9245 04:37:59.092928 Done allocating resources.
9246 04:37:59.095817 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9247 04:37:59.099198 Enabling resources...
9248 04:37:59.099304 done.
9249 04:37:59.102519 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9250 04:37:59.106414 Initializing devices...
9251 04:37:59.109445 Root Device init
9252 04:37:59.109556 init hardware done!
9253 04:37:59.112655 0x00000018: ctrlr->caps
9254 04:37:59.112776 52.000 MHz: ctrlr->f_max
9255 04:37:59.115801 0.400 MHz: ctrlr->f_min
9256 04:37:59.119151 0x40ff8080: ctrlr->voltages
9257 04:37:59.119260 sclk: 390625
9258 04:37:59.122453 Bus Width = 1
9259 04:37:59.122559 sclk: 390625
9260 04:37:59.122682 Bus Width = 1
9261 04:37:59.125997 Early init status = 3
9262 04:37:59.128894 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9263 04:37:59.134701 in-header: 03 fc 00 00 01 00 00 00
9264 04:37:59.137714 in-data: 00
9265 04:37:59.140763 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9266 04:37:59.146506 in-header: 03 fd 00 00 00 00 00 00
9267 04:37:59.149783 in-data:
9268 04:37:59.152821 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9269 04:37:59.157682 in-header: 03 fc 00 00 01 00 00 00
9270 04:37:59.160917 in-data: 00
9271 04:37:59.164584 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9272 04:37:59.169614 in-header: 03 fd 00 00 00 00 00 00
9273 04:37:59.172860 in-data:
9274 04:37:59.176581 [SSUSB] Setting up USB HOST controller...
9275 04:37:59.179686 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9276 04:37:59.183276 [SSUSB] phy power-on done.
9277 04:37:59.186217 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9278 04:37:59.193072 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9279 04:37:59.196516 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9280 04:37:59.202973 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9281 04:37:59.209561 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9282 04:37:59.216309 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9283 04:37:59.223059 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9284 04:37:59.229414 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9285 04:37:59.232954 SPM: binary array size = 0x9dc
9286 04:37:59.236311 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9287 04:37:59.242709 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9288 04:37:59.249994 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9289 04:37:59.253307 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9290 04:37:59.256440 configure_display: Starting display init
9291 04:37:59.293185 anx7625_power_on_init: Init interface.
9292 04:37:59.296639 anx7625_disable_pd_protocol: Disabled PD feature.
9293 04:37:59.299597 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9294 04:37:59.327423 anx7625_start_dp_work: Secure OCM version=00
9295 04:37:59.330570 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9296 04:37:59.345340 sp_tx_get_edid_block: EDID Block = 1
9297 04:37:59.448201 Extracted contents:
9298 04:37:59.451490 header: 00 ff ff ff ff ff ff 00
9299 04:37:59.454915 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9300 04:37:59.457925 version: 01 04
9301 04:37:59.461742 basic params: 95 1f 11 78 0a
9302 04:37:59.464857 chroma info: 76 90 94 55 54 90 27 21 50 54
9303 04:37:59.468341 established: 00 00 00
9304 04:37:59.474830 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9305 04:37:59.477857 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9306 04:37:59.484768 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9307 04:37:59.491576 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9308 04:37:59.498227 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9309 04:37:59.501640 extensions: 00
9310 04:37:59.501722 checksum: fb
9311 04:37:59.501785
9312 04:37:59.505263 Manufacturer: IVO Model 57d Serial Number 0
9313 04:37:59.507901 Made week 0 of 2020
9314 04:37:59.507981 EDID version: 1.4
9315 04:37:59.511422 Digital display
9316 04:37:59.514701 6 bits per primary color channel
9317 04:37:59.514815 DisplayPort interface
9318 04:37:59.518666 Maximum image size: 31 cm x 17 cm
9319 04:37:59.518774 Gamma: 220%
9320 04:37:59.521645 Check DPMS levels
9321 04:37:59.524571 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9322 04:37:59.528335 First detailed timing is preferred timing
9323 04:37:59.531394 Established timings supported:
9324 04:37:59.535168 Standard timings supported:
9325 04:37:59.535272 Detailed timings
9326 04:37:59.541611 Hex of detail: 383680a07038204018303c0035ae10000019
9327 04:37:59.544462 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9328 04:37:59.547870 0780 0798 07c8 0820 hborder 0
9329 04:37:59.555051 0438 043b 0447 0458 vborder 0
9330 04:37:59.555133 -hsync -vsync
9331 04:37:59.557977 Did detailed timing
9332 04:37:59.561438 Hex of detail: 000000000000000000000000000000000000
9333 04:37:59.565020 Manufacturer-specified data, tag 0
9334 04:37:59.571615 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9335 04:37:59.571700 ASCII string: InfoVision
9336 04:37:59.578223 Hex of detail: 000000fe00523134304e574635205248200a
9337 04:37:59.578301 ASCII string: R140NWF5 RH
9338 04:37:59.581582 Checksum
9339 04:37:59.581660 Checksum: 0xfb (valid)
9340 04:37:59.588369 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9341 04:37:59.588448 DSI data_rate: 832800000 bps
9342 04:37:59.596278 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9343 04:37:59.599498 anx7625_parse_edid: pixelclock(138800).
9344 04:37:59.602801 hactive(1920), hsync(48), hfp(24), hbp(88)
9345 04:37:59.605862 vactive(1080), vsync(12), vfp(3), vbp(17)
9346 04:37:59.609292 anx7625_dsi_config: config dsi.
9347 04:37:59.616115 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9348 04:37:59.629954 anx7625_dsi_config: success to config DSI
9349 04:37:59.633286 anx7625_dp_start: MIPI phy setup OK.
9350 04:37:59.636515 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9351 04:37:59.640195 mtk_ddp_mode_set invalid vrefresh 60
9352 04:37:59.643213 main_disp_path_setup
9353 04:37:59.643297 ovl_layer_smi_id_en
9354 04:37:59.647080 ovl_layer_smi_id_en
9355 04:37:59.647159 ccorr_config
9356 04:37:59.647222 aal_config
9357 04:37:59.650437 gamma_config
9358 04:37:59.650516 postmask_config
9359 04:37:59.654068 dither_config
9360 04:37:59.656564 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9361 04:37:59.663548 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9362 04:37:59.667089 Root Device init finished in 555 msecs
9363 04:37:59.667161 CPU_CLUSTER: 0 init
9364 04:37:59.676832 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9365 04:37:59.681061 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9366 04:37:59.683539 APU_MBOX 0x190000b0 = 0x10001
9367 04:37:59.686985 APU_MBOX 0x190001b0 = 0x10001
9368 04:37:59.690503 APU_MBOX 0x190005b0 = 0x10001
9369 04:37:59.693522 APU_MBOX 0x190006b0 = 0x10001
9370 04:37:59.696831 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9371 04:37:59.709293 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9372 04:37:59.721793 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9373 04:37:59.728405 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9374 04:37:59.739704 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9375 04:37:59.748685 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9376 04:37:59.752020 CPU_CLUSTER: 0 init finished in 81 msecs
9377 04:37:59.755746 Devices initialized
9378 04:37:59.758694 Show all devs... After init.
9379 04:37:59.758776 Root Device: enabled 1
9380 04:37:59.762453 CPU_CLUSTER: 0: enabled 1
9381 04:37:59.766289 CPU: 00: enabled 1
9382 04:37:59.768978 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9383 04:37:59.772318 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9384 04:37:59.775561 ELOG: NV offset 0x57f000 size 0x1000
9385 04:37:59.782242 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9386 04:37:59.788848 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9387 04:37:59.792611 ELOG: Event(17) added with size 13 at 2023-08-09 04:37:59 UTC
9388 04:37:59.795541 out: cmd=0x121: 03 db 21 01 00 00 00 00
9389 04:37:59.800552 in-header: 03 f2 00 00 2c 00 00 00
9390 04:37:59.813568 in-data: 6d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 04:37:59.820077 ELOG: Event(A1) added with size 10 at 2023-08-09 04:37:59 UTC
9392 04:37:59.827090 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9393 04:37:59.833819 ELOG: Event(A0) added with size 9 at 2023-08-09 04:37:59 UTC
9394 04:37:59.837323 elog_add_boot_reason: Logged dev mode boot
9395 04:37:59.840307 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9396 04:37:59.843626 Finalize devices...
9397 04:37:59.843724 Devices finalized
9398 04:37:59.850486 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9399 04:37:59.854050 Writing coreboot table at 0xffe64000
9400 04:37:59.857308 0. 000000000010a000-0000000000113fff: RAMSTAGE
9401 04:37:59.860584 1. 0000000040000000-00000000400fffff: RAM
9402 04:37:59.863726 2. 0000000040100000-000000004032afff: RAMSTAGE
9403 04:37:59.870805 3. 000000004032b000-00000000545fffff: RAM
9404 04:37:59.874049 4. 0000000054600000-000000005465ffff: BL31
9405 04:37:59.877255 5. 0000000054660000-00000000ffe63fff: RAM
9406 04:37:59.881096 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9407 04:37:59.887107 7. 0000000100000000-000000023fffffff: RAM
9408 04:37:59.887212 Passing 5 GPIOs to payload:
9409 04:37:59.894234 NAME | PORT | POLARITY | VALUE
9410 04:37:59.897633 EC in RW | 0x000000aa | low | undefined
9411 04:37:59.900537 EC interrupt | 0x00000005 | low | undefined
9412 04:37:59.907184 TPM interrupt | 0x000000ab | high | undefined
9413 04:37:59.910591 SD card detect | 0x00000011 | high | undefined
9414 04:37:59.917563 speaker enable | 0x00000093 | high | undefined
9415 04:37:59.920738 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9416 04:37:59.924257 in-header: 03 f9 00 00 02 00 00 00
9417 04:37:59.924370 in-data: 02 00
9418 04:37:59.927369 ADC[4]: Raw value=900221 ID=7
9419 04:37:59.931103 ADC[3]: Raw value=213336 ID=1
9420 04:37:59.931209 RAM Code: 0x71
9421 04:37:59.933820 ADC[6]: Raw value=74557 ID=0
9422 04:37:59.937320 ADC[5]: Raw value=211860 ID=1
9423 04:37:59.937423 SKU Code: 0x1
9424 04:37:59.944135 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae41
9425 04:37:59.947527 coreboot table: 964 bytes.
9426 04:37:59.950804 IMD ROOT 0. 0xfffff000 0x00001000
9427 04:37:59.953805 IMD SMALL 1. 0xffffe000 0x00001000
9428 04:37:59.957472 RO MCACHE 2. 0xffffc000 0x00001104
9429 04:37:59.960824 CONSOLE 3. 0xfff7c000 0x00080000
9430 04:37:59.960906 FMAP 4. 0xfff7b000 0x00000452
9431 04:37:59.964347 TIME STAMP 5. 0xfff7a000 0x00000910
9432 04:37:59.967601 VBOOT WORK 6. 0xfff66000 0x00014000
9433 04:37:59.970580 RAMOOPS 7. 0xffe66000 0x00100000
9434 04:37:59.973927 COREBOOT 8. 0xffe64000 0x00002000
9435 04:37:59.977496 IMD small region:
9436 04:37:59.980574 IMD ROOT 0. 0xffffec00 0x00000400
9437 04:37:59.984246 VPD 1. 0xffffeba0 0x0000004c
9438 04:37:59.987487 MMC STATUS 2. 0xffffeb80 0x00000004
9439 04:37:59.993984 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9440 04:37:59.994070 Probing TPM: done!
9441 04:38:00.000817 Connected to device vid:did:rid of 1ae0:0028:00
9442 04:38:00.007735 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9443 04:38:00.010774 Initialized TPM device CR50 revision 0
9444 04:38:00.014390 Checking cr50 for pending updates
9445 04:38:00.019819 Reading cr50 TPM mode
9446 04:38:00.028674 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9447 04:38:00.035649 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9448 04:38:00.075366 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9449 04:38:00.078538 Checking segment from ROM address 0x40100000
9450 04:38:00.082070 Checking segment from ROM address 0x4010001c
9451 04:38:00.088975 Loading segment from ROM address 0x40100000
9452 04:38:00.089056 code (compression=0)
9453 04:38:00.095630 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9454 04:38:00.106129 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9455 04:38:00.106217 it's not compressed!
9456 04:38:00.112148 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9457 04:38:00.115771 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9458 04:38:00.135771 Loading segment from ROM address 0x4010001c
9459 04:38:00.135880 Entry Point 0x80000000
9460 04:38:00.139223 Loaded segments
9461 04:38:00.142497 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9462 04:38:00.149254 Jumping to boot code at 0x80000000(0xffe64000)
9463 04:38:00.155753 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9464 04:38:00.162489 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9465 04:38:00.170585 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9466 04:38:00.173350 Checking segment from ROM address 0x40100000
9467 04:38:00.177312 Checking segment from ROM address 0x4010001c
9468 04:38:00.180364 Loading segment from ROM address 0x40100000
9469 04:38:00.183664 code (compression=1)
9470 04:38:00.190364 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9471 04:38:00.200521 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9472 04:38:00.200598 using LZMA
9473 04:38:00.208350 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9474 04:38:00.215306 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9475 04:38:00.218985 Loading segment from ROM address 0x4010001c
9476 04:38:00.219089 Entry Point 0x54601000
9477 04:38:00.221877 Loaded segments
9478 04:38:00.225608 NOTICE: MT8192 bl31_setup
9479 04:38:00.232054 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9480 04:38:00.235575 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9481 04:38:00.239199 WARNING: region 0:
9482 04:38:00.242111 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 04:38:00.242196 WARNING: region 1:
9484 04:38:00.248773 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9485 04:38:00.252298 WARNING: region 2:
9486 04:38:00.255679 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9487 04:38:00.258859 WARNING: region 3:
9488 04:38:00.262272 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 04:38:00.265356 WARNING: region 4:
9490 04:38:00.268769 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 04:38:00.272525 WARNING: region 5:
9492 04:38:00.276038 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 04:38:00.279011 WARNING: region 6:
9494 04:38:00.282474 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 04:38:00.282571 WARNING: region 7:
9496 04:38:00.288815 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 04:38:00.295641 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9498 04:38:00.299197 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9499 04:38:00.302390 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9500 04:38:00.305763 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9501 04:38:00.312322 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9502 04:38:00.315430 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9503 04:38:00.322684 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9504 04:38:00.325519 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9505 04:38:00.329215 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9506 04:38:00.336024 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9507 04:38:00.339585 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9508 04:38:00.342868 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9509 04:38:00.349100 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9510 04:38:00.352838 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9511 04:38:00.359243 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9512 04:38:00.362794 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9513 04:38:00.366166 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9514 04:38:00.372852 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9515 04:38:00.375832 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9516 04:38:00.380068 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9517 04:38:00.386226 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9518 04:38:00.389773 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9519 04:38:00.396860 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9520 04:38:00.399568 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9521 04:38:00.403470 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9522 04:38:00.410096 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9523 04:38:00.413056 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9524 04:38:00.416504 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9525 04:38:00.423075 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9526 04:38:00.426337 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9527 04:38:00.433143 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9528 04:38:00.436458 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9529 04:38:00.439922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9530 04:38:00.443587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9531 04:38:00.450261 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9532 04:38:00.453617 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9533 04:38:00.457083 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9534 04:38:00.460600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9535 04:38:00.466813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9536 04:38:00.470416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9537 04:38:00.473881 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9538 04:38:00.476973 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9539 04:38:00.480111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9540 04:38:00.487331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9541 04:38:00.490740 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9542 04:38:00.494067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9543 04:38:00.500388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9544 04:38:00.503763 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9545 04:38:00.507271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9546 04:38:00.514266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9547 04:38:00.517665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9548 04:38:00.520640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9549 04:38:00.527492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9550 04:38:00.530746 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9551 04:38:00.537522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9552 04:38:00.541197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9553 04:38:00.544009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9554 04:38:00.550831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9555 04:38:00.554417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9556 04:38:00.561257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9557 04:38:00.564521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9558 04:38:00.571187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9559 04:38:00.574516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9560 04:38:00.577446 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9561 04:38:00.584861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9562 04:38:00.588017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9563 04:38:00.594809 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9564 04:38:00.598179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9565 04:38:00.604680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9566 04:38:00.608263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9567 04:38:00.611530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9568 04:38:00.618511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9569 04:38:00.621318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9570 04:38:00.628194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9571 04:38:00.631721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9572 04:38:00.634845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9573 04:38:00.641818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9574 04:38:00.645061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9575 04:38:00.652282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9576 04:38:00.655334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9577 04:38:00.662019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9578 04:38:00.665643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9579 04:38:00.668831 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9580 04:38:00.675401 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9581 04:38:00.678650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9582 04:38:00.685310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9583 04:38:00.688456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9584 04:38:00.692116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9585 04:38:00.699116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9586 04:38:00.702066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9587 04:38:00.709241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9588 04:38:00.712494 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9589 04:38:00.719404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9590 04:38:00.723054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9591 04:38:00.726127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9592 04:38:00.732442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9593 04:38:00.736164 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9594 04:38:00.739507 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9595 04:38:00.745993 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9596 04:38:00.749429 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9597 04:38:00.752881 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9598 04:38:00.756429 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9599 04:38:00.763038 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9600 04:38:00.766142 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9601 04:38:00.772949 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9602 04:38:00.776015 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9603 04:38:00.780320 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9604 04:38:00.786522 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9605 04:38:00.789587 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9606 04:38:00.796810 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9607 04:38:00.799851 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9608 04:38:00.803658 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9609 04:38:00.809905 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9610 04:38:00.813321 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9611 04:38:00.819789 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9612 04:38:00.823564 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9613 04:38:00.826701 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9614 04:38:00.830098 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9615 04:38:00.836602 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9616 04:38:00.840040 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9617 04:38:00.843724 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9618 04:38:00.846511 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9619 04:38:00.853612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9620 04:38:00.857071 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9621 04:38:00.860495 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9622 04:38:00.866753 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9623 04:38:00.870381 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9624 04:38:00.874027 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9625 04:38:00.880503 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9626 04:38:00.883533 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9627 04:38:00.886915 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9628 04:38:00.893991 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9629 04:38:00.897080 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9630 04:38:00.903563 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9631 04:38:00.907403 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9632 04:38:00.910548 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9633 04:38:00.917312 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9634 04:38:00.920824 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9635 04:38:00.923819 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9636 04:38:00.931072 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9637 04:38:00.934015 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9638 04:38:00.940807 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9639 04:38:00.944283 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9640 04:38:00.947740 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9641 04:38:00.954666 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9642 04:38:00.957476 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9643 04:38:00.961350 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9644 04:38:00.967583 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9645 04:38:00.971103 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9646 04:38:00.978019 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9647 04:38:00.981514 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9648 04:38:00.984735 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9649 04:38:00.991243 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9650 04:38:00.994632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9651 04:38:00.998360 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9652 04:38:01.004710 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9653 04:38:01.008549 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9654 04:38:01.015098 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9655 04:38:01.018094 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9656 04:38:01.021461 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9657 04:38:01.028794 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9658 04:38:01.031948 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9659 04:38:01.035181 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9660 04:38:01.041667 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9661 04:38:01.044853 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9662 04:38:01.051601 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9663 04:38:01.055067 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9664 04:38:01.058366 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9665 04:38:01.064865 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9666 04:38:01.068401 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9667 04:38:01.071987 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9668 04:38:01.078441 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9669 04:38:01.081639 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9670 04:38:01.088592 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9671 04:38:01.092333 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9672 04:38:01.095184 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9673 04:38:01.102171 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9674 04:38:01.104969 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9675 04:38:01.112073 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9676 04:38:01.115023 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9677 04:38:01.118613 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9678 04:38:01.125439 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9679 04:38:01.128494 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9680 04:38:01.131604 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9681 04:38:01.138644 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9682 04:38:01.142020 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9683 04:38:01.148282 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9684 04:38:01.152042 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9685 04:38:01.155276 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9686 04:38:01.161843 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9687 04:38:01.165372 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9688 04:38:01.171956 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9689 04:38:01.175372 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9690 04:38:01.178583 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9691 04:38:01.185063 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9692 04:38:01.188671 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9693 04:38:01.195552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9694 04:38:01.198888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9695 04:38:01.205976 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9696 04:38:01.208396 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9697 04:38:01.212249 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9698 04:38:01.218529 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9699 04:38:01.221943 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9700 04:38:01.228881 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9701 04:38:01.231878 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9702 04:38:01.235149 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9703 04:38:01.241890 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9704 04:38:01.245464 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9705 04:38:01.251998 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9706 04:38:01.255512 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9707 04:38:01.259049 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9708 04:38:01.265232 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9709 04:38:01.268860 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9710 04:38:01.275309 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9711 04:38:01.278741 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9712 04:38:01.282245 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9713 04:38:01.288865 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9714 04:38:01.291971 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9715 04:38:01.298484 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9716 04:38:01.302110 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9717 04:38:01.309007 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9718 04:38:01.312146 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9719 04:38:01.315808 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9720 04:38:01.322089 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9721 04:38:01.325766 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9722 04:38:01.332059 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9723 04:38:01.335394 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9724 04:38:01.339393 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9725 04:38:01.345539 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9726 04:38:01.349118 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9727 04:38:01.352490 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9728 04:38:01.355892 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9729 04:38:01.362295 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9730 04:38:01.365671 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9731 04:38:01.369074 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9732 04:38:01.375511 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9733 04:38:01.378672 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9734 04:38:01.382800 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9735 04:38:01.388884 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9736 04:38:01.392282 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9737 04:38:01.395562 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9738 04:38:01.402546 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9739 04:38:01.405348 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9740 04:38:01.408590 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9741 04:38:01.415684 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9742 04:38:01.418961 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9743 04:38:01.425604 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9744 04:38:01.428486 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9745 04:38:01.432072 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9746 04:38:01.438756 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9747 04:38:01.441616 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9748 04:38:01.445673 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9749 04:38:01.451809 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9750 04:38:01.455107 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9751 04:38:01.458362 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9752 04:38:01.465412 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9753 04:38:01.468836 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9754 04:38:01.475345 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9755 04:38:01.478314 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9756 04:38:01.481693 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9757 04:38:01.488224 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9758 04:38:01.492159 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9759 04:38:01.494981 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9760 04:38:01.501897 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9761 04:38:01.505361 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9762 04:38:01.508777 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9763 04:38:01.515566 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9764 04:38:01.518871 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9765 04:38:01.522462 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9766 04:38:01.528610 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9767 04:38:01.532036 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9768 04:38:01.535670 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9769 04:38:01.538795 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9770 04:38:01.542370 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9771 04:38:01.548992 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9772 04:38:01.552028 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9773 04:38:01.555877 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9774 04:38:01.559293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9775 04:38:01.566404 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9776 04:38:01.568812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9777 04:38:01.572128 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9778 04:38:01.575540 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9779 04:38:01.582348 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9780 04:38:01.585591 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9781 04:38:01.592496 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9782 04:38:01.595913 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9783 04:38:01.602357 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9784 04:38:01.605848 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9785 04:38:01.609154 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9786 04:38:01.615539 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9787 04:38:01.619272 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9788 04:38:01.625505 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9789 04:38:01.629131 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9790 04:38:01.632455 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9791 04:38:01.639184 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9792 04:38:01.642123 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9793 04:38:01.649216 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9794 04:38:01.652851 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9795 04:38:01.655730 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9796 04:38:01.662729 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9797 04:38:01.665619 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9798 04:38:01.672617 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9799 04:38:01.675776 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9800 04:38:01.679317 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9801 04:38:01.686128 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9802 04:38:01.689521 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9803 04:38:01.692549 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9804 04:38:01.699207 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9805 04:38:01.702563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9806 04:38:01.709136 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9807 04:38:01.712608 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9808 04:38:01.719418 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9809 04:38:01.722695 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9810 04:38:01.725996 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9811 04:38:01.732952 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9812 04:38:01.735779 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9813 04:38:01.742648 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9814 04:38:01.746283 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9815 04:38:01.749112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9816 04:38:01.755931 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9817 04:38:01.759229 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9818 04:38:01.762855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9819 04:38:01.769030 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9820 04:38:01.772706 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9821 04:38:01.779505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9822 04:38:01.782451 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9823 04:38:01.789038 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9824 04:38:01.792514 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9825 04:38:01.795883 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9826 04:38:01.802811 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9827 04:38:01.805797 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9828 04:38:01.812633 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9829 04:38:01.815714 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9830 04:38:01.819388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9831 04:38:01.826290 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9832 04:38:01.829480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9833 04:38:01.836138 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9834 04:38:01.839625 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9835 04:38:01.842465 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9836 04:38:01.849500 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9837 04:38:01.852636 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9838 04:38:01.859178 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9839 04:38:01.862392 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9840 04:38:01.865892 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9841 04:38:01.872597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9842 04:38:01.875931 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9843 04:38:01.882658 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9844 04:38:01.886021 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9845 04:38:01.889252 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9846 04:38:01.895766 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9847 04:38:01.899267 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9848 04:38:01.906076 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9849 04:38:01.909074 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9850 04:38:01.912702 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9851 04:38:01.919176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9852 04:38:01.923068 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9853 04:38:01.929570 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9854 04:38:01.932607 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9855 04:38:01.939234 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9856 04:38:01.942584 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9857 04:38:01.945904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9858 04:38:01.952955 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9859 04:38:01.955881 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9860 04:38:01.962683 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9861 04:38:01.966345 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9862 04:38:01.969840 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9863 04:38:01.976538 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9864 04:38:01.979418 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9865 04:38:01.986246 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9866 04:38:01.989670 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9867 04:38:01.996559 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9868 04:38:01.999356 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9869 04:38:02.002820 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9870 04:38:02.009290 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9871 04:38:02.012705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9872 04:38:02.019393 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9873 04:38:02.022769 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9874 04:38:02.029770 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9875 04:38:02.033185 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9876 04:38:02.036280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9877 04:38:02.042841 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9878 04:38:02.046325 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9879 04:38:02.052900 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9880 04:38:02.056500 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9881 04:38:02.062803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9882 04:38:02.066503 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9883 04:38:02.069555 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9884 04:38:02.076270 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9885 04:38:02.079579 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9886 04:38:02.086210 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9887 04:38:02.090175 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9888 04:38:02.096539 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9889 04:38:02.100141 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9890 04:38:02.102961 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9891 04:38:02.109658 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9892 04:38:02.113054 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9893 04:38:02.119915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9894 04:38:02.123045 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9895 04:38:02.129919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9896 04:38:02.132922 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9897 04:38:02.136200 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9898 04:38:02.142781 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9899 04:38:02.146596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9900 04:38:02.152661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9901 04:38:02.156397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9902 04:38:02.159620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9903 04:38:02.166345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9904 04:38:02.169857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9905 04:38:02.176826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9906 04:38:02.179917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9907 04:38:02.186427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9908 04:38:02.189903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9909 04:38:02.196445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9910 04:38:02.199597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9911 04:38:02.206559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9912 04:38:02.210036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9913 04:38:02.216404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9914 04:38:02.220025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9915 04:38:02.226582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9916 04:38:02.230233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9917 04:38:02.236850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9918 04:38:02.239793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9919 04:38:02.243012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9920 04:38:02.250082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9921 04:38:02.253071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9922 04:38:02.259790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9923 04:38:02.263396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9924 04:38:02.269690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9925 04:38:02.273027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9926 04:38:02.279836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9927 04:38:02.283079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9928 04:38:02.289808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9929 04:38:02.293732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9930 04:38:02.299797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9931 04:38:02.303375 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9932 04:38:02.306400 INFO: [APUAPC] vio 0
9933 04:38:02.310010 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9934 04:38:02.316894 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9935 04:38:02.320413 INFO: [APUAPC] D0_APC_0: 0x400510
9936 04:38:02.323162 INFO: [APUAPC] D0_APC_1: 0x0
9937 04:38:02.326405 INFO: [APUAPC] D0_APC_2: 0x1540
9938 04:38:02.326494 INFO: [APUAPC] D0_APC_3: 0x0
9939 04:38:02.329747 INFO: [APUAPC] D1_APC_0: 0xffffffff
9940 04:38:02.333353 INFO: [APUAPC] D1_APC_1: 0xffffffff
9941 04:38:02.336648 INFO: [APUAPC] D1_APC_2: 0x3fffff
9942 04:38:02.339722 INFO: [APUAPC] D1_APC_3: 0x0
9943 04:38:02.342944 INFO: [APUAPC] D2_APC_0: 0xffffffff
9944 04:38:02.346942 INFO: [APUAPC] D2_APC_1: 0xffffffff
9945 04:38:02.349928 INFO: [APUAPC] D2_APC_2: 0x3fffff
9946 04:38:02.353289 INFO: [APUAPC] D2_APC_3: 0x0
9947 04:38:02.356845 INFO: [APUAPC] D3_APC_0: 0xffffffff
9948 04:38:02.359646 INFO: [APUAPC] D3_APC_1: 0xffffffff
9949 04:38:02.363606 INFO: [APUAPC] D3_APC_2: 0x3fffff
9950 04:38:02.366472 INFO: [APUAPC] D3_APC_3: 0x0
9951 04:38:02.369751 INFO: [APUAPC] D4_APC_0: 0xffffffff
9952 04:38:02.373153 INFO: [APUAPC] D4_APC_1: 0xffffffff
9953 04:38:02.376857 INFO: [APUAPC] D4_APC_2: 0x3fffff
9954 04:38:02.379691 INFO: [APUAPC] D4_APC_3: 0x0
9955 04:38:02.383532 INFO: [APUAPC] D5_APC_0: 0xffffffff
9956 04:38:02.386642 INFO: [APUAPC] D5_APC_1: 0xffffffff
9957 04:38:02.389923 INFO: [APUAPC] D5_APC_2: 0x3fffff
9958 04:38:02.393484 INFO: [APUAPC] D5_APC_3: 0x0
9959 04:38:02.396874 INFO: [APUAPC] D6_APC_0: 0xffffffff
9960 04:38:02.400590 INFO: [APUAPC] D6_APC_1: 0xffffffff
9961 04:38:02.403307 INFO: [APUAPC] D6_APC_2: 0x3fffff
9962 04:38:02.406765 INFO: [APUAPC] D6_APC_3: 0x0
9963 04:38:02.410029 INFO: [APUAPC] D7_APC_0: 0xffffffff
9964 04:38:02.413571 INFO: [APUAPC] D7_APC_1: 0xffffffff
9965 04:38:02.416777 INFO: [APUAPC] D7_APC_2: 0x3fffff
9966 04:38:02.419763 INFO: [APUAPC] D7_APC_3: 0x0
9967 04:38:02.423188 INFO: [APUAPC] D8_APC_0: 0xffffffff
9968 04:38:02.426975 INFO: [APUAPC] D8_APC_1: 0xffffffff
9969 04:38:02.429886 INFO: [APUAPC] D8_APC_2: 0x3fffff
9970 04:38:02.433607 INFO: [APUAPC] D8_APC_3: 0x0
9971 04:38:02.436676 INFO: [APUAPC] D9_APC_0: 0xffffffff
9972 04:38:02.439977 INFO: [APUAPC] D9_APC_1: 0xffffffff
9973 04:38:02.443722 INFO: [APUAPC] D9_APC_2: 0x3fffff
9974 04:38:02.443810 INFO: [APUAPC] D9_APC_3: 0x0
9975 04:38:02.446477 INFO: [APUAPC] D10_APC_0: 0xffffffff
9976 04:38:02.453581 INFO: [APUAPC] D10_APC_1: 0xffffffff
9977 04:38:02.457172 INFO: [APUAPC] D10_APC_2: 0x3fffff
9978 04:38:02.457264 INFO: [APUAPC] D10_APC_3: 0x0
9979 04:38:02.460275 INFO: [APUAPC] D11_APC_0: 0xffffffff
9980 04:38:02.466820 INFO: [APUAPC] D11_APC_1: 0xffffffff
9981 04:38:02.470424 INFO: [APUAPC] D11_APC_2: 0x3fffff
9982 04:38:02.470515 INFO: [APUAPC] D11_APC_3: 0x0
9983 04:38:02.473512 INFO: [APUAPC] D12_APC_0: 0xffffffff
9984 04:38:02.479790 INFO: [APUAPC] D12_APC_1: 0xffffffff
9985 04:38:02.483826 INFO: [APUAPC] D12_APC_2: 0x3fffff
9986 04:38:02.483917 INFO: [APUAPC] D12_APC_3: 0x0
9987 04:38:02.486682 INFO: [APUAPC] D13_APC_0: 0xffffffff
9988 04:38:02.493745 INFO: [APUAPC] D13_APC_1: 0xffffffff
9989 04:38:02.497300 INFO: [APUAPC] D13_APC_2: 0x3fffff
9990 04:38:02.497390 INFO: [APUAPC] D13_APC_3: 0x0
9991 04:38:02.500267 INFO: [APUAPC] D14_APC_0: 0xffffffff
9992 04:38:02.506661 INFO: [APUAPC] D14_APC_1: 0xffffffff
9993 04:38:02.510039 INFO: [APUAPC] D14_APC_2: 0x3fffff
9994 04:38:02.510126 INFO: [APUAPC] D14_APC_3: 0x0
9995 04:38:02.516542 INFO: [APUAPC] D15_APC_0: 0xffffffff
9996 04:38:02.520047 INFO: [APUAPC] D15_APC_1: 0xffffffff
9997 04:38:02.523696 INFO: [APUAPC] D15_APC_2: 0x3fffff
9998 04:38:02.523787 INFO: [APUAPC] D15_APC_3: 0x0
9999 04:38:02.526397 INFO: [APUAPC] APC_CON: 0x4
10000 04:38:02.530731 INFO: [NOCDAPC] D0_APC_0: 0x0
10001 04:38:02.533070 INFO: [NOCDAPC] D0_APC_1: 0x0
10002 04:38:02.536522 INFO: [NOCDAPC] D1_APC_0: 0x0
10003 04:38:02.540522 INFO: [NOCDAPC] D1_APC_1: 0xfff
10004 04:38:02.543309 INFO: [NOCDAPC] D2_APC_0: 0x0
10005 04:38:02.546953 INFO: [NOCDAPC] D2_APC_1: 0xfff
10006 04:38:02.549766 INFO: [NOCDAPC] D3_APC_0: 0x0
10007 04:38:02.549855 INFO: [NOCDAPC] D3_APC_1: 0xfff
10008 04:38:02.553106 INFO: [NOCDAPC] D4_APC_0: 0x0
10009 04:38:02.556927 INFO: [NOCDAPC] D4_APC_1: 0xfff
10010 04:38:02.560282 INFO: [NOCDAPC] D5_APC_0: 0x0
10011 04:38:02.563287 INFO: [NOCDAPC] D5_APC_1: 0xfff
10012 04:38:02.566777 INFO: [NOCDAPC] D6_APC_0: 0x0
10013 04:38:02.570122 INFO: [NOCDAPC] D6_APC_1: 0xfff
10014 04:38:02.573668 INFO: [NOCDAPC] D7_APC_0: 0x0
10015 04:38:02.577109 INFO: [NOCDAPC] D7_APC_1: 0xfff
10016 04:38:02.580263 INFO: [NOCDAPC] D8_APC_0: 0x0
10017 04:38:02.583611 INFO: [NOCDAPC] D8_APC_1: 0xfff
10018 04:38:02.583696 INFO: [NOCDAPC] D9_APC_0: 0x0
10019 04:38:02.587026 INFO: [NOCDAPC] D9_APC_1: 0xfff
10020 04:38:02.590504 INFO: [NOCDAPC] D10_APC_0: 0x0
10021 04:38:02.593462 INFO: [NOCDAPC] D10_APC_1: 0xfff
10022 04:38:02.596671 INFO: [NOCDAPC] D11_APC_0: 0x0
10023 04:38:02.599918 INFO: [NOCDAPC] D11_APC_1: 0xfff
10024 04:38:02.603610 INFO: [NOCDAPC] D12_APC_0: 0x0
10025 04:38:02.606942 INFO: [NOCDAPC] D12_APC_1: 0xfff
10026 04:38:02.610674 INFO: [NOCDAPC] D13_APC_0: 0x0
10027 04:38:02.613285 INFO: [NOCDAPC] D13_APC_1: 0xfff
10028 04:38:02.616635 INFO: [NOCDAPC] D14_APC_0: 0x0
10029 04:38:02.620245 INFO: [NOCDAPC] D14_APC_1: 0xfff
10030 04:38:02.623564 INFO: [NOCDAPC] D15_APC_0: 0x0
10031 04:38:02.623655 INFO: [NOCDAPC] D15_APC_1: 0xfff
10032 04:38:02.627110 INFO: [NOCDAPC] APC_CON: 0x4
10033 04:38:02.629878 INFO: [APUAPC] set_apusys_apc done
10034 04:38:02.633304 INFO: [DEVAPC] devapc_init done
10035 04:38:02.640219 INFO: GICv3 without legacy support detected.
10036 04:38:02.643635 INFO: ARM GICv3 driver initialized in EL3
10037 04:38:02.646752 INFO: Maximum SPI INTID supported: 639
10038 04:38:02.650172 INFO: BL31: Initializing runtime services
10039 04:38:02.656934 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10040 04:38:02.660025 INFO: SPM: enable CPC mode
10041 04:38:02.663340 INFO: mcdi ready for mcusys-off-idle and system suspend
10042 04:38:02.670454 INFO: BL31: Preparing for EL3 exit to normal world
10043 04:38:02.673305 INFO: Entry point address = 0x80000000
10044 04:38:02.673395 INFO: SPSR = 0x8
10045 04:38:02.679742
10046 04:38:02.679836
10047 04:38:02.679902
10048 04:38:02.683426 Starting depthcharge on Spherion...
10049 04:38:02.683512
10050 04:38:02.683578 Wipe memory regions:
10051 04:38:02.683639
10052 04:38:02.684322 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10053 04:38:02.684427 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10054 04:38:02.684512 Setting prompt string to ['asurada:']
10055 04:38:02.684593 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10056 04:38:02.686486 [0x00000040000000, 0x00000054600000)
10057 04:38:02.809184
10058 04:38:02.809360 [0x00000054660000, 0x00000080000000)
10059 04:38:03.069825
10060 04:38:03.069980 [0x000000821a7280, 0x000000ffe64000)
10061 04:38:03.814822
10062 04:38:03.814974 [0x00000100000000, 0x00000240000000)
10063 04:38:05.705134
10064 04:38:05.707961 Initializing XHCI USB controller at 0x11200000.
10065 04:38:06.746160
10066 04:38:06.749271 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10067 04:38:06.749366
10068 04:38:06.749432
10069 04:38:06.749493
10070 04:38:06.749775 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 04:38:06.850175 asurada: tftpboot 192.168.201.1 11241307/tftp-deploy-a8jao2y4/kernel/image.itb 11241307/tftp-deploy-a8jao2y4/kernel/cmdline
10073 04:38:06.850365 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 04:38:06.850485 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10075 04:38:06.855162 tftpboot 192.168.201.1 11241307/tftp-deploy-a8jao2y4/kernel/image.ittp-deploy-a8jao2y4/kernel/cmdline
10076 04:38:06.855256
10077 04:38:06.855321 Waiting for link
10078 04:38:07.015143
10079 04:38:07.015297 R8152: Initializing
10080 04:38:07.015365
10081 04:38:07.018345 Version 6 (ocp_data = 5c30)
10082 04:38:07.018445
10083 04:38:07.021645 R8152: Done initializing
10084 04:38:07.021746
10085 04:38:07.021840 Adding net device
10086 04:38:08.955772
10087 04:38:08.955945 done.
10088 04:38:08.956042
10089 04:38:08.956131 MAC: 00:24:32:30:78:52
10090 04:38:08.956218
10091 04:38:08.959188 Sending DHCP discover... done.
10092 04:38:08.959270
10093 04:38:13.014600 Waiting for reply... done.
10094 04:38:13.014832
10095 04:38:13.014913 Sending DHCP request... done.
10096 04:38:13.017792
10097 04:38:13.017873 Waiting for reply... done.
10098 04:38:13.017937
10099 04:38:13.021376 My ip is 192.168.201.14
10100 04:38:13.021470
10101 04:38:13.024410 The DHCP server ip is 192.168.201.1
10102 04:38:13.024490
10103 04:38:13.027670 TFTP server IP predefined by user: 192.168.201.1
10104 04:38:13.027750
10105 04:38:13.034554 Bootfile predefined by user: 11241307/tftp-deploy-a8jao2y4/kernel/image.itb
10106 04:38:13.034635
10107 04:38:13.037664 Sending tftp read request... done.
10108 04:38:13.037743
10109 04:38:13.041242 Waiting for the transfer...
10110 04:38:13.041326
10111 04:38:13.601562 00000000 ################################################################
10112 04:38:13.601715
10113 04:38:14.146129 00080000 ################################################################
10114 04:38:14.146305
10115 04:38:14.682138 00100000 ################################################################
10116 04:38:14.682286
10117 04:38:15.288502 00180000 ################################################################
10118 04:38:15.288679
10119 04:38:15.872738 00200000 ################################################################
10120 04:38:15.872881
10121 04:38:16.442284 00280000 ################################################################
10122 04:38:16.442431
10123 04:38:17.069693 00300000 ################################################################
10124 04:38:17.070210
10125 04:38:17.735687 00380000 ################################################################
10126 04:38:17.735825
10127 04:38:18.391938 00400000 ################################################################
10128 04:38:18.392601
10129 04:38:18.977779 00480000 ################################################################
10130 04:38:18.977958
10131 04:38:19.568187 00500000 ################################################################
10132 04:38:19.568324
10133 04:38:20.171743 00580000 ################################################################
10134 04:38:20.171963
10135 04:38:20.775998 00600000 ################################################################
10136 04:38:20.776189
10137 04:38:21.429373 00680000 ################################################################
10138 04:38:21.429510
10139 04:38:21.992543 00700000 ################################################################
10140 04:38:21.992747
10141 04:38:22.559913 00780000 ################################################################
10142 04:38:22.560046
10143 04:38:23.129651 00800000 ################################################################
10144 04:38:23.130117
10145 04:38:23.799930 00880000 ################################################################
10146 04:38:23.800515
10147 04:38:24.476748 00900000 ################################################################
10148 04:38:24.477253
10149 04:38:25.050652 00980000 ################################################################
10150 04:38:25.050799
10151 04:38:25.597191 00a00000 ################################################################
10152 04:38:25.597336
10153 04:38:26.150442 00a80000 ################################################################
10154 04:38:26.150594
10155 04:38:26.693833 00b00000 ################################################################
10156 04:38:26.693977
10157 04:38:27.230773 00b80000 ################################################################
10158 04:38:27.230909
10159 04:38:27.760165 00c00000 ################################################################
10160 04:38:27.760300
10161 04:38:28.278516 00c80000 ################################################################
10162 04:38:28.278655
10163 04:38:28.798912 00d00000 ################################################################
10164 04:38:28.799041
10165 04:38:29.379943 00d80000 ################################################################
10166 04:38:29.380078
10167 04:38:29.898451 00e00000 ################################################################
10168 04:38:29.898584
10169 04:38:30.421443 00e80000 ################################################################
10170 04:38:30.421570
10171 04:38:30.944815 00f00000 ################################################################
10172 04:38:30.944946
10173 04:38:31.465461 00f80000 ################################################################
10174 04:38:31.465592
10175 04:38:31.999066 01000000 ################################################################
10176 04:38:31.999221
10177 04:38:32.534205 01080000 ################################################################
10178 04:38:32.534331
10179 04:38:33.053349 01100000 ################################################################
10180 04:38:33.053490
10181 04:38:33.606861 01180000 ################################################################
10182 04:38:33.607009
10183 04:38:34.129466 01200000 ################################################################
10184 04:38:34.129600
10185 04:38:34.652631 01280000 ################################################################
10186 04:38:34.652772
10187 04:38:35.173859 01300000 ################################################################
10188 04:38:35.173993
10189 04:38:35.693336 01380000 ################################################################
10190 04:38:35.693464
10191 04:38:36.213588 01400000 ################################################################
10192 04:38:36.213722
10193 04:38:36.762995 01480000 ################################################################
10194 04:38:36.763132
10195 04:38:37.299110 01500000 ################################################################
10196 04:38:37.299241
10197 04:38:37.821577 01580000 ################################################################
10198 04:38:37.821707
10199 04:38:38.345277 01600000 ################################################################
10200 04:38:38.345414
10201 04:38:38.867084 01680000 ################################################################
10202 04:38:38.867218
10203 04:38:39.387752 01700000 ################################################################
10204 04:38:39.387885
10205 04:38:39.910664 01780000 ################################################################
10206 04:38:39.910795
10207 04:38:40.432441 01800000 ################################################################
10208 04:38:40.432619
10209 04:38:40.954310 01880000 ################################################################
10210 04:38:40.954442
10211 04:38:41.474856 01900000 ################################################################
10212 04:38:41.475021
10213 04:38:42.024781 01980000 ################################################################
10214 04:38:42.024919
10215 04:38:42.654959 01a00000 ################################################################
10216 04:38:42.655109
10217 04:38:43.260019 01a80000 ################################################################
10218 04:38:43.260181
10219 04:38:43.868064 01b00000 ################################################################
10220 04:38:43.868238
10221 04:38:44.496914 01b80000 ################################################################
10222 04:38:44.497050
10223 04:38:45.098160 01c00000 ################################################################
10224 04:38:45.098291
10225 04:38:45.699669 01c80000 ################################################################
10226 04:38:45.699831
10227 04:38:46.292613 01d00000 ################################################################
10228 04:38:46.292784
10229 04:38:46.961955 01d80000 ################################################################
10230 04:38:46.962439
10231 04:38:47.603819 01e00000 ################################################################
10232 04:38:47.604295
10233 04:38:48.018874 01e80000 ########################################### done.
10234 04:38:48.019015
10235 04:38:48.022096 The bootfile was 32327258 bytes long.
10236 04:38:48.022177
10237 04:38:48.025113 Sending tftp read request... done.
10238 04:38:48.025199
10239 04:38:48.028521 Waiting for the transfer...
10240 04:38:48.028626
10241 04:38:48.028750 00000000 # done.
10242 04:38:48.028813
10243 04:38:48.038885 Command line loaded dynamically from TFTP file: 11241307/tftp-deploy-a8jao2y4/kernel/cmdline
10244 04:38:48.038966
10245 04:38:48.052314 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10246 04:38:48.052405
10247 04:38:48.052473 Loading FIT.
10248 04:38:48.052537
10249 04:38:48.055488 Image ramdisk-1 has 21241578 bytes.
10250 04:38:48.055573
10251 04:38:48.058884 Image fdt-1 has 47278 bytes.
10252 04:38:48.058976
10253 04:38:48.062292 Image kernel-1 has 11036366 bytes.
10254 04:38:48.062392
10255 04:38:48.069396 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10256 04:38:48.072415
10257 04:38:48.089156 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10258 04:38:48.089418
10259 04:38:48.092481 Choosing best match conf-1 for compat google,spherion-rev2.
10260 04:38:48.098099
10261 04:38:48.102594 Connected to device vid:did:rid of 1ae0:0028:00
10262 04:38:48.110947
10263 04:38:48.114276 tpm_get_response: command 0x17b, return code 0x0
10264 04:38:48.114743
10265 04:38:48.117671 ec_init: CrosEC protocol v3 supported (256, 248)
10266 04:38:48.122439
10267 04:38:48.125521 tpm_cleanup: add release locality here.
10268 04:38:48.125975
10269 04:38:48.126337 Shutting down all USB controllers.
10270 04:38:48.128538
10271 04:38:48.129043 Removing current net device
10272 04:38:48.129408
10273 04:38:48.135137 Exiting depthcharge with code 4 at timestamp: 74820019
10274 04:38:48.135679
10275 04:38:48.138605 LZMA decompressing kernel-1 to 0x821a6718
10276 04:38:48.139059
10277 04:38:48.142074 LZMA decompressing kernel-1 to 0x40000000
10278 04:38:49.530372
10279 04:38:49.531080 jumping to kernel
10280 04:38:49.533299 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10281 04:38:49.533901 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10282 04:38:49.534316 Setting prompt string to ['Linux version [0-9]']
10283 04:38:49.534693 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10284 04:38:49.535082 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10285 04:38:49.611759
10286 04:38:49.615035 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10287 04:38:49.618593 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10288 04:38:49.619093 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10289 04:38:49.619570 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10290 04:38:49.619994 Using line separator: #'\n'#
10291 04:38:49.620339 No login prompt set.
10292 04:38:49.620718 Parsing kernel messages
10293 04:38:49.621065 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10294 04:38:49.622003 [login-action] Waiting for messages, (timeout 00:03:38)
10295 04:38:49.638444 [ 0.000000] Linux version 6.1.42-cip2 (KernelCI@build-j7071-arm64-gcc-10-defconfig-arm64-chromebook-7p24g) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 9 04:18:34 UTC 2023
10296 04:38:49.641552 [ 0.000000] random: crng init done
10297 04:38:49.645034 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10298 04:38:49.647907 [ 0.000000] efi: UEFI not found.
10299 04:38:49.658294 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10300 04:38:49.664759 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10301 04:38:49.674934 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10302 04:38:49.684755 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10303 04:38:49.691425 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10304 04:38:49.694823 [ 0.000000] printk: bootconsole [mtk8250] enabled
10305 04:38:49.702998 [ 0.000000] NUMA: No NUMA configuration found
10306 04:38:49.709806 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10307 04:38:49.716428 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10308 04:38:49.716808 [ 0.000000] Zone ranges:
10309 04:38:49.723245 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10310 04:38:49.726460 [ 0.000000] DMA32 empty
10311 04:38:49.733275 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10312 04:38:49.736474 [ 0.000000] Movable zone start for each node
10313 04:38:49.740179 [ 0.000000] Early memory node ranges
10314 04:38:49.746494 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10315 04:38:49.753424 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10316 04:38:49.759752 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10317 04:38:49.766468 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10318 04:38:49.773688 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10319 04:38:49.779840 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10320 04:38:49.836423 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10321 04:38:49.842779 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10322 04:38:49.849258 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10323 04:38:49.852927 [ 0.000000] psci: probing for conduit method from DT.
10324 04:38:49.859589 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10325 04:38:49.862890 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10326 04:38:49.870000 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10327 04:38:49.872981 [ 0.000000] psci: SMC Calling Convention v1.2
10328 04:38:49.879957 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10329 04:38:49.882920 [ 0.000000] Detected VIPT I-cache on CPU0
10330 04:38:49.889600 [ 0.000000] CPU features: detected: GIC system register CPU interface
10331 04:38:49.896162 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10332 04:38:49.902707 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10333 04:38:49.909445 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10334 04:38:49.916198 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10335 04:38:49.922780 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10336 04:38:49.929388 [ 0.000000] alternatives: applying boot alternatives
10337 04:38:49.933064 [ 0.000000] Fallback order for Node 0: 0
10338 04:38:49.939178 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10339 04:38:49.942517 [ 0.000000] Policy zone: Normal
10340 04:38:49.959464 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10341 04:38:49.969514 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10342 04:38:49.980402 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10343 04:38:49.990423 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10344 04:38:49.996718 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10345 04:38:50.000347 <6>[ 0.000000] software IO TLB: area num 8.
10346 04:38:50.056836 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10347 04:38:50.206492 <6>[ 0.000000] Memory: 7948808K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 403960K reserved, 32768K cma-reserved)
10348 04:38:50.213216 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10349 04:38:50.219550 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10350 04:38:50.223042 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10351 04:38:50.229403 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10352 04:38:50.236154 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10353 04:38:50.239795 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10354 04:38:50.249393 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10355 04:38:50.255830 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10356 04:38:50.259073 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10357 04:38:50.267018 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10358 04:38:50.270602 <6>[ 0.000000] GICv3: 608 SPIs implemented
10359 04:38:50.277223 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10360 04:38:50.280401 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10361 04:38:50.283893 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10362 04:38:50.290488 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10363 04:38:50.303943 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10364 04:38:50.317294 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10365 04:38:50.324115 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10366 04:38:50.332381 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10367 04:38:50.345965 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10368 04:38:50.352415 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10369 04:38:50.359091 <6>[ 0.009177] Console: colour dummy device 80x25
10370 04:38:50.369023 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10371 04:38:50.372396 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10372 04:38:50.378787 <6>[ 0.029248] LSM: Security Framework initializing
10373 04:38:50.385456 <6>[ 0.034217] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10374 04:38:50.395740 <6>[ 0.042029] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10375 04:38:50.402169 <6>[ 0.051456] cblist_init_generic: Setting adjustable number of callback queues.
10376 04:38:50.409216 <6>[ 0.058902] cblist_init_generic: Setting shift to 3 and lim to 1.
10377 04:38:50.419227 <6>[ 0.065241] cblist_init_generic: Setting adjustable number of callback queues.
10378 04:38:50.422247 <6>[ 0.072712] cblist_init_generic: Setting shift to 3 and lim to 1.
10379 04:38:50.428827 <6>[ 0.079110] rcu: Hierarchical SRCU implementation.
10380 04:38:50.435635 <6>[ 0.084124] rcu: Max phase no-delay instances is 1000.
10381 04:38:50.441934 <6>[ 0.091190] EFI services will not be available.
10382 04:38:50.445495 <6>[ 0.096164] smp: Bringing up secondary CPUs ...
10383 04:38:50.453300 <6>[ 0.101213] Detected VIPT I-cache on CPU1
10384 04:38:50.459761 <6>[ 0.101283] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10385 04:38:50.466494 <6>[ 0.101312] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10386 04:38:50.469338 <6>[ 0.101646] Detected VIPT I-cache on CPU2
10387 04:38:50.476069 <6>[ 0.101700] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10388 04:38:50.483089 <6>[ 0.101718] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10389 04:38:50.489505 <6>[ 0.101977] Detected VIPT I-cache on CPU3
10390 04:38:50.496081 <6>[ 0.102027] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10391 04:38:50.503333 <6>[ 0.102041] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10392 04:38:50.505885 <6>[ 0.102343] CPU features: detected: Spectre-v4
10393 04:38:50.512526 <6>[ 0.102350] CPU features: detected: Spectre-BHB
10394 04:38:50.515965 <6>[ 0.102356] Detected PIPT I-cache on CPU4
10395 04:38:50.522595 <6>[ 0.102413] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10396 04:38:50.529297 <6>[ 0.102429] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10397 04:38:50.532880 <6>[ 0.102722] Detected PIPT I-cache on CPU5
10398 04:38:50.542999 <6>[ 0.102785] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10399 04:38:50.549339 <6>[ 0.102801] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10400 04:38:50.552367 <6>[ 0.103083] Detected PIPT I-cache on CPU6
10401 04:38:50.559554 <6>[ 0.103140] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10402 04:38:50.565768 <6>[ 0.103156] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10403 04:38:50.569233 <6>[ 0.103439] Detected PIPT I-cache on CPU7
10404 04:38:50.579092 <6>[ 0.103497] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10405 04:38:50.585839 <6>[ 0.103513] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10406 04:38:50.589398 <6>[ 0.103559] smp: Brought up 1 node, 8 CPUs
10407 04:38:50.592313 <6>[ 0.244831] SMP: Total of 8 processors activated.
10408 04:38:50.599199 <6>[ 0.249753] CPU features: detected: 32-bit EL0 Support
10409 04:38:50.609062 <6>[ 0.255115] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10410 04:38:50.615691 <6>[ 0.263969] CPU features: detected: Common not Private translations
10411 04:38:50.618843 <6>[ 0.270445] CPU features: detected: CRC32 instructions
10412 04:38:50.625759 <6>[ 0.275814] CPU features: detected: RCpc load-acquire (LDAPR)
10413 04:38:50.632452 <6>[ 0.281773] CPU features: detected: LSE atomic instructions
10414 04:38:50.638776 <6>[ 0.287591] CPU features: detected: Privileged Access Never
10415 04:38:50.642369 <6>[ 0.293370] CPU features: detected: RAS Extension Support
10416 04:38:50.649028 <6>[ 0.299013] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10417 04:38:50.656044 <6>[ 0.306234] CPU: All CPU(s) started at EL2
10418 04:38:50.661986 <6>[ 0.310577] alternatives: applying system-wide alternatives
10419 04:38:50.670403 <6>[ 0.321255] devtmpfs: initialized
10420 04:38:50.682791 <6>[ 0.330347] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10421 04:38:50.692790 <6>[ 0.340312] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10422 04:38:50.699465 <6>[ 0.348334] pinctrl core: initialized pinctrl subsystem
10423 04:38:50.703008 <6>[ 0.354936] DMI not present or invalid.
10424 04:38:50.709515 <6>[ 0.359350] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10425 04:38:50.716313 <6>[ 0.366204] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10426 04:38:50.726472 <6>[ 0.373788] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10427 04:38:50.733536 <6>[ 0.382000] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10428 04:38:50.739814 <6>[ 0.390241] audit: initializing netlink subsys (disabled)
10429 04:38:50.746737 <5>[ 0.395937] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10430 04:38:50.753421 <6>[ 0.396643] thermal_sys: Registered thermal governor 'step_wise'
10431 04:38:50.759922 <6>[ 0.403899] thermal_sys: Registered thermal governor 'power_allocator'
10432 04:38:50.766455 <6>[ 0.410156] cpuidle: using governor menu
10433 04:38:50.769960 <6>[ 0.421120] NET: Registered PF_QIPCRTR protocol family
10434 04:38:50.777077 <6>[ 0.426602] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10435 04:38:50.783441 <6>[ 0.433709] ASID allocator initialised with 32768 entries
10436 04:38:50.790009 <6>[ 0.440271] Serial: AMBA PL011 UART driver
10437 04:38:50.798047 <4>[ 0.449045] Trying to register duplicate clock ID: 134
10438 04:38:50.855043 <6>[ 0.508907] KASLR enabled
10439 04:38:50.869690 <6>[ 0.516642] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10440 04:38:50.876346 <6>[ 0.523653] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10441 04:38:50.882924 <6>[ 0.530142] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10442 04:38:50.889880 <6>[ 0.537146] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10443 04:38:50.895937 <6>[ 0.543635] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10444 04:38:50.903025 <6>[ 0.550640] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10445 04:38:50.909445 <6>[ 0.557130] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10446 04:38:50.915823 <6>[ 0.564131] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10447 04:38:50.919139 <6>[ 0.571643] ACPI: Interpreter disabled.
10448 04:38:50.927847 <6>[ 0.578067] iommu: Default domain type: Translated
10449 04:38:50.934597 <6>[ 0.583181] iommu: DMA domain TLB invalidation policy: strict mode
10450 04:38:50.937764 <5>[ 0.589834] SCSI subsystem initialized
10451 04:38:50.944349 <6>[ 0.593998] usbcore: registered new interface driver usbfs
10452 04:38:50.950989 <6>[ 0.599735] usbcore: registered new interface driver hub
10453 04:38:50.954219 <6>[ 0.605289] usbcore: registered new device driver usb
10454 04:38:50.961027 <6>[ 0.611386] pps_core: LinuxPPS API ver. 1 registered
10455 04:38:50.971034 <6>[ 0.616580] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10456 04:38:50.974074 <6>[ 0.625929] PTP clock support registered
10457 04:38:50.977375 <6>[ 0.630171] EDAC MC: Ver: 3.0.0
10458 04:38:50.985084 <6>[ 0.635327] FPGA manager framework
10459 04:38:50.988163 <6>[ 0.639008] Advanced Linux Sound Architecture Driver Initialized.
10460 04:38:50.992202 <6>[ 0.645786] vgaarb: loaded
10461 04:38:50.998733 <6>[ 0.648955] clocksource: Switched to clocksource arch_sys_counter
10462 04:38:51.005445 <5>[ 0.655388] VFS: Disk quotas dquot_6.6.0
10463 04:38:51.012216 <6>[ 0.659569] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10464 04:38:51.015499 <6>[ 0.666757] pnp: PnP ACPI: disabled
10465 04:38:51.022872 <6>[ 0.673422] NET: Registered PF_INET protocol family
10466 04:38:51.032732 <6>[ 0.679012] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10467 04:38:51.044242 <6>[ 0.691313] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10468 04:38:51.054350 <6>[ 0.700125] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10469 04:38:51.060787 <6>[ 0.708096] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10470 04:38:51.068031 <6>[ 0.716799] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10471 04:38:51.079820 <6>[ 0.726554] TCP: Hash tables configured (established 65536 bind 65536)
10472 04:38:51.086443 <6>[ 0.733413] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10473 04:38:51.093092 <6>[ 0.740611] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10474 04:38:51.099856 <6>[ 0.748313] NET: Registered PF_UNIX/PF_LOCAL protocol family
10475 04:38:51.106169 <6>[ 0.754500] RPC: Registered named UNIX socket transport module.
10476 04:38:51.109694 <6>[ 0.760650] RPC: Registered udp transport module.
10477 04:38:51.116268 <6>[ 0.765582] RPC: Registered tcp transport module.
10478 04:38:51.123306 <6>[ 0.770517] RPC: Registered tcp NFSv4.1 backchannel transport module.
10479 04:38:51.126413 <6>[ 0.777188] PCI: CLS 0 bytes, default 64
10480 04:38:51.130058 <6>[ 0.781577] Unpacking initramfs...
10481 04:38:51.153993 <6>[ 0.801071] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10482 04:38:51.164099 <6>[ 0.809739] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10483 04:38:51.167628 <6>[ 0.818589] kvm [1]: IPA Size Limit: 40 bits
10484 04:38:51.174180 <6>[ 0.823113] kvm [1]: GICv3: no GICV resource entry
10485 04:38:51.177164 <6>[ 0.828133] kvm [1]: disabling GICv2 emulation
10486 04:38:51.183838 <6>[ 0.832818] kvm [1]: GIC system register CPU interface enabled
10487 04:38:51.187486 <6>[ 0.838992] kvm [1]: vgic interrupt IRQ18
10488 04:38:51.194053 <6>[ 0.843348] kvm [1]: VHE mode initialized successfully
10489 04:38:51.201142 <5>[ 0.849933] Initialise system trusted keyrings
10490 04:38:51.207558 <6>[ 0.854756] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10491 04:38:51.215381 <6>[ 0.865020] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10492 04:38:51.221520 <5>[ 0.871429] NFS: Registering the id_resolver key type
10493 04:38:51.224847 <5>[ 0.876737] Key type id_resolver registered
10494 04:38:51.231244 <5>[ 0.881153] Key type id_legacy registered
10495 04:38:51.237906 <6>[ 0.885433] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10496 04:38:51.244808 <6>[ 0.892350] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10497 04:38:51.251583 <6>[ 0.900073] 9p: Installing v9fs 9p2000 file system support
10498 04:38:51.287678 <5>[ 0.938076] Key type asymmetric registered
10499 04:38:51.290746 <5>[ 0.942416] Asymmetric key parser 'x509' registered
10500 04:38:51.301211 <6>[ 0.947566] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10501 04:38:51.304446 <6>[ 0.955179] io scheduler mq-deadline registered
10502 04:38:51.307540 <6>[ 0.959940] io scheduler kyber registered
10503 04:38:51.326439 <6>[ 0.977016] EINJ: ACPI disabled.
10504 04:38:51.359711 <4>[ 1.003102] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10505 04:38:51.369249 <4>[ 1.013763] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10506 04:38:51.384437 <6>[ 1.034548] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10507 04:38:51.392498 <6>[ 1.042510] printk: console [ttyS0] disabled
10508 04:38:51.420378 <6>[ 1.067161] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10509 04:38:51.427038 <6>[ 1.076637] printk: console [ttyS0] enabled
10510 04:38:51.430153 <6>[ 1.076637] printk: console [ttyS0] enabled
10511 04:38:51.437065 <6>[ 1.085531] printk: bootconsole [mtk8250] disabled
10512 04:38:51.440082 <6>[ 1.085531] printk: bootconsole [mtk8250] disabled
10513 04:38:51.447237 <6>[ 1.096811] SuperH (H)SCI(F) driver initialized
10514 04:38:51.449851 <6>[ 1.102101] msm_serial: driver initialized
10515 04:38:51.464615 <6>[ 1.111169] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10516 04:38:51.474258 <6>[ 1.119718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10517 04:38:51.481008 <6>[ 1.128262] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10518 04:38:51.491043 <6>[ 1.136890] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10519 04:38:51.497732 <6>[ 1.145599] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10520 04:38:51.507721 <6>[ 1.154314] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10521 04:38:51.517495 <6>[ 1.162854] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10522 04:38:51.524198 <6>[ 1.171658] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10523 04:38:51.533898 <6>[ 1.180204] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10524 04:38:51.545659 <6>[ 1.195950] loop: module loaded
10525 04:38:51.552215 <6>[ 1.202050] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10526 04:38:51.574974 <4>[ 1.225469] mtk-pmic-keys: Failed to locate of_node [id: -1]
10527 04:38:51.581971 <6>[ 1.232502] megasas: 07.719.03.00-rc1
10528 04:38:51.592122 <6>[ 1.242400] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10529 04:38:51.599234 <6>[ 1.248340] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10530 04:38:51.614643 <6>[ 1.264908] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10531 04:38:51.671223 <6>[ 1.315058] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10532 04:38:52.021764 <6>[ 1.671896] Freeing initrd memory: 20740K
10533 04:38:52.037014 <6>[ 1.687750] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10534 04:38:52.048042 <6>[ 1.698798] tun: Universal TUN/TAP device driver, 1.6
10535 04:38:52.051898 <6>[ 1.704878] thunder_xcv, ver 1.0
10536 04:38:52.055019 <6>[ 1.708384] thunder_bgx, ver 1.0
10537 04:38:52.058394 <6>[ 1.711883] nicpf, ver 1.0
10538 04:38:52.068798 <6>[ 1.715919] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10539 04:38:52.072018 <6>[ 1.723394] hns3: Copyright (c) 2017 Huawei Corporation.
10540 04:38:52.075659 <6>[ 1.728984] hclge is initializing
10541 04:38:52.082408 <6>[ 1.732561] e1000: Intel(R) PRO/1000 Network Driver
10542 04:38:52.088768 <6>[ 1.737691] e1000: Copyright (c) 1999-2006 Intel Corporation.
10543 04:38:52.092214 <6>[ 1.743704] e1000e: Intel(R) PRO/1000 Network Driver
10544 04:38:52.099152 <6>[ 1.748919] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10545 04:38:52.106165 <6>[ 1.755103] igb: Intel(R) Gigabit Ethernet Network Driver
10546 04:38:52.112135 <6>[ 1.760753] igb: Copyright (c) 2007-2014 Intel Corporation.
10547 04:38:52.119027 <6>[ 1.766590] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10548 04:38:52.121936 <6>[ 1.773108] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10549 04:38:52.129542 <6>[ 1.779575] sky2: driver version 1.30
10550 04:38:52.135758 <6>[ 1.784574] VFIO - User Level meta-driver version: 0.3
10551 04:38:52.142515 <6>[ 1.792852] usbcore: registered new interface driver usb-storage
10552 04:38:52.149161 <6>[ 1.799308] usbcore: registered new device driver onboard-usb-hub
10553 04:38:52.158333 <6>[ 1.808431] mt6397-rtc mt6359-rtc: registered as rtc0
10554 04:38:52.168399 <6>[ 1.813894] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-09T04:38:51 UTC (1691555931)
10555 04:38:52.171394 <6>[ 1.823496] i2c_dev: i2c /dev entries driver
10556 04:38:52.188018 <6>[ 1.835362] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10557 04:38:52.208994 <6>[ 1.859366] cpu cpu0: EM: created perf domain
10558 04:38:52.211863 <6>[ 1.864384] cpu cpu4: EM: created perf domain
10559 04:38:52.219805 <6>[ 1.870062] sdhci: Secure Digital Host Controller Interface driver
10560 04:38:52.226442 <6>[ 1.876495] sdhci: Copyright(c) Pierre Ossman
10561 04:38:52.232760 <6>[ 1.881451] Synopsys Designware Multimedia Card Interface Driver
10562 04:38:52.239850 <6>[ 1.888107] sdhci-pltfm: SDHCI platform and OF driver helper
10563 04:38:52.243051 <6>[ 1.888215] mmc0: CQHCI version 5.10
10564 04:38:52.249908 <6>[ 1.898082] ledtrig-cpu: registered to indicate activity on CPUs
10565 04:38:52.256645 <6>[ 1.905123] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10566 04:38:52.263547 <6>[ 1.912186] usbcore: registered new interface driver usbhid
10567 04:38:52.266595 <6>[ 1.918007] usbhid: USB HID core driver
10568 04:38:52.273147 <6>[ 1.922201] spi_master spi0: will run message pump with realtime priority
10569 04:38:52.317029 <6>[ 1.960297] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10570 04:38:52.336086 <6>[ 1.976120] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10571 04:38:52.342834 <6>[ 1.992430] cros-ec-spi spi0.0: Chrome EC device registered
10572 04:38:52.346782 <6>[ 1.998466] mmc0: Command Queue Engine enabled
10573 04:38:52.352909 <6>[ 2.003217] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10574 04:38:52.360549 <6>[ 2.010901] mmcblk0: mmc0:0001 DA4128 116 GiB
10575 04:38:52.370358 <6>[ 2.021252] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10576 04:38:52.380466 <6>[ 2.026176] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10577 04:38:52.387533 <6>[ 2.028669] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10578 04:38:52.390601 <6>[ 2.037715] NET: Registered PF_PACKET protocol family
10579 04:38:52.397383 <6>[ 2.042421] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10580 04:38:52.400482 <6>[ 2.047097] 9pnet: Installing 9P2000 support
10581 04:38:52.407222 <6>[ 2.053074] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10582 04:38:52.413586 <5>[ 2.056797] Key type dns_resolver registered
10583 04:38:52.416901 <6>[ 2.068211] registered taskstats version 1
10584 04:38:52.420273 <5>[ 2.072597] Loading compiled-in X.509 certificates
10585 04:38:52.451267 <4>[ 2.095250] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 04:38:52.461271 <4>[ 2.105981] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 04:38:52.468561 <3>[ 2.116536] debugfs: File 'uA_load' in directory '/' already present!
10588 04:38:52.475172 <3>[ 2.123255] debugfs: File 'min_uV' in directory '/' already present!
10589 04:38:52.481802 <3>[ 2.129923] debugfs: File 'max_uV' in directory '/' already present!
10590 04:38:52.488328 <3>[ 2.136623] debugfs: File 'constraint_flags' in directory '/' already present!
10591 04:38:52.499056 <3>[ 2.146310] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10592 04:38:52.510097 <6>[ 2.160698] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10593 04:38:52.517419 <6>[ 2.167503] xhci-mtk 11200000.usb: xHCI Host Controller
10594 04:38:52.523801 <6>[ 2.172995] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10595 04:38:52.533751 <6>[ 2.180836] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10596 04:38:52.540649 <6>[ 2.190255] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10597 04:38:52.546790 <6>[ 2.196328] xhci-mtk 11200000.usb: xHCI Host Controller
10598 04:38:52.553485 <6>[ 2.201807] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10599 04:38:52.560382 <6>[ 2.209454] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10600 04:38:52.566875 <6>[ 2.217173] hub 1-0:1.0: USB hub found
10601 04:38:52.570442 <6>[ 2.221185] hub 1-0:1.0: 1 port detected
10602 04:38:52.577068 <6>[ 2.225452] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10603 04:38:52.583605 <6>[ 2.234186] hub 2-0:1.0: USB hub found
10604 04:38:52.586848 <6>[ 2.238213] hub 2-0:1.0: 1 port detected
10605 04:38:52.595776 <6>[ 2.246239] mtk-msdc 11f70000.mmc: Got CD GPIO
10606 04:38:52.607061 <6>[ 2.254380] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10607 04:38:52.613900 <6>[ 2.262413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10608 04:38:52.623992 <4>[ 2.270324] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10609 04:38:52.633686 <6>[ 2.279857] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10610 04:38:52.639826 <6>[ 2.287933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10611 04:38:52.646819 <6>[ 2.295951] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10612 04:38:52.657443 <6>[ 2.303888] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10613 04:38:52.663558 <6>[ 2.311704] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10614 04:38:52.673879 <6>[ 2.319521] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10615 04:38:52.683559 <6>[ 2.329918] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10616 04:38:52.690138 <6>[ 2.338303] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10617 04:38:52.700365 <6>[ 2.346648] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10618 04:38:52.706785 <6>[ 2.354987] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10619 04:38:52.716544 <6>[ 2.363325] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10620 04:38:52.723442 <6>[ 2.371663] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10621 04:38:52.733813 <6>[ 2.380001] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10622 04:38:52.740006 <6>[ 2.388339] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10623 04:38:52.750085 <6>[ 2.396677] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10624 04:38:52.756791 <6>[ 2.405014] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10625 04:38:52.766740 <6>[ 2.413351] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10626 04:38:52.773283 <6>[ 2.421689] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10627 04:38:52.783269 <6>[ 2.430027] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10628 04:38:52.790123 <6>[ 2.438366] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10629 04:38:52.800190 <6>[ 2.446704] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10630 04:38:52.806621 <6>[ 2.455445] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10631 04:38:52.813670 <6>[ 2.462594] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10632 04:38:52.820157 <6>[ 2.469350] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10633 04:38:52.826850 <6>[ 2.476122] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10634 04:38:52.833916 <6>[ 2.483050] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10635 04:38:52.843387 <6>[ 2.489894] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10636 04:38:52.853522 <6>[ 2.499035] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10637 04:38:52.863626 <6>[ 2.508154] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10638 04:38:52.870269 <6>[ 2.517449] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10639 04:38:52.880154 <6>[ 2.526917] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10640 04:38:52.890137 <6>[ 2.536385] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10641 04:38:52.899976 <6>[ 2.545505] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10642 04:38:52.910288 <6>[ 2.554972] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10643 04:38:52.916968 <6>[ 2.564092] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10644 04:38:52.926718 <6>[ 2.573386] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10645 04:38:52.936895 <6>[ 2.583547] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10646 04:38:52.948220 <6>[ 2.595378] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10647 04:38:53.002184 <6>[ 2.649232] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10648 04:38:53.156730 <6>[ 2.807328] hub 1-1:1.0: USB hub found
10649 04:38:53.159894 <6>[ 2.811839] hub 1-1:1.0: 4 ports detected
10650 04:38:53.282040 <6>[ 2.929610] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10651 04:38:53.308098 <6>[ 2.958686] hub 2-1:1.0: USB hub found
10652 04:38:53.311269 <6>[ 2.963182] hub 2-1:1.0: 3 ports detected
10653 04:38:53.481522 <6>[ 3.129218] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10654 04:38:53.614048 <6>[ 3.264452] hub 1-1.4:1.0: USB hub found
10655 04:38:53.617386 <6>[ 3.269009] hub 1-1.4:1.0: 2 ports detected
10656 04:38:53.693877 <6>[ 3.341401] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10657 04:38:53.914357 <6>[ 3.561275] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10658 04:38:54.106700 <6>[ 3.753257] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10659 04:39:05.238385 <6>[ 14.894177] ALSA device list:
10660 04:39:05.245008 <6>[ 14.897461] No soundcards found.
10661 04:39:05.253085 <6>[ 14.905312] Freeing unused kernel memory: 8384K
10662 04:39:05.256458 <6>[ 14.910291] Run /init as init process
10663 04:39:05.281439 Starting syslogd: OK
10664 04:39:05.287000 Starting klogd: OK
10665 04:39:05.295460 Running sysctl: OK
10666 04:39:05.305469 Populating /dev using udev: <30>[ 14.956815] udevd[186]: starting version 3.2.9
10667 04:39:05.312213 <27>[ 14.964586] udevd[186]: specified user 'tss' unknown
10668 04:39:05.318992 <27>[ 14.970010] udevd[186]: specified group 'tss' unknown
10669 04:39:05.322178 <30>[ 14.976401] udevd[187]: starting eudev-3.2.9
10670 04:39:05.343898 <27>[ 14.996672] udevd[187]: specified user 'tss' unknown
10671 04:39:05.350999 <27>[ 15.002043] udevd[187]: specified group 'tss' unknown
10672 04:39:05.458511 <6>[ 15.107940] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10673 04:39:05.483506 <6>[ 15.135872] remoteproc remoteproc0: scp is available
10674 04:39:05.491717 <6>[ 15.144063] remoteproc remoteproc0: powering up scp
10675 04:39:05.501517 <6>[ 15.150139] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10676 04:39:05.508460 <6>[ 15.159134] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10677 04:39:05.514863 <6>[ 15.166632] mc: Linux media interface: v0.10
10678 04:39:05.521546 <6>[ 15.166975] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10679 04:39:05.531692 <6>[ 15.178806] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10680 04:39:05.538017 <6>[ 15.187554] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10681 04:39:05.544540 <6>[ 15.196761] videodev: Linux video capture interface: v2.00
10682 04:39:05.551238 <4>[ 15.198127] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10683 04:39:05.561012 <3>[ 15.201054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 04:39:05.568119 <3>[ 15.201075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 04:39:05.577923 <3>[ 15.201084] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 04:39:05.584242 <3>[ 15.201146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 04:39:05.594245 <3>[ 15.201154] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 04:39:05.601294 <3>[ 15.201162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 04:39:05.607353 <3>[ 15.201171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 04:39:05.617309 <3>[ 15.201178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 04:39:05.624311 <3>[ 15.201210] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 04:39:05.634216 <3>[ 15.201252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 04:39:05.640997 <3>[ 15.201260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 04:39:05.648257 <3>[ 15.201267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 04:39:05.657994 <3>[ 15.201325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 04:39:05.664731 <3>[ 15.201334] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 04:39:05.674530 <3>[ 15.201340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 04:39:05.681568 <3>[ 15.201348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 04:39:05.691543 <3>[ 15.201354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 04:39:05.698133 <3>[ 15.201381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 04:39:05.704927 <6>[ 15.224588] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10702 04:39:05.714962 <4>[ 15.226650] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10703 04:39:05.718672 <6>[ 15.234999] usbcore: registered new interface driver r8152
10704 04:39:05.727982 <4>[ 15.250970] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10705 04:39:05.731572 <4>[ 15.250970] Fallback method does not support PEC.
10706 04:39:05.741444 <6>[ 15.288824] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10707 04:39:05.747771 <6>[ 15.288825] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10708 04:39:05.757688 <3>[ 15.306401] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10709 04:39:05.764972 <6>[ 15.307217] remoteproc remoteproc0: remote processor scp is now up
10710 04:39:05.770911 <6>[ 15.318383] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10711 04:39:05.777858 <6>[ 15.323564] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10712 04:39:05.784434 <6>[ 15.331541] pci_bus 0000:00: root bus resource [bus 00-ff]
10713 04:39:05.794038 <6>[ 15.333433] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10714 04:39:05.800852 <6>[ 15.333752] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10715 04:39:05.810724 <3>[ 15.335722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10716 04:39:05.820720 <6>[ 15.347972] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10717 04:39:05.827250 <6>[ 15.357036] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10718 04:39:05.837002 <6>[ 15.366328] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10719 04:39:05.847005 <6>[ 15.370737] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10720 04:39:05.850544 <6>[ 15.399657] usbcore: registered new interface driver cdc_ether
10721 04:39:05.857190 <6>[ 15.399872] Bluetooth: Core ver 2.22
10722 04:39:05.860628 <6>[ 15.400041] NET: Registered PF_BLUETOOTH protocol family
10723 04:39:05.867416 <6>[ 15.400046] Bluetooth: HCI device and connection manager initialized
10724 04:39:05.873630 <6>[ 15.400118] Bluetooth: HCI socket layer initialized
10725 04:39:05.876885 <6>[ 15.400134] Bluetooth: L2CAP socket layer initialized
10726 04:39:05.883941 <6>[ 15.400163] Bluetooth: SCO socket layer initialized
10727 04:39:05.890919 <6>[ 15.400581] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10728 04:39:05.896976 <6>[ 15.405750] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10729 04:39:05.904165 <6>[ 15.428187] usbcore: registered new interface driver r8153_ecm
10730 04:39:05.910103 <6>[ 15.429104] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10731 04:39:05.923957 <6>[ 15.430534] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10732 04:39:05.930550 <6>[ 15.430707] usbcore: registered new interface driver uvcvideo
10733 04:39:05.936708 <6>[ 15.434936] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10734 04:39:05.946672 <4>[ 15.439616] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10735 04:39:05.953542 <4>[ 15.439623] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10736 04:39:05.959965 <6>[ 15.460514] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10737 04:39:05.966857 <6>[ 15.460770] usbcore: registered new interface driver btusb
10738 04:39:05.976772 <4>[ 15.461370] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10739 04:39:05.983890 <3>[ 15.461381] Bluetooth: hci0: Failed to load firmware file (-2)
10740 04:39:05.990162 <3>[ 15.461384] Bluetooth: hci0: Failed to set up firmware (-2)
10741 04:39:06.000323 <4>[ 15.461389] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10742 04:39:06.003544 <6>[ 15.468685] pci 0000:00:00.0: supports D1 D2
10743 04:39:06.006556 <6>[ 15.489310] r8152 2-1.3:1.0 eth0: v1.12.13
10744 04:39:06.013505 <6>[ 15.493428] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10745 04:39:06.023909 <6>[ 15.673183] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10746 04:39:06.030690 <6>[ 15.681549] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10747 04:39:06.037118 <6>[ 15.687832] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10748 04:39:06.044594 <6>[ 15.695316] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10749 04:39:06.054015 <6>[ 15.702799] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10750 04:39:06.057352 <6>[ 15.710374] pci 0000:01:00.0: supports D1 D2
10751 04:39:06.063788 <6>[ 15.714893] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10752 04:39:06.084078 <6>[ 15.733257] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10753 04:39:06.090467 <6>[ 15.740161] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10754 04:39:06.097764 <6>[ 15.748257] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10755 04:39:06.107509 <6>[ 15.756254] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10756 04:39:06.114045 <6>[ 15.764255] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10757 04:39:06.124184 <6>[ 15.772256] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10758 04:39:06.127089 <6>[ 15.780255] pci 0000:00:00.0: PCI bridge to [bus 01]
10759 04:39:06.137230 <6>[ 15.785476] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10760 04:39:06.144236 <6>[ 15.793620] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10761 04:39:06.150745 <6>[ 15.800486] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10762 04:39:06.157532 <6>[ 15.807306] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10763 04:39:06.179824 <5>[ 15.829315] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10764 04:39:06.210849 <5>[ 15.859827] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10765 04:39:06.217593 <4>[ 15.866727] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10766 04:39:06.223679 <6>[ 15.875647] cfg80211: failed to load regulatory.db
10767 04:39:06.284694 <6>[ 15.933697] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10768 04:39:06.291046 <6>[ 15.941242] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10769 04:39:06.315548 <6>[ 15.968157] mt7921e 0000:01:00.0: ASIC revision: 79610010
10770 04:39:06.423349 <4>[ 16.069494] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 04:39:06.439593 done
10772 04:39:06.443905 Saving random seed: OK
10773 04:39:06.460290 Starting network: OK
10774 04:39:06.497055 Starting dropbear sshd: <6>[ 16.149656] NET: Registered PF_INET6 protocol family
10775 04:39:06.503892 <6>[ 16.156062] Segment Routing with IPv6
10776 04:39:06.506827 <6>[ 16.160125] In-situ OAM (IOAM) with IPv6
10777 04:39:06.510488 OK
10778 04:39:06.521812 /bin/sh: can't access tty; job control turned off
10779 04:39:06.522184 Matched prompt #10: / #
10781 04:39:06.522397 Setting prompt string to ['/ #']
10782 04:39:06.522492 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10784 04:39:06.522690 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10785 04:39:06.522780 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
10786 04:39:06.522853 Setting prompt string to ['/ #']
10787 04:39:06.522916 Forcing a shell prompt, looking for ['/ #']
10789 04:39:06.573146 / #
10790 04:39:06.573330 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10791 04:39:06.573415 Waiting using forced prompt support (timeout 00:02:30)
10792 04:39:06.573519 <4>[ 16.188394] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 04:39:06.579028
10794 04:39:06.579332 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10795 04:39:06.579432 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
10796 04:39:06.579525 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10797 04:39:06.579612 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
10798 04:39:06.579698 end: 2 depthcharge-action (duration 00:01:39) [common]
10799 04:39:06.579787 start: 3 lava-test-retry (timeout 00:01:00) [common]
10800 04:39:06.579874 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10801 04:39:06.579948 Using namespace: common
10803 04:39:06.680309 / # #
10804 04:39:06.680494 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10805 04:39:06.680634 #<4>[ 16.309603] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 04:39:06.685719
10807 04:39:06.686018 Using /lava-11241307
10809 04:39:06.786434 / # export SHELL=/bin/sh
10810 04:39:06.786642 export SHELL=/bin/sh<4>[ 16.429443] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 04:39:06.792232
10813 04:39:06.892760 / # . /lava-11241307/environment
10814 04:39:06.903670 . /lava-11241307/environment<4>[ 16.549649] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 04:39:06.903767
10817 04:39:07.004301 / # /lava-11241307/bin/lava-test-runner /lava-11241307/0
10818 04:39:07.004472 Test shell timeout: 10s (minimum of the action and connection timeout)
10819 04:39:07.009929 /lava-11241307/bin/lava-test-runner /lava-11241307/0
10820 04:39:07.023515 <4>[ 16.669598] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 04:39:07.027136 + export 'TESTRUN_ID=0_dmesg'
10822 04:39:07.037044 + cd /lava-11241307<8>[ 16.686928] <LAVA_SIGNAL_STARTRUN 0_dmesg 11241307_1.5.2.3.1>
10823 04:39:07.037130 /0/tests/0_dmesg
10824 04:39:07.037195 + cat uuid
10825 04:39:07.037434 Received signal: <STARTRUN> 0_dmesg 11241307_1.5.2.3.1
10826 04:39:07.037504 Starting test lava.0_dmesg (11241307_1.5.2.3.1)
10827 04:39:07.037589 Skipping test definition patterns.
10828 04:39:07.040551 + UUID=11241307_1.5.2.3.1
10829 04:39:07.040634 + set +x
10830 04:39:07.046961 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10831 04:39:07.058911 <8>[ 16.708299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10832 04:39:07.059204 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10834 04:39:07.078996 <8>[ 16.728110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10835 04:39:07.079258 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10837 04:39:07.099007 <8>[ 16.747988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10838 04:39:07.099321 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10840 04:39:07.102236 + set +x
10841 04:39:07.105099 <8>[ 16.757455] <LAVA_SIGNAL_ENDRUN 0_dmesg 11241307_1.5.2.3.1>
10842 04:39:07.105355 Received signal: <ENDRUN> 0_dmesg 11241307_1.5.2.3.1
10843 04:39:07.105442 Ending use of test pattern.
10844 04:39:07.105505 Ending test lava.0_dmesg (11241307_1.5.2.3.1), duration 0.07
10846 04:39:07.108823 <LAVA_TEST_RUNNER EXIT>
10847 04:39:07.109072 ok: lava_test_shell seems to have completed
10848 04:39:07.109178 alert: pass
crit: pass
emerg: pass
10849 04:39:07.109270 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10850 04:39:07.109362 end: 3 lava-test-retry (duration 00:00:01) [common]
10851 04:39:07.109445 start: 4 lava-test-retry (timeout 00:01:00) [common]
10852 04:39:07.109526 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10853 04:39:07.109590 Using namespace: common
10855 04:39:07.209939 / # #
10856 04:39:07.210122 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10857 04:39:07.210237 Using /lava-11241307
10859 04:39:07.310585 export SHELL=/bin/sh
10860 04:39:07.310801 <4>[ 16.793896] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10861 04:39:07.310881 #
10862 04:39:07.310944 / # <4>[ 16.913903] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10864 04:39:07.411469 export SHELL=/bin/sh. /lava-11241307/environment
10865 04:39:07.411681
10866 04:39:07.411756 / # . /lava-11241307/environment<4>[ 17.034480] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10868 04:39:07.512332 /lava-11241307/bin/lava-test-runner /lava-11241307/1
10869 04:39:07.512507 Test shell timeout: 10s (minimum of the action and connection timeout)
10870 04:39:07.512659
10871 04:39:07.512769 / # /lava-11241307/bin/lava-test-runner /lava-11241307/1<4>[ 17.157820] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10872 04:39:07.517995
10873 04:39:07.560822 + export 'TESTRUN_ID=1_bootrr'
10874 04:39:07.560945 <8>[ 17.198880] <LAVA_SIGNAL_STARTRUN 1_bootrr 11241307_1.5.2.3.5>
10875 04:39:07.561013 + cd /lava-11241307/1/tests/1_bootrr
10876 04:39:07.561075 + cat uuid
10877 04:39:07.561133 + UUID=11241307_1.5.2.3.5
10878 04:39:07.561190 + set +x
10879 04:39:07.561428 Received signal: <STARTRUN> 1_bootrr 11241307_1.5.2.3.5
10880 04:39:07.561491 Starting test lava.1_bootrr (11241307_1.5.2.3.5)
10881 04:39:07.561570 Skipping test definition patterns.
10882 04:39:07.571380 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11241307/1/../bin<8>[ 17.219696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10883 04:39:07.571638 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10885 04:39:07.574740 :/sbin:/usr/sbin:/bin:/usr/bin'
10886 04:39:07.574820 + cd /opt/bootrr/libexec/bootrr
10887 04:39:07.578025 + sh helpers/bootrr-auto
10888 04:39:07.588078 /lava-11241307/1/../bin/lava-test-ca<8>[ 17.238317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10889 04:39:07.588162 se
10890 04:39:07.588397 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10892 04:39:07.591162 /lava-11241307/1/../bin/lava-test-case
10893 04:39:07.595101 /usr/bin/tpm2_getcap
10894 04:39:07.626383 <3>[ 17.279094] mt7921e 0000:01:00.0: hardware init failed
10895 04:39:07.634284 /lava-11241307/1/../bin/lava-test-case
10896 04:39:07.641081 <8>[ 17.292111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10897 04:39:07.641340 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10899 04:39:07.659448 /lava-11241307/1/../bin/lava-test-case
10900 04:39:07.666376 <8>[ 17.315568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10901 04:39:07.666633 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10903 04:39:07.677518 /lava-11241307/1/../bin/lava-test-case
10904 04:39:07.684150 <8>[ 17.333517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10905 04:39:07.684407 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10907 04:39:07.696043 /lava-11241307/1/../bin/lava-test-case
10908 04:39:07.702351 <8>[ 17.351782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10909 04:39:07.702611 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10911 04:39:07.714677 /lava-11241307/1/../bin/lava-test-case
10912 04:39:07.721140 <8>[ 17.372345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10913 04:39:07.721397 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10915 04:39:07.734033 /lava-11241307/1/../bin/lava-test-case
10916 04:39:07.740325 <8>[ 17.390588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10917 04:39:07.740595 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10919 04:39:07.749840 /lava-11241307/1/../bin/lava-test-case
10920 04:39:07.756406 <8>[ 17.406524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10921 04:39:07.756659 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10923 04:39:07.767620 /lava-11241307/1/../bin/lava-test-case
10924 04:39:07.774106 <8>[ 17.425732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10925 04:39:07.774360 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10927 04:39:07.791497 /lava-11241307/1/../bin/lava-tes<8>[ 17.440069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10928 04:39:07.791595 t-case
10929 04:39:07.791834 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10931 04:39:07.810459 /lava-11241307/1/../bin/lava-tes<8>[ 17.459248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10932 04:39:07.810551 t-case
10933 04:39:07.810789 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10935 04:39:07.822037 /lava-11241307/1/../bin/lava-test-case
10936 04:39:07.828635 <8>[ 17.477663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10937 04:39:07.828915 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10939 04:39:07.839770 /lava-11241307/1/../bin/lava-test-case
10940 04:39:07.846499 <8>[ 17.496556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10941 04:39:07.846755 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10943 04:39:07.858416 /lava-11241307/1/../bin/lava-test-case
10944 04:39:07.864958 <8>[ 17.514835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10945 04:39:07.865211 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10947 04:39:07.874376 /lava-11241307/1/../bin/lava-test-case
10948 04:39:07.880988 <8>[ 17.531599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10949 04:39:07.881246 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10951 04:39:07.893705 /lava-11241307/1/../bin/lava-test-case
10952 04:39:07.900023 <8>[ 17.549402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10953 04:39:07.900317 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10955 04:39:07.908310 /lava-11241307/1/../bin/lava-test-case
10956 04:39:07.914870 <8>[ 17.563696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10957 04:39:07.915126 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10959 04:39:07.935200 /lava-11241307/1/../bin/lava-tes<8>[ 17.584204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10960 04:39:07.935300 t-case
10961 04:39:07.935539 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10963 04:39:07.942705 /lava-11241307/1/../bin/lava-test-case
10964 04:39:07.949812 <8>[ 17.599060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10965 04:39:07.950069 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10967 04:39:07.964724 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10969 04:39:07.967839 /lava-11241307/1/../bin/lava-tes<8>[ 17.616243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10970 04:39:07.967923 t-case
10971 04:39:07.974673 /lava-11241307/1/../bin/lava-test-case
10972 04:39:07.981800 <8>[ 17.632081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10973 04:39:07.982056 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10975 04:39:07.995006 /lava-11241307/1/../bin/lava-test-case
10976 04:39:08.001999 <8>[ 17.650783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10977 04:39:08.002268 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10979 04:39:08.017768 /lava-11241307/1/../bin/lava-tes<8>[ 17.666385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10980 04:39:08.017858 t-case
10981 04:39:08.018116 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10983 04:39:08.037663 /lava-11241307/1/../bin/lava-tes<8>[ 17.686454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10984 04:39:08.037755 t-case
10985 04:39:08.038010 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10987 04:39:08.053999 /lava-11241307/1/../bin/lava-tes<8>[ 17.702568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10988 04:39:08.054101 t-case
10989 04:39:08.054362 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10991 04:39:08.069644 /lava-11241307/1/../bin/lava-tes<8>[ 17.718318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10992 04:39:08.069736 t-case
10993 04:39:08.069999 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10995 04:39:08.079004 /lava-11241307/1/../bin/lava-test-case
10996 04:39:08.089182 <8>[ 17.738790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10997 04:39:08.089439 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10999 04:39:08.097357 /lava-11241307/1/../bin/lava-test-case
11000 04:39:08.104367 <8>[ 17.753857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11001 04:39:08.104622 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11003 04:39:08.114806 /lava-11241307/1/../bin/lava-test-case
11004 04:39:08.121675 <8>[ 17.771811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11005 04:39:08.121930 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11007 04:39:08.134666 /lava-11241307/1/../bin/lava-test-case
11008 04:39:08.140953 <8>[ 17.790244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11009 04:39:08.141311 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11011 04:39:08.148760 /lava-11241307/1/../bin/lava-test-case
11012 04:39:08.158656 <8>[ 17.807714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11013 04:39:08.158973 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11015 04:39:08.169054 /lava-11241307/1/../bin/lava-test-case
11016 04:39:08.175314 <8>[ 17.825430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11017 04:39:08.175570 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11019 04:39:08.185836 /lava-11241307/1/../bin/lava-test-case
11020 04:39:08.191814 <8>[ 17.841616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11021 04:39:08.192052 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11023 04:39:08.202931 /lava-11241307/1/../bin/lava-test-case
11024 04:39:08.209386 <8>[ 17.859341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11025 04:39:08.209641 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11027 04:39:08.222813 /lava-11241307/1/../bin/lava-test-case
11028 04:39:08.229531 <8>[ 17.878653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11029 04:39:08.229789 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11031 04:39:08.244399 /lava-11241307/1/../bin/lava-tes<8>[ 17.893362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11032 04:39:08.244485 t-case
11033 04:39:08.244755 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11035 04:39:08.257795 /lava-11241307/1/../bin/lava-test-case
11036 04:39:08.264230 <8>[ 17.913842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11037 04:39:08.264542 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11039 04:39:08.279741 /lava-11241307/1/../bin/lava-tes<8>[ 17.928114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11040 04:39:08.279834 t-case
11041 04:39:08.280090 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11043 04:39:08.292892 /lava-11241307/1/../bin/lava-test-case
11044 04:39:08.299712 <8>[ 17.948939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11045 04:39:08.299986 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11047 04:39:08.307942 /lava-11241307/1/../bin/lava-test-case
11048 04:39:08.314598 <8>[ 17.964777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11049 04:39:08.314854 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11051 04:39:08.326377 /lava-11241307/1/../bin/lava-test-case
11052 04:39:08.333060 <8>[ 17.982918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11053 04:39:08.333323 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11055 04:39:08.341453 /lava-11241307/1/../bin/lava-test-case
11056 04:39:08.348160 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11058 04:39:08.351513 <8>[ 17.998817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11059 04:39:08.367845 /lava-11241307/1/../bin/lava-tes<8>[ 18.016727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11060 04:39:08.367936 t-case
11061 04:39:08.368197 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11063 04:39:08.375829 /lava-11241307/1/../bin/lava-test-case
11064 04:39:08.382641 <8>[ 18.033033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11065 04:39:08.382915 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11067 04:39:08.393961 /lava-11241307/1/../bin/lava-test-case
11068 04:39:08.400303 <8>[ 18.051001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11069 04:39:08.400583 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11071 04:39:08.409563 /lava-11241307/1/../bin/lava-test-case
11072 04:39:08.416302 <8>[ 18.065750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11073 04:39:08.416588 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11075 04:39:08.426858 /lava-11241307/1/../bin/lava-test-case
11076 04:39:08.433683 <8>[ 18.083432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11077 04:39:08.433938 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11079 04:39:08.441866 /lava-11241307/1/../bin/lava-test-case
11080 04:39:08.448238 <8>[ 18.098520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11081 04:39:08.448498 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11083 04:39:08.459299 /lava-11241307/1/../bin/lava-test-case
11084 04:39:08.465920 <8>[ 18.115671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11085 04:39:08.466189 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11087 04:39:08.483978 /lava-11241307/1/../bin/lava-tes<8>[ 18.132836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11088 04:39:08.484066 t-case
11089 04:39:08.484304 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11091 04:39:08.494196 /lava-11241307/1/../bin/lava-test-case
11092 04:39:08.500987 <8>[ 18.151372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11093 04:39:08.501246 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11095 04:39:08.512306 /lava-11241307/1/../bin/lava-test-case
11096 04:39:08.518725 <8>[ 18.168416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11097 04:39:08.518995 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11099 04:39:08.534448 /lava-11241307/1/../bin/lava-tes<8>[ 18.183379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11100 04:39:08.534534 t-case
11101 04:39:08.534771 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11103 04:39:08.544023 /lava-11241307/1/../bin/lava-test-case
11104 04:39:08.550524 <8>[ 18.200554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11105 04:39:08.550810 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11107 04:39:08.562171 /lava-11241307/1/../bin/lava-test-case
11108 04:39:08.568495 <8>[ 18.218069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11109 04:39:08.568748 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11111 04:39:08.578297 /lava-11241307/1/../bin/lava-test-case
11112 04:39:08.585120 <8>[ 18.235126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11113 04:39:08.585373 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11115 04:39:08.596610 /lava-11241307/1/../bin/lava-test-case
11116 04:39:08.603277 <8>[ 18.252385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11117 04:39:08.603531 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11119 04:39:08.612259 /lava-11241307/1/../bin/lava-test-case
11120 04:39:08.618882 <8>[ 18.269100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11121 04:39:08.619186 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11123 04:39:08.635035 /lava-11241307/1/../bin/lava-tes<8>[ 18.284205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11124 04:39:08.635128 t-case
11125 04:39:08.635385 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11127 04:39:08.648498 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11129 04:39:08.651261 /lava-11241307/1/../bin/lava-tes<8>[ 18.300200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11130 04:39:08.651370 t-case
11131 04:39:08.664741 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11133 04:39:08.668357 /lava-11241307/1/../bin/lava-tes<8>[ 18.316874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11134 04:39:08.668440 t-case
11135 04:39:08.675129 /lava-11241307/1/../bin/lava-test-case
11136 04:39:08.682178 <8>[ 18.330833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11137 04:39:08.682433 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11139 04:39:08.695619 /lava-11241307/1/../bin/lava-test-case
11140 04:39:08.702716 <8>[ 18.352015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11141 04:39:08.702991 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11143 04:39:08.717343 /lava-11241307/1/../bin/lava-tes<8>[ 18.365995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11144 04:39:08.717434 t-case
11145 04:39:08.717689 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11147 04:39:08.730197 /lava-11241307/1/../bin/lava-test-case
11148 04:39:08.736721 <8>[ 18.387240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11149 04:39:08.736974 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11151 04:39:08.746045 /lava-11241307/1/../bin/lava-test-case
11152 04:39:08.752255 <8>[ 18.401419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11153 04:39:08.752507 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11155 04:39:08.766527 /lava-11241307/1/../bin/lava-test-case
11156 04:39:08.772454 <8>[ 18.423005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11157 04:39:08.772705 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11159 04:39:08.782792 /lava-11241307/1/../bin/lava-test-case
11160 04:39:08.789743 <8>[ 18.440342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11161 04:39:08.789999 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11163 04:39:08.800050 /lava-11241307/1/../bin/lava-test-case
11164 04:39:08.806822 <8>[ 18.456746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11165 04:39:08.807084 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11167 04:39:08.817382 /lava-11241307/1/../bin/lava-test-case
11168 04:39:08.823840 <8>[ 18.473329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11169 04:39:08.824096 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11171 04:39:08.841818 /lava-11241307/1/../bin/lava-tes<8>[ 18.490725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11172 04:39:08.841903 t-case
11173 04:39:08.842138 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11175 04:39:08.852890 /lava-11241307/1/../bin/lava-test-case
11176 04:39:08.859754 <8>[ 18.510297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11177 04:39:08.860007 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11179 04:39:08.871239 /lava-11241307/1/../bin/lava-test-case
11180 04:39:08.877807 <8>[ 18.527687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11181 04:39:08.878061 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11183 04:39:08.887908 /lava-11241307/1/../bin/lava-test-case
11184 04:39:08.894333 <8>[ 18.544645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11185 04:39:08.894588 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11187 04:39:08.906266 /lava-11241307/1/../bin/lava-test-case
11188 04:39:08.912651 <8>[ 18.562626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11189 04:39:08.912946 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11191 04:39:08.922230 /lava-11241307/1/../bin/lava-test-case
11192 04:39:08.929223 <8>[ 18.578975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11193 04:39:08.929477 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11195 04:39:08.946999 /lava-11241307/1/../bin/lava-tes<8>[ 18.596240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11196 04:39:08.947083 t-case
11197 04:39:08.947318 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11199 04:39:08.956627 /lava-11241307/1/../bin/lava-test-case
11200 04:39:08.963275 <8>[ 18.613425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11201 04:39:08.963533 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11203 04:39:08.975216 /lava-11241307/1/../bin/lava-test-case
11204 04:39:08.981458 <8>[ 18.631126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11205 04:39:08.981737 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11207 04:39:08.991571 /lava-11241307/1/../bin/lava-test-case
11208 04:39:08.998341 <8>[ 18.648411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11209 04:39:08.998596 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11211 04:39:09.018179 /lava-11241307/1/../bin/lava-tes<8>[ 18.667333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11212 04:39:09.018263 t-case
11213 04:39:09.018498 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11215 04:39:09.032911 /lava-11241307/1/../bin/lava-tes<8>[ 18.681609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11216 04:39:09.032997 t-case
11217 04:39:09.033232 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11219 04:39:09.045162 /lava-11241307/1/../bin/lava-test-case
11220 04:39:09.051470 <8>[ 18.701351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11221 04:39:09.051723 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11223 04:39:09.059146 /lava-11241307/1/../bin/lava-test-case
11224 04:39:09.066129 <8>[ 18.716656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11225 04:39:09.066383 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11227 04:39:09.075350 /lava-11241307/1/../bin/lava-test-case
11228 04:39:09.085198 <8>[ 18.734607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11229 04:39:09.085451 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11231 04:39:09.092991 /lava-11241307/1/../bin/lava-test-case
11232 04:39:09.099327 <8>[ 18.749621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11233 04:39:09.099600 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11235 04:39:09.111938 /lava-11241307/1/../bin/lava-test-case
11236 04:39:09.118518 <8>[ 18.768404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11237 04:39:09.118788 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11239 04:39:09.127246 /lava-11241307/1/../bin/lava-test-case
11240 04:39:09.134056 <8>[ 18.784557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11241 04:39:09.134310 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11243 04:39:09.147041 /lava-11241307/1/../bin/lava-test-case
11244 04:39:09.153979 <8>[ 18.803612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11245 04:39:09.154270 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11247 04:39:09.168553 /lava-11241307/1/../bin/lava-tes<8>[ 18.817539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11248 04:39:09.168644 t-case
11249 04:39:09.168922 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11251 04:39:09.181406 /lava-11241307/1/../bin/lava-test-case
11252 04:39:09.187947 <8>[ 18.839569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11253 04:39:09.188203 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11255 04:39:09.198497 /lava-11241307/1/../bin/lava-test-case
11256 04:39:09.205157 <8>[ 18.855200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11257 04:39:09.205412 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11259 04:39:09.219901 /lava-11241307/1/../bin/lava-test-case
11260 04:39:09.226685 <8>[ 18.876164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11261 04:39:09.226939 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11263 04:39:09.236808 /lava-11241307/1/../bin/lava-test-case
11264 04:39:09.243403 <8>[ 18.893110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11265 04:39:09.243657 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11267 04:39:09.260632 /lava-11241307/1/../bin/lava-tes<8>[ 18.909925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11268 04:39:09.260766 t-case
11269 04:39:09.261003 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11271 04:39:09.270665 /lava-11241307/1/../bin/lava-test-case
11272 04:39:09.277044 <8>[ 18.927461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11273 04:39:09.277298 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11275 04:39:09.286837 /lava-11241307/1/../bin/lava-test-case
11276 04:39:09.293319 <8>[ 18.942520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11277 04:39:09.293580 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11279 04:39:09.303156 /lava-11241307/1/../bin/lava-test-case
11280 04:39:09.313292 <8>[ 18.963188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11281 04:39:09.313572 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11283 04:39:09.321602 /lava-11241307/1/../bin/lava-test-case
11284 04:39:09.327964 <8>[ 18.978661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11285 04:39:09.328226 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11287 04:39:10.342902 /lava-11241307/1/../bin/lava-test-case
11288 04:39:10.348948 <8>[ 19.999737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11289 04:39:10.349214 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11291 04:39:10.366869 /lava-11241307/1/../bin/lava-tes<8>[ 20.015746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11292 04:39:10.366959 t-case
11293 04:39:10.367194 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11295 04:39:11.378194 /lava-11241307/1/../bin/lava-test-case
11296 04:39:11.385058 <8>[ 21.034846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11297 04:39:11.385385 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11299 04:39:11.394606 /lava-11241307/1/../bin/lava-test-case
11300 04:39:11.400966 <8>[ 21.051068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11301 04:39:11.401294 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11303 04:39:12.415715 /lava-11241307/1/../bin/lava-test-case
11304 04:39:12.422614 <8>[ 22.072239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11305 04:39:12.422944 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11307 04:39:12.432201 /lava-11241307/1/../bin/lava-test-case
11308 04:39:12.438376 <8>[ 22.089486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11309 04:39:12.438713 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11311 04:39:13.453619 /lava-11241307/1/../bin/lava-test-case
11312 04:39:13.459788 <8>[ 23.110762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11313 04:39:13.460077 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11315 04:39:13.468111 /lava-11241307/1/../bin/lava-test-case
11316 04:39:13.478283 <8>[ 23.127960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11317 04:39:13.478599 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11319 04:39:14.487329 /lava-11241307/1/../bin/lava-test-case
11320 04:39:14.497168 <8>[ 24.147147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11321 04:39:14.497559 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11323 04:39:14.506912 /lava-11241307/1/../bin/lava-test-case
11324 04:39:14.513141 <8>[ 24.163371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11325 04:39:14.513433 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11327 04:39:15.530433 /lava-11241307/1/../bin/lava-test-case
11328 04:39:15.536709 <8>[ 25.187257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11329 04:39:15.537016 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11331 04:39:15.545482 /lava-11241307/1/../bin/lava-test-case
11332 04:39:15.552547 <8>[ 25.202958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11333 04:39:15.552934 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11335 04:39:16.568218 /lava-11241307/1/../bin/lava-test-case
11336 04:39:16.574929 <8>[ 26.225401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11337 04:39:16.575198 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11339 04:39:16.582844 /lava-11241307/1/../bin/lava-test-case
11340 04:39:16.593422 <8>[ 26.243669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11341 04:39:16.593694 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11343 04:39:16.602269 /lava-11241307/1/../bin/lava-test-case
11344 04:39:16.608918 <8>[ 26.259109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11345 04:39:16.609198 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11347 04:39:17.622043 /lava-11241307/1/../bin/lava-test-case
11348 04:39:17.628586 <8>[ 27.279340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11349 04:39:17.629062 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11351 04:39:17.638944 /lava-11241307/1/../bin/lava-test-case
11352 04:39:17.645139 <8>[ 27.296724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11353 04:39:17.645514 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11355 04:39:17.656371 /lava-11241307/1/../bin/lava-test-case
11356 04:39:17.663948 <8>[ 27.313685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11357 04:39:17.664220 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11359 04:39:17.672278 /lava-11241307/1/../bin/lava-test-case
11360 04:39:17.678889 <8>[ 27.330386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11361 04:39:17.679231 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11363 04:39:17.699035 /lava-11241307/1/../bin/lava-tes<8>[ 27.348644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11364 04:39:17.699151 t-case
11365 04:39:17.699390 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11367 04:39:17.718182 /lava-11241307/1/../bin/lava-tes<8>[ 27.368188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11368 04:39:17.718302 t-case
11369 04:39:17.718541 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11371 04:39:17.727588 /lava-11241307/1/../bin/lava-test-case
11372 04:39:17.734428 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11374 04:39:17.737473 <8>[ 27.386671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11375 04:39:17.745979 /lava-11241307/1/../bin/lava-test-case
11376 04:39:17.752491 <8>[ 27.404110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11377 04:39:17.752820 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11379 04:39:17.765562 /lava-11241307/1/../bin/lava-test-case
11380 04:39:17.771490 <8>[ 27.422537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11381 04:39:17.771812 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11383 04:39:17.781944 /lava-11241307/1/../bin/lava-test-case
11384 04:39:17.788635 <8>[ 27.440203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11385 04:39:17.788925 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11387 04:39:17.798594 /lava-11241307/1/../bin/lava-test-case
11388 04:39:17.805786 <8>[ 27.455552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11389 04:39:17.806135 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11391 04:39:17.822579 /lava-11241307/1/../bin/lava-tes<8>[ 27.472669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11392 04:39:17.822792 t-case
11393 04:39:17.823105 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11395 04:39:17.839200 /lava-11241307/1/../bin/lava-tes<8>[ 27.489403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11396 04:39:17.839367 t-case
11397 04:39:17.839676 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11399 04:39:17.850807 /lava-11241307/1/../bin/lava-test-case
11400 04:39:17.857557 <8>[ 27.508136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11401 04:39:17.857885 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11403 04:39:17.873279 /lava-11241307/1/../bin/lava-tes<8>[ 27.523025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11404 04:39:17.873437 t-case
11405 04:39:17.873748 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11407 04:39:17.890886 /lava-11241307/1/../bin/lava-tes<8>[ 27.540782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11408 04:39:17.891099 t-case
11409 04:39:17.891416 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11411 04:39:17.899194 /lava-11241307/1/../bin/lava-test-case
11412 04:39:17.908598 <8>[ 27.558315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11413 04:39:17.908968 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11415 04:39:17.920403 /lava-11241307/1/../bin/lava-test-case
11416 04:39:17.926603 <8>[ 27.577676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11417 04:39:17.926938 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11419 04:39:17.936097 /lava-11241307/1/../bin/lava-test-case
11420 04:39:17.942579 <8>[ 27.594020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11421 04:39:17.943215 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11423 04:39:17.955096 /lava-11241307/1/../bin/lava-test-case
11424 04:39:17.961823 <8>[ 27.612750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11425 04:39:17.962218 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11427 04:39:17.970805 /lava-11241307/1/../bin/lava-test-case
11428 04:39:17.977074 <8>[ 27.627970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11429 04:39:17.977399 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11431 04:39:18.990051 /lava-11241307/1/../bin/lava-test-case
11432 04:39:18.996549 <8>[ 28.647632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11433 04:39:18.996861 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11435 04:39:20.011171 /lava-11241307/1/../bin/lava-test-case
11436 04:39:20.017581 <8>[ 29.668208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11437 04:39:20.018471 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11439 04:39:20.025440 /lava-11241307/1/../bin/lava-test-case
11440 04:39:20.035230 <8>[ 29.684915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11441 04:39:20.036053 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11443 04:39:20.046221 /lava-11241307/1/../bin/lava-test-case
11444 04:39:20.052930 <8>[ 29.703586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11445 04:39:20.053614 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11447 04:39:20.060817 /lava-11241307/1/../bin/lava-test-case
11448 04:39:20.067368 <8>[ 29.718721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11449 04:39:20.068052 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11451 04:39:20.079037 /lava-11241307/1/../bin/lava-test-case
11452 04:39:20.085994 <8>[ 29.736567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11453 04:39:20.086779 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11455 04:39:20.094588 /lava-11241307/1/../bin/lava-test-case
11456 04:39:20.101111 <8>[ 29.751373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11457 04:39:20.101791 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11459 04:39:20.114138 /lava-11241307/1/../bin/lava-test-case
11460 04:39:20.120775 <8>[ 29.771002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11461 04:39:20.121539 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11463 04:39:20.129058 /lava-11241307/1/../bin/lava-test-case
11464 04:39:20.135019 <8>[ 29.785870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11465 04:39:20.135856 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11467 04:39:20.153516 /lava-11241307/1/../bin/lava-tes<8>[ 29.803144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11468 04:39:20.153941 t-case
11469 04:39:20.154529 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11471 04:39:20.167291 /lava-11241307/1/../bin/lava-tes<8>[ 29.816933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11472 04:39:20.167782 t-case
11473 04:39:20.168372 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11475 04:39:20.177789 /lava-11241307/1/../bin/lava-test-case
11476 04:39:20.184771 <8>[ 29.834868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11477 04:39:20.185509 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11479 04:39:20.198699 /lava-11241307/1/../bin/lava-tes<8>[ 29.848517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11480 04:39:20.199215 t-case
11481 04:39:20.199812 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11483 04:39:20.211890 /lava-11241307/1/../bin/lava-test-case
11484 04:39:20.218523 <8>[ 29.870188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11485 04:39:20.219227 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11487 04:39:20.228767 /lava-11241307/1/../bin/lava-test-case
11488 04:39:20.235155 <8>[ 29.886125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11489 04:39:20.235829 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11491 04:39:20.249377 /lava-11241307/1/../bin/lava-test-case
11492 04:39:20.255889 <8>[ 29.906273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11493 04:39:20.256888 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11495 04:39:20.263329 /lava-11241307/1/../bin/lava-test-case
11496 04:39:20.270008 <8>[ 29.921407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11497 04:39:20.270979 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11499 04:39:20.281713 /lava-11241307/1/../bin/lava-test-case
11500 04:39:20.289032 <8>[ 29.939231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11501 04:39:20.289626 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11503 04:39:20.303012 /lava-11241307/1/../bin/lava-tes<8>[ 29.953038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11504 04:39:20.303233 t-case
11505 04:39:20.303625 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11507 04:39:20.315504 /lava-11241307/1/../bin/lava-test-case
11508 04:39:20.321914 <8>[ 29.973885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11509 04:39:20.322252 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11511 04:39:20.331393 /lava-11241307/1/../bin/lava-test-case
11512 04:39:20.338086 <8>[ 29.990365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11513 04:39:20.338341 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11515 04:39:20.350449 /lava-11241307/1/../bin/lava-test-case
11516 04:39:20.357413 <8>[ 30.007520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11517 04:39:20.358394 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11519 04:39:21.371355 /lava-11241307/1/../bin/lava-test-case
11520 04:39:21.377810 <8>[ 31.029951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11521 04:39:21.378546 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11523 04:39:22.391078 /lava-11241307/1/../bin/lava-test-case
11524 04:39:22.397573 <8>[ 32.048832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11525 04:39:22.397833 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11526 04:39:22.397922 Bad test result: blocked
11527 04:39:22.406674 /lava-11241307/1/../bin/lava-test-case
11528 04:39:22.413842 <8>[ 32.065443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11529 04:39:22.414517 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11531 04:39:23.427556 /lava-11241307/1/../bin/lava-test-case
11532 04:39:23.434284 <8>[ 33.085042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11533 04:39:23.435147 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11535 04:39:23.441973 /lava-11241307/1/../bin/lava-test-case
11536 04:39:23.448377 <8>[ 33.100035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11537 04:39:23.449162 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11539 04:39:23.461546 /lava-11241307/1/../bin/lava-test-case
11540 04:39:23.468389 <8>[ 33.119656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11541 04:39:23.469274 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11543 04:39:23.477861 /lava-11241307/1/../bin/lava-test-case
11544 04:39:23.487982 <8>[ 33.138868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11545 04:39:23.488842 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11547 04:39:23.496986 /lava-11241307/1/../bin/lava-test-case
11548 04:39:23.503171 <8>[ 33.154528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11549 04:39:23.503858 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11551 04:39:23.513786 /lava-11241307/1/../bin/lava-test-case
11552 04:39:23.520727 <8>[ 33.171526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11553 04:39:23.521424 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11555 04:39:23.537216 /lava-11241307/1/../bin/lava-tes<8>[ 33.187570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11556 04:39:23.537637 t-case
11557 04:39:23.538215 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11559 04:39:24.550090 /lava-11241307/1/../bin/lava-test-case
11560 04:39:24.556862 <8>[ 34.208068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11561 04:39:24.557377 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11563 04:39:24.564634 /lava-11241307/1/../bin/lava-test-case
11564 04:39:24.575293 <8>[ 34.226067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11565 04:39:24.576083 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11567 04:39:25.587596 /lava-11241307/1/../bin/lava-test-case
11568 04:39:25.593798 <8>[ 35.245537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11569 04:39:25.594739 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11571 04:39:25.604010 /lava-11241307/1/../bin/lava-test-case
11572 04:39:25.611070 <8>[ 35.263868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11573 04:39:25.611908 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11575 04:39:26.624484 /lava-11241307/1/../bin/lava-test-case
11576 04:39:26.631124 <8>[ 36.282439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11577 04:39:26.631925 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11579 04:39:26.641122 /lava-11241307/1/../bin/lava-test-case
11580 04:39:26.647465 <8>[ 36.299005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11581 04:39:26.648349 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11583 04:39:27.659946 /lava-11241307/1/../bin/lava-test-case
11584 04:39:27.666368 <8>[ 37.318012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11585 04:39:27.666659 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11587 04:39:27.675568 /lava-11241307/1/../bin/lava-test-case
11588 04:39:27.682404 <8>[ 37.335234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11589 04:39:27.682684 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11591 04:39:27.693569 /lava-11241307/1/../bin/lava-test-case
11592 04:39:27.700458 <8>[ 37.351715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11593 04:39:27.700752 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11595 04:39:27.715934 /lava-11241307/1/../bin/lava-tes<8>[ 37.370672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11596 04:39:27.716220 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11598 04:39:27.719108 t-case
11599 04:39:27.726842 /lava-11241307/1/../bin/lava-test-case
11600 04:39:27.732920 <8>[ 37.384904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11601 04:39:27.733210 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11603 04:39:27.744105 /lava-11241307/1/../bin/lava-test-case
11604 04:39:27.751052 <8>[ 37.402836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11605 04:39:27.751340 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11607 04:39:27.758653 /lava-11241307/1/../bin/lava-test-case
11608 04:39:27.776980 <8>[ 37.416349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11609 04:39:27.777126 /lava-11241307/1/../bin/lava-test-case
11610 04:39:27.777429 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11612 04:39:27.783704 <8>[ 37.436144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11613 04:39:27.784002 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11615 04:39:27.792736 /lava-11241307/1/../bin/lava-test-case
11616 04:39:27.798727 <8>[ 37.451592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11617 04:39:27.799066 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11619 04:39:27.810454 /lava-11241307/1/../bin/lava-test-case
11620 04:39:27.816794 <8>[ 37.468575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11621 04:39:27.817092 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11623 04:39:27.820021 + set +x
11624 04:39:27.823438 Received signal: <ENDRUN> 1_bootrr 11241307_1.5.2.3.5
11625 04:39:27.823555 Ending use of test pattern.
11626 04:39:27.823661 Ending test lava.1_bootrr (11241307_1.5.2.3.5), duration 20.26
11628 04:39:27.826887 <8>[ 37.478817] <LAVA_SIGNAL_ENDRUN 1_bootrr 11241307_1.5.2.3.5>
11629 04:39:27.827173 ok: lava_test_shell seems to have completed
11630 04:39:27.829447 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11631 04:39:27.829644 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11632 04:39:27.829766 end: 4 lava-test-retry (duration 00:00:21) [common]
11633 04:39:27.829882 start: 5 finalize (timeout 00:07:42) [common]
11634 04:39:27.830020 start: 5.1 power-off (timeout 00:00:30) [common]
11635 04:39:27.830305 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11636 04:39:27.907414 >> Command sent successfully.
11637 04:39:27.912431 Returned 0 in 0 seconds
11638 04:39:28.013463 end: 5.1 power-off (duration 00:00:00) [common]
11640 04:39:28.015482 start: 5.2 read-feedback (timeout 00:07:42) [common]
11642 04:39:28.018099 Listened to connection for namespace 'common' for up to 1s
11643 04:39:29.016910 Finalising connection for namespace 'common'
11644 04:39:29.017573 Disconnecting from shell: Finalise
11645 04:39:29.017979 / #
11646 04:39:29.118960 end: 5.2 read-feedback (duration 00:00:01) [common]
11647 04:39:29.119722 end: 5 finalize (duration 00:00:01) [common]
11648 04:39:29.120336 Cleaning after the job
11649 04:39:29.120928 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/ramdisk
11650 04:39:29.310960 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/kernel
11651 04:39:29.336050 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/dtb
11652 04:39:29.336414 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241307/tftp-deploy-a8jao2y4/modules
11653 04:39:29.347356 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11241307
11654 04:39:29.858543 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11241307
11655 04:39:29.858729 Job finished correctly