Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 27
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 37
- Errors: 1
1 04:36:47.693140 lava-dispatcher, installed at version: 2023.05.1
2 04:36:47.693368 start: 0 validate
3 04:36:47.693501 Start time: 2023-08-09 04:36:47.693493+00:00 (UTC)
4 04:36:47.693631 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:36:47.693765 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 04:36:47.961264 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:36:47.961468 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:37:04.964126 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:37:04.964294 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:37:05.234011 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:37:05.234195 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:37:05.498713 Using caching service: 'http://localhost/cache/?uri=%s'
13 04:37:05.498915 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 04:37:08.504359 validate duration: 20.81
16 04:37:08.504693 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:37:08.504834 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:37:08.504957 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:37:08.505124 Not decompressing ramdisk as can be used compressed.
20 04:37:08.505249 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 04:37:08.505344 saving as /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/ramdisk/initrd.cpio.gz
22 04:37:08.505435 total size: 4665412 (4MB)
23 04:37:08.772809 progress 0% (0MB)
24 04:37:08.775181 progress 5% (0MB)
25 04:37:08.777172 progress 10% (0MB)
26 04:37:08.779133 progress 15% (0MB)
27 04:37:08.781114 progress 20% (0MB)
28 04:37:08.783097 progress 25% (1MB)
29 04:37:08.785090 progress 30% (1MB)
30 04:37:08.787065 progress 35% (1MB)
31 04:37:08.789110 progress 40% (1MB)
32 04:37:08.791413 progress 45% (2MB)
33 04:37:08.792698 progress 50% (2MB)
34 04:37:08.793980 progress 55% (2MB)
35 04:37:08.795265 progress 60% (2MB)
36 04:37:08.796557 progress 65% (2MB)
37 04:37:08.797843 progress 70% (3MB)
38 04:37:08.799116 progress 75% (3MB)
39 04:37:08.800387 progress 80% (3MB)
40 04:37:08.801829 progress 85% (3MB)
41 04:37:08.803094 progress 90% (4MB)
42 04:37:08.804368 progress 95% (4MB)
43 04:37:08.805669 progress 100% (4MB)
44 04:37:08.805831 4MB downloaded in 0.30s (14.81MB/s)
45 04:37:08.805984 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:37:08.806232 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:37:08.806323 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:37:08.806409 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:37:08.806564 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 04:37:08.806636 saving as /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/kernel/Image
52 04:37:08.806697 total size: 49220096 (46MB)
53 04:37:08.806760 No compression specified
54 04:37:08.807841 progress 0% (0MB)
55 04:37:08.821642 progress 5% (2MB)
56 04:37:08.835179 progress 10% (4MB)
57 04:37:08.848897 progress 15% (7MB)
58 04:37:08.863823 progress 20% (9MB)
59 04:37:08.878337 progress 25% (11MB)
60 04:37:08.892414 progress 30% (14MB)
61 04:37:08.906846 progress 35% (16MB)
62 04:37:08.921154 progress 40% (18MB)
63 04:37:08.934850 progress 45% (21MB)
64 04:37:08.948262 progress 50% (23MB)
65 04:37:08.962028 progress 55% (25MB)
66 04:37:08.976324 progress 60% (28MB)
67 04:37:08.990277 progress 65% (30MB)
68 04:37:09.003959 progress 70% (32MB)
69 04:37:09.017195 progress 75% (35MB)
70 04:37:09.030365 progress 80% (37MB)
71 04:37:09.043827 progress 85% (39MB)
72 04:37:09.057223 progress 90% (42MB)
73 04:37:09.070959 progress 95% (44MB)
74 04:37:09.084708 progress 100% (46MB)
75 04:37:09.084923 46MB downloaded in 0.28s (168.71MB/s)
76 04:37:09.085130 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:37:09.085521 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:37:09.085640 start: 1.3 download-retry (timeout 00:09:59) [common]
80 04:37:09.085762 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 04:37:09.085947 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 04:37:09.086046 saving as /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/dtb/mt8192-asurada-spherion-r0.dtb
83 04:37:09.086138 total size: 47278 (0MB)
84 04:37:09.086228 No compression specified
85 04:37:09.087794 progress 69% (0MB)
86 04:37:09.088094 progress 100% (0MB)
87 04:37:09.088284 0MB downloaded in 0.00s (21.04MB/s)
88 04:37:09.088465 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:37:09.088848 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:37:09.088975 start: 1.4 download-retry (timeout 00:09:59) [common]
92 04:37:09.089109 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 04:37:09.089268 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 04:37:09.089363 saving as /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/nfsrootfs/full.rootfs.tar
95 04:37:09.089455 total size: 125290964 (119MB)
96 04:37:09.089546 Using unxz to decompress xz
97 04:37:09.093789 progress 0% (0MB)
98 04:37:09.439803 progress 5% (6MB)
99 04:37:09.796353 progress 10% (11MB)
100 04:37:10.153208 progress 15% (17MB)
101 04:37:10.362489 progress 20% (23MB)
102 04:37:10.549941 progress 25% (29MB)
103 04:37:10.932743 progress 30% (35MB)
104 04:37:11.296112 progress 35% (41MB)
105 04:37:11.701443 progress 40% (47MB)
106 04:37:12.101864 progress 45% (53MB)
107 04:37:12.514172 progress 50% (59MB)
108 04:37:12.886405 progress 55% (65MB)
109 04:37:13.270289 progress 60% (71MB)
110 04:37:13.634485 progress 65% (77MB)
111 04:37:14.033709 progress 70% (83MB)
112 04:37:14.436511 progress 75% (89MB)
113 04:37:14.876146 progress 80% (95MB)
114 04:37:15.315504 progress 85% (101MB)
115 04:37:15.570595 progress 90% (107MB)
116 04:37:15.931754 progress 95% (113MB)
117 04:37:16.324267 progress 100% (119MB)
118 04:37:16.330069 119MB downloaded in 7.24s (16.50MB/s)
119 04:37:16.330399 end: 1.4.1 http-download (duration 00:00:07) [common]
121 04:37:16.330689 end: 1.4 download-retry (duration 00:00:07) [common]
122 04:37:16.330788 start: 1.5 download-retry (timeout 00:09:52) [common]
123 04:37:16.330878 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 04:37:16.331058 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 04:37:16.331172 saving as /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/modules/modules.tar
126 04:37:16.331263 total size: 8557308 (8MB)
127 04:37:16.331354 Using unxz to decompress xz
128 04:37:16.592828 progress 0% (0MB)
129 04:37:16.615350 progress 5% (0MB)
130 04:37:16.638343 progress 10% (0MB)
131 04:37:16.665355 progress 15% (1MB)
132 04:37:16.692003 progress 20% (1MB)
133 04:37:16.718861 progress 25% (2MB)
134 04:37:16.746460 progress 30% (2MB)
135 04:37:16.773290 progress 35% (2MB)
136 04:37:16.799962 progress 40% (3MB)
137 04:37:16.826205 progress 45% (3MB)
138 04:37:16.854378 progress 50% (4MB)
139 04:37:16.880841 progress 55% (4MB)
140 04:37:16.907350 progress 60% (4MB)
141 04:37:16.931236 progress 65% (5MB)
142 04:37:16.957634 progress 70% (5MB)
143 04:37:16.982963 progress 75% (6MB)
144 04:37:17.010307 progress 80% (6MB)
145 04:37:17.040897 progress 85% (6MB)
146 04:37:17.070531 progress 90% (7MB)
147 04:37:17.095905 progress 95% (7MB)
148 04:37:17.120439 progress 100% (8MB)
149 04:37:17.125278 8MB downloaded in 0.79s (10.28MB/s)
150 04:37:17.125614 end: 1.5.1 http-download (duration 00:00:01) [common]
152 04:37:17.125928 end: 1.5 download-retry (duration 00:00:01) [common]
153 04:37:17.126042 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 04:37:17.126156 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 04:37:19.643237 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11241313/extract-nfsrootfs-izw72tpv
156 04:37:19.643472 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 04:37:19.643584 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 04:37:19.643757 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6
159 04:37:19.643898 makedir: /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin
160 04:37:19.644007 makedir: /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/tests
161 04:37:19.644138 makedir: /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/results
162 04:37:19.644242 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-add-keys
163 04:37:19.644389 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-add-sources
164 04:37:19.644525 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-background-process-start
165 04:37:19.644663 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-background-process-stop
166 04:37:19.658704 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-common-functions
167 04:37:19.658909 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-echo-ipv4
168 04:37:19.659059 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-install-packages
169 04:37:19.659193 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-installed-packages
170 04:37:19.659322 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-os-build
171 04:37:19.659468 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-probe-channel
172 04:37:19.659602 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-probe-ip
173 04:37:19.661471 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-target-ip
174 04:37:19.661623 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-target-mac
175 04:37:19.661757 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-target-storage
176 04:37:19.661890 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-test-case
177 04:37:19.662022 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-test-event
178 04:37:19.662149 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-test-feedback
179 04:37:19.662302 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-test-raise
180 04:37:19.662443 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-test-reference
181 04:37:19.662571 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-test-runner
182 04:37:19.662700 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-test-set
183 04:37:19.662831 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-test-shell
184 04:37:19.662962 Updating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-install-packages (oe)
185 04:37:19.669684 Updating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/bin/lava-installed-packages (oe)
186 04:37:19.669884 Creating /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/environment
187 04:37:19.670005 LAVA metadata
188 04:37:19.670115 - LAVA_JOB_ID=11241313
189 04:37:19.670187 - LAVA_DISPATCHER_IP=192.168.201.1
190 04:37:19.670308 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 04:37:19.670385 skipped lava-vland-overlay
192 04:37:19.670465 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 04:37:19.670548 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 04:37:19.670613 skipped lava-multinode-overlay
195 04:37:19.670700 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 04:37:19.670780 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 04:37:19.670864 Loading test definitions
198 04:37:19.670963 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 04:37:19.671038 Using /lava-11241313 at stage 0
200 04:37:19.671390 uuid=11241313_1.6.2.3.1 testdef=None
201 04:37:19.671497 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 04:37:19.671585 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 04:37:19.672134 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 04:37:19.672359 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 04:37:19.679629 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 04:37:19.679927 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 04:37:19.685046 runner path: /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/0/tests/0_dmesg test_uuid 11241313_1.6.2.3.1
210 04:37:19.685259 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 04:37:19.685511 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 04:37:19.685589 Using /lava-11241313 at stage 1
214 04:37:19.685947 uuid=11241313_1.6.2.3.5 testdef=None
215 04:37:19.686039 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 04:37:19.686152 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 04:37:19.686844 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 04:37:19.687069 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 04:37:19.689971 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 04:37:19.690384 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 04:37:19.696196 runner path: /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/1/tests/1_bootrr test_uuid 11241313_1.6.2.3.5
224 04:37:19.696406 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 04:37:19.696631 Creating lava-test-runner.conf files
227 04:37:19.696704 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/0 for stage 0
228 04:37:19.696805 - 0_dmesg
229 04:37:19.696893 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11241313/lava-overlay-0dg6ljr6/lava-11241313/1 for stage 1
230 04:37:19.696989 - 1_bootrr
231 04:37:19.697089 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 04:37:19.697196 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 04:37:19.705140 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 04:37:19.705298 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 04:37:19.705397 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 04:37:19.705485 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 04:37:19.705571 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 04:37:19.830860 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 04:37:19.831393 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 04:37:19.831608 extracting modules file /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11241313/extract-nfsrootfs-izw72tpv
241 04:37:20.110132 extracting modules file /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11241313/extract-overlay-ramdisk-ohhq9io6/ramdisk
242 04:37:20.371535 end: 1.6.4 extract-modules (duration 00:00:01) [common]
243 04:37:20.371713 start: 1.6.5 apply-overlay-tftp (timeout 00:09:48) [common]
244 04:37:20.371815 [common] Applying overlay to NFS
245 04:37:20.371887 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11241313/compress-overlay-t_vs5zk1/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11241313/extract-nfsrootfs-izw72tpv
246 04:37:20.380535 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 04:37:20.380705 start: 1.6.6 configure-preseed-file (timeout 00:09:48) [common]
248 04:37:20.380808 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 04:37:20.380899 start: 1.6.7 compress-ramdisk (timeout 00:09:48) [common]
250 04:37:20.380990 Building ramdisk /var/lib/lava/dispatcher/tmp/11241313/extract-overlay-ramdisk-ohhq9io6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11241313/extract-overlay-ramdisk-ohhq9io6/ramdisk
251 04:37:20.691011 >> 117992 blocks
252 04:37:22.672411 rename /var/lib/lava/dispatcher/tmp/11241313/extract-overlay-ramdisk-ohhq9io6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/ramdisk/ramdisk.cpio.gz
253 04:37:22.672870 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 04:37:22.673007 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
255 04:37:22.673106 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
256 04:37:22.673213 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/kernel/Image'
257 04:37:36.699278 Returned 0 in 14 seconds
258 04:37:36.799939 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/kernel/image.itb
259 04:37:37.162054 output: FIT description: Kernel Image image with one or more FDT blobs
260 04:37:37.162430 output: Created: Wed Aug 9 05:37:37 2023
261 04:37:37.162539 output: Image 0 (kernel-1)
262 04:37:37.162612 output: Description:
263 04:37:37.162679 output: Created: Wed Aug 9 05:37:37 2023
264 04:37:37.162764 output: Type: Kernel Image
265 04:37:37.162830 output: Compression: lzma compressed
266 04:37:37.162894 output: Data Size: 11036366 Bytes = 10777.70 KiB = 10.53 MiB
267 04:37:37.162957 output: Architecture: AArch64
268 04:37:37.163057 output: OS: Linux
269 04:37:37.163122 output: Load Address: 0x00000000
270 04:37:37.163212 output: Entry Point: 0x00000000
271 04:37:37.163314 output: Hash algo: crc32
272 04:37:37.163405 output: Hash value: 9e750869
273 04:37:37.163464 output: Image 1 (fdt-1)
274 04:37:37.163534 output: Description: mt8192-asurada-spherion-r0
275 04:37:37.163612 output: Created: Wed Aug 9 05:37:37 2023
276 04:37:37.163673 output: Type: Flat Device Tree
277 04:37:37.163729 output: Compression: uncompressed
278 04:37:37.163783 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 04:37:37.163842 output: Architecture: AArch64
280 04:37:37.163910 output: Hash algo: crc32
281 04:37:37.163965 output: Hash value: cc4352de
282 04:37:37.164026 output: Image 2 (ramdisk-1)
283 04:37:37.164104 output: Description: unavailable
284 04:37:37.164163 output: Created: Wed Aug 9 05:37:37 2023
285 04:37:37.164218 output: Type: RAMDisk Image
286 04:37:37.164273 output: Compression: Unknown Compression
287 04:37:37.164329 output: Data Size: 17665617 Bytes = 17251.58 KiB = 16.85 MiB
288 04:37:37.164399 output: Architecture: AArch64
289 04:37:37.164454 output: OS: Linux
290 04:37:37.164508 output: Load Address: unavailable
291 04:37:37.164591 output: Entry Point: unavailable
292 04:37:37.164656 output: Hash algo: crc32
293 04:37:37.164710 output: Hash value: 6db2d08f
294 04:37:37.164765 output: Default Configuration: 'conf-1'
295 04:37:37.164819 output: Configuration 0 (conf-1)
296 04:37:37.164895 output: Description: mt8192-asurada-spherion-r0
297 04:37:37.164951 output: Kernel: kernel-1
298 04:37:37.165005 output: Init Ramdisk: ramdisk-1
299 04:37:37.165083 output: FDT: fdt-1
300 04:37:37.165151 output: Loadables: kernel-1
301 04:37:37.165206 output:
302 04:37:37.165431 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 04:37:37.165549 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 04:37:37.165683 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
305 04:37:37.165786 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
306 04:37:37.165882 No LXC device requested
307 04:37:37.165969 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 04:37:37.166082 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
309 04:37:37.166166 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 04:37:37.166259 Checking files for TFTP limit of 4294967296 bytes.
311 04:37:37.166840 end: 1 tftp-deploy (duration 00:00:29) [common]
312 04:37:37.166957 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 04:37:37.167093 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 04:37:37.167277 substitutions:
315 04:37:37.167384 - {DTB}: 11241313/tftp-deploy-_3v05fm7/dtb/mt8192-asurada-spherion-r0.dtb
316 04:37:37.167462 - {INITRD}: 11241313/tftp-deploy-_3v05fm7/ramdisk/ramdisk.cpio.gz
317 04:37:37.167553 - {KERNEL}: 11241313/tftp-deploy-_3v05fm7/kernel/Image
318 04:37:37.167617 - {LAVA_MAC}: None
319 04:37:37.167677 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11241313/extract-nfsrootfs-izw72tpv
320 04:37:37.167758 - {NFS_SERVER_IP}: 192.168.201.1
321 04:37:37.167818 - {PRESEED_CONFIG}: None
322 04:37:37.167876 - {PRESEED_LOCAL}: None
323 04:37:37.167933 - {RAMDISK}: 11241313/tftp-deploy-_3v05fm7/ramdisk/ramdisk.cpio.gz
324 04:37:37.168025 - {ROOT_PART}: None
325 04:37:37.168090 - {ROOT}: None
326 04:37:37.168151 - {SERVER_IP}: 192.168.201.1
327 04:37:37.168211 - {TEE}: None
328 04:37:37.168306 Parsed boot commands:
329 04:37:37.168391 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 04:37:37.168633 Parsed boot commands: tftpboot 192.168.201.1 11241313/tftp-deploy-_3v05fm7/kernel/image.itb 11241313/tftp-deploy-_3v05fm7/kernel/cmdline
331 04:37:37.168736 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 04:37:37.168827 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 04:37:37.168927 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 04:37:37.169043 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 04:37:37.169121 Not connected, no need to disconnect.
336 04:37:37.169202 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 04:37:37.169312 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 04:37:37.169382 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
339 04:37:37.173438 Setting prompt string to ['lava-test: # ']
340 04:37:37.173834 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 04:37:37.173946 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 04:37:37.174050 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 04:37:37.174167 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 04:37:37.174367 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 04:37:42.312968 >> Command sent successfully.
346 04:37:42.315966 Returned 0 in 5 seconds
347 04:37:42.416356 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 04:37:42.416805 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 04:37:42.416951 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 04:37:42.417083 Setting prompt string to 'Starting depthcharge on Spherion...'
352 04:37:42.417186 Changing prompt to 'Starting depthcharge on Spherion...'
353 04:37:42.417293 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 04:37:42.417689 [Enter `^Ec?' for help]
355 04:37:42.588742
356 04:37:42.588887
357 04:37:42.588964 F0: 102B 0000
358 04:37:42.589030
359 04:37:42.589092 F3: 1001 0000 [0200]
360 04:37:42.589152
361 04:37:42.591965 F3: 1001 0000
362 04:37:42.592046
363 04:37:42.592112 F7: 102D 0000
364 04:37:42.592178
365 04:37:42.595107 F1: 0000 0000
366 04:37:42.595180
367 04:37:42.595243 V0: 0000 0000 [0001]
368 04:37:42.595305
369 04:37:42.598976 00: 0007 8000
370 04:37:42.599056
371 04:37:42.599121 01: 0000 0000
372 04:37:42.599189
373 04:37:42.601792 BP: 0C00 0209 [0000]
374 04:37:42.601864
375 04:37:42.601925 G0: 1182 0000
376 04:37:42.601987
377 04:37:42.602046 EC: 0000 0021 [4000]
378 04:37:42.605348
379 04:37:42.605422 S7: 0000 0000 [0000]
380 04:37:42.605488
381 04:37:42.608846 CC: 0000 0000 [0001]
382 04:37:42.608962
383 04:37:42.609058 T0: 0000 0040 [010F]
384 04:37:42.609153
385 04:37:42.609253 Jump to BL
386 04:37:42.609351
387 04:37:42.635047
388 04:37:42.635191
389 04:37:42.635297
390 04:37:42.642226 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 04:37:42.645559 ARM64: Exception handlers installed.
392 04:37:42.649220 ARM64: Testing exception
393 04:37:42.652235 ARM64: Done test exception
394 04:37:42.659387 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 04:37:42.668901 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 04:37:42.676057 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 04:37:42.686321 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 04:37:42.692393 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 04:37:42.703099 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 04:37:42.713611 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 04:37:42.720793 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 04:37:42.738034 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 04:37:42.741170 WDT: Last reset was cold boot
404 04:37:42.745112 SPI1(PAD0) initialized at 2873684 Hz
405 04:37:42.748363 SPI5(PAD0) initialized at 992727 Hz
406 04:37:42.751331 VBOOT: Loading verstage.
407 04:37:42.757952 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 04:37:42.761113 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 04:37:42.764606 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 04:37:42.768026 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 04:37:42.775974 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 04:37:42.782475 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 04:37:42.793009 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
414 04:37:42.793128
415 04:37:42.793236
416 04:37:42.803023 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 04:37:42.806691 ARM64: Exception handlers installed.
418 04:37:42.809932 ARM64: Testing exception
419 04:37:42.810015 ARM64: Done test exception
420 04:37:42.817578 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 04:37:42.820782 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 04:37:42.833750 Probing TPM: . done!
423 04:37:42.833867 TPM ready after 0 ms
424 04:37:42.840640 Connected to device vid:did:rid of 1ae0:0028:00
425 04:37:42.847565 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 04:37:42.888583 Initialized TPM device CR50 revision 0
427 04:37:42.901029 tlcl_send_startup: Startup return code is 0
428 04:37:42.901134 TPM: setup succeeded
429 04:37:42.912175 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 04:37:42.921128 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 04:37:42.933196 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 04:37:42.941897 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 04:37:42.945662 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 04:37:42.949280 in-header: 03 07 00 00 08 00 00 00
435 04:37:42.952829 in-data: aa e4 47 04 13 02 00 00
436 04:37:42.956583 Chrome EC: UHEPI supported
437 04:37:42.963856 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 04:37:42.967194 in-header: 03 9d 00 00 08 00 00 00
439 04:37:42.971028 in-data: 10 20 20 08 00 00 00 00
440 04:37:42.971113 Phase 1
441 04:37:42.974199 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 04:37:42.981929 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 04:37:42.985916 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 04:37:42.988771 Recovery requested (1009000e)
445 04:37:42.993060 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 04:37:43.001853 tlcl_extend: response is 0
447 04:37:43.010023 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 04:37:43.015093 tlcl_extend: response is 0
449 04:37:43.022164 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 04:37:43.043347 read SPI 0x210d4 0x2173b: 15148 us, 9045 KB/s, 72.360 Mbps
451 04:37:43.050209 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 04:37:43.050338
453 04:37:43.050442
454 04:37:43.061106 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 04:37:43.061192 ARM64: Exception handlers installed.
456 04:37:43.064669 ARM64: Testing exception
457 04:37:43.068142 ARM64: Done test exception
458 04:37:43.088594 pmic_efuse_setting: Set efuses in 11 msecs
459 04:37:43.092424 pmwrap_interface_init: Select PMIF_VLD_RDY
460 04:37:43.095560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 04:37:43.103439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 04:37:43.107225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 04:37:43.110807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 04:37:43.117933 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 04:37:43.121640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 04:37:43.125211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 04:37:43.132004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 04:37:43.135238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 04:37:43.138925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 04:37:43.145259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 04:37:43.149029 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 04:37:43.155660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 04:37:43.158885 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 04:37:43.165685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 04:37:43.172005 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 04:37:43.178706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 04:37:43.182027 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 04:37:43.188927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 04:37:43.193165 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 04:37:43.200035 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 04:37:43.204174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 04:37:43.210951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 04:37:43.217707 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 04:37:43.220848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 04:37:43.227952 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 04:37:43.231450 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 04:37:43.238468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 04:37:43.242301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 04:37:43.245452 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 04:37:43.252494 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 04:37:43.256266 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 04:37:43.263088 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 04:37:43.266850 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 04:37:43.270713 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 04:37:43.278332 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 04:37:43.281570 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 04:37:43.287867 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 04:37:43.290912 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 04:37:43.294450 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 04:37:43.301288 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 04:37:43.304628 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 04:37:43.307945 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 04:37:43.314559 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 04:37:43.317763 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 04:37:43.321488 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 04:37:43.324427 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 04:37:43.331020 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 04:37:43.334712 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 04:37:43.337935 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 04:37:43.341191 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 04:37:43.350997 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 04:37:43.358138 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 04:37:43.364501 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 04:37:43.371485 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 04:37:43.381097 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 04:37:43.384532 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 04:37:43.387611 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 04:37:43.394591 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 04:37:43.401327 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x23
520 04:37:43.408107 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 04:37:43.411121 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 04:37:43.414425 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 04:37:43.425356 [RTC]rtc_get_frequency_meter,154: input=15, output=793
524 04:37:43.428194 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 04:37:43.435171 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 04:37:43.438578 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
527 04:37:43.441674 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 04:37:43.445293 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 04:37:43.448297 ADC[4]: Raw value=896670 ID=7
530 04:37:43.452115 ADC[3]: Raw value=213070 ID=1
531 04:37:43.455394 RAM Code: 0x71
532 04:37:43.458679 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 04:37:43.461717 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 04:37:43.471977 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 04:37:43.479336 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 04:37:43.482635 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 04:37:43.485778 in-header: 03 07 00 00 08 00 00 00
538 04:37:43.489003 in-data: aa e4 47 04 13 02 00 00
539 04:37:43.489111 Chrome EC: UHEPI supported
540 04:37:43.496185 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 04:37:43.499545 in-header: 03 d5 00 00 08 00 00 00
542 04:37:43.503242 in-data: 98 20 60 08 00 00 00 00
543 04:37:43.507212 MRC: failed to locate region type 0.
544 04:37:43.514033 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 04:37:43.517652 DRAM-K: Running full calibration
546 04:37:43.524329 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 04:37:43.524449 header.status = 0x0
548 04:37:43.527793 header.version = 0x6 (expected: 0x6)
549 04:37:43.531293 header.size = 0xd00 (expected: 0xd00)
550 04:37:43.534888 header.flags = 0x0
551 04:37:43.538643 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 04:37:43.557490 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
553 04:37:43.563920 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 04:37:43.567054 dram_init: ddr_geometry: 2
555 04:37:43.570693 [EMI] MDL number = 2
556 04:37:43.570774 [EMI] Get MDL freq = 0
557 04:37:43.573899 dram_init: ddr_type: 0
558 04:37:43.573974 is_discrete_lpddr4: 1
559 04:37:43.577144 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 04:37:43.577218
561 04:37:43.577280
562 04:37:43.580917 [Bian_co] ETT version 0.0.0.1
563 04:37:43.587455 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 04:37:43.587541
565 04:37:43.590672 dramc_set_vcore_voltage set vcore to 650000
566 04:37:43.593900 Read voltage for 800, 4
567 04:37:43.594000 Vio18 = 0
568 04:37:43.594068 Vcore = 650000
569 04:37:43.594130 Vdram = 0
570 04:37:43.597054 Vddq = 0
571 04:37:43.597138 Vmddr = 0
572 04:37:43.600949 dram_init: config_dvfs: 1
573 04:37:43.604129 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 04:37:43.610357 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 04:37:43.614132 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 04:37:43.617258 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 04:37:43.620524 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 04:37:43.623688 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 04:37:43.626901 MEM_TYPE=3, freq_sel=18
580 04:37:43.630467 sv_algorithm_assistance_LP4_1600
581 04:37:43.634094 ============ PULL DRAM RESETB DOWN ============
582 04:37:43.637365 ========== PULL DRAM RESETB DOWN end =========
583 04:37:43.643585 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 04:37:43.647069 ===================================
585 04:37:43.650584 LPDDR4 DRAM CONFIGURATION
586 04:37:43.653708 ===================================
587 04:37:43.653831 EX_ROW_EN[0] = 0x0
588 04:37:43.657352 EX_ROW_EN[1] = 0x0
589 04:37:43.657439 LP4Y_EN = 0x0
590 04:37:43.660746 WORK_FSP = 0x0
591 04:37:43.660830 WL = 0x2
592 04:37:43.664216 RL = 0x2
593 04:37:43.664299 BL = 0x2
594 04:37:43.667223 RPST = 0x0
595 04:37:43.667307 RD_PRE = 0x0
596 04:37:43.670952 WR_PRE = 0x1
597 04:37:43.671032 WR_PST = 0x0
598 04:37:43.674114 DBI_WR = 0x0
599 04:37:43.674211 DBI_RD = 0x0
600 04:37:43.677638 OTF = 0x1
601 04:37:43.681019 ===================================
602 04:37:43.684231 ===================================
603 04:37:43.684315 ANA top config
604 04:37:43.687405 ===================================
605 04:37:43.690793 DLL_ASYNC_EN = 0
606 04:37:43.694531 ALL_SLAVE_EN = 1
607 04:37:43.697428 NEW_RANK_MODE = 1
608 04:37:43.697508 DLL_IDLE_MODE = 1
609 04:37:43.700648 LP45_APHY_COMB_EN = 1
610 04:37:43.703852 TX_ODT_DIS = 1
611 04:37:43.707165 NEW_8X_MODE = 1
612 04:37:43.710271 ===================================
613 04:37:43.713979 ===================================
614 04:37:43.717016 data_rate = 1600
615 04:37:43.717099 CKR = 1
616 04:37:43.720655 DQ_P2S_RATIO = 8
617 04:37:43.723753 ===================================
618 04:37:43.727042 CA_P2S_RATIO = 8
619 04:37:43.730247 DQ_CA_OPEN = 0
620 04:37:43.734033 DQ_SEMI_OPEN = 0
621 04:37:43.736861 CA_SEMI_OPEN = 0
622 04:37:43.736942 CA_FULL_RATE = 0
623 04:37:43.740608 DQ_CKDIV4_EN = 1
624 04:37:43.743835 CA_CKDIV4_EN = 1
625 04:37:43.746732 CA_PREDIV_EN = 0
626 04:37:43.750601 PH8_DLY = 0
627 04:37:43.754028 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 04:37:43.754137 DQ_AAMCK_DIV = 4
629 04:37:43.757655 CA_AAMCK_DIV = 4
630 04:37:43.761187 CA_ADMCK_DIV = 4
631 04:37:43.764964 DQ_TRACK_CA_EN = 0
632 04:37:43.765049 CA_PICK = 800
633 04:37:43.768332 CA_MCKIO = 800
634 04:37:43.772494 MCKIO_SEMI = 0
635 04:37:43.776117 PLL_FREQ = 3068
636 04:37:43.776218 DQ_UI_PI_RATIO = 32
637 04:37:43.779607 CA_UI_PI_RATIO = 0
638 04:37:43.783658 ===================================
639 04:37:43.787497 ===================================
640 04:37:43.791186 memory_type:LPDDR4
641 04:37:43.791267 GP_NUM : 10
642 04:37:43.794436 SRAM_EN : 1
643 04:37:43.794517 MD32_EN : 0
644 04:37:43.798185 ===================================
645 04:37:43.802026 [ANA_INIT] >>>>>>>>>>>>>>
646 04:37:43.805801 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 04:37:43.809040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 04:37:43.809180 ===================================
649 04:37:43.812910 data_rate = 1600,PCW = 0X7600
650 04:37:43.817255 ===================================
651 04:37:43.820925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 04:37:43.824556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 04:37:43.831595 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 04:37:43.835876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 04:37:43.839500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 04:37:43.842560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 04:37:43.846267 [ANA_INIT] flow start
658 04:37:43.846349 [ANA_INIT] PLL >>>>>>>>
659 04:37:43.850132 [ANA_INIT] PLL <<<<<<<<
660 04:37:43.850230 [ANA_INIT] MIDPI >>>>>>>>
661 04:37:43.853856 [ANA_INIT] MIDPI <<<<<<<<
662 04:37:43.857710 [ANA_INIT] DLL >>>>>>>>
663 04:37:43.857828 [ANA_INIT] flow end
664 04:37:43.861052 ============ LP4 DIFF to SE enter ============
665 04:37:43.864927 ============ LP4 DIFF to SE exit ============
666 04:37:43.868361 [ANA_INIT] <<<<<<<<<<<<<
667 04:37:43.872211 [Flow] Enable top DCM control >>>>>
668 04:37:43.875851 [Flow] Enable top DCM control <<<<<
669 04:37:43.879841 Enable DLL master slave shuffle
670 04:37:43.883460 ==============================================================
671 04:37:43.887071 Gating Mode config
672 04:37:43.890530 ==============================================================
673 04:37:43.893541 Config description:
674 04:37:43.904035 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 04:37:43.910600 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 04:37:43.913882 SELPH_MODE 0: By rank 1: By Phase
677 04:37:43.920731 ==============================================================
678 04:37:43.923657 GAT_TRACK_EN = 1
679 04:37:43.927192 RX_GATING_MODE = 2
680 04:37:43.927273 RX_GATING_TRACK_MODE = 2
681 04:37:43.930262 SELPH_MODE = 1
682 04:37:43.933483 PICG_EARLY_EN = 1
683 04:37:43.937298 VALID_LAT_VALUE = 1
684 04:37:43.944069 ==============================================================
685 04:37:43.947072 Enter into Gating configuration >>>>
686 04:37:43.950797 Exit from Gating configuration <<<<
687 04:37:43.953910 Enter into DVFS_PRE_config >>>>>
688 04:37:43.963890 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 04:37:43.967028 Exit from DVFS_PRE_config <<<<<
690 04:37:43.970222 Enter into PICG configuration >>>>
691 04:37:43.973978 Exit from PICG configuration <<<<
692 04:37:43.977114 [RX_INPUT] configuration >>>>>
693 04:37:43.980250 [RX_INPUT] configuration <<<<<
694 04:37:43.983733 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 04:37:43.990360 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 04:37:43.996936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 04:37:44.000312 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 04:37:44.006979 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 04:37:44.013759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 04:37:44.016963 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 04:37:44.020832 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 04:37:44.027074 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 04:37:44.030093 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 04:37:44.033830 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 04:37:44.040332 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 04:37:44.043630 ===================================
707 04:37:44.043715 LPDDR4 DRAM CONFIGURATION
708 04:37:44.047260 ===================================
709 04:37:44.050553 EX_ROW_EN[0] = 0x0
710 04:37:44.053615 EX_ROW_EN[1] = 0x0
711 04:37:44.053702 LP4Y_EN = 0x0
712 04:37:44.056941 WORK_FSP = 0x0
713 04:37:44.057024 WL = 0x2
714 04:37:44.060700 RL = 0x2
715 04:37:44.060785 BL = 0x2
716 04:37:44.063835 RPST = 0x0
717 04:37:44.063918 RD_PRE = 0x0
718 04:37:44.067264 WR_PRE = 0x1
719 04:37:44.067347 WR_PST = 0x0
720 04:37:44.070269 DBI_WR = 0x0
721 04:37:44.070352 DBI_RD = 0x0
722 04:37:44.073565 OTF = 0x1
723 04:37:44.077019 ===================================
724 04:37:44.080255 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 04:37:44.083389 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 04:37:44.090475 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 04:37:44.093750 ===================================
728 04:37:44.093836 LPDDR4 DRAM CONFIGURATION
729 04:37:44.096902 ===================================
730 04:37:44.100102 EX_ROW_EN[0] = 0x10
731 04:37:44.100187 EX_ROW_EN[1] = 0x0
732 04:37:44.103930 LP4Y_EN = 0x0
733 04:37:44.104041 WORK_FSP = 0x0
734 04:37:44.107466 WL = 0x2
735 04:37:44.107548 RL = 0x2
736 04:37:44.111165 BL = 0x2
737 04:37:44.111245 RPST = 0x0
738 04:37:44.115199 RD_PRE = 0x0
739 04:37:44.115314 WR_PRE = 0x1
740 04:37:44.118911 WR_PST = 0x0
741 04:37:44.118992 DBI_WR = 0x0
742 04:37:44.122097 DBI_RD = 0x0
743 04:37:44.122184 OTF = 0x1
744 04:37:44.125778 ===================================
745 04:37:44.132873 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 04:37:44.136547 nWR fixed to 40
747 04:37:44.136660 [ModeRegInit_LP4] CH0 RK0
748 04:37:44.140409 [ModeRegInit_LP4] CH0 RK1
749 04:37:44.144269 [ModeRegInit_LP4] CH1 RK0
750 04:37:44.144351 [ModeRegInit_LP4] CH1 RK1
751 04:37:44.148162 match AC timing 13
752 04:37:44.151085 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 04:37:44.154843 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 04:37:44.158136 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 04:37:44.165681 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 04:37:44.169471 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 04:37:44.169557 [EMI DOE] emi_dcm 0
758 04:37:44.173413 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 04:37:44.177209 ==
760 04:37:44.177296 Dram Type= 6, Freq= 0, CH_0, rank 0
761 04:37:44.181060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 04:37:44.184808 ==
763 04:37:44.187898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 04:37:44.195553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 04:37:44.203490 [CA 0] Center 38 (7~69) winsize 63
766 04:37:44.207418 [CA 1] Center 37 (7~68) winsize 62
767 04:37:44.211235 [CA 2] Center 35 (5~66) winsize 62
768 04:37:44.215139 [CA 3] Center 35 (5~66) winsize 62
769 04:37:44.218133 [CA 4] Center 34 (4~65) winsize 62
770 04:37:44.222522 [CA 5] Center 34 (4~65) winsize 62
771 04:37:44.222643
772 04:37:44.225855 [CmdBusTrainingLP45] Vref(ca) range 1: 34
773 04:37:44.225964
774 04:37:44.229502 [CATrainingPosCal] consider 1 rank data
775 04:37:44.229613 u2DelayCellTimex100 = 270/100 ps
776 04:37:44.233299 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
777 04:37:44.236890 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
778 04:37:44.240635 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
779 04:37:44.244708 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
780 04:37:44.249037 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
781 04:37:44.253007 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
782 04:37:44.253117
783 04:37:44.256642 CA PerBit enable=1, Macro0, CA PI delay=34
784 04:37:44.256735
785 04:37:44.260283 [CBTSetCACLKResult] CA Dly = 34
786 04:37:44.260366 CS Dly: 6 (0~37)
787 04:37:44.260433 ==
788 04:37:44.263588 Dram Type= 6, Freq= 0, CH_0, rank 1
789 04:37:44.268328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 04:37:44.268421 ==
791 04:37:44.275048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 04:37:44.278821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 04:37:44.289545 [CA 0] Center 38 (7~69) winsize 63
794 04:37:44.293377 [CA 1] Center 37 (7~68) winsize 62
795 04:37:44.297125 [CA 2] Center 35 (5~66) winsize 62
796 04:37:44.300962 [CA 3] Center 35 (5~66) winsize 62
797 04:37:44.304791 [CA 4] Center 34 (4~65) winsize 62
798 04:37:44.308060 [CA 5] Center 34 (4~65) winsize 62
799 04:37:44.308146
800 04:37:44.311910 [CmdBusTrainingLP45] Vref(ca) range 1: 30
801 04:37:44.311995
802 04:37:44.315712 [CATrainingPosCal] consider 2 rank data
803 04:37:44.315797 u2DelayCellTimex100 = 270/100 ps
804 04:37:44.319399 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 04:37:44.323264 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 04:37:44.326744 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 04:37:44.330864 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 04:37:44.333950 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 04:37:44.337251 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
810 04:37:44.337338
811 04:37:44.344763 CA PerBit enable=1, Macro0, CA PI delay=34
812 04:37:44.344851
813 04:37:44.344918 [CBTSetCACLKResult] CA Dly = 34
814 04:37:44.348603 CS Dly: 6 (0~38)
815 04:37:44.348688
816 04:37:44.351891 ----->DramcWriteLeveling(PI) begin...
817 04:37:44.351980 ==
818 04:37:44.355939 Dram Type= 6, Freq= 0, CH_0, rank 0
819 04:37:44.359516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 04:37:44.359602 ==
821 04:37:44.362564 Write leveling (Byte 0): 35 => 35
822 04:37:44.366257 Write leveling (Byte 1): 31 => 31
823 04:37:44.366342 DramcWriteLeveling(PI) end<-----
824 04:37:44.366409
825 04:37:44.369946 ==
826 04:37:44.370031 Dram Type= 6, Freq= 0, CH_0, rank 0
827 04:37:44.378013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 04:37:44.378100 ==
829 04:37:44.378168 [Gating] SW mode calibration
830 04:37:44.385158 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 04:37:44.392281 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 04:37:44.395993 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 04:37:44.399947 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
834 04:37:44.403710 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
835 04:37:44.406887 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
836 04:37:44.413343 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 04:37:44.417279 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 04:37:44.420330 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 04:37:44.427265 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 04:37:44.430495 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 04:37:44.434344 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 04:37:44.438266 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 04:37:44.445579 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 04:37:44.448913 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 04:37:44.451910 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 04:37:44.456173 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 04:37:44.459499 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 04:37:44.466396 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 04:37:44.469552 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
850 04:37:44.473042 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
851 04:37:44.479756 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
852 04:37:44.482940 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 04:37:44.486044 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 04:37:44.493006 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 04:37:44.496472 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 04:37:44.499409 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 04:37:44.506393 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 04:37:44.509665 0 9 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
859 04:37:44.512968 0 9 12 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (0 0)
860 04:37:44.519452 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
861 04:37:44.523120 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 04:37:44.526083 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 04:37:44.533122 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 04:37:44.536387 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 04:37:44.539644 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 04:37:44.546415 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
867 04:37:44.549562 0 10 12 | B1->B0 | 3030 2727 | 0 0 | (0 1) (1 0)
868 04:37:44.552728 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 04:37:44.556554 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 04:37:44.563019 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 04:37:44.566774 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 04:37:44.569673 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 04:37:44.576627 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 04:37:44.579899 0 11 8 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (0 0)
875 04:37:44.583243 0 11 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
876 04:37:44.589448 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 04:37:44.593285 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 04:37:44.596109 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 04:37:44.603078 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 04:37:44.606100 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 04:37:44.609780 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 04:37:44.616083 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
883 04:37:44.619277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
884 04:37:44.622642 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 04:37:44.629323 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 04:37:44.633098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 04:37:44.636279 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 04:37:44.642770 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 04:37:44.645797 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 04:37:44.649550 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 04:37:44.655794 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 04:37:44.659564 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 04:37:44.662663 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 04:37:44.665826 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 04:37:44.672883 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 04:37:44.675972 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 04:37:44.679050 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 04:37:44.686072 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 04:37:44.689611 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
900 04:37:44.692643 Total UI for P1: 0, mck2ui 16
901 04:37:44.696314 best dqsien dly found for B0: ( 0, 14, 10)
902 04:37:44.699514 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 04:37:44.702758 Total UI for P1: 0, mck2ui 16
904 04:37:44.705964 best dqsien dly found for B1: ( 0, 14, 12)
905 04:37:44.709483 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
906 04:37:44.712988 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
907 04:37:44.713101
908 04:37:44.719359 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
909 04:37:44.722560 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
910 04:37:44.725790 [Gating] SW calibration Done
911 04:37:44.725871 ==
912 04:37:44.729540 Dram Type= 6, Freq= 0, CH_0, rank 0
913 04:37:44.732536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 04:37:44.732641 ==
915 04:37:44.732722 RX Vref Scan: 0
916 04:37:44.732783
917 04:37:44.736140 RX Vref 0 -> 0, step: 1
918 04:37:44.736213
919 04:37:44.739553 RX Delay -130 -> 252, step: 16
920 04:37:44.742821 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
921 04:37:44.746062 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
922 04:37:44.753117 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
923 04:37:44.756500 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
924 04:37:44.759613 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
925 04:37:44.762794 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
926 04:37:44.766426 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
927 04:37:44.769648 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
928 04:37:44.776024 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
929 04:37:44.779865 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
930 04:37:44.782726 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
931 04:37:44.786536 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
932 04:37:44.789777 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
933 04:37:44.796621 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
934 04:37:44.799811 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
935 04:37:44.802973 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
936 04:37:44.803056 ==
937 04:37:44.806270 Dram Type= 6, Freq= 0, CH_0, rank 0
938 04:37:44.809806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
939 04:37:44.809885 ==
940 04:37:44.812724 DQS Delay:
941 04:37:44.812801 DQS0 = 0, DQS1 = 0
942 04:37:44.816057 DQM Delay:
943 04:37:44.816181 DQM0 = 78, DQM1 = 69
944 04:37:44.816278 DQ Delay:
945 04:37:44.819726 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
946 04:37:44.822782 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =85
947 04:37:44.826268 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
948 04:37:44.829978 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
949 04:37:44.830059
950 04:37:44.830125
951 04:37:44.833185 ==
952 04:37:44.837132 Dram Type= 6, Freq= 0, CH_0, rank 0
953 04:37:44.840094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 04:37:44.840203 ==
955 04:37:44.840311
956 04:37:44.840402
957 04:37:44.840497 TX Vref Scan disable
958 04:37:44.843725 == TX Byte 0 ==
959 04:37:44.847248 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
960 04:37:44.850850 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
961 04:37:44.853815 == TX Byte 1 ==
962 04:37:44.857018 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
963 04:37:44.860688 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
964 04:37:44.863906 ==
965 04:37:44.867454 Dram Type= 6, Freq= 0, CH_0, rank 0
966 04:37:44.870580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 04:37:44.870656 ==
968 04:37:44.883284 TX Vref=22, minBit 3, minWin=26, winSum=432
969 04:37:44.886390 TX Vref=24, minBit 14, minWin=26, winSum=438
970 04:37:44.889522 TX Vref=26, minBit 2, minWin=27, winSum=441
971 04:37:44.893324 TX Vref=28, minBit 5, minWin=27, winSum=443
972 04:37:44.896482 TX Vref=30, minBit 5, minWin=27, winSum=444
973 04:37:44.899607 TX Vref=32, minBit 9, minWin=26, winSum=438
974 04:37:44.906273 [TxChooseVref] Worse bit 5, Min win 27, Win sum 444, Final Vref 30
975 04:37:44.906357
976 04:37:44.909564 Final TX Range 1 Vref 30
977 04:37:44.909639
978 04:37:44.909709 ==
979 04:37:44.913308 Dram Type= 6, Freq= 0, CH_0, rank 0
980 04:37:44.916626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 04:37:44.916707 ==
982 04:37:44.916774
983 04:37:44.919618
984 04:37:44.919691 TX Vref Scan disable
985 04:37:44.923000 == TX Byte 0 ==
986 04:37:44.926485 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
987 04:37:44.932962 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
988 04:37:44.933046 == TX Byte 1 ==
989 04:37:44.936659 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
990 04:37:44.943063 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
991 04:37:44.943146
992 04:37:44.943213 [DATLAT]
993 04:37:44.943278 Freq=800, CH0 RK0
994 04:37:44.943339
995 04:37:44.946264 DATLAT Default: 0xa
996 04:37:44.946365 0, 0xFFFF, sum = 0
997 04:37:44.949851 1, 0xFFFF, sum = 0
998 04:37:44.952764 2, 0xFFFF, sum = 0
999 04:37:44.952866 3, 0xFFFF, sum = 0
1000 04:37:44.956417 4, 0xFFFF, sum = 0
1001 04:37:44.956498 5, 0xFFFF, sum = 0
1002 04:37:44.959407 6, 0xFFFF, sum = 0
1003 04:37:44.959493 7, 0xFFFF, sum = 0
1004 04:37:44.963197 8, 0xFFFF, sum = 0
1005 04:37:44.963274 9, 0x0, sum = 1
1006 04:37:44.966267 10, 0x0, sum = 2
1007 04:37:44.966346 11, 0x0, sum = 3
1008 04:37:44.966411 12, 0x0, sum = 4
1009 04:37:44.969303 best_step = 10
1010 04:37:44.969373
1011 04:37:44.969439 ==
1012 04:37:44.973039 Dram Type= 6, Freq= 0, CH_0, rank 0
1013 04:37:44.976293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1014 04:37:44.976412 ==
1015 04:37:44.979501 RX Vref Scan: 1
1016 04:37:44.979578
1017 04:37:44.982574 Set Vref Range= 32 -> 127
1018 04:37:44.982682
1019 04:37:44.982785 RX Vref 32 -> 127, step: 1
1020 04:37:44.982887
1021 04:37:44.985845 RX Delay -111 -> 252, step: 8
1022 04:37:44.985958
1023 04:37:44.989728 Set Vref, RX VrefLevel [Byte0]: 32
1024 04:37:44.992791 [Byte1]: 32
1025 04:37:44.995964
1026 04:37:44.996088 Set Vref, RX VrefLevel [Byte0]: 33
1027 04:37:44.999201 [Byte1]: 33
1028 04:37:45.003794
1029 04:37:45.003912 Set Vref, RX VrefLevel [Byte0]: 34
1030 04:37:45.007021 [Byte1]: 34
1031 04:37:45.011518
1032 04:37:45.011624 Set Vref, RX VrefLevel [Byte0]: 35
1033 04:37:45.014562 [Byte1]: 35
1034 04:37:45.019457
1035 04:37:45.019538 Set Vref, RX VrefLevel [Byte0]: 36
1036 04:37:45.022078 [Byte1]: 36
1037 04:37:45.026633
1038 04:37:45.026713 Set Vref, RX VrefLevel [Byte0]: 37
1039 04:37:45.030114 [Byte1]: 37
1040 04:37:45.033968
1041 04:37:45.034070 Set Vref, RX VrefLevel [Byte0]: 38
1042 04:37:45.037514 [Byte1]: 38
1043 04:37:45.041926
1044 04:37:45.042030 Set Vref, RX VrefLevel [Byte0]: 39
1045 04:37:45.045347 [Byte1]: 39
1046 04:37:45.049334
1047 04:37:45.049412 Set Vref, RX VrefLevel [Byte0]: 40
1048 04:37:45.053093 [Byte1]: 40
1049 04:37:45.057312
1050 04:37:45.057389 Set Vref, RX VrefLevel [Byte0]: 41
1051 04:37:45.060265 [Byte1]: 41
1052 04:37:45.065084
1053 04:37:45.065159 Set Vref, RX VrefLevel [Byte0]: 42
1054 04:37:45.067977 [Byte1]: 42
1055 04:37:45.072289
1056 04:37:45.072365 Set Vref, RX VrefLevel [Byte0]: 43
1057 04:37:45.076016 [Byte1]: 43
1058 04:37:45.080479
1059 04:37:45.080571 Set Vref, RX VrefLevel [Byte0]: 44
1060 04:37:45.083670 [Byte1]: 44
1061 04:37:45.087491
1062 04:37:45.087565 Set Vref, RX VrefLevel [Byte0]: 45
1063 04:37:45.091312 [Byte1]: 45
1064 04:37:45.095708
1065 04:37:45.095846 Set Vref, RX VrefLevel [Byte0]: 46
1066 04:37:45.098800 [Byte1]: 46
1067 04:37:45.103150
1068 04:37:45.103229 Set Vref, RX VrefLevel [Byte0]: 47
1069 04:37:45.106380 [Byte1]: 47
1070 04:37:45.110883
1071 04:37:45.110976 Set Vref, RX VrefLevel [Byte0]: 48
1072 04:37:45.114139 [Byte1]: 48
1073 04:37:45.118631
1074 04:37:45.118724 Set Vref, RX VrefLevel [Byte0]: 49
1075 04:37:45.121853 [Byte1]: 49
1076 04:37:45.126224
1077 04:37:45.126316 Set Vref, RX VrefLevel [Byte0]: 50
1078 04:37:45.129790 [Byte1]: 50
1079 04:37:45.133997
1080 04:37:45.134079 Set Vref, RX VrefLevel [Byte0]: 51
1081 04:37:45.137265 [Byte1]: 51
1082 04:37:45.141808
1083 04:37:45.141881 Set Vref, RX VrefLevel [Byte0]: 52
1084 04:37:45.144697 [Byte1]: 52
1085 04:37:45.148691
1086 04:37:45.148768 Set Vref, RX VrefLevel [Byte0]: 53
1087 04:37:45.152020 [Byte1]: 53
1088 04:37:45.156310
1089 04:37:45.156386 Set Vref, RX VrefLevel [Byte0]: 54
1090 04:37:45.160104 [Byte1]: 54
1091 04:37:45.164264
1092 04:37:45.164337 Set Vref, RX VrefLevel [Byte0]: 55
1093 04:37:45.167445 [Byte1]: 55
1094 04:37:45.171622
1095 04:37:45.171701 Set Vref, RX VrefLevel [Byte0]: 56
1096 04:37:45.175065 [Byte1]: 56
1097 04:37:45.179290
1098 04:37:45.179395 Set Vref, RX VrefLevel [Byte0]: 57
1099 04:37:45.182998 [Byte1]: 57
1100 04:37:45.187247
1101 04:37:45.187355 Set Vref, RX VrefLevel [Byte0]: 58
1102 04:37:45.190570 [Byte1]: 58
1103 04:37:45.195037
1104 04:37:45.195114 Set Vref, RX VrefLevel [Byte0]: 59
1105 04:37:45.198241 [Byte1]: 59
1106 04:37:45.202490
1107 04:37:45.202566 Set Vref, RX VrefLevel [Byte0]: 60
1108 04:37:45.205738 [Byte1]: 60
1109 04:37:45.210213
1110 04:37:45.210289 Set Vref, RX VrefLevel [Byte0]: 61
1111 04:37:45.213361 [Byte1]: 61
1112 04:37:45.217898
1113 04:37:45.217971 Set Vref, RX VrefLevel [Byte0]: 62
1114 04:37:45.221192 [Byte1]: 62
1115 04:37:45.225146
1116 04:37:45.225226 Set Vref, RX VrefLevel [Byte0]: 63
1117 04:37:45.228982 [Byte1]: 63
1118 04:37:45.233348
1119 04:37:45.233438 Set Vref, RX VrefLevel [Byte0]: 64
1120 04:37:45.236420 [Byte1]: 64
1121 04:37:45.240475
1122 04:37:45.244291 Set Vref, RX VrefLevel [Byte0]: 65
1123 04:37:45.247497 [Byte1]: 65
1124 04:37:45.247608
1125 04:37:45.250713 Set Vref, RX VrefLevel [Byte0]: 66
1126 04:37:45.253975 [Byte1]: 66
1127 04:37:45.254102
1128 04:37:45.257086 Set Vref, RX VrefLevel [Byte0]: 67
1129 04:37:45.260651 [Byte1]: 67
1130 04:37:45.260757
1131 04:37:45.264241 Set Vref, RX VrefLevel [Byte0]: 68
1132 04:37:45.267337 [Byte1]: 68
1133 04:37:45.271086
1134 04:37:45.271202 Set Vref, RX VrefLevel [Byte0]: 69
1135 04:37:45.274648 [Byte1]: 69
1136 04:37:45.278984
1137 04:37:45.279066 Set Vref, RX VrefLevel [Byte0]: 70
1138 04:37:45.282307 [Byte1]: 70
1139 04:37:45.286451
1140 04:37:45.286527 Set Vref, RX VrefLevel [Byte0]: 71
1141 04:37:45.289881 [Byte1]: 71
1142 04:37:45.294461
1143 04:37:45.294556 Set Vref, RX VrefLevel [Byte0]: 72
1144 04:37:45.297560 [Byte1]: 72
1145 04:37:45.301975
1146 04:37:45.302058 Set Vref, RX VrefLevel [Byte0]: 73
1147 04:37:45.305295 [Byte1]: 73
1148 04:37:45.309367
1149 04:37:45.309444 Set Vref, RX VrefLevel [Byte0]: 74
1150 04:37:45.312603 [Byte1]: 74
1151 04:37:45.317179
1152 04:37:45.317282 Set Vref, RX VrefLevel [Byte0]: 75
1153 04:37:45.320375 [Byte1]: 75
1154 04:37:45.325004
1155 04:37:45.325082 Set Vref, RX VrefLevel [Byte0]: 76
1156 04:37:45.328040 [Byte1]: 76
1157 04:37:45.332491
1158 04:37:45.332567 Set Vref, RX VrefLevel [Byte0]: 77
1159 04:37:45.335582 [Byte1]: 77
1160 04:37:45.340415
1161 04:37:45.340492 Set Vref, RX VrefLevel [Byte0]: 78
1162 04:37:45.343262 [Byte1]: 78
1163 04:37:45.347914
1164 04:37:45.347989 Set Vref, RX VrefLevel [Byte0]: 79
1165 04:37:45.351046 [Byte1]: 79
1166 04:37:45.355345
1167 04:37:45.355431 Final RX Vref Byte 0 = 59 to rank0
1168 04:37:45.358653 Final RX Vref Byte 1 = 61 to rank0
1169 04:37:45.361890 Final RX Vref Byte 0 = 59 to rank1
1170 04:37:45.365573 Final RX Vref Byte 1 = 61 to rank1==
1171 04:37:45.368663 Dram Type= 6, Freq= 0, CH_0, rank 0
1172 04:37:45.375178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 04:37:45.375258 ==
1174 04:37:45.375323 DQS Delay:
1175 04:37:45.375402 DQS0 = 0, DQS1 = 0
1176 04:37:45.379195 DQM Delay:
1177 04:37:45.379297 DQM0 = 82, DQM1 = 68
1178 04:37:45.382191 DQ Delay:
1179 04:37:45.385267 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1180 04:37:45.385338 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1181 04:37:45.389194 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1182 04:37:45.395103 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =76
1183 04:37:45.395192
1184 04:37:45.395256
1185 04:37:45.401833 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1186 04:37:45.405367 CH0 RK0: MR19=606, MR18=2323
1187 04:37:45.412099 CH0_RK0: MR19=0x606, MR18=0x2323, DQSOSC=401, MR23=63, INC=91, DEC=61
1188 04:37:45.412183
1189 04:37:45.415914 ----->DramcWriteLeveling(PI) begin...
1190 04:37:45.416002 ==
1191 04:37:45.418528 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 04:37:45.421844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 04:37:45.421917 ==
1194 04:37:45.425471 Write leveling (Byte 0): 32 => 32
1195 04:37:45.428501 Write leveling (Byte 1): 31 => 31
1196 04:37:45.432359 DramcWriteLeveling(PI) end<-----
1197 04:37:45.432464
1198 04:37:45.432555 ==
1199 04:37:45.435489 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 04:37:45.438594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 04:37:45.438672 ==
1202 04:37:45.442330 [Gating] SW mode calibration
1203 04:37:45.448515 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1204 04:37:45.455568 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1205 04:37:45.458610 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 04:37:45.461854 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1207 04:37:45.468896 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1208 04:37:45.472108 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 04:37:45.475179 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 04:37:45.482227 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 04:37:45.485125 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 04:37:45.488330 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 04:37:45.495293 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 04:37:45.498347 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 04:37:45.501717 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 04:37:45.508735 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 04:37:45.512029 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 04:37:45.556055 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 04:37:45.556398 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 04:37:45.556490 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 04:37:45.556571 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 04:37:45.556637 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 04:37:45.556715 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1224 04:37:45.556780 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 04:37:45.556852 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 04:37:45.556925 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 04:37:45.556998 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 04:37:45.600125 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 04:37:45.600415 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 04:37:45.600491 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 04:37:45.600580 0 9 8 | B1->B0 | 2323 2e2e | 1 0 | (0 0) (0 0)
1232 04:37:45.600678 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 04:37:45.600787 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 04:37:45.600874 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 04:37:45.600936 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 04:37:45.601007 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 04:37:45.601078 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 04:37:45.619709 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1239 04:37:45.619978 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (1 0)
1240 04:37:45.620050 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 04:37:45.620125 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 04:37:45.623177 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 04:37:45.626519 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 04:37:45.630054 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 04:37:45.633126 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 04:37:45.639593 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1247 04:37:45.643342 0 11 8 | B1->B0 | 3131 4343 | 0 0 | (1 1) (0 0)
1248 04:37:45.646511 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1249 04:37:45.653061 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 04:37:45.656693 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 04:37:45.660026 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 04:37:45.666908 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 04:37:45.670482 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 04:37:45.673865 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1255 04:37:45.677702 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1256 04:37:45.681556 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1257 04:37:45.688096 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 04:37:45.691289 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 04:37:45.695148 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 04:37:45.699243 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 04:37:45.705334 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 04:37:45.709184 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 04:37:45.712261 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 04:37:45.718633 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 04:37:45.722565 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 04:37:45.725575 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 04:37:45.732339 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 04:37:45.735448 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 04:37:45.738670 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 04:37:45.745429 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1271 04:37:45.749214 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1272 04:37:45.752335 Total UI for P1: 0, mck2ui 16
1273 04:37:45.755466 best dqsien dly found for B0: ( 0, 14, 4)
1274 04:37:45.759244 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1275 04:37:45.765715 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 04:37:45.765808 Total UI for P1: 0, mck2ui 16
1277 04:37:45.768717 best dqsien dly found for B1: ( 0, 14, 10)
1278 04:37:45.775544 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1279 04:37:45.779131 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1280 04:37:45.779238
1281 04:37:45.782038 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1282 04:37:45.785800 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1283 04:37:45.789071 [Gating] SW calibration Done
1284 04:37:45.789147 ==
1285 04:37:45.792239 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 04:37:45.795804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 04:37:45.795942 ==
1288 04:37:45.796054 RX Vref Scan: 0
1289 04:37:45.799053
1290 04:37:45.799162 RX Vref 0 -> 0, step: 1
1291 04:37:45.799257
1292 04:37:45.802642 RX Delay -130 -> 252, step: 16
1293 04:37:45.805869 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1294 04:37:45.809445 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1295 04:37:45.815501 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1296 04:37:45.819229 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1297 04:37:45.822476 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1298 04:37:45.825582 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1299 04:37:45.829350 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1300 04:37:45.835656 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1301 04:37:45.839289 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1302 04:37:45.842237 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1303 04:37:45.845631 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1304 04:37:45.849078 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1305 04:37:45.856005 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1306 04:37:45.859252 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1307 04:37:45.862288 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1308 04:37:45.865513 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1309 04:37:45.865615 ==
1310 04:37:45.869168 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 04:37:45.875888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 04:37:45.876003 ==
1313 04:37:45.876103 DQS Delay:
1314 04:37:45.876191 DQS0 = 0, DQS1 = 0
1315 04:37:45.879656 DQM Delay:
1316 04:37:45.879745 DQM0 = 77, DQM1 = 69
1317 04:37:45.882558 DQ Delay:
1318 04:37:45.885552 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1319 04:37:45.885665 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1320 04:37:45.889065 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1321 04:37:45.892675 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1322 04:37:45.896028
1323 04:37:45.896140
1324 04:37:45.896231 ==
1325 04:37:45.899298 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 04:37:45.902384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 04:37:45.902467 ==
1328 04:37:45.902538
1329 04:37:45.902602
1330 04:37:45.906073 TX Vref Scan disable
1331 04:37:45.906175 == TX Byte 0 ==
1332 04:37:45.912286 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1333 04:37:45.915592 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1334 04:37:45.915669 == TX Byte 1 ==
1335 04:37:45.922280 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1336 04:37:45.925506 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1337 04:37:45.925609 ==
1338 04:37:45.929286 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 04:37:45.932515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 04:37:45.932619 ==
1341 04:37:45.946347 TX Vref=22, minBit 11, minWin=26, winSum=435
1342 04:37:45.949290 TX Vref=24, minBit 11, minWin=26, winSum=437
1343 04:37:45.952723 TX Vref=26, minBit 1, minWin=27, winSum=438
1344 04:37:45.955992 TX Vref=28, minBit 13, minWin=26, winSum=438
1345 04:37:45.959660 TX Vref=30, minBit 11, minWin=26, winSum=439
1346 04:37:45.965823 TX Vref=32, minBit 8, minWin=26, winSum=440
1347 04:37:45.969142 [TxChooseVref] Worse bit 1, Min win 27, Win sum 438, Final Vref 26
1348 04:37:45.969258
1349 04:37:45.972961 Final TX Range 1 Vref 26
1350 04:37:45.973059
1351 04:37:45.973123 ==
1352 04:37:45.976045 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 04:37:45.979242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 04:37:45.982351 ==
1355 04:37:45.982431
1356 04:37:45.982495
1357 04:37:45.982555 TX Vref Scan disable
1358 04:37:45.986485 == TX Byte 0 ==
1359 04:37:45.989405 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1360 04:37:45.992839 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1361 04:37:45.996210 == TX Byte 1 ==
1362 04:37:45.999531 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1363 04:37:46.003061 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1364 04:37:46.006246
1365 04:37:46.006341 [DATLAT]
1366 04:37:46.006421 Freq=800, CH0 RK1
1367 04:37:46.006481
1368 04:37:46.009416 DATLAT Default: 0xa
1369 04:37:46.009497 0, 0xFFFF, sum = 0
1370 04:37:46.013110 1, 0xFFFF, sum = 0
1371 04:37:46.013191 2, 0xFFFF, sum = 0
1372 04:37:46.016457 3, 0xFFFF, sum = 0
1373 04:37:46.016543 4, 0xFFFF, sum = 0
1374 04:37:46.019475 5, 0xFFFF, sum = 0
1375 04:37:46.023068 6, 0xFFFF, sum = 0
1376 04:37:46.023195 7, 0xFFFF, sum = 0
1377 04:37:46.026128 8, 0xFFFF, sum = 0
1378 04:37:46.026235 9, 0x0, sum = 1
1379 04:37:46.026333 10, 0x0, sum = 2
1380 04:37:46.030046 11, 0x0, sum = 3
1381 04:37:46.030155 12, 0x0, sum = 4
1382 04:37:46.032988 best_step = 10
1383 04:37:46.033088
1384 04:37:46.033179 ==
1385 04:37:46.036246 Dram Type= 6, Freq= 0, CH_0, rank 1
1386 04:37:46.039554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 04:37:46.039636 ==
1388 04:37:46.042729 RX Vref Scan: 0
1389 04:37:46.042831
1390 04:37:46.042923 RX Vref 0 -> 0, step: 1
1391 04:37:46.043017
1392 04:37:46.046409 RX Delay -111 -> 252, step: 8
1393 04:37:46.052941 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1394 04:37:46.056486 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1395 04:37:46.059492 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1396 04:37:46.063168 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1397 04:37:46.066204 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1398 04:37:46.072968 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1399 04:37:46.076571 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1400 04:37:46.079955 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1401 04:37:46.082728 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1402 04:37:46.086200 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1403 04:37:46.093227 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1404 04:37:46.096370 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1405 04:37:46.099428 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1406 04:37:46.102974 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1407 04:37:46.106400 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1408 04:37:46.112966 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1409 04:37:46.113077 ==
1410 04:37:46.116070 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 04:37:46.119913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 04:37:46.120003 ==
1413 04:37:46.120069 DQS Delay:
1414 04:37:46.122799 DQS0 = 0, DQS1 = 0
1415 04:37:46.122888 DQM Delay:
1416 04:37:46.126439 DQM0 = 79, DQM1 = 70
1417 04:37:46.126527 DQ Delay:
1418 04:37:46.129357 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1419 04:37:46.133005 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1420 04:37:46.136290 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1421 04:37:46.139540 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =80
1422 04:37:46.139617
1423 04:37:46.139687
1424 04:37:46.149753 [DQSOSCAuto] RK1, (LSB)MR18= 0x4824, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1425 04:37:46.149862 CH0 RK1: MR19=606, MR18=4824
1426 04:37:46.156382 CH0_RK1: MR19=0x606, MR18=0x4824, DQSOSC=391, MR23=63, INC=96, DEC=64
1427 04:37:46.159635 [RxdqsGatingPostProcess] freq 800
1428 04:37:46.165989 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1429 04:37:46.169683 Pre-setting of DQS Precalculation
1430 04:37:46.172970 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1431 04:37:46.173058 ==
1432 04:37:46.176162 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 04:37:46.179325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 04:37:46.179438 ==
1435 04:37:46.186260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1436 04:37:46.192611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1437 04:37:46.201445 [CA 0] Center 36 (6~66) winsize 61
1438 04:37:46.204689 [CA 1] Center 36 (6~67) winsize 62
1439 04:37:46.208377 [CA 2] Center 34 (4~65) winsize 62
1440 04:37:46.211558 [CA 3] Center 34 (4~64) winsize 61
1441 04:37:46.214920 [CA 4] Center 34 (4~65) winsize 62
1442 04:37:46.218170 [CA 5] Center 34 (4~64) winsize 61
1443 04:37:46.218258
1444 04:37:46.221496 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1445 04:37:46.221608
1446 04:37:46.224822 [CATrainingPosCal] consider 1 rank data
1447 04:37:46.227891 u2DelayCellTimex100 = 270/100 ps
1448 04:37:46.231105 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1449 04:37:46.234470 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1450 04:37:46.241303 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1451 04:37:46.244701 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1452 04:37:46.248133 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 04:37:46.251036 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1454 04:37:46.251175
1455 04:37:46.254264 CA PerBit enable=1, Macro0, CA PI delay=34
1456 04:37:46.254381
1457 04:37:46.257652 [CBTSetCACLKResult] CA Dly = 34
1458 04:37:46.257759 CS Dly: 5 (0~36)
1459 04:37:46.261302 ==
1460 04:37:46.261409 Dram Type= 6, Freq= 0, CH_1, rank 1
1461 04:37:46.267995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 04:37:46.268084 ==
1463 04:37:46.271018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 04:37:46.277832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 04:37:46.287321 [CA 0] Center 36 (6~66) winsize 61
1466 04:37:46.290555 [CA 1] Center 36 (6~67) winsize 62
1467 04:37:46.294447 [CA 2] Center 34 (4~65) winsize 62
1468 04:37:46.297604 [CA 3] Center 34 (4~64) winsize 61
1469 04:37:46.300722 [CA 4] Center 34 (4~64) winsize 61
1470 04:37:46.303840 [CA 5] Center 33 (3~64) winsize 62
1471 04:37:46.303919
1472 04:37:46.307427 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1473 04:37:46.307519
1474 04:37:46.310655 [CATrainingPosCal] consider 2 rank data
1475 04:37:46.313880 u2DelayCellTimex100 = 270/100 ps
1476 04:37:46.317698 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1477 04:37:46.320803 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 04:37:46.327666 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1479 04:37:46.331221 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1480 04:37:46.334765 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1481 04:37:46.338997 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1482 04:37:46.339113
1483 04:37:46.342724 CA PerBit enable=1, Macro0, CA PI delay=34
1484 04:37:46.342836
1485 04:37:46.342930 [CBTSetCACLKResult] CA Dly = 34
1486 04:37:46.346345 CS Dly: 6 (0~38)
1487 04:37:46.346422
1488 04:37:46.349778 ----->DramcWriteLeveling(PI) begin...
1489 04:37:46.349862 ==
1490 04:37:46.353171 Dram Type= 6, Freq= 0, CH_1, rank 0
1491 04:37:46.356786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1492 04:37:46.356874 ==
1493 04:37:46.360586 Write leveling (Byte 0): 29 => 29
1494 04:37:46.364595 Write leveling (Byte 1): 29 => 29
1495 04:37:46.364681 DramcWriteLeveling(PI) end<-----
1496 04:37:46.367796
1497 04:37:46.367881 ==
1498 04:37:46.370874 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 04:37:46.374035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 04:37:46.374145 ==
1501 04:37:46.377562 [Gating] SW mode calibration
1502 04:37:46.384402 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1503 04:37:46.387643 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1504 04:37:46.394054 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 04:37:46.397878 0 6 4 | B1->B0 | 2323 2322 | 0 1 | (1 1) (1 1)
1506 04:37:46.400984 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1507 04:37:46.407824 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 04:37:46.411200 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 04:37:46.414404 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 04:37:46.420637 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 04:37:46.424360 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 04:37:46.427565 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 04:37:46.434470 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 04:37:46.437371 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 04:37:46.440898 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 04:37:46.447025 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 04:37:46.450945 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 04:37:46.454133 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 04:37:46.460590 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 04:37:46.463888 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 04:37:46.467282 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1522 04:37:46.474321 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1523 04:37:46.477298 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 04:37:46.480378 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 04:37:46.486851 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 04:37:46.490672 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 04:37:46.493826 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 04:37:46.500736 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 04:37:46.504009 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 04:37:46.507072 0 9 8 | B1->B0 | 2727 2626 | 1 1 | (1 1) (1 1)
1531 04:37:46.513318 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 04:37:46.517041 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 04:37:46.520239 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 04:37:46.523566 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 04:37:46.530324 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 04:37:46.533347 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 04:37:46.536571 0 10 4 | B1->B0 | 3232 3333 | 0 1 | (0 0) (1 0)
1538 04:37:46.543263 0 10 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 0)
1539 04:37:46.547099 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 04:37:46.549939 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 04:37:46.557029 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 04:37:46.560320 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 04:37:46.563556 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 04:37:46.570218 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 04:37:46.573690 0 11 4 | B1->B0 | 2828 2828 | 1 1 | (0 0) (0 0)
1546 04:37:46.576884 0 11 8 | B1->B0 | 3e3e 3b3b | 0 0 | (0 0) (1 1)
1547 04:37:46.583467 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 04:37:46.586795 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 04:37:46.589891 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 04:37:46.596515 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 04:37:46.600401 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 04:37:46.603527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 04:37:46.609937 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1554 04:37:46.613553 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1555 04:37:46.616679 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1556 04:37:46.623149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 04:37:46.626787 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 04:37:46.630370 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 04:37:46.633081 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 04:37:46.640006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 04:37:46.643790 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 04:37:46.646857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 04:37:46.653648 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 04:37:46.657040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 04:37:46.660388 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 04:37:46.666481 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 04:37:46.669921 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 04:37:46.673576 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 04:37:46.680272 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 04:37:46.683496 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 04:37:46.686569 Total UI for P1: 0, mck2ui 16
1572 04:37:46.690046 best dqsien dly found for B0: ( 0, 14, 6)
1573 04:37:46.693633 Total UI for P1: 0, mck2ui 16
1574 04:37:46.697004 best dqsien dly found for B1: ( 0, 14, 6)
1575 04:37:46.699846 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1576 04:37:46.703153 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1577 04:37:46.703268
1578 04:37:46.706892 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1579 04:37:46.710313 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1580 04:37:46.713411 [Gating] SW calibration Done
1581 04:37:46.713513 ==
1582 04:37:46.716614 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 04:37:46.720319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 04:37:46.720425 ==
1585 04:37:46.723590 RX Vref Scan: 0
1586 04:37:46.723696
1587 04:37:46.726809 RX Vref 0 -> 0, step: 1
1588 04:37:46.726899
1589 04:37:46.726967 RX Delay -130 -> 252, step: 16
1590 04:37:46.733097 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1591 04:37:46.736818 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1592 04:37:46.740241 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1593 04:37:46.743049 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1594 04:37:46.746855 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1595 04:37:46.753139 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1596 04:37:46.756918 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1597 04:37:46.759724 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1598 04:37:46.763312 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1599 04:37:46.766420 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1600 04:37:46.773323 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1601 04:37:46.776657 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1602 04:37:46.780165 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1603 04:37:46.783341 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1604 04:37:46.786505 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1605 04:37:46.793516 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1606 04:37:46.793602 ==
1607 04:37:46.796740 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 04:37:46.800321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 04:37:46.800402 ==
1610 04:37:46.800468 DQS Delay:
1611 04:37:46.803227 DQS0 = 0, DQS1 = 0
1612 04:37:46.803339 DQM Delay:
1613 04:37:46.806908 DQM0 = 80, DQM1 = 71
1614 04:37:46.806991 DQ Delay:
1615 04:37:46.810029 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1616 04:37:46.813622 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1617 04:37:46.817016 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1618 04:37:46.820565 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1619 04:37:46.820658
1620 04:37:46.820726
1621 04:37:46.820792 ==
1622 04:37:46.823879 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 04:37:46.827113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 04:37:46.827232 ==
1625 04:37:46.827328
1626 04:37:46.827418
1627 04:37:46.830291 TX Vref Scan disable
1628 04:37:46.833479 == TX Byte 0 ==
1629 04:37:46.836693 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1630 04:37:46.840491 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1631 04:37:46.843551 == TX Byte 1 ==
1632 04:37:46.847179 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1633 04:37:46.850487 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1634 04:37:46.850571 ==
1635 04:37:46.853507 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 04:37:46.857294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 04:37:46.860510 ==
1638 04:37:46.871896 TX Vref=22, minBit 8, minWin=27, winSum=445
1639 04:37:46.874928 TX Vref=24, minBit 8, minWin=27, winSum=447
1640 04:37:46.878178 TX Vref=26, minBit 11, minWin=27, winSum=451
1641 04:37:46.881954 TX Vref=28, minBit 1, minWin=28, winSum=456
1642 04:37:46.885118 TX Vref=30, minBit 1, minWin=28, winSum=456
1643 04:37:46.888163 TX Vref=32, minBit 9, minWin=27, winSum=453
1644 04:37:46.895219 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 28
1645 04:37:46.895304
1646 04:37:46.898346 Final TX Range 1 Vref 28
1647 04:37:46.898429
1648 04:37:46.898496 ==
1649 04:37:46.901600 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 04:37:46.905372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 04:37:46.905468 ==
1652 04:37:46.905561
1653 04:37:46.908911
1654 04:37:46.908988 TX Vref Scan disable
1655 04:37:46.912394 == TX Byte 0 ==
1656 04:37:46.915583 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1657 04:37:46.919347 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1658 04:37:46.922523 == TX Byte 1 ==
1659 04:37:46.925899 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1660 04:37:46.928881 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1661 04:37:46.928964
1662 04:37:46.932277 [DATLAT]
1663 04:37:46.932361 Freq=800, CH1 RK0
1664 04:37:46.932429
1665 04:37:46.935838 DATLAT Default: 0xa
1666 04:37:46.935921 0, 0xFFFF, sum = 0
1667 04:37:46.939153 1, 0xFFFF, sum = 0
1668 04:37:46.939238 2, 0xFFFF, sum = 0
1669 04:37:46.942340 3, 0xFFFF, sum = 0
1670 04:37:46.942424 4, 0xFFFF, sum = 0
1671 04:37:46.946207 5, 0xFFFF, sum = 0
1672 04:37:46.946291 6, 0xFFFF, sum = 0
1673 04:37:46.949624 7, 0xFFFF, sum = 0
1674 04:37:46.949710 8, 0xFFFF, sum = 0
1675 04:37:46.952500 9, 0x0, sum = 1
1676 04:37:46.952585 10, 0x0, sum = 2
1677 04:37:46.955761 11, 0x0, sum = 3
1678 04:37:46.955907 12, 0x0, sum = 4
1679 04:37:46.955986 best_step = 10
1680 04:37:46.959265
1681 04:37:46.959348 ==
1682 04:37:46.962902 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 04:37:46.965842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1684 04:37:46.965966 ==
1685 04:37:46.966068 RX Vref Scan: 1
1686 04:37:46.966171
1687 04:37:46.968913 Set Vref Range= 32 -> 127
1688 04:37:46.969002
1689 04:37:46.972553 RX Vref 32 -> 127, step: 1
1690 04:37:46.972638
1691 04:37:46.976030 RX Delay -111 -> 252, step: 8
1692 04:37:46.976142
1693 04:37:46.979082 Set Vref, RX VrefLevel [Byte0]: 32
1694 04:37:46.982326 [Byte1]: 32
1695 04:37:46.982453
1696 04:37:46.986053 Set Vref, RX VrefLevel [Byte0]: 33
1697 04:37:46.989092 [Byte1]: 33
1698 04:37:46.989183
1699 04:37:46.992191 Set Vref, RX VrefLevel [Byte0]: 34
1700 04:37:46.996059 [Byte1]: 34
1701 04:37:46.999965
1702 04:37:47.000043 Set Vref, RX VrefLevel [Byte0]: 35
1703 04:37:47.003169 [Byte1]: 35
1704 04:37:47.007618
1705 04:37:47.007703 Set Vref, RX VrefLevel [Byte0]: 36
1706 04:37:47.010795 [Byte1]: 36
1707 04:37:47.015267
1708 04:37:47.015380 Set Vref, RX VrefLevel [Byte0]: 37
1709 04:37:47.018536 [Byte1]: 37
1710 04:37:47.022500
1711 04:37:47.022612 Set Vref, RX VrefLevel [Byte0]: 38
1712 04:37:47.026040 [Byte1]: 38
1713 04:37:47.030493
1714 04:37:47.030611 Set Vref, RX VrefLevel [Byte0]: 39
1715 04:37:47.033482 [Byte1]: 39
1716 04:37:47.038100
1717 04:37:47.038183 Set Vref, RX VrefLevel [Byte0]: 40
1718 04:37:47.041068 [Byte1]: 40
1719 04:37:47.045699
1720 04:37:47.045812 Set Vref, RX VrefLevel [Byte0]: 41
1721 04:37:47.048736 [Byte1]: 41
1722 04:37:47.053618
1723 04:37:47.053701 Set Vref, RX VrefLevel [Byte0]: 42
1724 04:37:47.056200 [Byte1]: 42
1725 04:37:47.061052
1726 04:37:47.061161 Set Vref, RX VrefLevel [Byte0]: 43
1727 04:37:47.064116 [Byte1]: 43
1728 04:37:47.068284
1729 04:37:47.068362 Set Vref, RX VrefLevel [Byte0]: 44
1730 04:37:47.071768 [Byte1]: 44
1731 04:37:47.076056
1732 04:37:47.076139 Set Vref, RX VrefLevel [Byte0]: 45
1733 04:37:47.079651 [Byte1]: 45
1734 04:37:47.083674
1735 04:37:47.083757 Set Vref, RX VrefLevel [Byte0]: 46
1736 04:37:47.087355 [Byte1]: 46
1737 04:37:47.091256
1738 04:37:47.091338 Set Vref, RX VrefLevel [Byte0]: 47
1739 04:37:47.094889 [Byte1]: 47
1740 04:37:47.099308
1741 04:37:47.099398 Set Vref, RX VrefLevel [Byte0]: 48
1742 04:37:47.102474 [Byte1]: 48
1743 04:37:47.107022
1744 04:37:47.107105 Set Vref, RX VrefLevel [Byte0]: 49
1745 04:37:47.110143 [Byte1]: 49
1746 04:37:47.114713
1747 04:37:47.114791 Set Vref, RX VrefLevel [Byte0]: 50
1748 04:37:47.117934 [Byte1]: 50
1749 04:37:47.121759
1750 04:37:47.121842 Set Vref, RX VrefLevel [Byte0]: 51
1751 04:37:47.125416 [Byte1]: 51
1752 04:37:47.129701
1753 04:37:47.129810 Set Vref, RX VrefLevel [Byte0]: 52
1754 04:37:47.132778 [Byte1]: 52
1755 04:37:47.137152
1756 04:37:47.140347 Set Vref, RX VrefLevel [Byte0]: 53
1757 04:37:47.143800 [Byte1]: 53
1758 04:37:47.143884
1759 04:37:47.147069 Set Vref, RX VrefLevel [Byte0]: 54
1760 04:37:47.150477 [Byte1]: 54
1761 04:37:47.150560
1762 04:37:47.153638 Set Vref, RX VrefLevel [Byte0]: 55
1763 04:37:47.157243 [Byte1]: 55
1764 04:37:47.157327
1765 04:37:47.160237 Set Vref, RX VrefLevel [Byte0]: 56
1766 04:37:47.164214 [Byte1]: 56
1767 04:37:47.167643
1768 04:37:47.167720 Set Vref, RX VrefLevel [Byte0]: 57
1769 04:37:47.171335 [Byte1]: 57
1770 04:37:47.175675
1771 04:37:47.175754 Set Vref, RX VrefLevel [Byte0]: 58
1772 04:37:47.178770 [Byte1]: 58
1773 04:37:47.183105
1774 04:37:47.183189 Set Vref, RX VrefLevel [Byte0]: 59
1775 04:37:47.186683 [Byte1]: 59
1776 04:37:47.190744
1777 04:37:47.190826 Set Vref, RX VrefLevel [Byte0]: 60
1778 04:37:47.193952 [Byte1]: 60
1779 04:37:47.198322
1780 04:37:47.198420 Set Vref, RX VrefLevel [Byte0]: 61
1781 04:37:47.201552 [Byte1]: 61
1782 04:37:47.206030
1783 04:37:47.206147 Set Vref, RX VrefLevel [Byte0]: 62
1784 04:37:47.209799 [Byte1]: 62
1785 04:37:47.213623
1786 04:37:47.213706 Set Vref, RX VrefLevel [Byte0]: 63
1787 04:37:47.217367 [Byte1]: 63
1788 04:37:47.221125
1789 04:37:47.221208 Set Vref, RX VrefLevel [Byte0]: 64
1790 04:37:47.225020 [Byte1]: 64
1791 04:37:47.228888
1792 04:37:47.228975 Set Vref, RX VrefLevel [Byte0]: 65
1793 04:37:47.232732 [Byte1]: 65
1794 04:37:47.236931
1795 04:37:47.237014 Set Vref, RX VrefLevel [Byte0]: 66
1796 04:37:47.240019 [Byte1]: 66
1797 04:37:47.244378
1798 04:37:47.244466 Set Vref, RX VrefLevel [Byte0]: 67
1799 04:37:47.247938 [Byte1]: 67
1800 04:37:47.251754
1801 04:37:47.251836 Set Vref, RX VrefLevel [Byte0]: 68
1802 04:37:47.255410 [Byte1]: 68
1803 04:37:47.259799
1804 04:37:47.259887 Set Vref, RX VrefLevel [Byte0]: 69
1805 04:37:47.262816 [Byte1]: 69
1806 04:37:47.267013
1807 04:37:47.267118 Set Vref, RX VrefLevel [Byte0]: 70
1808 04:37:47.270673 [Byte1]: 70
1809 04:37:47.275163
1810 04:37:47.275266 Set Vref, RX VrefLevel [Byte0]: 71
1811 04:37:47.277938 [Byte1]: 71
1812 04:37:47.282751
1813 04:37:47.282855 Set Vref, RX VrefLevel [Byte0]: 72
1814 04:37:47.285900 [Byte1]: 72
1815 04:37:47.290217
1816 04:37:47.290312 Set Vref, RX VrefLevel [Byte0]: 73
1817 04:37:47.293228 [Byte1]: 73
1818 04:37:47.297827
1819 04:37:47.297931 Set Vref, RX VrefLevel [Byte0]: 74
1820 04:37:47.301327 [Byte1]: 74
1821 04:37:47.305515
1822 04:37:47.305621 Set Vref, RX VrefLevel [Byte0]: 75
1823 04:37:47.308720 [Byte1]: 75
1824 04:37:47.313038
1825 04:37:47.313141 Final RX Vref Byte 0 = 51 to rank0
1826 04:37:47.316192 Final RX Vref Byte 1 = 53 to rank0
1827 04:37:47.320153 Final RX Vref Byte 0 = 51 to rank1
1828 04:37:47.323181 Final RX Vref Byte 1 = 53 to rank1==
1829 04:37:47.326450 Dram Type= 6, Freq= 0, CH_1, rank 0
1830 04:37:47.329618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 04:37:47.333585 ==
1832 04:37:47.333663 DQS Delay:
1833 04:37:47.333728 DQS0 = 0, DQS1 = 0
1834 04:37:47.336509 DQM Delay:
1835 04:37:47.336585 DQM0 = 80, DQM1 = 71
1836 04:37:47.339814 DQ Delay:
1837 04:37:47.343406 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1838 04:37:47.343484 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1839 04:37:47.346346 DQ8 =64, DQ9 =64, DQ10 =72, DQ11 =64
1840 04:37:47.349889 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1841 04:37:47.353443
1842 04:37:47.353527
1843 04:37:47.360151 [DQSOSCAuto] RK0, (LSB)MR18= 0xd18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1844 04:37:47.363339 CH1 RK0: MR19=606, MR18=D18
1845 04:37:47.370360 CH1_RK0: MR19=0x606, MR18=0xD18, DQSOSC=403, MR23=63, INC=90, DEC=60
1846 04:37:47.370459
1847 04:37:47.373281 ----->DramcWriteLeveling(PI) begin...
1848 04:37:47.373360 ==
1849 04:37:47.376804 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 04:37:47.380326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 04:37:47.380410 ==
1852 04:37:47.383337 Write leveling (Byte 0): 28 => 28
1853 04:37:47.386825 Write leveling (Byte 1): 31 => 31
1854 04:37:47.389818 DramcWriteLeveling(PI) end<-----
1855 04:37:47.389898
1856 04:37:47.389964 ==
1857 04:37:47.393626 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 04:37:47.396773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 04:37:47.396851 ==
1860 04:37:47.399832 [Gating] SW mode calibration
1861 04:37:47.406880 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1862 04:37:47.413160 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1863 04:37:47.416867 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1864 04:37:47.420008 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1865 04:37:47.426352 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 04:37:47.430088 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 04:37:47.433164 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 04:37:47.440037 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 04:37:47.443290 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 04:37:47.446746 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 04:37:47.449907 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 04:37:47.456435 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 04:37:47.459990 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 04:37:47.463220 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 04:37:47.470144 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 04:37:47.473254 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 04:37:47.476354 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 04:37:47.482903 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 04:37:47.486614 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1880 04:37:47.489686 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1881 04:37:47.496701 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 04:37:47.499620 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 04:37:47.503392 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 04:37:47.509698 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 04:37:47.513122 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 04:37:47.516450 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 04:37:47.522948 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 04:37:47.526832 0 9 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1889 04:37:47.529901 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1890 04:37:47.533093 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 04:37:47.539935 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 04:37:47.543204 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 04:37:47.546902 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 04:37:47.553503 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 04:37:47.556628 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1896 04:37:47.560295 0 10 4 | B1->B0 | 2f2f 2a2a | 0 0 | (0 1) (0 0)
1897 04:37:47.566522 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1898 04:37:47.570009 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 04:37:47.573437 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 04:37:47.580059 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 04:37:47.583675 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 04:37:47.586714 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 04:37:47.593472 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1904 04:37:47.596900 0 11 4 | B1->B0 | 3333 3d3d | 0 0 | (0 0) (0 0)
1905 04:37:47.599782 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1906 04:37:47.607015 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 04:37:47.610220 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 04:37:47.613253 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 04:37:47.616854 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 04:37:47.623211 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 04:37:47.626540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 04:37:47.630325 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1913 04:37:47.636576 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1914 04:37:47.640473 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 04:37:47.643596 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 04:37:47.650454 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 04:37:47.653560 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 04:37:47.657161 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 04:37:47.663352 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 04:37:47.667105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 04:37:47.670254 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 04:37:47.677063 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 04:37:47.680020 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 04:37:47.683545 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 04:37:47.690425 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 04:37:47.693740 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 04:37:47.697171 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 04:37:47.699990 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1929 04:37:47.707085 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1930 04:37:47.710282 Total UI for P1: 0, mck2ui 16
1931 04:37:47.713897 best dqsien dly found for B0: ( 0, 14, 4)
1932 04:37:47.716947 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 04:37:47.720085 Total UI for P1: 0, mck2ui 16
1934 04:37:47.723216 best dqsien dly found for B1: ( 0, 14, 6)
1935 04:37:47.726831 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1936 04:37:47.730392 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1937 04:37:47.730503
1938 04:37:47.733708 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1939 04:37:47.736976 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1940 04:37:47.740153 [Gating] SW calibration Done
1941 04:37:47.740239 ==
1942 04:37:47.743865 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 04:37:47.746970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 04:37:47.750104 ==
1945 04:37:47.750186 RX Vref Scan: 0
1946 04:37:47.750268
1947 04:37:47.753729 RX Vref 0 -> 0, step: 1
1948 04:37:47.753811
1949 04:37:47.756807 RX Delay -130 -> 252, step: 16
1950 04:37:47.760750 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1951 04:37:47.763583 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1952 04:37:47.767276 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1953 04:37:47.770391 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1954 04:37:47.777261 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1955 04:37:47.780491 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1956 04:37:47.783520 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1957 04:37:47.787268 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1958 04:37:47.790357 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1959 04:37:47.793999 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1960 04:37:47.800320 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1961 04:37:47.803924 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1962 04:37:47.806807 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1963 04:37:47.810498 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1964 04:37:47.816837 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1965 04:37:47.820225 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1966 04:37:47.820332 ==
1967 04:37:47.823801 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 04:37:47.826731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 04:37:47.826864 ==
1970 04:37:47.830300 DQS Delay:
1971 04:37:47.830404 DQS0 = 0, DQS1 = 0
1972 04:37:47.830500 DQM Delay:
1973 04:37:47.833338 DQM0 = 80, DQM1 = 76
1974 04:37:47.833445 DQ Delay:
1975 04:37:47.836856 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1976 04:37:47.840233 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1977 04:37:47.843531 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1978 04:37:47.847005 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1979 04:37:47.847113
1980 04:37:47.847210
1981 04:37:47.847306 ==
1982 04:37:47.850181 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 04:37:47.853745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 04:37:47.856823 ==
1985 04:37:47.856927
1986 04:37:47.857025
1987 04:37:47.857121 TX Vref Scan disable
1988 04:37:47.860690 == TX Byte 0 ==
1989 04:37:47.863555 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1990 04:37:47.867062 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1991 04:37:47.870180 == TX Byte 1 ==
1992 04:37:47.873944 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1993 04:37:47.877085 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1994 04:37:47.877189 ==
1995 04:37:47.880242 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 04:37:47.887035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 04:37:47.887149 ==
1998 04:37:47.899289 TX Vref=22, minBit 0, minWin=28, winSum=452
1999 04:37:47.902965 TX Vref=24, minBit 0, minWin=28, winSum=453
2000 04:37:47.905597 TX Vref=26, minBit 4, minWin=28, winSum=455
2001 04:37:47.909356 TX Vref=28, minBit 8, minWin=28, winSum=460
2002 04:37:47.912304 TX Vref=30, minBit 4, minWin=28, winSum=457
2003 04:37:47.919060 TX Vref=32, minBit 3, minWin=28, winSum=457
2004 04:37:47.922732 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
2005 04:37:47.922842
2006 04:37:47.925664 Final TX Range 1 Vref 28
2007 04:37:47.925770
2008 04:37:47.925869 ==
2009 04:37:47.929262 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 04:37:47.932151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 04:37:47.932261 ==
2012 04:37:47.932360
2013 04:37:47.935991
2014 04:37:47.936097 TX Vref Scan disable
2015 04:37:47.939100 == TX Byte 0 ==
2016 04:37:47.942559 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2017 04:37:47.948805 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2018 04:37:47.948915 == TX Byte 1 ==
2019 04:37:47.952237 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2020 04:37:47.959108 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2021 04:37:47.959218
2022 04:37:47.959318 [DATLAT]
2023 04:37:47.959424 Freq=800, CH1 RK1
2024 04:37:47.959524
2025 04:37:47.962231 DATLAT Default: 0xa
2026 04:37:47.962335 0, 0xFFFF, sum = 0
2027 04:37:47.965997 1, 0xFFFF, sum = 0
2028 04:37:47.966106 2, 0xFFFF, sum = 0
2029 04:37:47.969010 3, 0xFFFF, sum = 0
2030 04:37:47.969116 4, 0xFFFF, sum = 0
2031 04:37:47.972539 5, 0xFFFF, sum = 0
2032 04:37:47.975657 6, 0xFFFF, sum = 0
2033 04:37:47.975766 7, 0xFFFF, sum = 0
2034 04:37:47.979261 8, 0xFFFF, sum = 0
2035 04:37:47.979374 9, 0x0, sum = 1
2036 04:37:47.979478 10, 0x0, sum = 2
2037 04:37:47.982423 11, 0x0, sum = 3
2038 04:37:47.982534 12, 0x0, sum = 4
2039 04:37:47.985483 best_step = 10
2040 04:37:47.985588
2041 04:37:47.985685 ==
2042 04:37:47.989209 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 04:37:47.992252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 04:37:47.992360 ==
2045 04:37:47.995942 RX Vref Scan: 0
2046 04:37:47.996049
2047 04:37:47.996145 RX Vref 0 -> 0, step: 1
2048 04:37:47.996243
2049 04:37:47.998946 RX Delay -111 -> 252, step: 8
2050 04:37:48.005797 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2051 04:37:48.009251 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2052 04:37:48.012337 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2053 04:37:48.015908 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2054 04:37:48.019405 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2055 04:37:48.025706 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2056 04:37:48.029259 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2057 04:37:48.032446 iDelay=209, Bit 7, Center 72 (-47 ~ 192) 240
2058 04:37:48.036168 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2059 04:37:48.039240 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2060 04:37:48.045744 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2061 04:37:48.048999 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2062 04:37:48.052389 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2063 04:37:48.055969 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2064 04:37:48.059375 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2065 04:37:48.065813 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2066 04:37:48.065927 ==
2067 04:37:48.069256 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 04:37:48.072357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 04:37:48.072466 ==
2070 04:37:48.072563 DQS Delay:
2071 04:37:48.075950 DQS0 = 0, DQS1 = 0
2072 04:37:48.076055 DQM Delay:
2073 04:37:48.079026 DQM0 = 77, DQM1 = 72
2074 04:37:48.079132 DQ Delay:
2075 04:37:48.082774 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2076 04:37:48.085819 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =72
2077 04:37:48.088986 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
2078 04:37:48.092794 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
2079 04:37:48.092900
2080 04:37:48.093008
2081 04:37:48.099497 [DQSOSCAuto] RK1, (LSB)MR18= 0x2038, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2082 04:37:48.102687 CH1 RK1: MR19=606, MR18=2038
2083 04:37:48.109055 CH1_RK1: MR19=0x606, MR18=0x2038, DQSOSC=395, MR23=63, INC=94, DEC=63
2084 04:37:48.112870 [RxdqsGatingPostProcess] freq 800
2085 04:37:48.119195 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2086 04:37:48.122366 Pre-setting of DQS Precalculation
2087 04:37:48.126037 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2088 04:37:48.132171 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2089 04:37:48.139053 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2090 04:37:48.139166
2091 04:37:48.142241
2092 04:37:48.142351 [Calibration Summary] 1600 Mbps
2093 04:37:48.145419 CH 0, Rank 0
2094 04:37:48.145524 SW Impedance : PASS
2095 04:37:48.149119 DUTY Scan : NO K
2096 04:37:48.152227 ZQ Calibration : PASS
2097 04:37:48.152335 Jitter Meter : NO K
2098 04:37:48.155859 CBT Training : PASS
2099 04:37:48.158815 Write leveling : PASS
2100 04:37:48.158920 RX DQS gating : PASS
2101 04:37:48.162226 RX DQ/DQS(RDDQC) : PASS
2102 04:37:48.165820 TX DQ/DQS : PASS
2103 04:37:48.165928 RX DATLAT : PASS
2104 04:37:48.169409 RX DQ/DQS(Engine): PASS
2105 04:37:48.169521 TX OE : NO K
2106 04:37:48.172429 All Pass.
2107 04:37:48.172535
2108 04:37:48.172636 CH 0, Rank 1
2109 04:37:48.175547 SW Impedance : PASS
2110 04:37:48.175653 DUTY Scan : NO K
2111 04:37:48.178746 ZQ Calibration : PASS
2112 04:37:48.182487 Jitter Meter : NO K
2113 04:37:48.182592 CBT Training : PASS
2114 04:37:48.185576 Write leveling : PASS
2115 04:37:48.188684 RX DQS gating : PASS
2116 04:37:48.188795 RX DQ/DQS(RDDQC) : PASS
2117 04:37:48.192030 TX DQ/DQS : PASS
2118 04:37:48.195858 RX DATLAT : PASS
2119 04:37:48.195965 RX DQ/DQS(Engine): PASS
2120 04:37:48.198857 TX OE : NO K
2121 04:37:48.198967 All Pass.
2122 04:37:48.199062
2123 04:37:48.202761 CH 1, Rank 0
2124 04:37:48.202867 SW Impedance : PASS
2125 04:37:48.205618 DUTY Scan : NO K
2126 04:37:48.208791 ZQ Calibration : PASS
2127 04:37:48.208899 Jitter Meter : NO K
2128 04:37:48.212614 CBT Training : PASS
2129 04:37:48.215801 Write leveling : PASS
2130 04:37:48.215909 RX DQS gating : PASS
2131 04:37:48.218799 RX DQ/DQS(RDDQC) : PASS
2132 04:37:48.218906 TX DQ/DQS : PASS
2133 04:37:48.222634 RX DATLAT : PASS
2134 04:37:48.225906 RX DQ/DQS(Engine): PASS
2135 04:37:48.226015 TX OE : NO K
2136 04:37:48.228875 All Pass.
2137 04:37:48.228986
2138 04:37:48.229094 CH 1, Rank 1
2139 04:37:48.232477 SW Impedance : PASS
2140 04:37:48.232585 DUTY Scan : NO K
2141 04:37:48.235535 ZQ Calibration : PASS
2142 04:37:48.239245 Jitter Meter : NO K
2143 04:37:48.239354 CBT Training : PASS
2144 04:37:48.242328 Write leveling : PASS
2145 04:37:48.246042 RX DQS gating : PASS
2146 04:37:48.246150 RX DQ/DQS(RDDQC) : PASS
2147 04:37:48.249254 TX DQ/DQS : PASS
2148 04:37:48.252278 RX DATLAT : PASS
2149 04:37:48.252381 RX DQ/DQS(Engine): PASS
2150 04:37:48.255455 TX OE : NO K
2151 04:37:48.255558 All Pass.
2152 04:37:48.255653
2153 04:37:48.259410 DramC Write-DBI off
2154 04:37:48.262294 PER_BANK_REFRESH: Hybrid Mode
2155 04:37:48.262399 TX_TRACKING: ON
2156 04:37:48.265842 [GetDramInforAfterCalByMRR] Vendor 6.
2157 04:37:48.268798 [GetDramInforAfterCalByMRR] Revision 606.
2158 04:37:48.272452 [GetDramInforAfterCalByMRR] Revision 2 0.
2159 04:37:48.275711 MR0 0x3b3b
2160 04:37:48.275820 MR8 0x5151
2161 04:37:48.279057 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 04:37:48.279163
2163 04:37:48.279262 MR0 0x3b3b
2164 04:37:48.282382 MR8 0x5151
2165 04:37:48.285483 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 04:37:48.285593
2167 04:37:48.292337 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2168 04:37:48.298986 [FAST_K] Save calibration result to emmc
2169 04:37:48.301998 [FAST_K] Save calibration result to emmc
2170 04:37:48.302109 dram_init: config_dvfs: 1
2171 04:37:48.305527 dramc_set_vcore_voltage set vcore to 662500
2172 04:37:48.308799 Read voltage for 1200, 2
2173 04:37:48.308902 Vio18 = 0
2174 04:37:48.312285 Vcore = 662500
2175 04:37:48.312392 Vdram = 0
2176 04:37:48.312499 Vddq = 0
2177 04:37:48.315664 Vmddr = 0
2178 04:37:48.318723 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2179 04:37:48.325913 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2180 04:37:48.326021 MEM_TYPE=3, freq_sel=15
2181 04:37:48.328773 sv_algorithm_assistance_LP4_1600
2182 04:37:48.335804 ============ PULL DRAM RESETB DOWN ============
2183 04:37:48.338712 ========== PULL DRAM RESETB DOWN end =========
2184 04:37:48.342206 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2185 04:37:48.346077 ===================================
2186 04:37:48.349031 LPDDR4 DRAM CONFIGURATION
2187 04:37:48.352234 ===================================
2188 04:37:48.355864 EX_ROW_EN[0] = 0x0
2189 04:37:48.355967 EX_ROW_EN[1] = 0x0
2190 04:37:48.359029 LP4Y_EN = 0x0
2191 04:37:48.359134 WORK_FSP = 0x0
2192 04:37:48.362201 WL = 0x4
2193 04:37:48.362304 RL = 0x4
2194 04:37:48.365859 BL = 0x2
2195 04:37:48.365965 RPST = 0x0
2196 04:37:48.368905 RD_PRE = 0x0
2197 04:37:48.369010 WR_PRE = 0x1
2198 04:37:48.372388 WR_PST = 0x0
2199 04:37:48.372493 DBI_WR = 0x0
2200 04:37:48.375981 DBI_RD = 0x0
2201 04:37:48.376086 OTF = 0x1
2202 04:37:48.379161 ===================================
2203 04:37:48.382121 ===================================
2204 04:37:48.385640 ANA top config
2205 04:37:48.389187 ===================================
2206 04:37:48.389295 DLL_ASYNC_EN = 0
2207 04:37:48.392333 ALL_SLAVE_EN = 0
2208 04:37:48.395443 NEW_RANK_MODE = 1
2209 04:37:48.398599 DLL_IDLE_MODE = 1
2210 04:37:48.402289 LP45_APHY_COMB_EN = 1
2211 04:37:48.402395 TX_ODT_DIS = 1
2212 04:37:48.405396 NEW_8X_MODE = 1
2213 04:37:48.408989 ===================================
2214 04:37:48.412411 ===================================
2215 04:37:48.415517 data_rate = 2400
2216 04:37:48.419064 CKR = 1
2217 04:37:48.422261 DQ_P2S_RATIO = 8
2218 04:37:48.425283 ===================================
2219 04:37:48.428606 CA_P2S_RATIO = 8
2220 04:37:48.428733 DQ_CA_OPEN = 0
2221 04:37:48.431892 DQ_SEMI_OPEN = 0
2222 04:37:48.435744 CA_SEMI_OPEN = 0
2223 04:37:48.438896 CA_FULL_RATE = 0
2224 04:37:48.442346 DQ_CKDIV4_EN = 0
2225 04:37:48.442455 CA_CKDIV4_EN = 0
2226 04:37:48.445264 CA_PREDIV_EN = 0
2227 04:37:48.448752 PH8_DLY = 17
2228 04:37:48.451819 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2229 04:37:48.455678 DQ_AAMCK_DIV = 4
2230 04:37:48.458840 CA_AAMCK_DIV = 4
2231 04:37:48.458943 CA_ADMCK_DIV = 4
2232 04:37:48.462003 DQ_TRACK_CA_EN = 0
2233 04:37:48.465022 CA_PICK = 1200
2234 04:37:48.468775 CA_MCKIO = 1200
2235 04:37:48.471870 MCKIO_SEMI = 0
2236 04:37:48.475604 PLL_FREQ = 2366
2237 04:37:48.478599 DQ_UI_PI_RATIO = 32
2238 04:37:48.481775 CA_UI_PI_RATIO = 0
2239 04:37:48.481854 ===================================
2240 04:37:48.485719 ===================================
2241 04:37:48.488723 memory_type:LPDDR4
2242 04:37:48.492483 GP_NUM : 10
2243 04:37:48.492588 SRAM_EN : 1
2244 04:37:48.495446 MD32_EN : 0
2245 04:37:48.498597 ===================================
2246 04:37:48.501792 [ANA_INIT] >>>>>>>>>>>>>>
2247 04:37:48.505551 <<<<<< [CONFIGURE PHASE]: ANA_TX
2248 04:37:48.508572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2249 04:37:48.512312 ===================================
2250 04:37:48.512420 data_rate = 2400,PCW = 0X5b00
2251 04:37:48.515376 ===================================
2252 04:37:48.518450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2253 04:37:48.525183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 04:37:48.532320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2255 04:37:48.535529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2256 04:37:48.538913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2257 04:37:48.542337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2258 04:37:48.545091 [ANA_INIT] flow start
2259 04:37:48.545193 [ANA_INIT] PLL >>>>>>>>
2260 04:37:48.548656 [ANA_INIT] PLL <<<<<<<<
2261 04:37:48.552108 [ANA_INIT] MIDPI >>>>>>>>
2262 04:37:48.555539 [ANA_INIT] MIDPI <<<<<<<<
2263 04:37:48.555644 [ANA_INIT] DLL >>>>>>>>
2264 04:37:48.559091 [ANA_INIT] DLL <<<<<<<<
2265 04:37:48.562219 [ANA_INIT] flow end
2266 04:37:48.565398 ============ LP4 DIFF to SE enter ============
2267 04:37:48.568552 ============ LP4 DIFF to SE exit ============
2268 04:37:48.572258 [ANA_INIT] <<<<<<<<<<<<<
2269 04:37:48.575406 [Flow] Enable top DCM control >>>>>
2270 04:37:48.578660 [Flow] Enable top DCM control <<<<<
2271 04:37:48.582400 Enable DLL master slave shuffle
2272 04:37:48.585543 ==============================================================
2273 04:37:48.588508 Gating Mode config
2274 04:37:48.591995 ==============================================================
2275 04:37:48.595566 Config description:
2276 04:37:48.605551 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2277 04:37:48.611806 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2278 04:37:48.615495 SELPH_MODE 0: By rank 1: By Phase
2279 04:37:48.622079 ==============================================================
2280 04:37:48.625404 GAT_TRACK_EN = 1
2281 04:37:48.629021 RX_GATING_MODE = 2
2282 04:37:48.632061 RX_GATING_TRACK_MODE = 2
2283 04:37:48.635196 SELPH_MODE = 1
2284 04:37:48.635304 PICG_EARLY_EN = 1
2285 04:37:48.638847 VALID_LAT_VALUE = 1
2286 04:37:48.645404 ==============================================================
2287 04:37:48.648573 Enter into Gating configuration >>>>
2288 04:37:48.652234 Exit from Gating configuration <<<<
2289 04:37:48.655725 Enter into DVFS_PRE_config >>>>>
2290 04:37:48.665472 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2291 04:37:48.668745 Exit from DVFS_PRE_config <<<<<
2292 04:37:48.672250 Enter into PICG configuration >>>>
2293 04:37:48.675282 Exit from PICG configuration <<<<
2294 04:37:48.679277 [RX_INPUT] configuration >>>>>
2295 04:37:48.682128 [RX_INPUT] configuration <<<<<
2296 04:37:48.685800 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2297 04:37:48.692303 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2298 04:37:48.698976 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 04:37:48.705436 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 04:37:48.709023 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 04:37:48.715821 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 04:37:48.718961 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2303 04:37:48.725620 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2304 04:37:48.728679 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2305 04:37:48.732558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2306 04:37:48.735492 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2307 04:37:48.742414 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 04:37:48.745339 ===================================
2309 04:37:48.748837 LPDDR4 DRAM CONFIGURATION
2310 04:37:48.748925 ===================================
2311 04:37:48.752374 EX_ROW_EN[0] = 0x0
2312 04:37:48.755551 EX_ROW_EN[1] = 0x0
2313 04:37:48.755627 LP4Y_EN = 0x0
2314 04:37:48.758674 WORK_FSP = 0x0
2315 04:37:48.758773 WL = 0x4
2316 04:37:48.761783 RL = 0x4
2317 04:37:48.761889 BL = 0x2
2318 04:37:48.765624 RPST = 0x0
2319 04:37:48.765730 RD_PRE = 0x0
2320 04:37:48.768996 WR_PRE = 0x1
2321 04:37:48.769085 WR_PST = 0x0
2322 04:37:48.772041 DBI_WR = 0x0
2323 04:37:48.772138 DBI_RD = 0x0
2324 04:37:48.775410 OTF = 0x1
2325 04:37:48.778861 ===================================
2326 04:37:48.782078 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2327 04:37:48.785314 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2328 04:37:48.792102 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2329 04:37:48.795613 ===================================
2330 04:37:48.795698 LPDDR4 DRAM CONFIGURATION
2331 04:37:48.798513 ===================================
2332 04:37:48.801950 EX_ROW_EN[0] = 0x10
2333 04:37:48.805587 EX_ROW_EN[1] = 0x0
2334 04:37:48.805671 LP4Y_EN = 0x0
2335 04:37:48.808530 WORK_FSP = 0x0
2336 04:37:48.808613 WL = 0x4
2337 04:37:48.811788 RL = 0x4
2338 04:37:48.811872 BL = 0x2
2339 04:37:48.815512 RPST = 0x0
2340 04:37:48.815596 RD_PRE = 0x0
2341 04:37:48.818650 WR_PRE = 0x1
2342 04:37:48.818733 WR_PST = 0x0
2343 04:37:48.822336 DBI_WR = 0x0
2344 04:37:48.822420 DBI_RD = 0x0
2345 04:37:48.825464 OTF = 0x1
2346 04:37:48.828438 ===================================
2347 04:37:48.835101 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2348 04:37:48.835216 ==
2349 04:37:48.838718 Dram Type= 6, Freq= 0, CH_0, rank 0
2350 04:37:48.841835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2351 04:37:48.841944 ==
2352 04:37:48.845528 [Duty_Offset_Calibration]
2353 04:37:48.845636 B0:2 B1:0 CA:4
2354 04:37:48.845730
2355 04:37:48.848758 [DutyScan_Calibration_Flow] k_type=0
2356 04:37:48.858963
2357 04:37:48.859075 ==CLK 0==
2358 04:37:48.862088 Final CLK duty delay cell = 0
2359 04:37:48.865251 [0] MAX Duty = 5031%(X100), DQS PI = 12
2360 04:37:48.868270 [0] MIN Duty = 4907%(X100), DQS PI = 54
2361 04:37:48.871978 [0] AVG Duty = 4969%(X100)
2362 04:37:48.872052
2363 04:37:48.874896 CH0 CLK Duty spec in!! Max-Min= 124%
2364 04:37:48.878455 [DutyScan_Calibration_Flow] ====Done====
2365 04:37:48.878554
2366 04:37:48.881528 [DutyScan_Calibration_Flow] k_type=1
2367 04:37:48.897235
2368 04:37:48.897343 ==DQS 0 ==
2369 04:37:48.900339 Final DQS duty delay cell = 0
2370 04:37:48.903981 [0] MAX Duty = 5062%(X100), DQS PI = 12
2371 04:37:48.907324 [0] MIN Duty = 4907%(X100), DQS PI = 46
2372 04:37:48.910338 [0] AVG Duty = 4984%(X100)
2373 04:37:48.910438
2374 04:37:48.910538 ==DQS 1 ==
2375 04:37:48.913962 Final DQS duty delay cell = -4
2376 04:37:48.916972 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2377 04:37:48.920236 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2378 04:37:48.923675 [-4] AVG Duty = 4922%(X100)
2379 04:37:48.923789
2380 04:37:48.926889 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2381 04:37:48.926995
2382 04:37:48.930596 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2383 04:37:48.934124 [DutyScan_Calibration_Flow] ====Done====
2384 04:37:48.934237
2385 04:37:48.937225 [DutyScan_Calibration_Flow] k_type=3
2386 04:37:48.954445
2387 04:37:48.954556 ==DQM 0 ==
2388 04:37:48.958187 Final DQM duty delay cell = 0
2389 04:37:48.961213 [0] MAX Duty = 5124%(X100), DQS PI = 30
2390 04:37:48.964912 [0] MIN Duty = 4876%(X100), DQS PI = 0
2391 04:37:48.965034 [0] AVG Duty = 5000%(X100)
2392 04:37:48.965131
2393 04:37:48.967888 ==DQM 1 ==
2394 04:37:48.971583 Final DQM duty delay cell = 4
2395 04:37:48.974871 [4] MAX Duty = 5124%(X100), DQS PI = 50
2396 04:37:48.977870 [4] MIN Duty = 5000%(X100), DQS PI = 14
2397 04:37:48.977990 [4] AVG Duty = 5062%(X100)
2398 04:37:48.978090
2399 04:37:48.984476 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2400 04:37:48.984587
2401 04:37:48.988237 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2402 04:37:48.991430 [DutyScan_Calibration_Flow] ====Done====
2403 04:37:48.991539
2404 04:37:48.994412 [DutyScan_Calibration_Flow] k_type=2
2405 04:37:49.009618
2406 04:37:49.009731 ==DQ 0 ==
2407 04:37:49.012934 Final DQ duty delay cell = -4
2408 04:37:49.016018 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2409 04:37:49.019460 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2410 04:37:49.022488 [-4] AVG Duty = 4969%(X100)
2411 04:37:49.022594
2412 04:37:49.022693 ==DQ 1 ==
2413 04:37:49.025946 Final DQ duty delay cell = -4
2414 04:37:49.029416 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2415 04:37:49.032416 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2416 04:37:49.036137 [-4] AVG Duty = 4938%(X100)
2417 04:37:49.036248
2418 04:37:49.039061 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2419 04:37:49.039180
2420 04:37:49.042830 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2421 04:37:49.045727 [DutyScan_Calibration_Flow] ====Done====
2422 04:37:49.045843 ==
2423 04:37:49.049421 Dram Type= 6, Freq= 0, CH_1, rank 0
2424 04:37:49.052589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2425 04:37:49.052697 ==
2426 04:37:49.056331 [Duty_Offset_Calibration]
2427 04:37:49.056441 B0:1 B1:-2 CA:0
2428 04:37:49.056549
2429 04:37:49.059535 [DutyScan_Calibration_Flow] k_type=0
2430 04:37:49.070216
2431 04:37:49.070327 ==CLK 0==
2432 04:37:49.073399 Final CLK duty delay cell = 0
2433 04:37:49.076543 [0] MAX Duty = 5062%(X100), DQS PI = 30
2434 04:37:49.080342 [0] MIN Duty = 4876%(X100), DQS PI = 60
2435 04:37:49.080456 [0] AVG Duty = 4969%(X100)
2436 04:37:49.083330
2437 04:37:49.086871 CH1 CLK Duty spec in!! Max-Min= 186%
2438 04:37:49.089928 [DutyScan_Calibration_Flow] ====Done====
2439 04:37:49.090040
2440 04:37:49.093033 [DutyScan_Calibration_Flow] k_type=1
2441 04:37:49.108349
2442 04:37:49.108461 ==DQS 0 ==
2443 04:37:49.112053 Final DQS duty delay cell = -4
2444 04:37:49.115243 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2445 04:37:49.118722 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2446 04:37:49.121555 [-4] AVG Duty = 4953%(X100)
2447 04:37:49.121657
2448 04:37:49.121749 ==DQS 1 ==
2449 04:37:49.124845 Final DQS duty delay cell = 0
2450 04:37:49.128600 [0] MAX Duty = 5093%(X100), DQS PI = 0
2451 04:37:49.131734 [0] MIN Duty = 4844%(X100), DQS PI = 26
2452 04:37:49.134843 [0] AVG Duty = 4968%(X100)
2453 04:37:49.134947
2454 04:37:49.138107 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2455 04:37:49.138219
2456 04:37:49.141812 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2457 04:37:49.144980 [DutyScan_Calibration_Flow] ====Done====
2458 04:37:49.145090
2459 04:37:49.148294 [DutyScan_Calibration_Flow] k_type=3
2460 04:37:49.165511
2461 04:37:49.165595 ==DQM 0 ==
2462 04:37:49.168547 Final DQM duty delay cell = 0
2463 04:37:49.172250 [0] MAX Duty = 5000%(X100), DQS PI = 22
2464 04:37:49.175295 [0] MIN Duty = 4844%(X100), DQS PI = 56
2465 04:37:49.175404 [0] AVG Duty = 4922%(X100)
2466 04:37:49.178540
2467 04:37:49.178646 ==DQM 1 ==
2468 04:37:49.182241 Final DQM duty delay cell = 0
2469 04:37:49.185354 [0] MAX Duty = 5031%(X100), DQS PI = 36
2470 04:37:49.188481 [0] MIN Duty = 4907%(X100), DQS PI = 4
2471 04:37:49.188588 [0] AVG Duty = 4969%(X100)
2472 04:37:49.188681
2473 04:37:49.195628 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2474 04:37:49.195724
2475 04:37:49.198795 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2476 04:37:49.201921 [DutyScan_Calibration_Flow] ====Done====
2477 04:37:49.202028
2478 04:37:49.205523 [DutyScan_Calibration_Flow] k_type=2
2479 04:37:49.221757
2480 04:37:49.221839 ==DQ 0 ==
2481 04:37:49.224873 Final DQ duty delay cell = 0
2482 04:37:49.228045 [0] MAX Duty = 5062%(X100), DQS PI = 18
2483 04:37:49.231730 [0] MIN Duty = 4938%(X100), DQS PI = 52
2484 04:37:49.231840 [0] AVG Duty = 5000%(X100)
2485 04:37:49.235210
2486 04:37:49.235313 ==DQ 1 ==
2487 04:37:49.238614 Final DQ duty delay cell = 0
2488 04:37:49.241497 [0] MAX Duty = 5093%(X100), DQS PI = 18
2489 04:37:49.244945 [0] MIN Duty = 4969%(X100), DQS PI = 26
2490 04:37:49.245051 [0] AVG Duty = 5031%(X100)
2491 04:37:49.245147
2492 04:37:49.248577 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2493 04:37:49.248684
2494 04:37:49.252059 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2495 04:37:49.258182 [DutyScan_Calibration_Flow] ====Done====
2496 04:37:49.261428 nWR fixed to 30
2497 04:37:49.261536 [ModeRegInit_LP4] CH0 RK0
2498 04:37:49.264856 [ModeRegInit_LP4] CH0 RK1
2499 04:37:49.268476 [ModeRegInit_LP4] CH1 RK0
2500 04:37:49.268586 [ModeRegInit_LP4] CH1 RK1
2501 04:37:49.271530 match AC timing 7
2502 04:37:49.274748 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2503 04:37:49.278368 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2504 04:37:49.285047 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2505 04:37:49.288176 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2506 04:37:49.294981 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2507 04:37:49.295088 ==
2508 04:37:49.298584 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 04:37:49.301515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 04:37:49.301602 ==
2511 04:37:49.308217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2512 04:37:49.311489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2513 04:37:49.321462 [CA 0] Center 40 (10~71) winsize 62
2514 04:37:49.325365 [CA 1] Center 39 (9~70) winsize 62
2515 04:37:49.328567 [CA 2] Center 36 (6~66) winsize 61
2516 04:37:49.331737 [CA 3] Center 35 (5~66) winsize 62
2517 04:37:49.334818 [CA 4] Center 34 (4~65) winsize 62
2518 04:37:49.338486 [CA 5] Center 33 (3~63) winsize 61
2519 04:37:49.338593
2520 04:37:49.341483 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2521 04:37:49.341591
2522 04:37:49.345000 [CATrainingPosCal] consider 1 rank data
2523 04:37:49.348296 u2DelayCellTimex100 = 270/100 ps
2524 04:37:49.351649 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2525 04:37:49.358365 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2526 04:37:49.361393 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2527 04:37:49.365063 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2528 04:37:49.368129 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2529 04:37:49.371775 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2530 04:37:49.371885
2531 04:37:49.375079 CA PerBit enable=1, Macro0, CA PI delay=33
2532 04:37:49.375178
2533 04:37:49.378267 [CBTSetCACLKResult] CA Dly = 33
2534 04:37:49.378372 CS Dly: 7 (0~38)
2535 04:37:49.381713 ==
2536 04:37:49.381825 Dram Type= 6, Freq= 0, CH_0, rank 1
2537 04:37:49.388609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 04:37:49.388721 ==
2539 04:37:49.392308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2540 04:37:49.398623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2541 04:37:49.407503 [CA 0] Center 40 (10~70) winsize 61
2542 04:37:49.411081 [CA 1] Center 39 (9~70) winsize 62
2543 04:37:49.414117 [CA 2] Center 35 (5~66) winsize 62
2544 04:37:49.417851 [CA 3] Center 35 (5~66) winsize 62
2545 04:37:49.420924 [CA 4] Center 34 (4~65) winsize 62
2546 04:37:49.424679 [CA 5] Center 33 (3~64) winsize 62
2547 04:37:49.424784
2548 04:37:49.427801 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2549 04:37:49.427906
2550 04:37:49.431048 [CATrainingPosCal] consider 2 rank data
2551 04:37:49.434452 u2DelayCellTimex100 = 270/100 ps
2552 04:37:49.438017 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2553 04:37:49.444254 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2554 04:37:49.447865 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2555 04:37:49.450902 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2556 04:37:49.454331 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2557 04:37:49.457617 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2558 04:37:49.457724
2559 04:37:49.460910 CA PerBit enable=1, Macro0, CA PI delay=33
2560 04:37:49.461020
2561 04:37:49.464685 [CBTSetCACLKResult] CA Dly = 33
2562 04:37:49.464792 CS Dly: 8 (0~40)
2563 04:37:49.464891
2564 04:37:49.468465 ----->DramcWriteLeveling(PI) begin...
2565 04:37:49.471269 ==
2566 04:37:49.474350 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 04:37:49.478153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 04:37:49.478262 ==
2569 04:37:49.481215 Write leveling (Byte 0): 33 => 33
2570 04:37:49.484700 Write leveling (Byte 1): 29 => 29
2571 04:37:49.487560 DramcWriteLeveling(PI) end<-----
2572 04:37:49.487638
2573 04:37:49.487716 ==
2574 04:37:49.491177 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 04:37:49.494412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 04:37:49.494518 ==
2577 04:37:49.497880 [Gating] SW mode calibration
2578 04:37:49.504275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2579 04:37:49.508071 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2580 04:37:49.514475 0 15 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
2581 04:37:49.518119 0 15 4 | B1->B0 | 2828 3434 | 1 1 | (1 1) (0 0)
2582 04:37:49.521189 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 04:37:49.528098 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 04:37:49.531175 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 04:37:49.534312 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 04:37:49.541069 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 04:37:49.544248 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2588 04:37:49.547960 1 0 0 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (1 0)
2589 04:37:49.554284 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2590 04:37:49.557578 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 04:37:49.561260 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 04:37:49.568176 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 04:37:49.570899 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 04:37:49.574589 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 04:37:49.581014 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2596 04:37:49.584668 1 1 0 | B1->B0 | 2929 3a3a | 0 0 | (0 0) (0 0)
2597 04:37:49.587782 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2598 04:37:49.594595 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 04:37:49.597731 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 04:37:49.601410 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 04:37:49.607665 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 04:37:49.611411 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 04:37:49.614738 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2604 04:37:49.617981 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2605 04:37:49.624290 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2606 04:37:49.627907 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 04:37:49.631353 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 04:37:49.637656 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 04:37:49.641371 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 04:37:49.644490 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 04:37:49.651467 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 04:37:49.654579 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 04:37:49.658266 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 04:37:49.664448 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 04:37:49.668020 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 04:37:49.671166 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 04:37:49.678539 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 04:37:49.681391 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 04:37:49.684445 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2620 04:37:49.687892 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2621 04:37:49.694726 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2622 04:37:49.698077 Total UI for P1: 0, mck2ui 16
2623 04:37:49.701191 best dqsien dly found for B0: ( 1, 3, 30)
2624 04:37:49.704980 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 04:37:49.708097 Total UI for P1: 0, mck2ui 16
2626 04:37:49.711103 best dqsien dly found for B1: ( 1, 4, 2)
2627 04:37:49.714673 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2628 04:37:49.717762 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2629 04:37:49.717869
2630 04:37:49.721321 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2631 04:37:49.724771 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2632 04:37:49.727710 [Gating] SW calibration Done
2633 04:37:49.727819 ==
2634 04:37:49.731240 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 04:37:49.734654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 04:37:49.737753 ==
2637 04:37:49.737858 RX Vref Scan: 0
2638 04:37:49.737957
2639 04:37:49.741289 RX Vref 0 -> 0, step: 1
2640 04:37:49.741397
2641 04:37:49.744550 RX Delay -40 -> 252, step: 8
2642 04:37:49.747799 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2643 04:37:49.751577 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2644 04:37:49.754782 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2645 04:37:49.758089 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2646 04:37:49.764819 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2647 04:37:49.767891 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2648 04:37:49.771454 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2649 04:37:49.774709 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2650 04:37:49.778073 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2651 04:37:49.781560 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2652 04:37:49.788339 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2653 04:37:49.791530 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2654 04:37:49.794555 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2655 04:37:49.798360 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2656 04:37:49.801359 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2657 04:37:49.808044 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2658 04:37:49.808157 ==
2659 04:37:49.811144 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 04:37:49.814964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 04:37:49.815072 ==
2662 04:37:49.815172 DQS Delay:
2663 04:37:49.817976 DQS0 = 0, DQS1 = 0
2664 04:37:49.818083 DQM Delay:
2665 04:37:49.821618 DQM0 = 112, DQM1 = 103
2666 04:37:49.821724 DQ Delay:
2667 04:37:49.824742 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2668 04:37:49.827718 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2669 04:37:49.831253 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2670 04:37:49.834967 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =111
2671 04:37:49.835077
2672 04:37:49.835177
2673 04:37:49.838026 ==
2674 04:37:49.838132 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 04:37:49.844779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 04:37:49.844888 ==
2677 04:37:49.844989
2678 04:37:49.845081
2679 04:37:49.845173 TX Vref Scan disable
2680 04:37:49.848436 == TX Byte 0 ==
2681 04:37:49.852096 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2682 04:37:49.858306 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2683 04:37:49.858420 == TX Byte 1 ==
2684 04:37:49.861719 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2685 04:37:49.868400 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2686 04:37:49.868509 ==
2687 04:37:49.871611 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 04:37:49.875196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 04:37:49.875309 ==
2690 04:37:49.886911 TX Vref=22, minBit 1, minWin=25, winSum=416
2691 04:37:49.889945 TX Vref=24, minBit 1, minWin=26, winSum=424
2692 04:37:49.892994 TX Vref=26, minBit 7, minWin=25, winSum=432
2693 04:37:49.896768 TX Vref=28, minBit 2, minWin=26, winSum=434
2694 04:37:49.899691 TX Vref=30, minBit 10, minWin=25, winSum=434
2695 04:37:49.906520 TX Vref=32, minBit 2, minWin=26, winSum=428
2696 04:37:49.910119 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 28
2697 04:37:49.910226
2698 04:37:49.913348 Final TX Range 1 Vref 28
2699 04:37:49.913453
2700 04:37:49.913565 ==
2701 04:37:49.916896 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 04:37:49.920144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 04:37:49.920253 ==
2704 04:37:49.920348
2705 04:37:49.923186
2706 04:37:49.923290 TX Vref Scan disable
2707 04:37:49.926669 == TX Byte 0 ==
2708 04:37:49.929819 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2709 04:37:49.933089 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2710 04:37:49.936561 == TX Byte 1 ==
2711 04:37:49.940245 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2712 04:37:49.943589 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2713 04:37:49.946614
2714 04:37:49.946718 [DATLAT]
2715 04:37:49.946823 Freq=1200, CH0 RK0
2716 04:37:49.946926
2717 04:37:49.949661 DATLAT Default: 0xd
2718 04:37:49.949771 0, 0xFFFF, sum = 0
2719 04:37:49.953482 1, 0xFFFF, sum = 0
2720 04:37:49.953590 2, 0xFFFF, sum = 0
2721 04:37:49.956624 3, 0xFFFF, sum = 0
2722 04:37:49.956733 4, 0xFFFF, sum = 0
2723 04:37:49.959567 5, 0xFFFF, sum = 0
2724 04:37:49.963139 6, 0xFFFF, sum = 0
2725 04:37:49.963247 7, 0xFFFF, sum = 0
2726 04:37:49.966253 8, 0xFFFF, sum = 0
2727 04:37:49.966359 9, 0xFFFF, sum = 0
2728 04:37:49.969681 10, 0xFFFF, sum = 0
2729 04:37:49.969791 11, 0xFFFF, sum = 0
2730 04:37:49.973106 12, 0x0, sum = 1
2731 04:37:49.973213 13, 0x0, sum = 2
2732 04:37:49.976209 14, 0x0, sum = 3
2733 04:37:49.976316 15, 0x0, sum = 4
2734 04:37:49.976417 best_step = 13
2735 04:37:49.976510
2736 04:37:49.979689 ==
2737 04:37:49.983096 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 04:37:49.986267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 04:37:49.986373 ==
2740 04:37:49.986485 RX Vref Scan: 1
2741 04:37:49.986577
2742 04:37:49.989832 Set Vref Range= 32 -> 127
2743 04:37:49.989937
2744 04:37:49.992823 RX Vref 32 -> 127, step: 1
2745 04:37:49.992926
2746 04:37:49.996409 RX Delay -37 -> 252, step: 4
2747 04:37:49.996511
2748 04:37:49.999556 Set Vref, RX VrefLevel [Byte0]: 32
2749 04:37:50.003192 [Byte1]: 32
2750 04:37:50.003296
2751 04:37:50.006179 Set Vref, RX VrefLevel [Byte0]: 33
2752 04:37:50.009816 [Byte1]: 33
2753 04:37:50.012945
2754 04:37:50.013055 Set Vref, RX VrefLevel [Byte0]: 34
2755 04:37:50.016564 [Byte1]: 34
2756 04:37:50.020741
2757 04:37:50.020852 Set Vref, RX VrefLevel [Byte0]: 35
2758 04:37:50.024269 [Byte1]: 35
2759 04:37:50.029269
2760 04:37:50.029376 Set Vref, RX VrefLevel [Byte0]: 36
2761 04:37:50.032210 [Byte1]: 36
2762 04:37:50.037198
2763 04:37:50.037308 Set Vref, RX VrefLevel [Byte0]: 37
2764 04:37:50.040187 [Byte1]: 37
2765 04:37:50.044968
2766 04:37:50.045078 Set Vref, RX VrefLevel [Byte0]: 38
2767 04:37:50.048181 [Byte1]: 38
2768 04:37:50.053091
2769 04:37:50.053194 Set Vref, RX VrefLevel [Byte0]: 39
2770 04:37:50.056219 [Byte1]: 39
2771 04:37:50.061099
2772 04:37:50.061204 Set Vref, RX VrefLevel [Byte0]: 40
2773 04:37:50.064258 [Byte1]: 40
2774 04:37:50.069233
2775 04:37:50.069340 Set Vref, RX VrefLevel [Byte0]: 41
2776 04:37:50.072394 [Byte1]: 41
2777 04:37:50.077327
2778 04:37:50.077435 Set Vref, RX VrefLevel [Byte0]: 42
2779 04:37:50.080335 [Byte1]: 42
2780 04:37:50.085320
2781 04:37:50.085435 Set Vref, RX VrefLevel [Byte0]: 43
2782 04:37:50.088499 [Byte1]: 43
2783 04:37:50.092731
2784 04:37:50.092838 Set Vref, RX VrefLevel [Byte0]: 44
2785 04:37:50.096174 [Byte1]: 44
2786 04:37:50.101041
2787 04:37:50.101149 Set Vref, RX VrefLevel [Byte0]: 45
2788 04:37:50.104284 [Byte1]: 45
2789 04:37:50.109013
2790 04:37:50.109122 Set Vref, RX VrefLevel [Byte0]: 46
2791 04:37:50.112215 [Byte1]: 46
2792 04:37:50.117215
2793 04:37:50.117318 Set Vref, RX VrefLevel [Byte0]: 47
2794 04:37:50.120217 [Byte1]: 47
2795 04:37:50.125273
2796 04:37:50.125382 Set Vref, RX VrefLevel [Byte0]: 48
2797 04:37:50.128170 [Byte1]: 48
2798 04:37:50.132969
2799 04:37:50.133080 Set Vref, RX VrefLevel [Byte0]: 49
2800 04:37:50.136107 [Byte1]: 49
2801 04:37:50.140944
2802 04:37:50.141052 Set Vref, RX VrefLevel [Byte0]: 50
2803 04:37:50.144569 [Byte1]: 50
2804 04:37:50.149418
2805 04:37:50.149526 Set Vref, RX VrefLevel [Byte0]: 51
2806 04:37:50.152310 [Byte1]: 51
2807 04:37:50.157123
2808 04:37:50.157229 Set Vref, RX VrefLevel [Byte0]: 52
2809 04:37:50.160226 [Byte1]: 52
2810 04:37:50.165243
2811 04:37:50.165356 Set Vref, RX VrefLevel [Byte0]: 53
2812 04:37:50.168403 [Byte1]: 53
2813 04:37:50.172926
2814 04:37:50.173031 Set Vref, RX VrefLevel [Byte0]: 54
2815 04:37:50.176226 [Byte1]: 54
2816 04:37:50.181109
2817 04:37:50.181218 Set Vref, RX VrefLevel [Byte0]: 55
2818 04:37:50.184176 [Byte1]: 55
2819 04:37:50.189072
2820 04:37:50.189180 Set Vref, RX VrefLevel [Byte0]: 56
2821 04:37:50.192715 [Byte1]: 56
2822 04:37:50.197333
2823 04:37:50.197442 Set Vref, RX VrefLevel [Byte0]: 57
2824 04:37:50.200073 [Byte1]: 57
2825 04:37:50.204840
2826 04:37:50.204947 Set Vref, RX VrefLevel [Byte0]: 58
2827 04:37:50.208324 [Byte1]: 58
2828 04:37:50.213322
2829 04:37:50.213446 Set Vref, RX VrefLevel [Byte0]: 59
2830 04:37:50.216709 [Byte1]: 59
2831 04:37:50.221215
2832 04:37:50.221326 Set Vref, RX VrefLevel [Byte0]: 60
2833 04:37:50.224599 [Byte1]: 60
2834 04:37:50.228893
2835 04:37:50.229001 Set Vref, RX VrefLevel [Byte0]: 61
2836 04:37:50.232701 [Byte1]: 61
2837 04:37:50.237298
2838 04:37:50.237401 Set Vref, RX VrefLevel [Byte0]: 62
2839 04:37:50.240381 [Byte1]: 62
2840 04:37:50.245240
2841 04:37:50.245348 Set Vref, RX VrefLevel [Byte0]: 63
2842 04:37:50.248247 [Byte1]: 63
2843 04:37:50.253255
2844 04:37:50.253358 Set Vref, RX VrefLevel [Byte0]: 64
2845 04:37:50.256173 [Byte1]: 64
2846 04:37:50.261394
2847 04:37:50.261475 Set Vref, RX VrefLevel [Byte0]: 65
2848 04:37:50.264525 [Byte1]: 65
2849 04:37:50.269157
2850 04:37:50.269267 Set Vref, RX VrefLevel [Byte0]: 66
2851 04:37:50.272073 [Byte1]: 66
2852 04:37:50.277151
2853 04:37:50.277270 Set Vref, RX VrefLevel [Byte0]: 67
2854 04:37:50.280127 [Byte1]: 67
2855 04:37:50.285091
2856 04:37:50.285200 Set Vref, RX VrefLevel [Byte0]: 68
2857 04:37:50.288176 [Byte1]: 68
2858 04:37:50.293125
2859 04:37:50.293207 Set Vref, RX VrefLevel [Byte0]: 69
2860 04:37:50.296748 [Byte1]: 69
2861 04:37:50.301229
2862 04:37:50.301337 Set Vref, RX VrefLevel [Byte0]: 70
2863 04:37:50.304685 [Byte1]: 70
2864 04:37:50.309339
2865 04:37:50.309443 Set Vref, RX VrefLevel [Byte0]: 71
2866 04:37:50.312702 [Byte1]: 71
2867 04:37:50.317454
2868 04:37:50.317532 Set Vref, RX VrefLevel [Byte0]: 72
2869 04:37:50.320490 [Byte1]: 72
2870 04:37:50.325179
2871 04:37:50.325284 Set Vref, RX VrefLevel [Byte0]: 73
2872 04:37:50.328476 [Byte1]: 73
2873 04:37:50.333277
2874 04:37:50.333391 Final RX Vref Byte 0 = 61 to rank0
2875 04:37:50.336629 Final RX Vref Byte 1 = 51 to rank0
2876 04:37:50.339490 Final RX Vref Byte 0 = 61 to rank1
2877 04:37:50.343079 Final RX Vref Byte 1 = 51 to rank1==
2878 04:37:50.346087 Dram Type= 6, Freq= 0, CH_0, rank 0
2879 04:37:50.352987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 04:37:50.353069 ==
2881 04:37:50.353135 DQS Delay:
2882 04:37:50.353196 DQS0 = 0, DQS1 = 0
2883 04:37:50.356518 DQM Delay:
2884 04:37:50.356635 DQM0 = 111, DQM1 = 101
2885 04:37:50.359625 DQ Delay:
2886 04:37:50.362605 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2887 04:37:50.366155 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2888 04:37:50.369545 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2889 04:37:50.372968 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2890 04:37:50.373086
2891 04:37:50.373183
2892 04:37:50.379893 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2893 04:37:50.383026 CH0 RK0: MR19=303, MR18=FBFA
2894 04:37:50.390088 CH0_RK0: MR19=0x303, MR18=0xFBFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2895 04:37:50.390199
2896 04:37:50.393143 ----->DramcWriteLeveling(PI) begin...
2897 04:37:50.393244 ==
2898 04:37:50.396206 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 04:37:50.399742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 04:37:50.399843 ==
2901 04:37:50.402945 Write leveling (Byte 0): 34 => 34
2902 04:37:50.406694 Write leveling (Byte 1): 28 => 28
2903 04:37:50.409788 DramcWriteLeveling(PI) end<-----
2904 04:37:50.409866
2905 04:37:50.409949 ==
2906 04:37:50.413358 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 04:37:50.419676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 04:37:50.419763 ==
2909 04:37:50.419851 [Gating] SW mode calibration
2910 04:37:50.429881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2911 04:37:50.433108 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2912 04:37:50.436554 0 15 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2913 04:37:50.443156 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 04:37:50.446296 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 04:37:50.449783 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 04:37:50.456568 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 04:37:50.460001 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 04:37:50.463057 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2919 04:37:50.469468 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2920 04:37:50.473110 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2921 04:37:50.476082 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 04:37:50.483285 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 04:37:50.486447 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 04:37:50.489639 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 04:37:50.496523 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 04:37:50.499715 1 0 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
2927 04:37:50.502661 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2928 04:37:50.509516 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2929 04:37:50.513295 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 04:37:50.516164 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 04:37:50.523238 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 04:37:50.526244 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 04:37:50.529507 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 04:37:50.533211 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2935 04:37:50.539440 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2936 04:37:50.542998 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2937 04:37:50.545935 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 04:37:50.552627 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 04:37:50.556074 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 04:37:50.559871 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 04:37:50.566337 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 04:37:50.569885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 04:37:50.573208 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 04:37:50.579691 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 04:37:50.583437 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 04:37:50.586260 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 04:37:50.593354 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 04:37:50.596341 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 04:37:50.599390 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 04:37:50.606252 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 04:37:50.609834 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2952 04:37:50.612948 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 04:37:50.616053 Total UI for P1: 0, mck2ui 16
2954 04:37:50.619909 best dqsien dly found for B0: ( 1, 3, 28)
2955 04:37:50.622971 Total UI for P1: 0, mck2ui 16
2956 04:37:50.626126 best dqsien dly found for B1: ( 1, 3, 30)
2957 04:37:50.629415 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2958 04:37:50.633001 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2959 04:37:50.633090
2960 04:37:50.636448 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2961 04:37:50.643188 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2962 04:37:50.643274 [Gating] SW calibration Done
2963 04:37:50.643343 ==
2964 04:37:50.646190 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 04:37:50.653236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 04:37:50.653321 ==
2967 04:37:50.653405 RX Vref Scan: 0
2968 04:37:50.653470
2969 04:37:50.656335 RX Vref 0 -> 0, step: 1
2970 04:37:50.656431
2971 04:37:50.659859 RX Delay -40 -> 252, step: 8
2972 04:37:50.663009 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2973 04:37:50.666683 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2974 04:37:50.669875 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2975 04:37:50.672978 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2976 04:37:50.679671 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2977 04:37:50.683110 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2978 04:37:50.686270 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2979 04:37:50.690130 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2980 04:37:50.692857 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2981 04:37:50.699295 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2982 04:37:50.703000 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2983 04:37:50.706145 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2984 04:37:50.709299 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2985 04:37:50.712872 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2986 04:37:50.719160 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2987 04:37:50.722934 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2988 04:37:50.723050 ==
2989 04:37:50.726032 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 04:37:50.729664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 04:37:50.729779 ==
2992 04:37:50.732782 DQS Delay:
2993 04:37:50.732867 DQS0 = 0, DQS1 = 0
2994 04:37:50.732935 DQM Delay:
2995 04:37:50.736378 DQM0 = 112, DQM1 = 100
2996 04:37:50.736464 DQ Delay:
2997 04:37:50.739571 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2998 04:37:50.742503 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2999 04:37:50.745993 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3000 04:37:50.749559 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107
3001 04:37:50.752589
3002 04:37:50.752694
3003 04:37:50.752810 ==
3004 04:37:50.756118 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 04:37:50.759562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 04:37:50.759665 ==
3007 04:37:50.759735
3008 04:37:50.759806
3009 04:37:50.762625 TX Vref Scan disable
3010 04:37:50.762702 == TX Byte 0 ==
3011 04:37:50.769410 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3012 04:37:50.773116 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3013 04:37:50.773243 == TX Byte 1 ==
3014 04:37:50.779298 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3015 04:37:50.782907 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3016 04:37:50.783024 ==
3017 04:37:50.785898 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 04:37:50.789564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 04:37:50.789654 ==
3020 04:37:50.802109 TX Vref=22, minBit 2, minWin=25, winSum=419
3021 04:37:50.805517 TX Vref=24, minBit 0, minWin=26, winSum=423
3022 04:37:50.809184 TX Vref=26, minBit 9, minWin=25, winSum=426
3023 04:37:50.812298 TX Vref=28, minBit 8, minWin=26, winSum=432
3024 04:37:50.815868 TX Vref=30, minBit 8, minWin=25, winSum=432
3025 04:37:50.819067 TX Vref=32, minBit 2, minWin=26, winSum=434
3026 04:37:50.826020 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 32
3027 04:37:50.826141
3028 04:37:50.829089 Final TX Range 1 Vref 32
3029 04:37:50.829189
3030 04:37:50.829258 ==
3031 04:37:50.832358 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 04:37:50.835419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 04:37:50.835527 ==
3034 04:37:50.835598
3035 04:37:50.839263
3036 04:37:50.839349 TX Vref Scan disable
3037 04:37:50.842740 == TX Byte 0 ==
3038 04:37:50.845638 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3039 04:37:50.848768 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3040 04:37:50.852237 == TX Byte 1 ==
3041 04:37:50.855510 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3042 04:37:50.859154 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3043 04:37:50.859262
3044 04:37:50.862155 [DATLAT]
3045 04:37:50.862241 Freq=1200, CH0 RK1
3046 04:37:50.862310
3047 04:37:50.865707 DATLAT Default: 0xd
3048 04:37:50.865827 0, 0xFFFF, sum = 0
3049 04:37:50.869187 1, 0xFFFF, sum = 0
3050 04:37:50.869301 2, 0xFFFF, sum = 0
3051 04:37:50.872256 3, 0xFFFF, sum = 0
3052 04:37:50.872352 4, 0xFFFF, sum = 0
3053 04:37:50.875875 5, 0xFFFF, sum = 0
3054 04:37:50.875960 6, 0xFFFF, sum = 0
3055 04:37:50.878929 7, 0xFFFF, sum = 0
3056 04:37:50.879049 8, 0xFFFF, sum = 0
3057 04:37:50.882136 9, 0xFFFF, sum = 0
3058 04:37:50.885584 10, 0xFFFF, sum = 0
3059 04:37:50.885672 11, 0xFFFF, sum = 0
3060 04:37:50.888660 12, 0x0, sum = 1
3061 04:37:50.888744 13, 0x0, sum = 2
3062 04:37:50.892383 14, 0x0, sum = 3
3063 04:37:50.892474 15, 0x0, sum = 4
3064 04:37:50.892546 best_step = 13
3065 04:37:50.892613
3066 04:37:50.895580 ==
3067 04:37:50.895671 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 04:37:50.902144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 04:37:50.902261 ==
3070 04:37:50.902374 RX Vref Scan: 0
3071 04:37:50.902448
3072 04:37:50.905835 RX Vref 0 -> 0, step: 1
3073 04:37:50.905938
3074 04:37:50.908810 RX Delay -37 -> 252, step: 4
3075 04:37:50.912280 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3076 04:37:50.918936 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3077 04:37:50.921971 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3078 04:37:50.925704 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3079 04:37:50.928842 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3080 04:37:50.932588 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3081 04:37:50.938948 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3082 04:37:50.942660 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3083 04:37:50.945657 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3084 04:37:50.948616 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3085 04:37:50.952320 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3086 04:37:50.955498 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3087 04:37:50.962346 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3088 04:37:50.965754 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3089 04:37:50.968587 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3090 04:37:50.972151 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3091 04:37:50.972236 ==
3092 04:37:50.975528 Dram Type= 6, Freq= 0, CH_0, rank 1
3093 04:37:50.982231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 04:37:50.982320 ==
3095 04:37:50.982388 DQS Delay:
3096 04:37:50.985460 DQS0 = 0, DQS1 = 0
3097 04:37:50.985544 DQM Delay:
3098 04:37:50.985611 DQM0 = 111, DQM1 = 101
3099 04:37:50.988833 DQ Delay:
3100 04:37:50.992099 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =110
3101 04:37:50.995755 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =120
3102 04:37:50.998854 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =92
3103 04:37:51.002024 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3104 04:37:51.002108
3105 04:37:51.002174
3106 04:37:51.008656 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3107 04:37:51.012018 CH0 RK1: MR19=403, MR18=14FD
3108 04:37:51.018561 CH0_RK1: MR19=0x403, MR18=0x14FD, DQSOSC=402, MR23=63, INC=40, DEC=27
3109 04:37:51.022218 [RxdqsGatingPostProcess] freq 1200
3110 04:37:51.028794 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3111 04:37:51.032023 best DQS0 dly(2T, 0.5T) = (0, 11)
3112 04:37:51.032145 best DQS1 dly(2T, 0.5T) = (0, 12)
3113 04:37:51.035530 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3114 04:37:51.038665 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3115 04:37:51.042498 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 04:37:51.045596 best DQS1 dly(2T, 0.5T) = (0, 11)
3117 04:37:51.049012 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 04:37:51.052530 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3119 04:37:51.055485 Pre-setting of DQS Precalculation
3120 04:37:51.062360 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3121 04:37:51.062446 ==
3122 04:37:51.065482 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 04:37:51.068981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 04:37:51.069066 ==
3125 04:37:51.075166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 04:37:51.078809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3127 04:37:51.088507 [CA 0] Center 37 (7~67) winsize 61
3128 04:37:51.091696 [CA 1] Center 37 (7~68) winsize 62
3129 04:37:51.095247 [CA 2] Center 34 (4~64) winsize 61
3130 04:37:51.098144 [CA 3] Center 34 (4~64) winsize 61
3131 04:37:51.101910 [CA 4] Center 34 (4~64) winsize 61
3132 04:37:51.105039 [CA 5] Center 33 (3~63) winsize 61
3133 04:37:51.105123
3134 04:37:51.108216 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3135 04:37:51.108294
3136 04:37:51.111931 [CATrainingPosCal] consider 1 rank data
3137 04:37:51.115361 u2DelayCellTimex100 = 270/100 ps
3138 04:37:51.118585 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3139 04:37:51.121709 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3140 04:37:51.125462 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 04:37:51.131732 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 04:37:51.135181 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 04:37:51.138613 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3144 04:37:51.138701
3145 04:37:51.141900 CA PerBit enable=1, Macro0, CA PI delay=33
3146 04:37:51.142008
3147 04:37:51.145225 [CBTSetCACLKResult] CA Dly = 33
3148 04:37:51.145306 CS Dly: 6 (0~37)
3149 04:37:51.145376 ==
3150 04:37:51.148572 Dram Type= 6, Freq= 0, CH_1, rank 1
3151 04:37:51.155205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 04:37:51.155315 ==
3153 04:37:51.158264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3154 04:37:51.165197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3155 04:37:51.173892 [CA 0] Center 37 (7~67) winsize 61
3156 04:37:51.177348 [CA 1] Center 37 (7~68) winsize 62
3157 04:37:51.180619 [CA 2] Center 34 (4~65) winsize 62
3158 04:37:51.184084 [CA 3] Center 33 (3~64) winsize 62
3159 04:37:51.187121 [CA 4] Center 34 (4~64) winsize 61
3160 04:37:51.190589 [CA 5] Center 33 (3~63) winsize 61
3161 04:37:51.190673
3162 04:37:51.194264 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3163 04:37:51.194348
3164 04:37:51.197671 [CATrainingPosCal] consider 2 rank data
3165 04:37:51.200725 u2DelayCellTimex100 = 270/100 ps
3166 04:37:51.204337 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3167 04:37:51.207543 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3168 04:37:51.213777 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3169 04:37:51.217693 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 04:37:51.220411 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3171 04:37:51.224181 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3172 04:37:51.224269
3173 04:37:51.227340 CA PerBit enable=1, Macro0, CA PI delay=33
3174 04:37:51.227447
3175 04:37:51.230475 [CBTSetCACLKResult] CA Dly = 33
3176 04:37:51.230583 CS Dly: 7 (0~39)
3177 04:37:51.230675
3178 04:37:51.234308 ----->DramcWriteLeveling(PI) begin...
3179 04:37:51.237538 ==
3180 04:37:51.237622 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 04:37:51.243690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 04:37:51.243795 ==
3183 04:37:51.247260 Write leveling (Byte 0): 26 => 26
3184 04:37:51.250830 Write leveling (Byte 1): 28 => 28
3185 04:37:51.253915 DramcWriteLeveling(PI) end<-----
3186 04:37:51.253994
3187 04:37:51.254099 ==
3188 04:37:51.257186 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 04:37:51.261021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 04:37:51.261098 ==
3191 04:37:51.263819 [Gating] SW mode calibration
3192 04:37:51.270299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3193 04:37:51.274095 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3194 04:37:51.280410 0 15 0 | B1->B0 | 3030 2e2e | 1 0 | (0 0) (0 0)
3195 04:37:51.283883 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 04:37:51.287212 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 04:37:51.293906 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 04:37:51.297044 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 04:37:51.300389 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 04:37:51.307422 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 04:37:51.310472 0 15 28 | B1->B0 | 2929 2e2e | 0 0 | (0 1) (0 1)
3202 04:37:51.314074 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 04:37:51.320274 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 04:37:51.324038 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 04:37:51.327452 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 04:37:51.333720 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 04:37:51.336971 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 04:37:51.340918 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 04:37:51.346906 1 0 28 | B1->B0 | 3c3c 3d3d | 0 0 | (0 0) (0 0)
3210 04:37:51.350691 1 1 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3211 04:37:51.353844 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 04:37:51.360519 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 04:37:51.364185 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 04:37:51.367019 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 04:37:51.373789 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 04:37:51.377234 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 04:37:51.380180 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3218 04:37:51.383781 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3219 04:37:51.390643 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 04:37:51.393471 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 04:37:51.397216 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 04:37:51.403918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 04:37:51.407077 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 04:37:51.410484 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 04:37:51.417160 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 04:37:51.420175 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 04:37:51.423882 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 04:37:51.430046 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 04:37:51.433607 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 04:37:51.436689 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 04:37:51.443542 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 04:37:51.446612 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 04:37:51.450374 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3234 04:37:51.456807 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3235 04:37:51.456905 Total UI for P1: 0, mck2ui 16
3236 04:37:51.463412 best dqsien dly found for B1: ( 1, 3, 28)
3237 04:37:51.466803 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 04:37:51.470394 Total UI for P1: 0, mck2ui 16
3239 04:37:51.473632 best dqsien dly found for B0: ( 1, 3, 30)
3240 04:37:51.477136 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3241 04:37:51.479938 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3242 04:37:51.480044
3243 04:37:51.483213 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3244 04:37:51.486632 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3245 04:37:51.490343 [Gating] SW calibration Done
3246 04:37:51.490482 ==
3247 04:37:51.493446 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 04:37:51.497226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 04:37:51.497312 ==
3250 04:37:51.500209 RX Vref Scan: 0
3251 04:37:51.500285
3252 04:37:51.503578 RX Vref 0 -> 0, step: 1
3253 04:37:51.503671
3254 04:37:51.503738 RX Delay -40 -> 252, step: 8
3255 04:37:51.510287 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3256 04:37:51.513372 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3257 04:37:51.516949 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3258 04:37:51.520458 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3259 04:37:51.523515 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3260 04:37:51.529972 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3261 04:37:51.533818 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3262 04:37:51.536891 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3263 04:37:51.540460 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3264 04:37:51.543681 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3265 04:37:51.549941 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3266 04:37:51.553724 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3267 04:37:51.556871 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3268 04:37:51.560068 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3269 04:37:51.563756 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3270 04:37:51.570388 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3271 04:37:51.570473 ==
3272 04:37:51.573417 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 04:37:51.577193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 04:37:51.577277 ==
3275 04:37:51.577345 DQS Delay:
3276 04:37:51.580283 DQS0 = 0, DQS1 = 0
3277 04:37:51.580366 DQM Delay:
3278 04:37:51.583255 DQM0 = 114, DQM1 = 106
3279 04:37:51.583338 DQ Delay:
3280 04:37:51.587121 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3281 04:37:51.590464 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3282 04:37:51.593236 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3283 04:37:51.596917 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3284 04:37:51.597024
3285 04:37:51.597126
3286 04:37:51.599832 ==
3287 04:37:51.599939 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 04:37:51.606892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 04:37:51.607001 ==
3290 04:37:51.607096
3291 04:37:51.607189
3292 04:37:51.610026 TX Vref Scan disable
3293 04:37:51.610130 == TX Byte 0 ==
3294 04:37:51.613495 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3295 04:37:51.620146 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3296 04:37:51.620253 == TX Byte 1 ==
3297 04:37:51.623204 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3298 04:37:51.629776 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3299 04:37:51.629883 ==
3300 04:37:51.633417 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 04:37:51.636446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 04:37:51.636555 ==
3303 04:37:51.648733 TX Vref=22, minBit 8, minWin=24, winSum=406
3304 04:37:51.651778 TX Vref=24, minBit 10, minWin=24, winSum=408
3305 04:37:51.655120 TX Vref=26, minBit 8, minWin=25, winSum=417
3306 04:37:51.658718 TX Vref=28, minBit 9, minWin=25, winSum=422
3307 04:37:51.661888 TX Vref=30, minBit 9, minWin=24, winSum=422
3308 04:37:51.668783 TX Vref=32, minBit 9, minWin=25, winSum=422
3309 04:37:51.671728 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
3310 04:37:51.671830
3311 04:37:51.675298 Final TX Range 1 Vref 28
3312 04:37:51.675407
3313 04:37:51.675502 ==
3314 04:37:51.678206 Dram Type= 6, Freq= 0, CH_1, rank 0
3315 04:37:51.681957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3316 04:37:51.682064 ==
3317 04:37:51.682157
3318 04:37:51.685034
3319 04:37:51.685136 TX Vref Scan disable
3320 04:37:51.688639 == TX Byte 0 ==
3321 04:37:51.691778 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3322 04:37:51.695334 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3323 04:37:51.698291 == TX Byte 1 ==
3324 04:37:51.701873 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3325 04:37:51.705518 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3326 04:37:51.705629
3327 04:37:51.708473 [DATLAT]
3328 04:37:51.708557 Freq=1200, CH1 RK0
3329 04:37:51.708624
3330 04:37:51.711625 DATLAT Default: 0xd
3331 04:37:51.711709 0, 0xFFFF, sum = 0
3332 04:37:51.715327 1, 0xFFFF, sum = 0
3333 04:37:51.715421 2, 0xFFFF, sum = 0
3334 04:37:51.718578 3, 0xFFFF, sum = 0
3335 04:37:51.718672 4, 0xFFFF, sum = 0
3336 04:37:51.722267 5, 0xFFFF, sum = 0
3337 04:37:51.722345 6, 0xFFFF, sum = 0
3338 04:37:51.725021 7, 0xFFFF, sum = 0
3339 04:37:51.725099 8, 0xFFFF, sum = 0
3340 04:37:51.728270 9, 0xFFFF, sum = 0
3341 04:37:51.731630 10, 0xFFFF, sum = 0
3342 04:37:51.731734 11, 0xFFFF, sum = 0
3343 04:37:51.735236 12, 0x0, sum = 1
3344 04:37:51.735347 13, 0x0, sum = 2
3345 04:37:51.735431 14, 0x0, sum = 3
3346 04:37:51.738616 15, 0x0, sum = 4
3347 04:37:51.738695 best_step = 13
3348 04:37:51.738758
3349 04:37:51.738822 ==
3350 04:37:51.742051 Dram Type= 6, Freq= 0, CH_1, rank 0
3351 04:37:51.748702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3352 04:37:51.748785 ==
3353 04:37:51.748853 RX Vref Scan: 1
3354 04:37:51.748920
3355 04:37:51.751725 Set Vref Range= 32 -> 127
3356 04:37:51.751797
3357 04:37:51.755346 RX Vref 32 -> 127, step: 1
3358 04:37:51.755429
3359 04:37:51.758634 RX Delay -21 -> 252, step: 4
3360 04:37:51.758707
3361 04:37:51.762344 Set Vref, RX VrefLevel [Byte0]: 32
3362 04:37:51.765411 [Byte1]: 32
3363 04:37:51.765483
3364 04:37:51.768623 Set Vref, RX VrefLevel [Byte0]: 33
3365 04:37:51.771663 [Byte1]: 33
3366 04:37:51.771745
3367 04:37:51.775334 Set Vref, RX VrefLevel [Byte0]: 34
3368 04:37:51.778451 [Byte1]: 34
3369 04:37:51.782485
3370 04:37:51.782568 Set Vref, RX VrefLevel [Byte0]: 35
3371 04:37:51.785733 [Byte1]: 35
3372 04:37:51.790733
3373 04:37:51.790814 Set Vref, RX VrefLevel [Byte0]: 36
3374 04:37:51.793681 [Byte1]: 36
3375 04:37:51.798668
3376 04:37:51.798750 Set Vref, RX VrefLevel [Byte0]: 37
3377 04:37:51.801596 [Byte1]: 37
3378 04:37:51.806459
3379 04:37:51.806544 Set Vref, RX VrefLevel [Byte0]: 38
3380 04:37:51.809385 [Byte1]: 38
3381 04:37:51.814224
3382 04:37:51.814329 Set Vref, RX VrefLevel [Byte0]: 39
3383 04:37:51.817817 [Byte1]: 39
3384 04:37:51.822240
3385 04:37:51.822318 Set Vref, RX VrefLevel [Byte0]: 40
3386 04:37:51.825238 [Byte1]: 40
3387 04:37:51.830064
3388 04:37:51.830170 Set Vref, RX VrefLevel [Byte0]: 41
3389 04:37:51.833268 [Byte1]: 41
3390 04:37:51.838165
3391 04:37:51.838249 Set Vref, RX VrefLevel [Byte0]: 42
3392 04:37:51.841459 [Byte1]: 42
3393 04:37:51.845891
3394 04:37:51.845971 Set Vref, RX VrefLevel [Byte0]: 43
3395 04:37:51.849264 [Byte1]: 43
3396 04:37:51.853715
3397 04:37:51.853800 Set Vref, RX VrefLevel [Byte0]: 44
3398 04:37:51.857113 [Byte1]: 44
3399 04:37:51.861550
3400 04:37:51.861632 Set Vref, RX VrefLevel [Byte0]: 45
3401 04:37:51.865202 [Byte1]: 45
3402 04:37:51.869637
3403 04:37:51.869718 Set Vref, RX VrefLevel [Byte0]: 46
3404 04:37:51.872817 [Byte1]: 46
3405 04:37:51.877704
3406 04:37:51.877787 Set Vref, RX VrefLevel [Byte0]: 47
3407 04:37:51.880797 [Byte1]: 47
3408 04:37:51.885736
3409 04:37:51.885819 Set Vref, RX VrefLevel [Byte0]: 48
3410 04:37:51.888662 [Byte1]: 48
3411 04:37:51.893607
3412 04:37:51.893693 Set Vref, RX VrefLevel [Byte0]: 49
3413 04:37:51.896733 [Byte1]: 49
3414 04:37:51.901675
3415 04:37:51.901792 Set Vref, RX VrefLevel [Byte0]: 50
3416 04:37:51.904750 [Byte1]: 50
3417 04:37:51.909513
3418 04:37:51.909595 Set Vref, RX VrefLevel [Byte0]: 51
3419 04:37:51.912701 [Byte1]: 51
3420 04:37:51.917566
3421 04:37:51.917647 Set Vref, RX VrefLevel [Byte0]: 52
3422 04:37:51.920504 [Byte1]: 52
3423 04:37:51.925026
3424 04:37:51.925122 Set Vref, RX VrefLevel [Byte0]: 53
3425 04:37:51.928763 [Byte1]: 53
3426 04:37:51.932988
3427 04:37:51.933093 Set Vref, RX VrefLevel [Byte0]: 54
3428 04:37:51.936286 [Byte1]: 54
3429 04:37:51.941271
3430 04:37:51.941354 Set Vref, RX VrefLevel [Byte0]: 55
3431 04:37:51.944372 [Byte1]: 55
3432 04:37:51.948924
3433 04:37:51.949034 Set Vref, RX VrefLevel [Byte0]: 56
3434 04:37:51.952393 [Byte1]: 56
3435 04:37:51.957081
3436 04:37:51.957173 Set Vref, RX VrefLevel [Byte0]: 57
3437 04:37:51.960118 [Byte1]: 57
3438 04:37:51.964741
3439 04:37:51.964838 Set Vref, RX VrefLevel [Byte0]: 58
3440 04:37:51.968290 [Byte1]: 58
3441 04:37:51.972590
3442 04:37:51.972688 Set Vref, RX VrefLevel [Byte0]: 59
3443 04:37:51.976241 [Byte1]: 59
3444 04:37:51.980525
3445 04:37:51.980633 Set Vref, RX VrefLevel [Byte0]: 60
3446 04:37:51.984097 [Byte1]: 60
3447 04:37:51.988353
3448 04:37:51.988462 Set Vref, RX VrefLevel [Byte0]: 61
3449 04:37:51.991984 [Byte1]: 61
3450 04:37:51.996325
3451 04:37:51.996434 Set Vref, RX VrefLevel [Byte0]: 62
3452 04:37:51.999984 [Byte1]: 62
3453 04:37:52.004261
3454 04:37:52.004351 Set Vref, RX VrefLevel [Byte0]: 63
3455 04:37:52.007972 [Byte1]: 63
3456 04:37:52.012245
3457 04:37:52.012329 Set Vref, RX VrefLevel [Byte0]: 64
3458 04:37:52.015792 [Byte1]: 64
3459 04:37:52.020206
3460 04:37:52.020299 Final RX Vref Byte 0 = 53 to rank0
3461 04:37:52.023303 Final RX Vref Byte 1 = 51 to rank0
3462 04:37:52.026865 Final RX Vref Byte 0 = 53 to rank1
3463 04:37:52.030260 Final RX Vref Byte 1 = 51 to rank1==
3464 04:37:52.033761 Dram Type= 6, Freq= 0, CH_1, rank 0
3465 04:37:52.036820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 04:37:52.040111 ==
3467 04:37:52.040190 DQS Delay:
3468 04:37:52.040272 DQS0 = 0, DQS1 = 0
3469 04:37:52.043849 DQM Delay:
3470 04:37:52.043934 DQM0 = 114, DQM1 = 105
3471 04:37:52.046875 DQ Delay:
3472 04:37:52.050642 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =110
3473 04:37:52.053492 DQ4 =112, DQ5 =122, DQ6 =128, DQ7 =112
3474 04:37:52.056972 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =100
3475 04:37:52.060459 DQ12 =114, DQ13 =110, DQ14 =112, DQ15 =112
3476 04:37:52.060542
3477 04:37:52.060608
3478 04:37:52.067051 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3479 04:37:52.070055 CH1 RK0: MR19=303, MR18=ECF4
3480 04:37:52.076968 CH1_RK0: MR19=0x303, MR18=0xECF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3481 04:37:52.077058
3482 04:37:52.080544 ----->DramcWriteLeveling(PI) begin...
3483 04:37:52.080647 ==
3484 04:37:52.083402 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 04:37:52.087114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 04:37:52.087193 ==
3487 04:37:52.090042 Write leveling (Byte 0): 24 => 24
3488 04:37:52.093643 Write leveling (Byte 1): 27 => 27
3489 04:37:52.097248 DramcWriteLeveling(PI) end<-----
3490 04:37:52.097339
3491 04:37:52.097404 ==
3492 04:37:52.100449 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 04:37:52.107262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 04:37:52.107378 ==
3495 04:37:52.107474 [Gating] SW mode calibration
3496 04:37:52.116998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3497 04:37:52.120086 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3498 04:37:52.123837 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3499 04:37:52.130236 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 04:37:52.133883 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 04:37:52.137041 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 04:37:52.143692 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 04:37:52.147057 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 04:37:52.150152 0 15 24 | B1->B0 | 3333 2525 | 0 0 | (0 0) (0 0)
3505 04:37:52.156919 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3506 04:37:52.160437 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 04:37:52.163342 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 04:37:52.170412 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 04:37:52.173340 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 04:37:52.177052 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 04:37:52.183308 1 0 20 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
3512 04:37:52.187086 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
3513 04:37:52.190227 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
3514 04:37:52.196569 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 04:37:52.200246 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 04:37:52.203534 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 04:37:52.206946 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 04:37:52.213318 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 04:37:52.216630 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 04:37:52.220113 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3521 04:37:52.227098 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3522 04:37:52.230172 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 04:37:52.233295 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 04:37:52.240007 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 04:37:52.243178 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 04:37:52.246797 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 04:37:52.253390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 04:37:52.257294 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 04:37:52.260228 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 04:37:52.266739 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 04:37:52.270355 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 04:37:52.273353 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 04:37:52.279869 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 04:37:52.283676 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 04:37:52.286677 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 04:37:52.293081 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3537 04:37:52.296230 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3538 04:37:52.299959 Total UI for P1: 0, mck2ui 16
3539 04:37:52.302897 best dqsien dly found for B0: ( 1, 3, 24)
3540 04:37:52.306371 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 04:37:52.309807 Total UI for P1: 0, mck2ui 16
3542 04:37:52.313135 best dqsien dly found for B1: ( 1, 3, 26)
3543 04:37:52.316484 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3544 04:37:52.319528 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3545 04:37:52.319640
3546 04:37:52.322756 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3547 04:37:52.329698 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3548 04:37:52.329784 [Gating] SW calibration Done
3549 04:37:52.332809 ==
3550 04:37:52.332894 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 04:37:52.339766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 04:37:52.339860 ==
3553 04:37:52.339928 RX Vref Scan: 0
3554 04:37:52.339990
3555 04:37:52.342655 RX Vref 0 -> 0, step: 1
3556 04:37:52.342770
3557 04:37:52.346244 RX Delay -40 -> 252, step: 8
3558 04:37:52.349368 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3559 04:37:52.353097 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3560 04:37:52.356190 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3561 04:37:52.362817 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3562 04:37:52.365921 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3563 04:37:52.369532 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3564 04:37:52.372690 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3565 04:37:52.376365 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3566 04:37:52.382740 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3567 04:37:52.386190 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3568 04:37:52.389502 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3569 04:37:52.392483 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3570 04:37:52.396203 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3571 04:37:52.402388 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3572 04:37:52.405981 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3573 04:37:52.409117 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3574 04:37:52.409239 ==
3575 04:37:52.412188 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 04:37:52.415903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 04:37:52.418895 ==
3578 04:37:52.419022 DQS Delay:
3579 04:37:52.419120 DQS0 = 0, DQS1 = 0
3580 04:37:52.422510 DQM Delay:
3581 04:37:52.422627 DQM0 = 110, DQM1 = 109
3582 04:37:52.425944 DQ Delay:
3583 04:37:52.429041 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3584 04:37:52.432282 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3585 04:37:52.435484 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3586 04:37:52.438940 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3587 04:37:52.439054
3588 04:37:52.439156
3589 04:37:52.439253 ==
3590 04:37:52.442146 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 04:37:52.446000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 04:37:52.446118 ==
3593 04:37:52.446217
3594 04:37:52.446311
3595 04:37:52.448937 TX Vref Scan disable
3596 04:37:52.452007 == TX Byte 0 ==
3597 04:37:52.455576 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3598 04:37:52.458646 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3599 04:37:52.462397 == TX Byte 1 ==
3600 04:37:52.465350 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3601 04:37:52.468502 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3602 04:37:52.468591 ==
3603 04:37:52.472177 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 04:37:52.478279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 04:37:52.478389 ==
3606 04:37:52.488930 TX Vref=22, minBit 9, minWin=25, winSum=421
3607 04:37:52.492603 TX Vref=24, minBit 9, minWin=25, winSum=423
3608 04:37:52.495773 TX Vref=26, minBit 3, minWin=26, winSum=431
3609 04:37:52.499044 TX Vref=28, minBit 0, minWin=26, winSum=433
3610 04:37:52.502644 TX Vref=30, minBit 9, minWin=26, winSum=433
3611 04:37:52.509404 TX Vref=32, minBit 8, minWin=26, winSum=432
3612 04:37:52.512527 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
3613 04:37:52.512629
3614 04:37:52.515554 Final TX Range 1 Vref 28
3615 04:37:52.515657
3616 04:37:52.515761 ==
3617 04:37:52.518667 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 04:37:52.522706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 04:37:52.522823 ==
3620 04:37:52.525730
3621 04:37:52.525844
3622 04:37:52.525938 TX Vref Scan disable
3623 04:37:52.528949 == TX Byte 0 ==
3624 04:37:52.532354 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3625 04:37:52.535661 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3626 04:37:52.538538 == TX Byte 1 ==
3627 04:37:52.541785 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3628 04:37:52.549061 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3629 04:37:52.549144
3630 04:37:52.549210 [DATLAT]
3631 04:37:52.549271 Freq=1200, CH1 RK1
3632 04:37:52.549331
3633 04:37:52.551850 DATLAT Default: 0xd
3634 04:37:52.551932 0, 0xFFFF, sum = 0
3635 04:37:52.555215 1, 0xFFFF, sum = 0
3636 04:37:52.558878 2, 0xFFFF, sum = 0
3637 04:37:52.558996 3, 0xFFFF, sum = 0
3638 04:37:52.562000 4, 0xFFFF, sum = 0
3639 04:37:52.562109 5, 0xFFFF, sum = 0
3640 04:37:52.565293 6, 0xFFFF, sum = 0
3641 04:37:52.565403 7, 0xFFFF, sum = 0
3642 04:37:52.568880 8, 0xFFFF, sum = 0
3643 04:37:52.568992 9, 0xFFFF, sum = 0
3644 04:37:52.571868 10, 0xFFFF, sum = 0
3645 04:37:52.571946 11, 0xFFFF, sum = 0
3646 04:37:52.575541 12, 0x0, sum = 1
3647 04:37:52.575619 13, 0x0, sum = 2
3648 04:37:52.578501 14, 0x0, sum = 3
3649 04:37:52.578605 15, 0x0, sum = 4
3650 04:37:52.581701 best_step = 13
3651 04:37:52.581772
3652 04:37:52.581832 ==
3653 04:37:52.585312 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 04:37:52.588422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 04:37:52.588501 ==
3656 04:37:52.588567 RX Vref Scan: 0
3657 04:37:52.588630
3658 04:37:52.592168 RX Vref 0 -> 0, step: 1
3659 04:37:52.592251
3660 04:37:52.595384 RX Delay -21 -> 252, step: 4
3661 04:37:52.598398 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3662 04:37:52.605256 iDelay=195, Bit 1, Center 106 (35 ~ 178) 144
3663 04:37:52.608604 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3664 04:37:52.611644 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3665 04:37:52.615205 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3666 04:37:52.618326 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3667 04:37:52.625172 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3668 04:37:52.628304 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3669 04:37:52.631481 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3670 04:37:52.635110 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3671 04:37:52.638666 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3672 04:37:52.644852 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3673 04:37:52.648662 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3674 04:37:52.651651 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3675 04:37:52.654931 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3676 04:37:52.661733 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3677 04:37:52.661817 ==
3678 04:37:52.664991 Dram Type= 6, Freq= 0, CH_1, rank 1
3679 04:37:52.668034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3680 04:37:52.668128 ==
3681 04:37:52.668199 DQS Delay:
3682 04:37:52.671700 DQS0 = 0, DQS1 = 0
3683 04:37:52.671804 DQM Delay:
3684 04:37:52.674948 DQM0 = 110, DQM1 = 109
3685 04:37:52.675024 DQ Delay:
3686 04:37:52.678256 DQ0 =112, DQ1 =106, DQ2 =100, DQ3 =108
3687 04:37:52.681653 DQ4 =110, DQ5 =120, DQ6 =120, DQ7 =108
3688 04:37:52.684710 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =104
3689 04:37:52.687989 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3690 04:37:52.688069
3691 04:37:52.688134
3692 04:37:52.698361 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3693 04:37:52.701502 CH1 RK1: MR19=304, MR18=F707
3694 04:37:52.704592 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3695 04:37:52.708162 [RxdqsGatingPostProcess] freq 1200
3696 04:37:52.714734 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3697 04:37:52.717757 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 04:37:52.721392 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 04:37:52.724451 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 04:37:52.728076 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 04:37:52.731253 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 04:37:52.734280 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 04:37:52.737994 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 04:37:52.741079 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 04:37:52.744118 Pre-setting of DQS Precalculation
3706 04:37:52.747715 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3707 04:37:52.754250 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3708 04:37:52.764207 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3709 04:37:52.764293
3710 04:37:52.764360
3711 04:37:52.764421 [Calibration Summary] 2400 Mbps
3712 04:37:52.767190 CH 0, Rank 0
3713 04:37:52.767273 SW Impedance : PASS
3714 04:37:52.770822 DUTY Scan : NO K
3715 04:37:52.774281 ZQ Calibration : PASS
3716 04:37:52.774363 Jitter Meter : NO K
3717 04:37:52.777349 CBT Training : PASS
3718 04:37:52.780916 Write leveling : PASS
3719 04:37:52.780999 RX DQS gating : PASS
3720 04:37:52.783903 RX DQ/DQS(RDDQC) : PASS
3721 04:37:52.787621 TX DQ/DQS : PASS
3722 04:37:52.787704 RX DATLAT : PASS
3723 04:37:52.790521 RX DQ/DQS(Engine): PASS
3724 04:37:52.793708 TX OE : NO K
3725 04:37:52.793792 All Pass.
3726 04:37:52.793858
3727 04:37:52.793919 CH 0, Rank 1
3728 04:37:52.797099 SW Impedance : PASS
3729 04:37:52.800548 DUTY Scan : NO K
3730 04:37:52.800640 ZQ Calibration : PASS
3731 04:37:52.803606 Jitter Meter : NO K
3732 04:37:52.806787 CBT Training : PASS
3733 04:37:52.806895 Write leveling : PASS
3734 04:37:52.810387 RX DQS gating : PASS
3735 04:37:52.814009 RX DQ/DQS(RDDQC) : PASS
3736 04:37:52.814120 TX DQ/DQS : PASS
3737 04:37:52.817092 RX DATLAT : PASS
3738 04:37:52.820204 RX DQ/DQS(Engine): PASS
3739 04:37:52.820280 TX OE : NO K
3740 04:37:52.820345 All Pass.
3741 04:37:52.823809
3742 04:37:52.823893 CH 1, Rank 0
3743 04:37:52.827379 SW Impedance : PASS
3744 04:37:52.827465 DUTY Scan : NO K
3745 04:37:52.830105 ZQ Calibration : PASS
3746 04:37:52.830183 Jitter Meter : NO K
3747 04:37:52.833306 CBT Training : PASS
3748 04:37:52.836920 Write leveling : PASS
3749 04:37:52.837004 RX DQS gating : PASS
3750 04:37:52.840233 RX DQ/DQS(RDDQC) : PASS
3751 04:37:52.843206 TX DQ/DQS : PASS
3752 04:37:52.843282 RX DATLAT : PASS
3753 04:37:52.846937 RX DQ/DQS(Engine): PASS
3754 04:37:52.850079 TX OE : NO K
3755 04:37:52.850164 All Pass.
3756 04:37:52.850230
3757 04:37:52.850293 CH 1, Rank 1
3758 04:37:52.853646 SW Impedance : PASS
3759 04:37:52.856573 DUTY Scan : NO K
3760 04:37:52.856657 ZQ Calibration : PASS
3761 04:37:52.860068 Jitter Meter : NO K
3762 04:37:52.863197 CBT Training : PASS
3763 04:37:52.863274 Write leveling : PASS
3764 04:37:52.867000 RX DQS gating : PASS
3765 04:37:52.870097 RX DQ/DQS(RDDQC) : PASS
3766 04:37:52.870173 TX DQ/DQS : PASS
3767 04:37:52.873228 RX DATLAT : PASS
3768 04:37:52.876381 RX DQ/DQS(Engine): PASS
3769 04:37:52.876463 TX OE : NO K
3770 04:37:52.876530 All Pass.
3771 04:37:52.879907
3772 04:37:52.880024 DramC Write-DBI off
3773 04:37:52.883067 PER_BANK_REFRESH: Hybrid Mode
3774 04:37:52.883176 TX_TRACKING: ON
3775 04:37:52.893271 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3776 04:37:52.896405 [FAST_K] Save calibration result to emmc
3777 04:37:52.899963 dramc_set_vcore_voltage set vcore to 650000
3778 04:37:52.903247 Read voltage for 600, 5
3779 04:37:52.903358 Vio18 = 0
3780 04:37:52.906677 Vcore = 650000
3781 04:37:52.906790 Vdram = 0
3782 04:37:52.906883 Vddq = 0
3783 04:37:52.906976 Vmddr = 0
3784 04:37:52.913072 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3785 04:37:52.919761 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3786 04:37:52.919876 MEM_TYPE=3, freq_sel=19
3787 04:37:52.922801 sv_algorithm_assistance_LP4_1600
3788 04:37:52.926468 ============ PULL DRAM RESETB DOWN ============
3789 04:37:52.932707 ========== PULL DRAM RESETB DOWN end =========
3790 04:37:52.936259 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3791 04:37:52.939860 ===================================
3792 04:37:52.943184 LPDDR4 DRAM CONFIGURATION
3793 04:37:52.946353 ===================================
3794 04:37:52.946437 EX_ROW_EN[0] = 0x0
3795 04:37:52.949489 EX_ROW_EN[1] = 0x0
3796 04:37:52.949573 LP4Y_EN = 0x0
3797 04:37:52.953240 WORK_FSP = 0x0
3798 04:37:52.953354 WL = 0x2
3799 04:37:52.956332 RL = 0x2
3800 04:37:52.959477 BL = 0x2
3801 04:37:52.959589 RPST = 0x0
3802 04:37:52.962997 RD_PRE = 0x0
3803 04:37:52.963098 WR_PRE = 0x1
3804 04:37:52.966056 WR_PST = 0x0
3805 04:37:52.966161 DBI_WR = 0x0
3806 04:37:52.969717 DBI_RD = 0x0
3807 04:37:52.969820 OTF = 0x1
3808 04:37:52.972917 ===================================
3809 04:37:52.976087 ===================================
3810 04:37:52.979212 ANA top config
3811 04:37:52.982769 ===================================
3812 04:37:52.982871 DLL_ASYNC_EN = 0
3813 04:37:52.986031 ALL_SLAVE_EN = 1
3814 04:37:52.989276 NEW_RANK_MODE = 1
3815 04:37:52.992568 DLL_IDLE_MODE = 1
3816 04:37:52.992669 LP45_APHY_COMB_EN = 1
3817 04:37:52.996005 TX_ODT_DIS = 1
3818 04:37:52.999549 NEW_8X_MODE = 1
3819 04:37:53.002599 ===================================
3820 04:37:53.005798 ===================================
3821 04:37:53.009035 data_rate = 1200
3822 04:37:53.012517 CKR = 1
3823 04:37:53.015767 DQ_P2S_RATIO = 8
3824 04:37:53.015850 ===================================
3825 04:37:53.019585 CA_P2S_RATIO = 8
3826 04:37:53.022553 DQ_CA_OPEN = 0
3827 04:37:53.026021 DQ_SEMI_OPEN = 0
3828 04:37:53.028952 CA_SEMI_OPEN = 0
3829 04:37:53.032701 CA_FULL_RATE = 0
3830 04:37:53.032784 DQ_CKDIV4_EN = 1
3831 04:37:53.035811 CA_CKDIV4_EN = 1
3832 04:37:53.038988 CA_PREDIV_EN = 0
3833 04:37:53.042590 PH8_DLY = 0
3834 04:37:53.045665 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3835 04:37:53.049131 DQ_AAMCK_DIV = 4
3836 04:37:53.049215 CA_AAMCK_DIV = 4
3837 04:37:53.052559 CA_ADMCK_DIV = 4
3838 04:37:53.055827 DQ_TRACK_CA_EN = 0
3839 04:37:53.058911 CA_PICK = 600
3840 04:37:53.062510 CA_MCKIO = 600
3841 04:37:53.065796 MCKIO_SEMI = 0
3842 04:37:53.068737 PLL_FREQ = 2288
3843 04:37:53.072431 DQ_UI_PI_RATIO = 32
3844 04:37:53.072522 CA_UI_PI_RATIO = 0
3845 04:37:53.075463 ===================================
3846 04:37:53.079187 ===================================
3847 04:37:53.082246 memory_type:LPDDR4
3848 04:37:53.085426 GP_NUM : 10
3849 04:37:53.085511 SRAM_EN : 1
3850 04:37:53.088571 MD32_EN : 0
3851 04:37:53.092384 ===================================
3852 04:37:53.095360 [ANA_INIT] >>>>>>>>>>>>>>
3853 04:37:53.098447 <<<<<< [CONFIGURE PHASE]: ANA_TX
3854 04:37:53.101859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3855 04:37:53.105295 ===================================
3856 04:37:53.105396 data_rate = 1200,PCW = 0X5800
3857 04:37:53.108524 ===================================
3858 04:37:53.112086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3859 04:37:53.118378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 04:37:53.124901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3861 04:37:53.128236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3862 04:37:53.131466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3863 04:37:53.135196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3864 04:37:53.138798 [ANA_INIT] flow start
3865 04:37:53.142063 [ANA_INIT] PLL >>>>>>>>
3866 04:37:53.142174 [ANA_INIT] PLL <<<<<<<<
3867 04:37:53.144869 [ANA_INIT] MIDPI >>>>>>>>
3868 04:37:53.148030 [ANA_INIT] MIDPI <<<<<<<<
3869 04:37:53.148131 [ANA_INIT] DLL >>>>>>>>
3870 04:37:53.151767 [ANA_INIT] flow end
3871 04:37:53.154787 ============ LP4 DIFF to SE enter ============
3872 04:37:53.158089 ============ LP4 DIFF to SE exit ============
3873 04:37:53.161660 [ANA_INIT] <<<<<<<<<<<<<
3874 04:37:53.164725 [Flow] Enable top DCM control >>>>>
3875 04:37:53.168453 [Flow] Enable top DCM control <<<<<
3876 04:37:53.171532 Enable DLL master slave shuffle
3877 04:37:53.177720 ==============================================================
3878 04:37:53.177830 Gating Mode config
3879 04:37:53.184582 ==============================================================
3880 04:37:53.187700 Config description:
3881 04:37:53.194443 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3882 04:37:53.200742 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3883 04:37:53.207541 SELPH_MODE 0: By rank 1: By Phase
3884 04:37:53.214434 ==============================================================
3885 04:37:53.214521 GAT_TRACK_EN = 1
3886 04:37:53.217587 RX_GATING_MODE = 2
3887 04:37:53.221025 RX_GATING_TRACK_MODE = 2
3888 04:37:53.224060 SELPH_MODE = 1
3889 04:37:53.227164 PICG_EARLY_EN = 1
3890 04:37:53.230719 VALID_LAT_VALUE = 1
3891 04:37:53.237441 ==============================================================
3892 04:37:53.240976 Enter into Gating configuration >>>>
3893 04:37:53.244307 Exit from Gating configuration <<<<
3894 04:37:53.247227 Enter into DVFS_PRE_config >>>>>
3895 04:37:53.257360 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3896 04:37:53.260435 Exit from DVFS_PRE_config <<<<<
3897 04:37:53.264039 Enter into PICG configuration >>>>
3898 04:37:53.267467 Exit from PICG configuration <<<<
3899 04:37:53.270574 [RX_INPUT] configuration >>>>>
3900 04:37:53.270662 [RX_INPUT] configuration <<<<<
3901 04:37:53.277139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3902 04:37:53.284020 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3903 04:37:53.290665 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 04:37:53.293771 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 04:37:53.300540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 04:37:53.307295 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 04:37:53.310450 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3908 04:37:53.313432 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3909 04:37:53.320049 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3910 04:37:53.323537 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3911 04:37:53.326564 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3912 04:37:53.333228 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 04:37:53.336893 ===================================
3914 04:37:53.336979 LPDDR4 DRAM CONFIGURATION
3915 04:37:53.340008 ===================================
3916 04:37:53.343643 EX_ROW_EN[0] = 0x0
3917 04:37:53.346736 EX_ROW_EN[1] = 0x0
3918 04:37:53.346819 LP4Y_EN = 0x0
3919 04:37:53.349854 WORK_FSP = 0x0
3920 04:37:53.349969 WL = 0x2
3921 04:37:53.353389 RL = 0x2
3922 04:37:53.353490 BL = 0x2
3923 04:37:53.356825 RPST = 0x0
3924 04:37:53.356928 RD_PRE = 0x0
3925 04:37:53.359991 WR_PRE = 0x1
3926 04:37:53.360089 WR_PST = 0x0
3927 04:37:53.363092 DBI_WR = 0x0
3928 04:37:53.363191 DBI_RD = 0x0
3929 04:37:53.366454 OTF = 0x1
3930 04:37:53.370037 ===================================
3931 04:37:53.373362 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3932 04:37:53.376704 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3933 04:37:53.382946 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 04:37:53.386741 ===================================
3935 04:37:53.386828 LPDDR4 DRAM CONFIGURATION
3936 04:37:53.389930 ===================================
3937 04:37:53.393463 EX_ROW_EN[0] = 0x10
3938 04:37:53.393541 EX_ROW_EN[1] = 0x0
3939 04:37:53.396567 LP4Y_EN = 0x0
3940 04:37:53.399672 WORK_FSP = 0x0
3941 04:37:53.399761 WL = 0x2
3942 04:37:53.402778 RL = 0x2
3943 04:37:53.402880 BL = 0x2
3944 04:37:53.406441 RPST = 0x0
3945 04:37:53.406533 RD_PRE = 0x0
3946 04:37:53.409539 WR_PRE = 0x1
3947 04:37:53.409613 WR_PST = 0x0
3948 04:37:53.413317 DBI_WR = 0x0
3949 04:37:53.413396 DBI_RD = 0x0
3950 04:37:53.416414 OTF = 0x1
3951 04:37:53.419636 ===================================
3952 04:37:53.426398 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3953 04:37:53.429492 nWR fixed to 30
3954 04:37:53.429579 [ModeRegInit_LP4] CH0 RK0
3955 04:37:53.433001 [ModeRegInit_LP4] CH0 RK1
3956 04:37:53.435849 [ModeRegInit_LP4] CH1 RK0
3957 04:37:53.439393 [ModeRegInit_LP4] CH1 RK1
3958 04:37:53.439496 match AC timing 17
3959 04:37:53.443161 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3960 04:37:53.449298 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3961 04:37:53.452504 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3962 04:37:53.459457 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3963 04:37:53.462454 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3964 04:37:53.462534 ==
3965 04:37:53.466378 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 04:37:53.469191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 04:37:53.469304 ==
3968 04:37:53.475626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3969 04:37:53.482251 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3970 04:37:53.485797 [CA 0] Center 37 (7~67) winsize 61
3971 04:37:53.488723 [CA 1] Center 37 (7~67) winsize 61
3972 04:37:53.492535 [CA 2] Center 35 (5~65) winsize 61
3973 04:37:53.495500 [CA 3] Center 35 (5~65) winsize 61
3974 04:37:53.498884 [CA 4] Center 34 (4~65) winsize 62
3975 04:37:53.502102 [CA 5] Center 34 (4~64) winsize 61
3976 04:37:53.502180
3977 04:37:53.505858 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3978 04:37:53.505939
3979 04:37:53.508834 [CATrainingPosCal] consider 1 rank data
3980 04:37:53.512574 u2DelayCellTimex100 = 270/100 ps
3981 04:37:53.515625 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3982 04:37:53.518726 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3983 04:37:53.521848 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3984 04:37:53.525459 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3985 04:37:53.528442 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3986 04:37:53.531988 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3987 04:37:53.532064
3988 04:37:53.538598 CA PerBit enable=1, Macro0, CA PI delay=34
3989 04:37:53.538680
3990 04:37:53.538760 [CBTSetCACLKResult] CA Dly = 34
3991 04:37:53.542256 CS Dly: 5 (0~36)
3992 04:37:53.542331 ==
3993 04:37:53.545448 Dram Type= 6, Freq= 0, CH_0, rank 1
3994 04:37:53.548817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 04:37:53.548912 ==
3996 04:37:53.555246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 04:37:53.561881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3998 04:37:53.565455 [CA 0] Center 37 (7~67) winsize 61
3999 04:37:53.568432 [CA 1] Center 37 (7~67) winsize 61
4000 04:37:53.572230 [CA 2] Center 35 (5~65) winsize 61
4001 04:37:53.575109 [CA 3] Center 35 (5~65) winsize 61
4002 04:37:53.578652 [CA 4] Center 34 (4~65) winsize 62
4003 04:37:53.582285 [CA 5] Center 33 (3~64) winsize 62
4004 04:37:53.582398
4005 04:37:53.585070 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4006 04:37:53.585151
4007 04:37:53.588701 [CATrainingPosCal] consider 2 rank data
4008 04:37:53.591810 u2DelayCellTimex100 = 270/100 ps
4009 04:37:53.594815 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4010 04:37:53.598290 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4011 04:37:53.601618 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4012 04:37:53.604817 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4013 04:37:53.607994 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4014 04:37:53.614688 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4015 04:37:53.614810
4016 04:37:53.618514 CA PerBit enable=1, Macro0, CA PI delay=34
4017 04:37:53.618666
4018 04:37:53.621403 [CBTSetCACLKResult] CA Dly = 34
4019 04:37:53.621481 CS Dly: 6 (0~38)
4020 04:37:53.621570
4021 04:37:53.625117 ----->DramcWriteLeveling(PI) begin...
4022 04:37:53.625251 ==
4023 04:37:53.628175 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 04:37:53.634668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 04:37:53.634785 ==
4026 04:37:53.638284 Write leveling (Byte 0): 33 => 33
4027 04:37:53.638403 Write leveling (Byte 1): 30 => 30
4028 04:37:53.641820 DramcWriteLeveling(PI) end<-----
4029 04:37:53.641924
4030 04:37:53.642017 ==
4031 04:37:53.644822 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 04:37:53.651288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 04:37:53.651400 ==
4034 04:37:53.654801 [Gating] SW mode calibration
4035 04:37:53.661192 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4036 04:37:53.664961 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4037 04:37:53.671898 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 04:37:53.674690 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 04:37:53.677753 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 04:37:53.684289 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4041 04:37:53.687897 0 9 16 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 0)
4042 04:37:53.691219 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 04:37:53.697791 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 04:37:53.700955 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 04:37:53.704701 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 04:37:53.710872 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 04:37:53.714332 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 04:37:53.717652 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4049 04:37:53.724381 0 10 16 | B1->B0 | 3232 3d3d | 0 0 | (0 0) (1 1)
4050 04:37:53.727491 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 04:37:53.730975 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 04:37:53.737139 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 04:37:53.740931 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 04:37:53.743936 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 04:37:53.747066 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 04:37:53.753664 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 04:37:53.757333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4058 04:37:53.760444 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 04:37:53.767070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 04:37:53.770644 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 04:37:53.773982 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 04:37:53.780904 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 04:37:53.783834 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 04:37:53.787343 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 04:37:53.794101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 04:37:53.796878 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 04:37:53.800466 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 04:37:53.807120 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 04:37:53.810123 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 04:37:53.813684 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 04:37:53.820461 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 04:37:53.823490 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4073 04:37:53.826965 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4074 04:37:53.833348 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 04:37:53.833434 Total UI for P1: 0, mck2ui 16
4076 04:37:53.839847 best dqsien dly found for B0: ( 0, 13, 14)
4077 04:37:53.839942 Total UI for P1: 0, mck2ui 16
4078 04:37:53.846742 best dqsien dly found for B1: ( 0, 13, 18)
4079 04:37:53.850470 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4080 04:37:53.853561 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4081 04:37:53.853642
4082 04:37:53.856940 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4083 04:37:53.860058 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4084 04:37:53.863035 [Gating] SW calibration Done
4085 04:37:53.863150 ==
4086 04:37:53.866857 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 04:37:53.870214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 04:37:53.870294 ==
4089 04:37:53.873310 RX Vref Scan: 0
4090 04:37:53.873397
4091 04:37:53.873462 RX Vref 0 -> 0, step: 1
4092 04:37:53.877163
4093 04:37:53.877240 RX Delay -230 -> 252, step: 16
4094 04:37:53.882878 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4095 04:37:53.886504 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4096 04:37:53.889844 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4097 04:37:53.892771 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4098 04:37:53.899881 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4099 04:37:53.902839 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4100 04:37:53.906424 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4101 04:37:53.909543 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4102 04:37:53.913095 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4103 04:37:53.919680 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4104 04:37:53.923350 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4105 04:37:53.926225 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4106 04:37:53.929689 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4107 04:37:53.936206 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4108 04:37:53.939697 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4109 04:37:53.942535 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4110 04:37:53.942622 ==
4111 04:37:53.946352 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 04:37:53.949274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 04:37:53.952945 ==
4114 04:37:53.953024 DQS Delay:
4115 04:37:53.953089 DQS0 = 0, DQS1 = 0
4116 04:37:53.955963 DQM Delay:
4117 04:37:53.956042 DQM0 = 38, DQM1 = 30
4118 04:37:53.959273 DQ Delay:
4119 04:37:53.959389 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4120 04:37:53.962608 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4121 04:37:53.966018 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4122 04:37:53.969421 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4123 04:37:53.969512
4124 04:37:53.973004
4125 04:37:53.973082 ==
4126 04:37:53.976219 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 04:37:53.979229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 04:37:53.979338 ==
4129 04:37:53.979424
4130 04:37:53.979485
4131 04:37:53.982357 TX Vref Scan disable
4132 04:37:53.982468 == TX Byte 0 ==
4133 04:37:53.988997 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4134 04:37:53.992492 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4135 04:37:53.992573 == TX Byte 1 ==
4136 04:37:53.999132 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4137 04:37:54.002255 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4138 04:37:54.002365 ==
4139 04:37:54.005925 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 04:37:54.009366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 04:37:54.009454 ==
4142 04:37:54.009522
4143 04:37:54.009584
4144 04:37:54.012676 TX Vref Scan disable
4145 04:37:54.015768 == TX Byte 0 ==
4146 04:37:54.019248 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4147 04:37:54.022416 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4148 04:37:54.025870 == TX Byte 1 ==
4149 04:37:54.029509 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4150 04:37:54.032378 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4151 04:37:54.032463
4152 04:37:54.036092 [DATLAT]
4153 04:37:54.036178 Freq=600, CH0 RK0
4154 04:37:54.036245
4155 04:37:54.039080 DATLAT Default: 0x9
4156 04:37:54.039194 0, 0xFFFF, sum = 0
4157 04:37:54.042659 1, 0xFFFF, sum = 0
4158 04:37:54.042745 2, 0xFFFF, sum = 0
4159 04:37:54.046092 3, 0xFFFF, sum = 0
4160 04:37:54.046205 4, 0xFFFF, sum = 0
4161 04:37:54.049555 5, 0xFFFF, sum = 0
4162 04:37:54.049668 6, 0xFFFF, sum = 0
4163 04:37:54.052685 7, 0xFFFF, sum = 0
4164 04:37:54.052770 8, 0x0, sum = 1
4165 04:37:54.055774 9, 0x0, sum = 2
4166 04:37:54.055859 10, 0x0, sum = 3
4167 04:37:54.059422 11, 0x0, sum = 4
4168 04:37:54.059512 best_step = 9
4169 04:37:54.059579
4170 04:37:54.059644 ==
4171 04:37:54.062427 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 04:37:54.068967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 04:37:54.069052 ==
4174 04:37:54.069119 RX Vref Scan: 1
4175 04:37:54.069182
4176 04:37:54.072553 RX Vref 0 -> 0, step: 1
4177 04:37:54.072639
4178 04:37:54.075471 RX Delay -195 -> 252, step: 8
4179 04:37:54.075554
4180 04:37:54.078872 Set Vref, RX VrefLevel [Byte0]: 61
4181 04:37:54.082474 [Byte1]: 51
4182 04:37:54.082555
4183 04:37:54.085412 Final RX Vref Byte 0 = 61 to rank0
4184 04:37:54.089238 Final RX Vref Byte 1 = 51 to rank0
4185 04:37:54.092189 Final RX Vref Byte 0 = 61 to rank1
4186 04:37:54.095885 Final RX Vref Byte 1 = 51 to rank1==
4187 04:37:54.098830 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 04:37:54.102129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 04:37:54.102214 ==
4190 04:37:54.105344 DQS Delay:
4191 04:37:54.105435 DQS0 = 0, DQS1 = 0
4192 04:37:54.105501 DQM Delay:
4193 04:37:54.108461 DQM0 = 35, DQM1 = 29
4194 04:37:54.108536 DQ Delay:
4195 04:37:54.111747 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =28
4196 04:37:54.115187 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =44
4197 04:37:54.118633 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4198 04:37:54.121790 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4199 04:37:54.121941
4200 04:37:54.122050
4201 04:37:54.131892 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4202 04:37:54.135422 CH0 RK0: MR19=808, MR18=3C3C
4203 04:37:54.138269 CH0_RK0: MR19=0x808, MR18=0x3C3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4204 04:37:54.141934
4205 04:37:54.145168 ----->DramcWriteLeveling(PI) begin...
4206 04:37:54.145245 ==
4207 04:37:54.148175 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 04:37:54.151812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 04:37:54.151901 ==
4210 04:37:54.154879 Write leveling (Byte 0): 32 => 32
4211 04:37:54.158344 Write leveling (Byte 1): 30 => 30
4212 04:37:54.161418 DramcWriteLeveling(PI) end<-----
4213 04:37:54.161521
4214 04:37:54.161623 ==
4215 04:37:54.165012 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 04:37:54.167847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 04:37:54.167923 ==
4218 04:37:54.171406 [Gating] SW mode calibration
4219 04:37:54.178210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4220 04:37:54.184958 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4221 04:37:54.188001 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 04:37:54.190974 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 04:37:54.197966 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 04:37:54.201359 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4225 04:37:54.204503 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4226 04:37:54.211030 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 04:37:54.214685 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 04:37:54.217887 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 04:37:54.224187 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 04:37:54.228224 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 04:37:54.230954 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 04:37:54.237366 0 10 12 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
4233 04:37:54.241008 0 10 16 | B1->B0 | 3737 4242 | 0 0 | (0 0) (0 0)
4234 04:37:54.244231 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 04:37:54.250791 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 04:37:54.254379 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 04:37:54.257473 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 04:37:54.264125 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 04:37:54.267276 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 04:37:54.270990 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4241 04:37:54.277156 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 04:37:54.280824 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 04:37:54.283923 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 04:37:54.287159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 04:37:54.293751 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 04:37:54.297457 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 04:37:54.303978 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 04:37:54.307129 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 04:37:54.310322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 04:37:54.316826 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 04:37:54.320393 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 04:37:54.323461 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 04:37:54.329880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 04:37:54.333189 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 04:37:54.336576 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 04:37:54.343316 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4257 04:37:54.343430 Total UI for P1: 0, mck2ui 16
4258 04:37:54.346360 best dqsien dly found for B0: ( 0, 13, 10)
4259 04:37:54.352879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 04:37:54.356322 Total UI for P1: 0, mck2ui 16
4261 04:37:54.359982 best dqsien dly found for B1: ( 0, 13, 12)
4262 04:37:54.362836 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4263 04:37:54.366484 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4264 04:37:54.366577
4265 04:37:54.369502 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4266 04:37:54.373131 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4267 04:37:54.376058 [Gating] SW calibration Done
4268 04:37:54.376134 ==
4269 04:37:54.379694 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 04:37:54.382752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 04:37:54.382837 ==
4272 04:37:54.386334 RX Vref Scan: 0
4273 04:37:54.386439
4274 04:37:54.389404 RX Vref 0 -> 0, step: 1
4275 04:37:54.389499
4276 04:37:54.393093 RX Delay -230 -> 252, step: 16
4277 04:37:54.396056 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4278 04:37:54.399051 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4279 04:37:54.402628 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4280 04:37:54.409336 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4281 04:37:54.412481 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4282 04:37:54.416001 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4283 04:37:54.419448 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4284 04:37:54.422577 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4285 04:37:54.429245 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4286 04:37:54.432548 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4287 04:37:54.436070 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4288 04:37:54.439336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4289 04:37:54.445879 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4290 04:37:54.448924 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4291 04:37:54.452547 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4292 04:37:54.456058 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4293 04:37:54.456131 ==
4294 04:37:54.459302 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 04:37:54.465540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 04:37:54.465642 ==
4297 04:37:54.465708 DQS Delay:
4298 04:37:54.469558 DQS0 = 0, DQS1 = 0
4299 04:37:54.469692 DQM Delay:
4300 04:37:54.469803 DQM0 = 36, DQM1 = 28
4301 04:37:54.472352 DQ Delay:
4302 04:37:54.476018 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4303 04:37:54.478972 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4304 04:37:54.482525 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4305 04:37:54.486063 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4306 04:37:54.486137
4307 04:37:54.486204
4308 04:37:54.486262 ==
4309 04:37:54.489025 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 04:37:54.492023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 04:37:54.492097 ==
4312 04:37:54.492164
4313 04:37:54.492222
4314 04:37:54.495584 TX Vref Scan disable
4315 04:37:54.495670 == TX Byte 0 ==
4316 04:37:54.502264 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4317 04:37:54.505515 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4318 04:37:54.505588 == TX Byte 1 ==
4319 04:37:54.512033 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4320 04:37:54.515785 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4321 04:37:54.515859 ==
4322 04:37:54.518690 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 04:37:54.522407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 04:37:54.522488 ==
4325 04:37:54.522558
4326 04:37:54.525505
4327 04:37:54.525599 TX Vref Scan disable
4328 04:37:54.528983 == TX Byte 0 ==
4329 04:37:54.532083 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4330 04:37:54.538814 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4331 04:37:54.538924 == TX Byte 1 ==
4332 04:37:54.542381 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4333 04:37:54.548662 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4334 04:37:54.548739
4335 04:37:54.548800 [DATLAT]
4336 04:37:54.548866 Freq=600, CH0 RK1
4337 04:37:54.548930
4338 04:37:54.552543 DATLAT Default: 0x9
4339 04:37:54.552621 0, 0xFFFF, sum = 0
4340 04:37:54.555485 1, 0xFFFF, sum = 0
4341 04:37:54.555601 2, 0xFFFF, sum = 0
4342 04:37:54.558821 3, 0xFFFF, sum = 0
4343 04:37:54.562085 4, 0xFFFF, sum = 0
4344 04:37:54.562160 5, 0xFFFF, sum = 0
4345 04:37:54.565491 6, 0xFFFF, sum = 0
4346 04:37:54.565572 7, 0xFFFF, sum = 0
4347 04:37:54.568580 8, 0x0, sum = 1
4348 04:37:54.568677 9, 0x0, sum = 2
4349 04:37:54.568741 10, 0x0, sum = 3
4350 04:37:54.572203 11, 0x0, sum = 4
4351 04:37:54.572288 best_step = 9
4352 04:37:54.572353
4353 04:37:54.572414 ==
4354 04:37:54.575572 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 04:37:54.582293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 04:37:54.582376 ==
4357 04:37:54.582440 RX Vref Scan: 0
4358 04:37:54.582501
4359 04:37:54.585456 RX Vref 0 -> 0, step: 1
4360 04:37:54.585570
4361 04:37:54.588737 RX Delay -195 -> 252, step: 8
4362 04:37:54.591861 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4363 04:37:54.599056 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4364 04:37:54.601963 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4365 04:37:54.604993 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4366 04:37:54.608472 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4367 04:37:54.615131 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4368 04:37:54.618258 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4369 04:37:54.621998 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4370 04:37:54.624993 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4371 04:37:54.628568 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4372 04:37:54.635191 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4373 04:37:54.638219 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4374 04:37:54.641788 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4375 04:37:54.644824 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4376 04:37:54.651487 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4377 04:37:54.655021 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4378 04:37:54.655124 ==
4379 04:37:54.658168 Dram Type= 6, Freq= 0, CH_0, rank 1
4380 04:37:54.661594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 04:37:54.661691 ==
4382 04:37:54.665091 DQS Delay:
4383 04:37:54.665191 DQS0 = 0, DQS1 = 0
4384 04:37:54.667906 DQM Delay:
4385 04:37:54.668008 DQM0 = 34, DQM1 = 28
4386 04:37:54.668100 DQ Delay:
4387 04:37:54.671505 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4388 04:37:54.674529 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4389 04:37:54.677974 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4390 04:37:54.681245 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4391 04:37:54.681341
4392 04:37:54.681432
4393 04:37:54.691212 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4394 04:37:54.694276 CH0 RK1: MR19=808, MR18=6A38
4395 04:37:54.701122 CH0_RK1: MR19=0x808, MR18=0x6A38, DQSOSC=389, MR23=63, INC=173, DEC=115
4396 04:37:54.701235 [RxdqsGatingPostProcess] freq 600
4397 04:37:54.707496 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4398 04:37:54.710860 Pre-setting of DQS Precalculation
4399 04:37:54.714321 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4400 04:37:54.717803 ==
4401 04:37:54.717944 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 04:37:54.724430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 04:37:54.724540 ==
4404 04:37:54.727346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4405 04:37:54.733981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4406 04:37:54.738122 [CA 0] Center 35 (5~66) winsize 62
4407 04:37:54.741217 [CA 1] Center 36 (6~66) winsize 61
4408 04:37:54.744740 [CA 2] Center 34 (4~65) winsize 62
4409 04:37:54.747822 [CA 3] Center 34 (4~65) winsize 62
4410 04:37:54.751409 [CA 4] Center 34 (4~65) winsize 62
4411 04:37:54.754502 [CA 5] Center 33 (3~64) winsize 62
4412 04:37:54.754602
4413 04:37:54.758092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4414 04:37:54.758193
4415 04:37:54.761325 [CATrainingPosCal] consider 1 rank data
4416 04:37:54.764724 u2DelayCellTimex100 = 270/100 ps
4417 04:37:54.767671 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4418 04:37:54.770963 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4419 04:37:54.777714 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 04:37:54.781259 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4421 04:37:54.784250 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 04:37:54.787829 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4423 04:37:54.787927
4424 04:37:54.790818 CA PerBit enable=1, Macro0, CA PI delay=33
4425 04:37:54.790918
4426 04:37:54.794491 [CBTSetCACLKResult] CA Dly = 33
4427 04:37:54.794592 CS Dly: 4 (0~35)
4428 04:37:54.798031 ==
4429 04:37:54.798131 Dram Type= 6, Freq= 0, CH_1, rank 1
4430 04:37:54.804178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 04:37:54.804285 ==
4432 04:37:54.807706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4433 04:37:54.814434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4434 04:37:54.817752 [CA 0] Center 36 (6~66) winsize 61
4435 04:37:54.821495 [CA 1] Center 36 (6~67) winsize 62
4436 04:37:54.824457 [CA 2] Center 34 (4~65) winsize 62
4437 04:37:54.827950 [CA 3] Center 34 (3~65) winsize 63
4438 04:37:54.831146 [CA 4] Center 34 (4~65) winsize 62
4439 04:37:54.834470 [CA 5] Center 34 (3~65) winsize 63
4440 04:37:54.834547
4441 04:37:54.837835 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4442 04:37:54.837999
4443 04:37:54.841543 [CATrainingPosCal] consider 2 rank data
4444 04:37:54.844778 u2DelayCellTimex100 = 270/100 ps
4445 04:37:54.847823 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4446 04:37:54.851488 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4447 04:37:54.858226 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4448 04:37:54.861272 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 04:37:54.864374 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4450 04:37:54.868075 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4451 04:37:54.868213
4452 04:37:54.871079 CA PerBit enable=1, Macro0, CA PI delay=33
4453 04:37:54.871178
4454 04:37:54.874527 [CBTSetCACLKResult] CA Dly = 33
4455 04:37:54.874659 CS Dly: 5 (0~37)
4456 04:37:54.874751
4457 04:37:54.878005 ----->DramcWriteLeveling(PI) begin...
4458 04:37:54.880957 ==
4459 04:37:54.884643 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 04:37:54.887683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 04:37:54.887783 ==
4462 04:37:54.890764 Write leveling (Byte 0): 31 => 31
4463 04:37:54.894327 Write leveling (Byte 1): 32 => 32
4464 04:37:54.897853 DramcWriteLeveling(PI) end<-----
4465 04:37:54.897955
4466 04:37:54.898045 ==
4467 04:37:54.901472 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 04:37:54.904536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 04:37:54.904637 ==
4470 04:37:54.907662 [Gating] SW mode calibration
4471 04:37:54.914529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4472 04:37:54.920975 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4473 04:37:54.924465 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 04:37:54.927479 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 04:37:54.934035 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 04:37:54.937444 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (0 1)
4477 04:37:54.940720 0 9 16 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
4478 04:37:54.944138 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 04:37:54.950641 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 04:37:54.954109 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 04:37:54.957333 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 04:37:54.964219 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 04:37:54.967539 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 04:37:54.970522 0 10 12 | B1->B0 | 2f2f 2e2e | 0 1 | (0 0) (0 0)
4485 04:37:54.977171 0 10 16 | B1->B0 | 4242 4343 | 0 0 | (0 0) (1 1)
4486 04:37:54.980719 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 04:37:54.983952 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 04:37:54.990492 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 04:37:54.993528 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 04:37:54.997151 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 04:37:55.003814 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 04:37:55.006902 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 04:37:55.010119 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 04:37:55.017006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 04:37:55.019768 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 04:37:55.023602 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 04:37:55.029859 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 04:37:55.033499 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 04:37:55.036579 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 04:37:55.043169 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 04:37:55.046635 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 04:37:55.049669 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 04:37:55.056321 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 04:37:55.059445 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 04:37:55.063202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 04:37:55.069712 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 04:37:55.072849 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 04:37:55.076215 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4509 04:37:55.079588 Total UI for P1: 0, mck2ui 16
4510 04:37:55.082745 best dqsien dly found for B0: ( 0, 13, 10)
4511 04:37:55.089586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 04:37:55.089672 Total UI for P1: 0, mck2ui 16
4513 04:37:55.095959 best dqsien dly found for B1: ( 0, 13, 12)
4514 04:37:55.099669 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4515 04:37:55.102716 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4516 04:37:55.102799
4517 04:37:55.106298 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4518 04:37:55.109225 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4519 04:37:55.112970 [Gating] SW calibration Done
4520 04:37:55.113051 ==
4521 04:37:55.116028 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 04:37:55.119888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 04:37:55.119971 ==
4524 04:37:55.122580 RX Vref Scan: 0
4525 04:37:55.122661
4526 04:37:55.122726 RX Vref 0 -> 0, step: 1
4527 04:37:55.125913
4528 04:37:55.125995 RX Delay -230 -> 252, step: 16
4529 04:37:55.132778 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4530 04:37:55.136307 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4531 04:37:55.139433 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4532 04:37:55.142499 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4533 04:37:55.149313 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4534 04:37:55.152596 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4535 04:37:55.155590 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4536 04:37:55.159166 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4537 04:37:55.162218 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4538 04:37:55.169278 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4539 04:37:55.172403 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4540 04:37:55.176226 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4541 04:37:55.179004 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4542 04:37:55.185606 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4543 04:37:55.188679 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4544 04:37:55.192166 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4545 04:37:55.192281 ==
4546 04:37:55.195255 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 04:37:55.198659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 04:37:55.202381 ==
4549 04:37:55.202483 DQS Delay:
4550 04:37:55.202574 DQS0 = 0, DQS1 = 0
4551 04:37:55.205434 DQM Delay:
4552 04:37:55.205536 DQM0 = 42, DQM1 = 33
4553 04:37:55.208611 DQ Delay:
4554 04:37:55.212556 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4555 04:37:55.212635 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4556 04:37:55.215537 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4557 04:37:55.218728 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4558 04:37:55.222264
4559 04:37:55.222368
4560 04:37:55.222463 ==
4561 04:37:55.225193 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 04:37:55.228832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 04:37:55.228936 ==
4564 04:37:55.229030
4565 04:37:55.229120
4566 04:37:55.231795 TX Vref Scan disable
4567 04:37:55.231895 == TX Byte 0 ==
4568 04:37:55.238825 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4569 04:37:55.242207 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4570 04:37:55.242290 == TX Byte 1 ==
4571 04:37:55.248594 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4572 04:37:55.252186 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4573 04:37:55.252268 ==
4574 04:37:55.255183 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 04:37:55.258517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 04:37:55.258600 ==
4577 04:37:55.258666
4578 04:37:55.258727
4579 04:37:55.262173 TX Vref Scan disable
4580 04:37:55.265177 == TX Byte 0 ==
4581 04:37:55.268342 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4582 04:37:55.271846 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4583 04:37:55.274852 == TX Byte 1 ==
4584 04:37:55.278766 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4585 04:37:55.281817 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4586 04:37:55.284871
4587 04:37:55.284953 [DATLAT]
4588 04:37:55.285019 Freq=600, CH1 RK0
4589 04:37:55.285080
4590 04:37:55.288557 DATLAT Default: 0x9
4591 04:37:55.288638 0, 0xFFFF, sum = 0
4592 04:37:55.291586 1, 0xFFFF, sum = 0
4593 04:37:55.291669 2, 0xFFFF, sum = 0
4594 04:37:55.295091 3, 0xFFFF, sum = 0
4595 04:37:55.295174 4, 0xFFFF, sum = 0
4596 04:37:55.298670 5, 0xFFFF, sum = 0
4597 04:37:55.298755 6, 0xFFFF, sum = 0
4598 04:37:55.301575 7, 0xFFFF, sum = 0
4599 04:37:55.301658 8, 0x0, sum = 1
4600 04:37:55.304913 9, 0x0, sum = 2
4601 04:37:55.304996 10, 0x0, sum = 3
4602 04:37:55.308081 11, 0x0, sum = 4
4603 04:37:55.308181 best_step = 9
4604 04:37:55.308261
4605 04:37:55.308322 ==
4606 04:37:55.311417 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 04:37:55.318003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 04:37:55.318086 ==
4609 04:37:55.318151 RX Vref Scan: 1
4610 04:37:55.318214
4611 04:37:55.321632 RX Vref 0 -> 0, step: 1
4612 04:37:55.321730
4613 04:37:55.324600 RX Delay -195 -> 252, step: 8
4614 04:37:55.324682
4615 04:37:55.328376 Set Vref, RX VrefLevel [Byte0]: 53
4616 04:37:55.331482 [Byte1]: 51
4617 04:37:55.331565
4618 04:37:55.335082 Final RX Vref Byte 0 = 53 to rank0
4619 04:37:55.338014 Final RX Vref Byte 1 = 51 to rank0
4620 04:37:55.341467 Final RX Vref Byte 0 = 53 to rank1
4621 04:37:55.344522 Final RX Vref Byte 1 = 51 to rank1==
4622 04:37:55.348075 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 04:37:55.350957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 04:37:55.351059 ==
4625 04:37:55.354393 DQS Delay:
4626 04:37:55.354490 DQS0 = 0, DQS1 = 0
4627 04:37:55.358148 DQM Delay:
4628 04:37:55.358249 DQM0 = 38, DQM1 = 29
4629 04:37:55.358342 DQ Delay:
4630 04:37:55.361061 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4631 04:37:55.364365 DQ4 =36, DQ5 =44, DQ6 =52, DQ7 =36
4632 04:37:55.367846 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4633 04:37:55.370858 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4634 04:37:55.370962
4635 04:37:55.371054
4636 04:37:55.381215 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4637 04:37:55.384239 CH1 RK0: MR19=808, MR18=1F2C
4638 04:37:55.388071 CH1_RK0: MR19=0x808, MR18=0x1F2C, DQSOSC=401, MR23=63, INC=163, DEC=108
4639 04:37:55.390884
4640 04:37:55.394520 ----->DramcWriteLeveling(PI) begin...
4641 04:37:55.394624 ==
4642 04:37:55.397615 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 04:37:55.401129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 04:37:55.401237 ==
4645 04:37:55.404211 Write leveling (Byte 0): 30 => 30
4646 04:37:55.407808 Write leveling (Byte 1): 30 => 30
4647 04:37:55.410681 DramcWriteLeveling(PI) end<-----
4648 04:37:55.410822
4649 04:37:55.410913 ==
4650 04:37:55.414464 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 04:37:55.417587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 04:37:55.417687 ==
4653 04:37:55.421101 [Gating] SW mode calibration
4654 04:37:55.427761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4655 04:37:55.434018 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4656 04:37:55.437343 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 04:37:55.440757 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 04:37:55.447208 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4659 04:37:55.450368 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (0 0)
4660 04:37:55.454117 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4661 04:37:55.460452 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 04:37:55.463904 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 04:37:55.466912 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 04:37:55.474257 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 04:37:55.476872 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 04:37:55.480511 0 10 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
4667 04:37:55.487214 0 10 12 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
4668 04:37:55.490306 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4669 04:37:55.493945 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 04:37:55.500042 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 04:37:55.503635 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 04:37:55.506708 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 04:37:55.513283 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 04:37:55.516811 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 04:37:55.520374 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4676 04:37:55.523756 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 04:37:55.530164 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 04:37:55.533258 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 04:37:55.536854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 04:37:55.543652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 04:37:55.546712 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 04:37:55.549992 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 04:37:55.556866 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 04:37:55.559937 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 04:37:55.563000 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 04:37:55.570004 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 04:37:55.572931 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 04:37:55.576403 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 04:37:55.583300 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 04:37:55.586612 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 04:37:55.589794 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4692 04:37:55.596206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 04:37:55.599810 Total UI for P1: 0, mck2ui 16
4694 04:37:55.602953 best dqsien dly found for B0: ( 0, 13, 12)
4695 04:37:55.603054 Total UI for P1: 0, mck2ui 16
4696 04:37:55.609469 best dqsien dly found for B1: ( 0, 13, 12)
4697 04:37:55.613009 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4698 04:37:55.616112 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4699 04:37:55.616191
4700 04:37:55.619550 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4701 04:37:55.623055 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4702 04:37:55.626106 [Gating] SW calibration Done
4703 04:37:55.626205 ==
4704 04:37:55.629602 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 04:37:55.632783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 04:37:55.632885 ==
4707 04:37:55.636297 RX Vref Scan: 0
4708 04:37:55.636402
4709 04:37:55.636496 RX Vref 0 -> 0, step: 1
4710 04:37:55.639382
4711 04:37:55.639529 RX Delay -230 -> 252, step: 16
4712 04:37:55.645954 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4713 04:37:55.649462 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4714 04:37:55.652668 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4715 04:37:55.655698 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4716 04:37:55.662609 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4717 04:37:55.666086 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4718 04:37:55.669038 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4719 04:37:55.672659 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4720 04:37:55.675658 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4721 04:37:55.682826 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4722 04:37:55.685885 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4723 04:37:55.689313 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4724 04:37:55.692475 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4725 04:37:55.699159 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4726 04:37:55.702073 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4727 04:37:55.705773 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4728 04:37:55.705886 ==
4729 04:37:55.708886 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 04:37:55.712415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 04:37:55.715286 ==
4732 04:37:55.715409 DQS Delay:
4733 04:37:55.715476 DQS0 = 0, DQS1 = 0
4734 04:37:55.719001 DQM Delay:
4735 04:37:55.719100 DQM0 = 35, DQM1 = 28
4736 04:37:55.722465 DQ Delay:
4737 04:37:55.725454 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4738 04:37:55.725556 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4739 04:37:55.729229 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4740 04:37:55.732204 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4741 04:37:55.735819
4742 04:37:55.735896
4743 04:37:55.735968 ==
4744 04:37:55.738564 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 04:37:55.742145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 04:37:55.742252 ==
4747 04:37:55.742348
4748 04:37:55.742442
4749 04:37:55.745857 TX Vref Scan disable
4750 04:37:55.745957 == TX Byte 0 ==
4751 04:37:55.752344 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4752 04:37:55.755357 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4753 04:37:55.755442 == TX Byte 1 ==
4754 04:37:55.762126 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4755 04:37:55.764982 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4756 04:37:55.765083 ==
4757 04:37:55.768375 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 04:37:55.771882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 04:37:55.771987 ==
4760 04:37:55.772083
4761 04:37:55.772174
4762 04:37:55.775469 TX Vref Scan disable
4763 04:37:55.778504 == TX Byte 0 ==
4764 04:37:55.781837 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4765 04:37:55.785240 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4766 04:37:55.788256 == TX Byte 1 ==
4767 04:37:55.791736 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4768 04:37:55.795093 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4769 04:37:55.798546
4770 04:37:55.798648 [DATLAT]
4771 04:37:55.798741 Freq=600, CH1 RK1
4772 04:37:55.798835
4773 04:37:55.801639 DATLAT Default: 0x9
4774 04:37:55.801739 0, 0xFFFF, sum = 0
4775 04:37:55.805093 1, 0xFFFF, sum = 0
4776 04:37:55.805197 2, 0xFFFF, sum = 0
4777 04:37:55.808404 3, 0xFFFF, sum = 0
4778 04:37:55.811324 4, 0xFFFF, sum = 0
4779 04:37:55.811441 5, 0xFFFF, sum = 0
4780 04:37:55.814989 6, 0xFFFF, sum = 0
4781 04:37:55.815092 7, 0xFFFF, sum = 0
4782 04:37:55.818613 8, 0x0, sum = 1
4783 04:37:55.818723 9, 0x0, sum = 2
4784 04:37:55.818822 10, 0x0, sum = 3
4785 04:37:55.821449 11, 0x0, sum = 4
4786 04:37:55.821525 best_step = 9
4787 04:37:55.821588
4788 04:37:55.821652 ==
4789 04:37:55.824596 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 04:37:55.831653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 04:37:55.831755 ==
4792 04:37:55.831837 RX Vref Scan: 0
4793 04:37:55.831907
4794 04:37:55.834568 RX Vref 0 -> 0, step: 1
4795 04:37:55.834666
4796 04:37:55.838146 RX Delay -195 -> 252, step: 8
4797 04:37:55.841638 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4798 04:37:55.847861 iDelay=205, Bit 1, Center 28 (-131 ~ 188) 320
4799 04:37:55.851442 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4800 04:37:55.854490 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4801 04:37:55.858129 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4802 04:37:55.864738 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4803 04:37:55.868087 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4804 04:37:55.871297 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4805 04:37:55.874790 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4806 04:37:55.877887 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4807 04:37:55.884294 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4808 04:37:55.887885 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4809 04:37:55.891084 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4810 04:37:55.894732 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4811 04:37:55.901300 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4812 04:37:55.904417 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4813 04:37:55.904500 ==
4814 04:37:55.907879 Dram Type= 6, Freq= 0, CH_1, rank 1
4815 04:37:55.910710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4816 04:37:55.910793 ==
4817 04:37:55.914009 DQS Delay:
4818 04:37:55.914091 DQS0 = 0, DQS1 = 0
4819 04:37:55.914156 DQM Delay:
4820 04:37:55.917806 DQM0 = 35, DQM1 = 29
4821 04:37:55.917888 DQ Delay:
4822 04:37:55.920984 DQ0 =40, DQ1 =28, DQ2 =24, DQ3 =32
4823 04:37:55.923980 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4824 04:37:55.927530 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4825 04:37:55.931030 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4826 04:37:55.931112
4827 04:37:55.931178
4828 04:37:55.940638 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4829 04:37:55.944221 CH1 RK1: MR19=808, MR18=3B5B
4830 04:37:55.947312 CH1_RK1: MR19=0x808, MR18=0x3B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4831 04:37:55.950651 [RxdqsGatingPostProcess] freq 600
4832 04:37:55.957883 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4833 04:37:55.960677 Pre-setting of DQS Precalculation
4834 04:37:55.964346 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4835 04:37:55.973968 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4836 04:37:55.980564 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4837 04:37:55.980646
4838 04:37:55.980712
4839 04:37:55.984151 [Calibration Summary] 1200 Mbps
4840 04:37:55.984270 CH 0, Rank 0
4841 04:37:55.987545 SW Impedance : PASS
4842 04:37:55.987627 DUTY Scan : NO K
4843 04:37:55.990980 ZQ Calibration : PASS
4844 04:37:55.993984 Jitter Meter : NO K
4845 04:37:55.994099 CBT Training : PASS
4846 04:37:55.997497 Write leveling : PASS
4847 04:37:56.000776 RX DQS gating : PASS
4848 04:37:56.000858 RX DQ/DQS(RDDQC) : PASS
4849 04:37:56.004160 TX DQ/DQS : PASS
4850 04:37:56.004243 RX DATLAT : PASS
4851 04:37:56.007166 RX DQ/DQS(Engine): PASS
4852 04:37:56.010810 TX OE : NO K
4853 04:37:56.010908 All Pass.
4854 04:37:56.010973
4855 04:37:56.013815 CH 0, Rank 1
4856 04:37:56.013897 SW Impedance : PASS
4857 04:37:56.016739 DUTY Scan : NO K
4858 04:37:56.016821 ZQ Calibration : PASS
4859 04:37:56.020471 Jitter Meter : NO K
4860 04:37:56.023405 CBT Training : PASS
4861 04:37:56.023502 Write leveling : PASS
4862 04:37:56.026990 RX DQS gating : PASS
4863 04:37:56.030396 RX DQ/DQS(RDDQC) : PASS
4864 04:37:56.030479 TX DQ/DQS : PASS
4865 04:37:56.033730 RX DATLAT : PASS
4866 04:37:56.036731 RX DQ/DQS(Engine): PASS
4867 04:37:56.036814 TX OE : NO K
4868 04:37:56.040250 All Pass.
4869 04:37:56.040374
4870 04:37:56.040471 CH 1, Rank 0
4871 04:37:56.043220 SW Impedance : PASS
4872 04:37:56.043328 DUTY Scan : NO K
4873 04:37:56.046727 ZQ Calibration : PASS
4874 04:37:56.050273 Jitter Meter : NO K
4875 04:37:56.050370 CBT Training : PASS
4876 04:37:56.053166 Write leveling : PASS
4877 04:37:56.056664 RX DQS gating : PASS
4878 04:37:56.056767 RX DQ/DQS(RDDQC) : PASS
4879 04:37:56.060175 TX DQ/DQS : PASS
4880 04:37:56.063211 RX DATLAT : PASS
4881 04:37:56.063319 RX DQ/DQS(Engine): PASS
4882 04:37:56.066798 TX OE : NO K
4883 04:37:56.066881 All Pass.
4884 04:37:56.066961
4885 04:37:56.069771 CH 1, Rank 1
4886 04:37:56.069853 SW Impedance : PASS
4887 04:37:56.073442 DUTY Scan : NO K
4888 04:37:56.076457 ZQ Calibration : PASS
4889 04:37:56.076539 Jitter Meter : NO K
4890 04:37:56.079652 CBT Training : PASS
4891 04:37:56.079734 Write leveling : PASS
4892 04:37:56.082982 RX DQS gating : PASS
4893 04:37:56.086526 RX DQ/DQS(RDDQC) : PASS
4894 04:37:56.086608 TX DQ/DQS : PASS
4895 04:37:56.089547 RX DATLAT : PASS
4896 04:37:56.093148 RX DQ/DQS(Engine): PASS
4897 04:37:56.093246 TX OE : NO K
4898 04:37:56.096510 All Pass.
4899 04:37:56.096620
4900 04:37:56.096713 DramC Write-DBI off
4901 04:37:56.099974 PER_BANK_REFRESH: Hybrid Mode
4902 04:37:56.102926 TX_TRACKING: ON
4903 04:37:56.109776 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4904 04:37:56.112808 [FAST_K] Save calibration result to emmc
4905 04:37:56.119569 dramc_set_vcore_voltage set vcore to 662500
4906 04:37:56.119676 Read voltage for 933, 3
4907 04:37:56.119768 Vio18 = 0
4908 04:37:56.122523 Vcore = 662500
4909 04:37:56.122625 Vdram = 0
4910 04:37:56.122714 Vddq = 0
4911 04:37:56.126103 Vmddr = 0
4912 04:37:56.129102 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4913 04:37:56.135649 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4914 04:37:56.139281 MEM_TYPE=3, freq_sel=17
4915 04:37:56.139416 sv_algorithm_assistance_LP4_1600
4916 04:37:56.145716 ============ PULL DRAM RESETB DOWN ============
4917 04:37:56.149167 ========== PULL DRAM RESETB DOWN end =========
4918 04:37:56.152493 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4919 04:37:56.155826 ===================================
4920 04:37:56.158912 LPDDR4 DRAM CONFIGURATION
4921 04:37:56.162433 ===================================
4922 04:37:56.165633 EX_ROW_EN[0] = 0x0
4923 04:37:56.165735 EX_ROW_EN[1] = 0x0
4924 04:37:56.168746 LP4Y_EN = 0x0
4925 04:37:56.168849 WORK_FSP = 0x0
4926 04:37:56.172478 WL = 0x3
4927 04:37:56.172600 RL = 0x3
4928 04:37:56.175347 BL = 0x2
4929 04:37:56.175476 RPST = 0x0
4930 04:37:56.179100 RD_PRE = 0x0
4931 04:37:56.179204 WR_PRE = 0x1
4932 04:37:56.182244 WR_PST = 0x0
4933 04:37:56.182343 DBI_WR = 0x0
4934 04:37:56.185263 DBI_RD = 0x0
4935 04:37:56.188785 OTF = 0x1
4936 04:37:56.192269 ===================================
4937 04:37:56.192383 ===================================
4938 04:37:56.195031 ANA top config
4939 04:37:56.198909 ===================================
4940 04:37:56.201771 DLL_ASYNC_EN = 0
4941 04:37:56.201875 ALL_SLAVE_EN = 1
4942 04:37:56.205181 NEW_RANK_MODE = 1
4943 04:37:56.208634 DLL_IDLE_MODE = 1
4944 04:37:56.211920 LP45_APHY_COMB_EN = 1
4945 04:37:56.215284 TX_ODT_DIS = 1
4946 04:37:56.215392 NEW_8X_MODE = 1
4947 04:37:56.218329 ===================================
4948 04:37:56.222012 ===================================
4949 04:37:56.225024 data_rate = 1866
4950 04:37:56.228147 CKR = 1
4951 04:37:56.231629 DQ_P2S_RATIO = 8
4952 04:37:56.234638 ===================================
4953 04:37:56.238223 CA_P2S_RATIO = 8
4954 04:37:56.241364 DQ_CA_OPEN = 0
4955 04:37:56.241474 DQ_SEMI_OPEN = 0
4956 04:37:56.245036 CA_SEMI_OPEN = 0
4957 04:37:56.247857 CA_FULL_RATE = 0
4958 04:37:56.251353 DQ_CKDIV4_EN = 1
4959 04:37:56.254437 CA_CKDIV4_EN = 1
4960 04:37:56.258124 CA_PREDIV_EN = 0
4961 04:37:56.258228 PH8_DLY = 0
4962 04:37:56.261089 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4963 04:37:56.264900 DQ_AAMCK_DIV = 4
4964 04:37:56.268155 CA_AAMCK_DIV = 4
4965 04:37:56.271409 CA_ADMCK_DIV = 4
4966 04:37:56.274282 DQ_TRACK_CA_EN = 0
4967 04:37:56.278153 CA_PICK = 933
4968 04:37:56.278255 CA_MCKIO = 933
4969 04:37:56.281530 MCKIO_SEMI = 0
4970 04:37:56.284218 PLL_FREQ = 3732
4971 04:37:56.287448 DQ_UI_PI_RATIO = 32
4972 04:37:56.290876 CA_UI_PI_RATIO = 0
4973 04:37:56.294434 ===================================
4974 04:37:56.297694 ===================================
4975 04:37:56.301126 memory_type:LPDDR4
4976 04:37:56.301228 GP_NUM : 10
4977 04:37:56.304397 SRAM_EN : 1
4978 04:37:56.304501 MD32_EN : 0
4979 04:37:56.307669 ===================================
4980 04:37:56.311319 [ANA_INIT] >>>>>>>>>>>>>>
4981 04:37:56.314114 <<<<<< [CONFIGURE PHASE]: ANA_TX
4982 04:37:56.317560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4983 04:37:56.321117 ===================================
4984 04:37:56.324141 data_rate = 1866,PCW = 0X8f00
4985 04:37:56.327845 ===================================
4986 04:37:56.330849 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4987 04:37:56.337625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 04:37:56.341063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4989 04:37:56.347193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4990 04:37:56.350700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4991 04:37:56.354224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4992 04:37:56.354328 [ANA_INIT] flow start
4993 04:37:56.357198 [ANA_INIT] PLL >>>>>>>>
4994 04:37:56.360839 [ANA_INIT] PLL <<<<<<<<
4995 04:37:56.360944 [ANA_INIT] MIDPI >>>>>>>>
4996 04:37:56.363835 [ANA_INIT] MIDPI <<<<<<<<
4997 04:37:56.367747 [ANA_INIT] DLL >>>>>>>>
4998 04:37:56.367824 [ANA_INIT] flow end
4999 04:37:56.374257 ============ LP4 DIFF to SE enter ============
5000 04:37:56.377165 ============ LP4 DIFF to SE exit ============
5001 04:37:56.380466 [ANA_INIT] <<<<<<<<<<<<<
5002 04:37:56.383960 [Flow] Enable top DCM control >>>>>
5003 04:37:56.386905 [Flow] Enable top DCM control <<<<<
5004 04:37:56.387008 Enable DLL master slave shuffle
5005 04:37:56.393772 ==============================================================
5006 04:37:56.396986 Gating Mode config
5007 04:37:56.400154 ==============================================================
5008 04:37:56.403581 Config description:
5009 04:37:56.413305 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5010 04:37:56.419960 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5011 04:37:56.423200 SELPH_MODE 0: By rank 1: By Phase
5012 04:37:56.429765 ==============================================================
5013 04:37:56.433395 GAT_TRACK_EN = 1
5014 04:37:56.436491 RX_GATING_MODE = 2
5015 04:37:56.440197 RX_GATING_TRACK_MODE = 2
5016 04:37:56.443093 SELPH_MODE = 1
5017 04:37:56.443200 PICG_EARLY_EN = 1
5018 04:37:56.446634 VALID_LAT_VALUE = 1
5019 04:37:56.453157 ==============================================================
5020 04:37:56.456159 Enter into Gating configuration >>>>
5021 04:37:56.459644 Exit from Gating configuration <<<<
5022 04:37:56.463314 Enter into DVFS_PRE_config >>>>>
5023 04:37:56.472896 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5024 04:37:56.475942 Exit from DVFS_PRE_config <<<<<
5025 04:37:56.479614 Enter into PICG configuration >>>>
5026 04:37:56.482546 Exit from PICG configuration <<<<
5027 04:37:56.486166 [RX_INPUT] configuration >>>>>
5028 04:37:56.489441 [RX_INPUT] configuration <<<<<
5029 04:37:56.495712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5030 04:37:56.499308 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5031 04:37:56.506153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 04:37:56.512198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 04:37:56.518940 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 04:37:56.525882 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 04:37:56.528994 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5036 04:37:56.532169 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5037 04:37:56.535469 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5038 04:37:56.542123 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5039 04:37:56.545706 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5040 04:37:56.548629 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 04:37:56.552133 ===================================
5042 04:37:56.555765 LPDDR4 DRAM CONFIGURATION
5043 04:37:56.558713 ===================================
5044 04:37:56.558788 EX_ROW_EN[0] = 0x0
5045 04:37:56.562198 EX_ROW_EN[1] = 0x0
5046 04:37:56.565224 LP4Y_EN = 0x0
5047 04:37:56.565327 WORK_FSP = 0x0
5048 04:37:56.568865 WL = 0x3
5049 04:37:56.568979 RL = 0x3
5050 04:37:56.571917 BL = 0x2
5051 04:37:56.571996 RPST = 0x0
5052 04:37:56.575486 RD_PRE = 0x0
5053 04:37:56.575568 WR_PRE = 0x1
5054 04:37:56.578561 WR_PST = 0x0
5055 04:37:56.578660 DBI_WR = 0x0
5056 04:37:56.582203 DBI_RD = 0x0
5057 04:37:56.582275 OTF = 0x1
5058 04:37:56.585396 ===================================
5059 04:37:56.588521 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5060 04:37:56.595157 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5061 04:37:56.598797 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 04:37:56.602148 ===================================
5063 04:37:56.605289 LPDDR4 DRAM CONFIGURATION
5064 04:37:56.608465 ===================================
5065 04:37:56.608624 EX_ROW_EN[0] = 0x10
5066 04:37:56.612037 EX_ROW_EN[1] = 0x0
5067 04:37:56.615268 LP4Y_EN = 0x0
5068 04:37:56.615385 WORK_FSP = 0x0
5069 04:37:56.618161 WL = 0x3
5070 04:37:56.618258 RL = 0x3
5071 04:37:56.621732 BL = 0x2
5072 04:37:56.621824 RPST = 0x0
5073 04:37:56.624768 RD_PRE = 0x0
5074 04:37:56.624867 WR_PRE = 0x1
5075 04:37:56.628283 WR_PST = 0x0
5076 04:37:56.628380 DBI_WR = 0x0
5077 04:37:56.631725 DBI_RD = 0x0
5078 04:37:56.631831 OTF = 0x1
5079 04:37:56.635188 ===================================
5080 04:37:56.641279 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5081 04:37:56.645806 nWR fixed to 30
5082 04:37:56.649506 [ModeRegInit_LP4] CH0 RK0
5083 04:37:56.649617 [ModeRegInit_LP4] CH0 RK1
5084 04:37:56.652635 [ModeRegInit_LP4] CH1 RK0
5085 04:37:56.655719 [ModeRegInit_LP4] CH1 RK1
5086 04:37:56.655829 match AC timing 9
5087 04:37:56.662388 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5088 04:37:56.665648 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5089 04:37:56.668937 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5090 04:37:56.675722 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5091 04:37:56.678964 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5092 04:37:56.679068 ==
5093 04:37:56.682151 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 04:37:56.685470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 04:37:56.685588 ==
5096 04:37:56.692414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5097 04:37:56.699026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5098 04:37:56.701954 [CA 0] Center 38 (8~69) winsize 62
5099 04:37:56.705319 [CA 1] Center 38 (7~69) winsize 63
5100 04:37:56.708592 [CA 2] Center 35 (5~66) winsize 62
5101 04:37:56.712216 [CA 3] Center 35 (5~65) winsize 61
5102 04:37:56.715248 [CA 4] Center 34 (4~65) winsize 62
5103 04:37:56.718680 [CA 5] Center 34 (4~64) winsize 61
5104 04:37:56.718781
5105 04:37:56.722060 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5106 04:37:56.722165
5107 04:37:56.725744 [CATrainingPosCal] consider 1 rank data
5108 04:37:56.728713 u2DelayCellTimex100 = 270/100 ps
5109 04:37:56.731831 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5110 04:37:56.735361 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5111 04:37:56.738383 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5112 04:37:56.742185 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5113 04:37:56.745501 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5114 04:37:56.751648 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5115 04:37:56.751760
5116 04:37:56.755101 CA PerBit enable=1, Macro0, CA PI delay=34
5117 04:37:56.755206
5118 04:37:56.758402 [CBTSetCACLKResult] CA Dly = 34
5119 04:37:56.758511 CS Dly: 6 (0~37)
5120 04:37:56.758605 ==
5121 04:37:56.762037 Dram Type= 6, Freq= 0, CH_0, rank 1
5122 04:37:56.765278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 04:37:56.768727 ==
5124 04:37:56.771612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5125 04:37:56.778305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5126 04:37:56.781503 [CA 0] Center 38 (8~69) winsize 62
5127 04:37:56.785147 [CA 1] Center 38 (8~69) winsize 62
5128 04:37:56.788239 [CA 2] Center 35 (5~66) winsize 62
5129 04:37:56.791341 [CA 3] Center 35 (5~66) winsize 62
5130 04:37:56.795086 [CA 4] Center 34 (3~65) winsize 63
5131 04:37:56.798205 [CA 5] Center 33 (3~64) winsize 62
5132 04:37:56.798311
5133 04:37:56.801153 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5134 04:37:56.801254
5135 04:37:56.804810 [CATrainingPosCal] consider 2 rank data
5136 04:37:56.808181 u2DelayCellTimex100 = 270/100 ps
5137 04:37:56.811494 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5138 04:37:56.814920 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5139 04:37:56.817937 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5140 04:37:56.824651 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5141 04:37:56.827981 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5142 04:37:56.831495 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5143 04:37:56.831608
5144 04:37:56.834509 CA PerBit enable=1, Macro0, CA PI delay=34
5145 04:37:56.834591
5146 04:37:56.837669 [CBTSetCACLKResult] CA Dly = 34
5147 04:37:56.837773 CS Dly: 6 (0~38)
5148 04:37:56.837865
5149 04:37:56.840875 ----->DramcWriteLeveling(PI) begin...
5150 04:37:56.840946 ==
5151 04:37:56.844214 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 04:37:56.850856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 04:37:56.850965 ==
5154 04:37:56.853947 Write leveling (Byte 0): 30 => 30
5155 04:37:56.857497 Write leveling (Byte 1): 28 => 28
5156 04:37:56.860861 DramcWriteLeveling(PI) end<-----
5157 04:37:56.860947
5158 04:37:56.861021 ==
5159 04:37:56.864198 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 04:37:56.867607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 04:37:56.867691 ==
5162 04:37:56.871237 [Gating] SW mode calibration
5163 04:37:56.877676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5164 04:37:56.880889 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5165 04:37:56.887687 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5166 04:37:56.890754 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5167 04:37:56.893811 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 04:37:56.900454 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 04:37:56.904075 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 04:37:56.907110 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 04:37:56.913797 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 04:37:56.917390 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5173 04:37:56.920271 0 15 0 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 0)
5174 04:37:56.927105 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5175 04:37:56.930308 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 04:37:56.933754 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 04:37:56.940543 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 04:37:56.943844 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 04:37:56.946891 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 04:37:56.953805 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
5181 04:37:56.956775 1 0 0 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
5182 04:37:56.960621 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5183 04:37:56.967047 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 04:37:56.970018 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 04:37:56.973616 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 04:37:56.980362 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 04:37:56.983107 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 04:37:56.986729 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 04:37:56.993220 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5190 04:37:56.996467 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5191 04:37:57.000137 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 04:37:57.006542 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 04:37:57.010294 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 04:37:57.013131 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 04:37:57.019578 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 04:37:57.023255 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 04:37:57.026180 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 04:37:57.032975 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 04:37:57.036166 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 04:37:57.040005 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 04:37:57.046033 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 04:37:57.049685 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 04:37:57.052960 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 04:37:57.059431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5205 04:37:57.062520 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5206 04:37:57.066374 Total UI for P1: 0, mck2ui 16
5207 04:37:57.069498 best dqsien dly found for B0: ( 1, 2, 28)
5208 04:37:57.072946 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5209 04:37:57.079460 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 04:37:57.079546 Total UI for P1: 0, mck2ui 16
5211 04:37:57.082560 best dqsien dly found for B1: ( 1, 3, 2)
5212 04:37:57.089149 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5213 04:37:57.092465 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5214 04:37:57.092587
5215 04:37:57.095794 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5216 04:37:57.099154 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5217 04:37:57.102571 [Gating] SW calibration Done
5218 04:37:57.102652 ==
5219 04:37:57.105880 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 04:37:57.108853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 04:37:57.108938 ==
5222 04:37:57.112583 RX Vref Scan: 0
5223 04:37:57.112666
5224 04:37:57.112733 RX Vref 0 -> 0, step: 1
5225 04:37:57.112796
5226 04:37:57.115583 RX Delay -80 -> 252, step: 8
5227 04:37:57.119251 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5228 04:37:57.122245 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5229 04:37:57.128937 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5230 04:37:57.132367 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5231 04:37:57.135337 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5232 04:37:57.138982 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5233 04:37:57.142290 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5234 04:37:57.145320 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5235 04:37:57.151985 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5236 04:37:57.155495 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5237 04:37:57.158554 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5238 04:37:57.162164 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5239 04:37:57.165255 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5240 04:37:57.172374 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5241 04:37:57.175314 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5242 04:37:57.178796 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5243 04:37:57.178873 ==
5244 04:37:57.182140 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 04:37:57.185408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 04:37:57.185484 ==
5247 04:37:57.188882 DQS Delay:
5248 04:37:57.188956 DQS0 = 0, DQS1 = 0
5249 04:37:57.192044 DQM Delay:
5250 04:37:57.192121 DQM0 = 94, DQM1 = 82
5251 04:37:57.192184 DQ Delay:
5252 04:37:57.195587 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5253 04:37:57.198881 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5254 04:37:57.202294 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5255 04:37:57.205201 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5256 04:37:57.205281
5257 04:37:57.208604
5258 04:37:57.208677 ==
5259 04:37:57.212200 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 04:37:57.215241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 04:37:57.215358 ==
5262 04:37:57.215474
5263 04:37:57.215561
5264 04:37:57.218407 TX Vref Scan disable
5265 04:37:57.218493 == TX Byte 0 ==
5266 04:37:57.225217 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5267 04:37:57.228342 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5268 04:37:57.228454 == TX Byte 1 ==
5269 04:37:57.235107 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5270 04:37:57.238109 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5271 04:37:57.238187 ==
5272 04:37:57.241987 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 04:37:57.245105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 04:37:57.245224 ==
5275 04:37:57.245317
5276 04:37:57.245413
5277 04:37:57.248371 TX Vref Scan disable
5278 04:37:57.252031 == TX Byte 0 ==
5279 04:37:57.255259 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5280 04:37:57.257989 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5281 04:37:57.261339 == TX Byte 1 ==
5282 04:37:57.264985 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5283 04:37:57.268507 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5284 04:37:57.268602
5285 04:37:57.271610 [DATLAT]
5286 04:37:57.271715 Freq=933, CH0 RK0
5287 04:37:57.271818
5288 04:37:57.274689 DATLAT Default: 0xd
5289 04:37:57.274794 0, 0xFFFF, sum = 0
5290 04:37:57.278337 1, 0xFFFF, sum = 0
5291 04:37:57.278443 2, 0xFFFF, sum = 0
5292 04:37:57.281503 3, 0xFFFF, sum = 0
5293 04:37:57.281582 4, 0xFFFF, sum = 0
5294 04:37:57.284618 5, 0xFFFF, sum = 0
5295 04:37:57.284715 6, 0xFFFF, sum = 0
5296 04:37:57.288097 7, 0xFFFF, sum = 0
5297 04:37:57.288203 8, 0xFFFF, sum = 0
5298 04:37:57.291037 9, 0xFFFF, sum = 0
5299 04:37:57.291161 10, 0x0, sum = 1
5300 04:37:57.294525 11, 0x0, sum = 2
5301 04:37:57.294636 12, 0x0, sum = 3
5302 04:37:57.298242 13, 0x0, sum = 4
5303 04:37:57.298365 best_step = 11
5304 04:37:57.298496
5305 04:37:57.298582 ==
5306 04:37:57.301212 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 04:37:57.307729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 04:37:57.307814 ==
5309 04:37:57.307942 RX Vref Scan: 1
5310 04:37:57.308044
5311 04:37:57.311192 RX Vref 0 -> 0, step: 1
5312 04:37:57.311293
5313 04:37:57.314305 RX Delay -69 -> 252, step: 4
5314 04:37:57.314452
5315 04:37:57.317735 Set Vref, RX VrefLevel [Byte0]: 61
5316 04:37:57.320912 [Byte1]: 51
5317 04:37:57.321019
5318 04:37:57.324524 Final RX Vref Byte 0 = 61 to rank0
5319 04:37:57.327676 Final RX Vref Byte 1 = 51 to rank0
5320 04:37:57.331437 Final RX Vref Byte 0 = 61 to rank1
5321 04:37:57.334534 Final RX Vref Byte 1 = 51 to rank1==
5322 04:37:57.337444 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 04:37:57.341181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 04:37:57.341294 ==
5325 04:37:57.344229 DQS Delay:
5326 04:37:57.344339 DQS0 = 0, DQS1 = 0
5327 04:37:57.344440 DQM Delay:
5328 04:37:57.347429 DQM0 = 95, DQM1 = 82
5329 04:37:57.347508 DQ Delay:
5330 04:37:57.351240 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5331 04:37:57.354249 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5332 04:37:57.357666 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =76
5333 04:37:57.360832 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
5334 04:37:57.360916
5335 04:37:57.360987
5336 04:37:57.370769 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 417 ps
5337 04:37:57.374422 CH0 RK0: MR19=505, MR18=F0F
5338 04:37:57.377637 CH0_RK0: MR19=0x505, MR18=0xF0F, DQSOSC=417, MR23=63, INC=62, DEC=41
5339 04:37:57.377726
5340 04:37:57.380652 ----->DramcWriteLeveling(PI) begin...
5341 04:37:57.384208 ==
5342 04:37:57.387406 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 04:37:57.391098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 04:37:57.391207 ==
5345 04:37:57.394157 Write leveling (Byte 0): 32 => 32
5346 04:37:57.397651 Write leveling (Byte 1): 30 => 30
5347 04:37:57.400388 DramcWriteLeveling(PI) end<-----
5348 04:37:57.400465
5349 04:37:57.400530 ==
5350 04:37:57.403926 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 04:37:57.407215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 04:37:57.407329 ==
5353 04:37:57.410960 [Gating] SW mode calibration
5354 04:37:57.417394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5355 04:37:57.423699 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5356 04:37:57.427309 0 14 0 | B1->B0 | 2626 3434 | 1 0 | (1 1) (0 0)
5357 04:37:57.430355 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 04:37:57.437093 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 04:37:57.440839 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 04:37:57.444024 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 04:37:57.447451 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 04:37:57.454060 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 04:37:57.457114 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
5364 04:37:57.460811 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5365 04:37:57.467459 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 04:37:57.470527 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 04:37:57.473643 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 04:37:57.480303 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 04:37:57.483648 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 04:37:57.487077 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 04:37:57.493576 0 15 28 | B1->B0 | 2525 3434 | 0 0 | (0 0) (1 1)
5372 04:37:57.496621 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5373 04:37:57.500204 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 04:37:57.506924 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 04:37:57.510063 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 04:37:57.513201 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 04:37:57.520151 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 04:37:57.523239 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 04:37:57.526532 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5380 04:37:57.533224 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5381 04:37:57.536706 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 04:37:57.539684 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 04:37:57.546297 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 04:37:57.550315 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 04:37:57.553155 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 04:37:57.560028 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 04:37:57.563072 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 04:37:57.566967 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 04:37:57.573101 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 04:37:57.576335 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 04:37:57.580194 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 04:37:57.586348 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 04:37:57.590014 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 04:37:57.593026 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 04:37:57.600080 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5396 04:37:57.603197 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 04:37:57.606281 Total UI for P1: 0, mck2ui 16
5398 04:37:57.609671 best dqsien dly found for B0: ( 1, 2, 28)
5399 04:37:57.613055 Total UI for P1: 0, mck2ui 16
5400 04:37:57.615962 best dqsien dly found for B1: ( 1, 2, 30)
5401 04:37:57.619514 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5402 04:37:57.622614 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5403 04:37:57.622691
5404 04:37:57.626384 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5405 04:37:57.629528 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5406 04:37:57.632578 [Gating] SW calibration Done
5407 04:37:57.632658 ==
5408 04:37:57.636084 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 04:37:57.639642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 04:37:57.639756 ==
5411 04:37:57.642583 RX Vref Scan: 0
5412 04:37:57.642699
5413 04:37:57.645839 RX Vref 0 -> 0, step: 1
5414 04:37:57.645948
5415 04:37:57.646063 RX Delay -80 -> 252, step: 8
5416 04:37:57.652448 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5417 04:37:57.655951 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5418 04:37:57.659446 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5419 04:37:57.662702 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5420 04:37:57.665793 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5421 04:37:57.672516 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5422 04:37:57.676257 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5423 04:37:57.679397 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5424 04:37:57.683007 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5425 04:37:57.686067 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5426 04:37:57.689171 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5427 04:37:57.696007 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5428 04:37:57.699174 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5429 04:37:57.702334 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5430 04:37:57.705732 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5431 04:37:57.709262 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5432 04:37:57.712199 ==
5433 04:37:57.715704 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 04:37:57.718933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 04:37:57.719020 ==
5436 04:37:57.719088 DQS Delay:
5437 04:37:57.722311 DQS0 = 0, DQS1 = 0
5438 04:37:57.722381 DQM Delay:
5439 04:37:57.725365 DQM0 = 90, DQM1 = 82
5440 04:37:57.725438 DQ Delay:
5441 04:37:57.728525 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5442 04:37:57.732531 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5443 04:37:57.735674 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5444 04:37:57.738545 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5445 04:37:57.738629
5446 04:37:57.738694
5447 04:37:57.738754 ==
5448 04:37:57.742201 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 04:37:57.745433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 04:37:57.745522 ==
5451 04:37:57.745588
5452 04:37:57.745649
5453 04:37:57.748501 TX Vref Scan disable
5454 04:37:57.752128 == TX Byte 0 ==
5455 04:37:57.755626 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5456 04:37:57.758739 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5457 04:37:57.761957 == TX Byte 1 ==
5458 04:37:57.765083 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5459 04:37:57.768480 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5460 04:37:57.768560 ==
5461 04:37:57.772050 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 04:37:57.778883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 04:37:57.779000 ==
5464 04:37:57.779099
5465 04:37:57.779198
5466 04:37:57.779298 TX Vref Scan disable
5467 04:37:57.782609 == TX Byte 0 ==
5468 04:37:57.785822 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5469 04:37:57.792226 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5470 04:37:57.792304 == TX Byte 1 ==
5471 04:37:57.795847 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5472 04:37:57.798970 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5473 04:37:57.802709
5474 04:37:57.802791 [DATLAT]
5475 04:37:57.802857 Freq=933, CH0 RK1
5476 04:37:57.802919
5477 04:37:57.805829 DATLAT Default: 0xb
5478 04:37:57.805905 0, 0xFFFF, sum = 0
5479 04:37:57.809657 1, 0xFFFF, sum = 0
5480 04:37:57.809742 2, 0xFFFF, sum = 0
5481 04:37:57.812493 3, 0xFFFF, sum = 0
5482 04:37:57.812577 4, 0xFFFF, sum = 0
5483 04:37:57.815587 5, 0xFFFF, sum = 0
5484 04:37:57.819118 6, 0xFFFF, sum = 0
5485 04:37:57.819230 7, 0xFFFF, sum = 0
5486 04:37:57.822349 8, 0xFFFF, sum = 0
5487 04:37:57.822459 9, 0xFFFF, sum = 0
5488 04:37:57.826074 10, 0x0, sum = 1
5489 04:37:57.826161 11, 0x0, sum = 2
5490 04:37:57.828819 12, 0x0, sum = 3
5491 04:37:57.828916 13, 0x0, sum = 4
5492 04:37:57.828983 best_step = 11
5493 04:37:57.829053
5494 04:37:57.832136 ==
5495 04:37:57.835324 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 04:37:57.838839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 04:37:57.838917 ==
5498 04:37:57.838980 RX Vref Scan: 0
5499 04:37:57.839047
5500 04:37:57.842661 RX Vref 0 -> 0, step: 1
5501 04:37:57.842740
5502 04:37:57.845279 RX Delay -77 -> 252, step: 4
5503 04:37:57.848996 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5504 04:37:57.855621 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5505 04:37:57.858739 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5506 04:37:57.861844 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5507 04:37:57.865634 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5508 04:37:57.868854 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5509 04:37:57.875232 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5510 04:37:57.878584 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5511 04:37:57.881593 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5512 04:37:57.885284 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5513 04:37:57.888294 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5514 04:37:57.895059 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5515 04:37:57.898136 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5516 04:37:57.901790 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5517 04:37:57.904957 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5518 04:37:57.908086 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5519 04:37:57.908164 ==
5520 04:37:57.911769 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 04:37:57.918562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 04:37:57.918640 ==
5523 04:37:57.918704 DQS Delay:
5524 04:37:57.921352 DQS0 = 0, DQS1 = 0
5525 04:37:57.921431 DQM Delay:
5526 04:37:57.921494 DQM0 = 92, DQM1 = 84
5527 04:37:57.925136 DQ Delay:
5528 04:37:57.928181 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5529 04:37:57.931259 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5530 04:37:57.935013 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =76
5531 04:37:57.938212 DQ12 =88, DQ13 =92, DQ14 =94, DQ15 =92
5532 04:37:57.938292
5533 04:37:57.938358
5534 04:37:57.945005 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5535 04:37:57.947809 CH0 RK1: MR19=505, MR18=2E10
5536 04:37:57.954519 CH0_RK1: MR19=0x505, MR18=0x2E10, DQSOSC=407, MR23=63, INC=65, DEC=43
5537 04:37:57.957856 [RxdqsGatingPostProcess] freq 933
5538 04:37:57.961034 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5539 04:37:57.964228 best DQS0 dly(2T, 0.5T) = (0, 10)
5540 04:37:57.967537 best DQS1 dly(2T, 0.5T) = (0, 11)
5541 04:37:57.971115 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5542 04:37:57.974743 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5543 04:37:57.977602 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 04:37:57.980716 best DQS1 dly(2T, 0.5T) = (0, 10)
5545 04:37:57.984308 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 04:37:57.988049 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5547 04:37:57.991088 Pre-setting of DQS Precalculation
5548 04:37:57.997477 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5549 04:37:57.997607 ==
5550 04:37:58.000870 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 04:37:58.003898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 04:37:58.003982 ==
5553 04:37:58.010656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5554 04:37:58.013845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5555 04:37:58.018388 [CA 0] Center 37 (7~67) winsize 61
5556 04:37:58.021592 [CA 1] Center 37 (7~67) winsize 61
5557 04:37:58.024678 [CA 2] Center 35 (5~65) winsize 61
5558 04:37:58.027875 [CA 3] Center 34 (5~64) winsize 60
5559 04:37:58.031547 [CA 4] Center 35 (5~65) winsize 61
5560 04:37:58.034798 [CA 5] Center 34 (4~64) winsize 61
5561 04:37:58.034900
5562 04:37:58.037832 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5563 04:37:58.037942
5564 04:37:58.041740 [CATrainingPosCal] consider 1 rank data
5565 04:37:58.044961 u2DelayCellTimex100 = 270/100 ps
5566 04:37:58.047784 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5567 04:37:58.054676 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5568 04:37:58.057499 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5569 04:37:58.061427 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5570 04:37:58.064470 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5571 04:37:58.067468 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5572 04:37:58.067546
5573 04:37:58.070753 CA PerBit enable=1, Macro0, CA PI delay=34
5574 04:37:58.070856
5575 04:37:58.074589 [CBTSetCACLKResult] CA Dly = 34
5576 04:37:58.074681 CS Dly: 6 (0~37)
5577 04:37:58.077927 ==
5578 04:37:58.081201 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 04:37:58.084425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 04:37:58.084504 ==
5581 04:37:58.087647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5582 04:37:58.094143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5583 04:37:58.098031 [CA 0] Center 38 (8~68) winsize 61
5584 04:37:58.101431 [CA 1] Center 37 (7~68) winsize 62
5585 04:37:58.104776 [CA 2] Center 35 (5~65) winsize 61
5586 04:37:58.107873 [CA 3] Center 34 (4~64) winsize 61
5587 04:37:58.111179 [CA 4] Center 35 (5~65) winsize 61
5588 04:37:58.114663 [CA 5] Center 34 (4~64) winsize 61
5589 04:37:58.114773
5590 04:37:58.117856 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5591 04:37:58.117959
5592 04:37:58.121053 [CATrainingPosCal] consider 2 rank data
5593 04:37:58.124299 u2DelayCellTimex100 = 270/100 ps
5594 04:37:58.127807 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5595 04:37:58.134118 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5596 04:37:58.137792 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5597 04:37:58.141182 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5598 04:37:58.144305 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5599 04:37:58.147459 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5600 04:37:58.147547
5601 04:37:58.151161 CA PerBit enable=1, Macro0, CA PI delay=34
5602 04:37:58.151271
5603 04:37:58.154118 [CBTSetCACLKResult] CA Dly = 34
5604 04:37:58.154221 CS Dly: 7 (0~39)
5605 04:37:58.157645
5606 04:37:58.161111 ----->DramcWriteLeveling(PI) begin...
5607 04:37:58.161217 ==
5608 04:37:58.164565 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 04:37:58.167724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 04:37:58.167803 ==
5611 04:37:58.170801 Write leveling (Byte 0): 24 => 24
5612 04:37:58.174414 Write leveling (Byte 1): 28 => 28
5613 04:37:58.177296 DramcWriteLeveling(PI) end<-----
5614 04:37:58.177374
5615 04:37:58.177439 ==
5616 04:37:58.180547 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 04:37:58.184108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 04:37:58.184187 ==
5619 04:37:58.187413 [Gating] SW mode calibration
5620 04:37:58.194598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5621 04:37:58.200944 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5622 04:37:58.204202 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5623 04:37:58.207161 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 04:37:58.213819 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 04:37:58.217573 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 04:37:58.220331 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 04:37:58.226918 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 04:37:58.230603 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 04:37:58.233828 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
5630 04:37:58.240161 0 15 0 | B1->B0 | 2c2c 2929 | 1 0 | (1 0) (1 0)
5631 04:37:58.243998 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 04:37:58.247016 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 04:37:58.253590 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 04:37:58.257031 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 04:37:58.259864 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 04:37:58.266504 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 04:37:58.270064 0 15 28 | B1->B0 | 2b2b 3131 | 1 1 | (0 0) (0 0)
5638 04:37:58.273642 1 0 0 | B1->B0 | 4444 4343 | 0 0 | (1 1) (0 0)
5639 04:37:58.280103 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 04:37:58.283116 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 04:37:58.286860 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 04:37:58.293594 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 04:37:58.297022 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 04:37:58.300309 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 04:37:58.303335 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 04:37:58.309996 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5647 04:37:58.313609 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 04:37:58.316573 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 04:37:58.323112 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 04:37:58.326559 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 04:37:58.329901 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 04:37:58.336803 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 04:37:58.340042 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 04:37:58.343185 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 04:37:58.349592 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 04:37:58.352695 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 04:37:58.356253 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 04:37:58.362984 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 04:37:58.366549 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 04:37:58.369483 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 04:37:58.376138 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5662 04:37:58.379714 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5663 04:37:58.383017 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 04:37:58.386102 Total UI for P1: 0, mck2ui 16
5665 04:37:58.389747 best dqsien dly found for B0: ( 1, 2, 30)
5666 04:37:58.392984 Total UI for P1: 0, mck2ui 16
5667 04:37:58.395936 best dqsien dly found for B1: ( 1, 2, 30)
5668 04:37:58.399750 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5669 04:37:58.402731 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5670 04:37:58.402811
5671 04:37:58.409506 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5672 04:37:58.412978 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5673 04:37:58.413057 [Gating] SW calibration Done
5674 04:37:58.416168 ==
5675 04:37:58.419205 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 04:37:58.422791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 04:37:58.422894 ==
5678 04:37:58.422987 RX Vref Scan: 0
5679 04:37:58.423082
5680 04:37:58.426117 RX Vref 0 -> 0, step: 1
5681 04:37:58.426204
5682 04:37:58.429463 RX Delay -80 -> 252, step: 8
5683 04:37:58.432308 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5684 04:37:58.435813 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5685 04:37:58.442895 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5686 04:37:58.445759 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5687 04:37:58.449091 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5688 04:37:58.452472 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5689 04:37:58.455643 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5690 04:37:58.459457 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5691 04:37:58.465687 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5692 04:37:58.469469 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5693 04:37:58.472604 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5694 04:37:58.475783 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5695 04:37:58.478873 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5696 04:37:58.482692 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5697 04:37:58.488999 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5698 04:37:58.492361 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5699 04:37:58.492470 ==
5700 04:37:58.496021 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 04:37:58.498915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 04:37:58.499026 ==
5703 04:37:58.502114 DQS Delay:
5704 04:37:58.502200 DQS0 = 0, DQS1 = 0
5705 04:37:58.502267 DQM Delay:
5706 04:37:58.505635 DQM0 = 94, DQM1 = 86
5707 04:37:58.505718 DQ Delay:
5708 04:37:58.508594 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5709 04:37:58.512136 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5710 04:37:58.515250 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5711 04:37:58.518883 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5712 04:37:58.518992
5713 04:37:58.519086
5714 04:37:58.521965 ==
5715 04:37:58.522048 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 04:37:58.528369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 04:37:58.528453 ==
5718 04:37:58.528520
5719 04:37:58.528580
5720 04:37:58.532094 TX Vref Scan disable
5721 04:37:58.532177 == TX Byte 0 ==
5722 04:37:58.535581 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5723 04:37:58.541593 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5724 04:37:58.541713 == TX Byte 1 ==
5725 04:37:58.545158 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5726 04:37:58.551761 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5727 04:37:58.551842 ==
5728 04:37:58.555317 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 04:37:58.558391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 04:37:58.558477 ==
5731 04:37:58.558544
5732 04:37:58.558606
5733 04:37:58.562011 TX Vref Scan disable
5734 04:37:58.565036 == TX Byte 0 ==
5735 04:37:58.568580 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5736 04:37:58.571687 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5737 04:37:58.575098 == TX Byte 1 ==
5738 04:37:58.578182 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5739 04:37:58.581596 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5740 04:37:58.581675
5741 04:37:58.585256 [DATLAT]
5742 04:37:58.585340 Freq=933, CH1 RK0
5743 04:37:58.585406
5744 04:37:58.588280 DATLAT Default: 0xd
5745 04:37:58.588355 0, 0xFFFF, sum = 0
5746 04:37:58.591325 1, 0xFFFF, sum = 0
5747 04:37:58.591412 2, 0xFFFF, sum = 0
5748 04:37:58.595052 3, 0xFFFF, sum = 0
5749 04:37:58.595170 4, 0xFFFF, sum = 0
5750 04:37:58.598164 5, 0xFFFF, sum = 0
5751 04:37:58.598275 6, 0xFFFF, sum = 0
5752 04:37:58.601673 7, 0xFFFF, sum = 0
5753 04:37:58.601752 8, 0xFFFF, sum = 0
5754 04:37:58.604797 9, 0xFFFF, sum = 0
5755 04:37:58.604876 10, 0x0, sum = 1
5756 04:37:58.608050 11, 0x0, sum = 2
5757 04:37:58.608136 12, 0x0, sum = 3
5758 04:37:58.611755 13, 0x0, sum = 4
5759 04:37:58.611832 best_step = 11
5760 04:37:58.611896
5761 04:37:58.611997 ==
5762 04:37:58.614662 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 04:37:58.618166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 04:37:58.621475 ==
5765 04:37:58.621559 RX Vref Scan: 1
5766 04:37:58.621624
5767 04:37:58.624804 RX Vref 0 -> 0, step: 1
5768 04:37:58.624889
5769 04:37:58.628056 RX Delay -69 -> 252, step: 4
5770 04:37:58.628133
5771 04:37:58.631120 Set Vref, RX VrefLevel [Byte0]: 53
5772 04:37:58.634788 [Byte1]: 51
5773 04:37:58.634864
5774 04:37:58.637930 Final RX Vref Byte 0 = 53 to rank0
5775 04:37:58.640962 Final RX Vref Byte 1 = 51 to rank0
5776 04:37:58.644716 Final RX Vref Byte 0 = 53 to rank1
5777 04:37:58.647686 Final RX Vref Byte 1 = 51 to rank1==
5778 04:37:58.651457 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 04:37:58.654523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 04:37:58.654601 ==
5781 04:37:58.658052 DQS Delay:
5782 04:37:58.658130 DQS0 = 0, DQS1 = 0
5783 04:37:58.658194 DQM Delay:
5784 04:37:58.661100 DQM0 = 96, DQM1 = 88
5785 04:37:58.661178 DQ Delay:
5786 04:37:58.664740 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =94
5787 04:37:58.667776 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5788 04:37:58.671553 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =82
5789 04:37:58.674431 DQ12 =98, DQ13 =94, DQ14 =94, DQ15 =94
5790 04:37:58.674513
5791 04:37:58.674578
5792 04:37:58.684281 [DQSOSCAuto] RK0, (LSB)MR18= 0x109, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 421 ps
5793 04:37:58.684367 CH1 RK0: MR19=505, MR18=109
5794 04:37:58.691173 CH1_RK0: MR19=0x505, MR18=0x109, DQSOSC=419, MR23=63, INC=61, DEC=41
5795 04:37:58.691258
5796 04:37:58.694625 ----->DramcWriteLeveling(PI) begin...
5797 04:37:58.694699 ==
5798 04:37:58.697770 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 04:37:58.704183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 04:37:58.704264 ==
5801 04:37:58.707658 Write leveling (Byte 0): 26 => 26
5802 04:37:58.710501 Write leveling (Byte 1): 27 => 27
5803 04:37:58.714274 DramcWriteLeveling(PI) end<-----
5804 04:37:58.714360
5805 04:37:58.714424 ==
5806 04:37:58.717261 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 04:37:58.720998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 04:37:58.721077 ==
5809 04:37:58.724042 [Gating] SW mode calibration
5810 04:37:58.730485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5811 04:37:58.734273 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5812 04:37:58.740361 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 04:37:58.744026 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 04:37:58.747134 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 04:37:58.753632 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 04:37:58.757234 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 04:37:58.760254 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 04:37:58.766918 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
5819 04:37:58.770172 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
5820 04:37:58.773521 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5821 04:37:58.780225 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 04:37:58.783311 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 04:37:58.786658 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 04:37:58.793558 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 04:37:58.796682 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 04:37:58.800293 0 15 24 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
5827 04:37:58.806841 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5828 04:37:58.809992 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 04:37:58.813610 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 04:37:58.820232 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 04:37:58.823281 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 04:37:58.826546 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 04:37:58.833201 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 04:37:58.836809 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5835 04:37:58.839717 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5836 04:37:58.846561 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 04:37:58.850282 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 04:37:58.853205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 04:37:58.860082 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 04:37:58.863216 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 04:37:58.866788 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 04:37:58.872995 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 04:37:58.876671 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 04:37:58.879727 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 04:37:58.886378 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 04:37:58.889458 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 04:37:58.893161 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 04:37:58.899577 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 04:37:58.903166 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 04:37:58.906210 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5851 04:37:58.913006 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5852 04:37:58.913088 Total UI for P1: 0, mck2ui 16
5853 04:37:58.915982 best dqsien dly found for B0: ( 1, 2, 24)
5854 04:37:58.923224 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 04:37:58.926053 Total UI for P1: 0, mck2ui 16
5856 04:37:58.929705 best dqsien dly found for B1: ( 1, 2, 28)
5857 04:37:58.932910 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5858 04:37:58.936202 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5859 04:37:58.936281
5860 04:37:58.939673 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5861 04:37:58.942755 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5862 04:37:58.946093 [Gating] SW calibration Done
5863 04:37:58.946179 ==
5864 04:37:58.949636 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 04:37:58.952602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 04:37:58.952700 ==
5867 04:37:58.956121 RX Vref Scan: 0
5868 04:37:58.956194
5869 04:37:58.959488 RX Vref 0 -> 0, step: 1
5870 04:37:58.959579
5871 04:37:58.959642 RX Delay -80 -> 252, step: 8
5872 04:37:58.966106 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5873 04:37:58.969228 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5874 04:37:58.972652 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5875 04:37:58.976099 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5876 04:37:58.979082 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5877 04:37:58.985956 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5878 04:37:58.989059 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5879 04:37:58.992698 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5880 04:37:58.995786 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5881 04:37:58.999106 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5882 04:37:59.005570 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5883 04:37:59.009271 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5884 04:37:59.012286 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5885 04:37:59.015875 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5886 04:37:59.018892 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5887 04:37:59.022069 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5888 04:37:59.025697 ==
5889 04:37:59.028890 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 04:37:59.032320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 04:37:59.032404 ==
5892 04:37:59.032470 DQS Delay:
5893 04:37:59.035594 DQS0 = 0, DQS1 = 0
5894 04:37:59.035677 DQM Delay:
5895 04:37:59.038603 DQM0 = 91, DQM1 = 88
5896 04:37:59.038679 DQ Delay:
5897 04:37:59.042485 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =87
5898 04:37:59.045636 DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =87
5899 04:37:59.048651 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5900 04:37:59.052101 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5901 04:37:59.052185
5902 04:37:59.052251
5903 04:37:59.052313 ==
5904 04:37:59.055200 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 04:37:59.059091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 04:37:59.059206 ==
5907 04:37:59.059312
5908 04:37:59.059408
5909 04:37:59.062043 TX Vref Scan disable
5910 04:37:59.065513 == TX Byte 0 ==
5911 04:37:59.068627 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5912 04:37:59.072092 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5913 04:37:59.075278 == TX Byte 1 ==
5914 04:37:59.078405 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5915 04:37:59.081757 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5916 04:37:59.081834 ==
5917 04:37:59.085272 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 04:37:59.091795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 04:37:59.091905 ==
5920 04:37:59.092009
5921 04:37:59.092099
5922 04:37:59.092196 TX Vref Scan disable
5923 04:37:59.095533 == TX Byte 0 ==
5924 04:37:59.098656 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5925 04:37:59.105388 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5926 04:37:59.105502 == TX Byte 1 ==
5927 04:37:59.108541 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5928 04:37:59.115266 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5929 04:37:59.115383
5930 04:37:59.115452 [DATLAT]
5931 04:37:59.115515 Freq=933, CH1 RK1
5932 04:37:59.115576
5933 04:37:59.118459 DATLAT Default: 0xb
5934 04:37:59.118573 0, 0xFFFF, sum = 0
5935 04:37:59.121951 1, 0xFFFF, sum = 0
5936 04:37:59.122036 2, 0xFFFF, sum = 0
5937 04:37:59.125713 3, 0xFFFF, sum = 0
5938 04:37:59.128800 4, 0xFFFF, sum = 0
5939 04:37:59.128890 5, 0xFFFF, sum = 0
5940 04:37:59.131895 6, 0xFFFF, sum = 0
5941 04:37:59.131981 7, 0xFFFF, sum = 0
5942 04:37:59.135474 8, 0xFFFF, sum = 0
5943 04:37:59.135561 9, 0xFFFF, sum = 0
5944 04:37:59.138435 10, 0x0, sum = 1
5945 04:37:59.138519 11, 0x0, sum = 2
5946 04:37:59.142457 12, 0x0, sum = 3
5947 04:37:59.142551 13, 0x0, sum = 4
5948 04:37:59.142622 best_step = 11
5949 04:37:59.142684
5950 04:37:59.145267 ==
5951 04:37:59.148378 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 04:37:59.152209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 04:37:59.152292 ==
5954 04:37:59.152358 RX Vref Scan: 0
5955 04:37:59.152421
5956 04:37:59.155258 RX Vref 0 -> 0, step: 1
5957 04:37:59.155388
5958 04:37:59.158876 RX Delay -69 -> 252, step: 4
5959 04:37:59.162153 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5960 04:37:59.168679 iDelay=203, Bit 1, Center 88 (-9 ~ 186) 196
5961 04:37:59.171880 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5962 04:37:59.175002 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5963 04:37:59.178846 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5964 04:37:59.181802 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5965 04:37:59.188551 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5966 04:37:59.191730 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5967 04:37:59.195167 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5968 04:37:59.198603 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5969 04:37:59.201497 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5970 04:37:59.204983 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5971 04:37:59.211705 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5972 04:37:59.214630 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5973 04:37:59.218311 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5974 04:37:59.221420 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5975 04:37:59.221497 ==
5976 04:37:59.224716 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 04:37:59.231256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 04:37:59.231365 ==
5979 04:37:59.231443 DQS Delay:
5980 04:37:59.231504 DQS0 = 0, DQS1 = 0
5981 04:37:59.234925 DQM Delay:
5982 04:37:59.235025 DQM0 = 92, DQM1 = 91
5983 04:37:59.238010 DQ Delay:
5984 04:37:59.241610 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =88
5985 04:37:59.244644 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5986 04:37:59.247853 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
5987 04:37:59.251635 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =98
5988 04:37:59.251711
5989 04:37:59.251775
5990 04:37:59.257916 [DQSOSCAuto] RK1, (LSB)MR18= 0x1125, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5991 04:37:59.260929 CH1 RK1: MR19=505, MR18=1125
5992 04:37:59.267756 CH1_RK1: MR19=0x505, MR18=0x1125, DQSOSC=410, MR23=63, INC=64, DEC=42
5993 04:37:59.271411 [RxdqsGatingPostProcess] freq 933
5994 04:37:59.274579 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5995 04:37:59.277730 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 04:37:59.280929 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 04:37:59.283972 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 04:37:59.287636 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 04:37:59.290715 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 04:37:59.294273 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 04:37:59.297230 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 04:37:59.300824 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 04:37:59.303708 Pre-setting of DQS Precalculation
6004 04:37:59.307506 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6005 04:37:59.317378 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6006 04:37:59.324064 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6007 04:37:59.324169
6008 04:37:59.324237
6009 04:37:59.326880 [Calibration Summary] 1866 Mbps
6010 04:37:59.326964 CH 0, Rank 0
6011 04:37:59.330227 SW Impedance : PASS
6012 04:37:59.330336 DUTY Scan : NO K
6013 04:37:59.333752 ZQ Calibration : PASS
6014 04:37:59.337345 Jitter Meter : NO K
6015 04:37:59.337437 CBT Training : PASS
6016 04:37:59.340823 Write leveling : PASS
6017 04:37:59.343673 RX DQS gating : PASS
6018 04:37:59.343799 RX DQ/DQS(RDDQC) : PASS
6019 04:37:59.347135 TX DQ/DQS : PASS
6020 04:37:59.349893 RX DATLAT : PASS
6021 04:37:59.349997 RX DQ/DQS(Engine): PASS
6022 04:37:59.353621 TX OE : NO K
6023 04:37:59.353723 All Pass.
6024 04:37:59.353819
6025 04:37:59.357085 CH 0, Rank 1
6026 04:37:59.357195 SW Impedance : PASS
6027 04:37:59.360037 DUTY Scan : NO K
6028 04:37:59.363855 ZQ Calibration : PASS
6029 04:37:59.363939 Jitter Meter : NO K
6030 04:37:59.366924 CBT Training : PASS
6031 04:37:59.370554 Write leveling : PASS
6032 04:37:59.370637 RX DQS gating : PASS
6033 04:37:59.373705 RX DQ/DQS(RDDQC) : PASS
6034 04:37:59.376707 TX DQ/DQS : PASS
6035 04:37:59.376790 RX DATLAT : PASS
6036 04:37:59.380451 RX DQ/DQS(Engine): PASS
6037 04:37:59.380535 TX OE : NO K
6038 04:37:59.383528 All Pass.
6039 04:37:59.383611
6040 04:37:59.383677 CH 1, Rank 0
6041 04:37:59.386580 SW Impedance : PASS
6042 04:37:59.386662 DUTY Scan : NO K
6043 04:37:59.390172 ZQ Calibration : PASS
6044 04:37:59.393274 Jitter Meter : NO K
6045 04:37:59.393357 CBT Training : PASS
6046 04:37:59.396862 Write leveling : PASS
6047 04:37:59.399949 RX DQS gating : PASS
6048 04:37:59.400031 RX DQ/DQS(RDDQC) : PASS
6049 04:37:59.403392 TX DQ/DQS : PASS
6050 04:37:59.406495 RX DATLAT : PASS
6051 04:37:59.406578 RX DQ/DQS(Engine): PASS
6052 04:37:59.409590 TX OE : NO K
6053 04:37:59.409680 All Pass.
6054 04:37:59.409748
6055 04:37:59.413381 CH 1, Rank 1
6056 04:37:59.413464 SW Impedance : PASS
6057 04:37:59.416492 DUTY Scan : NO K
6058 04:37:59.419773 ZQ Calibration : PASS
6059 04:37:59.419870 Jitter Meter : NO K
6060 04:37:59.422857 CBT Training : PASS
6061 04:37:59.426546 Write leveling : PASS
6062 04:37:59.426655 RX DQS gating : PASS
6063 04:37:59.429604 RX DQ/DQS(RDDQC) : PASS
6064 04:37:59.432778 TX DQ/DQS : PASS
6065 04:37:59.432864 RX DATLAT : PASS
6066 04:37:59.436283 RX DQ/DQS(Engine): PASS
6067 04:37:59.439958 TX OE : NO K
6068 04:37:59.440044 All Pass.
6069 04:37:59.440111
6070 04:37:59.440173 DramC Write-DBI off
6071 04:37:59.442907 PER_BANK_REFRESH: Hybrid Mode
6072 04:37:59.446191 TX_TRACKING: ON
6073 04:37:59.452585 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6074 04:37:59.456315 [FAST_K] Save calibration result to emmc
6075 04:37:59.462519 dramc_set_vcore_voltage set vcore to 650000
6076 04:37:59.462603 Read voltage for 400, 6
6077 04:37:59.465885 Vio18 = 0
6078 04:37:59.466003 Vcore = 650000
6079 04:37:59.466098 Vdram = 0
6080 04:37:59.469433 Vddq = 0
6081 04:37:59.469531 Vmddr = 0
6082 04:37:59.472981 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6083 04:37:59.479132 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6084 04:37:59.482616 MEM_TYPE=3, freq_sel=20
6085 04:37:59.485793 sv_algorithm_assistance_LP4_800
6086 04:37:59.489191 ============ PULL DRAM RESETB DOWN ============
6087 04:37:59.492217 ========== PULL DRAM RESETB DOWN end =========
6088 04:37:59.495320 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6089 04:37:59.499182 ===================================
6090 04:37:59.502290 LPDDR4 DRAM CONFIGURATION
6091 04:37:59.505775 ===================================
6092 04:37:59.508786 EX_ROW_EN[0] = 0x0
6093 04:37:59.508862 EX_ROW_EN[1] = 0x0
6094 04:37:59.512199 LP4Y_EN = 0x0
6095 04:37:59.512284 WORK_FSP = 0x0
6096 04:37:59.515850 WL = 0x2
6097 04:37:59.515929 RL = 0x2
6098 04:37:59.518971 BL = 0x2
6099 04:37:59.519073 RPST = 0x0
6100 04:37:59.522086 RD_PRE = 0x0
6101 04:37:59.525800 WR_PRE = 0x1
6102 04:37:59.525885 WR_PST = 0x0
6103 04:37:59.528873 DBI_WR = 0x0
6104 04:37:59.528944 DBI_RD = 0x0
6105 04:37:59.532065 OTF = 0x1
6106 04:37:59.535389 ===================================
6107 04:37:59.539086 ===================================
6108 04:37:59.539194 ANA top config
6109 04:37:59.542052 ===================================
6110 04:37:59.545266 DLL_ASYNC_EN = 0
6111 04:37:59.548735 ALL_SLAVE_EN = 1
6112 04:37:59.548839 NEW_RANK_MODE = 1
6113 04:37:59.551641 DLL_IDLE_MODE = 1
6114 04:37:59.555189 LP45_APHY_COMB_EN = 1
6115 04:37:59.558220 TX_ODT_DIS = 1
6116 04:37:59.562013 NEW_8X_MODE = 1
6117 04:37:59.565290 ===================================
6118 04:37:59.568081 ===================================
6119 04:37:59.568183 data_rate = 800
6120 04:37:59.571583 CKR = 1
6121 04:37:59.574620 DQ_P2S_RATIO = 4
6122 04:37:59.578111 ===================================
6123 04:37:59.581364 CA_P2S_RATIO = 4
6124 04:37:59.585097 DQ_CA_OPEN = 0
6125 04:37:59.588041 DQ_SEMI_OPEN = 1
6126 04:37:59.588117 CA_SEMI_OPEN = 1
6127 04:37:59.591353 CA_FULL_RATE = 0
6128 04:37:59.594802 DQ_CKDIV4_EN = 0
6129 04:37:59.598253 CA_CKDIV4_EN = 1
6130 04:37:59.601248 CA_PREDIV_EN = 0
6131 04:37:59.604822 PH8_DLY = 0
6132 04:37:59.604929 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6133 04:37:59.607791 DQ_AAMCK_DIV = 0
6134 04:37:59.611329 CA_AAMCK_DIV = 0
6135 04:37:59.614294 CA_ADMCK_DIV = 4
6136 04:37:59.617758 DQ_TRACK_CA_EN = 0
6137 04:37:59.620803 CA_PICK = 800
6138 04:37:59.624378 CA_MCKIO = 400
6139 04:37:59.624486 MCKIO_SEMI = 400
6140 04:37:59.627596 PLL_FREQ = 3016
6141 04:37:59.631240 DQ_UI_PI_RATIO = 32
6142 04:37:59.634292 CA_UI_PI_RATIO = 32
6143 04:37:59.637862 ===================================
6144 04:37:59.640921 ===================================
6145 04:37:59.643983 memory_type:LPDDR4
6146 04:37:59.644068 GP_NUM : 10
6147 04:37:59.647892 SRAM_EN : 1
6148 04:37:59.650802 MD32_EN : 0
6149 04:37:59.654595 ===================================
6150 04:37:59.654688 [ANA_INIT] >>>>>>>>>>>>>>
6151 04:37:59.657439 <<<<<< [CONFIGURE PHASE]: ANA_TX
6152 04:37:59.660440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6153 04:37:59.664033 ===================================
6154 04:37:59.667509 data_rate = 800,PCW = 0X7400
6155 04:37:59.670993 ===================================
6156 04:37:59.673824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6157 04:37:59.680376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 04:37:59.690977 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 04:37:59.697057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6160 04:37:59.700713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6161 04:37:59.704126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6162 04:37:59.704211 [ANA_INIT] flow start
6163 04:37:59.707357 [ANA_INIT] PLL >>>>>>>>
6164 04:37:59.710448 [ANA_INIT] PLL <<<<<<<<
6165 04:37:59.710557 [ANA_INIT] MIDPI >>>>>>>>
6166 04:37:59.713713 [ANA_INIT] MIDPI <<<<<<<<
6167 04:37:59.717217 [ANA_INIT] DLL >>>>>>>>
6168 04:37:59.717300 [ANA_INIT] flow end
6169 04:37:59.723632 ============ LP4 DIFF to SE enter ============
6170 04:37:59.727149 ============ LP4 DIFF to SE exit ============
6171 04:37:59.730267 [ANA_INIT] <<<<<<<<<<<<<
6172 04:37:59.733554 [Flow] Enable top DCM control >>>>>
6173 04:37:59.736798 [Flow] Enable top DCM control <<<<<
6174 04:37:59.736881 Enable DLL master slave shuffle
6175 04:37:59.743279 ==============================================================
6176 04:37:59.747126 Gating Mode config
6177 04:37:59.750280 ==============================================================
6178 04:37:59.753338 Config description:
6179 04:37:59.763341 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6180 04:37:59.770053 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6181 04:37:59.773316 SELPH_MODE 0: By rank 1: By Phase
6182 04:37:59.779522 ==============================================================
6183 04:37:59.783151 GAT_TRACK_EN = 0
6184 04:37:59.786351 RX_GATING_MODE = 2
6185 04:37:59.790041 RX_GATING_TRACK_MODE = 2
6186 04:37:59.793036 SELPH_MODE = 1
6187 04:37:59.796108 PICG_EARLY_EN = 1
6188 04:37:59.796192 VALID_LAT_VALUE = 1
6189 04:37:59.803185 ==============================================================
6190 04:37:59.806303 Enter into Gating configuration >>>>
6191 04:37:59.809514 Exit from Gating configuration <<<<
6192 04:37:59.812609 Enter into DVFS_PRE_config >>>>>
6193 04:37:59.822967 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6194 04:37:59.826323 Exit from DVFS_PRE_config <<<<<
6195 04:37:59.829282 Enter into PICG configuration >>>>
6196 04:37:59.832897 Exit from PICG configuration <<<<
6197 04:37:59.836213 [RX_INPUT] configuration >>>>>
6198 04:37:59.839458 [RX_INPUT] configuration <<<<<
6199 04:37:59.846087 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6200 04:37:59.849219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6201 04:37:59.856202 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 04:37:59.862212 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 04:37:59.869347 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 04:37:59.875854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 04:37:59.878934 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6206 04:37:59.882077 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6207 04:37:59.885611 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6208 04:37:59.892176 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6209 04:37:59.895641 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6210 04:37:59.898699 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 04:37:59.902423 ===================================
6212 04:37:59.905524 LPDDR4 DRAM CONFIGURATION
6213 04:37:59.909312 ===================================
6214 04:37:59.909423 EX_ROW_EN[0] = 0x0
6215 04:37:59.912244 EX_ROW_EN[1] = 0x0
6216 04:37:59.915283 LP4Y_EN = 0x0
6217 04:37:59.915402 WORK_FSP = 0x0
6218 04:37:59.918637 WL = 0x2
6219 04:37:59.918720 RL = 0x2
6220 04:37:59.922060 BL = 0x2
6221 04:37:59.922142 RPST = 0x0
6222 04:37:59.925141 RD_PRE = 0x0
6223 04:37:59.925224 WR_PRE = 0x1
6224 04:37:59.928823 WR_PST = 0x0
6225 04:37:59.928905 DBI_WR = 0x0
6226 04:37:59.932083 DBI_RD = 0x0
6227 04:37:59.932166 OTF = 0x1
6228 04:37:59.935048 ===================================
6229 04:37:59.938626 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6230 04:37:59.945646 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6231 04:37:59.948589 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 04:37:59.951846 ===================================
6233 04:37:59.955104 LPDDR4 DRAM CONFIGURATION
6234 04:37:59.958537 ===================================
6235 04:37:59.958620 EX_ROW_EN[0] = 0x10
6236 04:37:59.962162 EX_ROW_EN[1] = 0x0
6237 04:37:59.962274 LP4Y_EN = 0x0
6238 04:37:59.965094 WORK_FSP = 0x0
6239 04:37:59.965198 WL = 0x2
6240 04:37:59.968599 RL = 0x2
6241 04:37:59.972050 BL = 0x2
6242 04:37:59.972128 RPST = 0x0
6243 04:37:59.975047 RD_PRE = 0x0
6244 04:37:59.975151 WR_PRE = 0x1
6245 04:37:59.978561 WR_PST = 0x0
6246 04:37:59.978642 DBI_WR = 0x0
6247 04:37:59.981754 DBI_RD = 0x0
6248 04:37:59.981858 OTF = 0x1
6249 04:37:59.985348 ===================================
6250 04:37:59.991700 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6251 04:37:59.995685 nWR fixed to 30
6252 04:37:59.998732 [ModeRegInit_LP4] CH0 RK0
6253 04:37:59.998812 [ModeRegInit_LP4] CH0 RK1
6254 04:38:00.002159 [ModeRegInit_LP4] CH1 RK0
6255 04:38:00.005823 [ModeRegInit_LP4] CH1 RK1
6256 04:38:00.005902 match AC timing 19
6257 04:38:00.012345 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6258 04:38:00.015358 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6259 04:38:00.018796 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6260 04:38:00.025279 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6261 04:38:00.029001 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6262 04:38:00.029083 ==
6263 04:38:00.032409 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 04:38:00.035518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 04:38:00.035593 ==
6266 04:38:00.042165 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 04:38:00.048814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6268 04:38:00.051867 [CA 0] Center 36 (8~64) winsize 57
6269 04:38:00.055319 [CA 1] Center 36 (8~64) winsize 57
6270 04:38:00.058251 [CA 2] Center 36 (8~64) winsize 57
6271 04:38:00.061681 [CA 3] Center 36 (8~64) winsize 57
6272 04:38:00.061784 [CA 4] Center 36 (8~64) winsize 57
6273 04:38:00.065058 [CA 5] Center 36 (8~64) winsize 57
6274 04:38:00.065140
6275 04:38:00.071562 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6276 04:38:00.071668
6277 04:38:00.075310 [CATrainingPosCal] consider 1 rank data
6278 04:38:00.078169 u2DelayCellTimex100 = 270/100 ps
6279 04:38:00.081750 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 04:38:00.085260 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 04:38:00.088411 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 04:38:00.091489 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 04:38:00.095184 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 04:38:00.098511 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 04:38:00.098606
6286 04:38:00.101345 CA PerBit enable=1, Macro0, CA PI delay=36
6287 04:38:00.101442
6288 04:38:00.104815 [CBTSetCACLKResult] CA Dly = 36
6289 04:38:00.108520 CS Dly: 1 (0~32)
6290 04:38:00.108622 ==
6291 04:38:00.111518 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 04:38:00.114618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 04:38:00.114700 ==
6294 04:38:00.121339 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 04:38:00.128105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6296 04:38:00.131446 [CA 0] Center 36 (8~64) winsize 57
6297 04:38:00.131524 [CA 1] Center 36 (8~64) winsize 57
6298 04:38:00.134523 [CA 2] Center 36 (8~64) winsize 57
6299 04:38:00.138204 [CA 3] Center 36 (8~64) winsize 57
6300 04:38:00.141197 [CA 4] Center 36 (8~64) winsize 57
6301 04:38:00.144819 [CA 5] Center 36 (8~64) winsize 57
6302 04:38:00.144924
6303 04:38:00.147948 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6304 04:38:00.148056
6305 04:38:00.151011 [CATrainingPosCal] consider 2 rank data
6306 04:38:00.154551 u2DelayCellTimex100 = 270/100 ps
6307 04:38:00.157694 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 04:38:00.164209 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 04:38:00.167800 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 04:38:00.171198 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 04:38:00.174176 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 04:38:00.177898 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 04:38:00.178002
6314 04:38:00.180724 CA PerBit enable=1, Macro0, CA PI delay=36
6315 04:38:00.180809
6316 04:38:00.184319 [CBTSetCACLKResult] CA Dly = 36
6317 04:38:00.187987 CS Dly: 1 (0~32)
6318 04:38:00.188093
6319 04:38:00.190689 ----->DramcWriteLeveling(PI) begin...
6320 04:38:00.190794 ==
6321 04:38:00.194233 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 04:38:00.197320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 04:38:00.197397 ==
6324 04:38:00.200936 Write leveling (Byte 0): 40 => 8
6325 04:38:00.204133 Write leveling (Byte 1): 40 => 8
6326 04:38:00.207266 DramcWriteLeveling(PI) end<-----
6327 04:38:00.207349
6328 04:38:00.207436 ==
6329 04:38:00.210788 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 04:38:00.214138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 04:38:00.214251 ==
6332 04:38:00.217398 [Gating] SW mode calibration
6333 04:38:00.223649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6334 04:38:00.230521 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6335 04:38:00.233670 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 04:38:00.237331 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 04:38:00.243362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 04:38:00.247171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 04:38:00.250316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 04:38:00.256890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 04:38:00.260569 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 04:38:00.263640 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 04:38:00.270040 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 04:38:00.270153 Total UI for P1: 0, mck2ui 16
6345 04:38:00.276538 best dqsien dly found for B0: ( 0, 14, 24)
6346 04:38:00.276624 Total UI for P1: 0, mck2ui 16
6347 04:38:00.283350 best dqsien dly found for B1: ( 0, 14, 24)
6348 04:38:00.286468 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6349 04:38:00.290167 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6350 04:38:00.290247
6351 04:38:00.293239 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 04:38:00.297016 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 04:38:00.300171 [Gating] SW calibration Done
6354 04:38:00.300252 ==
6355 04:38:00.303181 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 04:38:00.306657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 04:38:00.306738 ==
6358 04:38:00.309742 RX Vref Scan: 0
6359 04:38:00.309822
6360 04:38:00.309886 RX Vref 0 -> 0, step: 1
6361 04:38:00.309947
6362 04:38:00.313283 RX Delay -410 -> 252, step: 16
6363 04:38:00.320039 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6364 04:38:00.323289 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6365 04:38:00.326261 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6366 04:38:00.329835 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6367 04:38:00.336225 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6368 04:38:00.340030 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6369 04:38:00.342883 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6370 04:38:00.346560 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6371 04:38:00.353460 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6372 04:38:00.356486 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6373 04:38:00.359552 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6374 04:38:00.363110 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6375 04:38:00.369941 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6376 04:38:00.373354 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6377 04:38:00.376309 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6378 04:38:00.379914 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6379 04:38:00.382795 ==
6380 04:38:00.386471 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 04:38:00.389396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 04:38:00.389478 ==
6383 04:38:00.389542 DQS Delay:
6384 04:38:00.393040 DQS0 = 59, DQS1 = 59
6385 04:38:00.393121 DQM Delay:
6386 04:38:00.396527 DQM0 = 18, DQM1 = 10
6387 04:38:00.396608 DQ Delay:
6388 04:38:00.399609 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6389 04:38:00.402655 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6390 04:38:00.406183 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6391 04:38:00.409584 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6392 04:38:00.409666
6393 04:38:00.409731
6394 04:38:00.409792 ==
6395 04:38:00.412503 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 04:38:00.416161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 04:38:00.416242 ==
6398 04:38:00.416307
6399 04:38:00.416366
6400 04:38:00.419252 TX Vref Scan disable
6401 04:38:00.419333 == TX Byte 0 ==
6402 04:38:00.425845 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 04:38:00.429439 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 04:38:00.429520 == TX Byte 1 ==
6405 04:38:00.436293 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 04:38:00.439437 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 04:38:00.439532 ==
6408 04:38:00.442498 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 04:38:00.446055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 04:38:00.446136 ==
6411 04:38:00.446200
6412 04:38:00.446259
6413 04:38:00.449347 TX Vref Scan disable
6414 04:38:00.452154 == TX Byte 0 ==
6415 04:38:00.455701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 04:38:00.459027 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 04:38:00.459108 == TX Byte 1 ==
6418 04:38:00.465607 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 04:38:00.469077 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 04:38:00.469159
6421 04:38:00.469224 [DATLAT]
6422 04:38:00.472214 Freq=400, CH0 RK0
6423 04:38:00.472295
6424 04:38:00.472360 DATLAT Default: 0xf
6425 04:38:00.475814 0, 0xFFFF, sum = 0
6426 04:38:00.475897 1, 0xFFFF, sum = 0
6427 04:38:00.478812 2, 0xFFFF, sum = 0
6428 04:38:00.478894 3, 0xFFFF, sum = 0
6429 04:38:00.482329 4, 0xFFFF, sum = 0
6430 04:38:00.482412 5, 0xFFFF, sum = 0
6431 04:38:00.485909 6, 0xFFFF, sum = 0
6432 04:38:00.488798 7, 0xFFFF, sum = 0
6433 04:38:00.488879 8, 0xFFFF, sum = 0
6434 04:38:00.492388 9, 0xFFFF, sum = 0
6435 04:38:00.492470 10, 0xFFFF, sum = 0
6436 04:38:00.495965 11, 0xFFFF, sum = 0
6437 04:38:00.496048 12, 0xFFFF, sum = 0
6438 04:38:00.498848 13, 0x0, sum = 1
6439 04:38:00.498929 14, 0x0, sum = 2
6440 04:38:00.502431 15, 0x0, sum = 3
6441 04:38:00.502513 16, 0x0, sum = 4
6442 04:38:00.505444 best_step = 14
6443 04:38:00.505524
6444 04:38:00.505589 ==
6445 04:38:00.509075 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 04:38:00.512190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 04:38:00.512272 ==
6448 04:38:00.512337 RX Vref Scan: 1
6449 04:38:00.512396
6450 04:38:00.515666 RX Vref 0 -> 0, step: 1
6451 04:38:00.515747
6452 04:38:00.518641 RX Delay -359 -> 252, step: 8
6453 04:38:00.518721
6454 04:38:00.522298 Set Vref, RX VrefLevel [Byte0]: 61
6455 04:38:00.525199 [Byte1]: 51
6456 04:38:00.529554
6457 04:38:00.529648 Final RX Vref Byte 0 = 61 to rank0
6458 04:38:00.532538 Final RX Vref Byte 1 = 51 to rank0
6459 04:38:00.535785 Final RX Vref Byte 0 = 61 to rank1
6460 04:38:00.539133 Final RX Vref Byte 1 = 51 to rank1==
6461 04:38:00.542605 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 04:38:00.549176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 04:38:00.549276 ==
6464 04:38:00.549342 DQS Delay:
6465 04:38:00.552685 DQS0 = 60, DQS1 = 68
6466 04:38:00.552780 DQM Delay:
6467 04:38:00.552846 DQM0 = 14, DQM1 = 13
6468 04:38:00.555761 DQ Delay:
6469 04:38:00.559086 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =16
6470 04:38:00.562201 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6471 04:38:00.565745 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6472 04:38:00.568704 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6473 04:38:00.568799
6474 04:38:00.568883
6475 04:38:00.575753 [DQSOSCAuto] RK0, (LSB)MR18= 0x8281, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6476 04:38:00.579002 CH0 RK0: MR19=C0C, MR18=8281
6477 04:38:00.585331 CH0_RK0: MR19=0xC0C, MR18=0x8281, DQSOSC=393, MR23=63, INC=382, DEC=254
6478 04:38:00.585413 ==
6479 04:38:00.588861 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 04:38:00.591980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 04:38:00.592061 ==
6482 04:38:00.595670 [Gating] SW mode calibration
6483 04:38:00.602168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 04:38:00.608165 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6485 04:38:00.611790 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 04:38:00.614924 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 04:38:00.621525 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 04:38:00.625252 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 04:38:00.628454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 04:38:00.634996 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 04:38:00.638004 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 04:38:00.641680 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 04:38:00.648026 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 04:38:00.651707 Total UI for P1: 0, mck2ui 16
6495 04:38:00.654596 best dqsien dly found for B0: ( 0, 14, 24)
6496 04:38:00.654677 Total UI for P1: 0, mck2ui 16
6497 04:38:00.661250 best dqsien dly found for B1: ( 0, 14, 24)
6498 04:38:00.664813 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6499 04:38:00.668280 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6500 04:38:00.668361
6501 04:38:00.671123 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 04:38:00.674378 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 04:38:00.678042 [Gating] SW calibration Done
6504 04:38:00.678123 ==
6505 04:38:00.681359 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 04:38:00.684419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 04:38:00.684501 ==
6508 04:38:00.687947 RX Vref Scan: 0
6509 04:38:00.688027
6510 04:38:00.690834 RX Vref 0 -> 0, step: 1
6511 04:38:00.690914
6512 04:38:00.690979 RX Delay -410 -> 252, step: 16
6513 04:38:00.698082 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6514 04:38:00.701017 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6515 04:38:00.704116 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6516 04:38:00.710657 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6517 04:38:00.713960 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6518 04:38:00.717617 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6519 04:38:00.720627 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6520 04:38:00.727070 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6521 04:38:00.730690 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6522 04:38:00.733819 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6523 04:38:00.737427 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6524 04:38:00.744086 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6525 04:38:00.747157 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6526 04:38:00.750732 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6527 04:38:00.754036 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6528 04:38:00.760488 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6529 04:38:00.760569 ==
6530 04:38:00.763619 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 04:38:00.767261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 04:38:00.767391 ==
6533 04:38:00.767473 DQS Delay:
6534 04:38:00.770347 DQS0 = 59, DQS1 = 59
6535 04:38:00.770428 DQM Delay:
6536 04:38:00.773761 DQM0 = 16, DQM1 = 10
6537 04:38:00.773842 DQ Delay:
6538 04:38:00.776851 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6539 04:38:00.780236 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6540 04:38:00.783591 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6541 04:38:00.787103 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6542 04:38:00.787186
6543 04:38:00.787251
6544 04:38:00.787312 ==
6545 04:38:00.790085 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 04:38:00.793656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 04:38:00.797439 ==
6548 04:38:00.797520
6549 04:38:00.797584
6550 04:38:00.797643 TX Vref Scan disable
6551 04:38:00.800316 == TX Byte 0 ==
6552 04:38:00.803285 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6553 04:38:00.806805 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6554 04:38:00.810067 == TX Byte 1 ==
6555 04:38:00.813600 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6556 04:38:00.817026 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6557 04:38:00.817132 ==
6558 04:38:00.820530 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 04:38:00.823531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 04:38:00.826667 ==
6561 04:38:00.826748
6562 04:38:00.826812
6563 04:38:00.826872 TX Vref Scan disable
6564 04:38:00.830207 == TX Byte 0 ==
6565 04:38:00.833456 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6566 04:38:00.836490 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6567 04:38:00.840082 == TX Byte 1 ==
6568 04:38:00.843060 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6569 04:38:00.846569 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6570 04:38:00.846650
6571 04:38:00.849692 [DATLAT]
6572 04:38:00.849774 Freq=400, CH0 RK1
6573 04:38:00.849838
6574 04:38:00.853275 DATLAT Default: 0xe
6575 04:38:00.853355 0, 0xFFFF, sum = 0
6576 04:38:00.856772 1, 0xFFFF, sum = 0
6577 04:38:00.856854 2, 0xFFFF, sum = 0
6578 04:38:00.859600 3, 0xFFFF, sum = 0
6579 04:38:00.859709 4, 0xFFFF, sum = 0
6580 04:38:00.863465 5, 0xFFFF, sum = 0
6581 04:38:00.863547 6, 0xFFFF, sum = 0
6582 04:38:00.866305 7, 0xFFFF, sum = 0
6583 04:38:00.866413 8, 0xFFFF, sum = 0
6584 04:38:00.869930 9, 0xFFFF, sum = 0
6585 04:38:00.870013 10, 0xFFFF, sum = 0
6586 04:38:00.872968 11, 0xFFFF, sum = 0
6587 04:38:00.873050 12, 0xFFFF, sum = 0
6588 04:38:00.876425 13, 0x0, sum = 1
6589 04:38:00.876507 14, 0x0, sum = 2
6590 04:38:00.879416 15, 0x0, sum = 3
6591 04:38:00.879502 16, 0x0, sum = 4
6592 04:38:00.882971 best_step = 14
6593 04:38:00.883051
6594 04:38:00.883116 ==
6595 04:38:00.886543 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 04:38:00.889480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 04:38:00.889561 ==
6598 04:38:00.892774 RX Vref Scan: 0
6599 04:38:00.892854
6600 04:38:00.892918 RX Vref 0 -> 0, step: 1
6601 04:38:00.892979
6602 04:38:00.896402 RX Delay -359 -> 252, step: 8
6603 04:38:00.904258 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6604 04:38:00.907876 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6605 04:38:00.910912 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6606 04:38:00.917215 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6607 04:38:00.920610 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6608 04:38:00.924466 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6609 04:38:00.927607 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6610 04:38:00.930914 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6611 04:38:00.937157 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6612 04:38:00.940893 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6613 04:38:00.943881 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6614 04:38:00.950496 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6615 04:38:00.953933 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6616 04:38:00.957043 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6617 04:38:00.960686 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6618 04:38:00.967547 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6619 04:38:00.967628 ==
6620 04:38:00.970317 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 04:38:00.973638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 04:38:00.973720 ==
6623 04:38:00.973785 DQS Delay:
6624 04:38:00.977194 DQS0 = 60, DQS1 = 72
6625 04:38:00.977275 DQM Delay:
6626 04:38:00.980192 DQM0 = 11, DQM1 = 17
6627 04:38:00.980273 DQ Delay:
6628 04:38:00.983699 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6629 04:38:00.987283 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6630 04:38:00.990391 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6631 04:38:00.993363 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6632 04:38:00.993444
6633 04:38:00.993509
6634 04:38:01.000300 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6635 04:38:01.003835 CH0 RK1: MR19=C0C, MR18=C77C
6636 04:38:01.010441 CH0_RK1: MR19=0xC0C, MR18=0xC77C, DQSOSC=385, MR23=63, INC=398, DEC=265
6637 04:38:01.013432 [RxdqsGatingPostProcess] freq 400
6638 04:38:01.019973 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6639 04:38:01.023499 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 04:38:01.023619 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 04:38:01.026567 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 04:38:01.030253 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 04:38:01.033357 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 04:38:01.036536 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 04:38:01.040065 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 04:38:01.043192 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 04:38:01.046697 Pre-setting of DQS Precalculation
6648 04:38:01.053247 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6649 04:38:01.053329 ==
6650 04:38:01.056483 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 04:38:01.059798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 04:38:01.059881 ==
6653 04:38:01.066349 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 04:38:01.070081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6655 04:38:01.073041 [CA 0] Center 36 (8~64) winsize 57
6656 04:38:01.076766 [CA 1] Center 36 (8~64) winsize 57
6657 04:38:01.079726 [CA 2] Center 36 (8~64) winsize 57
6658 04:38:01.082995 [CA 3] Center 36 (8~64) winsize 57
6659 04:38:01.086270 [CA 4] Center 36 (8~64) winsize 57
6660 04:38:01.089761 [CA 5] Center 36 (8~64) winsize 57
6661 04:38:01.089868
6662 04:38:01.093340 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6663 04:38:01.093421
6664 04:38:01.096329 [CATrainingPosCal] consider 1 rank data
6665 04:38:01.099329 u2DelayCellTimex100 = 270/100 ps
6666 04:38:01.102892 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 04:38:01.109370 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 04:38:01.112695 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 04:38:01.115743 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 04:38:01.119281 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 04:38:01.122331 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 04:38:01.122412
6673 04:38:01.125997 CA PerBit enable=1, Macro0, CA PI delay=36
6674 04:38:01.126078
6675 04:38:01.128958 [CBTSetCACLKResult] CA Dly = 36
6676 04:38:01.129040 CS Dly: 1 (0~32)
6677 04:38:01.132453 ==
6678 04:38:01.136038 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 04:38:01.139049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 04:38:01.139130 ==
6681 04:38:01.142566 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 04:38:01.149105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6683 04:38:01.152140 [CA 0] Center 36 (8~64) winsize 57
6684 04:38:01.155892 [CA 1] Center 36 (8~64) winsize 57
6685 04:38:01.159200 [CA 2] Center 36 (8~64) winsize 57
6686 04:38:01.162170 [CA 3] Center 36 (8~64) winsize 57
6687 04:38:01.165448 [CA 4] Center 36 (8~64) winsize 57
6688 04:38:01.168666 [CA 5] Center 36 (8~64) winsize 57
6689 04:38:01.168746
6690 04:38:01.172028 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6691 04:38:01.172109
6692 04:38:01.175502 [CATrainingPosCal] consider 2 rank data
6693 04:38:01.178584 u2DelayCellTimex100 = 270/100 ps
6694 04:38:01.182127 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 04:38:01.185173 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 04:38:01.188645 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 04:38:01.195503 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 04:38:01.198676 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 04:38:01.201835 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 04:38:01.201917
6701 04:38:01.205440 CA PerBit enable=1, Macro0, CA PI delay=36
6702 04:38:01.205521
6703 04:38:01.208404 [CBTSetCACLKResult] CA Dly = 36
6704 04:38:01.208487 CS Dly: 1 (0~32)
6705 04:38:01.208551
6706 04:38:01.212025 ----->DramcWriteLeveling(PI) begin...
6707 04:38:01.212108 ==
6708 04:38:01.214960 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 04:38:01.221814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 04:38:01.221895 ==
6711 04:38:01.225502 Write leveling (Byte 0): 40 => 8
6712 04:38:01.228519 Write leveling (Byte 1): 40 => 8
6713 04:38:01.228600 DramcWriteLeveling(PI) end<-----
6714 04:38:01.228665
6715 04:38:01.231569 ==
6716 04:38:01.235034 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 04:38:01.238571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 04:38:01.238653 ==
6719 04:38:01.241729 [Gating] SW mode calibration
6720 04:38:01.248307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6721 04:38:01.251748 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6722 04:38:01.258450 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 04:38:01.261453 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 04:38:01.265030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 04:38:01.271243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 04:38:01.274508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 04:38:01.277883 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 04:38:01.284963 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 04:38:01.288109 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 04:38:01.291075 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 04:38:01.294651 Total UI for P1: 0, mck2ui 16
6732 04:38:01.297759 best dqsien dly found for B0: ( 0, 14, 24)
6733 04:38:01.301208 Total UI for P1: 0, mck2ui 16
6734 04:38:01.304545 best dqsien dly found for B1: ( 0, 14, 24)
6735 04:38:01.307636 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6736 04:38:01.311182 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6737 04:38:01.311311
6738 04:38:01.317545 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 04:38:01.320963 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 04:38:01.324477 [Gating] SW calibration Done
6741 04:38:01.324605 ==
6742 04:38:01.327761 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 04:38:01.330876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 04:38:01.330959 ==
6745 04:38:01.331024 RX Vref Scan: 0
6746 04:38:01.334002
6747 04:38:01.334082 RX Vref 0 -> 0, step: 1
6748 04:38:01.334147
6749 04:38:01.337588 RX Delay -410 -> 252, step: 16
6750 04:38:01.340587 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6751 04:38:01.347189 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6752 04:38:01.350987 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6753 04:38:01.353721 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6754 04:38:01.357354 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6755 04:38:01.364137 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6756 04:38:01.367163 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6757 04:38:01.370464 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6758 04:38:01.373866 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6759 04:38:01.380666 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6760 04:38:01.384181 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6761 04:38:01.387354 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6762 04:38:01.390340 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6763 04:38:01.396938 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6764 04:38:01.400869 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6765 04:38:01.404140 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6766 04:38:01.404224 ==
6767 04:38:01.407154 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 04:38:01.413659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 04:38:01.413741 ==
6770 04:38:01.413806 DQS Delay:
6771 04:38:01.417243 DQS0 = 43, DQS1 = 67
6772 04:38:01.417324 DQM Delay:
6773 04:38:01.417389 DQM0 = 6, DQM1 = 19
6774 04:38:01.420825 DQ Delay:
6775 04:38:01.424008 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6776 04:38:01.424090 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6777 04:38:01.426830 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6778 04:38:01.430133 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6779 04:38:01.430214
6780 04:38:01.433496
6781 04:38:01.433577 ==
6782 04:38:01.436868 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 04:38:01.439963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 04:38:01.440049 ==
6785 04:38:01.440113
6786 04:38:01.440173
6787 04:38:01.443690 TX Vref Scan disable
6788 04:38:01.443770 == TX Byte 0 ==
6789 04:38:01.446777 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 04:38:01.453319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 04:38:01.453403 == TX Byte 1 ==
6792 04:38:01.456424 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 04:38:01.463742 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 04:38:01.463824 ==
6795 04:38:01.466554 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 04:38:01.469896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 04:38:01.469977 ==
6798 04:38:01.470042
6799 04:38:01.470101
6800 04:38:01.473274 TX Vref Scan disable
6801 04:38:01.473355 == TX Byte 0 ==
6802 04:38:01.476946 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 04:38:01.482951 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 04:38:01.483033 == TX Byte 1 ==
6805 04:38:01.486608 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 04:38:01.493449 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 04:38:01.493530
6808 04:38:01.493595 [DATLAT]
6809 04:38:01.493655 Freq=400, CH1 RK0
6810 04:38:01.496436
6811 04:38:01.496517 DATLAT Default: 0xf
6812 04:38:01.500098 0, 0xFFFF, sum = 0
6813 04:38:01.500180 1, 0xFFFF, sum = 0
6814 04:38:01.503424 2, 0xFFFF, sum = 0
6815 04:38:01.503521 3, 0xFFFF, sum = 0
6816 04:38:01.506442 4, 0xFFFF, sum = 0
6817 04:38:01.506525 5, 0xFFFF, sum = 0
6818 04:38:01.509999 6, 0xFFFF, sum = 0
6819 04:38:01.510081 7, 0xFFFF, sum = 0
6820 04:38:01.512917 8, 0xFFFF, sum = 0
6821 04:38:01.512999 9, 0xFFFF, sum = 0
6822 04:38:01.516569 10, 0xFFFF, sum = 0
6823 04:38:01.516651 11, 0xFFFF, sum = 0
6824 04:38:01.519524 12, 0xFFFF, sum = 0
6825 04:38:01.519606 13, 0x0, sum = 1
6826 04:38:01.523095 14, 0x0, sum = 2
6827 04:38:01.523176 15, 0x0, sum = 3
6828 04:38:01.526375 16, 0x0, sum = 4
6829 04:38:01.526473 best_step = 14
6830 04:38:01.526536
6831 04:38:01.526597 ==
6832 04:38:01.529674 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 04:38:01.536267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 04:38:01.536348 ==
6835 04:38:01.536413 RX Vref Scan: 1
6836 04:38:01.536473
6837 04:38:01.539784 RX Vref 0 -> 0, step: 1
6838 04:38:01.539864
6839 04:38:01.542760 RX Delay -375 -> 252, step: 8
6840 04:38:01.542841
6841 04:38:01.546539 Set Vref, RX VrefLevel [Byte0]: 53
6842 04:38:01.549579 [Byte1]: 51
6843 04:38:01.549707
6844 04:38:01.553165 Final RX Vref Byte 0 = 53 to rank0
6845 04:38:01.556146 Final RX Vref Byte 1 = 51 to rank0
6846 04:38:01.559241 Final RX Vref Byte 0 = 53 to rank1
6847 04:38:01.562993 Final RX Vref Byte 1 = 51 to rank1==
6848 04:38:01.566456 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 04:38:01.569510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 04:38:01.572704 ==
6851 04:38:01.572786 DQS Delay:
6852 04:38:01.572852 DQS0 = 52, DQS1 = 64
6853 04:38:01.576052 DQM Delay:
6854 04:38:01.576134 DQM0 = 9, DQM1 = 11
6855 04:38:01.579211 DQ Delay:
6856 04:38:01.579292 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6857 04:38:01.583003 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6858 04:38:01.586322 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6859 04:38:01.589183 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6860 04:38:01.589265
6861 04:38:01.589329
6862 04:38:01.599290 [DQSOSCAuto] RK0, (LSB)MR18= 0x596c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6863 04:38:01.602341 CH1 RK0: MR19=C0C, MR18=596C
6864 04:38:01.609315 CH1_RK0: MR19=0xC0C, MR18=0x596C, DQSOSC=396, MR23=63, INC=376, DEC=251
6865 04:38:01.609397 ==
6866 04:38:01.612772 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 04:38:01.616227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 04:38:01.616309 ==
6869 04:38:01.619212 [Gating] SW mode calibration
6870 04:38:01.625842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6871 04:38:01.628952 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6872 04:38:01.636063 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 04:38:01.638983 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 04:38:01.642714 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 04:38:01.649236 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 04:38:01.652548 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 04:38:01.655603 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 04:38:01.662086 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 04:38:01.666023 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 04:38:01.668874 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 04:38:01.672504 Total UI for P1: 0, mck2ui 16
6882 04:38:01.675514 best dqsien dly found for B0: ( 0, 14, 24)
6883 04:38:01.679242 Total UI for P1: 0, mck2ui 16
6884 04:38:01.682229 best dqsien dly found for B1: ( 0, 14, 24)
6885 04:38:01.685819 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6886 04:38:01.688733 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6887 04:38:01.688815
6888 04:38:01.695801 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 04:38:01.698981 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 04:38:01.701982 [Gating] SW calibration Done
6891 04:38:01.702063 ==
6892 04:38:01.705351 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 04:38:01.709037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 04:38:01.709144 ==
6895 04:38:01.709245 RX Vref Scan: 0
6896 04:38:01.709309
6897 04:38:01.712082 RX Vref 0 -> 0, step: 1
6898 04:38:01.712162
6899 04:38:01.715514 RX Delay -410 -> 252, step: 16
6900 04:38:01.718337 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6901 04:38:01.725009 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6902 04:38:01.728531 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6903 04:38:01.732323 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6904 04:38:01.735315 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6905 04:38:01.742142 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6906 04:38:01.745719 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6907 04:38:01.748469 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6908 04:38:01.752111 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6909 04:38:01.758474 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6910 04:38:01.761925 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6911 04:38:01.765411 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6912 04:38:01.768327 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6913 04:38:01.774934 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6914 04:38:01.778835 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6915 04:38:01.781639 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6916 04:38:01.781721 ==
6917 04:38:01.785193 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 04:38:01.791444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 04:38:01.791526 ==
6920 04:38:01.791592 DQS Delay:
6921 04:38:01.795000 DQS0 = 59, DQS1 = 59
6922 04:38:01.795082 DQM Delay:
6923 04:38:01.795147 DQM0 = 19, DQM1 = 14
6924 04:38:01.798386 DQ Delay:
6925 04:38:01.802118 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6926 04:38:01.804872 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6927 04:38:01.804954 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6928 04:38:01.808090 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6929 04:38:01.811701
6930 04:38:01.811781
6931 04:38:01.811846 ==
6932 04:38:01.814800 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 04:38:01.818115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 04:38:01.818198 ==
6935 04:38:01.818263
6936 04:38:01.818323
6937 04:38:01.821502 TX Vref Scan disable
6938 04:38:01.821585 == TX Byte 0 ==
6939 04:38:01.824498 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6940 04:38:01.831510 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6941 04:38:01.831592 == TX Byte 1 ==
6942 04:38:01.834845 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6943 04:38:01.841268 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6944 04:38:01.841350 ==
6945 04:38:01.844760 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 04:38:01.848223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 04:38:01.848306 ==
6948 04:38:01.848371
6949 04:38:01.848431
6950 04:38:01.851106 TX Vref Scan disable
6951 04:38:01.851188 == TX Byte 0 ==
6952 04:38:01.854817 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6953 04:38:01.861308 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6954 04:38:01.861407 == TX Byte 1 ==
6955 04:38:01.864264 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6956 04:38:01.871093 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6957 04:38:01.871199
6958 04:38:01.871292 [DATLAT]
6959 04:38:01.871403 Freq=400, CH1 RK1
6960 04:38:01.874719
6961 04:38:01.874799 DATLAT Default: 0xe
6962 04:38:01.878091 0, 0xFFFF, sum = 0
6963 04:38:01.878174 1, 0xFFFF, sum = 0
6964 04:38:01.881123 2, 0xFFFF, sum = 0
6965 04:38:01.881205 3, 0xFFFF, sum = 0
6966 04:38:01.884081 4, 0xFFFF, sum = 0
6967 04:38:01.884164 5, 0xFFFF, sum = 0
6968 04:38:01.887649 6, 0xFFFF, sum = 0
6969 04:38:01.887731 7, 0xFFFF, sum = 0
6970 04:38:01.890669 8, 0xFFFF, sum = 0
6971 04:38:01.890751 9, 0xFFFF, sum = 0
6972 04:38:01.894327 10, 0xFFFF, sum = 0
6973 04:38:01.894411 11, 0xFFFF, sum = 0
6974 04:38:01.897324 12, 0xFFFF, sum = 0
6975 04:38:01.897406 13, 0x0, sum = 1
6976 04:38:01.900962 14, 0x0, sum = 2
6977 04:38:01.901045 15, 0x0, sum = 3
6978 04:38:01.904412 16, 0x0, sum = 4
6979 04:38:01.904495 best_step = 14
6980 04:38:01.904560
6981 04:38:01.904638 ==
6982 04:38:01.907335 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 04:38:01.914099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 04:38:01.914181 ==
6985 04:38:01.914246 RX Vref Scan: 0
6986 04:38:01.914307
6987 04:38:01.917056 RX Vref 0 -> 0, step: 1
6988 04:38:01.917138
6989 04:38:01.920274 RX Delay -359 -> 252, step: 8
6990 04:38:01.926935 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6991 04:38:01.930231 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6992 04:38:01.933479 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6993 04:38:01.940337 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6994 04:38:01.943793 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6995 04:38:01.946699 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6996 04:38:01.950185 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6997 04:38:01.953790 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6998 04:38:01.960217 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6999 04:38:01.963541 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7000 04:38:01.966932 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7001 04:38:01.973462 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7002 04:38:01.976716 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7003 04:38:01.980191 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7004 04:38:01.983663 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7005 04:38:01.990542 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7006 04:38:01.990623 ==
7007 04:38:01.993408 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 04:38:01.996972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 04:38:01.997053 ==
7010 04:38:01.997118 DQS Delay:
7011 04:38:02.000094 DQS0 = 60, DQS1 = 64
7012 04:38:02.000174 DQM Delay:
7013 04:38:02.003063 DQM0 = 13, DQM1 = 10
7014 04:38:02.003169 DQ Delay:
7015 04:38:02.006527 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7016 04:38:02.010031 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7017 04:38:02.013075 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7018 04:38:02.016697 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7019 04:38:02.016778
7020 04:38:02.016843
7021 04:38:02.023368 [DQSOSCAuto] RK1, (LSB)MR18= 0x77a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7022 04:38:02.026377 CH1 RK1: MR19=C0C, MR18=77A7
7023 04:38:02.033409 CH1_RK1: MR19=0xC0C, MR18=0x77A7, DQSOSC=389, MR23=63, INC=390, DEC=260
7024 04:38:02.036504 [RxdqsGatingPostProcess] freq 400
7025 04:38:02.043024 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7026 04:38:02.046190 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 04:38:02.046271 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 04:38:02.049752 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 04:38:02.053248 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 04:38:02.056300 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 04:38:02.059653 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 04:38:02.062989 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 04:38:02.066343 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 04:38:02.069963 Pre-setting of DQS Precalculation
7035 04:38:02.076546 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7036 04:38:02.082999 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7037 04:38:02.089811 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7038 04:38:02.089893
7039 04:38:02.089958
7040 04:38:02.092853 [Calibration Summary] 800 Mbps
7041 04:38:02.092934 CH 0, Rank 0
7042 04:38:02.096442 SW Impedance : PASS
7043 04:38:02.099461 DUTY Scan : NO K
7044 04:38:02.099542 ZQ Calibration : PASS
7045 04:38:02.103152 Jitter Meter : NO K
7046 04:38:02.103233 CBT Training : PASS
7047 04:38:02.106231 Write leveling : PASS
7048 04:38:02.109250 RX DQS gating : PASS
7049 04:38:02.109331 RX DQ/DQS(RDDQC) : PASS
7050 04:38:02.112907 TX DQ/DQS : PASS
7051 04:38:02.116312 RX DATLAT : PASS
7052 04:38:02.116393 RX DQ/DQS(Engine): PASS
7053 04:38:02.119350 TX OE : NO K
7054 04:38:02.119443 All Pass.
7055 04:38:02.119508
7056 04:38:02.123034 CH 0, Rank 1
7057 04:38:02.123114 SW Impedance : PASS
7058 04:38:02.126034 DUTY Scan : NO K
7059 04:38:02.129061 ZQ Calibration : PASS
7060 04:38:02.129143 Jitter Meter : NO K
7061 04:38:02.132617 CBT Training : PASS
7062 04:38:02.136194 Write leveling : NO K
7063 04:38:02.136275 RX DQS gating : PASS
7064 04:38:02.139129 RX DQ/DQS(RDDQC) : PASS
7065 04:38:02.142760 TX DQ/DQS : PASS
7066 04:38:02.142868 RX DATLAT : PASS
7067 04:38:02.146008 RX DQ/DQS(Engine): PASS
7068 04:38:02.149185 TX OE : NO K
7069 04:38:02.149302 All Pass.
7070 04:38:02.149399
7071 04:38:02.149476 CH 1, Rank 0
7072 04:38:02.152779 SW Impedance : PASS
7073 04:38:02.155743 DUTY Scan : NO K
7074 04:38:02.155823 ZQ Calibration : PASS
7075 04:38:02.159315 Jitter Meter : NO K
7076 04:38:02.159434 CBT Training : PASS
7077 04:38:02.162688 Write leveling : PASS
7078 04:38:02.165847 RX DQS gating : PASS
7079 04:38:02.165928 RX DQ/DQS(RDDQC) : PASS
7080 04:38:02.169337 TX DQ/DQS : PASS
7081 04:38:02.172700 RX DATLAT : PASS
7082 04:38:02.172783 RX DQ/DQS(Engine): PASS
7083 04:38:02.176276 TX OE : NO K
7084 04:38:02.176358 All Pass.
7085 04:38:02.176423
7086 04:38:02.179403 CH 1, Rank 1
7087 04:38:02.179498 SW Impedance : PASS
7088 04:38:02.182645 DUTY Scan : NO K
7089 04:38:02.185699 ZQ Calibration : PASS
7090 04:38:02.185782 Jitter Meter : NO K
7091 04:38:02.188887 CBT Training : PASS
7092 04:38:02.192521 Write leveling : NO K
7093 04:38:02.192602 RX DQS gating : PASS
7094 04:38:02.195474 RX DQ/DQS(RDDQC) : PASS
7095 04:38:02.199016 TX DQ/DQS : PASS
7096 04:38:02.199098 RX DATLAT : PASS
7097 04:38:02.202244 RX DQ/DQS(Engine): PASS
7098 04:38:02.205617 TX OE : NO K
7099 04:38:02.205699 All Pass.
7100 04:38:02.205764
7101 04:38:02.205824 DramC Write-DBI off
7102 04:38:02.209163 PER_BANK_REFRESH: Hybrid Mode
7103 04:38:02.212117 TX_TRACKING: ON
7104 04:38:02.218607 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7105 04:38:02.225362 [FAST_K] Save calibration result to emmc
7106 04:38:02.228957 dramc_set_vcore_voltage set vcore to 725000
7107 04:38:02.229040 Read voltage for 1600, 0
7108 04:38:02.231972 Vio18 = 0
7109 04:38:02.232053 Vcore = 725000
7110 04:38:02.232118 Vdram = 0
7111 04:38:02.235559 Vddq = 0
7112 04:38:02.235641 Vmddr = 0
7113 04:38:02.238541 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7114 04:38:02.245190 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7115 04:38:02.248842 MEM_TYPE=3, freq_sel=13
7116 04:38:02.251812 sv_algorithm_assistance_LP4_3733
7117 04:38:02.255275 ============ PULL DRAM RESETB DOWN ============
7118 04:38:02.258826 ========== PULL DRAM RESETB DOWN end =========
7119 04:38:02.264841 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7120 04:38:02.268591 ===================================
7121 04:38:02.268668 LPDDR4 DRAM CONFIGURATION
7122 04:38:02.271895 ===================================
7123 04:38:02.275159 EX_ROW_EN[0] = 0x0
7124 04:38:02.275259 EX_ROW_EN[1] = 0x0
7125 04:38:02.278433 LP4Y_EN = 0x0
7126 04:38:02.278528 WORK_FSP = 0x1
7127 04:38:02.281425 WL = 0x5
7128 04:38:02.281502 RL = 0x5
7129 04:38:02.284960 BL = 0x2
7130 04:38:02.287812 RPST = 0x0
7131 04:38:02.287893 RD_PRE = 0x0
7132 04:38:02.291319 WR_PRE = 0x1
7133 04:38:02.291424 WR_PST = 0x1
7134 04:38:02.294598 DBI_WR = 0x0
7135 04:38:02.294679 DBI_RD = 0x0
7136 04:38:02.298193 OTF = 0x1
7137 04:38:02.301325 ===================================
7138 04:38:02.305405 ===================================
7139 04:38:02.305487 ANA top config
7140 04:38:02.308403 ===================================
7141 04:38:02.311138 DLL_ASYNC_EN = 0
7142 04:38:02.314855 ALL_SLAVE_EN = 0
7143 04:38:02.314957 NEW_RANK_MODE = 1
7144 04:38:02.318217 DLL_IDLE_MODE = 1
7145 04:38:02.320938 LP45_APHY_COMB_EN = 1
7146 04:38:02.324794 TX_ODT_DIS = 0
7147 04:38:02.327856 NEW_8X_MODE = 1
7148 04:38:02.331061 ===================================
7149 04:38:02.334281 ===================================
7150 04:38:02.334363 data_rate = 3200
7151 04:38:02.337393 CKR = 1
7152 04:38:02.341031 DQ_P2S_RATIO = 8
7153 04:38:02.344174 ===================================
7154 04:38:02.348011 CA_P2S_RATIO = 8
7155 04:38:02.351056 DQ_CA_OPEN = 0
7156 04:38:02.354121 DQ_SEMI_OPEN = 0
7157 04:38:02.354228 CA_SEMI_OPEN = 0
7158 04:38:02.358015 CA_FULL_RATE = 0
7159 04:38:02.360797 DQ_CKDIV4_EN = 0
7160 04:38:02.364177 CA_CKDIV4_EN = 0
7161 04:38:02.367641 CA_PREDIV_EN = 0
7162 04:38:02.371039 PH8_DLY = 12
7163 04:38:02.371121 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7164 04:38:02.374013 DQ_AAMCK_DIV = 4
7165 04:38:02.377648 CA_AAMCK_DIV = 4
7166 04:38:02.380690 CA_ADMCK_DIV = 4
7167 04:38:02.383990 DQ_TRACK_CA_EN = 0
7168 04:38:02.387325 CA_PICK = 1600
7169 04:38:02.390594 CA_MCKIO = 1600
7170 04:38:02.390703 MCKIO_SEMI = 0
7171 04:38:02.394149 PLL_FREQ = 3068
7172 04:38:02.397155 DQ_UI_PI_RATIO = 32
7173 04:38:02.400847 CA_UI_PI_RATIO = 0
7174 04:38:02.403603 ===================================
7175 04:38:02.407279 ===================================
7176 04:38:02.410684 memory_type:LPDDR4
7177 04:38:02.410792 GP_NUM : 10
7178 04:38:02.413718 SRAM_EN : 1
7179 04:38:02.417314 MD32_EN : 0
7180 04:38:02.420483 ===================================
7181 04:38:02.420561 [ANA_INIT] >>>>>>>>>>>>>>
7182 04:38:02.423588 <<<<<< [CONFIGURE PHASE]: ANA_TX
7183 04:38:02.426870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7184 04:38:02.430326 ===================================
7185 04:38:02.434078 data_rate = 3200,PCW = 0X7600
7186 04:38:02.437216 ===================================
7187 04:38:02.440231 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7188 04:38:02.446959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 04:38:02.450736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 04:38:02.456957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7191 04:38:02.460740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7192 04:38:02.463345 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7193 04:38:02.463440 [ANA_INIT] flow start
7194 04:38:02.466936 [ANA_INIT] PLL >>>>>>>>
7195 04:38:02.470144 [ANA_INIT] PLL <<<<<<<<
7196 04:38:02.473854 [ANA_INIT] MIDPI >>>>>>>>
7197 04:38:02.473964 [ANA_INIT] MIDPI <<<<<<<<
7198 04:38:02.476673 [ANA_INIT] DLL >>>>>>>>
7199 04:38:02.480174 [ANA_INIT] DLL <<<<<<<<
7200 04:38:02.480251 [ANA_INIT] flow end
7201 04:38:02.483567 ============ LP4 DIFF to SE enter ============
7202 04:38:02.489858 ============ LP4 DIFF to SE exit ============
7203 04:38:02.489941 [ANA_INIT] <<<<<<<<<<<<<
7204 04:38:02.493272 [Flow] Enable top DCM control >>>>>
7205 04:38:02.496696 [Flow] Enable top DCM control <<<<<
7206 04:38:02.499902 Enable DLL master slave shuffle
7207 04:38:02.507064 ==============================================================
7208 04:38:02.507147 Gating Mode config
7209 04:38:02.513217 ==============================================================
7210 04:38:02.516470 Config description:
7211 04:38:02.526364 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7212 04:38:02.532987 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7213 04:38:02.536296 SELPH_MODE 0: By rank 1: By Phase
7214 04:38:02.543060 ==============================================================
7215 04:38:02.546565 GAT_TRACK_EN = 1
7216 04:38:02.549847 RX_GATING_MODE = 2
7217 04:38:02.549955 RX_GATING_TRACK_MODE = 2
7218 04:38:02.553023 SELPH_MODE = 1
7219 04:38:02.556133 PICG_EARLY_EN = 1
7220 04:38:02.559924 VALID_LAT_VALUE = 1
7221 04:38:02.566130 ==============================================================
7222 04:38:02.569595 Enter into Gating configuration >>>>
7223 04:38:02.572793 Exit from Gating configuration <<<<
7224 04:38:02.576452 Enter into DVFS_PRE_config >>>>>
7225 04:38:02.586419 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7226 04:38:02.589294 Exit from DVFS_PRE_config <<<<<
7227 04:38:02.592552 Enter into PICG configuration >>>>
7228 04:38:02.596099 Exit from PICG configuration <<<<
7229 04:38:02.599497 [RX_INPUT] configuration >>>>>
7230 04:38:02.602603 [RX_INPUT] configuration <<<<<
7231 04:38:02.605945 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7232 04:38:02.612451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7233 04:38:02.619354 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 04:38:02.626168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 04:38:02.629081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 04:38:02.635728 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 04:38:02.639329 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7238 04:38:02.645843 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7239 04:38:02.649054 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7240 04:38:02.652311 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7241 04:38:02.655678 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7242 04:38:02.662353 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 04:38:02.666056 ===================================
7244 04:38:02.669169 LPDDR4 DRAM CONFIGURATION
7245 04:38:02.672368 ===================================
7246 04:38:02.672453 EX_ROW_EN[0] = 0x0
7247 04:38:02.675863 EX_ROW_EN[1] = 0x0
7248 04:38:02.675947 LP4Y_EN = 0x0
7249 04:38:02.679020 WORK_FSP = 0x1
7250 04:38:02.679103 WL = 0x5
7251 04:38:02.682577 RL = 0x5
7252 04:38:02.682661 BL = 0x2
7253 04:38:02.685724 RPST = 0x0
7254 04:38:02.685833 RD_PRE = 0x0
7255 04:38:02.688962 WR_PRE = 0x1
7256 04:38:02.689058 WR_PST = 0x1
7257 04:38:02.692165 DBI_WR = 0x0
7258 04:38:02.692258 DBI_RD = 0x0
7259 04:38:02.696123 OTF = 0x1
7260 04:38:02.698796 ===================================
7261 04:38:02.702152 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7262 04:38:02.705315 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7263 04:38:02.711960 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 04:38:02.715346 ===================================
7265 04:38:02.715461 LPDDR4 DRAM CONFIGURATION
7266 04:38:02.719153 ===================================
7267 04:38:02.722127 EX_ROW_EN[0] = 0x10
7268 04:38:02.725277 EX_ROW_EN[1] = 0x0
7269 04:38:02.725352 LP4Y_EN = 0x0
7270 04:38:02.728938 WORK_FSP = 0x1
7271 04:38:02.729020 WL = 0x5
7272 04:38:02.732070 RL = 0x5
7273 04:38:02.732150 BL = 0x2
7274 04:38:02.735572 RPST = 0x0
7275 04:38:02.735668 RD_PRE = 0x0
7276 04:38:02.738523 WR_PRE = 0x1
7277 04:38:02.738603 WR_PST = 0x1
7278 04:38:02.742240 DBI_WR = 0x0
7279 04:38:02.742321 DBI_RD = 0x0
7280 04:38:02.745304 OTF = 0x1
7281 04:38:02.748537 ===================================
7282 04:38:02.755233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7283 04:38:02.755318 ==
7284 04:38:02.758967 Dram Type= 6, Freq= 0, CH_0, rank 0
7285 04:38:02.761890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 04:38:02.761973 ==
7287 04:38:02.765180 [Duty_Offset_Calibration]
7288 04:38:02.765261 B0:2 B1:0 CA:4
7289 04:38:02.765326
7290 04:38:02.768552 [DutyScan_Calibration_Flow] k_type=0
7291 04:38:02.779198
7292 04:38:02.779279 ==CLK 0==
7293 04:38:02.782327 Final CLK duty delay cell = 0
7294 04:38:02.786190 [0] MAX Duty = 5031%(X100), DQS PI = 20
7295 04:38:02.789317 [0] MIN Duty = 4876%(X100), DQS PI = 54
7296 04:38:02.792411 [0] AVG Duty = 4953%(X100)
7297 04:38:02.792493
7298 04:38:02.795644 CH0 CLK Duty spec in!! Max-Min= 155%
7299 04:38:02.799317 [DutyScan_Calibration_Flow] ====Done====
7300 04:38:02.799422
7301 04:38:02.802384 [DutyScan_Calibration_Flow] k_type=1
7302 04:38:02.819048
7303 04:38:02.819127 ==DQS 0 ==
7304 04:38:02.822121 Final DQS duty delay cell = 0
7305 04:38:02.825594 [0] MAX Duty = 5094%(X100), DQS PI = 20
7306 04:38:02.829236 [0] MIN Duty = 4875%(X100), DQS PI = 52
7307 04:38:02.832421 [0] AVG Duty = 4984%(X100)
7308 04:38:02.832502
7309 04:38:02.832566 ==DQS 1 ==
7310 04:38:02.835543 Final DQS duty delay cell = 0
7311 04:38:02.839126 [0] MAX Duty = 5156%(X100), DQS PI = 32
7312 04:38:02.842258 [0] MIN Duty = 5031%(X100), DQS PI = 12
7313 04:38:02.845270 [0] AVG Duty = 5093%(X100)
7314 04:38:02.845351
7315 04:38:02.849148 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7316 04:38:02.849229
7317 04:38:02.852227 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7318 04:38:02.855368 [DutyScan_Calibration_Flow] ====Done====
7319 04:38:02.855486
7320 04:38:02.859024 [DutyScan_Calibration_Flow] k_type=3
7321 04:38:02.876873
7322 04:38:02.876956 ==DQM 0 ==
7323 04:38:02.880408 Final DQM duty delay cell = 0
7324 04:38:02.883601 [0] MAX Duty = 5156%(X100), DQS PI = 32
7325 04:38:02.886660 [0] MIN Duty = 4875%(X100), DQS PI = 0
7326 04:38:02.890172 [0] AVG Duty = 5015%(X100)
7327 04:38:02.890263
7328 04:38:02.890357 ==DQM 1 ==
7329 04:38:02.893207 Final DQM duty delay cell = 4
7330 04:38:02.897146 [4] MAX Duty = 5187%(X100), DQS PI = 60
7331 04:38:02.899829 [4] MIN Duty = 5031%(X100), DQS PI = 14
7332 04:38:02.903600 [4] AVG Duty = 5109%(X100)
7333 04:38:02.903707
7334 04:38:02.906626 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7335 04:38:02.906707
7336 04:38:02.910330 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7337 04:38:02.913278 [DutyScan_Calibration_Flow] ====Done====
7338 04:38:02.913384
7339 04:38:02.916767 [DutyScan_Calibration_Flow] k_type=2
7340 04:38:02.933015
7341 04:38:02.933097 ==DQ 0 ==
7342 04:38:02.936399 Final DQ duty delay cell = -4
7343 04:38:02.939485 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7344 04:38:02.942958 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7345 04:38:02.946254 [-4] AVG Duty = 4938%(X100)
7346 04:38:02.946351
7347 04:38:02.946431 ==DQ 1 ==
7348 04:38:02.949870 Final DQ duty delay cell = 0
7349 04:38:02.953062 [0] MAX Duty = 5156%(X100), DQS PI = 60
7350 04:38:02.956287 [0] MIN Duty = 5000%(X100), DQS PI = 14
7351 04:38:02.959496 [0] AVG Duty = 5078%(X100)
7352 04:38:02.959593
7353 04:38:02.963115 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7354 04:38:02.963192
7355 04:38:02.966269 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7356 04:38:02.969401 [DutyScan_Calibration_Flow] ====Done====
7357 04:38:02.969512 ==
7358 04:38:02.972485 Dram Type= 6, Freq= 0, CH_1, rank 0
7359 04:38:02.976102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7360 04:38:02.976179 ==
7361 04:38:02.979357 [Duty_Offset_Calibration]
7362 04:38:02.979471 B0:1 B1:-2 CA:0
7363 04:38:02.979534
7364 04:38:02.982778 [DutyScan_Calibration_Flow] k_type=0
7365 04:38:02.993799
7366 04:38:02.993875 ==CLK 0==
7367 04:38:02.997032 Final CLK duty delay cell = 0
7368 04:38:03.000131 [0] MAX Duty = 5031%(X100), DQS PI = 52
7369 04:38:03.003751 [0] MIN Duty = 4907%(X100), DQS PI = 10
7370 04:38:03.006791 [0] AVG Duty = 4969%(X100)
7371 04:38:03.006872
7372 04:38:03.010046 CH1 CLK Duty spec in!! Max-Min= 124%
7373 04:38:03.013442 [DutyScan_Calibration_Flow] ====Done====
7374 04:38:03.013523
7375 04:38:03.016545 [DutyScan_Calibration_Flow] k_type=1
7376 04:38:03.032576
7377 04:38:03.032666 ==DQS 0 ==
7378 04:38:03.035764 Final DQS duty delay cell = -4
7379 04:38:03.038720 [-4] MAX Duty = 4938%(X100), DQS PI = 56
7380 04:38:03.042143 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7381 04:38:03.045955 [-4] AVG Duty = 4891%(X100)
7382 04:38:03.046061
7383 04:38:03.046157 ==DQS 1 ==
7384 04:38:03.049208 Final DQS duty delay cell = 0
7385 04:38:03.052007 [0] MAX Duty = 5124%(X100), DQS PI = 28
7386 04:38:03.055530 [0] MIN Duty = 4813%(X100), DQS PI = 58
7387 04:38:03.059300 [0] AVG Duty = 4968%(X100)
7388 04:38:03.059422
7389 04:38:03.062266 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7390 04:38:03.062350
7391 04:38:03.065418 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7392 04:38:03.069100 [DutyScan_Calibration_Flow] ====Done====
7393 04:38:03.069181
7394 04:38:03.072250 [DutyScan_Calibration_Flow] k_type=3
7395 04:38:03.089449
7396 04:38:03.089545 ==DQM 0 ==
7397 04:38:03.092889 Final DQM duty delay cell = 0
7398 04:38:03.095832 [0] MAX Duty = 5000%(X100), DQS PI = 0
7399 04:38:03.099570 [0] MIN Duty = 4844%(X100), DQS PI = 22
7400 04:38:03.102856 [0] AVG Duty = 4922%(X100)
7401 04:38:03.102936
7402 04:38:03.103001 ==DQM 1 ==
7403 04:38:03.106018 Final DQM duty delay cell = 0
7404 04:38:03.109371 [0] MAX Duty = 5062%(X100), DQS PI = 4
7405 04:38:03.112746 [0] MIN Duty = 4844%(X100), DQS PI = 56
7406 04:38:03.112827 [0] AVG Duty = 4953%(X100)
7407 04:38:03.116507
7408 04:38:03.119633 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7409 04:38:03.119714
7410 04:38:03.122661 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7411 04:38:03.125819 [DutyScan_Calibration_Flow] ====Done====
7412 04:38:03.125900
7413 04:38:03.129171 [DutyScan_Calibration_Flow] k_type=2
7414 04:38:03.146047
7415 04:38:03.146132 ==DQ 0 ==
7416 04:38:03.149783 Final DQ duty delay cell = 0
7417 04:38:03.152802 [0] MAX Duty = 5062%(X100), DQS PI = 0
7418 04:38:03.156014 [0] MIN Duty = 4938%(X100), DQS PI = 14
7419 04:38:03.156095 [0] AVG Duty = 5000%(X100)
7420 04:38:03.159230
7421 04:38:03.159312 ==DQ 1 ==
7422 04:38:03.162514 Final DQ duty delay cell = 0
7423 04:38:03.166042 [0] MAX Duty = 5156%(X100), DQS PI = 24
7424 04:38:03.169578 [0] MIN Duty = 4938%(X100), DQS PI = 56
7425 04:38:03.169689 [0] AVG Duty = 5047%(X100)
7426 04:38:03.169788
7427 04:38:03.175944 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7428 04:38:03.176053
7429 04:38:03.179462 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7430 04:38:03.182360 [DutyScan_Calibration_Flow] ====Done====
7431 04:38:03.186040 nWR fixed to 30
7432 04:38:03.186123 [ModeRegInit_LP4] CH0 RK0
7433 04:38:03.189058 [ModeRegInit_LP4] CH0 RK1
7434 04:38:03.192515 [ModeRegInit_LP4] CH1 RK0
7435 04:38:03.196091 [ModeRegInit_LP4] CH1 RK1
7436 04:38:03.196170 match AC timing 5
7437 04:38:03.202449 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7438 04:38:03.205788 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7439 04:38:03.209217 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7440 04:38:03.215445 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7441 04:38:03.219081 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7442 04:38:03.219162 [MiockJmeterHQA]
7443 04:38:03.219227
7444 04:38:03.222245 [DramcMiockJmeter] u1RxGatingPI = 0
7445 04:38:03.225336 0 : 4257, 4029
7446 04:38:03.225419 4 : 4370, 4145
7447 04:38:03.228621 8 : 4258, 4029
7448 04:38:03.228703 12 : 4255, 4030
7449 04:38:03.228779 16 : 4368, 4142
7450 04:38:03.232155 20 : 4368, 4139
7451 04:38:03.232237 24 : 4257, 4029
7452 04:38:03.235729 28 : 4255, 4030
7453 04:38:03.235815 32 : 4252, 4027
7454 04:38:03.238897 36 : 4260, 4032
7455 04:38:03.238979 40 : 4257, 4030
7456 04:38:03.242444 44 : 4363, 4140
7457 04:38:03.242527 48 : 4258, 4030
7458 04:38:03.242593 52 : 4255, 4029
7459 04:38:03.245279 56 : 4258, 4032
7460 04:38:03.245361 60 : 4365, 4140
7461 04:38:03.249028 64 : 4252, 4030
7462 04:38:03.249110 68 : 4255, 4029
7463 04:38:03.252273 72 : 4255, 4029
7464 04:38:03.252439 76 : 4253, 4029
7465 04:38:03.252583 80 : 4254, 4030
7466 04:38:03.255345 84 : 4366, 4140
7467 04:38:03.255497 88 : 4365, 4140
7468 04:38:03.258581 92 : 4252, 4029
7469 04:38:03.258695 96 : 4363, 4140
7470 04:38:03.262406 100 : 4255, 4030
7471 04:38:03.262503 104 : 4253, 3677
7472 04:38:03.265397 108 : 4366, 5
7473 04:38:03.265509 112 : 4365, 0
7474 04:38:03.265606 116 : 4250, 0
7475 04:38:03.268853 120 : 4252, 0
7476 04:38:03.268961 124 : 4255, 0
7477 04:38:03.269060 128 : 4365, 0
7478 04:38:03.272236 132 : 4253, 0
7479 04:38:03.272345 136 : 4363, 0
7480 04:38:03.275641 140 : 4252, 0
7481 04:38:03.275750 144 : 4252, 0
7482 04:38:03.275848 148 : 4252, 0
7483 04:38:03.278870 152 : 4252, 0
7484 04:38:03.278962 156 : 4258, 0
7485 04:38:03.282279 160 : 4366, 0
7486 04:38:03.282374 164 : 4252, 0
7487 04:38:03.282472 168 : 4253, 0
7488 04:38:03.285563 172 : 4253, 0
7489 04:38:03.285645 176 : 4253, 0
7490 04:38:03.288722 180 : 4368, 0
7491 04:38:03.288804 184 : 4252, 0
7492 04:38:03.288870 188 : 4253, 0
7493 04:38:03.291834 192 : 4366, 0
7494 04:38:03.291942 196 : 4253, 0
7495 04:38:03.295511 200 : 4252, 0
7496 04:38:03.295593 204 : 4252, 0
7497 04:38:03.295684 208 : 4257, 0
7498 04:38:03.298494 212 : 4253, 0
7499 04:38:03.298575 216 : 4252, 0
7500 04:38:03.298650 220 : 4257, 0
7501 04:38:03.302218 224 : 4253, 0
7502 04:38:03.302300 228 : 4252, 0
7503 04:38:03.305245 232 : 4257, 0
7504 04:38:03.305354 236 : 4253, 1344
7505 04:38:03.308778 240 : 4255, 4029
7506 04:38:03.308860 244 : 4255, 4029
7507 04:38:03.311913 248 : 4366, 4139
7508 04:38:03.311995 252 : 4250, 4026
7509 04:38:03.312071 256 : 4253, 4029
7510 04:38:03.315003 260 : 4366, 4142
7511 04:38:03.315110 264 : 4255, 4029
7512 04:38:03.318708 268 : 4252, 4029
7513 04:38:03.318816 272 : 4253, 4029
7514 04:38:03.321749 276 : 4365, 4142
7515 04:38:03.321831 280 : 4253, 4030
7516 04:38:03.325423 284 : 4363, 4140
7517 04:38:03.325535 288 : 4363, 4140
7518 04:38:03.328569 292 : 4252, 4026
7519 04:38:03.328680 296 : 4254, 4029
7520 04:38:03.331893 300 : 4257, 4032
7521 04:38:03.331975 304 : 4253, 4029
7522 04:38:03.335144 308 : 4253, 4029
7523 04:38:03.335257 312 : 4255, 4029
7524 04:38:03.335352 316 : 4250, 4027
7525 04:38:03.338507 320 : 4250, 4026
7526 04:38:03.338620 324 : 4255, 4029
7527 04:38:03.341494 328 : 4255, 4029
7528 04:38:03.341577 332 : 4366, 4140
7529 04:38:03.345299 336 : 4250, 4026
7530 04:38:03.345391 340 : 4253, 4029
7531 04:38:03.348266 344 : 4368, 4142
7532 04:38:03.348348 348 : 4254, 4029
7533 04:38:03.351281 352 : 4365, 4131
7534 04:38:03.351423 356 : 4255, 2780
7535 04:38:03.354953 360 : 4253, 4
7536 04:38:03.355065
7537 04:38:03.355141 MIOCK jitter meter ch=0
7538 04:38:03.355235
7539 04:38:03.358432 1T = (360-108) = 252 dly cells
7540 04:38:03.364875 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7541 04:38:03.364957 ==
7542 04:38:03.368373 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 04:38:03.371492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 04:38:03.371598 ==
7545 04:38:03.378323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 04:38:03.381566 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 04:38:03.384875 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 04:38:03.391192 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 04:38:03.400922 [CA 0] Center 44 (14~75) winsize 62
7550 04:38:03.404489 [CA 1] Center 43 (13~74) winsize 62
7551 04:38:03.407497 [CA 2] Center 39 (10~69) winsize 60
7552 04:38:03.411084 [CA 3] Center 39 (10~68) winsize 59
7553 04:38:03.414264 [CA 4] Center 37 (8~67) winsize 60
7554 04:38:03.417252 [CA 5] Center 37 (7~67) winsize 61
7555 04:38:03.417345
7556 04:38:03.421058 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7557 04:38:03.421139
7558 04:38:03.427556 [CATrainingPosCal] consider 1 rank data
7559 04:38:03.427668 u2DelayCellTimex100 = 258/100 ps
7560 04:38:03.434355 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7561 04:38:03.437428 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7562 04:38:03.440610 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7563 04:38:03.444324 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7564 04:38:03.447153 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7565 04:38:03.450853 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7566 04:38:03.450934
7567 04:38:03.454008 CA PerBit enable=1, Macro0, CA PI delay=37
7568 04:38:03.454110
7569 04:38:03.457131 [CBTSetCACLKResult] CA Dly = 37
7570 04:38:03.461111 CS Dly: 11 (0~42)
7571 04:38:03.464045 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 04:38:03.467596 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 04:38:03.467678 ==
7574 04:38:03.470541 Dram Type= 6, Freq= 0, CH_0, rank 1
7575 04:38:03.477134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 04:38:03.477216 ==
7577 04:38:03.480991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7578 04:38:03.487047 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7579 04:38:03.490476 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7580 04:38:03.496683 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7581 04:38:03.505366 [CA 0] Center 44 (14~74) winsize 61
7582 04:38:03.508012 [CA 1] Center 43 (13~74) winsize 62
7583 04:38:03.511221 [CA 2] Center 39 (10~68) winsize 59
7584 04:38:03.514758 [CA 3] Center 39 (10~68) winsize 59
7585 04:38:03.518060 [CA 4] Center 36 (7~66) winsize 60
7586 04:38:03.521305 [CA 5] Center 36 (7~66) winsize 60
7587 04:38:03.521418
7588 04:38:03.524339 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7589 04:38:03.524437
7590 04:38:03.530995 [CATrainingPosCal] consider 2 rank data
7591 04:38:03.531083 u2DelayCellTimex100 = 258/100 ps
7592 04:38:03.537826 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7593 04:38:03.540832 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7594 04:38:03.544692 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7595 04:38:03.547774 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7596 04:38:03.550785 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7597 04:38:03.554347 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7598 04:38:03.554433
7599 04:38:03.558048 CA PerBit enable=1, Macro0, CA PI delay=36
7600 04:38:03.558132
7601 04:38:03.561176 [CBTSetCACLKResult] CA Dly = 36
7602 04:38:03.564415 CS Dly: 11 (0~43)
7603 04:38:03.567406 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7604 04:38:03.571185 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7605 04:38:03.571269
7606 04:38:03.574483 ----->DramcWriteLeveling(PI) begin...
7607 04:38:03.577486 ==
7608 04:38:03.577570 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 04:38:03.584339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 04:38:03.584424 ==
7611 04:38:03.587430 Write leveling (Byte 0): 35 => 35
7612 04:38:03.591119 Write leveling (Byte 1): 28 => 28
7613 04:38:03.593987 DramcWriteLeveling(PI) end<-----
7614 04:38:03.594072
7615 04:38:03.594139 ==
7616 04:38:03.597621 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 04:38:03.600867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 04:38:03.600951 ==
7619 04:38:03.604009 [Gating] SW mode calibration
7620 04:38:03.610445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7621 04:38:03.617180 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7622 04:38:03.620332 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 04:38:03.623935 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 04:38:03.630532 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 04:38:03.633730 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 04:38:03.637046 1 4 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7627 04:38:03.643565 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7628 04:38:03.646934 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7629 04:38:03.650471 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 04:38:03.653588 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 04:38:03.660196 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 04:38:03.663794 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 04:38:03.666895 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7634 04:38:03.673706 1 5 16 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7635 04:38:03.676836 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
7636 04:38:03.680619 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7637 04:38:03.686750 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 04:38:03.690214 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 04:38:03.693660 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 04:38:03.700212 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 04:38:03.703588 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 04:38:03.707295 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7643 04:38:03.713316 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7644 04:38:03.716882 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
7645 04:38:03.719999 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 04:38:03.726690 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 04:38:03.730154 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 04:38:03.733271 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 04:38:03.740091 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7650 04:38:03.743533 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7651 04:38:03.746926 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7652 04:38:03.753344 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7653 04:38:03.756619 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7654 04:38:03.760293 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 04:38:03.766721 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 04:38:03.769850 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 04:38:03.773070 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 04:38:03.780037 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 04:38:03.783151 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 04:38:03.786255 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 04:38:03.793193 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 04:38:03.796182 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 04:38:03.799716 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 04:38:03.806110 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 04:38:03.809598 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7666 04:38:03.812985 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7667 04:38:03.819675 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7668 04:38:03.819758 Total UI for P1: 0, mck2ui 16
7669 04:38:03.822701 best dqsien dly found for B0: ( 1, 9, 14)
7670 04:38:03.829419 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7671 04:38:03.832829 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 04:38:03.835922 Total UI for P1: 0, mck2ui 16
7673 04:38:03.839149 best dqsien dly found for B1: ( 1, 9, 22)
7674 04:38:03.842178 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7675 04:38:03.846002 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7676 04:38:03.846084
7677 04:38:03.849131 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7678 04:38:03.855522 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7679 04:38:03.855605 [Gating] SW calibration Done
7680 04:38:03.859228 ==
7681 04:38:03.859310 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 04:38:03.865804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 04:38:03.865887 ==
7684 04:38:03.865952 RX Vref Scan: 0
7685 04:38:03.866013
7686 04:38:03.868925 RX Vref 0 -> 0, step: 1
7687 04:38:03.869037
7688 04:38:03.872478 RX Delay 0 -> 252, step: 8
7689 04:38:03.875749 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7690 04:38:03.878638 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7691 04:38:03.881866 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7692 04:38:03.888902 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7693 04:38:03.891818 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7694 04:38:03.895500 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7695 04:38:03.899044 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7696 04:38:03.902060 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7697 04:38:03.908673 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7698 04:38:03.912218 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7699 04:38:03.915580 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7700 04:38:03.918911 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7701 04:38:03.921785 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7702 04:38:03.928898 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7703 04:38:03.931906 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7704 04:38:03.935118 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7705 04:38:03.935227 ==
7706 04:38:03.938358 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 04:38:03.942044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 04:38:03.942127 ==
7709 04:38:03.945639 DQS Delay:
7710 04:38:03.945716 DQS0 = 0, DQS1 = 0
7711 04:38:03.948452 DQM Delay:
7712 04:38:03.948532 DQM0 = 127, DQM1 = 124
7713 04:38:03.952072 DQ Delay:
7714 04:38:03.955134 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7715 04:38:03.958674 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =143
7716 04:38:03.961730 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7717 04:38:03.965258 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7718 04:38:03.965334
7719 04:38:03.965411
7720 04:38:03.965498 ==
7721 04:38:03.968119 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 04:38:03.971564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 04:38:03.971662 ==
7724 04:38:03.971752
7725 04:38:03.971838
7726 04:38:03.975232 TX Vref Scan disable
7727 04:38:03.978575 == TX Byte 0 ==
7728 04:38:03.982135 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7729 04:38:03.985248 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7730 04:38:03.988213 == TX Byte 1 ==
7731 04:38:03.991574 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7732 04:38:03.995568 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7733 04:38:03.995667 ==
7734 04:38:03.998295 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 04:38:04.004976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 04:38:04.005058 ==
7737 04:38:04.017383
7738 04:38:04.020186 TX Vref early break, caculate TX vref
7739 04:38:04.023676 TX Vref=16, minBit 8, minWin=21, winSum=360
7740 04:38:04.027080 TX Vref=18, minBit 11, minWin=21, winSum=366
7741 04:38:04.030254 TX Vref=20, minBit 1, minWin=23, winSum=377
7742 04:38:04.033684 TX Vref=22, minBit 8, minWin=23, winSum=386
7743 04:38:04.036710 TX Vref=24, minBit 4, minWin=24, winSum=396
7744 04:38:04.043241 TX Vref=26, minBit 4, minWin=24, winSum=405
7745 04:38:04.046691 TX Vref=28, minBit 3, minWin=25, winSum=407
7746 04:38:04.050079 TX Vref=30, minBit 8, minWin=23, winSum=398
7747 04:38:04.053637 TX Vref=32, minBit 8, minWin=23, winSum=389
7748 04:38:04.056655 TX Vref=34, minBit 8, minWin=21, winSum=378
7749 04:38:04.063305 [TxChooseVref] Worse bit 3, Min win 25, Win sum 407, Final Vref 28
7750 04:38:04.063429
7751 04:38:04.066998 Final TX Range 0 Vref 28
7752 04:38:04.067080
7753 04:38:04.067145 ==
7754 04:38:04.070096 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 04:38:04.073087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 04:38:04.073169 ==
7757 04:38:04.073235
7758 04:38:04.073295
7759 04:38:04.076584 TX Vref Scan disable
7760 04:38:04.083143 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7761 04:38:04.083225 == TX Byte 0 ==
7762 04:38:04.086419 u2DelayCellOfst[0]=18 cells (5 PI)
7763 04:38:04.089877 u2DelayCellOfst[1]=18 cells (5 PI)
7764 04:38:04.093009 u2DelayCellOfst[2]=15 cells (4 PI)
7765 04:38:04.096407 u2DelayCellOfst[3]=15 cells (4 PI)
7766 04:38:04.099743 u2DelayCellOfst[4]=11 cells (3 PI)
7767 04:38:04.103026 u2DelayCellOfst[5]=0 cells (0 PI)
7768 04:38:04.106119 u2DelayCellOfst[6]=22 cells (6 PI)
7769 04:38:04.109804 u2DelayCellOfst[7]=22 cells (6 PI)
7770 04:38:04.112813 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7771 04:38:04.116069 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7772 04:38:04.119544 == TX Byte 1 ==
7773 04:38:04.122931 u2DelayCellOfst[8]=0 cells (0 PI)
7774 04:38:04.126634 u2DelayCellOfst[9]=3 cells (1 PI)
7775 04:38:04.126716 u2DelayCellOfst[10]=7 cells (2 PI)
7776 04:38:04.129527 u2DelayCellOfst[11]=7 cells (2 PI)
7777 04:38:04.132909 u2DelayCellOfst[12]=15 cells (4 PI)
7778 04:38:04.135856 u2DelayCellOfst[13]=11 cells (3 PI)
7779 04:38:04.139445 u2DelayCellOfst[14]=15 cells (4 PI)
7780 04:38:04.142536 u2DelayCellOfst[15]=11 cells (3 PI)
7781 04:38:04.149318 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7782 04:38:04.152344 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7783 04:38:04.152452 DramC Write-DBI on
7784 04:38:04.152545 ==
7785 04:38:04.155977 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 04:38:04.162599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 04:38:04.162683 ==
7788 04:38:04.162785
7789 04:38:04.162846
7790 04:38:04.165623 TX Vref Scan disable
7791 04:38:04.165704 == TX Byte 0 ==
7792 04:38:04.172063 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7793 04:38:04.172146 == TX Byte 1 ==
7794 04:38:04.175917 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7795 04:38:04.179057 DramC Write-DBI off
7796 04:38:04.179157
7797 04:38:04.179273 [DATLAT]
7798 04:38:04.182084 Freq=1600, CH0 RK0
7799 04:38:04.182166
7800 04:38:04.182259 DATLAT Default: 0xf
7801 04:38:04.185641 0, 0xFFFF, sum = 0
7802 04:38:04.185725 1, 0xFFFF, sum = 0
7803 04:38:04.188545 2, 0xFFFF, sum = 0
7804 04:38:04.188628 3, 0xFFFF, sum = 0
7805 04:38:04.192124 4, 0xFFFF, sum = 0
7806 04:38:04.192221 5, 0xFFFF, sum = 0
7807 04:38:04.195724 6, 0xFFFF, sum = 0
7808 04:38:04.198582 7, 0xFFFF, sum = 0
7809 04:38:04.198665 8, 0xFFFF, sum = 0
7810 04:38:04.201750 9, 0xFFFF, sum = 0
7811 04:38:04.201834 10, 0xFFFF, sum = 0
7812 04:38:04.205362 11, 0xFFFF, sum = 0
7813 04:38:04.205445 12, 0xFFFF, sum = 0
7814 04:38:04.208665 13, 0xFFFF, sum = 0
7815 04:38:04.208747 14, 0x0, sum = 1
7816 04:38:04.211626 15, 0x0, sum = 2
7817 04:38:04.211709 16, 0x0, sum = 3
7818 04:38:04.214983 17, 0x0, sum = 4
7819 04:38:04.215065 best_step = 15
7820 04:38:04.215153
7821 04:38:04.215243 ==
7822 04:38:04.218528 Dram Type= 6, Freq= 0, CH_0, rank 0
7823 04:38:04.221688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7824 04:38:04.225251 ==
7825 04:38:04.225333 RX Vref Scan: 1
7826 04:38:04.225420
7827 04:38:04.228159 Set Vref Range= 24 -> 127
7828 04:38:04.228266
7829 04:38:04.228361 RX Vref 24 -> 127, step: 1
7830 04:38:04.231691
7831 04:38:04.231773 RX Delay 11 -> 252, step: 4
7832 04:38:04.231839
7833 04:38:04.234643 Set Vref, RX VrefLevel [Byte0]: 24
7834 04:38:04.238271 [Byte1]: 24
7835 04:38:04.241890
7836 04:38:04.241971 Set Vref, RX VrefLevel [Byte0]: 25
7837 04:38:04.244998 [Byte1]: 25
7838 04:38:04.249774
7839 04:38:04.249883 Set Vref, RX VrefLevel [Byte0]: 26
7840 04:38:04.252940 [Byte1]: 26
7841 04:38:04.257094
7842 04:38:04.257202 Set Vref, RX VrefLevel [Byte0]: 27
7843 04:38:04.260374 [Byte1]: 27
7844 04:38:04.264788
7845 04:38:04.264869 Set Vref, RX VrefLevel [Byte0]: 28
7846 04:38:04.271227 [Byte1]: 28
7847 04:38:04.271335
7848 04:38:04.274845 Set Vref, RX VrefLevel [Byte0]: 29
7849 04:38:04.278012 [Byte1]: 29
7850 04:38:04.278094
7851 04:38:04.280971 Set Vref, RX VrefLevel [Byte0]: 30
7852 04:38:04.284713 [Byte1]: 30
7853 04:38:04.287784
7854 04:38:04.287865 Set Vref, RX VrefLevel [Byte0]: 31
7855 04:38:04.290749 [Byte1]: 31
7856 04:38:04.295248
7857 04:38:04.295330 Set Vref, RX VrefLevel [Byte0]: 32
7858 04:38:04.298750 [Byte1]: 32
7859 04:38:04.302851
7860 04:38:04.302932 Set Vref, RX VrefLevel [Byte0]: 33
7861 04:38:04.306260 [Byte1]: 33
7862 04:38:04.310433
7863 04:38:04.310515 Set Vref, RX VrefLevel [Byte0]: 34
7864 04:38:04.313531 [Byte1]: 34
7865 04:38:04.318585
7866 04:38:04.318666 Set Vref, RX VrefLevel [Byte0]: 35
7867 04:38:04.321234 [Byte1]: 35
7868 04:38:04.325569
7869 04:38:04.325650 Set Vref, RX VrefLevel [Byte0]: 36
7870 04:38:04.329102 [Byte1]: 36
7871 04:38:04.333135
7872 04:38:04.333229 Set Vref, RX VrefLevel [Byte0]: 37
7873 04:38:04.336521 [Byte1]: 37
7874 04:38:04.341184
7875 04:38:04.341287 Set Vref, RX VrefLevel [Byte0]: 38
7876 04:38:04.344182 [Byte1]: 38
7877 04:38:04.348614
7878 04:38:04.348723 Set Vref, RX VrefLevel [Byte0]: 39
7879 04:38:04.351521 [Byte1]: 39
7880 04:38:04.356300
7881 04:38:04.356407 Set Vref, RX VrefLevel [Byte0]: 40
7882 04:38:04.359667 [Byte1]: 40
7883 04:38:04.363453
7884 04:38:04.363543 Set Vref, RX VrefLevel [Byte0]: 41
7885 04:38:04.367188 [Byte1]: 41
7886 04:38:04.371512
7887 04:38:04.371607 Set Vref, RX VrefLevel [Byte0]: 42
7888 04:38:04.374470 [Byte1]: 42
7889 04:38:04.379013
7890 04:38:04.379124 Set Vref, RX VrefLevel [Byte0]: 43
7891 04:38:04.382148 [Byte1]: 43
7892 04:38:04.386482
7893 04:38:04.386563 Set Vref, RX VrefLevel [Byte0]: 44
7894 04:38:04.389832 [Byte1]: 44
7895 04:38:04.394131
7896 04:38:04.394240 Set Vref, RX VrefLevel [Byte0]: 45
7897 04:38:04.397177 [Byte1]: 45
7898 04:38:04.401942
7899 04:38:04.402024 Set Vref, RX VrefLevel [Byte0]: 46
7900 04:38:04.405002 [Byte1]: 46
7901 04:38:04.409826
7902 04:38:04.409908 Set Vref, RX VrefLevel [Byte0]: 47
7903 04:38:04.412639 [Byte1]: 47
7904 04:38:04.416985
7905 04:38:04.417096 Set Vref, RX VrefLevel [Byte0]: 48
7906 04:38:04.420176 [Byte1]: 48
7907 04:38:04.424479
7908 04:38:04.424561 Set Vref, RX VrefLevel [Byte0]: 49
7909 04:38:04.428356 [Byte1]: 49
7910 04:38:04.431990
7911 04:38:04.432074 Set Vref, RX VrefLevel [Byte0]: 50
7912 04:38:04.436024 [Byte1]: 50
7913 04:38:04.439655
7914 04:38:04.439826 Set Vref, RX VrefLevel [Byte0]: 51
7915 04:38:04.443080 [Byte1]: 51
7916 04:38:04.447352
7917 04:38:04.447456 Set Vref, RX VrefLevel [Byte0]: 52
7918 04:38:04.450531 [Byte1]: 52
7919 04:38:04.455119
7920 04:38:04.455239 Set Vref, RX VrefLevel [Byte0]: 53
7921 04:38:04.458498 [Byte1]: 53
7922 04:38:04.462699
7923 04:38:04.462823 Set Vref, RX VrefLevel [Byte0]: 54
7924 04:38:04.466072 [Byte1]: 54
7925 04:38:04.470578
7926 04:38:04.470657 Set Vref, RX VrefLevel [Byte0]: 55
7927 04:38:04.473615 [Byte1]: 55
7928 04:38:04.478331
7929 04:38:04.478442 Set Vref, RX VrefLevel [Byte0]: 56
7930 04:38:04.480971 [Byte1]: 56
7931 04:38:04.485615
7932 04:38:04.485723 Set Vref, RX VrefLevel [Byte0]: 57
7933 04:38:04.489117 [Byte1]: 57
7934 04:38:04.493453
7935 04:38:04.493550 Set Vref, RX VrefLevel [Byte0]: 58
7936 04:38:04.496601 [Byte1]: 58
7937 04:38:04.500963
7938 04:38:04.501046 Set Vref, RX VrefLevel [Byte0]: 59
7939 04:38:04.503950 [Byte1]: 59
7940 04:38:04.508152
7941 04:38:04.508278 Set Vref, RX VrefLevel [Byte0]: 60
7942 04:38:04.512058 [Byte1]: 60
7943 04:38:04.515954
7944 04:38:04.516036 Set Vref, RX VrefLevel [Byte0]: 61
7945 04:38:04.519333 [Byte1]: 61
7946 04:38:04.523536
7947 04:38:04.523617 Set Vref, RX VrefLevel [Byte0]: 62
7948 04:38:04.527120 [Byte1]: 62
7949 04:38:04.531334
7950 04:38:04.531435 Set Vref, RX VrefLevel [Byte0]: 63
7951 04:38:04.534330 [Byte1]: 63
7952 04:38:04.539182
7953 04:38:04.539264 Set Vref, RX VrefLevel [Byte0]: 64
7954 04:38:04.542196 [Byte1]: 64
7955 04:38:04.546321
7956 04:38:04.546431 Set Vref, RX VrefLevel [Byte0]: 65
7957 04:38:04.549967 [Byte1]: 65
7958 04:38:04.553722
7959 04:38:04.553805 Set Vref, RX VrefLevel [Byte0]: 66
7960 04:38:04.557135 [Byte1]: 66
7961 04:38:04.561966
7962 04:38:04.562078 Set Vref, RX VrefLevel [Byte0]: 67
7963 04:38:04.564784 [Byte1]: 67
7964 04:38:04.569051
7965 04:38:04.569135 Set Vref, RX VrefLevel [Byte0]: 68
7966 04:38:04.572337 [Byte1]: 68
7967 04:38:04.576923
7968 04:38:04.577009 Set Vref, RX VrefLevel [Byte0]: 69
7969 04:38:04.580484 [Byte1]: 69
7970 04:38:04.584678
7971 04:38:04.584762 Set Vref, RX VrefLevel [Byte0]: 70
7972 04:38:04.587479 [Byte1]: 70
7973 04:38:04.591822
7974 04:38:04.591906 Set Vref, RX VrefLevel [Byte0]: 71
7975 04:38:04.595480 [Byte1]: 71
7976 04:38:04.599908
7977 04:38:04.599991 Set Vref, RX VrefLevel [Byte0]: 72
7978 04:38:04.603022 [Byte1]: 72
7979 04:38:04.607549
7980 04:38:04.607632 Set Vref, RX VrefLevel [Byte0]: 73
7981 04:38:04.610398 [Byte1]: 73
7982 04:38:04.614726
7983 04:38:04.614809 Set Vref, RX VrefLevel [Byte0]: 74
7984 04:38:04.617913 [Byte1]: 74
7985 04:38:04.622760
7986 04:38:04.622843 Final RX Vref Byte 0 = 63 to rank0
7987 04:38:04.625701 Final RX Vref Byte 1 = 60 to rank0
7988 04:38:04.629032 Final RX Vref Byte 0 = 63 to rank1
7989 04:38:04.632148 Final RX Vref Byte 1 = 60 to rank1==
7990 04:38:04.635776 Dram Type= 6, Freq= 0, CH_0, rank 0
7991 04:38:04.642589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 04:38:04.642672 ==
7993 04:38:04.642739 DQS Delay:
7994 04:38:04.645660 DQS0 = 0, DQS1 = 0
7995 04:38:04.645743 DQM Delay:
7996 04:38:04.645824 DQM0 = 126, DQM1 = 120
7997 04:38:04.648884 DQ Delay:
7998 04:38:04.652505 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7999 04:38:04.655486 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8000 04:38:04.659037 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8001 04:38:04.662168 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8002 04:38:04.662250
8003 04:38:04.662316
8004 04:38:04.662423
8005 04:38:04.665349 [DramC_TX_OE_Calibration] TA2
8006 04:38:04.668806 Original DQ_B0 (3 6) =30, OEN = 27
8007 04:38:04.672456 Original DQ_B1 (3 6) =30, OEN = 27
8008 04:38:04.675659 24, 0x0, End_B0=24 End_B1=24
8009 04:38:04.675790 25, 0x0, End_B0=25 End_B1=25
8010 04:38:04.678633 26, 0x0, End_B0=26 End_B1=26
8011 04:38:04.682270 27, 0x0, End_B0=27 End_B1=27
8012 04:38:04.685359 28, 0x0, End_B0=28 End_B1=28
8013 04:38:04.688595 29, 0x0, End_B0=29 End_B1=29
8014 04:38:04.688678 30, 0x0, End_B0=30 End_B1=30
8015 04:38:04.692109 31, 0x4141, End_B0=30 End_B1=30
8016 04:38:04.695621 Byte0 end_step=30 best_step=27
8017 04:38:04.698763 Byte1 end_step=30 best_step=27
8018 04:38:04.701809 Byte0 TX OE(2T, 0.5T) = (3, 3)
8019 04:38:04.705050 Byte1 TX OE(2T, 0.5T) = (3, 3)
8020 04:38:04.705132
8021 04:38:04.705197
8022 04:38:04.711982 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8023 04:38:04.715576 CH0 RK0: MR19=303, MR18=1414
8024 04:38:04.721639 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
8025 04:38:04.721725
8026 04:38:04.725194 ----->DramcWriteLeveling(PI) begin...
8027 04:38:04.725308 ==
8028 04:38:04.728226 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 04:38:04.731814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 04:38:04.731899 ==
8031 04:38:04.735129 Write leveling (Byte 0): 35 => 35
8032 04:38:04.738568 Write leveling (Byte 1): 27 => 27
8033 04:38:04.741580 DramcWriteLeveling(PI) end<-----
8034 04:38:04.741664
8035 04:38:04.741730 ==
8036 04:38:04.745384 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 04:38:04.748387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 04:38:04.748471 ==
8039 04:38:04.751602 [Gating] SW mode calibration
8040 04:38:04.758051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8041 04:38:04.764766 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8042 04:38:04.768399 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 04:38:04.774926 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 04:38:04.777906 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 04:38:04.781369 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8046 04:38:04.788176 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8047 04:38:04.791521 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8048 04:38:04.794636 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 04:38:04.801558 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 04:38:04.804697 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 04:38:04.807922 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 04:38:04.814663 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 04:38:04.817955 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
8054 04:38:04.821102 1 5 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8055 04:38:04.824378 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8056 04:38:04.830951 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 04:38:04.834577 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 04:38:04.837646 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 04:38:04.844406 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 04:38:04.848051 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8061 04:38:04.851071 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8062 04:38:04.857610 1 6 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8063 04:38:04.861302 1 6 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8064 04:38:04.864342 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 04:38:04.870946 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 04:38:04.874528 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 04:38:04.877636 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 04:38:04.883795 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8069 04:38:04.887362 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8070 04:38:04.890770 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8071 04:38:04.897186 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8072 04:38:04.900614 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8073 04:38:04.903642 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 04:38:04.910218 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 04:38:04.913756 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 04:38:04.916865 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 04:38:04.924002 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 04:38:04.927282 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 04:38:04.930864 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 04:38:04.936990 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 04:38:04.940295 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 04:38:04.943467 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 04:38:04.950164 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 04:38:04.953602 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8085 04:38:04.956934 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8086 04:38:04.963713 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8087 04:38:04.963795 Total UI for P1: 0, mck2ui 16
8088 04:38:04.970122 best dqsien dly found for B0: ( 1, 9, 10)
8089 04:38:04.973718 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 04:38:04.976666 Total UI for P1: 0, mck2ui 16
8091 04:38:04.980473 best dqsien dly found for B1: ( 1, 9, 18)
8092 04:38:04.983496 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8093 04:38:04.986653 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8094 04:38:04.986737
8095 04:38:04.990405 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8096 04:38:04.993491 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8097 04:38:04.996657 [Gating] SW calibration Done
8098 04:38:04.996741 ==
8099 04:38:04.999766 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 04:38:05.003243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 04:38:05.006686 ==
8102 04:38:05.006761 RX Vref Scan: 0
8103 04:38:05.006823
8104 04:38:05.010160 RX Vref 0 -> 0, step: 1
8105 04:38:05.010242
8106 04:38:05.013256 RX Delay 0 -> 252, step: 8
8107 04:38:05.016647 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8108 04:38:05.019617 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8109 04:38:05.023286 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8110 04:38:05.026278 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8111 04:38:05.032918 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8112 04:38:05.036611 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8113 04:38:05.039644 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8114 04:38:05.043448 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8115 04:38:05.046775 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8116 04:38:05.049921 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8117 04:38:05.056596 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8118 04:38:05.059584 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8119 04:38:05.062865 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8120 04:38:05.066456 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8121 04:38:05.072850 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8122 04:38:05.076037 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8123 04:38:05.076131 ==
8124 04:38:05.079435 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 04:38:05.082956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 04:38:05.083072 ==
8127 04:38:05.086044 DQS Delay:
8128 04:38:05.086125 DQS0 = 0, DQS1 = 0
8129 04:38:05.086190 DQM Delay:
8130 04:38:05.089765 DQM0 = 127, DQM1 = 122
8131 04:38:05.089872 DQ Delay:
8132 04:38:05.092957 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8133 04:38:05.096125 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8134 04:38:05.099459 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8135 04:38:05.106220 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8136 04:38:05.106302
8137 04:38:05.106368
8138 04:38:05.106441 ==
8139 04:38:05.109260 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 04:38:05.112866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 04:38:05.112940 ==
8142 04:38:05.113004
8143 04:38:05.113063
8144 04:38:05.116276 TX Vref Scan disable
8145 04:38:05.116352 == TX Byte 0 ==
8146 04:38:05.122843 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8147 04:38:05.125972 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8148 04:38:05.129167 == TX Byte 1 ==
8149 04:38:05.132455 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8150 04:38:05.135686 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8151 04:38:05.135768 ==
8152 04:38:05.139361 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 04:38:05.142350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 04:38:05.145407 ==
8155 04:38:05.158488
8156 04:38:05.162125 TX Vref early break, caculate TX vref
8157 04:38:05.165055 TX Vref=16, minBit 8, minWin=21, winSum=368
8158 04:38:05.168757 TX Vref=18, minBit 8, minWin=22, winSum=374
8159 04:38:05.171785 TX Vref=20, minBit 2, minWin=23, winSum=383
8160 04:38:05.175169 TX Vref=22, minBit 0, minWin=24, winSum=391
8161 04:38:05.178313 TX Vref=24, minBit 8, minWin=24, winSum=401
8162 04:38:05.185111 TX Vref=26, minBit 8, minWin=24, winSum=405
8163 04:38:05.188072 TX Vref=28, minBit 13, minWin=24, winSum=408
8164 04:38:05.191418 TX Vref=30, minBit 8, minWin=24, winSum=410
8165 04:38:05.194957 TX Vref=32, minBit 4, minWin=24, winSum=397
8166 04:38:05.198259 TX Vref=34, minBit 8, minWin=22, winSum=389
8167 04:38:05.204433 TX Vref=36, minBit 8, minWin=22, winSum=376
8168 04:38:05.208127 [TxChooseVref] Worse bit 8, Min win 24, Win sum 410, Final Vref 30
8169 04:38:05.208210
8170 04:38:05.211241 Final TX Range 0 Vref 30
8171 04:38:05.211323
8172 04:38:05.211415 ==
8173 04:38:05.214655 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 04:38:05.218071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 04:38:05.220969 ==
8176 04:38:05.221051
8177 04:38:05.221115
8178 04:38:05.221176 TX Vref Scan disable
8179 04:38:05.227902 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8180 04:38:05.227995 == TX Byte 0 ==
8181 04:38:05.231310 u2DelayCellOfst[0]=11 cells (3 PI)
8182 04:38:05.235068 u2DelayCellOfst[1]=18 cells (5 PI)
8183 04:38:05.238168 u2DelayCellOfst[2]=11 cells (3 PI)
8184 04:38:05.241410 u2DelayCellOfst[3]=11 cells (3 PI)
8185 04:38:05.244650 u2DelayCellOfst[4]=7 cells (2 PI)
8186 04:38:05.248160 u2DelayCellOfst[5]=0 cells (0 PI)
8187 04:38:05.250966 u2DelayCellOfst[6]=18 cells (5 PI)
8188 04:38:05.254184 u2DelayCellOfst[7]=15 cells (4 PI)
8189 04:38:05.258034 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8190 04:38:05.261022 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8191 04:38:05.264045 == TX Byte 1 ==
8192 04:38:05.267247 u2DelayCellOfst[8]=0 cells (0 PI)
8193 04:38:05.270992 u2DelayCellOfst[9]=0 cells (0 PI)
8194 04:38:05.273963 u2DelayCellOfst[10]=7 cells (2 PI)
8195 04:38:05.277550 u2DelayCellOfst[11]=3 cells (1 PI)
8196 04:38:05.280846 u2DelayCellOfst[12]=11 cells (3 PI)
8197 04:38:05.283908 u2DelayCellOfst[13]=11 cells (3 PI)
8198 04:38:05.286991 u2DelayCellOfst[14]=18 cells (5 PI)
8199 04:38:05.290512 u2DelayCellOfst[15]=15 cells (4 PI)
8200 04:38:05.293877 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8201 04:38:05.297117 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8202 04:38:05.300927 DramC Write-DBI on
8203 04:38:05.301005 ==
8204 04:38:05.303788 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 04:38:05.307491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 04:38:05.307567 ==
8207 04:38:05.307630
8208 04:38:05.307688
8209 04:38:05.310641 TX Vref Scan disable
8210 04:38:05.310714 == TX Byte 0 ==
8211 04:38:05.317045 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8212 04:38:05.317121 == TX Byte 1 ==
8213 04:38:05.320518 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8214 04:38:05.323510 DramC Write-DBI off
8215 04:38:05.323611
8216 04:38:05.323701 [DATLAT]
8217 04:38:05.327148 Freq=1600, CH0 RK1
8218 04:38:05.327221
8219 04:38:05.330106 DATLAT Default: 0xf
8220 04:38:05.330180 0, 0xFFFF, sum = 0
8221 04:38:05.333324 1, 0xFFFF, sum = 0
8222 04:38:05.333400 2, 0xFFFF, sum = 0
8223 04:38:05.337015 3, 0xFFFF, sum = 0
8224 04:38:05.337119 4, 0xFFFF, sum = 0
8225 04:38:05.340170 5, 0xFFFF, sum = 0
8226 04:38:05.340279 6, 0xFFFF, sum = 0
8227 04:38:05.343572 7, 0xFFFF, sum = 0
8228 04:38:05.343649 8, 0xFFFF, sum = 0
8229 04:38:05.346602 9, 0xFFFF, sum = 0
8230 04:38:05.346677 10, 0xFFFF, sum = 0
8231 04:38:05.350300 11, 0xFFFF, sum = 0
8232 04:38:05.350376 12, 0xFFFF, sum = 0
8233 04:38:05.353263 13, 0xCFFF, sum = 0
8234 04:38:05.353373 14, 0x0, sum = 1
8235 04:38:05.356960 15, 0x0, sum = 2
8236 04:38:05.357043 16, 0x0, sum = 3
8237 04:38:05.360037 17, 0x0, sum = 4
8238 04:38:05.360146 best_step = 15
8239 04:38:05.360239
8240 04:38:05.360327 ==
8241 04:38:05.363523 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 04:38:05.369739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 04:38:05.369822 ==
8244 04:38:05.369887 RX Vref Scan: 0
8245 04:38:05.369978
8246 04:38:05.373294 RX Vref 0 -> 0, step: 1
8247 04:38:05.373375
8248 04:38:05.376362 RX Delay 3 -> 252, step: 4
8249 04:38:05.380104 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8250 04:38:05.382953 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8251 04:38:05.386661 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8252 04:38:05.393676 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8253 04:38:05.396669 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8254 04:38:05.399715 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8255 04:38:05.403237 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8256 04:38:05.406146 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8257 04:38:05.412804 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8258 04:38:05.416505 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8259 04:38:05.419559 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8260 04:38:05.423228 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8261 04:38:05.426281 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8262 04:38:05.432942 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8263 04:38:05.436436 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8264 04:38:05.439803 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8265 04:38:05.439889 ==
8266 04:38:05.442810 Dram Type= 6, Freq= 0, CH_0, rank 1
8267 04:38:05.446637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 04:38:05.449566 ==
8269 04:38:05.449649 DQS Delay:
8270 04:38:05.449730 DQS0 = 0, DQS1 = 0
8271 04:38:05.452693 DQM Delay:
8272 04:38:05.452777 DQM0 = 124, DQM1 = 118
8273 04:38:05.456346 DQ Delay:
8274 04:38:05.459589 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8275 04:38:05.462724 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8276 04:38:05.465749 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8277 04:38:05.469473 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8278 04:38:05.469557
8279 04:38:05.469623
8280 04:38:05.469685
8281 04:38:05.472694 [DramC_TX_OE_Calibration] TA2
8282 04:38:05.476166 Original DQ_B0 (3 6) =30, OEN = 27
8283 04:38:05.479281 Original DQ_B1 (3 6) =30, OEN = 27
8284 04:38:05.482389 24, 0x0, End_B0=24 End_B1=24
8285 04:38:05.482473 25, 0x0, End_B0=25 End_B1=25
8286 04:38:05.485907 26, 0x0, End_B0=26 End_B1=26
8287 04:38:05.489122 27, 0x0, End_B0=27 End_B1=27
8288 04:38:05.492780 28, 0x0, End_B0=28 End_B1=28
8289 04:38:05.492864 29, 0x0, End_B0=29 End_B1=29
8290 04:38:05.495983 30, 0x0, End_B0=30 End_B1=30
8291 04:38:05.499085 31, 0x4141, End_B0=30 End_B1=30
8292 04:38:05.502245 Byte0 end_step=30 best_step=27
8293 04:38:05.506045 Byte1 end_step=30 best_step=27
8294 04:38:05.509287 Byte0 TX OE(2T, 0.5T) = (3, 3)
8295 04:38:05.509370 Byte1 TX OE(2T, 0.5T) = (3, 3)
8296 04:38:05.512104
8297 04:38:05.512187
8298 04:38:05.519133 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8299 04:38:05.522141 CH0 RK1: MR19=303, MR18=2310
8300 04:38:05.529117 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8301 04:38:05.532203 [RxdqsGatingPostProcess] freq 1600
8302 04:38:05.535500 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8303 04:38:05.538537 best DQS0 dly(2T, 0.5T) = (1, 1)
8304 04:38:05.542178 best DQS1 dly(2T, 0.5T) = (1, 1)
8305 04:38:05.545597 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8306 04:38:05.549068 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8307 04:38:05.552133 best DQS0 dly(2T, 0.5T) = (1, 1)
8308 04:38:05.555499 best DQS1 dly(2T, 0.5T) = (1, 1)
8309 04:38:05.558805 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8310 04:38:05.562243 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8311 04:38:05.565530 Pre-setting of DQS Precalculation
8312 04:38:05.568777 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8313 04:38:05.568876 ==
8314 04:38:05.571721 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 04:38:05.575320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 04:38:05.575458 ==
8317 04:38:05.581987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 04:38:05.585094 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 04:38:05.592133 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 04:38:05.595242 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 04:38:05.605497 [CA 0] Center 41 (13~70) winsize 58
8322 04:38:05.608534 [CA 1] Center 42 (12~72) winsize 61
8323 04:38:05.612276 [CA 2] Center 37 (8~66) winsize 59
8324 04:38:05.615118 [CA 3] Center 36 (7~66) winsize 60
8325 04:38:05.618513 [CA 4] Center 37 (8~67) winsize 60
8326 04:38:05.621835 [CA 5] Center 36 (7~66) winsize 60
8327 04:38:05.621990
8328 04:38:05.625056 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8329 04:38:05.625128
8330 04:38:05.628695 [CATrainingPosCal] consider 1 rank data
8331 04:38:05.631788 u2DelayCellTimex100 = 258/100 ps
8332 04:38:05.634851 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8333 04:38:05.641826 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8334 04:38:05.644869 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8335 04:38:05.648538 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8336 04:38:05.651501 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8337 04:38:05.655155 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8338 04:38:05.655252
8339 04:38:05.658484 CA PerBit enable=1, Macro0, CA PI delay=36
8340 04:38:05.658576
8341 04:38:05.661273 [CBTSetCACLKResult] CA Dly = 36
8342 04:38:05.664619 CS Dly: 9 (0~40)
8343 04:38:05.668171 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 04:38:05.671228 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 04:38:05.671344 ==
8346 04:38:05.674901 Dram Type= 6, Freq= 0, CH_1, rank 1
8347 04:38:05.678055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 04:38:05.681316 ==
8349 04:38:05.684485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8350 04:38:05.688096 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8351 04:38:05.694493 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8352 04:38:05.701131 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8353 04:38:05.708329 [CA 0] Center 42 (13~71) winsize 59
8354 04:38:05.712247 [CA 1] Center 42 (12~72) winsize 61
8355 04:38:05.715104 [CA 2] Center 38 (9~68) winsize 60
8356 04:38:05.718597 [CA 3] Center 36 (7~66) winsize 60
8357 04:38:05.721656 [CA 4] Center 37 (8~67) winsize 60
8358 04:38:05.725061 [CA 5] Center 36 (7~66) winsize 60
8359 04:38:05.725146
8360 04:38:05.728582 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8361 04:38:05.728659
8362 04:38:05.731333 [CATrainingPosCal] consider 2 rank data
8363 04:38:05.734942 u2DelayCellTimex100 = 258/100 ps
8364 04:38:05.737996 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8365 04:38:05.745044 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8366 04:38:05.748142 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8367 04:38:05.751778 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8368 04:38:05.754806 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8369 04:38:05.758369 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8370 04:38:05.758457
8371 04:38:05.761397 CA PerBit enable=1, Macro0, CA PI delay=36
8372 04:38:05.761498
8373 04:38:05.764990 [CBTSetCACLKResult] CA Dly = 36
8374 04:38:05.768058 CS Dly: 11 (0~44)
8375 04:38:05.771445 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8376 04:38:05.774991 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8377 04:38:05.775097
8378 04:38:05.777959 ----->DramcWriteLeveling(PI) begin...
8379 04:38:05.778044 ==
8380 04:38:05.781498 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 04:38:05.784723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 04:38:05.788237 ==
8383 04:38:05.788320 Write leveling (Byte 0): 24 => 24
8384 04:38:05.791839 Write leveling (Byte 1): 27 => 27
8385 04:38:05.794624 DramcWriteLeveling(PI) end<-----
8386 04:38:05.794729
8387 04:38:05.794823 ==
8388 04:38:05.798369 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 04:38:05.804556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 04:38:05.804662 ==
8391 04:38:05.804756 [Gating] SW mode calibration
8392 04:38:05.814682 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8393 04:38:05.818433 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8394 04:38:05.824504 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 04:38:05.828165 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 04:38:05.831586 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 04:38:05.834394 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 04:38:05.841368 1 4 16 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
8399 04:38:05.844619 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 04:38:05.847759 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 04:38:05.854849 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 04:38:05.857809 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 04:38:05.861457 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 04:38:05.868278 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 04:38:05.871253 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8406 04:38:05.874857 1 5 16 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (1 0)
8407 04:38:05.881164 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 04:38:05.884962 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 04:38:05.888147 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 04:38:05.894663 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 04:38:05.898099 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 04:38:05.901369 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 04:38:05.907920 1 6 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8414 04:38:05.911211 1 6 16 | B1->B0 | 3f3f 4444 | 1 0 | (0 0) (0 0)
8415 04:38:05.914345 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 04:38:05.921136 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 04:38:05.924298 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 04:38:05.927443 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 04:38:05.934216 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 04:38:05.937771 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 04:38:05.940677 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8422 04:38:05.947785 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8423 04:38:05.950686 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 04:38:05.954355 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 04:38:05.960805 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 04:38:05.963710 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 04:38:05.967390 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 04:38:05.974132 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 04:38:05.977163 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 04:38:05.980738 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 04:38:05.987082 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 04:38:05.990017 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 04:38:05.993688 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 04:38:06.000532 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 04:38:06.003333 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 04:38:06.007019 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 04:38:06.013355 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8438 04:38:06.016714 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8439 04:38:06.019679 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 04:38:06.023441 Total UI for P1: 0, mck2ui 16
8441 04:38:06.026856 best dqsien dly found for B0: ( 1, 9, 14)
8442 04:38:06.030140 Total UI for P1: 0, mck2ui 16
8443 04:38:06.033104 best dqsien dly found for B1: ( 1, 9, 16)
8444 04:38:06.036349 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8445 04:38:06.039685 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8446 04:38:06.039767
8447 04:38:06.046604 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8448 04:38:06.049670 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8449 04:38:06.052841 [Gating] SW calibration Done
8450 04:38:06.052923 ==
8451 04:38:06.056267 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 04:38:06.059263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 04:38:06.059348 ==
8454 04:38:06.059443 RX Vref Scan: 0
8455 04:38:06.059506
8456 04:38:06.062826 RX Vref 0 -> 0, step: 1
8457 04:38:06.062908
8458 04:38:06.066393 RX Delay 0 -> 252, step: 8
8459 04:38:06.069462 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8460 04:38:06.073044 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8461 04:38:06.076250 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8462 04:38:06.082757 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8463 04:38:06.085796 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8464 04:38:06.089376 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8465 04:38:06.092844 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8466 04:38:06.099019 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8467 04:38:06.102693 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8468 04:38:06.105752 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8469 04:38:06.109459 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8470 04:38:06.112470 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8471 04:38:06.118968 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8472 04:38:06.122761 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8473 04:38:06.125670 iDelay=208, Bit 14, Center 131 (80 ~ 183) 104
8474 04:38:06.129463 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8475 04:38:06.129545 ==
8476 04:38:06.132406 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 04:38:06.139193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 04:38:06.139275 ==
8479 04:38:06.139341 DQS Delay:
8480 04:38:06.139445 DQS0 = 0, DQS1 = 0
8481 04:38:06.142180 DQM Delay:
8482 04:38:06.142324 DQM0 = 133, DQM1 = 125
8483 04:38:06.145637 DQ Delay:
8484 04:38:06.148818 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8485 04:38:06.152353 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =131
8486 04:38:06.155737 DQ8 =111, DQ9 =119, DQ10 =123, DQ11 =119
8487 04:38:06.158871 DQ12 =135, DQ13 =131, DQ14 =131, DQ15 =135
8488 04:38:06.158954
8489 04:38:06.159019
8490 04:38:06.159079 ==
8491 04:38:06.162505 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 04:38:06.165485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 04:38:06.169117 ==
8494 04:38:06.169199
8495 04:38:06.169263
8496 04:38:06.169324 TX Vref Scan disable
8497 04:38:06.172295 == TX Byte 0 ==
8498 04:38:06.175689 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8499 04:38:06.179201 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8500 04:38:06.182258 == TX Byte 1 ==
8501 04:38:06.185377 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8502 04:38:06.188959 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8503 04:38:06.189041 ==
8504 04:38:06.192601 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 04:38:06.199046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 04:38:06.199128 ==
8507 04:38:06.211735
8508 04:38:06.215446 TX Vref early break, caculate TX vref
8509 04:38:06.218248 TX Vref=16, minBit 0, minWin=21, winSum=359
8510 04:38:06.221746 TX Vref=18, minBit 0, minWin=22, winSum=365
8511 04:38:06.225357 TX Vref=20, minBit 0, minWin=23, winSum=381
8512 04:38:06.228255 TX Vref=22, minBit 0, minWin=24, winSum=395
8513 04:38:06.231531 TX Vref=24, minBit 0, minWin=24, winSum=404
8514 04:38:06.238205 TX Vref=26, minBit 0, minWin=24, winSum=408
8515 04:38:06.241790 TX Vref=28, minBit 6, minWin=24, winSum=417
8516 04:38:06.244872 TX Vref=30, minBit 6, minWin=24, winSum=416
8517 04:38:06.248523 TX Vref=32, minBit 0, minWin=23, winSum=405
8518 04:38:06.251621 TX Vref=34, minBit 0, minWin=23, winSum=398
8519 04:38:06.255208 TX Vref=36, minBit 0, minWin=23, winSum=387
8520 04:38:06.261841 [TxChooseVref] Worse bit 6, Min win 24, Win sum 417, Final Vref 28
8521 04:38:06.261950
8522 04:38:06.264837 Final TX Range 0 Vref 28
8523 04:38:06.264944
8524 04:38:06.265040 ==
8525 04:38:06.268649 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 04:38:06.271282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 04:38:06.271356 ==
8528 04:38:06.271460
8529 04:38:06.271521
8530 04:38:06.274651 TX Vref Scan disable
8531 04:38:06.281236 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8532 04:38:06.281346 == TX Byte 0 ==
8533 04:38:06.284591 u2DelayCellOfst[0]=22 cells (6 PI)
8534 04:38:06.288155 u2DelayCellOfst[1]=18 cells (5 PI)
8535 04:38:06.291278 u2DelayCellOfst[2]=0 cells (0 PI)
8536 04:38:06.294894 u2DelayCellOfst[3]=7 cells (2 PI)
8537 04:38:06.297832 u2DelayCellOfst[4]=11 cells (3 PI)
8538 04:38:06.301127 u2DelayCellOfst[5]=26 cells (7 PI)
8539 04:38:06.304720 u2DelayCellOfst[6]=22 cells (6 PI)
8540 04:38:06.307810 u2DelayCellOfst[7]=11 cells (3 PI)
8541 04:38:06.311282 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8542 04:38:06.314642 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8543 04:38:06.317719 == TX Byte 1 ==
8544 04:38:06.321432 u2DelayCellOfst[8]=0 cells (0 PI)
8545 04:38:06.324425 u2DelayCellOfst[9]=7 cells (2 PI)
8546 04:38:06.324507 u2DelayCellOfst[10]=11 cells (3 PI)
8547 04:38:06.327915 u2DelayCellOfst[11]=7 cells (2 PI)
8548 04:38:06.331009 u2DelayCellOfst[12]=15 cells (4 PI)
8549 04:38:06.334365 u2DelayCellOfst[13]=18 cells (5 PI)
8550 04:38:06.337633 u2DelayCellOfst[14]=18 cells (5 PI)
8551 04:38:06.341237 u2DelayCellOfst[15]=18 cells (5 PI)
8552 04:38:06.347937 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8553 04:38:06.350946 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8554 04:38:06.351028 DramC Write-DBI on
8555 04:38:06.351094 ==
8556 04:38:06.354443 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 04:38:06.361304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 04:38:06.361387 ==
8559 04:38:06.361453
8560 04:38:06.361513
8561 04:38:06.361571 TX Vref Scan disable
8562 04:38:06.364777 == TX Byte 0 ==
8563 04:38:06.368449 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8564 04:38:06.371548 == TX Byte 1 ==
8565 04:38:06.375158 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8566 04:38:06.378302 DramC Write-DBI off
8567 04:38:06.378380
8568 04:38:06.378444 [DATLAT]
8569 04:38:06.378504 Freq=1600, CH1 RK0
8570 04:38:06.378563
8571 04:38:06.381251 DATLAT Default: 0xf
8572 04:38:06.381352 0, 0xFFFF, sum = 0
8573 04:38:06.384770 1, 0xFFFF, sum = 0
8574 04:38:06.388469 2, 0xFFFF, sum = 0
8575 04:38:06.388553 3, 0xFFFF, sum = 0
8576 04:38:06.391179 4, 0xFFFF, sum = 0
8577 04:38:06.391262 5, 0xFFFF, sum = 0
8578 04:38:06.394535 6, 0xFFFF, sum = 0
8579 04:38:06.394617 7, 0xFFFF, sum = 0
8580 04:38:06.397736 8, 0xFFFF, sum = 0
8581 04:38:06.397819 9, 0xFFFF, sum = 0
8582 04:38:06.401164 10, 0xFFFF, sum = 0
8583 04:38:06.401273 11, 0xFFFF, sum = 0
8584 04:38:06.404684 12, 0xFFFF, sum = 0
8585 04:38:06.404767 13, 0x8FFF, sum = 0
8586 04:38:06.407961 14, 0x0, sum = 1
8587 04:38:06.408044 15, 0x0, sum = 2
8588 04:38:06.411233 16, 0x0, sum = 3
8589 04:38:06.411315 17, 0x0, sum = 4
8590 04:38:06.414400 best_step = 15
8591 04:38:06.414482
8592 04:38:06.414547 ==
8593 04:38:06.418115 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 04:38:06.421315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 04:38:06.421397 ==
8596 04:38:06.424422 RX Vref Scan: 1
8597 04:38:06.424504
8598 04:38:06.424569 Set Vref Range= 24 -> 127
8599 04:38:06.424630
8600 04:38:06.427802 RX Vref 24 -> 127, step: 1
8601 04:38:06.427883
8602 04:38:06.430968 RX Delay 11 -> 252, step: 4
8603 04:38:06.431066
8604 04:38:06.434436 Set Vref, RX VrefLevel [Byte0]: 24
8605 04:38:06.437462 [Byte1]: 24
8606 04:38:06.437544
8607 04:38:06.441433 Set Vref, RX VrefLevel [Byte0]: 25
8608 04:38:06.444148 [Byte1]: 25
8609 04:38:06.447797
8610 04:38:06.447878 Set Vref, RX VrefLevel [Byte0]: 26
8611 04:38:06.451444 [Byte1]: 26
8612 04:38:06.455176
8613 04:38:06.455257 Set Vref, RX VrefLevel [Byte0]: 27
8614 04:38:06.458787 [Byte1]: 27
8615 04:38:06.462889
8616 04:38:06.462973 Set Vref, RX VrefLevel [Byte0]: 28
8617 04:38:06.466584 [Byte1]: 28
8618 04:38:06.470712
8619 04:38:06.470793 Set Vref, RX VrefLevel [Byte0]: 29
8620 04:38:06.473699 [Byte1]: 29
8621 04:38:06.477941
8622 04:38:06.478023 Set Vref, RX VrefLevel [Byte0]: 30
8623 04:38:06.481633 [Byte1]: 30
8624 04:38:06.485933
8625 04:38:06.486037 Set Vref, RX VrefLevel [Byte0]: 31
8626 04:38:06.489041 [Byte1]: 31
8627 04:38:06.493798
8628 04:38:06.493879 Set Vref, RX VrefLevel [Byte0]: 32
8629 04:38:06.496927 [Byte1]: 32
8630 04:38:06.501214
8631 04:38:06.501295 Set Vref, RX VrefLevel [Byte0]: 33
8632 04:38:06.504388 [Byte1]: 33
8633 04:38:06.508549
8634 04:38:06.508658 Set Vref, RX VrefLevel [Byte0]: 34
8635 04:38:06.515008 [Byte1]: 34
8636 04:38:06.515090
8637 04:38:06.518589 Set Vref, RX VrefLevel [Byte0]: 35
8638 04:38:06.521611 [Byte1]: 35
8639 04:38:06.521692
8640 04:38:06.524843 Set Vref, RX VrefLevel [Byte0]: 36
8641 04:38:06.528278 [Byte1]: 36
8642 04:38:06.531651
8643 04:38:06.531732 Set Vref, RX VrefLevel [Byte0]: 37
8644 04:38:06.535029 [Byte1]: 37
8645 04:38:06.539010
8646 04:38:06.539091 Set Vref, RX VrefLevel [Byte0]: 38
8647 04:38:06.542703 [Byte1]: 38
8648 04:38:06.547048
8649 04:38:06.547129 Set Vref, RX VrefLevel [Byte0]: 39
8650 04:38:06.549763 [Byte1]: 39
8651 04:38:06.554390
8652 04:38:06.554472 Set Vref, RX VrefLevel [Byte0]: 40
8653 04:38:06.557821 [Byte1]: 40
8654 04:38:06.562059
8655 04:38:06.562139 Set Vref, RX VrefLevel [Byte0]: 41
8656 04:38:06.565014 [Byte1]: 41
8657 04:38:06.569835
8658 04:38:06.569914 Set Vref, RX VrefLevel [Byte0]: 42
8659 04:38:06.572993 [Byte1]: 42
8660 04:38:06.577277
8661 04:38:06.577357 Set Vref, RX VrefLevel [Byte0]: 43
8662 04:38:06.580314 [Byte1]: 43
8663 04:38:06.585299
8664 04:38:06.585378 Set Vref, RX VrefLevel [Byte0]: 44
8665 04:38:06.588182 [Byte1]: 44
8666 04:38:06.592424
8667 04:38:06.592504 Set Vref, RX VrefLevel [Byte0]: 45
8668 04:38:06.595461 [Byte1]: 45
8669 04:38:06.600386
8670 04:38:06.600466 Set Vref, RX VrefLevel [Byte0]: 46
8671 04:38:06.603192 [Byte1]: 46
8672 04:38:06.607842
8673 04:38:06.607922 Set Vref, RX VrefLevel [Byte0]: 47
8674 04:38:06.610889 [Byte1]: 47
8675 04:38:06.615307
8676 04:38:06.615421 Set Vref, RX VrefLevel [Byte0]: 48
8677 04:38:06.618453 [Byte1]: 48
8678 04:38:06.623200
8679 04:38:06.623279 Set Vref, RX VrefLevel [Byte0]: 49
8680 04:38:06.625963 [Byte1]: 49
8681 04:38:06.630366
8682 04:38:06.630446 Set Vref, RX VrefLevel [Byte0]: 50
8683 04:38:06.633816 [Byte1]: 50
8684 04:38:06.638364
8685 04:38:06.638444 Set Vref, RX VrefLevel [Byte0]: 51
8686 04:38:06.641328 [Byte1]: 51
8687 04:38:06.645796
8688 04:38:06.645875 Set Vref, RX VrefLevel [Byte0]: 52
8689 04:38:06.649285 [Byte1]: 52
8690 04:38:06.653030
8691 04:38:06.653110 Set Vref, RX VrefLevel [Byte0]: 53
8692 04:38:06.656764 [Byte1]: 53
8693 04:38:06.660781
8694 04:38:06.660862 Set Vref, RX VrefLevel [Byte0]: 54
8695 04:38:06.664022 [Byte1]: 54
8696 04:38:06.668757
8697 04:38:06.668841 Set Vref, RX VrefLevel [Byte0]: 55
8698 04:38:06.671767 [Byte1]: 55
8699 04:38:06.676381
8700 04:38:06.676462 Set Vref, RX VrefLevel [Byte0]: 56
8701 04:38:06.679418 [Byte1]: 56
8702 04:38:06.683729
8703 04:38:06.683809 Set Vref, RX VrefLevel [Byte0]: 57
8704 04:38:06.686819 [Byte1]: 57
8705 04:38:06.691690
8706 04:38:06.691771 Set Vref, RX VrefLevel [Byte0]: 58
8707 04:38:06.694757 [Byte1]: 58
8708 04:38:06.699111
8709 04:38:06.699190 Set Vref, RX VrefLevel [Byte0]: 59
8710 04:38:06.702107 [Byte1]: 59
8711 04:38:06.706762
8712 04:38:06.706842 Set Vref, RX VrefLevel [Byte0]: 60
8713 04:38:06.709588 [Byte1]: 60
8714 04:38:06.714517
8715 04:38:06.714596 Set Vref, RX VrefLevel [Byte0]: 61
8716 04:38:06.717576 [Byte1]: 61
8717 04:38:06.721769
8718 04:38:06.721864 Set Vref, RX VrefLevel [Byte0]: 62
8719 04:38:06.725469 [Byte1]: 62
8720 04:38:06.729730
8721 04:38:06.729841 Set Vref, RX VrefLevel [Byte0]: 63
8722 04:38:06.732649 [Byte1]: 63
8723 04:38:06.737033
8724 04:38:06.737142 Set Vref, RX VrefLevel [Byte0]: 64
8725 04:38:06.740359 [Byte1]: 64
8726 04:38:06.744997
8727 04:38:06.745104 Set Vref, RX VrefLevel [Byte0]: 65
8728 04:38:06.748271 [Byte1]: 65
8729 04:38:06.752403
8730 04:38:06.752484 Set Vref, RX VrefLevel [Byte0]: 66
8731 04:38:06.755538 [Byte1]: 66
8732 04:38:06.759868
8733 04:38:06.759950 Set Vref, RX VrefLevel [Byte0]: 67
8734 04:38:06.763190 [Byte1]: 67
8735 04:38:06.767506
8736 04:38:06.767604 Set Vref, RX VrefLevel [Byte0]: 68
8737 04:38:06.771043 [Byte1]: 68
8738 04:38:06.775303
8739 04:38:06.775442 Set Vref, RX VrefLevel [Byte0]: 69
8740 04:38:06.778608 [Byte1]: 69
8741 04:38:06.782545
8742 04:38:06.782626 Set Vref, RX VrefLevel [Byte0]: 70
8743 04:38:06.785725 [Byte1]: 70
8744 04:38:06.790075
8745 04:38:06.790156 Set Vref, RX VrefLevel [Byte0]: 71
8746 04:38:06.793611 [Byte1]: 71
8747 04:38:06.798005
8748 04:38:06.798087 Set Vref, RX VrefLevel [Byte0]: 72
8749 04:38:06.801540 [Byte1]: 72
8750 04:38:06.805818
8751 04:38:06.805898 Set Vref, RX VrefLevel [Byte0]: 73
8752 04:38:06.808794 [Byte1]: 73
8753 04:38:06.813525
8754 04:38:06.813606 Final RX Vref Byte 0 = 57 to rank0
8755 04:38:06.816419 Final RX Vref Byte 1 = 51 to rank0
8756 04:38:06.820116 Final RX Vref Byte 0 = 57 to rank1
8757 04:38:06.823318 Final RX Vref Byte 1 = 51 to rank1==
8758 04:38:06.826556 Dram Type= 6, Freq= 0, CH_1, rank 0
8759 04:38:06.833003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 04:38:06.833086 ==
8761 04:38:06.833151 DQS Delay:
8762 04:38:06.836405 DQS0 = 0, DQS1 = 0
8763 04:38:06.836486 DQM Delay:
8764 04:38:06.836552 DQM0 = 131, DQM1 = 122
8765 04:38:06.839333 DQ Delay:
8766 04:38:06.842919 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8767 04:38:06.846416 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8768 04:38:06.849918 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =114
8769 04:38:06.852985 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =130
8770 04:38:06.853066
8771 04:38:06.853131
8772 04:38:06.853191
8773 04:38:06.856665 [DramC_TX_OE_Calibration] TA2
8774 04:38:06.859637 Original DQ_B0 (3 6) =30, OEN = 27
8775 04:38:06.862752 Original DQ_B1 (3 6) =30, OEN = 27
8776 04:38:06.866522 24, 0x0, End_B0=24 End_B1=24
8777 04:38:06.866605 25, 0x0, End_B0=25 End_B1=25
8778 04:38:06.869451 26, 0x0, End_B0=26 End_B1=26
8779 04:38:06.873157 27, 0x0, End_B0=27 End_B1=27
8780 04:38:06.875864 28, 0x0, End_B0=28 End_B1=28
8781 04:38:06.879598 29, 0x0, End_B0=29 End_B1=29
8782 04:38:06.879708 30, 0x0, End_B0=30 End_B1=30
8783 04:38:06.882710 31, 0x4141, End_B0=30 End_B1=30
8784 04:38:06.885742 Byte0 end_step=30 best_step=27
8785 04:38:06.889539 Byte1 end_step=30 best_step=27
8786 04:38:06.892978 Byte0 TX OE(2T, 0.5T) = (3, 3)
8787 04:38:06.895695 Byte1 TX OE(2T, 0.5T) = (3, 3)
8788 04:38:06.895769
8789 04:38:06.895831
8790 04:38:06.902938 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8791 04:38:06.905917 CH1 RK0: MR19=303, MR18=90E
8792 04:38:06.912370 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8793 04:38:06.912452
8794 04:38:06.916071 ----->DramcWriteLeveling(PI) begin...
8795 04:38:06.916155 ==
8796 04:38:06.919395 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 04:38:06.922431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 04:38:06.922513 ==
8799 04:38:06.926096 Write leveling (Byte 0): 23 => 23
8800 04:38:06.929153 Write leveling (Byte 1): 27 => 27
8801 04:38:06.932226 DramcWriteLeveling(PI) end<-----
8802 04:38:06.932307
8803 04:38:06.932371 ==
8804 04:38:06.935779 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 04:38:06.938996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 04:38:06.939079 ==
8807 04:38:06.942081 [Gating] SW mode calibration
8808 04:38:06.949128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8809 04:38:06.955346 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8810 04:38:06.958813 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 04:38:06.962398 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 04:38:06.968981 1 4 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
8813 04:38:06.972059 1 4 12 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8814 04:38:06.975652 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 04:38:06.982228 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 04:38:06.985841 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 04:38:06.988747 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 04:38:06.995311 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 04:38:06.998559 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8820 04:38:07.001977 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8821 04:38:07.008743 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8822 04:38:07.011968 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8823 04:38:07.015491 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 04:38:07.022158 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 04:38:07.025475 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 04:38:07.028541 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 04:38:07.035219 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 04:38:07.038827 1 6 8 | B1->B0 | 2323 3b3a | 0 1 | (0 0) (0 0)
8829 04:38:07.041869 1 6 12 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8830 04:38:07.048429 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8831 04:38:07.051832 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 04:38:07.055171 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 04:38:07.061512 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 04:38:07.064838 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 04:38:07.068283 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 04:38:07.075072 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8837 04:38:07.078633 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8838 04:38:07.081691 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8839 04:38:07.088384 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 04:38:07.091306 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 04:38:07.094778 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 04:38:07.101277 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 04:38:07.104897 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 04:38:07.108261 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 04:38:07.114461 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 04:38:07.118006 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 04:38:07.121208 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 04:38:07.128002 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 04:38:07.131511 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 04:38:07.134574 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 04:38:07.138285 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8852 04:38:07.144503 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8853 04:38:07.148227 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8854 04:38:07.151063 Total UI for P1: 0, mck2ui 16
8855 04:38:07.154547 best dqsien dly found for B0: ( 1, 9, 6)
8856 04:38:07.158109 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 04:38:07.161041 Total UI for P1: 0, mck2ui 16
8858 04:38:07.164398 best dqsien dly found for B1: ( 1, 9, 12)
8859 04:38:07.167830 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8860 04:38:07.171194 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8861 04:38:07.174400
8862 04:38:07.177996 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8863 04:38:07.180886 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8864 04:38:07.183988 [Gating] SW calibration Done
8865 04:38:07.184069 ==
8866 04:38:07.187599 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 04:38:07.190661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 04:38:07.190743 ==
8869 04:38:07.193904 RX Vref Scan: 0
8870 04:38:07.193988
8871 04:38:07.194053 RX Vref 0 -> 0, step: 1
8872 04:38:07.194115
8873 04:38:07.197390 RX Delay 0 -> 252, step: 8
8874 04:38:07.200940 iDelay=200, Bit 0, Center 135 (72 ~ 199) 128
8875 04:38:07.204000 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8876 04:38:07.210672 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8877 04:38:07.214322 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8878 04:38:07.217199 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8879 04:38:07.220751 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8880 04:38:07.224149 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8881 04:38:07.230650 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8882 04:38:07.234298 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8883 04:38:07.237268 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8884 04:38:07.240521 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8885 04:38:07.243976 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8886 04:38:07.250621 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8887 04:38:07.254271 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8888 04:38:07.257359 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8889 04:38:07.260723 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8890 04:38:07.260852 ==
8891 04:38:07.263769 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 04:38:07.270314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 04:38:07.270436 ==
8894 04:38:07.270506 DQS Delay:
8895 04:38:07.273769 DQS0 = 0, DQS1 = 0
8896 04:38:07.273873 DQM Delay:
8897 04:38:07.276735 DQM0 = 129, DQM1 = 127
8898 04:38:07.276840 DQ Delay:
8899 04:38:07.280580 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =127
8900 04:38:07.283774 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8901 04:38:07.287351 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8902 04:38:07.290292 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8903 04:38:07.290366
8904 04:38:07.290428
8905 04:38:07.290496 ==
8906 04:38:07.293408 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 04:38:07.300179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 04:38:07.300302 ==
8909 04:38:07.300388
8910 04:38:07.300486
8911 04:38:07.300575 TX Vref Scan disable
8912 04:38:07.303621 == TX Byte 0 ==
8913 04:38:07.306672 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8914 04:38:07.313368 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8915 04:38:07.313482 == TX Byte 1 ==
8916 04:38:07.317039 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8917 04:38:07.323529 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 04:38:07.323629 ==
8919 04:38:07.326439 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 04:38:07.330042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 04:38:07.330157 ==
8922 04:38:07.342996
8923 04:38:07.345549 TX Vref early break, caculate TX vref
8924 04:38:07.348914 TX Vref=16, minBit 0, minWin=21, winSum=372
8925 04:38:07.352399 TX Vref=18, minBit 6, minWin=22, winSum=385
8926 04:38:07.355838 TX Vref=20, minBit 0, minWin=22, winSum=394
8927 04:38:07.359057 TX Vref=22, minBit 0, minWin=23, winSum=402
8928 04:38:07.362391 TX Vref=24, minBit 0, minWin=23, winSum=411
8929 04:38:07.369036 TX Vref=26, minBit 1, minWin=24, winSum=420
8930 04:38:07.372614 TX Vref=28, minBit 0, minWin=25, winSum=423
8931 04:38:07.376237 TX Vref=30, minBit 0, minWin=24, winSum=416
8932 04:38:07.379263 TX Vref=32, minBit 0, minWin=24, winSum=408
8933 04:38:07.382752 TX Vref=34, minBit 0, minWin=23, winSum=398
8934 04:38:07.389446 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8935 04:38:07.389552
8936 04:38:07.392826 Final TX Range 0 Vref 28
8937 04:38:07.392963
8938 04:38:07.393029 ==
8939 04:38:07.395697 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 04:38:07.399300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 04:38:07.399408 ==
8942 04:38:07.399490
8943 04:38:07.399551
8944 04:38:07.402430 TX Vref Scan disable
8945 04:38:07.408994 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8946 04:38:07.409094 == TX Byte 0 ==
8947 04:38:07.412542 u2DelayCellOfst[0]=18 cells (5 PI)
8948 04:38:07.415527 u2DelayCellOfst[1]=15 cells (4 PI)
8949 04:38:07.419254 u2DelayCellOfst[2]=0 cells (0 PI)
8950 04:38:07.422202 u2DelayCellOfst[3]=7 cells (2 PI)
8951 04:38:07.425966 u2DelayCellOfst[4]=7 cells (2 PI)
8952 04:38:07.428744 u2DelayCellOfst[5]=22 cells (6 PI)
8953 04:38:07.432258 u2DelayCellOfst[6]=26 cells (7 PI)
8954 04:38:07.432340 u2DelayCellOfst[7]=7 cells (2 PI)
8955 04:38:07.438861 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8956 04:38:07.442254 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8957 04:38:07.442336 == TX Byte 1 ==
8958 04:38:07.445269 u2DelayCellOfst[8]=0 cells (0 PI)
8959 04:38:07.448748 u2DelayCellOfst[9]=7 cells (2 PI)
8960 04:38:07.452443 u2DelayCellOfst[10]=15 cells (4 PI)
8961 04:38:07.455320 u2DelayCellOfst[11]=7 cells (2 PI)
8962 04:38:07.458600 u2DelayCellOfst[12]=18 cells (5 PI)
8963 04:38:07.462180 u2DelayCellOfst[13]=18 cells (5 PI)
8964 04:38:07.465524 u2DelayCellOfst[14]=18 cells (5 PI)
8965 04:38:07.468835 u2DelayCellOfst[15]=22 cells (6 PI)
8966 04:38:07.472042 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8967 04:38:07.478484 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8968 04:38:07.478570 DramC Write-DBI on
8969 04:38:07.478636 ==
8970 04:38:07.481989 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 04:38:07.485355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 04:38:07.488369 ==
8973 04:38:07.488450
8974 04:38:07.488515
8975 04:38:07.488575 TX Vref Scan disable
8976 04:38:07.491931 == TX Byte 0 ==
8977 04:38:07.495297 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8978 04:38:07.498594 == TX Byte 1 ==
8979 04:38:07.501847 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8980 04:38:07.504877 DramC Write-DBI off
8981 04:38:07.504958
8982 04:38:07.505022 [DATLAT]
8983 04:38:07.505083 Freq=1600, CH1 RK1
8984 04:38:07.505143
8985 04:38:07.508549 DATLAT Default: 0xf
8986 04:38:07.508646 0, 0xFFFF, sum = 0
8987 04:38:07.511555 1, 0xFFFF, sum = 0
8988 04:38:07.515134 2, 0xFFFF, sum = 0
8989 04:38:07.515216 3, 0xFFFF, sum = 0
8990 04:38:07.518215 4, 0xFFFF, sum = 0
8991 04:38:07.518298 5, 0xFFFF, sum = 0
8992 04:38:07.521792 6, 0xFFFF, sum = 0
8993 04:38:07.521874 7, 0xFFFF, sum = 0
8994 04:38:07.524798 8, 0xFFFF, sum = 0
8995 04:38:07.524881 9, 0xFFFF, sum = 0
8996 04:38:07.528551 10, 0xFFFF, sum = 0
8997 04:38:07.528633 11, 0xFFFF, sum = 0
8998 04:38:07.531513 12, 0xFFFF, sum = 0
8999 04:38:07.531595 13, 0x8FFF, sum = 0
9000 04:38:07.534485 14, 0x0, sum = 1
9001 04:38:07.534568 15, 0x0, sum = 2
9002 04:38:07.538064 16, 0x0, sum = 3
9003 04:38:07.538147 17, 0x0, sum = 4
9004 04:38:07.541518 best_step = 15
9005 04:38:07.541600
9006 04:38:07.541665 ==
9007 04:38:07.544463 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 04:38:07.547818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 04:38:07.547900 ==
9010 04:38:07.551477 RX Vref Scan: 0
9011 04:38:07.551558
9012 04:38:07.551623 RX Vref 0 -> 0, step: 1
9013 04:38:07.551684
9014 04:38:07.554485 RX Delay 3 -> 252, step: 4
9015 04:38:07.561047 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9016 04:38:07.564505 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9017 04:38:07.567502 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9018 04:38:07.571241 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9019 04:38:07.574086 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9020 04:38:07.580859 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9021 04:38:07.584438 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9022 04:38:07.587282 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9023 04:38:07.590705 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9024 04:38:07.594248 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9025 04:38:07.601084 iDelay=195, Bit 10, Center 124 (71 ~ 178) 108
9026 04:38:07.603861 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9027 04:38:07.607493 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9028 04:38:07.611013 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
9029 04:38:07.613776 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9030 04:38:07.620369 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
9031 04:38:07.620451 ==
9032 04:38:07.624084 Dram Type= 6, Freq= 0, CH_1, rank 1
9033 04:38:07.627061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9034 04:38:07.627142 ==
9035 04:38:07.627206 DQS Delay:
9036 04:38:07.630704 DQS0 = 0, DQS1 = 0
9037 04:38:07.630784 DQM Delay:
9038 04:38:07.633789 DQM0 = 127, DQM1 = 123
9039 04:38:07.633869 DQ Delay:
9040 04:38:07.636795 DQ0 =132, DQ1 =124, DQ2 =114, DQ3 =126
9041 04:38:07.640263 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9042 04:38:07.643815 DQ8 =108, DQ9 =112, DQ10 =124, DQ11 =118
9043 04:38:07.650453 DQ12 =132, DQ13 =130, DQ14 =130, DQ15 =132
9044 04:38:07.650534
9045 04:38:07.650598
9046 04:38:07.650658
9047 04:38:07.653347 [DramC_TX_OE_Calibration] TA2
9048 04:38:07.653428 Original DQ_B0 (3 6) =30, OEN = 27
9049 04:38:07.657089 Original DQ_B1 (3 6) =30, OEN = 27
9050 04:38:07.660160 24, 0x0, End_B0=24 End_B1=24
9051 04:38:07.663762 25, 0x0, End_B0=25 End_B1=25
9052 04:38:07.666911 26, 0x0, End_B0=26 End_B1=26
9053 04:38:07.670284 27, 0x0, End_B0=27 End_B1=27
9054 04:38:07.670366 28, 0x0, End_B0=28 End_B1=28
9055 04:38:07.673322 29, 0x0, End_B0=29 End_B1=29
9056 04:38:07.676952 30, 0x0, End_B0=30 End_B1=30
9057 04:38:07.679931 31, 0x4141, End_B0=30 End_B1=30
9058 04:38:07.683664 Byte0 end_step=30 best_step=27
9059 04:38:07.683744 Byte1 end_step=30 best_step=27
9060 04:38:07.686551 Byte0 TX OE(2T, 0.5T) = (3, 3)
9061 04:38:07.689942 Byte1 TX OE(2T, 0.5T) = (3, 3)
9062 04:38:07.690023
9063 04:38:07.690087
9064 04:38:07.699646 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9065 04:38:07.699728 CH1 RK1: MR19=303, MR18=101C
9066 04:38:07.706425 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9067 04:38:07.709693 [RxdqsGatingPostProcess] freq 1600
9068 04:38:07.716593 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9069 04:38:07.719694 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 04:38:07.723095 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 04:38:07.726597 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 04:38:07.730015 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 04:38:07.730096 best DQS0 dly(2T, 0.5T) = (1, 1)
9074 04:38:07.732915 best DQS1 dly(2T, 0.5T) = (1, 1)
9075 04:38:07.736585 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9076 04:38:07.739628 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9077 04:38:07.743195 Pre-setting of DQS Precalculation
9078 04:38:07.749492 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9079 04:38:07.756501 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9080 04:38:07.762588 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 04:38:07.762671
9082 04:38:07.762736
9083 04:38:07.766122 [Calibration Summary] 3200 Mbps
9084 04:38:07.766204 CH 0, Rank 0
9085 04:38:07.769479 SW Impedance : PASS
9086 04:38:07.772669 DUTY Scan : NO K
9087 04:38:07.772751 ZQ Calibration : PASS
9088 04:38:07.776110 Jitter Meter : NO K
9089 04:38:07.779642 CBT Training : PASS
9090 04:38:07.779724 Write leveling : PASS
9091 04:38:07.782627 RX DQS gating : PASS
9092 04:38:07.786324 RX DQ/DQS(RDDQC) : PASS
9093 04:38:07.786406 TX DQ/DQS : PASS
9094 04:38:07.789220 RX DATLAT : PASS
9095 04:38:07.792820 RX DQ/DQS(Engine): PASS
9096 04:38:07.792902 TX OE : PASS
9097 04:38:07.792967 All Pass.
9098 04:38:07.793028
9099 04:38:07.796238 CH 0, Rank 1
9100 04:38:07.799229 SW Impedance : PASS
9101 04:38:07.799311 DUTY Scan : NO K
9102 04:38:07.802751 ZQ Calibration : PASS
9103 04:38:07.802832 Jitter Meter : NO K
9104 04:38:07.805838 CBT Training : PASS
9105 04:38:07.809492 Write leveling : PASS
9106 04:38:07.809572 RX DQS gating : PASS
9107 04:38:07.812575 RX DQ/DQS(RDDQC) : PASS
9108 04:38:07.816177 TX DQ/DQS : PASS
9109 04:38:07.816283 RX DATLAT : PASS
9110 04:38:07.819037 RX DQ/DQS(Engine): PASS
9111 04:38:07.822603 TX OE : PASS
9112 04:38:07.822702 All Pass.
9113 04:38:07.822791
9114 04:38:07.822877 CH 1, Rank 0
9115 04:38:07.826213 SW Impedance : PASS
9116 04:38:07.829176 DUTY Scan : NO K
9117 04:38:07.829256 ZQ Calibration : PASS
9118 04:38:07.832689 Jitter Meter : NO K
9119 04:38:07.835732 CBT Training : PASS
9120 04:38:07.835812 Write leveling : PASS
9121 04:38:07.838958 RX DQS gating : PASS
9122 04:38:07.842517 RX DQ/DQS(RDDQC) : PASS
9123 04:38:07.842592 TX DQ/DQS : PASS
9124 04:38:07.845525 RX DATLAT : PASS
9125 04:38:07.849105 RX DQ/DQS(Engine): PASS
9126 04:38:07.849187 TX OE : PASS
9127 04:38:07.849251 All Pass.
9128 04:38:07.852622
9129 04:38:07.852701 CH 1, Rank 1
9130 04:38:07.855542 SW Impedance : PASS
9131 04:38:07.855622 DUTY Scan : NO K
9132 04:38:07.859034 ZQ Calibration : PASS
9133 04:38:07.859144 Jitter Meter : NO K
9134 04:38:07.862002 CBT Training : PASS
9135 04:38:07.865594 Write leveling : PASS
9136 04:38:07.865675 RX DQS gating : PASS
9137 04:38:07.868734 RX DQ/DQS(RDDQC) : PASS
9138 04:38:07.872204 TX DQ/DQS : PASS
9139 04:38:07.872288 RX DATLAT : PASS
9140 04:38:07.875408 RX DQ/DQS(Engine): PASS
9141 04:38:07.878702 TX OE : PASS
9142 04:38:07.878783 All Pass.
9143 04:38:07.878847
9144 04:38:07.882481 DramC Write-DBI on
9145 04:38:07.882564 PER_BANK_REFRESH: Hybrid Mode
9146 04:38:07.885668 TX_TRACKING: ON
9147 04:38:07.895947 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9148 04:38:07.902108 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9149 04:38:07.908532 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9150 04:38:07.912229 [FAST_K] Save calibration result to emmc
9151 04:38:07.915126 sync common calibartion params.
9152 04:38:07.918786 sync cbt_mode0:1, 1:1
9153 04:38:07.918866 dram_init: ddr_geometry: 2
9154 04:38:07.921732 dram_init: ddr_geometry: 2
9155 04:38:07.925352 dram_init: ddr_geometry: 2
9156 04:38:07.928466 0:dram_rank_size:100000000
9157 04:38:07.928549 1:dram_rank_size:100000000
9158 04:38:07.934987 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9159 04:38:07.938426 DFS_SHUFFLE_HW_MODE: ON
9160 04:38:07.942053 dramc_set_vcore_voltage set vcore to 725000
9161 04:38:07.942159 Read voltage for 1600, 0
9162 04:38:07.945053 Vio18 = 0
9163 04:38:07.945157 Vcore = 725000
9164 04:38:07.945248 Vdram = 0
9165 04:38:07.948101 Vddq = 0
9166 04:38:07.948192 Vmddr = 0
9167 04:38:07.951507 switch to 3200 Mbps bootup
9168 04:38:07.951581 [DramcRunTimeConfig]
9169 04:38:07.954849 PHYPLL
9170 04:38:07.954952 DPM_CONTROL_AFTERK: ON
9171 04:38:07.958563 PER_BANK_REFRESH: ON
9172 04:38:07.961627 REFRESH_OVERHEAD_REDUCTION: ON
9173 04:38:07.961735 CMD_PICG_NEW_MODE: OFF
9174 04:38:07.964635 XRTWTW_NEW_MODE: ON
9175 04:38:07.964745 XRTRTR_NEW_MODE: ON
9176 04:38:07.968256 TX_TRACKING: ON
9177 04:38:07.968359 RDSEL_TRACKING: OFF
9178 04:38:07.971418 DQS Precalculation for DVFS: ON
9179 04:38:07.974604 RX_TRACKING: OFF
9180 04:38:07.974710 HW_GATING DBG: ON
9181 04:38:07.978386 ZQCS_ENABLE_LP4: ON
9182 04:38:07.978480 RX_PICG_NEW_MODE: ON
9183 04:38:07.981349 TX_PICG_NEW_MODE: ON
9184 04:38:07.981442 ENABLE_RX_DCM_DPHY: ON
9185 04:38:07.985156 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9186 04:38:07.988162 DUMMY_READ_FOR_TRACKING: OFF
9187 04:38:07.991765 !!! SPM_CONTROL_AFTERK: OFF
9188 04:38:07.994813 !!! SPM could not control APHY
9189 04:38:07.994911 IMPEDANCE_TRACKING: ON
9190 04:38:07.998487 TEMP_SENSOR: ON
9191 04:38:07.998558 HW_SAVE_FOR_SR: OFF
9192 04:38:08.001478 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9193 04:38:08.005210 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9194 04:38:08.007895 Read ODT Tracking: ON
9195 04:38:08.011266 Refresh Rate DeBounce: ON
9196 04:38:08.011402 DFS_NO_QUEUE_FLUSH: ON
9197 04:38:08.015162 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9198 04:38:08.017886 ENABLE_DFS_RUNTIME_MRW: OFF
9199 04:38:08.021645 DDR_RESERVE_NEW_MODE: ON
9200 04:38:08.021733 MR_CBT_SWITCH_FREQ: ON
9201 04:38:08.024971 =========================
9202 04:38:08.043230 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9203 04:38:08.046240 dram_init: ddr_geometry: 2
9204 04:38:08.064931 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9205 04:38:08.068383 dram_init: dram init end (result: 0)
9206 04:38:08.074643 DRAM-K: Full calibration passed in 24545 msecs
9207 04:38:08.077891 MRC: failed to locate region type 0.
9208 04:38:08.077974 DRAM rank0 size:0x100000000,
9209 04:38:08.081214 DRAM rank1 size=0x100000000
9210 04:38:08.091746 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9211 04:38:08.098085 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9212 04:38:08.104786 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9213 04:38:08.111218 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9214 04:38:08.114500 DRAM rank0 size:0x100000000,
9215 04:38:08.117867 DRAM rank1 size=0x100000000
9216 04:38:08.117995 CBMEM:
9217 04:38:08.120963 IMD: root @ 0xfffff000 254 entries.
9218 04:38:08.124630 IMD: root @ 0xffffec00 62 entries.
9219 04:38:08.128123 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9220 04:38:08.131034 WARNING: RO_VPD is uninitialized or empty.
9221 04:38:08.137768 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9222 04:38:08.145082 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9223 04:38:08.157746 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9224 04:38:08.169197 BS: romstage times (exec / console): total (unknown) / 24015 ms
9225 04:38:08.169282
9226 04:38:08.169347
9227 04:38:08.179140 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9228 04:38:08.182161 ARM64: Exception handlers installed.
9229 04:38:08.185436 ARM64: Testing exception
9230 04:38:08.189024 ARM64: Done test exception
9231 04:38:08.189125 Enumerating buses...
9232 04:38:08.192062 Show all devs... Before device enumeration.
9233 04:38:08.195854 Root Device: enabled 1
9234 04:38:08.199131 CPU_CLUSTER: 0: enabled 1
9235 04:38:08.199217 CPU: 00: enabled 1
9236 04:38:08.202172 Compare with tree...
9237 04:38:08.202256 Root Device: enabled 1
9238 04:38:08.205947 CPU_CLUSTER: 0: enabled 1
9239 04:38:08.208763 CPU: 00: enabled 1
9240 04:38:08.208848 Root Device scanning...
9241 04:38:08.212240 scan_static_bus for Root Device
9242 04:38:08.215307 CPU_CLUSTER: 0 enabled
9243 04:38:08.218479 scan_static_bus for Root Device done
9244 04:38:08.221980 scan_bus: bus Root Device finished in 8 msecs
9245 04:38:08.222078 done
9246 04:38:08.228836 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9247 04:38:08.231812 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9248 04:38:08.238837 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9249 04:38:08.241672 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9250 04:38:08.245346 Allocating resources...
9251 04:38:08.248283 Reading resources...
9252 04:38:08.251919 Root Device read_resources bus 0 link: 0
9253 04:38:08.252006 DRAM rank0 size:0x100000000,
9254 04:38:08.254931 DRAM rank1 size=0x100000000
9255 04:38:08.258616 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9256 04:38:08.261590 CPU: 00 missing read_resources
9257 04:38:08.268224 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9258 04:38:08.271784 Root Device read_resources bus 0 link: 0 done
9259 04:38:08.271869 Done reading resources.
9260 04:38:08.278292 Show resources in subtree (Root Device)...After reading.
9261 04:38:08.281822 Root Device child on link 0 CPU_CLUSTER: 0
9262 04:38:08.284913 CPU_CLUSTER: 0 child on link 0 CPU: 00
9263 04:38:08.294698 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9264 04:38:08.294781 CPU: 00
9265 04:38:08.298357 Root Device assign_resources, bus 0 link: 0
9266 04:38:08.301266 CPU_CLUSTER: 0 missing set_resources
9267 04:38:08.307778 Root Device assign_resources, bus 0 link: 0 done
9268 04:38:08.307866 Done setting resources.
9269 04:38:08.314483 Show resources in subtree (Root Device)...After assigning values.
9270 04:38:08.318144 Root Device child on link 0 CPU_CLUSTER: 0
9271 04:38:08.321237 CPU_CLUSTER: 0 child on link 0 CPU: 00
9272 04:38:08.331336 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9273 04:38:08.331469 CPU: 00
9274 04:38:08.334706 Done allocating resources.
9275 04:38:08.340918 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9276 04:38:08.341011 Enabling resources...
9277 04:38:08.341079 done.
9278 04:38:08.347663 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9279 04:38:08.347744 Initializing devices...
9280 04:38:08.351032 Root Device init
9281 04:38:08.354320 init hardware done!
9282 04:38:08.354401 0x00000018: ctrlr->caps
9283 04:38:08.357860 52.000 MHz: ctrlr->f_max
9284 04:38:08.357980 0.400 MHz: ctrlr->f_min
9285 04:38:08.361219 0x40ff8080: ctrlr->voltages
9286 04:38:08.364120 sclk: 390625
9287 04:38:08.364196 Bus Width = 1
9288 04:38:08.364260 sclk: 390625
9289 04:38:08.367649 Bus Width = 1
9290 04:38:08.367738 Early init status = 3
9291 04:38:08.374174 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9292 04:38:08.377355 in-header: 03 fc 00 00 01 00 00 00
9293 04:38:08.380700 in-data: 00
9294 04:38:08.384234 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9295 04:38:08.389638 in-header: 03 fd 00 00 00 00 00 00
9296 04:38:08.393345 in-data:
9297 04:38:08.396152 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9298 04:38:08.400782 in-header: 03 fc 00 00 01 00 00 00
9299 04:38:08.403807 in-data: 00
9300 04:38:08.407221 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9301 04:38:08.412586 in-header: 03 fd 00 00 00 00 00 00
9302 04:38:08.416189 in-data:
9303 04:38:08.419203 [SSUSB] Setting up USB HOST controller...
9304 04:38:08.422876 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9305 04:38:08.425886 [SSUSB] phy power-on done.
9306 04:38:08.429352 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9307 04:38:08.435820 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9308 04:38:08.439541 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9309 04:38:08.445735 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9310 04:38:08.452254 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9311 04:38:08.458990 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9312 04:38:08.465651 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9313 04:38:08.472426 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9314 04:38:08.475522 SPM: binary array size = 0x9dc
9315 04:38:08.479131 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9316 04:38:08.485931 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9317 04:38:08.492003 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9318 04:38:08.498579 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9319 04:38:08.502109 configure_display: Starting display init
9320 04:38:08.536355 anx7625_power_on_init: Init interface.
9321 04:38:08.539346 anx7625_disable_pd_protocol: Disabled PD feature.
9322 04:38:08.542469 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9323 04:38:08.570665 anx7625_start_dp_work: Secure OCM version=00
9324 04:38:08.573707 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9325 04:38:08.588545 sp_tx_get_edid_block: EDID Block = 1
9326 04:38:08.691057 Extracted contents:
9327 04:38:08.694662 header: 00 ff ff ff ff ff ff 00
9328 04:38:08.697668 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9329 04:38:08.701245 version: 01 04
9330 04:38:08.704404 basic params: 95 1f 11 78 0a
9331 04:38:08.707578 chroma info: 76 90 94 55 54 90 27 21 50 54
9332 04:38:08.710647 established: 00 00 00
9333 04:38:08.717377 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9334 04:38:08.723909 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9335 04:38:08.727095 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9336 04:38:08.734111 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9337 04:38:08.740515 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9338 04:38:08.743662 extensions: 00
9339 04:38:08.743740 checksum: fb
9340 04:38:08.743805
9341 04:38:08.747089 Manufacturer: IVO Model 57d Serial Number 0
9342 04:38:08.750640 Made week 0 of 2020
9343 04:38:08.753755 EDID version: 1.4
9344 04:38:08.753837 Digital display
9345 04:38:08.757345 6 bits per primary color channel
9346 04:38:08.757423 DisplayPort interface
9347 04:38:08.760474 Maximum image size: 31 cm x 17 cm
9348 04:38:08.763560 Gamma: 220%
9349 04:38:08.763641 Check DPMS levels
9350 04:38:08.766751 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9351 04:38:08.773397 First detailed timing is preferred timing
9352 04:38:08.773485 Established timings supported:
9353 04:38:08.776779 Standard timings supported:
9354 04:38:08.780342 Detailed timings
9355 04:38:08.783424 Hex of detail: 383680a07038204018303c0035ae10000019
9356 04:38:08.790474 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9357 04:38:08.793920 0780 0798 07c8 0820 hborder 0
9358 04:38:08.797043 0438 043b 0447 0458 vborder 0
9359 04:38:08.800027 -hsync -vsync
9360 04:38:08.800107 Did detailed timing
9361 04:38:08.806746 Hex of detail: 000000000000000000000000000000000000
9362 04:38:08.809718 Manufacturer-specified data, tag 0
9363 04:38:08.813313 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9364 04:38:08.816361 ASCII string: InfoVision
9365 04:38:08.820282 Hex of detail: 000000fe00523134304e574635205248200a
9366 04:38:08.823111 ASCII string: R140NWF5 RH
9367 04:38:08.823190 Checksum
9368 04:38:08.826662 Checksum: 0xfb (valid)
9369 04:38:08.830091 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9370 04:38:08.833374 DSI data_rate: 832800000 bps
9371 04:38:08.839864 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9372 04:38:08.843183 anx7625_parse_edid: pixelclock(138800).
9373 04:38:08.846526 hactive(1920), hsync(48), hfp(24), hbp(88)
9374 04:38:08.849442 vactive(1080), vsync(12), vfp(3), vbp(17)
9375 04:38:08.852879 anx7625_dsi_config: config dsi.
9376 04:38:08.859394 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9377 04:38:08.872985 anx7625_dsi_config: success to config DSI
9378 04:38:08.876628 anx7625_dp_start: MIPI phy setup OK.
9379 04:38:08.879717 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9380 04:38:08.883230 mtk_ddp_mode_set invalid vrefresh 60
9381 04:38:08.886121 main_disp_path_setup
9382 04:38:08.886201 ovl_layer_smi_id_en
9383 04:38:08.889773 ovl_layer_smi_id_en
9384 04:38:08.889855 ccorr_config
9385 04:38:08.889919 aal_config
9386 04:38:08.892707 gamma_config
9387 04:38:08.892786 postmask_config
9388 04:38:08.896331 dither_config
9389 04:38:08.899341 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9390 04:38:08.906778 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9391 04:38:08.909629 Root Device init finished in 555 msecs
9392 04:38:08.913230 CPU_CLUSTER: 0 init
9393 04:38:08.919283 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9394 04:38:08.922933 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9395 04:38:08.925891 APU_MBOX 0x190000b0 = 0x10001
9396 04:38:08.929507 APU_MBOX 0x190001b0 = 0x10001
9397 04:38:08.932772 APU_MBOX 0x190005b0 = 0x10001
9398 04:38:08.936197 APU_MBOX 0x190006b0 = 0x10001
9399 04:38:08.942537 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9400 04:38:08.952448 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9401 04:38:08.964365 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9402 04:38:08.971075 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9403 04:38:08.982674 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9404 04:38:08.991900 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9405 04:38:08.995073 CPU_CLUSTER: 0 init finished in 81 msecs
9406 04:38:08.998751 Devices initialized
9407 04:38:09.002130 Show all devs... After init.
9408 04:38:09.002209 Root Device: enabled 1
9409 04:38:09.005165 CPU_CLUSTER: 0: enabled 1
9410 04:38:09.008234 CPU: 00: enabled 1
9411 04:38:09.011827 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9412 04:38:09.014884 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9413 04:38:09.018437 ELOG: NV offset 0x57f000 size 0x1000
9414 04:38:09.025451 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9415 04:38:09.031693 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9416 04:38:09.034786 ELOG: Event(17) added with size 13 at 2023-08-09 04:38:09 UTC
9417 04:38:09.041479 out: cmd=0x121: 03 db 21 01 00 00 00 00
9418 04:38:09.045107 in-header: 03 76 00 00 2c 00 00 00
9419 04:38:09.054922 in-data: e9 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9420 04:38:09.061117 ELOG: Event(A1) added with size 10 at 2023-08-09 04:38:09 UTC
9421 04:38:09.067829 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9422 04:38:09.074459 ELOG: Event(A0) added with size 9 at 2023-08-09 04:38:09 UTC
9423 04:38:09.077797 elog_add_boot_reason: Logged dev mode boot
9424 04:38:09.085071 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9425 04:38:09.085161 Finalize devices...
9426 04:38:09.087771 Devices finalized
9427 04:38:09.091405 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9428 04:38:09.094516 Writing coreboot table at 0xffe64000
9429 04:38:09.097943 0. 000000000010a000-0000000000113fff: RAMSTAGE
9430 04:38:09.104508 1. 0000000040000000-00000000400fffff: RAM
9431 04:38:09.107600 2. 0000000040100000-000000004032afff: RAMSTAGE
9432 04:38:09.110822 3. 000000004032b000-00000000545fffff: RAM
9433 04:38:09.114159 4. 0000000054600000-000000005465ffff: BL31
9434 04:38:09.117392 5. 0000000054660000-00000000ffe63fff: RAM
9435 04:38:09.124333 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9436 04:38:09.127484 7. 0000000100000000-000000023fffffff: RAM
9437 04:38:09.130838 Passing 5 GPIOs to payload:
9438 04:38:09.133783 NAME | PORT | POLARITY | VALUE
9439 04:38:09.140678 EC in RW | 0x000000aa | low | undefined
9440 04:38:09.143734 EC interrupt | 0x00000005 | low | undefined
9441 04:38:09.147653 TPM interrupt | 0x000000ab | high | undefined
9442 04:38:09.154008 SD card detect | 0x00000011 | high | undefined
9443 04:38:09.157355 speaker enable | 0x00000093 | high | undefined
9444 04:38:09.160838 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9445 04:38:09.163964 in-header: 03 f9 00 00 02 00 00 00
9446 04:38:09.166912 in-data: 02 00
9447 04:38:09.170620 ADC[4]: Raw value=894821 ID=7
9448 04:38:09.170702 ADC[3]: Raw value=212700 ID=1
9449 04:38:09.173832 RAM Code: 0x71
9450 04:38:09.176821 ADC[6]: Raw value=74722 ID=0
9451 04:38:09.176905 ADC[5]: Raw value=212330 ID=1
9452 04:38:09.180587 SKU Code: 0x1
9453 04:38:09.183629 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2dcf
9454 04:38:09.187174 coreboot table: 964 bytes.
9455 04:38:09.190341 IMD ROOT 0. 0xfffff000 0x00001000
9456 04:38:09.193683 IMD SMALL 1. 0xffffe000 0x00001000
9457 04:38:09.197183 RO MCACHE 2. 0xffffc000 0x00001104
9458 04:38:09.200188 CONSOLE 3. 0xfff7c000 0x00080000
9459 04:38:09.203293 FMAP 4. 0xfff7b000 0x00000452
9460 04:38:09.206920 TIME STAMP 5. 0xfff7a000 0x00000910
9461 04:38:09.209897 VBOOT WORK 6. 0xfff66000 0x00014000
9462 04:38:09.213653 RAMOOPS 7. 0xffe66000 0x00100000
9463 04:38:09.217365 COREBOOT 8. 0xffe64000 0x00002000
9464 04:38:09.220160 IMD small region:
9465 04:38:09.223299 IMD ROOT 0. 0xffffec00 0x00000400
9466 04:38:09.226735 VPD 1. 0xffffeba0 0x0000004c
9467 04:38:09.230266 MMC STATUS 2. 0xffffeb80 0x00000004
9468 04:38:09.233605 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9469 04:38:09.236616 Probing TPM: done!
9470 04:38:09.240014 Connected to device vid:did:rid of 1ae0:0028:00
9471 04:38:09.250654 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9472 04:38:09.254082 Initialized TPM device CR50 revision 0
9473 04:38:09.257466 Checking cr50 for pending updates
9474 04:38:09.261759 Reading cr50 TPM mode
9475 04:38:09.270305 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9476 04:38:09.277170 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9477 04:38:09.316872 read SPI 0x3990ec 0x4f1b0: 34857 us, 9295 KB/s, 74.360 Mbps
9478 04:38:09.320367 Checking segment from ROM address 0x40100000
9479 04:38:09.323993 Checking segment from ROM address 0x4010001c
9480 04:38:09.330466 Loading segment from ROM address 0x40100000
9481 04:38:09.330543 code (compression=0)
9482 04:38:09.340358 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9483 04:38:09.347068 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9484 04:38:09.347177 it's not compressed!
9485 04:38:09.353674 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9486 04:38:09.357227 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9487 04:38:09.377435 Loading segment from ROM address 0x4010001c
9488 04:38:09.377547 Entry Point 0x80000000
9489 04:38:09.380505 Loaded segments
9490 04:38:09.383883 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9491 04:38:09.390775 Jumping to boot code at 0x80000000(0xffe64000)
9492 04:38:09.397430 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9493 04:38:09.403950 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9494 04:38:09.411734 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9495 04:38:09.415366 Checking segment from ROM address 0x40100000
9496 04:38:09.418884 Checking segment from ROM address 0x4010001c
9497 04:38:09.425297 Loading segment from ROM address 0x40100000
9498 04:38:09.425404 code (compression=1)
9499 04:38:09.431728 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9500 04:38:09.442006 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9501 04:38:09.442117 using LZMA
9502 04:38:09.449949 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9503 04:38:09.456583 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9504 04:38:09.460062 Loading segment from ROM address 0x4010001c
9505 04:38:09.460170 Entry Point 0x54601000
9506 04:38:09.463479 Loaded segments
9507 04:38:09.466920 NOTICE: MT8192 bl31_setup
9508 04:38:09.473490 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9509 04:38:09.477071 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9510 04:38:09.480106 WARNING: region 0:
9511 04:38:09.483773 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 04:38:09.483854 WARNING: region 1:
9513 04:38:09.490212 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9514 04:38:09.493452 WARNING: region 2:
9515 04:38:09.497488 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9516 04:38:09.500477 WARNING: region 3:
9517 04:38:09.503823 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9518 04:38:09.506884 WARNING: region 4:
9519 04:38:09.513774 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9520 04:38:09.513903 WARNING: region 5:
9521 04:38:09.516893 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 04:38:09.520608 WARNING: region 6:
9523 04:38:09.523541 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 04:38:09.527055 WARNING: region 7:
9525 04:38:09.530039 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 04:38:09.537235 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9527 04:38:09.540201 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9528 04:38:09.543910 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9529 04:38:09.550643 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9530 04:38:09.554017 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9531 04:38:09.557296 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9532 04:38:09.563784 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9533 04:38:09.567292 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9534 04:38:09.573585 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9535 04:38:09.577156 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9536 04:38:09.580196 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9537 04:38:09.587225 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9538 04:38:09.590643 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9539 04:38:09.593651 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9540 04:38:09.600520 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9541 04:38:09.603912 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9542 04:38:09.607392 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9543 04:38:09.613972 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9544 04:38:09.616936 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9545 04:38:09.623667 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9546 04:38:09.627282 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9547 04:38:09.630678 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9548 04:38:09.637207 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9549 04:38:09.640501 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9550 04:38:09.647270 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9551 04:38:09.650298 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9552 04:38:09.653961 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9553 04:38:09.660362 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9554 04:38:09.663681 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9555 04:38:09.670172 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9556 04:38:09.673602 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9557 04:38:09.676878 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9558 04:38:09.683529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9559 04:38:09.687143 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9560 04:38:09.690123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9561 04:38:09.693682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9562 04:38:09.700232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9563 04:38:09.703331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9564 04:38:09.706804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9565 04:38:09.710631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9566 04:38:09.717200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9567 04:38:09.720122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9568 04:38:09.723761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9569 04:38:09.727173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9570 04:38:09.733760 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9571 04:38:09.736708 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9572 04:38:09.740565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9573 04:38:09.743381 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9574 04:38:09.750005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9575 04:38:09.753211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9576 04:38:09.760236 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9577 04:38:09.763429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9578 04:38:09.766918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9579 04:38:09.773631 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9580 04:38:09.777009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9581 04:38:09.783677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9582 04:38:09.786913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9583 04:38:09.793996 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9584 04:38:09.797055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9585 04:38:09.800721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9586 04:38:09.807245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9587 04:38:09.810479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9588 04:38:09.816896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9589 04:38:09.820428 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9590 04:38:09.826784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9591 04:38:09.830266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9592 04:38:09.833617 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9593 04:38:09.840602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9594 04:38:09.843796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9595 04:38:09.850392 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9596 04:38:09.854011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9597 04:38:09.860533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9598 04:38:09.864077 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9599 04:38:09.867091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9600 04:38:09.873522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9601 04:38:09.876896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9602 04:38:09.883983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9603 04:38:09.887120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9604 04:38:09.893532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9605 04:38:09.897267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9606 04:38:09.903845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9607 04:38:09.907388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9608 04:38:09.910472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9609 04:38:09.917139 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9610 04:38:09.920760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9611 04:38:09.927344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9612 04:38:09.930318 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9613 04:38:09.933842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9614 04:38:09.940176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9615 04:38:09.943857 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9616 04:38:09.950108 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9617 04:38:09.953761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9618 04:38:09.960292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9619 04:38:09.963796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9620 04:38:09.970399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9621 04:38:09.973381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9622 04:38:09.976939 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9623 04:38:09.983956 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9624 04:38:09.987024 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9625 04:38:09.990807 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9626 04:38:09.993621 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9627 04:38:10.000601 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9628 04:38:10.003673 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9629 04:38:10.010142 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9630 04:38:10.013672 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9631 04:38:10.016660 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9632 04:38:10.023672 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9633 04:38:10.026608 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9634 04:38:10.033358 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9635 04:38:10.036782 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9636 04:38:10.040376 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9637 04:38:10.046962 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9638 04:38:10.050518 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9639 04:38:10.056997 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9640 04:38:10.059963 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9641 04:38:10.064048 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9642 04:38:10.066722 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9643 04:38:10.073291 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9644 04:38:10.076952 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9645 04:38:10.079991 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9646 04:38:10.087027 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9647 04:38:10.089974 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9648 04:38:10.093576 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9649 04:38:10.097255 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9650 04:38:10.103674 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9651 04:38:10.107274 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9652 04:38:10.113580 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9653 04:38:10.117162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9654 04:38:10.120231 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9655 04:38:10.126881 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9656 04:38:10.130316 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9657 04:38:10.133288 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9658 04:38:10.140481 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9659 04:38:10.143461 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9660 04:38:10.150061 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9661 04:38:10.153619 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9662 04:38:10.157049 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9663 04:38:10.163703 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9664 04:38:10.167336 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9665 04:38:10.173880 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9666 04:38:10.176988 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9667 04:38:10.180433 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9668 04:38:10.187086 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9669 04:38:10.190044 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9670 04:38:10.193587 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9671 04:38:10.200086 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9672 04:38:10.203772 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9673 04:38:10.209935 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9674 04:38:10.213662 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9675 04:38:10.217234 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9676 04:38:10.223598 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9677 04:38:10.227080 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9678 04:38:10.233477 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9679 04:38:10.237017 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9680 04:38:10.239968 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9681 04:38:10.247140 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9682 04:38:10.250214 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9683 04:38:10.256997 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9684 04:38:10.259978 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9685 04:38:10.263423 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9686 04:38:10.269877 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9687 04:38:10.272953 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9688 04:38:10.279933 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9689 04:38:10.283275 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9690 04:38:10.286502 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9691 04:38:10.293346 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9692 04:38:10.296752 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9693 04:38:10.299634 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9694 04:38:10.306207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9695 04:38:10.309971 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9696 04:38:10.316130 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9697 04:38:10.319563 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9698 04:38:10.322926 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9699 04:38:10.329466 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9700 04:38:10.333305 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9701 04:38:10.339599 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9702 04:38:10.342977 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9703 04:38:10.346328 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9704 04:38:10.352565 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9705 04:38:10.355898 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9706 04:38:10.363051 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9707 04:38:10.365932 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9708 04:38:10.369507 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9709 04:38:10.375986 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9710 04:38:10.379096 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9711 04:38:10.385680 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9712 04:38:10.389185 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9713 04:38:10.392707 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9714 04:38:10.398933 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9715 04:38:10.402308 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9716 04:38:10.409222 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9717 04:38:10.412638 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9718 04:38:10.415628 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9719 04:38:10.422193 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9720 04:38:10.425315 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9721 04:38:10.432580 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9722 04:38:10.435631 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9723 04:38:10.442247 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9724 04:38:10.445715 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9725 04:38:10.448630 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9726 04:38:10.455324 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9727 04:38:10.458848 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9728 04:38:10.465471 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9729 04:38:10.468330 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9730 04:38:10.475318 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9731 04:38:10.478273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9732 04:38:10.481941 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9733 04:38:10.488765 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9734 04:38:10.491800 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9735 04:38:10.498206 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9736 04:38:10.501765 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9737 04:38:10.507914 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9738 04:38:10.511543 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9739 04:38:10.514367 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9740 04:38:10.521058 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9741 04:38:10.524683 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9742 04:38:10.531182 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9743 04:38:10.534338 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9744 04:38:10.537469 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9745 04:38:10.544714 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9746 04:38:10.547502 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9747 04:38:10.554109 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9748 04:38:10.557769 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9749 04:38:10.564295 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9750 04:38:10.567679 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9751 04:38:10.570712 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9752 04:38:10.577262 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9753 04:38:10.580803 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9754 04:38:10.587297 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9755 04:38:10.590964 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9756 04:38:10.594054 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9757 04:38:10.597579 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9758 04:38:10.603643 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9759 04:38:10.607362 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9760 04:38:10.610320 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9761 04:38:10.617012 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9762 04:38:10.620619 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9763 04:38:10.623645 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9764 04:38:10.630446 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9765 04:38:10.633778 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9766 04:38:10.637348 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9767 04:38:10.644091 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9768 04:38:10.647155 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9769 04:38:10.650550 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9770 04:38:10.656961 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9771 04:38:10.660423 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9772 04:38:10.666980 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9773 04:38:10.670342 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9774 04:38:10.673298 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9775 04:38:10.680408 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9776 04:38:10.683287 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9777 04:38:10.690094 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9778 04:38:10.693177 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9779 04:38:10.696814 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9780 04:38:10.703430 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9781 04:38:10.706865 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9782 04:38:10.709884 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9783 04:38:10.716511 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9784 04:38:10.720470 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9785 04:38:10.723278 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9786 04:38:10.729938 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9787 04:38:10.733000 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9788 04:38:10.739568 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9789 04:38:10.742963 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9790 04:38:10.746633 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9791 04:38:10.753378 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9792 04:38:10.756675 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9793 04:38:10.759927 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9794 04:38:10.766477 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9795 04:38:10.769419 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9796 04:38:10.773134 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9797 04:38:10.776086 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9798 04:38:10.782635 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9799 04:38:10.786260 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9800 04:38:10.789330 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9801 04:38:10.792907 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9802 04:38:10.799472 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9803 04:38:10.802803 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9804 04:38:10.806259 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9805 04:38:10.809331 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9806 04:38:10.815828 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9807 04:38:10.819311 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9808 04:38:10.822368 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9809 04:38:10.829062 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9810 04:38:10.832756 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9811 04:38:10.839307 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9812 04:38:10.842302 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9813 04:38:10.849022 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9814 04:38:10.852309 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9815 04:38:10.855723 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9816 04:38:10.862482 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9817 04:38:10.865473 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9818 04:38:10.871889 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9819 04:38:10.875826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9820 04:38:10.879073 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9821 04:38:10.885326 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9822 04:38:10.888888 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9823 04:38:10.895545 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9824 04:38:10.898516 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9825 04:38:10.902071 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9826 04:38:10.908779 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9827 04:38:10.912177 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9828 04:38:10.918665 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9829 04:38:10.922106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9830 04:38:10.928700 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9831 04:38:10.931721 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9832 04:38:10.935303 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9833 04:38:10.941968 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9834 04:38:10.945038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9835 04:38:10.951698 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9836 04:38:10.955312 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9837 04:38:10.958289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9838 04:38:10.965161 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9839 04:38:10.968308 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9840 04:38:10.975012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9841 04:38:10.978350 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9842 04:38:10.981781 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9843 04:38:10.988252 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9844 04:38:10.991649 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9845 04:38:10.998263 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9846 04:38:11.001265 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9847 04:38:11.004781 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9848 04:38:11.011568 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9849 04:38:11.014628 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9850 04:38:11.021310 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9851 04:38:11.024750 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9852 04:38:11.031339 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9853 04:38:11.034310 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9854 04:38:11.037906 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9855 04:38:11.044650 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9856 04:38:11.047714 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9857 04:38:11.054397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9858 04:38:11.057552 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9859 04:38:11.061194 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9860 04:38:11.068145 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9861 04:38:11.070923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9862 04:38:11.077614 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9863 04:38:11.081037 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9864 04:38:11.084437 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9865 04:38:11.090929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9866 04:38:11.094461 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9867 04:38:11.101002 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9868 04:38:11.104609 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9869 04:38:11.110819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9870 04:38:11.114401 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9871 04:38:11.117301 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9872 04:38:11.124245 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9873 04:38:11.127827 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9874 04:38:11.134084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9875 04:38:11.137187 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9876 04:38:11.140745 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9877 04:38:11.147491 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9878 04:38:11.150520 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9879 04:38:11.157150 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9880 04:38:11.160745 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9881 04:38:11.163787 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9882 04:38:11.170502 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9883 04:38:11.173448 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9884 04:38:11.180091 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9885 04:38:11.183420 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9886 04:38:11.190874 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9887 04:38:11.193804 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9888 04:38:11.197038 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9889 04:38:11.203299 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9890 04:38:11.207048 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9891 04:38:11.213489 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9892 04:38:11.216747 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9893 04:38:11.223585 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9894 04:38:11.226437 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9895 04:38:11.233535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9896 04:38:11.236916 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9897 04:38:11.239825 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9898 04:38:11.246295 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9899 04:38:11.250128 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9900 04:38:11.256838 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9901 04:38:11.259989 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9902 04:38:11.266578 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9903 04:38:11.269649 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9904 04:38:11.273239 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9905 04:38:11.279839 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9906 04:38:11.283361 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9907 04:38:11.289678 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9908 04:38:11.293084 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9909 04:38:11.299681 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9910 04:38:11.302791 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9911 04:38:11.309380 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9912 04:38:11.312674 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9913 04:38:11.315936 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9914 04:38:11.322750 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9915 04:38:11.326171 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9916 04:38:11.333079 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9917 04:38:11.336317 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9918 04:38:11.342792 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9919 04:38:11.346154 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9920 04:38:11.349061 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9921 04:38:11.356160 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9922 04:38:11.359340 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9923 04:38:11.365883 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9924 04:38:11.369007 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9925 04:38:11.375670 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9926 04:38:11.379275 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9927 04:38:11.385911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9928 04:38:11.389015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9929 04:38:11.392668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9930 04:38:11.398938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9931 04:38:11.402540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9932 04:38:11.409262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9933 04:38:11.412264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9934 04:38:11.418963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9935 04:38:11.422079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9936 04:38:11.428572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9937 04:38:11.432006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9938 04:38:11.438817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9939 04:38:11.442250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9940 04:38:11.448701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9941 04:38:11.452183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9942 04:38:11.458607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9943 04:38:11.461588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9944 04:38:11.468468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9945 04:38:11.472104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9946 04:38:11.478670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9947 04:38:11.481752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9948 04:38:11.485060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9949 04:38:11.492028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9950 04:38:11.495032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9951 04:38:11.501982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9952 04:38:11.505354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9953 04:38:11.511916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9954 04:38:11.515019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9955 04:38:11.522050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9956 04:38:11.524884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9957 04:38:11.531982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9958 04:38:11.535473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9959 04:38:11.541637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9960 04:38:11.544936 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9961 04:38:11.548409 INFO: [APUAPC] vio 0
9962 04:38:11.551750 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9963 04:38:11.558555 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9964 04:38:11.561465 INFO: [APUAPC] D0_APC_0: 0x400510
9965 04:38:11.564898 INFO: [APUAPC] D0_APC_1: 0x0
9966 04:38:11.568282 INFO: [APUAPC] D0_APC_2: 0x1540
9967 04:38:11.568411 INFO: [APUAPC] D0_APC_3: 0x0
9968 04:38:11.571826 INFO: [APUAPC] D1_APC_0: 0xffffffff
9969 04:38:11.574840 INFO: [APUAPC] D1_APC_1: 0xffffffff
9970 04:38:11.578558 INFO: [APUAPC] D1_APC_2: 0x3fffff
9971 04:38:11.581694 INFO: [APUAPC] D1_APC_3: 0x0
9972 04:38:11.584667 INFO: [APUAPC] D2_APC_0: 0xffffffff
9973 04:38:11.588419 INFO: [APUAPC] D2_APC_1: 0xffffffff
9974 04:38:11.591294 INFO: [APUAPC] D2_APC_2: 0x3fffff
9975 04:38:11.594535 INFO: [APUAPC] D2_APC_3: 0x0
9976 04:38:11.598056 INFO: [APUAPC] D3_APC_0: 0xffffffff
9977 04:38:11.601050 INFO: [APUAPC] D3_APC_1: 0xffffffff
9978 04:38:11.604755 INFO: [APUAPC] D3_APC_2: 0x3fffff
9979 04:38:11.608022 INFO: [APUAPC] D3_APC_3: 0x0
9980 04:38:11.611321 INFO: [APUAPC] D4_APC_0: 0xffffffff
9981 04:38:11.614322 INFO: [APUAPC] D4_APC_1: 0xffffffff
9982 04:38:11.618035 INFO: [APUAPC] D4_APC_2: 0x3fffff
9983 04:38:11.621213 INFO: [APUAPC] D4_APC_3: 0x0
9984 04:38:11.624776 INFO: [APUAPC] D5_APC_0: 0xffffffff
9985 04:38:11.627537 INFO: [APUAPC] D5_APC_1: 0xffffffff
9986 04:38:11.631170 INFO: [APUAPC] D5_APC_2: 0x3fffff
9987 04:38:11.634247 INFO: [APUAPC] D5_APC_3: 0x0
9988 04:38:11.637840 INFO: [APUAPC] D6_APC_0: 0xffffffff
9989 04:38:11.640624 INFO: [APUAPC] D6_APC_1: 0xffffffff
9990 04:38:11.644381 INFO: [APUAPC] D6_APC_2: 0x3fffff
9991 04:38:11.647644 INFO: [APUAPC] D6_APC_3: 0x0
9992 04:38:11.651145 INFO: [APUAPC] D7_APC_0: 0xffffffff
9993 04:38:11.654040 INFO: [APUAPC] D7_APC_1: 0xffffffff
9994 04:38:11.657406 INFO: [APUAPC] D7_APC_2: 0x3fffff
9995 04:38:11.660659 INFO: [APUAPC] D7_APC_3: 0x0
9996 04:38:11.663724 INFO: [APUAPC] D8_APC_0: 0xffffffff
9997 04:38:11.667042 INFO: [APUAPC] D8_APC_1: 0xffffffff
9998 04:38:11.670731 INFO: [APUAPC] D8_APC_2: 0x3fffff
9999 04:38:11.674212 INFO: [APUAPC] D8_APC_3: 0x0
10000 04:38:11.677370 INFO: [APUAPC] D9_APC_0: 0xffffffff
10001 04:38:11.680649 INFO: [APUAPC] D9_APC_1: 0xffffffff
10002 04:38:11.683655 INFO: [APUAPC] D9_APC_2: 0x3fffff
10003 04:38:11.687272 INFO: [APUAPC] D9_APC_3: 0x0
10004 04:38:11.690355 INFO: [APUAPC] D10_APC_0: 0xffffffff
10005 04:38:11.693875 INFO: [APUAPC] D10_APC_1: 0xffffffff
10006 04:38:11.696966 INFO: [APUAPC] D10_APC_2: 0x3fffff
10007 04:38:11.700513 INFO: [APUAPC] D10_APC_3: 0x0
10008 04:38:11.703427 INFO: [APUAPC] D11_APC_0: 0xffffffff
10009 04:38:11.707186 INFO: [APUAPC] D11_APC_1: 0xffffffff
10010 04:38:11.710116 INFO: [APUAPC] D11_APC_2: 0x3fffff
10011 04:38:11.713364 INFO: [APUAPC] D11_APC_3: 0x0
10012 04:38:11.716903 INFO: [APUAPC] D12_APC_0: 0xffffffff
10013 04:38:11.720366 INFO: [APUAPC] D12_APC_1: 0xffffffff
10014 04:38:11.723524 INFO: [APUAPC] D12_APC_2: 0x3fffff
10015 04:38:11.727070 INFO: [APUAPC] D12_APC_3: 0x0
10016 04:38:11.730181 INFO: [APUAPC] D13_APC_0: 0xffffffff
10017 04:38:11.733562 INFO: [APUAPC] D13_APC_1: 0xffffffff
10018 04:38:11.736564 INFO: [APUAPC] D13_APC_2: 0x3fffff
10019 04:38:11.739750 INFO: [APUAPC] D13_APC_3: 0x0
10020 04:38:11.743080 INFO: [APUAPC] D14_APC_0: 0xffffffff
10021 04:38:11.746728 INFO: [APUAPC] D14_APC_1: 0xffffffff
10022 04:38:11.750120 INFO: [APUAPC] D14_APC_2: 0x3fffff
10023 04:38:11.752960 INFO: [APUAPC] D14_APC_3: 0x0
10024 04:38:11.756379 INFO: [APUAPC] D15_APC_0: 0xffffffff
10025 04:38:11.759963 INFO: [APUAPC] D15_APC_1: 0xffffffff
10026 04:38:11.763013 INFO: [APUAPC] D15_APC_2: 0x3fffff
10027 04:38:11.766542 INFO: [APUAPC] D15_APC_3: 0x0
10028 04:38:11.769815 INFO: [APUAPC] APC_CON: 0x4
10029 04:38:11.773150 INFO: [NOCDAPC] D0_APC_0: 0x0
10030 04:38:11.776309 INFO: [NOCDAPC] D0_APC_1: 0x0
10031 04:38:11.779515 INFO: [NOCDAPC] D1_APC_0: 0x0
10032 04:38:11.782970 INFO: [NOCDAPC] D1_APC_1: 0xfff
10033 04:38:11.783087 INFO: [NOCDAPC] D2_APC_0: 0x0
10034 04:38:11.786264 INFO: [NOCDAPC] D2_APC_1: 0xfff
10035 04:38:11.789525 INFO: [NOCDAPC] D3_APC_0: 0x0
10036 04:38:11.792872 INFO: [NOCDAPC] D3_APC_1: 0xfff
10037 04:38:11.796623 INFO: [NOCDAPC] D4_APC_0: 0x0
10038 04:38:11.799533 INFO: [NOCDAPC] D4_APC_1: 0xfff
10039 04:38:11.803150 INFO: [NOCDAPC] D5_APC_0: 0x0
10040 04:38:11.806108 INFO: [NOCDAPC] D5_APC_1: 0xfff
10041 04:38:11.809688 INFO: [NOCDAPC] D6_APC_0: 0x0
10042 04:38:11.812812 INFO: [NOCDAPC] D6_APC_1: 0xfff
10043 04:38:11.816391 INFO: [NOCDAPC] D7_APC_0: 0x0
10044 04:38:11.816468 INFO: [NOCDAPC] D7_APC_1: 0xfff
10045 04:38:11.819287 INFO: [NOCDAPC] D8_APC_0: 0x0
10046 04:38:11.822881 INFO: [NOCDAPC] D8_APC_1: 0xfff
10047 04:38:11.826233 INFO: [NOCDAPC] D9_APC_0: 0x0
10048 04:38:11.829326 INFO: [NOCDAPC] D9_APC_1: 0xfff
10049 04:38:11.832678 INFO: [NOCDAPC] D10_APC_0: 0x0
10050 04:38:11.836256 INFO: [NOCDAPC] D10_APC_1: 0xfff
10051 04:38:11.839349 INFO: [NOCDAPC] D11_APC_0: 0x0
10052 04:38:11.843042 INFO: [NOCDAPC] D11_APC_1: 0xfff
10053 04:38:11.846176 INFO: [NOCDAPC] D12_APC_0: 0x0
10054 04:38:11.849201 INFO: [NOCDAPC] D12_APC_1: 0xfff
10055 04:38:11.852624 INFO: [NOCDAPC] D13_APC_0: 0x0
10056 04:38:11.855921 INFO: [NOCDAPC] D13_APC_1: 0xfff
10057 04:38:11.855997 INFO: [NOCDAPC] D14_APC_0: 0x0
10058 04:38:11.859065 INFO: [NOCDAPC] D14_APC_1: 0xfff
10059 04:38:11.862891 INFO: [NOCDAPC] D15_APC_0: 0x0
10060 04:38:11.865925 INFO: [NOCDAPC] D15_APC_1: 0xfff
10061 04:38:11.869215 INFO: [NOCDAPC] APC_CON: 0x4
10062 04:38:11.872345 INFO: [APUAPC] set_apusys_apc done
10063 04:38:11.875837 INFO: [DEVAPC] devapc_init done
10064 04:38:11.879565 INFO: GICv3 without legacy support detected.
10065 04:38:11.885753 INFO: ARM GICv3 driver initialized in EL3
10066 04:38:11.889304 INFO: Maximum SPI INTID supported: 639
10067 04:38:11.892474 INFO: BL31: Initializing runtime services
10068 04:38:11.899012 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10069 04:38:11.899086 INFO: SPM: enable CPC mode
10070 04:38:11.905713 INFO: mcdi ready for mcusys-off-idle and system suspend
10071 04:38:11.909325 INFO: BL31: Preparing for EL3 exit to normal world
10072 04:38:11.915431 INFO: Entry point address = 0x80000000
10073 04:38:11.915535 INFO: SPSR = 0x8
10074 04:38:11.922099
10075 04:38:11.922167
10076 04:38:11.922228
10077 04:38:11.925017 Starting depthcharge on Spherion...
10078 04:38:11.925093
10079 04:38:11.925158 Wipe memory regions:
10080 04:38:11.925221
10081 04:38:11.925867 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10082 04:38:11.925965 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10083 04:38:11.926056 Setting prompt string to ['asurada:']
10084 04:38:11.926361 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10085 04:38:11.928212 [0x00000040000000, 0x00000054600000)
10086 04:38:12.050861
10087 04:38:12.051020 [0x00000054660000, 0x00000080000000)
10088 04:38:12.311307
10089 04:38:12.311467 [0x000000821a7280, 0x000000ffe64000)
10090 04:38:13.056301
10091 04:38:13.056442 [0x00000100000000, 0x00000240000000)
10092 04:38:14.946840
10093 04:38:14.949947 Initializing XHCI USB controller at 0x11200000.
10094 04:38:15.988170
10095 04:38:15.991679 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10096 04:38:15.991769
10097 04:38:15.991845
10098 04:38:15.991905
10099 04:38:15.992178 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10101 04:38:16.092502 asurada: tftpboot 192.168.201.1 11241313/tftp-deploy-_3v05fm7/kernel/image.itb 11241313/tftp-deploy-_3v05fm7/kernel/cmdline
10102 04:38:16.092662 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10103 04:38:16.092784 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10104 04:38:16.097491 tftpboot 192.168.201.1 11241313/tftp-deploy-_3v05fm7/kernel/image.itp-deploy-_3v05fm7/kernel/cmdline
10105 04:38:16.097583
10106 04:38:16.097649 Waiting for link
10107 04:38:16.258016
10108 04:38:16.258161 R8152: Initializing
10109 04:38:16.258231
10110 04:38:16.261102 Version 6 (ocp_data = 5c30)
10111 04:38:16.261183
10112 04:38:16.264686 R8152: Done initializing
10113 04:38:16.264766
10114 04:38:16.264848 Adding net device
10115 04:38:18.168304
10116 04:38:18.168782 done.
10117 04:38:18.169113
10118 04:38:18.169417 MAC: 00:24:32:30:78:ff
10119 04:38:18.169767
10120 04:38:18.171156 Sending DHCP discover... done.
10121 04:38:18.171605
10122 04:38:21.777517 Waiting for reply... done.
10123 04:38:21.778265
10124 04:38:21.778661 Sending DHCP request... done.
10125 04:38:21.780629
10126 04:38:21.795644 Waiting for reply... done.
10127 04:38:21.796063
10128 04:38:21.796388 My ip is 192.168.201.21
10129 04:38:21.796691
10130 04:38:21.798789 The DHCP server ip is 192.168.201.1
10131 04:38:21.799284
10132 04:38:21.805531 TFTP server IP predefined by user: 192.168.201.1
10133 04:38:21.805985
10134 04:38:21.812195 Bootfile predefined by user: 11241313/tftp-deploy-_3v05fm7/kernel/image.itb
10135 04:38:21.812699
10136 04:38:21.813044 Sending tftp read request... done.
10137 04:38:21.814844
10138 04:38:21.821758 Waiting for the transfer...
10139 04:38:21.822195
10140 04:38:22.408792 00000000 ################################################################
10141 04:38:22.408934
10142 04:38:22.954393 00080000 ################################################################
10143 04:38:22.954559
10144 04:38:23.509626 00100000 ################################################################
10145 04:38:23.509763
10146 04:38:24.050126 00180000 ################################################################
10147 04:38:24.050261
10148 04:38:24.619779 00200000 ################################################################
10149 04:38:24.619921
10150 04:38:25.222122 00280000 ################################################################
10151 04:38:25.222284
10152 04:38:25.828522 00300000 ################################################################
10153 04:38:25.828658
10154 04:38:26.456272 00380000 ################################################################
10155 04:38:26.456415
10156 04:38:27.002481 00400000 ################################################################
10157 04:38:27.002616
10158 04:38:27.567778 00480000 ################################################################
10159 04:38:27.567912
10160 04:38:28.118805 00500000 ################################################################
10161 04:38:28.118936
10162 04:38:28.708288 00580000 ################################################################
10163 04:38:28.708425
10164 04:38:29.287278 00600000 ################################################################
10165 04:38:29.287448
10166 04:38:29.879919 00680000 ################################################################
10167 04:38:29.880062
10168 04:38:30.443864 00700000 ################################################################
10169 04:38:30.443995
10170 04:38:31.076520 00780000 ################################################################
10171 04:38:31.077061
10172 04:38:31.755977 00800000 ################################################################
10173 04:38:31.756551
10174 04:38:32.442811 00880000 ################################################################
10175 04:38:32.443348
10176 04:38:33.039905 00900000 ################################################################
10177 04:38:33.040039
10178 04:38:33.613479 00980000 ################################################################
10179 04:38:33.613613
10180 04:38:34.203865 00a00000 ################################################################
10181 04:38:34.204011
10182 04:38:34.873889 00a80000 ################################################################
10183 04:38:34.874456
10184 04:38:35.496723 00b00000 ################################################################
10185 04:38:35.496893
10186 04:38:36.112903 00b80000 ################################################################
10187 04:38:36.113036
10188 04:38:36.734118 00c00000 ################################################################
10189 04:38:36.734266
10190 04:38:37.287424 00c80000 ################################################################
10191 04:38:37.287586
10192 04:38:37.845084 00d00000 ################################################################
10193 04:38:37.845221
10194 04:38:38.391978 00d80000 ################################################################
10195 04:38:38.392116
10196 04:38:38.947185 00e00000 ################################################################
10197 04:38:38.947323
10198 04:38:39.496525 00e80000 ################################################################
10199 04:38:39.496686
10200 04:38:40.038267 00f00000 ################################################################
10201 04:38:40.038406
10202 04:38:40.570810 00f80000 ################################################################
10203 04:38:40.570961
10204 04:38:41.120995 01000000 ################################################################
10205 04:38:41.121132
10206 04:38:41.663719 01080000 ################################################################
10207 04:38:41.663854
10208 04:38:42.232208 01100000 ################################################################
10209 04:38:42.232341
10210 04:38:42.824652 01180000 ################################################################
10211 04:38:42.824813
10212 04:38:43.373612 01200000 ################################################################
10213 04:38:43.373746
10214 04:38:43.903107 01280000 ################################################################
10215 04:38:43.903241
10216 04:38:44.510287 01300000 ################################################################
10217 04:38:44.510438
10218 04:38:45.102599 01380000 ################################################################
10219 04:38:45.102750
10220 04:38:45.693536 01400000 ################################################################
10221 04:38:45.693671
10222 04:38:46.285655 01480000 ################################################################
10223 04:38:46.285791
10224 04:38:46.862528 01500000 ################################################################
10225 04:38:46.862665
10226 04:38:47.425286 01580000 ################################################################
10227 04:38:47.425418
10228 04:38:47.977541 01600000 ################################################################
10229 04:38:47.977680
10230 04:38:48.542315 01680000 ################################################################
10231 04:38:48.542502
10232 04:38:49.121010 01700000 ################################################################
10233 04:38:49.121164
10234 04:38:49.666087 01780000 ################################################################
10235 04:38:49.666241
10236 04:38:50.211779 01800000 ################################################################
10237 04:38:50.211931
10238 04:38:50.785302 01880000 ################################################################
10239 04:38:50.785456
10240 04:38:51.318155 01900000 ################################################################
10241 04:38:51.318332
10242 04:38:51.853504 01980000 ################################################################
10243 04:38:51.853661
10244 04:38:52.407679 01a00000 ################################################################
10245 04:38:52.407829
10246 04:38:52.938752 01a80000 ################################################################
10247 04:38:52.938899
10248 04:38:53.415186 01b00000 ###################################################### done.
10249 04:38:53.415319
10250 04:38:53.418012 The bootfile was 28751298 bytes long.
10251 04:38:53.418112
10252 04:38:53.421240 Sending tftp read request... done.
10253 04:38:53.421325
10254 04:38:53.421395 Waiting for the transfer...
10255 04:38:53.421486
10256 04:38:53.424655 00000000 # done.
10257 04:38:53.424741
10258 04:38:53.431604 Command line loaded dynamically from TFTP file: 11241313/tftp-deploy-_3v05fm7/kernel/cmdline
10259 04:38:53.431687
10260 04:38:53.454818 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11241313/extract-nfsrootfs-izw72tpv,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10261 04:38:53.454911
10262 04:38:53.454997 Loading FIT.
10263 04:38:53.455095
10264 04:38:53.457723 Image ramdisk-1 has 17665617 bytes.
10265 04:38:53.457805
10266 04:38:53.461187 Image fdt-1 has 47278 bytes.
10267 04:38:53.461271
10268 04:38:53.464290 Image kernel-1 has 11036366 bytes.
10269 04:38:53.464371
10270 04:38:53.474204 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10271 04:38:53.474313
10272 04:38:53.490757 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10273 04:38:53.490849
10274 04:38:53.497616 Choosing best match conf-1 for compat google,spherion-rev2.
10275 04:38:53.497698
10276 04:38:53.505268 Connected to device vid:did:rid of 1ae0:0028:00
10277 04:38:53.513492
10278 04:38:53.516598 tpm_get_response: command 0x17b, return code 0x0
10279 04:38:53.516680
10280 04:38:53.519907 ec_init: CrosEC protocol v3 supported (256, 248)
10281 04:38:53.523812
10282 04:38:53.527262 tpm_cleanup: add release locality here.
10283 04:38:53.527343
10284 04:38:53.527451 Shutting down all USB controllers.
10285 04:38:53.530706
10286 04:38:53.530788 Removing current net device
10287 04:38:53.530854
10288 04:38:53.536918 Exiting depthcharge with code 4 at timestamp: 70898064
10289 04:38:53.537001
10290 04:38:53.540521 LZMA decompressing kernel-1 to 0x821a6718
10291 04:38:53.540603
10292 04:38:53.543348 LZMA decompressing kernel-1 to 0x40000000
10293 04:38:54.932199
10294 04:38:54.932366 jumping to kernel
10295 04:38:54.933129 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10296 04:38:54.933287 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10297 04:38:54.933380 Setting prompt string to ['Linux version [0-9]']
10298 04:38:54.933478 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10299 04:38:54.933568 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10300 04:38:55.015045
10301 04:38:55.018342 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10302 04:38:55.021831 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10303 04:38:55.021947 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10304 04:38:55.022057 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10305 04:38:55.022132 Using line separator: #'\n'#
10306 04:38:55.022192 No login prompt set.
10307 04:38:55.022260 Parsing kernel messages
10308 04:38:55.022317 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10309 04:38:55.022419 [login-action] Waiting for messages, (timeout 00:03:42)
10310 04:38:55.041347 [ 0.000000] Linux version 6.1.42-cip2 (KernelCI@build-j7071-arm64-gcc-10-defconfig-arm64-chromebook-7p24g) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 9 04:18:34 UTC 2023
10311 04:38:55.044559 [ 0.000000] random: crng init done
10312 04:38:55.051299 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10313 04:38:55.051442 [ 0.000000] efi: UEFI not found.
10314 04:38:55.061756 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10315 04:38:55.067938 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10316 04:38:55.078014 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10317 04:38:55.087595 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10318 04:38:55.094508 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10319 04:38:55.101019 [ 0.000000] printk: bootconsole [mtk8250] enabled
10320 04:38:55.107586 [ 0.000000] NUMA: No NUMA configuration found
10321 04:38:55.114128 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10322 04:38:55.117702 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10323 04:38:55.120846 [ 0.000000] Zone ranges:
10324 04:38:55.127362 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10325 04:38:55.130985 [ 0.000000] DMA32 empty
10326 04:38:55.137646 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10327 04:38:55.141004 [ 0.000000] Movable zone start for each node
10328 04:38:55.144060 [ 0.000000] Early memory node ranges
10329 04:38:55.150678 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10330 04:38:55.157522 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10331 04:38:55.163921 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10332 04:38:55.170476 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10333 04:38:55.173686 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10334 04:38:55.183272 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10335 04:38:55.238820 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10336 04:38:55.245176 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10337 04:38:55.251711 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10338 04:38:55.255000 [ 0.000000] psci: probing for conduit method from DT.
10339 04:38:55.261897 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10340 04:38:55.264970 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10341 04:38:55.272063 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10342 04:38:55.274994 [ 0.000000] psci: SMC Calling Convention v1.2
10343 04:38:55.281644 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10344 04:38:55.285034 [ 0.000000] Detected VIPT I-cache on CPU0
10345 04:38:55.291572 [ 0.000000] CPU features: detected: GIC system register CPU interface
10346 04:38:55.298078 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10347 04:38:55.304596 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10348 04:38:55.311311 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10349 04:38:55.320884 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10350 04:38:55.327894 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10351 04:38:55.330782 [ 0.000000] alternatives: applying boot alternatives
10352 04:38:55.337583 [ 0.000000] Fallback order for Node 0: 0
10353 04:38:55.344210 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10354 04:38:55.347782 [ 0.000000] Policy zone: Normal
10355 04:38:55.371045 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11241313/extract-nfsrootfs-izw72tpv,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10356 04:38:55.380316 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10357 04:38:55.392193 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10358 04:38:55.401877 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10359 04:38:55.408582 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10360 04:38:55.411223 <6>[ 0.000000] software IO TLB: area num 8.
10361 04:38:55.468045 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10362 04:38:55.616974 <6>[ 0.000000] Memory: 7952304K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 400464K reserved, 32768K cma-reserved)
10363 04:38:55.623721 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10364 04:38:55.630495 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10365 04:38:55.633794 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10366 04:38:55.640429 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10367 04:38:55.646833 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10368 04:38:55.650108 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10369 04:38:55.660438 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10370 04:38:55.666863 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10371 04:38:55.673528 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10372 04:38:55.680193 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10373 04:38:55.683580 <6>[ 0.000000] GICv3: 608 SPIs implemented
10374 04:38:55.686498 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10375 04:38:55.693217 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10376 04:38:55.696490 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10377 04:38:55.703169 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10378 04:38:55.716503 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10379 04:38:55.729565 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10380 04:38:55.736077 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10381 04:38:55.743845 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10382 04:38:55.757050 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10383 04:38:55.763600 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10384 04:38:55.770424 <6>[ 0.009182] Console: colour dummy device 80x25
10385 04:38:55.780101 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10386 04:38:55.786663 <6>[ 0.024343] pid_max: default: 32768 minimum: 301
10387 04:38:55.790119 <6>[ 0.029215] LSM: Security Framework initializing
10388 04:38:55.796499 <6>[ 0.034180] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 04:38:55.806560 <6>[ 0.042042] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10390 04:38:55.816478 <6>[ 0.051476] cblist_init_generic: Setting adjustable number of callback queues.
10391 04:38:55.819800 <6>[ 0.058922] cblist_init_generic: Setting shift to 3 and lim to 1.
10392 04:38:55.829374 <6>[ 0.065260] cblist_init_generic: Setting adjustable number of callback queues.
10393 04:38:55.836512 <6>[ 0.072688] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 04:38:55.839309 <6>[ 0.079085] rcu: Hierarchical SRCU implementation.
10395 04:38:55.846600 <6>[ 0.084099] rcu: Max phase no-delay instances is 1000.
10396 04:38:55.852714 <6>[ 0.091129] EFI services will not be available.
10397 04:38:55.856017 <6>[ 0.096098] smp: Bringing up secondary CPUs ...
10398 04:38:55.864837 <6>[ 0.101147] Detected VIPT I-cache on CPU1
10399 04:38:55.871303 <6>[ 0.101219] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10400 04:38:55.877669 <6>[ 0.101249] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10401 04:38:55.881381 <6>[ 0.101586] Detected VIPT I-cache on CPU2
10402 04:38:55.888097 <6>[ 0.101639] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10403 04:38:55.894708 <6>[ 0.101657] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10404 04:38:55.901137 <6>[ 0.101916] Detected VIPT I-cache on CPU3
10405 04:38:55.907523 <6>[ 0.101963] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10406 04:38:55.914545 <6>[ 0.101978] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10407 04:38:55.917631 <6>[ 0.102281] CPU features: detected: Spectre-v4
10408 04:38:55.923971 <6>[ 0.102287] CPU features: detected: Spectre-BHB
10409 04:38:55.927815 <6>[ 0.102293] Detected PIPT I-cache on CPU4
10410 04:38:55.934287 <6>[ 0.102349] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10411 04:38:55.941080 <6>[ 0.102366] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10412 04:38:55.947702 <6>[ 0.102664] Detected PIPT I-cache on CPU5
10413 04:38:55.954061 <6>[ 0.102727] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10414 04:38:55.960868 <6>[ 0.102743] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10415 04:38:55.964314 <6>[ 0.103022] Detected PIPT I-cache on CPU6
10416 04:38:55.970426 <6>[ 0.103086] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10417 04:38:55.977383 <6>[ 0.103103] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10418 04:38:55.984068 <6>[ 0.103402] Detected PIPT I-cache on CPU7
10419 04:38:55.990405 <6>[ 0.103466] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10420 04:38:55.996936 <6>[ 0.103482] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10421 04:38:56.000427 <6>[ 0.103530] smp: Brought up 1 node, 8 CPUs
10422 04:38:56.006590 <6>[ 0.244727] SMP: Total of 8 processors activated.
10423 04:38:56.010429 <6>[ 0.249649] CPU features: detected: 32-bit EL0 Support
10424 04:38:56.020150 <6>[ 0.255011] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10425 04:38:56.026492 <6>[ 0.263811] CPU features: detected: Common not Private translations
10426 04:38:56.033277 <6>[ 0.270287] CPU features: detected: CRC32 instructions
10427 04:38:56.036792 <6>[ 0.275638] CPU features: detected: RCpc load-acquire (LDAPR)
10428 04:38:56.042859 <6>[ 0.281635] CPU features: detected: LSE atomic instructions
10429 04:38:56.049802 <6>[ 0.287416] CPU features: detected: Privileged Access Never
10430 04:38:56.056273 <6>[ 0.293231] CPU features: detected: RAS Extension Support
10431 04:38:56.062808 <6>[ 0.298840] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10432 04:38:56.066578 <6>[ 0.306060] CPU: All CPU(s) started at EL2
10433 04:38:56.072927 <6>[ 0.310377] alternatives: applying system-wide alternatives
10434 04:38:56.081968 <6>[ 0.321109] devtmpfs: initialized
10435 04:38:56.094422 <6>[ 0.330086] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10436 04:38:56.104077 <6>[ 0.340047] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10437 04:38:56.110618 <6>[ 0.348059] pinctrl core: initialized pinctrl subsystem
10438 04:38:56.114088 <6>[ 0.354705] DMI not present or invalid.
10439 04:38:56.120824 <6>[ 0.359116] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10440 04:38:56.130543 <6>[ 0.365904] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10441 04:38:56.137033 <6>[ 0.373487] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10442 04:38:56.146829 <6>[ 0.381699] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10443 04:38:56.150356 <6>[ 0.389940] audit: initializing netlink subsys (disabled)
10444 04:38:56.160492 <5>[ 0.395633] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10445 04:38:56.167149 <6>[ 0.396330] thermal_sys: Registered thermal governor 'step_wise'
10446 04:38:56.173625 <6>[ 0.403599] thermal_sys: Registered thermal governor 'power_allocator'
10447 04:38:56.176655 <6>[ 0.409853] cpuidle: using governor menu
10448 04:38:56.183453 <6>[ 0.420814] NET: Registered PF_QIPCRTR protocol family
10449 04:38:56.189873 <6>[ 0.426310] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10450 04:38:56.196284 <6>[ 0.433413] ASID allocator initialised with 32768 entries
10451 04:38:56.199817 <6>[ 0.439986] Serial: AMBA PL011 UART driver
10452 04:38:56.209311 <4>[ 0.448762] Trying to register duplicate clock ID: 134
10453 04:38:56.265992 <6>[ 0.508464] KASLR enabled
10454 04:38:56.280326 <6>[ 0.516193] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10455 04:38:56.287376 <6>[ 0.523203] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10456 04:38:56.293742 <6>[ 0.529691] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10457 04:38:56.300334 <6>[ 0.536697] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10458 04:38:56.306559 <6>[ 0.543182] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10459 04:38:56.312970 <6>[ 0.550181] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10460 04:38:56.319943 <6>[ 0.556668] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10461 04:38:56.326346 <6>[ 0.563673] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10462 04:38:56.329613 <6>[ 0.571184] ACPI: Interpreter disabled.
10463 04:38:56.338254 <6>[ 0.577626] iommu: Default domain type: Translated
10464 04:38:56.344956 <6>[ 0.582739] iommu: DMA domain TLB invalidation policy: strict mode
10465 04:38:56.348173 <5>[ 0.589397] SCSI subsystem initialized
10466 04:38:56.355341 <6>[ 0.593566] usbcore: registered new interface driver usbfs
10467 04:38:56.361656 <6>[ 0.599299] usbcore: registered new interface driver hub
10468 04:38:56.365038 <6>[ 0.604855] usbcore: registered new device driver usb
10469 04:38:56.371791 <6>[ 0.610958] pps_core: LinuxPPS API ver. 1 registered
10470 04:38:56.381822 <6>[ 0.616152] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10471 04:38:56.385408 <6>[ 0.625496] PTP clock support registered
10472 04:38:56.388303 <6>[ 0.629736] EDAC MC: Ver: 3.0.0
10473 04:38:56.395647 <6>[ 0.634867] FPGA manager framework
10474 04:38:56.402191 <6>[ 0.638551] Advanced Linux Sound Architecture Driver Initialized.
10475 04:38:56.405624 <6>[ 0.645327] vgaarb: loaded
10476 04:38:56.412103 <6>[ 0.648492] clocksource: Switched to clocksource arch_sys_counter
10477 04:38:56.415572 <5>[ 0.654930] VFS: Disk quotas dquot_6.6.0
10478 04:38:56.422174 <6>[ 0.659116] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10479 04:38:56.424994 <6>[ 0.666302] pnp: PnP ACPI: disabled
10480 04:38:56.433851 <6>[ 0.673032] NET: Registered PF_INET protocol family
10481 04:38:56.443528 <6>[ 0.678641] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10482 04:38:56.455095 <6>[ 0.690970] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10483 04:38:56.465160 <6>[ 0.699781] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10484 04:38:56.471815 <6>[ 0.707755] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10485 04:38:56.481788 <6>[ 0.716458] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10486 04:38:56.488361 <6>[ 0.726212] TCP: Hash tables configured (established 65536 bind 65536)
10487 04:38:56.494818 <6>[ 0.733073] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10488 04:38:56.504840 <6>[ 0.740274] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10489 04:38:56.511548 <6>[ 0.747977] NET: Registered PF_UNIX/PF_LOCAL protocol family
10490 04:38:56.514954 <6>[ 0.754129] RPC: Registered named UNIX socket transport module.
10491 04:38:56.521535 <6>[ 0.760284] RPC: Registered udp transport module.
10492 04:38:56.524368 <6>[ 0.765216] RPC: Registered tcp transport module.
10493 04:38:56.534175 <6>[ 0.770148] RPC: Registered tcp NFSv4.1 backchannel transport module.
10494 04:38:56.537531 <6>[ 0.776817] PCI: CLS 0 bytes, default 64
10495 04:38:56.540842 <6>[ 0.781143] Unpacking initramfs...
10496 04:38:56.564791 <6>[ 0.800605] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10497 04:38:56.574665 <6>[ 0.809251] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10498 04:38:56.578238 <6>[ 0.818052] kvm [1]: IPA Size Limit: 40 bits
10499 04:38:56.584697 <6>[ 0.822583] kvm [1]: GICv3: no GICV resource entry
10500 04:38:56.588293 <6>[ 0.827603] kvm [1]: disabling GICv2 emulation
10501 04:38:56.594751 <6>[ 0.832292] kvm [1]: GIC system register CPU interface enabled
10502 04:38:56.598106 <6>[ 0.838478] kvm [1]: vgic interrupt IRQ18
10503 04:38:56.604816 <6>[ 0.842834] kvm [1]: VHE mode initialized successfully
10504 04:38:56.611055 <5>[ 0.849259] Initialise system trusted keyrings
10505 04:38:56.617879 <6>[ 0.854090] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10506 04:38:56.625281 <6>[ 0.864207] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10507 04:38:56.631738 <5>[ 0.870667] NFS: Registering the id_resolver key type
10508 04:38:56.635310 <5>[ 0.875969] Key type id_resolver registered
10509 04:38:56.641561 <5>[ 0.880385] Key type id_legacy registered
10510 04:38:56.648560 <6>[ 0.884671] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10511 04:38:56.654901 <6>[ 0.891592] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10512 04:38:56.661632 <6>[ 0.899308] 9p: Installing v9fs 9p2000 file system support
10513 04:38:56.698141 <5>[ 0.937087] Key type asymmetric registered
10514 04:38:56.701734 <5>[ 0.941438] Asymmetric key parser 'x509' registered
10515 04:38:56.711303 <6>[ 0.946586] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10516 04:38:56.714385 <6>[ 0.954205] io scheduler mq-deadline registered
10517 04:38:56.718178 <6>[ 0.958965] io scheduler kyber registered
10518 04:38:56.737111 <6>[ 0.976100] EINJ: ACPI disabled.
10519 04:38:56.769601 <4>[ 1.001882] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10520 04:38:56.778985 <4>[ 1.012518] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10521 04:38:56.794525 <6>[ 1.033671] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10522 04:38:56.802610 <6>[ 1.041712] printk: console [ttyS0] disabled
10523 04:38:56.830665 <6>[ 1.066353] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10524 04:38:56.837378 <6>[ 1.075826] printk: console [ttyS0] enabled
10525 04:38:56.840849 <6>[ 1.075826] printk: console [ttyS0] enabled
10526 04:38:56.847080 <6>[ 1.084720] printk: bootconsole [mtk8250] disabled
10527 04:38:56.850686 <6>[ 1.084720] printk: bootconsole [mtk8250] disabled
10528 04:38:56.857021 <6>[ 1.096020] SuperH (H)SCI(F) driver initialized
10529 04:38:56.860476 <6>[ 1.101325] msm_serial: driver initialized
10530 04:38:56.874786 <6>[ 1.110327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10531 04:38:56.884301 <6>[ 1.118875] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10532 04:38:56.890868 <6>[ 1.127416] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10533 04:38:56.901254 <6>[ 1.136045] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10534 04:38:56.910899 <6>[ 1.144757] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10535 04:38:56.917514 <6>[ 1.153471] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10536 04:38:56.927294 <6>[ 1.162011] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10537 04:38:56.934182 <6>[ 1.170823] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10538 04:38:56.944325 <6>[ 1.179368] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10539 04:38:56.956177 <6>[ 1.195174] loop: module loaded
10540 04:38:56.962476 <6>[ 1.201294] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10541 04:38:56.985645 <4>[ 1.224704] mtk-pmic-keys: Failed to locate of_node [id: -1]
10542 04:38:56.992124 <6>[ 1.231577] megasas: 07.719.03.00-rc1
10543 04:38:57.002660 <6>[ 1.241400] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10544 04:38:57.008815 <6>[ 1.247882] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10545 04:38:57.025418 <6>[ 1.264438] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10546 04:38:57.081883 <6>[ 1.314561] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10547 04:38:57.275246 <6>[ 1.514754] Freeing initrd memory: 17248K
10548 04:38:57.285947 <6>[ 1.525234] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10549 04:38:57.297108 <6>[ 1.536090] tun: Universal TUN/TAP device driver, 1.6
10550 04:38:57.300030 <6>[ 1.542159] thunder_xcv, ver 1.0
10551 04:38:57.303416 <6>[ 1.545665] thunder_bgx, ver 1.0
10552 04:38:57.307122 <6>[ 1.549159] nicpf, ver 1.0
10553 04:38:57.317405 <6>[ 1.553190] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10554 04:38:57.320661 <6>[ 1.560667] hns3: Copyright (c) 2017 Huawei Corporation.
10555 04:38:57.327343 <6>[ 1.566252] hclge is initializing
10556 04:38:57.330755 <6>[ 1.569827] e1000: Intel(R) PRO/1000 Network Driver
10557 04:38:57.337431 <6>[ 1.574956] e1000: Copyright (c) 1999-2006 Intel Corporation.
10558 04:38:57.340583 <6>[ 1.580968] e1000e: Intel(R) PRO/1000 Network Driver
10559 04:38:57.347243 <6>[ 1.586182] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10560 04:38:57.353986 <6>[ 1.592369] igb: Intel(R) Gigabit Ethernet Network Driver
10561 04:38:57.360387 <6>[ 1.598019] igb: Copyright (c) 2007-2014 Intel Corporation.
10562 04:38:57.367270 <6>[ 1.603854] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10563 04:38:57.373547 <6>[ 1.610372] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10564 04:38:57.376971 <6>[ 1.616834] sky2: driver version 1.30
10565 04:38:57.383920 <6>[ 1.621831] VFIO - User Level meta-driver version: 0.3
10566 04:38:57.390870 <6>[ 1.630093] usbcore: registered new interface driver usb-storage
10567 04:38:57.397740 <6>[ 1.636547] usbcore: registered new device driver onboard-usb-hub
10568 04:38:57.406322 <6>[ 1.645659] mt6397-rtc mt6359-rtc: registered as rtc0
10569 04:38:57.416476 <6>[ 1.651127] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-09T04:38:57 UTC (1691555937)
10570 04:38:57.419839 <6>[ 1.660732] i2c_dev: i2c /dev entries driver
10571 04:38:57.436543 <6>[ 1.672545] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10572 04:38:57.456585 <6>[ 1.695538] cpu cpu0: EM: created perf domain
10573 04:38:57.459762 <6>[ 1.700548] cpu cpu4: EM: created perf domain
10574 04:38:57.466714 <6>[ 1.706158] sdhci: Secure Digital Host Controller Interface driver
10575 04:38:57.473452 <6>[ 1.712592] sdhci: Copyright(c) Pierre Ossman
10576 04:38:57.480172 <6>[ 1.717535] Synopsys Designware Multimedia Card Interface Driver
10577 04:38:57.486441 <6>[ 1.724176] sdhci-pltfm: SDHCI platform and OF driver helper
10578 04:38:57.490144 <6>[ 1.724297] mmc0: CQHCI version 5.10
10579 04:38:57.496985 <6>[ 1.734275] ledtrig-cpu: registered to indicate activity on CPUs
10580 04:38:57.503682 <6>[ 1.741336] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10581 04:38:57.509844 <6>[ 1.748402] usbcore: registered new interface driver usbhid
10582 04:38:57.513457 <6>[ 1.754225] usbhid: USB HID core driver
10583 04:38:57.519941 <6>[ 1.758427] spi_master spi0: will run message pump with realtime priority
10584 04:38:57.563651 <6>[ 1.796379] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10585 04:38:57.583013 <6>[ 1.812263] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10586 04:38:57.586227 <6>[ 1.825884] mmc0: Command Queue Engine enabled
10587 04:38:57.593075 <6>[ 1.830667] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10588 04:38:57.599391 <6>[ 1.837597] cros-ec-spi spi0.0: Chrome EC device registered
10589 04:38:57.602857 <6>[ 1.837927] mmcblk0: mmc0:0001 DA4128 116 GiB
10590 04:38:57.612539 <6>[ 1.852046] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10591 04:38:57.620050 <6>[ 1.859177] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10592 04:38:57.626474 <6>[ 1.865116] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10593 04:38:57.633538 <6>[ 1.870994] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10594 04:38:57.651382 <6>[ 1.887003] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10595 04:38:57.658935 <6>[ 1.897876] NET: Registered PF_PACKET protocol family
10596 04:38:57.662207 <6>[ 1.903277] 9pnet: Installing 9P2000 support
10597 04:38:57.668426 <5>[ 1.907844] Key type dns_resolver registered
10598 04:38:57.671969 <6>[ 1.912862] registered taskstats version 1
10599 04:38:57.678738 <5>[ 1.917254] Loading compiled-in X.509 certificates
10600 04:38:57.708046 <4>[ 1.940337] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 04:38:57.717916 <4>[ 1.951153] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 04:38:57.724325 <3>[ 1.961699] debugfs: File 'uA_load' in directory '/' already present!
10603 04:38:57.730914 <3>[ 1.968404] debugfs: File 'min_uV' in directory '/' already present!
10604 04:38:57.737917 <3>[ 1.975013] debugfs: File 'max_uV' in directory '/' already present!
10605 04:38:57.744199 <3>[ 1.981622] debugfs: File 'constraint_flags' in directory '/' already present!
10606 04:38:57.755135 <3>[ 1.991290] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10607 04:38:57.771027 <6>[ 2.010200] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10608 04:38:57.777910 <6>[ 2.017065] xhci-mtk 11200000.usb: xHCI Host Controller
10609 04:38:57.784500 <6>[ 2.022571] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10610 04:38:57.794561 <6>[ 2.030459] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10611 04:38:57.800960 <6>[ 2.039904] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10612 04:38:57.807834 <6>[ 2.045993] xhci-mtk 11200000.usb: xHCI Host Controller
10613 04:38:57.814388 <6>[ 2.051483] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10614 04:38:57.821090 <6>[ 2.059138] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10615 04:38:57.828032 <6>[ 2.067098] hub 1-0:1.0: USB hub found
10616 04:38:57.831081 <6>[ 2.071121] hub 1-0:1.0: 1 port detected
10617 04:38:57.840980 <6>[ 2.075433] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10618 04:38:57.844472 <6>[ 2.084267] hub 2-0:1.0: USB hub found
10619 04:38:57.847648 <6>[ 2.088290] hub 2-0:1.0: 1 port detected
10620 04:38:57.857407 <6>[ 2.096833] mtk-msdc 11f70000.mmc: Got CD GPIO
10621 04:38:57.869414 <6>[ 2.105298] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10622 04:38:57.875940 <6>[ 2.113326] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10623 04:38:57.886268 <4>[ 2.121245] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10624 04:38:57.896115 <6>[ 2.130827] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10625 04:38:57.903136 <6>[ 2.138905] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10626 04:38:57.908970 <6>[ 2.147066] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10627 04:38:57.919293 <6>[ 2.155008] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10628 04:38:57.925868 <6>[ 2.162831] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10629 04:38:57.935886 <6>[ 2.170648] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10630 04:38:57.945710 <6>[ 2.181236] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10631 04:38:57.952870 <6>[ 2.189623] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10632 04:38:57.962666 <6>[ 2.197968] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10633 04:38:57.968797 <6>[ 2.206310] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10634 04:38:57.978995 <6>[ 2.214647] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10635 04:38:57.985363 <6>[ 2.222984] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10636 04:38:57.995612 <6>[ 2.231323] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10637 04:38:58.001910 <6>[ 2.239661] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10638 04:38:58.012106 <6>[ 2.247998] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10639 04:38:58.019255 <6>[ 2.256345] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10640 04:38:58.028824 <6>[ 2.264683] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10641 04:38:58.035479 <6>[ 2.273022] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10642 04:38:58.045309 <6>[ 2.281360] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10643 04:38:58.052073 <6>[ 2.289698] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10644 04:38:58.062237 <6>[ 2.298035] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10645 04:38:58.068476 <6>[ 2.306781] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10646 04:38:58.075438 <6>[ 2.313970] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10647 04:38:58.081715 <6>[ 2.320747] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10648 04:38:58.088416 <6>[ 2.327513] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10649 04:38:58.098442 <6>[ 2.334451] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10650 04:38:58.105111 <6>[ 2.341309] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10651 04:38:58.114956 <6>[ 2.350441] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10652 04:38:58.124856 <6>[ 2.359561] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10653 04:38:58.134747 <6>[ 2.368857] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10654 04:38:58.144500 <6>[ 2.378326] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10655 04:38:58.151237 <6>[ 2.387797] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10656 04:38:58.161015 <6>[ 2.396919] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10657 04:38:58.171129 <6>[ 2.406387] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10658 04:38:58.181238 <6>[ 2.415506] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10659 04:38:58.191221 <6>[ 2.424801] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10660 04:38:58.201139 <6>[ 2.434960] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10661 04:38:58.210885 <6>[ 2.446553] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10662 04:38:58.217329 <6>[ 2.456310] Trying to probe devices needed for running init ...
10663 04:38:58.236583 <6>[ 2.472850] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10664 04:38:58.265405 <6>[ 2.504378] hub 2-1:1.0: USB hub found
10665 04:38:58.268324 <6>[ 2.508864] hub 2-1:1.0: 3 ports detected
10666 04:38:58.388749 <6>[ 2.624759] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10667 04:38:58.543924 <6>[ 2.782776] hub 1-1:1.0: USB hub found
10668 04:38:58.546639 <6>[ 2.787273] hub 1-1:1.0: 4 ports detected
10669 04:38:58.620750 <6>[ 2.857084] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10670 04:38:58.868794 <6>[ 3.104814] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10671 04:38:59.000544 <6>[ 3.240051] hub 1-1.4:1.0: USB hub found
10672 04:38:59.004247 <6>[ 3.244667] hub 1-1.4:1.0: 2 ports detected
10673 04:38:59.300624 <6>[ 3.536755] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10674 04:38:59.492675 <6>[ 3.728812] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10675 04:39:10.490340 <6>[ 14.733789] ALSA device list:
10676 04:39:10.496470 <6>[ 14.737085] No soundcards found.
10677 04:39:10.504491 <6>[ 14.744992] Freeing unused kernel memory: 8384K
10678 04:39:10.507555 <6>[ 14.750084] Run /init as init process
10679 04:39:10.519052 Loading, please wait...
10680 04:39:10.539086 Starting version 247.3-7+deb11u2
10681 04:39:10.771565 <6>[ 15.008778] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10682 04:39:10.784779 <6>[ 15.025527] remoteproc remoteproc0: scp is available
10683 04:39:10.791751 <6>[ 15.032006] remoteproc remoteproc0: powering up scp
10684 04:39:10.801561 <6>[ 15.037205] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10685 04:39:10.804978 <6>[ 15.045666] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10686 04:39:10.814632 <6>[ 15.047395] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10687 04:39:10.826446 <3>[ 15.063984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 04:39:10.833429 <6>[ 15.070237] usbcore: registered new interface driver r8152
10689 04:39:10.839591 <6>[ 15.073167] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10690 04:39:10.846330 <4>[ 15.078948] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10691 04:39:10.856469 <3>[ 15.080609] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 04:39:10.862736 <3>[ 15.080626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 04:39:10.872833 <3>[ 15.080741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 04:39:10.879691 <3>[ 15.080746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 04:39:10.886256 <3>[ 15.080749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 04:39:10.896974 <3>[ 15.080759] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 04:39:10.903018 <3>[ 15.080763] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 04:39:10.913366 <3>[ 15.080812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 04:39:10.919895 <3>[ 15.080853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 04:39:10.929791 <3>[ 15.080857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 04:39:10.936047 <3>[ 15.080861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 04:39:10.945887 <3>[ 15.080878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 04:39:10.952847 <3>[ 15.080881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 04:39:10.962626 <3>[ 15.080884] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 04:39:10.969096 <3>[ 15.080888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 04:39:10.975503 <3>[ 15.080892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 04:39:10.985970 <3>[ 15.080908] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 04:39:10.995673 <6>[ 15.088217] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10709 04:39:11.001943 <4>[ 15.093450] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10710 04:39:11.005749 <6>[ 15.093456] mc: Linux media interface: v0.10
10711 04:39:11.015255 <6>[ 15.102128] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10712 04:39:11.021918 <4>[ 15.122606] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10713 04:39:11.028617 <4>[ 15.122606] Fallback method does not support PEC.
10714 04:39:11.035210 <6>[ 15.177609] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10715 04:39:11.045375 <6>[ 15.177653] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10716 04:39:11.051663 <6>[ 15.177663] remoteproc remoteproc0: remote processor scp is now up
10717 04:39:11.058169 <6>[ 15.198698] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10718 04:39:11.068333 <6>[ 15.216786] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10719 04:39:11.075280 <6>[ 15.217601] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10720 04:39:11.085492 <6>[ 15.223327] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10721 04:39:11.095801 <6>[ 15.232045] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10722 04:39:11.102224 <6>[ 15.252017] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10723 04:39:11.105909 <6>[ 15.252091] usbcore: registered new interface driver cdc_ether
10724 04:39:11.112015 <6>[ 15.260770] usbcore: registered new interface driver r8153_ecm
10725 04:39:11.118606 <6>[ 15.261602] videodev: Linux video capture interface: v2.00
10726 04:39:11.125481 <6>[ 15.273916] pci_bus 0000:00: root bus resource [bus 00-ff]
10727 04:39:11.132005 <6>[ 15.273925] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10728 04:39:11.141943 <6>[ 15.273940] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10729 04:39:11.148839 <6>[ 15.273999] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10730 04:39:11.155294 <6>[ 15.274015] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10731 04:39:11.158284 <6>[ 15.274726] Bluetooth: Core ver 2.22
10732 04:39:11.165304 <6>[ 15.274805] NET: Registered PF_BLUETOOTH protocol family
10733 04:39:11.171706 <6>[ 15.274808] Bluetooth: HCI device and connection manager initialized
10734 04:39:11.175123 <6>[ 15.274849] Bluetooth: HCI socket layer initialized
10735 04:39:11.181753 <6>[ 15.274863] Bluetooth: L2CAP socket layer initialized
10736 04:39:11.188001 <6>[ 15.274880] Bluetooth: SCO socket layer initialized
10737 04:39:11.194750 <4>[ 15.284223] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10738 04:39:11.204801 <6>[ 15.284680] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10739 04:39:11.208031 <6>[ 15.289640] pci 0000:00:00.0: supports D1 D2
10740 04:39:11.217877 <4>[ 15.296081] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10741 04:39:11.224906 <6>[ 15.303161] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10742 04:39:11.230941 <6>[ 15.304313] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10743 04:39:11.237455 <6>[ 15.314109] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10744 04:39:11.247655 <3>[ 15.320096] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10745 04:39:11.254094 <6>[ 15.322666] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10746 04:39:11.260759 <6>[ 15.323295] usbcore: registered new interface driver btusb
10747 04:39:11.270720 <4>[ 15.323807] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10748 04:39:11.277304 <3>[ 15.323815] Bluetooth: hci0: Failed to load firmware file (-2)
10749 04:39:11.280672 <3>[ 15.323817] Bluetooth: hci0: Failed to set up firmware (-2)
10750 04:39:11.293962 <4>[ 15.323820] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10751 04:39:11.303475 <6>[ 15.332708] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10752 04:39:11.313412 <6>[ 15.339871] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10753 04:39:11.320132 <6>[ 15.340390] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10754 04:39:11.326960 <3>[ 15.343455] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10755 04:39:11.333293 <6>[ 15.346823] usbcore: registered new interface driver uvcvideo
10756 04:39:11.339846 <6>[ 15.352800] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10757 04:39:11.346850 <6>[ 15.360724] r8152 2-1.3:1.0 eth0: v1.12.13
10758 04:39:11.353429 <6>[ 15.364623] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10759 04:39:11.359966 <6>[ 15.376750] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10760 04:39:11.363019 <6>[ 15.377579] pci 0000:01:00.0: supports D1 D2
10761 04:39:11.369701 <6>[ 15.609236] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10762 04:39:11.391814 <6>[ 15.628933] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10763 04:39:11.397983 <6>[ 15.635849] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10764 04:39:11.404521 <6>[ 15.643930] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10765 04:39:11.414703 <6>[ 15.651935] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10766 04:39:11.421112 <6>[ 15.659936] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10767 04:39:11.431155 <6>[ 15.667938] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10768 04:39:11.434538 <6>[ 15.675938] pci 0000:00:00.0: PCI bridge to [bus 01]
10769 04:39:11.444404 <6>[ 15.681154] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10770 04:39:11.450739 <6>[ 15.689296] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10771 04:39:11.457183 <6>[ 15.696180] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10772 04:39:11.464065 <6>[ 15.702980] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10773 04:39:11.482121 <5>[ 15.719557] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10774 04:39:11.504585 <5>[ 15.741906] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10775 04:39:11.511676 <4>[ 15.748831] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10776 04:39:11.518124 <6>[ 15.757726] cfg80211: failed to load regulatory.db
10777 04:39:11.576583 <6>[ 15.814098] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10778 04:39:11.583124 <6>[ 15.821745] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10779 04:39:11.607807 <6>[ 15.848561] mt7921e 0000:01:00.0: ASIC revision: 79610010
10780 04:39:11.714552 <4>[ 15.948714] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 04:39:11.737523 Begin: Loading essential drivers ... done.
10782 04:39:11.740545 Begin: Running /scripts/init-premount ... done.
10783 04:39:11.747306 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10784 04:39:11.757064 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10785 04:39:11.759944 Device /sys/class/net/enx0024323078ff found
10786 04:39:11.760102 done.
10787 04:39:11.834826 <4>[ 16.069173] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 04:39:11.841722 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10789 04:39:11.958048 <4>[ 16.192413] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 04:39:12.078231 <4>[ 16.312310] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 04:39:12.198185 <4>[ 16.432404] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 04:39:12.318204 <4>[ 16.552271] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 04:39:12.438001 <4>[ 16.672374] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 04:39:12.557713 <4>[ 16.792280] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 04:39:12.678056 <4>[ 16.912388] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 04:39:12.773438 <6>[ 17.014174] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10797 04:39:12.800789 <4>[ 17.035407] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 04:39:12.910512 IP-Config: no response after 2 secs - giving up
10799 04:39:12.913922 <3>[ 17.154578] mt7921e 0000:01:00.0: hardware init failed
10800 04:39:12.914108
10801 04:39:12.966835 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10802 04:39:13.080570 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10803 04:39:13.087288 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10804 04:39:13.093521 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10805 04:39:13.100259 host : mt8192-asurada-spherion-r0-cbg-8
10806 04:39:13.106787 domain : lava-rack
10807 04:39:13.113493 rootserver: 192.168.201.1 rootpath:
10808 04:39:13.113708 filename :
10809 04:39:13.162259 done.
10810 04:39:13.169637 Begin: Running /scripts/nfs-bottom ... done.
10811 04:39:13.187449 Begin: Running /scripts/init-bottom ... done.
10812 04:39:14.396683 <6>[ 18.637977] NET: Registered PF_INET6 protocol family
10813 04:39:14.404033 <6>[ 18.645245] Segment Routing with IPv6
10814 04:39:14.407519 <6>[ 18.649281] In-situ OAM (IOAM) with IPv6
10815 04:39:14.533156 <30>[ 18.754345] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10816 04:39:14.536447 <30>[ 18.778723] systemd[1]: Detected architecture arm64.
10817 04:39:14.558128
10818 04:39:14.561618 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10819 04:39:14.561747
10820 04:39:14.577870 <30>[ 18.819053] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10821 04:39:15.439971 <30>[ 19.677687] systemd[1]: Queued start job for default target Graphical Interface.
10822 04:39:15.473858 <30>[ 19.715200] systemd[1]: Created slice system-getty.slice.
10823 04:39:15.480703 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10824 04:39:15.496949 <30>[ 19.738256] systemd[1]: Created slice system-modprobe.slice.
10825 04:39:15.503747 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10826 04:39:15.521330 <30>[ 19.762061] systemd[1]: Created slice system-serial\x2dgetty.slice.
10827 04:39:15.530550 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10828 04:39:15.544431 <30>[ 19.785835] systemd[1]: Created slice User and Session Slice.
10829 04:39:15.551515 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10830 04:39:15.571705 <30>[ 19.809631] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10831 04:39:15.581671 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10832 04:39:15.600011 <30>[ 19.837544] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10833 04:39:15.606261 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10834 04:39:15.630021 <30>[ 19.864962] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10835 04:39:15.637223 <30>[ 19.877112] systemd[1]: Reached target Local Encrypted Volumes.
10836 04:39:15.643352 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10837 04:39:15.660017 <30>[ 19.901365] systemd[1]: Reached target Paths.
10838 04:39:15.663549 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10839 04:39:15.679594 <30>[ 19.920773] systemd[1]: Reached target Remote File Systems.
10840 04:39:15.686064 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10841 04:39:15.703785 <30>[ 19.945147] systemd[1]: Reached target Slices.
10842 04:39:15.710407 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10843 04:39:15.723616 <30>[ 19.964822] systemd[1]: Reached target Swap.
10844 04:39:15.726807 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10845 04:39:15.747191 <30>[ 19.985308] systemd[1]: Listening on initctl Compatibility Named Pipe.
10846 04:39:15.753852 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10847 04:39:15.760560 <30>[ 20.001516] systemd[1]: Listening on Journal Audit Socket.
10848 04:39:15.767214 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10849 04:39:15.784989 <30>[ 20.026074] systemd[1]: Listening on Journal Socket (/dev/log).
10850 04:39:15.791528 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10851 04:39:15.808252 <30>[ 20.049366] systemd[1]: Listening on Journal Socket.
10852 04:39:15.814578 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10853 04:39:15.832300 <30>[ 20.070262] systemd[1]: Listening on Network Service Netlink Socket.
10854 04:39:15.838498 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10855 04:39:15.854550 <30>[ 20.095880] systemd[1]: Listening on udev Control Socket.
10856 04:39:15.860937 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10857 04:39:15.876069 <30>[ 20.117290] systemd[1]: Listening on udev Kernel Socket.
10858 04:39:15.882502 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10859 04:39:15.931893 <30>[ 20.173276] systemd[1]: Mounting Huge Pages File System...
10860 04:39:15.938404 Mounting [0;1;39mHuge Pages File System[0m...
10861 04:39:15.953805 <30>[ 20.195071] systemd[1]: Mounting POSIX Message Queue File System...
10862 04:39:15.960954 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10863 04:39:15.978430 <30>[ 20.220088] systemd[1]: Mounting Kernel Debug File System...
10864 04:39:15.985222 Mounting [0;1;39mKernel Debug File System[0m...
10865 04:39:16.003339 <30>[ 20.241241] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10866 04:39:16.017409 <30>[ 20.255842] systemd[1]: Starting Create list of static device nodes for the current kernel...
10867 04:39:16.024526 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10868 04:39:16.045024 <30>[ 20.286446] systemd[1]: Starting Load Kernel Module configfs...
10869 04:39:16.051863 Starting [0;1;39mLoad Kernel Module configfs[0m...
10870 04:39:16.072307 <30>[ 20.313592] systemd[1]: Starting Load Kernel Module drm...
10871 04:39:16.078923 Starting [0;1;39mLoad Kernel Module drm[0m...
10872 04:39:16.096283 <30>[ 20.337508] systemd[1]: Starting Load Kernel Module fuse...
10873 04:39:16.102772 Starting [0;1;39mLoad Kernel Module fuse[0m...
10874 04:39:16.139981 <30>[ 20.377916] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10875 04:39:16.146793 <6>[ 20.388221] fuse: init (API version 7.37)
10876 04:39:16.196869 <30>[ 20.437697] systemd[1]: Starting Journal Service...
10877 04:39:16.203189 Starting [0;1;39mJournal Service[0m...
10878 04:39:16.226655 <30>[ 20.468231] systemd[1]: Starting Load Kernel Modules...
10879 04:39:16.233722 Starting [0;1;39mLoad Kernel Modules[0m...
10880 04:39:16.253486 <30>[ 20.491572] systemd[1]: Starting Remount Root and Kernel File Systems...
10881 04:39:16.260025 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10882 04:39:16.279544 <30>[ 20.520530] systemd[1]: Starting Coldplug All udev Devices...
10883 04:39:16.286150 Starting [0;1;39mColdplug All udev Devices[0m...
10884 04:39:16.303495 <30>[ 20.544917] systemd[1]: Mounted Huge Pages File System.
10885 04:39:16.309877 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10886 04:39:16.324878 <30>[ 20.566389] systemd[1]: Mounted POSIX Message Queue File System.
10887 04:39:16.331313 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10888 04:39:16.348249 <30>[ 20.589548] systemd[1]: Mounted Kernel Debug File System.
10889 04:39:16.355104 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10890 04:39:16.365042 <3>[ 20.603292] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 04:39:16.376262 <30>[ 20.614548] systemd[1]: Finished Create list of static device nodes for the current kernel.
10892 04:39:16.386800 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10893 04:39:16.396880 <3>[ 20.633910] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 04:39:16.403240 <30>[ 20.643662] systemd[1]: modprobe@configfs.service: Succeeded.
10895 04:39:16.409895 <30>[ 20.650548] systemd[1]: Finished Load Kernel Module configfs.
10896 04:39:16.416430 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10897 04:39:16.432695 <30>[ 20.673861] systemd[1]: modprobe@drm.service: Succeeded.
10898 04:39:16.442803 <3>[ 20.677466] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 04:39:16.446106 <30>[ 20.680354] systemd[1]: Finished Load Kernel Module drm.
10900 04:39:16.452564 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10901 04:39:16.470782 <3>[ 20.708794] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 04:39:16.477116 <30>[ 20.709536] systemd[1]: modprobe@fuse.service: Succeeded.
10903 04:39:16.484169 <30>[ 20.723878] systemd[1]: Finished Load Kernel Module fuse.
10904 04:39:16.487464 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10905 04:39:16.499923 <3>[ 20.737949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 04:39:16.508638 <30>[ 20.750167] systemd[1]: Finished Load Kernel Modules.
10907 04:39:16.515123 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10908 04:39:16.529243 <3>[ 20.767253] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 04:39:16.540111 <30>[ 20.778285] systemd[1]: Finished Remount Root and Kernel File Systems.
10910 04:39:16.546977 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10911 04:39:16.559057 <3>[ 20.797186] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 04:39:16.588514 <3>[ 20.826846] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 04:39:16.608097 <30>[ 20.848770] systemd[1]: Mounting FUSE Control File System...
10914 04:39:16.621430 Mounting [0;1;39mFUSE <3>[ 20.856533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 04:39:16.621559 Control File System[0m...
10916 04:39:16.641302 <30>[ 20.879423] systemd[1]: Mounting Kernel Configuration File System...
10917 04:39:16.651393 Mounting [0;1;39mKerne<3>[ 20.888673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 04:39:16.655479 l Configuration File System[0m...
10919 04:39:16.679398 <30>[ 20.917216] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10920 04:39:16.689085 <30>[ 20.926500] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10921 04:39:16.698182 <30>[ 20.939300] systemd[1]: Starting Load/Save Random Seed...
10922 04:39:16.704789 Starting [0;1;39mLoad/Save Random Seed[0m...
10923 04:39:16.724233 <30>[ 20.965682] systemd[1]: Starting Apply Kernel Variables...
10924 04:39:16.730876 Starting [0;1;39mApply Kernel Variables[0m...
10925 04:39:16.747552 <30>[ 20.987830] systemd[1]: Starting Create System Users...
10926 04:39:16.753630 Starting [0;1;39mCreate System Users[0m...
10927 04:39:16.769807 <30>[ 21.010951] systemd[1]: Started Journal Service.
10928 04:39:16.776152 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10929 04:39:16.797692 <4>[ 21.029131] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10930 04:39:16.807720 <3>[ 21.045024] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10931 04:39:16.810685 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10932 04:39:16.829812 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10933 04:39:16.847586 See 'systemctl status systemd-udev-trigger.service' for details.
10934 04:39:16.864291 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10935 04:39:16.881224 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10936 04:39:16.901257 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10937 04:39:16.936036 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10938 04:39:17.001443 <46>[ 21.239599] systemd-journald[297]: Received client request to flush runtime journal.
10939 04:39:19.170288 [[0m[0;31m* [0m] (1 of 3) A start job is running for…reate System Users (3s / 1min 31s)
10940 04:39:19.326305 M
10941 04:39:19.332958 [K[[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10942 04:39:19.374376 [K[[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10943 04:39:19.421299 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10944 04:39:19.520590 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10945 04:39:19.535121 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10946 04:39:19.555319 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10947 04:39:19.623738 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10948 04:39:19.648644 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10949 04:39:19.802678 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10950 04:39:19.877101 Starting [0;1;39mNetwork Service[0m...
10951 04:39:19.971261 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10952 04:39:20.023749 Starting [0;1;39mNetwork Time Synchronization[0m...
10953 04:39:20.046652 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10954 04:39:20.096420 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10955 04:39:20.155654 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10956 04:39:20.178726 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10957 04:39:20.423044 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10958 04:39:20.556884 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10959 04:39:20.574675 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10960 04:39:20.616138 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10961 04:39:20.639862 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10962 04:39:20.672075 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10963 04:39:20.687657 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10964 04:39:20.703914 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10965 04:39:20.720095 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10966 04:39:20.738648 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10967 04:39:20.751282 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10968 04:39:20.767290 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10969 04:39:20.792733 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10970 04:39:20.813987 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10971 04:39:20.834067 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10972 04:39:20.854034 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10973 04:39:20.867298 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10974 04:39:20.888238 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10975 04:39:20.903347 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10976 04:39:20.919719 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10977 04:39:20.973230 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10978 04:39:21.026045 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10979 04:39:21.107148 Starting [0;1;39mUser Login Management[0m...
10980 04:39:21.217009 Starting [0;1;39mNetwork Name Resolution[0m...
10981 04:39:21.335850 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10982 04:39:21.408531 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10983 04:39:21.942971 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10984 04:39:21.962255 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10985 04:39:21.980216 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10986 04:39:22.312991 Starting [0;1;39mPermit User Sessions[0m...
10987 04:39:22.390782 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10988 04:39:22.430689 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10989 04:39:22.466077 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10990 04:39:22.485676 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10991 04:39:22.501862 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10992 04:39:22.517976 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10993 04:39:22.575827 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10994 04:39:22.619775 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10995 04:39:22.718123
10996 04:39:22.718778
10997 04:39:22.721385 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10998 04:39:22.721978
10999 04:39:22.724400 debian-bullseye-arm64 login: root (automatic login)
11000 04:39:22.724989
11001 04:39:22.725569
11002 04:39:23.072130 Linux debian-bullseye-arm64 6.1.42-cip2 #1 SMP PREEMPT Wed Aug 9 04:18:34 UTC 2023 aarch64
11003 04:39:23.072273
11004 04:39:23.078771 The programs included with the Debian GNU/Linux system are free software;
11005 04:39:23.085229 the exact distribution terms for each program are described in the
11006 04:39:23.088721 individual files in /usr/share/doc/*/copyright.
11007 04:39:23.088834
11008 04:39:23.095228 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11009 04:39:23.098362 permitted by applicable law.
11010 04:39:23.185117 Matched prompt #10: / #
11012 04:39:23.185530 Setting prompt string to ['/ #']
11013 04:39:23.185661 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11015 04:39:23.185985 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11016 04:39:23.186107 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11017 04:39:23.186207 Setting prompt string to ['/ #']
11018 04:39:23.186297 Forcing a shell prompt, looking for ['/ #']
11020 04:39:23.236566 / #
11021 04:39:23.236768 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11022 04:39:23.236871 Waiting using forced prompt support (timeout 00:02:30)
11023 04:39:23.242320
11024 04:39:23.242707 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11025 04:39:23.242852 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11027 04:39:23.343383 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11241313/extract-nfsrootfs-izw72tpv'
11028 04:39:23.348642 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11241313/extract-nfsrootfs-izw72tpv'
11030 04:39:23.449384 / # export NFS_SERVER_IP='192.168.201.1'
11031 04:39:23.454933 export NFS_SERVER_IP='192.168.201.1'
11032 04:39:23.455313 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11033 04:39:23.455476 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11034 04:39:23.455591 end: 2 depthcharge-action (duration 00:01:46) [common]
11035 04:39:23.455697 start: 3 lava-test-retry (timeout 00:01:00) [common]
11036 04:39:23.455787 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11037 04:39:23.455869 Using namespace: common
11039 04:39:23.556234 / # #
11040 04:39:23.556774 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11041 04:39:23.562472 #
11042 04:39:23.563269 Using /lava-11241313
11044 04:39:23.664341 / # export SHELL=/bin/sh
11045 04:39:23.670187 export SHELL=/bin/sh
11047 04:39:23.770846 / # . /lava-11241313/environment
11048 04:39:23.776414 . /lava-11241313/environment
11050 04:39:23.883102 / # /lava-11241313/bin/lava-test-runner /lava-11241313/0
11051 04:39:23.883298 Test shell timeout: 10s (minimum of the action and connection timeout)
11052 04:39:23.888358 /lava-11241313/bin/lava-test-runner /lava-11241313/0
11053 04:39:24.731732 + export TESTRUN_ID=0_dmesg
11054 04:39:24.735509 + cd /lava-11241313/0/tests/0_dmesg
11055 04:39:24.738204 + cat uuid
11056 04:39:24.752804 + UUID=11241313_<8>[ 28.991576] <LAVA_SIGNAL_STARTRUN 0_dmesg 11241313_1.6.2.3.1>
11057 04:39:24.752971 1.6.2.3.1
11058 04:39:24.753044 + set +x
11059 04:39:24.753289 Received signal: <STARTRUN> 0_dmesg 11241313_1.6.2.3.1
11060 04:39:24.753365 Starting test lava.0_dmesg (11241313_1.6.2.3.1)
11061 04:39:24.753448 Skipping test definition patterns.
11062 04:39:24.759149 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11063 04:39:24.866618 <8>[ 29.105678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11064 04:39:24.866969 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11066 04:39:24.957096 <8>[ 29.195950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11067 04:39:24.957770 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11069 04:39:25.045179 <8>[ 29.284084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11070 04:39:25.045511 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11072 04:39:25.051745 + <8>[ 29.293657] <LAVA_SIGNAL_ENDRUN 0_dmesg 11241313_1.6.2.3.1>
11073 04:39:25.051855 set +x
11074 04:39:25.052103 Received signal: <ENDRUN> 0_dmesg 11241313_1.6.2.3.1
11075 04:39:25.052198 Ending use of test pattern.
11076 04:39:25.052261 Ending test lava.0_dmesg (11241313_1.6.2.3.1), duration 0.30
11078 04:39:25.059684 <LAVA_TEST_RUNNER EXIT>
11079 04:39:25.060010 ok: lava_test_shell seems to have completed
11080 04:39:25.060235 alert: pass
crit: pass
emerg: pass
11081 04:39:25.060408 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11082 04:39:25.060574 end: 3 lava-test-retry (duration 00:00:02) [common]
11083 04:39:25.060738 start: 4 lava-test-retry (timeout 00:01:00) [common]
11084 04:39:25.060908 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11085 04:39:25.061044 Using namespace: common
11087 04:39:25.161586 / # #
11088 04:39:25.161798 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11089 04:39:25.161960 Using /lava-11241313
11091 04:39:25.262364 export SHELL=/bin/sh
11092 04:39:25.263072 #
11094 04:39:25.364329 / # export SHELL=/bin/sh. /lava-11241313/environment
11095 04:39:25.364568
11097 04:39:25.465099 / # . /lava-11241313/environment/lava-11241313/bin/lava-test-runner /lava-11241313/1
11098 04:39:25.465274 Test shell timeout: 10s (minimum of the action and connection timeout)
11099 04:39:25.465423
11100 04:39:25.470373 / # /lava-11241313/bin/lava-test-runner /lava-11241313/1
11101 04:39:25.616102 + export TESTRUN_ID=1_bootrr
11102 04:39:25.619947 + cd /lava-11241313/1/tests/1_bootrr
11103 04:39:25.622688 + cat uuid
11104 04:39:25.637500 + UUID=11241313_1.<8>[ 29.876706] <LAVA_SIGNAL_STARTRUN 1_bootrr 11241313_1.6.2.3.5>
11105 04:39:25.637807 6.2.3.5
11106 04:39:25.638018 + set +x
11107 04:39:25.638433 Received signal: <STARTRUN> 1_bootrr 11241313_1.6.2.3.5
11108 04:39:25.638644 Starting test lava.1_bootrr (11241313_1.6.2.3.5)
11109 04:39:25.638883 Skipping test definition patterns.
11110 04:39:25.650999 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11241313/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11111 04:39:25.654066 + cd /opt/bootrr/libexec/bootrr
11112 04:39:25.654256 + sh helpers/bootrr-auto
11113 04:39:25.731959 /lava-11241313/1/../bin/lava-test-case
11114 04:39:25.769354 <8>[ 30.008564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11115 04:39:25.769859 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11117 04:39:25.824802 /lava-11241313/1/../bin/lava-test-case
11118 04:39:25.857451 <8>[ 30.096551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11119 04:39:25.857972 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11121 04:39:25.887411 /lava-11241313/1/../bin/lava-test-case
11122 04:39:25.921573 <8>[ 30.160383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11123 04:39:25.922149 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11125 04:39:25.995313 /lava-11241313/1/../bin/lava-test-case
11126 04:39:26.025720 <8>[ 30.264706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11127 04:39:26.026045 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11129 04:39:26.065681 /lava-11241313/1/../bin/lava-test-case
11130 04:39:26.099181 <8>[ 30.338637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11131 04:39:26.099538 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11133 04:39:26.143887 /lava-11241313/1/../bin/lava-test-case
11134 04:39:26.181573 <8>[ 30.420330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11135 04:39:26.182753 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11137 04:39:26.224165 /lava-11241313/1/../bin/lava-test-case
11138 04:39:26.260534 <8>[ 30.499611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11139 04:39:26.261051 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11141 04:39:26.302734 /lava-11241313/1/../bin/lava-test-case
11142 04:39:26.334646 <8>[ 30.573889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11143 04:39:26.334967 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11145 04:39:26.365420 /lava-11241313/1/../bin/lava-test-case
11146 04:39:26.396346 <8>[ 30.635117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11147 04:39:26.397149 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11149 04:39:26.441259 /lava-11241313/1/../bin/lava-test-case
11150 04:39:26.477193 <8>[ 30.716261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11151 04:39:26.478164 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11153 04:39:26.504524 /lava-11241313/1/../bin/lava-test-case
11154 04:39:26.540662 <8>[ 30.779274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11155 04:39:26.541426 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11157 04:39:26.585898 /lava-11241313/1/../bin/lava-test-case
11158 04:39:26.625117 <8>[ 30.864154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11159 04:39:26.625917 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11161 04:39:26.670293 /lava-11241313/1/../bin/lava-test-case
11162 04:39:26.706111 <8>[ 30.945214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11163 04:39:26.706911 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11165 04:39:26.753641 /lava-11241313/1/../bin/lava-test-case
11166 04:39:26.786409 <8>[ 31.025631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11167 04:39:26.786927 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11169 04:39:26.827538 /lava-11241313/1/../bin/lava-test-case
11170 04:39:26.863972 <8>[ 31.102998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11171 04:39:26.865217 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11173 04:39:26.892243 /lava-11241313/1/../bin/lava-test-case
11174 04:39:26.927261 <8>[ 31.166450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11175 04:39:26.928108 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11177 04:39:26.974253 /lava-11241313/1/../bin/lava-test-case
11178 04:39:27.013587 <8>[ 31.252617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11179 04:39:27.014378 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11181 04:39:27.041356 /lava-11241313/1/../bin/lava-test-case
11182 04:39:27.077843 <8>[ 31.316781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11183 04:39:27.078956 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11185 04:39:27.124421 /lava-11241313/1/../bin/lava-test-case
11186 04:39:27.154190 <8>[ 31.393658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11187 04:39:27.154531 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11189 04:39:27.176720 /lava-11241313/1/../bin/lava-test-case
11190 04:39:27.207628 <8>[ 31.446423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11191 04:39:27.207952 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11193 04:39:27.244715 /lava-11241313/1/../bin/lava-test-case
11194 04:39:27.275996 <8>[ 31.515322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11195 04:39:27.276308 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11197 04:39:27.300562 /lava-11241313/1/../bin/lava-test-case
11198 04:39:28.626252 <8>[ 32.865911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11199 04:39:28.626632 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11201 04:39:28.667633 /lava-11241313/1/../bin/lava-test-case
11202 04:39:28.703974 <8>[ 32.943113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11203 04:39:28.704839 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11205 04:39:28.731041 /lava-11241313/1/../bin/lava-test-case
11206 04:39:28.761107 <8>[ 33.000355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11207 04:39:28.761526 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11209 04:39:28.799837 /lava-11241313/1/../bin/lava-test-case
11210 04:39:28.834011 <8>[ 33.072960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11211 04:39:28.834793 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11213 04:39:28.874722 /lava-11241313/1/../bin/lava-test-case
11214 04:39:28.908409 <8>[ 33.147612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11215 04:39:28.909367 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11217 04:39:28.942854 /lava-11241313/1/../bin/lava-test-case
11218 04:39:28.981340 <8>[ 33.220159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11219 04:39:28.982339 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11221 04:39:29.025809 /lava-11241313/1/../bin/lava-test-case
11222 04:39:29.065298 <8>[ 33.304516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11223 04:39:29.066110 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11225 04:39:29.093230 /lava-11241313/1/../bin/lava-test-case
11226 04:39:29.549079 <8>[ 33.367234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11227 04:39:29.550225 /lava-11241313/1/../bin/lava-test-case
11228 04:39:29.551419 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11230 04:39:29.626145 <8>[ 33.865690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11231 04:39:29.626933 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11233 04:39:29.665059 /lava-11241313/1/../bin/lava-test-case
11234 04:39:29.695518 <8>[ 33.935270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11235 04:39:29.695844 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11237 04:39:29.736969 /lava-11241313/1/../bin/lava-test-case
11238 04:39:29.771536 <8>[ 34.011147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11239 04:39:29.771860 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11241 04:39:29.812451 /lava-11241313/1/../bin/lava-test-case
11242 04:39:29.846121 <8>[ 34.085801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11243 04:39:29.846464 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11245 04:39:29.872464 /lava-11241313/1/../bin/lava-test-case
11246 04:39:29.906964 <8>[ 34.146771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11247 04:39:29.907288 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11249 04:39:29.960405 /lava-11241313/1/../bin/lava-test-case
11250 04:39:30.000421 <8>[ 34.239938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11251 04:39:30.001140 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11253 04:39:30.044851 /lava-11241313/1/../bin/lava-test-case
11254 04:39:30.080652 <8>[ 34.320230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11255 04:39:30.081143 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11257 04:39:30.108291 /lava-11241313/1/../bin/lava-test-case
11258 04:39:30.143406 <8>[ 34.382736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11259 04:39:30.144096 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11261 04:39:30.189953 /lava-11241313/1/../bin/lava-test-case
11262 04:39:30.224884 <8>[ 34.464497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11263 04:39:30.225253 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11265 04:39:30.251966 /lava-11241313/1/../bin/lava-test-case
11266 04:39:30.281413 <8>[ 34.520898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11267 04:39:30.281753 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11269 04:39:30.324511 /lava-11241313/1/../bin/lava-test-case
11270 04:39:30.354144 <8>[ 34.593852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11271 04:39:30.354476 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11273 04:39:30.400300 /lava-11241313/1/../bin/lava-test-case
11274 04:39:30.415757 <8>[ 34.655203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11275 04:39:30.416073 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11277 04:39:30.455224 /lava-11241313/1/../bin/lava-test-case
11278 04:39:30.489780 <8>[ 34.729661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11279 04:39:30.490518 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11281 04:39:30.520264 /lava-11241313/1/../bin/lava-test-case
11282 04:39:30.557621 <8>[ 34.797178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11283 04:39:30.558366 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11285 04:39:30.601905 /lava-11241313/1/../bin/lava-test-case
11286 04:39:31.141917 <8>[ 35.381524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11287 04:39:31.142282 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11289 04:39:31.171160 /lava-11241313/1/../bin/lava-test-case
11290 04:39:33.097356 <8>[ 37.079147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11291 04:39:33.097979 /lava-11241313/1/../bin/lava-test-case
11292 04:39:33.098807 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11294 04:39:33.113979 <8>[ 37.353542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11295 04:39:33.114372 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11297 04:39:33.141907 /lava-11241313/1/../bin/lava-test-case
11298 04:39:33.699217 <8>[ 37.939655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11299 04:39:33.699596 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11301 04:39:33.738471 /lava-11241313/1/../bin/lava-test-case
11302 04:39:33.797015 <8>[ 38.037051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11303 04:39:33.797463 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11305 04:39:33.819029 /lava-11241313/1/../bin/lava-test-case
11306 04:39:33.849248 <8>[ 38.089429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11307 04:39:33.849679 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11309 04:39:33.885419 /lava-11241313/1/../bin/lava-test-case
11310 04:39:33.915830 <8>[ 38.155644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11311 04:39:33.916166 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11313 04:39:33.948907 /lava-11241313/1/../bin/lava-test-case
11314 04:39:33.977730 <8>[ 38.218059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11315 04:39:33.978086 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11317 04:39:34.008184 /lava-11241313/1/../bin/lava-test-case
11318 04:39:34.036347 <8>[ 38.276481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11319 04:39:34.036679 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11321 04:39:34.073403 /lava-11241313/1/../bin/lava-test-case
11322 04:39:34.103640 <8>[ 38.343846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11323 04:39:34.103980 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11325 04:39:34.127158 /lava-11241313/1/../bin/lava-test-case
11326 04:39:34.157351 <8>[ 38.397559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11327 04:39:34.157684 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11329 04:39:34.194837 /lava-11241313/1/../bin/lava-test-case
11330 04:39:34.224310 <8>[ 38.464324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11331 04:39:34.224629 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11333 04:39:34.261436 /lava-11241313/1/../bin/lava-test-case
11334 04:39:34.289284 <8>[ 38.529481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11335 04:39:34.289642 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11337 04:39:34.335578 /lava-11241313/1/../bin/lava-test-case
11338 04:39:34.365580 <8>[ 38.605513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11339 04:39:34.365921 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11341 04:39:34.403016 /lava-11241313/1/../bin/lava-test-case
11342 04:39:34.432352 <8>[ 38.672611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11343 04:39:34.432675 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11345 04:39:34.470288 /lava-11241313/1/../bin/lava-test-case
11346 04:39:34.502090 <8>[ 38.742395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11347 04:39:34.502503 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11349 04:39:34.525678 /lava-11241313/1/../bin/lava-test-case
11350 04:39:34.554781 <8>[ 38.795223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11351 04:39:34.555117 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11353 04:39:34.590065 /lava-11241313/1/../bin/lava-test-case
11354 04:39:34.618092 <8>[ 38.858516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11355 04:39:34.618463 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11357 04:39:34.659493 /lava-11241313/1/../bin/lava-test-case
11358 04:39:34.688278 <8>[ 38.928257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11359 04:39:34.688614 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11361 04:39:34.710691 /lava-11241313/1/../bin/lava-test-case
11362 04:39:34.739216 <8>[ 38.979500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11363 04:39:34.739576 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11365 04:39:34.774085 /lava-11241313/1/../bin/lava-test-case
11366 04:39:34.802954 <8>[ 39.042733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11367 04:39:34.804102 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11369 04:39:34.827411 /lava-11241313/1/../bin/lava-test-case
11370 04:39:34.859196 <8>[ 39.099156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11371 04:39:34.859522 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11373 04:39:34.895202 /lava-11241313/1/../bin/lava-test-case
11374 04:39:34.925395 <8>[ 39.165291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11375 04:39:34.925754 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11377 04:39:34.949168 /lava-11241313/1/../bin/lava-test-case
11378 04:39:34.978619 <8>[ 39.218659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11379 04:39:34.978950 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11381 04:39:35.023365 /lava-11241313/1/../bin/lava-test-case
11382 04:39:35.055828 <8>[ 39.295571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11383 04:39:35.056677 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11385 04:39:35.095216 /lava-11241313/1/../bin/lava-test-case
11386 04:39:35.129936 <8>[ 39.369865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11387 04:39:35.130265 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11389 04:39:35.165023 /lava-11241313/1/../bin/lava-test-case
11390 04:39:35.197492 <8>[ 39.437537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11391 04:39:35.197805 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11393 04:39:35.233991 /lava-11241313/1/../bin/lava-test-case
11394 04:39:35.266693 <8>[ 39.506784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11395 04:39:35.267012 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11397 04:39:35.302670 /lava-11241313/1/../bin/lava-test-case
11398 04:39:35.330987 <8>[ 39.571353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11399 04:39:35.331346 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11401 04:39:35.374515 /lava-11241313/1/../bin/lava-test-case
11402 04:39:35.403189 <8>[ 39.643703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11403 04:39:35.403536 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11405 04:39:35.440155 /lava-11241313/1/../bin/lava-test-case
11406 04:39:35.471950 <8>[ 39.712238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11407 04:39:35.472293 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11409 04:39:35.508597 /lava-11241313/1/../bin/lava-test-case
11410 04:39:36.054921 <8>[ 40.295002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11411 04:39:36.055255 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11413 04:39:36.090362 /lava-11241313/1/../bin/lava-test-case
11414 04:39:36.128606 <8>[ 40.368745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11415 04:39:36.128940 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11417 04:39:36.165934 /lava-11241313/1/../bin/lava-test-case
11418 04:39:36.199519 <8>[ 40.440087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11419 04:39:36.199861 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11421 04:39:36.236152 /lava-11241313/1/../bin/lava-test-case
11422 04:39:36.264197 <8>[ 40.504455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11423 04:39:36.264530 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11425 04:39:36.303323 /lava-11241313/1/../bin/lava-test-case
11426 04:39:36.334063 <8>[ 40.574669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11427 04:39:36.334376 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11429 04:39:36.376650 /lava-11241313/1/../bin/lava-test-case
11430 04:39:36.407091 <8>[ 40.647678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11431 04:39:36.407417 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11433 04:39:36.444249 /lava-11241313/1/../bin/lava-test-case
11434 04:39:36.477282 <8>[ 40.717242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11435 04:39:36.477605 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11437 04:39:36.516585 /lava-11241313/1/../bin/lava-test-case
11438 04:39:36.548376 <8>[ 40.788711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11439 04:39:36.548696 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11441 04:39:36.572833 /lava-11241313/1/../bin/lava-test-case
11442 04:39:36.602122 <8>[ 40.842709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11443 04:39:36.602472 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11445 04:39:36.641727 /lava-11241313/1/../bin/lava-test-case
11446 04:39:36.674832 <8>[ 40.915261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11447 04:39:36.675158 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11449 04:39:36.704856 /lava-11241313/1/../bin/lava-test-case
11450 04:39:36.734737 <8>[ 40.975221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11451 04:39:36.735080 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11453 04:39:36.773604 /lava-11241313/1/../bin/lava-test-case
11454 04:39:36.804721 <8>[ 41.045272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11455 04:39:36.805074 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11457 04:39:36.827859 /lava-11241313/1/../bin/lava-test-case
11458 04:39:36.858685 <8>[ 41.098874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11459 04:39:36.859047 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11461 04:39:36.896513 /lava-11241313/1/../bin/lava-test-case
11462 04:39:36.926393 <8>[ 41.167038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11463 04:39:36.926722 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11465 04:39:36.950309 /lava-11241313/1/../bin/lava-test-case
11466 04:39:36.978875 <8>[ 41.219482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11467 04:39:36.979277 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11469 04:39:37.014884 /lava-11241313/1/../bin/lava-test-case
11470 04:39:37.043781 <8>[ 41.284394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11471 04:39:37.044128 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11473 04:39:37.074997 /lava-11241313/1/../bin/lava-test-case
11474 04:39:37.104312 <8>[ 41.344753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11475 04:39:37.104627 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11477 04:39:37.141508 /lava-11241313/1/../bin/lava-test-case
11478 04:39:37.171154 <8>[ 41.411413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11479 04:39:37.171525 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11481 04:39:37.194001 /lava-11241313/1/../bin/lava-test-case
11482 04:39:39.798553 <8>[ 44.039089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11483 04:39:39.798964 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11485 04:39:39.836820 /lava-11241313/1/../bin/lava-test-case
11486 04:39:39.869885 <8>[ 44.110161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11487 04:39:39.870200 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11489 04:39:39.905496 /lava-11241313/1/../bin/lava-test-case
11490 04:39:39.936746 <8>[ 44.177549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11491 04:39:39.937059 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11493 04:39:39.986393 /lava-11241313/1/../bin/lava-test-case
11494 04:39:40.000763 <8>[ 44.241717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11495 04:39:40.001079 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11497 04:39:40.037203 /lava-11241313/1/../bin/lava-test-case
11498 04:39:40.073414 <8>[ 44.314339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11499 04:39:40.073824 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11501 04:39:40.103051 /lava-11241313/1/../bin/lava-test-case
11502 04:39:40.133201 <8>[ 44.374184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11503 04:39:40.133549 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11505 04:39:40.168477 /lava-11241313/1/../bin/lava-test-case
11506 04:39:40.202079 <8>[ 44.442654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11507 04:39:40.202884 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11509 04:39:40.228147 /lava-11241313/1/../bin/lava-test-case
11510 04:39:40.259432 <8>[ 44.497863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11511 04:39:40.260176 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11513 04:39:41.314568 /lava-11241313/1/../bin/lava-test-case
11514 04:39:41.350254 <8>[ 45.591129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11515 04:39:41.350570 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11517 04:39:41.373035 /lava-11241313/1/../bin/lava-test-case
11518 04:39:41.403243 <8>[ 45.644336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11519 04:39:41.403599 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11521 04:39:42.001871 <6>[ 46.249299] vpu: disabling
11522 04:39:42.005188 <6>[ 46.252408] vproc2: disabling
11523 04:39:42.008221 <6>[ 46.255764] vproc1: disabling
11524 04:39:42.011539 <6>[ 46.259071] vaud18: disabling
11525 04:39:42.018154 <6>[ 46.262579] vsram_others: disabling
11526 04:39:42.021593 <6>[ 46.266609] va09: disabling
11527 04:39:42.024798 <6>[ 46.269775] vsram_md: disabling
11528 04:39:42.027984 <6>[ 46.273337] Vgpu: disabling
11529 04:39:42.453280 /lava-11241313/1/../bin/lava-test-case
11530 04:39:42.486267 <8>[ 46.727343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11531 04:39:42.486665 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11533 04:39:42.508019 /lava-11241313/1/../bin/lava-test-case
11534 04:39:42.540360 <8>[ 46.781715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11535 04:39:42.540716 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11537 04:39:43.594031 /lava-11241313/1/../bin/lava-test-case
11538 04:39:43.628712 <8>[ 47.869850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11539 04:39:43.629035 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11541 04:39:43.653382 /lava-11241313/1/../bin/lava-test-case
11542 04:39:43.684696 <8>[ 47.925714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11543 04:39:43.685019 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11545 04:39:44.741303 /lava-11241313/1/../bin/lava-test-case
11546 04:39:45.499581 <8>[ 49.738089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11547 04:39:45.500896 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11549 04:39:45.525184 /lava-11241313/1/../bin/lava-test-case
11550 04:39:45.558027 <8>[ 49.799263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11551 04:39:45.558386 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11553 04:39:46.616485 /lava-11241313/1/../bin/lava-test-case
11554 04:39:46.651710 <8>[ 50.893426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11555 04:39:46.652309 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11557 04:39:46.677191 /lava-11241313/1/../bin/lava-test-case
11558 04:39:46.711975 <8>[ 50.953004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11559 04:39:46.712626 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11561 04:39:47.764476 /lava-11241313/1/../bin/lava-test-case
11562 04:39:50.179187 <8>[ 54.421043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11563 04:39:50.179641 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11565 04:39:50.207045 /lava-11241313/1/../bin/lava-test-case
11566 04:39:50.240945 <8>[ 54.482615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11567 04:39:50.241606 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11569 04:39:51.294444 /lava-11241313/1/../bin/lava-test-case
11570 04:39:51.327823 <8>[ 55.569504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11571 04:39:51.328820 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11573 04:39:51.354109 /lava-11241313/1/../bin/lava-test-case
11574 04:39:51.387161 <8>[ 55.629329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11575 04:39:51.387534 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11577 04:39:51.412276 /lava-11241313/1/../bin/lava-test-case
11578 04:39:51.458960 <8>[ 55.701046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11579 04:39:51.459548 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11581 04:39:52.509802 /lava-11241313/1/../bin/lava-test-case
11582 04:39:52.538131 <8>[ 56.780393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11583 04:39:52.538481 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11585 04:39:52.561952 /lava-11241313/1/../bin/lava-test-case
11586 04:39:52.594623 <8>[ 56.836659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11587 04:39:52.594940 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11589 04:39:52.630500 /lava-11241313/1/../bin/lava-test-case
11590 04:39:52.660815 <8>[ 56.902675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11591 04:39:52.661201 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11593 04:39:52.682576 /lava-11241313/1/../bin/lava-test-case
11594 04:39:52.711820 <8>[ 56.954202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11595 04:39:52.712252 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11597 04:39:52.754612 /lava-11241313/1/../bin/lava-test-case
11598 04:39:52.792734 <8>[ 57.034886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11599 04:39:52.793084 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11601 04:39:52.835729 /lava-11241313/1/../bin/lava-test-case
11602 04:39:52.872697 <8>[ 57.114323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11603 04:39:52.873465 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11605 04:39:52.919936 /lava-11241313/1/../bin/lava-test-case
11606 04:39:52.948523 <8>[ 57.190787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11607 04:39:52.948906 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11609 04:39:52.972024 /lava-11241313/1/../bin/lava-test-case
11610 04:39:53.006354 <8>[ 57.248486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11611 04:39:53.006759 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11613 04:39:53.045134 /lava-11241313/1/../bin/lava-test-case
11614 04:39:53.077859 <8>[ 57.320246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11615 04:39:53.078505 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11617 04:39:53.116404 /lava-11241313/1/../bin/lava-test-case
11618 04:39:53.147415 <8>[ 57.389757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11619 04:39:53.148035 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11621 04:39:53.173300 /lava-11241313/1/../bin/lava-test-case
11622 04:39:53.205586 <8>[ 57.447840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11623 04:39:53.206164 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11625 04:39:53.245132 /lava-11241313/1/../bin/lava-test-case
11626 04:39:53.279849 <8>[ 57.521870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11627 04:39:53.280233 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11629 04:39:53.308069 /lava-11241313/1/../bin/lava-test-case
11630 04:39:53.341876 <8>[ 57.583981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11631 04:39:53.342300 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11633 04:39:53.381379 /lava-11241313/1/../bin/lava-test-case
11634 04:39:53.413141 <8>[ 57.655354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11635 04:39:53.413508 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11637 04:39:53.444684 /lava-11241313/1/../bin/lava-test-case
11638 04:39:53.481858 <8>[ 57.724108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11639 04:39:53.482652 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11641 04:39:53.523711 /lava-11241313/1/../bin/lava-test-case
11642 04:39:53.555700 <8>[ 57.797880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11643 04:39:53.556517 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11645 04:39:53.583005 /lava-11241313/1/../bin/lava-test-case
11646 04:39:53.619652 <8>[ 57.861749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11647 04:39:53.620730 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11649 04:39:53.662121 /lava-11241313/1/../bin/lava-test-case
11650 04:39:53.695459 <8>[ 57.937661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11651 04:39:53.695969 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11653 04:39:53.718962 /lava-11241313/1/../bin/lava-test-case
11654 04:39:53.748725 <8>[ 57.991186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11655 04:39:53.749060 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11657 04:39:53.792387 /lava-11241313/1/../bin/lava-test-case
11658 04:39:53.826438 <8>[ 58.068603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11659 04:39:53.827247 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11661 04:39:53.854404 /lava-11241313/1/../bin/lava-test-case
11662 04:39:53.890863 <8>[ 58.132999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11663 04:39:53.891291 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11665 04:39:54.947269 /lava-11241313/1/../bin/lava-test-case
11666 04:39:55.812972 <8>[ 60.055214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11667 04:39:55.813756 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11669 04:39:56.865587 /lava-11241313/1/../bin/lava-test-case
11670 04:39:56.894392 <8>[ 61.137267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11671 04:39:56.894724 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11673 04:39:56.916894 /lava-11241313/1/../bin/lava-test-case
11674 04:39:56.948619 <8>[ 61.191041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11675 04:39:56.948932 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11677 04:39:56.983112 /lava-11241313/1/../bin/lava-test-case
11678 04:39:57.013735 <8>[ 61.256405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11679 04:39:57.014054 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11681 04:39:57.035989 /lava-11241313/1/../bin/lava-test-case
11682 04:39:57.069248 <8>[ 61.312014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11683 04:39:57.069571 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11685 04:39:57.104943 /lava-11241313/1/../bin/lava-test-case
11686 04:39:57.133043 <8>[ 61.375849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11687 04:39:57.133371 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11689 04:39:57.155475 /lava-11241313/1/../bin/lava-test-case
11690 04:39:57.182806 <8>[ 61.425407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11691 04:39:57.183157 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11693 04:39:57.228409 /lava-11241313/1/../bin/lava-test-case
11694 04:39:57.260678 <8>[ 61.503187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11695 04:39:57.261000 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11697 04:39:57.283122 /lava-11241313/1/../bin/lava-test-case
11698 04:39:57.313108 <8>[ 61.556137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11699 04:39:57.313449 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11701 04:39:57.348739 /lava-11241313/1/../bin/lava-test-case
11702 04:39:57.376859 <8>[ 61.619812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11703 04:39:57.377177 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11705 04:39:57.400703 /lava-11241313/1/../bin/lava-test-case
11706 04:39:57.431886 <8>[ 61.674531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11707 04:39:57.432206 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11709 04:39:57.469265 /lava-11241313/1/../bin/lava-test-case
11710 04:39:57.500864 <8>[ 61.743446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11711 04:39:57.501426 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11713 04:39:57.524669 /lava-11241313/1/../bin/lava-test-case
11714 04:39:57.554874 <8>[ 61.797450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11715 04:39:57.555764 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11717 04:39:57.604327 /lava-11241313/1/../bin/lava-test-case
11718 04:39:57.637674 <8>[ 61.880309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11719 04:39:57.638192 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11721 04:39:57.662369 /lava-11241313/1/../bin/lava-test-case
11722 04:39:57.696903 <8>[ 61.939855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11723 04:39:57.697408 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11725 04:39:57.742678 /lava-11241313/1/../bin/lava-test-case
11726 04:39:57.775114 <8>[ 62.017606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11727 04:39:57.775972 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11729 04:39:57.801782 /lava-11241313/1/../bin/lava-test-case
11730 04:39:57.832817 <8>[ 62.075490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11731 04:39:57.833276 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11733 04:39:57.873972 /lava-11241313/1/../bin/lava-test-case
11734 04:39:57.914895 <8>[ 62.157429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11735 04:39:57.915850 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11737 04:39:57.942301 /lava-11241313/1/../bin/lava-test-case
11738 04:39:57.976172 <8>[ 62.219019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11739 04:39:57.976644 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11741 04:39:58.013469 /lava-11241313/1/../bin/lava-test-case
11742 04:39:58.044869 <8>[ 62.287538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11743 04:39:58.045184 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11745 04:39:58.067763 /lava-11241313/1/../bin/lava-test-case
11746 04:39:58.094605 <8>[ 62.337573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11747 04:39:58.094934 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11749 04:39:58.132124 /lava-11241313/1/../bin/lava-test-case
11750 04:39:58.163737 <8>[ 62.406461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11751 04:39:58.164065 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11753 04:39:59.200905 /lava-11241313/1/../bin/lava-test-case
11754 04:39:59.240964 <8>[ 63.483723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11755 04:39:59.241791 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11757 04:40:00.286947 /lava-11241313/1/../bin/lava-test-case
11758 04:40:00.323677 <8>[ 64.566625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11759 04:40:00.324315 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11760 04:40:00.324712 Bad test result: blocked
11761 04:40:00.351174 /lava-11241313/1/../bin/lava-test-case
11762 04:40:00.387888 <8>[ 64.630859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11763 04:40:00.388542 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11765 04:40:01.444464 /lava-11241313/1/../bin/lava-test-case
11766 04:40:01.476147 <8>[ 65.719274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11767 04:40:01.477028 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11769 04:40:01.501963 /lava-11241313/1/../bin/lava-test-case
11770 04:40:01.539301 <8>[ 65.782482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11771 04:40:01.539667 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11773 04:40:01.577124 /lava-11241313/1/../bin/lava-test-case
11774 04:40:01.610444 <8>[ 65.853633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11775 04:40:01.610758 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11777 04:40:01.644518 /lava-11241313/1/../bin/lava-test-case
11778 04:40:01.677840 <8>[ 65.920982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11779 04:40:01.678280 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11781 04:40:01.701821 /lava-11241313/1/../bin/lava-test-case
11782 04:40:01.759758 <8>[ 66.002546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11783 04:40:01.760407 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11785 04:40:01.806168 /lava-11241313/1/../bin/lava-test-case
11786 04:40:01.975419 <8>[ 66.218852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11787 04:40:01.975860 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11789 04:40:02.001372 /lava-11241313/1/../bin/lava-test-case
11790 04:40:02.031837 <8>[ 66.275010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11791 04:40:02.032354 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11793 04:40:03.085133 /lava-11241313/1/../bin/lava-test-case
11794 04:40:03.162162 <8>[ 67.405492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11795 04:40:03.162763 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11797 04:40:03.186952 /lava-11241313/1/../bin/lava-test-case
11798 04:40:03.218343 <8>[ 67.462000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11799 04:40:03.218773 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11801 04:40:04.275748 /lava-11241313/1/../bin/lava-test-case
11802 04:40:04.308864 <8>[ 68.552538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11803 04:40:04.309183 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11805 04:40:04.331339 /lava-11241313/1/../bin/lava-test-case
11806 04:40:04.362293 <8>[ 68.605528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11807 04:40:04.362645 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11809 04:40:05.409401 /lava-11241313/1/../bin/lava-test-case
11810 04:40:05.454731 <8>[ 69.698583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11811 04:40:05.455051 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11813 04:40:05.478185 /lava-11241313/1/../bin/lava-test-case
11814 04:40:05.508880 <8>[ 69.752798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11815 04:40:05.509192 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11817 04:40:06.564529 /lava-11241313/1/../bin/lava-test-case
11818 04:40:06.699395 <8>[ 70.943147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11819 04:40:06.699721 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11821 04:40:06.724148 /lava-11241313/1/../bin/lava-test-case
11822 04:40:06.756893 <8>[ 71.000561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11823 04:40:06.757229 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11825 04:40:06.792435 /lava-11241313/1/../bin/lava-test-case
11826 04:40:06.821602 <8>[ 71.065488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11827 04:40:06.821941 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11829 04:40:06.858171 /lava-11241313/1/../bin/lava-test-case
11830 04:40:06.889266 <8>[ 71.132943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11831 04:40:06.889581 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11833 04:40:06.912400 /lava-11241313/1/../bin/lava-test-case
11834 04:40:06.943634 <8>[ 71.187434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11835 04:40:06.944010 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11837 04:40:06.980829 /lava-11241313/1/../bin/lava-test-case
11838 04:40:07.018576 <8>[ 71.262171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11839 04:40:07.018908 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11841 04:40:07.050949 /lava-11241313/1/../bin/lava-test-case
11842 04:40:07.079844 <8>[ 71.323891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11843 04:40:07.080163 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11845 04:40:07.117070 /lava-11241313/1/../bin/lava-test-case
11846 04:40:07.146936 <8>[ 71.391023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11847 04:40:07.147277 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11849 04:40:07.171266 /lava-11241313/1/../bin/lava-test-case
11850 04:40:07.202848 <8>[ 71.446513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11851 04:40:07.203174 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11853 04:40:07.238877 /lava-11241313/1/../bin/lava-test-case
11854 04:40:07.270249 <8>[ 71.514489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11855 04:40:07.270600 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11857 04:40:07.277171 + set +x
11858 04:40:07.280596 Received signal: <ENDRUN> 1_bootrr 11241313_1.6.2.3.5
11859 04:40:07.280687 Ending use of test pattern.
11860 04:40:07.280754 Ending test lava.1_bootrr (11241313_1.6.2.3.5), duration 41.64
11862 04:40:07.283866 <8>[ 71.528084] <LAVA_SIGNAL_ENDRUN 1_bootrr 11241313_1.6.2.3.5>
11863 04:40:07.288689 <LAVA_TEST_RUNNER EXIT>
11864 04:40:07.288975 ok: lava_test_shell seems to have completed
11865 04:40:07.291128 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11866 04:40:07.291314 end: 4.1 lava-test-shell (duration 00:00:42) [common]
11867 04:40:07.291460 end: 4 lava-test-retry (duration 00:00:42) [common]
11868 04:40:07.291622 start: 5 finalize (timeout 00:07:01) [common]
11869 04:40:07.291750 start: 5.1 power-off (timeout 00:00:30) [common]
11870 04:40:07.292082 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11871 04:40:07.370981 >> Command sent successfully.
11872 04:40:07.374043 Returned 0 in 0 seconds
11873 04:40:07.474653 end: 5.1 power-off (duration 00:00:00) [common]
11875 04:40:07.475929 start: 5.2 read-feedback (timeout 00:07:01) [common]
11876 04:40:07.476839 Listened to connection for namespace 'common' for up to 1s
11877 04:40:08.477459 Finalising connection for namespace 'common'
11878 04:40:08.477664 Disconnecting from shell: Finalise
11879 04:40:08.477770 / #
11880 04:40:08.578078 end: 5.2 read-feedback (duration 00:00:01) [common]
11881 04:40:08.578265 end: 5 finalize (duration 00:00:01) [common]
11882 04:40:08.578397 Cleaning after the job
11883 04:40:08.578525 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/ramdisk
11884 04:40:08.581139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/kernel
11885 04:40:08.594163 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/dtb
11886 04:40:08.594389 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/nfsrootfs
11887 04:40:08.670066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241313/tftp-deploy-_3v05fm7/modules
11888 04:40:08.677242 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11241313
11889 04:40:09.061674 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11241313
11890 04:40:09.061840 Job finished correctly