Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 24
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 134
- Errors: 0
1 04:40:00.427368 lava-dispatcher, installed at version: 2023.05.1
2 04:40:00.427582 start: 0 validate
3 04:40:00.427718 Start time: 2023-08-09 04:40:00.427711+00:00 (UTC)
4 04:40:00.427838 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:40:00.427967 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:40:00.725806 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:40:00.726619 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:40:00.732064 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:40:00.732837 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:40:01.004040 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:40:01.004885 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.42-cip2-1-g47d13938e615%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:40:01.276155 validate duration: 0.85
14 04:40:01.276467 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:40:01.276588 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:40:01.276724 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:40:01.276892 Not decompressing ramdisk as can be used compressed.
18 04:40:01.277006 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 04:40:01.277086 saving as /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/ramdisk/rootfs.cpio.gz
20 04:40:01.277159 total size: 84918747 (80MB)
21 04:40:01.278518 progress 0% (0MB)
22 04:40:01.307622 progress 5% (4MB)
23 04:40:01.330395 progress 10% (8MB)
24 04:40:01.352606 progress 15% (12MB)
25 04:40:01.374687 progress 20% (16MB)
26 04:40:01.396565 progress 25% (20MB)
27 04:40:01.418730 progress 30% (24MB)
28 04:40:01.440583 progress 35% (28MB)
29 04:40:01.463403 progress 40% (32MB)
30 04:40:01.486900 progress 45% (36MB)
31 04:40:01.509045 progress 50% (40MB)
32 04:40:01.531023 progress 55% (44MB)
33 04:40:01.553188 progress 60% (48MB)
34 04:40:01.576730 progress 65% (52MB)
35 04:40:01.599105 progress 70% (56MB)
36 04:40:01.621509 progress 75% (60MB)
37 04:40:01.643770 progress 80% (64MB)
38 04:40:01.666490 progress 85% (68MB)
39 04:40:01.689353 progress 90% (72MB)
40 04:40:01.711664 progress 95% (76MB)
41 04:40:01.733612 progress 100% (80MB)
42 04:40:01.733844 80MB downloaded in 0.46s (177.33MB/s)
43 04:40:01.734008 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:40:01.734253 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:40:01.734340 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:40:01.734426 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:40:01.734572 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:40:01.734647 saving as /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/kernel/Image
50 04:40:01.734709 total size: 49220096 (46MB)
51 04:40:01.734769 No compression specified
52 04:40:01.736005 progress 0% (0MB)
53 04:40:01.749861 progress 5% (2MB)
54 04:40:01.762932 progress 10% (4MB)
55 04:40:01.775907 progress 15% (7MB)
56 04:40:01.788883 progress 20% (9MB)
57 04:40:01.801779 progress 25% (11MB)
58 04:40:01.814658 progress 30% (14MB)
59 04:40:01.827639 progress 35% (16MB)
60 04:40:01.840530 progress 40% (18MB)
61 04:40:01.853410 progress 45% (21MB)
62 04:40:01.866605 progress 50% (23MB)
63 04:40:01.879970 progress 55% (25MB)
64 04:40:01.892981 progress 60% (28MB)
65 04:40:01.905985 progress 65% (30MB)
66 04:40:01.918903 progress 70% (32MB)
67 04:40:01.931810 progress 75% (35MB)
68 04:40:01.944740 progress 80% (37MB)
69 04:40:01.957606 progress 85% (39MB)
70 04:40:01.970392 progress 90% (42MB)
71 04:40:01.983166 progress 95% (44MB)
72 04:40:01.995768 progress 100% (46MB)
73 04:40:01.995928 46MB downloaded in 0.26s (179.70MB/s)
74 04:40:01.996078 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:40:01.996304 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:40:01.996391 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:40:01.996476 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:40:01.996624 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:40:01.996737 saving as /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/dtb/mt8192-asurada-spherion-r0.dtb
81 04:40:01.996799 total size: 47278 (0MB)
82 04:40:01.996857 No compression specified
83 04:40:01.997918 progress 69% (0MB)
84 04:40:01.998189 progress 100% (0MB)
85 04:40:01.998342 0MB downloaded in 0.00s (29.26MB/s)
86 04:40:01.998458 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:40:01.998674 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:40:01.998758 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:40:01.998839 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:40:01.998953 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.42-cip2-1-g47d13938e615/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:40:01.999020 saving as /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/modules/modules.tar
93 04:40:01.999079 total size: 8557308 (8MB)
94 04:40:01.999137 Using unxz to decompress xz
95 04:40:02.003053 progress 0% (0MB)
96 04:40:02.024542 progress 5% (0MB)
97 04:40:02.046759 progress 10% (0MB)
98 04:40:02.072971 progress 15% (1MB)
99 04:40:02.098320 progress 20% (1MB)
100 04:40:02.123991 progress 25% (2MB)
101 04:40:02.150164 progress 30% (2MB)
102 04:40:02.175165 progress 35% (2MB)
103 04:40:02.200103 progress 40% (3MB)
104 04:40:02.224089 progress 45% (3MB)
105 04:40:02.250198 progress 50% (4MB)
106 04:40:02.275411 progress 55% (4MB)
107 04:40:02.299841 progress 60% (4MB)
108 04:40:02.322206 progress 65% (5MB)
109 04:40:02.347161 progress 70% (5MB)
110 04:40:02.371362 progress 75% (6MB)
111 04:40:02.397188 progress 80% (6MB)
112 04:40:02.426491 progress 85% (6MB)
113 04:40:02.454912 progress 90% (7MB)
114 04:40:02.479299 progress 95% (7MB)
115 04:40:02.502576 progress 100% (8MB)
116 04:40:02.507238 8MB downloaded in 0.51s (16.06MB/s)
117 04:40:02.507531 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:40:02.507795 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:40:02.507888 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:40:02.507985 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:40:02.508070 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:40:02.508155 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:40:02.508389 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj
125 04:40:02.508531 makedir: /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin
126 04:40:02.508640 makedir: /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/tests
127 04:40:02.508786 makedir: /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/results
128 04:40:02.508902 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-add-keys
129 04:40:02.509052 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-add-sources
130 04:40:02.509188 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-background-process-start
131 04:40:02.509324 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-background-process-stop
132 04:40:02.509454 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-common-functions
133 04:40:02.509582 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-echo-ipv4
134 04:40:02.509712 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-install-packages
135 04:40:02.509839 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-installed-packages
136 04:40:02.509964 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-os-build
137 04:40:02.510094 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-probe-channel
138 04:40:02.510223 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-probe-ip
139 04:40:02.510351 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-target-ip
140 04:40:02.510479 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-target-mac
141 04:40:02.510608 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-target-storage
142 04:40:02.510790 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-test-case
143 04:40:02.510919 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-test-event
144 04:40:02.511044 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-test-feedback
145 04:40:02.511173 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-test-raise
146 04:40:02.511307 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-test-reference
147 04:40:02.511435 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-test-runner
148 04:40:02.511562 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-test-set
149 04:40:02.511691 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-test-shell
150 04:40:02.511820 Updating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-install-packages (oe)
151 04:40:02.511979 Updating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/bin/lava-installed-packages (oe)
152 04:40:02.512114 Creating /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/environment
153 04:40:02.512226 LAVA metadata
154 04:40:02.512303 - LAVA_JOB_ID=11241319
155 04:40:02.512369 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:40:02.512476 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:40:02.512544 skipped lava-vland-overlay
158 04:40:02.512618 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:40:02.512736 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:40:02.512801 skipped lava-multinode-overlay
161 04:40:02.512876 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:40:02.512961 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:40:02.513034 Loading test definitions
164 04:40:02.513124 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 04:40:02.513198 Using /lava-11241319 at stage 0
166 04:40:02.513295 Fetching tests from https://github.com/kernelci/kernelci-core
167 04:40:02.513376 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/0/tests/0_sleep'
168 04:40:03.586329 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/0/tests/0_sleep
169 04:40:03.587657 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 04:40:03.588084 uuid=11241319_1.5.2.3.1 testdef=None
171 04:40:03.588237 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 04:40:03.588492 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 04:40:03.589115 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 04:40:03.589349 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 04:40:03.590064 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 04:40:03.590298 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 04:40:03.590970 runner path: /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/0/tests/0_sleep test_uuid 11241319_1.5.2.3.1
181 04:40:03.591056 sleep_params='mem freeze'
182 04:40:03.591269 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 04:40:03.591520 Creating lava-test-runner.conf files
185 04:40:03.591584 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11241319/lava-overlay-mxnqcmlj/lava-11241319/0 for stage 0
186 04:40:03.591678 - 0_sleep
187 04:40:03.591786 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 04:40:03.591890 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 04:40:03.715938 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 04:40:03.716094 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 04:40:03.716188 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 04:40:03.716293 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 04:40:03.716387 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 04:40:06.230912 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 04:40:06.231371 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 04:40:06.231539 extracting modules file /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11241319/extract-overlay-ramdisk-wlxogdfh/ramdisk
197 04:40:06.547403 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 04:40:06.547620 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 04:40:06.547752 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11241319/compress-overlay-rmgjmgx2/overlay-1.5.2.4.tar.gz to ramdisk
200 04:40:06.547865 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11241319/compress-overlay-rmgjmgx2/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11241319/extract-overlay-ramdisk-wlxogdfh/ramdisk
201 04:40:06.649138 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 04:40:06.649313 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 04:40:06.649420 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 04:40:06.649513 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 04:40:06.649607 Building ramdisk /var/lib/lava/dispatcher/tmp/11241319/extract-overlay-ramdisk-wlxogdfh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11241319/extract-overlay-ramdisk-wlxogdfh/ramdisk
206 04:40:08.236839 >> 562049 blocks
207 04:40:17.915279 rename /var/lib/lava/dispatcher/tmp/11241319/extract-overlay-ramdisk-wlxogdfh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/ramdisk/ramdisk.cpio.gz
208 04:40:17.915806 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 04:40:17.915975 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
210 04:40:17.916124 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
211 04:40:17.916275 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/kernel/Image'
212 04:40:30.979109 Returned 0 in 13 seconds
213 04:40:31.079766 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/kernel/image.itb
214 04:40:32.577849 output: FIT description: Kernel Image image with one or more FDT blobs
215 04:40:32.578263 output: Created: Wed Aug 9 05:40:32 2023
216 04:40:32.578374 output: Image 0 (kernel-1)
217 04:40:32.578482 output: Description:
218 04:40:32.578584 output: Created: Wed Aug 9 05:40:32 2023
219 04:40:32.578680 output: Type: Kernel Image
220 04:40:32.578777 output: Compression: lzma compressed
221 04:40:32.578845 output: Data Size: 11036366 Bytes = 10777.70 KiB = 10.53 MiB
222 04:40:32.578909 output: Architecture: AArch64
223 04:40:32.578979 output: OS: Linux
224 04:40:32.579070 output: Load Address: 0x00000000
225 04:40:32.579167 output: Entry Point: 0x00000000
226 04:40:32.579262 output: Hash algo: crc32
227 04:40:32.579352 output: Hash value: 9e750869
228 04:40:32.579437 output: Image 1 (fdt-1)
229 04:40:32.579525 output: Description: mt8192-asurada-spherion-r0
230 04:40:32.579610 output: Created: Wed Aug 9 05:40:32 2023
231 04:40:32.579708 output: Type: Flat Device Tree
232 04:40:32.579767 output: Compression: uncompressed
233 04:40:32.579822 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 04:40:32.579876 output: Architecture: AArch64
235 04:40:32.579937 output: Hash algo: crc32
236 04:40:32.579991 output: Hash value: cc4352de
237 04:40:32.580044 output: Image 2 (ramdisk-1)
238 04:40:32.580107 output: Description: unavailable
239 04:40:32.580192 output: Created: Wed Aug 9 05:40:32 2023
240 04:40:32.580283 output: Type: RAMDisk Image
241 04:40:32.580370 output: Compression: Unknown Compression
242 04:40:32.580457 output: Data Size: 98206511 Bytes = 95904.80 KiB = 93.66 MiB
243 04:40:32.580543 output: Architecture: AArch64
244 04:40:32.580627 output: OS: Linux
245 04:40:32.580711 output: Load Address: unavailable
246 04:40:32.580770 output: Entry Point: unavailable
247 04:40:32.580824 output: Hash algo: crc32
248 04:40:32.580877 output: Hash value: 3d83310d
249 04:40:32.580937 output: Default Configuration: 'conf-1'
250 04:40:32.580992 output: Configuration 0 (conf-1)
251 04:40:32.581045 output: Description: mt8192-asurada-spherion-r0
252 04:40:32.581098 output: Kernel: kernel-1
253 04:40:32.581185 output: Init Ramdisk: ramdisk-1
254 04:40:32.581281 output: FDT: fdt-1
255 04:40:32.581372 output: Loadables: kernel-1
256 04:40:32.581456 output:
257 04:40:32.581709 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 04:40:32.581840 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 04:40:32.581996 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
260 04:40:32.582131 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
261 04:40:32.582243 No LXC device requested
262 04:40:32.582362 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 04:40:32.582480 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
264 04:40:32.582596 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 04:40:32.582698 Checking files for TFTP limit of 4294967296 bytes.
266 04:40:32.583387 end: 1 tftp-deploy (duration 00:00:31) [common]
267 04:40:32.583528 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 04:40:32.583663 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 04:40:32.583822 substitutions:
270 04:40:32.583897 - {DTB}: 11241319/tftp-deploy-bswagsfv/dtb/mt8192-asurada-spherion-r0.dtb
271 04:40:32.583972 - {INITRD}: 11241319/tftp-deploy-bswagsfv/ramdisk/ramdisk.cpio.gz
272 04:40:32.584036 - {KERNEL}: 11241319/tftp-deploy-bswagsfv/kernel/Image
273 04:40:32.584095 - {LAVA_MAC}: None
274 04:40:32.584163 - {PRESEED_CONFIG}: None
275 04:40:32.584251 - {PRESEED_LOCAL}: None
276 04:40:32.584343 - {RAMDISK}: 11241319/tftp-deploy-bswagsfv/ramdisk/ramdisk.cpio.gz
277 04:40:32.584440 - {ROOT_PART}: None
278 04:40:32.584532 - {ROOT}: None
279 04:40:32.584620 - {SERVER_IP}: 192.168.201.1
280 04:40:32.584720 - {TEE}: None
281 04:40:32.584787 Parsed boot commands:
282 04:40:32.584844 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 04:40:32.585029 Parsed boot commands: tftpboot 192.168.201.1 11241319/tftp-deploy-bswagsfv/kernel/image.itb 11241319/tftp-deploy-bswagsfv/kernel/cmdline
284 04:40:32.585120 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 04:40:32.585240 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 04:40:32.585372 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 04:40:32.585490 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 04:40:32.585606 Not connected, no need to disconnect.
289 04:40:32.585720 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 04:40:32.585842 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 04:40:32.585948 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
292 04:40:32.589913 Setting prompt string to ['lava-test: # ']
293 04:40:32.590342 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 04:40:32.590494 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 04:40:32.590624 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 04:40:32.590754 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 04:40:32.591102 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
298 04:40:37.728053 >> Command sent successfully.
299 04:40:37.731154 Returned 0 in 5 seconds
300 04:40:37.831590 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 04:40:37.831983 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 04:40:37.832100 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 04:40:37.832232 Setting prompt string to 'Starting depthcharge on Spherion...'
305 04:40:37.832338 Changing prompt to 'Starting depthcharge on Spherion...'
306 04:40:37.832444 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 04:40:37.832798 [Enter `^Ec?' for help]
308 04:40:38.006431
309 04:40:38.006623
310 04:40:38.006741 F0: 102B 0000
311 04:40:38.006839
312 04:40:38.006938 F3: 1001 0000 [0200]
313 04:40:38.007038
314 04:40:38.010102 F3: 1001 0000
315 04:40:38.010214
316 04:40:38.010313 F7: 102D 0000
317 04:40:38.010415
318 04:40:38.010516 F1: 0000 0000
319 04:40:38.010611
320 04:40:38.014724 V0: 0000 0000 [0001]
321 04:40:38.014856
322 04:40:38.014954 00: 0007 8000
323 04:40:38.015055
324 04:40:38.015147 01: 0000 0000
325 04:40:38.018225
326 04:40:38.018339 BP: 0C00 0209 [0000]
327 04:40:38.018440
328 04:40:38.018537 G0: 1182 0000
329 04:40:38.018629
330 04:40:38.021683 EC: 0000 0021 [4000]
331 04:40:38.021794
332 04:40:38.021893 S7: 0000 0000 [0000]
333 04:40:38.021985
334 04:40:38.025471 CC: 0000 0000 [0001]
335 04:40:38.025581
336 04:40:38.025681 T0: 0000 0040 [010F]
337 04:40:38.025774
338 04:40:38.029051 Jump to BL
339 04:40:38.029164
340 04:40:38.053160
341 04:40:38.053343
342 04:40:38.053465
343 04:40:38.060924 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 04:40:38.063855 ARM64: Exception handlers installed.
345 04:40:38.067738 ARM64: Testing exception
346 04:40:38.071367 ARM64: Done test exception
347 04:40:38.078531 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 04:40:38.085742 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 04:40:38.092875 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 04:40:38.103981 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 04:40:38.110652 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 04:40:38.121050 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 04:40:38.131528 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 04:40:38.138384 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 04:40:38.155725 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 04:40:38.159320 WDT: Last reset was cold boot
357 04:40:38.163089 SPI1(PAD0) initialized at 2873684 Hz
358 04:40:38.165979 SPI5(PAD0) initialized at 992727 Hz
359 04:40:38.169215 VBOOT: Loading verstage.
360 04:40:38.176031 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 04:40:38.179297 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 04:40:38.182516 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 04:40:38.185921 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 04:40:38.193972 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 04:40:38.200537 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 04:40:38.211117 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 04:40:38.211256
368 04:40:38.211326
369 04:40:38.221312 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 04:40:38.224711 ARM64: Exception handlers installed.
371 04:40:38.227975 ARM64: Testing exception
372 04:40:38.228079 ARM64: Done test exception
373 04:40:38.234201 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 04:40:38.238164 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 04:40:38.252929 Probing TPM: . done!
376 04:40:38.253085 TPM ready after 0 ms
377 04:40:38.260393 Connected to device vid:did:rid of 1ae0:0028:00
378 04:40:38.267054 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 04:40:38.323758 Initialized TPM device CR50 revision 0
380 04:40:38.335736 tlcl_send_startup: Startup return code is 0
381 04:40:38.335892 TPM: setup succeeded
382 04:40:38.347225 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 04:40:38.356067 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 04:40:38.368462 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 04:40:38.377926 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 04:40:38.381315 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 04:40:38.386729 in-header: 03 07 00 00 08 00 00 00
388 04:40:38.390385 in-data: aa e4 47 04 13 02 00 00
389 04:40:38.393867 Chrome EC: UHEPI supported
390 04:40:38.401462 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 04:40:38.404987 in-header: 03 ad 00 00 08 00 00 00
392 04:40:38.405150 in-data: 00 20 20 08 00 00 00 00
393 04:40:38.409298 Phase 1
394 04:40:38.413078 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 04:40:38.416631 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 04:40:38.423366 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 04:40:38.427376 Recovery requested (1009000e)
398 04:40:38.435249 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 04:40:38.440970 tlcl_extend: response is 0
400 04:40:38.450589 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 04:40:38.455787 tlcl_extend: response is 0
402 04:40:38.462808 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 04:40:38.482346 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 04:40:38.489330 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 04:40:38.489489
406 04:40:38.489596
407 04:40:38.500009 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 04:40:38.503546 ARM64: Exception handlers installed.
409 04:40:38.503679 ARM64: Testing exception
410 04:40:38.506787 ARM64: Done test exception
411 04:40:38.527984 pmic_efuse_setting: Set efuses in 11 msecs
412 04:40:38.531477 pmwrap_interface_init: Select PMIF_VLD_RDY
413 04:40:38.538423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 04:40:38.541912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 04:40:38.545196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 04:40:38.552169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 04:40:38.555895 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 04:40:38.563384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 04:40:38.566676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 04:40:38.570254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 04:40:38.573817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 04:40:38.581380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 04:40:38.585646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 04:40:38.589018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 04:40:38.592416 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 04:40:38.600569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 04:40:38.607732 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 04:40:38.611188 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 04:40:38.618827 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 04:40:38.622460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 04:40:38.629791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 04:40:38.633351 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 04:40:38.641465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 04:40:38.644585 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 04:40:38.652023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 04:40:38.656001 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 04:40:38.663250 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 04:40:38.666899 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 04:40:38.673940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 04:40:38.678049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 04:40:38.681658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 04:40:38.689004 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 04:40:38.692248 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 04:40:38.696054 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 04:40:38.704085 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 04:40:38.707226 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 04:40:38.710665 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 04:40:38.718091 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 04:40:38.722040 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 04:40:38.725323 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 04:40:38.732863 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 04:40:38.736436 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 04:40:38.740149 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 04:40:38.743230 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 04:40:38.750789 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 04:40:38.754220 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 04:40:38.758066 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 04:40:38.761719 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 04:40:38.765752 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 04:40:38.769483 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 04:40:38.773181 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 04:40:38.780489 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 04:40:38.784086 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 04:40:38.791975 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 04:40:38.798990 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 04:40:38.802612 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 04:40:38.813907 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 04:40:38.820803 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 04:40:38.825096 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 04:40:38.828662 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 04:40:38.832064 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 04:40:38.841378 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x14
473 04:40:38.844711 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 04:40:38.852918 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 04:40:38.856623 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 04:40:38.865298 [RTC]rtc_get_frequency_meter,154: input=15, output=789
477 04:40:38.875137 [RTC]rtc_get_frequency_meter,154: input=23, output=978
478 04:40:38.884249 [RTC]rtc_get_frequency_meter,154: input=19, output=883
479 04:40:38.894593 [RTC]rtc_get_frequency_meter,154: input=17, output=837
480 04:40:38.903372 [RTC]rtc_get_frequency_meter,154: input=16, output=813
481 04:40:38.913570 [RTC]rtc_get_frequency_meter,154: input=15, output=789
482 04:40:38.922760 [RTC]rtc_get_frequency_meter,154: input=16, output=813
483 04:40:38.926574 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
484 04:40:38.930253 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
485 04:40:38.933840 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 04:40:38.941525 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 04:40:38.945444 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 04:40:38.949092 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 04:40:38.952650 ADC[4]: Raw value=901697 ID=7
490 04:40:38.952798 ADC[3]: Raw value=213336 ID=1
491 04:40:38.956676 RAM Code: 0x71
492 04:40:38.960201 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 04:40:38.964215 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 04:40:38.975556 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 04:40:38.979371 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 04:40:38.982916 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 04:40:38.986763 in-header: 03 07 00 00 08 00 00 00
498 04:40:38.990256 in-data: aa e4 47 04 13 02 00 00
499 04:40:38.993996 Chrome EC: UHEPI supported
500 04:40:38.997569 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 04:40:39.001835 in-header: 03 ed 00 00 08 00 00 00
502 04:40:39.005764 in-data: 80 20 60 08 00 00 00 00
503 04:40:39.009551 MRC: failed to locate region type 0.
504 04:40:39.016627 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 04:40:39.020184 DRAM-K: Running full calibration
506 04:40:39.024389 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 04:40:39.027445 header.status = 0x0
508 04:40:39.031262 header.version = 0x6 (expected: 0x6)
509 04:40:39.035242 header.size = 0xd00 (expected: 0xd00)
510 04:40:39.035352 header.flags = 0x0
511 04:40:39.041869 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 04:40:39.059829 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
513 04:40:39.066783 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 04:40:39.071102 dram_init: ddr_geometry: 2
515 04:40:39.071217 [EMI] MDL number = 2
516 04:40:39.074475 [EMI] Get MDL freq = 0
517 04:40:39.074568 dram_init: ddr_type: 0
518 04:40:39.077990 is_discrete_lpddr4: 1
519 04:40:39.082003 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 04:40:39.082118
521 04:40:39.082187
522 04:40:39.082248 [Bian_co] ETT version 0.0.0.1
523 04:40:39.089358 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 04:40:39.089480
525 04:40:39.092857 dramc_set_vcore_voltage set vcore to 650000
526 04:40:39.092953 Read voltage for 800, 4
527 04:40:39.096677 Vio18 = 0
528 04:40:39.096788 Vcore = 650000
529 04:40:39.096857 Vdram = 0
530 04:40:39.096919 Vddq = 0
531 04:40:39.100249 Vmddr = 0
532 04:40:39.100337 dram_init: config_dvfs: 1
533 04:40:39.107103 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 04:40:39.110659 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 04:40:39.114235 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
536 04:40:39.120604 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
537 04:40:39.124446 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
538 04:40:39.127693 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
539 04:40:39.130844 MEM_TYPE=3, freq_sel=18
540 04:40:39.130936 sv_algorithm_assistance_LP4_1600
541 04:40:39.137587 ============ PULL DRAM RESETB DOWN ============
542 04:40:39.140921 ========== PULL DRAM RESETB DOWN end =========
543 04:40:39.144081 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 04:40:39.147691 ===================================
545 04:40:39.151408 LPDDR4 DRAM CONFIGURATION
546 04:40:39.154475 ===================================
547 04:40:39.157546 EX_ROW_EN[0] = 0x0
548 04:40:39.157639 EX_ROW_EN[1] = 0x0
549 04:40:39.161458 LP4Y_EN = 0x0
550 04:40:39.161551 WORK_FSP = 0x0
551 04:40:39.164541 WL = 0x2
552 04:40:39.164657 RL = 0x2
553 04:40:39.167992 BL = 0x2
554 04:40:39.168082 RPST = 0x0
555 04:40:39.171167 RD_PRE = 0x0
556 04:40:39.171256 WR_PRE = 0x1
557 04:40:39.174534 WR_PST = 0x0
558 04:40:39.174628 DBI_WR = 0x0
559 04:40:39.178271 DBI_RD = 0x0
560 04:40:39.178363 OTF = 0x1
561 04:40:39.181268 ===================================
562 04:40:39.184498 ===================================
563 04:40:39.187994 ANA top config
564 04:40:39.191399 ===================================
565 04:40:39.191497 DLL_ASYNC_EN = 0
566 04:40:39.194953 ALL_SLAVE_EN = 1
567 04:40:39.197932 NEW_RANK_MODE = 1
568 04:40:39.201321 DLL_IDLE_MODE = 1
569 04:40:39.201415 LP45_APHY_COMB_EN = 1
570 04:40:39.204818 TX_ODT_DIS = 1
571 04:40:39.208013 NEW_8X_MODE = 1
572 04:40:39.211653 ===================================
573 04:40:39.214773 ===================================
574 04:40:39.218091 data_rate = 1600
575 04:40:39.221730 CKR = 1
576 04:40:39.221847 DQ_P2S_RATIO = 8
577 04:40:39.225048 ===================================
578 04:40:39.228138 CA_P2S_RATIO = 8
579 04:40:39.231695 DQ_CA_OPEN = 0
580 04:40:39.234619 DQ_SEMI_OPEN = 0
581 04:40:39.238195 CA_SEMI_OPEN = 0
582 04:40:39.241888 CA_FULL_RATE = 0
583 04:40:39.242006 DQ_CKDIV4_EN = 1
584 04:40:39.245202 CA_CKDIV4_EN = 1
585 04:40:39.248736 CA_PREDIV_EN = 0
586 04:40:39.263865 PH8_DLY = 0
587 04:40:39.264224 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 04:40:39.264372 DQ_AAMCK_DIV = 4
589 04:40:39.264516 CA_AAMCK_DIV = 4
590 04:40:39.264610 CA_ADMCK_DIV = 4
591 04:40:39.265125 DQ_TRACK_CA_EN = 0
592 04:40:39.268310 CA_PICK = 800
593 04:40:39.272273 CA_MCKIO = 800
594 04:40:39.275193 MCKIO_SEMI = 0
595 04:40:39.275312 PLL_FREQ = 3068
596 04:40:39.279448 DQ_UI_PI_RATIO = 32
597 04:40:39.282895 CA_UI_PI_RATIO = 0
598 04:40:39.286374 ===================================
599 04:40:39.290949 ===================================
600 04:40:39.291095 memory_type:LPDDR4
601 04:40:39.294466 GP_NUM : 10
602 04:40:39.294586 SRAM_EN : 1
603 04:40:39.297926 MD32_EN : 0
604 04:40:39.301746 ===================================
605 04:40:39.301899 [ANA_INIT] >>>>>>>>>>>>>>
606 04:40:39.305754 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 04:40:39.309675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 04:40:39.313536 ===================================
609 04:40:39.316734 data_rate = 1600,PCW = 0X7600
610 04:40:39.319933 ===================================
611 04:40:39.323604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 04:40:39.326644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 04:40:39.333671 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 04:40:39.336512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 04:40:39.340472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 04:40:39.343183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 04:40:39.346581 [ANA_INIT] flow start
618 04:40:39.350050 [ANA_INIT] PLL >>>>>>>>
619 04:40:39.350148 [ANA_INIT] PLL <<<<<<<<
620 04:40:39.353322 [ANA_INIT] MIDPI >>>>>>>>
621 04:40:39.357026 [ANA_INIT] MIDPI <<<<<<<<
622 04:40:39.357116 [ANA_INIT] DLL >>>>>>>>
623 04:40:39.359974 [ANA_INIT] flow end
624 04:40:39.363722 ============ LP4 DIFF to SE enter ============
625 04:40:39.367284 ============ LP4 DIFF to SE exit ============
626 04:40:39.370322 [ANA_INIT] <<<<<<<<<<<<<
627 04:40:39.373530 [Flow] Enable top DCM control >>>>>
628 04:40:39.376870 [Flow] Enable top DCM control <<<<<
629 04:40:39.380456 Enable DLL master slave shuffle
630 04:40:39.386831 ==============================================================
631 04:40:39.386956 Gating Mode config
632 04:40:39.393685 ==============================================================
633 04:40:39.393838 Config description:
634 04:40:39.403511 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 04:40:39.410533 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 04:40:39.417052 SELPH_MODE 0: By rank 1: By Phase
637 04:40:39.420386 ==============================================================
638 04:40:39.423685 GAT_TRACK_EN = 1
639 04:40:39.427073 RX_GATING_MODE = 2
640 04:40:39.430713 RX_GATING_TRACK_MODE = 2
641 04:40:39.433960 SELPH_MODE = 1
642 04:40:39.437061 PICG_EARLY_EN = 1
643 04:40:39.440741 VALID_LAT_VALUE = 1
644 04:40:39.444257 ==============================================================
645 04:40:39.447543 Enter into Gating configuration >>>>
646 04:40:39.450660 Exit from Gating configuration <<<<
647 04:40:39.454154 Enter into DVFS_PRE_config >>>>>
648 04:40:39.467382 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 04:40:39.467567 Exit from DVFS_PRE_config <<<<<
650 04:40:39.470878 Enter into PICG configuration >>>>
651 04:40:39.473837 Exit from PICG configuration <<<<
652 04:40:39.477433 [RX_INPUT] configuration >>>>>
653 04:40:39.481399 [RX_INPUT] configuration <<<<<
654 04:40:39.487263 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 04:40:39.490958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 04:40:39.497722 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 04:40:39.504626 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 04:40:39.511748 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 04:40:39.514808 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 04:40:39.521695 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 04:40:39.524636 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 04:40:39.528283 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 04:40:39.531693 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 04:40:39.534757 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 04:40:39.541749 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 04:40:39.545344 ===================================
667 04:40:39.545451 LPDDR4 DRAM CONFIGURATION
668 04:40:39.548570 ===================================
669 04:40:39.551717 EX_ROW_EN[0] = 0x0
670 04:40:39.555156 EX_ROW_EN[1] = 0x0
671 04:40:39.555269 LP4Y_EN = 0x0
672 04:40:39.558322 WORK_FSP = 0x0
673 04:40:39.558405 WL = 0x2
674 04:40:39.561957 RL = 0x2
675 04:40:39.562064 BL = 0x2
676 04:40:39.565302 RPST = 0x0
677 04:40:39.565400 RD_PRE = 0x0
678 04:40:39.568854 WR_PRE = 0x1
679 04:40:39.568947 WR_PST = 0x0
680 04:40:39.571978 DBI_WR = 0x0
681 04:40:39.572076 DBI_RD = 0x0
682 04:40:39.575370 OTF = 0x1
683 04:40:39.578878 ===================================
684 04:40:39.582160 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 04:40:39.585755 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 04:40:39.592116 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 04:40:39.595664 ===================================
688 04:40:39.595804 LPDDR4 DRAM CONFIGURATION
689 04:40:39.598616 ===================================
690 04:40:39.602361 EX_ROW_EN[0] = 0x10
691 04:40:39.602464 EX_ROW_EN[1] = 0x0
692 04:40:39.605489 LP4Y_EN = 0x0
693 04:40:39.605582 WORK_FSP = 0x0
694 04:40:39.609109 WL = 0x2
695 04:40:39.609208 RL = 0x2
696 04:40:39.612930 BL = 0x2
697 04:40:39.613066 RPST = 0x0
698 04:40:39.615596 RD_PRE = 0x0
699 04:40:39.615702 WR_PRE = 0x1
700 04:40:39.619056 WR_PST = 0x0
701 04:40:39.619151 DBI_WR = 0x0
702 04:40:39.622324 DBI_RD = 0x0
703 04:40:39.625918 OTF = 0x1
704 04:40:39.626041 ===================================
705 04:40:39.632591 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 04:40:39.637276 nWR fixed to 40
707 04:40:39.640541 [ModeRegInit_LP4] CH0 RK0
708 04:40:39.640673 [ModeRegInit_LP4] CH0 RK1
709 04:40:39.644389 [ModeRegInit_LP4] CH1 RK0
710 04:40:39.647415 [ModeRegInit_LP4] CH1 RK1
711 04:40:39.647530 match AC timing 13
712 04:40:39.653907 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 04:40:39.657405 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 04:40:39.661014 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 04:40:39.667766 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 04:40:39.671172 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 04:40:39.671300 [EMI DOE] emi_dcm 0
718 04:40:39.677344 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 04:40:39.677446 ==
720 04:40:39.681060 Dram Type= 6, Freq= 0, CH_0, rank 0
721 04:40:39.684597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 04:40:39.684717 ==
723 04:40:39.690936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 04:40:39.694399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 04:40:39.705087 [CA 0] Center 37 (7~68) winsize 62
726 04:40:39.708471 [CA 1] Center 37 (6~68) winsize 63
727 04:40:39.711552 [CA 2] Center 35 (5~66) winsize 62
728 04:40:39.715236 [CA 3] Center 34 (4~65) winsize 62
729 04:40:39.718585 [CA 4] Center 34 (3~65) winsize 63
730 04:40:39.721434 [CA 5] Center 33 (3~64) winsize 62
731 04:40:39.721538
732 04:40:39.725289 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 04:40:39.725406
734 04:40:39.728429 [CATrainingPosCal] consider 1 rank data
735 04:40:39.731780 u2DelayCellTimex100 = 270/100 ps
736 04:40:39.734836 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 04:40:39.738444 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 04:40:39.745051 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
739 04:40:39.748426 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 04:40:39.751730 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
741 04:40:39.755109 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 04:40:39.755242
743 04:40:39.758201 CA PerBit enable=1, Macro0, CA PI delay=33
744 04:40:39.758318
745 04:40:39.761610 [CBTSetCACLKResult] CA Dly = 33
746 04:40:39.761722 CS Dly: 5 (0~36)
747 04:40:39.761819 ==
748 04:40:39.765205 Dram Type= 6, Freq= 0, CH_0, rank 1
749 04:40:39.771702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 04:40:39.771827 ==
751 04:40:39.775402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 04:40:39.781823 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 04:40:39.791515 [CA 0] Center 37 (6~68) winsize 63
754 04:40:39.794771 [CA 1] Center 37 (7~68) winsize 62
755 04:40:39.797915 [CA 2] Center 35 (5~66) winsize 62
756 04:40:39.801621 [CA 3] Center 35 (4~66) winsize 63
757 04:40:39.804414 [CA 4] Center 34 (3~65) winsize 63
758 04:40:39.808040 [CA 5] Center 33 (3~64) winsize 62
759 04:40:39.808163
760 04:40:39.811474 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 04:40:39.811591
762 04:40:39.814508 [CATrainingPosCal] consider 2 rank data
763 04:40:39.818113 u2DelayCellTimex100 = 270/100 ps
764 04:40:39.821596 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 04:40:39.824968 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 04:40:39.831284 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 04:40:39.834794 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 04:40:39.838153 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
769 04:40:39.841341 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 04:40:39.841440
771 04:40:39.844994 CA PerBit enable=1, Macro0, CA PI delay=33
772 04:40:39.845112
773 04:40:39.848606 [CBTSetCACLKResult] CA Dly = 33
774 04:40:39.848720 CS Dly: 5 (0~37)
775 04:40:39.848789
776 04:40:39.851577 ----->DramcWriteLeveling(PI) begin...
777 04:40:39.851688 ==
778 04:40:39.854768 Dram Type= 6, Freq= 0, CH_0, rank 0
779 04:40:39.861806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 04:40:39.861929 ==
781 04:40:39.865175 Write leveling (Byte 0): 30 => 30
782 04:40:39.865276 Write leveling (Byte 1): 31 => 31
783 04:40:39.869159 DramcWriteLeveling(PI) end<-----
784 04:40:39.869286
785 04:40:39.869384 ==
786 04:40:39.873212 Dram Type= 6, Freq= 0, CH_0, rank 0
787 04:40:39.876636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 04:40:39.876764 ==
789 04:40:39.880252 [Gating] SW mode calibration
790 04:40:39.887151 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 04:40:39.894492 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 04:40:39.897433 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 04:40:39.901118 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 04:40:39.904208 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
795 04:40:39.911463 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 04:40:39.914816 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 04:40:39.917818 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 04:40:39.924829 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 04:40:39.927938 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 04:40:39.931373 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 04:40:39.938100 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 04:40:39.941260 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 04:40:39.944572 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 04:40:39.951518 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 04:40:39.954526 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 04:40:39.958136 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:40:39.961312 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:40:39.968047 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 04:40:39.971415 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 04:40:39.975091 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
811 04:40:39.981433 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
812 04:40:39.985057 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 04:40:39.988124 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 04:40:39.994891 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 04:40:39.998263 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 04:40:40.001745 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 04:40:40.008460 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 04:40:40.011858 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
819 04:40:40.015387 0 9 12 | B1->B0 | 2828 2f2f | 1 0 | (0 0) (1 1)
820 04:40:40.018968 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 04:40:40.025479 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 04:40:40.028432 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 04:40:40.032154 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 04:40:40.038804 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 04:40:40.041824 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
826 04:40:40.045511 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 1)
827 04:40:40.052017 0 10 12 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (1 0)
828 04:40:40.055688 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 04:40:40.058753 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 04:40:40.065854 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 04:40:40.068933 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 04:40:40.072365 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 04:40:40.075635 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 04:40:40.082318 0 11 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
835 04:40:40.085672 0 11 12 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
836 04:40:40.089424 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 04:40:40.095761 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 04:40:40.099550 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 04:40:40.102662 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 04:40:40.109524 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 04:40:40.112600 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
842 04:40:40.116367 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 04:40:40.122754 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 04:40:40.126155 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 04:40:40.129160 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 04:40:40.136146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 04:40:40.139478 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 04:40:40.143291 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 04:40:40.146234 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 04:40:40.153279 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 04:40:40.156199 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 04:40:40.159704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 04:40:40.166758 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 04:40:40.169538 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 04:40:40.172824 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 04:40:40.179669 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 04:40:40.183148 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 04:40:40.186585 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 04:40:40.189989 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 04:40:40.193313 Total UI for P1: 0, mck2ui 16
861 04:40:40.196769 best dqsien dly found for B0: ( 0, 14, 8)
862 04:40:40.199722 Total UI for P1: 0, mck2ui 16
863 04:40:40.203642 best dqsien dly found for B1: ( 0, 14, 8)
864 04:40:40.206541 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
865 04:40:40.210001 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 04:40:40.210128
867 04:40:40.217023 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
868 04:40:40.220025 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 04:40:40.220157 [Gating] SW calibration Done
870 04:40:40.223682 ==
871 04:40:40.223781 Dram Type= 6, Freq= 0, CH_0, rank 0
872 04:40:40.230482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 04:40:40.230626 ==
874 04:40:40.230728 RX Vref Scan: 0
875 04:40:40.230814
876 04:40:40.233549 RX Vref 0 -> 0, step: 1
877 04:40:40.233640
878 04:40:40.237339 RX Delay -130 -> 252, step: 16
879 04:40:40.240289 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 04:40:40.243890 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
881 04:40:40.247179 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 04:40:40.253620 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 04:40:40.257222 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
884 04:40:40.260920 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
885 04:40:40.263898 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
886 04:40:40.267380 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
887 04:40:40.270402 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
888 04:40:40.277155 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 04:40:40.280820 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 04:40:40.284347 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
891 04:40:40.287385 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
892 04:40:40.290683 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 04:40:40.297497 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 04:40:40.300821 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 04:40:40.300939 ==
896 04:40:40.304424 Dram Type= 6, Freq= 0, CH_0, rank 0
897 04:40:40.307614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 04:40:40.307703 ==
899 04:40:40.311050 DQS Delay:
900 04:40:40.311151 DQS0 = 0, DQS1 = 0
901 04:40:40.311242 DQM Delay:
902 04:40:40.313977 DQM0 = 84, DQM1 = 78
903 04:40:40.314067 DQ Delay:
904 04:40:40.317410 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
905 04:40:40.320866 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
906 04:40:40.324464 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
907 04:40:40.327908 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
908 04:40:40.327997
909 04:40:40.328088
910 04:40:40.328173 ==
911 04:40:40.330841 Dram Type= 6, Freq= 0, CH_0, rank 0
912 04:40:40.334422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 04:40:40.338166 ==
914 04:40:40.338255
915 04:40:40.338345
916 04:40:40.338429 TX Vref Scan disable
917 04:40:40.341038 == TX Byte 0 ==
918 04:40:40.344882 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
919 04:40:40.348383 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
920 04:40:40.351123 == TX Byte 1 ==
921 04:40:40.354796 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
922 04:40:40.357766 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
923 04:40:40.357882 ==
924 04:40:40.361284 Dram Type= 6, Freq= 0, CH_0, rank 0
925 04:40:40.368007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 04:40:40.368096 ==
927 04:40:40.379772 TX Vref=22, minBit 0, minWin=27, winSum=438
928 04:40:40.383267 TX Vref=24, minBit 3, minWin=27, winSum=443
929 04:40:40.386581 TX Vref=26, minBit 5, minWin=27, winSum=448
930 04:40:40.390030 TX Vref=28, minBit 9, minWin=27, winSum=450
931 04:40:40.393607 TX Vref=30, minBit 2, minWin=28, winSum=454
932 04:40:40.396804 TX Vref=32, minBit 1, minWin=28, winSum=453
933 04:40:40.403749 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 30
934 04:40:40.403847
935 04:40:40.406780 Final TX Range 1 Vref 30
936 04:40:40.406870
937 04:40:40.406939 ==
938 04:40:40.410619 Dram Type= 6, Freq= 0, CH_0, rank 0
939 04:40:40.413802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 04:40:40.413904 ==
941 04:40:40.413977
942 04:40:40.414043
943 04:40:40.416950 TX Vref Scan disable
944 04:40:40.420809 == TX Byte 0 ==
945 04:40:40.423870 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
946 04:40:40.426774 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
947 04:40:40.430446 == TX Byte 1 ==
948 04:40:40.433795 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
949 04:40:40.437270 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
950 04:40:40.437361
951 04:40:40.440440 [DATLAT]
952 04:40:40.440523 Freq=800, CH0 RK0
953 04:40:40.440591
954 04:40:40.444053 DATLAT Default: 0xa
955 04:40:40.444137 0, 0xFFFF, sum = 0
956 04:40:40.446889 1, 0xFFFF, sum = 0
957 04:40:40.446969 2, 0xFFFF, sum = 0
958 04:40:40.450365 3, 0xFFFF, sum = 0
959 04:40:40.450464 4, 0xFFFF, sum = 0
960 04:40:40.453441 5, 0xFFFF, sum = 0
961 04:40:40.453522 6, 0xFFFF, sum = 0
962 04:40:40.457141 7, 0xFFFF, sum = 0
963 04:40:40.457249 8, 0xFFFF, sum = 0
964 04:40:40.460205 9, 0x0, sum = 1
965 04:40:40.460319 10, 0x0, sum = 2
966 04:40:40.463671 11, 0x0, sum = 3
967 04:40:40.463749 12, 0x0, sum = 4
968 04:40:40.466791 best_step = 10
969 04:40:40.466901
970 04:40:40.466998 ==
971 04:40:40.470432 Dram Type= 6, Freq= 0, CH_0, rank 0
972 04:40:40.473388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 04:40:40.473496 ==
974 04:40:40.476905 RX Vref Scan: 1
975 04:40:40.476993
976 04:40:40.477061 Set Vref Range= 32 -> 127
977 04:40:40.477124
978 04:40:40.480498 RX Vref 32 -> 127, step: 1
979 04:40:40.480611
980 04:40:40.483503 RX Delay -95 -> 252, step: 8
981 04:40:40.483589
982 04:40:40.487116 Set Vref, RX VrefLevel [Byte0]: 32
983 04:40:40.490484 [Byte1]: 32
984 04:40:40.490572
985 04:40:40.494310 Set Vref, RX VrefLevel [Byte0]: 33
986 04:40:40.497251 [Byte1]: 33
987 04:40:40.497339
988 04:40:40.501064 Set Vref, RX VrefLevel [Byte0]: 34
989 04:40:40.504581 [Byte1]: 34
990 04:40:40.507581
991 04:40:40.507667 Set Vref, RX VrefLevel [Byte0]: 35
992 04:40:40.511137 [Byte1]: 35
993 04:40:40.515266
994 04:40:40.515352 Set Vref, RX VrefLevel [Byte0]: 36
995 04:40:40.518624 [Byte1]: 36
996 04:40:40.522904
997 04:40:40.523000 Set Vref, RX VrefLevel [Byte0]: 37
998 04:40:40.526543 [Byte1]: 37
999 04:40:40.530485
1000 04:40:40.530575 Set Vref, RX VrefLevel [Byte0]: 38
1001 04:40:40.533872 [Byte1]: 38
1002 04:40:40.538741
1003 04:40:40.538836 Set Vref, RX VrefLevel [Byte0]: 39
1004 04:40:40.541413 [Byte1]: 39
1005 04:40:40.546180
1006 04:40:40.546274 Set Vref, RX VrefLevel [Byte0]: 40
1007 04:40:40.549224 [Byte1]: 40
1008 04:40:40.554040
1009 04:40:40.554129 Set Vref, RX VrefLevel [Byte0]: 41
1010 04:40:40.556873 [Byte1]: 41
1011 04:40:40.561228
1012 04:40:40.561318 Set Vref, RX VrefLevel [Byte0]: 42
1013 04:40:40.564777 [Byte1]: 42
1014 04:40:40.568468
1015 04:40:40.568582 Set Vref, RX VrefLevel [Byte0]: 43
1016 04:40:40.571993 [Byte1]: 43
1017 04:40:40.576328
1018 04:40:40.576442 Set Vref, RX VrefLevel [Byte0]: 44
1019 04:40:40.579269 [Byte1]: 44
1020 04:40:40.583492
1021 04:40:40.583577 Set Vref, RX VrefLevel [Byte0]: 45
1022 04:40:40.586930 [Byte1]: 45
1023 04:40:40.591199
1024 04:40:40.591285 Set Vref, RX VrefLevel [Byte0]: 46
1025 04:40:40.594791 [Byte1]: 46
1026 04:40:40.598814
1027 04:40:40.598901 Set Vref, RX VrefLevel [Byte0]: 47
1028 04:40:40.602329 [Byte1]: 47
1029 04:40:40.606203
1030 04:40:40.606290 Set Vref, RX VrefLevel [Byte0]: 48
1031 04:40:40.609552 [Byte1]: 48
1032 04:40:40.614230
1033 04:40:40.614329 Set Vref, RX VrefLevel [Byte0]: 49
1034 04:40:40.617477 [Byte1]: 49
1035 04:40:40.621632
1036 04:40:40.621731 Set Vref, RX VrefLevel [Byte0]: 50
1037 04:40:40.625069 [Byte1]: 50
1038 04:40:40.629432
1039 04:40:40.629521 Set Vref, RX VrefLevel [Byte0]: 51
1040 04:40:40.632283 [Byte1]: 51
1041 04:40:40.636631
1042 04:40:40.636727 Set Vref, RX VrefLevel [Byte0]: 52
1043 04:40:40.640280 [Byte1]: 52
1044 04:40:40.644433
1045 04:40:40.644535 Set Vref, RX VrefLevel [Byte0]: 53
1046 04:40:40.647737 [Byte1]: 53
1047 04:40:40.651952
1048 04:40:40.652048 Set Vref, RX VrefLevel [Byte0]: 54
1049 04:40:40.655540 [Byte1]: 54
1050 04:40:40.659565
1051 04:40:40.659653 Set Vref, RX VrefLevel [Byte0]: 55
1052 04:40:40.662667 [Byte1]: 55
1053 04:40:40.667223
1054 04:40:40.667311 Set Vref, RX VrefLevel [Byte0]: 56
1055 04:40:40.670792 [Byte1]: 56
1056 04:40:40.675001
1057 04:40:40.675090 Set Vref, RX VrefLevel [Byte0]: 57
1058 04:40:40.677905 [Byte1]: 57
1059 04:40:40.682194
1060 04:40:40.682281 Set Vref, RX VrefLevel [Byte0]: 58
1061 04:40:40.685622 [Byte1]: 58
1062 04:40:40.690193
1063 04:40:40.690280 Set Vref, RX VrefLevel [Byte0]: 59
1064 04:40:40.693168 [Byte1]: 59
1065 04:40:40.697547
1066 04:40:40.697632 Set Vref, RX VrefLevel [Byte0]: 60
1067 04:40:40.701073 [Byte1]: 60
1068 04:40:40.704911
1069 04:40:40.705026 Set Vref, RX VrefLevel [Byte0]: 61
1070 04:40:40.708261 [Byte1]: 61
1071 04:40:40.712931
1072 04:40:40.713049 Set Vref, RX VrefLevel [Byte0]: 62
1073 04:40:40.716420 [Byte1]: 62
1074 04:40:40.720315
1075 04:40:40.720434 Set Vref, RX VrefLevel [Byte0]: 63
1076 04:40:40.723771 [Byte1]: 63
1077 04:40:40.728119
1078 04:40:40.728239 Set Vref, RX VrefLevel [Byte0]: 64
1079 04:40:40.731445 [Byte1]: 64
1080 04:40:40.735416
1081 04:40:40.735506 Set Vref, RX VrefLevel [Byte0]: 65
1082 04:40:40.739059 [Byte1]: 65
1083 04:40:40.743043
1084 04:40:40.743138 Set Vref, RX VrefLevel [Byte0]: 66
1085 04:40:40.746286 [Byte1]: 66
1086 04:40:40.750795
1087 04:40:40.750898 Set Vref, RX VrefLevel [Byte0]: 67
1088 04:40:40.754426 [Byte1]: 67
1089 04:40:40.758546
1090 04:40:40.758637 Set Vref, RX VrefLevel [Byte0]: 68
1091 04:40:40.761617 [Byte1]: 68
1092 04:40:40.765887
1093 04:40:40.765973 Set Vref, RX VrefLevel [Byte0]: 69
1094 04:40:40.769353 [Byte1]: 69
1095 04:40:40.773504
1096 04:40:40.773595 Set Vref, RX VrefLevel [Byte0]: 70
1097 04:40:40.776723 [Byte1]: 70
1098 04:40:40.781566
1099 04:40:40.781663 Set Vref, RX VrefLevel [Byte0]: 71
1100 04:40:40.784438 [Byte1]: 71
1101 04:40:40.788448
1102 04:40:40.788565 Set Vref, RX VrefLevel [Byte0]: 72
1103 04:40:40.791919 [Byte1]: 72
1104 04:40:40.796149
1105 04:40:40.796240 Set Vref, RX VrefLevel [Byte0]: 73
1106 04:40:40.799782 [Byte1]: 73
1107 04:40:40.803991
1108 04:40:40.804081 Set Vref, RX VrefLevel [Byte0]: 74
1109 04:40:40.807228 [Byte1]: 74
1110 04:40:40.811839
1111 04:40:40.811930 Set Vref, RX VrefLevel [Byte0]: 75
1112 04:40:40.818275 [Byte1]: 75
1113 04:40:40.818411
1114 04:40:40.821327 Set Vref, RX VrefLevel [Byte0]: 76
1115 04:40:40.824761 [Byte1]: 76
1116 04:40:40.824854
1117 04:40:40.828057 Final RX Vref Byte 0 = 61 to rank0
1118 04:40:40.831223 Final RX Vref Byte 1 = 57 to rank0
1119 04:40:40.834875 Final RX Vref Byte 0 = 61 to rank1
1120 04:40:40.837855 Final RX Vref Byte 1 = 57 to rank1==
1121 04:40:40.841439 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 04:40:40.844583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 04:40:40.844714 ==
1124 04:40:40.848060 DQS Delay:
1125 04:40:40.848147 DQS0 = 0, DQS1 = 0
1126 04:40:40.848214 DQM Delay:
1127 04:40:40.851590 DQM0 = 88, DQM1 = 78
1128 04:40:40.851678 DQ Delay:
1129 04:40:40.854974 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1130 04:40:40.858597 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1131 04:40:40.861443 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1132 04:40:40.865387 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1133 04:40:40.865508
1134 04:40:40.865597
1135 04:40:40.874691 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1136 04:40:40.874830 CH0 RK0: MR19=606, MR18=2910
1137 04:40:40.881903 CH0_RK0: MR19=0x606, MR18=0x2910, DQSOSC=399, MR23=63, INC=92, DEC=61
1138 04:40:40.882039
1139 04:40:40.885164 ----->DramcWriteLeveling(PI) begin...
1140 04:40:40.885272 ==
1141 04:40:40.888496 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 04:40:40.891372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 04:40:40.894969 ==
1144 04:40:40.895077 Write leveling (Byte 0): 30 => 30
1145 04:40:40.898461 Write leveling (Byte 1): 29 => 29
1146 04:40:40.902210 DramcWriteLeveling(PI) end<-----
1147 04:40:40.902358
1148 04:40:40.902461 ==
1149 04:40:40.905179 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 04:40:40.911989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 04:40:40.912116 ==
1152 04:40:40.912190 [Gating] SW mode calibration
1153 04:40:40.922122 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 04:40:40.925460 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 04:40:40.928409 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 04:40:40.935221 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 04:40:40.938636 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 04:40:40.983076 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 04:40:40.983472 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 04:40:40.983602 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 04:40:40.983707 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 04:40:40.983846 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 04:40:40.983949 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 04:40:40.984053 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 04:40:40.984168 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 04:40:40.984272 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 04:40:40.984392 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 04:40:41.027045 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 04:40:41.027408 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 04:40:41.027553 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 04:40:41.027654 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 04:40:41.027746 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 04:40:41.028430 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1174 04:40:41.028717 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 04:40:41.028844 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 04:40:41.028945 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 04:40:41.029058 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 04:40:41.046126 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 04:40:41.046482 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 04:40:41.046597 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 04:40:41.046695 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
1182 04:40:41.050056 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1183 04:40:41.053019 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 04:40:41.056442 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 04:40:41.063470 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 04:40:41.066917 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 04:40:41.069720 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1188 04:40:41.076285 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 04:40:41.079838 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
1190 04:40:41.083359 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1191 04:40:41.086462 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 04:40:41.093715 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 04:40:41.096615 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 04:40:41.100015 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 04:40:41.106907 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 04:40:41.110636 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 04:40:41.114374 0 11 8 | B1->B0 | 2626 3737 | 1 1 | (0 0) (0 0)
1198 04:40:41.117908 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1199 04:40:41.122316 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 04:40:41.128727 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 04:40:41.132372 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 04:40:41.135884 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 04:40:41.139327 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 04:40:41.146177 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 04:40:41.149758 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1206 04:40:41.153167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1207 04:40:41.159907 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 04:40:41.163031 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 04:40:41.166703 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 04:40:41.173457 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 04:40:41.176635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 04:40:41.180401 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 04:40:41.183439 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 04:40:41.190176 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 04:40:41.193847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 04:40:41.196728 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 04:40:41.203780 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 04:40:41.207203 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 04:40:41.210902 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 04:40:41.217049 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 04:40:41.220490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 04:40:41.223614 Total UI for P1: 0, mck2ui 16
1223 04:40:41.227119 best dqsien dly found for B0: ( 0, 14, 6)
1224 04:40:41.230811 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 04:40:41.233750 Total UI for P1: 0, mck2ui 16
1226 04:40:41.237338 best dqsien dly found for B1: ( 0, 14, 8)
1227 04:40:41.240346 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1228 04:40:41.243878 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 04:40:41.243965
1230 04:40:41.247362 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 04:40:41.250709 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 04:40:41.253827 [Gating] SW calibration Done
1233 04:40:41.253944 ==
1234 04:40:41.257697 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 04:40:41.260945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 04:40:41.264324 ==
1237 04:40:41.264438 RX Vref Scan: 0
1238 04:40:41.264534
1239 04:40:41.267263 RX Vref 0 -> 0, step: 1
1240 04:40:41.267366
1241 04:40:41.270662 RX Delay -130 -> 252, step: 16
1242 04:40:41.273905 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1243 04:40:41.277337 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1244 04:40:41.280856 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 04:40:41.283676 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 04:40:41.290502 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1247 04:40:41.294502 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1248 04:40:41.297406 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1249 04:40:41.300834 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1250 04:40:41.304260 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1251 04:40:41.310895 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1252 04:40:41.313861 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 04:40:41.317335 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1254 04:40:41.320579 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1255 04:40:41.324188 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 04:40:41.331021 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1257 04:40:41.333942 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1258 04:40:41.334092 ==
1259 04:40:41.337511 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 04:40:41.340797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 04:40:41.340942 ==
1262 04:40:41.341033 DQS Delay:
1263 04:40:41.344240 DQS0 = 0, DQS1 = 0
1264 04:40:41.344367 DQM Delay:
1265 04:40:41.347121 DQM0 = 86, DQM1 = 77
1266 04:40:41.347220 DQ Delay:
1267 04:40:41.350707 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1268 04:40:41.354387 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1269 04:40:41.357400 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1270 04:40:41.361112 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1271 04:40:41.361240
1272 04:40:41.361339
1273 04:40:41.361431 ==
1274 04:40:41.364122 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 04:40:41.367397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 04:40:41.371092 ==
1277 04:40:41.371227
1278 04:40:41.371337
1279 04:40:41.371432 TX Vref Scan disable
1280 04:40:41.374332 == TX Byte 0 ==
1281 04:40:41.377369 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1282 04:40:41.381003 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1283 04:40:41.384195 == TX Byte 1 ==
1284 04:40:41.387761 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1285 04:40:41.391372 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1286 04:40:41.391479 ==
1287 04:40:41.394737 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 04:40:41.401290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 04:40:41.401403 ==
1290 04:40:41.413346 TX Vref=22, minBit 3, minWin=27, winSum=446
1291 04:40:41.416378 TX Vref=24, minBit 7, minWin=27, winSum=448
1292 04:40:41.420121 TX Vref=26, minBit 3, minWin=27, winSum=450
1293 04:40:41.423315 TX Vref=28, minBit 6, minWin=27, winSum=453
1294 04:40:41.426393 TX Vref=30, minBit 0, minWin=28, winSum=456
1295 04:40:41.429950 TX Vref=32, minBit 0, minWin=28, winSum=455
1296 04:40:41.436443 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1297 04:40:41.436563
1298 04:40:41.440008 Final TX Range 1 Vref 30
1299 04:40:41.440116
1300 04:40:41.440222 ==
1301 04:40:41.443206 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 04:40:41.446694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 04:40:41.446813 ==
1304 04:40:41.446921
1305 04:40:41.450045
1306 04:40:41.450161 TX Vref Scan disable
1307 04:40:41.452836 == TX Byte 0 ==
1308 04:40:41.456320 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 04:40:41.460037 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 04:40:41.463188 == TX Byte 1 ==
1311 04:40:41.466832 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1312 04:40:41.469888 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1313 04:40:41.473347
1314 04:40:41.473456 [DATLAT]
1315 04:40:41.473550 Freq=800, CH0 RK1
1316 04:40:41.473641
1317 04:40:41.476475 DATLAT Default: 0xa
1318 04:40:41.476573 0, 0xFFFF, sum = 0
1319 04:40:41.479785 1, 0xFFFF, sum = 0
1320 04:40:41.479890 2, 0xFFFF, sum = 0
1321 04:40:41.483317 3, 0xFFFF, sum = 0
1322 04:40:41.483424 4, 0xFFFF, sum = 0
1323 04:40:41.486603 5, 0xFFFF, sum = 0
1324 04:40:41.486712 6, 0xFFFF, sum = 0
1325 04:40:41.489891 7, 0xFFFF, sum = 0
1326 04:40:41.489994 8, 0xFFFF, sum = 0
1327 04:40:41.493274 9, 0x0, sum = 1
1328 04:40:41.493376 10, 0x0, sum = 2
1329 04:40:41.496312 11, 0x0, sum = 3
1330 04:40:41.496440 12, 0x0, sum = 4
1331 04:40:41.499982 best_step = 10
1332 04:40:41.500085
1333 04:40:41.500176 ==
1334 04:40:41.503210 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 04:40:41.506681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 04:40:41.506797 ==
1337 04:40:41.509987 RX Vref Scan: 0
1338 04:40:41.510103
1339 04:40:41.510201 RX Vref 0 -> 0, step: 1
1340 04:40:41.510294
1341 04:40:41.513386 RX Delay -95 -> 252, step: 8
1342 04:40:41.520079 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1343 04:40:41.523350 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1344 04:40:41.526857 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1345 04:40:41.529998 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1346 04:40:41.533435 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1347 04:40:41.536818 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1348 04:40:41.543220 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1349 04:40:41.546818 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1350 04:40:41.550109 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1351 04:40:41.553448 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1352 04:40:41.557189 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1353 04:40:41.563842 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1354 04:40:41.566743 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1355 04:40:41.570367 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1356 04:40:41.573455 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1357 04:40:41.576872 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1358 04:40:41.580680 ==
1359 04:40:41.583910 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 04:40:41.586829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 04:40:41.586940 ==
1362 04:40:41.587039 DQS Delay:
1363 04:40:41.590529 DQS0 = 0, DQS1 = 0
1364 04:40:41.590613 DQM Delay:
1365 04:40:41.593896 DQM0 = 87, DQM1 = 77
1366 04:40:41.594006 DQ Delay:
1367 04:40:41.597167 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1368 04:40:41.600522 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1369 04:40:41.604269 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1370 04:40:41.607347 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1371 04:40:41.607438
1372 04:40:41.607509
1373 04:40:41.613957 [DQSOSCAuto] RK1, (LSB)MR18= 0x331c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1374 04:40:41.617189 CH0 RK1: MR19=606, MR18=331C
1375 04:40:41.624370 CH0_RK1: MR19=0x606, MR18=0x331C, DQSOSC=396, MR23=63, INC=94, DEC=62
1376 04:40:41.627154 [RxdqsGatingPostProcess] freq 800
1377 04:40:41.630646 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 04:40:41.634276 Pre-setting of DQS Precalculation
1379 04:40:41.641019 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 04:40:41.641118 ==
1381 04:40:41.643944 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 04:40:41.647374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 04:40:41.647463 ==
1384 04:40:41.654434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 04:40:41.657404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 04:40:41.668136 [CA 0] Center 36 (6~66) winsize 61
1387 04:40:41.671230 [CA 1] Center 36 (6~66) winsize 61
1388 04:40:41.674830 [CA 2] Center 34 (4~64) winsize 61
1389 04:40:41.678072 [CA 3] Center 33 (3~64) winsize 62
1390 04:40:41.681375 [CA 4] Center 34 (4~65) winsize 62
1391 04:40:41.684720 [CA 5] Center 33 (3~64) winsize 62
1392 04:40:41.684838
1393 04:40:41.688369 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 04:40:41.688449
1395 04:40:41.691495 [CATrainingPosCal] consider 1 rank data
1396 04:40:41.694645 u2DelayCellTimex100 = 270/100 ps
1397 04:40:41.698842 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1398 04:40:41.701746 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1399 04:40:41.704961 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1400 04:40:41.711763 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 04:40:41.714731 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 04:40:41.718261 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1403 04:40:41.718353
1404 04:40:41.721727 CA PerBit enable=1, Macro0, CA PI delay=33
1405 04:40:41.721819
1406 04:40:41.724977 [CBTSetCACLKResult] CA Dly = 33
1407 04:40:41.725101 CS Dly: 4 (0~35)
1408 04:40:41.725203 ==
1409 04:40:41.728259 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 04:40:41.734957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 04:40:41.735089 ==
1412 04:40:41.738219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 04:40:41.745002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 04:40:41.753979 [CA 0] Center 36 (6~66) winsize 61
1415 04:40:41.757174 [CA 1] Center 36 (6~66) winsize 61
1416 04:40:41.760377 [CA 2] Center 34 (4~65) winsize 62
1417 04:40:41.764043 [CA 3] Center 33 (3~64) winsize 62
1418 04:40:41.767639 [CA 4] Center 34 (4~65) winsize 62
1419 04:40:41.770564 [CA 5] Center 33 (3~64) winsize 62
1420 04:40:41.770657
1421 04:40:41.774254 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 04:40:41.774337
1423 04:40:41.777641 [CATrainingPosCal] consider 2 rank data
1424 04:40:41.781341 u2DelayCellTimex100 = 270/100 ps
1425 04:40:41.785171 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1426 04:40:41.788685 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1427 04:40:41.792989 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 04:40:41.796552 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 04:40:41.800055 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1430 04:40:41.804157 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 04:40:41.804262
1432 04:40:41.807649 CA PerBit enable=1, Macro0, CA PI delay=33
1433 04:40:41.807775
1434 04:40:41.811582 [CBTSetCACLKResult] CA Dly = 33
1435 04:40:41.811708 CS Dly: 5 (0~38)
1436 04:40:41.811794
1437 04:40:41.814894 ----->DramcWriteLeveling(PI) begin...
1438 04:40:41.815005 ==
1439 04:40:41.818759 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 04:40:41.821830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 04:40:41.821936 ==
1442 04:40:41.825345 Write leveling (Byte 0): 27 => 27
1443 04:40:41.828762 Write leveling (Byte 1): 31 => 31
1444 04:40:41.832095 DramcWriteLeveling(PI) end<-----
1445 04:40:41.832215
1446 04:40:41.832309 ==
1447 04:40:41.835269 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 04:40:41.838571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 04:40:41.842352 ==
1450 04:40:41.842447 [Gating] SW mode calibration
1451 04:40:41.848389 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 04:40:41.855354 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 04:40:41.858498 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 04:40:41.865721 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 04:40:41.868917 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 04:40:41.872435 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 04:40:41.875458 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 04:40:41.882120 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 04:40:41.885788 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 04:40:41.889147 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 04:40:41.895703 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 04:40:41.899239 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 04:40:41.902892 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 04:40:41.909170 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 04:40:41.912492 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 04:40:41.916221 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 04:40:41.922486 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 04:40:41.925899 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1469 04:40:41.929303 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 04:40:41.935752 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1471 04:40:41.939043 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1472 04:40:41.942404 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 04:40:41.946239 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 04:40:41.952833 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 04:40:41.956223 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 04:40:41.959591 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 04:40:41.966197 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 04:40:41.969325 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 04:40:41.972549 0 9 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1480 04:40:41.979351 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 04:40:41.982920 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 04:40:41.985950 0 9 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1483 04:40:41.993057 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1484 04:40:41.995980 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 04:40:41.999585 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1486 04:40:42.006456 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
1487 04:40:42.009777 0 10 8 | B1->B0 | 2d2d 2f2f | 1 0 | (1 0) (0 1)
1488 04:40:42.013169 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 04:40:42.016777 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 04:40:42.023340 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 04:40:42.026309 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 04:40:42.029997 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 04:40:42.036395 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 04:40:42.040270 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1495 04:40:42.043527 0 11 8 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
1496 04:40:42.049798 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 04:40:42.053726 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 04:40:42.056768 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 04:40:42.060231 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 04:40:42.067200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 04:40:42.070241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 04:40:42.073276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 04:40:42.080393 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1504 04:40:42.083667 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 04:40:42.086900 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 04:40:42.093578 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 04:40:42.097080 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 04:40:42.100607 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 04:40:42.107253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 04:40:42.110256 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 04:40:42.114352 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 04:40:42.120782 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 04:40:42.124276 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 04:40:42.127199 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 04:40:42.130685 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 04:40:42.137269 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 04:40:42.140784 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 04:40:42.144024 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 04:40:42.150755 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 04:40:42.150886 Total UI for P1: 0, mck2ui 16
1521 04:40:42.157712 best dqsien dly found for B0: ( 0, 14, 6)
1522 04:40:42.157834 Total UI for P1: 0, mck2ui 16
1523 04:40:42.163984 best dqsien dly found for B1: ( 0, 14, 6)
1524 04:40:42.167574 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1525 04:40:42.170739 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1526 04:40:42.170826
1527 04:40:42.174281 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 04:40:42.177704 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 04:40:42.180785 [Gating] SW calibration Done
1530 04:40:42.180871 ==
1531 04:40:42.184537 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 04:40:42.187426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 04:40:42.187540 ==
1534 04:40:42.187639 RX Vref Scan: 0
1535 04:40:42.190797
1536 04:40:42.190908 RX Vref 0 -> 0, step: 1
1537 04:40:42.191002
1538 04:40:42.194767 RX Delay -130 -> 252, step: 16
1539 04:40:42.197976 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1540 04:40:42.201256 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1541 04:40:42.207668 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1542 04:40:42.211290 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1543 04:40:42.214475 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1544 04:40:42.217777 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1545 04:40:42.221406 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1546 04:40:42.228541 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1547 04:40:42.231410 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1548 04:40:42.234601 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1549 04:40:42.238265 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1550 04:40:42.241523 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1551 04:40:42.247983 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1552 04:40:42.251477 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1553 04:40:42.255203 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1554 04:40:42.258164 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1555 04:40:42.258243 ==
1556 04:40:42.261555 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 04:40:42.264940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 04:40:42.265026 ==
1559 04:40:42.268693 DQS Delay:
1560 04:40:42.268778 DQS0 = 0, DQS1 = 0
1561 04:40:42.271826 DQM Delay:
1562 04:40:42.271953 DQM0 = 83, DQM1 = 75
1563 04:40:42.272050 DQ Delay:
1564 04:40:42.275244 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1565 04:40:42.278388 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77
1566 04:40:42.281801 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1567 04:40:42.285225 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1568 04:40:42.285310
1569 04:40:42.285396
1570 04:40:42.288820 ==
1571 04:40:42.288912 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 04:40:42.294979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 04:40:42.295095 ==
1574 04:40:42.295196
1575 04:40:42.295298
1576 04:40:42.298818 TX Vref Scan disable
1577 04:40:42.298906 == TX Byte 0 ==
1578 04:40:42.301931 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1579 04:40:42.308744 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1580 04:40:42.308856 == TX Byte 1 ==
1581 04:40:42.311636 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1582 04:40:42.318727 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1583 04:40:42.318843 ==
1584 04:40:42.322478 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 04:40:42.325174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 04:40:42.325263 ==
1587 04:40:42.338958 TX Vref=22, minBit 11, minWin=26, winSum=438
1588 04:40:42.341887 TX Vref=24, minBit 0, minWin=27, winSum=443
1589 04:40:42.345491 TX Vref=26, minBit 0, minWin=27, winSum=444
1590 04:40:42.348492 TX Vref=28, minBit 3, minWin=27, winSum=450
1591 04:40:42.352020 TX Vref=30, minBit 1, minWin=28, winSum=458
1592 04:40:42.355568 TX Vref=32, minBit 11, minWin=27, winSum=453
1593 04:40:42.362707 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 30
1594 04:40:42.362836
1595 04:40:42.366072 Final TX Range 1 Vref 30
1596 04:40:42.366156
1597 04:40:42.366224 ==
1598 04:40:42.369210 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 04:40:42.372628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 04:40:42.372727 ==
1601 04:40:42.372797
1602 04:40:42.372859
1603 04:40:42.376044 TX Vref Scan disable
1604 04:40:42.379307 == TX Byte 0 ==
1605 04:40:42.382498 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1606 04:40:42.385822 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1607 04:40:42.389499 == TX Byte 1 ==
1608 04:40:42.392880 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1609 04:40:42.395918 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1610 04:40:42.396026
1611 04:40:42.399481 [DATLAT]
1612 04:40:42.399589 Freq=800, CH1 RK0
1613 04:40:42.399682
1614 04:40:42.402585 DATLAT Default: 0xa
1615 04:40:42.402691 0, 0xFFFF, sum = 0
1616 04:40:42.405841 1, 0xFFFF, sum = 0
1617 04:40:42.405917 2, 0xFFFF, sum = 0
1618 04:40:42.409191 3, 0xFFFF, sum = 0
1619 04:40:42.409274 4, 0xFFFF, sum = 0
1620 04:40:42.412543 5, 0xFFFF, sum = 0
1621 04:40:42.412660 6, 0xFFFF, sum = 0
1622 04:40:42.415841 7, 0xFFFF, sum = 0
1623 04:40:42.415943 8, 0xFFFF, sum = 0
1624 04:40:42.419363 9, 0x0, sum = 1
1625 04:40:42.419465 10, 0x0, sum = 2
1626 04:40:42.422935 11, 0x0, sum = 3
1627 04:40:42.423045 12, 0x0, sum = 4
1628 04:40:42.426511 best_step = 10
1629 04:40:42.426596
1630 04:40:42.426662 ==
1631 04:40:42.429342 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 04:40:42.433010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 04:40:42.433096 ==
1634 04:40:42.433162 RX Vref Scan: 1
1635 04:40:42.433224
1636 04:40:42.436348 Set Vref Range= 32 -> 127
1637 04:40:42.436459
1638 04:40:42.440044 RX Vref 32 -> 127, step: 1
1639 04:40:42.440150
1640 04:40:42.442912 RX Delay -111 -> 252, step: 8
1641 04:40:42.443022
1642 04:40:42.446696 Set Vref, RX VrefLevel [Byte0]: 32
1643 04:40:42.449855 [Byte1]: 32
1644 04:40:42.449940
1645 04:40:42.453194 Set Vref, RX VrefLevel [Byte0]: 33
1646 04:40:42.456590 [Byte1]: 33
1647 04:40:42.456704
1648 04:40:42.459741 Set Vref, RX VrefLevel [Byte0]: 34
1649 04:40:42.463210 [Byte1]: 34
1650 04:40:42.466712
1651 04:40:42.466797 Set Vref, RX VrefLevel [Byte0]: 35
1652 04:40:42.470523 [Byte1]: 35
1653 04:40:42.474693
1654 04:40:42.474807 Set Vref, RX VrefLevel [Byte0]: 36
1655 04:40:42.477717 [Byte1]: 36
1656 04:40:42.482479
1657 04:40:42.482565 Set Vref, RX VrefLevel [Byte0]: 37
1658 04:40:42.485727 [Byte1]: 37
1659 04:40:42.489858
1660 04:40:42.489942 Set Vref, RX VrefLevel [Byte0]: 38
1661 04:40:42.493215 [Byte1]: 38
1662 04:40:42.497247
1663 04:40:42.497333 Set Vref, RX VrefLevel [Byte0]: 39
1664 04:40:42.500522 [Byte1]: 39
1665 04:40:42.505046
1666 04:40:42.505134 Set Vref, RX VrefLevel [Byte0]: 40
1667 04:40:42.508790 [Byte1]: 40
1668 04:40:42.512848
1669 04:40:42.512933 Set Vref, RX VrefLevel [Byte0]: 41
1670 04:40:42.516184 [Byte1]: 41
1671 04:40:42.520265
1672 04:40:42.520380 Set Vref, RX VrefLevel [Byte0]: 42
1673 04:40:42.523711 [Byte1]: 42
1674 04:40:42.528226
1675 04:40:42.528317 Set Vref, RX VrefLevel [Byte0]: 43
1676 04:40:42.531234 [Byte1]: 43
1677 04:40:42.535850
1678 04:40:42.535936 Set Vref, RX VrefLevel [Byte0]: 44
1679 04:40:42.539252 [Byte1]: 44
1680 04:40:42.543560
1681 04:40:42.543645 Set Vref, RX VrefLevel [Byte0]: 45
1682 04:40:42.546434 [Byte1]: 45
1683 04:40:42.551725
1684 04:40:42.551811 Set Vref, RX VrefLevel [Byte0]: 46
1685 04:40:42.554347 [Byte1]: 46
1686 04:40:42.558380
1687 04:40:42.558498 Set Vref, RX VrefLevel [Byte0]: 47
1688 04:40:42.561979 [Byte1]: 47
1689 04:40:42.566040
1690 04:40:42.566126 Set Vref, RX VrefLevel [Byte0]: 48
1691 04:40:42.569595 [Byte1]: 48
1692 04:40:42.573746
1693 04:40:42.573862 Set Vref, RX VrefLevel [Byte0]: 49
1694 04:40:42.577536 [Byte1]: 49
1695 04:40:42.581568
1696 04:40:42.581650 Set Vref, RX VrefLevel [Byte0]: 50
1697 04:40:42.584672 [Byte1]: 50
1698 04:40:42.589400
1699 04:40:42.589519 Set Vref, RX VrefLevel [Byte0]: 51
1700 04:40:42.592547 [Byte1]: 51
1701 04:40:42.596918
1702 04:40:42.596995 Set Vref, RX VrefLevel [Byte0]: 52
1703 04:40:42.600478 [Byte1]: 52
1704 04:40:42.604393
1705 04:40:42.604474 Set Vref, RX VrefLevel [Byte0]: 53
1706 04:40:42.607862 [Byte1]: 53
1707 04:40:42.611974
1708 04:40:42.612056 Set Vref, RX VrefLevel [Byte0]: 54
1709 04:40:42.615349 [Byte1]: 54
1710 04:40:42.619857
1711 04:40:42.619943 Set Vref, RX VrefLevel [Byte0]: 55
1712 04:40:42.623254 [Byte1]: 55
1713 04:40:42.627241
1714 04:40:42.627320 Set Vref, RX VrefLevel [Byte0]: 56
1715 04:40:42.630827 [Byte1]: 56
1716 04:40:42.634958
1717 04:40:42.635060 Set Vref, RX VrefLevel [Byte0]: 57
1718 04:40:42.638762 [Byte1]: 57
1719 04:40:42.642558
1720 04:40:42.642641 Set Vref, RX VrefLevel [Byte0]: 58
1721 04:40:42.646330 [Byte1]: 58
1722 04:40:42.650711
1723 04:40:42.650799 Set Vref, RX VrefLevel [Byte0]: 59
1724 04:40:42.653763 [Byte1]: 59
1725 04:40:42.657803
1726 04:40:42.657889 Set Vref, RX VrefLevel [Byte0]: 60
1727 04:40:42.661375 [Byte1]: 60
1728 04:40:42.665484
1729 04:40:42.665568 Set Vref, RX VrefLevel [Byte0]: 61
1730 04:40:42.672014 [Byte1]: 61
1731 04:40:42.672103
1732 04:40:42.675721 Set Vref, RX VrefLevel [Byte0]: 62
1733 04:40:42.678740 [Byte1]: 62
1734 04:40:42.678825
1735 04:40:42.682286 Set Vref, RX VrefLevel [Byte0]: 63
1736 04:40:42.685205 [Byte1]: 63
1737 04:40:42.685291
1738 04:40:42.688860 Set Vref, RX VrefLevel [Byte0]: 64
1739 04:40:42.692247 [Byte1]: 64
1740 04:40:42.696222
1741 04:40:42.696312 Set Vref, RX VrefLevel [Byte0]: 65
1742 04:40:42.699470 [Byte1]: 65
1743 04:40:42.703756
1744 04:40:42.703870 Set Vref, RX VrefLevel [Byte0]: 66
1745 04:40:42.707118 [Byte1]: 66
1746 04:40:42.711778
1747 04:40:42.711867 Set Vref, RX VrefLevel [Byte0]: 67
1748 04:40:42.715289 [Byte1]: 67
1749 04:40:42.719236
1750 04:40:42.719351 Set Vref, RX VrefLevel [Byte0]: 68
1751 04:40:42.722470 [Byte1]: 68
1752 04:40:42.726608
1753 04:40:42.726686 Set Vref, RX VrefLevel [Byte0]: 69
1754 04:40:42.730121 [Byte1]: 69
1755 04:40:42.734325
1756 04:40:42.734409 Set Vref, RX VrefLevel [Byte0]: 70
1757 04:40:42.737940 [Byte1]: 70
1758 04:40:42.742000
1759 04:40:42.742083 Set Vref, RX VrefLevel [Byte0]: 71
1760 04:40:42.745430 [Byte1]: 71
1761 04:40:42.749843
1762 04:40:42.749927 Set Vref, RX VrefLevel [Byte0]: 72
1763 04:40:42.753363 [Byte1]: 72
1764 04:40:42.757726
1765 04:40:42.757810 Set Vref, RX VrefLevel [Byte0]: 73
1766 04:40:42.760692 [Byte1]: 73
1767 04:40:42.765038
1768 04:40:42.765147 Set Vref, RX VrefLevel [Byte0]: 74
1769 04:40:42.768514 [Byte1]: 74
1770 04:40:42.772873
1771 04:40:42.772957 Set Vref, RX VrefLevel [Byte0]: 75
1772 04:40:42.776276 [Byte1]: 75
1773 04:40:42.780518
1774 04:40:42.780624 Set Vref, RX VrefLevel [Byte0]: 76
1775 04:40:42.783682 [Byte1]: 76
1776 04:40:42.788335
1777 04:40:42.788435 Set Vref, RX VrefLevel [Byte0]: 77
1778 04:40:42.791292 [Byte1]: 77
1779 04:40:42.795428
1780 04:40:42.795526 Set Vref, RX VrefLevel [Byte0]: 78
1781 04:40:42.799033 [Byte1]: 78
1782 04:40:42.803655
1783 04:40:42.803754 Final RX Vref Byte 0 = 64 to rank0
1784 04:40:42.806554 Final RX Vref Byte 1 = 58 to rank0
1785 04:40:42.810039 Final RX Vref Byte 0 = 64 to rank1
1786 04:40:42.813155 Final RX Vref Byte 1 = 58 to rank1==
1787 04:40:42.816641 Dram Type= 6, Freq= 0, CH_1, rank 0
1788 04:40:42.820107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 04:40:42.823403 ==
1790 04:40:42.823578 DQS Delay:
1791 04:40:42.823678 DQS0 = 0, DQS1 = 0
1792 04:40:42.826718 DQM Delay:
1793 04:40:42.826820 DQM0 = 83, DQM1 = 74
1794 04:40:42.829868 DQ Delay:
1795 04:40:42.833774 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1796 04:40:42.833881 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1797 04:40:42.836851 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1798 04:40:42.840384 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1799 04:40:42.840469
1800 04:40:42.843753
1801 04:40:42.850232 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1802 04:40:42.853298 CH1 RK0: MR19=605, MR18=26FB
1803 04:40:42.860258 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1804 04:40:42.860343
1805 04:40:42.863324 ----->DramcWriteLeveling(PI) begin...
1806 04:40:42.863410 ==
1807 04:40:42.866704 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 04:40:42.870218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 04:40:42.870302 ==
1810 04:40:42.874035 Write leveling (Byte 0): 27 => 27
1811 04:40:42.876956 Write leveling (Byte 1): 29 => 29
1812 04:40:42.880000 DramcWriteLeveling(PI) end<-----
1813 04:40:42.880084
1814 04:40:42.880149 ==
1815 04:40:42.883757 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 04:40:42.886745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 04:40:42.886824 ==
1818 04:40:42.890181 [Gating] SW mode calibration
1819 04:40:42.896864 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1820 04:40:42.903923 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1821 04:40:42.906819 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1822 04:40:42.910213 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1823 04:40:42.916978 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1824 04:40:42.920126 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 04:40:42.923371 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 04:40:42.926994 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 04:40:42.933500 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 04:40:42.936770 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 04:40:42.940549 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 04:40:42.947299 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 04:40:42.950624 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 04:40:42.953760 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 04:40:42.960204 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1834 04:40:42.963486 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1835 04:40:42.967149 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1836 04:40:42.973737 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1837 04:40:42.976837 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (1 1)
1838 04:40:42.980793 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1839 04:40:42.987204 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1840 04:40:42.990756 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 04:40:42.993849 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1842 04:40:43.000280 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 04:40:43.003728 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 04:40:43.007321 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 04:40:43.010555 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 04:40:43.017074 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1847 04:40:43.020922 0 9 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
1848 04:40:43.023852 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1849 04:40:43.030747 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 04:40:43.033831 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 04:40:43.037559 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 04:40:43.043844 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1853 04:40:43.047548 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1854 04:40:43.050760 0 10 4 | B1->B0 | 3131 2e2e | 0 0 | (1 0) (1 0)
1855 04:40:43.057103 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1856 04:40:43.060794 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 04:40:43.064266 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 04:40:43.070815 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 04:40:43.074583 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 04:40:43.077995 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 04:40:43.081116 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 04:40:43.087992 0 11 4 | B1->B0 | 2828 3131 | 0 0 | (1 1) (1 1)
1863 04:40:43.091163 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1864 04:40:43.094614 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 04:40:43.101183 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 04:40:43.104282 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 04:40:43.108115 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 04:40:43.114634 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 04:40:43.117836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 04:40:43.121413 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1871 04:40:43.124490 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 04:40:43.131566 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 04:40:43.135054 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 04:40:43.138233 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 04:40:43.144645 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 04:40:43.148374 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 04:40:43.151428 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 04:40:43.158308 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 04:40:43.161980 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 04:40:43.165303 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 04:40:43.171898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 04:40:43.175206 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 04:40:43.178673 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 04:40:43.181660 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 04:40:43.188997 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 04:40:43.191874 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1887 04:40:43.195231 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1888 04:40:43.199275 Total UI for P1: 0, mck2ui 16
1889 04:40:43.202058 best dqsien dly found for B0: ( 0, 14, 4)
1890 04:40:43.209001 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 04:40:43.209087 Total UI for P1: 0, mck2ui 16
1892 04:40:43.215755 best dqsien dly found for B1: ( 0, 14, 6)
1893 04:40:43.219315 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1894 04:40:43.222673 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1895 04:40:43.222781
1896 04:40:43.225494 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1897 04:40:43.229064 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1898 04:40:43.232176 [Gating] SW calibration Done
1899 04:40:43.232285 ==
1900 04:40:43.235883 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 04:40:43.238856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 04:40:43.238976 ==
1903 04:40:43.239046 RX Vref Scan: 0
1904 04:40:43.242283
1905 04:40:43.242392 RX Vref 0 -> 0, step: 1
1906 04:40:43.242459
1907 04:40:43.246043 RX Delay -130 -> 252, step: 16
1908 04:40:43.248903 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1909 04:40:43.252443 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1910 04:40:43.259025 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1911 04:40:43.262483 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1912 04:40:43.265643 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1913 04:40:43.269262 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1914 04:40:43.272584 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1915 04:40:43.279415 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1916 04:40:43.282752 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1917 04:40:43.286076 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1918 04:40:43.289767 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1919 04:40:43.292729 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1920 04:40:43.296267 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1921 04:40:43.303042 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1922 04:40:43.306410 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1923 04:40:43.309942 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1924 04:40:43.310027 ==
1925 04:40:43.312725 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 04:40:43.316387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 04:40:43.316472 ==
1928 04:40:43.319780 DQS Delay:
1929 04:40:43.319864 DQS0 = 0, DQS1 = 0
1930 04:40:43.323017 DQM Delay:
1931 04:40:43.323102 DQM0 = 80, DQM1 = 76
1932 04:40:43.323168 DQ Delay:
1933 04:40:43.326497 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1934 04:40:43.329886 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1935 04:40:43.333484 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1936 04:40:43.336493 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1937 04:40:43.336577
1938 04:40:43.336642
1939 04:40:43.340051 ==
1940 04:40:43.340135 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 04:40:43.346751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 04:40:43.346876 ==
1943 04:40:43.346949
1944 04:40:43.347012
1945 04:40:43.347071 TX Vref Scan disable
1946 04:40:43.350837 == TX Byte 0 ==
1947 04:40:43.353931 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1948 04:40:43.357364 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1949 04:40:43.360289 == TX Byte 1 ==
1950 04:40:43.364174 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1951 04:40:43.367026 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1952 04:40:43.370378 ==
1953 04:40:43.374664 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 04:40:43.377438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 04:40:43.377522 ==
1956 04:40:43.389441 TX Vref=22, minBit 0, minWin=27, winSum=442
1957 04:40:43.393067 TX Vref=24, minBit 10, minWin=27, winSum=446
1958 04:40:43.396052 TX Vref=26, minBit 10, minWin=27, winSum=448
1959 04:40:43.399602 TX Vref=28, minBit 0, minWin=28, winSum=453
1960 04:40:43.403407 TX Vref=30, minBit 0, minWin=28, winSum=456
1961 04:40:43.409993 TX Vref=32, minBit 0, minWin=28, winSum=454
1962 04:40:43.412715 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1963 04:40:43.412806
1964 04:40:43.416468 Final TX Range 1 Vref 30
1965 04:40:43.416553
1966 04:40:43.416622 ==
1967 04:40:43.419328 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 04:40:43.422954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 04:40:43.423040 ==
1970 04:40:43.423105
1971 04:40:43.426313
1972 04:40:43.426397 TX Vref Scan disable
1973 04:40:43.429665 == TX Byte 0 ==
1974 04:40:43.433442 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 04:40:43.436268 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 04:40:43.439728 == TX Byte 1 ==
1977 04:40:43.442758 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1978 04:40:43.446436 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1979 04:40:43.449352
1980 04:40:43.449448 [DATLAT]
1981 04:40:43.449516 Freq=800, CH1 RK1
1982 04:40:43.449578
1983 04:40:43.452967 DATLAT Default: 0xa
1984 04:40:43.453055 0, 0xFFFF, sum = 0
1985 04:40:43.456593 1, 0xFFFF, sum = 0
1986 04:40:43.456725 2, 0xFFFF, sum = 0
1987 04:40:43.459771 3, 0xFFFF, sum = 0
1988 04:40:43.459855 4, 0xFFFF, sum = 0
1989 04:40:43.462996 5, 0xFFFF, sum = 0
1990 04:40:43.463116 6, 0xFFFF, sum = 0
1991 04:40:43.466573 7, 0xFFFF, sum = 0
1992 04:40:43.469775 8, 0xFFFF, sum = 0
1993 04:40:43.469899 9, 0x0, sum = 1
1994 04:40:43.469972 10, 0x0, sum = 2
1995 04:40:43.473528 11, 0x0, sum = 3
1996 04:40:43.473614 12, 0x0, sum = 4
1997 04:40:43.476200 best_step = 10
1998 04:40:43.476284
1999 04:40:43.476351 ==
2000 04:40:43.479724 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 04:40:43.483298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 04:40:43.483384 ==
2003 04:40:43.486753 RX Vref Scan: 0
2004 04:40:43.486839
2005 04:40:43.486904 RX Vref 0 -> 0, step: 1
2006 04:40:43.486965
2007 04:40:43.489614 RX Delay -111 -> 252, step: 8
2008 04:40:43.496565 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2009 04:40:43.499899 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2010 04:40:43.503146 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2011 04:40:43.506890 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2012 04:40:43.509865 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2013 04:40:43.513506 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2014 04:40:43.520425 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2015 04:40:43.523473 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2016 04:40:43.526645 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2017 04:40:43.530115 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2018 04:40:43.533544 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2019 04:40:43.540263 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2020 04:40:43.543908 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2021 04:40:43.546890 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2022 04:40:43.550525 iDelay=201, Bit 14, Center 80 (-39 ~ 200) 240
2023 04:40:43.553529 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2024 04:40:43.557299 ==
2025 04:40:43.560171 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 04:40:43.563888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 04:40:43.564000 ==
2028 04:40:43.564099 DQS Delay:
2029 04:40:43.567318 DQS0 = 0, DQS1 = 0
2030 04:40:43.567426 DQM Delay:
2031 04:40:43.570459 DQM0 = 80, DQM1 = 75
2032 04:40:43.570564 DQ Delay:
2033 04:40:43.574296 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =80
2034 04:40:43.577156 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
2035 04:40:43.580911 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2036 04:40:43.584364 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2037 04:40:43.584452
2038 04:40:43.584556
2039 04:40:43.590544 [DQSOSCAuto] RK1, (LSB)MR18= 0x212c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2040 04:40:43.593958 CH1 RK1: MR19=606, MR18=212C
2041 04:40:43.600574 CH1_RK1: MR19=0x606, MR18=0x212C, DQSOSC=398, MR23=63, INC=93, DEC=62
2042 04:40:43.603979 [RxdqsGatingPostProcess] freq 800
2043 04:40:43.607235 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 04:40:43.610906 Pre-setting of DQS Precalculation
2045 04:40:43.617254 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 04:40:43.623896 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 04:40:43.631163 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 04:40:43.631258
2049 04:40:43.631361
2050 04:40:43.633994 [Calibration Summary] 1600 Mbps
2051 04:40:43.634082 CH 0, Rank 0
2052 04:40:43.637817 SW Impedance : PASS
2053 04:40:43.641035 DUTY Scan : NO K
2054 04:40:43.641122 ZQ Calibration : PASS
2055 04:40:43.644596 Jitter Meter : NO K
2056 04:40:43.647849 CBT Training : PASS
2057 04:40:43.647937 Write leveling : PASS
2058 04:40:43.650768 RX DQS gating : PASS
2059 04:40:43.650855 RX DQ/DQS(RDDQC) : PASS
2060 04:40:43.654189 TX DQ/DQS : PASS
2061 04:40:43.657699 RX DATLAT : PASS
2062 04:40:43.657787 RX DQ/DQS(Engine): PASS
2063 04:40:43.661434 TX OE : NO K
2064 04:40:43.661521 All Pass.
2065 04:40:43.661609
2066 04:40:43.664524 CH 0, Rank 1
2067 04:40:43.664610 SW Impedance : PASS
2068 04:40:43.668175 DUTY Scan : NO K
2069 04:40:43.671670 ZQ Calibration : PASS
2070 04:40:43.671760 Jitter Meter : NO K
2071 04:40:43.674736 CBT Training : PASS
2072 04:40:43.677972 Write leveling : PASS
2073 04:40:43.678060 RX DQS gating : PASS
2074 04:40:43.681267 RX DQ/DQS(RDDQC) : PASS
2075 04:40:43.681355 TX DQ/DQS : PASS
2076 04:40:43.684548 RX DATLAT : PASS
2077 04:40:43.688140 RX DQ/DQS(Engine): PASS
2078 04:40:43.688227 TX OE : NO K
2079 04:40:43.691132 All Pass.
2080 04:40:43.691225
2081 04:40:43.691313 CH 1, Rank 0
2082 04:40:43.694593 SW Impedance : PASS
2083 04:40:43.694680 DUTY Scan : NO K
2084 04:40:43.698265 ZQ Calibration : PASS
2085 04:40:43.701620 Jitter Meter : NO K
2086 04:40:43.701732 CBT Training : PASS
2087 04:40:43.704513 Write leveling : PASS
2088 04:40:43.708004 RX DQS gating : PASS
2089 04:40:43.708110 RX DQ/DQS(RDDQC) : PASS
2090 04:40:43.711412 TX DQ/DQS : PASS
2091 04:40:43.714727 RX DATLAT : PASS
2092 04:40:43.714811 RX DQ/DQS(Engine): PASS
2093 04:40:43.718166 TX OE : NO K
2094 04:40:43.718283 All Pass.
2095 04:40:43.718379
2096 04:40:43.718489 CH 1, Rank 1
2097 04:40:43.721280 SW Impedance : PASS
2098 04:40:43.724912 DUTY Scan : NO K
2099 04:40:43.725027 ZQ Calibration : PASS
2100 04:40:43.728573 Jitter Meter : NO K
2101 04:40:43.731963 CBT Training : PASS
2102 04:40:43.732076 Write leveling : PASS
2103 04:40:43.735034 RX DQS gating : PASS
2104 04:40:43.738668 RX DQ/DQS(RDDQC) : PASS
2105 04:40:43.738787 TX DQ/DQS : PASS
2106 04:40:43.741522 RX DATLAT : PASS
2107 04:40:43.745166 RX DQ/DQS(Engine): PASS
2108 04:40:43.745278 TX OE : NO K
2109 04:40:43.745374 All Pass.
2110 04:40:43.745471
2111 04:40:43.748994 DramC Write-DBI off
2112 04:40:43.752018 PER_BANK_REFRESH: Hybrid Mode
2113 04:40:43.752124 TX_TRACKING: ON
2114 04:40:43.755309 [GetDramInforAfterCalByMRR] Vendor 6.
2115 04:40:43.758417 [GetDramInforAfterCalByMRR] Revision 606.
2116 04:40:43.765271 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 04:40:43.765384 MR0 0x3b3b
2118 04:40:43.765486 MR8 0x5151
2119 04:40:43.768628 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 04:40:43.768749
2121 04:40:43.772313 MR0 0x3b3b
2122 04:40:43.772416 MR8 0x5151
2123 04:40:43.775138 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 04:40:43.775238
2125 04:40:43.785361 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 04:40:43.789048 [FAST_K] Save calibration result to emmc
2127 04:40:43.791829 [FAST_K] Save calibration result to emmc
2128 04:40:43.795490 dram_init: config_dvfs: 1
2129 04:40:43.798964 dramc_set_vcore_voltage set vcore to 662500
2130 04:40:43.799073 Read voltage for 1200, 2
2131 04:40:43.801879 Vio18 = 0
2132 04:40:43.801988 Vcore = 662500
2133 04:40:43.802083 Vdram = 0
2134 04:40:43.805341 Vddq = 0
2135 04:40:43.805448 Vmddr = 0
2136 04:40:43.808779 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 04:40:43.815591 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 04:40:43.818972 MEM_TYPE=3, freq_sel=15
2139 04:40:43.822413 sv_algorithm_assistance_LP4_1600
2140 04:40:43.825275 ============ PULL DRAM RESETB DOWN ============
2141 04:40:43.828892 ========== PULL DRAM RESETB DOWN end =========
2142 04:40:43.831835 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 04:40:43.835385 ===================================
2144 04:40:43.839031 LPDDR4 DRAM CONFIGURATION
2145 04:40:43.841924 ===================================
2146 04:40:43.845852 EX_ROW_EN[0] = 0x0
2147 04:40:43.845971 EX_ROW_EN[1] = 0x0
2148 04:40:43.849256 LP4Y_EN = 0x0
2149 04:40:43.849376 WORK_FSP = 0x0
2150 04:40:43.852192 WL = 0x4
2151 04:40:43.852302 RL = 0x4
2152 04:40:43.856006 BL = 0x2
2153 04:40:43.856116 RPST = 0x0
2154 04:40:43.859015 RD_PRE = 0x0
2155 04:40:43.859122 WR_PRE = 0x1
2156 04:40:43.862152 WR_PST = 0x0
2157 04:40:43.862258 DBI_WR = 0x0
2158 04:40:43.865701 DBI_RD = 0x0
2159 04:40:43.865811 OTF = 0x1
2160 04:40:43.869252 ===================================
2161 04:40:43.872629 ===================================
2162 04:40:43.875572 ANA top config
2163 04:40:43.879169 ===================================
2164 04:40:43.882118 DLL_ASYNC_EN = 0
2165 04:40:43.882197 ALL_SLAVE_EN = 0
2166 04:40:43.885848 NEW_RANK_MODE = 1
2167 04:40:43.889357 DLL_IDLE_MODE = 1
2168 04:40:43.892947 LP45_APHY_COMB_EN = 1
2169 04:40:43.893037 TX_ODT_DIS = 1
2170 04:40:43.896160 NEW_8X_MODE = 1
2171 04:40:43.899545 ===================================
2172 04:40:43.902560 ===================================
2173 04:40:43.906127 data_rate = 2400
2174 04:40:43.909738 CKR = 1
2175 04:40:43.912541 DQ_P2S_RATIO = 8
2176 04:40:43.916008 ===================================
2177 04:40:43.916096 CA_P2S_RATIO = 8
2178 04:40:43.919365 DQ_CA_OPEN = 0
2179 04:40:43.922799 DQ_SEMI_OPEN = 0
2180 04:40:43.926169 CA_SEMI_OPEN = 0
2181 04:40:43.929237 CA_FULL_RATE = 0
2182 04:40:43.932585 DQ_CKDIV4_EN = 0
2183 04:40:43.932701 CA_CKDIV4_EN = 0
2184 04:40:43.935914 CA_PREDIV_EN = 0
2185 04:40:43.939745 PH8_DLY = 17
2186 04:40:43.942891 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 04:40:43.946316 DQ_AAMCK_DIV = 4
2188 04:40:43.949816 CA_AAMCK_DIV = 4
2189 04:40:43.949923 CA_ADMCK_DIV = 4
2190 04:40:43.953478 DQ_TRACK_CA_EN = 0
2191 04:40:43.956483 CA_PICK = 1200
2192 04:40:43.959563 CA_MCKIO = 1200
2193 04:40:43.962980 MCKIO_SEMI = 0
2194 04:40:43.966334 PLL_FREQ = 2366
2195 04:40:43.969766 DQ_UI_PI_RATIO = 32
2196 04:40:43.969879 CA_UI_PI_RATIO = 0
2197 04:40:43.972872 ===================================
2198 04:40:43.976523 ===================================
2199 04:40:43.979872 memory_type:LPDDR4
2200 04:40:43.983013 GP_NUM : 10
2201 04:40:43.983145 SRAM_EN : 1
2202 04:40:43.986371 MD32_EN : 0
2203 04:40:43.989557 ===================================
2204 04:40:43.993037 [ANA_INIT] >>>>>>>>>>>>>>
2205 04:40:43.993146 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 04:40:43.996689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 04:40:44.000571 ===================================
2208 04:40:44.003306 data_rate = 2400,PCW = 0X5b00
2209 04:40:44.006930 ===================================
2210 04:40:44.010025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 04:40:44.016924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 04:40:44.020195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 04:40:44.026615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 04:40:44.029975 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 04:40:44.033674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 04:40:44.033789 [ANA_INIT] flow start
2217 04:40:44.036946 [ANA_INIT] PLL >>>>>>>>
2218 04:40:44.040387 [ANA_INIT] PLL <<<<<<<<
2219 04:40:44.043670 [ANA_INIT] MIDPI >>>>>>>>
2220 04:40:44.043798 [ANA_INIT] MIDPI <<<<<<<<
2221 04:40:44.047037 [ANA_INIT] DLL >>>>>>>>
2222 04:40:44.050433 [ANA_INIT] DLL <<<<<<<<
2223 04:40:44.050550 [ANA_INIT] flow end
2224 04:40:44.054300 ============ LP4 DIFF to SE enter ============
2225 04:40:44.060791 ============ LP4 DIFF to SE exit ============
2226 04:40:44.060905 [ANA_INIT] <<<<<<<<<<<<<
2227 04:40:44.064135 [Flow] Enable top DCM control >>>>>
2228 04:40:44.067273 [Flow] Enable top DCM control <<<<<
2229 04:40:44.070789 Enable DLL master slave shuffle
2230 04:40:44.077558 ==============================================================
2231 04:40:44.077668 Gating Mode config
2232 04:40:44.084152 ==============================================================
2233 04:40:44.087210 Config description:
2234 04:40:44.094422 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 04:40:44.100868 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 04:40:44.107442 SELPH_MODE 0: By rank 1: By Phase
2237 04:40:44.111176 ==============================================================
2238 04:40:44.114199 GAT_TRACK_EN = 1
2239 04:40:44.117498 RX_GATING_MODE = 2
2240 04:40:44.121121 RX_GATING_TRACK_MODE = 2
2241 04:40:44.124293 SELPH_MODE = 1
2242 04:40:44.127737 PICG_EARLY_EN = 1
2243 04:40:44.131382 VALID_LAT_VALUE = 1
2244 04:40:44.134343 ==============================================================
2245 04:40:44.138157 Enter into Gating configuration >>>>
2246 04:40:44.140787 Exit from Gating configuration <<<<
2247 04:40:44.144284 Enter into DVFS_PRE_config >>>>>
2248 04:40:44.158012 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 04:40:44.161162 Exit from DVFS_PRE_config <<<<<
2250 04:40:44.164820 Enter into PICG configuration >>>>
2251 04:40:44.164928 Exit from PICG configuration <<<<
2252 04:40:44.167725 [RX_INPUT] configuration >>>>>
2253 04:40:44.171318 [RX_INPUT] configuration <<<<<
2254 04:40:44.177813 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 04:40:44.181442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 04:40:44.188427 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 04:40:44.194746 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 04:40:44.201493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 04:40:44.208093 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 04:40:44.211281 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 04:40:44.214877 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 04:40:44.217982 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 04:40:44.225096 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 04:40:44.228369 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 04:40:44.231679 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 04:40:44.235096 ===================================
2267 04:40:44.238598 LPDDR4 DRAM CONFIGURATION
2268 04:40:44.242483 ===================================
2269 04:40:44.242605 EX_ROW_EN[0] = 0x0
2270 04:40:44.245033 EX_ROW_EN[1] = 0x0
2271 04:40:44.245137 LP4Y_EN = 0x0
2272 04:40:44.249185 WORK_FSP = 0x0
2273 04:40:44.249306 WL = 0x4
2274 04:40:44.251875 RL = 0x4
2275 04:40:44.251985 BL = 0x2
2276 04:40:44.255714 RPST = 0x0
2277 04:40:44.255824 RD_PRE = 0x0
2278 04:40:44.258502 WR_PRE = 0x1
2279 04:40:44.258602 WR_PST = 0x0
2280 04:40:44.261853 DBI_WR = 0x0
2281 04:40:44.265307 DBI_RD = 0x0
2282 04:40:44.265414 OTF = 0x1
2283 04:40:44.268797 ===================================
2284 04:40:44.271995 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 04:40:44.275439 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 04:40:44.281935 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 04:40:44.285405 ===================================
2288 04:40:44.285522 LPDDR4 DRAM CONFIGURATION
2289 04:40:44.288684 ===================================
2290 04:40:44.292645 EX_ROW_EN[0] = 0x10
2291 04:40:44.295325 EX_ROW_EN[1] = 0x0
2292 04:40:44.295450 LP4Y_EN = 0x0
2293 04:40:44.298985 WORK_FSP = 0x0
2294 04:40:44.299105 WL = 0x4
2295 04:40:44.302603 RL = 0x4
2296 04:40:44.302716 BL = 0x2
2297 04:40:44.305570 RPST = 0x0
2298 04:40:44.305674 RD_PRE = 0x0
2299 04:40:44.308793 WR_PRE = 0x1
2300 04:40:44.308879 WR_PST = 0x0
2301 04:40:44.312329 DBI_WR = 0x0
2302 04:40:44.312435 DBI_RD = 0x0
2303 04:40:44.315936 OTF = 0x1
2304 04:40:44.318755 ===================================
2305 04:40:44.325708 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 04:40:44.325821 ==
2307 04:40:44.328894 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 04:40:44.332393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 04:40:44.332497 ==
2310 04:40:44.335905 [Duty_Offset_Calibration]
2311 04:40:44.336025 B0:3 B1:-1 CA:1
2312 04:40:44.336126
2313 04:40:44.339299 [DutyScan_Calibration_Flow] k_type=0
2314 04:40:44.348387
2315 04:40:44.348509 ==CLK 0==
2316 04:40:44.351542 Final CLK duty delay cell = -4
2317 04:40:44.355332 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2318 04:40:44.358158 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2319 04:40:44.361298 [-4] AVG Duty = 4953%(X100)
2320 04:40:44.361381
2321 04:40:44.364990 CH0 CLK Duty spec in!! Max-Min= 156%
2322 04:40:44.368421 [DutyScan_Calibration_Flow] ====Done====
2323 04:40:44.368530
2324 04:40:44.371328 [DutyScan_Calibration_Flow] k_type=1
2325 04:40:44.387080
2326 04:40:44.387186 ==DQS 0 ==
2327 04:40:44.390933 Final DQS duty delay cell = 0
2328 04:40:44.393978 [0] MAX Duty = 5125%(X100), DQS PI = 42
2329 04:40:44.397218 [0] MIN Duty = 5000%(X100), DQS PI = 14
2330 04:40:44.397320 [0] AVG Duty = 5062%(X100)
2331 04:40:44.400340
2332 04:40:44.400436 ==DQS 1 ==
2333 04:40:44.403936 Final DQS duty delay cell = -4
2334 04:40:44.407455 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2335 04:40:44.410472 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2336 04:40:44.414173 [-4] AVG Duty = 5062%(X100)
2337 04:40:44.414270
2338 04:40:44.417167 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2339 04:40:44.417269
2340 04:40:44.421024 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2341 04:40:44.423867 [DutyScan_Calibration_Flow] ====Done====
2342 04:40:44.423951
2343 04:40:44.427404 [DutyScan_Calibration_Flow] k_type=3
2344 04:40:44.443960
2345 04:40:44.444065 ==DQM 0 ==
2346 04:40:44.447158 Final DQM duty delay cell = 0
2347 04:40:44.450728 [0] MAX Duty = 5000%(X100), DQS PI = 46
2348 04:40:44.454303 [0] MIN Duty = 4906%(X100), DQS PI = 2
2349 04:40:44.454394 [0] AVG Duty = 4953%(X100)
2350 04:40:44.457088
2351 04:40:44.457159 ==DQM 1 ==
2352 04:40:44.460518 Final DQM duty delay cell = 0
2353 04:40:44.463713 [0] MAX Duty = 5124%(X100), DQS PI = 62
2354 04:40:44.467224 [0] MIN Duty = 5000%(X100), DQS PI = 8
2355 04:40:44.467311 [0] AVG Duty = 5062%(X100)
2356 04:40:44.470911
2357 04:40:44.474018 CH0 DQM 0 Duty spec in!! Max-Min= 94%
2358 04:40:44.474115
2359 04:40:44.477559 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2360 04:40:44.481096 [DutyScan_Calibration_Flow] ====Done====
2361 04:40:44.481196
2362 04:40:44.484086 [DutyScan_Calibration_Flow] k_type=2
2363 04:40:44.499821
2364 04:40:44.500017 ==DQ 0 ==
2365 04:40:44.503058 Final DQ duty delay cell = -4
2366 04:40:44.506072 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2367 04:40:44.509673 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2368 04:40:44.513152 [-4] AVG Duty = 4984%(X100)
2369 04:40:44.513243
2370 04:40:44.513308 ==DQ 1 ==
2371 04:40:44.516329 Final DQ duty delay cell = 0
2372 04:40:44.519817 [0] MAX Duty = 5031%(X100), DQS PI = 18
2373 04:40:44.523016 [0] MIN Duty = 4907%(X100), DQS PI = 46
2374 04:40:44.523101 [0] AVG Duty = 4969%(X100)
2375 04:40:44.523173
2376 04:40:44.526438 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2377 04:40:44.530332
2378 04:40:44.533105 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2379 04:40:44.536697 [DutyScan_Calibration_Flow] ====Done====
2380 04:40:44.536796 ==
2381 04:40:44.539662 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 04:40:44.543141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 04:40:44.543231 ==
2384 04:40:44.546429 [Duty_Offset_Calibration]
2385 04:40:44.546505 B0:1 B1:1 CA:2
2386 04:40:44.546568
2387 04:40:44.549743 [DutyScan_Calibration_Flow] k_type=0
2388 04:40:44.559945
2389 04:40:44.560040 ==CLK 0==
2390 04:40:44.562884 Final CLK duty delay cell = 0
2391 04:40:44.566735 [0] MAX Duty = 5156%(X100), DQS PI = 24
2392 04:40:44.569802 [0] MIN Duty = 4969%(X100), DQS PI = 40
2393 04:40:44.569882 [0] AVG Duty = 5062%(X100)
2394 04:40:44.573289
2395 04:40:44.573380 CH1 CLK Duty spec in!! Max-Min= 187%
2396 04:40:44.579941 [DutyScan_Calibration_Flow] ====Done====
2397 04:40:44.580028
2398 04:40:44.583377 [DutyScan_Calibration_Flow] k_type=1
2399 04:40:44.598858
2400 04:40:44.598941 ==DQS 0 ==
2401 04:40:44.602769 Final DQS duty delay cell = 0
2402 04:40:44.606060 [0] MAX Duty = 5031%(X100), DQS PI = 18
2403 04:40:44.609088 [0] MIN Duty = 4844%(X100), DQS PI = 48
2404 04:40:44.609166 [0] AVG Duty = 4937%(X100)
2405 04:40:44.612785
2406 04:40:44.612881 ==DQS 1 ==
2407 04:40:44.616203 Final DQS duty delay cell = 0
2408 04:40:44.619302 [0] MAX Duty = 5062%(X100), DQS PI = 36
2409 04:40:44.623071 [0] MIN Duty = 4938%(X100), DQS PI = 0
2410 04:40:44.623178 [0] AVG Duty = 5000%(X100)
2411 04:40:44.623281
2412 04:40:44.625950 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2413 04:40:44.629550
2414 04:40:44.632536 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2415 04:40:44.636065 [DutyScan_Calibration_Flow] ====Done====
2416 04:40:44.636141
2417 04:40:44.639637 [DutyScan_Calibration_Flow] k_type=3
2418 04:40:44.655346
2419 04:40:44.655461 ==DQM 0 ==
2420 04:40:44.659164 Final DQM duty delay cell = 0
2421 04:40:44.662483 [0] MAX Duty = 5093%(X100), DQS PI = 18
2422 04:40:44.665397 [0] MIN Duty = 4907%(X100), DQS PI = 48
2423 04:40:44.665477 [0] AVG Duty = 5000%(X100)
2424 04:40:44.669065
2425 04:40:44.669156 ==DQM 1 ==
2426 04:40:44.672249 Final DQM duty delay cell = 0
2427 04:40:44.675573 [0] MAX Duty = 5156%(X100), DQS PI = 62
2428 04:40:44.679305 [0] MIN Duty = 4938%(X100), DQS PI = 22
2429 04:40:44.679416 [0] AVG Duty = 5047%(X100)
2430 04:40:44.679513
2431 04:40:44.685774 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2432 04:40:44.685863
2433 04:40:44.689304 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2434 04:40:44.692360 [DutyScan_Calibration_Flow] ====Done====
2435 04:40:44.692437
2436 04:40:44.695827 [DutyScan_Calibration_Flow] k_type=2
2437 04:40:44.712101
2438 04:40:44.712199 ==DQ 0 ==
2439 04:40:44.715551 Final DQ duty delay cell = 0
2440 04:40:44.719216 [0] MAX Duty = 5124%(X100), DQS PI = 18
2441 04:40:44.722097 [0] MIN Duty = 4938%(X100), DQS PI = 50
2442 04:40:44.722178 [0] AVG Duty = 5031%(X100)
2443 04:40:44.722243
2444 04:40:44.725618 ==DQ 1 ==
2445 04:40:44.729262 Final DQ duty delay cell = 0
2446 04:40:44.732079 [0] MAX Duty = 5093%(X100), DQS PI = 8
2447 04:40:44.735569 [0] MIN Duty = 5031%(X100), DQS PI = 2
2448 04:40:44.735652 [0] AVG Duty = 5062%(X100)
2449 04:40:44.735725
2450 04:40:44.739191 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2451 04:40:44.739266
2452 04:40:44.742186 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2453 04:40:44.748766 [DutyScan_Calibration_Flow] ====Done====
2454 04:40:44.752489 nWR fixed to 30
2455 04:40:44.752576 [ModeRegInit_LP4] CH0 RK0
2456 04:40:44.755663 [ModeRegInit_LP4] CH0 RK1
2457 04:40:44.758726 [ModeRegInit_LP4] CH1 RK0
2458 04:40:44.758800 [ModeRegInit_LP4] CH1 RK1
2459 04:40:44.762293 match AC timing 7
2460 04:40:44.765553 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 04:40:44.769137 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 04:40:44.776115 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 04:40:44.779429 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 04:40:44.782835 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 04:40:44.785757 ==
2466 04:40:44.789267 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 04:40:44.792865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 04:40:44.792950 ==
2469 04:40:44.795925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 04:40:44.802742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 04:40:44.812169 [CA 0] Center 40 (10~71) winsize 62
2472 04:40:44.815866 [CA 1] Center 39 (9~70) winsize 62
2473 04:40:44.818616 [CA 2] Center 36 (6~67) winsize 62
2474 04:40:44.822297 [CA 3] Center 35 (5~66) winsize 62
2475 04:40:44.825790 [CA 4] Center 35 (5~65) winsize 61
2476 04:40:44.829032 [CA 5] Center 34 (4~65) winsize 62
2477 04:40:44.829116
2478 04:40:44.831952 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2479 04:40:44.832027
2480 04:40:44.835547 [CATrainingPosCal] consider 1 rank data
2481 04:40:44.838649 u2DelayCellTimex100 = 270/100 ps
2482 04:40:44.842121 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2483 04:40:44.845700 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2484 04:40:44.852242 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2485 04:40:44.855369 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2486 04:40:44.858732 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2487 04:40:44.862456 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2488 04:40:44.862531
2489 04:40:44.865536 CA PerBit enable=1, Macro0, CA PI delay=34
2490 04:40:44.865613
2491 04:40:44.869078 [CBTSetCACLKResult] CA Dly = 34
2492 04:40:44.869152 CS Dly: 7 (0~38)
2493 04:40:44.869214 ==
2494 04:40:44.872112 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 04:40:44.879187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 04:40:44.879286 ==
2497 04:40:44.882218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 04:40:44.889207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2499 04:40:44.897841 [CA 0] Center 39 (9~70) winsize 62
2500 04:40:44.901463 [CA 1] Center 40 (10~70) winsize 61
2501 04:40:44.904353 [CA 2] Center 36 (6~67) winsize 62
2502 04:40:44.908358 [CA 3] Center 36 (6~67) winsize 62
2503 04:40:44.911414 [CA 4] Center 34 (4~65) winsize 62
2504 04:40:44.914791 [CA 5] Center 34 (4~64) winsize 61
2505 04:40:44.914866
2506 04:40:44.918345 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 04:40:44.918422
2508 04:40:44.921582 [CATrainingPosCal] consider 2 rank data
2509 04:40:44.924683 u2DelayCellTimex100 = 270/100 ps
2510 04:40:44.928342 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2511 04:40:44.931370 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2512 04:40:44.938494 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2513 04:40:44.941348 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2514 04:40:44.945233 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2515 04:40:44.948280 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2516 04:40:44.948363
2517 04:40:44.951593 CA PerBit enable=1, Macro0, CA PI delay=34
2518 04:40:44.951703
2519 04:40:44.955161 [CBTSetCACLKResult] CA Dly = 34
2520 04:40:44.955245 CS Dly: 8 (0~41)
2521 04:40:44.955311
2522 04:40:44.958119 ----->DramcWriteLeveling(PI) begin...
2523 04:40:44.958216 ==
2524 04:40:44.961447 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 04:40:44.968596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 04:40:44.968716 ==
2527 04:40:44.971699 Write leveling (Byte 0): 31 => 31
2528 04:40:44.975276 Write leveling (Byte 1): 31 => 31
2529 04:40:44.975360 DramcWriteLeveling(PI) end<-----
2530 04:40:44.975425
2531 04:40:44.978534 ==
2532 04:40:44.981837 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 04:40:44.985229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 04:40:44.985312 ==
2535 04:40:44.988299 [Gating] SW mode calibration
2536 04:40:44.995260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 04:40:44.998804 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 04:40:45.005161 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 04:40:45.008895 0 15 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2540 04:40:45.011874 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2541 04:40:45.018420 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 04:40:45.022025 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 04:40:45.025540 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 04:40:45.031684 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 04:40:45.035039 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 04:40:45.038794 1 0 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
2547 04:40:45.045180 1 0 4 | B1->B0 | 2c2c 2424 | 0 0 | (0 1) (1 0)
2548 04:40:45.048818 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 04:40:45.052253 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 04:40:45.055154 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 04:40:45.062318 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 04:40:45.065205 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 04:40:45.068714 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 04:40:45.075408 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2555 04:40:45.078926 1 1 4 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
2556 04:40:45.082612 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 04:40:45.089086 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 04:40:45.092078 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 04:40:45.095829 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 04:40:45.102305 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 04:40:45.105874 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 04:40:45.109158 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2563 04:40:45.112441 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 04:40:45.119082 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 04:40:45.122705 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 04:40:45.125729 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 04:40:45.153815 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 04:40:45.153967 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 04:40:45.154061 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 04:40:45.154145 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 04:40:45.154224 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 04:40:45.154307 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 04:40:45.156349 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 04:40:45.163147 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 04:40:45.166577 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 04:40:45.169801 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 04:40:45.176493 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 04:40:45.179905 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2579 04:40:45.183013 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2580 04:40:45.186778 Total UI for P1: 0, mck2ui 16
2581 04:40:45.190023 best dqsien dly found for B0: ( 1, 3, 30)
2582 04:40:45.196645 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 04:40:45.197082 Total UI for P1: 0, mck2ui 16
2584 04:40:45.200165 best dqsien dly found for B1: ( 1, 4, 2)
2585 04:40:45.206638 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2586 04:40:45.210457 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2587 04:40:45.210967
2588 04:40:45.213891 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2589 04:40:45.216964 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2590 04:40:45.220269 [Gating] SW calibration Done
2591 04:40:45.220820 ==
2592 04:40:45.223809 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 04:40:45.227179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 04:40:45.227910 ==
2595 04:40:45.228543 RX Vref Scan: 0
2596 04:40:45.230151
2597 04:40:45.230833 RX Vref 0 -> 0, step: 1
2598 04:40:45.231460
2599 04:40:45.234000 RX Delay -40 -> 252, step: 8
2600 04:40:45.236933 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2601 04:40:45.240335 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2602 04:40:45.246822 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2603 04:40:45.250247 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2604 04:40:45.253900 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2605 04:40:45.256953 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2606 04:40:45.260655 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2607 04:40:45.266990 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2608 04:40:45.270317 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2609 04:40:45.273994 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2610 04:40:45.277182 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2611 04:40:45.280509 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2612 04:40:45.283801 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2613 04:40:45.290254 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2614 04:40:45.293615 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2615 04:40:45.297267 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2616 04:40:45.297416 ==
2617 04:40:45.300631 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 04:40:45.303687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 04:40:45.303785 ==
2620 04:40:45.307404 DQS Delay:
2621 04:40:45.307567 DQS0 = 0, DQS1 = 0
2622 04:40:45.310255 DQM Delay:
2623 04:40:45.310344 DQM0 = 116, DQM1 = 107
2624 04:40:45.310432 DQ Delay:
2625 04:40:45.313859 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2626 04:40:45.317150 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2627 04:40:45.320449 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2628 04:40:45.327313 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2629 04:40:45.327401
2630 04:40:45.327468
2631 04:40:45.327530 ==
2632 04:40:45.330588 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 04:40:45.334159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 04:40:45.334244 ==
2635 04:40:45.334309
2636 04:40:45.334370
2637 04:40:45.337544 TX Vref Scan disable
2638 04:40:45.337635 == TX Byte 0 ==
2639 04:40:45.344105 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2640 04:40:45.347839 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2641 04:40:45.347977 == TX Byte 1 ==
2642 04:40:45.354378 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2643 04:40:45.357829 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2644 04:40:45.357957 ==
2645 04:40:45.361108 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 04:40:45.364067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 04:40:45.364209 ==
2648 04:40:45.376994 TX Vref=22, minBit 1, minWin=25, winSum=414
2649 04:40:45.379996 TX Vref=24, minBit 7, minWin=25, winSum=422
2650 04:40:45.383427 TX Vref=26, minBit 1, minWin=25, winSum=423
2651 04:40:45.387340 TX Vref=28, minBit 3, minWin=26, winSum=427
2652 04:40:45.390412 TX Vref=30, minBit 4, minWin=26, winSum=431
2653 04:40:45.393644 TX Vref=32, minBit 1, minWin=26, winSum=429
2654 04:40:45.400565 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 30
2655 04:40:45.401048
2656 04:40:45.404148 Final TX Range 1 Vref 30
2657 04:40:45.404570
2658 04:40:45.404983 ==
2659 04:40:45.407103 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 04:40:45.410771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 04:40:45.411359 ==
2662 04:40:45.411867
2663 04:40:45.412296
2664 04:40:45.413948 TX Vref Scan disable
2665 04:40:45.417305 == TX Byte 0 ==
2666 04:40:45.420914 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2667 04:40:45.424281 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2668 04:40:45.427593 == TX Byte 1 ==
2669 04:40:45.431238 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2670 04:40:45.434709 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2671 04:40:45.435478
2672 04:40:45.436013 [DATLAT]
2673 04:40:45.437583 Freq=1200, CH0 RK0
2674 04:40:45.438101
2675 04:40:45.441396 DATLAT Default: 0xd
2676 04:40:45.441971 0, 0xFFFF, sum = 0
2677 04:40:45.444467 1, 0xFFFF, sum = 0
2678 04:40:45.445254 2, 0xFFFF, sum = 0
2679 04:40:45.447873 3, 0xFFFF, sum = 0
2680 04:40:45.448422 4, 0xFFFF, sum = 0
2681 04:40:45.451093 5, 0xFFFF, sum = 0
2682 04:40:45.451832 6, 0xFFFF, sum = 0
2683 04:40:45.454275 7, 0xFFFF, sum = 0
2684 04:40:45.454870 8, 0xFFFF, sum = 0
2685 04:40:45.457358 9, 0xFFFF, sum = 0
2686 04:40:45.457945 10, 0xFFFF, sum = 0
2687 04:40:45.461005 11, 0xFFFF, sum = 0
2688 04:40:45.461598 12, 0x0, sum = 1
2689 04:40:45.464601 13, 0x0, sum = 2
2690 04:40:45.465473 14, 0x0, sum = 3
2691 04:40:45.467861 15, 0x0, sum = 4
2692 04:40:45.468435 best_step = 13
2693 04:40:45.469233
2694 04:40:45.469837 ==
2695 04:40:45.471739 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 04:40:45.474193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 04:40:45.477647 ==
2698 04:40:45.478035 RX Vref Scan: 1
2699 04:40:45.478503
2700 04:40:45.481248 Set Vref Range= 32 -> 127
2701 04:40:45.481603
2702 04:40:45.484469 RX Vref 32 -> 127, step: 1
2703 04:40:45.484877
2704 04:40:45.485116 RX Delay -21 -> 252, step: 4
2705 04:40:45.485359
2706 04:40:45.487689 Set Vref, RX VrefLevel [Byte0]: 32
2707 04:40:45.490975 [Byte1]: 32
2708 04:40:45.495111
2709 04:40:45.495524 Set Vref, RX VrefLevel [Byte0]: 33
2710 04:40:45.498681 [Byte1]: 33
2711 04:40:45.502963
2712 04:40:45.503390 Set Vref, RX VrefLevel [Byte0]: 34
2713 04:40:45.506364 [Byte1]: 34
2714 04:40:45.511124
2715 04:40:45.511430 Set Vref, RX VrefLevel [Byte0]: 35
2716 04:40:45.514129 [Byte1]: 35
2717 04:40:45.518735
2718 04:40:45.519069 Set Vref, RX VrefLevel [Byte0]: 36
2719 04:40:45.522332 [Byte1]: 36
2720 04:40:45.527052
2721 04:40:45.527384 Set Vref, RX VrefLevel [Byte0]: 37
2722 04:40:45.530126 [Byte1]: 37
2723 04:40:45.534481
2724 04:40:45.534815 Set Vref, RX VrefLevel [Byte0]: 38
2725 04:40:45.538089 [Byte1]: 38
2726 04:40:45.542864
2727 04:40:45.543222 Set Vref, RX VrefLevel [Byte0]: 39
2728 04:40:45.545785 [Byte1]: 39
2729 04:40:45.550425
2730 04:40:45.553679 Set Vref, RX VrefLevel [Byte0]: 40
2731 04:40:45.556824 [Byte1]: 40
2732 04:40:45.557148
2733 04:40:45.560451 Set Vref, RX VrefLevel [Byte0]: 41
2734 04:40:45.563652 [Byte1]: 41
2735 04:40:45.563938
2736 04:40:45.567091 Set Vref, RX VrefLevel [Byte0]: 42
2737 04:40:45.570496 [Byte1]: 42
2738 04:40:45.574355
2739 04:40:45.574679 Set Vref, RX VrefLevel [Byte0]: 43
2740 04:40:45.577544 [Byte1]: 43
2741 04:40:45.582457
2742 04:40:45.582871 Set Vref, RX VrefLevel [Byte0]: 44
2743 04:40:45.585466 [Byte1]: 44
2744 04:40:45.590411
2745 04:40:45.590863 Set Vref, RX VrefLevel [Byte0]: 45
2746 04:40:45.593287 [Byte1]: 45
2747 04:40:45.598017
2748 04:40:45.598329 Set Vref, RX VrefLevel [Byte0]: 46
2749 04:40:45.601482 [Byte1]: 46
2750 04:40:45.605745
2751 04:40:45.606069 Set Vref, RX VrefLevel [Byte0]: 47
2752 04:40:45.609313 [Byte1]: 47
2753 04:40:45.614077
2754 04:40:45.614393 Set Vref, RX VrefLevel [Byte0]: 48
2755 04:40:45.617071 [Byte1]: 48
2756 04:40:45.621799
2757 04:40:45.622245 Set Vref, RX VrefLevel [Byte0]: 49
2758 04:40:45.625421 [Byte1]: 49
2759 04:40:45.629777
2760 04:40:45.630114 Set Vref, RX VrefLevel [Byte0]: 50
2761 04:40:45.633347 [Byte1]: 50
2762 04:40:45.637503
2763 04:40:45.637893 Set Vref, RX VrefLevel [Byte0]: 51
2764 04:40:45.640892 [Byte1]: 51
2765 04:40:45.645665
2766 04:40:45.646000 Set Vref, RX VrefLevel [Byte0]: 52
2767 04:40:45.649283 [Byte1]: 52
2768 04:40:45.653472
2769 04:40:45.653774 Set Vref, RX VrefLevel [Byte0]: 53
2770 04:40:45.656884 [Byte1]: 53
2771 04:40:45.661540
2772 04:40:45.661846 Set Vref, RX VrefLevel [Byte0]: 54
2773 04:40:45.664559 [Byte1]: 54
2774 04:40:45.669686
2775 04:40:45.669987 Set Vref, RX VrefLevel [Byte0]: 55
2776 04:40:45.672630 [Byte1]: 55
2777 04:40:45.677459
2778 04:40:45.677830 Set Vref, RX VrefLevel [Byte0]: 56
2779 04:40:45.680722 [Byte1]: 56
2780 04:40:45.685209
2781 04:40:45.685599 Set Vref, RX VrefLevel [Byte0]: 57
2782 04:40:45.688721 [Byte1]: 57
2783 04:40:45.693202
2784 04:40:45.693505 Set Vref, RX VrefLevel [Byte0]: 58
2785 04:40:45.696843 [Byte1]: 58
2786 04:40:45.701243
2787 04:40:45.701606 Set Vref, RX VrefLevel [Byte0]: 59
2788 04:40:45.704458 [Byte1]: 59
2789 04:40:45.709336
2790 04:40:45.709640 Set Vref, RX VrefLevel [Byte0]: 60
2791 04:40:45.712502 [Byte1]: 60
2792 04:40:45.717045
2793 04:40:45.717348 Set Vref, RX VrefLevel [Byte0]: 61
2794 04:40:45.720550 [Byte1]: 61
2795 04:40:45.724969
2796 04:40:45.725297 Set Vref, RX VrefLevel [Byte0]: 62
2797 04:40:45.728541 [Byte1]: 62
2798 04:40:45.732838
2799 04:40:45.733163 Set Vref, RX VrefLevel [Byte0]: 63
2800 04:40:45.736426 [Byte1]: 63
2801 04:40:45.740421
2802 04:40:45.740884 Set Vref, RX VrefLevel [Byte0]: 64
2803 04:40:45.744040 [Byte1]: 64
2804 04:40:45.748541
2805 04:40:45.748948 Set Vref, RX VrefLevel [Byte0]: 65
2806 04:40:45.751885 [Byte1]: 65
2807 04:40:45.756321
2808 04:40:45.756685 Set Vref, RX VrefLevel [Byte0]: 66
2809 04:40:45.759761 [Byte1]: 66
2810 04:40:45.764432
2811 04:40:45.764895 Set Vref, RX VrefLevel [Byte0]: 67
2812 04:40:45.767850 [Byte1]: 67
2813 04:40:45.772330
2814 04:40:45.772775 Set Vref, RX VrefLevel [Byte0]: 68
2815 04:40:45.775901 [Byte1]: 68
2816 04:40:45.780698
2817 04:40:45.781037 Set Vref, RX VrefLevel [Byte0]: 69
2818 04:40:45.783721 [Byte1]: 69
2819 04:40:45.788526
2820 04:40:45.788893 Final RX Vref Byte 0 = 53 to rank0
2821 04:40:45.791730 Final RX Vref Byte 1 = 51 to rank0
2822 04:40:45.794918 Final RX Vref Byte 0 = 53 to rank1
2823 04:40:45.798811 Final RX Vref Byte 1 = 51 to rank1==
2824 04:40:45.802331 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 04:40:45.805014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 04:40:45.808977 ==
2827 04:40:45.809282 DQS Delay:
2828 04:40:45.809534 DQS0 = 0, DQS1 = 0
2829 04:40:45.811709 DQM Delay:
2830 04:40:45.812011 DQM0 = 115, DQM1 = 104
2831 04:40:45.815088 DQ Delay:
2832 04:40:45.818919 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2833 04:40:45.821817 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2834 04:40:45.825510 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2835 04:40:45.829269 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2836 04:40:45.829764
2837 04:40:45.830104
2838 04:40:45.835067 [DQSOSCAuto] RK0, (LSB)MR18= 0xffef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2839 04:40:45.838735 CH0 RK0: MR19=303, MR18=FFEF
2840 04:40:45.845468 CH0_RK0: MR19=0x303, MR18=0xFFEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2841 04:40:45.845777
2842 04:40:45.849070 ----->DramcWriteLeveling(PI) begin...
2843 04:40:45.849473 ==
2844 04:40:45.852080 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 04:40:45.855935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 04:40:45.856243 ==
2847 04:40:45.858721 Write leveling (Byte 0): 30 => 30
2848 04:40:45.862398 Write leveling (Byte 1): 28 => 28
2849 04:40:45.865522 DramcWriteLeveling(PI) end<-----
2850 04:40:45.865825
2851 04:40:45.866063 ==
2852 04:40:45.868873 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 04:40:45.872400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 04:40:45.872831 ==
2855 04:40:45.875948 [Gating] SW mode calibration
2856 04:40:45.882441 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 04:40:45.889212 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 04:40:45.892591 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2859 04:40:45.895940 0 15 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2860 04:40:45.902501 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 04:40:45.906033 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 04:40:45.909338 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 04:40:45.915926 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 04:40:45.919484 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2865 04:40:45.922973 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 1)
2866 04:40:45.929380 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2867 04:40:45.932363 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 04:40:45.935832 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 04:40:45.942582 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 04:40:45.946377 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 04:40:45.949427 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 04:40:45.955913 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2873 04:40:45.959140 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2874 04:40:45.962665 1 1 0 | B1->B0 | 2c2b 3e3e | 1 0 | (0 0) (0 0)
2875 04:40:45.966325 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2876 04:40:45.973044 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 04:40:45.976075 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 04:40:45.979621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 04:40:45.986475 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 04:40:45.989677 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2881 04:40:45.992672 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 04:40:45.999513 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2883 04:40:46.002859 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 04:40:46.006219 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 04:40:46.012824 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 04:40:46.016776 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 04:40:46.019786 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 04:40:46.023150 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 04:40:46.030016 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 04:40:46.032920 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 04:40:46.036431 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 04:40:46.043148 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 04:40:46.046507 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 04:40:46.050390 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 04:40:46.056831 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 04:40:46.059857 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 04:40:46.063207 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 04:40:46.070327 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2899 04:40:46.070444 Total UI for P1: 0, mck2ui 16
2900 04:40:46.073430 best dqsien dly found for B0: ( 1, 3, 26)
2901 04:40:46.080164 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2902 04:40:46.083511 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 04:40:46.087164 Total UI for P1: 0, mck2ui 16
2904 04:40:46.090189 best dqsien dly found for B1: ( 1, 4, 2)
2905 04:40:46.093344 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2906 04:40:46.097014 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2907 04:40:46.097134
2908 04:40:46.100175 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2909 04:40:46.103646 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2910 04:40:46.107286 [Gating] SW calibration Done
2911 04:40:46.107397 ==
2912 04:40:46.110224 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 04:40:46.113733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 04:40:46.117405 ==
2915 04:40:46.117514 RX Vref Scan: 0
2916 04:40:46.117620
2917 04:40:46.120925 RX Vref 0 -> 0, step: 1
2918 04:40:46.121043
2919 04:40:46.121146 RX Delay -40 -> 252, step: 8
2920 04:40:46.127479 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2921 04:40:46.131126 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2922 04:40:46.134036 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2923 04:40:46.137653 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2924 04:40:46.140510 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2925 04:40:46.147584 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2926 04:40:46.150660 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2927 04:40:46.154427 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2928 04:40:46.157439 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2929 04:40:46.161313 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2930 04:40:46.164719 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2931 04:40:46.171051 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2932 04:40:46.174524 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2933 04:40:46.177558 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2934 04:40:46.181129 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2935 04:40:46.184214 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2936 04:40:46.187707 ==
2937 04:40:46.191102 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 04:40:46.194793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 04:40:46.194911 ==
2940 04:40:46.195008 DQS Delay:
2941 04:40:46.198197 DQS0 = 0, DQS1 = 0
2942 04:40:46.198311 DQM Delay:
2943 04:40:46.201434 DQM0 = 115, DQM1 = 106
2944 04:40:46.201555 DQ Delay:
2945 04:40:46.204448 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2946 04:40:46.208108 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2947 04:40:46.211108 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2948 04:40:46.214613 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2949 04:40:46.214725
2950 04:40:46.214827
2951 04:40:46.214925 ==
2952 04:40:46.218479 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 04:40:46.221301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 04:40:46.224647 ==
2955 04:40:46.224768
2956 04:40:46.224863
2957 04:40:46.224955 TX Vref Scan disable
2958 04:40:46.227979 == TX Byte 0 ==
2959 04:40:46.231256 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2960 04:40:46.234645 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2961 04:40:46.238306 == TX Byte 1 ==
2962 04:40:46.241528 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2963 04:40:46.244831 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2964 04:40:46.244958 ==
2965 04:40:46.248265 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 04:40:46.254638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 04:40:46.254759 ==
2968 04:40:46.265878 TX Vref=22, minBit 1, minWin=25, winSum=424
2969 04:40:46.269482 TX Vref=24, minBit 3, minWin=26, winSum=432
2970 04:40:46.272281 TX Vref=26, minBit 2, minWin=26, winSum=436
2971 04:40:46.275647 TX Vref=28, minBit 0, minWin=27, winSum=440
2972 04:40:46.279190 TX Vref=30, minBit 12, minWin=26, winSum=438
2973 04:40:46.285752 TX Vref=32, minBit 0, minWin=27, winSum=438
2974 04:40:46.288841 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 28
2975 04:40:46.288946
2976 04:40:46.292378 Final TX Range 1 Vref 28
2977 04:40:46.292483
2978 04:40:46.292579 ==
2979 04:40:46.295399 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 04:40:46.299333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 04:40:46.299439 ==
2982 04:40:46.299542
2983 04:40:46.302552
2984 04:40:46.302657 TX Vref Scan disable
2985 04:40:46.305482 == TX Byte 0 ==
2986 04:40:46.309276 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2987 04:40:46.312442 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2988 04:40:46.315867 == TX Byte 1 ==
2989 04:40:46.318889 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2990 04:40:46.322544 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2991 04:40:46.322652
2992 04:40:46.326008 [DATLAT]
2993 04:40:46.326117 Freq=1200, CH0 RK1
2994 04:40:46.326215
2995 04:40:46.329096 DATLAT Default: 0xd
2996 04:40:46.329215 0, 0xFFFF, sum = 0
2997 04:40:46.332492 1, 0xFFFF, sum = 0
2998 04:40:46.332608 2, 0xFFFF, sum = 0
2999 04:40:46.336298 3, 0xFFFF, sum = 0
3000 04:40:46.336408 4, 0xFFFF, sum = 0
3001 04:40:46.339695 5, 0xFFFF, sum = 0
3002 04:40:46.339810 6, 0xFFFF, sum = 0
3003 04:40:46.342518 7, 0xFFFF, sum = 0
3004 04:40:46.342629 8, 0xFFFF, sum = 0
3005 04:40:46.346088 9, 0xFFFF, sum = 0
3006 04:40:46.346193 10, 0xFFFF, sum = 0
3007 04:40:46.349388 11, 0xFFFF, sum = 0
3008 04:40:46.349497 12, 0x0, sum = 1
3009 04:40:46.352672 13, 0x0, sum = 2
3010 04:40:46.352779 14, 0x0, sum = 3
3011 04:40:46.355862 15, 0x0, sum = 4
3012 04:40:46.355976 best_step = 13
3013 04:40:46.356089
3014 04:40:46.356183 ==
3015 04:40:46.359441 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 04:40:46.366327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 04:40:46.366438 ==
3018 04:40:46.366546 RX Vref Scan: 0
3019 04:40:46.366643
3020 04:40:46.369735 RX Vref 0 -> 0, step: 1
3021 04:40:46.369854
3022 04:40:46.372782 RX Delay -21 -> 252, step: 4
3023 04:40:46.376337 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3024 04:40:46.379204 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3025 04:40:46.386167 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3026 04:40:46.389839 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3027 04:40:46.392804 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3028 04:40:46.395937 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3029 04:40:46.399451 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3030 04:40:46.402988 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3031 04:40:46.409664 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3032 04:40:46.413145 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3033 04:40:46.416093 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3034 04:40:46.419837 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3035 04:40:46.422761 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3036 04:40:46.429880 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3037 04:40:46.433393 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3038 04:40:46.436526 iDelay=195, Bit 15, Center 112 (43 ~ 182) 140
3039 04:40:46.436647 ==
3040 04:40:46.439810 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 04:40:46.443148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 04:40:46.443276 ==
3043 04:40:46.446341 DQS Delay:
3044 04:40:46.446446 DQS0 = 0, DQS1 = 0
3045 04:40:46.449845 DQM Delay:
3046 04:40:46.449954 DQM0 = 114, DQM1 = 104
3047 04:40:46.450047 DQ Delay:
3048 04:40:46.453466 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3049 04:40:46.456742 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3050 04:40:46.459980 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3051 04:40:46.466346 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =112
3052 04:40:46.466469
3053 04:40:46.466571
3054 04:40:46.473149 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3055 04:40:46.476645 CH0 RK1: MR19=403, MR18=2F4
3056 04:40:46.483138 CH0_RK1: MR19=0x403, MR18=0x2F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3057 04:40:46.486818 [RxdqsGatingPostProcess] freq 1200
3058 04:40:46.490321 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 04:40:46.493467 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 04:40:46.497032 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 04:40:46.500014 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 04:40:46.503690 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 04:40:46.506776 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 04:40:46.510297 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 04:40:46.514333 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 04:40:46.517392 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 04:40:46.520409 Pre-setting of DQS Precalculation
3068 04:40:46.523542 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 04:40:46.523628 ==
3070 04:40:46.526707 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 04:40:46.530573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 04:40:46.530667 ==
3073 04:40:46.537394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 04:40:46.543777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3075 04:40:46.551434 [CA 0] Center 38 (9~68) winsize 60
3076 04:40:46.554892 [CA 1] Center 38 (8~68) winsize 61
3077 04:40:46.557864 [CA 2] Center 35 (5~65) winsize 61
3078 04:40:46.561754 [CA 3] Center 34 (4~65) winsize 62
3079 04:40:46.564532 [CA 4] Center 34 (4~65) winsize 62
3080 04:40:46.568422 [CA 5] Center 34 (4~64) winsize 61
3081 04:40:46.568538
3082 04:40:46.571367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 04:40:46.571465
3084 04:40:46.574537 [CATrainingPosCal] consider 1 rank data
3085 04:40:46.577844 u2DelayCellTimex100 = 270/100 ps
3086 04:40:46.581238 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3087 04:40:46.584754 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3088 04:40:46.588284 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3089 04:40:46.594821 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3090 04:40:46.598638 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3091 04:40:46.601348 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3092 04:40:46.601437
3093 04:40:46.604961 CA PerBit enable=1, Macro0, CA PI delay=34
3094 04:40:46.605059
3095 04:40:46.608137 [CBTSetCACLKResult] CA Dly = 34
3096 04:40:46.608233 CS Dly: 6 (0~37)
3097 04:40:46.608323 ==
3098 04:40:46.611642 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 04:40:46.618305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 04:40:46.618419 ==
3101 04:40:46.622334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 04:40:46.628416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 04:40:46.636688 [CA 0] Center 38 (8~68) winsize 61
3104 04:40:46.640211 [CA 1] Center 38 (8~68) winsize 61
3105 04:40:46.643503 [CA 2] Center 34 (4~65) winsize 62
3106 04:40:46.646967 [CA 3] Center 34 (4~65) winsize 62
3107 04:40:46.650458 [CA 4] Center 34 (4~65) winsize 62
3108 04:40:46.653961 [CA 5] Center 33 (3~63) winsize 61
3109 04:40:46.654069
3110 04:40:46.657268 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 04:40:46.657381
3112 04:40:46.660199 [CATrainingPosCal] consider 2 rank data
3113 04:40:46.663727 u2DelayCellTimex100 = 270/100 ps
3114 04:40:46.667308 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3115 04:40:46.670515 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 04:40:46.674177 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3117 04:40:46.681001 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3118 04:40:46.683565 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3119 04:40:46.686982 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3120 04:40:46.687090
3121 04:40:46.690292 CA PerBit enable=1, Macro0, CA PI delay=33
3122 04:40:46.690398
3123 04:40:46.693520 [CBTSetCACLKResult] CA Dly = 33
3124 04:40:46.693622 CS Dly: 7 (0~40)
3125 04:40:46.693720
3126 04:40:46.697414 ----->DramcWriteLeveling(PI) begin...
3127 04:40:46.697525 ==
3128 04:40:46.700780 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 04:40:46.707285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 04:40:46.707396 ==
3131 04:40:46.710340 Write leveling (Byte 0): 26 => 26
3132 04:40:46.713972 Write leveling (Byte 1): 29 => 29
3133 04:40:46.714078 DramcWriteLeveling(PI) end<-----
3134 04:40:46.714182
3135 04:40:46.717455 ==
3136 04:40:46.720566 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 04:40:46.724022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 04:40:46.724135 ==
3139 04:40:46.727146 [Gating] SW mode calibration
3140 04:40:46.734197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 04:40:46.737201 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 04:40:46.744133 0 15 0 | B1->B0 | 2a2a 2525 | 1 0 | (1 1) (0 0)
3143 04:40:46.747633 0 15 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3144 04:40:46.750834 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 04:40:46.757599 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 04:40:46.761009 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 04:40:46.764256 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3148 04:40:46.767752 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3149 04:40:46.774468 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 04:40:46.777477 1 0 0 | B1->B0 | 2323 2929 | 0 0 | (1 0) (1 0)
3151 04:40:46.781053 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 04:40:46.787660 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 04:40:46.791120 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3154 04:40:46.794279 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 04:40:46.801494 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 04:40:46.804219 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 04:40:46.807552 1 0 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3158 04:40:46.814734 1 1 0 | B1->B0 | 4242 3737 | 1 1 | (0 0) (0 0)
3159 04:40:46.817694 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 04:40:46.821324 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 04:40:46.828051 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 04:40:46.831129 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 04:40:46.834766 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 04:40:46.838063 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 04:40:46.845099 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 04:40:46.848330 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3167 04:40:46.851359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 04:40:46.858277 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 04:40:46.861308 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 04:40:46.865148 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 04:40:46.871917 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 04:40:46.874590 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 04:40:46.878221 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 04:40:46.884933 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 04:40:46.888302 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 04:40:46.891656 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 04:40:46.895116 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 04:40:46.901712 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 04:40:46.905322 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 04:40:46.908210 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 04:40:46.914967 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3182 04:40:46.918375 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 04:40:46.922169 Total UI for P1: 0, mck2ui 16
3184 04:40:46.925300 best dqsien dly found for B0: ( 1, 3, 28)
3185 04:40:46.928626 Total UI for P1: 0, mck2ui 16
3186 04:40:46.932663 best dqsien dly found for B1: ( 1, 3, 30)
3187 04:40:46.935137 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3188 04:40:46.938836 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3189 04:40:46.938914
3190 04:40:46.942452 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3191 04:40:46.945304 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3192 04:40:46.948650 [Gating] SW calibration Done
3193 04:40:46.948747 ==
3194 04:40:46.951908 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 04:40:46.955403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 04:40:46.955480 ==
3197 04:40:46.959193 RX Vref Scan: 0
3198 04:40:46.959298
3199 04:40:46.962472 RX Vref 0 -> 0, step: 1
3200 04:40:46.962549
3201 04:40:46.962612 RX Delay -40 -> 252, step: 8
3202 04:40:46.968704 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3203 04:40:46.972155 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3204 04:40:46.975609 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3205 04:40:46.978983 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3206 04:40:46.982187 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3207 04:40:46.985837 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3208 04:40:46.992381 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3209 04:40:46.995735 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3210 04:40:46.998953 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3211 04:40:47.002292 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3212 04:40:47.005839 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3213 04:40:47.012395 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3214 04:40:47.015743 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3215 04:40:47.019330 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3216 04:40:47.022672 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3217 04:40:47.025937 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3218 04:40:47.029763 ==
3219 04:40:47.029845 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 04:40:47.035872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 04:40:47.035950 ==
3222 04:40:47.036012 DQS Delay:
3223 04:40:47.039310 DQS0 = 0, DQS1 = 0
3224 04:40:47.039406 DQM Delay:
3225 04:40:47.043199 DQM0 = 116, DQM1 = 109
3226 04:40:47.043270 DQ Delay:
3227 04:40:47.045970 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3228 04:40:47.049805 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3229 04:40:47.052645 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3230 04:40:47.056231 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =111
3231 04:40:47.056338
3232 04:40:47.056430
3233 04:40:47.056517 ==
3234 04:40:47.059415 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 04:40:47.062645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 04:40:47.066173 ==
3237 04:40:47.066255
3238 04:40:47.066318
3239 04:40:47.066376 TX Vref Scan disable
3240 04:40:47.069498 == TX Byte 0 ==
3241 04:40:47.073178 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3242 04:40:47.076530 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3243 04:40:47.079936 == TX Byte 1 ==
3244 04:40:47.083087 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3245 04:40:47.086545 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3246 04:40:47.086645 ==
3247 04:40:47.089830 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 04:40:47.096248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 04:40:47.096355 ==
3250 04:40:47.107426 TX Vref=22, minBit 1, minWin=25, winSum=413
3251 04:40:47.110430 TX Vref=24, minBit 10, minWin=25, winSum=417
3252 04:40:47.114070 TX Vref=26, minBit 0, minWin=26, winSum=424
3253 04:40:47.117371 TX Vref=28, minBit 15, minWin=25, winSum=428
3254 04:40:47.120582 TX Vref=30, minBit 15, minWin=25, winSum=428
3255 04:40:47.123729 TX Vref=32, minBit 2, minWin=26, winSum=427
3256 04:40:47.130358 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 32
3257 04:40:47.130441
3258 04:40:47.134091 Final TX Range 1 Vref 32
3259 04:40:47.134192
3260 04:40:47.134281 ==
3261 04:40:47.137075 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 04:40:47.140795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 04:40:47.140868 ==
3264 04:40:47.140976
3265 04:40:47.141048
3266 04:40:47.144252 TX Vref Scan disable
3267 04:40:47.147358 == TX Byte 0 ==
3268 04:40:47.150803 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3269 04:40:47.153888 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3270 04:40:47.157546 == TX Byte 1 ==
3271 04:40:47.160523 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3272 04:40:47.164395 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3273 04:40:47.164498
3274 04:40:47.167279 [DATLAT]
3275 04:40:47.167389 Freq=1200, CH1 RK0
3276 04:40:47.167484
3277 04:40:47.170574 DATLAT Default: 0xd
3278 04:40:47.170656 0, 0xFFFF, sum = 0
3279 04:40:47.174053 1, 0xFFFF, sum = 0
3280 04:40:47.174160 2, 0xFFFF, sum = 0
3281 04:40:47.177452 3, 0xFFFF, sum = 0
3282 04:40:47.177527 4, 0xFFFF, sum = 0
3283 04:40:47.181026 5, 0xFFFF, sum = 0
3284 04:40:47.181104 6, 0xFFFF, sum = 0
3285 04:40:47.184471 7, 0xFFFF, sum = 0
3286 04:40:47.184573 8, 0xFFFF, sum = 0
3287 04:40:47.187433 9, 0xFFFF, sum = 0
3288 04:40:47.187515 10, 0xFFFF, sum = 0
3289 04:40:47.190702 11, 0xFFFF, sum = 0
3290 04:40:47.190802 12, 0x0, sum = 1
3291 04:40:47.194332 13, 0x0, sum = 2
3292 04:40:47.194433 14, 0x0, sum = 3
3293 04:40:47.197742 15, 0x0, sum = 4
3294 04:40:47.197851 best_step = 13
3295 04:40:47.197942
3296 04:40:47.198035 ==
3297 04:40:47.200756 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 04:40:47.207807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 04:40:47.207931 ==
3300 04:40:47.208027 RX Vref Scan: 1
3301 04:40:47.208118
3302 04:40:47.211481 Set Vref Range= 32 -> 127
3303 04:40:47.211582
3304 04:40:47.214586 RX Vref 32 -> 127, step: 1
3305 04:40:47.214669
3306 04:40:47.214733 RX Delay -21 -> 252, step: 4
3307 04:40:47.214793
3308 04:40:47.217961 Set Vref, RX VrefLevel [Byte0]: 32
3309 04:40:47.221009 [Byte1]: 32
3310 04:40:47.225769
3311 04:40:47.225851 Set Vref, RX VrefLevel [Byte0]: 33
3312 04:40:47.228906 [Byte1]: 33
3313 04:40:47.234033
3314 04:40:47.234116 Set Vref, RX VrefLevel [Byte0]: 34
3315 04:40:47.237072 [Byte1]: 34
3316 04:40:47.241701
3317 04:40:47.241783 Set Vref, RX VrefLevel [Byte0]: 35
3318 04:40:47.244497 [Byte1]: 35
3319 04:40:47.249479
3320 04:40:47.249560 Set Vref, RX VrefLevel [Byte0]: 36
3321 04:40:47.252414 [Byte1]: 36
3322 04:40:47.257118
3323 04:40:47.257208 Set Vref, RX VrefLevel [Byte0]: 37
3324 04:40:47.260791 [Byte1]: 37
3325 04:40:47.264944
3326 04:40:47.265050 Set Vref, RX VrefLevel [Byte0]: 38
3327 04:40:47.268518 [Byte1]: 38
3328 04:40:47.273286
3329 04:40:47.273369 Set Vref, RX VrefLevel [Byte0]: 39
3330 04:40:47.276582 [Byte1]: 39
3331 04:40:47.280733
3332 04:40:47.280808 Set Vref, RX VrefLevel [Byte0]: 40
3333 04:40:47.284350 [Byte1]: 40
3334 04:40:47.288662
3335 04:40:47.288772 Set Vref, RX VrefLevel [Byte0]: 41
3336 04:40:47.292445 [Byte1]: 41
3337 04:40:47.296972
3338 04:40:47.297085 Set Vref, RX VrefLevel [Byte0]: 42
3339 04:40:47.300055 [Byte1]: 42
3340 04:40:47.304672
3341 04:40:47.304782 Set Vref, RX VrefLevel [Byte0]: 43
3342 04:40:47.308460 [Byte1]: 43
3343 04:40:47.312671
3344 04:40:47.312776 Set Vref, RX VrefLevel [Byte0]: 44
3345 04:40:47.316238 [Byte1]: 44
3346 04:40:47.320861
3347 04:40:47.320955 Set Vref, RX VrefLevel [Byte0]: 45
3348 04:40:47.324021 [Byte1]: 45
3349 04:40:47.328394
3350 04:40:47.328501 Set Vref, RX VrefLevel [Byte0]: 46
3351 04:40:47.331885 [Byte1]: 46
3352 04:40:47.336398
3353 04:40:47.336502 Set Vref, RX VrefLevel [Byte0]: 47
3354 04:40:47.340144 [Byte1]: 47
3355 04:40:47.344496
3356 04:40:47.344602 Set Vref, RX VrefLevel [Byte0]: 48
3357 04:40:47.347361 [Byte1]: 48
3358 04:40:47.352324
3359 04:40:47.352431 Set Vref, RX VrefLevel [Byte0]: 49
3360 04:40:47.355472 [Byte1]: 49
3361 04:40:47.360247
3362 04:40:47.360366 Set Vref, RX VrefLevel [Byte0]: 50
3363 04:40:47.363675 [Byte1]: 50
3364 04:40:47.367899
3365 04:40:47.368001 Set Vref, RX VrefLevel [Byte0]: 51
3366 04:40:47.371495 [Byte1]: 51
3367 04:40:47.376337
3368 04:40:47.376436 Set Vref, RX VrefLevel [Byte0]: 52
3369 04:40:47.379295 [Byte1]: 52
3370 04:40:47.384053
3371 04:40:47.384151 Set Vref, RX VrefLevel [Byte0]: 53
3372 04:40:47.387325 [Byte1]: 53
3373 04:40:47.391853
3374 04:40:47.391933 Set Vref, RX VrefLevel [Byte0]: 54
3375 04:40:47.395017 [Byte1]: 54
3376 04:40:47.399781
3377 04:40:47.399860 Set Vref, RX VrefLevel [Byte0]: 55
3378 04:40:47.403130 [Byte1]: 55
3379 04:40:47.407950
3380 04:40:47.408053 Set Vref, RX VrefLevel [Byte0]: 56
3381 04:40:47.410816 [Byte1]: 56
3382 04:40:47.416313
3383 04:40:47.416415 Set Vref, RX VrefLevel [Byte0]: 57
3384 04:40:47.419109 [Byte1]: 57
3385 04:40:47.423528
3386 04:40:47.423638 Set Vref, RX VrefLevel [Byte0]: 58
3387 04:40:47.427163 [Byte1]: 58
3388 04:40:47.431270
3389 04:40:47.431369 Set Vref, RX VrefLevel [Byte0]: 59
3390 04:40:47.434934 [Byte1]: 59
3391 04:40:47.439755
3392 04:40:47.439849 Set Vref, RX VrefLevel [Byte0]: 60
3393 04:40:47.442728 [Byte1]: 60
3394 04:40:47.447063
3395 04:40:47.447165 Set Vref, RX VrefLevel [Byte0]: 61
3396 04:40:47.450430 [Byte1]: 61
3397 04:40:47.454982
3398 04:40:47.455094 Set Vref, RX VrefLevel [Byte0]: 62
3399 04:40:47.458587 [Byte1]: 62
3400 04:40:47.463151
3401 04:40:47.463260 Set Vref, RX VrefLevel [Byte0]: 63
3402 04:40:47.466310 [Byte1]: 63
3403 04:40:47.471025
3404 04:40:47.471141 Set Vref, RX VrefLevel [Byte0]: 64
3405 04:40:47.474172 [Byte1]: 64
3406 04:40:47.478719
3407 04:40:47.478821 Set Vref, RX VrefLevel [Byte0]: 65
3408 04:40:47.482345 [Byte1]: 65
3409 04:40:47.487294
3410 04:40:47.487395 Set Vref, RX VrefLevel [Byte0]: 66
3411 04:40:47.489988 [Byte1]: 66
3412 04:40:47.494632
3413 04:40:47.494733 Set Vref, RX VrefLevel [Byte0]: 67
3414 04:40:47.498020 [Byte1]: 67
3415 04:40:47.502883
3416 04:40:47.502963 Set Vref, RX VrefLevel [Byte0]: 68
3417 04:40:47.506342 [Byte1]: 68
3418 04:40:47.510535
3419 04:40:47.510668 Set Vref, RX VrefLevel [Byte0]: 69
3420 04:40:47.513907 [Byte1]: 69
3421 04:40:47.518319
3422 04:40:47.518425 Set Vref, RX VrefLevel [Byte0]: 70
3423 04:40:47.521841 [Byte1]: 70
3424 04:40:47.526520
3425 04:40:47.526624 Set Vref, RX VrefLevel [Byte0]: 71
3426 04:40:47.529674 [Byte1]: 71
3427 04:40:47.534246
3428 04:40:47.534350 Final RX Vref Byte 0 = 57 to rank0
3429 04:40:47.537878 Final RX Vref Byte 1 = 52 to rank0
3430 04:40:47.540864 Final RX Vref Byte 0 = 57 to rank1
3431 04:40:47.544544 Final RX Vref Byte 1 = 52 to rank1==
3432 04:40:47.547670 Dram Type= 6, Freq= 0, CH_1, rank 0
3433 04:40:47.551187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 04:40:47.554764 ==
3435 04:40:47.554868 DQS Delay:
3436 04:40:47.554958 DQS0 = 0, DQS1 = 0
3437 04:40:47.558060 DQM Delay:
3438 04:40:47.558164 DQM0 = 116, DQM1 = 110
3439 04:40:47.561450 DQ Delay:
3440 04:40:47.564793 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3441 04:40:47.568228 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =114
3442 04:40:47.571052 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =104
3443 04:40:47.574894 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =114
3444 04:40:47.575002
3445 04:40:47.575096
3446 04:40:47.581632 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3447 04:40:47.584479 CH1 RK0: MR19=303, MR18=FDE2
3448 04:40:47.591149 CH1_RK0: MR19=0x303, MR18=0xFDE2, DQSOSC=411, MR23=63, INC=38, DEC=25
3449 04:40:47.591253
3450 04:40:47.594641 ----->DramcWriteLeveling(PI) begin...
3451 04:40:47.594743 ==
3452 04:40:47.598166 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 04:40:47.601888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 04:40:47.601990 ==
3455 04:40:47.604820 Write leveling (Byte 0): 28 => 28
3456 04:40:47.607993 Write leveling (Byte 1): 29 => 29
3457 04:40:47.611238 DramcWriteLeveling(PI) end<-----
3458 04:40:47.611339
3459 04:40:47.611429 ==
3460 04:40:47.614828 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 04:40:47.618330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 04:40:47.621648 ==
3463 04:40:47.621725 [Gating] SW mode calibration
3464 04:40:47.628633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3465 04:40:47.634673 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3466 04:40:47.638849 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3467 04:40:47.645276 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 04:40:47.648312 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3469 04:40:47.651935 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 04:40:47.658499 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 04:40:47.661513 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3472 04:40:47.665440 0 15 24 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
3473 04:40:47.668193 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3474 04:40:47.675296 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 04:40:47.678411 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 04:40:47.681818 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 04:40:47.688327 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 04:40:47.692072 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 04:40:47.695200 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3480 04:40:47.702124 1 0 24 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
3481 04:40:47.705189 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3482 04:40:47.708663 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 04:40:47.715449 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 04:40:47.718469 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 04:40:47.721948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 04:40:47.725878 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 04:40:47.732158 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3488 04:40:47.735215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3489 04:40:47.738473 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3490 04:40:47.745491 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 04:40:47.749013 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 04:40:47.752304 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 04:40:47.758903 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 04:40:47.762020 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 04:40:47.765626 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 04:40:47.772379 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 04:40:47.775184 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 04:40:47.778937 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 04:40:47.785392 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 04:40:47.788600 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 04:40:47.792283 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 04:40:47.798867 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 04:40:47.801666 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 04:40:47.805284 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3505 04:40:47.811834 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3506 04:40:47.811913 Total UI for P1: 0, mck2ui 16
3507 04:40:47.818502 best dqsien dly found for B0: ( 1, 3, 24)
3508 04:40:47.821876 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 04:40:47.825239 Total UI for P1: 0, mck2ui 16
3510 04:40:47.828716 best dqsien dly found for B1: ( 1, 3, 30)
3511 04:40:47.831825 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3512 04:40:47.835445 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3513 04:40:47.835529
3514 04:40:47.838623 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3515 04:40:47.841751 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3516 04:40:47.845329 [Gating] SW calibration Done
3517 04:40:47.845411 ==
3518 04:40:47.848630 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 04:40:47.851575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 04:40:47.851672 ==
3521 04:40:47.854990 RX Vref Scan: 0
3522 04:40:47.855071
3523 04:40:47.858298 RX Vref 0 -> 0, step: 1
3524 04:40:47.858388
3525 04:40:47.858468 RX Delay -40 -> 252, step: 8
3526 04:40:47.865350 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3527 04:40:47.868380 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3528 04:40:47.871878 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3529 04:40:47.875395 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3530 04:40:47.878352 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3531 04:40:47.885768 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3532 04:40:47.888889 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3533 04:40:47.891934 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3534 04:40:47.895328 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3535 04:40:47.899254 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3536 04:40:47.902048 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3537 04:40:47.908489 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3538 04:40:47.912153 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3539 04:40:47.915410 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3540 04:40:47.918953 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3541 04:40:47.925347 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3542 04:40:47.925425 ==
3543 04:40:47.928876 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 04:40:47.932319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 04:40:47.932422 ==
3546 04:40:47.932520 DQS Delay:
3547 04:40:47.935406 DQS0 = 0, DQS1 = 0
3548 04:40:47.935508 DQM Delay:
3549 04:40:47.938878 DQM0 = 114, DQM1 = 110
3550 04:40:47.938974 DQ Delay:
3551 04:40:47.942014 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3552 04:40:47.945414 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3553 04:40:47.948893 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3554 04:40:47.952116 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3555 04:40:47.952191
3556 04:40:47.952298
3557 04:40:47.952400 ==
3558 04:40:47.955484 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 04:40:47.962326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 04:40:47.962431 ==
3561 04:40:47.962528
3562 04:40:47.962615
3563 04:40:47.962705 TX Vref Scan disable
3564 04:40:47.965717 == TX Byte 0 ==
3565 04:40:47.969120 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3566 04:40:47.972166 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3567 04:40:47.975665 == TX Byte 1 ==
3568 04:40:47.978848 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3569 04:40:47.981969 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3570 04:40:47.985721 ==
3571 04:40:47.989054 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 04:40:47.992287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 04:40:47.992402 ==
3574 04:40:48.003389 TX Vref=22, minBit 1, minWin=25, winSum=418
3575 04:40:48.006895 TX Vref=24, minBit 2, minWin=25, winSum=424
3576 04:40:48.010260 TX Vref=26, minBit 2, minWin=26, winSum=428
3577 04:40:48.013368 TX Vref=28, minBit 2, minWin=26, winSum=429
3578 04:40:48.016613 TX Vref=30, minBit 2, minWin=26, winSum=431
3579 04:40:48.019669 TX Vref=32, minBit 4, minWin=26, winSum=428
3580 04:40:48.026941 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 30
3581 04:40:48.027044
3582 04:40:48.029836 Final TX Range 1 Vref 30
3583 04:40:48.029937
3584 04:40:48.030026 ==
3585 04:40:48.033319 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 04:40:48.036325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 04:40:48.036409 ==
3588 04:40:48.036473
3589 04:40:48.039804
3590 04:40:48.039928 TX Vref Scan disable
3591 04:40:48.043379 == TX Byte 0 ==
3592 04:40:48.046412 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3593 04:40:48.050324 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3594 04:40:48.053199 == TX Byte 1 ==
3595 04:40:48.056825 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3596 04:40:48.059587 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3597 04:40:48.059736
3598 04:40:48.063307 [DATLAT]
3599 04:40:48.063406 Freq=1200, CH1 RK1
3600 04:40:48.063503
3601 04:40:48.066561 DATLAT Default: 0xd
3602 04:40:48.066672 0, 0xFFFF, sum = 0
3603 04:40:48.069888 1, 0xFFFF, sum = 0
3604 04:40:48.069991 2, 0xFFFF, sum = 0
3605 04:40:48.073069 3, 0xFFFF, sum = 0
3606 04:40:48.073180 4, 0xFFFF, sum = 0
3607 04:40:48.076615 5, 0xFFFF, sum = 0
3608 04:40:48.076738 6, 0xFFFF, sum = 0
3609 04:40:48.079804 7, 0xFFFF, sum = 0
3610 04:40:48.083282 8, 0xFFFF, sum = 0
3611 04:40:48.083384 9, 0xFFFF, sum = 0
3612 04:40:48.086350 10, 0xFFFF, sum = 0
3613 04:40:48.086603 11, 0xFFFF, sum = 0
3614 04:40:48.089957 12, 0x0, sum = 1
3615 04:40:48.090062 13, 0x0, sum = 2
3616 04:40:48.093168 14, 0x0, sum = 3
3617 04:40:48.093242 15, 0x0, sum = 4
3618 04:40:48.093303 best_step = 13
3619 04:40:48.093360
3620 04:40:48.096395 ==
3621 04:40:48.099898 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 04:40:48.103041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 04:40:48.103140 ==
3624 04:40:48.103235 RX Vref Scan: 0
3625 04:40:48.103322
3626 04:40:48.106294 RX Vref 0 -> 0, step: 1
3627 04:40:48.106393
3628 04:40:48.109840 RX Delay -21 -> 252, step: 4
3629 04:40:48.112790 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3630 04:40:48.119619 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3631 04:40:48.123472 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3632 04:40:48.126359 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3633 04:40:48.129840 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3634 04:40:48.132825 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3635 04:40:48.136394 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3636 04:40:48.143268 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3637 04:40:48.146291 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3638 04:40:48.149921 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3639 04:40:48.152894 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3640 04:40:48.156557 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3641 04:40:48.163134 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3642 04:40:48.166439 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3643 04:40:48.169646 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3644 04:40:48.173406 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3645 04:40:48.173483 ==
3646 04:40:48.176375 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 04:40:48.182813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 04:40:48.182920 ==
3649 04:40:48.183012 DQS Delay:
3650 04:40:48.186230 DQS0 = 0, DQS1 = 0
3651 04:40:48.186330 DQM Delay:
3652 04:40:48.186434 DQM0 = 113, DQM1 = 110
3653 04:40:48.189614 DQ Delay:
3654 04:40:48.192815 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3655 04:40:48.196424 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3656 04:40:48.199443 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3657 04:40:48.203203 DQ12 =116, DQ13 =120, DQ14 =118, DQ15 =116
3658 04:40:48.203306
3659 04:40:48.203398
3660 04:40:48.213098 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 413 ps
3661 04:40:48.213177 CH1 RK1: MR19=303, MR18=F7FD
3662 04:40:48.219548 CH1_RK1: MR19=0x303, MR18=0xF7FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3663 04:40:48.223156 [RxdqsGatingPostProcess] freq 1200
3664 04:40:48.229732 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3665 04:40:48.233345 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 04:40:48.236262 best DQS1 dly(2T, 0.5T) = (0, 11)
3667 04:40:48.239942 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 04:40:48.242901 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3669 04:40:48.243013 best DQS0 dly(2T, 0.5T) = (0, 11)
3670 04:40:48.246694 best DQS1 dly(2T, 0.5T) = (0, 11)
3671 04:40:48.250215 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3672 04:40:48.252983 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3673 04:40:48.256533 Pre-setting of DQS Precalculation
3674 04:40:48.263337 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3675 04:40:48.270024 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3676 04:40:48.276656 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3677 04:40:48.277026
3678 04:40:48.277287
3679 04:40:48.280111 [Calibration Summary] 2400 Mbps
3680 04:40:48.280615 CH 0, Rank 0
3681 04:40:48.283437 SW Impedance : PASS
3682 04:40:48.286760 DUTY Scan : NO K
3683 04:40:48.287363 ZQ Calibration : PASS
3684 04:40:48.290162 Jitter Meter : NO K
3685 04:40:48.290747 CBT Training : PASS
3686 04:40:48.293813 Write leveling : PASS
3687 04:40:48.297147 RX DQS gating : PASS
3688 04:40:48.297619 RX DQ/DQS(RDDQC) : PASS
3689 04:40:48.300592 TX DQ/DQS : PASS
3690 04:40:48.303772 RX DATLAT : PASS
3691 04:40:48.304253 RX DQ/DQS(Engine): PASS
3692 04:40:48.307730 TX OE : NO K
3693 04:40:48.308173 All Pass.
3694 04:40:48.308504
3695 04:40:48.310246 CH 0, Rank 1
3696 04:40:48.310670 SW Impedance : PASS
3697 04:40:48.313702 DUTY Scan : NO K
3698 04:40:48.316950 ZQ Calibration : PASS
3699 04:40:48.317464 Jitter Meter : NO K
3700 04:40:48.320599 CBT Training : PASS
3701 04:40:48.323469 Write leveling : PASS
3702 04:40:48.324070 RX DQS gating : PASS
3703 04:40:48.326629 RX DQ/DQS(RDDQC) : PASS
3704 04:40:48.330379 TX DQ/DQS : PASS
3705 04:40:48.330969 RX DATLAT : PASS
3706 04:40:48.333947 RX DQ/DQS(Engine): PASS
3707 04:40:48.334912 TX OE : NO K
3708 04:40:48.336911 All Pass.
3709 04:40:48.337776
3710 04:40:48.338387 CH 1, Rank 0
3711 04:40:48.339968 SW Impedance : PASS
3712 04:40:48.340707 DUTY Scan : NO K
3713 04:40:48.343346 ZQ Calibration : PASS
3714 04:40:48.346684 Jitter Meter : NO K
3715 04:40:48.347215 CBT Training : PASS
3716 04:40:48.350184 Write leveling : PASS
3717 04:40:48.354007 RX DQS gating : PASS
3718 04:40:48.354503 RX DQ/DQS(RDDQC) : PASS
3719 04:40:48.356945 TX DQ/DQS : PASS
3720 04:40:48.360429 RX DATLAT : PASS
3721 04:40:48.361056 RX DQ/DQS(Engine): PASS
3722 04:40:48.363927 TX OE : NO K
3723 04:40:48.364444 All Pass.
3724 04:40:48.365018
3725 04:40:48.367117 CH 1, Rank 1
3726 04:40:48.367579 SW Impedance : PASS
3727 04:40:48.370621 DUTY Scan : NO K
3728 04:40:48.373686 ZQ Calibration : PASS
3729 04:40:48.374144 Jitter Meter : NO K
3730 04:40:48.377430 CBT Training : PASS
3731 04:40:48.377878 Write leveling : PASS
3732 04:40:48.380167 RX DQS gating : PASS
3733 04:40:48.383662 RX DQ/DQS(RDDQC) : PASS
3734 04:40:48.384378 TX DQ/DQS : PASS
3735 04:40:48.387277 RX DATLAT : PASS
3736 04:40:48.390451 RX DQ/DQS(Engine): PASS
3737 04:40:48.390884 TX OE : NO K
3738 04:40:48.393958 All Pass.
3739 04:40:48.394443
3740 04:40:48.394848 DramC Write-DBI off
3741 04:40:48.397174 PER_BANK_REFRESH: Hybrid Mode
3742 04:40:48.397867 TX_TRACKING: ON
3743 04:40:48.406867 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3744 04:40:48.410605 [FAST_K] Save calibration result to emmc
3745 04:40:48.413449 dramc_set_vcore_voltage set vcore to 650000
3746 04:40:48.416985 Read voltage for 600, 5
3747 04:40:48.417475 Vio18 = 0
3748 04:40:48.420602 Vcore = 650000
3749 04:40:48.421169 Vdram = 0
3750 04:40:48.421602 Vddq = 0
3751 04:40:48.424059 Vmddr = 0
3752 04:40:48.427137 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3753 04:40:48.434304 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3754 04:40:48.434840 MEM_TYPE=3, freq_sel=19
3755 04:40:48.437323 sv_algorithm_assistance_LP4_1600
3756 04:40:48.440778 ============ PULL DRAM RESETB DOWN ============
3757 04:40:48.447141 ========== PULL DRAM RESETB DOWN end =========
3758 04:40:48.450633 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3759 04:40:48.453993 ===================================
3760 04:40:48.457081 LPDDR4 DRAM CONFIGURATION
3761 04:40:48.460617 ===================================
3762 04:40:48.461299 EX_ROW_EN[0] = 0x0
3763 04:40:48.464353 EX_ROW_EN[1] = 0x0
3764 04:40:48.464840 LP4Y_EN = 0x0
3765 04:40:48.467150 WORK_FSP = 0x0
3766 04:40:48.467592 WL = 0x2
3767 04:40:48.470630 RL = 0x2
3768 04:40:48.471070 BL = 0x2
3769 04:40:48.474270 RPST = 0x0
3770 04:40:48.474854 RD_PRE = 0x0
3771 04:40:48.477314 WR_PRE = 0x1
3772 04:40:48.480875 WR_PST = 0x0
3773 04:40:48.481315 DBI_WR = 0x0
3774 04:40:48.484029 DBI_RD = 0x0
3775 04:40:48.484464 OTF = 0x1
3776 04:40:48.487505 ===================================
3777 04:40:48.490925 ===================================
3778 04:40:48.491371 ANA top config
3779 04:40:48.493904 ===================================
3780 04:40:48.497125 DLL_ASYNC_EN = 0
3781 04:40:48.500544 ALL_SLAVE_EN = 1
3782 04:40:48.504057 NEW_RANK_MODE = 1
3783 04:40:48.507425 DLL_IDLE_MODE = 1
3784 04:40:48.508066 LP45_APHY_COMB_EN = 1
3785 04:40:48.510790 TX_ODT_DIS = 1
3786 04:40:48.514037 NEW_8X_MODE = 1
3787 04:40:48.517153 ===================================
3788 04:40:48.520627 ===================================
3789 04:40:48.524250 data_rate = 1200
3790 04:40:48.527178 CKR = 1
3791 04:40:48.527755 DQ_P2S_RATIO = 8
3792 04:40:48.530307 ===================================
3793 04:40:48.533754 CA_P2S_RATIO = 8
3794 04:40:48.537303 DQ_CA_OPEN = 0
3795 04:40:48.540763 DQ_SEMI_OPEN = 0
3796 04:40:48.543621 CA_SEMI_OPEN = 0
3797 04:40:48.546949 CA_FULL_RATE = 0
3798 04:40:48.547541 DQ_CKDIV4_EN = 1
3799 04:40:48.550509 CA_CKDIV4_EN = 1
3800 04:40:48.553911 CA_PREDIV_EN = 0
3801 04:40:48.557205 PH8_DLY = 0
3802 04:40:48.560731 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3803 04:40:48.563663 DQ_AAMCK_DIV = 4
3804 04:40:48.564151 CA_AAMCK_DIV = 4
3805 04:40:48.567405 CA_ADMCK_DIV = 4
3806 04:40:48.570289 DQ_TRACK_CA_EN = 0
3807 04:40:48.573731 CA_PICK = 600
3808 04:40:48.577260 CA_MCKIO = 600
3809 04:40:48.580762 MCKIO_SEMI = 0
3810 04:40:48.581288 PLL_FREQ = 2288
3811 04:40:48.583772 DQ_UI_PI_RATIO = 32
3812 04:40:48.587323 CA_UI_PI_RATIO = 0
3813 04:40:48.590366 ===================================
3814 04:40:48.594205 ===================================
3815 04:40:48.597509 memory_type:LPDDR4
3816 04:40:48.598179 GP_NUM : 10
3817 04:40:48.600852 SRAM_EN : 1
3818 04:40:48.603937 MD32_EN : 0
3819 04:40:48.607267 ===================================
3820 04:40:48.607906 [ANA_INIT] >>>>>>>>>>>>>>
3821 04:40:48.610781 <<<<<< [CONFIGURE PHASE]: ANA_TX
3822 04:40:48.613878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3823 04:40:48.617755 ===================================
3824 04:40:48.620593 data_rate = 1200,PCW = 0X5800
3825 04:40:48.624039 ===================================
3826 04:40:48.627843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3827 04:40:48.634010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 04:40:48.637689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 04:40:48.643449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3830 04:40:48.646683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3831 04:40:48.650657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3832 04:40:48.650768 [ANA_INIT] flow start
3833 04:40:48.653719 [ANA_INIT] PLL >>>>>>>>
3834 04:40:48.656854 [ANA_INIT] PLL <<<<<<<<
3835 04:40:48.660089 [ANA_INIT] MIDPI >>>>>>>>
3836 04:40:48.660202 [ANA_INIT] MIDPI <<<<<<<<
3837 04:40:48.663583 [ANA_INIT] DLL >>>>>>>>
3838 04:40:48.663694 [ANA_INIT] flow end
3839 04:40:48.670079 ============ LP4 DIFF to SE enter ============
3840 04:40:48.673881 ============ LP4 DIFF to SE exit ============
3841 04:40:48.677351 [ANA_INIT] <<<<<<<<<<<<<
3842 04:40:48.680272 [Flow] Enable top DCM control >>>>>
3843 04:40:48.683422 [Flow] Enable top DCM control <<<<<
3844 04:40:48.683536 Enable DLL master slave shuffle
3845 04:40:48.690573 ==============================================================
3846 04:40:48.693809 Gating Mode config
3847 04:40:48.697456 ==============================================================
3848 04:40:48.700185 Config description:
3849 04:40:48.710285 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3850 04:40:48.717062 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3851 04:40:48.720450 SELPH_MODE 0: By rank 1: By Phase
3852 04:40:48.726987 ==============================================================
3853 04:40:48.730334 GAT_TRACK_EN = 1
3854 04:40:48.734165 RX_GATING_MODE = 2
3855 04:40:48.736866 RX_GATING_TRACK_MODE = 2
3856 04:40:48.736951 SELPH_MODE = 1
3857 04:40:48.740387 PICG_EARLY_EN = 1
3858 04:40:48.743583 VALID_LAT_VALUE = 1
3859 04:40:48.750691 ==============================================================
3860 04:40:48.753618 Enter into Gating configuration >>>>
3861 04:40:48.757122 Exit from Gating configuration <<<<
3862 04:40:48.760233 Enter into DVFS_PRE_config >>>>>
3863 04:40:48.770661 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3864 04:40:48.773818 Exit from DVFS_PRE_config <<<<<
3865 04:40:48.776795 Enter into PICG configuration >>>>
3866 04:40:48.780552 Exit from PICG configuration <<<<
3867 04:40:48.783680 [RX_INPUT] configuration >>>>>
3868 04:40:48.786988 [RX_INPUT] configuration <<<<<
3869 04:40:48.790578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3870 04:40:48.796751 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3871 04:40:48.803881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3872 04:40:48.810427 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3873 04:40:48.813422 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3874 04:40:48.820074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3875 04:40:48.824077 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3876 04:40:48.830630 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3877 04:40:48.833676 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3878 04:40:48.837094 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3879 04:40:48.840721 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3880 04:40:48.847054 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 04:40:48.850756 ===================================
3882 04:40:48.850857 LPDDR4 DRAM CONFIGURATION
3883 04:40:48.853710 ===================================
3884 04:40:48.857177 EX_ROW_EN[0] = 0x0
3885 04:40:48.860146 EX_ROW_EN[1] = 0x0
3886 04:40:48.860244 LP4Y_EN = 0x0
3887 04:40:48.864008 WORK_FSP = 0x0
3888 04:40:48.864123 WL = 0x2
3889 04:40:48.866835 RL = 0x2
3890 04:40:48.866936 BL = 0x2
3891 04:40:48.870692 RPST = 0x0
3892 04:40:48.870791 RD_PRE = 0x0
3893 04:40:48.873508 WR_PRE = 0x1
3894 04:40:48.873598 WR_PST = 0x0
3895 04:40:48.877065 DBI_WR = 0x0
3896 04:40:48.877170 DBI_RD = 0x0
3897 04:40:48.880378 OTF = 0x1
3898 04:40:48.883832 ===================================
3899 04:40:48.887246 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3900 04:40:48.890253 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3901 04:40:48.897411 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3902 04:40:48.900375 ===================================
3903 04:40:48.900491 LPDDR4 DRAM CONFIGURATION
3904 04:40:48.903885 ===================================
3905 04:40:48.907341 EX_ROW_EN[0] = 0x10
3906 04:40:48.907446 EX_ROW_EN[1] = 0x0
3907 04:40:48.910432 LP4Y_EN = 0x0
3908 04:40:48.910533 WORK_FSP = 0x0
3909 04:40:48.913787 WL = 0x2
3910 04:40:48.917472 RL = 0x2
3911 04:40:48.917580 BL = 0x2
3912 04:40:48.920330 RPST = 0x0
3913 04:40:48.920430 RD_PRE = 0x0
3914 04:40:48.923775 WR_PRE = 0x1
3915 04:40:48.923878 WR_PST = 0x0
3916 04:40:48.927144 DBI_WR = 0x0
3917 04:40:48.927245 DBI_RD = 0x0
3918 04:40:48.930508 OTF = 0x1
3919 04:40:48.933837 ===================================
3920 04:40:48.936918 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3921 04:40:48.942912 nWR fixed to 30
3922 04:40:48.946086 [ModeRegInit_LP4] CH0 RK0
3923 04:40:48.946187 [ModeRegInit_LP4] CH0 RK1
3924 04:40:48.949392 [ModeRegInit_LP4] CH1 RK0
3925 04:40:48.953147 [ModeRegInit_LP4] CH1 RK1
3926 04:40:48.953257 match AC timing 17
3927 04:40:48.959937 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3928 04:40:48.962586 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3929 04:40:48.966401 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3930 04:40:48.972727 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3931 04:40:48.976220 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3932 04:40:48.976377 ==
3933 04:40:48.979787 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 04:40:48.982934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 04:40:48.983094 ==
3936 04:40:48.989392 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 04:40:48.996357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3938 04:40:48.999486 [CA 0] Center 36 (6~66) winsize 61
3939 04:40:49.003030 [CA 1] Center 36 (6~66) winsize 61
3940 04:40:49.005784 [CA 2] Center 34 (4~65) winsize 62
3941 04:40:49.009674 [CA 3] Center 34 (4~65) winsize 62
3942 04:40:49.012683 [CA 4] Center 33 (3~64) winsize 62
3943 04:40:49.016138 [CA 5] Center 33 (3~64) winsize 62
3944 04:40:49.016247
3945 04:40:49.019707 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3946 04:40:49.019804
3947 04:40:49.022599 [CATrainingPosCal] consider 1 rank data
3948 04:40:49.026182 u2DelayCellTimex100 = 270/100 ps
3949 04:40:49.029783 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3950 04:40:49.032840 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3951 04:40:49.036331 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 04:40:49.039537 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3953 04:40:49.042801 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 04:40:49.046355 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3955 04:40:49.046476
3956 04:40:49.050012 CA PerBit enable=1, Macro0, CA PI delay=33
3957 04:40:49.050126
3958 04:40:49.053290 [CBTSetCACLKResult] CA Dly = 33
3959 04:40:49.056174 CS Dly: 5 (0~36)
3960 04:40:49.056283 ==
3961 04:40:49.059674 Dram Type= 6, Freq= 0, CH_0, rank 1
3962 04:40:49.062926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 04:40:49.063032 ==
3964 04:40:49.069306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3965 04:40:49.076050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3966 04:40:49.079463 [CA 0] Center 36 (6~66) winsize 61
3967 04:40:49.082868 [CA 1] Center 36 (6~66) winsize 61
3968 04:40:49.086709 [CA 2] Center 34 (4~65) winsize 62
3969 04:40:49.089691 [CA 3] Center 34 (4~65) winsize 62
3970 04:40:49.093225 [CA 4] Center 33 (3~64) winsize 62
3971 04:40:49.096012 [CA 5] Center 33 (3~64) winsize 62
3972 04:40:49.096095
3973 04:40:49.099709 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3974 04:40:49.099785
3975 04:40:49.102729 [CATrainingPosCal] consider 2 rank data
3976 04:40:49.106275 u2DelayCellTimex100 = 270/100 ps
3977 04:40:49.109221 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3978 04:40:49.112930 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3979 04:40:49.116262 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3980 04:40:49.119440 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3981 04:40:49.122950 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 04:40:49.126092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3983 04:40:49.126196
3984 04:40:49.132853 CA PerBit enable=1, Macro0, CA PI delay=33
3985 04:40:49.132928
3986 04:40:49.132989 [CBTSetCACLKResult] CA Dly = 33
3987 04:40:49.136219 CS Dly: 5 (0~36)
3988 04:40:49.136315
3989 04:40:49.139356 ----->DramcWriteLeveling(PI) begin...
3990 04:40:49.139468 ==
3991 04:40:49.143089 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 04:40:49.146115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 04:40:49.146212 ==
3994 04:40:49.149371 Write leveling (Byte 0): 32 => 32
3995 04:40:49.153106 Write leveling (Byte 1): 29 => 29
3996 04:40:49.156115 DramcWriteLeveling(PI) end<-----
3997 04:40:49.156202
3998 04:40:49.156289 ==
3999 04:40:49.159578 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 04:40:49.162554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 04:40:49.166195 ==
4002 04:40:49.166306 [Gating] SW mode calibration
4003 04:40:49.172739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4004 04:40:49.179515 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4005 04:40:49.182898 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 04:40:49.189637 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 04:40:49.192994 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 04:40:49.196523 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4009 04:40:49.202877 0 9 16 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 0)
4010 04:40:49.206296 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 04:40:49.209871 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 04:40:49.212787 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 04:40:49.219400 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 04:40:49.222754 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 04:40:49.226537 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 04:40:49.232815 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 04:40:49.236478 0 10 16 | B1->B0 | 2e2e 4545 | 0 0 | (0 0) (0 0)
4018 04:40:49.239297 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 04:40:49.246315 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 04:40:49.249827 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 04:40:49.252706 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 04:40:49.259245 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 04:40:49.262731 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 04:40:49.266165 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 04:40:49.272817 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4026 04:40:49.276315 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4027 04:40:49.279413 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 04:40:49.286274 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 04:40:49.289566 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 04:40:49.292871 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 04:40:49.299583 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 04:40:49.302890 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 04:40:49.306608 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 04:40:49.309573 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 04:40:49.316226 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 04:40:49.319723 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 04:40:49.323267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 04:40:49.329672 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 04:40:49.333129 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 04:40:49.336552 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 04:40:49.343352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4042 04:40:49.343453 Total UI for P1: 0, mck2ui 16
4043 04:40:49.349934 best dqsien dly found for B0: ( 0, 13, 14)
4044 04:40:49.352885 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 04:40:49.356271 Total UI for P1: 0, mck2ui 16
4046 04:40:49.359643 best dqsien dly found for B1: ( 0, 13, 16)
4047 04:40:49.362999 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4048 04:40:49.366719 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4049 04:40:49.366802
4050 04:40:49.369558 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4051 04:40:49.372956 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4052 04:40:49.376587 [Gating] SW calibration Done
4053 04:40:49.376739 ==
4054 04:40:49.379699 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 04:40:49.383243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 04:40:49.386279 ==
4057 04:40:49.386361 RX Vref Scan: 0
4058 04:40:49.386426
4059 04:40:49.389999 RX Vref 0 -> 0, step: 1
4060 04:40:49.390080
4061 04:40:49.392936 RX Delay -230 -> 252, step: 16
4062 04:40:49.396442 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4063 04:40:49.399558 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4064 04:40:49.402920 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4065 04:40:49.406250 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4066 04:40:49.413119 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4067 04:40:49.416199 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4068 04:40:49.419431 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4069 04:40:49.423324 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4070 04:40:49.429675 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4071 04:40:49.433194 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4072 04:40:49.436331 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4073 04:40:49.439783 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4074 04:40:49.443414 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4075 04:40:49.449807 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4076 04:40:49.453402 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4077 04:40:49.456256 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4078 04:40:49.456330 ==
4079 04:40:49.459781 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 04:40:49.463242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 04:40:49.466794 ==
4082 04:40:49.466871 DQS Delay:
4083 04:40:49.466941 DQS0 = 0, DQS1 = 0
4084 04:40:49.470212 DQM Delay:
4085 04:40:49.470306 DQM0 = 40, DQM1 = 31
4086 04:40:49.473312 DQ Delay:
4087 04:40:49.473450 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4088 04:40:49.476480 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4089 04:40:49.479965 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4090 04:40:49.483231 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4091 04:40:49.483332
4092 04:40:49.486494
4093 04:40:49.486576 ==
4094 04:40:49.490068 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 04:40:49.493281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 04:40:49.493386 ==
4097 04:40:49.493506
4098 04:40:49.493604
4099 04:40:49.496422 TX Vref Scan disable
4100 04:40:49.496505 == TX Byte 0 ==
4101 04:40:49.503428 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4102 04:40:49.506772 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4103 04:40:49.506889 == TX Byte 1 ==
4104 04:40:49.513155 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4105 04:40:49.516811 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4106 04:40:49.516923 ==
4107 04:40:49.520380 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 04:40:49.523929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 04:40:49.524074 ==
4110 04:40:49.524199
4111 04:40:49.524261
4112 04:40:49.526341 TX Vref Scan disable
4113 04:40:49.530330 == TX Byte 0 ==
4114 04:40:49.533904 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4115 04:40:49.536646 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4116 04:40:49.539988 == TX Byte 1 ==
4117 04:40:49.543098 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4118 04:40:49.546939 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4119 04:40:49.547054
4120 04:40:49.549876 [DATLAT]
4121 04:40:49.549958 Freq=600, CH0 RK0
4122 04:40:49.550038
4123 04:40:49.553486 DATLAT Default: 0x9
4124 04:40:49.553599 0, 0xFFFF, sum = 0
4125 04:40:49.556340 1, 0xFFFF, sum = 0
4126 04:40:49.556424 2, 0xFFFF, sum = 0
4127 04:40:49.559777 3, 0xFFFF, sum = 0
4128 04:40:49.559875 4, 0xFFFF, sum = 0
4129 04:40:49.563151 5, 0xFFFF, sum = 0
4130 04:40:49.563252 6, 0xFFFF, sum = 0
4131 04:40:49.566508 7, 0xFFFF, sum = 0
4132 04:40:49.566594 8, 0x0, sum = 1
4133 04:40:49.570045 9, 0x0, sum = 2
4134 04:40:49.570168 10, 0x0, sum = 3
4135 04:40:49.573498 11, 0x0, sum = 4
4136 04:40:49.573585 best_step = 9
4137 04:40:49.573650
4138 04:40:49.573723 ==
4139 04:40:49.576662 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 04:40:49.580104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 04:40:49.583346 ==
4142 04:40:49.583432 RX Vref Scan: 1
4143 04:40:49.583497
4144 04:40:49.586942 RX Vref 0 -> 0, step: 1
4145 04:40:49.587022
4146 04:40:49.587085 RX Delay -195 -> 252, step: 8
4147 04:40:49.589853
4148 04:40:49.589938 Set Vref, RX VrefLevel [Byte0]: 53
4149 04:40:49.593219 [Byte1]: 51
4150 04:40:49.598074
4151 04:40:49.598188 Final RX Vref Byte 0 = 53 to rank0
4152 04:40:49.601420 Final RX Vref Byte 1 = 51 to rank0
4153 04:40:49.604931 Final RX Vref Byte 0 = 53 to rank1
4154 04:40:49.608065 Final RX Vref Byte 1 = 51 to rank1==
4155 04:40:49.611476 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 04:40:49.618101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 04:40:49.618189 ==
4158 04:40:49.618255 DQS Delay:
4159 04:40:49.618317 DQS0 = 0, DQS1 = 0
4160 04:40:49.621843 DQM Delay:
4161 04:40:49.621928 DQM0 = 43, DQM1 = 33
4162 04:40:49.625558 DQ Delay:
4163 04:40:49.628232 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =44
4164 04:40:49.628317 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4165 04:40:49.632038 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4166 04:40:49.635173 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4167 04:40:49.635287
4168 04:40:49.638472
4169 04:40:49.644991 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b19, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
4170 04:40:49.648329 CH0 RK0: MR19=808, MR18=3B19
4171 04:40:49.654976 CH0_RK0: MR19=0x808, MR18=0x3B19, DQSOSC=398, MR23=63, INC=165, DEC=110
4172 04:40:49.655062
4173 04:40:49.658531 ----->DramcWriteLeveling(PI) begin...
4174 04:40:49.658617 ==
4175 04:40:49.661643 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 04:40:49.664993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 04:40:49.665079 ==
4178 04:40:49.668684 Write leveling (Byte 0): 31 => 31
4179 04:40:49.671491 Write leveling (Byte 1): 31 => 31
4180 04:40:49.674844 DramcWriteLeveling(PI) end<-----
4181 04:40:49.674930
4182 04:40:49.674996 ==
4183 04:40:49.678633 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 04:40:49.681683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 04:40:49.681769 ==
4186 04:40:49.685314 [Gating] SW mode calibration
4187 04:40:49.691801 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4188 04:40:49.698486 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4189 04:40:49.701695 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 04:40:49.705097 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 04:40:49.711898 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 04:40:49.715391 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
4193 04:40:49.718272 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
4194 04:40:49.725285 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 04:40:49.728801 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 04:40:49.731656 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 04:40:49.735086 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 04:40:49.741811 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 04:40:49.745269 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 04:40:49.748889 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4201 04:40:49.755485 0 10 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
4202 04:40:49.758401 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 04:40:49.762089 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 04:40:49.768692 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 04:40:49.771820 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 04:40:49.775210 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 04:40:49.781571 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 04:40:49.785296 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4209 04:40:49.788266 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4210 04:40:49.795615 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4211 04:40:49.798479 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 04:40:49.802090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 04:40:49.808318 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 04:40:49.811745 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 04:40:49.815167 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 04:40:49.821567 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 04:40:49.825258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 04:40:49.828317 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 04:40:49.834997 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 04:40:49.838307 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 04:40:49.841432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 04:40:49.847993 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 04:40:49.851606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 04:40:49.854563 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4225 04:40:49.861367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 04:40:49.861445 Total UI for P1: 0, mck2ui 16
4227 04:40:49.865005 best dqsien dly found for B0: ( 0, 13, 12)
4228 04:40:49.868590 Total UI for P1: 0, mck2ui 16
4229 04:40:49.871498 best dqsien dly found for B1: ( 0, 13, 14)
4230 04:40:49.874937 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4231 04:40:49.881748 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4232 04:40:49.881828
4233 04:40:49.884723 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4234 04:40:49.888237 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4235 04:40:49.891297 [Gating] SW calibration Done
4236 04:40:49.891382 ==
4237 04:40:49.894986 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 04:40:49.898065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 04:40:49.898142 ==
4240 04:40:49.898205 RX Vref Scan: 0
4241 04:40:49.901648
4242 04:40:49.901721 RX Vref 0 -> 0, step: 1
4243 04:40:49.901791
4244 04:40:49.904631 RX Delay -230 -> 252, step: 16
4245 04:40:49.908158 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4246 04:40:49.915221 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4247 04:40:49.918047 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4248 04:40:49.921494 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4249 04:40:49.925219 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4250 04:40:49.928431 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4251 04:40:49.935097 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4252 04:40:49.938271 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4253 04:40:49.941353 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4254 04:40:49.944915 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4255 04:40:49.951504 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4256 04:40:49.954835 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4257 04:40:49.958409 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4258 04:40:49.961578 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4259 04:40:49.964813 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4260 04:40:49.971444 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4261 04:40:49.971537 ==
4262 04:40:49.975028 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 04:40:49.978474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 04:40:49.978557 ==
4265 04:40:49.978621 DQS Delay:
4266 04:40:49.982085 DQS0 = 0, DQS1 = 0
4267 04:40:49.982162 DQM Delay:
4268 04:40:49.985532 DQM0 = 41, DQM1 = 31
4269 04:40:49.985611 DQ Delay:
4270 04:40:49.988223 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4271 04:40:49.991925 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4272 04:40:49.994969 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4273 04:40:49.998539 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4274 04:40:49.998623
4275 04:40:49.998692
4276 04:40:49.998754 ==
4277 04:40:50.001941 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 04:40:50.005186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 04:40:50.005277 ==
4280 04:40:50.008848
4281 04:40:50.008933
4282 04:40:50.008996 TX Vref Scan disable
4283 04:40:50.011701 == TX Byte 0 ==
4284 04:40:50.015150 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4285 04:40:50.018591 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4286 04:40:50.021647 == TX Byte 1 ==
4287 04:40:50.025156 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4288 04:40:50.028388 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4289 04:40:50.028466 ==
4290 04:40:50.032370 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 04:40:50.038442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 04:40:50.038603 ==
4293 04:40:50.038701
4294 04:40:50.038840
4295 04:40:50.038945 TX Vref Scan disable
4296 04:40:50.043206 == TX Byte 0 ==
4297 04:40:50.046365 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4298 04:40:50.049852 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4299 04:40:50.052773 == TX Byte 1 ==
4300 04:40:50.056601 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4301 04:40:50.059401 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4302 04:40:50.062908
4303 04:40:50.062993 [DATLAT]
4304 04:40:50.063061 Freq=600, CH0 RK1
4305 04:40:50.063122
4306 04:40:50.066429 DATLAT Default: 0x9
4307 04:40:50.066534 0, 0xFFFF, sum = 0
4308 04:40:50.069379 1, 0xFFFF, sum = 0
4309 04:40:50.069467 2, 0xFFFF, sum = 0
4310 04:40:50.073318 3, 0xFFFF, sum = 0
4311 04:40:50.073395 4, 0xFFFF, sum = 0
4312 04:40:50.076383 5, 0xFFFF, sum = 0
4313 04:40:50.076490 6, 0xFFFF, sum = 0
4314 04:40:50.079685 7, 0xFFFF, sum = 0
4315 04:40:50.079762 8, 0x0, sum = 1
4316 04:40:50.082730 9, 0x0, sum = 2
4317 04:40:50.082808 10, 0x0, sum = 3
4318 04:40:50.086202 11, 0x0, sum = 4
4319 04:40:50.086292 best_step = 9
4320 04:40:50.086360
4321 04:40:50.086420 ==
4322 04:40:50.089801 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 04:40:50.096247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 04:40:50.096340 ==
4325 04:40:50.096407 RX Vref Scan: 0
4326 04:40:50.096475
4327 04:40:50.099990 RX Vref 0 -> 0, step: 1
4328 04:40:50.100071
4329 04:40:50.102562 RX Delay -195 -> 252, step: 8
4330 04:40:50.106152 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4331 04:40:50.113023 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4332 04:40:50.116252 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4333 04:40:50.119737 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4334 04:40:50.122610 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4335 04:40:50.126137 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4336 04:40:50.133488 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4337 04:40:50.136275 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4338 04:40:50.139855 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4339 04:40:50.142639 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4340 04:40:50.149603 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4341 04:40:50.152714 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4342 04:40:50.156444 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4343 04:40:50.159360 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4344 04:40:50.162910 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4345 04:40:50.169687 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4346 04:40:50.169770 ==
4347 04:40:50.172704 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 04:40:50.176060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 04:40:50.176135 ==
4350 04:40:50.176199 DQS Delay:
4351 04:40:50.179758 DQS0 = 0, DQS1 = 0
4352 04:40:50.179839 DQM Delay:
4353 04:40:50.182847 DQM0 = 39, DQM1 = 34
4354 04:40:50.182924 DQ Delay:
4355 04:40:50.186216 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4356 04:40:50.189363 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4357 04:40:50.192661 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4358 04:40:50.196296 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4359 04:40:50.196406
4360 04:40:50.196475
4361 04:40:50.202687 [DQSOSCAuto] RK1, (LSB)MR18= 0x482b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4362 04:40:50.206245 CH0 RK1: MR19=808, MR18=482B
4363 04:40:50.212770 CH0_RK1: MR19=0x808, MR18=0x482B, DQSOSC=396, MR23=63, INC=167, DEC=111
4364 04:40:50.216385 [RxdqsGatingPostProcess] freq 600
4365 04:40:50.223161 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4366 04:40:50.226510 Pre-setting of DQS Precalculation
4367 04:40:50.229867 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4368 04:40:50.229951 ==
4369 04:40:50.232766 Dram Type= 6, Freq= 0, CH_1, rank 0
4370 04:40:50.236743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 04:40:50.236821 ==
4372 04:40:50.243167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 04:40:50.249675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 04:40:50.253396 [CA 0] Center 35 (5~65) winsize 61
4375 04:40:50.256036 [CA 1] Center 35 (5~66) winsize 62
4376 04:40:50.259577 [CA 2] Center 33 (3~64) winsize 62
4377 04:40:50.263244 [CA 3] Center 33 (3~64) winsize 62
4378 04:40:50.266107 [CA 4] Center 34 (3~65) winsize 63
4379 04:40:50.269642 [CA 5] Center 33 (3~64) winsize 62
4380 04:40:50.269732
4381 04:40:50.272639 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 04:40:50.272732
4383 04:40:50.276330 [CATrainingPosCal] consider 1 rank data
4384 04:40:50.279592 u2DelayCellTimex100 = 270/100 ps
4385 04:40:50.283343 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4386 04:40:50.286179 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4387 04:40:50.289798 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 04:40:50.292958 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 04:40:50.296132 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4390 04:40:50.299608 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 04:40:50.302706
4392 04:40:50.306220 CA PerBit enable=1, Macro0, CA PI delay=33
4393 04:40:50.306303
4394 04:40:50.309623 [CBTSetCACLKResult] CA Dly = 33
4395 04:40:50.309702 CS Dly: 4 (0~35)
4396 04:40:50.309766 ==
4397 04:40:50.313179 Dram Type= 6, Freq= 0, CH_1, rank 1
4398 04:40:50.316396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 04:40:50.316490 ==
4400 04:40:50.322908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4401 04:40:50.329526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4402 04:40:50.332877 [CA 0] Center 35 (5~66) winsize 62
4403 04:40:50.336438 [CA 1] Center 36 (6~66) winsize 61
4404 04:40:50.339740 [CA 2] Center 34 (4~65) winsize 62
4405 04:40:50.342792 [CA 3] Center 33 (3~64) winsize 62
4406 04:40:50.346597 [CA 4] Center 34 (3~65) winsize 63
4407 04:40:50.349719 [CA 5] Center 33 (3~64) winsize 62
4408 04:40:50.349800
4409 04:40:50.352981 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4410 04:40:50.353054
4411 04:40:50.356689 [CATrainingPosCal] consider 2 rank data
4412 04:40:50.359679 u2DelayCellTimex100 = 270/100 ps
4413 04:40:50.362761 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4414 04:40:50.366369 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4415 04:40:50.369351 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4416 04:40:50.373138 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 04:40:50.376319 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4418 04:40:50.382879 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 04:40:50.382967
4420 04:40:50.386584 CA PerBit enable=1, Macro0, CA PI delay=33
4421 04:40:50.386663
4422 04:40:50.389807 [CBTSetCACLKResult] CA Dly = 33
4423 04:40:50.389893 CS Dly: 5 (0~37)
4424 04:40:50.389959
4425 04:40:50.393081 ----->DramcWriteLeveling(PI) begin...
4426 04:40:50.393160 ==
4427 04:40:50.396614 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 04:40:50.399614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 04:40:50.403126 ==
4430 04:40:50.403208 Write leveling (Byte 0): 30 => 30
4431 04:40:50.406470 Write leveling (Byte 1): 30 => 30
4432 04:40:50.409677 DramcWriteLeveling(PI) end<-----
4433 04:40:50.409754
4434 04:40:50.409825 ==
4435 04:40:50.413108 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 04:40:50.419600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 04:40:50.419684 ==
4438 04:40:50.419748 [Gating] SW mode calibration
4439 04:40:50.429493 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4440 04:40:50.433017 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4441 04:40:50.435921 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 04:40:50.443119 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 04:40:50.446125 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4444 04:40:50.449703 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4445 04:40:50.456288 0 9 16 | B1->B0 | 2c2c 2727 | 0 0 | (1 1) (1 1)
4446 04:40:50.459852 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4447 04:40:50.463416 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 04:40:50.469973 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 04:40:50.473413 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 04:40:50.476430 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 04:40:50.483084 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 04:40:50.486549 0 10 12 | B1->B0 | 2929 2c2c | 0 0 | (0 0) (0 0)
4453 04:40:50.490173 0 10 16 | B1->B0 | 3c3c 3d3d | 0 0 | (0 0) (0 0)
4454 04:40:50.493373 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 04:40:50.500256 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 04:40:50.503225 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 04:40:50.506815 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 04:40:50.513465 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 04:40:50.516725 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 04:40:50.520435 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4461 04:40:50.527151 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 04:40:50.530058 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 04:40:50.533616 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 04:40:50.540147 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 04:40:50.543606 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 04:40:50.546764 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 04:40:50.553367 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 04:40:50.556397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 04:40:50.559964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 04:40:50.566805 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 04:40:50.570211 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 04:40:50.573119 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 04:40:50.580169 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 04:40:50.583409 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 04:40:50.586506 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 04:40:50.593509 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 04:40:50.596494 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4478 04:40:50.600123 Total UI for P1: 0, mck2ui 16
4479 04:40:50.603173 best dqsien dly found for B0: ( 0, 13, 14)
4480 04:40:50.606805 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 04:40:50.609677 Total UI for P1: 0, mck2ui 16
4482 04:40:50.613535 best dqsien dly found for B1: ( 0, 13, 16)
4483 04:40:50.616311 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4484 04:40:50.620103 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4485 04:40:50.620231
4486 04:40:50.623181 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4487 04:40:50.629737 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4488 04:40:50.629818 [Gating] SW calibration Done
4489 04:40:50.629883 ==
4490 04:40:50.633415 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 04:40:50.639875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 04:40:50.639979 ==
4493 04:40:50.640046 RX Vref Scan: 0
4494 04:40:50.640164
4495 04:40:50.642896 RX Vref 0 -> 0, step: 1
4496 04:40:50.642966
4497 04:40:50.646334 RX Delay -230 -> 252, step: 16
4498 04:40:50.649718 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4499 04:40:50.653248 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4500 04:40:50.656456 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4501 04:40:50.663410 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4502 04:40:50.666774 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4503 04:40:50.669721 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4504 04:40:50.673381 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4505 04:40:50.676789 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4506 04:40:50.683343 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4507 04:40:50.686480 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4508 04:40:50.689502 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4509 04:40:50.693311 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4510 04:40:50.699650 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4511 04:40:50.703243 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4512 04:40:50.706901 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4513 04:40:50.709939 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4514 04:40:50.710017 ==
4515 04:40:50.712870 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 04:40:50.720069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 04:40:50.720161 ==
4518 04:40:50.720240 DQS Delay:
4519 04:40:50.723098 DQS0 = 0, DQS1 = 0
4520 04:40:50.723192 DQM Delay:
4521 04:40:50.723265 DQM0 = 43, DQM1 = 35
4522 04:40:50.726591 DQ Delay:
4523 04:40:50.729612 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4524 04:40:50.733435 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4525 04:40:50.736683 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4526 04:40:50.740129 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4527 04:40:50.740210
4528 04:40:50.740290
4529 04:40:50.740354 ==
4530 04:40:50.743149 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 04:40:50.746277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 04:40:50.746356 ==
4533 04:40:50.746441
4534 04:40:50.746502
4535 04:40:50.749700 TX Vref Scan disable
4536 04:40:50.752998 == TX Byte 0 ==
4537 04:40:50.756292 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4538 04:40:50.759608 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4539 04:40:50.763036 == TX Byte 1 ==
4540 04:40:50.766527 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4541 04:40:50.770254 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4542 04:40:50.770334 ==
4543 04:40:50.773289 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 04:40:50.776773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 04:40:50.776876 ==
4546 04:40:50.776943
4547 04:40:50.779898
4548 04:40:50.780026 TX Vref Scan disable
4549 04:40:50.783312 == TX Byte 0 ==
4550 04:40:50.786607 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4551 04:40:50.789751 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4552 04:40:50.793146 == TX Byte 1 ==
4553 04:40:50.796649 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4554 04:40:50.803549 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4555 04:40:50.803673
4556 04:40:50.803772 [DATLAT]
4557 04:40:50.803862 Freq=600, CH1 RK0
4558 04:40:50.803953
4559 04:40:50.806672 DATLAT Default: 0x9
4560 04:40:50.806782 0, 0xFFFF, sum = 0
4561 04:40:50.810274 1, 0xFFFF, sum = 0
4562 04:40:50.810398 2, 0xFFFF, sum = 0
4563 04:40:50.813234 3, 0xFFFF, sum = 0
4564 04:40:50.813325 4, 0xFFFF, sum = 0
4565 04:40:50.817146 5, 0xFFFF, sum = 0
4566 04:40:50.819800 6, 0xFFFF, sum = 0
4567 04:40:50.819890 7, 0xFFFF, sum = 0
4568 04:40:50.819964 8, 0x0, sum = 1
4569 04:40:50.823286 9, 0x0, sum = 2
4570 04:40:50.823364 10, 0x0, sum = 3
4571 04:40:50.826484 11, 0x0, sum = 4
4572 04:40:50.826569 best_step = 9
4573 04:40:50.826652
4574 04:40:50.826730 ==
4575 04:40:50.829673 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 04:40:50.836962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 04:40:50.837051 ==
4578 04:40:50.837135 RX Vref Scan: 1
4579 04:40:50.837214
4580 04:40:50.840114 RX Vref 0 -> 0, step: 1
4581 04:40:50.840243
4582 04:40:50.843217 RX Delay -195 -> 252, step: 8
4583 04:40:50.843291
4584 04:40:50.846881 Set Vref, RX VrefLevel [Byte0]: 57
4585 04:40:50.849814 [Byte1]: 52
4586 04:40:50.849891
4587 04:40:50.853413 Final RX Vref Byte 0 = 57 to rank0
4588 04:40:50.856501 Final RX Vref Byte 1 = 52 to rank0
4589 04:40:50.859950 Final RX Vref Byte 0 = 57 to rank1
4590 04:40:50.863522 Final RX Vref Byte 1 = 52 to rank1==
4591 04:40:50.866462 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 04:40:50.870203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 04:40:50.870288 ==
4594 04:40:50.873437 DQS Delay:
4595 04:40:50.873512 DQS0 = 0, DQS1 = 0
4596 04:40:50.873585 DQM Delay:
4597 04:40:50.876326 DQM0 = 40, DQM1 = 33
4598 04:40:50.876399 DQ Delay:
4599 04:40:50.879903 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4600 04:40:50.883320 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4601 04:40:50.886736 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4602 04:40:50.890018 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4603 04:40:50.890094
4604 04:40:50.890163
4605 04:40:50.900152 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c02, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4606 04:40:50.900241 CH1 RK0: MR19=808, MR18=3C02
4607 04:40:50.906699 CH1_RK0: MR19=0x808, MR18=0x3C02, DQSOSC=398, MR23=63, INC=165, DEC=110
4608 04:40:50.906784
4609 04:40:50.909870 ----->DramcWriteLeveling(PI) begin...
4610 04:40:50.909942 ==
4611 04:40:50.913438 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 04:40:50.920168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 04:40:50.920264 ==
4614 04:40:50.923037 Write leveling (Byte 0): 30 => 30
4615 04:40:50.926635 Write leveling (Byte 1): 31 => 31
4616 04:40:50.926720 DramcWriteLeveling(PI) end<-----
4617 04:40:50.930233
4618 04:40:50.930314 ==
4619 04:40:50.933270 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 04:40:50.936902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 04:40:50.936977 ==
4622 04:40:50.939774 [Gating] SW mode calibration
4623 04:40:50.946615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4624 04:40:50.950137 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4625 04:40:50.956769 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 04:40:50.960710 0 9 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4627 04:40:50.963150 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4628 04:40:50.970271 0 9 12 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4629 04:40:50.973468 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4630 04:40:50.976953 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 04:40:50.983761 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4632 04:40:50.986802 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 04:40:50.990159 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 04:40:50.993641 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 04:40:51.000359 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4636 04:40:51.003420 0 10 12 | B1->B0 | 3333 3b3b | 0 0 | (0 0) (1 1)
4637 04:40:51.006838 0 10 16 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
4638 04:40:51.013694 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 04:40:51.017055 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 04:40:51.020016 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 04:40:51.026967 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 04:40:51.030251 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 04:40:51.033628 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 04:40:51.040334 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4645 04:40:51.043394 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 04:40:51.047110 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 04:40:51.053323 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 04:40:51.056801 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 04:40:51.060373 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 04:40:51.066714 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 04:40:51.069984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 04:40:51.073717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 04:40:51.080188 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 04:40:51.083194 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 04:40:51.087339 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 04:40:51.090010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 04:40:51.097201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 04:40:51.099987 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 04:40:51.103809 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 04:40:51.110619 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4661 04:40:51.114029 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 04:40:51.116761 Total UI for P1: 0, mck2ui 16
4663 04:40:51.120513 best dqsien dly found for B0: ( 0, 13, 12)
4664 04:40:51.123452 Total UI for P1: 0, mck2ui 16
4665 04:40:51.127034 best dqsien dly found for B1: ( 0, 13, 14)
4666 04:40:51.130662 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4667 04:40:51.134046 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4668 04:40:51.134122
4669 04:40:51.137145 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4670 04:40:51.140425 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4671 04:40:51.143574 [Gating] SW calibration Done
4672 04:40:51.143656 ==
4673 04:40:51.147249 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 04:40:51.150418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 04:40:51.153842 ==
4676 04:40:51.153923 RX Vref Scan: 0
4677 04:40:51.153994
4678 04:40:51.156997 RX Vref 0 -> 0, step: 1
4679 04:40:51.157078
4680 04:40:51.160532 RX Delay -230 -> 252, step: 16
4681 04:40:51.163604 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4682 04:40:51.167319 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4683 04:40:51.170399 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4684 04:40:51.174087 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4685 04:40:51.180432 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4686 04:40:51.183814 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4687 04:40:51.187358 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4688 04:40:51.190314 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4689 04:40:51.196877 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4690 04:40:51.200285 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4691 04:40:51.203873 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4692 04:40:51.206799 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4693 04:40:51.213989 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4694 04:40:51.217662 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4695 04:40:51.220430 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4696 04:40:51.223759 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4697 04:40:51.223841 ==
4698 04:40:51.227174 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 04:40:51.234010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 04:40:51.234136 ==
4701 04:40:51.234200 DQS Delay:
4702 04:40:51.234260 DQS0 = 0, DQS1 = 0
4703 04:40:51.237241 DQM Delay:
4704 04:40:51.237335 DQM0 = 40, DQM1 = 36
4705 04:40:51.240690 DQ Delay:
4706 04:40:51.244112 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4707 04:40:51.244192 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4708 04:40:51.247013 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4709 04:40:51.250508 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4710 04:40:51.254151
4711 04:40:51.254228
4712 04:40:51.254290 ==
4713 04:40:51.257126 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 04:40:51.260861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 04:40:51.260939 ==
4716 04:40:51.261002
4717 04:40:51.261068
4718 04:40:51.263886 TX Vref Scan disable
4719 04:40:51.263960 == TX Byte 0 ==
4720 04:40:51.270600 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 04:40:51.274032 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 04:40:51.274108 == TX Byte 1 ==
4723 04:40:51.280544 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4724 04:40:51.283905 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4725 04:40:51.283990 ==
4726 04:40:51.287068 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 04:40:51.290392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 04:40:51.290481 ==
4729 04:40:51.290545
4730 04:40:51.290603
4731 04:40:51.294099 TX Vref Scan disable
4732 04:40:51.297320 == TX Byte 0 ==
4733 04:40:51.301362 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4734 04:40:51.304554 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4735 04:40:51.307472 == TX Byte 1 ==
4736 04:40:51.310948 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4737 04:40:51.314293 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4738 04:40:51.314379
4739 04:40:51.317626 [DATLAT]
4740 04:40:51.317710 Freq=600, CH1 RK1
4741 04:40:51.317776
4742 04:40:51.320596 DATLAT Default: 0x9
4743 04:40:51.320729 0, 0xFFFF, sum = 0
4744 04:40:51.324248 1, 0xFFFF, sum = 0
4745 04:40:51.324327 2, 0xFFFF, sum = 0
4746 04:40:51.327209 3, 0xFFFF, sum = 0
4747 04:40:51.327300 4, 0xFFFF, sum = 0
4748 04:40:51.330813 5, 0xFFFF, sum = 0
4749 04:40:51.330890 6, 0xFFFF, sum = 0
4750 04:40:51.334251 7, 0xFFFF, sum = 0
4751 04:40:51.334328 8, 0x0, sum = 1
4752 04:40:51.337423 9, 0x0, sum = 2
4753 04:40:51.337540 10, 0x0, sum = 3
4754 04:40:51.340863 11, 0x0, sum = 4
4755 04:40:51.340954 best_step = 9
4756 04:40:51.341020
4757 04:40:51.341080 ==
4758 04:40:51.344344 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 04:40:51.347227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 04:40:51.347307 ==
4761 04:40:51.350773 RX Vref Scan: 0
4762 04:40:51.350857
4763 04:40:51.353924 RX Vref 0 -> 0, step: 1
4764 04:40:51.354001
4765 04:40:51.354072 RX Delay -179 -> 252, step: 8
4766 04:40:51.361799 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4767 04:40:51.365232 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4768 04:40:51.368989 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4769 04:40:51.372486 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4770 04:40:51.378769 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4771 04:40:51.382453 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4772 04:40:51.385464 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4773 04:40:51.389053 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4774 04:40:51.392647 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4775 04:40:51.399089 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4776 04:40:51.401974 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4777 04:40:51.405830 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4778 04:40:51.409154 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4779 04:40:51.415670 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4780 04:40:51.418753 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4781 04:40:51.422285 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4782 04:40:51.422367 ==
4783 04:40:51.425513 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 04:40:51.428938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 04:40:51.429021 ==
4786 04:40:51.432702 DQS Delay:
4787 04:40:51.432797 DQS0 = 0, DQS1 = 0
4788 04:40:51.435880 DQM Delay:
4789 04:40:51.435962 DQM0 = 38, DQM1 = 33
4790 04:40:51.436025 DQ Delay:
4791 04:40:51.438791 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4792 04:40:51.442485 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4793 04:40:51.446066 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4794 04:40:51.448829 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4795 04:40:51.448930
4796 04:40:51.449026
4797 04:40:51.459101 [DQSOSCAuto] RK1, (LSB)MR18= 0x3140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4798 04:40:51.462762 CH1 RK1: MR19=808, MR18=3140
4799 04:40:51.465501 CH1_RK1: MR19=0x808, MR18=0x3140, DQSOSC=397, MR23=63, INC=166, DEC=110
4800 04:40:51.468970 [RxdqsGatingPostProcess] freq 600
4801 04:40:51.475632 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4802 04:40:51.479372 Pre-setting of DQS Precalculation
4803 04:40:51.482616 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4804 04:40:51.492643 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4805 04:40:51.499321 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4806 04:40:51.499445
4807 04:40:51.499539
4808 04:40:51.502522 [Calibration Summary] 1200 Mbps
4809 04:40:51.502622 CH 0, Rank 0
4810 04:40:51.505998 SW Impedance : PASS
4811 04:40:51.506097 DUTY Scan : NO K
4812 04:40:51.509304 ZQ Calibration : PASS
4813 04:40:51.512387 Jitter Meter : NO K
4814 04:40:51.512501 CBT Training : PASS
4815 04:40:51.515786 Write leveling : PASS
4816 04:40:51.515861 RX DQS gating : PASS
4817 04:40:51.518998 RX DQ/DQS(RDDQC) : PASS
4818 04:40:51.522425 TX DQ/DQS : PASS
4819 04:40:51.522537 RX DATLAT : PASS
4820 04:40:51.526136 RX DQ/DQS(Engine): PASS
4821 04:40:51.529212 TX OE : NO K
4822 04:40:51.529288 All Pass.
4823 04:40:51.529363
4824 04:40:51.529433 CH 0, Rank 1
4825 04:40:51.532253 SW Impedance : PASS
4826 04:40:51.535976 DUTY Scan : NO K
4827 04:40:51.536089 ZQ Calibration : PASS
4828 04:40:51.539212 Jitter Meter : NO K
4829 04:40:51.542706 CBT Training : PASS
4830 04:40:51.542817 Write leveling : PASS
4831 04:40:51.546205 RX DQS gating : PASS
4832 04:40:51.549712 RX DQ/DQS(RDDQC) : PASS
4833 04:40:51.549787 TX DQ/DQS : PASS
4834 04:40:51.552562 RX DATLAT : PASS
4835 04:40:51.552661 RX DQ/DQS(Engine): PASS
4836 04:40:51.555801 TX OE : NO K
4837 04:40:51.555893 All Pass.
4838 04:40:51.555965
4839 04:40:51.559177 CH 1, Rank 0
4840 04:40:51.559292 SW Impedance : PASS
4841 04:40:51.562869 DUTY Scan : NO K
4842 04:40:51.566165 ZQ Calibration : PASS
4843 04:40:51.566255 Jitter Meter : NO K
4844 04:40:51.569678 CBT Training : PASS
4845 04:40:51.572568 Write leveling : PASS
4846 04:40:51.572698 RX DQS gating : PASS
4847 04:40:51.575940 RX DQ/DQS(RDDQC) : PASS
4848 04:40:51.579363 TX DQ/DQS : PASS
4849 04:40:51.579475 RX DATLAT : PASS
4850 04:40:51.582756 RX DQ/DQS(Engine): PASS
4851 04:40:51.586078 TX OE : NO K
4852 04:40:51.586162 All Pass.
4853 04:40:51.586233
4854 04:40:51.586292 CH 1, Rank 1
4855 04:40:51.589601 SW Impedance : PASS
4856 04:40:51.592569 DUTY Scan : NO K
4857 04:40:51.592726 ZQ Calibration : PASS
4858 04:40:51.596122 Jitter Meter : NO K
4859 04:40:51.596202 CBT Training : PASS
4860 04:40:51.599197 Write leveling : PASS
4861 04:40:51.602820 RX DQS gating : PASS
4862 04:40:51.602935 RX DQ/DQS(RDDQC) : PASS
4863 04:40:51.605814 TX DQ/DQS : PASS
4864 04:40:51.609364 RX DATLAT : PASS
4865 04:40:51.609454 RX DQ/DQS(Engine): PASS
4866 04:40:51.612975 TX OE : NO K
4867 04:40:51.613067 All Pass.
4868 04:40:51.613132
4869 04:40:51.615984 DramC Write-DBI off
4870 04:40:51.619585 PER_BANK_REFRESH: Hybrid Mode
4871 04:40:51.619694 TX_TRACKING: ON
4872 04:40:51.629506 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4873 04:40:51.632857 [FAST_K] Save calibration result to emmc
4874 04:40:51.636148 dramc_set_vcore_voltage set vcore to 662500
4875 04:40:51.639504 Read voltage for 933, 3
4876 04:40:51.639578 Vio18 = 0
4877 04:40:51.639641 Vcore = 662500
4878 04:40:51.643054 Vdram = 0
4879 04:40:51.643146 Vddq = 0
4880 04:40:51.643258 Vmddr = 0
4881 04:40:51.649364 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4882 04:40:51.652823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4883 04:40:51.656583 MEM_TYPE=3, freq_sel=17
4884 04:40:51.659417 sv_algorithm_assistance_LP4_1600
4885 04:40:51.663070 ============ PULL DRAM RESETB DOWN ============
4886 04:40:51.666155 ========== PULL DRAM RESETB DOWN end =========
4887 04:40:51.673138 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4888 04:40:51.676085 ===================================
4889 04:40:51.676167 LPDDR4 DRAM CONFIGURATION
4890 04:40:51.679509 ===================================
4891 04:40:51.682820 EX_ROW_EN[0] = 0x0
4892 04:40:51.686269 EX_ROW_EN[1] = 0x0
4893 04:40:51.686346 LP4Y_EN = 0x0
4894 04:40:51.689595 WORK_FSP = 0x0
4895 04:40:51.689675 WL = 0x3
4896 04:40:51.692743 RL = 0x3
4897 04:40:51.692845 BL = 0x2
4898 04:40:51.696336 RPST = 0x0
4899 04:40:51.696414 RD_PRE = 0x0
4900 04:40:51.699906 WR_PRE = 0x1
4901 04:40:51.699992 WR_PST = 0x0
4902 04:40:51.702938 DBI_WR = 0x0
4903 04:40:51.703026 DBI_RD = 0x0
4904 04:40:51.706564 OTF = 0x1
4905 04:40:51.709474 ===================================
4906 04:40:51.713043 ===================================
4907 04:40:51.713156 ANA top config
4908 04:40:51.716950 ===================================
4909 04:40:51.719700 DLL_ASYNC_EN = 0
4910 04:40:51.723251 ALL_SLAVE_EN = 1
4911 04:40:51.723334 NEW_RANK_MODE = 1
4912 04:40:51.726355 DLL_IDLE_MODE = 1
4913 04:40:51.729789 LP45_APHY_COMB_EN = 1
4914 04:40:51.733361 TX_ODT_DIS = 1
4915 04:40:51.733439 NEW_8X_MODE = 1
4916 04:40:51.736542 ===================================
4917 04:40:51.740175 ===================================
4918 04:40:51.743343 data_rate = 1866
4919 04:40:51.746638 CKR = 1
4920 04:40:51.749707 DQ_P2S_RATIO = 8
4921 04:40:51.753128 ===================================
4922 04:40:51.756368 CA_P2S_RATIO = 8
4923 04:40:51.760008 DQ_CA_OPEN = 0
4924 04:40:51.760088 DQ_SEMI_OPEN = 0
4925 04:40:51.763114 CA_SEMI_OPEN = 0
4926 04:40:51.766502 CA_FULL_RATE = 0
4927 04:40:51.769954 DQ_CKDIV4_EN = 1
4928 04:40:51.773218 CA_CKDIV4_EN = 1
4929 04:40:51.776302 CA_PREDIV_EN = 0
4930 04:40:51.776386 PH8_DLY = 0
4931 04:40:51.779936 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4932 04:40:51.783285 DQ_AAMCK_DIV = 4
4933 04:40:51.786313 CA_AAMCK_DIV = 4
4934 04:40:51.790097 CA_ADMCK_DIV = 4
4935 04:40:51.793456 DQ_TRACK_CA_EN = 0
4936 04:40:51.793544 CA_PICK = 933
4937 04:40:51.796547 CA_MCKIO = 933
4938 04:40:51.799799 MCKIO_SEMI = 0
4939 04:40:51.803034 PLL_FREQ = 3732
4940 04:40:51.806441 DQ_UI_PI_RATIO = 32
4941 04:40:51.809955 CA_UI_PI_RATIO = 0
4942 04:40:51.813453 ===================================
4943 04:40:51.817402 ===================================
4944 04:40:51.817494 memory_type:LPDDR4
4945 04:40:51.820172 GP_NUM : 10
4946 04:40:51.823124 SRAM_EN : 1
4947 04:40:51.823226 MD32_EN : 0
4948 04:40:51.826614 ===================================
4949 04:40:51.830409 [ANA_INIT] >>>>>>>>>>>>>>
4950 04:40:51.833806 <<<<<< [CONFIGURE PHASE]: ANA_TX
4951 04:40:51.836602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4952 04:40:51.840132 ===================================
4953 04:40:51.843153 data_rate = 1866,PCW = 0X8f00
4954 04:40:51.846926 ===================================
4955 04:40:51.849876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4956 04:40:51.853486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 04:40:51.859983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 04:40:51.863600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4959 04:40:51.866983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4960 04:40:51.869784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4961 04:40:51.873111 [ANA_INIT] flow start
4962 04:40:51.876633 [ANA_INIT] PLL >>>>>>>>
4963 04:40:51.876731 [ANA_INIT] PLL <<<<<<<<
4964 04:40:51.879852 [ANA_INIT] MIDPI >>>>>>>>
4965 04:40:51.883364 [ANA_INIT] MIDPI <<<<<<<<
4966 04:40:51.883474 [ANA_INIT] DLL >>>>>>>>
4967 04:40:51.886911 [ANA_INIT] flow end
4968 04:40:51.890082 ============ LP4 DIFF to SE enter ============
4969 04:40:51.893184 ============ LP4 DIFF to SE exit ============
4970 04:40:51.896814 [ANA_INIT] <<<<<<<<<<<<<
4971 04:40:51.899841 [Flow] Enable top DCM control >>>>>
4972 04:40:51.903731 [Flow] Enable top DCM control <<<<<
4973 04:40:51.906511 Enable DLL master slave shuffle
4974 04:40:51.913142 ==============================================================
4975 04:40:51.913223 Gating Mode config
4976 04:40:51.920153 ==============================================================
4977 04:40:51.920258 Config description:
4978 04:40:51.930310 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4979 04:40:51.936921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4980 04:40:51.943799 SELPH_MODE 0: By rank 1: By Phase
4981 04:40:51.946685 ==============================================================
4982 04:40:51.950464 GAT_TRACK_EN = 1
4983 04:40:51.953478 RX_GATING_MODE = 2
4984 04:40:51.956974 RX_GATING_TRACK_MODE = 2
4985 04:40:51.960026 SELPH_MODE = 1
4986 04:40:51.963508 PICG_EARLY_EN = 1
4987 04:40:51.966713 VALID_LAT_VALUE = 1
4988 04:40:51.973206 ==============================================================
4989 04:40:51.976875 Enter into Gating configuration >>>>
4990 04:40:51.976991 Exit from Gating configuration <<<<
4991 04:40:51.979791 Enter into DVFS_PRE_config >>>>>
4992 04:40:51.993583 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4993 04:40:51.996976 Exit from DVFS_PRE_config <<<<<
4994 04:40:51.999824 Enter into PICG configuration >>>>
4995 04:40:52.003274 Exit from PICG configuration <<<<
4996 04:40:52.003368 [RX_INPUT] configuration >>>>>
4997 04:40:52.006517 [RX_INPUT] configuration <<<<<
4998 04:40:52.013313 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4999 04:40:52.016541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5000 04:40:52.023481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 04:40:52.030416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 04:40:52.036773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 04:40:52.043651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 04:40:52.046703 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5005 04:40:52.050194 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5006 04:40:52.053901 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5007 04:40:52.060434 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5008 04:40:52.063589 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5009 04:40:52.067152 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 04:40:52.070121 ===================================
5011 04:40:52.073719 LPDDR4 DRAM CONFIGURATION
5012 04:40:52.076536 ===================================
5013 04:40:52.080261 EX_ROW_EN[0] = 0x0
5014 04:40:52.080363 EX_ROW_EN[1] = 0x0
5015 04:40:52.083157 LP4Y_EN = 0x0
5016 04:40:52.083256 WORK_FSP = 0x0
5017 04:40:52.086737 WL = 0x3
5018 04:40:52.086842 RL = 0x3
5019 04:40:52.089899 BL = 0x2
5020 04:40:52.089973 RPST = 0x0
5021 04:40:52.093453 RD_PRE = 0x0
5022 04:40:52.093523 WR_PRE = 0x1
5023 04:40:52.097186 WR_PST = 0x0
5024 04:40:52.097271 DBI_WR = 0x0
5025 04:40:52.099967 DBI_RD = 0x0
5026 04:40:52.100063 OTF = 0x1
5027 04:40:52.103404 ===================================
5028 04:40:52.110065 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5029 04:40:52.113054 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5030 04:40:52.116461 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 04:40:52.120062 ===================================
5032 04:40:52.123072 LPDDR4 DRAM CONFIGURATION
5033 04:40:52.126649 ===================================
5034 04:40:52.126733 EX_ROW_EN[0] = 0x10
5035 04:40:52.129937 EX_ROW_EN[1] = 0x0
5036 04:40:52.133280 LP4Y_EN = 0x0
5037 04:40:52.133364 WORK_FSP = 0x0
5038 04:40:52.136264 WL = 0x3
5039 04:40:52.136348 RL = 0x3
5040 04:40:52.139772 BL = 0x2
5041 04:40:52.139857 RPST = 0x0
5042 04:40:52.142822 RD_PRE = 0x0
5043 04:40:52.142908 WR_PRE = 0x1
5044 04:40:52.146852 WR_PST = 0x0
5045 04:40:52.146936 DBI_WR = 0x0
5046 04:40:52.149703 DBI_RD = 0x0
5047 04:40:52.149786 OTF = 0x1
5048 04:40:52.153257 ===================================
5049 04:40:52.160316 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5050 04:40:52.164210 nWR fixed to 30
5051 04:40:52.167171 [ModeRegInit_LP4] CH0 RK0
5052 04:40:52.167254 [ModeRegInit_LP4] CH0 RK1
5053 04:40:52.170762 [ModeRegInit_LP4] CH1 RK0
5054 04:40:52.173872 [ModeRegInit_LP4] CH1 RK1
5055 04:40:52.173951 match AC timing 9
5056 04:40:52.180862 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5057 04:40:52.184202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5058 04:40:52.187277 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5059 04:40:52.194591 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5060 04:40:52.197394 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5061 04:40:52.197467 ==
5062 04:40:52.200949 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 04:40:52.204161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 04:40:52.204231 ==
5065 04:40:52.210571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 04:40:52.217301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5067 04:40:52.220829 [CA 0] Center 38 (8~69) winsize 62
5068 04:40:52.224328 [CA 1] Center 37 (7~68) winsize 62
5069 04:40:52.227256 [CA 2] Center 35 (5~66) winsize 62
5070 04:40:52.230759 [CA 3] Center 34 (4~65) winsize 62
5071 04:40:52.234599 [CA 4] Center 34 (4~65) winsize 62
5072 04:40:52.237488 [CA 5] Center 34 (4~64) winsize 61
5073 04:40:52.237559
5074 04:40:52.240958 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5075 04:40:52.241033
5076 04:40:52.244289 [CATrainingPosCal] consider 1 rank data
5077 04:40:52.247464 u2DelayCellTimex100 = 270/100 ps
5078 04:40:52.250733 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5079 04:40:52.254433 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5080 04:40:52.257276 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5081 04:40:52.260558 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5082 04:40:52.264168 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 04:40:52.267295 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5084 04:40:52.267396
5085 04:40:52.273911 CA PerBit enable=1, Macro0, CA PI delay=34
5086 04:40:52.273988
5087 04:40:52.274051 [CBTSetCACLKResult] CA Dly = 34
5088 04:40:52.277303 CS Dly: 6 (0~37)
5089 04:40:52.277402 ==
5090 04:40:52.280955 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 04:40:52.284044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 04:40:52.284122 ==
5093 04:40:52.290669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 04:40:52.297193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5095 04:40:52.300811 [CA 0] Center 38 (7~69) winsize 63
5096 04:40:52.304497 [CA 1] Center 38 (7~69) winsize 63
5097 04:40:52.307389 [CA 2] Center 35 (5~66) winsize 62
5098 04:40:52.310796 [CA 3] Center 35 (4~66) winsize 63
5099 04:40:52.314500 [CA 4] Center 34 (3~65) winsize 63
5100 04:40:52.317635 [CA 5] Center 33 (3~64) winsize 62
5101 04:40:52.317707
5102 04:40:52.321075 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5103 04:40:52.321145
5104 04:40:52.323961 [CATrainingPosCal] consider 2 rank data
5105 04:40:52.327451 u2DelayCellTimex100 = 270/100 ps
5106 04:40:52.330977 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5107 04:40:52.333998 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5108 04:40:52.337567 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5109 04:40:52.340528 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5110 04:40:52.344100 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5111 04:40:52.347815 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5112 04:40:52.347941
5113 04:40:52.350705 CA PerBit enable=1, Macro0, CA PI delay=34
5114 04:40:52.354053
5115 04:40:52.354135 [CBTSetCACLKResult] CA Dly = 34
5116 04:40:52.357927 CS Dly: 7 (0~39)
5117 04:40:52.358010
5118 04:40:52.361126 ----->DramcWriteLeveling(PI) begin...
5119 04:40:52.361210 ==
5120 04:40:52.364181 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 04:40:52.367542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 04:40:52.367646 ==
5123 04:40:52.370764 Write leveling (Byte 0): 29 => 29
5124 04:40:52.374265 Write leveling (Byte 1): 27 => 27
5125 04:40:52.378009 DramcWriteLeveling(PI) end<-----
5126 04:40:52.378082
5127 04:40:52.378160 ==
5128 04:40:52.380508 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 04:40:52.384075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 04:40:52.384148 ==
5131 04:40:52.387810 [Gating] SW mode calibration
5132 04:40:52.394349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5133 04:40:52.400930 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5134 04:40:52.404389 0 14 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
5135 04:40:52.410998 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5136 04:40:52.414314 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 04:40:52.417801 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 04:40:52.424261 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 04:40:52.427274 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 04:40:52.430736 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 04:40:52.434294 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5142 04:40:52.440814 0 15 0 | B1->B0 | 3131 2929 | 0 0 | (0 1) (1 0)
5143 04:40:52.444465 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 04:40:52.447539 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 04:40:52.454177 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 04:40:52.457756 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 04:40:52.460919 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 04:40:52.467918 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 04:40:52.470989 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 04:40:52.474557 1 0 0 | B1->B0 | 2a2a 3c3c | 0 0 | (0 0) (0 0)
5151 04:40:52.480946 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 04:40:52.484176 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 04:40:52.487712 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 04:40:52.494627 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 04:40:52.497844 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 04:40:52.501251 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 04:40:52.508082 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 04:40:52.511031 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 04:40:52.514571 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5160 04:40:52.518392 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 04:40:52.524550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 04:40:52.528112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 04:40:52.531280 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 04:40:52.538015 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 04:40:52.540968 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 04:40:52.544705 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 04:40:52.551252 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 04:40:52.554231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 04:40:52.557944 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 04:40:52.564468 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 04:40:52.567632 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 04:40:52.571212 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 04:40:52.578171 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 04:40:52.581303 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5175 04:40:52.584316 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5176 04:40:52.588017 Total UI for P1: 0, mck2ui 16
5177 04:40:52.591287 best dqsien dly found for B0: ( 1, 3, 0)
5178 04:40:52.594421 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 04:40:52.598037 Total UI for P1: 0, mck2ui 16
5180 04:40:52.601222 best dqsien dly found for B1: ( 1, 3, 4)
5181 04:40:52.604476 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5182 04:40:52.607746 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5183 04:40:52.611254
5184 04:40:52.614348 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5185 04:40:52.618145 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5186 04:40:52.618225 [Gating] SW calibration Done
5187 04:40:52.621171 ==
5188 04:40:52.624574 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 04:40:52.627788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 04:40:52.627863 ==
5191 04:40:52.627926 RX Vref Scan: 0
5192 04:40:52.627992
5193 04:40:52.631357 RX Vref 0 -> 0, step: 1
5194 04:40:52.631455
5195 04:40:52.634747 RX Delay -80 -> 252, step: 8
5196 04:40:52.638560 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5197 04:40:52.641304 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5198 04:40:52.644885 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5199 04:40:52.651439 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5200 04:40:52.654896 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5201 04:40:52.657964 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5202 04:40:52.661497 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5203 04:40:52.664817 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5204 04:40:52.668119 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5205 04:40:52.671234 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5206 04:40:52.678283 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5207 04:40:52.681472 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5208 04:40:52.684655 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5209 04:40:52.688288 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5210 04:40:52.691740 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5211 04:40:52.698148 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5212 04:40:52.698241 ==
5213 04:40:52.701386 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 04:40:52.704714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 04:40:52.704810 ==
5216 04:40:52.704876 DQS Delay:
5217 04:40:52.708232 DQS0 = 0, DQS1 = 0
5218 04:40:52.708312 DQM Delay:
5219 04:40:52.711675 DQM0 = 97, DQM1 = 87
5220 04:40:52.711788 DQ Delay:
5221 04:40:52.714532 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5222 04:40:52.718106 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5223 04:40:52.721446 DQ8 =79, DQ9 =83, DQ10 =87, DQ11 =79
5224 04:40:52.725151 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5225 04:40:52.725229
5226 04:40:52.725301
5227 04:40:52.725362 ==
5228 04:40:52.728265 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 04:40:52.731428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 04:40:52.731505 ==
5231 04:40:52.734846
5232 04:40:52.734952
5233 04:40:52.735031 TX Vref Scan disable
5234 04:40:52.738185 == TX Byte 0 ==
5235 04:40:52.741237 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5236 04:40:52.744612 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5237 04:40:52.747896 == TX Byte 1 ==
5238 04:40:52.751521 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5239 04:40:52.754653 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5240 04:40:52.754730 ==
5241 04:40:52.758218 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 04:40:52.764592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 04:40:52.764676 ==
5244 04:40:52.764741
5245 04:40:52.764844
5246 04:40:52.764937 TX Vref Scan disable
5247 04:40:52.768728 == TX Byte 0 ==
5248 04:40:52.772416 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5249 04:40:52.776229 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5250 04:40:52.779101 == TX Byte 1 ==
5251 04:40:52.782636 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5252 04:40:52.785565 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5253 04:40:52.785656
5254 04:40:52.788929 [DATLAT]
5255 04:40:52.789002 Freq=933, CH0 RK0
5256 04:40:52.789063
5257 04:40:52.792611 DATLAT Default: 0xd
5258 04:40:52.792743 0, 0xFFFF, sum = 0
5259 04:40:52.795797 1, 0xFFFF, sum = 0
5260 04:40:52.795869 2, 0xFFFF, sum = 0
5261 04:40:52.799301 3, 0xFFFF, sum = 0
5262 04:40:52.799404 4, 0xFFFF, sum = 0
5263 04:40:52.802131 5, 0xFFFF, sum = 0
5264 04:40:52.802232 6, 0xFFFF, sum = 0
5265 04:40:52.805823 7, 0xFFFF, sum = 0
5266 04:40:52.809124 8, 0xFFFF, sum = 0
5267 04:40:52.809211 9, 0xFFFF, sum = 0
5268 04:40:52.809286 10, 0x0, sum = 1
5269 04:40:52.812607 11, 0x0, sum = 2
5270 04:40:52.812743 12, 0x0, sum = 3
5271 04:40:52.815527 13, 0x0, sum = 4
5272 04:40:52.815625 best_step = 11
5273 04:40:52.815698
5274 04:40:52.815759 ==
5275 04:40:52.819223 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 04:40:52.825725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 04:40:52.825803 ==
5278 04:40:52.825865 RX Vref Scan: 1
5279 04:40:52.825933
5280 04:40:52.829331 RX Vref 0 -> 0, step: 1
5281 04:40:52.829405
5282 04:40:52.832345 RX Delay -61 -> 252, step: 4
5283 04:40:52.832426
5284 04:40:52.835831 Set Vref, RX VrefLevel [Byte0]: 53
5285 04:40:52.839130 [Byte1]: 51
5286 04:40:52.839206
5287 04:40:52.842722 Final RX Vref Byte 0 = 53 to rank0
5288 04:40:52.846035 Final RX Vref Byte 1 = 51 to rank0
5289 04:40:52.849025 Final RX Vref Byte 0 = 53 to rank1
5290 04:40:52.852506 Final RX Vref Byte 1 = 51 to rank1==
5291 04:40:52.855834 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 04:40:52.859267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 04:40:52.859383 ==
5294 04:40:52.862226 DQS Delay:
5295 04:40:52.862299 DQS0 = 0, DQS1 = 0
5296 04:40:52.862375 DQM Delay:
5297 04:40:52.865685 DQM0 = 97, DQM1 = 88
5298 04:40:52.865758 DQ Delay:
5299 04:40:52.868817 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5300 04:40:52.872411 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =102
5301 04:40:52.875492 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =80
5302 04:40:52.878964 DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =98
5303 04:40:52.879045
5304 04:40:52.879107
5305 04:40:52.889307 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5306 04:40:52.892219 CH0 RK0: MR19=504, MR18=12FD
5307 04:40:52.895637 CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5308 04:40:52.898650
5309 04:40:52.902077 ----->DramcWriteLeveling(PI) begin...
5310 04:40:52.902173 ==
5311 04:40:52.905702 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 04:40:52.908840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 04:40:52.908914 ==
5314 04:40:52.912038 Write leveling (Byte 0): 33 => 33
5315 04:40:52.915573 Write leveling (Byte 1): 28 => 28
5316 04:40:52.919191 DramcWriteLeveling(PI) end<-----
5317 04:40:52.919273
5318 04:40:52.919335 ==
5319 04:40:52.922473 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 04:40:52.925401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 04:40:52.925489 ==
5322 04:40:52.929156 [Gating] SW mode calibration
5323 04:40:52.935782 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5324 04:40:52.939449 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5325 04:40:52.945981 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
5326 04:40:52.948909 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5327 04:40:52.952309 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 04:40:52.959251 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 04:40:52.962730 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 04:40:52.965571 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 04:40:52.972413 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5332 04:40:52.975749 0 14 28 | B1->B0 | 3333 2626 | 0 0 | (0 0) (0 0)
5333 04:40:52.979060 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5334 04:40:52.985570 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 04:40:52.989191 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 04:40:52.992199 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 04:40:52.999121 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 04:40:53.003005 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 04:40:53.005603 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 04:40:53.012343 0 15 28 | B1->B0 | 2323 3232 | 1 0 | (0 0) (0 0)
5341 04:40:53.015686 1 0 0 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
5342 04:40:53.019208 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 04:40:53.025615 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 04:40:53.029117 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 04:40:53.032616 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 04:40:53.038905 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 04:40:53.042266 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5348 04:40:53.046213 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5349 04:40:53.049115 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 04:40:53.055777 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 04:40:53.059315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 04:40:53.062240 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 04:40:53.069138 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 04:40:53.072343 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 04:40:53.076164 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 04:40:53.082259 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 04:40:53.086397 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 04:40:53.089089 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 04:40:53.095690 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 04:40:53.099156 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 04:40:53.102569 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 04:40:53.109123 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 04:40:53.112586 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5364 04:40:53.115578 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5365 04:40:53.122602 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 04:40:53.122684 Total UI for P1: 0, mck2ui 16
5367 04:40:53.126172 best dqsien dly found for B0: ( 1, 2, 26)
5368 04:40:53.132656 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5369 04:40:53.136043 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 04:40:53.139043 Total UI for P1: 0, mck2ui 16
5371 04:40:53.142386 best dqsien dly found for B1: ( 1, 3, 2)
5372 04:40:53.146015 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5373 04:40:53.149374 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5374 04:40:53.149452
5375 04:40:53.152725 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5376 04:40:53.155582 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5377 04:40:53.159298 [Gating] SW calibration Done
5378 04:40:53.159373 ==
5379 04:40:53.162471 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 04:40:53.165621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 04:40:53.169101 ==
5382 04:40:53.169173 RX Vref Scan: 0
5383 04:40:53.169239
5384 04:40:53.172604 RX Vref 0 -> 0, step: 1
5385 04:40:53.172736
5386 04:40:53.175623 RX Delay -80 -> 252, step: 8
5387 04:40:53.179057 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5388 04:40:53.182519 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5389 04:40:53.185638 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5390 04:40:53.188975 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5391 04:40:53.192517 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5392 04:40:53.199054 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5393 04:40:53.202477 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5394 04:40:53.205790 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5395 04:40:53.208877 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5396 04:40:53.212375 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5397 04:40:53.215610 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5398 04:40:53.222179 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5399 04:40:53.225780 iDelay=200, Bit 12, Center 87 (-8 ~ 183) 192
5400 04:40:53.229197 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5401 04:40:53.232388 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5402 04:40:53.235515 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5403 04:40:53.235598 ==
5404 04:40:53.239270 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 04:40:53.245880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 04:40:53.245962 ==
5407 04:40:53.246027 DQS Delay:
5408 04:40:53.248878 DQS0 = 0, DQS1 = 0
5409 04:40:53.248959 DQM Delay:
5410 04:40:53.249025 DQM0 = 96, DQM1 = 87
5411 04:40:53.252801 DQ Delay:
5412 04:40:53.255976 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5413 04:40:53.259226 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5414 04:40:53.262156 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5415 04:40:53.266303 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5416 04:40:53.266377
5417 04:40:53.266438
5418 04:40:53.266495 ==
5419 04:40:53.269012 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 04:40:53.272580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 04:40:53.272701 ==
5422 04:40:53.272763
5423 04:40:53.272822
5424 04:40:53.275617 TX Vref Scan disable
5425 04:40:53.275681 == TX Byte 0 ==
5426 04:40:53.282756 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5427 04:40:53.285615 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5428 04:40:53.289298 == TX Byte 1 ==
5429 04:40:53.292217 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5430 04:40:53.295888 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5431 04:40:53.295967 ==
5432 04:40:53.298987 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 04:40:53.302504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 04:40:53.302574 ==
5435 04:40:53.302637
5436 04:40:53.305451
5437 04:40:53.305522 TX Vref Scan disable
5438 04:40:53.308863 == TX Byte 0 ==
5439 04:40:53.312289 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5440 04:40:53.315891 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5441 04:40:53.319795 == TX Byte 1 ==
5442 04:40:53.322243 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5443 04:40:53.326028 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5444 04:40:53.329307
5445 04:40:53.329429 [DATLAT]
5446 04:40:53.329501 Freq=933, CH0 RK1
5447 04:40:53.329577
5448 04:40:53.332183 DATLAT Default: 0xb
5449 04:40:53.332264 0, 0xFFFF, sum = 0
5450 04:40:53.335902 1, 0xFFFF, sum = 0
5451 04:40:53.335987 2, 0xFFFF, sum = 0
5452 04:40:53.339221 3, 0xFFFF, sum = 0
5453 04:40:53.339323 4, 0xFFFF, sum = 0
5454 04:40:53.342029 5, 0xFFFF, sum = 0
5455 04:40:53.345613 6, 0xFFFF, sum = 0
5456 04:40:53.345691 7, 0xFFFF, sum = 0
5457 04:40:53.348638 8, 0xFFFF, sum = 0
5458 04:40:53.348754 9, 0xFFFF, sum = 0
5459 04:40:53.352248 10, 0x0, sum = 1
5460 04:40:53.352352 11, 0x0, sum = 2
5461 04:40:53.352445 12, 0x0, sum = 3
5462 04:40:53.355700 13, 0x0, sum = 4
5463 04:40:53.355780 best_step = 11
5464 04:40:53.355846
5465 04:40:53.358898 ==
5466 04:40:53.358997 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 04:40:53.365061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 04:40:53.365137 ==
5469 04:40:53.365198 RX Vref Scan: 0
5470 04:40:53.365257
5471 04:40:53.368819 RX Vref 0 -> 0, step: 1
5472 04:40:53.368917
5473 04:40:53.372177 RX Delay -61 -> 252, step: 4
5474 04:40:53.375160 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5475 04:40:53.382335 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5476 04:40:53.385674 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5477 04:40:53.388661 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5478 04:40:53.392242 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5479 04:40:53.395710 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5480 04:40:53.398668 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5481 04:40:53.405379 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5482 04:40:53.408645 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5483 04:40:53.411979 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5484 04:40:53.414934 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5485 04:40:53.418802 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5486 04:40:53.421777 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5487 04:40:53.428380 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5488 04:40:53.432175 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5489 04:40:53.435010 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5490 04:40:53.435105 ==
5491 04:40:53.438272 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 04:40:53.441880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 04:40:53.441964 ==
5494 04:40:53.445050 DQS Delay:
5495 04:40:53.445133 DQS0 = 0, DQS1 = 0
5496 04:40:53.448700 DQM Delay:
5497 04:40:53.448794 DQM0 = 95, DQM1 = 87
5498 04:40:53.448861 DQ Delay:
5499 04:40:53.451568 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5500 04:40:53.455044 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =104
5501 04:40:53.458494 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =80
5502 04:40:53.462188 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =96
5503 04:40:53.462302
5504 04:40:53.462366
5505 04:40:53.472187 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5506 04:40:53.475588 CH0 RK1: MR19=505, MR18=1B09
5507 04:40:53.478601 CH0_RK1: MR19=0x505, MR18=0x1B09, DQSOSC=413, MR23=63, INC=63, DEC=42
5508 04:40:53.482272 [RxdqsGatingPostProcess] freq 933
5509 04:40:53.488628 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5510 04:40:53.492337 best DQS0 dly(2T, 0.5T) = (0, 11)
5511 04:40:53.496290 best DQS1 dly(2T, 0.5T) = (0, 11)
5512 04:40:53.498604 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5513 04:40:53.502133 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5514 04:40:53.505268 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 04:40:53.508737 best DQS1 dly(2T, 0.5T) = (0, 11)
5516 04:40:53.511729 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 04:40:53.515447 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5518 04:40:53.515526 Pre-setting of DQS Precalculation
5519 04:40:53.522249 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5520 04:40:53.522329 ==
5521 04:40:53.525617 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 04:40:53.528552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 04:40:53.528694 ==
5524 04:40:53.535184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 04:40:53.542136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 04:40:53.544944 [CA 0] Center 36 (6~67) winsize 62
5527 04:40:53.548384 [CA 1] Center 36 (6~67) winsize 62
5528 04:40:53.552167 [CA 2] Center 34 (4~64) winsize 61
5529 04:40:53.555645 [CA 3] Center 34 (4~64) winsize 61
5530 04:40:53.558929 [CA 4] Center 34 (4~65) winsize 62
5531 04:40:53.561736 [CA 5] Center 33 (3~64) winsize 62
5532 04:40:53.561806
5533 04:40:53.564986 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 04:40:53.565055
5535 04:40:53.568863 [CATrainingPosCal] consider 1 rank data
5536 04:40:53.571787 u2DelayCellTimex100 = 270/100 ps
5537 04:40:53.574933 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 04:40:53.578577 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5539 04:40:53.581896 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 04:40:53.585112 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5541 04:40:53.588851 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5542 04:40:53.592361 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5543 04:40:53.592437
5544 04:40:53.598714 CA PerBit enable=1, Macro0, CA PI delay=33
5545 04:40:53.598791
5546 04:40:53.598857 [CBTSetCACLKResult] CA Dly = 33
5547 04:40:53.601996 CS Dly: 4 (0~35)
5548 04:40:53.602070 ==
5549 04:40:53.604858 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 04:40:53.608785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 04:40:53.608857 ==
5552 04:40:53.615064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 04:40:53.621832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 04:40:53.624898 [CA 0] Center 36 (6~67) winsize 62
5555 04:40:53.629153 [CA 1] Center 36 (6~67) winsize 62
5556 04:40:53.631961 [CA 2] Center 33 (3~64) winsize 62
5557 04:40:53.635273 [CA 3] Center 33 (3~64) winsize 62
5558 04:40:53.638369 [CA 4] Center 34 (4~64) winsize 61
5559 04:40:53.641861 [CA 5] Center 32 (2~63) winsize 62
5560 04:40:53.641935
5561 04:40:53.645865 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 04:40:53.645945
5563 04:40:53.648427 [CATrainingPosCal] consider 2 rank data
5564 04:40:53.651549 u2DelayCellTimex100 = 270/100 ps
5565 04:40:53.655084 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 04:40:53.658755 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 04:40:53.661736 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 04:40:53.665230 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 04:40:53.668827 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5570 04:40:53.672135 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5571 04:40:53.672209
5572 04:40:53.675589 CA PerBit enable=1, Macro0, CA PI delay=33
5573 04:40:53.679021
5574 04:40:53.679144 [CBTSetCACLKResult] CA Dly = 33
5575 04:40:53.681817 CS Dly: 5 (0~38)
5576 04:40:53.681888
5577 04:40:53.685501 ----->DramcWriteLeveling(PI) begin...
5578 04:40:53.685575 ==
5579 04:40:53.689088 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 04:40:53.691909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 04:40:53.691981 ==
5582 04:40:53.695309 Write leveling (Byte 0): 29 => 29
5583 04:40:53.698927 Write leveling (Byte 1): 29 => 29
5584 04:40:53.702414 DramcWriteLeveling(PI) end<-----
5585 04:40:53.702494
5586 04:40:53.702555 ==
5587 04:40:53.705427 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 04:40:53.708623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 04:40:53.708730 ==
5590 04:40:53.712128 [Gating] SW mode calibration
5591 04:40:53.718708 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 04:40:53.725540 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5593 04:40:53.729114 0 14 0 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
5594 04:40:53.735615 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5595 04:40:53.739047 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 04:40:53.741966 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 04:40:53.748876 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 04:40:53.751967 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 04:40:53.755394 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5600 04:40:53.758916 0 14 28 | B1->B0 | 3131 3131 | 1 1 | (1 0) (1 0)
5601 04:40:53.765574 0 15 0 | B1->B0 | 2828 2929 | 0 0 | (0 0) (1 0)
5602 04:40:53.769016 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5603 04:40:53.771946 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 04:40:53.779334 0 15 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5605 04:40:53.782123 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 04:40:53.785370 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 04:40:53.791877 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5608 04:40:53.795378 0 15 28 | B1->B0 | 2d2d 2c2c | 0 0 | (0 0) (0 0)
5609 04:40:53.798780 1 0 0 | B1->B0 | 4545 4141 | 0 0 | (0 0) (1 1)
5610 04:40:53.805597 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 04:40:53.808946 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 04:40:53.812591 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 04:40:53.818803 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 04:40:53.822328 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 04:40:53.825306 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 04:40:53.831948 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5617 04:40:53.835588 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5618 04:40:53.838689 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 04:40:53.842250 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 04:40:53.849096 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 04:40:53.852300 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 04:40:53.855935 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 04:40:53.862442 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 04:40:53.865296 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 04:40:53.868906 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 04:40:53.875746 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 04:40:53.878592 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 04:40:53.882120 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 04:40:53.888936 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 04:40:53.892297 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 04:40:53.895284 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 04:40:53.902213 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5633 04:40:53.902292 Total UI for P1: 0, mck2ui 16
5634 04:40:53.908728 best dqsien dly found for B0: ( 1, 2, 26)
5635 04:40:53.912228 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 04:40:53.915291 Total UI for P1: 0, mck2ui 16
5637 04:40:53.919019 best dqsien dly found for B1: ( 1, 2, 28)
5638 04:40:53.922143 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5639 04:40:53.925260 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5640 04:40:53.925339
5641 04:40:53.928907 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5642 04:40:53.931891 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5643 04:40:53.935440 [Gating] SW calibration Done
5644 04:40:53.935515 ==
5645 04:40:53.939043 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 04:40:53.942023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 04:40:53.942094 ==
5648 04:40:53.945644 RX Vref Scan: 0
5649 04:40:53.945725
5650 04:40:53.948921 RX Vref 0 -> 0, step: 1
5651 04:40:53.948996
5652 04:40:53.949059 RX Delay -80 -> 252, step: 8
5653 04:40:53.955656 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5654 04:40:53.958505 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5655 04:40:53.962371 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5656 04:40:53.965306 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5657 04:40:53.968822 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5658 04:40:53.972307 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5659 04:40:53.979088 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5660 04:40:53.982120 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5661 04:40:53.985484 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5662 04:40:53.989246 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5663 04:40:53.991924 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5664 04:40:53.998566 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5665 04:40:54.002082 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5666 04:40:54.005318 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5667 04:40:54.009393 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5668 04:40:54.012047 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5669 04:40:54.012122 ==
5670 04:40:54.015479 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 04:40:54.018824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 04:40:54.022026 ==
5673 04:40:54.022100 DQS Delay:
5674 04:40:54.022164 DQS0 = 0, DQS1 = 0
5675 04:40:54.025392 DQM Delay:
5676 04:40:54.025476 DQM0 = 96, DQM1 = 88
5677 04:40:54.029082 DQ Delay:
5678 04:40:54.029195 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =99
5679 04:40:54.031937 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5680 04:40:54.035750 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5681 04:40:54.039047 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5682 04:40:54.042126
5683 04:40:54.042199
5684 04:40:54.042259 ==
5685 04:40:54.045699 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 04:40:54.048783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 04:40:54.048859 ==
5688 04:40:54.048920
5689 04:40:54.048976
5690 04:40:54.052426 TX Vref Scan disable
5691 04:40:54.052522 == TX Byte 0 ==
5692 04:40:54.058784 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5693 04:40:54.061910 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5694 04:40:54.061980 == TX Byte 1 ==
5695 04:40:54.068930 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5696 04:40:54.072027 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5697 04:40:54.072123 ==
5698 04:40:54.075387 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 04:40:54.079596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 04:40:54.079671 ==
5701 04:40:54.079733
5702 04:40:54.079791
5703 04:40:54.082535 TX Vref Scan disable
5704 04:40:54.085502 == TX Byte 0 ==
5705 04:40:54.088899 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5706 04:40:54.091885 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5707 04:40:54.095373 == TX Byte 1 ==
5708 04:40:54.098897 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5709 04:40:54.101862 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5710 04:40:54.101934
5711 04:40:54.105238 [DATLAT]
5712 04:40:54.105339 Freq=933, CH1 RK0
5713 04:40:54.105433
5714 04:40:54.108767 DATLAT Default: 0xd
5715 04:40:54.108838 0, 0xFFFF, sum = 0
5716 04:40:54.111835 1, 0xFFFF, sum = 0
5717 04:40:54.111908 2, 0xFFFF, sum = 0
5718 04:40:54.115364 3, 0xFFFF, sum = 0
5719 04:40:54.115440 4, 0xFFFF, sum = 0
5720 04:40:54.119123 5, 0xFFFF, sum = 0
5721 04:40:54.119195 6, 0xFFFF, sum = 0
5722 04:40:54.121883 7, 0xFFFF, sum = 0
5723 04:40:54.121952 8, 0xFFFF, sum = 0
5724 04:40:54.125562 9, 0xFFFF, sum = 0
5725 04:40:54.125631 10, 0x0, sum = 1
5726 04:40:54.128969 11, 0x0, sum = 2
5727 04:40:54.129081 12, 0x0, sum = 3
5728 04:40:54.131821 13, 0x0, sum = 4
5729 04:40:54.131896 best_step = 11
5730 04:40:54.131959
5731 04:40:54.132015 ==
5732 04:40:54.135269 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 04:40:54.138550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 04:40:54.142020 ==
5735 04:40:54.142089 RX Vref Scan: 1
5736 04:40:54.142148
5737 04:40:54.145971 RX Vref 0 -> 0, step: 1
5738 04:40:54.146057
5739 04:40:54.148805 RX Delay -69 -> 252, step: 4
5740 04:40:54.148888
5741 04:40:54.152388 Set Vref, RX VrefLevel [Byte0]: 57
5742 04:40:54.152469 [Byte1]: 52
5743 04:40:54.157413
5744 04:40:54.157493 Final RX Vref Byte 0 = 57 to rank0
5745 04:40:54.160656 Final RX Vref Byte 1 = 52 to rank0
5746 04:40:54.163937 Final RX Vref Byte 0 = 57 to rank1
5747 04:40:54.167154 Final RX Vref Byte 1 = 52 to rank1==
5748 04:40:54.170717 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 04:40:54.177436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 04:40:54.177518 ==
5751 04:40:54.177582 DQS Delay:
5752 04:40:54.177641 DQS0 = 0, DQS1 = 0
5753 04:40:54.180542 DQM Delay:
5754 04:40:54.180622 DQM0 = 97, DQM1 = 90
5755 04:40:54.183808 DQ Delay:
5756 04:40:54.187308 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5757 04:40:54.190774 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =94
5758 04:40:54.193609 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =86
5759 04:40:54.197240 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =94
5760 04:40:54.197320
5761 04:40:54.197384
5762 04:40:54.203860 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5763 04:40:54.207193 CH1 RK0: MR19=504, MR18=17F3
5764 04:40:54.213948 CH1_RK0: MR19=0x504, MR18=0x17F3, DQSOSC=414, MR23=63, INC=63, DEC=42
5765 04:40:54.214053
5766 04:40:54.217394 ----->DramcWriteLeveling(PI) begin...
5767 04:40:54.217514 ==
5768 04:40:54.220934 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 04:40:54.224043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 04:40:54.224146 ==
5771 04:40:54.226875 Write leveling (Byte 0): 31 => 31
5772 04:40:54.230867 Write leveling (Byte 1): 25 => 25
5773 04:40:54.233717 DramcWriteLeveling(PI) end<-----
5774 04:40:54.233790
5775 04:40:54.233851 ==
5776 04:40:54.237227 Dram Type= 6, Freq= 0, CH_1, rank 1
5777 04:40:54.240435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 04:40:54.240542 ==
5779 04:40:54.243659 [Gating] SW mode calibration
5780 04:40:54.250187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5781 04:40:54.256907 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5782 04:40:54.260355 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 04:40:54.263542 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 04:40:54.270161 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 04:40:54.273934 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5786 04:40:54.277166 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5787 04:40:54.283492 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 04:40:54.287361 0 14 24 | B1->B0 | 3131 2a2a | 1 1 | (1 0) (1 0)
5789 04:40:54.290722 0 14 28 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5790 04:40:54.297266 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5791 04:40:54.300267 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 04:40:54.303843 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 04:40:54.310072 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 04:40:54.313559 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 04:40:54.317247 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5796 04:40:54.324001 0 15 24 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
5797 04:40:54.327489 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
5798 04:40:54.330534 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 04:40:54.337366 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 04:40:54.340316 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 04:40:54.343746 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 04:40:54.350211 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 04:40:54.353786 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5804 04:40:54.357260 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5805 04:40:54.360208 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 04:40:54.367111 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5807 04:40:54.370493 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 04:40:54.374185 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 04:40:54.380963 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 04:40:54.384127 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 04:40:54.387474 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 04:40:54.393623 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 04:40:54.397485 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 04:40:54.400976 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 04:40:54.407305 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 04:40:54.410738 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 04:40:54.413730 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 04:40:54.420673 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 04:40:54.423867 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5820 04:40:54.427391 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5821 04:40:54.434054 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5822 04:40:54.434135 Total UI for P1: 0, mck2ui 16
5823 04:40:54.437634 best dqsien dly found for B0: ( 1, 2, 22)
5824 04:40:54.444198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 04:40:54.447595 Total UI for P1: 0, mck2ui 16
5826 04:40:54.450707 best dqsien dly found for B1: ( 1, 2, 28)
5827 04:40:54.454001 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5828 04:40:54.457260 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5829 04:40:54.457341
5830 04:40:54.460471 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5831 04:40:54.464262 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5832 04:40:54.467582 [Gating] SW calibration Done
5833 04:40:54.467663 ==
5834 04:40:54.470796 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 04:40:54.474284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 04:40:54.474367 ==
5837 04:40:54.477363 RX Vref Scan: 0
5838 04:40:54.477445
5839 04:40:54.477507 RX Vref 0 -> 0, step: 1
5840 04:40:54.481327
5841 04:40:54.481408 RX Delay -80 -> 252, step: 8
5842 04:40:54.484267 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5843 04:40:54.490953 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5844 04:40:54.493946 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5845 04:40:54.497576 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5846 04:40:54.501198 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5847 04:40:54.504291 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5848 04:40:54.507123 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5849 04:40:54.514305 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5850 04:40:54.517334 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5851 04:40:54.520928 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5852 04:40:54.523913 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5853 04:40:54.527468 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5854 04:40:54.534092 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5855 04:40:54.537411 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5856 04:40:54.540658 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5857 04:40:54.544299 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5858 04:40:54.544380 ==
5859 04:40:54.547589 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 04:40:54.550854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 04:40:54.550937 ==
5862 04:40:54.553920 DQS Delay:
5863 04:40:54.554002 DQS0 = 0, DQS1 = 0
5864 04:40:54.557712 DQM Delay:
5865 04:40:54.557792 DQM0 = 94, DQM1 = 88
5866 04:40:54.557856 DQ Delay:
5867 04:40:54.561320 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5868 04:40:54.564201 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5869 04:40:54.567401 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5870 04:40:54.570617 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5871 04:40:54.570698
5872 04:40:54.570761
5873 04:40:54.574254 ==
5874 04:40:54.574335 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 04:40:54.580771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 04:40:54.580852 ==
5877 04:40:54.580915
5878 04:40:54.580973
5879 04:40:54.581028 TX Vref Scan disable
5880 04:40:54.584901 == TX Byte 0 ==
5881 04:40:54.587849 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5882 04:40:54.594829 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5883 04:40:54.594910 == TX Byte 1 ==
5884 04:40:54.597899 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5885 04:40:54.604460 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5886 04:40:54.604541 ==
5887 04:40:54.608320 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 04:40:54.611686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 04:40:54.611767 ==
5890 04:40:54.611830
5891 04:40:54.611888
5892 04:40:54.614650 TX Vref Scan disable
5893 04:40:54.614730 == TX Byte 0 ==
5894 04:40:54.621286 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5895 04:40:54.624883 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5896 04:40:54.624965 == TX Byte 1 ==
5897 04:40:54.631472 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5898 04:40:54.634767 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5899 04:40:54.634848
5900 04:40:54.634912 [DATLAT]
5901 04:40:54.638239 Freq=933, CH1 RK1
5902 04:40:54.638320
5903 04:40:54.638383 DATLAT Default: 0xb
5904 04:40:54.641605 0, 0xFFFF, sum = 0
5905 04:40:54.641688 1, 0xFFFF, sum = 0
5906 04:40:54.644894 2, 0xFFFF, sum = 0
5907 04:40:54.644976 3, 0xFFFF, sum = 0
5908 04:40:54.648385 4, 0xFFFF, sum = 0
5909 04:40:54.648467 5, 0xFFFF, sum = 0
5910 04:40:54.651698 6, 0xFFFF, sum = 0
5911 04:40:54.651780 7, 0xFFFF, sum = 0
5912 04:40:54.654687 8, 0xFFFF, sum = 0
5913 04:40:54.654769 9, 0xFFFF, sum = 0
5914 04:40:54.658162 10, 0x0, sum = 1
5915 04:40:54.658244 11, 0x0, sum = 2
5916 04:40:54.661971 12, 0x0, sum = 3
5917 04:40:54.662053 13, 0x0, sum = 4
5918 04:40:54.665121 best_step = 11
5919 04:40:54.665201
5920 04:40:54.665264 ==
5921 04:40:54.667960 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 04:40:54.671490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 04:40:54.671569 ==
5924 04:40:54.674702 RX Vref Scan: 0
5925 04:40:54.674773
5926 04:40:54.674836 RX Vref 0 -> 0, step: 1
5927 04:40:54.674897
5928 04:41:04.894717 RX Delay -61 -> 252, step: 4
5929 04:41:04.894856 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5930 04:41:04.894925 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5931 04:41:04.894991 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5932 04:41:04.895049 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5933 04:41:04.895105 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5934 04:41:04.895160 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5935 04:41:04.895218 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5936 04:41:04.895273 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5937 04:41:04.895331 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5938 04:41:04.895385 iDelay=199, Bit 9, Center 82 (-5 ~ 170) 176
5939 04:41:04.895477 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5940 04:41:04.895564 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5941 04:41:04.895620 iDelay=199, Bit 12, Center 94 (3 ~ 186) 184
5942 04:41:04.895676 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5943 04:41:04.895729 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5944 04:41:04.895781 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5945 04:41:04.895832 ==
5946 04:41:04.895886 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 04:41:04.895941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 04:41:04.896036 ==
5949 04:41:04.896090 DQS Delay:
5950 04:41:04.896144 DQS0 = 0, DQS1 = 0
5951 04:41:04.896199 DQM Delay:
5952 04:41:04.896252 DQM0 = 95, DQM1 = 90
5953 04:41:04.896304 DQ Delay:
5954 04:41:04.896355 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5955 04:41:04.896406 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5956 04:41:04.896470 DQ8 =80, DQ9 =82, DQ10 =90, DQ11 =84
5957 04:41:04.896574 DQ12 =94, DQ13 =98, DQ14 =98, DQ15 =98
5958 04:41:04.896661
5959 04:41:04.896764
5960 04:41:04.896834 [DQSOSCAuto] RK1, (LSB)MR18= 0xb14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5961 04:41:04.896889 CH1 RK1: MR19=505, MR18=B14
5962 04:41:04.896944 CH1_RK1: MR19=0x505, MR18=0xB14, DQSOSC=415, MR23=63, INC=62, DEC=41
5963 04:41:04.897000 [RxdqsGatingPostProcess] freq 933
5964 04:41:04.897057 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5965 04:41:04.897120 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 04:41:04.897178 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 04:41:04.897233 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 04:41:04.897288 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 04:41:04.897341 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 04:41:04.897392 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 04:41:04.897442 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 04:41:04.897530 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 04:41:04.897583 Pre-setting of DQS Precalculation
5974 04:41:04.897638 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5975 04:41:04.897694 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5976 04:41:04.897749 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5977 04:41:04.897805
5978 04:41:04.897859
5979 04:41:04.897911 [Calibration Summary] 1866 Mbps
5980 04:41:04.897966 CH 0, Rank 0
5981 04:41:04.898063 SW Impedance : PASS
5982 04:41:04.898118 DUTY Scan : NO K
5983 04:41:04.898171 ZQ Calibration : PASS
5984 04:41:04.898223 Jitter Meter : NO K
5985 04:41:04.898327 CBT Training : PASS
5986 04:41:04.898394 Write leveling : PASS
5987 04:41:04.898445 RX DQS gating : PASS
5988 04:41:04.898498 RX DQ/DQS(RDDQC) : PASS
5989 04:41:04.898551 TX DQ/DQS : PASS
5990 04:41:04.898606 RX DATLAT : PASS
5991 04:41:04.898659 RX DQ/DQS(Engine): PASS
5992 04:41:04.898709 TX OE : NO K
5993 04:41:04.898760 All Pass.
5994 04:41:04.898846
5995 04:41:04.898900 CH 0, Rank 1
5996 04:41:04.898955 SW Impedance : PASS
5997 04:41:04.899023 DUTY Scan : NO K
5998 04:41:04.899095 ZQ Calibration : PASS
5999 04:41:04.899148 Jitter Meter : NO K
6000 04:41:04.899202 CBT Training : PASS
6001 04:41:04.899271 Write leveling : PASS
6002 04:41:04.899341 RX DQS gating : PASS
6003 04:41:04.899394 RX DQ/DQS(RDDQC) : PASS
6004 04:41:04.899445 TX DQ/DQS : PASS
6005 04:41:04.899512 RX DATLAT : PASS
6006 04:41:04.899611 RX DQ/DQS(Engine): PASS
6007 04:41:04.899664 TX OE : NO K
6008 04:41:04.899715 All Pass.
6009 04:41:04.899769
6010 04:41:04.899851 CH 1, Rank 0
6011 04:41:04.899906 SW Impedance : PASS
6012 04:41:04.899958 DUTY Scan : NO K
6013 04:41:04.900010 ZQ Calibration : PASS
6014 04:41:04.900060 Jitter Meter : NO K
6015 04:41:04.900110 CBT Training : PASS
6016 04:41:04.900161 Write leveling : PASS
6017 04:41:04.900259 RX DQS gating : PASS
6018 04:41:04.900326 RX DQ/DQS(RDDQC) : PASS
6019 04:41:04.900379 TX DQ/DQS : PASS
6020 04:41:04.900429 RX DATLAT : PASS
6021 04:41:04.900480 RX DQ/DQS(Engine): PASS
6022 04:41:04.900547 TX OE : NO K
6023 04:41:04.900603 All Pass.
6024 04:41:04.900658
6025 04:41:04.900785 CH 1, Rank 1
6026 04:41:04.900870 SW Impedance : PASS
6027 04:41:04.900952 DUTY Scan : NO K
6028 04:41:04.901004 ZQ Calibration : PASS
6029 04:41:04.901059 Jitter Meter : NO K
6030 04:41:04.901112 CBT Training : PASS
6031 04:41:04.901169 Write leveling : PASS
6032 04:41:04.901222 RX DQS gating : PASS
6033 04:41:04.901273 RX DQ/DQS(RDDQC) : PASS
6034 04:41:04.901327 TX DQ/DQS : PASS
6035 04:41:04.901382 RX DATLAT : PASS
6036 04:41:04.901436 RX DQ/DQS(Engine): PASS
6037 04:41:04.901489 TX OE : NO K
6038 04:41:04.901543 All Pass.
6039 04:41:04.901597
6040 04:41:04.901652 DramC Write-DBI off
6041 04:41:04.901705 PER_BANK_REFRESH: Hybrid Mode
6042 04:41:04.901757 TX_TRACKING: ON
6043 04:41:04.901808 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6044 04:41:04.901861 [FAST_K] Save calibration result to emmc
6045 04:41:04.901912 dramc_set_vcore_voltage set vcore to 650000
6046 04:41:04.901966 Read voltage for 400, 6
6047 04:41:04.902024 Vio18 = 0
6048 04:41:04.902077 Vcore = 650000
6049 04:41:04.902131 Vdram = 0
6050 04:41:04.902185 Vddq = 0
6051 04:41:04.902236 Vmddr = 0
6052 04:41:04.902289 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6053 04:41:04.902340 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6054 04:41:04.902392 MEM_TYPE=3, freq_sel=20
6055 04:41:04.902446 sv_algorithm_assistance_LP4_800
6056 04:41:04.902503 ============ PULL DRAM RESETB DOWN ============
6057 04:41:04.902558 ========== PULL DRAM RESETB DOWN end =========
6058 04:41:04.902611 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6059 04:41:04.902662 ===================================
6060 04:41:04.902713 LPDDR4 DRAM CONFIGURATION
6061 04:41:04.902768 ===================================
6062 04:41:04.902822 EX_ROW_EN[0] = 0x0
6063 04:41:04.902873 EX_ROW_EN[1] = 0x0
6064 04:41:04.903111 LP4Y_EN = 0x0
6065 04:41:04.903174 WORK_FSP = 0x0
6066 04:41:04.903230 WL = 0x2
6067 04:41:04.903285 RL = 0x2
6068 04:41:04.903342 BL = 0x2
6069 04:41:04.903393 RPST = 0x0
6070 04:41:04.903448 RD_PRE = 0x0
6071 04:41:04.903503 WR_PRE = 0x1
6072 04:41:04.903557 WR_PST = 0x0
6073 04:41:04.903611 DBI_WR = 0x0
6074 04:41:04.903662 DBI_RD = 0x0
6075 04:41:04.903713 OTF = 0x1
6076 04:41:04.903765 ===================================
6077 04:41:04.903820 ===================================
6078 04:41:04.903874 ANA top config
6079 04:41:04.903937 ===================================
6080 04:41:04.903991 DLL_ASYNC_EN = 0
6081 04:41:04.904042 ALL_SLAVE_EN = 1
6082 04:41:04.904096 NEW_RANK_MODE = 1
6083 04:41:04.904151 DLL_IDLE_MODE = 1
6084 04:41:04.904204 LP45_APHY_COMB_EN = 1
6085 04:41:04.904260 TX_ODT_DIS = 1
6086 04:41:04.904312 NEW_8X_MODE = 1
6087 04:41:04.904366 ===================================
6088 04:41:04.904421 ===================================
6089 04:41:04.904471 data_rate = 800
6090 04:41:04.904522 CKR = 1
6091 04:41:04.904577 DQ_P2S_RATIO = 4
6092 04:41:04.904631 ===================================
6093 04:41:04.904713 CA_P2S_RATIO = 4
6094 04:41:04.904782 DQ_CA_OPEN = 0
6095 04:41:04.904836 DQ_SEMI_OPEN = 1
6096 04:41:04.904888 CA_SEMI_OPEN = 1
6097 04:41:04.904940 CA_FULL_RATE = 0
6098 04:41:04.904991 DQ_CKDIV4_EN = 0
6099 04:41:04.905044 CA_CKDIV4_EN = 1
6100 04:41:04.905099 CA_PREDIV_EN = 0
6101 04:41:04.905154 PH8_DLY = 0
6102 04:41:04.905206 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6103 04:41:04.905260 DQ_AAMCK_DIV = 0
6104 04:41:04.905314 CA_AAMCK_DIV = 0
6105 04:41:04.905369 CA_ADMCK_DIV = 4
6106 04:41:04.905422 DQ_TRACK_CA_EN = 0
6107 04:41:04.905473 CA_PICK = 800
6108 04:41:04.905524 CA_MCKIO = 400
6109 04:41:04.905597 MCKIO_SEMI = 400
6110 04:41:04.905684 PLL_FREQ = 3016
6111 04:41:04.905786 DQ_UI_PI_RATIO = 32
6112 04:41:04.905839 CA_UI_PI_RATIO = 32
6113 04:41:04.905895 ===================================
6114 04:41:04.905950 ===================================
6115 04:41:04.906004 memory_type:LPDDR4
6116 04:41:04.906055 GP_NUM : 10
6117 04:41:04.906106 SRAM_EN : 1
6118 04:41:04.906161 MD32_EN : 0
6119 04:41:04.906215 ===================================
6120 04:41:04.906266 [ANA_INIT] >>>>>>>>>>>>>>
6121 04:41:04.906318 <<<<<< [CONFIGURE PHASE]: ANA_TX
6122 04:41:04.906373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6123 04:41:04.906427 ===================================
6124 04:41:04.906482 data_rate = 800,PCW = 0X7400
6125 04:41:04.906535 ===================================
6126 04:41:04.906590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6127 04:41:04.906644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 04:41:04.906695 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6129 04:41:04.906750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6130 04:41:04.906802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6131 04:41:04.906857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6132 04:41:04.906911 [ANA_INIT] flow start
6133 04:41:04.906966 [ANA_INIT] PLL >>>>>>>>
6134 04:41:04.907023 [ANA_INIT] PLL <<<<<<<<
6135 04:41:04.907077 [ANA_INIT] MIDPI >>>>>>>>
6136 04:41:04.907130 [ANA_INIT] MIDPI <<<<<<<<
6137 04:41:04.907181 [ANA_INIT] DLL >>>>>>>>
6138 04:41:04.907232 [ANA_INIT] flow end
6139 04:41:04.907286 ============ LP4 DIFF to SE enter ============
6140 04:41:04.907341 ============ LP4 DIFF to SE exit ============
6141 04:41:04.907395 [ANA_INIT] <<<<<<<<<<<<<
6142 04:41:04.907450 [Flow] Enable top DCM control >>>>>
6143 04:41:04.907503 [Flow] Enable top DCM control <<<<<
6144 04:41:04.907554 Enable DLL master slave shuffle
6145 04:41:04.907609 ==============================================================
6146 04:41:04.907663 Gating Mode config
6147 04:41:04.907717 ==============================================================
6148 04:41:04.907772 Config description:
6149 04:41:04.907825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6150 04:41:04.907878 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6151 04:41:04.907930 SELPH_MODE 0: By rank 1: By Phase
6152 04:41:04.907985 ==============================================================
6153 04:41:04.908040 GAT_TRACK_EN = 0
6154 04:41:04.908093 RX_GATING_MODE = 2
6155 04:41:04.908144 RX_GATING_TRACK_MODE = 2
6156 04:41:04.908195 SELPH_MODE = 1
6157 04:41:04.908250 PICG_EARLY_EN = 1
6158 04:41:04.908306 VALID_LAT_VALUE = 1
6159 04:41:04.908358 ==============================================================
6160 04:41:04.908408 Enter into Gating configuration >>>>
6161 04:41:04.908463 Exit from Gating configuration <<<<
6162 04:41:04.908517 Enter into DVFS_PRE_config >>>>>
6163 04:41:04.908574 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6164 04:41:04.908630 Exit from DVFS_PRE_config <<<<<
6165 04:41:04.908691 Enter into PICG configuration >>>>
6166 04:41:04.908793 Exit from PICG configuration <<<<
6167 04:41:04.908879 [RX_INPUT] configuration >>>>>
6168 04:41:04.908930 [RX_INPUT] configuration <<<<<
6169 04:41:04.908982 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6170 04:41:04.909036 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6171 04:41:04.909091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 04:41:04.909146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 04:41:04.909382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 04:41:04.909442 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 04:41:04.909499 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6176 04:41:04.909553 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6177 04:41:04.909605 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6178 04:41:04.909657 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6179 04:41:04.909747 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6180 04:41:04.909802 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 04:41:04.909857 ===================================
6182 04:41:04.909911 LPDDR4 DRAM CONFIGURATION
6183 04:41:04.909965 ===================================
6184 04:41:04.910019 EX_ROW_EN[0] = 0x0
6185 04:41:04.910074 EX_ROW_EN[1] = 0x0
6186 04:41:04.910128 LP4Y_EN = 0x0
6187 04:41:04.910182 WORK_FSP = 0x0
6188 04:41:04.910236 WL = 0x2
6189 04:41:04.910286 RL = 0x2
6190 04:41:04.910340 BL = 0x2
6191 04:41:04.910395 RPST = 0x0
6192 04:41:04.910449 RD_PRE = 0x0
6193 04:41:04.910540 WR_PRE = 0x1
6194 04:41:04.910644 WR_PST = 0x0
6195 04:41:04.910714 DBI_WR = 0x0
6196 04:41:04.910765 DBI_RD = 0x0
6197 04:41:04.910816 OTF = 0x1
6198 04:41:04.910871 ===================================
6199 04:41:04.910928 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6200 04:41:04.910981 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6201 04:41:04.911036 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 04:41:04.911089 ===================================
6203 04:41:04.911141 LPDDR4 DRAM CONFIGURATION
6204 04:41:04.911209 ===================================
6205 04:41:04.911278 EX_ROW_EN[0] = 0x10
6206 04:41:04.911332 EX_ROW_EN[1] = 0x0
6207 04:41:04.911383 LP4Y_EN = 0x0
6208 04:41:04.911458 WORK_FSP = 0x0
6209 04:41:04.911526 WL = 0x2
6210 04:41:04.911581 RL = 0x2
6211 04:41:04.911634 BL = 0x2
6212 04:41:04.911709 RPST = 0x0
6213 04:41:04.911812 RD_PRE = 0x0
6214 04:41:04.911864 WR_PRE = 0x1
6215 04:41:04.911915 WR_PST = 0x0
6216 04:41:04.911969 DBI_WR = 0x0
6217 04:41:04.912022 DBI_RD = 0x0
6218 04:41:04.912115 OTF = 0x1
6219 04:41:04.912169 ===================================
6220 04:41:04.912268 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6221 04:41:04.912325 nWR fixed to 30
6222 04:41:04.912379 [ModeRegInit_LP4] CH0 RK0
6223 04:41:04.912434 [ModeRegInit_LP4] CH0 RK1
6224 04:41:04.912488 [ModeRegInit_LP4] CH1 RK0
6225 04:41:04.912543 [ModeRegInit_LP4] CH1 RK1
6226 04:41:04.912596 match AC timing 19
6227 04:41:04.912649 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6228 04:41:04.912744 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6229 04:41:04.912800 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6230 04:41:04.912851 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6231 04:41:04.912908 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6232 04:41:04.912962 ==
6233 04:41:04.913014 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 04:41:04.913065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 04:41:04.913120 ==
6236 04:41:04.913197 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 04:41:04.913296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6238 04:41:04.913350 [CA 0] Center 36 (8~64) winsize 57
6239 04:41:04.913404 [CA 1] Center 36 (8~64) winsize 57
6240 04:41:04.913459 [CA 2] Center 36 (8~64) winsize 57
6241 04:41:04.913513 [CA 3] Center 36 (8~64) winsize 57
6242 04:41:04.913582 [CA 4] Center 36 (8~64) winsize 57
6243 04:41:04.913651 [CA 5] Center 36 (8~64) winsize 57
6244 04:41:04.913706
6245 04:41:04.913776 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6246 04:41:04.913845
6247 04:41:04.913899 [CATrainingPosCal] consider 1 rank data
6248 04:41:04.913952 u2DelayCellTimex100 = 270/100 ps
6249 04:41:04.914008 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 04:41:04.914061 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 04:41:04.914117 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 04:41:04.914169 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 04:41:04.914221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 04:41:04.914302 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 04:41:04.914357
6256 04:41:04.914408 CA PerBit enable=1, Macro0, CA PI delay=36
6257 04:41:04.914462
6258 04:41:04.914515 [CBTSetCACLKResult] CA Dly = 36
6259 04:41:04.914587 CS Dly: 1 (0~32)
6260 04:41:04.914686 ==
6261 04:41:04.914741 Dram Type= 6, Freq= 0, CH_0, rank 1
6262 04:41:04.914795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 04:41:04.914848 ==
6264 04:41:04.914902 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 04:41:04.914958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6266 04:41:04.915014 [CA 0] Center 36 (8~64) winsize 57
6267 04:41:04.915067 [CA 1] Center 36 (8~64) winsize 57
6268 04:41:04.915118 [CA 2] Center 36 (8~64) winsize 57
6269 04:41:04.915201 [CA 3] Center 36 (8~64) winsize 57
6270 04:41:04.915257 [CA 4] Center 36 (8~64) winsize 57
6271 04:41:04.915312 [CA 5] Center 36 (8~64) winsize 57
6272 04:41:04.915365
6273 04:41:04.915419 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6274 04:41:04.915480
6275 04:41:04.915573 [CATrainingPosCal] consider 2 rank data
6276 04:41:04.915628 u2DelayCellTimex100 = 270/100 ps
6277 04:41:04.915682 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 04:41:04.915769 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 04:41:04.915823 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 04:41:04.915876 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 04:41:04.915930 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 04:41:04.916022 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 04:41:04.916076
6284 04:41:04.916128 CA PerBit enable=1, Macro0, CA PI delay=36
6285 04:41:04.916225
6286 04:41:04.916295 [CBTSetCACLKResult] CA Dly = 36
6287 04:41:04.916348 CS Dly: 1 (0~32)
6288 04:41:04.916400
6289 04:41:04.916450 ----->DramcWriteLeveling(PI) begin...
6290 04:41:04.916519 ==
6291 04:41:04.916575 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 04:41:04.916631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 04:41:04.916708 ==
6294 04:41:04.916789 Write leveling (Byte 0): 40 => 8
6295 04:41:04.916843 Write leveling (Byte 1): 32 => 0
6296 04:41:04.916896 DramcWriteLeveling(PI) end<-----
6297 04:41:04.916947
6298 04:41:04.917014 ==
6299 04:41:04.917083 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 04:41:04.917137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 04:41:04.917192 ==
6302 04:41:04.917246 [Gating] SW mode calibration
6303 04:41:04.917508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6304 04:41:04.917573 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6305 04:41:04.917642 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 04:41:04.917699 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6307 04:41:04.917751 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 04:41:04.917801 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 04:41:04.917852 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 04:41:04.917948 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 04:41:04.918034 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 04:41:04.918142 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 04:41:04.918225 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 04:41:04.918280 Total UI for P1: 0, mck2ui 16
6315 04:41:04.918335 best dqsien dly found for B0: ( 0, 14, 24)
6316 04:41:04.918390 Total UI for P1: 0, mck2ui 16
6317 04:41:04.918445 best dqsien dly found for B1: ( 0, 14, 24)
6318 04:41:04.918497 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6319 04:41:04.918548 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6320 04:41:04.918602
6321 04:41:04.918665 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 04:41:04.918728 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6323 04:41:04.918782 [Gating] SW calibration Done
6324 04:41:04.918834 ==
6325 04:41:04.918904 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 04:41:04.918959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 04:41:04.919027 ==
6328 04:41:04.919139 RX Vref Scan: 0
6329 04:41:04.919209
6330 04:41:04.919260 RX Vref 0 -> 0, step: 1
6331 04:41:04.919326
6332 04:41:04.919397 RX Delay -410 -> 252, step: 16
6333 04:41:04.919455 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6334 04:41:04.919519 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6335 04:41:04.919606 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6336 04:41:04.919706 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6337 04:41:04.919807 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6338 04:41:04.919864 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6339 04:41:04.919916 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6340 04:41:04.919970 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6341 04:41:04.920027 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6342 04:41:04.920081 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6343 04:41:04.920135 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6344 04:41:04.920190 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6345 04:41:04.920241 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6346 04:41:04.920297 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6347 04:41:04.920348 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6348 04:41:04.920398 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6349 04:41:04.920452 ==
6350 04:41:04.920506 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 04:41:04.920559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 04:41:04.920614 ==
6353 04:41:04.920678 DQS Delay:
6354 04:41:04.920766 DQS0 = 35, DQS1 = 51
6355 04:41:04.920816 DQM Delay:
6356 04:41:04.920872 DQM0 = 7, DQM1 = 10
6357 04:41:04.920925 DQ Delay:
6358 04:41:04.920979 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6359 04:41:04.921032 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6360 04:41:04.921083 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6361 04:41:04.921134 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6362 04:41:04.921191
6363 04:41:04.921242
6364 04:41:04.921296 ==
6365 04:41:04.921348 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 04:41:04.921402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 04:41:04.921460 ==
6368 04:41:04.921581
6369 04:41:04.921648
6370 04:41:04.921701 TX Vref Scan disable
6371 04:41:04.921755 == TX Byte 0 ==
6372 04:41:04.921808 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 04:41:04.921860 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 04:41:04.921953 == TX Byte 1 ==
6375 04:41:04.922008 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6376 04:41:04.922062 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6377 04:41:04.922117 ==
6378 04:41:04.922170 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 04:41:04.922224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 04:41:04.922275 ==
6381 04:41:04.922343
6382 04:41:04.922409
6383 04:41:04.922463 TX Vref Scan disable
6384 04:41:04.922516 == TX Byte 0 ==
6385 04:41:04.922569 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 04:41:04.922620 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 04:41:04.922670 == TX Byte 1 ==
6388 04:41:04.922751 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6389 04:41:04.922805 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6390 04:41:04.922860
6391 04:41:04.922911 [DATLAT]
6392 04:41:04.922964 Freq=400, CH0 RK0
6393 04:41:04.923019
6394 04:41:04.923110 DATLAT Default: 0xf
6395 04:41:04.923165 0, 0xFFFF, sum = 0
6396 04:41:04.923238 1, 0xFFFF, sum = 0
6397 04:41:04.923306 2, 0xFFFF, sum = 0
6398 04:41:04.923376 3, 0xFFFF, sum = 0
6399 04:41:04.923482 4, 0xFFFF, sum = 0
6400 04:41:04.923539 5, 0xFFFF, sum = 0
6401 04:41:04.923619 6, 0xFFFF, sum = 0
6402 04:41:04.923677 7, 0xFFFF, sum = 0
6403 04:41:04.923731 8, 0xFFFF, sum = 0
6404 04:41:04.923784 9, 0xFFFF, sum = 0
6405 04:41:04.923856 10, 0xFFFF, sum = 0
6406 04:41:04.923913 11, 0xFFFF, sum = 0
6407 04:41:04.923968 12, 0xFFFF, sum = 0
6408 04:41:04.924022 13, 0x0, sum = 1
6409 04:41:04.924075 14, 0x0, sum = 2
6410 04:41:04.924126 15, 0x0, sum = 3
6411 04:41:04.924179 16, 0x0, sum = 4
6412 04:41:04.924233 best_step = 14
6413 04:41:04.924286
6414 04:41:04.924338 ==
6415 04:41:04.924391 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 04:41:04.924444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 04:41:04.924497 ==
6418 04:41:04.924547 RX Vref Scan: 1
6419 04:41:04.924597
6420 04:41:04.924651 RX Vref 0 -> 0, step: 1
6421 04:41:04.924741
6422 04:41:04.924796 RX Delay -343 -> 252, step: 8
6423 04:41:04.924848
6424 04:41:04.924903 Set Vref, RX VrefLevel [Byte0]: 53
6425 04:41:04.924957 [Byte1]: 51
6426 04:41:04.925010
6427 04:41:04.925061 Final RX Vref Byte 0 = 53 to rank0
6428 04:41:04.925115 Final RX Vref Byte 1 = 51 to rank0
6429 04:41:04.925169 Final RX Vref Byte 0 = 53 to rank1
6430 04:41:04.925222 Final RX Vref Byte 1 = 51 to rank1==
6431 04:41:04.925273 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 04:41:04.925324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 04:41:04.925379 ==
6434 04:41:04.925432 DQS Delay:
6435 04:41:04.925496 DQS0 = 44, DQS1 = 56
6436 04:41:04.925639 DQM Delay:
6437 04:41:04.925743 DQM0 = 11, DQM1 = 11
6438 04:41:04.925841 DQ Delay:
6439 04:41:04.925896 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6440 04:41:04.925950 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6441 04:41:04.926003 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6442 04:41:04.926054 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6443 04:41:04.926152
6444 04:41:04.926221
6445 04:41:04.926464 [DQSOSCAuto] RK0, (LSB)MR18= 0x7c4a, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
6446 04:41:04.926528 CH0 RK0: MR19=C0C, MR18=7C4A
6447 04:41:04.926580 CH0_RK0: MR19=0xC0C, MR18=0x7C4A, DQSOSC=394, MR23=63, INC=380, DEC=253
6448 04:41:04.926636 ==
6449 04:41:04.926690 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 04:41:04.926742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 04:41:04.926793 ==
6452 04:41:04.926847 [Gating] SW mode calibration
6453 04:41:04.926899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6454 04:41:04.926955 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6455 04:41:04.927008 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 04:41:04.927060 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6457 04:41:04.927153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 04:41:04.927207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 04:41:04.927261 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 04:41:04.927314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 04:41:04.927369 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 04:41:04.927423 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 04:41:04.927476 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 04:41:04.927527 Total UI for P1: 0, mck2ui 16
6465 04:41:04.927578 best dqsien dly found for B0: ( 0, 14, 24)
6466 04:41:04.927635 Total UI for P1: 0, mck2ui 16
6467 04:41:04.927688 best dqsien dly found for B1: ( 0, 14, 24)
6468 04:41:04.927752 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6469 04:41:04.927838 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6470 04:41:04.927895
6471 04:41:04.927947 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 04:41:04.927999 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6473 04:41:04.928049 [Gating] SW calibration Done
6474 04:41:04.928104 ==
6475 04:41:04.928158 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 04:41:04.928212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 04:41:04.928265 ==
6478 04:41:04.928319 RX Vref Scan: 0
6479 04:41:04.928369
6480 04:41:04.928419 RX Vref 0 -> 0, step: 1
6481 04:41:04.928472
6482 04:41:04.928527 RX Delay -410 -> 252, step: 16
6483 04:41:04.928581 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6484 04:41:04.928634 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6485 04:41:04.928738 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6486 04:41:04.928797 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6487 04:41:04.928853 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6488 04:41:04.928908 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6489 04:41:04.928961 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6490 04:41:04.929011 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6491 04:41:04.929065 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6492 04:41:04.929132 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6493 04:41:04.929185 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6494 04:41:04.929236 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6495 04:41:04.929287 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6496 04:41:04.929342 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6497 04:41:04.929395 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6498 04:41:04.929450 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6499 04:41:04.929503 ==
6500 04:41:04.929557 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 04:41:04.929611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 04:41:04.929665 ==
6503 04:41:04.929733 DQS Delay:
6504 04:41:04.929786 DQS0 = 43, DQS1 = 51
6505 04:41:04.929840 DQM Delay:
6506 04:41:04.929894 DQM0 = 11, DQM1 = 10
6507 04:41:04.929946 DQ Delay:
6508 04:41:04.929997 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6509 04:41:04.930047 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6510 04:41:04.930101 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6511 04:41:04.930155 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6512 04:41:04.930212
6513 04:41:04.930263
6514 04:41:04.930317 ==
6515 04:41:04.930369 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 04:41:04.930419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 04:41:04.930470 ==
6518 04:41:04.930523
6519 04:41:04.930577
6520 04:41:04.930629 TX Vref Scan disable
6521 04:41:04.930683 == TX Byte 0 ==
6522 04:41:04.930736 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6523 04:41:04.930791 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6524 04:41:04.930844 == TX Byte 1 ==
6525 04:41:04.930895 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6526 04:41:04.930948 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6527 04:41:04.931035 ==
6528 04:41:04.931092 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 04:41:04.931144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 04:41:04.931198 ==
6531 04:41:04.931252
6532 04:41:04.931304
6533 04:41:04.931354 TX Vref Scan disable
6534 04:41:04.931408 == TX Byte 0 ==
6535 04:41:04.931462 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6536 04:41:04.931513 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6537 04:41:04.931564 == TX Byte 1 ==
6538 04:41:04.931617 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6539 04:41:04.931671 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6540 04:41:04.931727
6541 04:41:04.931780 [DATLAT]
6542 04:41:04.931830 Freq=400, CH0 RK1
6543 04:41:04.931880
6544 04:41:04.931934 DATLAT Default: 0xe
6545 04:41:04.931987 0, 0xFFFF, sum = 0
6546 04:41:04.932044 1, 0xFFFF, sum = 0
6547 04:41:04.932097 2, 0xFFFF, sum = 0
6548 04:41:04.932149 3, 0xFFFF, sum = 0
6549 04:41:04.932216 4, 0xFFFF, sum = 0
6550 04:41:04.932274 5, 0xFFFF, sum = 0
6551 04:41:04.932330 6, 0xFFFF, sum = 0
6552 04:41:04.932383 7, 0xFFFF, sum = 0
6553 04:41:04.932439 8, 0xFFFF, sum = 0
6554 04:41:04.932494 9, 0xFFFF, sum = 0
6555 04:41:04.932548 10, 0xFFFF, sum = 0
6556 04:41:04.932611 11, 0xFFFF, sum = 0
6557 04:41:04.932727 12, 0xFFFF, sum = 0
6558 04:41:04.932784 13, 0x0, sum = 1
6559 04:41:04.932837 14, 0x0, sum = 2
6560 04:41:04.932888 15, 0x0, sum = 3
6561 04:41:04.932946 16, 0x0, sum = 4
6562 04:41:04.932999 best_step = 14
6563 04:41:04.933050
6564 04:41:04.933105 ==
6565 04:41:04.933158 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 04:41:04.933224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 04:41:04.933279 ==
6568 04:41:04.933333 RX Vref Scan: 0
6569 04:41:04.933384
6570 04:41:04.933437 RX Vref 0 -> 0, step: 1
6571 04:41:04.933502
6572 04:41:04.933557 RX Delay -343 -> 252, step: 8
6573 04:41:04.933608 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6574 04:41:04.933659 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6575 04:41:04.933713 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6576 04:41:04.933767 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6577 04:41:04.933821 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6578 04:41:04.933873 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6579 04:41:04.933927 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6580 04:41:04.934171 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6581 04:41:04.934288 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6582 04:41:04.934397 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6583 04:41:04.934510 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6584 04:41:04.934615 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6585 04:41:04.934729 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6586 04:41:04.934840 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6587 04:41:04.934951 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6588 04:41:04.935056 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6589 04:41:04.935148 ==
6590 04:41:04.935244 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 04:41:04.935306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 04:41:04.935361 ==
6593 04:41:04.935413 DQS Delay:
6594 04:41:04.935467 DQS0 = 48, DQS1 = 60
6595 04:41:04.935527 DQM Delay:
6596 04:41:04.935595 DQM0 = 12, DQM1 = 13
6597 04:41:04.935655 DQ Delay:
6598 04:41:04.935708 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6599 04:41:04.935760 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =20
6600 04:41:04.935810 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6601 04:41:04.935861 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6602 04:41:04.935911
6603 04:41:04.935969
6604 04:41:04.936024 [DQSOSCAuto] RK1, (LSB)MR18= 0x9466, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6605 04:41:04.936079 CH0 RK1: MR19=C0C, MR18=9466
6606 04:41:04.936133 CH0_RK1: MR19=0xC0C, MR18=0x9466, DQSOSC=391, MR23=63, INC=386, DEC=257
6607 04:41:04.936184 [RxdqsGatingPostProcess] freq 400
6608 04:41:04.936239 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6609 04:41:04.936293 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 04:41:04.936346 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 04:41:04.936400 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 04:41:04.936455 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 04:41:04.936506 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 04:41:04.936561 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 04:41:04.936613 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 04:41:04.936723 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 04:41:04.936797 Pre-setting of DQS Precalculation
6618 04:41:04.936858 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6619 04:41:04.936913 ==
6620 04:41:04.936966 Dram Type= 6, Freq= 0, CH_1, rank 0
6621 04:41:04.937024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 04:41:04.937079 ==
6623 04:41:04.937130 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 04:41:04.937182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6625 04:41:04.937234 [CA 0] Center 36 (8~64) winsize 57
6626 04:41:04.937285 [CA 1] Center 36 (8~64) winsize 57
6627 04:41:04.937341 [CA 2] Center 36 (8~64) winsize 57
6628 04:41:04.937392 [CA 3] Center 36 (8~64) winsize 57
6629 04:41:04.937448 [CA 4] Center 36 (8~64) winsize 57
6630 04:41:04.937501 [CA 5] Center 36 (8~64) winsize 57
6631 04:41:04.937551
6632 04:41:04.937605 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6633 04:41:04.937656
6634 04:41:04.937706 [CATrainingPosCal] consider 1 rank data
6635 04:41:04.937757 u2DelayCellTimex100 = 270/100 ps
6636 04:41:04.937810 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 04:41:04.937864 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 04:41:04.937918 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 04:41:04.937970 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 04:41:04.938020 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 04:41:04.938074 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 04:41:04.938127
6643 04:41:04.938181 CA PerBit enable=1, Macro0, CA PI delay=36
6644 04:41:04.938234
6645 04:41:04.938286 [CBTSetCACLKResult] CA Dly = 36
6646 04:41:04.938340 CS Dly: 1 (0~32)
6647 04:41:04.938393 ==
6648 04:41:04.938446 Dram Type= 6, Freq= 0, CH_1, rank 1
6649 04:41:04.938500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 04:41:04.938552 ==
6651 04:41:04.938606 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 04:41:04.938657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6653 04:41:04.938707 [CA 0] Center 36 (8~64) winsize 57
6654 04:41:04.938761 [CA 1] Center 36 (8~64) winsize 57
6655 04:41:04.938814 [CA 2] Center 36 (8~64) winsize 57
6656 04:41:04.938867 [CA 3] Center 36 (8~64) winsize 57
6657 04:41:04.938917 [CA 4] Center 36 (8~64) winsize 57
6658 04:41:04.938970 [CA 5] Center 36 (8~64) winsize 57
6659 04:41:04.939023
6660 04:41:04.939077 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6661 04:41:04.939143
6662 04:41:04.939195 [CATrainingPosCal] consider 2 rank data
6663 04:41:04.939249 u2DelayCellTimex100 = 270/100 ps
6664 04:41:04.939303 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 04:41:04.939357 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 04:41:04.939412 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 04:41:04.939465 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 04:41:04.939515 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 04:41:04.939566 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 04:41:04.939621
6671 04:41:04.939672 CA PerBit enable=1, Macro0, CA PI delay=36
6672 04:41:04.939722
6673 04:41:04.939788 [CBTSetCACLKResult] CA Dly = 36
6674 04:41:04.939860 CS Dly: 1 (0~32)
6675 04:41:04.939926
6676 04:41:04.940000 ----->DramcWriteLeveling(PI) begin...
6677 04:41:04.940059 ==
6678 04:41:04.940117 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 04:41:04.940179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 04:41:04.940234 ==
6681 04:41:04.940289 Write leveling (Byte 0): 40 => 8
6682 04:41:04.940344 Write leveling (Byte 1): 40 => 8
6683 04:41:04.940396 DramcWriteLeveling(PI) end<-----
6684 04:41:04.940447
6685 04:41:04.940500 ==
6686 04:41:04.940550 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 04:41:04.940605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 04:41:04.940658 ==
6689 04:41:04.940755 [Gating] SW mode calibration
6690 04:41:04.940807 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6691 04:41:04.940859 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6692 04:41:04.940909 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 04:41:04.940964 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6694 04:41:04.941017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 04:41:04.941068 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 04:41:04.941118 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 04:41:04.941169 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 04:41:04.941412 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 04:41:04.941529 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 04:41:04.941638 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 04:41:04.941743 Total UI for P1: 0, mck2ui 16
6702 04:41:04.941854 best dqsien dly found for B0: ( 0, 14, 24)
6703 04:41:04.941956 Total UI for P1: 0, mck2ui 16
6704 04:41:04.942050 best dqsien dly found for B1: ( 0, 14, 24)
6705 04:41:04.942151 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6706 04:41:04.942238 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6707 04:41:04.942320
6708 04:41:04.942404 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 04:41:04.942489 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6710 04:41:04.942570 [Gating] SW calibration Done
6711 04:41:04.942649 ==
6712 04:41:04.942729 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 04:41:04.942815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 04:41:04.942899 ==
6715 04:41:04.942981 RX Vref Scan: 0
6716 04:41:04.943066
6717 04:41:04.943150 RX Vref 0 -> 0, step: 1
6718 04:41:04.943234
6719 04:41:04.943326 RX Delay -410 -> 252, step: 16
6720 04:41:04.943411 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6721 04:41:04.943497 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6722 04:41:04.943582 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6723 04:41:04.943640 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6724 04:41:04.943694 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6725 04:41:04.943745 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6726 04:41:04.943796 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6727 04:41:04.943850 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6728 04:41:04.943905 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6729 04:41:04.943961 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6730 04:41:04.944012 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6731 04:41:04.944066 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6732 04:41:04.944119 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6733 04:41:04.944174 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6734 04:41:04.944227 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6735 04:41:04.944278 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6736 04:41:04.944329 ==
6737 04:41:04.944380 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 04:41:04.944436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 04:41:04.944504 ==
6740 04:41:04.944557 DQS Delay:
6741 04:41:04.944613 DQS0 = 43, DQS1 = 59
6742 04:41:04.944688 DQM Delay:
6743 04:41:04.944760 DQM0 = 12, DQM1 = 17
6744 04:41:04.944814 DQ Delay:
6745 04:41:04.944864 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6746 04:41:04.944950 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6747 04:41:04.945001 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6748 04:41:04.945052 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6749 04:41:04.945106
6750 04:41:04.945158
6751 04:41:04.945208 ==
6752 04:41:04.945261 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 04:41:04.945312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 04:41:04.945366 ==
6755 04:41:04.945420
6756 04:41:04.945482
6757 04:41:04.945562 TX Vref Scan disable
6758 04:41:04.945628 == TX Byte 0 ==
6759 04:41:04.945683 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 04:41:04.945744 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 04:41:04.945798 == TX Byte 1 ==
6762 04:41:04.945852 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 04:41:04.945904 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 04:41:04.945999 ==
6765 04:41:04.946052 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 04:41:04.946106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 04:41:04.946162 ==
6768 04:41:04.946215
6769 04:41:04.946265
6770 04:41:04.946315 TX Vref Scan disable
6771 04:41:04.946366 == TX Byte 0 ==
6772 04:41:04.946435 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 04:41:04.946502 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 04:41:04.946556 == TX Byte 1 ==
6775 04:41:04.946608 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 04:41:04.946659 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 04:41:04.946710
6778 04:41:04.946760 [DATLAT]
6779 04:41:04.946814 Freq=400, CH1 RK0
6780 04:41:04.946869
6781 04:41:04.946937 DATLAT Default: 0xf
6782 04:41:04.946990 0, 0xFFFF, sum = 0
6783 04:41:04.947046 1, 0xFFFF, sum = 0
6784 04:41:04.947101 2, 0xFFFF, sum = 0
6785 04:41:04.947154 3, 0xFFFF, sum = 0
6786 04:41:04.947208 4, 0xFFFF, sum = 0
6787 04:41:04.947262 5, 0xFFFF, sum = 0
6788 04:41:04.947313 6, 0xFFFF, sum = 0
6789 04:41:04.947367 7, 0xFFFF, sum = 0
6790 04:41:04.947422 8, 0xFFFF, sum = 0
6791 04:41:04.947482 9, 0xFFFF, sum = 0
6792 04:41:04.947549 10, 0xFFFF, sum = 0
6793 04:41:04.947645 11, 0xFFFF, sum = 0
6794 04:41:04.947751 12, 0xFFFF, sum = 0
6795 04:41:04.947840 13, 0x0, sum = 1
6796 04:41:04.947928 14, 0x0, sum = 2
6797 04:41:04.948013 15, 0x0, sum = 3
6798 04:41:04.948097 16, 0x0, sum = 4
6799 04:41:04.948182 best_step = 14
6800 04:41:04.948261
6801 04:41:04.948347 ==
6802 04:41:04.948430 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 04:41:04.948523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 04:41:04.948630 ==
6805 04:41:04.948756 RX Vref Scan: 1
6806 04:41:04.948820
6807 04:41:04.948874 RX Vref 0 -> 0, step: 1
6808 04:41:04.948924
6809 04:41:04.948983 RX Delay -359 -> 252, step: 8
6810 04:41:04.949046
6811 04:41:04.949116 Set Vref, RX VrefLevel [Byte0]: 57
6812 04:41:04.949171 [Byte1]: 52
6813 04:41:04.949236
6814 04:41:04.949297 Final RX Vref Byte 0 = 57 to rank0
6815 04:41:04.949352 Final RX Vref Byte 1 = 52 to rank0
6816 04:41:04.949408 Final RX Vref Byte 0 = 57 to rank1
6817 04:41:04.949459 Final RX Vref Byte 1 = 52 to rank1==
6818 04:41:04.949513 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 04:41:04.949565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 04:41:04.949616 ==
6821 04:41:04.949667 DQS Delay:
6822 04:41:04.949721 DQS0 = 48, DQS1 = 60
6823 04:41:04.949774 DQM Delay:
6824 04:41:04.949829 DQM0 = 13, DQM1 = 12
6825 04:41:04.949882 DQ Delay:
6826 04:41:04.949948 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6827 04:41:04.950000 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6828 04:41:04.950051 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6829 04:41:04.950105 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6830 04:41:04.950160
6831 04:41:04.950215
6832 04:41:04.950269 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a31, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6833 04:41:04.950322 CH1 RK0: MR19=C0C, MR18=8A31
6834 04:41:04.950378 CH1_RK0: MR19=0xC0C, MR18=0x8A31, DQSOSC=392, MR23=63, INC=384, DEC=256
6835 04:41:04.950432 ==
6836 04:41:04.950487 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 04:41:04.950539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 04:41:04.950594 ==
6839 04:41:04.950647 [Gating] SW mode calibration
6840 04:41:04.950698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6841 04:41:04.950750 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6842 04:41:04.950810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 04:41:04.951068 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6844 04:41:04.951138 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 04:41:04.951199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 04:41:04.951252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 04:41:04.951304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 04:41:04.951358 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 04:41:04.951412 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 04:41:04.951463 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 04:41:04.951518 Total UI for P1: 0, mck2ui 16
6852 04:41:04.951571 best dqsien dly found for B0: ( 0, 14, 24)
6853 04:41:04.951627 Total UI for P1: 0, mck2ui 16
6854 04:41:04.951679 best dqsien dly found for B1: ( 0, 14, 24)
6855 04:41:04.951730 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6856 04:41:04.951784 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6857 04:41:04.951838
6858 04:41:04.951892 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 04:41:04.951945 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6860 04:41:04.951996 [Gating] SW calibration Done
6861 04:41:04.952048 ==
6862 04:41:04.952099 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 04:41:04.952150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 04:41:04.952204 ==
6865 04:41:04.952258 RX Vref Scan: 0
6866 04:41:04.952312
6867 04:41:04.952364 RX Vref 0 -> 0, step: 1
6868 04:41:04.952414
6869 04:41:04.952467 RX Delay -410 -> 252, step: 16
6870 04:41:04.952528 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6871 04:41:04.952582 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6872 04:41:04.952637 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6873 04:41:04.952740 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6874 04:41:04.952794 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6875 04:41:04.952845 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6876 04:41:04.952898 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6877 04:41:04.952949 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6878 04:41:04.953002 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6879 04:41:04.953053 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6880 04:41:04.953104 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6881 04:41:04.953158 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6882 04:41:04.953212 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6883 04:41:04.953268 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6884 04:41:04.953319 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6885 04:41:04.953372 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6886 04:41:04.953438 ==
6887 04:41:04.953496 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 04:41:04.953547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 04:41:04.953600 ==
6890 04:41:04.953652 DQS Delay:
6891 04:41:04.953707 DQS0 = 43, DQS1 = 59
6892 04:41:04.953758 DQM Delay:
6893 04:41:04.953810 DQM0 = 9, DQM1 = 20
6894 04:41:04.953865 DQ Delay:
6895 04:41:04.953916 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6896 04:41:04.953969 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6897 04:41:04.954023 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6898 04:41:04.954077 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6899 04:41:04.954130
6900 04:41:04.954181
6901 04:41:04.954232 ==
6902 04:41:04.954286 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 04:41:04.954343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 04:41:04.954398 ==
6905 04:41:04.954451
6906 04:41:04.954504
6907 04:41:04.954555 TX Vref Scan disable
6908 04:41:04.954605 == TX Byte 0 ==
6909 04:41:04.954659 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6910 04:41:04.954711 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6911 04:41:04.954762 == TX Byte 1 ==
6912 04:41:04.954812 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6913 04:41:04.954867 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6914 04:41:04.954921 ==
6915 04:41:04.954973 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 04:41:04.955024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 04:41:04.955077 ==
6918 04:41:04.955142
6919 04:41:04.955199
6920 04:41:04.955252 TX Vref Scan disable
6921 04:41:04.955303 == TX Byte 0 ==
6922 04:41:04.955356 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6923 04:41:04.955426 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6924 04:41:04.955495 == TX Byte 1 ==
6925 04:41:04.955549 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6926 04:41:04.955602 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6927 04:41:04.955656
6928 04:41:04.955708 [DATLAT]
6929 04:41:04.955758 Freq=400, CH1 RK1
6930 04:41:04.955813
6931 04:41:04.955865 DATLAT Default: 0xe
6932 04:41:04.955920 0, 0xFFFF, sum = 0
6933 04:41:04.955973 1, 0xFFFF, sum = 0
6934 04:41:04.956027 2, 0xFFFF, sum = 0
6935 04:41:04.956079 3, 0xFFFF, sum = 0
6936 04:41:04.956133 4, 0xFFFF, sum = 0
6937 04:41:04.956187 5, 0xFFFF, sum = 0
6938 04:41:04.956242 6, 0xFFFF, sum = 0
6939 04:41:04.956295 7, 0xFFFF, sum = 0
6940 04:41:04.956351 8, 0xFFFF, sum = 0
6941 04:41:04.956405 9, 0xFFFF, sum = 0
6942 04:41:04.956459 10, 0xFFFF, sum = 0
6943 04:41:04.956510 11, 0xFFFF, sum = 0
6944 04:41:04.956565 12, 0xFFFF, sum = 0
6945 04:41:05.193797 13, 0x0, sum = 1
6946 04:41:05.193935 14, 0x0, sum = 2
6947 04:41:05.194002 15, 0x0, sum = 3
6948 04:41:05.194067 16, 0x0, sum = 4
6949 04:41:05.194130 best_step = 14
6950 04:41:05.194188
6951 04:41:05.194242 ==
6952 04:41:05.194299 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 04:41:05.194353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 04:41:05.194406 ==
6955 04:41:05.194458 RX Vref Scan: 0
6956 04:41:05.194510
6957 04:41:05.194565 RX Vref 0 -> 0, step: 1
6958 04:41:05.194617
6959 04:41:05.194668 RX Delay -359 -> 252, step: 8
6960 04:41:05.194719 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6961 04:41:05.194774 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6962 04:41:05.194826 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6963 04:41:05.194877 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6964 04:41:05.194928 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6965 04:41:05.194982 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6966 04:41:05.195051 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6967 04:41:05.195115 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6968 04:41:05.195168 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6969 04:41:05.195219 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6970 04:41:05.195273 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6971 04:41:05.195330 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6972 04:41:05.195383 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6973 04:41:05.195434 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6974 04:41:05.195488 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6975 04:41:05.195539 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6976 04:41:05.195593 ==
6977 04:41:05.195647 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 04:41:05.195930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 04:41:05.196059 ==
6980 04:41:05.196169 DQS Delay:
6981 04:41:05.196281 DQS0 = 52, DQS1 = 60
6982 04:41:05.196384 DQM Delay:
6983 04:41:05.196493 DQM0 = 13, DQM1 = 13
6984 04:41:05.196602 DQ Delay:
6985 04:41:05.196790 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6986 04:41:05.196899 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6987 04:41:05.196993 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6988 04:41:05.197081 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6989 04:41:05.197167
6990 04:41:05.197247
6991 04:41:05.197330 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6992 04:41:05.197414 CH1 RK1: MR19=C0C, MR18=6E84
6993 04:41:05.197500 CH1_RK1: MR19=0xC0C, MR18=0x6E84, DQSOSC=393, MR23=63, INC=382, DEC=254
6994 04:41:05.197583 [RxdqsGatingPostProcess] freq 400
6995 04:41:05.197667 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6996 04:41:05.197748 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 04:41:05.197828 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 04:41:05.197910 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 04:41:05.197991 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 04:41:05.198074 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 04:41:05.198159 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 04:41:05.198243 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 04:41:05.198323 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 04:41:05.198403 Pre-setting of DQS Precalculation
7005 04:41:05.198491 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7006 04:41:05.198574 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7007 04:41:05.198659 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7008 04:41:05.198739
7009 04:41:05.198818
7010 04:41:05.198902 [Calibration Summary] 800 Mbps
7011 04:41:05.198985 CH 0, Rank 0
7012 04:41:05.199065 SW Impedance : PASS
7013 04:41:05.199147 DUTY Scan : NO K
7014 04:41:05.199231 ZQ Calibration : PASS
7015 04:41:05.199292 Jitter Meter : NO K
7016 04:41:05.199346 CBT Training : PASS
7017 04:41:05.199400 Write leveling : PASS
7018 04:41:05.199451 RX DQS gating : PASS
7019 04:41:05.199502 RX DQ/DQS(RDDQC) : PASS
7020 04:41:05.199552 TX DQ/DQS : PASS
7021 04:41:05.199603 RX DATLAT : PASS
7022 04:41:05.199658 RX DQ/DQS(Engine): PASS
7023 04:41:05.199712 TX OE : NO K
7024 04:41:05.199764 All Pass.
7025 04:41:05.199814
7026 04:41:05.199865 CH 0, Rank 1
7027 04:41:05.199918 SW Impedance : PASS
7028 04:41:05.199969 DUTY Scan : NO K
7029 04:41:05.200020 ZQ Calibration : PASS
7030 04:41:05.200071 Jitter Meter : NO K
7031 04:41:05.200121 CBT Training : PASS
7032 04:41:05.200176 Write leveling : NO K
7033 04:41:05.200230 RX DQS gating : PASS
7034 04:41:05.200283 RX DQ/DQS(RDDQC) : PASS
7035 04:41:05.200334 TX DQ/DQS : PASS
7036 04:41:05.200387 RX DATLAT : PASS
7037 04:41:05.200439 RX DQ/DQS(Engine): PASS
7038 04:41:05.200489 TX OE : NO K
7039 04:41:05.200540 All Pass.
7040 04:41:05.200595
7041 04:41:05.200684 CH 1, Rank 0
7042 04:41:05.200750 SW Impedance : PASS
7043 04:41:05.200802 DUTY Scan : NO K
7044 04:41:05.200858 ZQ Calibration : PASS
7045 04:41:05.200911 Jitter Meter : NO K
7046 04:41:05.200965 CBT Training : PASS
7047 04:41:05.201017 Write leveling : PASS
7048 04:41:05.201069 RX DQS gating : PASS
7049 04:41:05.201119 RX DQ/DQS(RDDQC) : PASS
7050 04:41:05.201174 TX DQ/DQS : PASS
7051 04:41:05.201229 RX DATLAT : PASS
7052 04:41:05.201282 RX DQ/DQS(Engine): PASS
7053 04:41:05.201336 TX OE : NO K
7054 04:41:05.201390 All Pass.
7055 04:41:05.201445
7056 04:41:05.201496 CH 1, Rank 1
7057 04:41:05.201547 SW Impedance : PASS
7058 04:41:05.201602 DUTY Scan : NO K
7059 04:41:05.201658 ZQ Calibration : PASS
7060 04:41:05.201710 Jitter Meter : NO K
7061 04:41:05.201760 CBT Training : PASS
7062 04:41:05.201811 Write leveling : NO K
7063 04:41:05.201862 RX DQS gating : PASS
7064 04:41:05.201917 RX DQ/DQS(RDDQC) : PASS
7065 04:41:05.201971 TX DQ/DQS : PASS
7066 04:41:05.202023 RX DATLAT : PASS
7067 04:41:05.202076 RX DQ/DQS(Engine): PASS
7068 04:41:05.202130 TX OE : NO K
7069 04:41:05.202185 All Pass.
7070 04:41:05.202238
7071 04:41:05.202288 DramC Write-DBI off
7072 04:41:05.202339 PER_BANK_REFRESH: Hybrid Mode
7073 04:41:05.202390 TX_TRACKING: ON
7074 04:41:05.202444 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7075 04:41:05.202497 [FAST_K] Save calibration result to emmc
7076 04:41:05.202548 dramc_set_vcore_voltage set vcore to 725000
7077 04:41:05.202603 Read voltage for 1600, 0
7078 04:41:05.202656 Vio18 = 0
7079 04:41:05.202711 Vcore = 725000
7080 04:41:05.202761 Vdram = 0
7081 04:41:05.202812 Vddq = 0
7082 04:41:05.202863 Vmddr = 0
7083 04:41:05.202917 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7084 04:41:05.202969 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7085 04:41:05.203021 MEM_TYPE=3, freq_sel=13
7086 04:41:05.203076 sv_algorithm_assistance_LP4_3733
7087 04:41:05.203129 ============ PULL DRAM RESETB DOWN ============
7088 04:41:05.203184 ========== PULL DRAM RESETB DOWN end =========
7089 04:41:05.203240 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7090 04:41:05.203293 ===================================
7091 04:41:05.203345 LPDDR4 DRAM CONFIGURATION
7092 04:41:05.203398 ===================================
7093 04:41:05.203464 EX_ROW_EN[0] = 0x0
7094 04:41:05.203530 EX_ROW_EN[1] = 0x0
7095 04:41:05.203583 LP4Y_EN = 0x0
7096 04:41:05.203635 WORK_FSP = 0x1
7097 04:41:05.203690 WL = 0x5
7098 04:41:05.203742 RL = 0x5
7099 04:41:05.203793 BL = 0x2
7100 04:41:05.203847 RPST = 0x0
7101 04:41:05.203900 RD_PRE = 0x0
7102 04:41:05.203955 WR_PRE = 0x1
7103 04:41:05.204008 WR_PST = 0x1
7104 04:41:05.204059 DBI_WR = 0x0
7105 04:41:05.204109 DBI_RD = 0x0
7106 04:41:05.204160 OTF = 0x1
7107 04:41:05.204211 ===================================
7108 04:41:05.204262 ===================================
7109 04:41:05.204317 ANA top config
7110 04:41:05.204431 ===================================
7111 04:41:05.204502 DLL_ASYNC_EN = 0
7112 04:41:05.204556 ALL_SLAVE_EN = 0
7113 04:41:05.204609 NEW_RANK_MODE = 1
7114 04:41:05.204704 DLL_IDLE_MODE = 1
7115 04:41:05.204776 LP45_APHY_COMB_EN = 1
7116 04:41:05.204827 TX_ODT_DIS = 0
7117 04:41:05.204879 NEW_8X_MODE = 1
7118 04:41:05.204933 ===================================
7119 04:41:05.204985 ===================================
7120 04:41:05.205039 data_rate = 3200
7121 04:41:05.205093 CKR = 1
7122 04:41:05.205148 DQ_P2S_RATIO = 8
7123 04:41:05.205203 ===================================
7124 04:41:05.205441 CA_P2S_RATIO = 8
7125 04:41:05.205501 DQ_CA_OPEN = 0
7126 04:41:05.205554 DQ_SEMI_OPEN = 0
7127 04:41:05.205610 CA_SEMI_OPEN = 0
7128 04:41:05.205662 CA_FULL_RATE = 0
7129 04:41:05.205722 DQ_CKDIV4_EN = 0
7130 04:41:05.205785 CA_CKDIV4_EN = 0
7131 04:41:05.205840 CA_PREDIV_EN = 0
7132 04:41:05.205894 PH8_DLY = 12
7133 04:41:05.205946 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7134 04:41:05.205998 DQ_AAMCK_DIV = 4
7135 04:41:05.206049 CA_AAMCK_DIV = 4
7136 04:41:05.206104 CA_ADMCK_DIV = 4
7137 04:41:05.206159 DQ_TRACK_CA_EN = 0
7138 04:41:05.206214 CA_PICK = 1600
7139 04:41:05.206267 CA_MCKIO = 1600
7140 04:41:05.206323 MCKIO_SEMI = 0
7141 04:41:05.206377 PLL_FREQ = 3068
7142 04:41:05.206428 DQ_UI_PI_RATIO = 32
7143 04:41:05.206480 CA_UI_PI_RATIO = 0
7144 04:41:05.206533 ===================================
7145 04:41:05.206585 ===================================
7146 04:41:05.206656 memory_type:LPDDR4
7147 04:41:05.206725 GP_NUM : 10
7148 04:41:05.206778 SRAM_EN : 1
7149 04:41:05.206833 MD32_EN : 0
7150 04:41:05.206887 ===================================
7151 04:41:05.206938 [ANA_INIT] >>>>>>>>>>>>>>
7152 04:41:05.206989 <<<<<< [CONFIGURE PHASE]: ANA_TX
7153 04:41:05.207080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7154 04:41:05.207187 ===================================
7155 04:41:05.207259 data_rate = 3200,PCW = 0X7600
7156 04:41:05.207315 ===================================
7157 04:41:05.207367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7158 04:41:05.207419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 04:41:05.207470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7160 04:41:05.207522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7161 04:41:05.207577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7162 04:41:05.207632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7163 04:41:05.207685 [ANA_INIT] flow start
7164 04:41:05.207746 [ANA_INIT] PLL >>>>>>>>
7165 04:41:05.207808 [ANA_INIT] PLL <<<<<<<<
7166 04:41:05.207861 [ANA_INIT] MIDPI >>>>>>>>
7167 04:41:05.207912 [ANA_INIT] MIDPI <<<<<<<<
7168 04:41:05.207963 [ANA_INIT] DLL >>>>>>>>
7169 04:41:05.208017 [ANA_INIT] DLL <<<<<<<<
7170 04:41:05.208071 [ANA_INIT] flow end
7171 04:41:05.208123 ============ LP4 DIFF to SE enter ============
7172 04:41:05.208177 ============ LP4 DIFF to SE exit ============
7173 04:41:05.208229 [ANA_INIT] <<<<<<<<<<<<<
7174 04:41:05.208283 [Flow] Enable top DCM control >>>>>
7175 04:41:05.208335 [Flow] Enable top DCM control <<<<<
7176 04:41:05.208386 Enable DLL master slave shuffle
7177 04:41:05.208437 ==============================================================
7178 04:41:05.208489 Gating Mode config
7179 04:41:05.208544 ==============================================================
7180 04:41:05.208599 Config description:
7181 04:41:05.208653 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7182 04:41:05.208750 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7183 04:41:05.208806 SELPH_MODE 0: By rank 1: By Phase
7184 04:41:05.208859 ==============================================================
7185 04:41:05.208911 GAT_TRACK_EN = 1
7186 04:41:05.208962 RX_GATING_MODE = 2
7187 04:41:05.209016 RX_GATING_TRACK_MODE = 2
7188 04:41:05.209068 SELPH_MODE = 1
7189 04:41:05.209123 PICG_EARLY_EN = 1
7190 04:41:05.209176 VALID_LAT_VALUE = 1
7191 04:41:05.209228 ==============================================================
7192 04:41:05.209283 Enter into Gating configuration >>>>
7193 04:41:05.209335 Exit from Gating configuration <<<<
7194 04:41:05.209386 Enter into DVFS_PRE_config >>>>>
7195 04:41:05.209438 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7196 04:41:05.209490 Exit from DVFS_PRE_config <<<<<
7197 04:41:05.209545 Enter into PICG configuration >>>>
7198 04:41:05.209596 Exit from PICG configuration <<<<
7199 04:41:05.209647 [RX_INPUT] configuration >>>>>
7200 04:41:05.209700 [RX_INPUT] configuration <<<<<
7201 04:41:05.209769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7202 04:41:05.209824 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7203 04:41:05.209876 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 04:41:05.209928 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 04:41:05.209979 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 04:41:05.210033 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 04:41:05.210085 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7208 04:41:05.210136 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7209 04:41:05.210187 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7210 04:41:05.210242 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7211 04:41:05.210297 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7212 04:41:05.210350 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 04:41:05.210402 ===================================
7214 04:41:05.210453 LPDDR4 DRAM CONFIGURATION
7215 04:41:05.210519 ===================================
7216 04:41:05.210575 EX_ROW_EN[0] = 0x0
7217 04:41:05.210628 EX_ROW_EN[1] = 0x0
7218 04:41:05.210682 LP4Y_EN = 0x0
7219 04:41:05.210734 WORK_FSP = 0x1
7220 04:41:05.210784 WL = 0x5
7221 04:41:05.210836 RL = 0x5
7222 04:41:05.210887 BL = 0x2
7223 04:41:05.210940 RPST = 0x0
7224 04:41:05.210991 RD_PRE = 0x0
7225 04:41:05.211069 WR_PRE = 0x1
7226 04:41:05.211154 WR_PST = 0x1
7227 04:41:05.211219 DBI_WR = 0x0
7228 04:41:05.211273 DBI_RD = 0x0
7229 04:41:05.211326 OTF = 0x1
7230 04:41:05.211560 ===================================
7231 04:41:05.211659 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7232 04:41:05.211772 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7233 04:41:05.211924 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 04:41:05.212029 ===================================
7235 04:41:05.212133 LPDDR4 DRAM CONFIGURATION
7236 04:41:05.212244 ===================================
7237 04:41:05.212350 EX_ROW_EN[0] = 0x10
7238 04:41:05.212461 EX_ROW_EN[1] = 0x0
7239 04:41:05.212568 LP4Y_EN = 0x0
7240 04:41:05.212709 WORK_FSP = 0x1
7241 04:41:05.212807 WL = 0x5
7242 04:41:05.212892 RL = 0x5
7243 04:41:05.212977 BL = 0x2
7244 04:41:05.213059 RPST = 0x0
7245 04:41:05.213140 RD_PRE = 0x0
7246 04:41:05.213224 WR_PRE = 0x1
7247 04:41:05.213308 WR_PST = 0x1
7248 04:41:05.213393 DBI_WR = 0x0
7249 04:41:05.213476 DBI_RD = 0x0
7250 04:41:05.213562 OTF = 0x1
7251 04:41:05.213646 ===================================
7252 04:41:05.213734 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7253 04:41:05.213815 ==
7254 04:41:05.213891 Dram Type= 6, Freq= 0, CH_0, rank 0
7255 04:41:05.213950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7256 04:41:05.214003 ==
7257 04:41:05.214056 [Duty_Offset_Calibration]
7258 04:41:05.214107 B0:2 B1:-1 CA:1
7259 04:41:05.214206
7260 04:41:05.214261 [DutyScan_Calibration_Flow] k_type=0
7261 04:41:05.214313
7262 04:41:05.214363 ==CLK 0==
7263 04:41:05.214414 Final CLK duty delay cell = -4
7264 04:41:05.214469 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7265 04:41:05.214521 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7266 04:41:05.214572 [-4] AVG Duty = 4937%(X100)
7267 04:41:05.214640
7268 04:41:05.214696 CH0 CLK Duty spec in!! Max-Min= 187%
7269 04:41:05.214748 [DutyScan_Calibration_Flow] ====Done====
7270 04:41:05.214799
7271 04:41:05.214853 [DutyScan_Calibration_Flow] k_type=1
7272 04:41:05.214907
7273 04:41:05.214958 ==DQS 0 ==
7274 04:41:05.215013 Final DQS duty delay cell = 0
7275 04:41:05.215077 [0] MAX Duty = 5125%(X100), DQS PI = 20
7276 04:41:05.215169 [0] MIN Duty = 5000%(X100), DQS PI = 14
7277 04:41:05.215224 [0] AVG Duty = 5062%(X100)
7278 04:41:05.215275
7279 04:41:05.215326 ==DQS 1 ==
7280 04:41:05.215380 Final DQS duty delay cell = -4
7281 04:41:05.215437 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7282 04:41:05.215492 [-4] MIN Duty = 5031%(X100), DQS PI = 6
7283 04:41:05.215545 [-4] AVG Duty = 5062%(X100)
7284 04:41:05.215596
7285 04:41:05.215649 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7286 04:41:05.215702
7287 04:41:05.215755 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7288 04:41:05.215812 [DutyScan_Calibration_Flow] ====Done====
7289 04:41:05.215875
7290 04:41:05.216007 [DutyScan_Calibration_Flow] k_type=3
7291 04:41:05.216059
7292 04:41:05.216113 ==DQM 0 ==
7293 04:41:05.216171 Final DQM duty delay cell = 0
7294 04:41:05.216226 [0] MAX Duty = 5000%(X100), DQS PI = 20
7295 04:41:05.216281 [0] MIN Duty = 4875%(X100), DQS PI = 6
7296 04:41:05.216334 [0] AVG Duty = 4937%(X100)
7297 04:41:05.216385
7298 04:41:05.216439 ==DQM 1 ==
7299 04:41:05.216493 Final DQM duty delay cell = 0
7300 04:41:05.216548 [0] MAX Duty = 5218%(X100), DQS PI = 58
7301 04:41:05.216601 [0] MIN Duty = 4969%(X100), DQS PI = 20
7302 04:41:05.216655 [0] AVG Duty = 5093%(X100)
7303 04:41:05.216762
7304 04:41:05.216851 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7305 04:41:05.216920
7306 04:41:05.216971 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7307 04:41:05.217022 [DutyScan_Calibration_Flow] ====Done====
7308 04:41:05.217075
7309 04:41:05.217127 [DutyScan_Calibration_Flow] k_type=2
7310 04:41:05.217180
7311 04:41:05.217231 ==DQ 0 ==
7312 04:41:05.217282 Final DQ duty delay cell = 0
7313 04:41:05.217333 [0] MAX Duty = 5156%(X100), DQS PI = 0
7314 04:41:05.217383 [0] MIN Duty = 5031%(X100), DQS PI = 12
7315 04:41:05.217437 [0] AVG Duty = 5093%(X100)
7316 04:41:05.217492
7317 04:41:05.217544 ==DQ 1 ==
7318 04:41:05.217594 Final DQ duty delay cell = 0
7319 04:41:05.217648 [0] MAX Duty = 5000%(X100), DQS PI = 12
7320 04:41:05.217699 [0] MIN Duty = 4907%(X100), DQS PI = 26
7321 04:41:05.217753 [0] AVG Duty = 4953%(X100)
7322 04:41:05.217806
7323 04:41:05.217871 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7324 04:41:05.217933
7325 04:41:05.217987 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7326 04:41:05.218039 [DutyScan_Calibration_Flow] ====Done====
7327 04:41:05.218090 ==
7328 04:41:05.218144 Dram Type= 6, Freq= 0, CH_1, rank 0
7329 04:41:05.218199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7330 04:41:05.218252 ==
7331 04:41:05.218304 [Duty_Offset_Calibration]
7332 04:41:05.218354 B0:1 B1:1 CA:2
7333 04:41:05.218408
7334 04:41:05.218458 [DutyScan_Calibration_Flow] k_type=0
7335 04:41:05.218509
7336 04:41:05.218559 ==CLK 0==
7337 04:41:05.218609 Final CLK duty delay cell = 0
7338 04:41:05.218663 [0] MAX Duty = 5187%(X100), DQS PI = 24
7339 04:41:05.218718 [0] MIN Duty = 4938%(X100), DQS PI = 48
7340 04:41:05.218771 [0] AVG Duty = 5062%(X100)
7341 04:41:05.218822
7342 04:41:05.218874 CH1 CLK Duty spec in!! Max-Min= 249%
7343 04:41:05.218937 [DutyScan_Calibration_Flow] ====Done====
7344 04:41:05.219007
7345 04:41:05.219078 [DutyScan_Calibration_Flow] k_type=1
7346 04:41:05.219130
7347 04:41:05.219183 ==DQS 0 ==
7348 04:41:05.219238 Final DQS duty delay cell = 0
7349 04:41:05.219290 [0] MAX Duty = 5062%(X100), DQS PI = 22
7350 04:41:05.219343 [0] MIN Duty = 4813%(X100), DQS PI = 52
7351 04:41:05.219394 [0] AVG Duty = 4937%(X100)
7352 04:41:05.219449
7353 04:41:05.219500 ==DQS 1 ==
7354 04:41:05.219554 Final DQS duty delay cell = 0
7355 04:41:05.219607 [0] MAX Duty = 5031%(X100), DQS PI = 34
7356 04:41:05.219661 [0] MIN Duty = 4938%(X100), DQS PI = 14
7357 04:41:05.219712 [0] AVG Duty = 4984%(X100)
7358 04:41:05.219763
7359 04:41:05.219813 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7360 04:41:05.219863
7361 04:41:05.219917 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7362 04:41:05.219971 [DutyScan_Calibration_Flow] ====Done====
7363 04:41:05.220028
7364 04:41:05.220088 [DutyScan_Calibration_Flow] k_type=3
7365 04:41:05.220142
7366 04:41:05.220195 ==DQM 0 ==
7367 04:41:05.220246 Final DQM duty delay cell = 0
7368 04:41:05.220297 [0] MAX Duty = 5187%(X100), DQS PI = 20
7369 04:41:05.220347 [0] MIN Duty = 4813%(X100), DQS PI = 52
7370 04:41:05.220416 [0] AVG Duty = 5000%(X100)
7371 04:41:05.220467
7372 04:41:05.220517 ==DQM 1 ==
7373 04:41:05.220572 Final DQM duty delay cell = 0
7374 04:41:05.220625 [0] MAX Duty = 5156%(X100), DQS PI = 60
7375 04:41:05.220721 [0] MIN Duty = 4875%(X100), DQS PI = 22
7376 04:41:05.220775 [0] AVG Duty = 5015%(X100)
7377 04:41:05.220826
7378 04:41:05.220876 CH1 DQM 0 Duty spec in!! Max-Min= 374%
7379 04:41:05.220931
7380 04:41:05.220981 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7381 04:41:05.221032 [DutyScan_Calibration_Flow] ====Done====
7382 04:41:05.221086
7383 04:41:05.221139 [DutyScan_Calibration_Flow] k_type=2
7384 04:41:05.221193
7385 04:41:05.221245 ==DQ 0 ==
7386 04:41:05.221296 Final DQ duty delay cell = 0
7387 04:41:05.221347 [0] MAX Duty = 5156%(X100), DQS PI = 20
7388 04:41:05.221400 [0] MIN Duty = 4907%(X100), DQS PI = 52
7389 04:41:05.221451 [0] AVG Duty = 5031%(X100)
7390 04:41:05.221502
7391 04:41:05.221552 ==DQ 1 ==
7392 04:41:05.221812 Final DQ duty delay cell = 0
7393 04:41:05.221888 [0] MAX Duty = 5124%(X100), DQS PI = 42
7394 04:41:05.221943 [0] MIN Duty = 5031%(X100), DQS PI = 0
7395 04:41:05.221995 [0] AVG Duty = 5077%(X100)
7396 04:41:05.222045
7397 04:41:05.222095 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7398 04:41:05.222149
7399 04:41:05.222200 CH1 DQ 1 Duty spec in!! Max-Min= 93%
7400 04:41:05.222250 [DutyScan_Calibration_Flow] ====Done====
7401 04:41:05.222305 nWR fixed to 30
7402 04:41:05.222361 [ModeRegInit_LP4] CH0 RK0
7403 04:41:05.222416 [ModeRegInit_LP4] CH0 RK1
7404 04:41:05.222466 [ModeRegInit_LP4] CH1 RK0
7405 04:41:05.222517 [ModeRegInit_LP4] CH1 RK1
7406 04:41:05.222567 match AC timing 5
7407 04:41:05.222618 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7408 04:41:05.222673 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7409 04:41:05.222726 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7410 04:41:05.222777 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7411 04:41:05.222829 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7412 04:41:05.222879 [MiockJmeterHQA]
7413 04:41:05.222933
7414 04:41:05.222983 [DramcMiockJmeter] u1RxGatingPI = 0
7415 04:41:05.223033 0 : 4252, 4027
7416 04:41:05.223085 4 : 4253, 4027
7417 04:41:05.223138 8 : 4363, 4137
7418 04:41:05.223192 12 : 4253, 4027
7419 04:41:05.223248 16 : 4252, 4027
7420 04:41:05.223301 20 : 4363, 4138
7421 04:41:05.223409 24 : 4360, 4137
7422 04:41:05.223481 28 : 4252, 4027
7423 04:41:05.223533 32 : 4250, 4027
7424 04:41:05.223584 36 : 4250, 4026
7425 04:41:05.223635 40 : 4363, 4138
7426 04:41:05.223690 44 : 4250, 4027
7427 04:41:05.223746 48 : 4361, 4137
7428 04:41:05.223799 52 : 4253, 4027
7429 04:41:05.223850 56 : 4250, 4026
7430 04:41:05.223929 60 : 4250, 4027
7431 04:41:05.223997 64 : 4252, 4029
7432 04:41:05.224049 68 : 4250, 4026
7433 04:41:05.224100 72 : 4250, 4027
7434 04:41:05.224153 76 : 4363, 4140
7435 04:41:05.224205 80 : 4250, 4027
7436 04:41:05.224259 84 : 4252, 4029
7437 04:41:05.224311 88 : 4250, 4026
7438 04:41:05.224364 92 : 4360, 4138
7439 04:41:05.224419 96 : 4249, 3223
7440 04:41:05.224470 100 : 4361, 0
7441 04:41:05.224521 104 : 4361, 0
7442 04:41:05.224572 108 : 4250, 0
7443 04:41:05.224623 112 : 4360, 0
7444 04:41:05.224720 116 : 4250, 0
7445 04:41:05.224773 120 : 4250, 0
7446 04:41:05.224825 124 : 4250, 0
7447 04:41:05.224876 128 : 4250, 0
7448 04:41:05.224930 132 : 4253, 0
7449 04:41:05.224986 136 : 4360, 0
7450 04:41:05.225039 140 : 4360, 0
7451 04:41:05.225091 144 : 4248, 0
7452 04:41:05.225144 148 : 4250, 0
7453 04:41:05.225196 152 : 4360, 0
7454 04:41:05.225247 156 : 4361, 0
7455 04:41:05.225299 160 : 4250, 0
7456 04:41:05.225353 164 : 4361, 0
7457 04:41:05.225408 168 : 4250, 0
7458 04:41:05.225461 172 : 4250, 0
7459 04:41:05.225512 176 : 4250, 0
7460 04:41:05.225563 180 : 4250, 0
7461 04:41:05.225617 184 : 4253, 0
7462 04:41:05.225672 188 : 4360, 0
7463 04:41:05.225725 192 : 4250, 0
7464 04:41:05.225777 196 : 4250, 0
7465 04:41:05.225829 200 : 4249, 0
7466 04:41:05.225880 204 : 4360, 0
7467 04:41:05.225934 208 : 4361, 0
7468 04:41:05.225985 212 : 4250, 29
7469 04:41:05.226037 216 : 4360, 3512
7470 04:41:05.226088 220 : 4250, 4027
7471 04:41:05.226143 224 : 4251, 4027
7472 04:41:05.226198 228 : 4252, 4029
7473 04:41:05.226252 232 : 4250, 4027
7474 04:41:05.226307 236 : 4250, 4027
7475 04:41:05.226358 240 : 4250, 4027
7476 04:41:05.226413 244 : 4250, 4027
7477 04:41:05.226464 248 : 4250, 4027
7478 04:41:05.226515 252 : 4360, 4138
7479 04:41:05.226589 256 : 4360, 4138
7480 04:41:05.226647 260 : 4250, 4026
7481 04:41:05.226702 264 : 4363, 4139
7482 04:41:05.226756 268 : 4360, 4138
7483 04:41:05.226808 272 : 4250, 4027
7484 04:41:05.226860 276 : 4250, 4027
7485 04:41:05.226914 280 : 4252, 4029
7486 04:41:05.226969 284 : 4250, 4027
7487 04:41:05.227022 288 : 4250, 4027
7488 04:41:05.227074 292 : 4250, 4027
7489 04:41:05.227136 296 : 4252, 4029
7490 04:41:05.227192 300 : 4250, 4027
7491 04:41:05.227244 304 : 4360, 4138
7492 04:41:05.227320 308 : 4360, 4138
7493 04:41:05.227404 312 : 4250, 4027
7494 04:41:05.227474 316 : 4363, 4139
7495 04:41:05.227529 320 : 4360, 4138
7496 04:41:05.227583 324 : 4250, 4027
7497 04:41:05.227637 328 : 4250, 4027
7498 04:41:05.227689 332 : 4252, 3163
7499 04:41:05.227740 336 : 4250, 62
7500 04:41:05.227791
7501 04:41:05.227845 MIOCK jitter meter ch=0
7502 04:41:05.227899
7503 04:41:05.227952 1T = (336-100) = 236 dly cells
7504 04:41:05.228007 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7505 04:41:05.228058 ==
7506 04:41:05.228109 Dram Type= 6, Freq= 0, CH_0, rank 0
7507 04:41:05.228163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7508 04:41:05.228218 ==
7509 04:41:05.228270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7510 04:41:05.228322 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7511 04:41:05.228373 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7512 04:41:05.228427 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7513 04:41:05.228478 [CA 0] Center 44 (14~75) winsize 62
7514 04:41:05.228529 [CA 1] Center 44 (14~74) winsize 61
7515 04:41:05.228583 [CA 2] Center 39 (10~68) winsize 59
7516 04:41:05.228636 [CA 3] Center 39 (10~68) winsize 59
7517 04:41:05.228754 [CA 4] Center 37 (7~67) winsize 61
7518 04:41:05.228836 [CA 5] Center 37 (7~67) winsize 61
7519 04:41:05.228919
7520 04:41:05.229000 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7521 04:41:05.229091
7522 04:41:05.229156 [CATrainingPosCal] consider 1 rank data
7523 04:41:05.229210 u2DelayCellTimex100 = 275/100 ps
7524 04:41:05.229261 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7525 04:41:05.229312 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7526 04:41:05.229364 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7527 04:41:05.229417 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7528 04:41:05.229472 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7529 04:41:05.229526 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7530 04:41:05.229576
7531 04:41:05.229627 CA PerBit enable=1, Macro0, CA PI delay=37
7532 04:41:05.229681
7533 04:41:05.229732 [CBTSetCACLKResult] CA Dly = 37
7534 04:41:05.229783 CS Dly: 10 (0~41)
7535 04:41:05.229834 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7536 04:41:05.229884 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7537 04:41:05.229960 ==
7538 04:41:05.230030 Dram Type= 6, Freq= 0, CH_0, rank 1
7539 04:41:05.230092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 04:41:05.230173 ==
7541 04:41:05.230231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7542 04:41:05.230292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7543 04:41:05.230353 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7544 04:41:05.230413 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7545 04:41:05.230478 [CA 0] Center 44 (14~75) winsize 62
7546 04:41:05.230544 [CA 1] Center 44 (14~75) winsize 62
7547 04:41:05.230598 [CA 2] Center 40 (11~69) winsize 59
7548 04:41:05.230657 [CA 3] Center 39 (10~69) winsize 60
7549 04:41:05.230723 [CA 4] Center 38 (8~68) winsize 61
7550 04:41:05.230784 [CA 5] Center 37 (7~67) winsize 61
7551 04:41:05.230850
7552 04:41:05.230913 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7553 04:41:05.230986
7554 04:41:05.231041 [CATrainingPosCal] consider 2 rank data
7555 04:41:05.231125 u2DelayCellTimex100 = 275/100 ps
7556 04:41:05.231183 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7557 04:41:05.231446 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7558 04:41:05.231554 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7559 04:41:05.231677 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7560 04:41:05.231803 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7561 04:41:05.231911 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7562 04:41:05.232014
7563 04:41:05.232122 CA PerBit enable=1, Macro0, CA PI delay=37
7564 04:41:05.232225
7565 04:41:05.232337 [CBTSetCACLKResult] CA Dly = 37
7566 04:41:05.232447 CS Dly: 11 (0~44)
7567 04:41:05.232554 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7568 04:41:05.232647 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7569 04:41:05.232754
7570 04:41:05.232815 ----->DramcWriteLeveling(PI) begin...
7571 04:41:05.232886 ==
7572 04:41:05.232950 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 04:41:05.233005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 04:41:05.233064 ==
7575 04:41:05.233123 Write leveling (Byte 0): 34 => 34
7576 04:41:05.233183 Write leveling (Byte 1): 30 => 30
7577 04:41:05.233248 DramcWriteLeveling(PI) end<-----
7578 04:41:05.233308
7579 04:41:05.233368 ==
7580 04:41:05.233434 Dram Type= 6, Freq= 0, CH_0, rank 0
7581 04:41:05.233494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 04:41:05.233564 ==
7583 04:41:05.233632 [Gating] SW mode calibration
7584 04:41:05.233694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7585 04:41:05.233755 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7586 04:41:05.233816 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 04:41:05.233882 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 04:41:05.233942 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 04:41:05.234001 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 04:41:05.234061 1 4 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7591 04:41:05.234127 1 4 20 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
7592 04:41:05.234188 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7593 04:41:05.234248 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 04:41:05.234310 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 04:41:05.234377 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 04:41:05.234432 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 04:41:05.234486 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 04:41:05.234537 1 5 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7599 04:41:05.234587 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7600 04:41:05.234639 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
7601 04:41:05.234693 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 04:41:05.234747 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 04:41:05.234800 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 04:41:05.234851 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 04:41:05.234904 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 04:41:05.234956 1 6 16 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7607 04:41:05.235006 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7608 04:41:05.235057 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7609 04:41:05.235108 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 04:41:05.235175 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 04:41:05.235231 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 04:41:05.235287 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 04:41:05.235340 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 04:41:05.235394 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 04:41:05.235446 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7616 04:41:05.235496 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 04:41:05.235547 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 04:41:05.235598 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 04:41:05.235653 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 04:41:05.235707 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 04:41:05.235760 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 04:41:05.235811 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 04:41:05.235862 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 04:41:05.235913 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 04:41:05.235967 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 04:41:05.236019 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 04:41:05.236070 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 04:41:05.236122 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 04:41:05.236175 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 04:41:05.236230 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7631 04:41:05.236282 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7632 04:41:05.236333 Total UI for P1: 0, mck2ui 16
7633 04:41:05.236385 best dqsien dly found for B0: ( 1, 9, 16)
7634 04:41:05.236440 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7635 04:41:05.236490 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 04:41:05.236545 Total UI for P1: 0, mck2ui 16
7637 04:41:05.236598 best dqsien dly found for B1: ( 1, 9, 20)
7638 04:41:05.236652 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7639 04:41:05.236746 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7640 04:41:05.236797
7641 04:41:05.236849 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7642 04:41:05.236900 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7643 04:41:05.236954 [Gating] SW calibration Done
7644 04:41:05.237009 ==
7645 04:41:05.237062 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 04:41:05.237126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 04:41:05.237181 ==
7648 04:41:05.237232 RX Vref Scan: 0
7649 04:41:05.237282
7650 04:41:05.237337 RX Vref 0 -> 0, step: 1
7651 04:41:05.237392
7652 04:41:05.237445 RX Delay 0 -> 252, step: 8
7653 04:41:05.237501 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7654 04:41:05.237553 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7655 04:41:05.237608 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7656 04:41:05.237660 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7657 04:41:05.237711 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7658 04:41:05.237947 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7659 04:41:05.238008 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7660 04:41:05.238064 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7661 04:41:05.238115 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7662 04:41:05.238167 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7663 04:41:05.238221 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7664 04:41:05.238276 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7665 04:41:05.238328 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7666 04:41:05.238380 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7667 04:41:05.238430 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7668 04:41:05.238481 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7669 04:41:05.238535 ==
7670 04:41:05.238593 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 04:41:05.238646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 04:41:05.238703 ==
7673 04:41:05.238760 DQS Delay:
7674 04:41:05.238811 DQS0 = 0, DQS1 = 0
7675 04:41:05.238861 DQM Delay:
7676 04:41:05.238916 DQM0 = 132, DQM1 = 123
7677 04:41:05.238966 DQ Delay:
7678 04:41:05.239017 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7679 04:41:05.239067 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7680 04:41:05.239118 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7681 04:41:05.239172 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7682 04:41:05.239223
7683 04:41:05.239272
7684 04:41:05.239322 ==
7685 04:41:05.239373 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 04:41:05.239427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 04:41:05.239482 ==
7688 04:41:05.239534
7689 04:41:05.239585
7690 04:41:05.239637 TX Vref Scan disable
7691 04:41:05.239689 == TX Byte 0 ==
7692 04:41:05.239738 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7693 04:41:05.239790 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7694 04:41:05.239845 == TX Byte 1 ==
7695 04:41:05.239898 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7696 04:41:05.239953 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7697 04:41:05.240004 ==
7698 04:41:05.240054 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 04:41:05.240105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 04:41:05.240159 ==
7701 04:41:05.240214
7702 04:41:05.240266 TX Vref early break, caculate TX vref
7703 04:41:05.240317 TX Vref=16, minBit 1, minWin=22, winSum=369
7704 04:41:05.240371 TX Vref=18, minBit 7, minWin=22, winSum=379
7705 04:41:05.240425 TX Vref=20, minBit 1, minWin=23, winSum=391
7706 04:41:05.240479 TX Vref=22, minBit 7, minWin=23, winSum=400
7707 04:41:05.240533 TX Vref=24, minBit 4, minWin=24, winSum=414
7708 04:41:05.240586 TX Vref=26, minBit 0, minWin=25, winSum=419
7709 04:41:05.240697 TX Vref=28, minBit 4, minWin=25, winSum=423
7710 04:41:05.240768 TX Vref=30, minBit 0, minWin=26, winSum=428
7711 04:41:05.240824 TX Vref=32, minBit 4, minWin=24, winSum=416
7712 04:41:05.240876 TX Vref=34, minBit 2, minWin=25, winSum=409
7713 04:41:05.240927 TX Vref=36, minBit 10, minWin=23, winSum=397
7714 04:41:05.240978 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
7715 04:41:05.241033
7716 04:41:05.241084 Final TX Range 0 Vref 30
7717 04:41:05.241139
7718 04:41:05.241191 ==
7719 04:41:05.241242 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 04:41:05.241296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 04:41:05.241347 ==
7722 04:41:05.241398
7723 04:41:05.241451
7724 04:41:05.241503 TX Vref Scan disable
7725 04:41:05.241557 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7726 04:41:05.241609 == TX Byte 0 ==
7727 04:41:05.241659 u2DelayCellOfst[0]=14 cells (4 PI)
7728 04:41:05.241710 u2DelayCellOfst[1]=21 cells (6 PI)
7729 04:41:05.241761 u2DelayCellOfst[2]=14 cells (4 PI)
7730 04:41:05.241815 u2DelayCellOfst[3]=17 cells (5 PI)
7731 04:41:05.241865 u2DelayCellOfst[4]=10 cells (3 PI)
7732 04:41:05.241916 u2DelayCellOfst[5]=0 cells (0 PI)
7733 04:41:05.241967 u2DelayCellOfst[6]=21 cells (6 PI)
7734 04:41:05.242034 u2DelayCellOfst[7]=21 cells (6 PI)
7735 04:41:05.242087 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7736 04:41:05.242139 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7737 04:41:05.242189 == TX Byte 1 ==
7738 04:41:05.242243 u2DelayCellOfst[8]=0 cells (0 PI)
7739 04:41:05.242303 u2DelayCellOfst[9]=0 cells (0 PI)
7740 04:41:05.242354 u2DelayCellOfst[10]=3 cells (1 PI)
7741 04:41:05.242405 u2DelayCellOfst[11]=0 cells (0 PI)
7742 04:41:05.242456 u2DelayCellOfst[12]=10 cells (3 PI)
7743 04:41:05.242510 u2DelayCellOfst[13]=10 cells (3 PI)
7744 04:41:05.242565 u2DelayCellOfst[14]=14 cells (4 PI)
7745 04:41:05.242620 u2DelayCellOfst[15]=10 cells (3 PI)
7746 04:41:05.242673 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7747 04:41:05.242724 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7748 04:41:05.242775 DramC Write-DBI on
7749 04:41:05.242837 ==
7750 04:41:05.242942 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 04:41:05.242997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 04:41:05.243051 ==
7753 04:41:05.243102
7754 04:41:05.243153
7755 04:41:05.243203 TX Vref Scan disable
7756 04:41:05.243256 == TX Byte 0 ==
7757 04:41:05.243307 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7758 04:41:05.243362 == TX Byte 1 ==
7759 04:41:05.243413 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7760 04:41:05.243464 DramC Write-DBI off
7761 04:41:05.243514
7762 04:41:05.243571 [DATLAT]
7763 04:41:05.243623 Freq=1600, CH0 RK0
7764 04:41:05.243686
7765 04:41:05.243738 DATLAT Default: 0xf
7766 04:41:05.243793 0, 0xFFFF, sum = 0
7767 04:41:05.243849 1, 0xFFFF, sum = 0
7768 04:41:05.243903 2, 0xFFFF, sum = 0
7769 04:41:05.243959 3, 0xFFFF, sum = 0
7770 04:41:05.244034 4, 0xFFFF, sum = 0
7771 04:41:05.244089 5, 0xFFFF, sum = 0
7772 04:41:05.244141 6, 0xFFFF, sum = 0
7773 04:41:05.244192 7, 0xFFFF, sum = 0
7774 04:41:05.244248 8, 0xFFFF, sum = 0
7775 04:41:05.244302 9, 0xFFFF, sum = 0
7776 04:41:05.244357 10, 0xFFFF, sum = 0
7777 04:41:05.244409 11, 0xFFFF, sum = 0
7778 04:41:05.244461 12, 0xFFFF, sum = 0
7779 04:41:05.244513 13, 0xFFFF, sum = 0
7780 04:41:05.244567 14, 0x0, sum = 1
7781 04:41:05.244619 15, 0x0, sum = 2
7782 04:41:05.244751 16, 0x0, sum = 3
7783 04:41:05.244857 17, 0x0, sum = 4
7784 04:41:05.244915 best_step = 15
7785 04:41:05.244967
7786 04:41:05.245021 ==
7787 04:41:05.245072 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 04:41:05.245127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 04:41:05.245181 ==
7790 04:41:05.245233 RX Vref Scan: 1
7791 04:41:05.245288
7792 04:41:05.245338 Set Vref Range= 24 -> 127
7793 04:41:05.245389
7794 04:41:05.245439 RX Vref 24 -> 127, step: 1
7795 04:41:05.245490
7796 04:41:05.245543 RX Delay 11 -> 252, step: 4
7797 04:41:05.245593
7798 04:41:05.245643 Set Vref, RX VrefLevel [Byte0]: 24
7799 04:41:05.245694 [Byte1]: 24
7800 04:41:05.245745
7801 04:41:05.245805 Set Vref, RX VrefLevel [Byte0]: 25
7802 04:41:05.245856 [Byte1]: 25
7803 04:41:05.245907
7804 04:41:05.245961 Set Vref, RX VrefLevel [Byte0]: 26
7805 04:41:05.246022 [Byte1]: 26
7806 04:41:05.246074
7807 04:41:05.246310 Set Vref, RX VrefLevel [Byte0]: 27
7808 04:41:05.246373 [Byte1]: 27
7809 04:41:05.246443
7810 04:41:05.246549 Set Vref, RX VrefLevel [Byte0]: 28
7811 04:41:05.246652 [Byte1]: 28
7812 04:41:05.246760
7813 04:41:05.246865 Set Vref, RX VrefLevel [Byte0]: 29
7814 04:41:05.247000 [Byte1]: 29
7815 04:41:05.247127
7816 04:41:05.247235 Set Vref, RX VrefLevel [Byte0]: 30
7817 04:41:05.247339 [Byte1]: 30
7818 04:41:05.247422
7819 04:41:05.247508 Set Vref, RX VrefLevel [Byte0]: 31
7820 04:41:05.247594 [Byte1]: 31
7821 04:41:05.247678
7822 04:41:05.247762 Set Vref, RX VrefLevel [Byte0]: 32
7823 04:41:05.247842 [Byte1]: 32
7824 04:41:05.247925
7825 04:41:05.248057 Set Vref, RX VrefLevel [Byte0]: 33
7826 04:41:05.248147 [Byte1]: 33
7827 04:41:05.248230
7828 04:41:05.248314 Set Vref, RX VrefLevel [Byte0]: 34
7829 04:41:05.248399 [Byte1]: 34
7830 04:41:05.248479
7831 04:41:05.248564 Set Vref, RX VrefLevel [Byte0]: 35
7832 04:41:05.248651 [Byte1]: 35
7833 04:41:05.248752
7834 04:41:05.248804 Set Vref, RX VrefLevel [Byte0]: 36
7835 04:41:05.248855 [Byte1]: 36
7836 04:41:05.248910
7837 04:41:05.248960 Set Vref, RX VrefLevel [Byte0]: 37
7838 04:41:05.249010 [Byte1]: 37
7839 04:41:05.249060
7840 04:41:05.249114 Set Vref, RX VrefLevel [Byte0]: 38
7841 04:41:05.249169 [Byte1]: 38
7842 04:41:05.249222
7843 04:41:05.249273 Set Vref, RX VrefLevel [Byte0]: 39
7844 04:41:05.249323 [Byte1]: 39
7845 04:41:05.249373
7846 04:41:05.249427 Set Vref, RX VrefLevel [Byte0]: 40
7847 04:41:05.249481 [Byte1]: 40
7848 04:41:05.249532
7849 04:41:05.249582 Set Vref, RX VrefLevel [Byte0]: 41
7850 04:41:05.249632 [Byte1]: 41
7851 04:41:05.249685
7852 04:41:05.249735 Set Vref, RX VrefLevel [Byte0]: 42
7853 04:41:05.249786 [Byte1]: 42
7854 04:41:05.249836
7855 04:41:05.249885 Set Vref, RX VrefLevel [Byte0]: 43
7856 04:41:05.249939 [Byte1]: 43
7857 04:41:05.250002
7858 04:41:05.250090 Set Vref, RX VrefLevel [Byte0]: 44
7859 04:41:05.250144 [Byte1]: 44
7860 04:41:05.250198
7861 04:41:05.250249 Set Vref, RX VrefLevel [Byte0]: 45
7862 04:41:05.250298 [Byte1]: 45
7863 04:41:05.250349
7864 04:41:05.250413 Set Vref, RX VrefLevel [Byte0]: 46
7865 04:41:05.250468 [Byte1]: 46
7866 04:41:05.250525
7867 04:41:05.250579 Set Vref, RX VrefLevel [Byte0]: 47
7868 04:41:05.250645 [Byte1]: 47
7869 04:41:05.250700
7870 04:41:05.250752 Set Vref, RX VrefLevel [Byte0]: 48
7871 04:41:05.250807 [Byte1]: 48
7872 04:41:05.250857
7873 04:41:05.250908 Set Vref, RX VrefLevel [Byte0]: 49
7874 04:41:05.250959 [Byte1]: 49
7875 04:41:05.251010
7876 04:41:05.251063 Set Vref, RX VrefLevel [Byte0]: 50
7877 04:41:05.251114 [Byte1]: 50
7878 04:41:05.251168
7879 04:41:05.251220 Set Vref, RX VrefLevel [Byte0]: 51
7880 04:41:05.251274 [Byte1]: 51
7881 04:41:05.251325
7882 04:41:05.251375 Set Vref, RX VrefLevel [Byte0]: 52
7883 04:41:05.251425 [Byte1]: 52
7884 04:41:05.251476
7885 04:41:05.251529 Set Vref, RX VrefLevel [Byte0]: 53
7886 04:41:05.251583 [Byte1]: 53
7887 04:41:05.251634
7888 04:41:05.251686 Set Vref, RX VrefLevel [Byte0]: 54
7889 04:41:05.251737 [Byte1]: 54
7890 04:41:05.251791
7891 04:41:05.251841 Set Vref, RX VrefLevel [Byte0]: 55
7892 04:41:05.251892 [Byte1]: 55
7893 04:41:05.251942
7894 04:41:05.252001 Set Vref, RX VrefLevel [Byte0]: 56
7895 04:41:05.252057 [Byte1]: 56
7896 04:41:05.252112
7897 04:41:05.252164 Set Vref, RX VrefLevel [Byte0]: 57
7898 04:41:05.252214 [Byte1]: 57
7899 04:41:05.252264
7900 04:41:05.252318 Set Vref, RX VrefLevel [Byte0]: 58
7901 04:41:05.252369 [Byte1]: 58
7902 04:41:05.252419
7903 04:41:05.252469 Set Vref, RX VrefLevel [Byte0]: 59
7904 04:41:05.252523 [Byte1]: 59
7905 04:41:05.252574
7906 04:41:05.252624 Set Vref, RX VrefLevel [Byte0]: 60
7907 04:41:05.252738 [Byte1]: 60
7908 04:41:05.252796
7909 04:41:05.252847 Set Vref, RX VrefLevel [Byte0]: 61
7910 04:41:05.252898 [Byte1]: 61
7911 04:41:05.252949
7912 04:41:05.252999 Set Vref, RX VrefLevel [Byte0]: 62
7913 04:41:05.253054 [Byte1]: 62
7914 04:41:05.253109
7915 04:41:05.253163 Set Vref, RX VrefLevel [Byte0]: 63
7916 04:41:05.253217 [Byte1]: 63
7917 04:41:05.253271
7918 04:41:05.253322 Set Vref, RX VrefLevel [Byte0]: 64
7919 04:41:05.253372 [Byte1]: 64
7920 04:41:05.253423
7921 04:41:05.253477 Set Vref, RX VrefLevel [Byte0]: 65
7922 04:41:05.253529 [Byte1]: 65
7923 04:41:05.253584
7924 04:41:05.253636 Set Vref, RX VrefLevel [Byte0]: 66
7925 04:41:05.253701 [Byte1]: 66
7926 04:41:05.253753
7927 04:41:05.253807 Set Vref, RX VrefLevel [Byte0]: 67
7928 04:41:05.253862 [Byte1]: 67
7929 04:41:05.253915
7930 04:41:05.253969 Set Vref, RX VrefLevel [Byte0]: 68
7931 04:41:05.254035 [Byte1]: 68
7932 04:41:05.254122
7933 04:41:05.254186 Set Vref, RX VrefLevel [Byte0]: 69
7934 04:41:05.254286 [Byte1]: 69
7935 04:41:05.254366
7936 04:41:05.254450 Set Vref, RX VrefLevel [Byte0]: 70
7937 04:41:05.254534 [Byte1]: 70
7938 04:41:05.254614
7939 04:41:05.254697 Set Vref, RX VrefLevel [Byte0]: 71
7940 04:41:05.254779 [Byte1]: 71
7941 04:41:05.254861
7942 04:41:05.254946 Set Vref, RX VrefLevel [Byte0]: 72
7943 04:41:05.255029 [Byte1]: 72
7944 04:41:05.255109
7945 04:41:05.255189 Set Vref, RX VrefLevel [Byte0]: 73
7946 04:41:05.255269 [Byte1]: 73
7947 04:41:05.255351
7948 04:41:05.255434 Set Vref, RX VrefLevel [Byte0]: 74
7949 04:41:05.255519 [Byte1]: 74
7950 04:41:05.255598
7951 04:41:05.255678 Set Vref, RX VrefLevel [Byte0]: 75
7952 04:41:05.255758 [Byte1]: 75
7953 04:41:05.255840
7954 04:41:05.255924 Set Vref, RX VrefLevel [Byte0]: 76
7955 04:41:05.255976 [Byte1]: 76
7956 04:41:05.256030
7957 04:41:05.256081 Final RX Vref Byte 0 = 58 to rank0
7958 04:41:05.480186 Final RX Vref Byte 1 = 62 to rank0
7959 04:41:05.480326 Final RX Vref Byte 0 = 58 to rank1
7960 04:41:05.480397 Final RX Vref Byte 1 = 62 to rank1==
7961 04:41:05.480460 Dram Type= 6, Freq= 0, CH_0, rank 0
7962 04:41:05.480520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 04:41:05.480576 ==
7964 04:41:05.480632 DQS Delay:
7965 04:41:05.480718 DQS0 = 0, DQS1 = 0
7966 04:41:05.480790 DQM Delay:
7967 04:41:05.480845 DQM0 = 130, DQM1 = 121
7968 04:41:05.480899 DQ Delay:
7969 04:41:05.481164 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =128
7970 04:41:05.481242 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7971 04:41:05.481295 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7972 04:41:05.481348 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7973 04:41:05.481403
7974 04:41:05.481457
7975 04:41:05.481510
7976 04:41:05.481562 [DramC_TX_OE_Calibration] TA2
7977 04:41:05.481612 Original DQ_B0 (3 6) =30, OEN = 27
7978 04:41:05.481667 Original DQ_B1 (3 6) =30, OEN = 27
7979 04:41:05.481721 24, 0x0, End_B0=24 End_B1=24
7980 04:41:05.481773 25, 0x0, End_B0=25 End_B1=25
7981 04:41:05.481828 26, 0x0, End_B0=26 End_B1=26
7982 04:41:05.481883 27, 0x0, End_B0=27 End_B1=27
7983 04:41:05.481937 28, 0x0, End_B0=28 End_B1=28
7984 04:41:05.481989 29, 0x0, End_B0=29 End_B1=29
7985 04:41:05.482041 30, 0x0, End_B0=30 End_B1=30
7986 04:41:05.482096 31, 0x4141, End_B0=30 End_B1=30
7987 04:41:05.482197 Byte0 end_step=30 best_step=27
7988 04:41:05.482248 Byte1 end_step=30 best_step=27
7989 04:41:05.482302 Byte0 TX OE(2T, 0.5T) = (3, 3)
7990 04:41:05.482353 Byte1 TX OE(2T, 0.5T) = (3, 3)
7991 04:41:05.482408
7992 04:41:05.482460
7993 04:41:05.482511 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7994 04:41:05.482568 CH0 RK0: MR19=303, MR18=1509
7995 04:41:05.482620 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7996 04:41:05.482671
7997 04:41:05.482721 ----->DramcWriteLeveling(PI) begin...
7998 04:41:05.482776 ==
7999 04:41:05.482827 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 04:41:05.482877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 04:41:05.482928 ==
8002 04:41:05.482978 Write leveling (Byte 0): 32 => 32
8003 04:41:05.483032 Write leveling (Byte 1): 26 => 26
8004 04:41:05.483085 DramcWriteLeveling(PI) end<-----
8005 04:41:05.483136
8006 04:41:05.483188 ==
8007 04:41:05.483238 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 04:41:05.483293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 04:41:05.483346 ==
8010 04:41:05.483396 [Gating] SW mode calibration
8011 04:41:05.483447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8012 04:41:05.483502 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8013 04:41:05.483555 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 04:41:05.483606 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 04:41:05.483661 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8016 04:41:05.483746 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
8017 04:41:05.483859 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8018 04:41:05.483936 1 4 20 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
8019 04:41:05.483989 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 04:41:05.484041 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 04:41:05.484092 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 04:41:05.484146 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 04:41:05.484197 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8024 04:41:05.484252 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
8025 04:41:05.484305 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8026 04:41:05.484373 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
8027 04:41:05.484442 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 04:41:05.484495 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 04:41:05.484546 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 04:41:05.484597 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 04:41:05.484654 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8032 04:41:05.484764 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8033 04:41:05.484817 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8034 04:41:05.484868 1 6 20 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8035 04:41:05.484922 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 04:41:05.484974 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 04:41:05.485025 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 04:41:05.485075 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 04:41:05.485126 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8040 04:41:05.485179 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8041 04:41:05.485230 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 04:41:05.485284 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8043 04:41:05.485335 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 04:41:05.485390 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 04:41:05.485443 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 04:41:05.485493 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 04:41:05.485544 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 04:41:05.485595 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 04:41:05.485648 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 04:41:05.485699 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 04:41:05.485756 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 04:41:05.485807 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 04:41:05.485897 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 04:41:05.485966 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 04:41:05.486019 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8056 04:41:05.486070 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8057 04:41:05.486121 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8058 04:41:05.486175 Total UI for P1: 0, mck2ui 16
8059 04:41:05.486230 best dqsien dly found for B0: ( 1, 9, 8)
8060 04:41:05.486284 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8061 04:41:05.486336 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 04:41:05.486388 Total UI for P1: 0, mck2ui 16
8063 04:41:05.486443 best dqsien dly found for B1: ( 1, 9, 20)
8064 04:41:05.486497 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8065 04:41:05.486548 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8066 04:41:05.486599
8067 04:41:05.486652 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8068 04:41:05.486706 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8069 04:41:05.486950 [Gating] SW calibration Done
8070 04:41:05.487014 ==
8071 04:41:05.487069 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 04:41:05.487120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 04:41:05.487172 ==
8074 04:41:05.487226 RX Vref Scan: 0
8075 04:41:05.487280
8076 04:41:05.487332 RX Vref 0 -> 0, step: 1
8077 04:41:05.487385
8078 04:41:05.487439 RX Delay 0 -> 252, step: 8
8079 04:41:05.487521 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8080 04:41:05.487594 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8081 04:41:05.487651 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8082 04:41:05.487705 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8083 04:41:05.487758 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8084 04:41:05.487810 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8085 04:41:05.487864 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8086 04:41:05.487918 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8087 04:41:05.487971 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8088 04:41:05.488022 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8089 04:41:05.488073 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8090 04:41:05.488124 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8091 04:41:05.488177 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8092 04:41:05.488231 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8093 04:41:05.488285 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8094 04:41:05.488336 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8095 04:41:05.488391 ==
8096 04:41:05.488445 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 04:41:05.488498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 04:41:05.488549 ==
8099 04:41:05.488604 DQS Delay:
8100 04:41:05.488657 DQS0 = 0, DQS1 = 0
8101 04:41:05.488753 DQM Delay:
8102 04:41:05.488807 DQM0 = 131, DQM1 = 124
8103 04:41:05.488858 DQ Delay:
8104 04:41:05.488913 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8105 04:41:05.488967 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8106 04:41:05.489018 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8107 04:41:05.489071 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8108 04:41:05.489125
8109 04:41:05.489179
8110 04:41:05.489232 ==
8111 04:41:05.489287 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 04:41:05.489339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 04:41:05.489394 ==
8114 04:41:05.489458
8115 04:41:05.489513
8116 04:41:05.489564 TX Vref Scan disable
8117 04:41:05.489617 == TX Byte 0 ==
8118 04:41:05.489670 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8119 04:41:05.489740 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8120 04:41:05.489797 == TX Byte 1 ==
8121 04:41:05.489865 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8122 04:41:05.489916 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8123 04:41:05.489968 ==
8124 04:41:05.490021 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 04:41:05.490073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 04:41:05.490140 ==
8127 04:41:05.490206
8128 04:41:05.490277 TX Vref early break, caculate TX vref
8129 04:41:05.490333 TX Vref=16, minBit 3, minWin=22, winSum=371
8130 04:41:05.490419 TX Vref=18, minBit 9, minWin=22, winSum=378
8131 04:41:05.490508 TX Vref=20, minBit 3, minWin=23, winSum=393
8132 04:41:05.490594 TX Vref=22, minBit 8, minWin=24, winSum=399
8133 04:41:05.490649 TX Vref=24, minBit 3, minWin=24, winSum=403
8134 04:41:05.490705 TX Vref=26, minBit 4, minWin=25, winSum=414
8135 04:41:05.490762 TX Vref=28, minBit 0, minWin=26, winSum=422
8136 04:41:05.490818 TX Vref=30, minBit 10, minWin=25, winSum=420
8137 04:41:05.490873 TX Vref=32, minBit 8, minWin=24, winSum=411
8138 04:41:05.490925 TX Vref=34, minBit 1, minWin=24, winSum=401
8139 04:41:05.490981 TX Vref=36, minBit 13, minWin=23, winSum=394
8140 04:41:05.491036 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
8141 04:41:05.491092
8142 04:41:05.491144 Final TX Range 0 Vref 28
8143 04:41:05.491199
8144 04:41:05.491255 ==
8145 04:41:05.491323 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 04:41:05.491374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 04:41:05.491429 ==
8148 04:41:05.491497
8149 04:41:05.491565
8150 04:41:05.491627 TX Vref Scan disable
8151 04:41:05.491701 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8152 04:41:05.491799 == TX Byte 0 ==
8153 04:41:05.491853 u2DelayCellOfst[0]=14 cells (4 PI)
8154 04:41:05.491906 u2DelayCellOfst[1]=21 cells (6 PI)
8155 04:41:05.491957 u2DelayCellOfst[2]=10 cells (3 PI)
8156 04:41:05.492008 u2DelayCellOfst[3]=14 cells (4 PI)
8157 04:41:05.492090 u2DelayCellOfst[4]=10 cells (3 PI)
8158 04:41:05.492144 u2DelayCellOfst[5]=0 cells (0 PI)
8159 04:41:05.492197 u2DelayCellOfst[6]=21 cells (6 PI)
8160 04:41:05.492247 u2DelayCellOfst[7]=21 cells (6 PI)
8161 04:41:05.492315 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8162 04:41:05.492383 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8163 04:41:05.492441 == TX Byte 1 ==
8164 04:41:05.492509 u2DelayCellOfst[8]=0 cells (0 PI)
8165 04:41:05.492565 u2DelayCellOfst[9]=0 cells (0 PI)
8166 04:41:05.492618 u2DelayCellOfst[10]=7 cells (2 PI)
8167 04:41:05.492680 u2DelayCellOfst[11]=0 cells (0 PI)
8168 04:41:05.492751 u2DelayCellOfst[12]=10 cells (3 PI)
8169 04:41:05.492834 u2DelayCellOfst[13]=10 cells (3 PI)
8170 04:41:05.492887 u2DelayCellOfst[14]=14 cells (4 PI)
8171 04:41:05.492939 u2DelayCellOfst[15]=10 cells (3 PI)
8172 04:41:05.492990 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8173 04:41:05.493059 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8174 04:41:05.493127 DramC Write-DBI on
8175 04:41:05.493179 ==
8176 04:41:05.493235 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 04:41:05.493306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 04:41:05.493373 ==
8179 04:41:05.493427
8180 04:41:05.493480
8181 04:41:05.493547 TX Vref Scan disable
8182 04:41:05.493615 == TX Byte 0 ==
8183 04:41:05.493666 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8184 04:41:05.493718 == TX Byte 1 ==
8185 04:41:05.493788 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8186 04:41:05.493857 DramC Write-DBI off
8187 04:41:05.493909
8188 04:41:05.493965 [DATLAT]
8189 04:41:05.494044 Freq=1600, CH0 RK1
8190 04:41:05.494115
8191 04:41:05.494168 DATLAT Default: 0xf
8192 04:41:05.494219 0, 0xFFFF, sum = 0
8193 04:41:05.494272 1, 0xFFFF, sum = 0
8194 04:41:05.494328 2, 0xFFFF, sum = 0
8195 04:41:05.494398 3, 0xFFFF, sum = 0
8196 04:41:05.494470 4, 0xFFFF, sum = 0
8197 04:41:05.494522 5, 0xFFFF, sum = 0
8198 04:41:05.494577 6, 0xFFFF, sum = 0
8199 04:41:05.494648 7, 0xFFFF, sum = 0
8200 04:41:05.494718 8, 0xFFFF, sum = 0
8201 04:41:05.494773 9, 0xFFFF, sum = 0
8202 04:41:05.494827 10, 0xFFFF, sum = 0
8203 04:41:05.494896 11, 0xFFFF, sum = 0
8204 04:41:05.494964 12, 0xFFFF, sum = 0
8205 04:41:05.495018 13, 0xFFFF, sum = 0
8206 04:41:05.495070 14, 0x0, sum = 1
8207 04:41:05.495139 15, 0x0, sum = 2
8208 04:41:05.495210 16, 0x0, sum = 3
8209 04:41:05.495262 17, 0x0, sum = 4
8210 04:41:05.495337 best_step = 15
8211 04:41:05.495412
8212 04:41:05.495466 ==
8213 04:41:05.495522 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 04:41:05.495777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 04:41:05.495913 ==
8216 04:41:05.496039 RX Vref Scan: 0
8217 04:41:05.496156
8218 04:41:05.496247 RX Vref 0 -> 0, step: 1
8219 04:41:05.496334
8220 04:41:05.496435 RX Delay 11 -> 252, step: 4
8221 04:41:05.496519 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8222 04:41:05.496603 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8223 04:41:05.496710 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8224 04:41:05.496842 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8225 04:41:05.496923 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8226 04:41:05.497009 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8227 04:41:05.497090 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8228 04:41:05.497178 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8229 04:41:05.497259 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8230 04:41:05.497340 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8231 04:41:05.497443 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8232 04:41:05.497572 iDelay=191, Bit 11, Center 114 (63 ~ 166) 104
8233 04:41:05.497657 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8234 04:41:05.497741 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8235 04:41:05.497827 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8236 04:41:05.497927 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8237 04:41:05.498032 ==
8238 04:41:05.498115 Dram Type= 6, Freq= 0, CH_0, rank 1
8239 04:41:05.498201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 04:41:05.498287 ==
8241 04:41:05.498384 DQS Delay:
8242 04:41:05.498484 DQS0 = 0, DQS1 = 0
8243 04:41:05.498601 DQM Delay:
8244 04:41:05.498685 DQM0 = 126, DQM1 = 122
8245 04:41:05.498767 DQ Delay:
8246 04:41:05.498848 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8247 04:41:05.498948 DQ4 =124, DQ5 =116, DQ6 =134, DQ7 =136
8248 04:41:05.499017 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =114
8249 04:41:05.499069 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8250 04:41:05.499153
8251 04:41:05.499206
8252 04:41:05.499293
8253 04:41:05.499348 [DramC_TX_OE_Calibration] TA2
8254 04:41:05.499401 Original DQ_B0 (3 6) =30, OEN = 27
8255 04:41:05.499457 Original DQ_B1 (3 6) =30, OEN = 27
8256 04:41:05.499508 24, 0x0, End_B0=24 End_B1=24
8257 04:41:05.499560 25, 0x0, End_B0=25 End_B1=25
8258 04:41:05.499612 26, 0x0, End_B0=26 End_B1=26
8259 04:41:05.499667 27, 0x0, End_B0=27 End_B1=27
8260 04:41:05.499741 28, 0x0, End_B0=28 End_B1=28
8261 04:41:05.499809 29, 0x0, End_B0=29 End_B1=29
8262 04:41:05.499865 30, 0x0, End_B0=30 End_B1=30
8263 04:41:05.499949 31, 0x5151, End_B0=30 End_B1=30
8264 04:41:05.500050 Byte0 end_step=30 best_step=27
8265 04:41:05.500106 Byte1 end_step=30 best_step=27
8266 04:41:05.500159 Byte0 TX OE(2T, 0.5T) = (3, 3)
8267 04:41:05.500212 Byte1 TX OE(2T, 0.5T) = (3, 3)
8268 04:41:05.500269
8269 04:41:05.500338
8270 04:41:05.500391 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8271 04:41:05.500443 CH0 RK1: MR19=303, MR18=180D
8272 04:41:05.500494 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8273 04:41:05.500549 [RxdqsGatingPostProcess] freq 1600
8274 04:41:05.500602 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8275 04:41:05.500653 best DQS0 dly(2T, 0.5T) = (1, 1)
8276 04:41:05.500751 best DQS1 dly(2T, 0.5T) = (1, 1)
8277 04:41:05.500807 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8278 04:41:05.500859 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8279 04:41:05.500910 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 04:41:05.500961 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 04:41:05.501017 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 04:41:05.501069 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 04:41:05.501126 Pre-setting of DQS Precalculation
8284 04:41:05.501178 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8285 04:41:05.501229 ==
8286 04:41:05.501280 Dram Type= 6, Freq= 0, CH_1, rank 0
8287 04:41:05.501334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 04:41:05.501387 ==
8289 04:41:05.501442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8290 04:41:05.501496 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8291 04:41:05.501547 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8292 04:41:05.501602 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8293 04:41:05.501654 [CA 0] Center 43 (15~72) winsize 58
8294 04:41:05.501705 [CA 1] Center 43 (14~72) winsize 59
8295 04:41:05.501756 [CA 2] Center 38 (9~67) winsize 59
8296 04:41:05.501811 [CA 3] Center 37 (9~66) winsize 58
8297 04:41:05.501864 [CA 4] Center 38 (9~68) winsize 60
8298 04:41:05.501915 [CA 5] Center 37 (8~66) winsize 59
8299 04:41:05.501971
8300 04:41:05.502076 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8301 04:41:05.502148
8302 04:41:05.502199 [CATrainingPosCal] consider 1 rank data
8303 04:41:05.502250 u2DelayCellTimex100 = 275/100 ps
8304 04:41:05.502304 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8305 04:41:05.502358 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8306 04:41:05.502413 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8307 04:41:05.502468 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8308 04:41:05.502520 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8309 04:41:05.502573 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8310 04:41:05.502625
8311 04:41:05.502674 CA PerBit enable=1, Macro0, CA PI delay=37
8312 04:41:05.502725
8313 04:41:05.502775 [CBTSetCACLKResult] CA Dly = 37
8314 04:41:05.502829 CS Dly: 8 (0~39)
8315 04:41:05.502881 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8316 04:41:05.502966 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8317 04:41:05.503069 ==
8318 04:41:05.503122 Dram Type= 6, Freq= 0, CH_1, rank 1
8319 04:41:05.503173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 04:41:05.503224 ==
8321 04:41:05.503274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8322 04:41:05.503328 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8323 04:41:05.503381 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8324 04:41:05.503436 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8325 04:41:05.503489 [CA 0] Center 42 (13~72) winsize 60
8326 04:41:05.503542 [CA 1] Center 43 (14~72) winsize 59
8327 04:41:05.503593 [CA 2] Center 37 (8~67) winsize 60
8328 04:41:05.503647 [CA 3] Center 37 (9~66) winsize 58
8329 04:41:05.503700 [CA 4] Center 38 (9~67) winsize 59
8330 04:41:05.503750 [CA 5] Center 36 (7~66) winsize 60
8331 04:41:05.503809
8332 04:41:05.503893 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8333 04:41:05.503963
8334 04:41:05.504226 [CATrainingPosCal] consider 2 rank data
8335 04:41:05.504289 u2DelayCellTimex100 = 275/100 ps
8336 04:41:05.504345 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8337 04:41:05.504400 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8338 04:41:05.504454 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8339 04:41:05.504506 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8340 04:41:05.504577 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8341 04:41:05.504633 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8342 04:41:05.504708
8343 04:41:05.504764 CA PerBit enable=1, Macro0, CA PI delay=37
8344 04:41:05.504819
8345 04:41:05.504871 [CBTSetCACLKResult] CA Dly = 37
8346 04:41:05.504922 CS Dly: 10 (0~44)
8347 04:41:05.504972 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8348 04:41:05.505026 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8349 04:41:05.505077
8350 04:41:05.505130 ----->DramcWriteLeveling(PI) begin...
8351 04:41:05.505181 ==
8352 04:41:05.505232 Dram Type= 6, Freq= 0, CH_1, rank 0
8353 04:41:05.505300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 04:41:05.505370 ==
8355 04:41:05.505422 Write leveling (Byte 0): 26 => 26
8356 04:41:05.505476 Write leveling (Byte 1): 29 => 29
8357 04:41:05.505528 DramcWriteLeveling(PI) end<-----
8358 04:41:05.505582
8359 04:41:05.505634 ==
8360 04:41:05.505685 Dram Type= 6, Freq= 0, CH_1, rank 0
8361 04:41:05.505735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8362 04:41:05.505790 ==
8363 04:41:05.505842 [Gating] SW mode calibration
8364 04:41:05.505896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8365 04:41:05.505957 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8366 04:41:05.506066 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 04:41:05.506212 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 04:41:05.506285 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 04:41:05.506337 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 04:41:05.506391 1 4 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8371 04:41:05.506445 1 4 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8372 04:41:05.506499 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 04:41:05.506552 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 04:41:05.506606 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 04:41:05.506658 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 04:41:05.506710 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 04:41:05.506761 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8378 04:41:05.506815 1 5 16 | B1->B0 | 3232 3434 | 0 0 | (0 1) (0 1)
8379 04:41:05.506866 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 04:41:05.506920 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 04:41:05.506972 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 04:41:05.507024 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 04:41:05.507078 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 04:41:05.507130 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 04:41:05.507181 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 04:41:05.507247 1 6 16 | B1->B0 | 3333 2929 | 1 0 | (0 0) (1 1)
8387 04:41:05.507315 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 04:41:05.507370 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 04:41:05.507421 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 04:41:05.507471 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 04:41:05.507522 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 04:41:05.507575 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 04:41:05.507636 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8394 04:41:05.507720 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8395 04:41:05.507836 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8396 04:41:05.507890 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8397 04:41:05.507943 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 04:41:05.507994 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 04:41:05.508107 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 04:41:05.508164 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 04:41:05.508216 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 04:41:05.508270 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 04:41:05.508324 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 04:41:05.508377 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 04:41:05.508432 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 04:41:05.508484 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 04:41:05.508537 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 04:41:05.508589 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 04:41:05.508641 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8410 04:41:05.508733 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8411 04:41:05.508789 Total UI for P1: 0, mck2ui 16
8412 04:41:05.508843 best dqsien dly found for B1: ( 1, 9, 12)
8413 04:41:05.508898 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 04:41:05.508948 Total UI for P1: 0, mck2ui 16
8415 04:41:05.509003 best dqsien dly found for B0: ( 1, 9, 14)
8416 04:41:05.509056 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8417 04:41:05.509155 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8418 04:41:05.509209
8419 04:41:05.509260 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8420 04:41:05.509310 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8421 04:41:05.509378 [Gating] SW calibration Done
8422 04:41:05.509477 ==
8423 04:41:05.509530 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 04:41:05.509581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 04:41:05.509634 ==
8426 04:41:05.509687 RX Vref Scan: 0
8427 04:41:05.509741
8428 04:41:05.509792 RX Vref 0 -> 0, step: 1
8429 04:41:05.509843
8430 04:41:05.509893 RX Delay 0 -> 252, step: 8
8431 04:41:05.509943 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8432 04:41:05.510003 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8433 04:41:05.510054 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8434 04:41:05.510105 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8435 04:41:05.510344 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8436 04:41:05.510442 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8437 04:41:05.510552 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8438 04:41:05.510656 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8439 04:41:05.510765 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8440 04:41:05.510871 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8441 04:41:05.511014 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8442 04:41:05.511124 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8443 04:41:05.511231 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8444 04:41:05.511341 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8445 04:41:05.511435 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8446 04:41:05.511516 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8447 04:41:05.511597 ==
8448 04:41:05.511686 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 04:41:05.511748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 04:41:05.511807 ==
8451 04:41:05.511861 DQS Delay:
8452 04:41:05.511944 DQS0 = 0, DQS1 = 0
8453 04:41:05.512021 DQM Delay:
8454 04:41:05.512094 DQM0 = 134, DQM1 = 126
8455 04:41:05.512179 DQ Delay:
8456 04:41:05.512232 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8457 04:41:05.512286 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8458 04:41:05.512339 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8459 04:41:05.512440 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
8460 04:41:05.512495
8461 04:41:05.512546
8462 04:41:05.512597 ==
8463 04:41:05.512672 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 04:41:05.512742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 04:41:05.512797 ==
8466 04:41:05.512851
8467 04:41:05.512904
8468 04:41:05.512958 TX Vref Scan disable
8469 04:41:05.513008 == TX Byte 0 ==
8470 04:41:05.513058 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8471 04:41:05.513110 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8472 04:41:05.513161 == TX Byte 1 ==
8473 04:41:05.513215 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8474 04:41:05.513268 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8475 04:41:05.513322 ==
8476 04:41:05.513375 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 04:41:05.513429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 04:41:05.513483 ==
8479 04:41:05.513536
8480 04:41:05.513586 TX Vref early break, caculate TX vref
8481 04:41:05.513642 TX Vref=16, minBit 13, minWin=20, winSum=355
8482 04:41:05.513695 TX Vref=18, minBit 5, minWin=21, winSum=366
8483 04:41:05.513749 TX Vref=20, minBit 8, minWin=22, winSum=376
8484 04:41:05.513802 TX Vref=22, minBit 8, minWin=22, winSum=385
8485 04:41:05.513853 TX Vref=24, minBit 5, minWin=24, winSum=402
8486 04:41:05.513904 TX Vref=26, minBit 5, minWin=24, winSum=407
8487 04:41:05.513963 TX Vref=28, minBit 8, minWin=24, winSum=415
8488 04:41:05.514046 TX Vref=30, minBit 8, minWin=24, winSum=415
8489 04:41:05.514101 TX Vref=32, minBit 0, minWin=25, winSum=410
8490 04:41:05.514153 TX Vref=34, minBit 11, minWin=23, winSum=398
8491 04:41:05.514207 TX Vref=36, minBit 3, minWin=23, winSum=385
8492 04:41:05.514261 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 32
8493 04:41:05.514315
8494 04:41:05.514368 Final TX Range 0 Vref 32
8495 04:41:05.514422
8496 04:41:05.514475 ==
8497 04:41:05.514527 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 04:41:05.514578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 04:41:05.514629 ==
8500 04:41:05.514682
8501 04:41:05.514734
8502 04:41:05.514788 TX Vref Scan disable
8503 04:41:05.514839 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8504 04:41:05.514890 == TX Byte 0 ==
8505 04:41:05.514943 u2DelayCellOfst[0]=17 cells (5 PI)
8506 04:41:05.514994 u2DelayCellOfst[1]=14 cells (4 PI)
8507 04:41:05.515044 u2DelayCellOfst[2]=0 cells (0 PI)
8508 04:41:05.515094 u2DelayCellOfst[3]=7 cells (2 PI)
8509 04:41:05.515144 u2DelayCellOfst[4]=10 cells (3 PI)
8510 04:41:05.515194 u2DelayCellOfst[5]=17 cells (5 PI)
8511 04:41:05.515248 u2DelayCellOfst[6]=17 cells (5 PI)
8512 04:41:05.515300 u2DelayCellOfst[7]=7 cells (2 PI)
8513 04:41:05.515351 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8514 04:41:05.515402 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8515 04:41:05.515456 == TX Byte 1 ==
8516 04:41:05.515506 u2DelayCellOfst[8]=0 cells (0 PI)
8517 04:41:05.515565 u2DelayCellOfst[9]=7 cells (2 PI)
8518 04:41:05.515619 u2DelayCellOfst[10]=10 cells (3 PI)
8519 04:41:05.515670 u2DelayCellOfst[11]=7 cells (2 PI)
8520 04:41:05.515724 u2DelayCellOfst[12]=14 cells (4 PI)
8521 04:41:05.515778 u2DelayCellOfst[13]=17 cells (5 PI)
8522 04:41:05.515828 u2DelayCellOfst[14]=17 cells (5 PI)
8523 04:41:05.515879 u2DelayCellOfst[15]=17 cells (5 PI)
8524 04:41:05.515929 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8525 04:41:05.515997 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8526 04:41:05.516057 DramC Write-DBI on
8527 04:41:05.516115 ==
8528 04:41:05.516206 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 04:41:05.516260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 04:41:05.516314 ==
8531 04:41:05.516368
8532 04:41:05.516421
8533 04:41:05.516474 TX Vref Scan disable
8534 04:41:05.516527 == TX Byte 0 ==
8535 04:41:05.516580 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8536 04:41:05.516630 == TX Byte 1 ==
8537 04:41:05.516710 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8538 04:41:05.516779 DramC Write-DBI off
8539 04:41:05.516833
8540 04:41:05.516885 [DATLAT]
8541 04:41:05.516939 Freq=1600, CH1 RK0
8542 04:41:05.516992
8543 04:41:05.517042 DATLAT Default: 0xf
8544 04:41:05.517095 0, 0xFFFF, sum = 0
8545 04:41:05.517147 1, 0xFFFF, sum = 0
8546 04:41:05.517202 2, 0xFFFF, sum = 0
8547 04:41:05.517255 3, 0xFFFF, sum = 0
8548 04:41:05.517317 4, 0xFFFF, sum = 0
8549 04:41:05.517380 5, 0xFFFF, sum = 0
8550 04:41:05.517441 6, 0xFFFF, sum = 0
8551 04:41:05.517507 7, 0xFFFF, sum = 0
8552 04:41:05.517569 8, 0xFFFF, sum = 0
8553 04:41:05.517634 9, 0xFFFF, sum = 0
8554 04:41:05.517700 10, 0xFFFF, sum = 0
8555 04:41:05.517761 11, 0xFFFF, sum = 0
8556 04:41:05.517824 12, 0xFFFF, sum = 0
8557 04:41:05.517878 13, 0xFFFF, sum = 0
8558 04:41:05.517939 14, 0x0, sum = 1
8559 04:41:05.518011 15, 0x0, sum = 2
8560 04:41:05.518077 16, 0x0, sum = 3
8561 04:41:05.518142 17, 0x0, sum = 4
8562 04:41:05.518203 best_step = 15
8563 04:41:05.518264
8564 04:41:05.518318 ==
8565 04:41:05.518379 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 04:41:05.518444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 04:41:05.518499 ==
8568 04:41:05.518558 RX Vref Scan: 1
8569 04:41:05.518619
8570 04:41:05.518677 Set Vref Range= 24 -> 127
8571 04:41:05.518738
8572 04:41:05.518798 RX Vref 24 -> 127, step: 1
8573 04:41:05.518858
8574 04:41:05.518917 RX Delay 11 -> 252, step: 4
8575 04:41:05.518984
8576 04:41:05.519051 Set Vref, RX VrefLevel [Byte0]: 24
8577 04:41:05.519114 [Byte1]: 24
8578 04:41:05.519180
8579 04:41:05.519239 Set Vref, RX VrefLevel [Byte0]: 25
8580 04:41:05.519299 [Byte1]: 25
8581 04:41:05.519361
8582 04:41:05.519417 Set Vref, RX VrefLevel [Byte0]: 26
8583 04:41:05.519470 [Byte1]: 26
8584 04:41:05.519523
8585 04:41:05.519774 Set Vref, RX VrefLevel [Byte0]: 27
8586 04:41:05.519846 [Byte1]: 27
8587 04:41:05.519915
8588 04:41:05.519986 Set Vref, RX VrefLevel [Byte0]: 28
8589 04:41:05.520116 [Byte1]: 28
8590 04:41:05.520206
8591 04:41:05.520269 Set Vref, RX VrefLevel [Byte0]: 29
8592 04:41:05.520333 [Byte1]: 29
8593 04:41:05.520393
8594 04:41:05.520444 Set Vref, RX VrefLevel [Byte0]: 30
8595 04:41:05.520498 [Byte1]: 30
8596 04:41:05.520575
8597 04:41:05.520631 Set Vref, RX VrefLevel [Byte0]: 31
8598 04:41:05.520707 [Byte1]: 31
8599 04:41:05.520760
8600 04:41:05.520810 Set Vref, RX VrefLevel [Byte0]: 32
8601 04:41:05.520864 [Byte1]: 32
8602 04:41:05.520917
8603 04:41:05.520979 Set Vref, RX VrefLevel [Byte0]: 33
8604 04:41:05.521038 [Byte1]: 33
8605 04:41:05.521098
8606 04:41:05.521157 Set Vref, RX VrefLevel [Byte0]: 34
8607 04:41:05.521218 [Byte1]: 34
8608 04:41:05.521276
8609 04:41:05.521339 Set Vref, RX VrefLevel [Byte0]: 35
8610 04:41:05.521398 [Byte1]: 35
8611 04:41:05.521458
8612 04:41:05.521516 Set Vref, RX VrefLevel [Byte0]: 36
8613 04:41:05.521579 [Byte1]: 36
8614 04:41:05.521637
8615 04:41:05.521696 Set Vref, RX VrefLevel [Byte0]: 37
8616 04:41:05.521758 [Byte1]: 37
8617 04:41:05.521827
8618 04:41:05.521888 Set Vref, RX VrefLevel [Byte0]: 38
8619 04:41:05.521947 [Byte1]: 38
8620 04:41:05.522037
8621 04:41:05.522133 Set Vref, RX VrefLevel [Byte0]: 39
8622 04:41:05.522227 [Byte1]: 39
8623 04:41:05.522323
8624 04:41:05.522406 Set Vref, RX VrefLevel [Byte0]: 40
8625 04:41:05.522473 [Byte1]: 40
8626 04:41:05.522525
8627 04:41:05.522579 Set Vref, RX VrefLevel [Byte0]: 41
8628 04:41:05.522630 [Byte1]: 41
8629 04:41:05.522707
8630 04:41:05.522773 Set Vref, RX VrefLevel [Byte0]: 42
8631 04:41:05.522828 [Byte1]: 42
8632 04:41:05.522881
8633 04:41:05.522931 Set Vref, RX VrefLevel [Byte0]: 43
8634 04:41:05.522982 [Byte1]: 43
8635 04:41:05.523035
8636 04:41:05.523086 Set Vref, RX VrefLevel [Byte0]: 44
8637 04:41:05.523135 [Byte1]: 44
8638 04:41:05.523185
8639 04:41:05.523235 Set Vref, RX VrefLevel [Byte0]: 45
8640 04:41:05.523289 [Byte1]: 45
8641 04:41:05.523342
8642 04:41:05.523391 Set Vref, RX VrefLevel [Byte0]: 46
8643 04:41:05.523442 [Byte1]: 46
8644 04:41:05.523492
8645 04:41:05.523546 Set Vref, RX VrefLevel [Byte0]: 47
8646 04:41:05.523596 [Byte1]: 47
8647 04:41:05.523647
8648 04:41:05.523696 Set Vref, RX VrefLevel [Byte0]: 48
8649 04:41:05.523747 [Byte1]: 48
8650 04:41:05.523799
8651 04:41:05.523852 Set Vref, RX VrefLevel [Byte0]: 49
8652 04:41:05.523906 [Byte1]: 49
8653 04:41:05.523962
8654 04:41:05.524122 Set Vref, RX VrefLevel [Byte0]: 50
8655 04:41:05.524212 [Byte1]: 50
8656 04:41:05.524272
8657 04:41:05.524325 Set Vref, RX VrefLevel [Byte0]: 51
8658 04:41:05.524381 [Byte1]: 51
8659 04:41:05.524434
8660 04:41:05.524485 Set Vref, RX VrefLevel [Byte0]: 52
8661 04:41:05.524538 [Byte1]: 52
8662 04:41:05.524638
8663 04:41:05.524729 Set Vref, RX VrefLevel [Byte0]: 53
8664 04:41:05.524785 [Byte1]: 53
8665 04:41:05.524838
8666 04:41:05.524889 Set Vref, RX VrefLevel [Byte0]: 54
8667 04:41:05.524940 [Byte1]: 54
8668 04:41:05.524991
8669 04:41:05.525044 Set Vref, RX VrefLevel [Byte0]: 55
8670 04:41:05.525094 [Byte1]: 55
8671 04:41:05.525148
8672 04:41:05.525200 Set Vref, RX VrefLevel [Byte0]: 56
8673 04:41:05.525250 [Byte1]: 56
8674 04:41:05.525303
8675 04:41:05.525356 Set Vref, RX VrefLevel [Byte0]: 57
8676 04:41:05.525409 [Byte1]: 57
8677 04:41:05.525459
8678 04:41:05.525509 Set Vref, RX VrefLevel [Byte0]: 58
8679 04:41:05.525563 [Byte1]: 58
8680 04:41:05.525616
8681 04:41:05.525668 Set Vref, RX VrefLevel [Byte0]: 59
8682 04:41:05.525719 [Byte1]: 59
8683 04:41:05.525772
8684 04:41:05.525823 Set Vref, RX VrefLevel [Byte0]: 60
8685 04:41:05.525875 [Byte1]: 60
8686 04:41:05.525926
8687 04:41:05.525977 Set Vref, RX VrefLevel [Byte0]: 61
8688 04:41:05.526030 [Byte1]: 61
8689 04:41:05.526089
8690 04:41:05.526141 Set Vref, RX VrefLevel [Byte0]: 62
8691 04:41:05.526193 [Byte1]: 62
8692 04:41:05.526243
8693 04:41:05.526297 Set Vref, RX VrefLevel [Byte0]: 63
8694 04:41:05.526376 [Byte1]: 63
8695 04:41:05.526456
8696 04:41:05.526539 Set Vref, RX VrefLevel [Byte0]: 64
8697 04:41:05.526635 [Byte1]: 64
8698 04:41:05.526720
8699 04:41:05.526804 Set Vref, RX VrefLevel [Byte0]: 65
8700 04:41:05.526888 [Byte1]: 65
8701 04:41:05.526967
8702 04:41:05.527024 Set Vref, RX VrefLevel [Byte0]: 66
8703 04:41:05.527077 [Byte1]: 66
8704 04:41:05.527127
8705 04:41:05.527178 Set Vref, RX VrefLevel [Byte0]: 67
8706 04:41:05.527233 [Byte1]: 67
8707 04:41:05.527286
8708 04:41:05.527340 Set Vref, RX VrefLevel [Byte0]: 68
8709 04:41:05.527395 [Byte1]: 68
8710 04:41:05.527447
8711 04:41:05.527498 Set Vref, RX VrefLevel [Byte0]: 69
8712 04:41:05.527548 [Byte1]: 69
8713 04:41:05.527603
8714 04:41:05.527656 Set Vref, RX VrefLevel [Byte0]: 70
8715 04:41:05.527707 [Byte1]: 70
8716 04:41:05.527758
8717 04:41:05.527811 Set Vref, RX VrefLevel [Byte0]: 71
8718 04:41:05.527863 [Byte1]: 71
8719 04:41:05.527915
8720 04:41:05.527971 Set Vref, RX VrefLevel [Byte0]: 72
8721 04:41:05.528022 [Byte1]: 72
8722 04:41:05.528079
8723 04:41:05.528142 Final RX Vref Byte 0 = 62 to rank0
8724 04:41:05.528244 Final RX Vref Byte 1 = 60 to rank0
8725 04:41:05.528365 Final RX Vref Byte 0 = 62 to rank1
8726 04:41:05.528453 Final RX Vref Byte 1 = 60 to rank1==
8727 04:41:05.528536 Dram Type= 6, Freq= 0, CH_1, rank 0
8728 04:41:05.528622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 04:41:05.528730 ==
8730 04:41:05.528784 DQS Delay:
8731 04:41:05.528839 DQS0 = 0, DQS1 = 0
8732 04:41:05.528892 DQM Delay:
8733 04:41:05.528947 DQM0 = 131, DQM1 = 124
8734 04:41:05.529000 DQ Delay:
8735 04:41:05.529051 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8736 04:41:05.529104 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8737 04:41:05.529159 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8738 04:41:05.529209 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8739 04:41:05.529260
8740 04:41:05.529313
8741 04:41:05.529367
8742 04:41:05.529420 [DramC_TX_OE_Calibration] TA2
8743 04:41:05.529489 Original DQ_B0 (3 6) =30, OEN = 27
8744 04:41:05.529547 Original DQ_B1 (3 6) =30, OEN = 27
8745 04:41:05.529791 24, 0x0, End_B0=24 End_B1=24
8746 04:41:05.529904 25, 0x0, End_B0=25 End_B1=25
8747 04:41:05.530012 26, 0x0, End_B0=26 End_B1=26
8748 04:41:05.530122 27, 0x0, End_B0=27 End_B1=27
8749 04:41:05.530233 28, 0x0, End_B0=28 End_B1=28
8750 04:41:05.530352 29, 0x0, End_B0=29 End_B1=29
8751 04:41:05.530479 30, 0x0, End_B0=30 End_B1=30
8752 04:41:05.530585 31, 0x4141, End_B0=30 End_B1=30
8753 04:41:05.530674 Byte0 end_step=30 best_step=27
8754 04:41:05.530758 Byte1 end_step=30 best_step=27
8755 04:41:05.530841 Byte0 TX OE(2T, 0.5T) = (3, 3)
8756 04:41:05.530922 Byte1 TX OE(2T, 0.5T) = (3, 3)
8757 04:41:05.531002
8758 04:41:05.531085
8759 04:41:05.531167 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8760 04:41:05.531253 CH1 RK0: MR19=302, MR18=13FE
8761 04:41:05.531338 CH1_RK0: MR19=0x302, MR18=0x13FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8762 04:41:05.531417
8763 04:41:05.531498 ----->DramcWriteLeveling(PI) begin...
8764 04:41:05.531582 ==
8765 04:41:05.531667 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 04:41:05.531750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 04:41:05.531834 ==
8768 04:41:05.531914 Write leveling (Byte 0): 25 => 25
8769 04:41:05.531995 Write leveling (Byte 1): 28 => 28
8770 04:41:05.532079 DramcWriteLeveling(PI) end<-----
8771 04:41:05.532161
8772 04:41:05.532240 ==
8773 04:41:05.532326 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 04:41:05.532407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 04:41:05.532492 ==
8776 04:41:05.532575 [Gating] SW mode calibration
8777 04:41:05.532662 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8778 04:41:05.532764 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8779 04:41:05.532817 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 04:41:05.532869 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 04:41:05.532929 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8782 04:41:05.532981 1 4 12 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
8783 04:41:05.533036 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 04:41:05.533088 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 04:41:05.533140 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 04:41:05.533191 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 04:41:05.533241 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 04:41:05.533295 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8789 04:41:05.533345 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8790 04:41:05.533395 1 5 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
8791 04:41:05.533446 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 04:41:05.533501 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 04:41:05.533554 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 04:41:05.533608 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 04:41:05.533661 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 04:41:05.533715 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 04:41:05.533766 1 6 8 | B1->B0 | 2424 3838 | 0 1 | (0 0) (0 0)
8798 04:41:05.533816 1 6 12 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
8799 04:41:05.533870 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 04:41:05.533923 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 04:41:05.533977 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 04:41:05.534029 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 04:41:05.534079 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 04:41:05.534130 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 04:41:05.534184 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8806 04:41:05.534234 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8807 04:41:05.534288 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8808 04:41:05.534341 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 04:41:05.534394 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 04:41:05.534444 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 04:41:05.534497 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 04:41:05.534548 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 04:41:05.534602 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 04:41:05.534655 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 04:41:05.534710 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 04:41:05.534761 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 04:41:05.534811 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 04:41:05.534861 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 04:41:05.534915 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 04:41:05.534972 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 04:41:05.535032 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8822 04:41:05.535083 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 04:41:05.535134 Total UI for P1: 0, mck2ui 16
8824 04:41:05.535189 best dqsien dly found for B0: ( 1, 9, 8)
8825 04:41:05.535241 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8826 04:41:05.535291 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 04:41:05.535345 Total UI for P1: 0, mck2ui 16
8828 04:41:05.535398 best dqsien dly found for B1: ( 1, 9, 14)
8829 04:41:05.535452 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8830 04:41:05.535506 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8831 04:41:05.535557
8832 04:41:05.535607 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8833 04:41:05.535662 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8834 04:41:05.535716 [Gating] SW calibration Done
8835 04:41:05.535768 ==
8836 04:41:05.535819 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 04:41:05.535869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 04:41:05.535924 ==
8839 04:41:05.535976 RX Vref Scan: 0
8840 04:41:05.536027
8841 04:41:05.536142 RX Vref 0 -> 0, step: 1
8842 04:41:05.536225
8843 04:41:05.536305 RX Delay 0 -> 252, step: 8
8844 04:41:05.536395 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8845 04:41:05.536479 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8846 04:41:05.536562 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8847 04:41:05.536829 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8848 04:41:05.536893 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8849 04:41:05.536953 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8850 04:41:05.537021 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8851 04:41:05.537074 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8852 04:41:05.537127 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8853 04:41:05.537181 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8854 04:41:05.537232 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8855 04:41:05.537282 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8856 04:41:05.537332 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8857 04:41:05.537387 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8858 04:41:05.537439 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8859 04:41:05.537494 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8860 04:41:05.537546 ==
8861 04:41:05.537597 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 04:41:05.537650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 04:41:05.537702 ==
8864 04:41:05.537755 DQS Delay:
8865 04:41:05.537806 DQS0 = 0, DQS1 = 0
8866 04:41:05.537859 DQM Delay:
8867 04:41:05.537912 DQM0 = 132, DQM1 = 130
8868 04:41:05.537965 DQ Delay:
8869 04:41:05.538015 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8870 04:41:05.538066 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8871 04:41:05.538117 DQ8 =115, DQ9 =115, DQ10 =135, DQ11 =119
8872 04:41:05.538171 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8873 04:41:05.538221
8874 04:41:05.538272
8875 04:41:05.538322 ==
8876 04:41:05.538372 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 04:41:05.538426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 04:41:05.538479 ==
8879 04:41:05.538533
8880 04:41:05.538585
8881 04:41:05.538635 TX Vref Scan disable
8882 04:41:05.538689 == TX Byte 0 ==
8883 04:41:05.538739 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8884 04:41:05.538790 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8885 04:41:05.538841 == TX Byte 1 ==
8886 04:41:05.538895 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8887 04:41:05.538948 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8888 04:41:05.539010 ==
8889 04:41:05.539070 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 04:41:05.539122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 04:41:05.539177 ==
8892 04:41:05.539228
8893 04:41:05.539279 TX Vref early break, caculate TX vref
8894 04:41:05.539333 TX Vref=16, minBit 8, minWin=21, winSum=377
8895 04:41:05.539389 TX Vref=18, minBit 8, minWin=22, winSum=381
8896 04:41:05.539445 TX Vref=20, minBit 8, minWin=23, winSum=394
8897 04:41:05.539498 TX Vref=22, minBit 5, minWin=24, winSum=403
8898 04:41:05.539548 TX Vref=24, minBit 0, minWin=25, winSum=409
8899 04:41:05.539599 TX Vref=26, minBit 11, minWin=25, winSum=418
8900 04:41:05.539652 TX Vref=28, minBit 9, minWin=25, winSum=421
8901 04:41:05.539703 TX Vref=30, minBit 0, minWin=25, winSum=419
8902 04:41:05.539754 TX Vref=32, minBit 0, minWin=24, winSum=414
8903 04:41:05.539805 TX Vref=34, minBit 0, minWin=24, winSum=402
8904 04:41:05.539856 TX Vref=36, minBit 5, minWin=24, winSum=398
8905 04:41:05.539911 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
8906 04:41:05.539964
8907 04:41:05.540014 Final TX Range 0 Vref 28
8908 04:41:05.540065
8909 04:41:05.540114 ==
8910 04:41:05.540168 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 04:41:05.540219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 04:41:05.540270 ==
8913 04:41:05.540320
8914 04:41:05.540370
8915 04:41:05.540423 TX Vref Scan disable
8916 04:41:05.540476 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8917 04:41:05.540527 == TX Byte 0 ==
8918 04:41:05.540577 u2DelayCellOfst[0]=17 cells (5 PI)
8919 04:41:05.540628 u2DelayCellOfst[1]=10 cells (3 PI)
8920 04:41:05.540728 u2DelayCellOfst[2]=0 cells (0 PI)
8921 04:41:05.540816 u2DelayCellOfst[3]=7 cells (2 PI)
8922 04:41:05.540899 u2DelayCellOfst[4]=10 cells (3 PI)
8923 04:41:05.541000 u2DelayCellOfst[5]=17 cells (5 PI)
8924 04:41:05.541054 u2DelayCellOfst[6]=17 cells (5 PI)
8925 04:41:05.541106 u2DelayCellOfst[7]=7 cells (2 PI)
8926 04:41:05.541160 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8927 04:41:05.541215 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8928 04:41:05.541268 == TX Byte 1 ==
8929 04:41:05.541318 u2DelayCellOfst[8]=0 cells (0 PI)
8930 04:41:05.541371 u2DelayCellOfst[9]=3 cells (1 PI)
8931 04:41:05.541421 u2DelayCellOfst[10]=10 cells (3 PI)
8932 04:41:05.753686 u2DelayCellOfst[11]=7 cells (2 PI)
8933 04:41:05.753831 u2DelayCellOfst[12]=14 cells (4 PI)
8934 04:41:05.753900 u2DelayCellOfst[13]=14 cells (4 PI)
8935 04:41:05.753961 u2DelayCellOfst[14]=17 cells (5 PI)
8936 04:41:05.754019 u2DelayCellOfst[15]=17 cells (5 PI)
8937 04:41:05.754079 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8938 04:41:05.754136 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8939 04:41:05.754194 DramC Write-DBI on
8940 04:41:05.754255 ==
8941 04:41:05.754316 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 04:41:05.754376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 04:41:05.754430 ==
8944 04:41:05.754484
8945 04:41:05.754539
8946 04:41:05.754607 TX Vref Scan disable
8947 04:41:05.754661 == TX Byte 0 ==
8948 04:41:05.754715 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8949 04:41:05.754767 == TX Byte 1 ==
8950 04:41:05.754823 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8951 04:41:05.754880 DramC Write-DBI off
8952 04:41:05.754935
8953 04:41:05.754987 [DATLAT]
8954 04:41:05.755039 Freq=1600, CH1 RK1
8955 04:41:05.755094
8956 04:41:05.755147 DATLAT Default: 0xf
8957 04:41:05.755199 0, 0xFFFF, sum = 0
8958 04:41:05.755253 1, 0xFFFF, sum = 0
8959 04:41:05.755306 2, 0xFFFF, sum = 0
8960 04:41:05.755362 3, 0xFFFF, sum = 0
8961 04:41:05.755419 4, 0xFFFF, sum = 0
8962 04:41:05.755488 5, 0xFFFF, sum = 0
8963 04:41:05.755549 6, 0xFFFF, sum = 0
8964 04:41:05.755605 7, 0xFFFF, sum = 0
8965 04:41:05.755657 8, 0xFFFF, sum = 0
8966 04:41:05.755711 9, 0xFFFF, sum = 0
8967 04:41:05.755764 10, 0xFFFF, sum = 0
8968 04:41:05.755826 11, 0xFFFF, sum = 0
8969 04:41:05.755880 12, 0xFFFF, sum = 0
8970 04:41:05.755933 13, 0xFFFF, sum = 0
8971 04:41:05.755986 14, 0x0, sum = 1
8972 04:41:05.756038 15, 0x0, sum = 2
8973 04:41:05.756094 16, 0x0, sum = 3
8974 04:41:05.756147 17, 0x0, sum = 4
8975 04:41:05.756204 best_step = 15
8976 04:41:05.756268
8977 04:41:05.756355 ==
8978 04:41:05.756438 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 04:41:05.756521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 04:41:05.756606 ==
8981 04:41:05.756695 RX Vref Scan: 0
8982 04:41:05.756751
8983 04:41:05.756807 RX Vref 0 -> 0, step: 1
8984 04:41:05.756862
8985 04:41:05.756917 RX Delay 11 -> 252, step: 4
8986 04:41:05.756973 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8987 04:41:05.757026 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8988 04:41:05.757078 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8989 04:41:05.757135 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
8990 04:41:05.757392 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8991 04:41:05.757461 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8992 04:41:05.757528 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8993 04:41:05.757624 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8994 04:41:05.757735 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8995 04:41:05.757840 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8996 04:41:05.757951 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8997 04:41:05.758038 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
8998 04:41:05.758120 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8999 04:41:05.758205 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9000 04:41:05.758294 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
9001 04:41:05.758358 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9002 04:41:05.758416 ==
9003 04:41:05.758473 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 04:41:05.758526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 04:41:05.758578 ==
9006 04:41:05.758634 DQS Delay:
9007 04:41:05.758688 DQS0 = 0, DQS1 = 0
9008 04:41:05.758743 DQM Delay:
9009 04:41:05.758797 DQM0 = 130, DQM1 = 126
9010 04:41:05.758849 DQ Delay:
9011 04:41:05.758904 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =128
9012 04:41:05.758959 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9013 04:41:05.759014 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9014 04:41:05.759066 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9015 04:41:05.759118
9016 04:41:05.759172
9017 04:41:05.759223
9018 04:41:05.759274 [DramC_TX_OE_Calibration] TA2
9019 04:41:05.759336 Original DQ_B0 (3 6) =30, OEN = 27
9020 04:41:05.759402 Original DQ_B1 (3 6) =30, OEN = 27
9021 04:41:05.759459 24, 0x0, End_B0=24 End_B1=24
9022 04:41:05.759515 25, 0x0, End_B0=25 End_B1=25
9023 04:41:05.759569 26, 0x0, End_B0=26 End_B1=26
9024 04:41:05.759621 27, 0x0, End_B0=27 End_B1=27
9025 04:41:05.759674 28, 0x0, End_B0=28 End_B1=28
9026 04:41:05.759730 29, 0x0, End_B0=29 End_B1=29
9027 04:41:05.759786 30, 0x0, End_B0=30 End_B1=30
9028 04:41:05.759841 31, 0x4545, End_B0=30 End_B1=30
9029 04:41:05.759897 Byte0 end_step=30 best_step=27
9030 04:41:05.759949 Byte1 end_step=30 best_step=27
9031 04:41:05.760001 Byte0 TX OE(2T, 0.5T) = (3, 3)
9032 04:41:05.760057 Byte1 TX OE(2T, 0.5T) = (3, 3)
9033 04:41:05.760115
9034 04:41:05.760170
9035 04:41:05.760231 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9036 04:41:05.760324 CH1 RK1: MR19=303, MR18=1117
9037 04:41:05.760413 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9038 04:41:05.760496 [RxdqsGatingPostProcess] freq 1600
9039 04:41:05.760579 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9040 04:41:05.760670 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 04:41:05.760732 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 04:41:05.760787 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 04:41:05.760839 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 04:41:05.760892 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 04:41:05.760960 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 04:41:05.761014 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 04:41:05.761066 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 04:41:05.761119 Pre-setting of DQS Precalculation
9049 04:41:05.761174 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9050 04:41:05.761227 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9051 04:41:05.761280 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 04:41:05.761333
9053 04:41:05.761389
9054 04:41:05.761443 [Calibration Summary] 3200 Mbps
9055 04:41:05.761498 CH 0, Rank 0
9056 04:41:05.761550 SW Impedance : PASS
9057 04:41:05.761602 DUTY Scan : NO K
9058 04:41:05.761654 ZQ Calibration : PASS
9059 04:41:05.761708 Jitter Meter : NO K
9060 04:41:05.761760 CBT Training : PASS
9061 04:41:05.761815 Write leveling : PASS
9062 04:41:05.761869 RX DQS gating : PASS
9063 04:41:05.761921 RX DQ/DQS(RDDQC) : PASS
9064 04:41:05.761975 TX DQ/DQS : PASS
9065 04:41:05.762028 RX DATLAT : PASS
9066 04:41:05.762078 RX DQ/DQS(Engine): PASS
9067 04:41:05.762129 TX OE : PASS
9068 04:41:05.762181 All Pass.
9069 04:41:05.762244
9070 04:41:05.762323 CH 0, Rank 1
9071 04:41:05.762415 SW Impedance : PASS
9072 04:41:05.762478 DUTY Scan : NO K
9073 04:41:05.762535 ZQ Calibration : PASS
9074 04:41:05.762590 Jitter Meter : NO K
9075 04:41:05.762642 CBT Training : PASS
9076 04:41:05.762698 Write leveling : PASS
9077 04:41:05.762753 RX DQS gating : PASS
9078 04:41:05.762807 RX DQ/DQS(RDDQC) : PASS
9079 04:41:05.762859 TX DQ/DQS : PASS
9080 04:41:05.762915 RX DATLAT : PASS
9081 04:41:05.762967 RX DQ/DQS(Engine): PASS
9082 04:41:05.763018 TX OE : PASS
9083 04:41:05.763074 All Pass.
9084 04:41:05.763128
9085 04:41:05.763183 CH 1, Rank 0
9086 04:41:05.763235 SW Impedance : PASS
9087 04:41:05.763287 DUTY Scan : NO K
9088 04:41:05.763339 ZQ Calibration : PASS
9089 04:41:05.763390 Jitter Meter : NO K
9090 04:41:05.763444 CBT Training : PASS
9091 04:41:05.763497 Write leveling : PASS
9092 04:41:05.763552 RX DQS gating : PASS
9093 04:41:05.763605 RX DQ/DQS(RDDQC) : PASS
9094 04:41:05.763657 TX DQ/DQS : PASS
9095 04:41:05.763712 RX DATLAT : PASS
9096 04:41:05.763768 RX DQ/DQS(Engine): PASS
9097 04:41:05.763823 TX OE : PASS
9098 04:41:05.763876 All Pass.
9099 04:41:05.763931
9100 04:41:05.763985 CH 1, Rank 1
9101 04:41:05.764040 SW Impedance : PASS
9102 04:41:05.764094 DUTY Scan : NO K
9103 04:41:05.764146 ZQ Calibration : PASS
9104 04:41:05.764210 Jitter Meter : NO K
9105 04:41:05.764305 CBT Training : PASS
9106 04:41:05.764396 Write leveling : PASS
9107 04:41:05.764494 RX DQS gating : PASS
9108 04:41:05.764601 RX DQ/DQS(RDDQC) : PASS
9109 04:41:05.764696 TX DQ/DQS : PASS
9110 04:41:05.764782 RX DATLAT : PASS
9111 04:41:05.764869 RX DQ/DQS(Engine): PASS
9112 04:41:05.764957 TX OE : PASS
9113 04:41:05.765039 All Pass.
9114 04:41:05.765121
9115 04:41:05.765205 DramC Write-DBI on
9116 04:41:05.765287 PER_BANK_REFRESH: Hybrid Mode
9117 04:41:05.765369 TX_TRACKING: ON
9118 04:41:05.765457 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9119 04:41:05.765547 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9120 04:41:05.765631 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 04:41:05.765717 [FAST_K] Save calibration result to emmc
9122 04:41:05.765800 sync common calibartion params.
9123 04:41:05.765882 sync cbt_mode0:1, 1:1
9124 04:41:05.765967 dram_init: ddr_geometry: 2
9125 04:41:05.766054 dram_init: ddr_geometry: 2
9126 04:41:05.766136 dram_init: ddr_geometry: 2
9127 04:41:05.766222 0:dram_rank_size:100000000
9128 04:41:05.766498 1:dram_rank_size:100000000
9129 04:41:05.766613 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9130 04:41:05.766732 DFS_SHUFFLE_HW_MODE: ON
9131 04:41:05.766838 dramc_set_vcore_voltage set vcore to 725000
9132 04:41:05.766923 Read voltage for 1600, 0
9133 04:41:05.767009 Vio18 = 0
9134 04:41:05.767092 Vcore = 725000
9135 04:41:05.767174 Vdram = 0
9136 04:41:05.767261 Vddq = 0
9137 04:41:05.767348 Vmddr = 0
9138 04:41:05.767431 switch to 3200 Mbps bootup
9139 04:41:05.767516 [DramcRunTimeConfig]
9140 04:41:05.767598 PHYPLL
9141 04:41:05.767692 DPM_CONTROL_AFTERK: ON
9142 04:41:05.767783 PER_BANK_REFRESH: ON
9143 04:41:05.767841 REFRESH_OVERHEAD_REDUCTION: ON
9144 04:41:05.767895 CMD_PICG_NEW_MODE: OFF
9145 04:41:05.767950 XRTWTW_NEW_MODE: ON
9146 04:41:05.768003 XRTRTR_NEW_MODE: ON
9147 04:41:05.768056 TX_TRACKING: ON
9148 04:41:05.768108 RDSEL_TRACKING: OFF
9149 04:41:05.768160 DQS Precalculation for DVFS: ON
9150 04:41:05.768215 RX_TRACKING: OFF
9151 04:41:05.768268 HW_GATING DBG: ON
9152 04:41:05.768324 ZQCS_ENABLE_LP4: ON
9153 04:41:05.768378 RX_PICG_NEW_MODE: ON
9154 04:41:05.768430 TX_PICG_NEW_MODE: ON
9155 04:41:05.768486 ENABLE_RX_DCM_DPHY: ON
9156 04:41:05.768538 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9157 04:41:05.768591 DUMMY_READ_FOR_TRACKING: OFF
9158 04:41:05.768646 !!! SPM_CONTROL_AFTERK: OFF
9159 04:41:05.768725 !!! SPM could not control APHY
9160 04:41:05.768823 IMPEDANCE_TRACKING: ON
9161 04:41:05.768920 TEMP_SENSOR: ON
9162 04:41:05.769012 HW_SAVE_FOR_SR: OFF
9163 04:41:05.769096 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9164 04:41:05.769179 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9165 04:41:05.769265 Read ODT Tracking: ON
9166 04:41:05.769350 Refresh Rate DeBounce: ON
9167 04:41:05.769438 DFS_NO_QUEUE_FLUSH: ON
9168 04:41:05.769520 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9169 04:41:05.769603 ENABLE_DFS_RUNTIME_MRW: OFF
9170 04:41:05.769689 DDR_RESERVE_NEW_MODE: ON
9171 04:41:05.769774 MR_CBT_SWITCH_FREQ: ON
9172 04:41:05.769858 =========================
9173 04:41:05.769945 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9174 04:41:05.770028 dram_init: ddr_geometry: 2
9175 04:41:05.770112 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9176 04:41:05.770198 dram_init: dram init end (result: 0)
9177 04:41:05.770281 DRAM-K: Full calibration passed in 24580 msecs
9178 04:41:05.770364 MRC: failed to locate region type 0.
9179 04:41:05.770449 DRAM rank0 size:0x100000000,
9180 04:41:05.770535 DRAM rank1 size=0x100000000
9181 04:41:05.770624 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9182 04:41:05.770714 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9183 04:41:05.770801 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9184 04:41:05.770886 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9185 04:41:05.770969 DRAM rank0 size:0x100000000,
9186 04:41:05.771051 DRAM rank1 size=0x100000000
9187 04:41:05.771144 CBMEM:
9188 04:41:05.771230 IMD: root @ 0xfffff000 254 entries.
9189 04:41:05.771316 IMD: root @ 0xffffec00 62 entries.
9190 04:41:05.771399 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9191 04:41:05.771486 WARNING: RO_VPD is uninitialized or empty.
9192 04:41:05.771575 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9193 04:41:05.771661 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9194 04:41:05.771749 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9195 04:41:05.771837 BS: romstage times (exec / console): total (unknown) / 24083 ms
9196 04:41:05.771922
9197 04:41:05.772008
9198 04:41:05.772097 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9199 04:41:05.772186 ARM64: Exception handlers installed.
9200 04:41:05.772271 ARM64: Testing exception
9201 04:41:05.772359 ARM64: Done test exception
9202 04:41:05.772444 Enumerating buses...
9203 04:41:05.772526 Show all devs... Before device enumeration.
9204 04:41:05.772609 Root Device: enabled 1
9205 04:41:05.772696 CPU_CLUSTER: 0: enabled 1
9206 04:41:05.772759 CPU: 00: enabled 1
9207 04:41:05.772812 Compare with tree...
9208 04:41:05.772864 Root Device: enabled 1
9209 04:41:05.772928 CPU_CLUSTER: 0: enabled 1
9210 04:41:05.772981 CPU: 00: enabled 1
9211 04:41:05.773034 Root Device scanning...
9212 04:41:05.773086 scan_static_bus for Root Device
9213 04:41:05.773138 CPU_CLUSTER: 0 enabled
9214 04:41:05.773194 scan_static_bus for Root Device done
9215 04:41:05.773247 scan_bus: bus Root Device finished in 8 msecs
9216 04:41:05.773299 done
9217 04:41:05.773353 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9218 04:41:05.773409 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9219 04:41:05.773462 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9220 04:41:05.773515 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9221 04:41:05.773567 Allocating resources...
9222 04:41:05.773619 Reading resources...
9223 04:41:05.773674 Root Device read_resources bus 0 link: 0
9224 04:41:05.773727 DRAM rank0 size:0x100000000,
9225 04:41:05.773782 DRAM rank1 size=0x100000000
9226 04:41:05.773836 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9227 04:41:05.773891 CPU: 00 missing read_resources
9228 04:41:05.773944 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9229 04:41:05.773996 Root Device read_resources bus 0 link: 0 done
9230 04:41:05.774048 Done reading resources.
9231 04:41:05.774100 Show resources in subtree (Root Device)...After reading.
9232 04:41:05.774156 Root Device child on link 0 CPU_CLUSTER: 0
9233 04:41:05.774216 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 04:41:05.774270 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 04:41:05.774323 CPU: 00
9236 04:41:05.774375 Root Device assign_resources, bus 0 link: 0
9237 04:41:05.774430 CPU_CLUSTER: 0 missing set_resources
9238 04:41:05.774482 Root Device assign_resources, bus 0 link: 0 done
9239 04:41:05.774534 Done setting resources.
9240 04:41:05.774590 Show resources in subtree (Root Device)...After assigning values.
9241 04:41:05.774645 Root Device child on link 0 CPU_CLUSTER: 0
9242 04:41:05.774701 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 04:41:05.774941 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 04:41:05.775004 CPU: 00
9245 04:41:05.775058 Done allocating resources.
9246 04:41:05.775111 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9247 04:41:05.775167 Enabling resources...
9248 04:41:05.775223 done.
9249 04:41:05.775278 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9250 04:41:05.775330 Initializing devices...
9251 04:41:05.775385 Root Device init
9252 04:41:05.775438 init hardware done!
9253 04:41:05.775490 0x00000018: ctrlr->caps
9254 04:41:05.775547 52.000 MHz: ctrlr->f_max
9255 04:41:05.775605 0.400 MHz: ctrlr->f_min
9256 04:41:05.775664 0x40ff8080: ctrlr->voltages
9257 04:41:05.775719 sclk: 390625
9258 04:41:05.775771 Bus Width = 1
9259 04:41:05.775822 sclk: 390625
9260 04:41:05.775874 Bus Width = 1
9261 04:41:05.775929 Early init status = 3
9262 04:41:05.775981 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9263 04:41:05.776037 in-header: 03 fc 00 00 01 00 00 00
9264 04:41:05.776091 in-data: 00
9265 04:41:05.776147 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9266 04:41:05.776204 in-header: 03 fd 00 00 00 00 00 00
9267 04:41:05.776259 in-data:
9268 04:41:05.776310 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9269 04:41:05.776362 in-header: 03 fc 00 00 01 00 00 00
9270 04:41:05.776417 in-data: 00
9271 04:41:05.776470 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9272 04:41:05.776522 in-header: 03 fd 00 00 00 00 00 00
9273 04:41:05.776575 in-data:
9274 04:41:05.776675 [SSUSB] Setting up USB HOST controller...
9275 04:41:05.776739 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9276 04:41:05.776794 [SSUSB] phy power-on done.
9277 04:41:05.776847 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9278 04:41:05.776903 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9279 04:41:05.776957 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9280 04:41:05.777010 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9281 04:41:05.777063 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9282 04:41:05.777119 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9283 04:41:05.777175 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9284 04:41:05.777231 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9285 04:41:05.777289 SPM: binary array size = 0x9dc
9286 04:41:05.777345 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9287 04:41:05.777401 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9288 04:41:05.777456 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9289 04:41:05.777509 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9290 04:41:05.777565 configure_display: Starting display init
9291 04:41:05.777617 anx7625_power_on_init: Init interface.
9292 04:41:05.777670 anx7625_disable_pd_protocol: Disabled PD feature.
9293 04:41:05.777734 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9294 04:41:05.777791 anx7625_start_dp_work: Secure OCM version=00
9295 04:41:05.777844 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9296 04:41:05.777897 sp_tx_get_edid_block: EDID Block = 1
9297 04:41:05.777950 Extracted contents:
9298 04:41:05.778005 header: 00 ff ff ff ff ff ff 00
9299 04:41:05.778061 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9300 04:41:05.778117 version: 01 04
9301 04:41:05.778174 basic params: 95 1f 11 78 0a
9302 04:41:05.778226 chroma info: 76 90 94 55 54 90 27 21 50 54
9303 04:41:05.778282 established: 00 00 00
9304 04:41:05.778335 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9305 04:41:05.778387 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9306 04:41:05.778443 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9307 04:41:05.778495 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9308 04:41:05.778552 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9309 04:41:05.778604 extensions: 00
9310 04:41:05.778659 checksum: fb
9311 04:41:05.778711
9312 04:41:05.778763 Manufacturer: IVO Model 57d Serial Number 0
9313 04:41:05.778819 Made week 0 of 2020
9314 04:41:05.778872 EDID version: 1.4
9315 04:41:05.778926 Digital display
9316 04:41:05.778978 6 bits per primary color channel
9317 04:41:05.779031 DisplayPort interface
9318 04:41:05.779088 Maximum image size: 31 cm x 17 cm
9319 04:41:05.779143 Gamma: 220%
9320 04:41:05.779195 Check DPMS levels
9321 04:41:05.779246 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9322 04:41:05.779297 First detailed timing is preferred timing
9323 04:41:05.779350 Established timings supported:
9324 04:41:05.779405 Standard timings supported:
9325 04:41:05.779462 Detailed timings
9326 04:41:05.779517 Hex of detail: 383680a07038204018303c0035ae10000019
9327 04:41:05.779573 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9328 04:41:05.779628 0780 0798 07c8 0820 hborder 0
9329 04:41:05.779680 0438 043b 0447 0458 vborder 0
9330 04:41:05.779732 -hsync -vsync
9331 04:41:05.779786 Did detailed timing
9332 04:41:05.779838 Hex of detail: 000000000000000000000000000000000000
9333 04:41:05.779890 Manufacturer-specified data, tag 0
9334 04:41:05.779942 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9335 04:41:05.779994 ASCII string: InfoVision
9336 04:41:05.780050 Hex of detail: 000000fe00523134304e574635205248200a
9337 04:41:05.780106 ASCII string: R140NWF5 RH
9338 04:41:05.780161 Checksum
9339 04:41:05.780217 Checksum: 0xfb (valid)
9340 04:41:05.780272 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9341 04:41:05.780327 DSI data_rate: 832800000 bps
9342 04:41:05.780379 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9343 04:41:05.780430 anx7625_parse_edid: pixelclock(138800).
9344 04:41:05.780482 hactive(1920), hsync(48), hfp(24), hbp(88)
9345 04:41:05.780572 vactive(1080), vsync(12), vfp(3), vbp(17)
9346 04:41:05.780660 anx7625_dsi_config: config dsi.
9347 04:41:05.780914 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9348 04:41:05.780974 anx7625_dsi_config: success to config DSI
9349 04:41:05.781031 anx7625_dp_start: MIPI phy setup OK.
9350 04:41:05.781083 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9351 04:41:05.781135 mtk_ddp_mode_set invalid vrefresh 60
9352 04:41:05.781187 main_disp_path_setup
9353 04:41:05.781245 ovl_layer_smi_id_en
9354 04:41:05.781304 ovl_layer_smi_id_en
9355 04:41:05.781360 ccorr_config
9356 04:41:05.781413 aal_config
9357 04:41:05.781465 gamma_config
9358 04:41:05.781519 postmask_config
9359 04:41:05.781571 dither_config
9360 04:41:05.781622 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9361 04:41:05.781677 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9362 04:41:05.781733 Root Device init finished in 553 msecs
9363 04:41:05.781789 CPU_CLUSTER: 0 init
9364 04:41:05.781843 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9365 04:41:05.781896 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9366 04:41:05.781948 APU_MBOX 0x190000b0 = 0x10001
9367 04:41:05.782003 APU_MBOX 0x190001b0 = 0x10001
9368 04:41:05.782058 APU_MBOX 0x190005b0 = 0x10001
9369 04:41:05.782112 APU_MBOX 0x190006b0 = 0x10001
9370 04:41:05.782163 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9371 04:41:05.782216 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9372 04:41:05.782272 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9373 04:41:05.782329 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9374 04:41:05.782383 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9375 04:41:05.782436 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9376 04:41:05.782491 CPU_CLUSTER: 0 init finished in 81 msecs
9377 04:41:05.782543 Devices initialized
9378 04:41:05.782594 Show all devs... After init.
9379 04:41:05.782645 Root Device: enabled 1
9380 04:41:05.782697 CPU_CLUSTER: 0: enabled 1
9381 04:41:05.782749 CPU: 00: enabled 1
9382 04:41:05.782803 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9383 04:41:05.782859 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9384 04:41:05.782914 ELOG: NV offset 0x57f000 size 0x1000
9385 04:41:05.782971 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9386 04:41:05.783024 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9387 04:41:05.783080 ELOG: Event(17) added with size 13 at 2023-08-09 04:41:04 UTC
9388 04:41:05.783132 out: cmd=0x121: 03 db 21 01 00 00 00 00
9389 04:41:05.783184 in-header: 03 cd 00 00 2c 00 00 00
9390 04:41:05.783236 in-data: 92 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 04:41:05.783295 ELOG: Event(A1) added with size 10 at 2023-08-09 04:41:04 UTC
9392 04:41:05.783348 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9393 04:41:05.783401 ELOG: Event(A0) added with size 9 at 2023-08-09 04:41:04 UTC
9394 04:41:05.783453 elog_add_boot_reason: Logged dev mode boot
9395 04:41:05.783505 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9396 04:41:05.783560 Finalize devices...
9397 04:41:05.783616 Devices finalized
9398 04:41:05.783670 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9399 04:41:05.783722 Writing coreboot table at 0xffe64000
9400 04:41:05.783777 0. 000000000010a000-0000000000113fff: RAMSTAGE
9401 04:41:05.783833 1. 0000000040000000-00000000400fffff: RAM
9402 04:41:05.783887 2. 0000000040100000-000000004032afff: RAMSTAGE
9403 04:41:05.783939 3. 000000004032b000-00000000545fffff: RAM
9404 04:41:05.783991 4. 0000000054600000-000000005465ffff: BL31
9405 04:41:05.784046 5. 0000000054660000-00000000ffe63fff: RAM
9406 04:41:05.784098 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9407 04:41:05.784151 7. 0000000100000000-000000023fffffff: RAM
9408 04:41:05.784206 Passing 5 GPIOs to payload:
9409 04:41:05.784263 NAME | PORT | POLARITY | VALUE
9410 04:41:05.784320 EC in RW | 0x000000aa | low | undefined
9411 04:41:05.784372 EC interrupt | 0x00000005 | low | undefined
9412 04:41:05.784428 TPM interrupt | 0x000000ab | high | undefined
9413 04:41:05.784489 SD card detect | 0x00000011 | high | undefined
9414 04:41:05.784546 speaker enable | 0x00000093 | high | undefined
9415 04:41:05.784600 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9416 04:41:05.784653 in-header: 03 f9 00 00 02 00 00 00
9417 04:41:05.784716 in-data: 02 00
9418 04:41:05.784768 ADC[4]: Raw value=900221 ID=7
9419 04:41:05.784823 ADC[3]: Raw value=213336 ID=1
9420 04:41:05.784874 RAM Code: 0x71
9421 04:41:05.784926 ADC[6]: Raw value=74557 ID=0
9422 04:41:05.784978 ADC[5]: Raw value=212229 ID=1
9423 04:41:05.785029 SKU Code: 0x1
9424 04:41:05.785084 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae41
9425 04:41:05.785141 coreboot table: 964 bytes.
9426 04:41:05.785194 IMD ROOT 0. 0xfffff000 0x00001000
9427 04:41:05.785245 IMD SMALL 1. 0xffffe000 0x00001000
9428 04:41:05.785300 RO MCACHE 2. 0xffffc000 0x00001104
9429 04:41:05.785355 CONSOLE 3. 0xfff7c000 0x00080000
9430 04:41:05.785408 FMAP 4. 0xfff7b000 0x00000452
9431 04:41:05.785460 TIME STAMP 5. 0xfff7a000 0x00000910
9432 04:41:05.785513 VBOOT WORK 6. 0xfff66000 0x00014000
9433 04:41:05.785568 RAMOOPS 7. 0xffe66000 0x00100000
9434 04:41:05.785620 COREBOOT 8. 0xffe64000 0x00002000
9435 04:41:05.785671 IMD small region:
9436 04:41:05.785722 IMD ROOT 0. 0xffffec00 0x00000400
9437 04:41:05.785777 VPD 1. 0xffffeba0 0x0000004c
9438 04:41:05.785833 MMC STATUS 2. 0xffffeb80 0x00000004
9439 04:41:05.785886 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9440 04:41:05.785938 Probing TPM: done!
9441 04:41:05.785990 Connected to device vid:did:rid of 1ae0:0028:00
9442 04:41:05.786229 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9443 04:41:05.786308 Initialized TPM device CR50 revision 0
9444 04:41:05.786364 Checking cr50 for pending updates
9445 04:41:05.786421 Reading cr50 TPM mode
9446 04:41:05.786475 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9447 04:41:05.786531 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9448 04:41:05.786584 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9449 04:41:05.786637 Checking segment from ROM address 0x40100000
9450 04:41:05.786693 Checking segment from ROM address 0x4010001c
9451 04:41:05.786747 Loading segment from ROM address 0x40100000
9452 04:41:05.786802 code (compression=0)
9453 04:41:05.786858 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9454 04:41:05.786913 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9455 04:41:05.786965 it's not compressed!
9456 04:41:05.787019 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9457 04:41:05.787072 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9458 04:41:05.787124 Loading segment from ROM address 0x4010001c
9459 04:41:05.787180 Entry Point 0x80000000
9460 04:41:05.787234 Loaded segments
9461 04:41:05.787290 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9462 04:41:05.787346 Jumping to boot code at 0x80000000(0xffe64000)
9463 04:41:05.787400 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9464 04:41:05.787457 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9465 04:41:05.787512 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9466 04:41:05.787568 Checking segment from ROM address 0x40100000
9467 04:41:05.787620 Checking segment from ROM address 0x4010001c
9468 04:41:05.787671 Loading segment from ROM address 0x40100000
9469 04:41:05.787722 code (compression=1)
9470 04:41:05.787776 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9471 04:41:05.787828 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9472 04:41:05.787887 using LZMA
9473 04:41:05.787949 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9474 04:41:05.788003 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9475 04:41:05.788059 Loading segment from ROM address 0x4010001c
9476 04:41:05.788111 Entry Point 0x54601000
9477 04:41:05.788163 Loaded segments
9478 04:41:05.788215 NOTICE: MT8192 bl31_setup
9479 04:41:05.788267 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9480 04:41:05.788324 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9481 04:41:05.788391 WARNING: region 0:
9482 04:41:05.788446 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 04:41:05.788499 WARNING: region 1:
9484 04:41:05.788554 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9485 04:41:05.788611 WARNING: region 2:
9486 04:41:05.788685 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9487 04:41:05.788742 WARNING: region 3:
9488 04:41:05.788798 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 04:41:05.788851 WARNING: region 4:
9490 04:41:05.788902 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 04:41:05.788958 WARNING: region 5:
9492 04:41:05.789013 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 04:41:05.789068 WARNING: region 6:
9494 04:41:05.789123 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 04:41:05.789177 WARNING: region 7:
9496 04:41:05.789232 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 04:41:05.789287 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9498 04:41:05.789342 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9499 04:41:05.789396 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9500 04:41:05.789449 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9501 04:41:05.789505 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9502 04:41:05.789559 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9503 04:41:05.789611 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9504 04:41:05.789667 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9505 04:41:05.789719 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9506 04:41:05.789771 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9507 04:41:05.789823 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9508 04:41:05.789874 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9509 04:41:05.789929 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9510 04:41:05.789985 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9511 04:41:05.790039 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9512 04:41:05.790095 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9513 04:41:05.790152 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9514 04:41:05.790208 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9515 04:41:05.790262 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9516 04:41:05.790315 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9517 04:41:05.790367 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9518 04:41:05.790423 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9519 04:41:05.790478 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9520 04:41:05.790533 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9521 04:41:05.790588 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9522 04:41:05.790643 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9523 04:41:05.790698 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9524 04:41:05.790754 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9525 04:41:05.790808 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9526 04:41:05.791043 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9527 04:41:05.791105 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9528 04:41:05.791161 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9529 04:41:05.791221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9530 04:41:05.791279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9531 04:41:05.791334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9532 04:41:05.791386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9533 04:41:05.791442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9534 04:41:05.791493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9535 04:41:05.791559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9536 04:41:05.791620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9537 04:41:05.791681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9538 04:41:05.791737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9539 04:41:05.791790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9540 04:41:05.791864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9541 04:41:05.791922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9542 04:41:05.791990 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9543 04:41:05.792047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9544 04:41:05.792099 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9545 04:41:05.792169 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9546 04:41:05.792227 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9547 04:41:05.792288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9548 04:41:05.792351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9549 04:41:05.792416 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9550 04:41:05.792474 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9551 04:41:05.792539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9552 04:41:05.792611 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9553 04:41:05.792678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9554 04:41:05.792734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9555 04:41:05.792805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9556 04:41:05.792869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9557 04:41:05.792932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9558 04:41:05.793003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9559 04:41:05.793064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9560 04:41:05.793128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9561 04:41:05.793194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9562 04:41:05.793255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9563 04:41:05.793319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9564 04:41:05.793389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9565 04:41:05.793454 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9566 04:41:05.793515 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9567 04:41:05.793583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9568 04:41:05.793643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9569 04:41:05.793709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9570 04:41:05.793764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9571 04:41:05.793837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9572 04:41:05.793893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9573 04:41:05.793957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9574 04:41:05.794028 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9575 04:41:05.794089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9576 04:41:05.794150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9577 04:41:05.794212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9578 04:41:05.794283 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9579 04:41:05.794345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9580 04:41:05.794405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9581 04:41:05.794475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9582 04:41:05.794536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9583 04:41:05.794608 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9584 04:41:05.794677 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9585 04:41:05.794741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9586 04:41:05.794797 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9587 04:41:05.794864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9588 04:41:05.794926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9589 04:41:05.794988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9590 04:41:05.795049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9591 04:41:05.795118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9592 04:41:05.795179 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9593 04:41:05.795247 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9594 04:41:05.795310 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9595 04:41:05.795371 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9596 04:41:05.795432 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9597 04:41:05.795500 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9598 04:41:05.795561 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9599 04:41:05.795622 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9600 04:41:05.795683 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9601 04:41:05.795744 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9602 04:41:05.795806 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9603 04:41:05.796053 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9604 04:41:05.796116 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9605 04:41:05.796173 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9606 04:41:05.796227 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9607 04:41:05.796282 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9608 04:41:05.796346 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9609 04:41:05.796404 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9610 04:41:05.796459 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9611 04:41:05.796515 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9612 04:41:05.796571 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9613 04:41:05.796625 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9614 04:41:05.796686 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9615 04:41:05.796740 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9616 04:41:05.796793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9617 04:41:05.796848 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9618 04:41:05.796906 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9619 04:41:05.796958 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9620 04:41:05.797013 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9621 04:41:05.797066 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9622 04:41:05.797118 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9623 04:41:05.797171 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9624 04:41:05.797227 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9625 04:41:05.797280 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9626 04:41:05.797336 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9627 04:41:05.797388 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9628 04:41:05.797443 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9629 04:41:05.797497 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9630 04:41:05.797553 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9631 04:41:05.797605 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9632 04:41:05.797657 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9633 04:41:05.797708 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9634 04:41:05.797771 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9635 04:41:05.797828 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9636 04:41:05.797882 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9637 04:41:05.797937 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9638 04:41:05.797992 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9639 04:41:05.798048 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9640 04:41:05.798103 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9641 04:41:05.798157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9642 04:41:05.798209 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9643 04:41:05.798265 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9644 04:41:05.798318 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9645 04:41:05.798375 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9646 04:41:05.798427 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9647 04:41:05.798483 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9648 04:41:05.798537 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9649 04:41:05.798592 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9650 04:41:05.798644 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9651 04:41:05.798696 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9652 04:41:05.798748 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9653 04:41:05.798803 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9654 04:41:05.798874 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9655 04:41:05.798929 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9656 04:41:05.798994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9657 04:41:05.804660 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9658 04:41:05.807786 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9659 04:41:05.814322 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9660 04:41:05.818018 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9661 04:41:05.820865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9662 04:41:05.828027 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9663 04:41:05.831103 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9664 04:41:05.837685 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9665 04:41:05.841145 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9666 04:41:05.844478 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9667 04:41:05.851169 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9668 04:41:05.854297 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9669 04:41:05.857808 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9670 04:41:05.864634 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9671 04:41:05.868038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9672 04:41:05.874659 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9673 04:41:05.878040 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9674 04:41:05.881583 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9675 04:41:05.888180 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9676 04:41:05.891134 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9677 04:41:05.894837 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9678 04:41:05.901535 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9679 04:41:05.904521 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9680 04:41:05.911007 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9681 04:41:05.914472 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9682 04:41:05.918255 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9683 04:41:05.924742 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9684 04:41:05.928345 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9685 04:41:05.934934 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9686 04:41:05.938137 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9687 04:41:05.941905 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9688 04:41:05.948922 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9689 04:41:05.951594 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9690 04:41:05.958545 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9691 04:41:05.961857 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9692 04:41:05.964803 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9693 04:41:05.971699 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9694 04:41:05.975103 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9695 04:41:05.981676 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9696 04:41:05.985360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9697 04:41:05.988217 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9698 04:41:05.995354 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9699 04:41:05.998466 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9700 04:41:06.004882 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9701 04:41:06.008641 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9702 04:41:06.012213 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9703 04:41:06.018660 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9704 04:41:06.022261 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9705 04:41:06.028390 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9706 04:41:06.032370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9707 04:41:06.035084 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9708 04:41:06.041768 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9709 04:41:06.045359 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9710 04:41:06.051751 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9711 04:41:06.054853 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9712 04:41:06.061982 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9713 04:41:06.065353 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9714 04:41:06.068550 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9715 04:41:06.075202 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9716 04:41:06.078526 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9717 04:41:06.085427 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9718 04:41:06.088520 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9719 04:41:06.091873 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9720 04:41:06.098443 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9721 04:41:06.101965 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9722 04:41:06.108518 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9723 04:41:06.112105 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9724 04:41:06.115119 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9725 04:41:06.121767 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9726 04:41:06.125286 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9727 04:41:06.128997 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9728 04:41:06.132066 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9729 04:41:06.138614 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9730 04:41:06.142006 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9731 04:41:06.145749 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9732 04:41:06.152514 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9733 04:41:06.155708 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9734 04:41:06.158777 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9735 04:41:06.165609 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9736 04:41:06.169347 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9737 04:41:06.172330 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9738 04:41:06.178819 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9739 04:41:06.182261 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9740 04:41:06.185661 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9741 04:41:06.192044 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9742 04:41:06.195564 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9743 04:41:06.202056 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9744 04:41:06.205857 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9745 04:41:06.208690 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9746 04:41:06.215584 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9747 04:41:06.219068 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9748 04:41:06.222505 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9749 04:41:06.229140 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9750 04:41:06.232510 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9751 04:41:06.235615 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9752 04:41:06.242675 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9753 04:41:06.246065 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9754 04:41:06.249084 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9755 04:41:06.256263 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9756 04:41:06.259229 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9757 04:41:06.262747 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9758 04:41:06.269068 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9759 04:41:06.272520 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9760 04:41:06.275893 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9761 04:41:06.282702 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9762 04:41:06.286254 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9763 04:41:06.292810 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9764 04:41:06.296272 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9765 04:41:06.299348 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9766 04:41:06.303000 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9767 04:41:06.309768 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9768 04:41:06.312713 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9769 04:41:06.316387 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9770 04:41:06.319407 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9771 04:41:06.326063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9772 04:41:06.329567 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9773 04:41:06.333250 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9774 04:41:06.335997 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9775 04:41:06.339709 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9776 04:41:06.346115 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9777 04:41:06.349626 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9778 04:41:06.353170 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9779 04:41:06.359637 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9780 04:41:06.363290 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9781 04:41:06.370213 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9782 04:41:06.373267 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9783 04:41:06.376381 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9784 04:41:06.383284 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9785 04:41:06.386447 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9786 04:41:06.389691 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9787 04:41:06.396778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9788 04:41:06.400032 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9789 04:41:06.406859 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9790 04:41:06.409994 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9791 04:41:06.416513 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9792 04:41:06.419562 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9793 04:41:06.423152 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9794 04:41:06.429765 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9795 04:41:06.433269 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9796 04:41:06.439887 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9797 04:41:06.443376 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9798 04:41:06.446424 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9799 04:41:06.453164 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9800 04:41:06.456447 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9801 04:41:06.463266 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9802 04:41:06.466448 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9803 04:41:06.469994 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9804 04:41:06.476640 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9805 04:41:06.479922 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9806 04:41:06.486724 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9807 04:41:06.489728 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9808 04:41:06.493129 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9809 04:41:06.500121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9810 04:41:06.503119 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9811 04:41:06.509776 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9812 04:41:06.513231 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9813 04:41:06.516822 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9814 04:41:06.523032 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9815 04:41:06.526735 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9816 04:41:06.533503 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9817 04:41:06.536354 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9818 04:41:06.540064 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9819 04:41:06.546534 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9820 04:41:06.550173 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9821 04:41:06.556731 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9822 04:41:06.559685 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9823 04:41:06.563402 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9824 04:41:06.569779 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9825 04:41:06.573130 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9826 04:41:06.580084 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9827 04:41:06.583512 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9828 04:41:06.587081 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9829 04:41:06.593062 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9830 04:41:06.596822 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9831 04:41:06.603079 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9832 04:41:06.606805 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9833 04:41:06.610154 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9834 04:41:06.616728 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9835 04:41:06.620006 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9836 04:41:06.626825 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9837 04:41:06.630067 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9838 04:41:06.633065 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9839 04:41:06.640279 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9840 04:41:06.643449 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9841 04:41:06.649885 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9842 04:41:06.653342 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9843 04:41:06.656444 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9844 04:41:06.663041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9845 04:41:06.666522 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9846 04:41:06.673318 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9847 04:41:06.676659 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9848 04:41:06.680013 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9849 04:41:06.686653 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9850 04:41:06.689835 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9851 04:41:06.696844 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9852 04:41:06.700058 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9853 04:41:06.706839 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9854 04:41:06.709731 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9855 04:41:06.713270 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9856 04:41:06.720159 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9857 04:41:06.723644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9858 04:41:06.730145 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9859 04:41:06.733549 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9860 04:41:06.736904 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9861 04:41:06.743534 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9862 04:41:06.746526 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9863 04:41:06.753756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9864 04:41:06.756496 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9865 04:41:06.763258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9866 04:41:06.766928 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9867 04:41:06.769942 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9868 04:41:06.776488 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9869 04:41:06.780347 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9870 04:41:06.786587 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9871 04:41:06.790286 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9872 04:41:06.796788 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9873 04:41:06.800154 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9874 04:41:06.803150 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9875 04:41:06.810395 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9876 04:41:06.813634 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9877 04:41:06.820193 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9878 04:41:06.823646 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9879 04:41:06.830455 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9880 04:41:06.833889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9881 04:41:06.840009 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9882 04:41:06.843346 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9883 04:41:06.846772 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9884 04:41:06.853229 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9885 04:41:06.856773 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9886 04:41:06.863185 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9887 04:41:06.866743 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9888 04:41:06.873544 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9889 04:41:06.876775 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9890 04:41:06.880197 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9891 04:41:06.886866 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9892 04:41:06.890334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9893 04:41:06.896510 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9894 04:41:06.899824 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9895 04:41:06.903408 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9896 04:41:06.910270 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9897 04:41:06.913142 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9898 04:41:06.920196 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9899 04:41:06.922968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9900 04:41:06.926749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9901 04:41:06.933598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9902 04:41:06.936990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9903 04:41:06.943684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9904 04:41:06.946626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9905 04:41:06.953563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9906 04:41:06.956558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9907 04:41:06.963614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9908 04:41:06.966709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9909 04:41:06.973681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9910 04:41:06.977463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9911 04:41:06.983360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9912 04:41:06.987083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9913 04:41:06.993774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9914 04:41:06.997459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9915 04:41:07.003602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9916 04:41:07.007089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9917 04:41:07.010783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9918 04:41:07.017512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9919 04:41:07.020258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9920 04:41:07.027251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9921 04:41:07.031015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9922 04:41:07.037311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9923 04:41:07.040272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9924 04:41:07.046835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9925 04:41:07.050278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9926 04:41:07.057786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9927 04:41:07.060180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9928 04:41:07.066706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9929 04:41:07.070417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9930 04:41:07.077226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9931 04:41:07.080581 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9932 04:41:07.083572 INFO: [APUAPC] vio 0
9933 04:41:07.087183 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9934 04:41:07.093802 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9935 04:41:07.096940 INFO: [APUAPC] D0_APC_0: 0x400510
9936 04:41:07.097026 INFO: [APUAPC] D0_APC_1: 0x0
9937 04:41:07.100565 INFO: [APUAPC] D0_APC_2: 0x1540
9938 04:41:07.103488 INFO: [APUAPC] D0_APC_3: 0x0
9939 04:41:07.106955 INFO: [APUAPC] D1_APC_0: 0xffffffff
9940 04:41:07.110558 INFO: [APUAPC] D1_APC_1: 0xffffffff
9941 04:41:07.114017 INFO: [APUAPC] D1_APC_2: 0x3fffff
9942 04:41:07.117024 INFO: [APUAPC] D1_APC_3: 0x0
9943 04:41:07.121184 INFO: [APUAPC] D2_APC_0: 0xffffffff
9944 04:41:07.123950 INFO: [APUAPC] D2_APC_1: 0xffffffff
9945 04:41:07.127758 INFO: [APUAPC] D2_APC_2: 0x3fffff
9946 04:41:07.131066 INFO: [APUAPC] D2_APC_3: 0x0
9947 04:41:07.134166 INFO: [APUAPC] D3_APC_0: 0xffffffff
9948 04:41:07.137352 INFO: [APUAPC] D3_APC_1: 0xffffffff
9949 04:41:07.141099 INFO: [APUAPC] D3_APC_2: 0x3fffff
9950 04:41:07.144136 INFO: [APUAPC] D3_APC_3: 0x0
9951 04:41:07.147387 INFO: [APUAPC] D4_APC_0: 0xffffffff
9952 04:41:07.150736 INFO: [APUAPC] D4_APC_1: 0xffffffff
9953 04:41:07.154186 INFO: [APUAPC] D4_APC_2: 0x3fffff
9954 04:41:07.157156 INFO: [APUAPC] D4_APC_3: 0x0
9955 04:41:07.160868 INFO: [APUAPC] D5_APC_0: 0xffffffff
9956 04:41:07.164077 INFO: [APUAPC] D5_APC_1: 0xffffffff
9957 04:41:07.167128 INFO: [APUAPC] D5_APC_2: 0x3fffff
9958 04:41:07.171240 INFO: [APUAPC] D5_APC_3: 0x0
9959 04:41:07.174002 INFO: [APUAPC] D6_APC_0: 0xffffffff
9960 04:41:07.177380 INFO: [APUAPC] D6_APC_1: 0xffffffff
9961 04:41:07.180940 INFO: [APUAPC] D6_APC_2: 0x3fffff
9962 04:41:07.183946 INFO: [APUAPC] D6_APC_3: 0x0
9963 04:41:07.187547 INFO: [APUAPC] D7_APC_0: 0xffffffff
9964 04:41:07.190762 INFO: [APUAPC] D7_APC_1: 0xffffffff
9965 04:41:07.194469 INFO: [APUAPC] D7_APC_2: 0x3fffff
9966 04:41:07.197138 INFO: [APUAPC] D7_APC_3: 0x0
9967 04:41:07.200647 INFO: [APUAPC] D8_APC_0: 0xffffffff
9968 04:41:07.204427 INFO: [APUAPC] D8_APC_1: 0xffffffff
9969 04:41:07.207435 INFO: [APUAPC] D8_APC_2: 0x3fffff
9970 04:41:07.207886 INFO: [APUAPC] D8_APC_3: 0x0
9971 04:41:07.211037 INFO: [APUAPC] D9_APC_0: 0xffffffff
9972 04:41:07.217797 INFO: [APUAPC] D9_APC_1: 0xffffffff
9973 04:41:07.218238 INFO: [APUAPC] D9_APC_2: 0x3fffff
9974 04:41:07.221217 INFO: [APUAPC] D9_APC_3: 0x0
9975 04:41:07.224000 INFO: [APUAPC] D10_APC_0: 0xffffffff
9976 04:41:07.227227 INFO: [APUAPC] D10_APC_1: 0xffffffff
9977 04:41:07.230597 INFO: [APUAPC] D10_APC_2: 0x3fffff
9978 04:41:07.233913 INFO: [APUAPC] D10_APC_3: 0x0
9979 04:41:07.237207 INFO: [APUAPC] D11_APC_0: 0xffffffff
9980 04:41:07.240661 INFO: [APUAPC] D11_APC_1: 0xffffffff
9981 04:41:07.243770 INFO: [APUAPC] D11_APC_2: 0x3fffff
9982 04:41:07.247315 INFO: [APUAPC] D11_APC_3: 0x0
9983 04:41:07.250654 INFO: [APUAPC] D12_APC_0: 0xffffffff
9984 04:41:07.253894 INFO: [APUAPC] D12_APC_1: 0xffffffff
9985 04:41:07.260958 INFO: [APUAPC] D12_APC_2: 0x3fffff
9986 04:41:07.261458 INFO: [APUAPC] D12_APC_3: 0x0
9987 04:41:07.263953 INFO: [APUAPC] D13_APC_0: 0xffffffff
9988 04:41:07.270274 INFO: [APUAPC] D13_APC_1: 0xffffffff
9989 04:41:07.270424 INFO: [APUAPC] D13_APC_2: 0x3fffff
9990 04:41:07.273958 INFO: [APUAPC] D13_APC_3: 0x0
9991 04:41:07.276944 INFO: [APUAPC] D14_APC_0: 0xffffffff
9992 04:41:07.280326 INFO: [APUAPC] D14_APC_1: 0xffffffff
9993 04:41:07.283940 INFO: [APUAPC] D14_APC_2: 0x3fffff
9994 04:41:07.287085 INFO: [APUAPC] D14_APC_3: 0x0
9995 04:41:07.290486 INFO: [APUAPC] D15_APC_0: 0xffffffff
9996 04:41:07.293516 INFO: [APUAPC] D15_APC_1: 0xffffffff
9997 04:41:07.297368 INFO: [APUAPC] D15_APC_2: 0x3fffff
9998 04:41:07.300552 INFO: [APUAPC] D15_APC_3: 0x0
9999 04:41:07.303977 INFO: [APUAPC] APC_CON: 0x4
10000 04:41:07.306945 INFO: [NOCDAPC] D0_APC_0: 0x0
10001 04:41:07.310604 INFO: [NOCDAPC] D0_APC_1: 0x0
10002 04:41:07.314123 INFO: [NOCDAPC] D1_APC_0: 0x0
10003 04:41:07.317055 INFO: [NOCDAPC] D1_APC_1: 0xfff
10004 04:41:07.320265 INFO: [NOCDAPC] D2_APC_0: 0x0
10005 04:41:07.323699 INFO: [NOCDAPC] D2_APC_1: 0xfff
10006 04:41:07.323853 INFO: [NOCDAPC] D3_APC_0: 0x0
10007 04:41:07.327304 INFO: [NOCDAPC] D3_APC_1: 0xfff
10008 04:41:07.330803 INFO: [NOCDAPC] D4_APC_0: 0x0
10009 04:41:07.333779 INFO: [NOCDAPC] D4_APC_1: 0xfff
10010 04:41:07.336828 INFO: [NOCDAPC] D5_APC_0: 0x0
10011 04:41:07.340037 INFO: [NOCDAPC] D5_APC_1: 0xfff
10012 04:41:07.343809 INFO: [NOCDAPC] D6_APC_0: 0x0
10013 04:41:07.346823 INFO: [NOCDAPC] D6_APC_1: 0xfff
10014 04:41:07.350374 INFO: [NOCDAPC] D7_APC_0: 0x0
10015 04:41:07.353994 INFO: [NOCDAPC] D7_APC_1: 0xfff
10016 04:41:07.357039 INFO: [NOCDAPC] D8_APC_0: 0x0
10017 04:41:07.360826 INFO: [NOCDAPC] D8_APC_1: 0xfff
10018 04:41:07.361213 INFO: [NOCDAPC] D9_APC_0: 0x0
10019 04:41:07.363885 INFO: [NOCDAPC] D9_APC_1: 0xfff
10020 04:41:07.366971 INFO: [NOCDAPC] D10_APC_0: 0x0
10021 04:41:07.370729 INFO: [NOCDAPC] D10_APC_1: 0xfff
10022 04:41:07.373898 INFO: [NOCDAPC] D11_APC_0: 0x0
10023 04:41:07.377266 INFO: [NOCDAPC] D11_APC_1: 0xfff
10024 04:41:07.380608 INFO: [NOCDAPC] D12_APC_0: 0x0
10025 04:41:07.383559 INFO: [NOCDAPC] D12_APC_1: 0xfff
10026 04:41:07.386862 INFO: [NOCDAPC] D13_APC_0: 0x0
10027 04:41:07.390412 INFO: [NOCDAPC] D13_APC_1: 0xfff
10028 04:41:07.393739 INFO: [NOCDAPC] D14_APC_0: 0x0
10029 04:41:07.397155 INFO: [NOCDAPC] D14_APC_1: 0xfff
10030 04:41:07.400618 INFO: [NOCDAPC] D15_APC_0: 0x0
10031 04:41:07.403543 INFO: [NOCDAPC] D15_APC_1: 0xfff
10032 04:41:07.404057 INFO: [NOCDAPC] APC_CON: 0x4
10033 04:41:07.407130 INFO: [APUAPC] set_apusys_apc done
10034 04:41:07.410465 INFO: [DEVAPC] devapc_init done
10035 04:41:07.416927 INFO: GICv3 without legacy support detected.
10036 04:41:07.420549 INFO: ARM GICv3 driver initialized in EL3
10037 04:41:07.423751 INFO: Maximum SPI INTID supported: 639
10038 04:41:07.427234 INFO: BL31: Initializing runtime services
10039 04:41:07.433455 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10040 04:41:07.437015 INFO: SPM: enable CPC mode
10041 04:41:07.440607 INFO: mcdi ready for mcusys-off-idle and system suspend
10042 04:41:07.447080 INFO: BL31: Preparing for EL3 exit to normal world
10043 04:41:07.450074 INFO: Entry point address = 0x80000000
10044 04:41:07.450606 INFO: SPSR = 0x8
10045 04:41:07.457102
10046 04:41:07.457598
10047 04:41:07.457910
10048 04:41:07.460551 Starting depthcharge on Spherion...
10049 04:41:07.461215
10050 04:41:07.461768 Wipe memory regions:
10051 04:41:07.462300
10052 04:41:07.464440 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10053 04:41:07.465033 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10054 04:41:07.465481 Setting prompt string to ['asurada:']
10055 04:41:07.465864 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10056 04:41:07.466490 [0x00000040000000, 0x00000054600000)
10057 04:41:07.585868
10058 04:41:07.586480 [0x00000054660000, 0x00000080000000)
10059 04:41:07.846204
10060 04:41:07.846684 [0x000000821a7280, 0x000000ffe64000)
10061 04:41:08.589362
10062 04:41:08.589856 [0x00000100000000, 0x00000240000000)
10063 04:41:10.475855
10064 04:41:10.478633 Initializing XHCI USB controller at 0x11200000.
10065 04:41:11.516805
10066 04:41:11.519635 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10067 04:41:11.519758
10068 04:41:11.519850
10069 04:41:11.519937
10070 04:41:11.520259 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 04:41:11.620613 asurada: tftpboot 192.168.201.1 11241319/tftp-deploy-bswagsfv/kernel/image.itb 11241319/tftp-deploy-bswagsfv/kernel/cmdline
10073 04:41:11.620786 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 04:41:11.620880 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10075 04:41:11.624910 tftpboot 192.168.201.1 11241319/tftp-deploy-bswagsfv/kernel/image.ittp-deploy-bswagsfv/kernel/cmdline
10076 04:41:11.625020
10077 04:41:11.625113 Waiting for link
10078 04:41:11.785639
10079 04:41:11.785795 R8152: Initializing
10080 04:41:11.785864
10081 04:41:11.789052 Version 6 (ocp_data = 5c30)
10082 04:41:11.789135
10083 04:41:11.792018 R8152: Done initializing
10084 04:41:11.792099
10085 04:41:11.792163 Adding net device
10086 04:41:13.648216
10087 04:41:13.648373 done.
10088 04:41:13.648443
10089 04:41:13.648535 MAC: 00:24:32:30:78:52
10090 04:41:13.648594
10091 04:41:13.651678 Sending DHCP discover... done.
10092 04:41:13.651761
10093 04:41:17.070340 Waiting for reply... done.
10094 04:41:17.070897
10095 04:41:17.071269 Sending DHCP request... done.
10096 04:41:17.073624
10097 04:41:17.074268 Waiting for reply... done.
10098 04:41:17.076587
10099 04:41:17.077338 My ip is 192.168.201.14
10100 04:41:17.077902
10101 04:41:17.079995 The DHCP server ip is 192.168.201.1
10102 04:41:17.080526
10103 04:41:17.083484 TFTP server IP predefined by user: 192.168.201.1
10104 04:41:17.084012
10105 04:41:17.090222 Bootfile predefined by user: 11241319/tftp-deploy-bswagsfv/kernel/image.itb
10106 04:41:17.090652
10107 04:41:17.093430 Sending tftp read request... done.
10108 04:41:17.093856
10109 04:41:17.102650 Waiting for the transfer...
10110 04:41:17.103219
10111 04:41:17.657671 00000000 ################################################################
10112 04:41:17.657805
10113 04:41:18.259961 00080000 ################################################################
10114 04:41:18.260152
10115 04:41:18.825088 00100000 ################################################################
10116 04:41:18.825255
10117 04:41:19.398589 00180000 ################################################################
10118 04:41:19.398728
10119 04:41:19.960585 00200000 ################################################################
10120 04:41:19.960779
10121 04:41:20.563584 00280000 ################################################################
10122 04:41:20.563747
10123 04:41:21.126911 00300000 ################################################################
10124 04:41:21.127066
10125 04:41:21.697411 00380000 ################################################################
10126 04:41:21.697551
10127 04:41:22.277030 00400000 ################################################################
10128 04:41:22.277181
10129 04:41:22.838182 00480000 ################################################################
10130 04:41:22.838326
10131 04:41:23.401833 00500000 ################################################################
10132 04:41:23.401971
10133 04:41:23.972554 00580000 ################################################################
10134 04:41:23.973038
10135 04:41:24.595712 00600000 ################################################################
10136 04:41:24.595886
10137 04:41:25.164038 00680000 ################################################################
10138 04:41:25.164214
10139 04:41:25.750509 00700000 ################################################################
10140 04:41:25.750648
10141 04:41:26.323608 00780000 ################################################################
10142 04:41:26.323770
10143 04:41:26.908649 00800000 ################################################################
10144 04:41:26.908832
10145 04:41:27.465700 00880000 ################################################################
10146 04:41:27.465843
10147 04:41:28.027744 00900000 ################################################################
10148 04:41:28.027883
10149 04:41:28.603173 00980000 ################################################################
10150 04:41:28.603755
10151 04:41:29.183607 00a00000 ################################################################
10152 04:41:29.183744
10153 04:41:29.756123 00a80000 ################################################################
10154 04:41:29.756257
10155 04:41:30.359792 00b00000 ################################################################
10156 04:41:30.360393
10157 04:41:30.964942 00b80000 ################################################################
10158 04:41:30.965139
10159 04:41:31.518400 00c00000 ################################################################
10160 04:41:31.518537
10161 04:41:32.087543 00c80000 ################################################################
10162 04:41:32.087729
10163 04:41:32.713761 00d00000 ################################################################
10164 04:41:32.714488
10165 04:41:33.384946 00d80000 ################################################################
10166 04:41:33.385502
10167 04:41:34.015034 00e00000 ################################################################
10168 04:41:34.015187
10169 04:41:34.564089 00e80000 ################################################################
10170 04:41:34.564239
10171 04:41:35.154590 00f00000 ################################################################
10172 04:41:35.154744
10173 04:41:35.775118 00f80000 ################################################################
10174 04:41:35.775639
10175 04:41:36.333744 01000000 ################################################################
10176 04:41:36.333924
10177 04:41:36.912025 01080000 ################################################################
10178 04:41:36.912186
10179 04:41:37.475456 01100000 ################################################################
10180 04:41:37.475638
10181 04:41:38.024170 01180000 ################################################################
10182 04:41:38.024903
10183 04:41:38.675837 01200000 ################################################################
10184 04:41:38.675990
10185 04:41:39.228313 01280000 ################################################################
10186 04:41:39.228468
10187 04:41:39.789752 01300000 ################################################################
10188 04:41:39.790271
10189 04:41:40.430283 01380000 ################################################################
10190 04:41:40.430865
10191 04:41:41.084275 01400000 ################################################################
10192 04:41:41.084836
10193 04:41:41.686509 01480000 ################################################################
10194 04:41:41.686702
10195 04:41:42.339699 01500000 ################################################################
10196 04:41:42.340204
10197 04:41:42.971761 01580000 ################################################################
10198 04:41:42.971897
10199 04:41:43.635412 01600000 ################################################################
10200 04:41:43.635579
10201 04:41:44.276293 01680000 ################################################################
10202 04:41:44.276970
10203 04:41:44.919696 01700000 ################################################################
10204 04:41:44.920243
10205 04:41:45.575476 01780000 ################################################################
10206 04:41:45.576146
10207 04:41:46.223438 01800000 ################################################################
10208 04:41:46.223627
10209 04:41:46.863770 01880000 ################################################################
10210 04:41:46.863920
10211 04:41:47.461380 01900000 ################################################################
10212 04:41:47.461634
10213 04:41:48.115557 01980000 ################################################################
10214 04:41:48.115734
10215 04:41:48.708850 01a00000 ################################################################
10216 04:41:48.709078
10217 04:41:49.291793 01a80000 ################################################################
10218 04:41:49.291936
10219 04:41:49.939557 01b00000 ################################################################
10220 04:41:49.940272
10221 04:41:50.560075 01b80000 ################################################################
10222 04:41:50.560719
10223 04:41:51.181767 01c00000 ################################################################
10224 04:41:51.182012
10225 04:41:51.750052 01c80000 ################################################################
10226 04:41:51.750225
10227 04:41:52.390634 01d00000 ################################################################
10228 04:41:52.390787
10229 04:41:52.955702 01d80000 ################################################################
10230 04:41:52.955846
10231 04:41:53.598764 01e00000 ################################################################
10232 04:41:53.599485
10233 04:41:54.229599 01e80000 ################################################################
10234 04:41:54.230326
10235 04:41:54.869592 01f00000 ################################################################
10236 04:41:54.869783
10237 04:41:55.460062 01f80000 ################################################################
10238 04:41:55.460249
10239 04:41:56.068379 02000000 ################################################################
10240 04:41:56.068554
10241 04:41:56.702702 02080000 ################################################################
10242 04:41:56.703246
10243 04:41:57.344103 02100000 ################################################################
10244 04:41:57.344263
10245 04:41:57.939398 02180000 ################################################################
10246 04:41:57.940063
10247 04:41:58.511179 02200000 ################################################################
10248 04:41:58.511353
10249 04:41:59.140276 02280000 ################################################################
10250 04:41:59.140445
10251 04:41:59.759301 02300000 ################################################################
10252 04:41:59.759457
10253 04:42:00.350560 02380000 ################################################################
10254 04:42:00.350710
10255 04:42:00.949258 02400000 ################################################################
10256 04:42:00.949777
10257 04:42:01.561015 02480000 ################################################################
10258 04:42:01.561528
10259 04:42:02.162672 02500000 ################################################################
10260 04:42:02.162823
10261 04:42:02.768352 02580000 ################################################################
10262 04:42:02.769023
10263 04:42:03.401745 02600000 ################################################################
10264 04:42:03.401917
10265 04:42:04.000215 02680000 ################################################################
10266 04:42:04.000393
10267 04:42:04.580823 02700000 ################################################################
10268 04:42:04.581354
10269 04:42:05.236350 02780000 ################################################################
10270 04:42:05.237184
10271 04:42:05.839622 02800000 ################################################################
10272 04:42:05.839804
10273 04:42:06.450782 02880000 ################################################################
10274 04:42:06.451487
10275 04:42:07.101032 02900000 ################################################################
10276 04:42:07.101228
10277 04:42:07.690459 02980000 ################################################################
10278 04:42:07.690616
10279 04:42:08.307387 02a00000 ################################################################
10280 04:42:08.307561
10281 04:42:08.943573 02a80000 ################################################################
10282 04:42:08.943747
10283 04:42:09.535789 02b00000 ################################################################
10284 04:42:09.536535
10285 04:42:10.159541 02b80000 ################################################################
10286 04:42:10.159712
10287 04:42:10.744070 02c00000 ################################################################
10288 04:42:10.744215
10289 04:42:11.334617 02c80000 ################################################################
10290 04:42:11.334765
10291 04:42:11.927602 02d00000 ################################################################
10292 04:42:11.927755
10293 04:42:12.518498 02d80000 ################################################################
10294 04:42:12.518673
10295 04:42:13.139932 02e00000 ################################################################
10296 04:42:13.140596
10297 04:42:13.806846 02e80000 ################################################################
10298 04:42:13.806995
10299 04:42:14.428560 02f00000 ################################################################
10300 04:42:14.428743
10301 04:42:15.009985 02f80000 ################################################################
10302 04:42:15.010152
10303 04:42:15.607944 03000000 ################################################################
10304 04:42:15.608099
10305 04:42:16.186700 03080000 ################################################################
10306 04:42:16.186848
10307 04:42:16.770813 03100000 ################################################################
10308 04:42:16.770968
10309 04:42:17.340073 03180000 ################################################################
10310 04:42:17.340597
10311 04:42:17.946891 03200000 ################################################################
10312 04:42:17.947065
10313 04:42:18.588771 03280000 ################################################################
10314 04:42:18.589349
10315 04:42:19.187151 03300000 ################################################################
10316 04:42:19.187328
10317 04:42:19.807220 03380000 ################################################################
10318 04:42:19.807363
10319 04:42:20.402011 03400000 ################################################################
10320 04:42:20.402617
10321 04:42:21.038497 03480000 ################################################################
10322 04:42:21.038642
10323 04:42:21.640925 03500000 ################################################################
10324 04:42:21.641074
10325 04:42:22.206339 03580000 ################################################################
10326 04:42:22.206486
10327 04:42:22.738522 03600000 ################################################################
10328 04:42:22.738738
10329 04:42:23.299096 03680000 ################################################################
10330 04:42:23.299264
10331 04:42:23.850762 03700000 ################################################################
10332 04:42:23.850910
10333 04:42:24.384256 03780000 ################################################################
10334 04:42:24.384404
10335 04:42:24.925603 03800000 ################################################################
10336 04:42:24.925745
10337 04:42:25.502286 03880000 ################################################################
10338 04:42:25.502467
10339 04:42:26.045691 03900000 ################################################################
10340 04:42:26.045880
10341 04:42:26.578755 03980000 ################################################################
10342 04:42:26.578935
10343 04:42:27.105583 03a00000 ################################################################
10344 04:42:27.105734
10345 04:42:27.633076 03a80000 ################################################################
10346 04:42:27.633233
10347 04:42:28.167563 03b00000 ################################################################
10348 04:42:28.167765
10349 04:42:28.692123 03b80000 ################################################################
10350 04:42:28.692275
10351 04:42:29.252141 03c00000 ################################################################
10352 04:42:29.252318
10353 04:42:29.814692 03c80000 ################################################################
10354 04:42:29.814849
10355 04:42:30.347738 03d00000 ################################################################
10356 04:42:30.347960
10357 04:42:30.888176 03d80000 ################################################################
10358 04:42:30.888351
10359 04:42:31.447819 03e00000 ################################################################
10360 04:42:31.447971
10361 04:42:32.001285 03e80000 ################################################################
10362 04:42:32.001438
10363 04:42:32.536871 03f00000 ################################################################
10364 04:42:32.537018
10365 04:42:33.093001 03f80000 ################################################################
10366 04:42:33.093224
10367 04:42:33.641180 04000000 ################################################################
10368 04:42:33.641376
10369 04:42:34.192945 04080000 ################################################################
10370 04:42:34.193101
10371 04:42:34.764476 04100000 ################################################################
10372 04:42:34.764661
10373 04:42:35.346130 04180000 ################################################################
10374 04:42:35.346289
10375 04:42:35.894869 04200000 ################################################################
10376 04:42:35.895031
10377 04:42:36.450031 04280000 ################################################################
10378 04:42:36.450251
10379 04:42:37.002740 04300000 ################################################################
10380 04:42:37.002941
10381 04:42:37.561101 04380000 ################################################################
10382 04:42:37.561311
10383 04:42:38.104650 04400000 ################################################################
10384 04:42:38.104882
10385 04:42:38.663041 04480000 ################################################################
10386 04:42:38.663202
10387 04:42:39.262595 04500000 ################################################################
10388 04:42:39.262751
10389 04:42:39.804954 04580000 ################################################################
10390 04:42:39.805107
10391 04:42:40.360043 04600000 ################################################################
10392 04:42:40.360263
10393 04:42:40.903493 04680000 ################################################################
10394 04:42:40.903687
10395 04:42:41.492276 04700000 ################################################################
10396 04:42:41.492476
10397 04:42:42.094777 04780000 ################################################################
10398 04:42:42.094938
10399 04:42:42.687030 04800000 ################################################################
10400 04:42:42.687188
10401 04:42:43.306003 04880000 ################################################################
10402 04:42:43.306614
10403 04:42:43.888686 04900000 ################################################################
10404 04:42:43.888865
10405 04:42:44.514439 04980000 ################################################################
10406 04:42:44.515118
10407 04:42:45.186285 04a00000 ################################################################
10408 04:42:45.186849
10409 04:42:45.829481 04a80000 ################################################################
10410 04:42:45.829664
10411 04:42:46.402446 04b00000 ################################################################
10412 04:42:46.402578
10413 04:42:46.972969 04b80000 ################################################################
10414 04:42:46.973106
10415 04:42:47.583583 04c00000 ################################################################
10416 04:42:47.584189
10417 04:42:48.229839 04c80000 ################################################################
10418 04:42:48.230358
10419 04:42:48.834536 04d00000 ################################################################
10420 04:42:48.834669
10421 04:42:49.404342 04d80000 ################################################################
10422 04:42:49.404484
10423 04:42:50.038290 04e00000 ################################################################
10424 04:42:50.038968
10425 04:42:50.590048 04e80000 ################################################################
10426 04:42:50.590192
10427 04:42:51.119989 04f00000 ################################################################
10428 04:42:51.120132
10429 04:42:51.640313 04f80000 ################################################################
10430 04:42:51.640460
10431 04:42:52.161044 05000000 ################################################################
10432 04:42:52.161195
10433 04:42:52.732293 05080000 ################################################################
10434 04:42:52.732443
10435 04:42:53.263342 05100000 ################################################################
10436 04:42:53.263469
10437 04:42:53.801416 05180000 ################################################################
10438 04:42:53.801573
10439 04:42:54.370683 05200000 ################################################################
10440 04:42:54.370821
10441 04:42:54.885139 05280000 ################################################################
10442 04:42:54.885298
10443 04:42:55.405268 05300000 ################################################################
10444 04:42:55.405460
10445 04:42:55.921687 05380000 ################################################################
10446 04:42:55.921838
10447 04:42:56.439815 05400000 ################################################################
10448 04:42:56.439959
10449 04:42:56.956738 05480000 ################################################################
10450 04:42:56.956912
10451 04:42:57.526300 05500000 ################################################################
10452 04:42:57.526481
10453 04:42:58.070649 05580000 ################################################################
10454 04:42:58.070788
10455 04:42:58.671601 05600000 ################################################################
10456 04:42:58.671735
10457 04:42:59.310974 05680000 ################################################################
10458 04:42:59.311110
10459 04:42:59.935117 05700000 ################################################################
10460 04:42:59.935663
10461 04:43:00.599868 05780000 ################################################################
10462 04:43:00.600459
10463 04:43:01.234964 05800000 ################################################################
10464 04:43:01.235167
10465 04:43:01.762172 05880000 ################################################################
10466 04:43:01.762306
10467 04:43:02.296082 05900000 ################################################################
10468 04:43:02.296245
10469 04:43:02.831339 05980000 ################################################################
10470 04:43:02.831474
10471 04:43:03.384137 05a00000 ################################################################
10472 04:43:03.384273
10473 04:43:03.920239 05a80000 ################################################################
10474 04:43:03.920378
10475 04:43:04.461150 05b00000 ################################################################
10476 04:43:04.461289
10477 04:43:05.037825 05b80000 ################################################################
10478 04:43:05.037970
10479 04:43:05.586004 05c00000 ################################################################
10480 04:43:05.586235
10481 04:43:06.131272 05c80000 ################################################################
10482 04:43:06.131414
10483 04:43:06.663467 05d00000 ################################################################
10484 04:43:06.663613
10485 04:43:07.184973 05d80000 ################################################################
10486 04:43:07.185172
10487 04:43:07.711865 05e00000 ################################################################
10488 04:43:07.712040
10489 04:43:08.263099 05e80000 ################################################################
10490 04:43:08.263289
10491 04:43:08.825247 05f00000 ################################################################
10492 04:43:08.825405
10493 04:43:09.393610 05f80000 ################################################################
10494 04:43:09.393761
10495 04:43:09.974916 06000000 ################################################################
10496 04:43:09.975099
10497 04:43:10.544560 06080000 ################################################################
10498 04:43:10.544765
10499 04:43:11.098111 06100000 ################################################################
10500 04:43:11.098272
10501 04:43:11.640720 06180000 ################################################################
10502 04:43:11.640867
10503 04:43:12.199212 06200000 ################################################################
10504 04:43:12.199392
10505 04:43:12.738571 06280000 ################################################################
10506 04:43:12.738710
10507 04:43:13.291292 06300000 ################################################################
10508 04:43:13.291430
10509 04:43:13.855934 06380000 ################################################################
10510 04:43:13.856078
10511 04:43:14.477615 06400000 ################################################################
10512 04:43:14.477775
10513 04:43:15.072049 06480000 ################################################################
10514 04:43:15.072778
10515 04:43:15.707319 06500000 ################################################################
10516 04:43:15.707827
10517 04:43:16.342695 06580000 ################################################################
10518 04:43:16.342873
10519 04:43:16.932340 06600000 ################################################################
10520 04:43:16.932494
10521 04:43:17.515311 06680000 ################################################################
10522 04:43:17.516007
10523 04:43:18.148396 06700000 ################################################################
10524 04:43:18.148546
10525 04:43:18.730337 06780000 ################################################################
10526 04:43:18.730487
10527 04:43:18.989448 06800000 ############################## done.
10528 04:43:18.989594
10529 04:43:18.993084 The bootfile was 109292190 bytes long.
10530 04:43:18.996444
10531 04:43:18.996534 Sending tftp read request... done.
10532 04:43:18.996600
10533 04:43:19.000086 Waiting for the transfer...
10534 04:43:19.000171
10535 04:43:19.003078 00000000 # done.
10536 04:43:19.003163
10537 04:43:19.009517 Command line loaded dynamically from TFTP file: 11241319/tftp-deploy-bswagsfv/kernel/cmdline
10538 04:43:19.009618
10539 04:43:19.023144 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10540 04:43:19.023247
10541 04:43:19.023315 Loading FIT.
10542 04:43:19.026681
10543 04:43:19.026765 Image ramdisk-1 has 98206511 bytes.
10544 04:43:19.026832
10545 04:43:19.029694 Image fdt-1 has 47278 bytes.
10546 04:43:19.029779
10547 04:43:19.033212 Image kernel-1 has 11036366 bytes.
10548 04:43:19.033296
10549 04:43:19.042792 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10550 04:43:19.042882
10551 04:43:19.059781 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10552 04:43:19.059884
10553 04:43:19.066915 Choosing best match conf-1 for compat google,spherion-rev2.
10554 04:43:19.067001
10555 04:43:19.073962 Connected to device vid:did:rid of 1ae0:0028:00
10556 04:43:19.082462
10557 04:43:19.085909 tpm_get_response: command 0x17b, return code 0x0
10558 04:43:19.085995
10559 04:43:19.088835 ec_init: CrosEC protocol v3 supported (256, 248)
10560 04:43:19.093086
10561 04:43:19.096659 tpm_cleanup: add release locality here.
10562 04:43:19.096772
10563 04:43:19.096838 Shutting down all USB controllers.
10564 04:43:19.099353
10565 04:43:19.099437 Removing current net device
10566 04:43:19.099502
10567 04:43:19.106251 Exiting depthcharge with code 4 at timestamp: 161049873
10568 04:43:19.106338
10569 04:43:19.109691 LZMA decompressing kernel-1 to 0x821a6718
10570 04:43:19.109793
10571 04:43:19.113108 LZMA decompressing kernel-1 to 0x40000000
10572 04:43:20.501333
10573 04:43:20.501475 jumping to kernel
10574 04:43:20.501958 end: 2.2.4 bootloader-commands (duration 00:02:13) [common]
10575 04:43:20.502060 start: 2.2.5 auto-login-action (timeout 00:02:12) [common]
10576 04:43:20.502140 Setting prompt string to ['Linux version [0-9]']
10577 04:43:20.502213 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10578 04:43:20.502286 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10579 04:43:20.583712
10580 04:43:20.587185 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10581 04:43:20.590893 start: 2.2.5.1 login-action (timeout 00:02:12) [common]
10582 04:43:20.591010 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10583 04:43:20.591101 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10584 04:43:20.591177 Using line separator: #'\n'#
10585 04:43:20.591238 No login prompt set.
10586 04:43:20.591301 Parsing kernel messages
10587 04:43:20.591357 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10588 04:43:20.591488 [login-action] Waiting for messages, (timeout 00:02:12)
10589 04:43:20.610275 [ 0.000000] Linux version 6.1.42-cip2 (KernelCI@build-j7071-arm64-gcc-10-defconfig-arm64-chromebook-7p24g) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 9 04:18:34 UTC 2023
10590 04:43:20.613651 [ 0.000000] random: crng init done
10591 04:43:20.620551 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10592 04:43:20.620686 [ 0.000000] efi: UEFI not found.
10593 04:43:20.630496 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10594 04:43:20.636982 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10595 04:43:20.647136 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10596 04:43:20.657288 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10597 04:43:20.663743 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10598 04:43:20.666676 [ 0.000000] printk: bootconsole [mtk8250] enabled
10599 04:43:20.675605 [ 0.000000] NUMA: No NUMA configuration found
10600 04:43:20.682024 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10601 04:43:20.688584 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10602 04:43:20.688824 [ 0.000000] Zone ranges:
10603 04:43:20.695636 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10604 04:43:20.698794 [ 0.000000] DMA32 empty
10605 04:43:20.705548 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10606 04:43:20.708781 [ 0.000000] Movable zone start for each node
10607 04:43:20.711956 [ 0.000000] Early memory node ranges
10608 04:43:20.718767 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10609 04:43:20.725125 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10610 04:43:20.731886 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10611 04:43:20.738377 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10612 04:43:20.745373 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10613 04:43:20.751929 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10614 04:43:20.807857 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10615 04:43:20.814228 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10616 04:43:20.821276 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10617 04:43:20.824821 [ 0.000000] psci: probing for conduit method from DT.
10618 04:43:20.831214 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10619 04:43:20.834233 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10620 04:43:20.841308 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10621 04:43:20.844646 [ 0.000000] psci: SMC Calling Convention v1.2
10622 04:43:20.850872 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10623 04:43:20.854620 [ 0.000000] Detected VIPT I-cache on CPU0
10624 04:43:20.860863 [ 0.000000] CPU features: detected: GIC system register CPU interface
10625 04:43:20.867527 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10626 04:43:20.874771 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10627 04:43:20.880898 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10628 04:43:20.887875 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10629 04:43:20.894627 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10630 04:43:20.901302 [ 0.000000] alternatives: applying boot alternatives
10631 04:43:20.904158 [ 0.000000] Fallback order for Node 0: 0
10632 04:43:20.911270 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10633 04:43:20.914719 [ 0.000000] Policy zone: Normal
10634 04:43:20.931348 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10635 04:43:20.940800 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10636 04:43:20.952411 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10637 04:43:20.962559 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10638 04:43:20.969321 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10639 04:43:20.972305 <6>[ 0.000000] software IO TLB: area num 8.
10640 04:43:21.028158 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10641 04:43:21.177540 <6>[ 0.000000] Memory: 7873652K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 479116K reserved, 32768K cma-reserved)
10642 04:43:21.184284 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10643 04:43:21.191230 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10644 04:43:21.194416 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10645 04:43:21.200683 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10646 04:43:21.207471 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10647 04:43:21.211029 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10648 04:43:21.221017 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10649 04:43:21.227680 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10650 04:43:21.230737 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10651 04:43:21.238253 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10652 04:43:21.241620 <6>[ 0.000000] GICv3: 608 SPIs implemented
10653 04:43:21.248496 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10654 04:43:21.251762 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10655 04:43:21.255160 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10656 04:43:21.265138 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10657 04:43:21.275162 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10658 04:43:21.288336 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10659 04:43:21.294715 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10660 04:43:21.303789 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10661 04:43:21.317553 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10662 04:43:21.323579 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10663 04:43:21.330730 <6>[ 0.009183] Console: colour dummy device 80x25
10664 04:43:21.341138 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10665 04:43:21.343923 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10666 04:43:21.350458 <6>[ 0.029225] LSM: Security Framework initializing
10667 04:43:21.357454 <6>[ 0.034165] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10668 04:43:21.367429 <6>[ 0.041978] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10669 04:43:21.373672 <6>[ 0.051468] cblist_init_generic: Setting adjustable number of callback queues.
10670 04:43:21.381020 <6>[ 0.058914] cblist_init_generic: Setting shift to 3 and lim to 1.
10671 04:43:21.390983 <6>[ 0.065251] cblist_init_generic: Setting adjustable number of callback queues.
10672 04:43:21.394222 <6>[ 0.072723] cblist_init_generic: Setting shift to 3 and lim to 1.
10673 04:43:21.400264 <6>[ 0.079123] rcu: Hierarchical SRCU implementation.
10674 04:43:21.407160 <6>[ 0.084138] rcu: Max phase no-delay instances is 1000.
10675 04:43:21.413833 <6>[ 0.091177] EFI services will not be available.
10676 04:43:21.416960 <6>[ 0.096149] smp: Bringing up secondary CPUs ...
10677 04:43:21.424865 <6>[ 0.101227] Detected VIPT I-cache on CPU1
10678 04:43:21.431606 <6>[ 0.101298] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10679 04:43:21.438381 <6>[ 0.101327] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10680 04:43:21.442259 <6>[ 0.101664] Detected VIPT I-cache on CPU2
10681 04:43:21.448338 <6>[ 0.101719] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10682 04:43:21.454836 <6>[ 0.101736] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10683 04:43:21.461654 <6>[ 0.101992] Detected VIPT I-cache on CPU3
10684 04:43:21.468579 <6>[ 0.102039] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10685 04:43:21.475340 <6>[ 0.102053] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10686 04:43:21.478744 <6>[ 0.102356] CPU features: detected: Spectre-v4
10687 04:43:21.485089 <6>[ 0.102363] CPU features: detected: Spectre-BHB
10688 04:43:21.488797 <6>[ 0.102369] Detected PIPT I-cache on CPU4
10689 04:43:21.495356 <6>[ 0.102426] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10690 04:43:21.501975 <6>[ 0.102442] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10691 04:43:21.505015 <6>[ 0.102732] Detected PIPT I-cache on CPU5
10692 04:43:21.515001 <6>[ 0.102796] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10693 04:43:21.521926 <6>[ 0.102813] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10694 04:43:21.524874 <6>[ 0.103093] Detected PIPT I-cache on CPU6
10695 04:43:21.531532 <6>[ 0.103158] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10696 04:43:21.538255 <6>[ 0.103174] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10697 04:43:21.541643 <6>[ 0.103470] Detected PIPT I-cache on CPU7
10698 04:43:21.551856 <6>[ 0.103536] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10699 04:43:21.558311 <6>[ 0.103552] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10700 04:43:21.561188 <6>[ 0.103599] smp: Brought up 1 node, 8 CPUs
10701 04:43:21.564776 <6>[ 0.244779] SMP: Total of 8 processors activated.
10702 04:43:21.571810 <6>[ 0.249700] CPU features: detected: 32-bit EL0 Support
10703 04:43:21.581360 <6>[ 0.255095] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10704 04:43:21.587797 <6>[ 0.263895] CPU features: detected: Common not Private translations
10705 04:43:21.591083 <6>[ 0.270371] CPU features: detected: CRC32 instructions
10706 04:43:21.598069 <6>[ 0.275722] CPU features: detected: RCpc load-acquire (LDAPR)
10707 04:43:21.604522 <6>[ 0.281682] CPU features: detected: LSE atomic instructions
10708 04:43:21.611432 <6>[ 0.287464] CPU features: detected: Privileged Access Never
10709 04:43:21.614404 <6>[ 0.293243] CPU features: detected: RAS Extension Support
10710 04:43:21.621351 <6>[ 0.298887] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10711 04:43:21.627894 <6>[ 0.306101] CPU: All CPU(s) started at EL2
10712 04:43:21.631312 <6>[ 0.310444] alternatives: applying system-wide alternatives
10713 04:43:21.642739 <6>[ 0.321172] devtmpfs: initialized
10714 04:43:21.654782 <6>[ 0.330090] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10715 04:43:21.664989 <6>[ 0.340055] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10716 04:43:21.671388 <6>[ 0.348069] pinctrl core: initialized pinctrl subsystem
10717 04:43:21.674502 <6>[ 0.354942] DMI not present or invalid.
10718 04:43:21.681149 <6>[ 0.359352] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10719 04:43:21.691328 <6>[ 0.366221] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10720 04:43:21.698192 <6>[ 0.373807] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10721 04:43:21.708044 <6>[ 0.382018] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10722 04:43:21.711179 <6>[ 0.390258] audit: initializing netlink subsys (disabled)
10723 04:43:21.721491 <5>[ 0.395948] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10724 04:43:21.727558 <6>[ 0.396715] thermal_sys: Registered thermal governor 'step_wise'
10725 04:43:21.734729 <6>[ 0.403911] thermal_sys: Registered thermal governor 'power_allocator'
10726 04:43:21.737634 <6>[ 0.410168] cpuidle: using governor menu
10727 04:43:21.741256 <6>[ 0.421129] NET: Registered PF_QIPCRTR protocol family
10728 04:43:21.751281 <6>[ 0.426609] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10729 04:43:21.754267 <6>[ 0.433716] ASID allocator initialised with 32768 entries
10730 04:43:21.761265 <6>[ 0.440367] Serial: AMBA PL011 UART driver
10731 04:43:21.770823 <4>[ 0.449455] Trying to register duplicate clock ID: 134
10732 04:43:21.827603 <6>[ 0.509825] KASLR enabled
10733 04:43:21.842129 <6>[ 0.517597] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10734 04:43:21.848517 <6>[ 0.524608] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10735 04:43:21.855349 <6>[ 0.531099] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10736 04:43:21.862380 <6>[ 0.538106] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10737 04:43:21.868891 <6>[ 0.544594] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10738 04:43:21.875446 <6>[ 0.551601] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10739 04:43:21.882035 <6>[ 0.558089] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10740 04:43:21.888628 <6>[ 0.565093] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10741 04:43:21.892169 <6>[ 0.572600] ACPI: Interpreter disabled.
10742 04:43:21.900270 <6>[ 0.579088] iommu: Default domain type: Translated
10743 04:43:21.906940 <6>[ 0.584202] iommu: DMA domain TLB invalidation policy: strict mode
10744 04:43:21.910015 <5>[ 0.590857] SCSI subsystem initialized
10745 04:43:21.916989 <6>[ 0.595032] usbcore: registered new interface driver usbfs
10746 04:43:21.923239 <6>[ 0.600763] usbcore: registered new interface driver hub
10747 04:43:21.926768 <6>[ 0.606315] usbcore: registered new device driver usb
10748 04:43:21.933389 <6>[ 0.612450] pps_core: LinuxPPS API ver. 1 registered
10749 04:43:21.943714 <6>[ 0.617641] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10750 04:43:21.946803 <6>[ 0.626989] PTP clock support registered
10751 04:43:21.950292 <6>[ 0.631236] EDAC MC: Ver: 3.0.0
10752 04:43:21.958159 <6>[ 0.636425] FPGA manager framework
10753 04:43:21.960965 <6>[ 0.640104] Advanced Linux Sound Architecture Driver Initialized.
10754 04:43:21.964524 <6>[ 0.646883] vgaarb: loaded
10755 04:43:21.971448 <6>[ 0.650072] clocksource: Switched to clocksource arch_sys_counter
10756 04:43:21.978015 <5>[ 0.656509] VFS: Disk quotas dquot_6.6.0
10757 04:43:21.984899 <6>[ 0.660691] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10758 04:43:21.988183 <6>[ 0.667876] pnp: PnP ACPI: disabled
10759 04:43:21.996024 <6>[ 0.674562] NET: Registered PF_INET protocol family
10760 04:43:22.005747 <6>[ 0.680150] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10761 04:43:22.017200 <6>[ 0.692445] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10762 04:43:22.027146 <6>[ 0.701262] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10763 04:43:22.033487 <6>[ 0.709235] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10764 04:43:22.040266 <6>[ 0.717937] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10765 04:43:22.052210 <6>[ 0.727681] TCP: Hash tables configured (established 65536 bind 65536)
10766 04:43:22.058743 <6>[ 0.734539] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10767 04:43:22.065734 <6>[ 0.741736] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10768 04:43:22.071996 <6>[ 0.749439] NET: Registered PF_UNIX/PF_LOCAL protocol family
10769 04:43:22.079072 <6>[ 0.755617] RPC: Registered named UNIX socket transport module.
10770 04:43:22.082018 <6>[ 0.761773] RPC: Registered udp transport module.
10771 04:43:22.088566 <6>[ 0.766703] RPC: Registered tcp transport module.
10772 04:43:22.095286 <6>[ 0.771633] RPC: Registered tcp NFSv4.1 backchannel transport module.
10773 04:43:22.098932 <6>[ 0.778304] PCI: CLS 0 bytes, default 64
10774 04:43:22.101941 <6>[ 0.782706] Unpacking initramfs...
10775 04:43:22.126966 <6>[ 0.802234] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10776 04:43:22.136579 <6>[ 0.810884] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10777 04:43:22.140381 <6>[ 0.819749] kvm [1]: IPA Size Limit: 40 bits
10778 04:43:22.146780 <6>[ 0.824275] kvm [1]: GICv3: no GICV resource entry
10779 04:43:22.150323 <6>[ 0.829297] kvm [1]: disabling GICv2 emulation
10780 04:43:22.156814 <6>[ 0.833983] kvm [1]: GIC system register CPU interface enabled
10781 04:43:22.159815 <6>[ 0.840152] kvm [1]: vgic interrupt IRQ18
10782 04:43:22.166823 <6>[ 0.844509] kvm [1]: VHE mode initialized successfully
10783 04:43:22.173521 <5>[ 0.851051] Initialise system trusted keyrings
10784 04:43:22.179827 <6>[ 0.855895] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10785 04:43:22.186909 <6>[ 0.865945] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10786 04:43:22.193946 <5>[ 0.872384] NFS: Registering the id_resolver key type
10787 04:43:22.197511 <5>[ 0.877686] Key type id_resolver registered
10788 04:43:22.203965 <5>[ 0.882100] Key type id_legacy registered
10789 04:43:22.210392 <6>[ 0.886389] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10790 04:43:22.217067 <6>[ 0.893311] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10791 04:43:22.223927 <6>[ 0.901043] 9p: Installing v9fs 9p2000 file system support
10792 04:43:22.259768 <5>[ 0.938647] Key type asymmetric registered
10793 04:43:22.262721 <5>[ 0.942996] Asymmetric key parser 'x509' registered
10794 04:43:22.273403 <6>[ 0.948165] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10795 04:43:22.276480 <6>[ 0.955783] io scheduler mq-deadline registered
10796 04:43:22.279987 <6>[ 0.960540] io scheduler kyber registered
10797 04:43:22.299105 <6>[ 0.978019] EINJ: ACPI disabled.
10798 04:43:22.332334 <4>[ 1.004397] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10799 04:43:22.342168 <4>[ 1.015057] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10800 04:43:22.357492 <6>[ 1.036003] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10801 04:43:22.364842 <6>[ 1.044007] printk: console [ttyS0] disabled
10802 04:43:22.393147 <6>[ 1.068658] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10803 04:43:22.400174 <6>[ 1.078135] printk: console [ttyS0] enabled
10804 04:43:22.403259 <6>[ 1.078135] printk: console [ttyS0] enabled
10805 04:43:22.410075 <6>[ 1.087028] printk: bootconsole [mtk8250] disabled
10806 04:43:22.413376 <6>[ 1.087028] printk: bootconsole [mtk8250] disabled
10807 04:43:22.419621 <6>[ 1.098437] SuperH (H)SCI(F) driver initialized
10808 04:43:22.423085 <6>[ 1.103739] msm_serial: driver initialized
10809 04:43:22.437296 <6>[ 1.112874] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10810 04:43:22.447600 <6>[ 1.121421] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10811 04:43:22.453682 <6>[ 1.129966] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10812 04:43:22.463874 <6>[ 1.138596] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10813 04:43:22.470491 <6>[ 1.147303] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10814 04:43:22.480305 <6>[ 1.156025] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10815 04:43:22.490619 <6>[ 1.164566] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10816 04:43:22.496810 <6>[ 1.173376] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10817 04:43:22.506729 <6>[ 1.181925] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10818 04:43:22.518932 <6>[ 1.197662] loop: module loaded
10819 04:43:22.525256 <6>[ 1.203635] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10820 04:43:22.547848 <4>[ 1.226901] mtk-pmic-keys: Failed to locate of_node [id: -1]
10821 04:43:22.555292 <6>[ 1.233698] megasas: 07.719.03.00-rc1
10822 04:43:22.564436 <6>[ 1.243375] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10823 04:43:22.571535 <6>[ 1.249448] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10824 04:43:22.587380 <6>[ 1.266115] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10825 04:43:22.644201 <6>[ 1.316268] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10826 04:43:26.106603 <6>[ 4.785711] Freeing initrd memory: 95900K
10827 04:43:26.117040 <6>[ 4.796224] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10828 04:43:26.128328 <6>[ 4.807381] tun: Universal TUN/TAP device driver, 1.6
10829 04:43:26.131627 <6>[ 4.813501] thunder_xcv, ver 1.0
10830 04:43:26.134937 <6>[ 4.817006] thunder_bgx, ver 1.0
10831 04:43:26.138278 <6>[ 4.820503] nicpf, ver 1.0
10832 04:43:26.148581 <6>[ 4.824570] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10833 04:43:26.152214 <6>[ 4.832046] hns3: Copyright (c) 2017 Huawei Corporation.
10834 04:43:26.158502 <6>[ 4.837651] hclge is initializing
10835 04:43:26.161742 <6>[ 4.841231] e1000: Intel(R) PRO/1000 Network Driver
10836 04:43:26.168355 <6>[ 4.846360] e1000: Copyright (c) 1999-2006 Intel Corporation.
10837 04:43:26.171837 <6>[ 4.852375] e1000e: Intel(R) PRO/1000 Network Driver
10838 04:43:26.178714 <6>[ 4.857591] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10839 04:43:26.185192 <6>[ 4.863775] igb: Intel(R) Gigabit Ethernet Network Driver
10840 04:43:26.191806 <6>[ 4.869425] igb: Copyright (c) 2007-2014 Intel Corporation.
10841 04:43:26.198616 <6>[ 4.875260] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10842 04:43:26.204852 <6>[ 4.881777] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10843 04:43:26.208456 <6>[ 4.888247] sky2: driver version 1.30
10844 04:43:26.215144 <6>[ 4.893288] VFIO - User Level meta-driver version: 0.3
10845 04:43:26.222102 <6>[ 4.901638] usbcore: registered new interface driver usb-storage
10846 04:43:26.228733 <6>[ 4.908090] usbcore: registered new device driver onboard-usb-hub
10847 04:43:26.238011 <6>[ 4.917273] mt6397-rtc mt6359-rtc: registered as rtc0
10848 04:43:26.248091 <6>[ 4.922735] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-09T04:43:26 UTC (1691556206)
10849 04:43:26.251101 <6>[ 4.932326] i2c_dev: i2c /dev entries driver
10850 04:43:26.268494 <6>[ 4.944305] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10851 04:43:26.288160 <6>[ 4.967328] cpu cpu0: EM: created perf domain
10852 04:43:26.291189 <6>[ 4.972359] cpu cpu4: EM: created perf domain
10853 04:43:26.298834 <6>[ 4.978041] sdhci: Secure Digital Host Controller Interface driver
10854 04:43:26.305333 <6>[ 4.984476] sdhci: Copyright(c) Pierre Ossman
10855 04:43:26.312357 <6>[ 4.989441] Synopsys Designware Multimedia Card Interface Driver
10856 04:43:26.318866 <6>[ 4.996094] sdhci-pltfm: SDHCI platform and OF driver helper
10857 04:43:26.322286 <6>[ 4.996096] mmc0: CQHCI version 5.10
10858 04:43:26.328788 <6>[ 5.006087] ledtrig-cpu: registered to indicate activity on CPUs
10859 04:43:26.335482 <6>[ 5.013136] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10860 04:43:26.342094 <6>[ 5.020193] usbcore: registered new interface driver usbhid
10861 04:43:26.345653 <6>[ 5.026016] usbhid: USB HID core driver
10862 04:43:26.351553 <6>[ 5.030248] spi_master spi0: will run message pump with realtime priority
10863 04:43:26.395183 <6>[ 5.067929] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10864 04:43:26.414912 <6>[ 5.083852] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10865 04:43:26.418686 <6>[ 5.098798] mmc0: Command Queue Engine enabled
10866 04:43:26.425038 <6>[ 5.103557] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10867 04:43:26.431628 <6>[ 5.110331] cros-ec-spi spi0.0: Chrome EC device registered
10868 04:43:26.437970 <6>[ 5.110728] mmcblk0: mmc0:0001 DA4128 116 GiB
10869 04:43:26.446553 <6>[ 5.125982] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10870 04:43:26.454090 <6>[ 5.133186] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10871 04:43:26.460311 <6>[ 5.139107] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10872 04:43:26.467017 <6>[ 5.144998] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10873 04:43:26.483238 <6>[ 5.159041] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10874 04:43:26.490455 <6>[ 5.169753] NET: Registered PF_PACKET protocol family
10875 04:43:26.494250 <6>[ 5.175159] 9pnet: Installing 9P2000 support
10876 04:43:26.500626 <5>[ 5.179722] Key type dns_resolver registered
10877 04:43:26.504121 <6>[ 5.184745] registered taskstats version 1
10878 04:43:26.510699 <5>[ 5.189134] Loading compiled-in X.509 certificates
10879 04:43:26.541106 <4>[ 5.213574] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10880 04:43:26.551646 <4>[ 5.224458] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10881 04:43:26.558346 <3>[ 5.235061] debugfs: File 'uA_load' in directory '/' already present!
10882 04:43:26.564843 <3>[ 5.241768] debugfs: File 'min_uV' in directory '/' already present!
10883 04:43:26.571516 <3>[ 5.248376] debugfs: File 'max_uV' in directory '/' already present!
10884 04:43:26.577728 <3>[ 5.254982] debugfs: File 'constraint_flags' in directory '/' already present!
10885 04:43:26.588592 <3>[ 5.264568] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10886 04:43:26.598104 <6>[ 5.277317] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10887 04:43:26.604910 <6>[ 5.284004] xhci-mtk 11200000.usb: xHCI Host Controller
10888 04:43:26.611531 <6>[ 5.289517] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10889 04:43:26.621624 <6>[ 5.297365] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10890 04:43:26.628316 <6>[ 5.306795] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10891 04:43:26.634829 <6>[ 5.312863] xhci-mtk 11200000.usb: xHCI Host Controller
10892 04:43:26.641551 <6>[ 5.318338] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10893 04:43:26.648551 <6>[ 5.325984] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10894 04:43:26.654845 <6>[ 5.333660] hub 1-0:1.0: USB hub found
10895 04:43:26.657945 <6>[ 5.337668] hub 1-0:1.0: 1 port detected
10896 04:43:26.664866 <6>[ 5.341954] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10897 04:43:26.671277 <6>[ 5.350488] hub 2-0:1.0: USB hub found
10898 04:43:26.675014 <6>[ 5.354493] hub 2-0:1.0: 1 port detected
10899 04:43:26.683565 <6>[ 5.362860] mtk-msdc 11f70000.mmc: Got CD GPIO
10900 04:43:26.693570 <6>[ 5.369865] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10901 04:43:26.700296 <6>[ 5.377894] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10902 04:43:26.710550 <4>[ 5.385800] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10903 04:43:26.720551 <6>[ 5.395327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10904 04:43:26.727097 <6>[ 5.403404] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10905 04:43:26.733620 <6>[ 5.411433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10906 04:43:26.743567 <6>[ 5.419350] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10907 04:43:26.750242 <6>[ 5.427166] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10908 04:43:26.760289 <6>[ 5.434983] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10909 04:43:26.769785 <6>[ 5.445444] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10910 04:43:26.776820 <6>[ 5.453803] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10911 04:43:26.786265 <6>[ 5.462155] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10912 04:43:26.793146 <6>[ 5.470495] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10913 04:43:26.803275 <6>[ 5.478834] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10914 04:43:26.809897 <6>[ 5.487172] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10915 04:43:26.819606 <6>[ 5.495511] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10916 04:43:26.826326 <6>[ 5.503849] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10917 04:43:26.836700 <6>[ 5.512186] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10918 04:43:26.843239 <6>[ 5.520528] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10919 04:43:26.852580 <6>[ 5.528866] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10920 04:43:26.859646 <6>[ 5.537204] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10921 04:43:26.869488 <6>[ 5.545542] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10922 04:43:26.879542 <6>[ 5.553882] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10923 04:43:26.886353 <6>[ 5.562219] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10924 04:43:26.892603 <6>[ 5.570995] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10925 04:43:26.899713 <6>[ 5.578196] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10926 04:43:26.906636 <6>[ 5.584974] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10927 04:43:26.912537 <6>[ 5.591744] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10928 04:43:26.922855 <6>[ 5.598694] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10929 04:43:26.929367 <6>[ 5.605546] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10930 04:43:26.939252 <6>[ 5.614688] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10931 04:43:26.948716 <6>[ 5.623812] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10932 04:43:26.959039 <6>[ 5.633107] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10933 04:43:26.968919 <6>[ 5.642574] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10934 04:43:26.975905 <6>[ 5.652041] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10935 04:43:26.985356 <6>[ 5.661161] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10936 04:43:26.995325 <6>[ 5.670628] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10937 04:43:27.005596 <6>[ 5.679747] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10938 04:43:27.015453 <6>[ 5.689041] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10939 04:43:27.025109 <6>[ 5.699201] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10940 04:43:27.035154 <6>[ 5.709971] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10941 04:43:27.082413 <6>[ 5.758346] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10942 04:43:27.237168 <6>[ 5.916387] hub 1-1:1.0: USB hub found
10943 04:43:27.240521 <6>[ 5.920900] hub 1-1:1.0: 4 ports detected
10944 04:43:27.362476 <6>[ 6.038418] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10945 04:43:27.388828 <6>[ 6.067426] hub 2-1:1.0: USB hub found
10946 04:43:27.391615 <6>[ 6.071883] hub 2-1:1.0: 3 ports detected
10947 04:43:27.562469 <6>[ 6.238393] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10948 04:43:27.695830 <6>[ 6.374496] hub 1-1.4:1.0: USB hub found
10949 04:43:27.698669 <6>[ 6.379088] hub 1-1.4:1.0: 2 ports detected
10950 04:43:27.774366 <6>[ 6.450530] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10951 04:43:27.994856 <6>[ 6.670445] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10952 04:43:28.186206 <6>[ 6.862392] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10953 04:43:39.315413 <6>[ 17.999385] ALSA device list:
10954 04:43:39.321737 <6>[ 18.002680] No soundcards found.
10955 04:43:39.329905 <6>[ 18.010648] Freeing unused kernel memory: 8384K
10956 04:43:39.333344 <6>[ 18.015656] Run /init as init process
10957 04:43:39.381672 <6>[ 18.061987] NET: Registered PF_INET6 protocol family
10958 04:43:39.388059 <6>[ 18.068153] Segment Routing with IPv6
10959 04:43:39.391091 <6>[ 18.072097] In-situ OAM (IOAM) with IPv6
10960 04:43:39.422700 <30>[ 18.086665] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10961 04:43:39.429903 <30>[ 18.110565] systemd[1]: Detected architecture arm64.
10962 04:43:39.430349
10963 04:43:39.436808 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10964 04:43:39.437274
10965 04:43:39.450072 <30>[ 18.130425] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10966 04:43:39.588295 <30>[ 18.265537] systemd[1]: Queued start job for default target Graphical Interface.
10967 04:43:39.627139 <30>[ 18.307384] systemd[1]: Created slice system-getty.slice.
10968 04:43:39.633472 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10969 04:43:39.650314 <30>[ 18.330923] systemd[1]: Created slice system-modprobe.slice.
10970 04:43:39.657247 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10971 04:43:39.674760 <30>[ 18.355018] systemd[1]: Created slice system-serial\x2dgetty.slice.
10972 04:43:39.684329 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10973 04:43:39.699273 <30>[ 18.379643] systemd[1]: Created slice User and Session Slice.
10974 04:43:39.705746 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10975 04:43:39.725999 <30>[ 18.403061] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10976 04:43:39.736317 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10977 04:43:39.754051 <30>[ 18.431067] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10978 04:43:39.760777 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10979 04:43:39.785567 <30>[ 18.458880] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10980 04:43:39.791618 <30>[ 18.471129] systemd[1]: Reached target Local Encrypted Volumes.
10981 04:43:39.798471 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10982 04:43:39.814606 <30>[ 18.494878] systemd[1]: Reached target Paths.
10983 04:43:39.817933 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10984 04:43:39.834029 <30>[ 18.514352] systemd[1]: Reached target Remote File Systems.
10985 04:43:39.840792 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10986 04:43:39.853786 <30>[ 18.534334] systemd[1]: Reached target Slices.
10987 04:43:39.860365 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10988 04:43:39.873956 <30>[ 18.554374] systemd[1]: Reached target Swap.
10989 04:43:39.877160 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10990 04:43:39.897859 <30>[ 18.574838] systemd[1]: Listening on initctl Compatibility Named Pipe.
10991 04:43:39.904628 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10992 04:43:39.911286 <30>[ 18.589926] systemd[1]: Listening on Journal Audit Socket.
10993 04:43:39.917867 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10994 04:43:39.930693 <30>[ 18.610857] systemd[1]: Listening on Journal Socket (/dev/log).
10995 04:43:39.937162 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10996 04:43:39.955078 <30>[ 18.635612] systemd[1]: Listening on Journal Socket.
10997 04:43:39.961655 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10998 04:43:39.974619 <30>[ 18.654927] systemd[1]: Listening on udev Control Socket.
10999 04:43:39.981398 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
11000 04:43:39.998911 <30>[ 18.679400] systemd[1]: Listening on udev Kernel Socket.
11001 04:43:40.005267 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11002 04:43:40.061915 <30>[ 18.742597] systemd[1]: Mounting Huge Pages File System...
11003 04:43:40.068654 Mounting [0;1;39mHuge Pages File System[0m...
11004 04:43:40.084470 <30>[ 18.765076] systemd[1]: Mounting POSIX Message Queue File System...
11005 04:43:40.091278 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11006 04:43:40.109439 <30>[ 18.789748] systemd[1]: Mounting Kernel Debug File System...
11007 04:43:40.115652 Mounting [0;1;39mKernel Debug File System[0m...
11008 04:43:40.133348 <30>[ 18.810606] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11009 04:43:40.146483 <30>[ 18.823511] systemd[1]: Starting Create list of static device nodes for the current kernel...
11010 04:43:40.153069 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11011 04:43:40.174009 <30>[ 18.854738] systemd[1]: Starting Load Kernel Module configfs...
11012 04:43:40.180519 Starting [0;1;39mLoad Kernel Module configfs[0m...
11013 04:43:40.198650 <30>[ 18.878683] systemd[1]: Starting Load Kernel Module drm...
11014 04:43:40.205045 Starting [0;1;39mLoad Kernel Module drm[0m...
11015 04:43:40.221142 <30>[ 18.898578] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11016 04:43:40.254049 <30>[ 18.934708] systemd[1]: Starting Journal Service...
11017 04:43:40.257455 Starting [0;1;39mJournal Service[0m...
11018 04:43:40.276564 <30>[ 18.957275] systemd[1]: Starting Load Kernel Modules...
11019 04:43:40.283213 Starting [0;1;39mLoad Kernel Modules[0m...
11020 04:43:40.303887 <30>[ 18.981142] systemd[1]: Starting Remount Root and Kernel File Systems...
11021 04:43:40.310537 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11022 04:43:40.328623 <30>[ 19.009316] systemd[1]: Starting Coldplug All udev Devices...
11023 04:43:40.335677 Starting [0;1;39mColdplug All udev Devices[0m...
11024 04:43:40.352542 <30>[ 19.033223] systemd[1]: Started Journal Service.
11025 04:43:40.358979 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11026 04:43:40.376053 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11027 04:43:40.395118 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11028 04:43:40.410684 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11029 04:43:40.430932 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11030 04:43:40.448105 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11031 04:43:40.469089 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11032 04:43:40.490057 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11033 04:43:40.510139 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11034 04:43:40.525802 See 'systemctl status systemd-remount-fs.service' for details.
11035 04:43:40.590147 Mounting [0;1;39mKernel Configuration File System[0m...
11036 04:43:40.610784 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11037 04:43:40.624133 <46>[ 19.301468] systemd-journald[187]: Received client request to flush runtime journal.
11038 04:43:40.635166 Starting [0;1;39mLoad/Save Random Seed[0m...
11039 04:43:40.655500 Starting [0;1;39mApply Kernel Variables[0m...
11040 04:43:40.675192 Starting [0;1;39mCreate System Users[0m...
11041 04:43:40.695597 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11042 04:43:40.710874 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11043 04:43:40.731105 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11044 04:43:40.743709 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11045 04:43:40.759780 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11046 04:43:40.779290 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11047 04:43:40.830058 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11048 04:43:40.851163 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11049 04:43:40.869776 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11050 04:43:40.890348 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11051 04:43:40.934557 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11052 04:43:40.962825 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11053 04:43:40.991891 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11054 04:43:41.011049 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11055 04:43:41.072718 Starting [0;1;39mNetwork Time Synchronization[0m...
11056 04:43:41.092854 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11057 04:43:41.125901 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11058 04:43:41.146538 <6>[ 19.824051] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11059 04:43:41.156616 <6>[ 19.832329] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11060 04:43:41.166693 <6>[ 19.843701] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11061 04:43:41.183798 <4>[ 19.861140] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11062 04:43:41.196846 <4>[ 19.873899] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11063 04:43:41.203230 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11064 04:43:41.221743 <6>[ 19.898973] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11065 04:43:41.228729 <3>[ 19.900381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11066 04:43:41.238327 [[0;32m OK [<3>[ 19.915097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11067 04:43:41.248213 <3>[ 19.924588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11068 04:43:41.254951 0m] Started [0;1;39mNetwork Tim<6>[ 19.934563] remoteproc remoteproc0: scp is available
11069 04:43:41.264769 e Synchronizatio<3>[ 19.936935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11070 04:43:41.265213 n[0m.
11071 04:43:41.271418 <6>[ 19.940769] remoteproc remoteproc0: powering up scp
11072 04:43:41.275137 <6>[ 19.942653] usbcore: registered new interface driver r8152
11073 04:43:41.284658 <3>[ 19.950443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11074 04:43:41.291276 <6>[ 19.955982] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11075 04:43:41.301547 <3>[ 19.961711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11076 04:43:41.308066 <3>[ 19.961720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11077 04:43:41.318075 <3>[ 19.961724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11078 04:43:41.324701 <3>[ 19.970303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11079 04:43:41.330912 <6>[ 19.978372] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11080 04:43:41.334836 <6>[ 19.979686] mc: Linux media interface: v0.10
11081 04:43:41.340813 <6>[ 19.985978] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11082 04:43:41.347737 <6>[ 19.985989] pci_bus 0000:00: root bus resource [bus 00-ff]
11083 04:43:41.354526 <6>[ 19.986003] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11084 04:43:41.364210 <6>[ 19.986013] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11085 04:43:41.370758 <6>[ 19.986575] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11086 04:43:41.380901 <3>[ 20.000934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11087 04:43:41.387653 <6>[ 20.003010] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11088 04:43:41.397736 <6>[ 20.008598] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11089 04:43:41.404301 <3>[ 20.010845] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11090 04:43:41.413850 <6>[ 20.010990] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11091 04:43:41.423910 <6>[ 20.012122] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11092 04:43:41.430387 <6>[ 20.015412] videodev: Linux video capture interface: v2.00
11093 04:43:41.433484 <6>[ 20.016615] pci 0000:00:00.0: supports D1 D2
11094 04:43:41.443487 <3>[ 20.021004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11095 04:43:41.449939 <3>[ 20.021165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11096 04:43:41.456594 <6>[ 20.027916] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11097 04:43:41.466706 <3>[ 20.033674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11098 04:43:41.473224 <6>[ 20.043502] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11099 04:43:41.483578 <3>[ 20.051158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11100 04:43:41.490077 <6>[ 20.053579] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11101 04:43:41.496819 <6>[ 20.053736] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11102 04:43:41.503106 <6>[ 20.053773] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11103 04:43:41.513259 <6>[ 20.053799] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11104 04:43:41.519955 <6>[ 20.053818] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11105 04:43:41.523188 <6>[ 20.053985] pci 0000:01:00.0: supports D1 D2
11106 04:43:41.530384 <6>[ 20.053991] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11107 04:43:41.536522 <6>[ 20.065717] usbcore: registered new interface driver cdc_ether
11108 04:43:41.543043 <6>[ 20.066144] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11109 04:43:41.553177 <6>[ 20.066178] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11110 04:43:41.559928 <6>[ 20.066181] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11111 04:43:41.567558 <6>[ 20.066190] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11112 04:43:41.577981 <6>[ 20.066203] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11113 04:43:41.584602 <6>[ 20.066216] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11114 04:43:41.591316 <6>[ 20.066229] pci 0000:00:00.0: PCI bridge to [bus 01]
11115 04:43:41.597684 <6>[ 20.066234] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11116 04:43:41.605029 <6>[ 20.066429] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11117 04:43:41.611323 <6>[ 20.067050] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11118 04:43:41.614934 <6>[ 20.067270] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11119 04:43:41.621809 <6>[ 20.072710] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11120 04:43:41.632173 <3>[ 20.073512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11121 04:43:41.638609 <3>[ 20.073526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11122 04:43:41.648502 <3>[ 20.073592] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11123 04:43:41.655257 <4>[ 20.087712] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11124 04:43:41.661796 <4>[ 20.087712] Fallback method does not support PEC.
11125 04:43:41.668486 <6>[ 20.115889] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11126 04:43:41.679421 <6>[ 20.115890] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11127 04:43:41.682748 <6>[ 20.115934] remoteproc remoteproc0: remote processor scp is now up
11128 04:43:41.686123 <6>[ 20.117836] Bluetooth: Core ver 2.22
11129 04:43:41.692637 <6>[ 20.117855] usbcore: registered new interface driver r8153_ecm
11130 04:43:41.699206 <6>[ 20.117996] NET: Registered PF_BLUETOOTH protocol family
11131 04:43:41.706840 <6>[ 20.118006] Bluetooth: HCI device and connection manager initialized
11132 04:43:41.709702 <6>[ 20.118428] Bluetooth: HCI socket layer initialized
11133 04:43:41.716871 <6>[ 20.118438] Bluetooth: L2CAP socket layer initialized
11134 04:43:41.719803 <6>[ 20.118459] Bluetooth: SCO socket layer initialized
11135 04:43:41.726444 <6>[ 20.128266] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11136 04:43:41.733252 <6>[ 20.187625] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11137 04:43:41.743260 <4>[ 20.190928] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11138 04:43:41.757238 <6>[ 20.200409] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11139 04:43:41.763552 <4>[ 20.205419] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11140 04:43:41.770201 <6>[ 20.207569] usbcore: registered new interface driver btusb
11141 04:43:41.776896 <6>[ 20.208541] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11142 04:43:41.787259 <5>[ 20.209296] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11143 04:43:41.796909 <4>[ 20.210784] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11144 04:43:41.804044 <6>[ 20.210950] usbcore: registered new interface driver uvcvideo
11145 04:43:41.810364 <5>[ 20.226304] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11146 04:43:41.817342 <3>[ 20.230454] Bluetooth: hci0: Failed to load firmware file (-2)
11147 04:43:41.823931 <6>[ 20.230505] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11148 04:43:41.833968 <4>[ 20.239238] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11149 04:43:41.837237 <3>[ 20.246790] Bluetooth: hci0: Failed to set up firmware (-2)
11150 04:43:41.847401 <3>[ 20.253650] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11151 04:43:41.857415 <3>[ 20.254362] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
11152 04:43:41.860492 <6>[ 20.254783] cfg80211: failed to load regulatory.db
11153 04:43:41.863999 <6>[ 20.258215] r8152 2-1.3:1.0 eth0: v1.12.13
11154 04:43:41.877667 <4>[ 20.263406] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11155 04:43:41.881719 <6>[ 20.282715] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11156 04:43:41.891196 <3>[ 20.290372] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11157 04:43:41.897637 <3>[ 20.291295] power_supply sbs-5-000b: driver failed to report `status' property: -6
11158 04:43:41.907356 <3>[ 20.307694] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11159 04:43:41.914479 <6>[ 20.336508] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11160 04:43:41.924092 <3>[ 20.369161] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11161 04:43:41.931041 <6>[ 20.369806] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11162 04:43:41.937565 <3>[ 20.395813] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11163 04:43:41.944033 <6>[ 20.417062] mt7921e 0000:01:00.0: ASIC revision: 79610010
11164 04:43:41.950763 <3>[ 20.441775] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11165 04:43:41.964315 <4>[ 20.541878] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11166 04:43:41.973929 <3>[ 20.568810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11167 04:43:41.980442 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11168 04:43:42.008406 <3>[ 20.686160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11169 04:43:42.021531 <4>[ 20.688937] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11170 04:43:42.024680 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11171 04:43:42.064833 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11172 04:43:42.138041 <4>[ 20.812418] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11173 04:43:42.186534 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11174 04:43:42.205714 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11175 04:43:42.224868 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11176 04:43:42.256166 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.<4>[ 20.928517] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11177 04:43:42.256625
11178 04:43:42.270152 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11179 04:43:42.294119 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11180 04:43:42.309828 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11181 04:43:42.333807 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11182 04:43:42.350096 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11183 04:43:42.376492 [[0;32m OK [0m] Reached targ<4>[ 21.048804] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11184 04:43:42.379666 et [0;1;39mBasic System[0m.
11185 04:43:42.398824 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11186 04:43:42.438758 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11187 04:43:42.465907 Starting [0;1;39mUser Login Management[0m...
11188 04:43:42.495357 <4>[ 21.170016] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11189 04:43:42.502187 Starting [0;1;39mPermit User Sessions[0m...
11190 04:43:42.521291 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11191 04:43:42.566598 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11192 04:43:42.586476 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11193 04:43:42.613728 [[0;32m OK [0m] Reached target [0;1;39mLogi<4>[ 21.288559] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11194 04:43:42.617128 n Prompts[0m.
11195 04:43:42.654717 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11196 04:43:42.670730 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11197 04:43:42.686725 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11198 04:43:42.694451 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11199 04:43:42.710349 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11200 04:43:42.734705 <4>[ 21.408520] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11201 04:43:42.766554 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11202 04:43:42.797902 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11203 04:43:42.829169
11204 04:43:42.829599
11205 04:43:42.832495 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11206 04:43:42.832950
11207 04:43:42.835984 debian-bullseye-arm64 login: root (automatic login)
11208 04:43:42.836405
11209 04:43:42.836766
11210 04:43:42.857250 <4>[ 21.531090] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11211 04:43:42.863935 Linux debian-bullseye-arm64 6.1.42-cip2 #1 SMP PREEMPT Wed Aug 9 04:18:34 UTC 2023 aarch64
11212 04:43:42.864499
11213 04:43:42.870282 The programs included with the Debian GNU/Linux system are free software;
11214 04:43:42.876941 the exact distribution terms for each program are described in the
11215 04:43:42.883906 individual files in /usr/share/doc/*/copyright.
11216 04:43:42.884330
11217 04:43:42.886863 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11218 04:43:42.890571 permitted by applicable law.
11219 04:43:42.891679 Matched prompt #10: / #
11221 04:43:42.892729 Setting prompt string to ['/ #']
11222 04:43:42.893175 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11224 04:43:42.894155 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11225 04:43:42.894586 start: 2.2.6 expect-shell-connection (timeout 00:01:50) [common]
11226 04:43:42.894936 Setting prompt string to ['/ #']
11227 04:43:42.895241 Forcing a shell prompt, looking for ['/ #']
11229 04:43:42.945924 / #
11230 04:43:42.946028 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11231 04:43:42.946142 Waiting using forced prompt support (timeout 00:02:30)
11232 04:43:42.951419
11233 04:43:42.951710 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11234 04:43:42.951806 start: 2.2.7 export-device-env (timeout 00:01:50) [common]
11235 04:43:42.951904 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11236 04:43:42.951994 end: 2.2 depthcharge-retry (duration 00:03:10) [common]
11237 04:43:42.952081 end: 2 depthcharge-action (duration 00:03:10) [common]
11238 04:43:42.952170 start: 3 lava-test-retry (timeout 00:05:00) [common]
11239 04:43:42.952253 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11240 04:43:42.952323 Using namespace: common
11242 04:43:43.052656 / # #
11243 04:43:43.052843 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11244 04:43:43.052954 <4>[ 21.652600] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11245 04:43:43.058005 #
11246 04:43:43.058273 Using /lava-11241319
11248 04:43:43.158555 / # export SHELL=/bin/sh
11249 04:43:43.158751 <3>[ 21.770577] mt7921e 0000:01:00.0: hardware init failed
11250 04:43:43.163928 export SHELL=/bin/sh
11252 04:43:43.264417 / # . /lava-11241319/environment
11253 04:43:43.270179 . /lava-11241319/environment
11255 04:43:43.370741 / # /lava-11241319/bin/lava-test-runner /lava-11241319/0
11256 04:43:43.370888 Test shell timeout: 10s (minimum of the action and connection timeout)
11257 04:43:43.376041 /lava-11241319/bin/lava-test-runner /lava-11241319/0
11258 04:43:43.396419 + export TESTRUN_ID=0_sleep
11259 04:43:43.399402 + cd /lava-11241319/0/tests/0_sleep
11260 04:43:43.402851 + cat uuid
11261 04:43:43.403329 + UUID=11241319_1.5.2.3.1
11262 04:43:43.403680 + set +x
11263 04:43:43.409661 <LAVA_SIGNAL_STARTRUN 0_sleep 11241319_1.5.2.3.1>
11264 04:43:43.410364 Received signal: <STARTRUN> 0_sleep 11241319_1.5.2.3.1
11265 04:43:43.410735 Starting test lava.0_sleep (11241319_1.5.2.3.1)
11266 04:43:43.411134 Skipping test definition patterns.
11267 04:43:43.413348 + ./config/lava/sleep/sleep.sh mem freeze
11268 04:43:43.416353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11269 04:43:43.417631 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11271 04:43:43.422584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11272 04:43:43.423453 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11274 04:43:45.582852 rtcwake: assuming RTC uses UTC ...
11275 04:43:45.583359 rtcwake: wakeup from "mem" using rtc0 at Wed<6>[ 22.115774] PM: suspend entry (deep)
11276 04:43:45.583830 Aug 9 04:43:49<6>[ 22.120505] Filesystems sync: 0.000 seconds
11277 04:43:45.584306 2023
11278 04:43:45.584831 <6>[ 22.127948] Freezing user space processes
11279 04:43:45.585377 <6>[ 22.133744] Freezing user space processes completed (elapsed 0.001 seconds)
11280 04:43:45.585846 <6>[ 22.140978] OOM killer disabled.
11281 04:43:45.586331 <6>[ 22.144461] Freezing remaining freezable tasks
11282 04:43:45.586967 <6>[ 22.150093] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11283 04:43:45.587444 <6>[ 22.157745] printk: Suspending console(s) (use no_console_suspend to debug)
11284 04:43:46.711334 <3>[ 25.166477] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11285 04:43:46.721482 <3>[ 25.166509] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11286 04:43:46.731303 <3>[ 25.166555] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11287 04:43:46.737881 <3>[ 25.166594] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11288 04:43:46.744468 <3>[ 25.166854] PM: Some devices failed to suspend, or early wake event detected
11289 04:43:46.750967 <4>[ 25.182079] typec port0-partner: PM: parent port0 should not be sleeping
11290 04:43:46.758017 <6>[ 25.439106] OOM killer enabled.
11291 04:43:46.761051 <6>[ 25.442515] Restarting tasks ... done.
11292 04:43:46.767665 <5>[ 25.448660] random: crng reseeded on system resumption
11293 04:43:46.771158 <6>[ 25.455062] PM: suspend exit
11294 04:43:46.774677 rtcwake: write error
11295 04:43:46.781987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11296 04:43:46.782852 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11298 04:43:46.784924 rtcwake: assuming RTC uses UTC ...
11299 04:43:46.791332 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:43:52 2023
11300 04:43:46.803355 <6>[ 25.484693] PM: suspend entry (deep)
11301 04:43:46.806753 <6>[ 25.488585] Filesystems sync: 0.000 seconds
11302 04:43:46.810226 <6>[ 25.493577] Freezing user space processes
11303 04:43:46.821437 <6>[ 25.499482] Freezing user space processes completed (elapsed 0.001 seconds)
11304 04:43:46.825101 <6>[ 25.506703] OOM killer disabled.
11305 04:43:46.828087 <6>[ 25.510192] Freezing remaining freezable tasks
11306 04:43:46.838279 <6>[ 25.516224] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11307 04:43:46.844867 <6>[ 25.523895] printk: Suspending console(s) (use no_console_suspend to debug)
11308 04:43:50.302518 <3>[ 28.750418] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11309 04:43:50.312644 <3>[ 28.750447] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11310 04:43:50.322941 <3>[ 28.750492] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11311 04:43:50.329750 <3>[ 28.750532] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11312 04:43:50.336266 <3>[ 28.750824] PM: Some devices failed to suspend, or early wake event detected
11313 04:43:50.339731 <6>[ 29.024242] OOM killer enabled.
11314 04:43:50.348063 <6>[ 29.027653] Restarting tasks ... done.
11315 04:43:50.351243 <5>[ 29.033847] random: crng reseeded on system resumption
11316 04:43:50.354885 <6>[ 29.040217] PM: suspend exit
11317 04:43:50.358482 rtcwake: write error
11318 04:43:50.365810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11319 04:43:50.366556 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11321 04:43:50.369575 rtcwake: assuming RTC uses UTC ...
11322 04:43:50.375753 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:43:56 2023
11323 04:43:50.389374 <6>[ 29.071281] PM: suspend entry (deep)
11324 04:43:50.393320 <6>[ 29.075222] Filesystems sync: 0.000 seconds
11325 04:43:50.396395 <6>[ 29.080380] Freezing user space processes
11326 04:43:50.407699 <6>[ 29.086203] Freezing user space processes completed (elapsed 0.001 seconds)
11327 04:43:50.411483 <6>[ 29.093518] OOM killer disabled.
11328 04:43:50.414326 <6>[ 29.097019] Freezing remaining freezable tasks
11329 04:43:50.424558 <6>[ 29.102969] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11330 04:43:50.430886 <6>[ 29.110633] printk: Suspending console(s) (use no_console_suspend to debug)
11331 04:43:53.877795 <3>[ 32.334343] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11332 04:43:53.887580 <3>[ 32.334367] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11333 04:43:53.897140 <3>[ 32.334396] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11334 04:43:53.904409 <3>[ 32.334424] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11335 04:43:53.911103 <3>[ 32.334642] PM: Some devices failed to suspend, or early wake event detected
11336 04:43:53.914058 <6>[ 32.599796] OOM killer enabled.
11337 04:43:53.928236 <6>[ 32.603209] Restarting tasks ... done.
11338 04:43:53.931998 <5>[ 32.614971] random: crng reseeded on system resumption
11339 04:43:53.935802 <6>[ 32.621670] PM: suspend exit
11340 04:43:53.939108 rtcwake: write error
11341 04:43:53.947176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11342 04:43:53.947478 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11344 04:43:53.950099 rtcwake: assuming RTC uses UTC ...
11345 04:43:53.956623 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:43:59 2023
11346 04:43:53.969885 <6>[ 32.652121] PM: suspend entry (deep)
11347 04:43:53.973283 <6>[ 32.656015] Filesystems sync: 0.000 seconds
11348 04:43:53.975993 <6>[ 32.661061] Freezing user space processes
11349 04:43:53.987855 <6>[ 32.666981] Freezing user space processes completed (elapsed 0.001 seconds)
11350 04:43:53.991353 <6>[ 32.674210] OOM killer disabled.
11351 04:43:53.994415 <6>[ 32.677687] Freezing remaining freezable tasks
11352 04:43:54.004815 <6>[ 32.683822] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11353 04:43:54.011247 <6>[ 32.691504] printk: Suspending console(s) (use no_console_suspend to debug)
11354 04:43:57.461495 <3>[ 35.918392] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11355 04:43:57.471095 <3>[ 35.918422] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11356 04:43:57.481382 <3>[ 35.918467] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11357 04:43:57.487766 <3>[ 35.918508] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11358 04:43:57.494839 <3>[ 35.918813] PM: Some devices failed to suspend, or early wake event detected
11359 04:43:57.497860 <6>[ 36.184012] OOM killer enabled.
11360 04:43:57.506451 <6>[ 36.187429] Restarting tasks ... done.
11361 04:43:57.509830 <5>[ 36.193485] random: crng reseeded on system resumption
11362 04:43:57.513961 <6>[ 36.200399] PM: suspend exit
11363 04:43:57.517507 rtcwake: write error
11364 04:43:57.525428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11365 04:43:57.525707 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11367 04:43:57.528660 rtcwake: assuming RTC uses UTC ...
11368 04:43:57.535335 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:44:03 2023
11369 04:43:57.547978 <6>[ 36.230831] PM: suspend entry (deep)
11370 04:43:57.551606 <6>[ 36.234717] Filesystems sync: 0.000 seconds
11371 04:43:57.554679 <6>[ 36.239744] Freezing user space processes
11372 04:43:57.566465 <6>[ 36.245726] Freezing user space processes completed (elapsed 0.001 seconds)
11373 04:43:57.570176 <6>[ 36.252962] OOM killer disabled.
11374 04:43:57.573439 <6>[ 36.256442] Freezing remaining freezable tasks
11375 04:43:57.583147 <6>[ 36.262172] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11376 04:43:57.589852 <6>[ 36.269827] printk: Suspending console(s) (use no_console_suspend to debug)
11377 04:44:01.049338 <3>[ 39.502388] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11378 04:44:01.059798 <3>[ 39.502418] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11379 04:44:01.069512 <3>[ 39.502462] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11380 04:44:01.076410 <3>[ 39.502503] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11381 04:44:01.082922 <3>[ 39.502820] PM: Some devices failed to suspend, or early wake event detected
11382 04:44:01.086082 <6>[ 39.772499] OOM killer enabled.
11383 04:44:01.094546 <6>[ 39.775910] Restarting tasks ... done.
11384 04:44:01.101725 <5>[ 39.783476] random: crng reseeded on system resumption
11385 04:44:01.105044 <6>[ 39.789951] PM: suspend exit
11386 04:44:01.107773 rtcwake: write error
11387 04:44:01.115198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11388 04:44:01.116057 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11390 04:44:01.118321 rtcwake: assuming RTC uses UTC ...
11391 04:44:01.125383 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:44:06 2023
11392 04:44:01.137505 <6>[ 39.820692] PM: suspend entry (deep)
11393 04:44:01.140826 <6>[ 39.824615] Filesystems sync: 0.000 seconds
11394 04:44:01.144879 <6>[ 39.829611] Freezing user space processes
11395 04:44:01.155829 <6>[ 39.835615] Freezing user space processes completed (elapsed 0.001 seconds)
11396 04:44:01.159451 <6>[ 39.842856] OOM killer disabled.
11397 04:44:01.162400 <6>[ 39.846339] Freezing remaining freezable tasks
11398 04:44:01.172636 <6>[ 39.852442] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11399 04:44:01.179257 <6>[ 39.860118] printk: Suspending console(s) (use no_console_suspend to debug)
11400 04:44:04.637081 <3>[ 43.086373] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11401 04:44:04.647273 <3>[ 43.086404] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11402 04:44:04.657202 <3>[ 43.086449] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11403 04:44:04.663758 <3>[ 43.086489] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11404 04:44:04.671173 <3>[ 43.086726] PM: Some devices failed to suspend, or early wake event detected
11405 04:44:04.673872 <6>[ 43.360429] OOM killer enabled.
11406 04:44:04.686808 <6>[ 43.363839] Restarting tasks ... done.
11407 04:44:04.690533 <5>[ 43.374443] random: crng reseeded on system resumption
11408 04:44:04.694759 <6>[ 43.381512] PM: suspend exit
11409 04:44:04.697831 rtcwake: write error
11410 04:44:04.706217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11411 04:44:04.707201 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11413 04:44:04.709591 rtcwake: assuming RTC uses UTC ...
11414 04:44:04.715779 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:44:10 2023
11415 04:44:04.729056 <6>[ 43.412065] PM: suspend entry (deep)
11416 04:44:04.731910 <6>[ 43.415949] Filesystems sync: 0.000 seconds
11417 04:44:04.735432 <6>[ 43.420966] Freezing user space processes
11418 04:44:04.747210 <6>[ 43.426894] Freezing user space processes completed (elapsed 0.001 seconds)
11419 04:44:04.750071 <6>[ 43.434138] OOM killer disabled.
11420 04:44:04.753640 <6>[ 43.437616] Freezing remaining freezable tasks
11421 04:44:04.764229 <6>[ 43.443755] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11422 04:44:04.770381 <6>[ 43.451424] printk: Suspending console(s) (use no_console_suspend to debug)
11423 04:44:08.216723 <3>[ 46.670454] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11424 04:44:08.226449 <3>[ 46.670489] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11425 04:44:08.236686 <3>[ 46.670537] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11426 04:44:08.243504 <3>[ 46.670579] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11427 04:44:08.250074 <3>[ 46.670811] PM: Some devices failed to suspend, or early wake event detected
11428 04:44:08.253573 <6>[ 46.940497] OOM killer enabled.
11429 04:44:08.262096 <6>[ 46.943907] Restarting tasks ... done.
11430 04:44:08.265377 <5>[ 46.949832] random: crng reseeded on system resumption
11431 04:44:08.268280 <6>[ 46.956148] PM: suspend exit
11432 04:44:08.271882 rtcwake: write error
11433 04:44:08.280189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11434 04:44:08.280468 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11436 04:44:08.283320 rtcwake: assuming RTC uses UTC ...
11437 04:44:08.290364 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:44:14 2023
11438 04:44:08.302340 <6>[ 46.986660] PM: suspend entry (deep)
11439 04:44:08.305740 <6>[ 46.990551] Filesystems sync: 0.000 seconds
11440 04:44:08.309272 <6>[ 46.995566] Freezing user space processes
11441 04:44:08.321031 <6>[ 47.001554] Freezing user space processes completed (elapsed 0.001 seconds)
11442 04:44:08.324314 <6>[ 47.008794] OOM killer disabled.
11443 04:44:08.327681 <6>[ 47.012276] Freezing remaining freezable tasks
11444 04:44:08.337667 <6>[ 47.018287] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11445 04:44:08.343917 <6>[ 47.025950] printk: Suspending console(s) (use no_console_suspend to debug)
11446 04:44:11.800634 <6>[ 48.206521] vpu: disabling
11447 04:44:11.804141 <6>[ 48.206673] vproc2: disabling
11448 04:44:11.807092 <6>[ 48.206728] vproc1: disabling
11449 04:44:11.810757 <6>[ 48.206782] vaud18: disabling
11450 04:44:11.813822 <6>[ 48.207027] vsram_others: disabling
11451 04:44:11.817548 <6>[ 48.207224] va09: disabling
11452 04:44:11.820458 <6>[ 48.207302] vsram_md: disabling
11453 04:44:11.824164 <6>[ 48.207429] Vgpu: disabling
11454 04:44:11.831063 <3>[ 50.254416] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11455 04:44:11.840923 <3>[ 50.254452] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11456 04:44:11.850481 <3>[ 50.254500] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11457 04:44:11.857622 <3>[ 50.254543] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11458 04:44:11.864421 <3>[ 50.254817] PM: Some devices failed to suspend, or early wake event detected
11459 04:44:11.867261 <6>[ 50.554342] OOM killer enabled.
11460 04:44:11.875035 <6>[ 50.557740] Restarting tasks ... done.
11461 04:44:11.881865 <5>[ 50.564489] random: crng reseeded on system resumption
11462 04:44:11.885365 <6>[ 50.570837] PM: suspend exit
11463 04:44:11.885790 rtcwake: write error
11464 04:44:11.894533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11465 04:44:11.895252 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11467 04:44:11.897535 rtcwake: assuming RTC uses UTC ...
11468 04:44:11.904150 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:44:17 2023
11469 04:44:11.917061 <6>[ 50.601201] PM: suspend entry (deep)
11470 04:44:11.920787 <6>[ 50.605106] Filesystems sync: 0.000 seconds
11471 04:44:11.923789 <6>[ 50.610193] Freezing user space processes
11472 04:44:11.935490 <6>[ 50.616143] Freezing user space processes completed (elapsed 0.001 seconds)
11473 04:44:11.939170 <6>[ 50.623386] OOM killer disabled.
11474 04:44:11.942193 <6>[ 50.626866] Freezing remaining freezable tasks
11475 04:44:11.951929 <6>[ 50.632942] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11476 04:44:11.958726 <6>[ 50.640621] printk: Suspending console(s) (use no_console_suspend to debug)
11477 04:44:15.387897 <3>[ 53.838446] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11478 04:44:15.398356 <3>[ 53.838483] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11479 04:44:15.408194 <3>[ 53.838530] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11480 04:44:15.414854 <3>[ 53.838569] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11481 04:44:15.421536 <3>[ 53.838836] PM: Some devices failed to suspend, or early wake event detected
11482 04:44:15.425117 <6>[ 54.112437] OOM killer enabled.
11483 04:44:15.439459 <6>[ 54.115848] Restarting tasks ... done.
11484 04:44:15.442843 <5>[ 54.127966] random: crng reseeded on system resumption
11485 04:44:15.446765 <6>[ 54.134552] PM: suspend exit
11486 04:44:15.450105 rtcwake: write error
11487 04:44:15.457604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11488 04:44:15.458307 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11490 04:44:15.461062 rtcwake: assuming RTC uses UTC ...
11491 04:44:15.467746 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:44:21 2023
11492 04:44:15.480538 <6>[ 54.164835] PM: suspend entry (deep)
11493 04:44:15.483764 <6>[ 54.168736] Filesystems sync: 0.000 seconds
11494 04:44:15.486982 <6>[ 54.173735] Freezing user space processes
11495 04:44:15.498813 <6>[ 54.179819] Freezing user space processes completed (elapsed 0.001 seconds)
11496 04:44:15.501833 <6>[ 54.187052] OOM killer disabled.
11497 04:44:15.505335 <6>[ 54.190537] Freezing remaining freezable tasks
11498 04:44:15.515224 <6>[ 54.196664] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11499 04:44:15.522115 <6>[ 54.204337] printk: Suspending console(s) (use no_console_suspend to debug)
11500 04:44:18.971356 <3>[ 57.422374] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11501 04:44:18.981514 <3>[ 57.422405] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11502 04:44:18.991300 <3>[ 57.422449] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11503 04:44:18.997821 <3>[ 57.422491] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11504 04:44:19.004403 <3>[ 57.422729] PM: Some devices failed to suspend, or early wake event detected
11505 04:44:19.007971 <6>[ 57.696429] OOM killer enabled.
11506 04:44:19.017939 <6>[ 57.699839] Restarting tasks ... done.
11507 04:44:19.020858 <5>[ 57.706876] random: crng reseeded on system resumption
11508 04:44:19.025376 <6>[ 57.713724] PM: suspend exit
11509 04:44:19.028376 rtcwake: write error
11510 04:44:19.036224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11511 04:44:19.036996 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11513 04:44:19.039535 rtcwake: assuming RTC uses UTC ...
11514 04:44:19.046512 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:24 2023
11515 04:44:19.060487 <6>[ 57.745630] PM: suspend entry (s2idle)
11516 04:44:19.063783 <6>[ 57.749690] Filesystems sync: 0.000 seconds
11517 04:44:19.070365 <6>[ 57.754830] Freezing user space processes
11518 04:44:19.077075 <6>[ 57.760723] Freezing user space processes completed (elapsed 0.001 seconds)
11519 04:44:19.080515 <6>[ 57.767956] OOM killer disabled.
11520 04:44:19.087226 <6>[ 57.771440] Freezing remaining freezable tasks
11521 04:44:19.093679 <6>[ 57.777473] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11522 04:44:19.103623 <6>[ 57.785141] printk: Suspending console(s) (use no_console_suspend to debug)
11523 04:44:22.554862 <3>[ 61.006406] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11524 04:44:22.564811 <3>[ 61.006441] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11525 04:44:22.574539 <3>[ 61.006499] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11526 04:44:22.581399 <3>[ 61.006553] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11527 04:44:22.587719 <3>[ 61.006835] PM: Some devices failed to suspend, or early wake event detected
11528 04:44:22.591449 <6>[ 61.280392] OOM killer enabled.
11529 04:44:22.599796 <6>[ 61.283803] Restarting tasks ... done.
11530 04:44:22.603184 <5>[ 61.289773] random: crng reseeded on system resumption
11531 04:44:22.606896 <6>[ 61.295973] PM: suspend exit
11532 04:44:22.609915 rtcwake: write error
11533 04:44:22.617756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11534 04:44:22.618084 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11536 04:44:22.621160 rtcwake: assuming RTC uses UTC ...
11537 04:44:22.627927 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:28 2023
11538 04:44:22.640605 <6>[ 61.326353] PM: suspend entry (s2idle)
11539 04:44:22.644094 <6>[ 61.330408] Filesystems sync: 0.000 seconds
11540 04:44:22.646946 <6>[ 61.335386] Freezing user space processes
11541 04:44:22.659440 <6>[ 61.341315] Freezing user space processes completed (elapsed 0.001 seconds)
11542 04:44:22.662358 <6>[ 61.348549] OOM killer disabled.
11543 04:44:22.666258 <6>[ 61.352030] Freezing remaining freezable tasks
11544 04:44:22.676174 <6>[ 61.358081] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11545 04:44:22.682854 <6>[ 61.365744] printk: Suspending console(s) (use no_console_suspend to debug)
11546 04:44:26.138814 <3>[ 64.590377] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11547 04:44:26.148750 <3>[ 64.590406] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11548 04:44:26.158683 <3>[ 64.590451] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11549 04:44:26.164980 <3>[ 64.590491] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11550 04:44:26.171625 <3>[ 64.590773] PM: Some devices failed to suspend, or early wake event detected
11551 04:44:26.175131 <6>[ 64.864390] OOM killer enabled.
11552 04:44:26.183901 <6>[ 64.867801] Restarting tasks ... done.
11553 04:44:26.187312 <5>[ 64.873862] random: crng reseeded on system resumption
11554 04:44:26.191566 <6>[ 64.881109] PM: suspend exit
11555 04:44:26.195106 rtcwake: write error
11556 04:44:26.203241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11557 04:44:26.203946 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11559 04:44:26.206349 rtcwake: assuming RTC uses UTC ...
11560 04:44:26.213146 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:32 2023
11561 04:44:26.225834 <6>[ 64.911743] PM: suspend entry (s2idle)
11562 04:44:26.229598 <6>[ 64.915806] Filesystems sync: 0.000 seconds
11563 04:44:26.232544 <6>[ 64.920793] Freezing user space processes
11564 04:44:26.243580 <6>[ 64.926229] Freezing user space processes completed (elapsed 0.001 seconds)
11565 04:44:26.247325 <6>[ 64.933445] OOM killer disabled.
11566 04:44:26.250235 <6>[ 64.936925] Freezing remaining freezable tasks
11567 04:44:26.260468 <6>[ 64.942906] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11568 04:44:26.266769 <6>[ 64.950556] printk: Suspending console(s) (use no_console_suspend to debug)
11569 04:44:29.722086 <3>[ 68.174379] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11570 04:44:29.732101 <3>[ 68.174408] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11571 04:44:29.741799 <3>[ 68.174453] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11572 04:44:29.748485 <3>[ 68.174494] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11573 04:44:29.754865 <3>[ 68.174734] PM: Some devices failed to suspend, or early wake event detected
11574 04:44:29.758661 <6>[ 68.448390] OOM killer enabled.
11575 04:44:29.766889 <6>[ 68.451807] Restarting tasks ... done.
11576 04:44:29.769957 <5>[ 68.457694] random: crng reseeded on system resumption
11577 04:44:29.773666 <6>[ 68.463992] PM: suspend exit
11578 04:44:29.777270 rtcwake: write error
11579 04:44:29.784443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11580 04:44:29.784695 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11582 04:44:29.787844 rtcwake: assuming RTC uses UTC ...
11583 04:44:29.794410 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:35 2023
11584 04:44:29.807045 <6>[ 68.494043] PM: suspend entry (s2idle)
11585 04:44:29.810767 <6>[ 68.498105] Filesystems sync: 0.000 seconds
11586 04:44:29.814002 <6>[ 68.503130] Freezing user space processes
11587 04:44:29.825702 <6>[ 68.509065] Freezing user space processes completed (elapsed 0.001 seconds)
11588 04:44:29.829212 <6>[ 68.516294] OOM killer disabled.
11589 04:44:29.832396 <6>[ 68.519778] Freezing remaining freezable tasks
11590 04:44:29.842402 <6>[ 68.525857] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11591 04:44:29.849140 <6>[ 68.533528] printk: Suspending console(s) (use no_console_suspend to debug)
11592 04:44:33.305658 <3>[ 71.758375] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11593 04:44:33.315658 <3>[ 71.758404] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11594 04:44:33.326004 <3>[ 71.758449] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11595 04:44:33.332528 <3>[ 71.758490] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11596 04:44:33.339044 <3>[ 71.758774] PM: Some devices failed to suspend, or early wake event detected
11597 04:44:33.342627 <6>[ 72.032383] OOM killer enabled.
11598 04:44:33.350866 <6>[ 72.035799] Restarting tasks ... done.
11599 04:44:33.354306 <5>[ 72.041730] random: crng reseeded on system resumption
11600 04:44:33.357561 <6>[ 72.047970] PM: suspend exit
11601 04:44:33.361224 rtcwake: write error
11602 04:44:33.368770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11603 04:44:33.369517 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11605 04:44:33.371861 rtcwake: assuming RTC uses UTC ...
11606 04:44:33.378745 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:39 2023
11607 04:44:33.391424 <6>[ 72.078090] PM: suspend entry (s2idle)
11608 04:44:33.394942 <6>[ 72.082148] Filesystems sync: 0.000 seconds
11609 04:44:33.398056 <6>[ 72.087132] Freezing user space processes
11610 04:44:33.409566 <6>[ 72.093044] Freezing user space processes completed (elapsed 0.001 seconds)
11611 04:44:33.412831 <6>[ 72.100275] OOM killer disabled.
11612 04:44:33.416065 <6>[ 72.103756] Freezing remaining freezable tasks
11613 04:44:33.426407 <6>[ 72.109826] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11614 04:44:33.433222 <6>[ 72.117497] printk: Suspending console(s) (use no_console_suspend to debug)
11615 04:44:36.888984 <3>[ 75.342375] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11616 04:44:36.899248 <3>[ 75.342406] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11617 04:44:36.909149 <3>[ 75.342451] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11618 04:44:36.915703 <3>[ 75.342491] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11619 04:44:36.922710 <3>[ 75.342792] PM: Some devices failed to suspend, or early wake event detected
11620 04:44:36.925716 <6>[ 75.616380] OOM killer enabled.
11621 04:44:36.934765 <6>[ 75.619791] Restarting tasks ... done.
11622 04:44:36.937723 <5>[ 75.625890] random: crng reseeded on system resumption
11623 04:44:36.941694 <6>[ 75.632157] PM: suspend exit
11624 04:44:36.944904 rtcwake: write error
11625 04:44:36.953017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11626 04:44:36.953794 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11628 04:44:36.956004 rtcwake: assuming RTC uses UTC ...
11629 04:44:36.962843 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:42 2023
11630 04:44:36.975741 <6>[ 75.662602] PM: suspend entry (s2idle)
11631 04:44:36.978823 <6>[ 75.666667] Filesystems sync: 0.000 seconds
11632 04:44:36.981902 <6>[ 75.671640] Freezing user space processes
11633 04:44:36.994073 <6>[ 75.677557] Freezing user space processes completed (elapsed 0.001 seconds)
11634 04:44:36.997177 <6>[ 75.684786] OOM killer disabled.
11635 04:44:37.000612 <6>[ 75.688269] Freezing remaining freezable tasks
11636 04:44:37.010537 <6>[ 75.694321] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11637 04:44:37.017149 <6>[ 75.701985] printk: Suspending console(s) (use no_console_suspend to debug)
11638 04:44:40.468794 <3>[ 78.926405] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11639 04:44:40.478735 <3>[ 78.926443] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11640 04:44:40.488678 <3>[ 78.926491] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11641 04:44:40.495404 <3>[ 78.926538] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11642 04:44:40.502103 <3>[ 78.926872] PM: Some devices failed to suspend, or early wake event detected
11643 04:44:40.505137 <6>[ 79.196359] OOM killer enabled.
11644 04:44:40.513620 <6>[ 79.199770] Restarting tasks ... done.
11645 04:44:40.516639 <5>[ 79.205683] random: crng reseeded on system resumption
11646 04:44:40.520471 <6>[ 79.211889] PM: suspend exit
11647 04:44:40.523982 rtcwake: write error
11648 04:44:40.531364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11649 04:44:40.531651 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11651 04:44:40.534685 rtcwake: assuming RTC uses UTC ...
11652 04:44:40.541407 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:46 2023
11653 04:44:40.554051 <6>[ 79.241930] PM: suspend entry (s2idle)
11654 04:44:40.557613 <6>[ 79.246003] Filesystems sync: 0.000 seconds
11655 04:44:40.560425 <6>[ 79.251035] Freezing user space processes
11656 04:44:40.572021 <6>[ 79.256971] Freezing user space processes completed (elapsed 0.001 seconds)
11657 04:44:40.575623 <6>[ 79.264200] OOM killer disabled.
11658 04:44:40.579129 <6>[ 79.267682] Freezing remaining freezable tasks
11659 04:44:40.589098 <6>[ 79.273728] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11660 04:44:40.595508 <6>[ 79.281397] printk: Suspending console(s) (use no_console_suspend to debug)
11661 04:44:44.051864 <3>[ 82.510452] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11662 04:44:44.061973 <3>[ 82.510489] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11663 04:44:44.072053 <3>[ 82.510540] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11664 04:44:44.078851 <3>[ 82.510577] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11665 04:44:44.085583 <3>[ 82.510847] PM: Some devices failed to suspend, or early wake event detected
11666 04:44:44.088727 <6>[ 82.780342] OOM killer enabled.
11667 04:44:44.098841 <6>[ 82.783753] Restarting tasks ... done.
11668 04:44:44.105946 <5>[ 82.792720] random: crng reseeded on system resumption
11669 04:44:44.109075 <6>[ 82.799069] PM: suspend exit
11670 04:44:44.112774 rtcwake: write error
11671 04:44:44.119191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11672 04:44:44.119446 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11674 04:44:44.122151 rtcwake: assuming RTC uses UTC ...
11675 04:44:44.128757 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:49 2023
11676 04:44:44.140789 <6>[ 82.829104] PM: suspend entry (s2idle)
11677 04:44:44.144327 <6>[ 82.833185] Filesystems sync: 0.000 seconds
11678 04:44:44.150987 <6>[ 82.838266] Freezing user space processes
11679 04:44:44.157055 <6>[ 82.844197] Freezing user space processes completed (elapsed 0.001 seconds)
11680 04:44:44.160780 <6>[ 82.851427] OOM killer disabled.
11681 04:44:44.167282 <6>[ 82.854909] Freezing remaining freezable tasks
11682 04:44:44.174271 <6>[ 82.861033] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11683 04:44:44.184064 <6>[ 82.868706] printk: Suspending console(s) (use no_console_suspend to debug)
11684 04:44:47.635856 <3>[ 86.094374] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11685 04:44:47.645442 <3>[ 86.094403] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11686 04:44:47.655671 <3>[ 86.094448] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11687 04:44:47.662813 <3>[ 86.094488] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11688 04:44:47.669520 <3>[ 86.094727] PM: Some devices failed to suspend, or early wake event detected
11689 04:44:47.672362 <6>[ 86.364396] OOM killer enabled.
11690 04:44:47.680691 <6>[ 86.367809] Restarting tasks ... done.
11691 04:44:47.684018 <5>[ 86.373843] random: crng reseeded on system resumption
11692 04:44:47.687695 <6>[ 86.379981] PM: suspend exit
11693 04:44:47.691058 rtcwake: write error
11694 04:44:47.698884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11695 04:44:47.699146 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11697 04:44:47.701741 rtcwake: assuming RTC uses UTC ...
11698 04:44:47.708358 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:53 2023
11699 04:44:47.721221 <6>[ 86.409939] PM: suspend entry (s2idle)
11700 04:44:47.724831 <6>[ 86.414007] Filesystems sync: 0.000 seconds
11701 04:44:47.727612 <6>[ 86.419017] Freezing user space processes
11702 04:44:47.739238 <6>[ 86.424971] Freezing user space processes completed (elapsed 0.001 seconds)
11703 04:44:47.742828 <6>[ 86.432202] OOM killer disabled.
11704 04:44:47.745912 <6>[ 86.435683] Freezing remaining freezable tasks
11705 04:44:47.756329 <6>[ 86.441754] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11706 04:44:47.762857 <6>[ 86.449426] printk: Suspending console(s) (use no_console_suspend to debug)
11707 04:44:51.219298 <3>[ 89.678393] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11708 04:44:51.229560 <3>[ 89.678423] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11709 04:44:51.240016 <3>[ 89.678468] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11710 04:44:51.246565 <3>[ 89.678509] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11711 04:44:51.253397 <3>[ 89.678771] PM: Some devices failed to suspend, or early wake event detected
11712 04:44:51.256183 <6>[ 89.948381] OOM killer enabled.
11713 04:44:51.264804 <6>[ 89.951797] Restarting tasks ... done.
11714 04:44:51.267825 <5>[ 89.957742] random: crng reseeded on system resumption
11715 04:44:51.271581 <6>[ 89.963994] PM: suspend exit
11716 04:44:51.274929 rtcwake: write error
11717 04:44:51.282428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11718 04:44:51.283166 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11720 04:44:51.285840 rtcwake: assuming RTC uses UTC ...
11721 04:44:51.292263 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:44:57 2023
11722 04:44:51.305200 <6>[ 89.993979] PM: suspend entry (s2idle)
11723 04:44:51.309111 <6>[ 89.998042] Filesystems sync: 0.000 seconds
11724 04:44:51.311883 <6>[ 90.003052] Freezing user space processes
11725 04:44:51.323140 <6>[ 90.009004] Freezing user space processes completed (elapsed 0.001 seconds)
11726 04:44:51.326845 <6>[ 90.016236] OOM killer disabled.
11727 04:44:51.330019 <6>[ 90.019719] Freezing remaining freezable tasks
11728 04:44:51.340471 <6>[ 90.025789] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11729 04:44:51.347072 <6>[ 90.033468] printk: Suspending console(s) (use no_console_suspend to debug)
11730 04:44:54.803090 <3>[ 93.262443] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11731 04:44:54.812895 <3>[ 93.262481] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11732 04:44:54.823214 <3>[ 93.262532] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11733 04:44:54.829938 <3>[ 93.262576] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11734 04:44:54.836629 <3>[ 93.262898] PM: Some devices failed to suspend, or early wake event detected
11735 04:44:54.843526 <6>[ 93.532424] OOM killer enabled.
11736 04:44:54.849861 <6>[ 93.535834] Restarting tasks ... done.
11737 04:44:54.853378 <5>[ 93.542857] random: crng reseeded on system resumption
11738 04:44:54.856730 <6>[ 93.549198] PM: suspend exit
11739 04:44:54.859617 rtcwake: write error
11740 04:44:54.867658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11741 04:44:54.868126 + set +x
11742 04:44:54.868789 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11744 04:44:54.874839 <LAVA_SIGNAL_ENDRUN 0_sleep 11241319_1.5.2.3.1>
11745 04:44:54.875286 <LAVA_TEST_RUNNER EXIT>
11746 04:44:54.875880 Received signal: <ENDRUN> 0_sleep 11241319_1.5.2.3.1
11747 04:44:54.876283 Ending use of test pattern.
11748 04:44:54.876594 Ending test lava.0_sleep (11241319_1.5.2.3.1), duration 71.47
11750 04:44:54.878559 ok: lava_test_shell seems to have completed
11751 04:44:54.879515 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11752 04:44:54.879972 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11753 04:44:54.880395 end: 3 lava-test-retry (duration 00:01:12) [common]
11754 04:44:54.880865 start: 4 finalize (timeout 00:05:06) [common]
11755 04:44:54.881297 start: 4.1 power-off (timeout 00:00:30) [common]
11756 04:44:54.882038 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11757 04:44:55.001503 >> Command sent successfully.
11758 04:44:55.003885 Returned 0 in 0 seconds
11759 04:44:55.104633 end: 4.1 power-off (duration 00:00:00) [common]
11761 04:44:55.106047 start: 4.2 read-feedback (timeout 00:05:06) [common]
11762 04:44:55.107246 Listened to connection for namespace 'common' for up to 1s
11763 04:44:56.107844 Finalising connection for namespace 'common'
11764 04:44:56.108427 Disconnecting from shell: Finalise
11765 04:44:56.108844 / #
11766 04:44:56.209480 end: 4.2 read-feedback (duration 00:00:01) [common]
11767 04:44:56.209645 end: 4 finalize (duration 00:00:01) [common]
11768 04:44:56.209763 Cleaning after the job
11769 04:44:56.209866 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/ramdisk
11770 04:44:56.222772 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/kernel
11771 04:44:56.245103 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/dtb
11772 04:44:56.245350 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11241319/tftp-deploy-bswagsfv/modules
11773 04:44:56.252039 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11241319
11774 04:44:56.419608 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11241319
11775 04:44:56.419785 Job finished correctly