Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 19
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 28
- Errors: 1
1 12:19:37.267093 lava-dispatcher, installed at version: 2023.06
2 12:19:37.267338 start: 0 validate
3 12:19:37.267483 Start time: 2023-08-16 12:19:37.267475+00:00 (UTC)
4 12:19:37.267631 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:19:37.267782 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:19:37.528837 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:19:37.529540 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:20:18.292098 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:20:18.292832 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:20:18.546509 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:20:18.547294 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:20:24.806290 validate duration: 47.54
14 12:20:24.806553 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:20:24.806648 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:20:24.806734 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:20:24.806861 Not decompressing ramdisk as can be used compressed.
18 12:20:24.806948 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 12:20:24.807014 saving as /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/ramdisk/rootfs.cpio.gz
20 12:20:24.807078 total size: 8181372 (7 MB)
21 12:20:25.063754 progress 0 % (0 MB)
22 12:20:25.066198 progress 5 % (0 MB)
23 12:20:25.068368 progress 10 % (0 MB)
24 12:20:25.070675 progress 15 % (1 MB)
25 12:20:25.072821 progress 20 % (1 MB)
26 12:20:25.075134 progress 25 % (1 MB)
27 12:20:25.077268 progress 30 % (2 MB)
28 12:20:25.079528 progress 35 % (2 MB)
29 12:20:25.081651 progress 40 % (3 MB)
30 12:20:25.083900 progress 45 % (3 MB)
31 12:20:25.086033 progress 50 % (3 MB)
32 12:20:25.088289 progress 55 % (4 MB)
33 12:20:25.090333 progress 60 % (4 MB)
34 12:20:25.092581 progress 65 % (5 MB)
35 12:20:25.094625 progress 70 % (5 MB)
36 12:20:25.096862 progress 75 % (5 MB)
37 12:20:25.098906 progress 80 % (6 MB)
38 12:20:25.101140 progress 85 % (6 MB)
39 12:20:25.103280 progress 90 % (7 MB)
40 12:20:25.105543 progress 95 % (7 MB)
41 12:20:25.107691 progress 100 % (7 MB)
42 12:20:25.107891 7 MB downloaded in 0.30 s (25.94 MB/s)
43 12:20:25.108087 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:20:25.108325 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:20:25.108409 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:20:25.108491 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:20:25.108627 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:20:25.108697 saving as /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/kernel/Image
50 12:20:25.108756 total size: 49220096 (46 MB)
51 12:20:25.108815 No compression specified
52 12:20:25.109962 progress 0 % (0 MB)
53 12:20:25.122970 progress 5 % (2 MB)
54 12:20:25.135765 progress 10 % (4 MB)
55 12:20:25.148917 progress 15 % (7 MB)
56 12:20:25.162405 progress 20 % (9 MB)
57 12:20:25.175421 progress 25 % (11 MB)
58 12:20:25.188793 progress 30 % (14 MB)
59 12:20:25.201924 progress 35 % (16 MB)
60 12:20:25.214639 progress 40 % (18 MB)
61 12:20:25.227307 progress 45 % (21 MB)
62 12:20:25.240204 progress 50 % (23 MB)
63 12:20:25.252968 progress 55 % (25 MB)
64 12:20:25.265972 progress 60 % (28 MB)
65 12:20:25.278932 progress 65 % (30 MB)
66 12:20:25.291865 progress 70 % (32 MB)
67 12:20:25.305003 progress 75 % (35 MB)
68 12:20:25.317959 progress 80 % (37 MB)
69 12:20:25.330691 progress 85 % (39 MB)
70 12:20:25.343500 progress 90 % (42 MB)
71 12:20:25.356399 progress 95 % (44 MB)
72 12:20:25.369418 progress 100 % (46 MB)
73 12:20:25.369577 46 MB downloaded in 0.26 s (179.97 MB/s)
74 12:20:25.369732 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:20:25.369963 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:20:25.370053 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:20:25.370138 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:20:25.370292 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:20:25.370362 saving as /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/dtb/mt8192-asurada-spherion-r0.dtb
81 12:20:25.370421 total size: 47278 (0 MB)
82 12:20:25.370482 No compression specified
83 12:20:25.371560 progress 69 % (0 MB)
84 12:20:25.371833 progress 100 % (0 MB)
85 12:20:25.372000 0 MB downloaded in 0.00 s (28.61 MB/s)
86 12:20:25.372127 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:20:25.372355 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:20:25.372439 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:20:25.372520 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:20:25.372635 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:20:25.372702 saving as /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/modules/modules.tar
93 12:20:25.372761 total size: 8615968 (8 MB)
94 12:20:25.372820 Using unxz to decompress xz
95 12:20:25.377108 progress 0 % (0 MB)
96 12:20:25.399595 progress 5 % (0 MB)
97 12:20:25.423151 progress 10 % (0 MB)
98 12:20:25.450644 progress 15 % (1 MB)
99 12:20:25.477073 progress 20 % (1 MB)
100 12:20:25.504788 progress 25 % (2 MB)
101 12:20:25.532784 progress 30 % (2 MB)
102 12:20:25.560973 progress 35 % (2 MB)
103 12:20:25.586138 progress 40 % (3 MB)
104 12:20:25.610493 progress 45 % (3 MB)
105 12:20:25.636507 progress 50 % (4 MB)
106 12:20:25.661540 progress 55 % (4 MB)
107 12:20:25.685768 progress 60 % (4 MB)
108 12:20:25.708669 progress 65 % (5 MB)
109 12:20:25.736291 progress 70 % (5 MB)
110 12:20:25.760859 progress 75 % (6 MB)
111 12:20:25.787401 progress 80 % (6 MB)
112 12:20:25.817161 progress 85 % (7 MB)
113 12:20:25.844074 progress 90 % (7 MB)
114 12:20:25.868509 progress 95 % (7 MB)
115 12:20:25.892690 progress 100 % (8 MB)
116 12:20:25.899170 8 MB downloaded in 0.53 s (15.61 MB/s)
117 12:20:25.899495 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:20:25.899897 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:20:25.900080 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:20:25.900224 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:20:25.900352 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:20:25.900476 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:20:25.900766 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib
125 12:20:25.900957 makedir: /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin
126 12:20:25.901104 makedir: /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/tests
127 12:20:25.901256 makedir: /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/results
128 12:20:25.901415 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-add-keys
129 12:20:25.901573 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-add-sources
130 12:20:25.901712 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-background-process-start
131 12:20:25.901843 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-background-process-stop
132 12:20:25.901970 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-common-functions
133 12:20:25.902094 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-echo-ipv4
134 12:20:25.902220 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-install-packages
135 12:20:25.902345 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-installed-packages
136 12:20:25.902470 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-os-build
137 12:20:25.902594 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-probe-channel
138 12:20:25.902718 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-probe-ip
139 12:20:25.902843 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-target-ip
140 12:20:25.902968 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-target-mac
141 12:20:25.903093 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-target-storage
142 12:20:25.903222 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-test-case
143 12:20:25.903348 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-test-event
144 12:20:25.903471 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-test-feedback
145 12:20:25.903596 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-test-raise
146 12:20:25.903722 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-test-reference
147 12:20:25.903846 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-test-runner
148 12:20:25.903979 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-test-set
149 12:20:25.904107 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-test-shell
150 12:20:25.904235 Updating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-install-packages (oe)
151 12:20:25.904387 Updating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/bin/lava-installed-packages (oe)
152 12:20:25.904508 Creating /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/environment
153 12:20:25.904617 LAVA metadata
154 12:20:25.904692 - LAVA_JOB_ID=11299281
155 12:20:25.904757 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:20:25.904858 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:20:25.904923 skipped lava-vland-overlay
158 12:20:25.904997 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:20:25.905075 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:20:25.905140 skipped lava-multinode-overlay
161 12:20:25.905211 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:20:25.905294 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:20:25.905369 Loading test definitions
164 12:20:25.905459 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:20:25.905532 Using /lava-11299281 at stage 0
166 12:20:25.905844 uuid=11299281_1.5.2.3.1 testdef=None
167 12:20:25.905931 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:20:25.906015 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:20:25.906548 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:20:25.906766 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:20:25.907413 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:20:25.907637 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:20:25.908273 runner path: /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/0/tests/0_dmesg test_uuid 11299281_1.5.2.3.1
176 12:20:25.908427 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:20:25.908654 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 12:20:25.908725 Using /lava-11299281 at stage 1
180 12:20:25.909024 uuid=11299281_1.5.2.3.5 testdef=None
181 12:20:25.909110 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 12:20:25.909194 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 12:20:25.909814 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 12:20:25.910126 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 12:20:25.911254 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 12:20:25.911481 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 12:20:25.912157 runner path: /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/1/tests/1_bootrr test_uuid 11299281_1.5.2.3.5
190 12:20:25.912308 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 12:20:25.912512 Creating lava-test-runner.conf files
193 12:20:25.912575 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/0 for stage 0
194 12:20:25.912664 - 0_dmesg
195 12:20:25.912744 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11299281/lava-overlay-qhlvz6ib/lava-11299281/1 for stage 1
196 12:20:25.912835 - 1_bootrr
197 12:20:25.912928 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 12:20:25.913015 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 12:20:25.921154 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 12:20:25.921262 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 12:20:25.921348 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 12:20:25.921431 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 12:20:25.921516 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 12:20:26.173879 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 12:20:26.174266 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 12:20:26.174384 extracting modules file /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11299281/extract-overlay-ramdisk-33mlfugt/ramdisk
207 12:20:26.392720 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 12:20:26.392879 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 12:20:26.392978 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299281/compress-overlay-1f5lmoj1/overlay-1.5.2.4.tar.gz to ramdisk
210 12:20:26.393051 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299281/compress-overlay-1f5lmoj1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11299281/extract-overlay-ramdisk-33mlfugt/ramdisk
211 12:20:26.401395 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 12:20:26.401506 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 12:20:26.401592 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 12:20:26.401681 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 12:20:26.401758 Building ramdisk /var/lib/lava/dispatcher/tmp/11299281/extract-overlay-ramdisk-33mlfugt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11299281/extract-overlay-ramdisk-33mlfugt/ramdisk
216 12:20:26.798754 >> 145124 blocks
217 12:20:29.090259 rename /var/lib/lava/dispatcher/tmp/11299281/extract-overlay-ramdisk-33mlfugt/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/ramdisk/ramdisk.cpio.gz
218 12:20:29.090716 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 12:20:29.090844 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 12:20:29.090947 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 12:20:29.091068 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/kernel/Image'
222 12:20:41.238234 Returned 0 in 12 seconds
223 12:20:41.338975 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/kernel/image.itb
224 12:20:41.742521 output: FIT description: Kernel Image image with one or more FDT blobs
225 12:20:41.742930 output: Created: Wed Aug 16 13:20:41 2023
226 12:20:41.743048 output: Image 0 (kernel-1)
227 12:20:41.743120 output: Description:
228 12:20:41.743187 output: Created: Wed Aug 16 13:20:41 2023
229 12:20:41.743248 output: Type: Kernel Image
230 12:20:41.743310 output: Compression: lzma compressed
231 12:20:41.743379 output: Data Size: 11040376 Bytes = 10781.62 KiB = 10.53 MiB
232 12:20:41.743472 output: Architecture: AArch64
233 12:20:41.743562 output: OS: Linux
234 12:20:41.743671 output: Load Address: 0x00000000
235 12:20:41.743756 output: Entry Point: 0x00000000
236 12:20:41.743840 output: Hash algo: crc32
237 12:20:41.743950 output: Hash value: 79630449
238 12:20:41.744041 output: Image 1 (fdt-1)
239 12:20:41.744098 output: Description: mt8192-asurada-spherion-r0
240 12:20:41.744160 output: Created: Wed Aug 16 13:20:41 2023
241 12:20:41.744216 output: Type: Flat Device Tree
242 12:20:41.744270 output: Compression: uncompressed
243 12:20:41.744323 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 12:20:41.744377 output: Architecture: AArch64
245 12:20:41.744430 output: Hash algo: crc32
246 12:20:41.744483 output: Hash value: cc4352de
247 12:20:41.744536 output: Image 2 (ramdisk-1)
248 12:20:41.744588 output: Description: unavailable
249 12:20:41.744640 output: Created: Wed Aug 16 13:20:41 2023
250 12:20:41.744694 output: Type: RAMDisk Image
251 12:20:41.744757 output: Compression: Unknown Compression
252 12:20:41.744810 output: Data Size: 21359021 Bytes = 20858.42 KiB = 20.37 MiB
253 12:20:41.744864 output: Architecture: AArch64
254 12:20:41.744916 output: OS: Linux
255 12:20:41.744970 output: Load Address: unavailable
256 12:20:41.745022 output: Entry Point: unavailable
257 12:20:41.745075 output: Hash algo: crc32
258 12:20:41.745127 output: Hash value: 704b0416
259 12:20:41.745180 output: Default Configuration: 'conf-1'
260 12:20:41.745233 output: Configuration 0 (conf-1)
261 12:20:41.745294 output: Description: mt8192-asurada-spherion-r0
262 12:20:41.745348 output: Kernel: kernel-1
263 12:20:41.745409 output: Init Ramdisk: ramdisk-1
264 12:20:41.745463 output: FDT: fdt-1
265 12:20:41.745516 output: Loadables: kernel-1
266 12:20:41.745569 output:
267 12:20:41.745815 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 12:20:41.745958 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 12:20:41.746100 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 12:20:41.746232 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
271 12:20:41.746343 No LXC device requested
272 12:20:41.746460 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 12:20:41.746580 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
274 12:20:41.746690 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 12:20:41.746788 Checking files for TFTP limit of 4294967296 bytes.
276 12:20:41.747349 end: 1 tftp-deploy (duration 00:00:17) [common]
277 12:20:41.747452 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 12:20:41.747544 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 12:20:41.747665 substitutions:
280 12:20:41.747739 - {DTB}: 11299281/tftp-deploy-fog2iav_/dtb/mt8192-asurada-spherion-r0.dtb
281 12:20:41.747835 - {INITRD}: 11299281/tftp-deploy-fog2iav_/ramdisk/ramdisk.cpio.gz
282 12:20:41.747965 - {KERNEL}: 11299281/tftp-deploy-fog2iav_/kernel/Image
283 12:20:41.748054 - {LAVA_MAC}: None
284 12:20:41.748140 - {PRESEED_CONFIG}: None
285 12:20:41.748224 - {PRESEED_LOCAL}: None
286 12:20:41.748309 - {RAMDISK}: 11299281/tftp-deploy-fog2iav_/ramdisk/ramdisk.cpio.gz
287 12:20:41.748393 - {ROOT_PART}: None
288 12:20:41.748462 - {ROOT}: None
289 12:20:41.748518 - {SERVER_IP}: 192.168.201.1
290 12:20:41.748573 - {TEE}: None
291 12:20:41.748627 Parsed boot commands:
292 12:20:41.748683 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 12:20:41.748874 Parsed boot commands: tftpboot 192.168.201.1 11299281/tftp-deploy-fog2iav_/kernel/image.itb 11299281/tftp-deploy-fog2iav_/kernel/cmdline
294 12:20:41.748965 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 12:20:41.749054 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 12:20:41.749167 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 12:20:41.749291 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 12:20:41.749394 Not connected, no need to disconnect.
299 12:20:41.749502 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 12:20:41.749614 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 12:20:41.749712 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
302 12:20:41.753962 Setting prompt string to ['lava-test: # ']
303 12:20:41.754355 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 12:20:41.754474 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 12:20:41.754574 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 12:20:41.754845 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 12:20:41.755057 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
308 12:20:46.891490 >> Command sent successfully.
309 12:20:46.893996 Returned 0 in 5 seconds
310 12:20:46.994393 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 12:20:46.994731 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 12:20:46.994835 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 12:20:46.994932 Setting prompt string to 'Starting depthcharge on Spherion...'
315 12:20:46.995005 Changing prompt to 'Starting depthcharge on Spherion...'
316 12:20:46.995074 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 12:20:46.995345 [Enter `^Ec?' for help]
318 12:20:47.168749
319 12:20:47.168917
320 12:20:47.168994 F0: 102B 0000
321 12:20:47.169059
322 12:20:47.169119 F3: 1001 0000 [0200]
323 12:20:47.169178
324 12:20:47.172994 F3: 1001 0000
325 12:20:47.173089
326 12:20:47.173157 F7: 102D 0000
327 12:20:47.173218
328 12:20:47.173278 F1: 0000 0000
329 12:20:47.173336
330 12:20:47.176743 V0: 0000 0000 [0001]
331 12:20:47.176836
332 12:20:47.176903 00: 0007 8000
333 12:20:47.176969
334 12:20:47.180786 01: 0000 0000
335 12:20:47.180883
336 12:20:47.180952 BP: 0C00 0209 [0000]
337 12:20:47.181015
338 12:20:47.181074 G0: 1182 0000
339 12:20:47.184440
340 12:20:47.184526 EC: 0000 0021 [4000]
341 12:20:47.184593
342 12:20:47.184655 S7: 0000 0000 [0000]
343 12:20:47.187634
344 12:20:47.187727 CC: 0000 0000 [0001]
345 12:20:47.187795
346 12:20:47.191505 T0: 0000 0040 [010F]
347 12:20:47.191595
348 12:20:47.191671 Jump to BL
349 12:20:47.191733
350 12:20:47.216477
351 12:20:47.216636
352 12:20:47.216704
353 12:20:47.222785 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 12:20:47.226373 ARM64: Exception handlers installed.
355 12:20:47.229860 ARM64: Testing exception
356 12:20:47.233359 ARM64: Done test exception
357 12:20:47.240864 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 12:20:47.250849 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 12:20:47.257651 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 12:20:47.267891 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 12:20:47.274489 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 12:20:47.280594 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 12:20:47.293253 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 12:20:47.298872 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 12:20:47.318514 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 12:20:47.321557 WDT: Last reset was cold boot
367 12:20:47.325112 SPI1(PAD0) initialized at 2873684 Hz
368 12:20:47.328617 SPI5(PAD0) initialized at 992727 Hz
369 12:20:47.332021 VBOOT: Loading verstage.
370 12:20:47.338225 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 12:20:47.341630 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 12:20:47.345265 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 12:20:47.347974 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 12:20:47.356221 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 12:20:47.362234 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 12:20:47.373407 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 12:20:47.373496
378 12:20:47.373562
379 12:20:47.383019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 12:20:47.386807 ARM64: Exception handlers installed.
381 12:20:47.389890 ARM64: Testing exception
382 12:20:47.389975 ARM64: Done test exception
383 12:20:47.397489 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 12:20:47.400888 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 12:20:47.414456 Probing TPM: . done!
386 12:20:47.414542 TPM ready after 0 ms
387 12:20:47.425026 Connected to device vid:did:rid of 1ae0:0028:00
388 12:20:47.430666 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 12:20:47.491787 Initialized TPM device CR50 revision 0
390 12:20:47.502682 tlcl_send_startup: Startup return code is 0
391 12:20:47.502787 TPM: setup succeeded
392 12:20:47.513672 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 12:20:47.522747 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 12:20:47.535387 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 12:20:47.543007 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 12:20:47.547261 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 12:20:47.550721 in-header: 03 07 00 00 08 00 00 00
398 12:20:47.554588 in-data: aa e4 47 04 13 02 00 00
399 12:20:47.557964 Chrome EC: UHEPI supported
400 12:20:47.561486 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 12:20:47.564813 in-header: 03 95 00 00 08 00 00 00
402 12:20:47.568704 in-data: 18 20 20 08 00 00 00 00
403 12:20:47.573058 Phase 1
404 12:20:47.576513 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 12:20:47.580247 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 12:20:47.586360 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 12:20:47.590234 Recovery requested (1009000e)
408 12:20:47.598428 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 12:20:47.603821 tlcl_extend: response is 0
410 12:20:47.613197 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 12:20:47.618442 tlcl_extend: response is 0
412 12:20:47.625072 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 12:20:47.645188 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 12:20:47.652015 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 12:20:47.652107
416 12:20:47.652173
417 12:20:47.661809 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 12:20:47.665270 ARM64: Exception handlers installed.
419 12:20:47.668829 ARM64: Testing exception
420 12:20:47.668912 ARM64: Done test exception
421 12:20:47.690765 pmic_efuse_setting: Set efuses in 11 msecs
422 12:20:47.694070 pmwrap_interface_init: Select PMIF_VLD_RDY
423 12:20:47.700494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 12:20:47.703882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 12:20:47.710934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 12:20:47.714417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 12:20:47.718149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 12:20:47.725624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 12:20:47.729177 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 12:20:47.733146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 12:20:47.737236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 12:20:47.744169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 12:20:47.748260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 12:20:47.751837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 12:20:47.755048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 12:20:47.762756 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 12:20:47.770325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 12:20:47.773909 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 12:20:47.781552 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 12:20:47.784530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 12:20:47.792471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 12:20:47.796066 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 12:20:47.802982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 12:20:47.807574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 12:20:47.814701 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 12:20:47.818002 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 12:20:47.825295 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 12:20:47.829231 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 12:20:47.836251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 12:20:47.839819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 12:20:47.843642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 12:20:47.851168 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 12:20:47.853928 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 12:20:47.861457 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 12:20:47.864855 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 12:20:47.868692 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 12:20:47.876066 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 12:20:47.879598 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 12:20:47.883118 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 12:20:47.891118 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 12:20:47.894513 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 12:20:47.897796 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 12:20:47.902596 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 12:20:47.909576 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 12:20:47.912912 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 12:20:47.917048 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 12:20:47.920302 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 12:20:47.924901 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 12:20:47.927407 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 12:20:47.934934 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 12:20:47.938908 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 12:20:47.942246 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 12:20:47.945827 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 12:20:47.953235 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 12:20:47.960659 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 12:20:47.968241 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 12:20:47.975457 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 12:20:47.982013 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 12:20:47.990166 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 12:20:47.993855 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 12:20:47.997195 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 12:20:48.004285 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x17
483 12:20:48.007562 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 12:20:48.016161 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
485 12:20:48.019375 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 12:20:48.028491 [RTC]rtc_get_frequency_meter,154: input=15, output=852
487 12:20:48.038446 [RTC]rtc_get_frequency_meter,154: input=7, output=723
488 12:20:48.047129 [RTC]rtc_get_frequency_meter,154: input=11, output=787
489 12:20:48.057291 [RTC]rtc_get_frequency_meter,154: input=13, output=819
490 12:20:48.066920 [RTC]rtc_get_frequency_meter,154: input=12, output=803
491 12:20:48.075607 [RTC]rtc_get_frequency_meter,154: input=11, output=788
492 12:20:48.085377 [RTC]rtc_get_frequency_meter,154: input=12, output=804
493 12:20:48.088352 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
494 12:20:48.095870 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
495 12:20:48.099482 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 12:20:48.103020 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 12:20:48.107330 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 12:20:48.111420 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 12:20:48.114691 ADC[4]: Raw value=904064 ID=7
500 12:20:48.117682 ADC[3]: Raw value=213916 ID=1
501 12:20:48.117773 RAM Code: 0x71
502 12:20:48.121249 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 12:20:48.128881 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 12:20:48.136865 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 12:20:48.144053 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 12:20:48.147172 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 12:20:48.150515 in-header: 03 07 00 00 08 00 00 00
508 12:20:48.154402 in-data: aa e4 47 04 13 02 00 00
509 12:20:48.154493 Chrome EC: UHEPI supported
510 12:20:48.161949 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 12:20:48.165788 in-header: 03 95 00 00 08 00 00 00
512 12:20:48.169421 in-data: 18 20 20 08 00 00 00 00
513 12:20:48.173280 MRC: failed to locate region type 0.
514 12:20:48.180313 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 12:20:48.180442 DRAM-K: Running full calibration
516 12:20:48.188414 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 12:20:48.192222 header.status = 0x0
518 12:20:48.192336 header.version = 0x6 (expected: 0x6)
519 12:20:48.195176 header.size = 0xd00 (expected: 0xd00)
520 12:20:48.199369 header.flags = 0x0
521 12:20:48.202788 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 12:20:48.222779 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
523 12:20:48.230251 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 12:20:48.230399 dram_init: ddr_geometry: 2
525 12:20:48.234041 [EMI] MDL number = 2
526 12:20:48.237269 [EMI] Get MDL freq = 0
527 12:20:48.237371 dram_init: ddr_type: 0
528 12:20:48.241455 is_discrete_lpddr4: 1
529 12:20:48.244675 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 12:20:48.244768
531 12:20:48.244834
532 12:20:48.244896 [Bian_co] ETT version 0.0.0.1
533 12:20:48.252171 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 12:20:48.252267
535 12:20:48.255680 dramc_set_vcore_voltage set vcore to 650000
536 12:20:48.255764 Read voltage for 800, 4
537 12:20:48.259267 Vio18 = 0
538 12:20:48.259352 Vcore = 650000
539 12:20:48.259480 Vdram = 0
540 12:20:48.262801 Vddq = 0
541 12:20:48.262884 Vmddr = 0
542 12:20:48.262949 dram_init: config_dvfs: 1
543 12:20:48.269370 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 12:20:48.275790 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 12:20:48.279294 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 12:20:48.283270 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 12:20:48.286910 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 12:20:48.290803 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 12:20:48.290891 MEM_TYPE=3, freq_sel=18
550 12:20:48.294803 sv_algorithm_assistance_LP4_1600
551 12:20:48.297914 ============ PULL DRAM RESETB DOWN ============
552 12:20:48.304756 ========== PULL DRAM RESETB DOWN end =========
553 12:20:48.307850 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 12:20:48.311288 ===================================
555 12:20:48.315482 LPDDR4 DRAM CONFIGURATION
556 12:20:48.317890 ===================================
557 12:20:48.317975 EX_ROW_EN[0] = 0x0
558 12:20:48.321265 EX_ROW_EN[1] = 0x0
559 12:20:48.321350 LP4Y_EN = 0x0
560 12:20:48.324643 WORK_FSP = 0x0
561 12:20:48.324734 WL = 0x2
562 12:20:48.328304 RL = 0x2
563 12:20:48.328438 BL = 0x2
564 12:20:48.331362 RPST = 0x0
565 12:20:48.331478 RD_PRE = 0x0
566 12:20:48.335035 WR_PRE = 0x1
567 12:20:48.335134 WR_PST = 0x0
568 12:20:48.339019 DBI_WR = 0x0
569 12:20:48.339129 DBI_RD = 0x0
570 12:20:48.341521 OTF = 0x1
571 12:20:48.345320 ===================================
572 12:20:48.347693 ===================================
573 12:20:48.347778 ANA top config
574 12:20:48.351315 ===================================
575 12:20:48.354625 DLL_ASYNC_EN = 0
576 12:20:48.357906 ALL_SLAVE_EN = 1
577 12:20:48.361502 NEW_RANK_MODE = 1
578 12:20:48.361588 DLL_IDLE_MODE = 1
579 12:20:48.365239 LP45_APHY_COMB_EN = 1
580 12:20:48.368250 TX_ODT_DIS = 1
581 12:20:48.371377 NEW_8X_MODE = 1
582 12:20:48.374651 ===================================
583 12:20:48.377449 ===================================
584 12:20:48.381053 data_rate = 1600
585 12:20:48.384934 CKR = 1
586 12:20:48.385020 DQ_P2S_RATIO = 8
587 12:20:48.387472 ===================================
588 12:20:48.391281 CA_P2S_RATIO = 8
589 12:20:48.394742 DQ_CA_OPEN = 0
590 12:20:48.398215 DQ_SEMI_OPEN = 0
591 12:20:48.401610 CA_SEMI_OPEN = 0
592 12:20:48.401695 CA_FULL_RATE = 0
593 12:20:48.404799 DQ_CKDIV4_EN = 1
594 12:20:48.408124 CA_CKDIV4_EN = 1
595 12:20:48.411569 CA_PREDIV_EN = 0
596 12:20:48.414885 PH8_DLY = 0
597 12:20:48.418364 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 12:20:48.418447 DQ_AAMCK_DIV = 4
599 12:20:48.421753 CA_AAMCK_DIV = 4
600 12:20:48.425007 CA_ADMCK_DIV = 4
601 12:20:48.427865 DQ_TRACK_CA_EN = 0
602 12:20:48.431544 CA_PICK = 800
603 12:20:48.434331 CA_MCKIO = 800
604 12:20:48.434414 MCKIO_SEMI = 0
605 12:20:48.438474 PLL_FREQ = 3068
606 12:20:48.442069 DQ_UI_PI_RATIO = 32
607 12:20:48.445352 CA_UI_PI_RATIO = 0
608 12:20:48.449731 ===================================
609 12:20:48.453499 ===================================
610 12:20:48.453584 memory_type:LPDDR4
611 12:20:48.456577 GP_NUM : 10
612 12:20:48.456660 SRAM_EN : 1
613 12:20:48.460474 MD32_EN : 0
614 12:20:48.463928 ===================================
615 12:20:48.464029 [ANA_INIT] >>>>>>>>>>>>>>
616 12:20:48.467817 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 12:20:48.471725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 12:20:48.474824 ===================================
619 12:20:48.478089 data_rate = 1600,PCW = 0X7600
620 12:20:48.481362 ===================================
621 12:20:48.484745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 12:20:48.491318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 12:20:48.494445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 12:20:48.501242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 12:20:48.504241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 12:20:48.508241 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 12:20:48.508324 [ANA_INIT] flow start
628 12:20:48.511228 [ANA_INIT] PLL >>>>>>>>
629 12:20:48.514098 [ANA_INIT] PLL <<<<<<<<
630 12:20:48.514180 [ANA_INIT] MIDPI >>>>>>>>
631 12:20:48.517837 [ANA_INIT] MIDPI <<<<<<<<
632 12:20:48.521360 [ANA_INIT] DLL >>>>>>>>
633 12:20:48.521443 [ANA_INIT] flow end
634 12:20:48.527783 ============ LP4 DIFF to SE enter ============
635 12:20:48.531021 ============ LP4 DIFF to SE exit ============
636 12:20:48.534511 [ANA_INIT] <<<<<<<<<<<<<
637 12:20:48.537295 [Flow] Enable top DCM control >>>>>
638 12:20:48.540885 [Flow] Enable top DCM control <<<<<
639 12:20:48.544372 Enable DLL master slave shuffle
640 12:20:48.547272 ==============================================================
641 12:20:48.550625 Gating Mode config
642 12:20:48.554096 ==============================================================
643 12:20:48.557086 Config description:
644 12:20:48.567731 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 12:20:48.573915 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 12:20:48.577171 SELPH_MODE 0: By rank 1: By Phase
647 12:20:48.583539 ==============================================================
648 12:20:48.587186 GAT_TRACK_EN = 1
649 12:20:48.590314 RX_GATING_MODE = 2
650 12:20:48.593763 RX_GATING_TRACK_MODE = 2
651 12:20:48.597305 SELPH_MODE = 1
652 12:20:48.600365 PICG_EARLY_EN = 1
653 12:20:48.603828 VALID_LAT_VALUE = 1
654 12:20:48.607057 ==============================================================
655 12:20:48.610760 Enter into Gating configuration >>>>
656 12:20:48.614163 Exit from Gating configuration <<<<
657 12:20:48.617295 Enter into DVFS_PRE_config >>>>>
658 12:20:48.626952 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 12:20:48.630573 Exit from DVFS_PRE_config <<<<<
660 12:20:48.633606 Enter into PICG configuration >>>>
661 12:20:48.636771 Exit from PICG configuration <<<<
662 12:20:48.640397 [RX_INPUT] configuration >>>>>
663 12:20:48.643543 [RX_INPUT] configuration <<<<<
664 12:20:48.650388 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 12:20:48.653404 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 12:20:48.659851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 12:20:48.666386 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 12:20:48.672989 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 12:20:48.679766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 12:20:48.683450 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 12:20:48.686502 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 12:20:48.689615 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 12:20:48.696423 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 12:20:48.699567 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 12:20:48.702939 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 12:20:48.706641 ===================================
677 12:20:48.709746 LPDDR4 DRAM CONFIGURATION
678 12:20:48.713452 ===================================
679 12:20:48.713538 EX_ROW_EN[0] = 0x0
680 12:20:48.716199 EX_ROW_EN[1] = 0x0
681 12:20:48.719434 LP4Y_EN = 0x0
682 12:20:48.719516 WORK_FSP = 0x0
683 12:20:48.723245 WL = 0x2
684 12:20:48.723329 RL = 0x2
685 12:20:48.726201 BL = 0x2
686 12:20:48.726319 RPST = 0x0
687 12:20:48.729414 RD_PRE = 0x0
688 12:20:48.729499 WR_PRE = 0x1
689 12:20:48.732994 WR_PST = 0x0
690 12:20:48.733078 DBI_WR = 0x0
691 12:20:48.736332 DBI_RD = 0x0
692 12:20:48.736417 OTF = 0x1
693 12:20:48.740299 ===================================
694 12:20:48.742972 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 12:20:48.749699 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 12:20:48.753480 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:20:48.756251 ===================================
698 12:20:48.759304 LPDDR4 DRAM CONFIGURATION
699 12:20:48.762616 ===================================
700 12:20:48.762702 EX_ROW_EN[0] = 0x10
701 12:20:48.766507 EX_ROW_EN[1] = 0x0
702 12:20:48.766592 LP4Y_EN = 0x0
703 12:20:48.769688 WORK_FSP = 0x0
704 12:20:48.772831 WL = 0x2
705 12:20:48.772914 RL = 0x2
706 12:20:48.777076 BL = 0x2
707 12:20:48.777160 RPST = 0x0
708 12:20:48.779276 RD_PRE = 0x0
709 12:20:48.779369 WR_PRE = 0x1
710 12:20:48.783211 WR_PST = 0x0
711 12:20:48.783298 DBI_WR = 0x0
712 12:20:48.786223 DBI_RD = 0x0
713 12:20:48.786306 OTF = 0x1
714 12:20:48.789315 ===================================
715 12:20:48.796173 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 12:20:48.800510 nWR fixed to 40
717 12:20:48.803232 [ModeRegInit_LP4] CH0 RK0
718 12:20:48.803317 [ModeRegInit_LP4] CH0 RK1
719 12:20:48.806685 [ModeRegInit_LP4] CH1 RK0
720 12:20:48.810020 [ModeRegInit_LP4] CH1 RK1
721 12:20:48.810103 match AC timing 13
722 12:20:48.816844 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 12:20:48.820444 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 12:20:48.823855 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 12:20:48.829815 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 12:20:48.833174 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 12:20:48.833261 [EMI DOE] emi_dcm 0
728 12:20:48.840014 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 12:20:48.840101 ==
730 12:20:48.843426 Dram Type= 6, Freq= 0, CH_0, rank 0
731 12:20:48.846740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 12:20:48.846824 ==
733 12:20:48.853799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 12:20:48.859810 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 12:20:48.867347 [CA 0] Center 37 (7~68) winsize 62
736 12:20:48.871225 [CA 1] Center 37 (7~68) winsize 62
737 12:20:48.873884 [CA 2] Center 34 (4~65) winsize 62
738 12:20:48.877186 [CA 3] Center 35 (4~66) winsize 63
739 12:20:48.880733 [CA 4] Center 33 (3~64) winsize 62
740 12:20:48.884179 [CA 5] Center 33 (3~64) winsize 62
741 12:20:48.884263
742 12:20:48.887775 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 12:20:48.887859
744 12:20:48.891419 [CATrainingPosCal] consider 1 rank data
745 12:20:48.894488 u2DelayCellTimex100 = 270/100 ps
746 12:20:48.897074 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
747 12:20:48.900561 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
748 12:20:48.907354 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 12:20:48.911099 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
750 12:20:48.913752 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 12:20:48.917666 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 12:20:48.917751
753 12:20:48.920804 CA PerBit enable=1, Macro0, CA PI delay=33
754 12:20:48.920887
755 12:20:48.924102 [CBTSetCACLKResult] CA Dly = 33
756 12:20:48.924186 CS Dly: 5 (0~36)
757 12:20:48.927791 ==
758 12:20:48.930920 Dram Type= 6, Freq= 0, CH_0, rank 1
759 12:20:48.933958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 12:20:48.934045 ==
761 12:20:48.937299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 12:20:48.943846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 12:20:48.953914 [CA 0] Center 38 (7~69) winsize 63
764 12:20:48.957374 [CA 1] Center 37 (7~68) winsize 62
765 12:20:48.960506 [CA 2] Center 35 (4~66) winsize 63
766 12:20:48.963943 [CA 3] Center 34 (4~65) winsize 62
767 12:20:48.967163 [CA 4] Center 34 (3~65) winsize 63
768 12:20:48.970580 [CA 5] Center 33 (3~64) winsize 62
769 12:20:48.970665
770 12:20:48.973636 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 12:20:48.973721
772 12:20:48.977596 [CATrainingPosCal] consider 2 rank data
773 12:20:48.980965 u2DelayCellTimex100 = 270/100 ps
774 12:20:48.984219 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 12:20:48.987376 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 12:20:48.993768 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 12:20:48.997044 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 12:20:49.000510 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 12:20:49.003729 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 12:20:49.003811
781 12:20:49.006956 CA PerBit enable=1, Macro0, CA PI delay=33
782 12:20:49.007041
783 12:20:49.011109 [CBTSetCACLKResult] CA Dly = 33
784 12:20:49.011193 CS Dly: 5 (0~37)
785 12:20:49.011258
786 12:20:49.013855 ----->DramcWriteLeveling(PI) begin...
787 12:20:49.017146 ==
788 12:20:49.017229 Dram Type= 6, Freq= 0, CH_0, rank 0
789 12:20:49.024368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 12:20:49.024456 ==
791 12:20:49.028506 Write leveling (Byte 0): 33 => 33
792 12:20:49.028590 Write leveling (Byte 1): 29 => 29
793 12:20:49.031832 DramcWriteLeveling(PI) end<-----
794 12:20:49.031959
795 12:20:49.032027 ==
796 12:20:49.034933 Dram Type= 6, Freq= 0, CH_0, rank 0
797 12:20:49.038680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 12:20:49.041790 ==
799 12:20:49.041874 [Gating] SW mode calibration
800 12:20:49.049180 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 12:20:49.055739 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 12:20:49.059518 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
803 12:20:49.062386 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 12:20:49.069133 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 12:20:49.072464 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:20:49.075646 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:20:49.082574 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:20:49.085522 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:20:49.088907 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:20:49.095530 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:20:49.099272 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:20:49.102907 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:20:49.108950 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:20:49.112450 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:20:49.115663 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:20:49.122545 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:20:49.125705 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:20:49.128770 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:20:49.135576 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 12:20:49.139009 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 12:20:49.142311 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:20:49.149381 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:20:49.152292 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:20:49.155582 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:20:49.162039 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:20:49.165295 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:20:49.169282 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:20:49.175387 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
829 12:20:49.178605 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
830 12:20:49.182044 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 12:20:49.188616 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 12:20:49.191727 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 12:20:49.195379 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 12:20:49.198680 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 12:20:49.205452 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
836 12:20:49.208654 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
837 12:20:49.212233 0 10 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
838 12:20:49.219108 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:20:49.221823 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:20:49.225388 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 12:20:49.231933 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 12:20:49.234963 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:20:49.238300 0 11 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
844 12:20:49.245055 0 11 8 | B1->B0 | 2525 4040 | 0 0 | (0 0) (1 1)
845 12:20:49.247844 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
846 12:20:49.251240 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:20:49.258366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 12:20:49.261635 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 12:20:49.264836 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:20:49.271397 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 12:20:49.274547 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 12:20:49.278474 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 12:20:49.284631 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 12:20:49.287617 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:20:49.291245 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:20:49.297876 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:20:49.301264 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:20:49.304087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 12:20:49.312249 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 12:20:49.314105 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 12:20:49.317554 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 12:20:49.324040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 12:20:49.327398 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 12:20:49.331026 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 12:20:49.337417 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 12:20:49.340494 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 12:20:49.344012 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
868 12:20:49.350970 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
869 12:20:49.354283 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 12:20:49.357349 Total UI for P1: 0, mck2ui 16
871 12:20:49.360633 best dqsien dly found for B0: ( 0, 14, 6)
872 12:20:49.363968 Total UI for P1: 0, mck2ui 16
873 12:20:49.367537 best dqsien dly found for B1: ( 0, 14, 6)
874 12:20:49.370671 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
875 12:20:49.373820 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
876 12:20:49.373906
877 12:20:49.377064 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
878 12:20:49.380659 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
879 12:20:49.383857 [Gating] SW calibration Done
880 12:20:49.383996 ==
881 12:20:49.387542 Dram Type= 6, Freq= 0, CH_0, rank 0
882 12:20:49.390506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 12:20:49.394749 ==
884 12:20:49.394835 RX Vref Scan: 0
885 12:20:49.394902
886 12:20:49.394963 RX Vref 0 -> 0, step: 1
887 12:20:49.397764
888 12:20:49.397848 RX Delay -130 -> 252, step: 16
889 12:20:49.404320 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
890 12:20:49.407610 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
891 12:20:49.410878 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
892 12:20:49.414422 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 12:20:49.417736 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
894 12:20:49.424982 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
895 12:20:49.427298 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
896 12:20:49.431423 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
897 12:20:49.434070 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
898 12:20:49.437272 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
899 12:20:49.444167 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
900 12:20:49.448160 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
901 12:20:49.451118 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
902 12:20:49.453704 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
903 12:20:49.460734 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
904 12:20:49.464457 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
905 12:20:49.464545 ==
906 12:20:49.467150 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:20:49.470411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:20:49.470504 ==
909 12:20:49.470570 DQS Delay:
910 12:20:49.473645 DQS0 = 0, DQS1 = 0
911 12:20:49.473729 DQM Delay:
912 12:20:49.476899 DQM0 = 91, DQM1 = 77
913 12:20:49.476982 DQ Delay:
914 12:20:49.480409 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
915 12:20:49.483498 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
916 12:20:49.486700 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
917 12:20:49.490494 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
918 12:20:49.490577
919 12:20:49.490642
920 12:20:49.490702 ==
921 12:20:49.493301 Dram Type= 6, Freq= 0, CH_0, rank 0
922 12:20:49.500325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 12:20:49.500412 ==
924 12:20:49.500478
925 12:20:49.500538
926 12:20:49.500599 TX Vref Scan disable
927 12:20:49.503623 == TX Byte 0 ==
928 12:20:49.507116 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
929 12:20:49.510642 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
930 12:20:49.513554 == TX Byte 1 ==
931 12:20:49.517354 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
932 12:20:49.520011 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
933 12:20:49.523625 ==
934 12:20:49.526772 Dram Type= 6, Freq= 0, CH_0, rank 0
935 12:20:49.530108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 12:20:49.530218 ==
937 12:20:49.542987 TX Vref=22, minBit 1, minWin=27, winSum=442
938 12:20:49.546514 TX Vref=24, minBit 4, minWin=27, winSum=446
939 12:20:49.549958 TX Vref=26, minBit 1, minWin=27, winSum=449
940 12:20:49.552821 TX Vref=28, minBit 1, minWin=28, winSum=453
941 12:20:49.556067 TX Vref=30, minBit 0, minWin=28, winSum=453
942 12:20:49.562935 TX Vref=32, minBit 4, minWin=27, winSum=447
943 12:20:49.566115 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 28
944 12:20:49.566213
945 12:20:49.569706 Final TX Range 1 Vref 28
946 12:20:49.569792
947 12:20:49.569857 ==
948 12:20:49.572384 Dram Type= 6, Freq= 0, CH_0, rank 0
949 12:20:49.575842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 12:20:49.579157 ==
951 12:20:49.579241
952 12:20:49.579307
953 12:20:49.579367 TX Vref Scan disable
954 12:20:49.583268 == TX Byte 0 ==
955 12:20:49.586199 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
956 12:20:49.589498 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
957 12:20:49.592731 == TX Byte 1 ==
958 12:20:49.596624 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
959 12:20:49.599770 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
960 12:20:49.603603
961 12:20:49.603691 [DATLAT]
962 12:20:49.603756 Freq=800, CH0 RK0
963 12:20:49.603817
964 12:20:49.606538 DATLAT Default: 0xa
965 12:20:49.606621 0, 0xFFFF, sum = 0
966 12:20:49.609669 1, 0xFFFF, sum = 0
967 12:20:49.609753 2, 0xFFFF, sum = 0
968 12:20:49.613079 3, 0xFFFF, sum = 0
969 12:20:49.613165 4, 0xFFFF, sum = 0
970 12:20:49.616319 5, 0xFFFF, sum = 0
971 12:20:49.616404 6, 0xFFFF, sum = 0
972 12:20:49.619770 7, 0xFFFF, sum = 0
973 12:20:49.619882 8, 0xFFFF, sum = 0
974 12:20:49.623134 9, 0x0, sum = 1
975 12:20:49.623218 10, 0x0, sum = 2
976 12:20:49.626774 11, 0x0, sum = 3
977 12:20:49.626858 12, 0x0, sum = 4
978 12:20:49.630400 best_step = 10
979 12:20:49.630488
980 12:20:49.630565 ==
981 12:20:49.633371 Dram Type= 6, Freq= 0, CH_0, rank 0
982 12:20:49.636593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 12:20:49.636688 ==
984 12:20:49.639591 RX Vref Scan: 1
985 12:20:49.639676
986 12:20:49.639742 Set Vref Range= 32 -> 127
987 12:20:49.642798
988 12:20:49.642881 RX Vref 32 -> 127, step: 1
989 12:20:49.642947
990 12:20:49.646312 RX Delay -95 -> 252, step: 8
991 12:20:49.646411
992 12:20:49.649506 Set Vref, RX VrefLevel [Byte0]: 32
993 12:20:49.653050 [Byte1]: 32
994 12:20:49.653136
995 12:20:49.656295 Set Vref, RX VrefLevel [Byte0]: 33
996 12:20:49.659941 [Byte1]: 33
997 12:20:49.663126
998 12:20:49.663211 Set Vref, RX VrefLevel [Byte0]: 34
999 12:20:49.666824 [Byte1]: 34
1000 12:20:49.670946
1001 12:20:49.671031 Set Vref, RX VrefLevel [Byte0]: 35
1002 12:20:49.674288 [Byte1]: 35
1003 12:20:49.678511
1004 12:20:49.678597 Set Vref, RX VrefLevel [Byte0]: 36
1005 12:20:49.681690 [Byte1]: 36
1006 12:20:49.686161
1007 12:20:49.686250 Set Vref, RX VrefLevel [Byte0]: 37
1008 12:20:49.689351 [Byte1]: 37
1009 12:20:49.694356
1010 12:20:49.694446 Set Vref, RX VrefLevel [Byte0]: 38
1011 12:20:49.697494 [Byte1]: 38
1012 12:20:49.702565
1013 12:20:49.702654 Set Vref, RX VrefLevel [Byte0]: 39
1014 12:20:49.705118 [Byte1]: 39
1015 12:20:49.708993
1016 12:20:49.709080 Set Vref, RX VrefLevel [Byte0]: 40
1017 12:20:49.712789 [Byte1]: 40
1018 12:20:49.716649
1019 12:20:49.716737 Set Vref, RX VrefLevel [Byte0]: 41
1020 12:20:49.720098 [Byte1]: 41
1021 12:20:49.724232
1022 12:20:49.724317 Set Vref, RX VrefLevel [Byte0]: 42
1023 12:20:49.727895 [Byte1]: 42
1024 12:20:49.731813
1025 12:20:49.731969 Set Vref, RX VrefLevel [Byte0]: 43
1026 12:20:49.735287 [Byte1]: 43
1027 12:20:49.739127
1028 12:20:49.739214 Set Vref, RX VrefLevel [Byte0]: 44
1029 12:20:49.742554 [Byte1]: 44
1030 12:20:49.747861
1031 12:20:49.748001 Set Vref, RX VrefLevel [Byte0]: 45
1032 12:20:49.750245 [Byte1]: 45
1033 12:20:49.754852
1034 12:20:49.754945 Set Vref, RX VrefLevel [Byte0]: 46
1035 12:20:49.757724 [Byte1]: 46
1036 12:20:49.762028
1037 12:20:49.762112 Set Vref, RX VrefLevel [Byte0]: 47
1038 12:20:49.765230 [Byte1]: 47
1039 12:20:49.770353
1040 12:20:49.770442 Set Vref, RX VrefLevel [Byte0]: 48
1041 12:20:49.772876 [Byte1]: 48
1042 12:20:49.777245
1043 12:20:49.777328 Set Vref, RX VrefLevel [Byte0]: 49
1044 12:20:49.780481 [Byte1]: 49
1045 12:20:49.785152
1046 12:20:49.785238 Set Vref, RX VrefLevel [Byte0]: 50
1047 12:20:49.788150 [Byte1]: 50
1048 12:20:49.792505
1049 12:20:49.792589 Set Vref, RX VrefLevel [Byte0]: 51
1050 12:20:49.795593 [Byte1]: 51
1051 12:20:49.799968
1052 12:20:49.800055 Set Vref, RX VrefLevel [Byte0]: 52
1053 12:20:49.803497 [Byte1]: 52
1054 12:20:49.807499
1055 12:20:49.807584 Set Vref, RX VrefLevel [Byte0]: 53
1056 12:20:49.810848 [Byte1]: 53
1057 12:20:49.815771
1058 12:20:49.815860 Set Vref, RX VrefLevel [Byte0]: 54
1059 12:20:49.818936 [Byte1]: 54
1060 12:20:49.822767
1061 12:20:49.822867 Set Vref, RX VrefLevel [Byte0]: 55
1062 12:20:49.826026 [Byte1]: 55
1063 12:20:49.830613
1064 12:20:49.830716 Set Vref, RX VrefLevel [Byte0]: 56
1065 12:20:49.833899 [Byte1]: 56
1066 12:20:49.838053
1067 12:20:49.838140 Set Vref, RX VrefLevel [Byte0]: 57
1068 12:20:49.841086 [Byte1]: 57
1069 12:20:49.845694
1070 12:20:49.845829 Set Vref, RX VrefLevel [Byte0]: 58
1071 12:20:49.849029 [Byte1]: 58
1072 12:20:49.853053
1073 12:20:49.853141 Set Vref, RX VrefLevel [Byte0]: 59
1074 12:20:49.856549 [Byte1]: 59
1075 12:20:49.860739
1076 12:20:49.860824 Set Vref, RX VrefLevel [Byte0]: 60
1077 12:20:49.864545 [Byte1]: 60
1078 12:20:49.868547
1079 12:20:49.868632 Set Vref, RX VrefLevel [Byte0]: 61
1080 12:20:49.871631 [Byte1]: 61
1081 12:20:49.876055
1082 12:20:49.876140 Set Vref, RX VrefLevel [Byte0]: 62
1083 12:20:49.879025 [Byte1]: 62
1084 12:20:49.883593
1085 12:20:49.883675 Set Vref, RX VrefLevel [Byte0]: 63
1086 12:20:49.886910 [Byte1]: 63
1087 12:20:49.891020
1088 12:20:49.891104 Set Vref, RX VrefLevel [Byte0]: 64
1089 12:20:49.894728 [Byte1]: 64
1090 12:20:49.898966
1091 12:20:49.899051 Set Vref, RX VrefLevel [Byte0]: 65
1092 12:20:49.902010 [Byte1]: 65
1093 12:20:49.906505
1094 12:20:49.906591 Set Vref, RX VrefLevel [Byte0]: 66
1095 12:20:49.909420 [Byte1]: 66
1096 12:20:49.913902
1097 12:20:49.913986 Set Vref, RX VrefLevel [Byte0]: 67
1098 12:20:49.916969 [Byte1]: 67
1099 12:20:49.921687
1100 12:20:49.921773 Set Vref, RX VrefLevel [Byte0]: 68
1101 12:20:49.925132 [Byte1]: 68
1102 12:20:49.929143
1103 12:20:49.929233 Set Vref, RX VrefLevel [Byte0]: 69
1104 12:20:49.932320 [Byte1]: 69
1105 12:20:49.937097
1106 12:20:49.937183 Set Vref, RX VrefLevel [Byte0]: 70
1107 12:20:49.939844 [Byte1]: 70
1108 12:20:49.944115
1109 12:20:49.944199 Set Vref, RX VrefLevel [Byte0]: 71
1110 12:20:49.947434 [Byte1]: 71
1111 12:20:49.952137
1112 12:20:49.952227 Set Vref, RX VrefLevel [Byte0]: 72
1113 12:20:49.955372 [Byte1]: 72
1114 12:20:49.959189
1115 12:20:49.959274 Set Vref, RX VrefLevel [Byte0]: 73
1116 12:20:49.963086 [Byte1]: 73
1117 12:20:49.967178
1118 12:20:49.967265 Set Vref, RX VrefLevel [Byte0]: 74
1119 12:20:49.970423 [Byte1]: 74
1120 12:20:49.974597
1121 12:20:49.974682 Set Vref, RX VrefLevel [Byte0]: 75
1122 12:20:49.977756 [Byte1]: 75
1123 12:20:49.982574
1124 12:20:49.982658 Final RX Vref Byte 0 = 56 to rank0
1125 12:20:49.985378 Final RX Vref Byte 1 = 57 to rank0
1126 12:20:49.989119 Final RX Vref Byte 0 = 56 to rank1
1127 12:20:49.992283 Final RX Vref Byte 1 = 57 to rank1==
1128 12:20:49.995675 Dram Type= 6, Freq= 0, CH_0, rank 0
1129 12:20:50.002343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 12:20:50.002432 ==
1131 12:20:50.002498 DQS Delay:
1132 12:20:50.002559 DQS0 = 0, DQS1 = 0
1133 12:20:50.006134 DQM Delay:
1134 12:20:50.006217 DQM0 = 88, DQM1 = 75
1135 12:20:50.008776 DQ Delay:
1136 12:20:50.012081 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1137 12:20:50.015700 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1138 12:20:50.015782 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1139 12:20:50.022213 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1140 12:20:50.022297
1141 12:20:50.022362
1142 12:20:50.028607 [DQSOSCAuto] RK0, (LSB)MR18= 0x302a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1143 12:20:50.031782 CH0 RK0: MR19=606, MR18=302A
1144 12:20:50.038629 CH0_RK0: MR19=0x606, MR18=0x302A, DQSOSC=397, MR23=63, INC=93, DEC=62
1145 12:20:50.038725
1146 12:20:50.042659 ----->DramcWriteLeveling(PI) begin...
1147 12:20:50.042745 ==
1148 12:20:50.045510 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 12:20:50.048656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 12:20:50.048741 ==
1151 12:20:50.051973 Write leveling (Byte 0): 31 => 31
1152 12:20:50.055305 Write leveling (Byte 1): 28 => 28
1153 12:20:50.058602 DramcWriteLeveling(PI) end<-----
1154 12:20:50.058688
1155 12:20:50.058774 ==
1156 12:20:50.062358 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 12:20:50.065137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 12:20:50.065223 ==
1159 12:20:50.068421 [Gating] SW mode calibration
1160 12:20:50.075129 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1161 12:20:50.081768 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1162 12:20:50.125605 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 12:20:50.126123 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1164 12:20:50.126211 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1165 12:20:50.127067 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:20:50.127332 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:20:50.127407 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:20:50.127675 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:20:50.127771 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:20:50.127883 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:20:50.127999 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:20:50.170313 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:20:50.170667 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:20:50.170747 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:20:50.171030 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:20:50.171280 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:20:50.171603 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:20:50.171871 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:20:50.171994 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1180 12:20:50.172092 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1181 12:20:50.172351 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:20:50.192468 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:20:50.193608 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:20:50.193698 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:20:50.193968 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:20:50.194223 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:20:50.196355 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1188 12:20:50.200079 0 9 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
1189 12:20:50.203429 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1190 12:20:50.209831 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 12:20:50.213162 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 12:20:50.216710 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 12:20:50.223638 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 12:20:50.226699 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 12:20:50.229785 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
1196 12:20:50.236100 0 10 8 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 1)
1197 12:20:50.240680 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1198 12:20:50.242887 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 12:20:50.249687 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 12:20:50.253176 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 12:20:50.256664 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 12:20:50.263250 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:20:50.266941 0 11 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1204 12:20:50.270207 0 11 8 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
1205 12:20:50.274598 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1206 12:20:50.278183 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 12:20:50.284954 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 12:20:50.288040 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 12:20:50.291896 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 12:20:50.296015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 12:20:50.302432 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 12:20:50.305730 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1213 12:20:50.308700 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:20:50.316060 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:20:50.318777 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:20:50.322734 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:20:50.329156 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:20:50.332269 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:20:50.335870 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:20:50.342854 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:20:50.345270 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:20:50.348530 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:20:50.355256 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:20:50.358399 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:20:50.362148 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:20:50.365393 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:20:50.371714 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1228 12:20:50.375159 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1229 12:20:50.378447 Total UI for P1: 0, mck2ui 16
1230 12:20:50.381704 best dqsien dly found for B0: ( 0, 14, 4)
1231 12:20:50.385060 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 12:20:50.388859 Total UI for P1: 0, mck2ui 16
1233 12:20:50.391681 best dqsien dly found for B1: ( 0, 14, 8)
1234 12:20:50.395302 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1235 12:20:50.398324 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1236 12:20:50.401910
1237 12:20:50.405227 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1238 12:20:50.408290 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1239 12:20:50.411653 [Gating] SW calibration Done
1240 12:20:50.411735 ==
1241 12:20:50.415183 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 12:20:50.418680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1243 12:20:50.418764 ==
1244 12:20:50.418828 RX Vref Scan: 0
1245 12:20:50.418887
1246 12:20:50.421942 RX Vref 0 -> 0, step: 1
1247 12:20:50.422024
1248 12:20:50.425071 RX Delay -130 -> 252, step: 16
1249 12:20:50.428384 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1250 12:20:50.432057 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1251 12:20:50.439135 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1252 12:20:50.441451 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1253 12:20:50.445030 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1254 12:20:50.448064 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1255 12:20:50.451460 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1256 12:20:50.458232 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1257 12:20:50.461129 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1258 12:20:50.464843 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1259 12:20:50.468130 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1260 12:20:50.471244 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1261 12:20:50.478129 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1262 12:20:50.481154 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1263 12:20:50.484450 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1264 12:20:50.487948 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1265 12:20:50.488030 ==
1266 12:20:50.491133 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 12:20:50.498133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 12:20:50.498217 ==
1269 12:20:50.498287 DQS Delay:
1270 12:20:50.501029 DQS0 = 0, DQS1 = 0
1271 12:20:50.501110 DQM Delay:
1272 12:20:50.501174 DQM0 = 84, DQM1 = 77
1273 12:20:50.504467 DQ Delay:
1274 12:20:50.507724 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1275 12:20:50.511214 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1276 12:20:50.514710 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1277 12:20:50.518067 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1278 12:20:50.518149
1279 12:20:50.518213
1280 12:20:50.518273 ==
1281 12:20:50.520859 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 12:20:50.524580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 12:20:50.524663 ==
1284 12:20:50.524728
1285 12:20:50.524788
1286 12:20:50.527743 TX Vref Scan disable
1287 12:20:50.531088 == TX Byte 0 ==
1288 12:20:50.534716 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1289 12:20:50.537625 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1290 12:20:50.540640 == TX Byte 1 ==
1291 12:20:50.544335 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1292 12:20:50.548294 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1293 12:20:50.548376 ==
1294 12:20:50.550599 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 12:20:50.553995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 12:20:50.557142 ==
1297 12:20:50.568904 TX Vref=22, minBit 1, minWin=27, winSum=442
1298 12:20:50.571946 TX Vref=24, minBit 0, minWin=27, winSum=440
1299 12:20:50.575254 TX Vref=26, minBit 1, minWin=27, winSum=447
1300 12:20:50.578676 TX Vref=28, minBit 1, minWin=27, winSum=453
1301 12:20:50.582059 TX Vref=30, minBit 7, minWin=27, winSum=453
1302 12:20:50.585803 TX Vref=32, minBit 1, minWin=27, winSum=449
1303 12:20:50.592799 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 28
1304 12:20:50.592882
1305 12:20:50.595410 Final TX Range 1 Vref 28
1306 12:20:50.595493
1307 12:20:50.595556 ==
1308 12:20:50.598875 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 12:20:50.602157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 12:20:50.602241 ==
1311 12:20:50.604996
1312 12:20:50.605077
1313 12:20:50.605139 TX Vref Scan disable
1314 12:20:50.608440 == TX Byte 0 ==
1315 12:20:50.611885 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1316 12:20:50.615912 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1317 12:20:50.618552 == TX Byte 1 ==
1318 12:20:50.621729 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1319 12:20:50.628596 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1320 12:20:50.628677
1321 12:20:50.628741 [DATLAT]
1322 12:20:50.628800 Freq=800, CH0 RK1
1323 12:20:50.628857
1324 12:20:50.631629 DATLAT Default: 0xa
1325 12:20:50.631710 0, 0xFFFF, sum = 0
1326 12:20:50.635034 1, 0xFFFF, sum = 0
1327 12:20:50.635118 2, 0xFFFF, sum = 0
1328 12:20:50.638314 3, 0xFFFF, sum = 0
1329 12:20:50.642070 4, 0xFFFF, sum = 0
1330 12:20:50.642153 5, 0xFFFF, sum = 0
1331 12:20:50.644831 6, 0xFFFF, sum = 0
1332 12:20:50.644913 7, 0xFFFF, sum = 0
1333 12:20:50.648377 8, 0xFFFF, sum = 0
1334 12:20:50.648460 9, 0x0, sum = 1
1335 12:20:50.648525 10, 0x0, sum = 2
1336 12:20:50.652134 11, 0x0, sum = 3
1337 12:20:50.652231 12, 0x0, sum = 4
1338 12:20:50.655192 best_step = 10
1339 12:20:50.655289
1340 12:20:50.655358 ==
1341 12:20:50.658500 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 12:20:50.661508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 12:20:50.661590 ==
1344 12:20:50.665647 RX Vref Scan: 0
1345 12:20:50.665735
1346 12:20:50.665800 RX Vref 0 -> 0, step: 1
1347 12:20:50.665860
1348 12:20:50.668322 RX Delay -95 -> 252, step: 8
1349 12:20:50.675210 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1350 12:20:50.678332 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1351 12:20:50.681784 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1352 12:20:50.685081 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1353 12:20:50.691838 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1354 12:20:50.694642 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1355 12:20:50.698292 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1356 12:20:50.701324 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1357 12:20:50.704619 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1358 12:20:50.711056 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1359 12:20:50.714492 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1360 12:20:50.718498 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1361 12:20:50.721319 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1362 12:20:50.724912 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1363 12:20:50.731124 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1364 12:20:50.734492 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1365 12:20:50.734576 ==
1366 12:20:50.738169 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 12:20:50.741795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 12:20:50.741878 ==
1369 12:20:50.744497 DQS Delay:
1370 12:20:50.744577 DQS0 = 0, DQS1 = 0
1371 12:20:50.744641 DQM Delay:
1372 12:20:50.748781 DQM0 = 86, DQM1 = 77
1373 12:20:50.748860 DQ Delay:
1374 12:20:50.750665 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1375 12:20:50.754123 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1376 12:20:50.757554 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1377 12:20:50.761149 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1378 12:20:50.761230
1379 12:20:50.761293
1380 12:20:50.770631 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1381 12:20:50.773855 CH0 RK1: MR19=606, MR18=2B28
1382 12:20:50.777556 CH0_RK1: MR19=0x606, MR18=0x2B28, DQSOSC=398, MR23=63, INC=93, DEC=62
1383 12:20:50.780826 [RxdqsGatingPostProcess] freq 800
1384 12:20:50.787067 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1385 12:20:50.790602 Pre-setting of DQS Precalculation
1386 12:20:50.793902 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1387 12:20:50.797220 ==
1388 12:20:50.800231 Dram Type= 6, Freq= 0, CH_1, rank 0
1389 12:20:50.803435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 12:20:50.803517 ==
1391 12:20:50.807657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 12:20:50.813691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 12:20:50.823672 [CA 0] Center 37 (6~68) winsize 63
1394 12:20:50.826782 [CA 1] Center 37 (6~68) winsize 63
1395 12:20:50.830330 [CA 2] Center 35 (5~66) winsize 62
1396 12:20:50.833999 [CA 3] Center 35 (5~65) winsize 61
1397 12:20:50.836783 [CA 4] Center 35 (4~66) winsize 63
1398 12:20:50.840408 [CA 5] Center 34 (4~65) winsize 62
1399 12:20:50.840490
1400 12:20:50.843508 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1401 12:20:50.843589
1402 12:20:50.847054 [CATrainingPosCal] consider 1 rank data
1403 12:20:50.849925 u2DelayCellTimex100 = 270/100 ps
1404 12:20:50.853384 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1405 12:20:50.859908 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1406 12:20:50.863259 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1407 12:20:50.866804 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1408 12:20:50.870115 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1409 12:20:50.873506 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 12:20:50.873588
1411 12:20:50.877001 CA PerBit enable=1, Macro0, CA PI delay=34
1412 12:20:50.877082
1413 12:20:50.879816 [CBTSetCACLKResult] CA Dly = 34
1414 12:20:50.879897 CS Dly: 4 (0~35)
1415 12:20:50.883216 ==
1416 12:20:50.886274 Dram Type= 6, Freq= 0, CH_1, rank 1
1417 12:20:50.889681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 12:20:50.889802 ==
1419 12:20:50.893227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 12:20:50.899733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 12:20:50.909629 [CA 0] Center 36 (6~67) winsize 62
1422 12:20:50.912984 [CA 1] Center 36 (6~67) winsize 62
1423 12:20:50.916590 [CA 2] Center 35 (4~66) winsize 63
1424 12:20:50.919507 [CA 3] Center 34 (4~65) winsize 62
1425 12:20:50.923054 [CA 4] Center 34 (4~65) winsize 62
1426 12:20:50.926535 [CA 5] Center 34 (4~65) winsize 62
1427 12:20:50.926617
1428 12:20:50.929999 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1429 12:20:50.930080
1430 12:20:50.934062 [CATrainingPosCal] consider 2 rank data
1431 12:20:50.937442 u2DelayCellTimex100 = 270/100 ps
1432 12:20:50.941137 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 12:20:50.944612 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 12:20:50.947949 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1435 12:20:50.952140 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1436 12:20:50.955849 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 12:20:50.959531 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 12:20:50.959615
1439 12:20:50.963147 CA PerBit enable=1, Macro0, CA PI delay=34
1440 12:20:50.963228
1441 12:20:50.966941 [CBTSetCACLKResult] CA Dly = 34
1442 12:20:50.967026 CS Dly: 5 (0~37)
1443 12:20:50.967091
1444 12:20:50.969522 ----->DramcWriteLeveling(PI) begin...
1445 12:20:50.973233 ==
1446 12:20:50.973315 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 12:20:50.979591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 12:20:50.979675 ==
1449 12:20:50.983260 Write leveling (Byte 0): 27 => 27
1450 12:20:50.986109 Write leveling (Byte 1): 28 => 28
1451 12:20:50.989474 DramcWriteLeveling(PI) end<-----
1452 12:20:50.989570
1453 12:20:50.989635 ==
1454 12:20:50.992781 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 12:20:50.996711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 12:20:50.996794 ==
1457 12:20:50.999680 [Gating] SW mode calibration
1458 12:20:51.007056 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1459 12:20:51.010362 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1460 12:20:51.016249 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1461 12:20:51.019409 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 12:20:51.023192 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:20:51.029515 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:20:51.033094 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:20:51.036140 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:20:51.043130 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:20:51.045876 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:20:51.049429 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:20:51.055728 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:20:51.059174 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:20:51.063129 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:20:51.069654 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:20:51.072338 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:20:51.075761 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:20:51.082207 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:20:51.085760 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1477 12:20:51.089353 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1478 12:20:51.095526 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:20:51.099273 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:20:51.102271 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:20:51.108839 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:20:51.112287 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:20:51.115841 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:20:51.122027 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:20:51.125575 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:20:51.128765 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1487 12:20:51.135600 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 12:20:51.138711 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 12:20:51.141949 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 12:20:51.148980 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 12:20:51.152242 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 12:20:51.155361 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 12:20:51.162079 0 10 4 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 1)
1494 12:20:51.165055 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1495 12:20:51.169085 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 12:20:51.174988 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 12:20:51.178477 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 12:20:51.182131 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:20:51.185251 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 12:20:51.192123 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:20:51.195217 0 11 4 | B1->B0 | 2828 3030 | 0 0 | (0 0) (0 0)
1502 12:20:51.198590 0 11 8 | B1->B0 | 3838 4040 | 1 1 | (0 0) (0 0)
1503 12:20:51.205136 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 12:20:51.209309 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 12:20:51.211770 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 12:20:51.218746 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 12:20:51.221869 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 12:20:51.225258 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 12:20:51.232142 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1510 12:20:51.234724 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1511 12:20:51.238288 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:20:51.244972 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:20:51.248504 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:20:51.251548 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:20:51.258084 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:20:51.261332 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:20:51.264762 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:20:51.271569 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:20:51.274557 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:20:51.277900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 12:20:51.284745 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:20:51.288204 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:20:51.291347 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:20:51.297766 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:20:51.301249 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1526 12:20:51.304799 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1527 12:20:51.307727 Total UI for P1: 0, mck2ui 16
1528 12:20:51.311271 best dqsien dly found for B0: ( 0, 14, 4)
1529 12:20:51.318541 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 12:20:51.318628 Total UI for P1: 0, mck2ui 16
1531 12:20:51.324220 best dqsien dly found for B1: ( 0, 14, 6)
1532 12:20:51.327604 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1533 12:20:51.330933 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1534 12:20:51.331017
1535 12:20:51.334133 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1536 12:20:51.337848 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1537 12:20:51.341314 [Gating] SW calibration Done
1538 12:20:51.341399 ==
1539 12:20:51.344207 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 12:20:51.348203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 12:20:51.348287 ==
1542 12:20:51.351060 RX Vref Scan: 0
1543 12:20:51.351147
1544 12:20:51.351231 RX Vref 0 -> 0, step: 1
1545 12:20:51.351311
1546 12:20:51.354066 RX Delay -130 -> 252, step: 16
1547 12:20:51.357539 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1548 12:20:51.363916 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1549 12:20:51.367361 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1550 12:20:51.370808 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1551 12:20:51.374136 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1552 12:20:51.377619 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1553 12:20:51.384104 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1554 12:20:51.387205 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1555 12:20:51.390897 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1556 12:20:51.394159 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1557 12:20:51.397488 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1558 12:20:51.403619 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1559 12:20:51.407111 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1560 12:20:51.411025 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1561 12:20:51.413577 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1562 12:20:51.420574 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1563 12:20:51.420663 ==
1564 12:20:51.424975 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 12:20:51.427158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 12:20:51.427244 ==
1567 12:20:51.427330 DQS Delay:
1568 12:20:51.430587 DQS0 = 0, DQS1 = 0
1569 12:20:51.430671 DQM Delay:
1570 12:20:51.433827 DQM0 = 87, DQM1 = 79
1571 12:20:51.433911 DQ Delay:
1572 12:20:51.437161 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1573 12:20:51.440377 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1574 12:20:51.443466 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1575 12:20:51.447295 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1576 12:20:51.447380
1577 12:20:51.447480
1578 12:20:51.447578 ==
1579 12:20:51.450725 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 12:20:51.453576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 12:20:51.453669 ==
1582 12:20:51.453752
1583 12:20:51.453814
1584 12:20:51.456972 TX Vref Scan disable
1585 12:20:51.460499 == TX Byte 0 ==
1586 12:20:51.463285 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1587 12:20:51.467225 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1588 12:20:51.471007 == TX Byte 1 ==
1589 12:20:51.473528 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1590 12:20:51.477316 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1591 12:20:51.477399 ==
1592 12:20:51.480896 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 12:20:51.487120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 12:20:51.487230 ==
1595 12:20:51.498980 TX Vref=22, minBit 4, minWin=26, winSum=439
1596 12:20:51.501863 TX Vref=24, minBit 0, minWin=26, winSum=442
1597 12:20:51.504961 TX Vref=26, minBit 1, minWin=27, winSum=446
1598 12:20:51.508143 TX Vref=28, minBit 2, minWin=27, winSum=449
1599 12:20:51.512325 TX Vref=30, minBit 1, minWin=27, winSum=451
1600 12:20:51.515941 TX Vref=32, minBit 1, minWin=27, winSum=453
1601 12:20:51.522739 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 32
1602 12:20:51.522828
1603 12:20:51.525758 Final TX Range 1 Vref 32
1604 12:20:51.525844
1605 12:20:51.525929 ==
1606 12:20:51.529494 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 12:20:51.532886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 12:20:51.532971 ==
1609 12:20:51.533056
1610 12:20:51.533136
1611 12:20:51.535465 TX Vref Scan disable
1612 12:20:51.538816 == TX Byte 0 ==
1613 12:20:51.542284 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1614 12:20:51.546278 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1615 12:20:51.549234 == TX Byte 1 ==
1616 12:20:51.552249 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1617 12:20:51.555700 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1618 12:20:51.555784
1619 12:20:51.559354 [DATLAT]
1620 12:20:51.559438 Freq=800, CH1 RK0
1621 12:20:51.559525
1622 12:20:51.562209 DATLAT Default: 0xa
1623 12:20:51.562293 0, 0xFFFF, sum = 0
1624 12:20:51.565745 1, 0xFFFF, sum = 0
1625 12:20:51.565830 2, 0xFFFF, sum = 0
1626 12:20:51.569082 3, 0xFFFF, sum = 0
1627 12:20:51.569168 4, 0xFFFF, sum = 0
1628 12:20:51.571880 5, 0xFFFF, sum = 0
1629 12:20:51.572007 6, 0xFFFF, sum = 0
1630 12:20:51.576068 7, 0xFFFF, sum = 0
1631 12:20:51.576153 8, 0xFFFF, sum = 0
1632 12:20:51.578601 9, 0x0, sum = 1
1633 12:20:51.578685 10, 0x0, sum = 2
1634 12:20:51.582673 11, 0x0, sum = 3
1635 12:20:51.582758 12, 0x0, sum = 4
1636 12:20:51.585330 best_step = 10
1637 12:20:51.585413
1638 12:20:51.585497 ==
1639 12:20:51.588651 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 12:20:51.592030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 12:20:51.592114 ==
1642 12:20:51.596059 RX Vref Scan: 1
1643 12:20:51.596142
1644 12:20:51.596226 Set Vref Range= 32 -> 127
1645 12:20:51.596306
1646 12:20:51.598726 RX Vref 32 -> 127, step: 1
1647 12:20:51.598810
1648 12:20:51.602435 RX Delay -95 -> 252, step: 8
1649 12:20:51.602543
1650 12:20:51.605886 Set Vref, RX VrefLevel [Byte0]: 32
1651 12:20:51.609087 [Byte1]: 32
1652 12:20:51.609171
1653 12:20:51.612296 Set Vref, RX VrefLevel [Byte0]: 33
1654 12:20:51.615713 [Byte1]: 33
1655 12:20:51.619128
1656 12:20:51.619212 Set Vref, RX VrefLevel [Byte0]: 34
1657 12:20:51.622836 [Byte1]: 34
1658 12:20:51.626080
1659 12:20:51.626164 Set Vref, RX VrefLevel [Byte0]: 35
1660 12:20:51.629826 [Byte1]: 35
1661 12:20:51.634297
1662 12:20:51.634380 Set Vref, RX VrefLevel [Byte0]: 36
1663 12:20:51.637326 [Byte1]: 36
1664 12:20:51.641419
1665 12:20:51.641512 Set Vref, RX VrefLevel [Byte0]: 37
1666 12:20:51.645304 [Byte1]: 37
1667 12:20:51.649131
1668 12:20:51.649215 Set Vref, RX VrefLevel [Byte0]: 38
1669 12:20:51.652274 [Byte1]: 38
1670 12:20:51.656597
1671 12:20:51.656681 Set Vref, RX VrefLevel [Byte0]: 39
1672 12:20:51.660521 [Byte1]: 39
1673 12:20:51.664353
1674 12:20:51.664437 Set Vref, RX VrefLevel [Byte0]: 40
1675 12:20:51.667763 [Byte1]: 40
1676 12:20:51.672056
1677 12:20:51.672140 Set Vref, RX VrefLevel [Byte0]: 41
1678 12:20:51.675477 [Byte1]: 41
1679 12:20:51.679509
1680 12:20:51.679592 Set Vref, RX VrefLevel [Byte0]: 42
1681 12:20:51.682858 [Byte1]: 42
1682 12:20:51.686814
1683 12:20:51.686898 Set Vref, RX VrefLevel [Byte0]: 43
1684 12:20:51.690827 [Byte1]: 43
1685 12:20:51.694710
1686 12:20:51.694794 Set Vref, RX VrefLevel [Byte0]: 44
1687 12:20:51.698132 [Byte1]: 44
1688 12:20:51.701989
1689 12:20:51.702072 Set Vref, RX VrefLevel [Byte0]: 45
1690 12:20:51.705993 [Byte1]: 45
1691 12:20:51.710755
1692 12:20:51.710839 Set Vref, RX VrefLevel [Byte0]: 46
1693 12:20:51.713274 [Byte1]: 46
1694 12:20:51.718374
1695 12:20:51.718458 Set Vref, RX VrefLevel [Byte0]: 47
1696 12:20:51.720947 [Byte1]: 47
1697 12:20:51.724948
1698 12:20:51.725031 Set Vref, RX VrefLevel [Byte0]: 48
1699 12:20:51.728270 [Byte1]: 48
1700 12:20:51.732711
1701 12:20:51.732798 Set Vref, RX VrefLevel [Byte0]: 49
1702 12:20:51.735703 [Byte1]: 49
1703 12:20:51.740951
1704 12:20:51.741035 Set Vref, RX VrefLevel [Byte0]: 50
1705 12:20:51.743529 [Byte1]: 50
1706 12:20:51.748476
1707 12:20:51.748560 Set Vref, RX VrefLevel [Byte0]: 51
1708 12:20:51.751320 [Byte1]: 51
1709 12:20:51.755816
1710 12:20:51.755900 Set Vref, RX VrefLevel [Byte0]: 52
1711 12:20:51.758886 [Byte1]: 52
1712 12:20:51.763577
1713 12:20:51.763662 Set Vref, RX VrefLevel [Byte0]: 53
1714 12:20:51.766070 [Byte1]: 53
1715 12:20:51.771184
1716 12:20:51.774281 Set Vref, RX VrefLevel [Byte0]: 54
1717 12:20:51.774365 [Byte1]: 54
1718 12:20:51.777981
1719 12:20:51.778065 Set Vref, RX VrefLevel [Byte0]: 55
1720 12:20:51.781875 [Byte1]: 55
1721 12:20:51.785887
1722 12:20:51.785976 Set Vref, RX VrefLevel [Byte0]: 56
1723 12:20:51.789007 [Byte1]: 56
1724 12:20:51.793583
1725 12:20:51.793664 Set Vref, RX VrefLevel [Byte0]: 57
1726 12:20:51.796516 [Byte1]: 57
1727 12:20:51.801348
1728 12:20:51.801444 Set Vref, RX VrefLevel [Byte0]: 58
1729 12:20:51.804496 [Byte1]: 58
1730 12:20:51.808602
1731 12:20:51.808686 Set Vref, RX VrefLevel [Byte0]: 59
1732 12:20:51.812127 [Byte1]: 59
1733 12:20:51.816249
1734 12:20:51.816329 Set Vref, RX VrefLevel [Byte0]: 60
1735 12:20:51.819475 [Byte1]: 60
1736 12:20:51.823885
1737 12:20:51.823994 Set Vref, RX VrefLevel [Byte0]: 61
1738 12:20:51.826719 [Byte1]: 61
1739 12:20:51.831071
1740 12:20:51.831152 Set Vref, RX VrefLevel [Byte0]: 62
1741 12:20:51.834947 [Byte1]: 62
1742 12:20:51.838986
1743 12:20:51.839069 Set Vref, RX VrefLevel [Byte0]: 63
1744 12:20:51.842263 [Byte1]: 63
1745 12:20:51.846754
1746 12:20:51.846835 Set Vref, RX VrefLevel [Byte0]: 64
1747 12:20:51.849870 [Byte1]: 64
1748 12:20:51.854674
1749 12:20:51.854754 Set Vref, RX VrefLevel [Byte0]: 65
1750 12:20:51.857482 [Byte1]: 65
1751 12:20:51.861492
1752 12:20:51.861573 Set Vref, RX VrefLevel [Byte0]: 66
1753 12:20:51.864917 [Byte1]: 66
1754 12:20:51.869260
1755 12:20:51.869342 Set Vref, RX VrefLevel [Byte0]: 67
1756 12:20:51.873102 [Byte1]: 67
1757 12:20:51.877101
1758 12:20:51.877182 Set Vref, RX VrefLevel [Byte0]: 68
1759 12:20:51.880202 [Byte1]: 68
1760 12:20:51.884803
1761 12:20:51.884884 Set Vref, RX VrefLevel [Byte0]: 69
1762 12:20:51.887801 [Byte1]: 69
1763 12:20:51.892542
1764 12:20:51.892623 Set Vref, RX VrefLevel [Byte0]: 70
1765 12:20:51.895539 [Byte1]: 70
1766 12:20:51.899682
1767 12:20:51.899762 Set Vref, RX VrefLevel [Byte0]: 71
1768 12:20:51.903281 [Byte1]: 71
1769 12:20:51.907659
1770 12:20:51.907740 Set Vref, RX VrefLevel [Byte0]: 72
1771 12:20:51.910548 [Byte1]: 72
1772 12:20:51.914788
1773 12:20:51.914868 Set Vref, RX VrefLevel [Byte0]: 73
1774 12:20:51.918630 [Byte1]: 73
1775 12:20:51.922460
1776 12:20:51.922540 Set Vref, RX VrefLevel [Byte0]: 74
1777 12:20:51.925959 [Byte1]: 74
1778 12:20:51.929985
1779 12:20:51.930067 Set Vref, RX VrefLevel [Byte0]: 75
1780 12:20:51.933338 [Byte1]: 75
1781 12:20:51.937546
1782 12:20:51.937629 Final RX Vref Byte 0 = 59 to rank0
1783 12:20:51.941170 Final RX Vref Byte 1 = 58 to rank0
1784 12:20:51.944222 Final RX Vref Byte 0 = 59 to rank1
1785 12:20:51.947757 Final RX Vref Byte 1 = 58 to rank1==
1786 12:20:51.951142 Dram Type= 6, Freq= 0, CH_1, rank 0
1787 12:20:51.957615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 12:20:51.957699 ==
1789 12:20:51.957763 DQS Delay:
1790 12:20:51.957823 DQS0 = 0, DQS1 = 0
1791 12:20:51.960753 DQM Delay:
1792 12:20:51.960835 DQM0 = 86, DQM1 = 81
1793 12:20:51.964336 DQ Delay:
1794 12:20:51.967950 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1795 12:20:51.968032 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =84
1796 12:20:51.971164 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1797 12:20:51.977243 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1798 12:20:51.977325
1799 12:20:51.977388
1800 12:20:51.984132 [DQSOSCAuto] RK0, (LSB)MR18= 0x1327, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
1801 12:20:51.987436 CH1 RK0: MR19=606, MR18=1327
1802 12:20:51.994212 CH1_RK0: MR19=0x606, MR18=0x1327, DQSOSC=400, MR23=63, INC=92, DEC=61
1803 12:20:51.994295
1804 12:20:51.997805 ----->DramcWriteLeveling(PI) begin...
1805 12:20:51.997889 ==
1806 12:20:52.000790 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 12:20:52.003796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 12:20:52.003878 ==
1809 12:20:52.007290 Write leveling (Byte 0): 27 => 27
1810 12:20:52.010684 Write leveling (Byte 1): 29 => 29
1811 12:20:52.013987 DramcWriteLeveling(PI) end<-----
1812 12:20:52.014068
1813 12:20:52.014131 ==
1814 12:20:52.017321 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 12:20:52.020901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 12:20:52.020982 ==
1817 12:20:52.023959 [Gating] SW mode calibration
1818 12:20:52.030646 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1819 12:20:52.036846 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1820 12:20:52.040195 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1821 12:20:52.046899 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1822 12:20:52.050074 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:20:52.053691 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:20:52.060360 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:20:52.063745 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:20:52.067173 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:20:52.073404 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:20:52.076780 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:20:52.079779 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:20:52.086633 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:20:52.089820 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:20:52.093143 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:20:52.099858 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:20:52.103407 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:20:52.106829 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:20:52.113343 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:20:52.116145 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1838 12:20:52.119577 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1839 12:20:52.123407 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:20:52.130009 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:20:52.132573 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:20:52.136417 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:20:52.143159 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:20:52.145949 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:20:52.149591 0 9 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1846 12:20:52.155858 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1847 12:20:52.159109 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 12:20:52.162742 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 12:20:52.169258 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 12:20:52.172997 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 12:20:52.175850 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 12:20:52.182261 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1853 12:20:52.185556 0 10 4 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (0 0)
1854 12:20:52.189202 0 10 8 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
1855 12:20:52.196072 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:20:52.198922 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:20:52.202562 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:20:52.209267 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:20:52.212242 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:20:52.215965 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1861 12:20:52.222336 0 11 4 | B1->B0 | 2828 3939 | 0 0 | (0 0) (0 0)
1862 12:20:52.225715 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1863 12:20:52.229522 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 12:20:52.235491 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 12:20:52.239024 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:20:52.242589 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:20:52.248721 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 12:20:52.252311 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 12:20:52.255635 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1870 12:20:52.262568 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:20:52.265311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:20:52.268807 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:20:52.275949 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:20:52.278375 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:20:52.282582 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:20:52.288687 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:20:52.291628 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:20:52.296140 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:20:52.301973 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:20:52.305309 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:20:52.308726 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:20:52.312022 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:20:52.318528 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:20:52.322095 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 12:20:52.325367 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1886 12:20:52.329122 Total UI for P1: 0, mck2ui 16
1887 12:20:52.331576 best dqsien dly found for B0: ( 0, 14, 2)
1888 12:20:52.338455 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1889 12:20:52.342061 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 12:20:52.345483 Total UI for P1: 0, mck2ui 16
1891 12:20:52.348192 best dqsien dly found for B1: ( 0, 14, 6)
1892 12:20:52.352186 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1893 12:20:52.354865 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1894 12:20:52.354945
1895 12:20:52.358934 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1896 12:20:52.361928 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1897 12:20:52.364886 [Gating] SW calibration Done
1898 12:20:52.364966 ==
1899 12:20:52.368462 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 12:20:52.371862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 12:20:52.374688 ==
1902 12:20:52.374770 RX Vref Scan: 0
1903 12:20:52.374833
1904 12:20:52.378788 RX Vref 0 -> 0, step: 1
1905 12:20:52.378869
1906 12:20:52.381891 RX Delay -130 -> 252, step: 16
1907 12:20:52.385023 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1908 12:20:52.388457 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1909 12:20:52.391647 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1910 12:20:52.395518 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1911 12:20:52.401193 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1912 12:20:52.404728 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1913 12:20:52.408381 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1914 12:20:52.412103 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1915 12:20:52.415074 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1916 12:20:52.421398 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1917 12:20:52.424984 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1918 12:20:52.427812 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1919 12:20:52.431365 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1920 12:20:52.438327 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1921 12:20:52.442020 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1922 12:20:52.444867 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1923 12:20:52.444949 ==
1924 12:20:52.447758 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 12:20:52.451751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 12:20:52.451834 ==
1927 12:20:52.454421 DQS Delay:
1928 12:20:52.454503 DQS0 = 0, DQS1 = 0
1929 12:20:52.457748 DQM Delay:
1930 12:20:52.457829 DQM0 = 84, DQM1 = 83
1931 12:20:52.457913 DQ Delay:
1932 12:20:52.461113 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1933 12:20:52.464068 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1934 12:20:52.467384 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1935 12:20:52.470961 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1936 12:20:52.471044
1937 12:20:52.471129
1938 12:20:52.471208 ==
1939 12:20:52.474964 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 12:20:52.480917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 12:20:52.481004 ==
1942 12:20:52.481089
1943 12:20:52.481169
1944 12:20:52.484079 TX Vref Scan disable
1945 12:20:52.484162 == TX Byte 0 ==
1946 12:20:52.487694 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1947 12:20:52.494331 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1948 12:20:52.494415 == TX Byte 1 ==
1949 12:20:52.497385 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1950 12:20:52.503895 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1951 12:20:52.503986 ==
1952 12:20:52.507499 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 12:20:52.511057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 12:20:52.511141 ==
1955 12:20:52.524075 TX Vref=22, minBit 6, minWin=26, winSum=439
1956 12:20:52.527189 TX Vref=24, minBit 1, minWin=26, winSum=439
1957 12:20:52.530655 TX Vref=26, minBit 2, minWin=27, winSum=449
1958 12:20:52.533875 TX Vref=28, minBit 2, minWin=27, winSum=451
1959 12:20:52.537044 TX Vref=30, minBit 3, minWin=27, winSum=455
1960 12:20:52.541073 TX Vref=32, minBit 0, minWin=27, winSum=450
1961 12:20:52.547816 [TxChooseVref] Worse bit 3, Min win 27, Win sum 455, Final Vref 30
1962 12:20:52.547901
1963 12:20:52.550640 Final TX Range 1 Vref 30
1964 12:20:52.550724
1965 12:20:52.550809 ==
1966 12:20:52.553928 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 12:20:52.557425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 12:20:52.557509 ==
1969 12:20:52.557594
1970 12:20:52.560892
1971 12:20:52.560975 TX Vref Scan disable
1972 12:20:52.564225 == TX Byte 0 ==
1973 12:20:52.567475 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1974 12:20:52.574129 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1975 12:20:52.574213 == TX Byte 1 ==
1976 12:20:52.577526 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1977 12:20:52.583851 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1978 12:20:52.583970
1979 12:20:52.584055 [DATLAT]
1980 12:20:52.584136 Freq=800, CH1 RK1
1981 12:20:52.584215
1982 12:20:52.587154 DATLAT Default: 0xa
1983 12:20:52.587238 0, 0xFFFF, sum = 0
1984 12:20:52.590094 1, 0xFFFF, sum = 0
1985 12:20:52.593911 2, 0xFFFF, sum = 0
1986 12:20:52.593996 3, 0xFFFF, sum = 0
1987 12:20:52.597055 4, 0xFFFF, sum = 0
1988 12:20:52.597147 5, 0xFFFF, sum = 0
1989 12:20:52.600155 6, 0xFFFF, sum = 0
1990 12:20:52.600240 7, 0xFFFF, sum = 0
1991 12:20:52.603718 8, 0xFFFF, sum = 0
1992 12:20:52.603829 9, 0x0, sum = 1
1993 12:20:52.607287 10, 0x0, sum = 2
1994 12:20:52.607370 11, 0x0, sum = 3
1995 12:20:52.607435 12, 0x0, sum = 4
1996 12:20:52.610379 best_step = 10
1997 12:20:52.610460
1998 12:20:52.610524 ==
1999 12:20:52.613437 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 12:20:52.616879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 12:20:52.616961 ==
2002 12:20:52.620534 RX Vref Scan: 0
2003 12:20:52.620623
2004 12:20:52.620686 RX Vref 0 -> 0, step: 1
2005 12:20:52.624105
2006 12:20:52.624186 RX Delay -95 -> 252, step: 8
2007 12:20:52.630591 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2008 12:20:52.633757 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2009 12:20:52.637936 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2010 12:20:52.640761 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
2011 12:20:52.644019 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2012 12:20:52.650857 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2013 12:20:52.654227 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2014 12:20:52.657393 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2015 12:20:52.660265 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2016 12:20:52.664092 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2017 12:20:52.670934 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2018 12:20:52.673735 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2019 12:20:52.677024 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2020 12:20:52.680550 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2021 12:20:52.684233 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2022 12:20:52.690622 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2023 12:20:52.690705 ==
2024 12:20:52.694085 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 12:20:52.697613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 12:20:52.697697 ==
2027 12:20:52.697783 DQS Delay:
2028 12:20:52.700942 DQS0 = 0, DQS1 = 0
2029 12:20:52.701025 DQM Delay:
2030 12:20:52.704214 DQM0 = 87, DQM1 = 83
2031 12:20:52.704298 DQ Delay:
2032 12:20:52.707494 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2033 12:20:52.710160 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2034 12:20:52.713655 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
2035 12:20:52.718367 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
2036 12:20:52.718451
2037 12:20:52.718536
2038 12:20:52.727267 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2039 12:20:52.727353 CH1 RK1: MR19=606, MR18=1B36
2040 12:20:52.733866 CH1_RK1: MR19=0x606, MR18=0x1B36, DQSOSC=396, MR23=63, INC=94, DEC=62
2041 12:20:52.737140 [RxdqsGatingPostProcess] freq 800
2042 12:20:52.743947 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 12:20:52.746747 Pre-setting of DQS Precalculation
2044 12:20:52.750536 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 12:20:52.757003 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 12:20:52.763296 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 12:20:52.766699
2048 12:20:52.766782
2049 12:20:52.766869 [Calibration Summary] 1600 Mbps
2050 12:20:52.770099 CH 0, Rank 0
2051 12:20:52.770182 SW Impedance : PASS
2052 12:20:52.773727 DUTY Scan : NO K
2053 12:20:52.777199 ZQ Calibration : PASS
2054 12:20:52.777283 Jitter Meter : NO K
2055 12:20:52.780117 CBT Training : PASS
2056 12:20:52.783392 Write leveling : PASS
2057 12:20:52.783475 RX DQS gating : PASS
2058 12:20:52.787774 RX DQ/DQS(RDDQC) : PASS
2059 12:20:52.789998 TX DQ/DQS : PASS
2060 12:20:52.790082 RX DATLAT : PASS
2061 12:20:52.793025 RX DQ/DQS(Engine): PASS
2062 12:20:52.796618 TX OE : NO K
2063 12:20:52.796702 All Pass.
2064 12:20:52.796787
2065 12:20:52.796867 CH 0, Rank 1
2066 12:20:52.800026 SW Impedance : PASS
2067 12:20:52.803221 DUTY Scan : NO K
2068 12:20:52.803305 ZQ Calibration : PASS
2069 12:20:52.806560 Jitter Meter : NO K
2070 12:20:52.809743 CBT Training : PASS
2071 12:20:52.809826 Write leveling : PASS
2072 12:20:52.813675 RX DQS gating : PASS
2073 12:20:52.816950 RX DQ/DQS(RDDQC) : PASS
2074 12:20:52.817035 TX DQ/DQS : PASS
2075 12:20:52.820143 RX DATLAT : PASS
2076 12:20:52.822764 RX DQ/DQS(Engine): PASS
2077 12:20:52.822848 TX OE : NO K
2078 12:20:52.822933 All Pass.
2079 12:20:52.826124
2080 12:20:52.826208 CH 1, Rank 0
2081 12:20:52.830384 SW Impedance : PASS
2082 12:20:52.830469 DUTY Scan : NO K
2083 12:20:52.832846 ZQ Calibration : PASS
2084 12:20:52.832930 Jitter Meter : NO K
2085 12:20:52.836410 CBT Training : PASS
2086 12:20:52.839684 Write leveling : PASS
2087 12:20:52.840069 RX DQS gating : PASS
2088 12:20:52.843115 RX DQ/DQS(RDDQC) : PASS
2089 12:20:52.846774 TX DQ/DQS : PASS
2090 12:20:52.847111 RX DATLAT : PASS
2091 12:20:52.849945 RX DQ/DQS(Engine): PASS
2092 12:20:52.852910 TX OE : NO K
2093 12:20:52.853194 All Pass.
2094 12:20:52.853442
2095 12:20:52.853676 CH 1, Rank 1
2096 12:20:52.856346 SW Impedance : PASS
2097 12:20:52.859276 DUTY Scan : NO K
2098 12:20:52.859521 ZQ Calibration : PASS
2099 12:20:52.862788 Jitter Meter : NO K
2100 12:20:52.866002 CBT Training : PASS
2101 12:20:52.866261 Write leveling : PASS
2102 12:20:52.869294 RX DQS gating : PASS
2103 12:20:52.872702 RX DQ/DQS(RDDQC) : PASS
2104 12:20:52.872939 TX DQ/DQS : PASS
2105 12:20:52.876272 RX DATLAT : PASS
2106 12:20:52.879506 RX DQ/DQS(Engine): PASS
2107 12:20:52.879839 TX OE : NO K
2108 12:20:52.883894 All Pass.
2109 12:20:52.884352
2110 12:20:52.884611 DramC Write-DBI off
2111 12:20:52.886944 PER_BANK_REFRESH: Hybrid Mode
2112 12:20:52.887358 TX_TRACKING: ON
2113 12:20:52.889278 [GetDramInforAfterCalByMRR] Vendor 6.
2114 12:20:52.896388 [GetDramInforAfterCalByMRR] Revision 606.
2115 12:20:52.899629 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 12:20:52.900018 MR0 0x3b3b
2117 12:20:52.900303 MR8 0x5151
2118 12:20:52.902632 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 12:20:52.902987
2120 12:20:52.906682 MR0 0x3b3b
2121 12:20:52.907137 MR8 0x5151
2122 12:20:52.909486 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 12:20:52.909837
2124 12:20:52.919900 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 12:20:52.923144 [FAST_K] Save calibration result to emmc
2126 12:20:52.925954 [FAST_K] Save calibration result to emmc
2127 12:20:52.929488 dram_init: config_dvfs: 1
2128 12:20:52.932534 dramc_set_vcore_voltage set vcore to 662500
2129 12:20:52.936348 Read voltage for 1200, 2
2130 12:20:52.936807 Vio18 = 0
2131 12:20:52.937276 Vcore = 662500
2132 12:20:52.938836 Vdram = 0
2133 12:20:52.938936 Vddq = 0
2134 12:20:52.939024 Vmddr = 0
2135 12:20:52.946191 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 12:20:52.949037 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 12:20:52.952445 MEM_TYPE=3, freq_sel=15
2138 12:20:52.955572 sv_algorithm_assistance_LP4_1600
2139 12:20:52.958913 ============ PULL DRAM RESETB DOWN ============
2140 12:20:52.962410 ========== PULL DRAM RESETB DOWN end =========
2141 12:20:52.968934 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 12:20:52.971803 ===================================
2143 12:20:52.971969 LPDDR4 DRAM CONFIGURATION
2144 12:20:52.975173 ===================================
2145 12:20:52.978427 EX_ROW_EN[0] = 0x0
2146 12:20:52.982118 EX_ROW_EN[1] = 0x0
2147 12:20:52.982251 LP4Y_EN = 0x0
2148 12:20:52.985088 WORK_FSP = 0x0
2149 12:20:52.985206 WL = 0x4
2150 12:20:52.989188 RL = 0x4
2151 12:20:52.989322 BL = 0x2
2152 12:20:52.991681 RPST = 0x0
2153 12:20:52.991792 RD_PRE = 0x0
2154 12:20:52.994985 WR_PRE = 0x1
2155 12:20:52.995101 WR_PST = 0x0
2156 12:20:52.998250 DBI_WR = 0x0
2157 12:20:52.998338 DBI_RD = 0x0
2158 12:20:53.001701 OTF = 0x1
2159 12:20:53.005175 ===================================
2160 12:20:53.008944 ===================================
2161 12:20:53.009047 ANA top config
2162 12:20:53.011653 ===================================
2163 12:20:53.015394 DLL_ASYNC_EN = 0
2164 12:20:53.018719 ALL_SLAVE_EN = 0
2165 12:20:53.021805 NEW_RANK_MODE = 1
2166 12:20:53.021928 DLL_IDLE_MODE = 1
2167 12:20:53.025271 LP45_APHY_COMB_EN = 1
2168 12:20:53.028279 TX_ODT_DIS = 1
2169 12:20:53.031661 NEW_8X_MODE = 1
2170 12:20:53.034950 ===================================
2171 12:20:53.038667 ===================================
2172 12:20:53.041525 data_rate = 2400
2173 12:20:53.041616 CKR = 1
2174 12:20:53.044993 DQ_P2S_RATIO = 8
2175 12:20:53.048727 ===================================
2176 12:20:53.051707 CA_P2S_RATIO = 8
2177 12:20:53.054829 DQ_CA_OPEN = 0
2178 12:20:53.058297 DQ_SEMI_OPEN = 0
2179 12:20:53.061310 CA_SEMI_OPEN = 0
2180 12:20:53.061392 CA_FULL_RATE = 0
2181 12:20:53.065485 DQ_CKDIV4_EN = 0
2182 12:20:53.067765 CA_CKDIV4_EN = 0
2183 12:20:53.071087 CA_PREDIV_EN = 0
2184 12:20:53.074640 PH8_DLY = 17
2185 12:20:53.078212 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 12:20:53.078301 DQ_AAMCK_DIV = 4
2187 12:20:53.080956 CA_AAMCK_DIV = 4
2188 12:20:53.084470 CA_ADMCK_DIV = 4
2189 12:20:53.087919 DQ_TRACK_CA_EN = 0
2190 12:20:53.091018 CA_PICK = 1200
2191 12:20:53.094593 CA_MCKIO = 1200
2192 12:20:53.097735 MCKIO_SEMI = 0
2193 12:20:53.100815 PLL_FREQ = 2366
2194 12:20:53.100940 DQ_UI_PI_RATIO = 32
2195 12:20:53.105024 CA_UI_PI_RATIO = 0
2196 12:20:53.107828 ===================================
2197 12:20:53.111451 ===================================
2198 12:20:53.114836 memory_type:LPDDR4
2199 12:20:53.118143 GP_NUM : 10
2200 12:20:53.118239 SRAM_EN : 1
2201 12:20:53.121256 MD32_EN : 0
2202 12:20:53.124850 ===================================
2203 12:20:53.124947 [ANA_INIT] >>>>>>>>>>>>>>
2204 12:20:53.127654 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 12:20:53.131257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 12:20:53.134271 ===================================
2207 12:20:53.137259 data_rate = 2400,PCW = 0X5b00
2208 12:20:53.141473 ===================================
2209 12:20:53.144122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 12:20:53.151929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 12:20:53.157578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 12:20:53.160985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 12:20:53.164221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 12:20:53.168325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 12:20:53.170404 [ANA_INIT] flow start
2216 12:20:53.170510 [ANA_INIT] PLL >>>>>>>>
2217 12:20:53.174469 [ANA_INIT] PLL <<<<<<<<
2218 12:20:53.177412 [ANA_INIT] MIDPI >>>>>>>>
2219 12:20:53.177493 [ANA_INIT] MIDPI <<<<<<<<
2220 12:20:53.180387 [ANA_INIT] DLL >>>>>>>>
2221 12:20:53.184106 [ANA_INIT] DLL <<<<<<<<
2222 12:20:53.184191 [ANA_INIT] flow end
2223 12:20:53.190702 ============ LP4 DIFF to SE enter ============
2224 12:20:53.193979 ============ LP4 DIFF to SE exit ============
2225 12:20:53.196916 [ANA_INIT] <<<<<<<<<<<<<
2226 12:20:53.201041 [Flow] Enable top DCM control >>>>>
2227 12:20:53.203755 [Flow] Enable top DCM control <<<<<
2228 12:20:53.203862 Enable DLL master slave shuffle
2229 12:20:53.210682 ==============================================================
2230 12:20:53.213578 Gating Mode config
2231 12:20:53.217257 ==============================================================
2232 12:20:53.220537 Config description:
2233 12:20:53.231117 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 12:20:53.237544 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 12:20:53.240503 SELPH_MODE 0: By rank 1: By Phase
2236 12:20:53.247396 ==============================================================
2237 12:20:53.250847 GAT_TRACK_EN = 1
2238 12:20:53.253663 RX_GATING_MODE = 2
2239 12:20:53.256889 RX_GATING_TRACK_MODE = 2
2240 12:20:53.256969 SELPH_MODE = 1
2241 12:20:53.260292 PICG_EARLY_EN = 1
2242 12:20:53.263472 VALID_LAT_VALUE = 1
2243 12:20:53.270603 ==============================================================
2244 12:20:53.273493 Enter into Gating configuration >>>>
2245 12:20:53.276859 Exit from Gating configuration <<<<
2246 12:20:53.280114 Enter into DVFS_PRE_config >>>>>
2247 12:20:53.290713 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 12:20:53.293619 Exit from DVFS_PRE_config <<<<<
2249 12:20:53.296640 Enter into PICG configuration >>>>
2250 12:20:53.300356 Exit from PICG configuration <<<<
2251 12:20:53.303588 [RX_INPUT] configuration >>>>>
2252 12:20:53.307348 [RX_INPUT] configuration <<<<<
2253 12:20:53.310610 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 12:20:53.316666 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 12:20:53.323393 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 12:20:53.330248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 12:20:53.336978 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 12:20:53.339879 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 12:20:53.346530 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 12:20:53.349630 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 12:20:53.353811 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 12:20:53.356603 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 12:20:53.362713 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 12:20:53.366055 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 12:20:53.369674 ===================================
2266 12:20:53.372724 LPDDR4 DRAM CONFIGURATION
2267 12:20:53.376947 ===================================
2268 12:20:53.377029 EX_ROW_EN[0] = 0x0
2269 12:20:53.379753 EX_ROW_EN[1] = 0x0
2270 12:20:53.379822 LP4Y_EN = 0x0
2271 12:20:53.383253 WORK_FSP = 0x0
2272 12:20:53.383334 WL = 0x4
2273 12:20:53.386099 RL = 0x4
2274 12:20:53.386179 BL = 0x2
2275 12:20:53.389505 RPST = 0x0
2276 12:20:53.392717 RD_PRE = 0x0
2277 12:20:53.392823 WR_PRE = 0x1
2278 12:20:53.396104 WR_PST = 0x0
2279 12:20:53.396184 DBI_WR = 0x0
2280 12:20:53.399178 DBI_RD = 0x0
2281 12:20:53.399272 OTF = 0x1
2282 12:20:53.402517 ===================================
2283 12:20:53.405946 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 12:20:53.412311 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 12:20:53.416232 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 12:20:53.419798 ===================================
2287 12:20:53.422240 LPDDR4 DRAM CONFIGURATION
2288 12:20:53.426005 ===================================
2289 12:20:53.426086 EX_ROW_EN[0] = 0x10
2290 12:20:53.429452 EX_ROW_EN[1] = 0x0
2291 12:20:53.429533 LP4Y_EN = 0x0
2292 12:20:53.432170 WORK_FSP = 0x0
2293 12:20:53.432251 WL = 0x4
2294 12:20:53.436181 RL = 0x4
2295 12:20:53.436262 BL = 0x2
2296 12:20:53.438924 RPST = 0x0
2297 12:20:53.442821 RD_PRE = 0x0
2298 12:20:53.442901 WR_PRE = 0x1
2299 12:20:53.446004 WR_PST = 0x0
2300 12:20:53.446084 DBI_WR = 0x0
2301 12:20:53.449146 DBI_RD = 0x0
2302 12:20:53.449225 OTF = 0x1
2303 12:20:53.452244 ===================================
2304 12:20:53.459432 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 12:20:53.459514 ==
2306 12:20:53.463730 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 12:20:53.465560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 12:20:53.465642 ==
2309 12:20:53.469165 [Duty_Offset_Calibration]
2310 12:20:53.471724 B0:2 B1:0 CA:4
2311 12:20:53.471827
2312 12:20:53.475393 [DutyScan_Calibration_Flow] k_type=0
2313 12:20:53.482719
2314 12:20:53.482802 ==CLK 0==
2315 12:20:53.485732 Final CLK duty delay cell = -4
2316 12:20:53.489078 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2317 12:20:53.492500 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2318 12:20:53.495551 [-4] AVG Duty = 4937%(X100)
2319 12:20:53.495633
2320 12:20:53.499502 CH0 CLK Duty spec in!! Max-Min= 187%
2321 12:20:53.502423 [DutyScan_Calibration_Flow] ====Done====
2322 12:20:53.502499
2323 12:20:53.506009 [DutyScan_Calibration_Flow] k_type=1
2324 12:20:53.521462
2325 12:20:53.521549 ==DQS 0 ==
2326 12:20:53.524785 Final DQS duty delay cell = -4
2327 12:20:53.527895 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2328 12:20:53.532133 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2329 12:20:53.534813 [-4] AVG Duty = 4922%(X100)
2330 12:20:53.534894
2331 12:20:53.534957 ==DQS 1 ==
2332 12:20:53.537812 Final DQS duty delay cell = 0
2333 12:20:53.541161 [0] MAX Duty = 5125%(X100), DQS PI = 6
2334 12:20:53.545016 [0] MIN Duty = 5000%(X100), DQS PI = 0
2335 12:20:53.548854 [0] AVG Duty = 5062%(X100)
2336 12:20:53.548936
2337 12:20:53.551417 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2338 12:20:53.551498
2339 12:20:53.554628 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2340 12:20:53.557678 [DutyScan_Calibration_Flow] ====Done====
2341 12:20:53.557759
2342 12:20:53.560795 [DutyScan_Calibration_Flow] k_type=3
2343 12:20:53.578214
2344 12:20:53.578314 ==DQM 0 ==
2345 12:20:53.581226 Final DQM duty delay cell = 0
2346 12:20:53.584482 [0] MAX Duty = 5125%(X100), DQS PI = 20
2347 12:20:53.587615 [0] MIN Duty = 4844%(X100), DQS PI = 52
2348 12:20:53.590955 [0] AVG Duty = 4984%(X100)
2349 12:20:53.591036
2350 12:20:53.591101 ==DQM 1 ==
2351 12:20:53.594640 Final DQM duty delay cell = 0
2352 12:20:53.598291 [0] MAX Duty = 4969%(X100), DQS PI = 0
2353 12:20:53.601136 [0] MIN Duty = 4907%(X100), DQS PI = 12
2354 12:20:53.605283 [0] AVG Duty = 4938%(X100)
2355 12:20:53.605364
2356 12:20:53.607875 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2357 12:20:53.608006
2358 12:20:53.610863 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2359 12:20:53.614386 [DutyScan_Calibration_Flow] ====Done====
2360 12:20:53.614467
2361 12:20:53.617589 [DutyScan_Calibration_Flow] k_type=2
2362 12:20:53.634657
2363 12:20:53.634752 ==DQ 0 ==
2364 12:20:53.637731 Final DQ duty delay cell = 0
2365 12:20:53.641074 [0] MAX Duty = 5125%(X100), DQS PI = 18
2366 12:20:53.644210 [0] MIN Duty = 4969%(X100), DQS PI = 58
2367 12:20:53.644294 [0] AVG Duty = 5047%(X100)
2368 12:20:53.648045
2369 12:20:53.648127 ==DQ 1 ==
2370 12:20:53.650715 Final DQ duty delay cell = 0
2371 12:20:53.654066 [0] MAX Duty = 5125%(X100), DQS PI = 4
2372 12:20:53.658404 [0] MIN Duty = 4938%(X100), DQS PI = 16
2373 12:20:53.658487 [0] AVG Duty = 5031%(X100)
2374 12:20:53.658550
2375 12:20:53.660718 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2376 12:20:53.664511
2377 12:20:53.667319 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2378 12:20:53.670645 [DutyScan_Calibration_Flow] ====Done====
2379 12:20:53.670727 ==
2380 12:20:53.674188 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 12:20:53.677260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 12:20:53.677343 ==
2383 12:20:53.680583 [Duty_Offset_Calibration]
2384 12:20:53.680666 B0:0 B1:-1 CA:3
2385 12:20:53.680730
2386 12:20:53.684468 [DutyScan_Calibration_Flow] k_type=0
2387 12:20:53.693240
2388 12:20:53.693322 ==CLK 0==
2389 12:20:53.696993 Final CLK duty delay cell = -4
2390 12:20:53.700886 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2391 12:20:53.703374 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2392 12:20:53.707110 [-4] AVG Duty = 4938%(X100)
2393 12:20:53.707192
2394 12:20:53.710109 CH1 CLK Duty spec in!! Max-Min= 124%
2395 12:20:53.714123 [DutyScan_Calibration_Flow] ====Done====
2396 12:20:53.714205
2397 12:20:53.717312 [DutyScan_Calibration_Flow] k_type=1
2398 12:20:53.732920
2399 12:20:53.733007 ==DQS 0 ==
2400 12:20:53.736675 Final DQS duty delay cell = 0
2401 12:20:53.739488 [0] MAX Duty = 5187%(X100), DQS PI = 18
2402 12:20:53.743126 [0] MIN Duty = 4907%(X100), DQS PI = 38
2403 12:20:53.743209 [0] AVG Duty = 5047%(X100)
2404 12:20:53.746855
2405 12:20:53.746937 ==DQS 1 ==
2406 12:20:53.749955 Final DQS duty delay cell = 0
2407 12:20:53.753154 [0] MAX Duty = 5156%(X100), DQS PI = 10
2408 12:20:53.757006 [0] MIN Duty = 5031%(X100), DQS PI = 20
2409 12:20:53.757088 [0] AVG Duty = 5093%(X100)
2410 12:20:53.759799
2411 12:20:53.763023 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2412 12:20:53.763135
2413 12:20:53.766548 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2414 12:20:53.769642 [DutyScan_Calibration_Flow] ====Done====
2415 12:20:53.769724
2416 12:20:53.773433 [DutyScan_Calibration_Flow] k_type=3
2417 12:20:53.789696
2418 12:20:53.789786 ==DQM 0 ==
2419 12:20:53.792932 Final DQM duty delay cell = 0
2420 12:20:53.796442 [0] MAX Duty = 5031%(X100), DQS PI = 28
2421 12:20:53.799812 [0] MIN Duty = 4813%(X100), DQS PI = 38
2422 12:20:53.802860 [0] AVG Duty = 4922%(X100)
2423 12:20:53.802942
2424 12:20:53.803006 ==DQM 1 ==
2425 12:20:53.806097 Final DQM duty delay cell = 0
2426 12:20:53.809493 [0] MAX Duty = 5000%(X100), DQS PI = 34
2427 12:20:53.812742 [0] MIN Duty = 4844%(X100), DQS PI = 0
2428 12:20:53.816307 [0] AVG Duty = 4922%(X100)
2429 12:20:53.816389
2430 12:20:53.819519 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2431 12:20:53.819600
2432 12:20:53.822894 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2433 12:20:53.826139 [DutyScan_Calibration_Flow] ====Done====
2434 12:20:53.826220
2435 12:20:53.829319 [DutyScan_Calibration_Flow] k_type=2
2436 12:20:53.845257
2437 12:20:53.845349 ==DQ 0 ==
2438 12:20:53.848824 Final DQ duty delay cell = -4
2439 12:20:53.852101 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2440 12:20:53.855330 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2441 12:20:53.858359 [-4] AVG Duty = 4937%(X100)
2442 12:20:53.858441
2443 12:20:53.858506 ==DQ 1 ==
2444 12:20:53.862139 Final DQ duty delay cell = 0
2445 12:20:53.865415 [0] MAX Duty = 5031%(X100), DQS PI = 34
2446 12:20:53.868746 [0] MIN Duty = 4844%(X100), DQS PI = 62
2447 12:20:53.871871 [0] AVG Duty = 4937%(X100)
2448 12:20:53.871994
2449 12:20:53.875502 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2450 12:20:53.875585
2451 12:20:53.878515 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2452 12:20:53.881931 [DutyScan_Calibration_Flow] ====Done====
2453 12:20:53.885012 nWR fixed to 30
2454 12:20:53.888181 [ModeRegInit_LP4] CH0 RK0
2455 12:20:53.888263 [ModeRegInit_LP4] CH0 RK1
2456 12:20:53.891770 [ModeRegInit_LP4] CH1 RK0
2457 12:20:53.895288 [ModeRegInit_LP4] CH1 RK1
2458 12:20:53.895370 match AC timing 7
2459 12:20:53.901518 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 12:20:53.905086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 12:20:53.908750 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 12:20:53.914980 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 12:20:53.918229 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 12:20:53.918311 ==
2465 12:20:53.921719 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 12:20:53.924915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 12:20:53.924998 ==
2468 12:20:53.932480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 12:20:53.938027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 12:20:53.945689 [CA 0] Center 39 (9~70) winsize 62
2471 12:20:53.949112 [CA 1] Center 39 (9~70) winsize 62
2472 12:20:53.952178 [CA 2] Center 35 (5~66) winsize 62
2473 12:20:53.955867 [CA 3] Center 35 (5~66) winsize 62
2474 12:20:53.959022 [CA 4] Center 33 (3~64) winsize 62
2475 12:20:53.962176 [CA 5] Center 33 (3~63) winsize 61
2476 12:20:53.962275
2477 12:20:53.965283 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 12:20:53.965365
2479 12:20:53.968915 [CATrainingPosCal] consider 1 rank data
2480 12:20:53.972034 u2DelayCellTimex100 = 270/100 ps
2481 12:20:53.975616 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2482 12:20:53.981839 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2483 12:20:53.985420 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 12:20:53.988575 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2485 12:20:53.992321 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2486 12:20:53.995665 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2487 12:20:53.995747
2488 12:20:53.998351 CA PerBit enable=1, Macro0, CA PI delay=33
2489 12:20:53.998434
2490 12:20:54.001808 [CBTSetCACLKResult] CA Dly = 33
2491 12:20:54.005264 CS Dly: 7 (0~38)
2492 12:20:54.005346 ==
2493 12:20:54.008430 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 12:20:54.012085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 12:20:54.012168 ==
2496 12:20:54.018669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 12:20:54.021526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2498 12:20:54.031448 [CA 0] Center 39 (9~70) winsize 62
2499 12:20:54.034894 [CA 1] Center 39 (9~70) winsize 62
2500 12:20:54.037807 [CA 2] Center 35 (5~66) winsize 62
2501 12:20:54.041704 [CA 3] Center 35 (5~66) winsize 62
2502 12:20:54.044580 [CA 4] Center 34 (4~65) winsize 62
2503 12:20:54.047761 [CA 5] Center 33 (3~64) winsize 62
2504 12:20:54.047868
2505 12:20:54.051077 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2506 12:20:54.051159
2507 12:20:54.054806 [CATrainingPosCal] consider 2 rank data
2508 12:20:54.058316 u2DelayCellTimex100 = 270/100 ps
2509 12:20:54.061108 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2510 12:20:54.068608 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2511 12:20:54.070769 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 12:20:54.074157 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 12:20:54.077777 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2514 12:20:54.081326 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2515 12:20:54.081408
2516 12:20:54.084204 CA PerBit enable=1, Macro0, CA PI delay=33
2517 12:20:54.084287
2518 12:20:54.087882 [CBTSetCACLKResult] CA Dly = 33
2519 12:20:54.091147 CS Dly: 8 (0~41)
2520 12:20:54.091233
2521 12:20:54.093955 ----->DramcWriteLeveling(PI) begin...
2522 12:20:54.094083 ==
2523 12:20:54.097529 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 12:20:54.100708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 12:20:54.100792 ==
2526 12:20:54.104940 Write leveling (Byte 0): 32 => 32
2527 12:20:54.107102 Write leveling (Byte 1): 27 => 27
2528 12:20:54.111460 DramcWriteLeveling(PI) end<-----
2529 12:20:54.111541
2530 12:20:54.111605 ==
2531 12:20:54.114210 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 12:20:54.117419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 12:20:54.117502 ==
2534 12:20:54.120566 [Gating] SW mode calibration
2535 12:20:54.127195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 12:20:54.134109 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 12:20:54.137652 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2538 12:20:54.141237 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2539 12:20:54.147346 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 12:20:54.150554 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 12:20:54.153935 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 12:20:54.160645 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 12:20:54.163943 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 12:20:54.167541 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2545 12:20:54.173971 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2546 12:20:54.177082 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2547 12:20:54.180918 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 12:20:54.187094 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 12:20:54.191061 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 12:20:54.193679 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 12:20:54.200836 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2552 12:20:54.203619 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2553 12:20:54.207080 1 1 0 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
2554 12:20:54.213414 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2555 12:20:54.217083 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 12:20:54.220019 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:20:54.226583 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:20:54.229993 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:20:54.233523 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2560 12:20:54.236943 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2561 12:20:54.243255 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 12:20:54.246990 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:20:54.250230 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:20:54.256797 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:20:54.259817 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:20:54.263178 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:20:54.270163 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:20:54.273520 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:20:54.276675 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:20:54.282982 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:20:54.286642 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:20:54.290365 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:20:54.296534 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:20:54.299851 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 12:20:54.303016 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 12:20:54.309646 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 12:20:54.313552 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2578 12:20:54.316338 Total UI for P1: 0, mck2ui 16
2579 12:20:54.320047 best dqsien dly found for B0: ( 1, 3, 28)
2580 12:20:54.323263 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2581 12:20:54.329878 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 12:20:54.330050 Total UI for P1: 0, mck2ui 16
2583 12:20:54.336249 best dqsien dly found for B1: ( 1, 4, 2)
2584 12:20:54.339774 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2585 12:20:54.343082 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2586 12:20:54.343271
2587 12:20:54.346813 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2588 12:20:54.349837 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2589 12:20:54.353176 [Gating] SW calibration Done
2590 12:20:54.353373 ==
2591 12:20:54.356215 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 12:20:54.360625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 12:20:54.361085 ==
2594 12:20:54.363480 RX Vref Scan: 0
2595 12:20:54.363857
2596 12:20:54.364209 RX Vref 0 -> 0, step: 1
2597 12:20:54.364496
2598 12:20:54.366610 RX Delay -40 -> 252, step: 8
2599 12:20:54.369838 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2600 12:20:54.376447 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2601 12:20:54.379590 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2602 12:20:54.383746 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2603 12:20:54.386553 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2604 12:20:54.390224 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2605 12:20:54.397108 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2606 12:20:54.399758 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2607 12:20:54.403432 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2608 12:20:54.406697 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2609 12:20:54.409998 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2610 12:20:54.416791 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2611 12:20:54.419771 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2612 12:20:54.423285 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2613 12:20:54.426476 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2614 12:20:54.429971 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2615 12:20:54.432859 ==
2616 12:20:54.433260 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 12:20:54.440049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 12:20:54.440588 ==
2619 12:20:54.441067 DQS Delay:
2620 12:20:54.443079 DQS0 = 0, DQS1 = 0
2621 12:20:54.443459 DQM Delay:
2622 12:20:54.446228 DQM0 = 117, DQM1 = 107
2623 12:20:54.446609 DQ Delay:
2624 12:20:54.450926 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2625 12:20:54.453722 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2626 12:20:54.456865 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2627 12:20:54.460027 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2628 12:20:54.460514
2629 12:20:54.460820
2630 12:20:54.461098 ==
2631 12:20:54.462979 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 12:20:54.466412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 12:20:54.470858 ==
2634 12:20:54.471407
2635 12:20:54.471714
2636 12:20:54.472048 TX Vref Scan disable
2637 12:20:54.472759 == TX Byte 0 ==
2638 12:20:54.476132 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2639 12:20:54.479567 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2640 12:20:54.483218 == TX Byte 1 ==
2641 12:20:54.486166 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2642 12:20:54.489971 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2643 12:20:54.492676 ==
2644 12:20:54.496400 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 12:20:54.499491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 12:20:54.500017 ==
2647 12:20:54.510794 TX Vref=22, minBit 10, minWin=24, winSum=413
2648 12:20:54.514170 TX Vref=24, minBit 10, minWin=24, winSum=417
2649 12:20:54.518307 TX Vref=26, minBit 4, minWin=25, winSum=422
2650 12:20:54.521356 TX Vref=28, minBit 7, minWin=26, winSum=428
2651 12:20:54.523869 TX Vref=30, minBit 4, minWin=26, winSum=429
2652 12:20:54.531047 TX Vref=32, minBit 4, minWin=26, winSum=429
2653 12:20:54.533767 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 30
2654 12:20:54.534147
2655 12:20:54.537134 Final TX Range 1 Vref 30
2656 12:20:54.537513
2657 12:20:54.537814 ==
2658 12:20:54.540701 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 12:20:54.544198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 12:20:54.546925 ==
2661 12:20:54.547324
2662 12:20:54.547645
2663 12:20:54.548075 TX Vref Scan disable
2664 12:20:54.550682 == TX Byte 0 ==
2665 12:20:54.553905 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2666 12:20:54.560993 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2667 12:20:54.561380 == TX Byte 1 ==
2668 12:20:54.564229 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2669 12:20:54.570545 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2670 12:20:54.570894
2671 12:20:54.571169 [DATLAT]
2672 12:20:54.571482 Freq=1200, CH0 RK0
2673 12:20:54.571744
2674 12:20:54.573800 DATLAT Default: 0xd
2675 12:20:54.574158 0, 0xFFFF, sum = 0
2676 12:20:54.577499 1, 0xFFFF, sum = 0
2677 12:20:54.581240 2, 0xFFFF, sum = 0
2678 12:20:54.581595 3, 0xFFFF, sum = 0
2679 12:20:54.583977 4, 0xFFFF, sum = 0
2680 12:20:54.584338 5, 0xFFFF, sum = 0
2681 12:20:54.587389 6, 0xFFFF, sum = 0
2682 12:20:54.587769 7, 0xFFFF, sum = 0
2683 12:20:54.590996 8, 0xFFFF, sum = 0
2684 12:20:54.591351 9, 0xFFFF, sum = 0
2685 12:20:54.593831 10, 0xFFFF, sum = 0
2686 12:20:54.594189 11, 0xFFFF, sum = 0
2687 12:20:54.597734 12, 0x0, sum = 1
2688 12:20:54.598203 13, 0x0, sum = 2
2689 12:20:54.601245 14, 0x0, sum = 3
2690 12:20:54.601606 15, 0x0, sum = 4
2691 12:20:54.604313 best_step = 13
2692 12:20:54.604662
2693 12:20:54.604975 ==
2694 12:20:54.607383 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 12:20:54.610906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 12:20:54.611370 ==
2697 12:20:54.611657 RX Vref Scan: 1
2698 12:20:54.611987
2699 12:20:54.614159 Set Vref Range= 32 -> 127
2700 12:20:54.614616
2701 12:20:54.617740 RX Vref 32 -> 127, step: 1
2702 12:20:54.618228
2703 12:20:54.620728 RX Delay -21 -> 252, step: 4
2704 12:20:54.621110
2705 12:20:54.623853 Set Vref, RX VrefLevel [Byte0]: 32
2706 12:20:54.627314 [Byte1]: 32
2707 12:20:54.627805
2708 12:20:54.630370 Set Vref, RX VrefLevel [Byte0]: 33
2709 12:20:54.633739 [Byte1]: 33
2710 12:20:54.637348
2711 12:20:54.637728 Set Vref, RX VrefLevel [Byte0]: 34
2712 12:20:54.640847 [Byte1]: 34
2713 12:20:54.645283
2714 12:20:54.645667 Set Vref, RX VrefLevel [Byte0]: 35
2715 12:20:54.648289 [Byte1]: 35
2716 12:20:54.653185
2717 12:20:54.653578 Set Vref, RX VrefLevel [Byte0]: 36
2718 12:20:54.656523 [Byte1]: 36
2719 12:20:54.661294
2720 12:20:54.661687 Set Vref, RX VrefLevel [Byte0]: 37
2721 12:20:54.667608 [Byte1]: 37
2722 12:20:54.668014
2723 12:20:54.671000 Set Vref, RX VrefLevel [Byte0]: 38
2724 12:20:54.674368 [Byte1]: 38
2725 12:20:54.674716
2726 12:20:54.677998 Set Vref, RX VrefLevel [Byte0]: 39
2727 12:20:54.680820 [Byte1]: 39
2728 12:20:54.684708
2729 12:20:54.685057 Set Vref, RX VrefLevel [Byte0]: 40
2730 12:20:54.687943 [Byte1]: 40
2731 12:20:54.692822
2732 12:20:54.693167 Set Vref, RX VrefLevel [Byte0]: 41
2733 12:20:54.696090 [Byte1]: 41
2734 12:20:54.700862
2735 12:20:54.701314 Set Vref, RX VrefLevel [Byte0]: 42
2736 12:20:54.703831 [Byte1]: 42
2737 12:20:54.708882
2738 12:20:54.709235 Set Vref, RX VrefLevel [Byte0]: 43
2739 12:20:54.711886 [Byte1]: 43
2740 12:20:54.716458
2741 12:20:54.716814 Set Vref, RX VrefLevel [Byte0]: 44
2742 12:20:54.720286 [Byte1]: 44
2743 12:20:54.724599
2744 12:20:54.725053 Set Vref, RX VrefLevel [Byte0]: 45
2745 12:20:54.727928 [Byte1]: 45
2746 12:20:54.732371
2747 12:20:54.732719 Set Vref, RX VrefLevel [Byte0]: 46
2748 12:20:54.736223 [Byte1]: 46
2749 12:20:54.740642
2750 12:20:54.741102 Set Vref, RX VrefLevel [Byte0]: 47
2751 12:20:54.743540 [Byte1]: 47
2752 12:20:54.748656
2753 12:20:54.749140 Set Vref, RX VrefLevel [Byte0]: 48
2754 12:20:54.751895 [Byte1]: 48
2755 12:20:54.756389
2756 12:20:54.756874 Set Vref, RX VrefLevel [Byte0]: 49
2757 12:20:54.759968 [Byte1]: 49
2758 12:20:54.764552
2759 12:20:54.764936 Set Vref, RX VrefLevel [Byte0]: 50
2760 12:20:54.767731 [Byte1]: 50
2761 12:20:54.772007
2762 12:20:54.772358 Set Vref, RX VrefLevel [Byte0]: 51
2763 12:20:54.775117 [Byte1]: 51
2764 12:20:54.780073
2765 12:20:54.780452 Set Vref, RX VrefLevel [Byte0]: 52
2766 12:20:54.783684 [Byte1]: 52
2767 12:20:54.788454
2768 12:20:54.788938 Set Vref, RX VrefLevel [Byte0]: 53
2769 12:20:54.791651 [Byte1]: 53
2770 12:20:54.796198
2771 12:20:54.799654 Set Vref, RX VrefLevel [Byte0]: 54
2772 12:20:54.800202 [Byte1]: 54
2773 12:20:54.804133
2774 12:20:54.804514 Set Vref, RX VrefLevel [Byte0]: 55
2775 12:20:54.807287 [Byte1]: 55
2776 12:20:54.811983
2777 12:20:54.812466 Set Vref, RX VrefLevel [Byte0]: 56
2778 12:20:54.815305 [Byte1]: 56
2779 12:20:54.819531
2780 12:20:54.820062 Set Vref, RX VrefLevel [Byte0]: 57
2781 12:20:54.823557 [Byte1]: 57
2782 12:20:54.828778
2783 12:20:54.829285 Set Vref, RX VrefLevel [Byte0]: 58
2784 12:20:54.831298 [Byte1]: 58
2785 12:20:54.836073
2786 12:20:54.836594 Set Vref, RX VrefLevel [Byte0]: 59
2787 12:20:54.839157 [Byte1]: 59
2788 12:20:54.843475
2789 12:20:54.844043 Set Vref, RX VrefLevel [Byte0]: 60
2790 12:20:54.847044 [Byte1]: 60
2791 12:20:54.851748
2792 12:20:54.852315 Set Vref, RX VrefLevel [Byte0]: 61
2793 12:20:54.854804 [Byte1]: 61
2794 12:20:54.859958
2795 12:20:54.860474 Set Vref, RX VrefLevel [Byte0]: 62
2796 12:20:54.862601 [Byte1]: 62
2797 12:20:54.867388
2798 12:20:54.867830 Set Vref, RX VrefLevel [Byte0]: 63
2799 12:20:54.870311 [Byte1]: 63
2800 12:20:54.874924
2801 12:20:54.875335 Set Vref, RX VrefLevel [Byte0]: 64
2802 12:20:54.878526 [Byte1]: 64
2803 12:20:54.882833
2804 12:20:54.883350 Set Vref, RX VrefLevel [Byte0]: 65
2805 12:20:54.886402 [Byte1]: 65
2806 12:20:54.890791
2807 12:20:54.891171 Set Vref, RX VrefLevel [Byte0]: 66
2808 12:20:54.897364 [Byte1]: 66
2809 12:20:54.897745
2810 12:20:54.900574 Set Vref, RX VrefLevel [Byte0]: 67
2811 12:20:54.903623 [Byte1]: 67
2812 12:20:54.904125
2813 12:20:54.907438 Set Vref, RX VrefLevel [Byte0]: 68
2814 12:20:54.910995 [Byte1]: 68
2815 12:20:54.914500
2816 12:20:54.914878 Set Vref, RX VrefLevel [Byte0]: 69
2817 12:20:54.918386 [Byte1]: 69
2818 12:20:54.922706
2819 12:20:54.923088 Final RX Vref Byte 0 = 51 to rank0
2820 12:20:54.925976 Final RX Vref Byte 1 = 49 to rank0
2821 12:20:54.929204 Final RX Vref Byte 0 = 51 to rank1
2822 12:20:54.932344 Final RX Vref Byte 1 = 49 to rank1==
2823 12:20:54.935590 Dram Type= 6, Freq= 0, CH_0, rank 0
2824 12:20:54.942414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 12:20:54.942800 ==
2826 12:20:54.943106 DQS Delay:
2827 12:20:54.943389 DQS0 = 0, DQS1 = 0
2828 12:20:54.946265 DQM Delay:
2829 12:20:54.946647 DQM0 = 117, DQM1 = 104
2830 12:20:54.949633 DQ Delay:
2831 12:20:54.952565 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2832 12:20:54.955731 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2833 12:20:54.958793 DQ8 =92, DQ9 =88, DQ10 =104, DQ11 =100
2834 12:20:54.962495 DQ12 =112, DQ13 =108, DQ14 =116, DQ15 =112
2835 12:20:54.962986
2836 12:20:54.963365
2837 12:20:54.969218 [DQSOSCAuto] RK0, (LSB)MR18= 0xfffa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2838 12:20:54.972788 CH0 RK0: MR19=303, MR18=FFFA
2839 12:20:54.979186 CH0_RK0: MR19=0x303, MR18=0xFFFA, DQSOSC=410, MR23=63, INC=39, DEC=26
2840 12:20:54.979679
2841 12:20:54.982784 ----->DramcWriteLeveling(PI) begin...
2842 12:20:54.983311 ==
2843 12:20:54.985517 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 12:20:54.992570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 12:20:54.993099 ==
2846 12:20:54.995458 Write leveling (Byte 0): 32 => 32
2847 12:20:54.995870 Write leveling (Byte 1): 25 => 25
2848 12:20:54.999139 DramcWriteLeveling(PI) end<-----
2849 12:20:54.999665
2850 12:20:55.002569 ==
2851 12:20:55.002986 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 12:20:55.009285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 12:20:55.009802 ==
2854 12:20:55.012392 [Gating] SW mode calibration
2855 12:20:55.018632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2856 12:20:55.021944 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2857 12:20:55.028521 0 15 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2858 12:20:55.032052 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2859 12:20:55.035745 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 12:20:55.042010 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:20:55.045020 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 12:20:55.048305 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 12:20:55.055160 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2864 12:20:55.058477 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
2865 12:20:55.061996 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2866 12:20:55.068791 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 12:20:55.072538 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 12:20:55.075461 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:20:55.081825 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 12:20:55.085052 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 12:20:55.088474 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2872 12:20:55.091767 1 0 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2873 12:20:55.099270 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2874 12:20:55.101769 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 12:20:55.105112 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:20:55.112098 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:20:55.115394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:20:55.119047 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 12:20:55.125060 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2880 12:20:55.128872 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2881 12:20:55.132287 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2882 12:20:55.138323 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:20:55.141990 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:20:55.145018 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:20:55.151691 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:20:55.155390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:20:55.158165 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:20:55.164544 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:20:55.167973 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:20:55.171346 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:20:55.178062 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:20:55.180994 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:20:55.184973 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:20:55.191244 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:20:55.195380 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2896 12:20:55.197641 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 12:20:55.204815 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2898 12:20:55.205331 Total UI for P1: 0, mck2ui 16
2899 12:20:55.211980 best dqsien dly found for B0: ( 1, 3, 26)
2900 12:20:55.214177 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 12:20:55.217709 Total UI for P1: 0, mck2ui 16
2902 12:20:55.220938 best dqsien dly found for B1: ( 1, 4, 0)
2903 12:20:55.224323 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2904 12:20:55.227657 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2905 12:20:55.228215
2906 12:20:55.231217 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2907 12:20:55.234468 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2908 12:20:55.238316 [Gating] SW calibration Done
2909 12:20:55.238849 ==
2910 12:20:55.241198 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 12:20:55.244205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 12:20:55.244747 ==
2913 12:20:55.247556 RX Vref Scan: 0
2914 12:20:55.248124
2915 12:20:55.251054 RX Vref 0 -> 0, step: 1
2916 12:20:55.251470
2917 12:20:55.251800 RX Delay -40 -> 252, step: 8
2918 12:20:55.257589 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2919 12:20:55.260858 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2920 12:20:55.264035 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2921 12:20:55.267732 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2922 12:20:55.270770 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2923 12:20:55.277838 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2924 12:20:55.281078 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2925 12:20:55.284295 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2926 12:20:55.287625 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2927 12:20:55.290691 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2928 12:20:55.297646 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2929 12:20:55.300561 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2930 12:20:55.303835 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2931 12:20:55.307342 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2932 12:20:55.314050 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2933 12:20:55.317050 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2934 12:20:55.317488 ==
2935 12:20:55.320163 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 12:20:55.323494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 12:20:55.324019 ==
2938 12:20:55.324357 DQS Delay:
2939 12:20:55.327032 DQS0 = 0, DQS1 = 0
2940 12:20:55.327435 DQM Delay:
2941 12:20:55.330219 DQM0 = 115, DQM1 = 106
2942 12:20:55.330644 DQ Delay:
2943 12:20:55.333668 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2944 12:20:55.337318 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2945 12:20:55.340576 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2946 12:20:55.343948 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2947 12:20:55.347146
2948 12:20:55.347535
2949 12:20:55.347834 ==
2950 12:20:55.350066 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 12:20:55.353755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 12:20:55.354149 ==
2953 12:20:55.354470
2954 12:20:55.354757
2955 12:20:55.356640 TX Vref Scan disable
2956 12:20:55.357038 == TX Byte 0 ==
2957 12:20:55.363448 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2958 12:20:55.366968 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2959 12:20:55.367352 == TX Byte 1 ==
2960 12:20:55.374269 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2961 12:20:55.376883 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2962 12:20:55.377304 ==
2963 12:20:55.379942 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 12:20:55.383598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 12:20:55.384057 ==
2966 12:20:55.396569 TX Vref=22, minBit 13, minWin=25, winSum=418
2967 12:20:55.399936 TX Vref=24, minBit 13, minWin=25, winSum=426
2968 12:20:55.403061 TX Vref=26, minBit 13, minWin=25, winSum=428
2969 12:20:55.406699 TX Vref=28, minBit 13, minWin=25, winSum=425
2970 12:20:55.409816 TX Vref=30, minBit 10, minWin=26, winSum=431
2971 12:20:55.416899 TX Vref=32, minBit 8, minWin=26, winSum=431
2972 12:20:55.419948 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
2973 12:20:55.420470
2974 12:20:55.423343 Final TX Range 1 Vref 30
2975 12:20:55.423866
2976 12:20:55.424259 ==
2977 12:20:55.426531 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 12:20:55.433310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 12:20:55.433838 ==
2980 12:20:55.434177
2981 12:20:55.434484
2982 12:20:55.434775 TX Vref Scan disable
2983 12:20:55.437401 == TX Byte 0 ==
2984 12:20:55.440014 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2985 12:20:55.444002 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2986 12:20:55.447212 == TX Byte 1 ==
2987 12:20:55.450367 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2988 12:20:55.456818 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2989 12:20:55.457329
2990 12:20:55.457659 [DATLAT]
2991 12:20:55.457966 Freq=1200, CH0 RK1
2992 12:20:55.458264
2993 12:20:55.459667 DATLAT Default: 0xd
2994 12:20:55.463698 0, 0xFFFF, sum = 0
2995 12:20:55.464298 1, 0xFFFF, sum = 0
2996 12:20:55.466715 2, 0xFFFF, sum = 0
2997 12:20:55.467247 3, 0xFFFF, sum = 0
2998 12:20:55.469959 4, 0xFFFF, sum = 0
2999 12:20:55.470384 5, 0xFFFF, sum = 0
3000 12:20:55.473162 6, 0xFFFF, sum = 0
3001 12:20:55.473585 7, 0xFFFF, sum = 0
3002 12:20:55.476486 8, 0xFFFF, sum = 0
3003 12:20:55.476933 9, 0xFFFF, sum = 0
3004 12:20:55.479819 10, 0xFFFF, sum = 0
3005 12:20:55.480263 11, 0xFFFF, sum = 0
3006 12:20:55.483269 12, 0x0, sum = 1
3007 12:20:55.483693 13, 0x0, sum = 2
3008 12:20:55.486571 14, 0x0, sum = 3
3009 12:20:55.487119 15, 0x0, sum = 4
3010 12:20:55.490365 best_step = 13
3011 12:20:55.490923
3012 12:20:55.491435 ==
3013 12:20:55.493793 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 12:20:55.496285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 12:20:55.496704 ==
3016 12:20:55.497034 RX Vref Scan: 0
3017 12:20:55.499938
3018 12:20:55.500463 RX Vref 0 -> 0, step: 1
3019 12:20:55.500797
3020 12:20:55.503101 RX Delay -21 -> 252, step: 4
3021 12:20:55.510025 iDelay=191, Bit 0, Center 114 (51 ~ 178) 128
3022 12:20:55.513761 iDelay=191, Bit 1, Center 116 (47 ~ 186) 140
3023 12:20:55.516479 iDelay=191, Bit 2, Center 110 (43 ~ 178) 136
3024 12:20:55.519744 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3025 12:20:55.522795 iDelay=191, Bit 4, Center 118 (51 ~ 186) 136
3026 12:20:55.529345 iDelay=191, Bit 5, Center 108 (43 ~ 174) 132
3027 12:20:55.532601 iDelay=191, Bit 6, Center 124 (59 ~ 190) 132
3028 12:20:55.536374 iDelay=191, Bit 7, Center 120 (55 ~ 186) 132
3029 12:20:55.539459 iDelay=191, Bit 8, Center 96 (27 ~ 166) 140
3030 12:20:55.542489 iDelay=191, Bit 9, Center 92 (23 ~ 162) 140
3031 12:20:55.546487 iDelay=191, Bit 10, Center 106 (39 ~ 174) 136
3032 12:20:55.552936 iDelay=191, Bit 11, Center 98 (31 ~ 166) 136
3033 12:20:55.556658 iDelay=191, Bit 12, Center 110 (43 ~ 178) 136
3034 12:20:55.559247 iDelay=191, Bit 13, Center 110 (43 ~ 178) 136
3035 12:20:55.562798 iDelay=191, Bit 14, Center 118 (51 ~ 186) 136
3036 12:20:55.569297 iDelay=191, Bit 15, Center 110 (43 ~ 178) 136
3037 12:20:55.569811 ==
3038 12:20:55.572845 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 12:20:55.576075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 12:20:55.576594 ==
3041 12:20:55.576929 DQS Delay:
3042 12:20:55.579697 DQS0 = 0, DQS1 = 0
3043 12:20:55.580277 DQM Delay:
3044 12:20:55.583374 DQM0 = 115, DQM1 = 105
3045 12:20:55.583893 DQ Delay:
3046 12:20:55.586738 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3047 12:20:55.589763 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
3048 12:20:55.592646 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3049 12:20:55.596061 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =110
3050 12:20:55.596586
3051 12:20:55.596921
3052 12:20:55.605686 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3053 12:20:55.609688 CH0 RK1: MR19=303, MR18=FFFD
3054 12:20:55.613056 CH0_RK1: MR19=0x303, MR18=0xFFFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3055 12:20:55.615825 [RxdqsGatingPostProcess] freq 1200
3056 12:20:55.622562 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 12:20:55.625966 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 12:20:55.629609 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 12:20:55.632548 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 12:20:55.636010 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 12:20:55.639270 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 12:20:55.642562 best DQS1 dly(2T, 0.5T) = (0, 12)
3063 12:20:55.645804 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 12:20:55.648707 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3065 12:20:55.652262 Pre-setting of DQS Precalculation
3066 12:20:55.656200 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 12:20:55.656847 ==
3068 12:20:55.658710 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 12:20:55.662599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 12:20:55.663038 ==
3071 12:20:55.668763 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 12:20:55.675621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3073 12:20:55.683128 [CA 0] Center 38 (8~68) winsize 61
3074 12:20:55.686343 [CA 1] Center 37 (7~68) winsize 62
3075 12:20:55.689428 [CA 2] Center 35 (5~65) winsize 61
3076 12:20:55.692725 [CA 3] Center 34 (4~64) winsize 61
3077 12:20:55.696244 [CA 4] Center 34 (5~64) winsize 60
3078 12:20:55.699686 [CA 5] Center 33 (3~64) winsize 62
3079 12:20:55.700168
3080 12:20:55.702729 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3081 12:20:55.703140
3082 12:20:55.706341 [CATrainingPosCal] consider 1 rank data
3083 12:20:55.709906 u2DelayCellTimex100 = 270/100 ps
3084 12:20:55.712898 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3085 12:20:55.716353 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 12:20:55.722847 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 12:20:55.725879 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 12:20:55.729307 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3089 12:20:55.733226 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3090 12:20:55.733658
3091 12:20:55.736421 CA PerBit enable=1, Macro0, CA PI delay=33
3092 12:20:55.736841
3093 12:20:55.739720 [CBTSetCACLKResult] CA Dly = 33
3094 12:20:55.740186 CS Dly: 4 (0~35)
3095 12:20:55.743140 ==
3096 12:20:55.743554 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 12:20:55.749466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 12:20:55.749888 ==
3099 12:20:55.752709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 12:20:55.758898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3101 12:20:55.768541 [CA 0] Center 37 (7~68) winsize 62
3102 12:20:55.772188 [CA 1] Center 38 (8~68) winsize 61
3103 12:20:55.775149 [CA 2] Center 35 (5~65) winsize 61
3104 12:20:55.778942 [CA 3] Center 33 (3~64) winsize 62
3105 12:20:55.782031 [CA 4] Center 34 (4~64) winsize 61
3106 12:20:55.785117 [CA 5] Center 33 (3~63) winsize 61
3107 12:20:55.785501
3108 12:20:55.788553 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 12:20:55.788941
3110 12:20:55.791816 [CATrainingPosCal] consider 2 rank data
3111 12:20:55.795396 u2DelayCellTimex100 = 270/100 ps
3112 12:20:55.799087 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3113 12:20:55.802418 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3114 12:20:55.808802 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3115 12:20:55.812335 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 12:20:55.815086 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3117 12:20:55.818390 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3118 12:20:55.818845
3119 12:20:55.821815 CA PerBit enable=1, Macro0, CA PI delay=33
3120 12:20:55.822336
3121 12:20:55.824951 [CBTSetCACLKResult] CA Dly = 33
3122 12:20:55.825369 CS Dly: 6 (0~39)
3123 12:20:55.828461
3124 12:20:55.831349 ----->DramcWriteLeveling(PI) begin...
3125 12:20:55.831788 ==
3126 12:20:55.834602 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 12:20:55.838265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 12:20:55.838684 ==
3129 12:20:55.841366 Write leveling (Byte 0): 25 => 25
3130 12:20:55.844779 Write leveling (Byte 1): 27 => 27
3131 12:20:55.848002 DramcWriteLeveling(PI) end<-----
3132 12:20:55.848570
3133 12:20:55.848906 ==
3134 12:20:55.851533 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 12:20:55.854700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 12:20:55.855117 ==
3137 12:20:55.857916 [Gating] SW mode calibration
3138 12:20:55.864652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 12:20:55.871044 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 12:20:55.875032 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3141 12:20:55.877960 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 12:20:55.884448 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 12:20:55.887645 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 12:20:55.891445 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 12:20:55.897894 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 12:20:55.900786 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
3147 12:20:55.904199 0 15 28 | B1->B0 | 2929 2424 | 0 0 | (1 0) (1 0)
3148 12:20:55.911023 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 12:20:55.914734 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 12:20:55.917739 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 12:20:55.924145 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:20:55.927380 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:20:55.930834 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 12:20:55.937638 1 0 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
3155 12:20:55.941342 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
3156 12:20:55.944529 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 12:20:55.947817 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:20:55.954548 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 12:20:55.958041 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:20:55.961277 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:20:55.967455 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:20:55.971036 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3163 12:20:55.974158 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3164 12:20:55.980445 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:20:55.984195 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:20:55.987130 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:20:55.994248 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:20:55.997357 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:20:56.000390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:20:56.007069 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:20:56.010448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:20:56.013697 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:20:56.020559 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:20:56.024229 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:20:56.027407 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:20:56.033692 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:20:56.037194 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:20:56.040206 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3179 12:20:56.046877 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3180 12:20:56.050651 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 12:20:56.053691 Total UI for P1: 0, mck2ui 16
3182 12:20:56.056857 best dqsien dly found for B0: ( 1, 3, 26)
3183 12:20:56.060175 Total UI for P1: 0, mck2ui 16
3184 12:20:56.063796 best dqsien dly found for B1: ( 1, 3, 28)
3185 12:20:56.066983 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3186 12:20:56.070029 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3187 12:20:56.070454
3188 12:20:56.073713 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3189 12:20:56.077369 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3190 12:20:56.080761 [Gating] SW calibration Done
3191 12:20:56.081183 ==
3192 12:20:56.083615 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 12:20:56.087264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 12:20:56.090371 ==
3195 12:20:56.090794 RX Vref Scan: 0
3196 12:20:56.091129
3197 12:20:56.093873 RX Vref 0 -> 0, step: 1
3198 12:20:56.094396
3199 12:20:56.094735 RX Delay -40 -> 252, step: 8
3200 12:20:56.100584 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3201 12:20:56.103717 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3202 12:20:56.106796 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3203 12:20:56.110322 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3204 12:20:56.113674 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3205 12:20:56.120135 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3206 12:20:56.123859 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3207 12:20:56.127030 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3208 12:20:56.130347 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3209 12:20:56.133930 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3210 12:20:56.140262 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3211 12:20:56.143694 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3212 12:20:56.146786 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3213 12:20:56.150672 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3214 12:20:56.157248 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3215 12:20:56.159890 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3216 12:20:56.160355 ==
3217 12:20:56.163596 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 12:20:56.166851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 12:20:56.167277 ==
3220 12:20:56.169868 DQS Delay:
3221 12:20:56.170290 DQS0 = 0, DQS1 = 0
3222 12:20:56.170625 DQM Delay:
3223 12:20:56.173060 DQM0 = 115, DQM1 = 113
3224 12:20:56.173483 DQ Delay:
3225 12:20:56.176805 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3226 12:20:56.180559 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3227 12:20:56.183226 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3228 12:20:56.190123 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3229 12:20:56.190636
3230 12:20:56.190970
3231 12:20:56.191279 ==
3232 12:20:56.193451 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 12:20:56.196546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 12:20:56.196975 ==
3235 12:20:56.197310
3236 12:20:56.197617
3237 12:20:56.199900 TX Vref Scan disable
3238 12:20:56.200475 == TX Byte 0 ==
3239 12:20:56.206639 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3240 12:20:56.210432 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3241 12:20:56.210971 == TX Byte 1 ==
3242 12:20:56.216578 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 12:20:56.219852 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 12:20:56.220426 ==
3245 12:20:56.223298 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 12:20:56.226083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 12:20:56.226613 ==
3248 12:20:56.239033 TX Vref=22, minBit 9, minWin=24, winSum=411
3249 12:20:56.242677 TX Vref=24, minBit 8, minWin=25, winSum=417
3250 12:20:56.245831 TX Vref=26, minBit 9, minWin=24, winSum=421
3251 12:20:56.248885 TX Vref=28, minBit 9, minWin=25, winSum=423
3252 12:20:56.252333 TX Vref=30, minBit 8, minWin=26, winSum=429
3253 12:20:56.255418 TX Vref=32, minBit 9, minWin=25, winSum=426
3254 12:20:56.262980 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3255 12:20:56.263602
3256 12:20:56.265411 Final TX Range 1 Vref 30
3257 12:20:56.265863
3258 12:20:56.266197 ==
3259 12:20:56.269265 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 12:20:56.272331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 12:20:56.272759 ==
3262 12:20:56.273099
3263 12:20:56.273412
3264 12:20:56.275290 TX Vref Scan disable
3265 12:20:56.278756 == TX Byte 0 ==
3266 12:20:56.282353 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3267 12:20:56.286003 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3268 12:20:56.288579 == TX Byte 1 ==
3269 12:20:56.292197 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3270 12:20:56.295287 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3271 12:20:56.295711
3272 12:20:56.298705 [DATLAT]
3273 12:20:56.299123 Freq=1200, CH1 RK0
3274 12:20:56.299524
3275 12:20:56.301739 DATLAT Default: 0xd
3276 12:20:56.302217 0, 0xFFFF, sum = 0
3277 12:20:56.304981 1, 0xFFFF, sum = 0
3278 12:20:56.305413 2, 0xFFFF, sum = 0
3279 12:20:56.308331 3, 0xFFFF, sum = 0
3280 12:20:56.311377 4, 0xFFFF, sum = 0
3281 12:20:56.311808 5, 0xFFFF, sum = 0
3282 12:20:56.315038 6, 0xFFFF, sum = 0
3283 12:20:56.315464 7, 0xFFFF, sum = 0
3284 12:20:56.318300 8, 0xFFFF, sum = 0
3285 12:20:56.318724 9, 0xFFFF, sum = 0
3286 12:20:56.321349 10, 0xFFFF, sum = 0
3287 12:20:56.321780 11, 0xFFFF, sum = 0
3288 12:20:56.324604 12, 0x0, sum = 1
3289 12:20:56.325036 13, 0x0, sum = 2
3290 12:20:56.328287 14, 0x0, sum = 3
3291 12:20:56.328719 15, 0x0, sum = 4
3292 12:20:56.331374 best_step = 13
3293 12:20:56.331792
3294 12:20:56.332162 ==
3295 12:20:56.335125 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 12:20:56.338550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 12:20:56.339076 ==
3298 12:20:56.339417 RX Vref Scan: 1
3299 12:20:56.341319
3300 12:20:56.341736 Set Vref Range= 32 -> 127
3301 12:20:56.342074
3302 12:20:56.344543 RX Vref 32 -> 127, step: 1
3303 12:20:56.344968
3304 12:20:56.348192 RX Delay -13 -> 252, step: 4
3305 12:20:56.348615
3306 12:20:56.351279 Set Vref, RX VrefLevel [Byte0]: 32
3307 12:20:56.354398 [Byte1]: 32
3308 12:20:56.354821
3309 12:20:56.357905 Set Vref, RX VrefLevel [Byte0]: 33
3310 12:20:56.360920 [Byte1]: 33
3311 12:20:56.364873
3312 12:20:56.365278 Set Vref, RX VrefLevel [Byte0]: 34
3313 12:20:56.368455 [Byte1]: 34
3314 12:20:56.372659
3315 12:20:56.373080 Set Vref, RX VrefLevel [Byte0]: 35
3316 12:20:56.376152 [Byte1]: 35
3317 12:20:56.380404
3318 12:20:56.380690 Set Vref, RX VrefLevel [Byte0]: 36
3319 12:20:56.383946 [Byte1]: 36
3320 12:20:56.388315
3321 12:20:56.388703 Set Vref, RX VrefLevel [Byte0]: 37
3322 12:20:56.391560 [Byte1]: 37
3323 12:20:56.396628
3324 12:20:56.397018 Set Vref, RX VrefLevel [Byte0]: 38
3325 12:20:56.399523 [Byte1]: 38
3326 12:20:56.404329
3327 12:20:56.404629 Set Vref, RX VrefLevel [Byte0]: 39
3328 12:20:56.407767 [Byte1]: 39
3329 12:20:56.412183
3330 12:20:56.412587 Set Vref, RX VrefLevel [Byte0]: 40
3331 12:20:56.415485 [Byte1]: 40
3332 12:20:56.420307
3333 12:20:56.420813 Set Vref, RX VrefLevel [Byte0]: 41
3334 12:20:56.423310 [Byte1]: 41
3335 12:20:56.427573
3336 12:20:56.428052 Set Vref, RX VrefLevel [Byte0]: 42
3337 12:20:56.431289 [Byte1]: 42
3338 12:20:56.435708
3339 12:20:56.436191 Set Vref, RX VrefLevel [Byte0]: 43
3340 12:20:56.439077 [Byte1]: 43
3341 12:20:56.443419
3342 12:20:56.444006 Set Vref, RX VrefLevel [Byte0]: 44
3343 12:20:56.446846 [Byte1]: 44
3344 12:20:56.451655
3345 12:20:56.452200 Set Vref, RX VrefLevel [Byte0]: 45
3346 12:20:56.454837 [Byte1]: 45
3347 12:20:56.459567
3348 12:20:56.460020 Set Vref, RX VrefLevel [Byte0]: 46
3349 12:20:56.462736 [Byte1]: 46
3350 12:20:56.467086
3351 12:20:56.467499 Set Vref, RX VrefLevel [Byte0]: 47
3352 12:20:56.470482 [Byte1]: 47
3353 12:20:56.475282
3354 12:20:56.475690 Set Vref, RX VrefLevel [Byte0]: 48
3355 12:20:56.478406 [Byte1]: 48
3356 12:20:56.483534
3357 12:20:56.484086 Set Vref, RX VrefLevel [Byte0]: 49
3358 12:20:56.486643 [Byte1]: 49
3359 12:20:56.490815
3360 12:20:56.491325 Set Vref, RX VrefLevel [Byte0]: 50
3361 12:20:56.494449 [Byte1]: 50
3362 12:20:56.498887
3363 12:20:56.499295 Set Vref, RX VrefLevel [Byte0]: 51
3364 12:20:56.502336 [Byte1]: 51
3365 12:20:56.506615
3366 12:20:56.507025 Set Vref, RX VrefLevel [Byte0]: 52
3367 12:20:56.510550 [Byte1]: 52
3368 12:20:56.515198
3369 12:20:56.515722 Set Vref, RX VrefLevel [Byte0]: 53
3370 12:20:56.517733 [Byte1]: 53
3371 12:20:56.522545
3372 12:20:56.523057 Set Vref, RX VrefLevel [Byte0]: 54
3373 12:20:56.525648 [Byte1]: 54
3374 12:20:56.530875
3375 12:20:56.531390 Set Vref, RX VrefLevel [Byte0]: 55
3376 12:20:56.533988 [Byte1]: 55
3377 12:20:56.538391
3378 12:20:56.538908 Set Vref, RX VrefLevel [Byte0]: 56
3379 12:20:56.541352 [Byte1]: 56
3380 12:20:56.546467
3381 12:20:56.546986 Set Vref, RX VrefLevel [Byte0]: 57
3382 12:20:56.549592 [Byte1]: 57
3383 12:20:56.554085
3384 12:20:56.554501 Set Vref, RX VrefLevel [Byte0]: 58
3385 12:20:56.556968 [Byte1]: 58
3386 12:20:56.561819
3387 12:20:56.562239 Set Vref, RX VrefLevel [Byte0]: 59
3388 12:20:56.565549 [Byte1]: 59
3389 12:20:56.569712
3390 12:20:56.570130 Set Vref, RX VrefLevel [Byte0]: 60
3391 12:20:56.573354 [Byte1]: 60
3392 12:20:56.577813
3393 12:20:56.578240 Set Vref, RX VrefLevel [Byte0]: 61
3394 12:20:56.581014 [Byte1]: 61
3395 12:20:56.585940
3396 12:20:56.586360 Set Vref, RX VrefLevel [Byte0]: 62
3397 12:20:56.589188 [Byte1]: 62
3398 12:20:56.593505
3399 12:20:56.593924 Set Vref, RX VrefLevel [Byte0]: 63
3400 12:20:56.596596 [Byte1]: 63
3401 12:20:56.601355
3402 12:20:56.601769 Set Vref, RX VrefLevel [Byte0]: 64
3403 12:20:56.604385 [Byte1]: 64
3404 12:20:56.608979
3405 12:20:56.609396 Set Vref, RX VrefLevel [Byte0]: 65
3406 12:20:56.612313 [Byte1]: 65
3407 12:20:56.617156
3408 12:20:56.617568 Final RX Vref Byte 0 = 51 to rank0
3409 12:20:56.620271 Final RX Vref Byte 1 = 50 to rank0
3410 12:20:56.623842 Final RX Vref Byte 0 = 51 to rank1
3411 12:20:56.627389 Final RX Vref Byte 1 = 50 to rank1==
3412 12:20:56.630273 Dram Type= 6, Freq= 0, CH_1, rank 0
3413 12:20:56.636685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 12:20:56.637105 ==
3415 12:20:56.637435 DQS Delay:
3416 12:20:56.637744 DQS0 = 0, DQS1 = 0
3417 12:20:56.640439 DQM Delay:
3418 12:20:56.640855 DQM0 = 114, DQM1 = 112
3419 12:20:56.643718 DQ Delay:
3420 12:20:56.646914 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3421 12:20:56.650466 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3422 12:20:56.653447 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =106
3423 12:20:56.656871 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3424 12:20:56.657345
3425 12:20:56.657676
3426 12:20:56.666921 [DQSOSCAuto] RK0, (LSB)MR18= 0xf501, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3427 12:20:56.667347 CH1 RK0: MR19=304, MR18=F501
3428 12:20:56.673428 CH1_RK0: MR19=0x304, MR18=0xF501, DQSOSC=409, MR23=63, INC=39, DEC=26
3429 12:20:56.673851
3430 12:20:56.676718 ----->DramcWriteLeveling(PI) begin...
3431 12:20:56.677143 ==
3432 12:20:56.679734 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 12:20:56.686631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 12:20:56.687147 ==
3435 12:20:56.690118 Write leveling (Byte 0): 27 => 27
3436 12:20:56.690652 Write leveling (Byte 1): 28 => 28
3437 12:20:56.693980 DramcWriteLeveling(PI) end<-----
3438 12:20:56.694663
3439 12:20:56.696604 ==
3440 12:20:56.697021 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 12:20:56.703043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 12:20:56.703563 ==
3443 12:20:56.706370 [Gating] SW mode calibration
3444 12:20:56.713492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3445 12:20:56.716855 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3446 12:20:56.722853 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3447 12:20:56.726317 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 12:20:56.729316 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 12:20:56.736258 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 12:20:56.739466 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 12:20:56.742581 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
3452 12:20:56.749495 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
3453 12:20:56.752516 0 15 28 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
3454 12:20:56.755884 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 12:20:56.762531 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 12:20:56.766166 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 12:20:56.768905 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 12:20:56.775736 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 12:20:56.779543 1 0 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3460 12:20:56.782299 1 0 24 | B1->B0 | 2424 4141 | 0 1 | (0 0) (0 0)
3461 12:20:56.788818 1 0 28 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3462 12:20:56.792104 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 12:20:56.795685 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 12:20:56.802444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 12:20:56.805113 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 12:20:56.808866 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 12:20:56.814873 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 12:20:56.818558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3469 12:20:56.821986 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3470 12:20:56.828066 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3471 12:20:56.831420 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:20:56.834838 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:20:56.841301 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:20:56.844286 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:20:56.848168 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:20:56.854661 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:20:56.857415 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:20:56.860942 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:20:56.867631 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:20:56.870803 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:20:56.874288 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:20:56.880773 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:20:56.884050 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:20:56.887215 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3485 12:20:56.891052 Total UI for P1: 0, mck2ui 16
3486 12:20:56.893888 best dqsien dly found for B0: ( 1, 3, 22)
3487 12:20:56.900460 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3488 12:20:56.903775 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 12:20:56.907170 Total UI for P1: 0, mck2ui 16
3490 12:20:56.910276 best dqsien dly found for B1: ( 1, 3, 26)
3491 12:20:56.913364 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3492 12:20:56.916696 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3493 12:20:56.917111
3494 12:20:56.920076 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3495 12:20:56.927092 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3496 12:20:56.927638 [Gating] SW calibration Done
3497 12:20:56.928039 ==
3498 12:20:56.930015 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 12:20:56.936371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 12:20:56.936882 ==
3501 12:20:56.937248 RX Vref Scan: 0
3502 12:20:56.937562
3503 12:20:56.939853 RX Vref 0 -> 0, step: 1
3504 12:20:56.940320
3505 12:20:56.943054 RX Delay -40 -> 252, step: 8
3506 12:20:56.946688 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3507 12:20:56.950770 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3508 12:20:56.952921 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3509 12:20:56.959653 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3510 12:20:56.962906 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3511 12:20:56.965988 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3512 12:20:56.969524 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3513 12:20:56.976323 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3514 12:20:56.979563 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3515 12:20:56.982918 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3516 12:20:56.986680 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3517 12:20:56.989754 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3518 12:20:56.995672 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3519 12:20:56.999412 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3520 12:20:57.002697 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3521 12:20:57.005571 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3522 12:20:57.005999 ==
3523 12:20:57.008766 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 12:20:57.015306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 12:20:57.015729 ==
3526 12:20:57.016110 DQS Delay:
3527 12:20:57.018851 DQS0 = 0, DQS1 = 0
3528 12:20:57.019265 DQM Delay:
3529 12:20:57.019597 DQM0 = 115, DQM1 = 111
3530 12:20:57.022101 DQ Delay:
3531 12:20:57.025428 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3532 12:20:57.028432 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3533 12:20:57.032119 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3534 12:20:57.035049 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3535 12:20:57.035479
3536 12:20:57.035808
3537 12:20:57.036174 ==
3538 12:20:57.038158 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 12:20:57.045216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 12:20:57.045742 ==
3541 12:20:57.046074
3542 12:20:57.046380
3543 12:20:57.046670 TX Vref Scan disable
3544 12:20:57.048276 == TX Byte 0 ==
3545 12:20:57.051455 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3546 12:20:57.058578 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3547 12:20:57.059090 == TX Byte 1 ==
3548 12:20:57.061829 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3549 12:20:57.068305 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3550 12:20:57.068723 ==
3551 12:20:57.071090 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 12:20:57.074603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 12:20:57.075024 ==
3554 12:20:57.085706 TX Vref=22, minBit 3, minWin=25, winSum=420
3555 12:20:57.089807 TX Vref=24, minBit 9, minWin=25, winSum=424
3556 12:20:57.092594 TX Vref=26, minBit 1, minWin=26, winSum=428
3557 12:20:57.096280 TX Vref=28, minBit 1, minWin=26, winSum=431
3558 12:20:57.099396 TX Vref=30, minBit 8, minWin=25, winSum=430
3559 12:20:57.106011 TX Vref=32, minBit 1, minWin=26, winSum=429
3560 12:20:57.109269 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3561 12:20:57.109688
3562 12:20:57.112837 Final TX Range 1 Vref 28
3563 12:20:57.113354
3564 12:20:57.113681 ==
3565 12:20:57.115990 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 12:20:57.119256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 12:20:57.122492 ==
3568 12:20:57.123012
3569 12:20:57.123344
3570 12:20:57.123650 TX Vref Scan disable
3571 12:20:57.125981 == TX Byte 0 ==
3572 12:20:57.128574 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3573 12:20:57.135999 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3574 12:20:57.136548 == TX Byte 1 ==
3575 12:20:57.139337 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3576 12:20:57.145636 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3577 12:20:57.146168
3578 12:20:57.146500 [DATLAT]
3579 12:20:57.146808 Freq=1200, CH1 RK1
3580 12:20:57.147146
3581 12:20:57.148596 DATLAT Default: 0xd
3582 12:20:57.152211 0, 0xFFFF, sum = 0
3583 12:20:57.152636 1, 0xFFFF, sum = 0
3584 12:20:57.155062 2, 0xFFFF, sum = 0
3585 12:20:57.155483 3, 0xFFFF, sum = 0
3586 12:20:57.159227 4, 0xFFFF, sum = 0
3587 12:20:57.159762 5, 0xFFFF, sum = 0
3588 12:20:57.162301 6, 0xFFFF, sum = 0
3589 12:20:57.162723 7, 0xFFFF, sum = 0
3590 12:20:57.165194 8, 0xFFFF, sum = 0
3591 12:20:57.165645 9, 0xFFFF, sum = 0
3592 12:20:57.168084 10, 0xFFFF, sum = 0
3593 12:20:57.168508 11, 0xFFFF, sum = 0
3594 12:20:57.171392 12, 0x0, sum = 1
3595 12:20:57.171811 13, 0x0, sum = 2
3596 12:20:57.174946 14, 0x0, sum = 3
3597 12:20:57.175366 15, 0x0, sum = 4
3598 12:20:57.178673 best_step = 13
3599 12:20:57.179090
3600 12:20:57.179417 ==
3601 12:20:57.181260 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 12:20:57.184906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 12:20:57.185327 ==
3604 12:20:57.187986 RX Vref Scan: 0
3605 12:20:57.188496
3606 12:20:57.188833 RX Vref 0 -> 0, step: 1
3607 12:20:57.189143
3608 12:20:57.191679 RX Delay -13 -> 252, step: 4
3609 12:20:57.197805 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3610 12:20:57.201206 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3611 12:20:57.204670 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3612 12:20:57.207885 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3613 12:20:57.211010 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3614 12:20:57.217512 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3615 12:20:57.221530 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3616 12:20:57.224450 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3617 12:20:57.227463 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3618 12:20:57.230937 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3619 12:20:57.237095 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3620 12:20:57.240790 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3621 12:20:57.244473 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3622 12:20:57.247244 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3623 12:20:57.253892 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3624 12:20:57.257226 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3625 12:20:57.257808 ==
3626 12:20:57.260386 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 12:20:57.263535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 12:20:57.264002 ==
3629 12:20:57.267053 DQS Delay:
3630 12:20:57.267481 DQS0 = 0, DQS1 = 0
3631 12:20:57.267815 DQM Delay:
3632 12:20:57.269978 DQM0 = 115, DQM1 = 112
3633 12:20:57.270392 DQ Delay:
3634 12:20:57.273851 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3635 12:20:57.276569 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =112
3636 12:20:57.283277 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3637 12:20:57.286271 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3638 12:20:57.286497
3639 12:20:57.286673
3640 12:20:57.292878 [DQSOSCAuto] RK1, (LSB)MR18= 0xf407, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
3641 12:20:57.296122 CH1 RK1: MR19=304, MR18=F407
3642 12:20:57.302948 CH1_RK1: MR19=0x304, MR18=0xF407, DQSOSC=407, MR23=63, INC=39, DEC=26
3643 12:20:57.306122 [RxdqsGatingPostProcess] freq 1200
3644 12:20:57.312905 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3645 12:20:57.313020 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 12:20:57.316267 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 12:20:57.319509 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 12:20:57.322791 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 12:20:57.325935 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 12:20:57.329561 best DQS1 dly(2T, 0.5T) = (0, 11)
3651 12:20:57.332520 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 12:20:57.335724 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3653 12:20:57.339257 Pre-setting of DQS Precalculation
3654 12:20:57.346237 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3655 12:20:57.352684 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3656 12:20:57.358648 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3657 12:20:57.358773
3658 12:20:57.358863
3659 12:20:57.362125 [Calibration Summary] 2400 Mbps
3660 12:20:57.362238 CH 0, Rank 0
3661 12:20:57.365314 SW Impedance : PASS
3662 12:20:57.368680 DUTY Scan : NO K
3663 12:20:57.368794 ZQ Calibration : PASS
3664 12:20:57.372031 Jitter Meter : NO K
3665 12:20:57.375081 CBT Training : PASS
3666 12:20:57.375195 Write leveling : PASS
3667 12:20:57.378982 RX DQS gating : PASS
3668 12:20:57.381806 RX DQ/DQS(RDDQC) : PASS
3669 12:20:57.381920 TX DQ/DQS : PASS
3670 12:20:57.384973 RX DATLAT : PASS
3671 12:20:57.388569 RX DQ/DQS(Engine): PASS
3672 12:20:57.388683 TX OE : NO K
3673 12:20:57.392046 All Pass.
3674 12:20:57.392159
3675 12:20:57.392248 CH 0, Rank 1
3676 12:20:57.395560 SW Impedance : PASS
3677 12:20:57.395701 DUTY Scan : NO K
3678 12:20:57.398797 ZQ Calibration : PASS
3679 12:20:57.401804 Jitter Meter : NO K
3680 12:20:57.402220 CBT Training : PASS
3681 12:20:57.405112 Write leveling : PASS
3682 12:20:57.408846 RX DQS gating : PASS
3683 12:20:57.409265 RX DQ/DQS(RDDQC) : PASS
3684 12:20:57.412042 TX DQ/DQS : PASS
3685 12:20:57.412464 RX DATLAT : PASS
3686 12:20:57.415454 RX DQ/DQS(Engine): PASS
3687 12:20:57.418569 TX OE : NO K
3688 12:20:57.418992 All Pass.
3689 12:20:57.419322
3690 12:20:57.419630 CH 1, Rank 0
3691 12:20:57.422532 SW Impedance : PASS
3692 12:20:57.424786 DUTY Scan : NO K
3693 12:20:57.425083 ZQ Calibration : PASS
3694 12:20:57.429132 Jitter Meter : NO K
3695 12:20:57.431864 CBT Training : PASS
3696 12:20:57.432115 Write leveling : PASS
3697 12:20:57.435132 RX DQS gating : PASS
3698 12:20:57.438025 RX DQ/DQS(RDDQC) : PASS
3699 12:20:57.438203 TX DQ/DQS : PASS
3700 12:20:57.441224 RX DATLAT : PASS
3701 12:20:57.444609 RX DQ/DQS(Engine): PASS
3702 12:20:57.444737 TX OE : NO K
3703 12:20:57.448159 All Pass.
3704 12:20:57.448285
3705 12:20:57.448373 CH 1, Rank 1
3706 12:20:57.451197 SW Impedance : PASS
3707 12:20:57.451310 DUTY Scan : NO K
3708 12:20:57.454271 ZQ Calibration : PASS
3709 12:20:57.457927 Jitter Meter : NO K
3710 12:20:57.458040 CBT Training : PASS
3711 12:20:57.461384 Write leveling : PASS
3712 12:20:57.464625 RX DQS gating : PASS
3713 12:20:57.465079 RX DQ/DQS(RDDQC) : PASS
3714 12:20:57.467929 TX DQ/DQS : PASS
3715 12:20:57.471533 RX DATLAT : PASS
3716 12:20:57.472112 RX DQ/DQS(Engine): PASS
3717 12:20:57.474633 TX OE : NO K
3718 12:20:57.475049 All Pass.
3719 12:20:57.475376
3720 12:20:57.477883 DramC Write-DBI off
3721 12:20:57.481186 PER_BANK_REFRESH: Hybrid Mode
3722 12:20:57.481601 TX_TRACKING: ON
3723 12:20:57.491671 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3724 12:20:57.494637 [FAST_K] Save calibration result to emmc
3725 12:20:57.497639 dramc_set_vcore_voltage set vcore to 650000
3726 12:20:57.500941 Read voltage for 600, 5
3727 12:20:57.501355 Vio18 = 0
3728 12:20:57.501681 Vcore = 650000
3729 12:20:57.504133 Vdram = 0
3730 12:20:57.504545 Vddq = 0
3731 12:20:57.504892 Vmddr = 0
3732 12:20:57.510776 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3733 12:20:57.513791 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3734 12:20:57.517761 MEM_TYPE=3, freq_sel=19
3735 12:20:57.520703 sv_algorithm_assistance_LP4_1600
3736 12:20:57.523952 ============ PULL DRAM RESETB DOWN ============
3737 12:20:57.530201 ========== PULL DRAM RESETB DOWN end =========
3738 12:20:57.534210 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3739 12:20:57.537139 ===================================
3740 12:20:57.540356 LPDDR4 DRAM CONFIGURATION
3741 12:20:57.544004 ===================================
3742 12:20:57.544425 EX_ROW_EN[0] = 0x0
3743 12:20:57.547012 EX_ROW_EN[1] = 0x0
3744 12:20:57.547530 LP4Y_EN = 0x0
3745 12:20:57.550471 WORK_FSP = 0x0
3746 12:20:57.551021 WL = 0x2
3747 12:20:57.553356 RL = 0x2
3748 12:20:57.553771 BL = 0x2
3749 12:20:57.556595 RPST = 0x0
3750 12:20:57.559721 RD_PRE = 0x0
3751 12:20:57.560184 WR_PRE = 0x1
3752 12:20:57.563011 WR_PST = 0x0
3753 12:20:57.563425 DBI_WR = 0x0
3754 12:20:57.566689 DBI_RD = 0x0
3755 12:20:57.567290 OTF = 0x1
3756 12:20:57.569876 ===================================
3757 12:20:57.572824 ===================================
3758 12:20:57.576351 ANA top config
3759 12:20:57.579601 ===================================
3760 12:20:57.580159 DLL_ASYNC_EN = 0
3761 12:20:57.582725 ALL_SLAVE_EN = 1
3762 12:20:57.585919 NEW_RANK_MODE = 1
3763 12:20:57.589519 DLL_IDLE_MODE = 1
3764 12:20:57.590028 LP45_APHY_COMB_EN = 1
3765 12:20:57.592959 TX_ODT_DIS = 1
3766 12:20:57.596706 NEW_8X_MODE = 1
3767 12:20:57.599522 ===================================
3768 12:20:57.602891 ===================================
3769 12:20:57.606362 data_rate = 1200
3770 12:20:57.609054 CKR = 1
3771 12:20:57.612367 DQ_P2S_RATIO = 8
3772 12:20:57.616062 ===================================
3773 12:20:57.616678 CA_P2S_RATIO = 8
3774 12:20:57.619012 DQ_CA_OPEN = 0
3775 12:20:57.622064 DQ_SEMI_OPEN = 0
3776 12:20:57.625667 CA_SEMI_OPEN = 0
3777 12:20:57.628873 CA_FULL_RATE = 0
3778 12:20:57.631876 DQ_CKDIV4_EN = 1
3779 12:20:57.632362 CA_CKDIV4_EN = 1
3780 12:20:57.635481 CA_PREDIV_EN = 0
3781 12:20:57.638984 PH8_DLY = 0
3782 12:20:57.641893 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3783 12:20:57.645091 DQ_AAMCK_DIV = 4
3784 12:20:57.649268 CA_AAMCK_DIV = 4
3785 12:20:57.652319 CA_ADMCK_DIV = 4
3786 12:20:57.652738 DQ_TRACK_CA_EN = 0
3787 12:20:57.655237 CA_PICK = 600
3788 12:20:57.658784 CA_MCKIO = 600
3789 12:20:57.661997 MCKIO_SEMI = 0
3790 12:20:57.665170 PLL_FREQ = 2288
3791 12:20:57.668336 DQ_UI_PI_RATIO = 32
3792 12:20:57.671859 CA_UI_PI_RATIO = 0
3793 12:20:57.675209 ===================================
3794 12:20:57.678673 ===================================
3795 12:20:57.679091 memory_type:LPDDR4
3796 12:20:57.681661 GP_NUM : 10
3797 12:20:57.685292 SRAM_EN : 1
3798 12:20:57.685708 MD32_EN : 0
3799 12:20:57.688344 ===================================
3800 12:20:57.691774 [ANA_INIT] >>>>>>>>>>>>>>
3801 12:20:57.695021 <<<<<< [CONFIGURE PHASE]: ANA_TX
3802 12:20:57.698247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3803 12:20:57.702098 ===================================
3804 12:20:57.704702 data_rate = 1200,PCW = 0X5800
3805 12:20:57.707989 ===================================
3806 12:20:57.711456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3807 12:20:57.715050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 12:20:57.721154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 12:20:57.724741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3810 12:20:57.727784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3811 12:20:57.731102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3812 12:20:57.734647 [ANA_INIT] flow start
3813 12:20:57.737376 [ANA_INIT] PLL >>>>>>>>
3814 12:20:57.737925 [ANA_INIT] PLL <<<<<<<<
3815 12:20:57.740846 [ANA_INIT] MIDPI >>>>>>>>
3816 12:20:57.744331 [ANA_INIT] MIDPI <<<<<<<<
3817 12:20:57.747700 [ANA_INIT] DLL >>>>>>>>
3818 12:20:57.748186 [ANA_INIT] flow end
3819 12:20:57.750620 ============ LP4 DIFF to SE enter ============
3820 12:20:57.757275 ============ LP4 DIFF to SE exit ============
3821 12:20:57.757712 [ANA_INIT] <<<<<<<<<<<<<
3822 12:20:57.761093 [Flow] Enable top DCM control >>>>>
3823 12:20:57.764061 [Flow] Enable top DCM control <<<<<
3824 12:20:57.767361 Enable DLL master slave shuffle
3825 12:20:57.773862 ==============================================================
3826 12:20:57.774426 Gating Mode config
3827 12:20:57.780735 ==============================================================
3828 12:20:57.784162 Config description:
3829 12:20:57.793671 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3830 12:20:57.800447 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3831 12:20:57.803738 SELPH_MODE 0: By rank 1: By Phase
3832 12:20:57.810421 ==============================================================
3833 12:20:57.813890 GAT_TRACK_EN = 1
3834 12:20:57.816826 RX_GATING_MODE = 2
3835 12:20:57.820164 RX_GATING_TRACK_MODE = 2
3836 12:20:57.820832 SELPH_MODE = 1
3837 12:20:57.823393 PICG_EARLY_EN = 1
3838 12:20:57.826829 VALID_LAT_VALUE = 1
3839 12:20:57.833668 ==============================================================
3840 12:20:57.836895 Enter into Gating configuration >>>>
3841 12:20:57.839868 Exit from Gating configuration <<<<
3842 12:20:57.843618 Enter into DVFS_PRE_config >>>>>
3843 12:20:57.853154 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3844 12:20:57.856427 Exit from DVFS_PRE_config <<<<<
3845 12:20:57.859707 Enter into PICG configuration >>>>
3846 12:20:57.863311 Exit from PICG configuration <<<<
3847 12:20:57.866439 [RX_INPUT] configuration >>>>>
3848 12:20:57.869544 [RX_INPUT] configuration <<<<<
3849 12:20:57.873041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3850 12:20:57.879450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3851 12:20:57.885648 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 12:20:57.892807 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 12:20:57.899430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3854 12:20:57.905834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3855 12:20:57.909075 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3856 12:20:57.912329 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3857 12:20:57.916133 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3858 12:20:57.922608 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3859 12:20:57.925465 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3860 12:20:57.929348 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3861 12:20:57.932267 ===================================
3862 12:20:57.935735 LPDDR4 DRAM CONFIGURATION
3863 12:20:57.939055 ===================================
3864 12:20:57.939571 EX_ROW_EN[0] = 0x0
3865 12:20:57.942546 EX_ROW_EN[1] = 0x0
3866 12:20:57.945845 LP4Y_EN = 0x0
3867 12:20:57.946358 WORK_FSP = 0x0
3868 12:20:57.948969 WL = 0x2
3869 12:20:57.949482 RL = 0x2
3870 12:20:57.951849 BL = 0x2
3871 12:20:57.952401 RPST = 0x0
3872 12:20:57.955733 RD_PRE = 0x0
3873 12:20:57.956296 WR_PRE = 0x1
3874 12:20:57.958639 WR_PST = 0x0
3875 12:20:57.959052 DBI_WR = 0x0
3876 12:20:57.962172 DBI_RD = 0x0
3877 12:20:57.962688 OTF = 0x1
3878 12:20:57.965303 ===================================
3879 12:20:57.968524 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3880 12:20:57.975093 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3881 12:20:57.978359 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 12:20:57.981479 ===================================
3883 12:20:57.985025 LPDDR4 DRAM CONFIGURATION
3884 12:20:57.988258 ===================================
3885 12:20:57.988709 EX_ROW_EN[0] = 0x10
3886 12:20:57.991710 EX_ROW_EN[1] = 0x0
3887 12:20:57.994826 LP4Y_EN = 0x0
3888 12:20:57.995240 WORK_FSP = 0x0
3889 12:20:57.998265 WL = 0x2
3890 12:20:57.998812 RL = 0x2
3891 12:20:58.002576 BL = 0x2
3892 12:20:58.003229 RPST = 0x0
3893 12:20:58.004768 RD_PRE = 0x0
3894 12:20:58.005178 WR_PRE = 0x1
3895 12:20:58.008248 WR_PST = 0x0
3896 12:20:58.008687 DBI_WR = 0x0
3897 12:20:58.011345 DBI_RD = 0x0
3898 12:20:58.011797 OTF = 0x1
3899 12:20:58.014555 ===================================
3900 12:20:58.021055 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3901 12:20:58.025440 nWR fixed to 30
3902 12:20:58.028715 [ModeRegInit_LP4] CH0 RK0
3903 12:20:58.029154 [ModeRegInit_LP4] CH0 RK1
3904 12:20:58.032010 [ModeRegInit_LP4] CH1 RK0
3905 12:20:58.035451 [ModeRegInit_LP4] CH1 RK1
3906 12:20:58.035868 match AC timing 17
3907 12:20:58.041831 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3908 12:20:58.045179 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3909 12:20:58.048881 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3910 12:20:58.054957 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3911 12:20:58.058305 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3912 12:20:58.058896 ==
3913 12:20:58.061749 Dram Type= 6, Freq= 0, CH_0, rank 0
3914 12:20:58.065293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3915 12:20:58.068096 ==
3916 12:20:58.072296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3917 12:20:58.078214 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3918 12:20:58.081349 [CA 0] Center 36 (6~67) winsize 62
3919 12:20:58.084865 [CA 1] Center 36 (6~66) winsize 61
3920 12:20:58.088451 [CA 2] Center 34 (4~65) winsize 62
3921 12:20:58.091395 [CA 3] Center 34 (4~65) winsize 62
3922 12:20:58.094661 [CA 4] Center 33 (3~64) winsize 62
3923 12:20:58.098320 [CA 5] Center 33 (3~64) winsize 62
3924 12:20:58.098838
3925 12:20:58.101519 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3926 12:20:58.102040
3927 12:20:58.104576 [CATrainingPosCal] consider 1 rank data
3928 12:20:58.107782 u2DelayCellTimex100 = 270/100 ps
3929 12:20:58.111282 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3930 12:20:58.114412 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3931 12:20:58.121442 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3932 12:20:58.124092 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3933 12:20:58.127533 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3934 12:20:58.130730 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3935 12:20:58.131146
3936 12:20:58.134092 CA PerBit enable=1, Macro0, CA PI delay=33
3937 12:20:58.134523
3938 12:20:58.137660 [CBTSetCACLKResult] CA Dly = 33
3939 12:20:58.138182 CS Dly: 4 (0~35)
3940 12:20:58.141233 ==
3941 12:20:58.141753 Dram Type= 6, Freq= 0, CH_0, rank 1
3942 12:20:58.146980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 12:20:58.147402 ==
3944 12:20:58.150354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 12:20:58.157046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3946 12:20:58.160686 [CA 0] Center 36 (6~67) winsize 62
3947 12:20:58.163989 [CA 1] Center 36 (6~67) winsize 62
3948 12:20:58.167774 [CA 2] Center 34 (4~65) winsize 62
3949 12:20:58.170960 [CA 3] Center 34 (4~65) winsize 62
3950 12:20:58.174180 [CA 4] Center 34 (3~65) winsize 63
3951 12:20:58.177767 [CA 5] Center 33 (3~64) winsize 62
3952 12:20:58.178278
3953 12:20:58.180658 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3954 12:20:58.181173
3955 12:20:58.183695 [CATrainingPosCal] consider 2 rank data
3956 12:20:58.186860 u2DelayCellTimex100 = 270/100 ps
3957 12:20:58.190453 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3958 12:20:58.196853 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3959 12:20:58.200764 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 12:20:58.203942 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 12:20:58.207161 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 12:20:58.210289 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 12:20:58.210797
3964 12:20:58.213397 CA PerBit enable=1, Macro0, CA PI delay=33
3965 12:20:58.213812
3966 12:20:58.216847 [CBTSetCACLKResult] CA Dly = 33
3967 12:20:58.220427 CS Dly: 5 (0~37)
3968 12:20:58.220941
3969 12:20:58.223417 ----->DramcWriteLeveling(PI) begin...
3970 12:20:58.223968 ==
3971 12:20:58.226652 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 12:20:58.230187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 12:20:58.230610 ==
3974 12:20:58.233560 Write leveling (Byte 0): 35 => 35
3975 12:20:58.236970 Write leveling (Byte 1): 30 => 30
3976 12:20:58.240641 DramcWriteLeveling(PI) end<-----
3977 12:20:58.241160
3978 12:20:58.241493 ==
3979 12:20:58.243073 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 12:20:58.246157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 12:20:58.246581 ==
3982 12:20:58.249591 [Gating] SW mode calibration
3983 12:20:58.256151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3984 12:20:58.263044 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3985 12:20:58.266549 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 12:20:58.272440 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 12:20:58.275755 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 12:20:58.279310 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3989 12:20:58.286082 0 9 16 | B1->B0 | 2e2e 2525 | 1 0 | (1 1) (0 0)
3990 12:20:58.288951 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 12:20:58.292291 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 12:20:58.298989 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 12:20:58.302145 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 12:20:58.305833 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 12:20:58.311785 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 12:20:58.315497 0 10 12 | B1->B0 | 2626 3131 | 0 0 | (0 0) (1 1)
3997 12:20:58.318912 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3998 12:20:58.325586 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 12:20:58.328915 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 12:20:58.332048 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 12:20:58.338728 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 12:20:58.342161 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 12:20:58.344890 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 12:20:58.351771 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 12:20:58.355047 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:20:58.358568 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:20:58.364499 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:20:58.368052 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:20:58.370901 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:20:58.377401 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:20:58.380991 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:20:58.384159 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:20:58.390788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:20:58.394304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:20:58.397240 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:20:58.403858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:20:58.406962 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:20:58.410929 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:20:58.417274 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:20:58.420638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4021 12:20:58.423758 Total UI for P1: 0, mck2ui 16
4022 12:20:58.427133 best dqsien dly found for B0: ( 0, 13, 10)
4023 12:20:58.430441 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4024 12:20:58.437071 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 12:20:58.437495 Total UI for P1: 0, mck2ui 16
4026 12:20:58.444017 best dqsien dly found for B1: ( 0, 13, 18)
4027 12:20:58.446646 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4028 12:20:58.450111 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4029 12:20:58.450534
4030 12:20:58.453225 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4031 12:20:58.457012 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4032 12:20:58.459723 [Gating] SW calibration Done
4033 12:20:58.460297 ==
4034 12:20:58.463164 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 12:20:58.466330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 12:20:58.466747 ==
4037 12:20:58.469784 RX Vref Scan: 0
4038 12:20:58.470203
4039 12:20:58.472813 RX Vref 0 -> 0, step: 1
4040 12:20:58.473233
4041 12:20:58.473564 RX Delay -230 -> 252, step: 16
4042 12:20:58.480369 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4043 12:20:58.483008 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4044 12:20:58.486268 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4045 12:20:58.489903 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4046 12:20:58.496493 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4047 12:20:58.499549 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4048 12:20:58.502915 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4049 12:20:58.505917 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4050 12:20:58.512683 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4051 12:20:58.515890 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4052 12:20:58.519070 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4053 12:20:58.522667 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4054 12:20:58.529165 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4055 12:20:58.532047 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4056 12:20:58.535406 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4057 12:20:58.539089 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4058 12:20:58.539503 ==
4059 12:20:58.541909 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 12:20:58.548826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 12:20:58.549240 ==
4062 12:20:58.549565 DQS Delay:
4063 12:20:58.551680 DQS0 = 0, DQS1 = 0
4064 12:20:58.552122 DQM Delay:
4065 12:20:58.554885 DQM0 = 40, DQM1 = 32
4066 12:20:58.555296 DQ Delay:
4067 12:20:58.558768 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4068 12:20:58.562107 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4069 12:20:58.564782 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4070 12:20:58.568266 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4071 12:20:58.568785
4072 12:20:58.569113
4073 12:20:58.569413 ==
4074 12:20:58.571430 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 12:20:58.574755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 12:20:58.575174 ==
4077 12:20:58.575600
4078 12:20:58.576046
4079 12:20:58.578390 TX Vref Scan disable
4080 12:20:58.581887 == TX Byte 0 ==
4081 12:20:58.584826 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4082 12:20:58.588274 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4083 12:20:58.591317 == TX Byte 1 ==
4084 12:20:58.594739 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4085 12:20:58.598025 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4086 12:20:58.598444 ==
4087 12:20:58.601576 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 12:20:58.608670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 12:20:58.609313 ==
4090 12:20:58.609654
4091 12:20:58.609990
4092 12:20:58.610288 TX Vref Scan disable
4093 12:20:58.612420 == TX Byte 0 ==
4094 12:20:58.616893 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4095 12:20:58.622527 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4096 12:20:58.623044 == TX Byte 1 ==
4097 12:20:58.625948 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4098 12:20:58.632296 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4099 12:20:58.632829
4100 12:20:58.633166 [DATLAT]
4101 12:20:58.633476 Freq=600, CH0 RK0
4102 12:20:58.633891
4103 12:20:58.635474 DATLAT Default: 0x9
4104 12:20:58.638729 0, 0xFFFF, sum = 0
4105 12:20:58.639147 1, 0xFFFF, sum = 0
4106 12:20:58.641823 2, 0xFFFF, sum = 0
4107 12:20:58.642241 3, 0xFFFF, sum = 0
4108 12:20:58.645261 4, 0xFFFF, sum = 0
4109 12:20:58.645677 5, 0xFFFF, sum = 0
4110 12:20:58.648405 6, 0xFFFF, sum = 0
4111 12:20:58.648822 7, 0xFFFF, sum = 0
4112 12:20:58.652232 8, 0x0, sum = 1
4113 12:20:58.652648 9, 0x0, sum = 2
4114 12:20:58.655576 10, 0x0, sum = 3
4115 12:20:58.656136 11, 0x0, sum = 4
4116 12:20:58.656478 best_step = 9
4117 12:20:58.656782
4118 12:20:58.658720 ==
4119 12:20:58.661744 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 12:20:58.665462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 12:20:58.665880 ==
4122 12:20:58.666209 RX Vref Scan: 1
4123 12:20:58.666517
4124 12:20:58.668467 RX Vref 0 -> 0, step: 1
4125 12:20:58.668882
4126 12:20:58.672032 RX Delay -195 -> 252, step: 8
4127 12:20:58.672450
4128 12:20:58.675236 Set Vref, RX VrefLevel [Byte0]: 51
4129 12:20:58.678795 [Byte1]: 49
4130 12:20:58.679315
4131 12:20:58.681995 Final RX Vref Byte 0 = 51 to rank0
4132 12:20:58.685110 Final RX Vref Byte 1 = 49 to rank0
4133 12:20:58.688395 Final RX Vref Byte 0 = 51 to rank1
4134 12:20:58.691975 Final RX Vref Byte 1 = 49 to rank1==
4135 12:20:58.695277 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 12:20:58.698634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 12:20:58.701623 ==
4138 12:20:58.702144 DQS Delay:
4139 12:20:58.702479 DQS0 = 0, DQS1 = 0
4140 12:20:58.704665 DQM Delay:
4141 12:20:58.705076 DQM0 = 42, DQM1 = 34
4142 12:20:58.708104 DQ Delay:
4143 12:20:58.712455 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4144 12:20:58.712899 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4145 12:20:58.714855 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4146 12:20:58.721472 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4147 12:20:58.722019
4148 12:20:58.722390
4149 12:20:58.728062 [DQSOSCAuto] RK0, (LSB)MR18= 0x453d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4150 12:20:58.731265 CH0 RK0: MR19=808, MR18=453D
4151 12:20:58.737916 CH0_RK0: MR19=0x808, MR18=0x453D, DQSOSC=396, MR23=63, INC=167, DEC=111
4152 12:20:58.738329
4153 12:20:58.741030 ----->DramcWriteLeveling(PI) begin...
4154 12:20:58.741451 ==
4155 12:20:58.744355 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 12:20:58.747349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 12:20:58.747766 ==
4158 12:20:58.752616 Write leveling (Byte 0): 35 => 35
4159 12:20:58.753813 Write leveling (Byte 1): 29 => 29
4160 12:20:58.757400 DramcWriteLeveling(PI) end<-----
4161 12:20:58.757488
4162 12:20:58.757551 ==
4163 12:20:58.760484 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 12:20:58.763518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 12:20:58.763599 ==
4166 12:20:58.767318 [Gating] SW mode calibration
4167 12:20:58.773650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4168 12:20:58.779800 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4169 12:20:58.783209 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 12:20:58.790126 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 12:20:58.793177 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 12:20:58.796887 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4173 12:20:58.803022 0 9 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (1 0)
4174 12:20:58.806258 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 12:20:58.810038 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 12:20:58.816241 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 12:20:58.819837 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 12:20:58.822969 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 12:20:58.829737 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4180 12:20:58.832665 0 10 12 | B1->B0 | 2424 3232 | 1 0 | (0 0) (0 0)
4181 12:20:58.836282 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4182 12:20:58.843247 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 12:20:58.846612 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 12:20:58.849495 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 12:20:58.856314 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 12:20:58.859302 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 12:20:58.862674 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 12:20:58.869404 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 12:20:58.872299 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4190 12:20:58.875645 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:20:58.882346 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:20:58.885458 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:20:58.889112 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:20:58.895675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:20:58.899027 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:20:58.902786 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:20:58.908797 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:20:58.912017 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:20:58.915324 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:20:58.921942 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:20:58.925111 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:20:58.928384 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:20:58.935368 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4204 12:20:58.938450 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4205 12:20:58.941912 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4206 12:20:58.944639 Total UI for P1: 0, mck2ui 16
4207 12:20:58.948604 best dqsien dly found for B0: ( 0, 13, 10)
4208 12:20:58.954987 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 12:20:58.958472 Total UI for P1: 0, mck2ui 16
4210 12:20:58.961590 best dqsien dly found for B1: ( 0, 13, 16)
4211 12:20:58.964528 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4212 12:20:58.968482 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4213 12:20:58.969000
4214 12:20:58.971235 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4215 12:20:58.974123 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4216 12:20:58.977613 [Gating] SW calibration Done
4217 12:20:58.978025 ==
4218 12:20:58.980887 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 12:20:58.984407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 12:20:58.984944 ==
4221 12:20:58.987559 RX Vref Scan: 0
4222 12:20:58.987999
4223 12:20:58.991082 RX Vref 0 -> 0, step: 1
4224 12:20:58.991592
4225 12:20:58.994472 RX Delay -230 -> 252, step: 16
4226 12:20:58.997769 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4227 12:20:59.000448 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4228 12:20:59.004081 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4229 12:20:59.007480 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4230 12:20:59.014292 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4231 12:20:59.017222 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4232 12:20:59.021177 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4233 12:20:59.024317 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4234 12:20:59.030621 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4235 12:20:59.034176 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4236 12:20:59.036914 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4237 12:20:59.040703 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4238 12:20:59.046884 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4239 12:20:59.050141 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4240 12:20:59.054209 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4241 12:20:59.057233 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4242 12:20:59.057788 ==
4243 12:20:59.060458 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 12:20:59.066608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 12:20:59.067072 ==
4246 12:20:59.067439 DQS Delay:
4247 12:20:59.070130 DQS0 = 0, DQS1 = 0
4248 12:20:59.070658 DQM Delay:
4249 12:20:59.073052 DQM0 = 43, DQM1 = 33
4250 12:20:59.073492 DQ Delay:
4251 12:20:59.076157 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4252 12:20:59.079687 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4253 12:20:59.083099 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4254 12:20:59.086361 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4255 12:20:59.086780
4256 12:20:59.087253
4257 12:20:59.087702 ==
4258 12:20:59.089532 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 12:20:59.093083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 12:20:59.093502 ==
4261 12:20:59.093832
4262 12:20:59.094137
4263 12:20:59.095872 TX Vref Scan disable
4264 12:20:59.099802 == TX Byte 0 ==
4265 12:20:59.102514 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4266 12:20:59.105951 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4267 12:20:59.109488 == TX Byte 1 ==
4268 12:20:59.112575 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4269 12:20:59.115693 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4270 12:20:59.116143 ==
4271 12:20:59.119089 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 12:20:59.125578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 12:20:59.125997 ==
4274 12:20:59.126325
4275 12:20:59.126628
4276 12:20:59.129204 TX Vref Scan disable
4277 12:20:59.129623 == TX Byte 0 ==
4278 12:20:59.135516 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4279 12:20:59.139196 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4280 12:20:59.139611 == TX Byte 1 ==
4281 12:20:59.145188 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4282 12:20:59.149116 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4283 12:20:59.149641
4284 12:20:59.149974 [DATLAT]
4285 12:20:59.152229 Freq=600, CH0 RK1
4286 12:20:59.152648
4287 12:20:59.152974 DATLAT Default: 0x9
4288 12:20:59.155485 0, 0xFFFF, sum = 0
4289 12:20:59.158575 1, 0xFFFF, sum = 0
4290 12:20:59.159095 2, 0xFFFF, sum = 0
4291 12:20:59.161647 3, 0xFFFF, sum = 0
4292 12:20:59.162075 4, 0xFFFF, sum = 0
4293 12:20:59.165125 5, 0xFFFF, sum = 0
4294 12:20:59.165547 6, 0xFFFF, sum = 0
4295 12:20:59.168345 7, 0xFFFF, sum = 0
4296 12:20:59.168826 8, 0x0, sum = 1
4297 12:20:59.171522 9, 0x0, sum = 2
4298 12:20:59.171994 10, 0x0, sum = 3
4299 12:20:59.172343 11, 0x0, sum = 4
4300 12:20:59.175231 best_step = 9
4301 12:20:59.175681
4302 12:20:59.176066 ==
4303 12:20:59.178265 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 12:20:59.181767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 12:20:59.182184 ==
4306 12:20:59.185109 RX Vref Scan: 0
4307 12:20:59.185523
4308 12:20:59.188058 RX Vref 0 -> 0, step: 1
4309 12:20:59.188469
4310 12:20:59.188798 RX Delay -195 -> 252, step: 8
4311 12:20:59.196077 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4312 12:20:59.199382 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4313 12:20:59.202398 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4314 12:20:59.205682 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4315 12:20:59.212428 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4316 12:20:59.215280 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4317 12:20:59.218647 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4318 12:20:59.222136 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4319 12:20:59.228737 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4320 12:20:59.232157 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4321 12:20:59.235539 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4322 12:20:59.239091 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4323 12:20:59.245419 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4324 12:20:59.248571 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4325 12:20:59.251886 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4326 12:20:59.255246 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4327 12:20:59.255664 ==
4328 12:20:59.258369 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 12:20:59.265085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 12:20:59.265504 ==
4331 12:20:59.265833 DQS Delay:
4332 12:20:59.268282 DQS0 = 0, DQS1 = 0
4333 12:20:59.268693 DQM Delay:
4334 12:20:59.269016 DQM0 = 40, DQM1 = 34
4335 12:20:59.272136 DQ Delay:
4336 12:20:59.274818 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4337 12:20:59.278294 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4338 12:20:59.281893 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4339 12:20:59.284735 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4340 12:20:59.285165
4341 12:20:59.285495
4342 12:20:59.291604 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4343 12:20:59.294295 CH0 RK1: MR19=808, MR18=3B37
4344 12:20:59.301153 CH0_RK1: MR19=0x808, MR18=0x3B37, DQSOSC=398, MR23=63, INC=165, DEC=110
4345 12:20:59.304562 [RxdqsGatingPostProcess] freq 600
4346 12:20:59.310722 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4347 12:20:59.314563 Pre-setting of DQS Precalculation
4348 12:20:59.317787 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4349 12:20:59.318310 ==
4350 12:20:59.320845 Dram Type= 6, Freq= 0, CH_1, rank 0
4351 12:20:59.324168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 12:20:59.324584 ==
4353 12:20:59.330566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4354 12:20:59.337504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4355 12:20:59.340867 [CA 0] Center 35 (5~66) winsize 62
4356 12:20:59.343744 [CA 1] Center 35 (5~66) winsize 62
4357 12:20:59.347381 [CA 2] Center 35 (5~65) winsize 61
4358 12:20:59.350387 [CA 3] Center 33 (3~64) winsize 62
4359 12:20:59.353615 [CA 4] Center 34 (4~65) winsize 62
4360 12:20:59.356762 [CA 5] Center 33 (3~64) winsize 62
4361 12:20:59.357180
4362 12:20:59.360154 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4363 12:20:59.360589
4364 12:20:59.363348 [CATrainingPosCal] consider 1 rank data
4365 12:20:59.366879 u2DelayCellTimex100 = 270/100 ps
4366 12:20:59.370129 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4367 12:20:59.373190 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4368 12:20:59.376603 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4369 12:20:59.383566 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4370 12:20:59.386542 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 12:20:59.390234 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4372 12:20:59.390814
4373 12:20:59.393052 CA PerBit enable=1, Macro0, CA PI delay=33
4374 12:20:59.393708
4375 12:20:59.396604 [CBTSetCACLKResult] CA Dly = 33
4376 12:20:59.397060 CS Dly: 5 (0~36)
4377 12:20:59.397403 ==
4378 12:20:59.399716 Dram Type= 6, Freq= 0, CH_1, rank 1
4379 12:20:59.406258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 12:20:59.406679 ==
4381 12:20:59.409773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4382 12:20:59.416742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4383 12:20:59.420015 [CA 0] Center 36 (6~66) winsize 61
4384 12:20:59.423367 [CA 1] Center 36 (6~66) winsize 61
4385 12:20:59.426390 [CA 2] Center 34 (4~65) winsize 62
4386 12:20:59.429314 [CA 3] Center 34 (3~65) winsize 63
4387 12:20:59.432581 [CA 4] Center 34 (3~65) winsize 63
4388 12:20:59.436145 [CA 5] Center 34 (3~65) winsize 63
4389 12:20:59.436679
4390 12:20:59.439435 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4391 12:20:59.439858
4392 12:20:59.442649 [CATrainingPosCal] consider 2 rank data
4393 12:20:59.446038 u2DelayCellTimex100 = 270/100 ps
4394 12:20:59.449254 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4395 12:20:59.455516 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4396 12:20:59.459036 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4397 12:20:59.462338 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 12:20:59.466103 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 12:20:59.469373 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4400 12:20:59.469849
4401 12:20:59.472194 CA PerBit enable=1, Macro0, CA PI delay=33
4402 12:20:59.472642
4403 12:20:59.475459 [CBTSetCACLKResult] CA Dly = 33
4404 12:20:59.479020 CS Dly: 5 (0~36)
4405 12:20:59.479479
4406 12:20:59.482168 ----->DramcWriteLeveling(PI) begin...
4407 12:20:59.482721 ==
4408 12:20:59.485683 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 12:20:59.488692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 12:20:59.489315 ==
4411 12:20:59.492027 Write leveling (Byte 0): 29 => 29
4412 12:20:59.495646 Write leveling (Byte 1): 29 => 29
4413 12:20:59.498624 DramcWriteLeveling(PI) end<-----
4414 12:20:59.499173
4415 12:20:59.499728 ==
4416 12:20:59.501813 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 12:20:59.505402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 12:20:59.505817 ==
4419 12:20:59.508400 [Gating] SW mode calibration
4420 12:20:59.515219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4421 12:20:59.521525 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4422 12:20:59.524989 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 12:20:59.531330 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 12:20:59.534539 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 12:20:59.538239 0 9 12 | B1->B0 | 3232 2f2f | 0 0 | (1 1) (1 1)
4426 12:20:59.544681 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 12:20:59.548163 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 12:20:59.551309 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 12:20:59.554452 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 12:20:59.561369 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 12:20:59.564812 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 12:20:59.568134 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 12:20:59.574548 0 10 12 | B1->B0 | 3131 3636 | 0 0 | (0 0) (0 0)
4434 12:20:59.577982 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 12:20:59.581188 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 12:20:59.587890 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 12:20:59.591140 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 12:20:59.594432 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 12:20:59.600503 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 12:20:59.603871 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 12:20:59.610709 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4442 12:20:59.614110 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:20:59.617389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:20:59.623713 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:20:59.626951 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:20:59.630554 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:20:59.636947 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:20:59.640385 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:20:59.643312 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:20:59.650280 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:20:59.653548 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:20:59.656541 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:20:59.662969 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:20:59.666062 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:20:59.669559 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:20:59.676462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:20:59.679469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4458 12:20:59.683222 Total UI for P1: 0, mck2ui 16
4459 12:20:59.685835 best dqsien dly found for B1: ( 0, 13, 10)
4460 12:20:59.689539 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4461 12:20:59.692976 Total UI for P1: 0, mck2ui 16
4462 12:20:59.696003 best dqsien dly found for B0: ( 0, 13, 12)
4463 12:20:59.699374 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4464 12:20:59.702974 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4465 12:20:59.703492
4466 12:20:59.709164 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4467 12:20:59.712514 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4468 12:20:59.715891 [Gating] SW calibration Done
4469 12:20:59.716354 ==
4470 12:20:59.719071 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 12:20:59.722172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 12:20:59.722693 ==
4473 12:20:59.723025 RX Vref Scan: 0
4474 12:20:59.723333
4475 12:20:59.725528 RX Vref 0 -> 0, step: 1
4476 12:20:59.725942
4477 12:20:59.728720 RX Delay -230 -> 252, step: 16
4478 12:20:59.732480 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4479 12:20:59.739315 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4480 12:20:59.742050 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4481 12:20:59.745527 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4482 12:20:59.748558 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4483 12:20:59.751890 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4484 12:20:59.758656 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4485 12:20:59.761834 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4486 12:20:59.765506 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4487 12:20:59.768512 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4488 12:20:59.775028 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4489 12:20:59.778398 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4490 12:20:59.781610 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4491 12:20:59.785309 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4492 12:20:59.791451 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4493 12:20:59.794890 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4494 12:20:59.795413 ==
4495 12:20:59.798132 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 12:20:59.801938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 12:20:59.802465 ==
4498 12:20:59.804724 DQS Delay:
4499 12:20:59.805140 DQS0 = 0, DQS1 = 0
4500 12:20:59.807664 DQM Delay:
4501 12:20:59.808079 DQM0 = 43, DQM1 = 38
4502 12:20:59.808399 DQ Delay:
4503 12:20:59.810954 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4504 12:20:59.814201 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4505 12:20:59.817524 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4506 12:20:59.820926 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4507 12:20:59.821393
4508 12:20:59.821730
4509 12:20:59.824304 ==
4510 12:20:59.824723 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 12:20:59.831405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 12:20:59.832151 ==
4513 12:20:59.832532
4514 12:20:59.832848
4515 12:20:59.834029 TX Vref Scan disable
4516 12:20:59.834464 == TX Byte 0 ==
4517 12:20:59.840704 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4518 12:20:59.844338 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4519 12:20:59.844876 == TX Byte 1 ==
4520 12:20:59.850775 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 12:20:59.853704 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 12:20:59.854122 ==
4523 12:20:59.857223 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 12:20:59.860338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 12:20:59.860764 ==
4526 12:20:59.861098
4527 12:20:59.861406
4528 12:20:59.863584 TX Vref Scan disable
4529 12:20:59.866989 == TX Byte 0 ==
4530 12:20:59.870327 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4531 12:20:59.873635 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4532 12:20:59.877270 == TX Byte 1 ==
4533 12:20:59.880152 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 12:20:59.883675 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 12:20:59.884135
4536 12:20:59.887080 [DATLAT]
4537 12:20:59.887492 Freq=600, CH1 RK0
4538 12:20:59.888045
4539 12:20:59.890210 DATLAT Default: 0x9
4540 12:20:59.890629 0, 0xFFFF, sum = 0
4541 12:20:59.893272 1, 0xFFFF, sum = 0
4542 12:20:59.893728 2, 0xFFFF, sum = 0
4543 12:20:59.896428 3, 0xFFFF, sum = 0
4544 12:20:59.896868 4, 0xFFFF, sum = 0
4545 12:20:59.899806 5, 0xFFFF, sum = 0
4546 12:20:59.900293 6, 0xFFFF, sum = 0
4547 12:20:59.903251 7, 0xFFFF, sum = 0
4548 12:20:59.903682 8, 0x0, sum = 1
4549 12:20:59.906601 9, 0x0, sum = 2
4550 12:20:59.907026 10, 0x0, sum = 3
4551 12:20:59.909609 11, 0x0, sum = 4
4552 12:20:59.910065 best_step = 9
4553 12:20:59.910414
4554 12:20:59.910758 ==
4555 12:20:59.913039 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 12:20:59.920005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 12:20:59.920449 ==
4558 12:20:59.920781 RX Vref Scan: 1
4559 12:20:59.921086
4560 12:20:59.923382 RX Vref 0 -> 0, step: 1
4561 12:20:59.923791
4562 12:20:59.926178 RX Delay -179 -> 252, step: 8
4563 12:20:59.926587
4564 12:20:59.930120 Set Vref, RX VrefLevel [Byte0]: 51
4565 12:20:59.933652 [Byte1]: 50
4566 12:20:59.934168
4567 12:20:59.936171 Final RX Vref Byte 0 = 51 to rank0
4568 12:20:59.940000 Final RX Vref Byte 1 = 50 to rank0
4569 12:20:59.943439 Final RX Vref Byte 0 = 51 to rank1
4570 12:20:59.946736 Final RX Vref Byte 1 = 50 to rank1==
4571 12:20:59.949541 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 12:20:59.952912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 12:20:59.953463 ==
4574 12:20:59.956180 DQS Delay:
4575 12:20:59.956696 DQS0 = 0, DQS1 = 0
4576 12:20:59.960007 DQM Delay:
4577 12:20:59.960524 DQM0 = 42, DQM1 = 34
4578 12:20:59.960860 DQ Delay:
4579 12:20:59.962593 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4580 12:20:59.966133 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4581 12:20:59.969232 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4582 12:20:59.972687 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4583 12:20:59.973118
4584 12:20:59.973444
4585 12:20:59.983025 [DQSOSCAuto] RK0, (LSB)MR18= 0x243e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
4586 12:20:59.985612 CH1 RK0: MR19=808, MR18=243E
4587 12:20:59.992596 CH1_RK0: MR19=0x808, MR18=0x243E, DQSOSC=398, MR23=63, INC=165, DEC=110
4588 12:20:59.993015
4589 12:20:59.996005 ----->DramcWriteLeveling(PI) begin...
4590 12:20:59.996423 ==
4591 12:20:59.999317 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 12:21:00.002453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 12:21:00.002868 ==
4594 12:21:00.005574 Write leveling (Byte 0): 27 => 27
4595 12:21:00.008808 Write leveling (Byte 1): 30 => 30
4596 12:21:00.012723 DramcWriteLeveling(PI) end<-----
4597 12:21:00.013135
4598 12:21:00.013461 ==
4599 12:21:00.015454 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 12:21:00.018728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 12:21:00.019146 ==
4602 12:21:00.021966 [Gating] SW mode calibration
4603 12:21:00.029100 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4604 12:21:00.035331 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4605 12:21:00.038686 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 12:21:00.041653 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 12:21:00.048451 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4608 12:21:00.051795 0 9 12 | B1->B0 | 3131 2b2b | 1 0 | (1 0) (0 0)
4609 12:21:00.055152 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 12:21:00.062177 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 12:21:00.065241 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 12:21:00.068261 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 12:21:00.074720 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 12:21:00.078347 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 12:21:00.081863 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4616 12:21:00.088005 0 10 12 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
4617 12:21:00.091838 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 12:21:00.094802 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 12:21:00.101324 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 12:21:00.104986 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 12:21:00.108047 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 12:21:00.114386 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 12:21:00.118110 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 12:21:00.121112 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4625 12:21:00.128368 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:21:00.131211 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:21:00.134519 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:21:00.140767 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:21:00.144212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:21:00.147678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:21:00.154115 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:21:00.158033 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:21:00.160457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:21:00.167456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:21:00.170857 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:21:00.173941 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:21:00.180415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:21:00.183885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:21:00.187285 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:21:00.193626 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4641 12:21:00.197128 Total UI for P1: 0, mck2ui 16
4642 12:21:00.200254 best dqsien dly found for B0: ( 0, 13, 10)
4643 12:21:00.203219 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 12:21:00.207354 Total UI for P1: 0, mck2ui 16
4645 12:21:00.209681 best dqsien dly found for B1: ( 0, 13, 12)
4646 12:21:00.213233 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4647 12:21:00.216650 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4648 12:21:00.217063
4649 12:21:00.219552 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4650 12:21:00.226450 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4651 12:21:00.226906 [Gating] SW calibration Done
4652 12:21:00.227265 ==
4653 12:21:00.230311 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 12:21:00.236409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 12:21:00.236824 ==
4656 12:21:00.237156 RX Vref Scan: 0
4657 12:21:00.237462
4658 12:21:00.239836 RX Vref 0 -> 0, step: 1
4659 12:21:00.240294
4660 12:21:00.242900 RX Delay -230 -> 252, step: 16
4661 12:21:00.246031 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4662 12:21:00.249600 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4663 12:21:00.256397 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4664 12:21:00.259130 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4665 12:21:00.262608 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4666 12:21:00.265772 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4667 12:21:00.269568 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4668 12:21:00.275756 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4669 12:21:00.279259 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4670 12:21:00.282795 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4671 12:21:00.286201 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4672 12:21:00.292016 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4673 12:21:00.295606 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4674 12:21:00.299240 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4675 12:21:00.302302 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4676 12:21:00.308864 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4677 12:21:00.309398 ==
4678 12:21:00.311849 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 12:21:00.315033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 12:21:00.315446 ==
4681 12:21:00.315774 DQS Delay:
4682 12:21:00.318860 DQS0 = 0, DQS1 = 0
4683 12:21:00.319518 DQM Delay:
4684 12:21:00.321866 DQM0 = 41, DQM1 = 39
4685 12:21:00.322306 DQ Delay:
4686 12:21:00.325156 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4687 12:21:00.329230 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4688 12:21:00.332465 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4689 12:21:00.335757 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4690 12:21:00.336289
4691 12:21:00.336627
4692 12:21:00.337022 ==
4693 12:21:00.338309 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 12:21:00.341581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 12:21:00.345006 ==
4696 12:21:00.345420
4697 12:21:00.345745
4698 12:21:00.346132 TX Vref Scan disable
4699 12:21:00.348227 == TX Byte 0 ==
4700 12:21:00.351703 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4701 12:21:00.358217 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4702 12:21:00.358704 == TX Byte 1 ==
4703 12:21:00.361806 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 12:21:00.368208 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 12:21:00.368714 ==
4706 12:21:00.371278 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 12:21:00.374920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 12:21:00.375338 ==
4709 12:21:00.375665
4710 12:21:00.376033
4711 12:21:00.378065 TX Vref Scan disable
4712 12:21:00.381380 == TX Byte 0 ==
4713 12:21:00.384410 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4714 12:21:00.387318 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4715 12:21:00.390598 == TX Byte 1 ==
4716 12:21:00.393867 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4717 12:21:00.397230 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4718 12:21:00.397311
4719 12:21:00.397374 [DATLAT]
4720 12:21:00.400897 Freq=600, CH1 RK1
4721 12:21:00.401059
4722 12:21:00.404182 DATLAT Default: 0x9
4723 12:21:00.404343 0, 0xFFFF, sum = 0
4724 12:21:00.407368 1, 0xFFFF, sum = 0
4725 12:21:00.407524 2, 0xFFFF, sum = 0
4726 12:21:00.410882 3, 0xFFFF, sum = 0
4727 12:21:00.411057 4, 0xFFFF, sum = 0
4728 12:21:00.413857 5, 0xFFFF, sum = 0
4729 12:21:00.414026 6, 0xFFFF, sum = 0
4730 12:21:00.417261 7, 0xFFFF, sum = 0
4731 12:21:00.417414 8, 0x0, sum = 1
4732 12:21:00.420649 9, 0x0, sum = 2
4733 12:21:00.420847 10, 0x0, sum = 3
4734 12:21:00.423593 11, 0x0, sum = 4
4735 12:21:00.423739 best_step = 9
4736 12:21:00.423846
4737 12:21:00.423958 ==
4738 12:21:00.427004 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 12:21:00.430412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 12:21:00.430563 ==
4741 12:21:00.433958 RX Vref Scan: 0
4742 12:21:00.434127
4743 12:21:00.437072 RX Vref 0 -> 0, step: 1
4744 12:21:00.437240
4745 12:21:00.437373 RX Delay -179 -> 252, step: 8
4746 12:21:00.445414 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4747 12:21:00.448623 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4748 12:21:00.451845 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4749 12:21:00.454998 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4750 12:21:00.462320 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4751 12:21:00.465444 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4752 12:21:00.468548 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4753 12:21:00.472036 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4754 12:21:00.478511 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4755 12:21:00.481899 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4756 12:21:00.484912 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4757 12:21:00.487981 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4758 12:21:00.495013 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4759 12:21:00.498109 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4760 12:21:00.501512 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4761 12:21:00.504591 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4762 12:21:00.505008 ==
4763 12:21:00.508327 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 12:21:00.514394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 12:21:00.514814 ==
4766 12:21:00.515145 DQS Delay:
4767 12:21:00.518309 DQS0 = 0, DQS1 = 0
4768 12:21:00.518725 DQM Delay:
4769 12:21:00.519056 DQM0 = 38, DQM1 = 35
4770 12:21:00.521497 DQ Delay:
4771 12:21:00.524692 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4772 12:21:00.528163 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4773 12:21:00.531662 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4774 12:21:00.534684 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4775 12:21:00.535201
4776 12:21:00.535530
4777 12:21:00.541280 [DQSOSCAuto] RK1, (LSB)MR18= 0x3358, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4778 12:21:00.544294 CH1 RK1: MR19=808, MR18=3358
4779 12:21:00.550854 CH1_RK1: MR19=0x808, MR18=0x3358, DQSOSC=393, MR23=63, INC=169, DEC=113
4780 12:21:00.554051 [RxdqsGatingPostProcess] freq 600
4781 12:21:00.557291 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4782 12:21:00.561144 Pre-setting of DQS Precalculation
4783 12:21:00.567501 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4784 12:21:00.573635 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4785 12:21:00.580736 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4786 12:21:00.581159
4787 12:21:00.581485
4788 12:21:00.583952 [Calibration Summary] 1200 Mbps
4789 12:21:00.587237 CH 0, Rank 0
4790 12:21:00.587774 SW Impedance : PASS
4791 12:21:00.590447 DUTY Scan : NO K
4792 12:21:00.593679 ZQ Calibration : PASS
4793 12:21:00.594095 Jitter Meter : NO K
4794 12:21:00.597632 CBT Training : PASS
4795 12:21:00.600166 Write leveling : PASS
4796 12:21:00.600584 RX DQS gating : PASS
4797 12:21:00.603440 RX DQ/DQS(RDDQC) : PASS
4798 12:21:00.603856 TX DQ/DQS : PASS
4799 12:21:00.606756 RX DATLAT : PASS
4800 12:21:00.610317 RX DQ/DQS(Engine): PASS
4801 12:21:00.610776 TX OE : NO K
4802 12:21:00.613711 All Pass.
4803 12:21:00.614136
4804 12:21:00.614463 CH 0, Rank 1
4805 12:21:00.616849 SW Impedance : PASS
4806 12:21:00.617265 DUTY Scan : NO K
4807 12:21:00.620004 ZQ Calibration : PASS
4808 12:21:00.623412 Jitter Meter : NO K
4809 12:21:00.623970 CBT Training : PASS
4810 12:21:00.626653 Write leveling : PASS
4811 12:21:00.630244 RX DQS gating : PASS
4812 12:21:00.630662 RX DQ/DQS(RDDQC) : PASS
4813 12:21:00.633331 TX DQ/DQS : PASS
4814 12:21:00.636557 RX DATLAT : PASS
4815 12:21:00.636973 RX DQ/DQS(Engine): PASS
4816 12:21:00.639615 TX OE : NO K
4817 12:21:00.640138 All Pass.
4818 12:21:00.640487
4819 12:21:00.642971 CH 1, Rank 0
4820 12:21:00.643384 SW Impedance : PASS
4821 12:21:00.646243 DUTY Scan : NO K
4822 12:21:00.649790 ZQ Calibration : PASS
4823 12:21:00.650207 Jitter Meter : NO K
4824 12:21:00.653162 CBT Training : PASS
4825 12:21:00.656398 Write leveling : PASS
4826 12:21:00.656816 RX DQS gating : PASS
4827 12:21:00.659590 RX DQ/DQS(RDDQC) : PASS
4828 12:21:00.663409 TX DQ/DQS : PASS
4829 12:21:00.663981 RX DATLAT : PASS
4830 12:21:00.666084 RX DQ/DQS(Engine): PASS
4831 12:21:00.670025 TX OE : NO K
4832 12:21:00.670557 All Pass.
4833 12:21:00.670890
4834 12:21:00.671358 CH 1, Rank 1
4835 12:21:00.673158 SW Impedance : PASS
4836 12:21:00.676065 DUTY Scan : NO K
4837 12:21:00.676575 ZQ Calibration : PASS
4838 12:21:00.679134 Jitter Meter : NO K
4839 12:21:00.682359 CBT Training : PASS
4840 12:21:00.682779 Write leveling : PASS
4841 12:21:00.685731 RX DQS gating : PASS
4842 12:21:00.686152 RX DQ/DQS(RDDQC) : PASS
4843 12:21:00.689216 TX DQ/DQS : PASS
4844 12:21:00.692282 RX DATLAT : PASS
4845 12:21:00.692700 RX DQ/DQS(Engine): PASS
4846 12:21:00.695631 TX OE : NO K
4847 12:21:00.696090 All Pass.
4848 12:21:00.696427
4849 12:21:00.699672 DramC Write-DBI off
4850 12:21:00.702386 PER_BANK_REFRESH: Hybrid Mode
4851 12:21:00.702804 TX_TRACKING: ON
4852 12:21:00.712187 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4853 12:21:00.715447 [FAST_K] Save calibration result to emmc
4854 12:21:00.718883 dramc_set_vcore_voltage set vcore to 662500
4855 12:21:00.721706 Read voltage for 933, 3
4856 12:21:00.722125 Vio18 = 0
4857 12:21:00.725306 Vcore = 662500
4858 12:21:00.725726 Vdram = 0
4859 12:21:00.726061 Vddq = 0
4860 12:21:00.726365 Vmddr = 0
4861 12:21:00.731619 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4862 12:21:00.738579 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4863 12:21:00.738997 MEM_TYPE=3, freq_sel=17
4864 12:21:00.741689 sv_algorithm_assistance_LP4_1600
4865 12:21:00.744928 ============ PULL DRAM RESETB DOWN ============
4866 12:21:00.751718 ========== PULL DRAM RESETB DOWN end =========
4867 12:21:00.754720 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4868 12:21:00.758580 ===================================
4869 12:21:00.761875 LPDDR4 DRAM CONFIGURATION
4870 12:21:00.764809 ===================================
4871 12:21:00.765278 EX_ROW_EN[0] = 0x0
4872 12:21:00.768440 EX_ROW_EN[1] = 0x0
4873 12:21:00.768859 LP4Y_EN = 0x0
4874 12:21:00.771256 WORK_FSP = 0x0
4875 12:21:00.774716 WL = 0x3
4876 12:21:00.775138 RL = 0x3
4877 12:21:00.778194 BL = 0x2
4878 12:21:00.778659 RPST = 0x0
4879 12:21:00.781471 RD_PRE = 0x0
4880 12:21:00.781897 WR_PRE = 0x1
4881 12:21:00.784385 WR_PST = 0x0
4882 12:21:00.784815 DBI_WR = 0x0
4883 12:21:00.787548 DBI_RD = 0x0
4884 12:21:00.788002 OTF = 0x1
4885 12:21:00.791131 ===================================
4886 12:21:00.794189 ===================================
4887 12:21:00.797477 ANA top config
4888 12:21:00.800759 ===================================
4889 12:21:00.801215 DLL_ASYNC_EN = 0
4890 12:21:00.804468 ALL_SLAVE_EN = 1
4891 12:21:00.807518 NEW_RANK_MODE = 1
4892 12:21:00.810629 DLL_IDLE_MODE = 1
4893 12:21:00.813990 LP45_APHY_COMB_EN = 1
4894 12:21:00.814412 TX_ODT_DIS = 1
4895 12:21:00.817534 NEW_8X_MODE = 1
4896 12:21:00.820536 ===================================
4897 12:21:00.823814 ===================================
4898 12:21:00.827761 data_rate = 1866
4899 12:21:00.830498 CKR = 1
4900 12:21:00.834257 DQ_P2S_RATIO = 8
4901 12:21:00.837484 ===================================
4902 12:21:00.840543 CA_P2S_RATIO = 8
4903 12:21:00.841023 DQ_CA_OPEN = 0
4904 12:21:00.843649 DQ_SEMI_OPEN = 0
4905 12:21:00.846833 CA_SEMI_OPEN = 0
4906 12:21:00.850499 CA_FULL_RATE = 0
4907 12:21:00.853429 DQ_CKDIV4_EN = 1
4908 12:21:00.856640 CA_CKDIV4_EN = 1
4909 12:21:00.857067 CA_PREDIV_EN = 0
4910 12:21:00.860296 PH8_DLY = 0
4911 12:21:00.863387 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4912 12:21:00.866637 DQ_AAMCK_DIV = 4
4913 12:21:00.870698 CA_AAMCK_DIV = 4
4914 12:21:00.873392 CA_ADMCK_DIV = 4
4915 12:21:00.876112 DQ_TRACK_CA_EN = 0
4916 12:21:00.876566 CA_PICK = 933
4917 12:21:00.879868 CA_MCKIO = 933
4918 12:21:00.883352 MCKIO_SEMI = 0
4919 12:21:00.886604 PLL_FREQ = 3732
4920 12:21:00.889857 DQ_UI_PI_RATIO = 32
4921 12:21:00.892859 CA_UI_PI_RATIO = 0
4922 12:21:00.896564 ===================================
4923 12:21:00.899469 ===================================
4924 12:21:00.902646 memory_type:LPDDR4
4925 12:21:00.903081 GP_NUM : 10
4926 12:21:00.906132 SRAM_EN : 1
4927 12:21:00.906552 MD32_EN : 0
4928 12:21:00.909371 ===================================
4929 12:21:00.912765 [ANA_INIT] >>>>>>>>>>>>>>
4930 12:21:00.916129 <<<<<< [CONFIGURE PHASE]: ANA_TX
4931 12:21:00.919611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4932 12:21:00.922705 ===================================
4933 12:21:00.925453 data_rate = 1866,PCW = 0X8f00
4934 12:21:00.929011 ===================================
4935 12:21:00.932142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4936 12:21:00.938957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 12:21:00.942539 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4938 12:21:00.948663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4939 12:21:00.951836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4940 12:21:00.955152 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4941 12:21:00.955596 [ANA_INIT] flow start
4942 12:21:00.958552 [ANA_INIT] PLL >>>>>>>>
4943 12:21:00.961966 [ANA_INIT] PLL <<<<<<<<
4944 12:21:00.962495 [ANA_INIT] MIDPI >>>>>>>>
4945 12:21:00.965287 [ANA_INIT] MIDPI <<<<<<<<
4946 12:21:00.968536 [ANA_INIT] DLL >>>>>>>>
4947 12:21:00.969067 [ANA_INIT] flow end
4948 12:21:00.974863 ============ LP4 DIFF to SE enter ============
4949 12:21:00.978710 ============ LP4 DIFF to SE exit ============
4950 12:21:00.981745 [ANA_INIT] <<<<<<<<<<<<<
4951 12:21:00.984952 [Flow] Enable top DCM control >>>>>
4952 12:21:00.988377 [Flow] Enable top DCM control <<<<<
4953 12:21:00.991450 Enable DLL master slave shuffle
4954 12:21:00.994680 ==============================================================
4955 12:21:00.998126 Gating Mode config
4956 12:21:01.001463 ==============================================================
4957 12:21:01.004711 Config description:
4958 12:21:01.014729 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4959 12:21:01.021366 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4960 12:21:01.024497 SELPH_MODE 0: By rank 1: By Phase
4961 12:21:01.031047 ==============================================================
4962 12:21:01.034397 GAT_TRACK_EN = 1
4963 12:21:01.037567 RX_GATING_MODE = 2
4964 12:21:01.040707 RX_GATING_TRACK_MODE = 2
4965 12:21:01.044704 SELPH_MODE = 1
4966 12:21:01.047299 PICG_EARLY_EN = 1
4967 12:21:01.050472 VALID_LAT_VALUE = 1
4968 12:21:01.054554 ==============================================================
4969 12:21:01.057718 Enter into Gating configuration >>>>
4970 12:21:01.060794 Exit from Gating configuration <<<<
4971 12:21:01.064298 Enter into DVFS_PRE_config >>>>>
4972 12:21:01.077149 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4973 12:21:01.080379 Exit from DVFS_PRE_config <<<<<
4974 12:21:01.083730 Enter into PICG configuration >>>>
4975 12:21:01.084195 Exit from PICG configuration <<<<
4976 12:21:01.087057 [RX_INPUT] configuration >>>>>
4977 12:21:01.090447 [RX_INPUT] configuration <<<<<
4978 12:21:01.096572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4979 12:21:01.100138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4980 12:21:01.106888 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4981 12:21:01.113264 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4982 12:21:01.119496 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 12:21:01.126768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 12:21:01.130078 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4985 12:21:01.132776 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4986 12:21:01.139309 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4987 12:21:01.142608 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4988 12:21:01.146403 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4989 12:21:01.152534 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 12:21:01.155799 ===================================
4991 12:21:01.156295 LPDDR4 DRAM CONFIGURATION
4992 12:21:01.158834 ===================================
4993 12:21:01.162473 EX_ROW_EN[0] = 0x0
4994 12:21:01.162947 EX_ROW_EN[1] = 0x0
4995 12:21:01.165757 LP4Y_EN = 0x0
4996 12:21:01.169150 WORK_FSP = 0x0
4997 12:21:01.169638 WL = 0x3
4998 12:21:01.172183 RL = 0x3
4999 12:21:01.172623 BL = 0x2
5000 12:21:01.175648 RPST = 0x0
5001 12:21:01.176181 RD_PRE = 0x0
5002 12:21:01.178643 WR_PRE = 0x1
5003 12:21:01.179086 WR_PST = 0x0
5004 12:21:01.181841 DBI_WR = 0x0
5005 12:21:01.182252 DBI_RD = 0x0
5006 12:21:01.185443 OTF = 0x1
5007 12:21:01.188656 ===================================
5008 12:21:01.191752 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5009 12:21:01.195412 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5010 12:21:01.201798 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 12:21:01.205018 ===================================
5012 12:21:01.205461 LPDDR4 DRAM CONFIGURATION
5013 12:21:01.208019 ===================================
5014 12:21:01.211532 EX_ROW_EN[0] = 0x10
5015 12:21:01.214722 EX_ROW_EN[1] = 0x0
5016 12:21:01.215150 LP4Y_EN = 0x0
5017 12:21:01.218394 WORK_FSP = 0x0
5018 12:21:01.218902 WL = 0x3
5019 12:21:01.221543 RL = 0x3
5020 12:21:01.222030 BL = 0x2
5021 12:21:01.225053 RPST = 0x0
5022 12:21:01.225472 RD_PRE = 0x0
5023 12:21:01.228194 WR_PRE = 0x1
5024 12:21:01.228622 WR_PST = 0x0
5025 12:21:01.231439 DBI_WR = 0x0
5026 12:21:01.231998 DBI_RD = 0x0
5027 12:21:01.236154 OTF = 0x1
5028 12:21:01.238065 ===================================
5029 12:21:01.244599 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5030 12:21:01.247867 nWR fixed to 30
5031 12:21:01.248333 [ModeRegInit_LP4] CH0 RK0
5032 12:21:01.251343 [ModeRegInit_LP4] CH0 RK1
5033 12:21:01.254538 [ModeRegInit_LP4] CH1 RK0
5034 12:21:01.257934 [ModeRegInit_LP4] CH1 RK1
5035 12:21:01.258465 match AC timing 9
5036 12:21:01.264443 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5037 12:21:01.267802 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5038 12:21:01.271200 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5039 12:21:01.278250 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5040 12:21:01.280843 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5041 12:21:01.281310 ==
5042 12:21:01.284177 Dram Type= 6, Freq= 0, CH_0, rank 0
5043 12:21:01.287948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5044 12:21:01.288364 ==
5045 12:21:01.293918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5046 12:21:01.300444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5047 12:21:01.304402 [CA 0] Center 37 (7~68) winsize 62
5048 12:21:01.307546 [CA 1] Center 37 (7~68) winsize 62
5049 12:21:01.310792 [CA 2] Center 34 (4~65) winsize 62
5050 12:21:01.314056 [CA 3] Center 34 (4~65) winsize 62
5051 12:21:01.317435 [CA 4] Center 32 (2~63) winsize 62
5052 12:21:01.320577 [CA 5] Center 32 (2~63) winsize 62
5053 12:21:01.320989
5054 12:21:01.323861 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5055 12:21:01.324292
5056 12:21:01.327110 [CATrainingPosCal] consider 1 rank data
5057 12:21:01.330725 u2DelayCellTimex100 = 270/100 ps
5058 12:21:01.333966 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5059 12:21:01.337133 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5060 12:21:01.340592 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5061 12:21:01.343306 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5062 12:21:01.346527 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5063 12:21:01.353759 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5064 12:21:01.354173
5065 12:21:01.356429 CA PerBit enable=1, Macro0, CA PI delay=32
5066 12:21:01.356845
5067 12:21:01.359682 [CBTSetCACLKResult] CA Dly = 32
5068 12:21:01.360131 CS Dly: 5 (0~36)
5069 12:21:01.360462 ==
5070 12:21:01.363401 Dram Type= 6, Freq= 0, CH_0, rank 1
5071 12:21:01.370357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 12:21:01.370794 ==
5073 12:21:01.373381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5074 12:21:01.379707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5075 12:21:01.383460 [CA 0] Center 38 (8~68) winsize 61
5076 12:21:01.386895 [CA 1] Center 37 (7~68) winsize 62
5077 12:21:01.389738 [CA 2] Center 34 (4~65) winsize 62
5078 12:21:01.392676 [CA 3] Center 34 (4~65) winsize 62
5079 12:21:01.396391 [CA 4] Center 33 (2~64) winsize 63
5080 12:21:01.399661 [CA 5] Center 32 (2~63) winsize 62
5081 12:21:01.400109
5082 12:21:01.402711 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5083 12:21:01.403129
5084 12:21:01.406259 [CATrainingPosCal] consider 2 rank data
5085 12:21:01.409396 u2DelayCellTimex100 = 270/100 ps
5086 12:21:01.412887 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5087 12:21:01.415715 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5088 12:21:01.422184 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5089 12:21:01.425558 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5090 12:21:01.429278 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5091 12:21:01.432353 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5092 12:21:01.432766
5093 12:21:01.435598 CA PerBit enable=1, Macro0, CA PI delay=32
5094 12:21:01.436261
5095 12:21:01.438872 [CBTSetCACLKResult] CA Dly = 32
5096 12:21:01.442788 CS Dly: 6 (0~39)
5097 12:21:01.443204
5098 12:21:01.445236 ----->DramcWriteLeveling(PI) begin...
5099 12:21:01.445654 ==
5100 12:21:01.448975 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 12:21:01.452203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 12:21:01.452797 ==
5103 12:21:01.455278 Write leveling (Byte 0): 33 => 33
5104 12:21:01.458977 Write leveling (Byte 1): 30 => 30
5105 12:21:01.461685 DramcWriteLeveling(PI) end<-----
5106 12:21:01.462100
5107 12:21:01.462422 ==
5108 12:21:01.465152 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 12:21:01.468233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 12:21:01.468650 ==
5111 12:21:01.471271 [Gating] SW mode calibration
5112 12:21:01.478336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5113 12:21:01.484842 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5114 12:21:01.488278 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (0 0)
5115 12:21:01.491450 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5116 12:21:01.498248 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 12:21:01.501197 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 12:21:01.504838 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 12:21:01.511808 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 12:21:01.514783 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5121 12:21:01.518073 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
5122 12:21:01.524408 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5123 12:21:01.527683 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5124 12:21:01.530984 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 12:21:01.537764 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 12:21:01.540940 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 12:21:01.547325 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 12:21:01.550446 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 12:21:01.554049 0 15 28 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
5130 12:21:01.560451 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5131 12:21:01.563499 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 12:21:01.567129 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 12:21:01.573921 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 12:21:01.576745 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 12:21:01.580190 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 12:21:01.583795 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5137 12:21:01.590601 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5138 12:21:01.593811 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5139 12:21:01.597262 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5140 12:21:01.603460 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:21:01.606908 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:21:01.610375 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:21:01.616483 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:21:01.621097 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:21:01.623435 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:21:01.630076 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:21:01.633162 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:21:01.636477 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:21:01.643062 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:21:01.646991 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:21:01.649845 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:21:01.656546 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5153 12:21:01.659645 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5154 12:21:01.663292 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5155 12:21:01.669746 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 12:21:01.673079 Total UI for P1: 0, mck2ui 16
5157 12:21:01.676166 best dqsien dly found for B0: ( 1, 2, 28)
5158 12:21:01.679281 Total UI for P1: 0, mck2ui 16
5159 12:21:01.682412 best dqsien dly found for B1: ( 1, 3, 2)
5160 12:21:01.685641 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5161 12:21:01.688948 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5162 12:21:01.689431
5163 12:21:01.692746 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5164 12:21:01.695775 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5165 12:21:01.698921 [Gating] SW calibration Done
5166 12:21:01.699336 ==
5167 12:21:01.702416 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 12:21:01.705620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 12:21:01.706135 ==
5170 12:21:01.708863 RX Vref Scan: 0
5171 12:21:01.709274
5172 12:21:01.712021 RX Vref 0 -> 0, step: 1
5173 12:21:01.712436
5174 12:21:01.712762 RX Delay -80 -> 252, step: 8
5175 12:21:01.718743 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5176 12:21:01.722278 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5177 12:21:01.725425 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5178 12:21:01.728887 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5179 12:21:01.732082 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5180 12:21:01.735224 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5181 12:21:01.741796 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5182 12:21:01.745750 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5183 12:21:01.748414 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5184 12:21:01.751792 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5185 12:21:01.754755 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5186 12:21:01.761497 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5187 12:21:01.764704 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5188 12:21:01.768520 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5189 12:21:01.771743 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5190 12:21:01.774621 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5191 12:21:01.775032 ==
5192 12:21:01.778075 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 12:21:01.784779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 12:21:01.785194 ==
5195 12:21:01.785519 DQS Delay:
5196 12:21:01.787674 DQS0 = 0, DQS1 = 0
5197 12:21:01.788118 DQM Delay:
5198 12:21:01.791197 DQM0 = 100, DQM1 = 88
5199 12:21:01.791717 DQ Delay:
5200 12:21:01.794448 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5201 12:21:01.798292 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5202 12:21:01.801163 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5203 12:21:01.804224 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5204 12:21:01.804636
5205 12:21:01.804956
5206 12:21:01.805256 ==
5207 12:21:01.807580 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 12:21:01.810700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 12:21:01.811114 ==
5210 12:21:01.811437
5211 12:21:01.814600
5212 12:21:01.815119 TX Vref Scan disable
5213 12:21:01.817918 == TX Byte 0 ==
5214 12:21:01.820838 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5215 12:21:01.823822 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5216 12:21:01.827506 == TX Byte 1 ==
5217 12:21:01.830738 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5218 12:21:01.833925 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5219 12:21:01.834444 ==
5220 12:21:01.837270 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 12:21:01.843482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 12:21:01.843978 ==
5223 12:21:01.844484
5224 12:21:01.844995
5225 12:21:01.846733 TX Vref Scan disable
5226 12:21:01.847302 == TX Byte 0 ==
5227 12:21:01.853769 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5228 12:21:01.857096 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5229 12:21:01.857681 == TX Byte 1 ==
5230 12:21:01.863178 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5231 12:21:01.866464 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5232 12:21:01.866877
5233 12:21:01.867261 [DATLAT]
5234 12:21:01.870148 Freq=933, CH0 RK0
5235 12:21:01.870722
5236 12:21:01.871267 DATLAT Default: 0xd
5237 12:21:01.873197 0, 0xFFFF, sum = 0
5238 12:21:01.873616 1, 0xFFFF, sum = 0
5239 12:21:01.876357 2, 0xFFFF, sum = 0
5240 12:21:01.876775 3, 0xFFFF, sum = 0
5241 12:21:01.879893 4, 0xFFFF, sum = 0
5242 12:21:01.880362 5, 0xFFFF, sum = 0
5243 12:21:01.883455 6, 0xFFFF, sum = 0
5244 12:21:01.886673 7, 0xFFFF, sum = 0
5245 12:21:01.887191 8, 0xFFFF, sum = 0
5246 12:21:01.889837 9, 0xFFFF, sum = 0
5247 12:21:01.890258 10, 0x0, sum = 1
5248 12:21:01.892844 11, 0x0, sum = 2
5249 12:21:01.893265 12, 0x0, sum = 3
5250 12:21:01.893597 13, 0x0, sum = 4
5251 12:21:01.896288 best_step = 11
5252 12:21:01.896727
5253 12:21:01.897051 ==
5254 12:21:01.899793 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 12:21:01.903027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 12:21:01.903529 ==
5257 12:21:01.906539 RX Vref Scan: 1
5258 12:21:01.907017
5259 12:21:01.909341 RX Vref 0 -> 0, step: 1
5260 12:21:01.909818
5261 12:21:01.910275 RX Delay -61 -> 252, step: 4
5262 12:21:01.910597
5263 12:21:01.912653 Set Vref, RX VrefLevel [Byte0]: 51
5264 12:21:01.916044 [Byte1]: 49
5265 12:21:01.920971
5266 12:21:01.921384 Final RX Vref Byte 0 = 51 to rank0
5267 12:21:01.923648 Final RX Vref Byte 1 = 49 to rank0
5268 12:21:01.927151 Final RX Vref Byte 0 = 51 to rank1
5269 12:21:01.930375 Final RX Vref Byte 1 = 49 to rank1==
5270 12:21:01.933769 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 12:21:01.940589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 12:21:01.941067 ==
5273 12:21:01.941400 DQS Delay:
5274 12:21:01.943378 DQS0 = 0, DQS1 = 0
5275 12:21:01.943824 DQM Delay:
5276 12:21:01.944215 DQM0 = 99, DQM1 = 87
5277 12:21:01.946916 DQ Delay:
5278 12:21:01.950458 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5279 12:21:01.953740 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5280 12:21:01.956798 DQ8 =80, DQ9 =74, DQ10 =86, DQ11 =82
5281 12:21:01.960198 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5282 12:21:01.960611
5283 12:21:01.960934
5284 12:21:01.967026 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5285 12:21:01.970228 CH0 RK0: MR19=505, MR18=1A14
5286 12:21:01.976775 CH0_RK0: MR19=0x505, MR18=0x1A14, DQSOSC=413, MR23=63, INC=63, DEC=42
5287 12:21:01.977192
5288 12:21:01.980077 ----->DramcWriteLeveling(PI) begin...
5289 12:21:01.980505 ==
5290 12:21:01.983649 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 12:21:01.987060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 12:21:01.987574 ==
5293 12:21:01.989985 Write leveling (Byte 0): 34 => 34
5294 12:21:01.993209 Write leveling (Byte 1): 25 => 25
5295 12:21:01.996455 DramcWriteLeveling(PI) end<-----
5296 12:21:01.996869
5297 12:21:01.997194 ==
5298 12:21:02.000165 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 12:21:02.006918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 12:21:02.007453 ==
5301 12:21:02.007962 [Gating] SW mode calibration
5302 12:21:02.016098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5303 12:21:02.020046 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5304 12:21:02.023407 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5305 12:21:02.030023 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 12:21:02.033200 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 12:21:02.036366 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 12:21:02.042646 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 12:21:02.045892 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 12:21:02.049641 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5311 12:21:02.056376 0 14 28 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 0)
5312 12:21:02.059467 0 15 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (0 0)
5313 12:21:02.062507 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 12:21:02.068998 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 12:21:02.072643 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 12:21:02.078822 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 12:21:02.082107 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 12:21:02.085379 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5319 12:21:02.091808 0 15 28 | B1->B0 | 2e2e 3d3d | 1 0 | (0 0) (0 0)
5320 12:21:02.095391 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5321 12:21:02.098669 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 12:21:02.105432 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 12:21:02.108116 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 12:21:02.111885 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 12:21:02.118797 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 12:21:02.122049 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 12:21:02.124883 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5328 12:21:02.131437 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5329 12:21:02.134614 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5330 12:21:02.138032 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:21:02.144645 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:21:02.148151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:21:02.151865 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:21:02.158003 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:21:02.161507 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:21:02.164522 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:21:02.170831 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:21:02.174510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:21:02.177739 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:21:02.184075 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:21:02.187487 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:21:02.190608 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5343 12:21:02.197724 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5344 12:21:02.200478 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5345 12:21:02.203816 Total UI for P1: 0, mck2ui 16
5346 12:21:02.207114 best dqsien dly found for B0: ( 1, 2, 26)
5347 12:21:02.210299 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 12:21:02.213877 Total UI for P1: 0, mck2ui 16
5349 12:21:02.217161 best dqsien dly found for B1: ( 1, 2, 30)
5350 12:21:02.220235 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5351 12:21:02.223675 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5352 12:21:02.224137
5353 12:21:02.230023 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5354 12:21:02.233821 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5355 12:21:02.234237 [Gating] SW calibration Done
5356 12:21:02.236903 ==
5357 12:21:02.239986 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 12:21:02.243069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 12:21:02.243488 ==
5360 12:21:02.243814 RX Vref Scan: 0
5361 12:21:02.244183
5362 12:21:02.247392 RX Vref 0 -> 0, step: 1
5363 12:21:02.247802
5364 12:21:02.249727 RX Delay -80 -> 252, step: 8
5365 12:21:02.253329 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5366 12:21:02.256769 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5367 12:21:02.259942 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5368 12:21:02.266602 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5369 12:21:02.269778 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5370 12:21:02.273014 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5371 12:21:02.276439 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5372 12:21:02.279502 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5373 12:21:02.282638 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5374 12:21:02.289589 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5375 12:21:02.292809 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5376 12:21:02.295753 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5377 12:21:02.299495 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5378 12:21:02.302661 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5379 12:21:02.309075 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5380 12:21:02.312303 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5381 12:21:02.312719 ==
5382 12:21:02.315588 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 12:21:02.319013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 12:21:02.319429 ==
5385 12:21:02.322813 DQS Delay:
5386 12:21:02.323226 DQS0 = 0, DQS1 = 0
5387 12:21:02.323554 DQM Delay:
5388 12:21:02.326306 DQM0 = 97, DQM1 = 88
5389 12:21:02.326916 DQ Delay:
5390 12:21:02.329206 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5391 12:21:02.332133 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5392 12:21:02.335049 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5393 12:21:02.338387 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5394 12:21:02.338803
5395 12:21:02.339127
5396 12:21:02.339431 ==
5397 12:21:02.342022 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 12:21:02.348214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 12:21:02.348637 ==
5400 12:21:02.348964
5401 12:21:02.349267
5402 12:21:02.351508 TX Vref Scan disable
5403 12:21:02.351961 == TX Byte 0 ==
5404 12:21:02.354874 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5405 12:21:02.361881 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5406 12:21:02.362299 == TX Byte 1 ==
5407 12:21:02.368665 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5408 12:21:02.372036 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5409 12:21:02.372558 ==
5410 12:21:02.375266 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 12:21:02.378441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 12:21:02.378967 ==
5413 12:21:02.379297
5414 12:21:02.379603
5415 12:21:02.381502 TX Vref Scan disable
5416 12:21:02.384697 == TX Byte 0 ==
5417 12:21:02.387989 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5418 12:21:02.391485 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5419 12:21:02.394664 == TX Byte 1 ==
5420 12:21:02.397994 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5421 12:21:02.401888 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5422 12:21:02.402409
5423 12:21:02.404470 [DATLAT]
5424 12:21:02.404883 Freq=933, CH0 RK1
5425 12:21:02.405213
5426 12:21:02.407590 DATLAT Default: 0xb
5427 12:21:02.408057 0, 0xFFFF, sum = 0
5428 12:21:02.410804 1, 0xFFFF, sum = 0
5429 12:21:02.411283 2, 0xFFFF, sum = 0
5430 12:21:02.414188 3, 0xFFFF, sum = 0
5431 12:21:02.414611 4, 0xFFFF, sum = 0
5432 12:21:02.417454 5, 0xFFFF, sum = 0
5433 12:21:02.417876 6, 0xFFFF, sum = 0
5434 12:21:02.420833 7, 0xFFFF, sum = 0
5435 12:21:02.424161 8, 0xFFFF, sum = 0
5436 12:21:02.424583 9, 0xFFFF, sum = 0
5437 12:21:02.424919 10, 0x0, sum = 1
5438 12:21:02.427247 11, 0x0, sum = 2
5439 12:21:02.427667 12, 0x0, sum = 3
5440 12:21:02.430781 13, 0x0, sum = 4
5441 12:21:02.431205 best_step = 11
5442 12:21:02.431535
5443 12:21:02.431840 ==
5444 12:21:02.433836 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 12:21:02.440774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 12:21:02.441191 ==
5447 12:21:02.441519 RX Vref Scan: 0
5448 12:21:02.441828
5449 12:21:02.444395 RX Vref 0 -> 0, step: 1
5450 12:21:02.444811
5451 12:21:02.447511 RX Delay -61 -> 252, step: 4
5452 12:21:02.450756 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5453 12:21:02.457043 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5454 12:21:02.460351 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5455 12:21:02.463630 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5456 12:21:02.467386 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5457 12:21:02.470548 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5458 12:21:02.473678 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5459 12:21:02.480423 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5460 12:21:02.483750 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5461 12:21:02.486621 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5462 12:21:02.490388 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5463 12:21:02.493274 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5464 12:21:02.500261 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5465 12:21:02.503398 iDelay=195, Bit 13, Center 94 (7 ~ 182) 176
5466 12:21:02.506341 iDelay=195, Bit 14, Center 102 (15 ~ 190) 176
5467 12:21:02.510119 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5468 12:21:02.510644 ==
5469 12:21:02.513359 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 12:21:02.519859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 12:21:02.520309 ==
5472 12:21:02.520637 DQS Delay:
5473 12:21:02.523449 DQS0 = 0, DQS1 = 0
5474 12:21:02.524035 DQM Delay:
5475 12:21:02.524375 DQM0 = 97, DQM1 = 88
5476 12:21:02.526138 DQ Delay:
5477 12:21:02.529975 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5478 12:21:02.532507 DQ4 =102, DQ5 =86, DQ6 =106, DQ7 =104
5479 12:21:02.536586 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5480 12:21:02.539616 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =94
5481 12:21:02.540183
5482 12:21:02.540517
5483 12:21:02.545963 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5484 12:21:02.549264 CH0 RK1: MR19=505, MR18=1512
5485 12:21:02.556092 CH0_RK1: MR19=0x505, MR18=0x1512, DQSOSC=415, MR23=63, INC=62, DEC=41
5486 12:21:02.559239 [RxdqsGatingPostProcess] freq 933
5487 12:21:02.566276 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5488 12:21:02.566849 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 12:21:02.568878 best DQS1 dly(2T, 0.5T) = (0, 11)
5490 12:21:02.572337 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 12:21:02.575715 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5492 12:21:02.578644 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 12:21:02.582069 best DQS1 dly(2T, 0.5T) = (0, 10)
5494 12:21:02.585230 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 12:21:02.588690 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5496 12:21:02.592071 Pre-setting of DQS Precalculation
5497 12:21:02.598650 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5498 12:21:02.599194 ==
5499 12:21:02.602015 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 12:21:02.604749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 12:21:02.605210 ==
5502 12:21:02.612326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5503 12:21:02.618185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5504 12:21:02.621609 [CA 0] Center 36 (6~67) winsize 62
5505 12:21:02.624667 [CA 1] Center 36 (6~67) winsize 62
5506 12:21:02.627944 [CA 2] Center 35 (5~65) winsize 61
5507 12:21:02.631425 [CA 3] Center 34 (4~64) winsize 61
5508 12:21:02.634503 [CA 4] Center 34 (4~65) winsize 62
5509 12:21:02.634916 [CA 5] Center 33 (3~64) winsize 62
5510 12:21:02.638579
5511 12:21:02.641312 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5512 12:21:02.641729
5513 12:21:02.644558 [CATrainingPosCal] consider 1 rank data
5514 12:21:02.648202 u2DelayCellTimex100 = 270/100 ps
5515 12:21:02.651112 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5516 12:21:02.654291 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5517 12:21:02.657623 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5518 12:21:02.660693 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5519 12:21:02.664100 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5520 12:21:02.667119 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5521 12:21:02.667299
5522 12:21:02.673627 CA PerBit enable=1, Macro0, CA PI delay=33
5523 12:21:02.673778
5524 12:21:02.673897 [CBTSetCACLKResult] CA Dly = 33
5525 12:21:02.677256 CS Dly: 6 (0~37)
5526 12:21:02.677387 ==
5527 12:21:02.680606 Dram Type= 6, Freq= 0, CH_1, rank 1
5528 12:21:02.683418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 12:21:02.683538 ==
5530 12:21:02.690135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 12:21:02.697179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 12:21:02.700158 [CA 0] Center 36 (6~67) winsize 62
5533 12:21:02.703290 [CA 1] Center 36 (6~67) winsize 62
5534 12:21:02.706502 [CA 2] Center 34 (4~65) winsize 62
5535 12:21:02.709922 [CA 3] Center 33 (3~64) winsize 62
5536 12:21:02.713162 [CA 4] Center 34 (4~65) winsize 62
5537 12:21:02.716229 [CA 5] Center 33 (3~64) winsize 62
5538 12:21:02.716311
5539 12:21:02.719784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 12:21:02.719914
5541 12:21:02.722913 [CATrainingPosCal] consider 2 rank data
5542 12:21:02.726355 u2DelayCellTimex100 = 270/100 ps
5543 12:21:02.729464 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5544 12:21:02.732768 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5545 12:21:02.736457 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5546 12:21:02.739555 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5547 12:21:02.746451 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5548 12:21:02.749686 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5549 12:21:02.749768
5550 12:21:02.752550 CA PerBit enable=1, Macro0, CA PI delay=33
5551 12:21:02.752633
5552 12:21:02.756302 [CBTSetCACLKResult] CA Dly = 33
5553 12:21:02.756384 CS Dly: 7 (0~39)
5554 12:21:02.756448
5555 12:21:02.759473 ----->DramcWriteLeveling(PI) begin...
5556 12:21:02.759556 ==
5557 12:21:02.762670 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 12:21:02.769264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 12:21:02.769348 ==
5560 12:21:02.772416 Write leveling (Byte 0): 23 => 23
5561 12:21:02.775707 Write leveling (Byte 1): 28 => 28
5562 12:21:02.775797 DramcWriteLeveling(PI) end<-----
5563 12:21:02.779417
5564 12:21:02.779504 ==
5565 12:21:02.782415 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 12:21:02.785436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 12:21:02.785527 ==
5568 12:21:02.788714 [Gating] SW mode calibration
5569 12:21:02.795570 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5570 12:21:02.798789 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5571 12:21:02.805521 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 12:21:02.809055 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 12:21:02.812147 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 12:21:02.818751 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 12:21:02.822183 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 12:21:02.828775 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 12:21:02.831962 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5578 12:21:02.835332 0 14 28 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
5579 12:21:02.841776 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 12:21:02.845389 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 12:21:02.848286 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 12:21:02.855092 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 12:21:02.857950 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 12:21:02.861234 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 12:21:02.867807 0 15 24 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
5586 12:21:02.871171 0 15 28 | B1->B0 | 3636 4242 | 0 0 | (0 0) (0 0)
5587 12:21:02.874792 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:21:02.881250 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 12:21:02.884901 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 12:21:02.887671 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:21:02.894226 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:21:02.897498 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 12:21:02.901267 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5594 12:21:02.907788 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5595 12:21:02.910821 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5596 12:21:02.914752 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:21:02.921302 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:21:02.924396 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:21:02.927550 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:21:02.934231 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:21:02.937229 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:21:02.940829 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:21:02.947660 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:21:02.950890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:21:02.953870 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:21:02.960448 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:21:02.964132 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:21:02.966946 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:21:02.973428 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:21:02.976986 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5611 12:21:02.979942 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 12:21:02.983276 Total UI for P1: 0, mck2ui 16
5613 12:21:02.986154 best dqsien dly found for B0: ( 1, 2, 28)
5614 12:21:02.989373 Total UI for P1: 0, mck2ui 16
5615 12:21:02.993395 best dqsien dly found for B1: ( 1, 2, 28)
5616 12:21:02.996765 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5617 12:21:02.999771 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5618 12:21:03.000225
5619 12:21:03.006438 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5620 12:21:03.009786 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5621 12:21:03.010201 [Gating] SW calibration Done
5622 12:21:03.012996 ==
5623 12:21:03.016063 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 12:21:03.019676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 12:21:03.020136 ==
5626 12:21:03.020470 RX Vref Scan: 0
5627 12:21:03.020778
5628 12:21:03.022883 RX Vref 0 -> 0, step: 1
5629 12:21:03.023322
5630 12:21:03.026456 RX Delay -80 -> 252, step: 8
5631 12:21:03.029864 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5632 12:21:03.032976 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5633 12:21:03.039217 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5634 12:21:03.042993 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5635 12:21:03.046018 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5636 12:21:03.049408 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5637 12:21:03.052480 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5638 12:21:03.056078 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5639 12:21:03.062097 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5640 12:21:03.065254 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5641 12:21:03.068700 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5642 12:21:03.071622 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5643 12:21:03.075669 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5644 12:21:03.078613 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5645 12:21:03.085077 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5646 12:21:03.088191 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5647 12:21:03.088272 ==
5648 12:21:03.091412 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 12:21:03.095020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 12:21:03.095102 ==
5651 12:21:03.097996 DQS Delay:
5652 12:21:03.098076 DQS0 = 0, DQS1 = 0
5653 12:21:03.098140 DQM Delay:
5654 12:21:03.101896 DQM0 = 98, DQM1 = 93
5655 12:21:03.102068 DQ Delay:
5656 12:21:03.105331 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5657 12:21:03.107946 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5658 12:21:03.111668 DQ8 =79, DQ9 =87, DQ10 =91, DQ11 =87
5659 12:21:03.114994 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5660 12:21:03.115151
5661 12:21:03.115244
5662 12:21:03.117891 ==
5663 12:21:03.121497 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 12:21:03.124397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 12:21:03.124518 ==
5666 12:21:03.124614
5667 12:21:03.124703
5668 12:21:03.127614 TX Vref Scan disable
5669 12:21:03.127748 == TX Byte 0 ==
5670 12:21:03.134328 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5671 12:21:03.138292 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5672 12:21:03.138463 == TX Byte 1 ==
5673 12:21:03.144560 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5674 12:21:03.147632 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5675 12:21:03.147880 ==
5676 12:21:03.151011 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 12:21:03.154689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 12:21:03.155089 ==
5679 12:21:03.155336
5680 12:21:03.155554
5681 12:21:03.157886 TX Vref Scan disable
5682 12:21:03.161647 == TX Byte 0 ==
5683 12:21:03.164906 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5684 12:21:03.167647 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5685 12:21:03.171371 == TX Byte 1 ==
5686 12:21:03.174593 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5687 12:21:03.177646 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5688 12:21:03.178167
5689 12:21:03.181282 [DATLAT]
5690 12:21:03.181857 Freq=933, CH1 RK0
5691 12:21:03.182224
5692 12:21:03.183975 DATLAT Default: 0xd
5693 12:21:03.184439 0, 0xFFFF, sum = 0
5694 12:21:03.187671 1, 0xFFFF, sum = 0
5695 12:21:03.188215 2, 0xFFFF, sum = 0
5696 12:21:03.190994 3, 0xFFFF, sum = 0
5697 12:21:03.191413 4, 0xFFFF, sum = 0
5698 12:21:03.194100 5, 0xFFFF, sum = 0
5699 12:21:03.194647 6, 0xFFFF, sum = 0
5700 12:21:03.197498 7, 0xFFFF, sum = 0
5701 12:21:03.198080 8, 0xFFFF, sum = 0
5702 12:21:03.200775 9, 0xFFFF, sum = 0
5703 12:21:03.201193 10, 0x0, sum = 1
5704 12:21:03.203779 11, 0x0, sum = 2
5705 12:21:03.204258 12, 0x0, sum = 3
5706 12:21:03.207089 13, 0x0, sum = 4
5707 12:21:03.207509 best_step = 11
5708 12:21:03.207835
5709 12:21:03.208235 ==
5710 12:21:03.210692 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 12:21:03.217182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 12:21:03.217744 ==
5713 12:21:03.218090 RX Vref Scan: 1
5714 12:21:03.218399
5715 12:21:03.220462 RX Vref 0 -> 0, step: 1
5716 12:21:03.220880
5717 12:21:03.223455 RX Delay -61 -> 252, step: 4
5718 12:21:03.223870
5719 12:21:03.226821 Set Vref, RX VrefLevel [Byte0]: 51
5720 12:21:03.230309 [Byte1]: 50
5721 12:21:03.230838
5722 12:21:03.233427 Final RX Vref Byte 0 = 51 to rank0
5723 12:21:03.237254 Final RX Vref Byte 1 = 50 to rank0
5724 12:21:03.240493 Final RX Vref Byte 0 = 51 to rank1
5725 12:21:03.244348 Final RX Vref Byte 1 = 50 to rank1==
5726 12:21:03.246535 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 12:21:03.250108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 12:21:03.254189 ==
5729 12:21:03.254719 DQS Delay:
5730 12:21:03.255054 DQS0 = 0, DQS1 = 0
5731 12:21:03.256643 DQM Delay:
5732 12:21:03.257058 DQM0 = 96, DQM1 = 93
5733 12:21:03.260186 DQ Delay:
5734 12:21:03.260597 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5735 12:21:03.263754 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =92
5736 12:21:03.267035 DQ8 =76, DQ9 =84, DQ10 =94, DQ11 =86
5737 12:21:03.273049 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5738 12:21:03.273573
5739 12:21:03.273912
5740 12:21:03.279969 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5741 12:21:03.283204 CH1 RK0: MR19=505, MR18=919
5742 12:21:03.289823 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5743 12:21:03.290346
5744 12:21:03.293595 ----->DramcWriteLeveling(PI) begin...
5745 12:21:03.294121 ==
5746 12:21:03.296244 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 12:21:03.299475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 12:21:03.299894 ==
5749 12:21:03.303279 Write leveling (Byte 0): 26 => 26
5750 12:21:03.306239 Write leveling (Byte 1): 27 => 27
5751 12:21:03.309781 DramcWriteLeveling(PI) end<-----
5752 12:21:03.310304
5753 12:21:03.310636 ==
5754 12:21:03.313234 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 12:21:03.316429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 12:21:03.316849 ==
5757 12:21:03.319401 [Gating] SW mode calibration
5758 12:21:03.325725 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5759 12:21:03.332409 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5760 12:21:03.335431 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 12:21:03.342040 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 12:21:03.345525 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 12:21:03.348642 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 12:21:03.355135 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 12:21:03.358962 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 12:21:03.362443 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5767 12:21:03.369342 0 14 28 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
5768 12:21:03.371621 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 12:21:03.375732 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 12:21:03.381638 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 12:21:03.385015 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 12:21:03.388283 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 12:21:03.395281 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 12:21:03.398440 0 15 24 | B1->B0 | 2b2b 3636 | 0 0 | (0 0) (0 0)
5775 12:21:03.401772 0 15 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5776 12:21:03.408099 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 12:21:03.411831 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 12:21:03.414900 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 12:21:03.420921 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 12:21:03.424256 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 12:21:03.428497 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 12:21:03.434198 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5783 12:21:03.437569 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5784 12:21:03.440712 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:21:03.447077 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:21:03.450819 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:21:03.453907 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:21:03.460357 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:21:03.463575 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:21:03.466952 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:21:03.473983 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:21:03.477147 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:21:03.480266 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:21:03.486726 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:21:03.490288 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:21:03.493290 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:21:03.501118 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:21:03.503209 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5799 12:21:03.509759 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5800 12:21:03.510256 Total UI for P1: 0, mck2ui 16
5801 12:21:03.513499 best dqsien dly found for B0: ( 1, 2, 24)
5802 12:21:03.519604 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 12:21:03.522927 Total UI for P1: 0, mck2ui 16
5804 12:21:03.526416 best dqsien dly found for B1: ( 1, 2, 28)
5805 12:21:03.529816 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5806 12:21:03.534060 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5807 12:21:03.534774
5808 12:21:03.535975 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5809 12:21:03.539570 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5810 12:21:03.542789 [Gating] SW calibration Done
5811 12:21:03.543381 ==
5812 12:21:03.546004 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 12:21:03.549291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 12:21:03.552896 ==
5815 12:21:03.553417 RX Vref Scan: 0
5816 12:21:03.553753
5817 12:21:03.556260 RX Vref 0 -> 0, step: 1
5818 12:21:03.556683
5819 12:21:03.559074 RX Delay -80 -> 252, step: 8
5820 12:21:03.562748 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5821 12:21:03.565553 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5822 12:21:03.569395 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5823 12:21:03.571963 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5824 12:21:03.576016 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5825 12:21:03.581910 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5826 12:21:03.585663 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5827 12:21:03.588626 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5828 12:21:03.592565 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5829 12:21:03.595319 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5830 12:21:03.602315 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5831 12:21:03.605263 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5832 12:21:03.608914 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5833 12:21:03.611638 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5834 12:21:03.615537 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5835 12:21:03.621796 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5836 12:21:03.622339 ==
5837 12:21:03.625009 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 12:21:03.628136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 12:21:03.628692 ==
5840 12:21:03.629056 DQS Delay:
5841 12:21:03.631494 DQS0 = 0, DQS1 = 0
5842 12:21:03.632095 DQM Delay:
5843 12:21:03.634872 DQM0 = 96, DQM1 = 93
5844 12:21:03.635325 DQ Delay:
5845 12:21:03.638036 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5846 12:21:03.641827 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5847 12:21:03.644528 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5848 12:21:03.648383 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5849 12:21:03.648940
5850 12:21:03.649306
5851 12:21:03.649639 ==
5852 12:21:03.651490 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 12:21:03.654635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 12:21:03.658136 ==
5855 12:21:03.658684
5856 12:21:03.659042
5857 12:21:03.659380 TX Vref Scan disable
5858 12:21:03.661818 == TX Byte 0 ==
5859 12:21:03.664694 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5860 12:21:03.667860 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5861 12:21:03.671426 == TX Byte 1 ==
5862 12:21:03.674124 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 12:21:03.678181 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 12:21:03.680718 ==
5865 12:21:03.684025 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 12:21:03.687496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 12:21:03.688015 ==
5868 12:21:03.688493
5869 12:21:03.688845
5870 12:21:03.690885 TX Vref Scan disable
5871 12:21:03.691444 == TX Byte 0 ==
5872 12:21:03.697154 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5873 12:21:03.701282 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5874 12:21:03.701850 == TX Byte 1 ==
5875 12:21:03.707464 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5876 12:21:03.710578 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5877 12:21:03.711150
5878 12:21:03.711521 [DATLAT]
5879 12:21:03.713798 Freq=933, CH1 RK1
5880 12:21:03.714363
5881 12:21:03.714733 DATLAT Default: 0xb
5882 12:21:03.717017 0, 0xFFFF, sum = 0
5883 12:21:03.717489 1, 0xFFFF, sum = 0
5884 12:21:03.720480 2, 0xFFFF, sum = 0
5885 12:21:03.723317 3, 0xFFFF, sum = 0
5886 12:21:03.723747 4, 0xFFFF, sum = 0
5887 12:21:03.726555 5, 0xFFFF, sum = 0
5888 12:21:03.726980 6, 0xFFFF, sum = 0
5889 12:21:03.729818 7, 0xFFFF, sum = 0
5890 12:21:03.730244 8, 0xFFFF, sum = 0
5891 12:21:03.733265 9, 0xFFFF, sum = 0
5892 12:21:03.733736 10, 0x0, sum = 1
5893 12:21:03.736414 11, 0x0, sum = 2
5894 12:21:03.736838 12, 0x0, sum = 3
5895 12:21:03.740241 13, 0x0, sum = 4
5896 12:21:03.740670 best_step = 11
5897 12:21:03.741003
5898 12:21:03.741312 ==
5899 12:21:03.742851 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 12:21:03.746131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 12:21:03.749738 ==
5902 12:21:03.750157 RX Vref Scan: 0
5903 12:21:03.750489
5904 12:21:03.755215 RX Vref 0 -> 0, step: 1
5905 12:21:03.755638
5906 12:21:03.756313 RX Delay -61 -> 252, step: 4
5907 12:21:03.759401 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5908 12:21:03.763100 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5909 12:21:03.769524 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5910 12:21:03.772563 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5911 12:21:03.775945 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5912 12:21:03.779167 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5913 12:21:03.782761 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5914 12:21:03.785568 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5915 12:21:03.792588 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5916 12:21:03.795878 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5917 12:21:03.799128 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5918 12:21:03.802240 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5919 12:21:03.805713 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5920 12:21:03.812118 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5921 12:21:03.815137 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5922 12:21:03.819311 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5923 12:21:03.819935 ==
5924 12:21:03.822124 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 12:21:03.825427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 12:21:03.828232 ==
5927 12:21:03.828653 DQS Delay:
5928 12:21:03.829043 DQS0 = 0, DQS1 = 0
5929 12:21:03.831871 DQM Delay:
5930 12:21:03.832341 DQM0 = 96, DQM1 = 92
5931 12:21:03.834910 DQ Delay:
5932 12:21:03.838240 DQ0 =102, DQ1 =94, DQ2 =84, DQ3 =94
5933 12:21:03.841518 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =92
5934 12:21:03.844925 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5935 12:21:03.848110 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
5936 12:21:03.848584
5937 12:21:03.848994
5938 12:21:03.854725 [DQSOSCAuto] RK1, (LSB)MR18= 0xa21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5939 12:21:03.858049 CH1 RK1: MR19=505, MR18=A21
5940 12:21:03.864368 CH1_RK1: MR19=0x505, MR18=0xA21, DQSOSC=411, MR23=63, INC=64, DEC=42
5941 12:21:03.867894 [RxdqsGatingPostProcess] freq 933
5942 12:21:03.871036 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5943 12:21:03.874642 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 12:21:03.878157 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 12:21:03.881355 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 12:21:03.884307 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 12:21:03.887827 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 12:21:03.890965 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 12:21:03.894268 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 12:21:03.897301 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 12:21:03.901418 Pre-setting of DQS Precalculation
5952 12:21:03.907122 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5953 12:21:03.913764 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5954 12:21:03.920123 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5955 12:21:03.920546
5956 12:21:03.920875
5957 12:21:03.923877 [Calibration Summary] 1866 Mbps
5958 12:21:03.924349 CH 0, Rank 0
5959 12:21:03.927067 SW Impedance : PASS
5960 12:21:03.930588 DUTY Scan : NO K
5961 12:21:03.931009 ZQ Calibration : PASS
5962 12:21:03.933807 Jitter Meter : NO K
5963 12:21:03.936911 CBT Training : PASS
5964 12:21:03.937330 Write leveling : PASS
5965 12:21:03.940158 RX DQS gating : PASS
5966 12:21:03.943783 RX DQ/DQS(RDDQC) : PASS
5967 12:21:03.944278 TX DQ/DQS : PASS
5968 12:21:03.946919 RX DATLAT : PASS
5969 12:21:03.947337 RX DQ/DQS(Engine): PASS
5970 12:21:03.949941 TX OE : NO K
5971 12:21:03.950365 All Pass.
5972 12:21:03.950697
5973 12:21:03.954043 CH 0, Rank 1
5974 12:21:03.956698 SW Impedance : PASS
5975 12:21:03.957121 DUTY Scan : NO K
5976 12:21:03.960022 ZQ Calibration : PASS
5977 12:21:03.960442 Jitter Meter : NO K
5978 12:21:03.963358 CBT Training : PASS
5979 12:21:03.966682 Write leveling : PASS
5980 12:21:03.967100 RX DQS gating : PASS
5981 12:21:03.969853 RX DQ/DQS(RDDQC) : PASS
5982 12:21:03.973155 TX DQ/DQS : PASS
5983 12:21:03.973638 RX DATLAT : PASS
5984 12:21:03.977426 RX DQ/DQS(Engine): PASS
5985 12:21:03.979445 TX OE : NO K
5986 12:21:03.979884 All Pass.
5987 12:21:03.980254
5988 12:21:03.980568 CH 1, Rank 0
5989 12:21:03.983060 SW Impedance : PASS
5990 12:21:03.986528 DUTY Scan : NO K
5991 12:21:03.986962 ZQ Calibration : PASS
5992 12:21:03.989424 Jitter Meter : NO K
5993 12:21:03.992908 CBT Training : PASS
5994 12:21:03.993517 Write leveling : PASS
5995 12:21:03.995858 RX DQS gating : PASS
5996 12:21:03.998999 RX DQ/DQS(RDDQC) : PASS
5997 12:21:03.999601 TX DQ/DQS : PASS
5998 12:21:04.002534 RX DATLAT : PASS
5999 12:21:04.005799 RX DQ/DQS(Engine): PASS
6000 12:21:04.006361 TX OE : NO K
6001 12:21:04.009727 All Pass.
6002 12:21:04.010301
6003 12:21:04.010894 CH 1, Rank 1
6004 12:21:04.012680 SW Impedance : PASS
6005 12:21:04.013256 DUTY Scan : NO K
6006 12:21:04.015859 ZQ Calibration : PASS
6007 12:21:04.019645 Jitter Meter : NO K
6008 12:21:04.020280 CBT Training : PASS
6009 12:21:04.022718 Write leveling : PASS
6010 12:21:04.025748 RX DQS gating : PASS
6011 12:21:04.026380 RX DQ/DQS(RDDQC) : PASS
6012 12:21:04.029139 TX DQ/DQS : PASS
6013 12:21:04.032205 RX DATLAT : PASS
6014 12:21:04.032745 RX DQ/DQS(Engine): PASS
6015 12:21:04.036025 TX OE : NO K
6016 12:21:04.036531 All Pass.
6017 12:21:04.036945
6018 12:21:04.038986 DramC Write-DBI off
6019 12:21:04.042007 PER_BANK_REFRESH: Hybrid Mode
6020 12:21:04.042650 TX_TRACKING: ON
6021 12:21:04.052327 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6022 12:21:04.055332 [FAST_K] Save calibration result to emmc
6023 12:21:04.058441 dramc_set_vcore_voltage set vcore to 650000
6024 12:21:04.061397 Read voltage for 400, 6
6025 12:21:04.061489 Vio18 = 0
6026 12:21:04.061559 Vcore = 650000
6027 12:21:04.064889 Vdram = 0
6028 12:21:04.064971 Vddq = 0
6029 12:21:04.065035 Vmddr = 0
6030 12:21:04.071810 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6031 12:21:04.074909 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6032 12:21:04.078394 MEM_TYPE=3, freq_sel=20
6033 12:21:04.081576 sv_algorithm_assistance_LP4_800
6034 12:21:04.084737 ============ PULL DRAM RESETB DOWN ============
6035 12:21:04.087749 ========== PULL DRAM RESETB DOWN end =========
6036 12:21:04.094329 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6037 12:21:04.097899 ===================================
6038 12:21:04.100802 LPDDR4 DRAM CONFIGURATION
6039 12:21:04.104320 ===================================
6040 12:21:04.104394 EX_ROW_EN[0] = 0x0
6041 12:21:04.107511 EX_ROW_EN[1] = 0x0
6042 12:21:04.107609 LP4Y_EN = 0x0
6043 12:21:04.111003 WORK_FSP = 0x0
6044 12:21:04.111076 WL = 0x2
6045 12:21:04.114071 RL = 0x2
6046 12:21:04.114145 BL = 0x2
6047 12:21:04.117481 RPST = 0x0
6048 12:21:04.117550 RD_PRE = 0x0
6049 12:21:04.120630 WR_PRE = 0x1
6050 12:21:04.120699 WR_PST = 0x0
6051 12:21:04.124313 DBI_WR = 0x0
6052 12:21:04.124395 DBI_RD = 0x0
6053 12:21:04.127425 OTF = 0x1
6054 12:21:04.130683 ===================================
6055 12:21:04.133867 ===================================
6056 12:21:04.133941 ANA top config
6057 12:21:04.137131 ===================================
6058 12:21:04.140642 DLL_ASYNC_EN = 0
6059 12:21:04.143800 ALL_SLAVE_EN = 1
6060 12:21:04.147447 NEW_RANK_MODE = 1
6061 12:21:04.150373 DLL_IDLE_MODE = 1
6062 12:21:04.150482 LP45_APHY_COMB_EN = 1
6063 12:21:04.153527 TX_ODT_DIS = 1
6064 12:21:04.156765 NEW_8X_MODE = 1
6065 12:21:04.160019 ===================================
6066 12:21:04.163705 ===================================
6067 12:21:04.166884 data_rate = 800
6068 12:21:04.170009 CKR = 1
6069 12:21:04.173928 DQ_P2S_RATIO = 4
6070 12:21:04.176587 ===================================
6071 12:21:04.176669 CA_P2S_RATIO = 4
6072 12:21:04.180165 DQ_CA_OPEN = 0
6073 12:21:04.183224 DQ_SEMI_OPEN = 1
6074 12:21:04.186641 CA_SEMI_OPEN = 1
6075 12:21:04.190161 CA_FULL_RATE = 0
6076 12:21:04.190239 DQ_CKDIV4_EN = 0
6077 12:21:04.193529 CA_CKDIV4_EN = 1
6078 12:21:04.196441 CA_PREDIV_EN = 0
6079 12:21:04.199794 PH8_DLY = 0
6080 12:21:04.203462 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6081 12:21:04.206373 DQ_AAMCK_DIV = 0
6082 12:21:04.209731 CA_AAMCK_DIV = 0
6083 12:21:04.209812 CA_ADMCK_DIV = 4
6084 12:21:04.213039 DQ_TRACK_CA_EN = 0
6085 12:21:04.216449 CA_PICK = 800
6086 12:21:04.219901 CA_MCKIO = 400
6087 12:21:04.222812 MCKIO_SEMI = 400
6088 12:21:04.226426 PLL_FREQ = 3016
6089 12:21:04.229306 DQ_UI_PI_RATIO = 32
6090 12:21:04.232785 CA_UI_PI_RATIO = 32
6091 12:21:04.236095 ===================================
6092 12:21:04.239083 ===================================
6093 12:21:04.239165 memory_type:LPDDR4
6094 12:21:04.242788 GP_NUM : 10
6095 12:21:04.245861 SRAM_EN : 1
6096 12:21:04.245943 MD32_EN : 0
6097 12:21:04.249034 ===================================
6098 12:21:04.252430 [ANA_INIT] >>>>>>>>>>>>>>
6099 12:21:04.255499 <<<<<< [CONFIGURE PHASE]: ANA_TX
6100 12:21:04.258732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6101 12:21:04.262101 ===================================
6102 12:21:04.265725 data_rate = 800,PCW = 0X7400
6103 12:21:04.269098 ===================================
6104 12:21:04.272432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6105 12:21:04.276065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 12:21:04.289134 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 12:21:04.291813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6108 12:21:04.294814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6109 12:21:04.298431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6110 12:21:04.301786 [ANA_INIT] flow start
6111 12:21:04.305871 [ANA_INIT] PLL >>>>>>>>
6112 12:21:04.305953 [ANA_INIT] PLL <<<<<<<<
6113 12:21:04.308586 [ANA_INIT] MIDPI >>>>>>>>
6114 12:21:04.311345 [ANA_INIT] MIDPI <<<<<<<<
6115 12:21:04.311426 [ANA_INIT] DLL >>>>>>>>
6116 12:21:04.314941 [ANA_INIT] flow end
6117 12:21:04.318360 ============ LP4 DIFF to SE enter ============
6118 12:21:04.324719 ============ LP4 DIFF to SE exit ============
6119 12:21:04.324801 [ANA_INIT] <<<<<<<<<<<<<
6120 12:21:04.328251 [Flow] Enable top DCM control >>>>>
6121 12:21:04.331227 [Flow] Enable top DCM control <<<<<
6122 12:21:04.334263 Enable DLL master slave shuffle
6123 12:21:04.341004 ==============================================================
6124 12:21:04.341085 Gating Mode config
6125 12:21:04.347461 ==============================================================
6126 12:21:04.350912 Config description:
6127 12:21:04.360888 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6128 12:21:04.367377 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6129 12:21:04.370362 SELPH_MODE 0: By rank 1: By Phase
6130 12:21:04.377100 ==============================================================
6131 12:21:04.380487 GAT_TRACK_EN = 0
6132 12:21:04.384204 RX_GATING_MODE = 2
6133 12:21:04.384286 RX_GATING_TRACK_MODE = 2
6134 12:21:04.387508 SELPH_MODE = 1
6135 12:21:04.390326 PICG_EARLY_EN = 1
6136 12:21:04.393688 VALID_LAT_VALUE = 1
6137 12:21:04.400064 ==============================================================
6138 12:21:04.403716 Enter into Gating configuration >>>>
6139 12:21:04.407100 Exit from Gating configuration <<<<
6140 12:21:04.410485 Enter into DVFS_PRE_config >>>>>
6141 12:21:04.420088 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6142 12:21:04.423335 Exit from DVFS_PRE_config <<<<<
6143 12:21:04.426453 Enter into PICG configuration >>>>
6144 12:21:04.430033 Exit from PICG configuration <<<<
6145 12:21:04.432896 [RX_INPUT] configuration >>>>>
6146 12:21:04.436454 [RX_INPUT] configuration <<<<<
6147 12:21:04.439742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6148 12:21:04.446525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6149 12:21:04.453058 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6150 12:21:04.459817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6151 12:21:04.465816 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 12:21:04.472864 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 12:21:04.476068 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6154 12:21:04.479232 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6155 12:21:04.482700 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6156 12:21:04.489284 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6157 12:21:04.492225 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6158 12:21:04.495441 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 12:21:04.499147 ===================================
6160 12:21:04.502432 LPDDR4 DRAM CONFIGURATION
6161 12:21:04.505753 ===================================
6162 12:21:04.505835 EX_ROW_EN[0] = 0x0
6163 12:21:04.508901 EX_ROW_EN[1] = 0x0
6164 12:21:04.511870 LP4Y_EN = 0x0
6165 12:21:04.511992 WORK_FSP = 0x0
6166 12:21:04.515423 WL = 0x2
6167 12:21:04.515544 RL = 0x2
6168 12:21:04.518643 BL = 0x2
6169 12:21:04.518724 RPST = 0x0
6170 12:21:04.522488 RD_PRE = 0x0
6171 12:21:04.522569 WR_PRE = 0x1
6172 12:21:04.525098 WR_PST = 0x0
6173 12:21:04.525180 DBI_WR = 0x0
6174 12:21:04.528384 DBI_RD = 0x0
6175 12:21:04.528465 OTF = 0x1
6176 12:21:04.531804 ===================================
6177 12:21:04.535506 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6178 12:21:04.541638 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6179 12:21:04.544810 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 12:21:04.548350 ===================================
6181 12:21:04.551847 LPDDR4 DRAM CONFIGURATION
6182 12:21:04.555141 ===================================
6183 12:21:04.555223 EX_ROW_EN[0] = 0x10
6184 12:21:04.558379 EX_ROW_EN[1] = 0x0
6185 12:21:04.561566 LP4Y_EN = 0x0
6186 12:21:04.561638 WORK_FSP = 0x0
6187 12:21:04.564691 WL = 0x2
6188 12:21:04.564772 RL = 0x2
6189 12:21:04.568003 BL = 0x2
6190 12:21:04.568085 RPST = 0x0
6191 12:21:04.571456 RD_PRE = 0x0
6192 12:21:04.571537 WR_PRE = 0x1
6193 12:21:04.574499 WR_PST = 0x0
6194 12:21:04.574580 DBI_WR = 0x0
6195 12:21:04.577769 DBI_RD = 0x0
6196 12:21:04.577851 OTF = 0x1
6197 12:21:04.581368 ===================================
6198 12:21:04.587637 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6199 12:21:04.592345 nWR fixed to 30
6200 12:21:04.595668 [ModeRegInit_LP4] CH0 RK0
6201 12:21:04.595775 [ModeRegInit_LP4] CH0 RK1
6202 12:21:04.598933 [ModeRegInit_LP4] CH1 RK0
6203 12:21:04.602182 [ModeRegInit_LP4] CH1 RK1
6204 12:21:04.602264 match AC timing 19
6205 12:21:04.608512 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6206 12:21:04.612498 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6207 12:21:04.615174 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6208 12:21:04.622105 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6209 12:21:04.625260 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6210 12:21:04.625342 ==
6211 12:21:04.628145 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 12:21:04.631782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6213 12:21:04.631863 ==
6214 12:21:04.638363 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6215 12:21:04.644631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6216 12:21:04.648172 [CA 0] Center 36 (8~64) winsize 57
6217 12:21:04.651272 [CA 1] Center 36 (8~64) winsize 57
6218 12:21:04.655037 [CA 2] Center 36 (8~64) winsize 57
6219 12:21:04.658079 [CA 3] Center 36 (8~64) winsize 57
6220 12:21:04.661259 [CA 4] Center 36 (8~64) winsize 57
6221 12:21:04.664543 [CA 5] Center 36 (8~64) winsize 57
6222 12:21:04.664625
6223 12:21:04.668244 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6224 12:21:04.668326
6225 12:21:04.671065 [CATrainingPosCal] consider 1 rank data
6226 12:21:04.674775 u2DelayCellTimex100 = 270/100 ps
6227 12:21:04.677855 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 12:21:04.681344 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 12:21:04.684231 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 12:21:04.687531 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:21:04.690961 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:21:04.694043 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:21:04.694164
6234 12:21:04.700789 CA PerBit enable=1, Macro0, CA PI delay=36
6235 12:21:04.700871
6236 12:21:04.700936 [CBTSetCACLKResult] CA Dly = 36
6237 12:21:04.704341 CS Dly: 1 (0~32)
6238 12:21:04.704423 ==
6239 12:21:04.707652 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 12:21:04.710792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 12:21:04.710874 ==
6242 12:21:04.717422 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 12:21:04.724009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6244 12:21:04.727567 [CA 0] Center 36 (8~64) winsize 57
6245 12:21:04.730710 [CA 1] Center 36 (8~64) winsize 57
6246 12:21:04.733908 [CA 2] Center 36 (8~64) winsize 57
6247 12:21:04.737051 [CA 3] Center 36 (8~64) winsize 57
6248 12:21:04.740236 [CA 4] Center 36 (8~64) winsize 57
6249 12:21:04.740318 [CA 5] Center 36 (8~64) winsize 57
6250 12:21:04.743844
6251 12:21:04.746776 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6252 12:21:04.746860
6253 12:21:04.750156 [CATrainingPosCal] consider 2 rank data
6254 12:21:04.754779 u2DelayCellTimex100 = 270/100 ps
6255 12:21:04.757249 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 12:21:04.760074 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 12:21:04.763521 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 12:21:04.766590 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 12:21:04.770064 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 12:21:04.773707 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:21:04.773789
6262 12:21:04.776636 CA PerBit enable=1, Macro0, CA PI delay=36
6263 12:21:04.776718
6264 12:21:04.780211 [CBTSetCACLKResult] CA Dly = 36
6265 12:21:04.783457 CS Dly: 1 (0~32)
6266 12:21:04.783538
6267 12:21:04.786860 ----->DramcWriteLeveling(PI) begin...
6268 12:21:04.786943 ==
6269 12:21:04.790001 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 12:21:04.793125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 12:21:04.793208 ==
6272 12:21:04.796288 Write leveling (Byte 0): 40 => 8
6273 12:21:04.800037 Write leveling (Byte 1): 40 => 8
6274 12:21:04.803107 DramcWriteLeveling(PI) end<-----
6275 12:21:04.803191
6276 12:21:04.803256 ==
6277 12:21:04.806551 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 12:21:04.809569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 12:21:04.809652 ==
6280 12:21:04.813173 [Gating] SW mode calibration
6281 12:21:04.819821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6282 12:21:04.826408 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6283 12:21:04.829443 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 12:21:04.836145 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 12:21:04.839546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 12:21:04.842504 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 12:21:04.849014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 12:21:04.852422 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 12:21:04.855674 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 12:21:04.862766 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 12:21:04.865625 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 12:21:04.869045 Total UI for P1: 0, mck2ui 16
6293 12:21:04.872137 best dqsien dly found for B0: ( 0, 14, 24)
6294 12:21:04.875503 Total UI for P1: 0, mck2ui 16
6295 12:21:04.878849 best dqsien dly found for B1: ( 0, 14, 24)
6296 12:21:04.882396 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6297 12:21:04.885429 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6298 12:21:04.885536
6299 12:21:04.888792 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 12:21:04.891685 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 12:21:04.895352 [Gating] SW calibration Done
6302 12:21:04.895434 ==
6303 12:21:04.899094 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 12:21:04.904984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 12:21:04.905066 ==
6306 12:21:04.905131 RX Vref Scan: 0
6307 12:21:04.905191
6308 12:21:04.908591 RX Vref 0 -> 0, step: 1
6309 12:21:04.908672
6310 12:21:04.911501 RX Delay -410 -> 252, step: 16
6311 12:21:04.914807 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6312 12:21:04.918159 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6313 12:21:04.924952 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6314 12:21:04.928774 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6315 12:21:04.931499 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6316 12:21:04.934870 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6317 12:21:04.941423 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6318 12:21:04.944714 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6319 12:21:04.947880 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6320 12:21:04.951212 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6321 12:21:04.957932 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6322 12:21:04.960972 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6323 12:21:04.964762 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6324 12:21:04.967697 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6325 12:21:04.974120 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6326 12:21:04.977490 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6327 12:21:04.977572 ==
6328 12:21:04.981007 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 12:21:04.984480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 12:21:04.984587 ==
6331 12:21:04.987757 DQS Delay:
6332 12:21:04.987863 DQS0 = 35, DQS1 = 51
6333 12:21:04.990830 DQM Delay:
6334 12:21:04.990911 DQM0 = 5, DQM1 = 10
6335 12:21:04.990974 DQ Delay:
6336 12:21:04.994550 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6337 12:21:04.997702 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6338 12:21:05.000659 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6339 12:21:05.004495 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6340 12:21:05.004577
6341 12:21:05.004640
6342 12:21:05.004698 ==
6343 12:21:05.007291 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 12:21:05.014496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 12:21:05.014578 ==
6346 12:21:05.014643
6347 12:21:05.014702
6348 12:21:05.014759 TX Vref Scan disable
6349 12:21:05.017229 == TX Byte 0 ==
6350 12:21:05.020809 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 12:21:05.023754 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 12:21:05.027157 == TX Byte 1 ==
6353 12:21:05.030460 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 12:21:05.033799 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 12:21:05.033880 ==
6356 12:21:05.037134 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 12:21:05.043808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 12:21:05.043890 ==
6359 12:21:05.043994
6360 12:21:05.044054
6361 12:21:05.047040 TX Vref Scan disable
6362 12:21:05.047121 == TX Byte 0 ==
6363 12:21:05.050511 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 12:21:05.056785 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 12:21:05.056866 == TX Byte 1 ==
6366 12:21:05.060682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 12:21:05.066496 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 12:21:05.066576
6369 12:21:05.066639 [DATLAT]
6370 12:21:05.066698 Freq=400, CH0 RK0
6371 12:21:05.066755
6372 12:21:05.070147 DATLAT Default: 0xf
6373 12:21:05.070228 0, 0xFFFF, sum = 0
6374 12:21:05.073577 1, 0xFFFF, sum = 0
6375 12:21:05.076323 2, 0xFFFF, sum = 0
6376 12:21:05.076406 3, 0xFFFF, sum = 0
6377 12:21:05.079873 4, 0xFFFF, sum = 0
6378 12:21:05.079996 5, 0xFFFF, sum = 0
6379 12:21:05.082872 6, 0xFFFF, sum = 0
6380 12:21:05.082953 7, 0xFFFF, sum = 0
6381 12:21:05.086688 8, 0xFFFF, sum = 0
6382 12:21:05.086769 9, 0xFFFF, sum = 0
6383 12:21:05.089819 10, 0xFFFF, sum = 0
6384 12:21:05.089901 11, 0xFFFF, sum = 0
6385 12:21:05.092814 12, 0xFFFF, sum = 0
6386 12:21:05.092897 13, 0x0, sum = 1
6387 12:21:05.096237 14, 0x0, sum = 2
6388 12:21:05.096320 15, 0x0, sum = 3
6389 12:21:05.099314 16, 0x0, sum = 4
6390 12:21:05.099396 best_step = 14
6391 12:21:05.099459
6392 12:21:05.099519 ==
6393 12:21:05.103011 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 12:21:05.109522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 12:21:05.109604 ==
6396 12:21:05.109668 RX Vref Scan: 1
6397 12:21:05.109728
6398 12:21:05.112756 RX Vref 0 -> 0, step: 1
6399 12:21:05.112838
6400 12:21:05.116222 RX Delay -343 -> 252, step: 8
6401 12:21:05.116306
6402 12:21:05.119195 Set Vref, RX VrefLevel [Byte0]: 51
6403 12:21:05.122683 [Byte1]: 49
6404 12:21:05.122763
6405 12:21:05.125915 Final RX Vref Byte 0 = 51 to rank0
6406 12:21:05.129166 Final RX Vref Byte 1 = 49 to rank0
6407 12:21:05.132662 Final RX Vref Byte 0 = 51 to rank1
6408 12:21:05.135655 Final RX Vref Byte 1 = 49 to rank1==
6409 12:21:05.139094 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 12:21:05.145416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 12:21:05.145497 ==
6412 12:21:05.145561 DQS Delay:
6413 12:21:05.148847 DQS0 = 44, DQS1 = 56
6414 12:21:05.148928 DQM Delay:
6415 12:21:05.148991 DQM0 = 10, DQM1 = 14
6416 12:21:05.151875 DQ Delay:
6417 12:21:05.155142 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6418 12:21:05.158306 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6419 12:21:05.158387 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6420 12:21:05.162010 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6421 12:21:05.165137
6422 12:21:05.165217
6423 12:21:05.171503 [DQSOSCAuto] RK0, (LSB)MR18= 0x9488, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6424 12:21:05.174864 CH0 RK0: MR19=C0C, MR18=9488
6425 12:21:05.181723 CH0_RK0: MR19=0xC0C, MR18=0x9488, DQSOSC=391, MR23=63, INC=386, DEC=257
6426 12:21:05.181805 ==
6427 12:21:05.184841 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 12:21:05.188098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 12:21:05.188181 ==
6430 12:21:05.191301 [Gating] SW mode calibration
6431 12:21:05.198097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 12:21:05.204764 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6433 12:21:05.207614 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 12:21:05.211511 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 12:21:05.217823 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 12:21:05.221322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 12:21:05.224383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 12:21:05.231209 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 12:21:05.234239 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 12:21:05.237550 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 12:21:05.244100 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 12:21:05.247293 Total UI for P1: 0, mck2ui 16
6443 12:21:05.250854 best dqsien dly found for B0: ( 0, 14, 24)
6444 12:21:05.250936 Total UI for P1: 0, mck2ui 16
6445 12:21:05.257476 best dqsien dly found for B1: ( 0, 14, 24)
6446 12:21:05.260871 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6447 12:21:05.264032 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6448 12:21:05.264114
6449 12:21:05.267001 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 12:21:05.270676 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 12:21:05.274072 [Gating] SW calibration Done
6452 12:21:05.274153 ==
6453 12:21:05.276835 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 12:21:05.280092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 12:21:05.280174 ==
6456 12:21:05.283601 RX Vref Scan: 0
6457 12:21:05.283683
6458 12:21:05.286865 RX Vref 0 -> 0, step: 1
6459 12:21:05.286947
6460 12:21:05.287012 RX Delay -410 -> 252, step: 16
6461 12:21:05.293925 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6462 12:21:05.297263 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6463 12:21:05.300476 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6464 12:21:05.307124 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6465 12:21:05.309851 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6466 12:21:05.313251 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6467 12:21:05.316480 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6468 12:21:05.323237 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6469 12:21:05.326496 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6470 12:21:05.329893 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6471 12:21:05.333428 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6472 12:21:05.339893 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6473 12:21:05.343522 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6474 12:21:05.346131 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6475 12:21:05.349610 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6476 12:21:05.356088 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6477 12:21:05.356170 ==
6478 12:21:05.359190 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 12:21:05.362710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 12:21:05.362793 ==
6481 12:21:05.366041 DQS Delay:
6482 12:21:05.366122 DQS0 = 35, DQS1 = 51
6483 12:21:05.366187 DQM Delay:
6484 12:21:05.369643 DQM0 = 7, DQM1 = 10
6485 12:21:05.369724 DQ Delay:
6486 12:21:05.372425 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6487 12:21:05.375992 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6488 12:21:05.379472 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6489 12:21:05.382409 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6490 12:21:05.382490
6491 12:21:05.382554
6492 12:21:05.382614 ==
6493 12:21:05.385498 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 12:21:05.389212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 12:21:05.389293 ==
6496 12:21:05.392154
6497 12:21:05.392236
6498 12:21:05.392300 TX Vref Scan disable
6499 12:21:05.395629 == TX Byte 0 ==
6500 12:21:05.398975 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6501 12:21:05.402809 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6502 12:21:05.405632 == TX Byte 1 ==
6503 12:21:05.409004 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6504 12:21:05.412037 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6505 12:21:05.412118 ==
6506 12:21:05.415631 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 12:21:05.418635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 12:21:05.421951 ==
6509 12:21:05.422032
6510 12:21:05.422095
6511 12:21:05.422167 TX Vref Scan disable
6512 12:21:05.425329 == TX Byte 0 ==
6513 12:21:05.428795 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6514 12:21:05.432372 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6515 12:21:05.435134 == TX Byte 1 ==
6516 12:21:05.438539 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6517 12:21:05.441682 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6518 12:21:05.441763
6519 12:21:05.445585 [DATLAT]
6520 12:21:05.445667 Freq=400, CH0 RK1
6521 12:21:05.445731
6522 12:21:05.448544 DATLAT Default: 0xe
6523 12:21:05.448655 0, 0xFFFF, sum = 0
6524 12:21:05.451718 1, 0xFFFF, sum = 0
6525 12:21:05.451801 2, 0xFFFF, sum = 0
6526 12:21:05.455074 3, 0xFFFF, sum = 0
6527 12:21:05.455158 4, 0xFFFF, sum = 0
6528 12:21:05.458261 5, 0xFFFF, sum = 0
6529 12:21:05.458344 6, 0xFFFF, sum = 0
6530 12:21:05.461453 7, 0xFFFF, sum = 0
6531 12:21:05.461567 8, 0xFFFF, sum = 0
6532 12:21:05.465216 9, 0xFFFF, sum = 0
6533 12:21:05.465300 10, 0xFFFF, sum = 0
6534 12:21:05.467854 11, 0xFFFF, sum = 0
6535 12:21:05.471325 12, 0xFFFF, sum = 0
6536 12:21:05.471408 13, 0x0, sum = 1
6537 12:21:05.474898 14, 0x0, sum = 2
6538 12:21:05.475012 15, 0x0, sum = 3
6539 12:21:05.475125 16, 0x0, sum = 4
6540 12:21:05.477858 best_step = 14
6541 12:21:05.477939
6542 12:21:05.478002 ==
6543 12:21:05.481812 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 12:21:05.484866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 12:21:05.484979 ==
6546 12:21:05.488173 RX Vref Scan: 0
6547 12:21:05.488254
6548 12:21:05.488318 RX Vref 0 -> 0, step: 1
6549 12:21:05.491481
6550 12:21:05.491612 RX Delay -343 -> 252, step: 8
6551 12:21:05.499950 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6552 12:21:05.502773 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6553 12:21:05.506532 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6554 12:21:05.512874 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6555 12:21:05.516056 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6556 12:21:05.519226 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6557 12:21:05.522922 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6558 12:21:05.529365 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6559 12:21:05.532513 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6560 12:21:05.535691 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6561 12:21:05.538830 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6562 12:21:05.545516 iDelay=209, Bit 11, Center -48 (-287 ~ 192) 480
6563 12:21:05.548993 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6564 12:21:05.553031 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6565 12:21:05.555380 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6566 12:21:05.562459 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6567 12:21:05.562541 ==
6568 12:21:05.565373 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 12:21:05.568977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 12:21:05.569059 ==
6571 12:21:05.571836 DQS Delay:
6572 12:21:05.571988 DQS0 = 44, DQS1 = 60
6573 12:21:05.572060 DQM Delay:
6574 12:21:05.575647 DQM0 = 9, DQM1 = 15
6575 12:21:05.575728 DQ Delay:
6576 12:21:05.578572 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6577 12:21:05.581854 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6578 12:21:05.585114 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6579 12:21:05.588938 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6580 12:21:05.589019
6581 12:21:05.589083
6582 12:21:05.598738 [DQSOSCAuto] RK1, (LSB)MR18= 0x817d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6583 12:21:05.598821 CH0 RK1: MR19=C0C, MR18=817D
6584 12:21:05.605041 CH0_RK1: MR19=0xC0C, MR18=0x817D, DQSOSC=393, MR23=63, INC=382, DEC=254
6585 12:21:05.607966 [RxdqsGatingPostProcess] freq 400
6586 12:21:05.614849 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6587 12:21:05.618223 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 12:21:05.621233 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 12:21:05.624550 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 12:21:05.627856 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 12:21:05.631343 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 12:21:05.634644 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 12:21:05.637562 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 12:21:05.641079 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 12:21:05.641156 Pre-setting of DQS Precalculation
6596 12:21:05.647753 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6597 12:21:05.647867 ==
6598 12:21:05.650858 Dram Type= 6, Freq= 0, CH_1, rank 0
6599 12:21:05.654047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 12:21:05.654130 ==
6601 12:21:05.661001 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6602 12:21:05.667618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6603 12:21:05.670421 [CA 0] Center 36 (8~64) winsize 57
6604 12:21:05.673695 [CA 1] Center 36 (8~64) winsize 57
6605 12:21:05.677351 [CA 2] Center 36 (8~64) winsize 57
6606 12:21:05.680622 [CA 3] Center 36 (8~64) winsize 57
6607 12:21:05.683848 [CA 4] Center 36 (8~64) winsize 57
6608 12:21:05.687033 [CA 5] Center 36 (8~64) winsize 57
6609 12:21:05.687113
6610 12:21:05.690499 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6611 12:21:05.690571
6612 12:21:05.693983 [CATrainingPosCal] consider 1 rank data
6613 12:21:05.697178 u2DelayCellTimex100 = 270/100 ps
6614 12:21:05.700565 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 12:21:05.703280 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 12:21:05.707175 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 12:21:05.709938 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:21:05.713338 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:21:05.717345 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:21:05.717428
6621 12:21:05.723478 CA PerBit enable=1, Macro0, CA PI delay=36
6622 12:21:05.723560
6623 12:21:05.723624 [CBTSetCACLKResult] CA Dly = 36
6624 12:21:05.726769 CS Dly: 1 (0~32)
6625 12:21:05.726850 ==
6626 12:21:05.730036 Dram Type= 6, Freq= 0, CH_1, rank 1
6627 12:21:05.733291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 12:21:05.733372 ==
6629 12:21:05.739689 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 12:21:05.746404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 12:21:05.749367 [CA 0] Center 36 (8~64) winsize 57
6632 12:21:05.752668 [CA 1] Center 36 (8~64) winsize 57
6633 12:21:05.756287 [CA 2] Center 36 (8~64) winsize 57
6634 12:21:05.759159 [CA 3] Center 36 (8~64) winsize 57
6635 12:21:05.762952 [CA 4] Center 36 (8~64) winsize 57
6636 12:21:05.763033 [CA 5] Center 36 (8~64) winsize 57
6637 12:21:05.766233
6638 12:21:05.769105 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 12:21:05.769187
6640 12:21:05.772953 [CATrainingPosCal] consider 2 rank data
6641 12:21:05.775612 u2DelayCellTimex100 = 270/100 ps
6642 12:21:05.778883 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 12:21:05.782220 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 12:21:05.785701 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 12:21:05.789092 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 12:21:05.792415 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 12:21:05.796004 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:21:05.796086
6649 12:21:05.798799 CA PerBit enable=1, Macro0, CA PI delay=36
6650 12:21:05.802241
6651 12:21:05.802323 [CBTSetCACLKResult] CA Dly = 36
6652 12:21:05.805655 CS Dly: 1 (0~32)
6653 12:21:05.805736
6654 12:21:05.808572 ----->DramcWriteLeveling(PI) begin...
6655 12:21:05.808655 ==
6656 12:21:05.812021 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 12:21:05.815385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 12:21:05.815467 ==
6659 12:21:05.818390 Write leveling (Byte 0): 40 => 8
6660 12:21:05.822529 Write leveling (Byte 1): 40 => 8
6661 12:21:05.825214 DramcWriteLeveling(PI) end<-----
6662 12:21:05.825345
6663 12:21:05.825409 ==
6664 12:21:05.828582 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 12:21:05.831784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 12:21:05.834768 ==
6667 12:21:05.834849 [Gating] SW mode calibration
6668 12:21:05.844644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6669 12:21:05.848294 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6670 12:21:05.851162 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 12:21:05.857896 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 12:21:05.861762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 12:21:05.864499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 12:21:05.871389 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 12:21:05.874253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 12:21:05.877533 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 12:21:05.884042 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 12:21:05.887580 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 12:21:05.890903 Total UI for P1: 0, mck2ui 16
6680 12:21:05.894086 best dqsien dly found for B0: ( 0, 14, 24)
6681 12:21:05.897217 Total UI for P1: 0, mck2ui 16
6682 12:21:05.900608 best dqsien dly found for B1: ( 0, 14, 24)
6683 12:21:05.903938 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6684 12:21:05.907042 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6685 12:21:05.907124
6686 12:21:05.910404 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 12:21:05.916818 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 12:21:05.916900 [Gating] SW calibration Done
6689 12:21:05.920196 ==
6690 12:21:05.923334 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 12:21:05.926948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 12:21:05.927030 ==
6693 12:21:05.927095 RX Vref Scan: 0
6694 12:21:05.927155
6695 12:21:05.930290 RX Vref 0 -> 0, step: 1
6696 12:21:05.930371
6697 12:21:05.933496 RX Delay -410 -> 252, step: 16
6698 12:21:05.936803 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6699 12:21:05.943229 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6700 12:21:05.946423 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6701 12:21:05.950040 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6702 12:21:05.953507 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6703 12:21:05.959688 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6704 12:21:05.963192 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6705 12:21:05.966074 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6706 12:21:05.969999 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6707 12:21:05.976343 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6708 12:21:05.979448 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6709 12:21:05.982831 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6710 12:21:05.986075 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6711 12:21:05.992940 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6712 12:21:05.996201 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6713 12:21:05.999545 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6714 12:21:05.999652 ==
6715 12:21:06.002874 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 12:21:06.009532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 12:21:06.009614 ==
6718 12:21:06.009679 DQS Delay:
6719 12:21:06.012498 DQS0 = 43, DQS1 = 51
6720 12:21:06.012579 DQM Delay:
6721 12:21:06.012644 DQM0 = 13, DQM1 = 13
6722 12:21:06.016051 DQ Delay:
6723 12:21:06.019020 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6724 12:21:06.019101 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6725 12:21:06.022714 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6726 12:21:06.025947 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6727 12:21:06.026029
6728 12:21:06.028952
6729 12:21:06.029033 ==
6730 12:21:06.032882 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 12:21:06.035500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 12:21:06.035582 ==
6733 12:21:06.035646
6734 12:21:06.035705
6735 12:21:06.039132 TX Vref Scan disable
6736 12:21:06.039214 == TX Byte 0 ==
6737 12:21:06.042670 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 12:21:06.048906 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 12:21:06.048989 == TX Byte 1 ==
6740 12:21:06.052253 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 12:21:06.058789 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 12:21:06.058870 ==
6743 12:21:06.061988 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 12:21:06.065503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 12:21:06.065584 ==
6746 12:21:06.065648
6747 12:21:06.065717
6748 12:21:06.068826 TX Vref Scan disable
6749 12:21:06.068907 == TX Byte 0 ==
6750 12:21:06.075229 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 12:21:06.078915 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 12:21:06.078997 == TX Byte 1 ==
6753 12:21:06.085069 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 12:21:06.088526 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 12:21:06.088607
6756 12:21:06.088672 [DATLAT]
6757 12:21:06.091834 Freq=400, CH1 RK0
6758 12:21:06.091951
6759 12:21:06.092019 DATLAT Default: 0xf
6760 12:21:06.094966 0, 0xFFFF, sum = 0
6761 12:21:06.095049 1, 0xFFFF, sum = 0
6762 12:21:06.098679 2, 0xFFFF, sum = 0
6763 12:21:06.098765 3, 0xFFFF, sum = 0
6764 12:21:06.101681 4, 0xFFFF, sum = 0
6765 12:21:06.101765 5, 0xFFFF, sum = 0
6766 12:21:06.104935 6, 0xFFFF, sum = 0
6767 12:21:06.105018 7, 0xFFFF, sum = 0
6768 12:21:06.108286 8, 0xFFFF, sum = 0
6769 12:21:06.108368 9, 0xFFFF, sum = 0
6770 12:21:06.111626 10, 0xFFFF, sum = 0
6771 12:21:06.111709 11, 0xFFFF, sum = 0
6772 12:21:06.114814 12, 0xFFFF, sum = 0
6773 12:21:06.118233 13, 0x0, sum = 1
6774 12:21:06.118315 14, 0x0, sum = 2
6775 12:21:06.118381 15, 0x0, sum = 3
6776 12:21:06.121579 16, 0x0, sum = 4
6777 12:21:06.121661 best_step = 14
6778 12:21:06.121725
6779 12:21:06.124734 ==
6780 12:21:06.124815 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 12:21:06.131497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 12:21:06.131589 ==
6783 12:21:06.131663 RX Vref Scan: 1
6784 12:21:06.131725
6785 12:21:06.134769 RX Vref 0 -> 0, step: 1
6786 12:21:06.134838
6787 12:21:06.137629 RX Delay -343 -> 252, step: 8
6788 12:21:06.137705
6789 12:21:06.140854 Set Vref, RX VrefLevel [Byte0]: 51
6790 12:21:06.144289 [Byte1]: 50
6791 12:21:06.148180
6792 12:21:06.148249 Final RX Vref Byte 0 = 51 to rank0
6793 12:21:06.151183 Final RX Vref Byte 1 = 50 to rank0
6794 12:21:06.154381 Final RX Vref Byte 0 = 51 to rank1
6795 12:21:06.157658 Final RX Vref Byte 1 = 50 to rank1==
6796 12:21:06.161027 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 12:21:06.167857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 12:21:06.167950 ==
6799 12:21:06.168014 DQS Delay:
6800 12:21:06.171162 DQS0 = 44, DQS1 = 56
6801 12:21:06.171234 DQM Delay:
6802 12:21:06.171293 DQM0 = 11, DQM1 = 14
6803 12:21:06.174503 DQ Delay:
6804 12:21:06.177825 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6805 12:21:06.181026 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6806 12:21:06.181095 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6807 12:21:06.184567 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6808 12:21:06.187730
6809 12:21:06.187805
6810 12:21:06.194037 [DQSOSCAuto] RK0, (LSB)MR18= 0x688f, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6811 12:21:06.197445 CH1 RK0: MR19=C0C, MR18=688F
6812 12:21:06.204651 CH1_RK0: MR19=0xC0C, MR18=0x688F, DQSOSC=391, MR23=63, INC=386, DEC=257
6813 12:21:06.204733 ==
6814 12:21:06.207393 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 12:21:06.210763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 12:21:06.210846 ==
6817 12:21:06.213869 [Gating] SW mode calibration
6818 12:21:06.220765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6819 12:21:06.227240 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6820 12:21:06.230511 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 12:21:06.234006 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 12:21:06.240582 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 12:21:06.243878 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 12:21:06.247212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 12:21:06.253542 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 12:21:06.256844 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 12:21:06.259937 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 12:21:06.266692 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 12:21:06.266769 Total UI for P1: 0, mck2ui 16
6830 12:21:06.273329 best dqsien dly found for B0: ( 0, 14, 24)
6831 12:21:06.273407 Total UI for P1: 0, mck2ui 16
6832 12:21:06.280277 best dqsien dly found for B1: ( 0, 14, 24)
6833 12:21:06.283064 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6834 12:21:06.286530 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6835 12:21:06.286604
6836 12:21:06.289730 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 12:21:06.293434 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 12:21:06.296372 [Gating] SW calibration Done
6839 12:21:06.296443 ==
6840 12:21:06.299615 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 12:21:06.302638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 12:21:06.302708 ==
6843 12:21:06.306247 RX Vref Scan: 0
6844 12:21:06.306315
6845 12:21:06.309382 RX Vref 0 -> 0, step: 1
6846 12:21:06.309455
6847 12:21:06.309523 RX Delay -410 -> 252, step: 16
6848 12:21:06.316015 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6849 12:21:06.319684 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6850 12:21:06.322425 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6851 12:21:06.329231 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6852 12:21:06.332418 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6853 12:21:06.335576 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6854 12:21:06.339082 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6855 12:21:06.346008 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6856 12:21:06.348894 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6857 12:21:06.352207 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6858 12:21:06.355434 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6859 12:21:06.362087 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6860 12:21:06.365454 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6861 12:21:06.368698 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6862 12:21:06.371987 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6863 12:21:06.378616 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6864 12:21:06.378692 ==
6865 12:21:06.381787 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 12:21:06.385347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 12:21:06.385429 ==
6868 12:21:06.388770 DQS Delay:
6869 12:21:06.388839 DQS0 = 43, DQS1 = 51
6870 12:21:06.388904 DQM Delay:
6871 12:21:06.391569 DQM0 = 9, DQM1 = 16
6872 12:21:06.391637 DQ Delay:
6873 12:21:06.395313 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6874 12:21:06.398458 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6875 12:21:06.402256 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6876 12:21:06.405033 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6877 12:21:06.405103
6878 12:21:06.405162
6879 12:21:06.405225 ==
6880 12:21:06.408167 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 12:21:06.411713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 12:21:06.411778 ==
6883 12:21:06.415185
6884 12:21:06.415252
6885 12:21:06.415315 TX Vref Scan disable
6886 12:21:06.418363 == TX Byte 0 ==
6887 12:21:06.421996 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 12:21:06.425325 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 12:21:06.427841 == TX Byte 1 ==
6890 12:21:06.431697 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6891 12:21:06.434371 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6892 12:21:06.434437 ==
6893 12:21:06.437648 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 12:21:06.444727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 12:21:06.444803 ==
6896 12:21:06.444865
6897 12:21:06.444922
6898 12:21:06.444978 TX Vref Scan disable
6899 12:21:06.447713 == TX Byte 0 ==
6900 12:21:06.451272 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6901 12:21:06.454385 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6902 12:21:06.457695 == TX Byte 1 ==
6903 12:21:06.460831 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6904 12:21:06.464216 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6905 12:21:06.464293
6906 12:21:06.467327 [DATLAT]
6907 12:21:06.467393 Freq=400, CH1 RK1
6908 12:21:06.467452
6909 12:21:06.470875 DATLAT Default: 0xe
6910 12:21:06.470942 0, 0xFFFF, sum = 0
6911 12:21:06.473804 1, 0xFFFF, sum = 0
6912 12:21:06.473876 2, 0xFFFF, sum = 0
6913 12:21:06.477006 3, 0xFFFF, sum = 0
6914 12:21:06.477083 4, 0xFFFF, sum = 0
6915 12:21:06.480271 5, 0xFFFF, sum = 0
6916 12:21:06.480356 6, 0xFFFF, sum = 0
6917 12:21:06.483634 7, 0xFFFF, sum = 0
6918 12:21:06.483740 8, 0xFFFF, sum = 0
6919 12:21:06.486987 9, 0xFFFF, sum = 0
6920 12:21:06.490374 10, 0xFFFF, sum = 0
6921 12:21:06.490453 11, 0xFFFF, sum = 0
6922 12:21:06.494074 12, 0xFFFF, sum = 0
6923 12:21:06.494155 13, 0x0, sum = 1
6924 12:21:06.496799 14, 0x0, sum = 2
6925 12:21:06.496872 15, 0x0, sum = 3
6926 12:21:06.500178 16, 0x0, sum = 4
6927 12:21:06.500280 best_step = 14
6928 12:21:06.500368
6929 12:21:06.500460 ==
6930 12:21:06.503500 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 12:21:06.506848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 12:21:06.506922 ==
6933 12:21:06.509931 RX Vref Scan: 0
6934 12:21:06.510006
6935 12:21:06.513102 RX Vref 0 -> 0, step: 1
6936 12:21:06.513177
6937 12:21:06.513242 RX Delay -343 -> 252, step: 8
6938 12:21:06.522098 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6939 12:21:06.525484 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6940 12:21:06.528689 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6941 12:21:06.532122 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6942 12:21:06.538738 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6943 12:21:06.542035 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6944 12:21:06.545453 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6945 12:21:06.551842 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6946 12:21:06.555423 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6947 12:21:06.558338 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6948 12:21:06.561941 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6949 12:21:06.568109 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6950 12:21:06.571449 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6951 12:21:06.574809 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6952 12:21:06.578064 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6953 12:21:06.584558 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6954 12:21:06.584629 ==
6955 12:21:06.588160 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 12:21:06.591416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 12:21:06.591489 ==
6958 12:21:06.591549 DQS Delay:
6959 12:21:06.594417 DQS0 = 48, DQS1 = 56
6960 12:21:06.594492 DQM Delay:
6961 12:21:06.597876 DQM0 = 12, DQM1 = 13
6962 12:21:06.597952 DQ Delay:
6963 12:21:06.601052 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6964 12:21:06.604248 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6965 12:21:06.607827 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6966 12:21:06.610798 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6967 12:21:06.610895
6968 12:21:06.610983
6969 12:21:06.620799 [DQSOSCAuto] RK1, (LSB)MR18= 0x6aa1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6970 12:21:06.620883 CH1 RK1: MR19=C0C, MR18=6AA1
6971 12:21:06.627385 CH1_RK1: MR19=0xC0C, MR18=0x6AA1, DQSOSC=389, MR23=63, INC=390, DEC=260
6972 12:21:06.630575 [RxdqsGatingPostProcess] freq 400
6973 12:21:06.637609 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6974 12:21:06.640936 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 12:21:06.644054 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 12:21:06.647163 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 12:21:06.650405 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 12:21:06.654182 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 12:21:06.657506 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 12:21:06.660501 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 12:21:06.663818 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 12:21:06.663956 Pre-setting of DQS Precalculation
6983 12:21:06.670407 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6984 12:21:06.676632 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6985 12:21:06.683589 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6986 12:21:06.683667
6987 12:21:06.683749
6988 12:21:06.686931 [Calibration Summary] 800 Mbps
6989 12:21:06.689978 CH 0, Rank 0
6990 12:21:06.690081 SW Impedance : PASS
6991 12:21:06.693311 DUTY Scan : NO K
6992 12:21:06.696453 ZQ Calibration : PASS
6993 12:21:06.696527 Jitter Meter : NO K
6994 12:21:06.700126 CBT Training : PASS
6995 12:21:06.703016 Write leveling : PASS
6996 12:21:06.703089 RX DQS gating : PASS
6997 12:21:06.706932 RX DQ/DQS(RDDQC) : PASS
6998 12:21:06.709986 TX DQ/DQS : PASS
6999 12:21:06.710062 RX DATLAT : PASS
7000 12:21:06.712823 RX DQ/DQS(Engine): PASS
7001 12:21:06.716102 TX OE : NO K
7002 12:21:06.716214 All Pass.
7003 12:21:06.716280
7004 12:21:06.716338 CH 0, Rank 1
7005 12:21:06.719989 SW Impedance : PASS
7006 12:21:06.722750 DUTY Scan : NO K
7007 12:21:06.722817 ZQ Calibration : PASS
7008 12:21:06.726364 Jitter Meter : NO K
7009 12:21:06.729559 CBT Training : PASS
7010 12:21:06.729628 Write leveling : NO K
7011 12:21:06.732663 RX DQS gating : PASS
7012 12:21:06.732737 RX DQ/DQS(RDDQC) : PASS
7013 12:21:06.736078 TX DQ/DQS : PASS
7014 12:21:06.739779 RX DATLAT : PASS
7015 12:21:06.739877 RX DQ/DQS(Engine): PASS
7016 12:21:06.742625 TX OE : NO K
7017 12:21:06.742711 All Pass.
7018 12:21:06.742784
7019 12:21:06.746025 CH 1, Rank 0
7020 12:21:06.746093 SW Impedance : PASS
7021 12:21:06.749099 DUTY Scan : NO K
7022 12:21:06.752637 ZQ Calibration : PASS
7023 12:21:06.752706 Jitter Meter : NO K
7024 12:21:06.756071 CBT Training : PASS
7025 12:21:06.759219 Write leveling : PASS
7026 12:21:06.759287 RX DQS gating : PASS
7027 12:21:06.762714 RX DQ/DQS(RDDQC) : PASS
7028 12:21:06.765558 TX DQ/DQS : PASS
7029 12:21:06.765625 RX DATLAT : PASS
7030 12:21:06.768655 RX DQ/DQS(Engine): PASS
7031 12:21:06.772594 TX OE : NO K
7032 12:21:06.772666 All Pass.
7033 12:21:06.772735
7034 12:21:06.772792 CH 1, Rank 1
7035 12:21:06.775388 SW Impedance : PASS
7036 12:21:06.778787 DUTY Scan : NO K
7037 12:21:06.778975 ZQ Calibration : PASS
7038 12:21:06.782100 Jitter Meter : NO K
7039 12:21:06.785631 CBT Training : PASS
7040 12:21:06.785701 Write leveling : NO K
7041 12:21:06.788930 RX DQS gating : PASS
7042 12:21:06.792272 RX DQ/DQS(RDDQC) : PASS
7043 12:21:06.792369 TX DQ/DQS : PASS
7044 12:21:06.795188 RX DATLAT : PASS
7045 12:21:06.798422 RX DQ/DQS(Engine): PASS
7046 12:21:06.798492 TX OE : NO K
7047 12:21:06.802785 All Pass.
7048 12:21:06.802855
7049 12:21:06.802914 DramC Write-DBI off
7050 12:21:06.805382 PER_BANK_REFRESH: Hybrid Mode
7051 12:21:06.805449 TX_TRACKING: ON
7052 12:21:06.814592 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7053 12:21:06.817895 [FAST_K] Save calibration result to emmc
7054 12:21:06.821417 dramc_set_vcore_voltage set vcore to 725000
7055 12:21:06.824924 Read voltage for 1600, 0
7056 12:21:06.825001 Vio18 = 0
7057 12:21:06.828215 Vcore = 725000
7058 12:21:06.828286 Vdram = 0
7059 12:21:06.828351 Vddq = 0
7060 12:21:06.831358 Vmddr = 0
7061 12:21:06.834566 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7062 12:21:06.841407 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7063 12:21:06.841479 MEM_TYPE=3, freq_sel=13
7064 12:21:06.844290 sv_algorithm_assistance_LP4_3733
7065 12:21:06.851611 ============ PULL DRAM RESETB DOWN ============
7066 12:21:06.854203 ========== PULL DRAM RESETB DOWN end =========
7067 12:21:06.857629 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7068 12:21:06.860851 ===================================
7069 12:21:06.864318 LPDDR4 DRAM CONFIGURATION
7070 12:21:06.867468 ===================================
7071 12:21:06.871403 EX_ROW_EN[0] = 0x0
7072 12:21:06.871488 EX_ROW_EN[1] = 0x0
7073 12:21:06.873813 LP4Y_EN = 0x0
7074 12:21:06.873888 WORK_FSP = 0x1
7075 12:21:06.877342 WL = 0x5
7076 12:21:06.877456 RL = 0x5
7077 12:21:06.880541 BL = 0x2
7078 12:21:06.880615 RPST = 0x0
7079 12:21:06.883584 RD_PRE = 0x0
7080 12:21:06.883685 WR_PRE = 0x1
7081 12:21:06.886994 WR_PST = 0x1
7082 12:21:06.887099 DBI_WR = 0x0
7083 12:21:06.890799 DBI_RD = 0x0
7084 12:21:06.893648 OTF = 0x1
7085 12:21:06.897279 ===================================
7086 12:21:06.900330 ===================================
7087 12:21:06.900409 ANA top config
7088 12:21:06.903624 ===================================
7089 12:21:06.907275 DLL_ASYNC_EN = 0
7090 12:21:06.910600 ALL_SLAVE_EN = 0
7091 12:21:06.910680 NEW_RANK_MODE = 1
7092 12:21:06.913470 DLL_IDLE_MODE = 1
7093 12:21:06.916916 LP45_APHY_COMB_EN = 1
7094 12:21:06.920182 TX_ODT_DIS = 0
7095 12:21:06.920262 NEW_8X_MODE = 1
7096 12:21:06.923368 ===================================
7097 12:21:06.926732 ===================================
7098 12:21:06.930164 data_rate = 3200
7099 12:21:06.932961 CKR = 1
7100 12:21:06.936510 DQ_P2S_RATIO = 8
7101 12:21:06.939869 ===================================
7102 12:21:06.943154 CA_P2S_RATIO = 8
7103 12:21:06.946591 DQ_CA_OPEN = 0
7104 12:21:06.949506 DQ_SEMI_OPEN = 0
7105 12:21:06.949586 CA_SEMI_OPEN = 0
7106 12:21:06.953098 CA_FULL_RATE = 0
7107 12:21:06.956180 DQ_CKDIV4_EN = 0
7108 12:21:06.959471 CA_CKDIV4_EN = 0
7109 12:21:06.962608 CA_PREDIV_EN = 0
7110 12:21:06.965897 PH8_DLY = 12
7111 12:21:06.965977 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7112 12:21:06.969299 DQ_AAMCK_DIV = 4
7113 12:21:06.972478 CA_AAMCK_DIV = 4
7114 12:21:06.976087 CA_ADMCK_DIV = 4
7115 12:21:06.979730 DQ_TRACK_CA_EN = 0
7116 12:21:06.982887 CA_PICK = 1600
7117 12:21:06.985637 CA_MCKIO = 1600
7118 12:21:06.985721 MCKIO_SEMI = 0
7119 12:21:06.988927 PLL_FREQ = 3068
7120 12:21:06.993168 DQ_UI_PI_RATIO = 32
7121 12:21:06.995519 CA_UI_PI_RATIO = 0
7122 12:21:06.999061 ===================================
7123 12:21:07.002081 ===================================
7124 12:21:07.005746 memory_type:LPDDR4
7125 12:21:07.005825 GP_NUM : 10
7126 12:21:07.008956 SRAM_EN : 1
7127 12:21:07.011990 MD32_EN : 0
7128 12:21:07.015343 ===================================
7129 12:21:07.015424 [ANA_INIT] >>>>>>>>>>>>>>
7130 12:21:07.019337 <<<<<< [CONFIGURE PHASE]: ANA_TX
7131 12:21:07.022371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7132 12:21:07.025286 ===================================
7133 12:21:07.028502 data_rate = 3200,PCW = 0X7600
7134 12:21:07.031954 ===================================
7135 12:21:07.035371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7136 12:21:07.041769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 12:21:07.048532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 12:21:07.051438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7139 12:21:07.055617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7140 12:21:07.058354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7141 12:21:07.062112 [ANA_INIT] flow start
7142 12:21:07.062192 [ANA_INIT] PLL >>>>>>>>
7143 12:21:07.064826 [ANA_INIT] PLL <<<<<<<<
7144 12:21:07.068198 [ANA_INIT] MIDPI >>>>>>>>
7145 12:21:07.068278 [ANA_INIT] MIDPI <<<<<<<<
7146 12:21:07.071349 [ANA_INIT] DLL >>>>>>>>
7147 12:21:07.074901 [ANA_INIT] DLL <<<<<<<<
7148 12:21:07.075007 [ANA_INIT] flow end
7149 12:21:07.081131 ============ LP4 DIFF to SE enter ============
7150 12:21:07.084609 ============ LP4 DIFF to SE exit ============
7151 12:21:07.088017 [ANA_INIT] <<<<<<<<<<<<<
7152 12:21:07.090717 [Flow] Enable top DCM control >>>>>
7153 12:21:07.094022 [Flow] Enable top DCM control <<<<<
7154 12:21:07.097696 Enable DLL master slave shuffle
7155 12:21:07.100789 ==============================================================
7156 12:21:07.104425 Gating Mode config
7157 12:21:07.107227 ==============================================================
7158 12:21:07.110623 Config description:
7159 12:21:07.120437 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7160 12:21:07.127340 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7161 12:21:07.130612 SELPH_MODE 0: By rank 1: By Phase
7162 12:21:07.137457 ==============================================================
7163 12:21:07.140303 GAT_TRACK_EN = 1
7164 12:21:07.143539 RX_GATING_MODE = 2
7165 12:21:07.146989 RX_GATING_TRACK_MODE = 2
7166 12:21:07.150093 SELPH_MODE = 1
7167 12:21:07.153780 PICG_EARLY_EN = 1
7168 12:21:07.156915 VALID_LAT_VALUE = 1
7169 12:21:07.160232 ==============================================================
7170 12:21:07.163433 Enter into Gating configuration >>>>
7171 12:21:07.167721 Exit from Gating configuration <<<<
7172 12:21:07.169841 Enter into DVFS_PRE_config >>>>>
7173 12:21:07.183227 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7174 12:21:07.186333 Exit from DVFS_PRE_config <<<<<
7175 12:21:07.186417 Enter into PICG configuration >>>>
7176 12:21:07.189604 Exit from PICG configuration <<<<
7177 12:21:07.193292 [RX_INPUT] configuration >>>>>
7178 12:21:07.196532 [RX_INPUT] configuration <<<<<
7179 12:21:07.203049 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7180 12:21:07.205992 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7181 12:21:07.212968 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7182 12:21:07.219355 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7183 12:21:07.226389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 12:21:07.232583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 12:21:07.236044 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7186 12:21:07.239371 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7187 12:21:07.246066 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7188 12:21:07.248877 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7189 12:21:07.252105 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7190 12:21:07.255623 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 12:21:07.258898 ===================================
7192 12:21:07.261837 LPDDR4 DRAM CONFIGURATION
7193 12:21:07.265049 ===================================
7194 12:21:07.268699 EX_ROW_EN[0] = 0x0
7195 12:21:07.268782 EX_ROW_EN[1] = 0x0
7196 12:21:07.271868 LP4Y_EN = 0x0
7197 12:21:07.272028 WORK_FSP = 0x1
7198 12:21:07.275028 WL = 0x5
7199 12:21:07.275111 RL = 0x5
7200 12:21:07.278802 BL = 0x2
7201 12:21:07.282004 RPST = 0x0
7202 12:21:07.282088 RD_PRE = 0x0
7203 12:21:07.284907 WR_PRE = 0x1
7204 12:21:07.284991 WR_PST = 0x1
7205 12:21:07.289046 DBI_WR = 0x0
7206 12:21:07.289130 DBI_RD = 0x0
7207 12:21:07.291796 OTF = 0x1
7208 12:21:07.294977 ===================================
7209 12:21:07.298260 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7210 12:21:07.301664 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7211 12:21:07.304862 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 12:21:07.308252 ===================================
7213 12:21:07.311497 LPDDR4 DRAM CONFIGURATION
7214 12:21:07.314647 ===================================
7215 12:21:07.317947 EX_ROW_EN[0] = 0x10
7216 12:21:07.318031 EX_ROW_EN[1] = 0x0
7217 12:21:07.321669 LP4Y_EN = 0x0
7218 12:21:07.321752 WORK_FSP = 0x1
7219 12:21:07.324717 WL = 0x5
7220 12:21:07.328232 RL = 0x5
7221 12:21:07.328316 BL = 0x2
7222 12:21:07.331444 RPST = 0x0
7223 12:21:07.331527 RD_PRE = 0x0
7224 12:21:07.334578 WR_PRE = 0x1
7225 12:21:07.334661 WR_PST = 0x1
7226 12:21:07.338029 DBI_WR = 0x0
7227 12:21:07.338113 DBI_RD = 0x0
7228 12:21:07.341168 OTF = 0x1
7229 12:21:07.344418 ===================================
7230 12:21:07.351070 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7231 12:21:07.351154 ==
7232 12:21:07.354451 Dram Type= 6, Freq= 0, CH_0, rank 0
7233 12:21:07.357606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7234 12:21:07.357690 ==
7235 12:21:07.360827 [Duty_Offset_Calibration]
7236 12:21:07.360910 B0:2 B1:0 CA:4
7237 12:21:07.360995
7238 12:21:07.364088 [DutyScan_Calibration_Flow] k_type=0
7239 12:21:07.373724
7240 12:21:07.373807 ==CLK 0==
7241 12:21:07.377006 Final CLK duty delay cell = -4
7242 12:21:07.380515 [-4] MAX Duty = 5031%(X100), DQS PI = 16
7243 12:21:07.383544 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7244 12:21:07.386871 [-4] AVG Duty = 4937%(X100)
7245 12:21:07.386954
7246 12:21:07.390258 CH0 CLK Duty spec in!! Max-Min= 187%
7247 12:21:07.393275 [DutyScan_Calibration_Flow] ====Done====
7248 12:21:07.393359
7249 12:21:07.396951 [DutyScan_Calibration_Flow] k_type=1
7250 12:21:07.413944
7251 12:21:07.414027 ==DQS 0 ==
7252 12:21:07.417409 Final DQS duty delay cell = 0
7253 12:21:07.420362 [0] MAX Duty = 5218%(X100), DQS PI = 38
7254 12:21:07.423722 [0] MIN Duty = 5093%(X100), DQS PI = 14
7255 12:21:07.427363 [0] AVG Duty = 5155%(X100)
7256 12:21:07.427447
7257 12:21:07.427531 ==DQS 1 ==
7258 12:21:07.430240 Final DQS duty delay cell = 0
7259 12:21:07.434310 [0] MAX Duty = 5156%(X100), DQS PI = 2
7260 12:21:07.437443 [0] MIN Duty = 4969%(X100), DQS PI = 10
7261 12:21:07.440322 [0] AVG Duty = 5062%(X100)
7262 12:21:07.440406
7263 12:21:07.443482 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7264 12:21:07.443565
7265 12:21:07.447254 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7266 12:21:07.449998 [DutyScan_Calibration_Flow] ====Done====
7267 12:21:07.450081
7268 12:21:07.453405 [DutyScan_Calibration_Flow] k_type=3
7269 12:21:07.471184
7270 12:21:07.471266 ==DQM 0 ==
7271 12:21:07.474549 Final DQM duty delay cell = 0
7272 12:21:07.477570 [0] MAX Duty = 5156%(X100), DQS PI = 22
7273 12:21:07.481409 [0] MIN Duty = 4875%(X100), DQS PI = 54
7274 12:21:07.484262 [0] AVG Duty = 5015%(X100)
7275 12:21:07.484345
7276 12:21:07.484430 ==DQM 1 ==
7277 12:21:07.487569 Final DQM duty delay cell = 0
7278 12:21:07.491180 [0] MAX Duty = 5000%(X100), DQS PI = 4
7279 12:21:07.494377 [0] MIN Duty = 4813%(X100), DQS PI = 16
7280 12:21:07.497486 [0] AVG Duty = 4906%(X100)
7281 12:21:07.497570
7282 12:21:07.500525 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7283 12:21:07.500608
7284 12:21:07.503815 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7285 12:21:07.507105 [DutyScan_Calibration_Flow] ====Done====
7286 12:21:07.507189
7287 12:21:07.510610 [DutyScan_Calibration_Flow] k_type=2
7288 12:21:07.528468
7289 12:21:07.528551 ==DQ 0 ==
7290 12:21:07.531359 Final DQ duty delay cell = 0
7291 12:21:07.535193 [0] MAX Duty = 5156%(X100), DQS PI = 26
7292 12:21:07.537791 [0] MIN Duty = 4938%(X100), DQS PI = 12
7293 12:21:07.541252 [0] AVG Duty = 5047%(X100)
7294 12:21:07.541332
7295 12:21:07.541394 ==DQ 1 ==
7296 12:21:07.544691 Final DQ duty delay cell = 0
7297 12:21:07.548047 [0] MAX Duty = 5187%(X100), DQS PI = 2
7298 12:21:07.551174 [0] MIN Duty = 4907%(X100), DQS PI = 34
7299 12:21:07.551252 [0] AVG Duty = 5047%(X100)
7300 12:21:07.555020
7301 12:21:07.557623 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7302 12:21:07.557704
7303 12:21:07.561116 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7304 12:21:07.564284 [DutyScan_Calibration_Flow] ====Done====
7305 12:21:07.564365 ==
7306 12:21:07.567745 Dram Type= 6, Freq= 0, CH_1, rank 0
7307 12:21:07.571239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 12:21:07.571321 ==
7309 12:21:07.574478 [Duty_Offset_Calibration]
7310 12:21:07.574557 B0:0 B1:-1 CA:3
7311 12:21:07.574620
7312 12:21:07.577378 [DutyScan_Calibration_Flow] k_type=0
7313 12:21:07.587768
7314 12:21:07.587882 ==CLK 0==
7315 12:21:07.590938 Final CLK duty delay cell = -4
7316 12:21:07.594074 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7317 12:21:07.597529 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7318 12:21:07.601159 [-4] AVG Duty = 4922%(X100)
7319 12:21:07.601238
7320 12:21:07.603984 CH1 CLK Duty spec in!! Max-Min= 156%
7321 12:21:07.607578 [DutyScan_Calibration_Flow] ====Done====
7322 12:21:07.607675
7323 12:21:07.610778 [DutyScan_Calibration_Flow] k_type=1
7324 12:21:07.626947
7325 12:21:07.627026 ==DQS 0 ==
7326 12:21:07.630134 Final DQS duty delay cell = 0
7327 12:21:07.633107 [0] MAX Duty = 5250%(X100), DQS PI = 28
7328 12:21:07.636872 [0] MIN Duty = 4938%(X100), DQS PI = 56
7329 12:21:07.639909 [0] AVG Duty = 5094%(X100)
7330 12:21:07.640020
7331 12:21:07.640093 ==DQS 1 ==
7332 12:21:07.643328 Final DQS duty delay cell = -4
7333 12:21:07.646722 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7334 12:21:07.649855 [-4] MIN Duty = 4844%(X100), DQS PI = 16
7335 12:21:07.653908 [-4] AVG Duty = 4922%(X100)
7336 12:21:07.654007
7337 12:21:07.656386 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7338 12:21:07.656465
7339 12:21:07.659565 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7340 12:21:07.663281 [DutyScan_Calibration_Flow] ====Done====
7341 12:21:07.663360
7342 12:21:07.666053 [DutyScan_Calibration_Flow] k_type=3
7343 12:21:07.684265
7344 12:21:07.684343 ==DQM 0 ==
7345 12:21:07.687416 Final DQM duty delay cell = 0
7346 12:21:07.690826 [0] MAX Duty = 5062%(X100), DQS PI = 30
7347 12:21:07.693786 [0] MIN Duty = 4750%(X100), DQS PI = 40
7348 12:21:07.697179 [0] AVG Duty = 4906%(X100)
7349 12:21:07.697259
7350 12:21:07.697321 ==DQM 1 ==
7351 12:21:07.700924 Final DQM duty delay cell = 0
7352 12:21:07.704052 [0] MAX Duty = 5031%(X100), DQS PI = 32
7353 12:21:07.707184 [0] MIN Duty = 4813%(X100), DQS PI = 12
7354 12:21:07.710373 [0] AVG Duty = 4922%(X100)
7355 12:21:07.710452
7356 12:21:07.713711 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7357 12:21:07.713790
7358 12:21:07.717204 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7359 12:21:07.720372 [DutyScan_Calibration_Flow] ====Done====
7360 12:21:07.720452
7361 12:21:07.723770 [DutyScan_Calibration_Flow] k_type=2
7362 12:21:07.740436
7363 12:21:07.740515 ==DQ 0 ==
7364 12:21:07.743586 Final DQ duty delay cell = -4
7365 12:21:07.746799 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7366 12:21:07.750555 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7367 12:21:07.753525 [-4] AVG Duty = 4891%(X100)
7368 12:21:07.753605
7369 12:21:07.753668 ==DQ 1 ==
7370 12:21:07.757114 Final DQ duty delay cell = 0
7371 12:21:07.760618 [0] MAX Duty = 5031%(X100), DQS PI = 32
7372 12:21:07.763258 [0] MIN Duty = 4875%(X100), DQS PI = 0
7373 12:21:07.767270 [0] AVG Duty = 4953%(X100)
7374 12:21:07.767349
7375 12:21:07.769958 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7376 12:21:07.770039
7377 12:21:07.773122 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7378 12:21:07.776364 [DutyScan_Calibration_Flow] ====Done====
7379 12:21:07.779590 nWR fixed to 30
7380 12:21:07.782959 [ModeRegInit_LP4] CH0 RK0
7381 12:21:07.783039 [ModeRegInit_LP4] CH0 RK1
7382 12:21:07.786755 [ModeRegInit_LP4] CH1 RK0
7383 12:21:07.789516 [ModeRegInit_LP4] CH1 RK1
7384 12:21:07.789598 match AC timing 5
7385 12:21:07.796379 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7386 12:21:07.799353 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7387 12:21:07.802995 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7388 12:21:07.809476 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7389 12:21:07.812720 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7390 12:21:07.815778 [MiockJmeterHQA]
7391 12:21:07.815882
7392 12:21:07.819173 [DramcMiockJmeter] u1RxGatingPI = 0
7393 12:21:07.819253 0 : 4252, 4027
7394 12:21:07.819317 4 : 4253, 4026
7395 12:21:07.822378 8 : 4363, 4137
7396 12:21:07.822459 12 : 4252, 4027
7397 12:21:07.826103 16 : 4252, 4026
7398 12:21:07.826184 20 : 4363, 4138
7399 12:21:07.829045 24 : 4363, 4137
7400 12:21:07.829126 28 : 4252, 4027
7401 12:21:07.829191 32 : 4253, 4027
7402 12:21:07.832340 36 : 4253, 4026
7403 12:21:07.832420 40 : 4252, 4027
7404 12:21:07.835496 44 : 4254, 4029
7405 12:21:07.835577 48 : 4363, 4137
7406 12:21:07.839157 52 : 4249, 4027
7407 12:21:07.839239 56 : 4250, 4026
7408 12:21:07.842132 60 : 4250, 4027
7409 12:21:07.842213 64 : 4252, 4029
7410 12:21:07.842276 68 : 4250, 4026
7411 12:21:07.845281 72 : 4360, 4138
7412 12:21:07.845389 76 : 4361, 4137
7413 12:21:07.848707 80 : 4252, 4027
7414 12:21:07.848788 84 : 4250, 4027
7415 12:21:07.852321 88 : 4250, 4027
7416 12:21:07.852402 92 : 4250, 4027
7417 12:21:07.855402 96 : 4253, 3545
7418 12:21:07.855483 100 : 4360, 0
7419 12:21:07.855547 104 : 4252, 0
7420 12:21:07.858895 108 : 4253, 0
7421 12:21:07.858976 112 : 4360, 0
7422 12:21:07.862140 116 : 4250, 0
7423 12:21:07.862221 120 : 4250, 0
7424 12:21:07.862284 124 : 4250, 0
7425 12:21:07.865140 128 : 4250, 0
7426 12:21:07.865222 132 : 4250, 0
7427 12:21:07.868573 136 : 4250, 0
7428 12:21:07.868655 140 : 4250, 0
7429 12:21:07.868720 144 : 4252, 0
7430 12:21:07.871887 148 : 4253, 0
7431 12:21:07.871986 152 : 4250, 0
7432 12:21:07.872051 156 : 4252, 0
7433 12:21:07.875016 160 : 4252, 0
7434 12:21:07.875097 164 : 4360, 0
7435 12:21:07.878799 168 : 4360, 0
7436 12:21:07.878881 172 : 4250, 0
7437 12:21:07.878945 176 : 4250, 0
7438 12:21:07.881649 180 : 4250, 0
7439 12:21:07.881731 184 : 4250, 0
7440 12:21:07.885216 188 : 4250, 0
7441 12:21:07.885298 192 : 4250, 0
7442 12:21:07.885362 196 : 4252, 0
7443 12:21:07.888493 200 : 4253, 0
7444 12:21:07.888574 204 : 4250, 0
7445 12:21:07.891897 208 : 4363, 0
7446 12:21:07.892035 212 : 4363, 0
7447 12:21:07.892099 216 : 4360, 0
7448 12:21:07.894801 220 : 4363, 307
7449 12:21:07.894882 224 : 4252, 3932
7450 12:21:07.898209 228 : 4253, 4027
7451 12:21:07.898290 232 : 4249, 4027
7452 12:21:07.901528 236 : 4250, 4026
7453 12:21:07.901609 240 : 4252, 4027
7454 12:21:07.905199 244 : 4363, 4138
7455 12:21:07.905280 248 : 4250, 4027
7456 12:21:07.908497 252 : 4250, 4026
7457 12:21:07.908579 256 : 4361, 4137
7458 12:21:07.908644 260 : 4250, 4027
7459 12:21:07.911311 264 : 4250, 4027
7460 12:21:07.911392 268 : 4363, 4140
7461 12:21:07.914650 272 : 4250, 4026
7462 12:21:07.914730 276 : 4250, 4027
7463 12:21:07.918386 280 : 4250, 4027
7464 12:21:07.918468 284 : 4252, 4029
7465 12:21:07.921707 288 : 4250, 4026
7466 12:21:07.921806 292 : 4250, 4027
7467 12:21:07.924459 296 : 4360, 4138
7468 12:21:07.924540 300 : 4250, 4027
7469 12:21:07.927766 304 : 4250, 4026
7470 12:21:07.927846 308 : 4361, 4137
7471 12:21:07.932061 312 : 4250, 4027
7472 12:21:07.932142 316 : 4253, 4027
7473 12:21:07.934597 320 : 4362, 4140
7474 12:21:07.934678 324 : 4250, 4026
7475 12:21:07.937522 328 : 4250, 4027
7476 12:21:07.937603 332 : 4250, 4027
7477 12:21:07.937667 336 : 4252, 2291
7478 12:21:07.941254 340 : 4250, 71
7479 12:21:07.941335
7480 12:21:07.944547 MIOCK jitter meter ch=0
7481 12:21:07.944627
7482 12:21:07.944690 1T = (340-100) = 240 dly cells
7483 12:21:07.950751 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7484 12:21:07.950848 ==
7485 12:21:07.954164 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 12:21:07.961134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 12:21:07.961214 ==
7488 12:21:07.964229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 12:21:07.967336 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 12:21:07.973855 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 12:21:07.980793 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 12:21:07.988432 [CA 0] Center 44 (14~74) winsize 61
7493 12:21:07.991785 [CA 1] Center 43 (13~74) winsize 62
7494 12:21:07.995115 [CA 2] Center 38 (9~68) winsize 60
7495 12:21:07.998029 [CA 3] Center 38 (9~68) winsize 60
7496 12:21:08.001154 [CA 4] Center 36 (7~66) winsize 60
7497 12:21:08.004388 [CA 5] Center 36 (6~66) winsize 61
7498 12:21:08.004468
7499 12:21:08.008099 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 12:21:08.008179
7501 12:21:08.014910 [CATrainingPosCal] consider 1 rank data
7502 12:21:08.014989 u2DelayCellTimex100 = 271/100 ps
7503 12:21:08.021217 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7504 12:21:08.024695 CA1 delay=43 (13~74),Diff = 7 PI (25 cell)
7505 12:21:08.027799 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7506 12:21:08.030561 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7507 12:21:08.034316 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7508 12:21:08.037143 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7509 12:21:08.037223
7510 12:21:08.041157 CA PerBit enable=1, Macro0, CA PI delay=36
7511 12:21:08.041236
7512 12:21:08.043852 [CBTSetCACLKResult] CA Dly = 36
7513 12:21:08.047262 CS Dly: 11 (0~42)
7514 12:21:08.050430 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 12:21:08.054046 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 12:21:08.054126 ==
7517 12:21:08.056999 Dram Type= 6, Freq= 0, CH_0, rank 1
7518 12:21:08.063592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 12:21:08.063673 ==
7520 12:21:08.067036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 12:21:08.073525 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 12:21:08.076860 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 12:21:08.083306 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 12:21:08.091797 [CA 0] Center 44 (14~75) winsize 62
7525 12:21:08.094968 [CA 1] Center 44 (14~74) winsize 61
7526 12:21:08.098336 [CA 2] Center 39 (10~69) winsize 60
7527 12:21:08.101907 [CA 3] Center 39 (10~68) winsize 59
7528 12:21:08.104873 [CA 4] Center 37 (7~67) winsize 61
7529 12:21:08.108023 [CA 5] Center 36 (7~66) winsize 60
7530 12:21:08.108103
7531 12:21:08.111492 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7532 12:21:08.114617
7533 12:21:08.118144 [CATrainingPosCal] consider 2 rank data
7534 12:21:08.118224 u2DelayCellTimex100 = 271/100 ps
7535 12:21:08.124382 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7536 12:21:08.127737 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7537 12:21:08.130809 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7538 12:21:08.134246 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7539 12:21:08.137465 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7540 12:21:08.140673 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7541 12:21:08.140753
7542 12:21:08.144220 CA PerBit enable=1, Macro0, CA PI delay=36
7543 12:21:08.147577
7544 12:21:08.147656 [CBTSetCACLKResult] CA Dly = 36
7545 12:21:08.150729 CS Dly: 11 (0~43)
7546 12:21:08.153832 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 12:21:08.157694 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 12:21:08.160625
7549 12:21:08.163669 ----->DramcWriteLeveling(PI) begin...
7550 12:21:08.163750 ==
7551 12:21:08.167003 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 12:21:08.170500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 12:21:08.170581 ==
7554 12:21:08.173939 Write leveling (Byte 0): 34 => 34
7555 12:21:08.177209 Write leveling (Byte 1): 27 => 27
7556 12:21:08.180295 DramcWriteLeveling(PI) end<-----
7557 12:21:08.180375
7558 12:21:08.180437 ==
7559 12:21:08.183751 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 12:21:08.186884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 12:21:08.186964 ==
7562 12:21:08.190127 [Gating] SW mode calibration
7563 12:21:08.196790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7564 12:21:08.203069 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7565 12:21:08.206461 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 12:21:08.210260 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 12:21:08.217207 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 12:21:08.219656 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7569 12:21:08.222881 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7570 12:21:08.229660 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7571 12:21:08.232822 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7572 12:21:08.238958 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 12:21:08.242705 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 12:21:08.245959 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 12:21:08.252398 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7576 12:21:08.255869 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7577 12:21:08.258863 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7578 12:21:08.265292 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7579 12:21:08.268763 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7580 12:21:08.271944 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 12:21:08.278774 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 12:21:08.282105 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 12:21:08.285461 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7584 12:21:08.291670 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7585 12:21:08.294767 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7586 12:21:08.298236 1 6 20 | B1->B0 | 3a39 4646 | 1 0 | (1 1) (0 0)
7587 12:21:08.305167 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 12:21:08.308168 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 12:21:08.311666 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 12:21:08.317824 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 12:21:08.321739 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 12:21:08.324887 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 12:21:08.331139 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7594 12:21:08.334695 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 12:21:08.337873 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7596 12:21:08.344555 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 12:21:08.347900 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 12:21:08.350829 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 12:21:08.357678 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 12:21:08.361148 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 12:21:08.364196 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 12:21:08.370618 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 12:21:08.373745 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 12:21:08.377100 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 12:21:08.383832 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 12:21:08.387468 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 12:21:08.390697 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 12:21:08.397271 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7609 12:21:08.400306 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7610 12:21:08.403625 Total UI for P1: 0, mck2ui 16
7611 12:21:08.407057 best dqsien dly found for B0: ( 1, 9, 12)
7612 12:21:08.410517 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7613 12:21:08.416829 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7614 12:21:08.420112 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 12:21:08.423516 Total UI for P1: 0, mck2ui 16
7616 12:21:08.426751 best dqsien dly found for B1: ( 1, 9, 22)
7617 12:21:08.430180 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7618 12:21:08.433460 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7619 12:21:08.433540
7620 12:21:08.436564 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7621 12:21:08.440197 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7622 12:21:08.443337 [Gating] SW calibration Done
7623 12:21:08.443416 ==
7624 12:21:08.446734 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 12:21:08.453155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 12:21:08.453241 ==
7627 12:21:08.453305 RX Vref Scan: 0
7628 12:21:08.453365
7629 12:21:08.456587 RX Vref 0 -> 0, step: 1
7630 12:21:08.456668
7631 12:21:08.459859 RX Delay 0 -> 252, step: 8
7632 12:21:08.463135 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7633 12:21:08.466551 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7634 12:21:08.469771 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7635 12:21:08.472944 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7636 12:21:08.479830 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7637 12:21:08.482766 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7638 12:21:08.486026 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7639 12:21:08.489680 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7640 12:21:08.492989 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7641 12:21:08.499394 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7642 12:21:08.502630 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7643 12:21:08.506323 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7644 12:21:08.509594 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7645 12:21:08.512816 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7646 12:21:08.519204 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7647 12:21:08.522597 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7648 12:21:08.522677 ==
7649 12:21:08.525996 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 12:21:08.529133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 12:21:08.529213 ==
7652 12:21:08.532535 DQS Delay:
7653 12:21:08.532614 DQS0 = 0, DQS1 = 0
7654 12:21:08.532677 DQM Delay:
7655 12:21:08.535682 DQM0 = 131, DQM1 = 126
7656 12:21:08.535762 DQ Delay:
7657 12:21:08.539085 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7658 12:21:08.542537 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7659 12:21:08.548908 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7660 12:21:08.552004 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7661 12:21:08.552083
7662 12:21:08.552146
7663 12:21:08.552204 ==
7664 12:21:08.555475 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 12:21:08.558702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 12:21:08.558782 ==
7667 12:21:08.558845
7668 12:21:08.558903
7669 12:21:08.562120 TX Vref Scan disable
7670 12:21:08.566191 == TX Byte 0 ==
7671 12:21:08.568529 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7672 12:21:08.572013 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7673 12:21:08.575551 == TX Byte 1 ==
7674 12:21:08.578678 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7675 12:21:08.581842 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7676 12:21:08.581922 ==
7677 12:21:08.585319 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 12:21:08.591539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 12:21:08.591620 ==
7680 12:21:08.604617
7681 12:21:08.608261 TX Vref early break, caculate TX vref
7682 12:21:08.611844 TX Vref=16, minBit 1, minWin=21, winSum=368
7683 12:21:08.615108 TX Vref=18, minBit 8, minWin=22, winSum=380
7684 12:21:08.617910 TX Vref=20, minBit 1, minWin=23, winSum=388
7685 12:21:08.621294 TX Vref=22, minBit 1, minWin=23, winSum=401
7686 12:21:08.624554 TX Vref=24, minBit 7, minWin=24, winSum=410
7687 12:21:08.631333 TX Vref=26, minBit 1, minWin=25, winSum=416
7688 12:21:08.634445 TX Vref=28, minBit 2, minWin=25, winSum=421
7689 12:21:08.637520 TX Vref=30, minBit 2, minWin=25, winSum=420
7690 12:21:08.641267 TX Vref=32, minBit 4, minWin=24, winSum=409
7691 12:21:08.644319 TX Vref=34, minBit 7, minWin=23, winSum=401
7692 12:21:08.650735 TX Vref=36, minBit 2, minWin=23, winSum=388
7693 12:21:08.654239 [TxChooseVref] Worse bit 2, Min win 25, Win sum 421, Final Vref 28
7694 12:21:08.654319
7695 12:21:08.657432 Final TX Range 0 Vref 28
7696 12:21:08.657512
7697 12:21:08.657574 ==
7698 12:21:08.660825 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 12:21:08.664029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 12:21:08.667154 ==
7701 12:21:08.667234
7702 12:21:08.667296
7703 12:21:08.667354 TX Vref Scan disable
7704 12:21:08.673839 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7705 12:21:08.673918 == TX Byte 0 ==
7706 12:21:08.677347 u2DelayCellOfst[0]=14 cells (4 PI)
7707 12:21:08.681070 u2DelayCellOfst[1]=18 cells (5 PI)
7708 12:21:08.684246 u2DelayCellOfst[2]=14 cells (4 PI)
7709 12:21:08.687342 u2DelayCellOfst[3]=10 cells (3 PI)
7710 12:21:08.690632 u2DelayCellOfst[4]=10 cells (3 PI)
7711 12:21:08.694199 u2DelayCellOfst[5]=0 cells (0 PI)
7712 12:21:08.697545 u2DelayCellOfst[6]=21 cells (6 PI)
7713 12:21:08.700297 u2DelayCellOfst[7]=18 cells (5 PI)
7714 12:21:08.704094 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7715 12:21:08.710403 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7716 12:21:08.710483 == TX Byte 1 ==
7717 12:21:08.713523 u2DelayCellOfst[8]=0 cells (0 PI)
7718 12:21:08.716697 u2DelayCellOfst[9]=3 cells (1 PI)
7719 12:21:08.720264 u2DelayCellOfst[10]=7 cells (2 PI)
7720 12:21:08.723201 u2DelayCellOfst[11]=3 cells (1 PI)
7721 12:21:08.726852 u2DelayCellOfst[12]=10 cells (3 PI)
7722 12:21:08.730004 u2DelayCellOfst[13]=10 cells (3 PI)
7723 12:21:08.733370 u2DelayCellOfst[14]=14 cells (4 PI)
7724 12:21:08.736501 u2DelayCellOfst[15]=10 cells (3 PI)
7725 12:21:08.739508 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7726 12:21:08.743250 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7727 12:21:08.746725 DramC Write-DBI on
7728 12:21:08.746804 ==
7729 12:21:08.749660 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 12:21:08.753250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 12:21:08.753330 ==
7732 12:21:08.753393
7733 12:21:08.753451
7734 12:21:08.756330 TX Vref Scan disable
7735 12:21:08.759563 == TX Byte 0 ==
7736 12:21:08.762659 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7737 12:21:08.762740 == TX Byte 1 ==
7738 12:21:08.769360 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7739 12:21:08.769440 DramC Write-DBI off
7740 12:21:08.769503
7741 12:21:08.772631 [DATLAT]
7742 12:21:08.772711 Freq=1600, CH0 RK0
7743 12:21:08.772775
7744 12:21:08.775781 DATLAT Default: 0xf
7745 12:21:08.775886 0, 0xFFFF, sum = 0
7746 12:21:08.779107 1, 0xFFFF, sum = 0
7747 12:21:08.779188 2, 0xFFFF, sum = 0
7748 12:21:08.782398 3, 0xFFFF, sum = 0
7749 12:21:08.782479 4, 0xFFFF, sum = 0
7750 12:21:08.785871 5, 0xFFFF, sum = 0
7751 12:21:08.785952 6, 0xFFFF, sum = 0
7752 12:21:08.788881 7, 0xFFFF, sum = 0
7753 12:21:08.788989 8, 0xFFFF, sum = 0
7754 12:21:08.792622 9, 0xFFFF, sum = 0
7755 12:21:08.792703 10, 0xFFFF, sum = 0
7756 12:21:08.795659 11, 0xFFFF, sum = 0
7757 12:21:08.799152 12, 0xFFFF, sum = 0
7758 12:21:08.799234 13, 0xFFFF, sum = 0
7759 12:21:08.802214 14, 0x0, sum = 1
7760 12:21:08.802295 15, 0x0, sum = 2
7761 12:21:08.806017 16, 0x0, sum = 3
7762 12:21:08.806099 17, 0x0, sum = 4
7763 12:21:08.806163 best_step = 15
7764 12:21:08.806221
7765 12:21:08.808760 ==
7766 12:21:08.812070 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 12:21:08.815240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 12:21:08.815320 ==
7769 12:21:08.815384 RX Vref Scan: 1
7770 12:21:08.815442
7771 12:21:08.818431 Set Vref Range= 24 -> 127
7772 12:21:08.818556
7773 12:21:08.821772 RX Vref 24 -> 127, step: 1
7774 12:21:08.821870
7775 12:21:08.825146 RX Delay 11 -> 252, step: 4
7776 12:21:08.825233
7777 12:21:08.828534 Set Vref, RX VrefLevel [Byte0]: 24
7778 12:21:08.832455 [Byte1]: 24
7779 12:21:08.832535
7780 12:21:08.835206 Set Vref, RX VrefLevel [Byte0]: 25
7781 12:21:08.838649 [Byte1]: 25
7782 12:21:08.838729
7783 12:21:08.841936 Set Vref, RX VrefLevel [Byte0]: 26
7784 12:21:08.844936 [Byte1]: 26
7785 12:21:08.848864
7786 12:21:08.848944 Set Vref, RX VrefLevel [Byte0]: 27
7787 12:21:08.852047 [Byte1]: 27
7788 12:21:08.856098
7789 12:21:08.856177 Set Vref, RX VrefLevel [Byte0]: 28
7790 12:21:08.859360 [Byte1]: 28
7791 12:21:08.863837
7792 12:21:08.863922 Set Vref, RX VrefLevel [Byte0]: 29
7793 12:21:08.867219 [Byte1]: 29
7794 12:21:08.871261
7795 12:21:08.871340 Set Vref, RX VrefLevel [Byte0]: 30
7796 12:21:08.874994 [Byte1]: 30
7797 12:21:08.878933
7798 12:21:08.879012 Set Vref, RX VrefLevel [Byte0]: 31
7799 12:21:08.882414 [Byte1]: 31
7800 12:21:08.886665
7801 12:21:08.886745 Set Vref, RX VrefLevel [Byte0]: 32
7802 12:21:08.889943 [Byte1]: 32
7803 12:21:08.894333
7804 12:21:08.894412 Set Vref, RX VrefLevel [Byte0]: 33
7805 12:21:08.897518 [Byte1]: 33
7806 12:21:08.902117
7807 12:21:08.902196 Set Vref, RX VrefLevel [Byte0]: 34
7808 12:21:08.905997 [Byte1]: 34
7809 12:21:08.909520
7810 12:21:08.909602 Set Vref, RX VrefLevel [Byte0]: 35
7811 12:21:08.913539 [Byte1]: 35
7812 12:21:08.917426
7813 12:21:08.917515 Set Vref, RX VrefLevel [Byte0]: 36
7814 12:21:08.920323 [Byte1]: 36
7815 12:21:08.924878
7816 12:21:08.924959 Set Vref, RX VrefLevel [Byte0]: 37
7817 12:21:08.928897 [Byte1]: 37
7818 12:21:08.932268
7819 12:21:08.932348 Set Vref, RX VrefLevel [Byte0]: 38
7820 12:21:08.935844 [Byte1]: 38
7821 12:21:08.939898
7822 12:21:08.940017 Set Vref, RX VrefLevel [Byte0]: 39
7823 12:21:08.943285 [Byte1]: 39
7824 12:21:08.947700
7825 12:21:08.947796 Set Vref, RX VrefLevel [Byte0]: 40
7826 12:21:08.950990 [Byte1]: 40
7827 12:21:08.955726
7828 12:21:08.955831 Set Vref, RX VrefLevel [Byte0]: 41
7829 12:21:08.958796 [Byte1]: 41
7830 12:21:08.962739
7831 12:21:08.962817 Set Vref, RX VrefLevel [Byte0]: 42
7832 12:21:08.966302 [Byte1]: 42
7833 12:21:08.970327
7834 12:21:08.970406 Set Vref, RX VrefLevel [Byte0]: 43
7835 12:21:08.974021 [Byte1]: 43
7836 12:21:08.978670
7837 12:21:08.978750 Set Vref, RX VrefLevel [Byte0]: 44
7838 12:21:08.981162 [Byte1]: 44
7839 12:21:08.985786
7840 12:21:08.985865 Set Vref, RX VrefLevel [Byte0]: 45
7841 12:21:08.988771 [Byte1]: 45
7842 12:21:08.994142
7843 12:21:08.994221 Set Vref, RX VrefLevel [Byte0]: 46
7844 12:21:08.996584 [Byte1]: 46
7845 12:21:09.000965
7846 12:21:09.001045 Set Vref, RX VrefLevel [Byte0]: 47
7847 12:21:09.004140 [Byte1]: 47
7848 12:21:09.008359
7849 12:21:09.008439 Set Vref, RX VrefLevel [Byte0]: 48
7850 12:21:09.011651 [Byte1]: 48
7851 12:21:09.016296
7852 12:21:09.016375 Set Vref, RX VrefLevel [Byte0]: 49
7853 12:21:09.019772 [Byte1]: 49
7854 12:21:09.023870
7855 12:21:09.024022 Set Vref, RX VrefLevel [Byte0]: 50
7856 12:21:09.026889 [Byte1]: 50
7857 12:21:09.031319
7858 12:21:09.031398 Set Vref, RX VrefLevel [Byte0]: 51
7859 12:21:09.034408 [Byte1]: 51
7860 12:21:09.039038
7861 12:21:09.039117 Set Vref, RX VrefLevel [Byte0]: 52
7862 12:21:09.042569 [Byte1]: 52
7863 12:21:09.046370
7864 12:21:09.046449 Set Vref, RX VrefLevel [Byte0]: 53
7865 12:21:09.049585 [Byte1]: 53
7866 12:21:09.054300
7867 12:21:09.054380 Set Vref, RX VrefLevel [Byte0]: 54
7868 12:21:09.058315 [Byte1]: 54
7869 12:21:09.062072
7870 12:21:09.062151 Set Vref, RX VrefLevel [Byte0]: 55
7871 12:21:09.065561 [Byte1]: 55
7872 12:21:09.069900
7873 12:21:09.069982 Set Vref, RX VrefLevel [Byte0]: 56
7874 12:21:09.072707 [Byte1]: 56
7875 12:21:09.077437
7876 12:21:09.077516 Set Vref, RX VrefLevel [Byte0]: 57
7877 12:21:09.080376 [Byte1]: 57
7878 12:21:09.084367
7879 12:21:09.084446 Set Vref, RX VrefLevel [Byte0]: 58
7880 12:21:09.087864 [Byte1]: 58
7881 12:21:09.092045
7882 12:21:09.092124 Set Vref, RX VrefLevel [Byte0]: 59
7883 12:21:09.095491 [Byte1]: 59
7884 12:21:09.099747
7885 12:21:09.099852 Set Vref, RX VrefLevel [Byte0]: 60
7886 12:21:09.103055 [Byte1]: 60
7887 12:21:09.107342
7888 12:21:09.107422 Set Vref, RX VrefLevel [Byte0]: 61
7889 12:21:09.111040 [Byte1]: 61
7890 12:21:09.115009
7891 12:21:09.115088 Set Vref, RX VrefLevel [Byte0]: 62
7892 12:21:09.118684 [Byte1]: 62
7893 12:21:09.122570
7894 12:21:09.122649 Set Vref, RX VrefLevel [Byte0]: 63
7895 12:21:09.125991 [Byte1]: 63
7896 12:21:09.130215
7897 12:21:09.130294 Set Vref, RX VrefLevel [Byte0]: 64
7898 12:21:09.133508 [Byte1]: 64
7899 12:21:09.138175
7900 12:21:09.138255 Set Vref, RX VrefLevel [Byte0]: 65
7901 12:21:09.141467 [Byte1]: 65
7902 12:21:09.145506
7903 12:21:09.145585 Set Vref, RX VrefLevel [Byte0]: 66
7904 12:21:09.149131 [Byte1]: 66
7905 12:21:09.153252
7906 12:21:09.153332 Set Vref, RX VrefLevel [Byte0]: 67
7907 12:21:09.156198 [Byte1]: 67
7908 12:21:09.160594
7909 12:21:09.160673 Set Vref, RX VrefLevel [Byte0]: 68
7910 12:21:09.163814 [Byte1]: 68
7911 12:21:09.168491
7912 12:21:09.168570 Set Vref, RX VrefLevel [Byte0]: 69
7913 12:21:09.172125 [Byte1]: 69
7914 12:21:09.176350
7915 12:21:09.176430 Set Vref, RX VrefLevel [Byte0]: 70
7916 12:21:09.179433 [Byte1]: 70
7917 12:21:09.183637
7918 12:21:09.183716 Set Vref, RX VrefLevel [Byte0]: 71
7919 12:21:09.186815 [Byte1]: 71
7920 12:21:09.191028
7921 12:21:09.191108 Set Vref, RX VrefLevel [Byte0]: 72
7922 12:21:09.194633 [Byte1]: 72
7923 12:21:09.199070
7924 12:21:09.199149 Set Vref, RX VrefLevel [Byte0]: 73
7925 12:21:09.202096 [Byte1]: 73
7926 12:21:09.206645
7927 12:21:09.206725 Set Vref, RX VrefLevel [Byte0]: 74
7928 12:21:09.209773 [Byte1]: 74
7929 12:21:09.213829
7930 12:21:09.213909 Set Vref, RX VrefLevel [Byte0]: 75
7931 12:21:09.217276 [Byte1]: 75
7932 12:21:09.221688
7933 12:21:09.221767 Final RX Vref Byte 0 = 60 to rank0
7934 12:21:09.224927 Final RX Vref Byte 1 = 60 to rank0
7935 12:21:09.228284 Final RX Vref Byte 0 = 60 to rank1
7936 12:21:09.231446 Final RX Vref Byte 1 = 60 to rank1==
7937 12:21:09.234605 Dram Type= 6, Freq= 0, CH_0, rank 0
7938 12:21:09.241387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 12:21:09.241468 ==
7940 12:21:09.241531 DQS Delay:
7941 12:21:09.244727 DQS0 = 0, DQS1 = 0
7942 12:21:09.244807 DQM Delay:
7943 12:21:09.244869 DQM0 = 129, DQM1 = 123
7944 12:21:09.247957 DQ Delay:
7945 12:21:09.251184 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7946 12:21:09.255228 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
7947 12:21:09.258029 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7948 12:21:09.260858 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7949 12:21:09.260938
7950 12:21:09.261000
7951 12:21:09.261058
7952 12:21:09.264685 [DramC_TX_OE_Calibration] TA2
7953 12:21:09.267942 Original DQ_B0 (3 6) =30, OEN = 27
7954 12:21:09.270763 Original DQ_B1 (3 6) =30, OEN = 27
7955 12:21:09.274047 24, 0x0, End_B0=24 End_B1=24
7956 12:21:09.277899 25, 0x0, End_B0=25 End_B1=25
7957 12:21:09.277980 26, 0x0, End_B0=26 End_B1=26
7958 12:21:09.280600 27, 0x0, End_B0=27 End_B1=27
7959 12:21:09.284141 28, 0x0, End_B0=28 End_B1=28
7960 12:21:09.287513 29, 0x0, End_B0=29 End_B1=29
7961 12:21:09.290512 30, 0x0, End_B0=30 End_B1=30
7962 12:21:09.290593 31, 0x4141, End_B0=30 End_B1=30
7963 12:21:09.294157 Byte0 end_step=30 best_step=27
7964 12:21:09.297298 Byte1 end_step=30 best_step=27
7965 12:21:09.300500 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 12:21:09.303629 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 12:21:09.303708
7968 12:21:09.303770
7969 12:21:09.310128 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7970 12:21:09.313747 CH0 RK0: MR19=303, MR18=1916
7971 12:21:09.320141 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7972 12:21:09.320222
7973 12:21:09.323421 ----->DramcWriteLeveling(PI) begin...
7974 12:21:09.323502 ==
7975 12:21:09.326756 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 12:21:09.329847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 12:21:09.333698 ==
7978 12:21:09.333778 Write leveling (Byte 0): 33 => 33
7979 12:21:09.336786 Write leveling (Byte 1): 26 => 26
7980 12:21:09.340366 DramcWriteLeveling(PI) end<-----
7981 12:21:09.340445
7982 12:21:09.340508 ==
7983 12:21:09.343046 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 12:21:09.350098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 12:21:09.350177 ==
7986 12:21:09.353201 [Gating] SW mode calibration
7987 12:21:09.359760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7988 12:21:09.362944 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7989 12:21:09.369861 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 12:21:09.372523 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 12:21:09.376510 1 4 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7992 12:21:09.382624 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7993 12:21:09.386138 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7994 12:21:09.389003 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 12:21:09.396552 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 12:21:09.398983 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 12:21:09.402717 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 12:21:09.409211 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7999 12:21:09.412501 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
8000 12:21:09.415450 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8001 12:21:09.422364 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8002 12:21:09.425753 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8003 12:21:09.429003 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 12:21:09.435414 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 12:21:09.438655 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 12:21:09.441920 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 12:21:09.448600 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8008 12:21:09.451923 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8009 12:21:09.455222 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8010 12:21:09.462004 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8011 12:21:09.465186 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 12:21:09.468211 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 12:21:09.475413 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 12:21:09.478300 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 12:21:09.481392 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8016 12:21:09.488061 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8017 12:21:09.491235 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8018 12:21:09.495053 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8019 12:21:09.501372 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8020 12:21:09.504889 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 12:21:09.507716 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 12:21:09.515232 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 12:21:09.518003 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 12:21:09.521048 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 12:21:09.527386 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 12:21:09.530952 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 12:21:09.534107 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 12:21:09.540605 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 12:21:09.544142 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 12:21:09.547672 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8031 12:21:09.554379 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8032 12:21:09.557095 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8033 12:21:09.560517 Total UI for P1: 0, mck2ui 16
8034 12:21:09.563715 best dqsien dly found for B0: ( 1, 9, 6)
8035 12:21:09.567291 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8036 12:21:09.573371 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8037 12:21:09.577204 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8038 12:21:09.580321 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 12:21:09.583392 Total UI for P1: 0, mck2ui 16
8040 12:21:09.586503 best dqsien dly found for B1: ( 1, 9, 20)
8041 12:21:09.590069 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8042 12:21:09.593040 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8043 12:21:09.593120
8044 12:21:09.599647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8045 12:21:09.603015 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8046 12:21:09.606664 [Gating] SW calibration Done
8047 12:21:09.606745 ==
8048 12:21:09.609532 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 12:21:09.612889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 12:21:09.612969 ==
8051 12:21:09.613033 RX Vref Scan: 0
8052 12:21:09.616121
8053 12:21:09.616210 RX Vref 0 -> 0, step: 1
8054 12:21:09.616273
8055 12:21:09.619625 RX Delay 0 -> 252, step: 8
8056 12:21:09.622647 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8057 12:21:09.626621 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8058 12:21:09.633247 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8059 12:21:09.636174 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8060 12:21:09.639450 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8061 12:21:09.642758 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8062 12:21:09.645899 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8063 12:21:09.652463 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8064 12:21:09.655793 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8065 12:21:09.658939 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8066 12:21:09.662122 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8067 12:21:09.666163 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8068 12:21:09.672504 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8069 12:21:09.675646 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8070 12:21:09.679021 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8071 12:21:09.682209 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8072 12:21:09.685586 ==
8073 12:21:09.688465 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 12:21:09.692231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 12:21:09.692312 ==
8076 12:21:09.692375 DQS Delay:
8077 12:21:09.695131 DQS0 = 0, DQS1 = 0
8078 12:21:09.695211 DQM Delay:
8079 12:21:09.698288 DQM0 = 131, DQM1 = 127
8080 12:21:09.698406 DQ Delay:
8081 12:21:09.701776 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8082 12:21:09.705238 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8083 12:21:09.708142 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8084 12:21:09.711892 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8085 12:21:09.711995
8086 12:21:09.712058
8087 12:21:09.712116 ==
8088 12:21:09.714949 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 12:21:09.722053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 12:21:09.722134 ==
8091 12:21:09.722196
8092 12:21:09.722254
8093 12:21:09.724727 TX Vref Scan disable
8094 12:21:09.724806 == TX Byte 0 ==
8095 12:21:09.728052 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8096 12:21:09.734550 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8097 12:21:09.734632 == TX Byte 1 ==
8098 12:21:09.737936 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8099 12:21:09.744766 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8100 12:21:09.744846 ==
8101 12:21:09.747867 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 12:21:09.751173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 12:21:09.751253 ==
8104 12:21:09.765131
8105 12:21:09.768177 TX Vref early break, caculate TX vref
8106 12:21:09.771977 TX Vref=16, minBit 1, minWin=23, winSum=378
8107 12:21:09.774840 TX Vref=18, minBit 9, minWin=23, winSum=387
8108 12:21:09.777938 TX Vref=20, minBit 9, minWin=23, winSum=393
8109 12:21:09.781240 TX Vref=22, minBit 1, minWin=25, winSum=408
8110 12:21:09.784771 TX Vref=24, minBit 1, minWin=25, winSum=411
8111 12:21:09.791246 TX Vref=26, minBit 4, minWin=25, winSum=420
8112 12:21:09.794932 TX Vref=28, minBit 4, minWin=25, winSum=419
8113 12:21:09.797832 TX Vref=30, minBit 1, minWin=25, winSum=417
8114 12:21:09.801225 TX Vref=32, minBit 1, minWin=24, winSum=406
8115 12:21:09.804470 TX Vref=34, minBit 1, minWin=24, winSum=398
8116 12:21:09.810954 [TxChooseVref] Worse bit 4, Min win 25, Win sum 420, Final Vref 26
8117 12:21:09.811035
8118 12:21:09.814183 Final TX Range 0 Vref 26
8119 12:21:09.814263
8120 12:21:09.814325 ==
8121 12:21:09.817888 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 12:21:09.820864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 12:21:09.820944 ==
8124 12:21:09.821007
8125 12:21:09.821064
8126 12:21:09.824524 TX Vref Scan disable
8127 12:21:09.831096 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8128 12:21:09.831177 == TX Byte 0 ==
8129 12:21:09.833966 u2DelayCellOfst[0]=14 cells (4 PI)
8130 12:21:09.837334 u2DelayCellOfst[1]=18 cells (5 PI)
8131 12:21:09.840782 u2DelayCellOfst[2]=10 cells (3 PI)
8132 12:21:09.844154 u2DelayCellOfst[3]=14 cells (4 PI)
8133 12:21:09.847146 u2DelayCellOfst[4]=10 cells (3 PI)
8134 12:21:09.850236 u2DelayCellOfst[5]=0 cells (0 PI)
8135 12:21:09.853668 u2DelayCellOfst[6]=18 cells (5 PI)
8136 12:21:09.857496 u2DelayCellOfst[7]=18 cells (5 PI)
8137 12:21:09.860680 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8138 12:21:09.864137 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8139 12:21:09.867282 == TX Byte 1 ==
8140 12:21:09.870438 u2DelayCellOfst[8]=0 cells (0 PI)
8141 12:21:09.873652 u2DelayCellOfst[9]=0 cells (0 PI)
8142 12:21:09.876589 u2DelayCellOfst[10]=3 cells (1 PI)
8143 12:21:09.879946 u2DelayCellOfst[11]=3 cells (1 PI)
8144 12:21:09.883627 u2DelayCellOfst[12]=7 cells (2 PI)
8145 12:21:09.883706 u2DelayCellOfst[13]=7 cells (2 PI)
8146 12:21:09.886940 u2DelayCellOfst[14]=14 cells (4 PI)
8147 12:21:09.889690 u2DelayCellOfst[15]=10 cells (3 PI)
8148 12:21:09.896637 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8149 12:21:09.899841 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8150 12:21:09.903002 DramC Write-DBI on
8151 12:21:09.903085 ==
8152 12:21:09.906339 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 12:21:09.909634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 12:21:09.909715 ==
8155 12:21:09.909778
8156 12:21:09.909837
8157 12:21:09.912883 TX Vref Scan disable
8158 12:21:09.912964 == TX Byte 0 ==
8159 12:21:09.919539 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8160 12:21:09.919619 == TX Byte 1 ==
8161 12:21:09.922735 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8162 12:21:09.926067 DramC Write-DBI off
8163 12:21:09.926146
8164 12:21:09.926208 [DATLAT]
8165 12:21:09.929411 Freq=1600, CH0 RK1
8166 12:21:09.929492
8167 12:21:09.929555 DATLAT Default: 0xf
8168 12:21:09.932430 0, 0xFFFF, sum = 0
8169 12:21:09.935592 1, 0xFFFF, sum = 0
8170 12:21:09.935699 2, 0xFFFF, sum = 0
8171 12:21:09.939423 3, 0xFFFF, sum = 0
8172 12:21:09.939504 4, 0xFFFF, sum = 0
8173 12:21:09.942560 5, 0xFFFF, sum = 0
8174 12:21:09.942640 6, 0xFFFF, sum = 0
8175 12:21:09.945633 7, 0xFFFF, sum = 0
8176 12:21:09.945715 8, 0xFFFF, sum = 0
8177 12:21:09.948987 9, 0xFFFF, sum = 0
8178 12:21:09.949068 10, 0xFFFF, sum = 0
8179 12:21:09.952215 11, 0xFFFF, sum = 0
8180 12:21:09.952296 12, 0xFFFF, sum = 0
8181 12:21:09.955767 13, 0xFFFF, sum = 0
8182 12:21:09.955851 14, 0x0, sum = 1
8183 12:21:09.959051 15, 0x0, sum = 2
8184 12:21:09.959131 16, 0x0, sum = 3
8185 12:21:09.962012 17, 0x0, sum = 4
8186 12:21:09.962093 best_step = 15
8187 12:21:09.962156
8188 12:21:09.962215 ==
8189 12:21:09.965743 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 12:21:09.972390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 12:21:09.972471 ==
8192 12:21:09.972533 RX Vref Scan: 0
8193 12:21:09.972591
8194 12:21:09.975816 RX Vref 0 -> 0, step: 1
8195 12:21:09.975918
8196 12:21:09.979074 RX Delay 11 -> 252, step: 4
8197 12:21:09.982661 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8198 12:21:09.985580 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8199 12:21:09.988853 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8200 12:21:09.995752 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8201 12:21:09.998416 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8202 12:21:10.002192 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8203 12:21:10.004949 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8204 12:21:10.008835 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8205 12:21:10.015425 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8206 12:21:10.018403 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8207 12:21:10.021991 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8208 12:21:10.024960 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8209 12:21:10.031702 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8210 12:21:10.035238 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8211 12:21:10.038212 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8212 12:21:10.041762 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8213 12:21:10.041841 ==
8214 12:21:10.045269 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 12:21:10.051700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 12:21:10.051780 ==
8217 12:21:10.051844 DQS Delay:
8218 12:21:10.051909 DQS0 = 0, DQS1 = 0
8219 12:21:10.054510 DQM Delay:
8220 12:21:10.054592 DQM0 = 128, DQM1 = 123
8221 12:21:10.058080 DQ Delay:
8222 12:21:10.061539 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8223 12:21:10.064490 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
8224 12:21:10.067841 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8225 12:21:10.070951 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8226 12:21:10.071031
8227 12:21:10.071093
8228 12:21:10.071151
8229 12:21:10.074309 [DramC_TX_OE_Calibration] TA2
8230 12:21:10.077970 Original DQ_B0 (3 6) =30, OEN = 27
8231 12:21:10.081123 Original DQ_B1 (3 6) =30, OEN = 27
8232 12:21:10.084211 24, 0x0, End_B0=24 End_B1=24
8233 12:21:10.084319 25, 0x0, End_B0=25 End_B1=25
8234 12:21:10.087683 26, 0x0, End_B0=26 End_B1=26
8235 12:21:10.091492 27, 0x0, End_B0=27 End_B1=27
8236 12:21:10.094187 28, 0x0, End_B0=28 End_B1=28
8237 12:21:10.097389 29, 0x0, End_B0=29 End_B1=29
8238 12:21:10.097497 30, 0x0, End_B0=30 End_B1=30
8239 12:21:10.100510 31, 0x4545, End_B0=30 End_B1=30
8240 12:21:10.104324 Byte0 end_step=30 best_step=27
8241 12:21:10.107421 Byte1 end_step=30 best_step=27
8242 12:21:10.110826 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 12:21:10.114127 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 12:21:10.114207
8245 12:21:10.114269
8246 12:21:10.120506 [DQSOSCAuto] RK1, (LSB)MR18= 0x110f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8247 12:21:10.123799 CH0 RK1: MR19=303, MR18=110F
8248 12:21:10.130549 CH0_RK1: MR19=0x303, MR18=0x110F, DQSOSC=401, MR23=63, INC=22, DEC=15
8249 12:21:10.133462 [RxdqsGatingPostProcess] freq 1600
8250 12:21:10.140169 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8251 12:21:10.140249 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 12:21:10.143661 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 12:21:10.146723 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 12:21:10.150110 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 12:21:10.153138 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 12:21:10.156480 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 12:21:10.159777 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 12:21:10.163391 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 12:21:10.166435 Pre-setting of DQS Precalculation
8260 12:21:10.169900 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8261 12:21:10.169980 ==
8262 12:21:10.172853 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 12:21:10.179463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 12:21:10.179543 ==
8265 12:21:10.183012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 12:21:10.189720 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 12:21:10.192473 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 12:21:10.199560 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 12:21:10.207876 [CA 0] Center 42 (12~72) winsize 61
8270 12:21:10.210641 [CA 1] Center 42 (12~72) winsize 61
8271 12:21:10.214237 [CA 2] Center 38 (9~67) winsize 59
8272 12:21:10.217712 [CA 3] Center 37 (8~66) winsize 59
8273 12:21:10.221039 [CA 4] Center 37 (8~67) winsize 60
8274 12:21:10.224207 [CA 5] Center 36 (6~66) winsize 61
8275 12:21:10.224287
8276 12:21:10.227360 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8277 12:21:10.227440
8278 12:21:10.230345 [CATrainingPosCal] consider 1 rank data
8279 12:21:10.234086 u2DelayCellTimex100 = 271/100 ps
8280 12:21:10.240724 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8281 12:21:10.243845 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8282 12:21:10.246950 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8283 12:21:10.250236 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8284 12:21:10.253551 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8285 12:21:10.256827 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8286 12:21:10.256907
8287 12:21:10.260808 CA PerBit enable=1, Macro0, CA PI delay=36
8288 12:21:10.260888
8289 12:21:10.263727 [CBTSetCACLKResult] CA Dly = 36
8290 12:21:10.266640 CS Dly: 8 (0~39)
8291 12:21:10.270034 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 12:21:10.273767 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 12:21:10.273847 ==
8294 12:21:10.276749 Dram Type= 6, Freq= 0, CH_1, rank 1
8295 12:21:10.280345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 12:21:10.283541 ==
8297 12:21:10.287048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 12:21:10.290392 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 12:21:10.296997 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 12:21:10.303501 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 12:21:10.310615 [CA 0] Center 42 (12~72) winsize 61
8302 12:21:10.313683 [CA 1] Center 43 (14~72) winsize 59
8303 12:21:10.317110 [CA 2] Center 38 (8~68) winsize 61
8304 12:21:10.320504 [CA 3] Center 37 (7~67) winsize 61
8305 12:21:10.323970 [CA 4] Center 37 (8~67) winsize 60
8306 12:21:10.327221 [CA 5] Center 37 (7~67) winsize 61
8307 12:21:10.327301
8308 12:21:10.330192 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8309 12:21:10.330271
8310 12:21:10.334394 [CATrainingPosCal] consider 2 rank data
8311 12:21:10.337018 u2DelayCellTimex100 = 271/100 ps
8312 12:21:10.343602 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8313 12:21:10.346806 CA1 delay=43 (14~72),Diff = 7 PI (25 cell)
8314 12:21:10.350391 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8315 12:21:10.353201 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8316 12:21:10.356468 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8317 12:21:10.359848 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8318 12:21:10.359982
8319 12:21:10.363256 CA PerBit enable=1, Macro0, CA PI delay=36
8320 12:21:10.363335
8321 12:21:10.366654 [CBTSetCACLKResult] CA Dly = 36
8322 12:21:10.369870 CS Dly: 9 (0~42)
8323 12:21:10.373044 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 12:21:10.376691 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 12:21:10.376770
8326 12:21:10.379658 ----->DramcWriteLeveling(PI) begin...
8327 12:21:10.379764 ==
8328 12:21:10.383080 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 12:21:10.389476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 12:21:10.389592 ==
8331 12:21:10.392902 Write leveling (Byte 0): 24 => 24
8332 12:21:10.395981 Write leveling (Byte 1): 27 => 27
8333 12:21:10.396062 DramcWriteLeveling(PI) end<-----
8334 12:21:10.399448
8335 12:21:10.399545 ==
8336 12:21:10.403269 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 12:21:10.406207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 12:21:10.406287 ==
8339 12:21:10.409276 [Gating] SW mode calibration
8340 12:21:10.416070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8341 12:21:10.419401 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8342 12:21:10.425918 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 12:21:10.428959 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 12:21:10.432372 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 12:21:10.438971 1 4 12 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
8346 12:21:10.442076 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 12:21:10.445469 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 12:21:10.452263 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 12:21:10.455204 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 12:21:10.458588 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 12:21:10.465349 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 12:21:10.468511 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8353 12:21:10.472155 1 5 12 | B1->B0 | 3131 2424 | 0 0 | (0 1) (1 0)
8354 12:21:10.478277 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8355 12:21:10.481941 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 12:21:10.488077 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 12:21:10.492992 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 12:21:10.494739 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 12:21:10.502003 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 12:21:10.504656 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8361 12:21:10.508183 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
8362 12:21:10.514544 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 12:21:10.517696 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 12:21:10.521394 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 12:21:10.527942 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 12:21:10.531108 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 12:21:10.534513 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 12:21:10.540929 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 12:21:10.544455 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8370 12:21:10.547432 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 12:21:10.554345 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 12:21:10.557878 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 12:21:10.561171 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 12:21:10.567247 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 12:21:10.570383 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 12:21:10.574275 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 12:21:10.580381 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 12:21:10.583839 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 12:21:10.587338 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 12:21:10.593952 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 12:21:10.596963 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 12:21:10.599843 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 12:21:10.606922 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 12:21:10.610183 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8385 12:21:10.613071 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8386 12:21:10.619954 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8387 12:21:10.620037 Total UI for P1: 0, mck2ui 16
8388 12:21:10.627003 best dqsien dly found for B0: ( 1, 9, 10)
8389 12:21:10.630311 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 12:21:10.632931 Total UI for P1: 0, mck2ui 16
8391 12:21:10.636419 best dqsien dly found for B1: ( 1, 9, 14)
8392 12:21:10.640433 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8393 12:21:10.643239 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8394 12:21:10.643321
8395 12:21:10.646515 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8396 12:21:10.649609 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8397 12:21:10.652942 [Gating] SW calibration Done
8398 12:21:10.653023 ==
8399 12:21:10.656385 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 12:21:10.659374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 12:21:10.662816 ==
8402 12:21:10.662897 RX Vref Scan: 0
8403 12:21:10.662961
8404 12:21:10.666458 RX Vref 0 -> 0, step: 1
8405 12:21:10.666539
8406 12:21:10.669374 RX Delay 0 -> 252, step: 8
8407 12:21:10.673052 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8408 12:21:10.676474 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8409 12:21:10.679209 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8410 12:21:10.682663 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8411 12:21:10.689589 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8412 12:21:10.692300 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8413 12:21:10.695823 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8414 12:21:10.699183 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8415 12:21:10.702450 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8416 12:21:10.708806 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8417 12:21:10.712183 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8418 12:21:10.715914 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8419 12:21:10.718931 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8420 12:21:10.722564 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8421 12:21:10.729111 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8422 12:21:10.732113 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8423 12:21:10.732194 ==
8424 12:21:10.735928 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 12:21:10.738446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 12:21:10.738528 ==
8427 12:21:10.741807 DQS Delay:
8428 12:21:10.741888 DQS0 = 0, DQS1 = 0
8429 12:21:10.745171 DQM Delay:
8430 12:21:10.745252 DQM0 = 135, DQM1 = 129
8431 12:21:10.745317 DQ Delay:
8432 12:21:10.748746 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8433 12:21:10.755661 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8434 12:21:10.758609 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =127
8435 12:21:10.761738 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8436 12:21:10.761820
8437 12:21:10.761883
8438 12:21:10.761942 ==
8439 12:21:10.764878 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 12:21:10.768650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 12:21:10.768732 ==
8442 12:21:10.768796
8443 12:21:10.768855
8444 12:21:10.771268 TX Vref Scan disable
8445 12:21:10.774714 == TX Byte 0 ==
8446 12:21:10.778106 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8447 12:21:10.781232 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8448 12:21:10.784573 == TX Byte 1 ==
8449 12:21:10.788200 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8450 12:21:10.791076 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8451 12:21:10.791157 ==
8452 12:21:10.794456 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 12:21:10.800947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 12:21:10.801029 ==
8455 12:21:10.812636
8456 12:21:10.816695 TX Vref early break, caculate TX vref
8457 12:21:10.819284 TX Vref=16, minBit 8, minWin=21, winSum=368
8458 12:21:10.822698 TX Vref=18, minBit 8, minWin=22, winSum=379
8459 12:21:10.825713 TX Vref=20, minBit 8, minWin=23, winSum=384
8460 12:21:10.829202 TX Vref=22, minBit 8, minWin=23, winSum=394
8461 12:21:10.832509 TX Vref=24, minBit 8, minWin=24, winSum=403
8462 12:21:10.839630 TX Vref=26, minBit 0, minWin=25, winSum=412
8463 12:21:10.842371 TX Vref=28, minBit 0, minWin=25, winSum=419
8464 12:21:10.845494 TX Vref=30, minBit 9, minWin=24, winSum=411
8465 12:21:10.849205 TX Vref=32, minBit 9, minWin=24, winSum=406
8466 12:21:10.852188 TX Vref=34, minBit 9, minWin=23, winSum=396
8467 12:21:10.858561 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8468 12:21:10.858642
8469 12:21:10.861863 Final TX Range 0 Vref 28
8470 12:21:10.861944
8471 12:21:10.862007 ==
8472 12:21:10.865071 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 12:21:10.868310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 12:21:10.868393 ==
8475 12:21:10.868455
8476 12:21:10.871630
8477 12:21:10.871710 TX Vref Scan disable
8478 12:21:10.878428 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8479 12:21:10.878511 == TX Byte 0 ==
8480 12:21:10.881780 u2DelayCellOfst[0]=10 cells (3 PI)
8481 12:21:10.885225 u2DelayCellOfst[1]=7 cells (2 PI)
8482 12:21:10.888052 u2DelayCellOfst[2]=0 cells (0 PI)
8483 12:21:10.891257 u2DelayCellOfst[3]=3 cells (1 PI)
8484 12:21:10.894653 u2DelayCellOfst[4]=7 cells (2 PI)
8485 12:21:10.897869 u2DelayCellOfst[5]=14 cells (4 PI)
8486 12:21:10.901235 u2DelayCellOfst[6]=14 cells (4 PI)
8487 12:21:10.904480 u2DelayCellOfst[7]=3 cells (1 PI)
8488 12:21:10.907649 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8489 12:21:10.911257 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8490 12:21:10.914932 == TX Byte 1 ==
8491 12:21:10.917634 u2DelayCellOfst[8]=0 cells (0 PI)
8492 12:21:10.921095 u2DelayCellOfst[9]=3 cells (1 PI)
8493 12:21:10.924147 u2DelayCellOfst[10]=14 cells (4 PI)
8494 12:21:10.927891 u2DelayCellOfst[11]=3 cells (1 PI)
8495 12:21:10.928037 u2DelayCellOfst[12]=14 cells (4 PI)
8496 12:21:10.930712 u2DelayCellOfst[13]=14 cells (4 PI)
8497 12:21:10.934121 u2DelayCellOfst[14]=18 cells (5 PI)
8498 12:21:10.937240 u2DelayCellOfst[15]=18 cells (5 PI)
8499 12:21:10.943825 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8500 12:21:10.947675 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8501 12:21:10.947756 DramC Write-DBI on
8502 12:21:10.950527 ==
8503 12:21:10.954369 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 12:21:10.957318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 12:21:10.957400 ==
8506 12:21:10.957464
8507 12:21:10.957523
8508 12:21:10.960583 TX Vref Scan disable
8509 12:21:10.960667 == TX Byte 0 ==
8510 12:21:10.967538 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8511 12:21:10.967620 == TX Byte 1 ==
8512 12:21:10.970033 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8513 12:21:10.973675 DramC Write-DBI off
8514 12:21:10.973757
8515 12:21:10.973820 [DATLAT]
8516 12:21:10.976930 Freq=1600, CH1 RK0
8517 12:21:10.977012
8518 12:21:10.977076 DATLAT Default: 0xf
8519 12:21:10.980086 0, 0xFFFF, sum = 0
8520 12:21:10.980169 1, 0xFFFF, sum = 0
8521 12:21:10.983304 2, 0xFFFF, sum = 0
8522 12:21:10.986824 3, 0xFFFF, sum = 0
8523 12:21:10.986907 4, 0xFFFF, sum = 0
8524 12:21:10.989692 5, 0xFFFF, sum = 0
8525 12:21:10.989775 6, 0xFFFF, sum = 0
8526 12:21:10.993726 7, 0xFFFF, sum = 0
8527 12:21:10.993809 8, 0xFFFF, sum = 0
8528 12:21:10.996684 9, 0xFFFF, sum = 0
8529 12:21:10.996766 10, 0xFFFF, sum = 0
8530 12:21:10.999661 11, 0xFFFF, sum = 0
8531 12:21:10.999743 12, 0xFFFF, sum = 0
8532 12:21:11.003047 13, 0xFFFF, sum = 0
8533 12:21:11.003130 14, 0x0, sum = 1
8534 12:21:11.006541 15, 0x0, sum = 2
8535 12:21:11.006623 16, 0x0, sum = 3
8536 12:21:11.009508 17, 0x0, sum = 4
8537 12:21:11.009590 best_step = 15
8538 12:21:11.009654
8539 12:21:11.009714 ==
8540 12:21:11.013174 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 12:21:11.019804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 12:21:11.019909 ==
8543 12:21:11.019992 RX Vref Scan: 1
8544 12:21:11.020051
8545 12:21:11.022979 Set Vref Range= 24 -> 127
8546 12:21:11.023061
8547 12:21:11.026043 RX Vref 24 -> 127, step: 1
8548 12:21:11.026125
8549 12:21:11.026190 RX Delay 11 -> 252, step: 4
8550 12:21:11.029380
8551 12:21:11.029460 Set Vref, RX VrefLevel [Byte0]: 24
8552 12:21:11.032755 [Byte1]: 24
8553 12:21:11.036959
8554 12:21:11.040177 Set Vref, RX VrefLevel [Byte0]: 25
8555 12:21:11.043130 [Byte1]: 25
8556 12:21:11.043212
8557 12:21:11.047164 Set Vref, RX VrefLevel [Byte0]: 26
8558 12:21:11.049899 [Byte1]: 26
8559 12:21:11.049981
8560 12:21:11.053696 Set Vref, RX VrefLevel [Byte0]: 27
8561 12:21:11.056491 [Byte1]: 27
8562 12:21:11.059718
8563 12:21:11.059799 Set Vref, RX VrefLevel [Byte0]: 28
8564 12:21:11.063003 [Byte1]: 28
8565 12:21:11.067133
8566 12:21:11.067213 Set Vref, RX VrefLevel [Byte0]: 29
8567 12:21:11.070792 [Byte1]: 29
8568 12:21:11.074971
8569 12:21:11.075051 Set Vref, RX VrefLevel [Byte0]: 30
8570 12:21:11.078109 [Byte1]: 30
8571 12:21:11.082837
8572 12:21:11.082916 Set Vref, RX VrefLevel [Byte0]: 31
8573 12:21:11.086092 [Byte1]: 31
8574 12:21:11.090372
8575 12:21:11.090451 Set Vref, RX VrefLevel [Byte0]: 32
8576 12:21:11.093570 [Byte1]: 32
8577 12:21:11.097807
8578 12:21:11.097915 Set Vref, RX VrefLevel [Byte0]: 33
8579 12:21:11.101264 [Byte1]: 33
8580 12:21:11.105476
8581 12:21:11.105556 Set Vref, RX VrefLevel [Byte0]: 34
8582 12:21:11.108790 [Byte1]: 34
8583 12:21:11.113035
8584 12:21:11.113115 Set Vref, RX VrefLevel [Byte0]: 35
8585 12:21:11.116115 [Byte1]: 35
8586 12:21:11.120599
8587 12:21:11.120678 Set Vref, RX VrefLevel [Byte0]: 36
8588 12:21:11.123859 [Byte1]: 36
8589 12:21:11.128179
8590 12:21:11.128258 Set Vref, RX VrefLevel [Byte0]: 37
8591 12:21:11.131703 [Byte1]: 37
8592 12:21:11.136007
8593 12:21:11.136087 Set Vref, RX VrefLevel [Byte0]: 38
8594 12:21:11.139374 [Byte1]: 38
8595 12:21:11.143404
8596 12:21:11.143483 Set Vref, RX VrefLevel [Byte0]: 39
8597 12:21:11.146860 [Byte1]: 39
8598 12:21:11.151211
8599 12:21:11.151291 Set Vref, RX VrefLevel [Byte0]: 40
8600 12:21:11.154315 [Byte1]: 40
8601 12:21:11.158898
8602 12:21:11.158977 Set Vref, RX VrefLevel [Byte0]: 41
8603 12:21:11.162076 [Byte1]: 41
8604 12:21:11.166297
8605 12:21:11.166377 Set Vref, RX VrefLevel [Byte0]: 42
8606 12:21:11.169564 [Byte1]: 42
8607 12:21:11.173944
8608 12:21:11.174029 Set Vref, RX VrefLevel [Byte0]: 43
8609 12:21:11.177057 [Byte1]: 43
8610 12:21:11.182489
8611 12:21:11.182598 Set Vref, RX VrefLevel [Byte0]: 44
8612 12:21:11.184888 [Byte1]: 44
8613 12:21:11.189512
8614 12:21:11.189591 Set Vref, RX VrefLevel [Byte0]: 45
8615 12:21:11.192642 [Byte1]: 45
8616 12:21:11.196938
8617 12:21:11.197018 Set Vref, RX VrefLevel [Byte0]: 46
8618 12:21:11.200048 [Byte1]: 46
8619 12:21:11.204543
8620 12:21:11.204623 Set Vref, RX VrefLevel [Byte0]: 47
8621 12:21:11.207710 [Byte1]: 47
8622 12:21:11.212064
8623 12:21:11.212144 Set Vref, RX VrefLevel [Byte0]: 48
8624 12:21:11.215637 [Byte1]: 48
8625 12:21:11.219939
8626 12:21:11.220032 Set Vref, RX VrefLevel [Byte0]: 49
8627 12:21:11.223000 [Byte1]: 49
8628 12:21:11.227333
8629 12:21:11.227413 Set Vref, RX VrefLevel [Byte0]: 50
8630 12:21:11.231025 [Byte1]: 50
8631 12:21:11.234721
8632 12:21:11.234801 Set Vref, RX VrefLevel [Byte0]: 51
8633 12:21:11.238415 [Byte1]: 51
8634 12:21:11.242505
8635 12:21:11.242585 Set Vref, RX VrefLevel [Byte0]: 52
8636 12:21:11.245794 [Byte1]: 52
8637 12:21:11.250180
8638 12:21:11.250260 Set Vref, RX VrefLevel [Byte0]: 53
8639 12:21:11.253468 [Byte1]: 53
8640 12:21:11.257735
8641 12:21:11.257815 Set Vref, RX VrefLevel [Byte0]: 54
8642 12:21:11.261378 [Byte1]: 54
8643 12:21:11.265322
8644 12:21:11.265401 Set Vref, RX VrefLevel [Byte0]: 55
8645 12:21:11.268682 [Byte1]: 55
8646 12:21:11.272941
8647 12:21:11.273021 Set Vref, RX VrefLevel [Byte0]: 56
8648 12:21:11.276156 [Byte1]: 56
8649 12:21:11.280514
8650 12:21:11.280594 Set Vref, RX VrefLevel [Byte0]: 57
8651 12:21:11.284090 [Byte1]: 57
8652 12:21:11.288175
8653 12:21:11.288256 Set Vref, RX VrefLevel [Byte0]: 58
8654 12:21:11.291520 [Byte1]: 58
8655 12:21:11.295819
8656 12:21:11.295926 Set Vref, RX VrefLevel [Byte0]: 59
8657 12:21:11.299700 [Byte1]: 59
8658 12:21:11.303543
8659 12:21:11.303625 Set Vref, RX VrefLevel [Byte0]: 60
8660 12:21:11.306526 [Byte1]: 60
8661 12:21:11.310998
8662 12:21:11.311080 Set Vref, RX VrefLevel [Byte0]: 61
8663 12:21:11.314356 [Byte1]: 61
8664 12:21:11.318392
8665 12:21:11.318473 Set Vref, RX VrefLevel [Byte0]: 62
8666 12:21:11.322022 [Byte1]: 62
8667 12:21:11.326243
8668 12:21:11.326324 Set Vref, RX VrefLevel [Byte0]: 63
8669 12:21:11.329363 [Byte1]: 63
8670 12:21:11.334159
8671 12:21:11.334241 Set Vref, RX VrefLevel [Byte0]: 64
8672 12:21:11.337079 [Byte1]: 64
8673 12:21:11.341357
8674 12:21:11.341438 Set Vref, RX VrefLevel [Byte0]: 65
8675 12:21:11.344869 [Byte1]: 65
8676 12:21:11.349386
8677 12:21:11.349467 Set Vref, RX VrefLevel [Byte0]: 66
8678 12:21:11.352824 [Byte1]: 66
8679 12:21:11.356651
8680 12:21:11.356732 Set Vref, RX VrefLevel [Byte0]: 67
8681 12:21:11.360184 [Byte1]: 67
8682 12:21:11.364659
8683 12:21:11.364740 Set Vref, RX VrefLevel [Byte0]: 68
8684 12:21:11.367893 [Byte1]: 68
8685 12:21:11.371909
8686 12:21:11.371992 Set Vref, RX VrefLevel [Byte0]: 69
8687 12:21:11.375174 [Byte1]: 69
8688 12:21:11.379527
8689 12:21:11.379609 Set Vref, RX VrefLevel [Byte0]: 70
8690 12:21:11.383184 [Byte1]: 70
8691 12:21:11.386947
8692 12:21:11.387028 Set Vref, RX VrefLevel [Byte0]: 71
8693 12:21:11.390226 [Byte1]: 71
8694 12:21:11.394573
8695 12:21:11.394655 Set Vref, RX VrefLevel [Byte0]: 72
8696 12:21:11.401305 [Byte1]: 72
8697 12:21:11.401387
8698 12:21:11.404511 Set Vref, RX VrefLevel [Byte0]: 73
8699 12:21:11.407822 [Byte1]: 73
8700 12:21:11.407944
8701 12:21:11.411049 Final RX Vref Byte 0 = 55 to rank0
8702 12:21:11.414198 Final RX Vref Byte 1 = 59 to rank0
8703 12:21:11.417673 Final RX Vref Byte 0 = 55 to rank1
8704 12:21:11.421123 Final RX Vref Byte 1 = 59 to rank1==
8705 12:21:11.424020 Dram Type= 6, Freq= 0, CH_1, rank 0
8706 12:21:11.427246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 12:21:11.427328 ==
8708 12:21:11.430541 DQS Delay:
8709 12:21:11.430622 DQS0 = 0, DQS1 = 0
8710 12:21:11.434080 DQM Delay:
8711 12:21:11.434161 DQM0 = 133, DQM1 = 128
8712 12:21:11.434225 DQ Delay:
8713 12:21:11.437815 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =130
8714 12:21:11.444056 DQ4 =128, DQ5 =142, DQ6 =146, DQ7 =128
8715 12:21:11.447263 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =120
8716 12:21:11.450436 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8717 12:21:11.450518
8718 12:21:11.450582
8719 12:21:11.450641
8720 12:21:11.453636 [DramC_TX_OE_Calibration] TA2
8721 12:21:11.456982 Original DQ_B0 (3 6) =30, OEN = 27
8722 12:21:11.460611 Original DQ_B1 (3 6) =30, OEN = 27
8723 12:21:11.460693 24, 0x0, End_B0=24 End_B1=24
8724 12:21:11.463941 25, 0x0, End_B0=25 End_B1=25
8725 12:21:11.467194 26, 0x0, End_B0=26 End_B1=26
8726 12:21:11.470472 27, 0x0, End_B0=27 End_B1=27
8727 12:21:11.473980 28, 0x0, End_B0=28 End_B1=28
8728 12:21:11.474063 29, 0x0, End_B0=29 End_B1=29
8729 12:21:11.476654 30, 0x0, End_B0=30 End_B1=30
8730 12:21:11.479941 31, 0x4545, End_B0=30 End_B1=30
8731 12:21:11.483681 Byte0 end_step=30 best_step=27
8732 12:21:11.486764 Byte1 end_step=30 best_step=27
8733 12:21:11.490230 Byte0 TX OE(2T, 0.5T) = (3, 3)
8734 12:21:11.490312 Byte1 TX OE(2T, 0.5T) = (3, 3)
8735 12:21:11.490376
8736 12:21:11.490435
8737 12:21:11.500121 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8738 12:21:11.503398 CH1 RK0: MR19=303, MR18=C16
8739 12:21:11.509696 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8740 12:21:11.509778
8741 12:21:11.512952 ----->DramcWriteLeveling(PI) begin...
8742 12:21:11.513035 ==
8743 12:21:11.516758 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 12:21:11.520141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 12:21:11.520223 ==
8746 12:21:11.522792 Write leveling (Byte 0): 24 => 24
8747 12:21:11.525987 Write leveling (Byte 1): 26 => 26
8748 12:21:11.529509 DramcWriteLeveling(PI) end<-----
8749 12:21:11.529590
8750 12:21:11.529654 ==
8751 12:21:11.532817 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 12:21:11.536341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 12:21:11.536422 ==
8754 12:21:11.540041 [Gating] SW mode calibration
8755 12:21:11.546111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8756 12:21:11.552972 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8757 12:21:11.556139 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 12:21:11.559290 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 12:21:11.565425 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8760 12:21:11.569342 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8761 12:21:11.572297 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 12:21:11.579026 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 12:21:11.582204 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 12:21:11.586150 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 12:21:11.592119 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 12:21:11.595346 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8767 12:21:11.598498 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
8768 12:21:11.605314 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8769 12:21:11.608304 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8770 12:21:11.611629 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 12:21:11.618293 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 12:21:11.621894 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 12:21:11.625038 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 12:21:11.631498 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8775 12:21:11.634508 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8776 12:21:11.637916 1 6 12 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8777 12:21:11.644838 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 12:21:11.648230 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 12:21:11.654423 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 12:21:11.657768 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 12:21:11.661330 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 12:21:11.667250 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 12:21:11.671074 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8784 12:21:11.674323 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8785 12:21:11.680461 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:21:11.684019 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:21:11.687310 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:21:11.694099 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:21:11.696997 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 12:21:11.700288 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 12:21:11.707068 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 12:21:11.710346 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:21:11.713432 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 12:21:11.719958 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 12:21:11.723126 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 12:21:11.726493 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 12:21:11.733273 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 12:21:11.737032 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 12:21:11.739598 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8800 12:21:11.746184 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8801 12:21:11.750396 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8802 12:21:11.753144 Total UI for P1: 0, mck2ui 16
8803 12:21:11.756330 best dqsien dly found for B0: ( 1, 9, 10)
8804 12:21:11.759664 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 12:21:11.763149 Total UI for P1: 0, mck2ui 16
8806 12:21:11.766276 best dqsien dly found for B1: ( 1, 9, 14)
8807 12:21:11.769452 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8808 12:21:11.772702 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8809 12:21:11.772784
8810 12:21:11.779686 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8811 12:21:11.782730 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8812 12:21:11.782812 [Gating] SW calibration Done
8813 12:21:11.786143 ==
8814 12:21:11.789274 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 12:21:11.792605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 12:21:11.792687 ==
8817 12:21:11.792751 RX Vref Scan: 0
8818 12:21:11.792811
8819 12:21:11.795883 RX Vref 0 -> 0, step: 1
8820 12:21:11.796002
8821 12:21:11.799600 RX Delay 0 -> 252, step: 8
8822 12:21:11.802678 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8823 12:21:11.806080 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8824 12:21:11.809210 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8825 12:21:11.815869 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8826 12:21:11.819672 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8827 12:21:11.822621 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8828 12:21:11.825723 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8829 12:21:11.828995 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8830 12:21:11.835839 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8831 12:21:11.839322 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8832 12:21:11.842545 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8833 12:21:11.845286 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8834 12:21:11.852022 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8835 12:21:11.855603 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8836 12:21:11.858469 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8837 12:21:11.861893 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8838 12:21:11.861975 ==
8839 12:21:11.865067 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 12:21:11.872081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 12:21:11.872164 ==
8842 12:21:11.872228 DQS Delay:
8843 12:21:11.875142 DQS0 = 0, DQS1 = 0
8844 12:21:11.875223 DQM Delay:
8845 12:21:11.878472 DQM0 = 134, DQM1 = 131
8846 12:21:11.878554 DQ Delay:
8847 12:21:11.882002 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =131
8848 12:21:11.884823 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8849 12:21:11.888448 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8850 12:21:11.891654 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8851 12:21:11.891735
8852 12:21:11.891799
8853 12:21:11.891857 ==
8854 12:21:11.894833 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 12:21:11.901649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 12:21:11.901731 ==
8857 12:21:11.901795
8858 12:21:11.901855
8859 12:21:11.901912 TX Vref Scan disable
8860 12:21:11.905027 == TX Byte 0 ==
8861 12:21:11.908437 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8862 12:21:11.914749 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8863 12:21:11.914831 == TX Byte 1 ==
8864 12:21:11.917916 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8865 12:21:11.924474 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8866 12:21:11.924555 ==
8867 12:21:11.927939 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 12:21:11.931299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 12:21:11.931381 ==
8870 12:21:11.944894
8871 12:21:11.948573 TX Vref early break, caculate TX vref
8872 12:21:11.951012 TX Vref=16, minBit 9, minWin=21, winSum=378
8873 12:21:11.954496 TX Vref=18, minBit 9, minWin=22, winSum=385
8874 12:21:11.957598 TX Vref=20, minBit 9, minWin=22, winSum=390
8875 12:21:11.961112 TX Vref=22, minBit 9, minWin=23, winSum=401
8876 12:21:11.964287 TX Vref=24, minBit 9, minWin=24, winSum=406
8877 12:21:11.971060 TX Vref=26, minBit 9, minWin=24, winSum=413
8878 12:21:11.974444 TX Vref=28, minBit 9, minWin=24, winSum=420
8879 12:21:11.977867 TX Vref=30, minBit 9, minWin=24, winSum=416
8880 12:21:11.980960 TX Vref=32, minBit 0, minWin=24, winSum=411
8881 12:21:11.984068 TX Vref=34, minBit 0, minWin=24, winSum=400
8882 12:21:11.987360 TX Vref=36, minBit 8, minWin=23, winSum=395
8883 12:21:11.994029 [TxChooseVref] Worse bit 9, Min win 24, Win sum 420, Final Vref 28
8884 12:21:11.994111
8885 12:21:11.997475 Final TX Range 0 Vref 28
8886 12:21:11.997557
8887 12:21:11.997621 ==
8888 12:21:12.000736 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 12:21:12.003881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 12:21:12.004003 ==
8891 12:21:12.007243
8892 12:21:12.007323
8893 12:21:12.007387 TX Vref Scan disable
8894 12:21:12.014217 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8895 12:21:12.014299 == TX Byte 0 ==
8896 12:21:12.017225 u2DelayCellOfst[0]=14 cells (4 PI)
8897 12:21:12.020741 u2DelayCellOfst[1]=7 cells (2 PI)
8898 12:21:12.023924 u2DelayCellOfst[2]=0 cells (0 PI)
8899 12:21:12.027188 u2DelayCellOfst[3]=7 cells (2 PI)
8900 12:21:12.030262 u2DelayCellOfst[4]=7 cells (2 PI)
8901 12:21:12.033544 u2DelayCellOfst[5]=14 cells (4 PI)
8902 12:21:12.036743 u2DelayCellOfst[6]=14 cells (4 PI)
8903 12:21:12.040125 u2DelayCellOfst[7]=7 cells (2 PI)
8904 12:21:12.043494 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8905 12:21:12.046686 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8906 12:21:12.050399 == TX Byte 1 ==
8907 12:21:12.053676 u2DelayCellOfst[8]=0 cells (0 PI)
8908 12:21:12.056920 u2DelayCellOfst[9]=3 cells (1 PI)
8909 12:21:12.060116 u2DelayCellOfst[10]=10 cells (3 PI)
8910 12:21:12.063020 u2DelayCellOfst[11]=3 cells (1 PI)
8911 12:21:12.066491 u2DelayCellOfst[12]=14 cells (4 PI)
8912 12:21:12.069566 u2DelayCellOfst[13]=14 cells (4 PI)
8913 12:21:12.069648 u2DelayCellOfst[14]=18 cells (5 PI)
8914 12:21:12.073384 u2DelayCellOfst[15]=14 cells (4 PI)
8915 12:21:12.080018 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8916 12:21:12.083258 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8917 12:21:12.086143 DramC Write-DBI on
8918 12:21:12.086224 ==
8919 12:21:12.089592 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 12:21:12.092563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 12:21:12.092645 ==
8922 12:21:12.092709
8923 12:21:12.092768
8924 12:21:12.096243 TX Vref Scan disable
8925 12:21:12.096324 == TX Byte 0 ==
8926 12:21:12.103075 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8927 12:21:12.103157 == TX Byte 1 ==
8928 12:21:12.105838 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8929 12:21:12.109157 DramC Write-DBI off
8930 12:21:12.109238
8931 12:21:12.109303 [DATLAT]
8932 12:21:12.112975 Freq=1600, CH1 RK1
8933 12:21:12.113056
8934 12:21:12.113120 DATLAT Default: 0xf
8935 12:21:12.115782 0, 0xFFFF, sum = 0
8936 12:21:12.115892 1, 0xFFFF, sum = 0
8937 12:21:12.118998 2, 0xFFFF, sum = 0
8938 12:21:12.122411 3, 0xFFFF, sum = 0
8939 12:21:12.122494 4, 0xFFFF, sum = 0
8940 12:21:12.125610 5, 0xFFFF, sum = 0
8941 12:21:12.125761 6, 0xFFFF, sum = 0
8942 12:21:12.128914 7, 0xFFFF, sum = 0
8943 12:21:12.128997 8, 0xFFFF, sum = 0
8944 12:21:12.132577 9, 0xFFFF, sum = 0
8945 12:21:12.132659 10, 0xFFFF, sum = 0
8946 12:21:12.135757 11, 0xFFFF, sum = 0
8947 12:21:12.135839 12, 0xFFFF, sum = 0
8948 12:21:12.139194 13, 0xFFFF, sum = 0
8949 12:21:12.139276 14, 0x0, sum = 1
8950 12:21:12.142376 15, 0x0, sum = 2
8951 12:21:12.142459 16, 0x0, sum = 3
8952 12:21:12.145381 17, 0x0, sum = 4
8953 12:21:12.145463 best_step = 15
8954 12:21:12.145527
8955 12:21:12.145587 ==
8956 12:21:12.148762 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 12:21:12.155760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 12:21:12.155843 ==
8959 12:21:12.155973 RX Vref Scan: 0
8960 12:21:12.156035
8961 12:21:12.158804 RX Vref 0 -> 0, step: 1
8962 12:21:12.158884
8963 12:21:12.161937 RX Delay 19 -> 252, step: 4
8964 12:21:12.165630 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8965 12:21:12.169040 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8966 12:21:12.172282 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8967 12:21:12.178621 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8968 12:21:12.181714 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8969 12:21:12.185157 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8970 12:21:12.188483 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8971 12:21:12.191823 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8972 12:21:12.198282 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8973 12:21:12.201891 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8974 12:21:12.204719 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
8975 12:21:12.208353 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8976 12:21:12.214995 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8977 12:21:12.218098 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8978 12:21:12.221525 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8979 12:21:12.224562 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8980 12:21:12.224644 ==
8981 12:21:12.227801 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 12:21:12.234428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 12:21:12.234509 ==
8984 12:21:12.234574 DQS Delay:
8985 12:21:12.237782 DQS0 = 0, DQS1 = 0
8986 12:21:12.237864 DQM Delay:
8987 12:21:12.237929 DQM0 = 131, DQM1 = 128
8988 12:21:12.240947 DQ Delay:
8989 12:21:12.244243 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
8990 12:21:12.247569 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =130
8991 12:21:12.250761 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8992 12:21:12.254437 DQ12 =138, DQ13 =136, DQ14 =132, DQ15 =138
8993 12:21:12.254518
8994 12:21:12.254581
8995 12:21:12.254671
8996 12:21:12.257290 [DramC_TX_OE_Calibration] TA2
8997 12:21:12.261006 Original DQ_B0 (3 6) =30, OEN = 27
8998 12:21:12.263990 Original DQ_B1 (3 6) =30, OEN = 27
8999 12:21:12.267458 24, 0x0, End_B0=24 End_B1=24
9000 12:21:12.270877 25, 0x0, End_B0=25 End_B1=25
9001 12:21:12.270960 26, 0x0, End_B0=26 End_B1=26
9002 12:21:12.274079 27, 0x0, End_B0=27 End_B1=27
9003 12:21:12.277568 28, 0x0, End_B0=28 End_B1=28
9004 12:21:12.280335 29, 0x0, End_B0=29 End_B1=29
9005 12:21:12.280417 30, 0x0, End_B0=30 End_B1=30
9006 12:21:12.283582 31, 0x4141, End_B0=30 End_B1=30
9007 12:21:12.286817 Byte0 end_step=30 best_step=27
9008 12:21:12.290196 Byte1 end_step=30 best_step=27
9009 12:21:12.293702 Byte0 TX OE(2T, 0.5T) = (3, 3)
9010 12:21:12.296635 Byte1 TX OE(2T, 0.5T) = (3, 3)
9011 12:21:12.296716
9012 12:21:12.296780
9013 12:21:12.303506 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9014 12:21:12.306957 CH1 RK1: MR19=303, MR18=D1A
9015 12:21:12.313346 CH1_RK1: MR19=0x303, MR18=0xD1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9016 12:21:12.316767 [RxdqsGatingPostProcess] freq 1600
9017 12:21:12.323066 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9018 12:21:12.323148 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 12:21:12.326596 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 12:21:12.330088 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 12:21:12.333222 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 12:21:12.336721 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 12:21:12.339555 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 12:21:12.343159 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 12:21:12.346514 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 12:21:12.349680 Pre-setting of DQS Precalculation
9027 12:21:12.352590 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9028 12:21:12.362529 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9029 12:21:12.369340 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9030 12:21:12.369421
9031 12:21:12.369485
9032 12:21:12.372569 [Calibration Summary] 3200 Mbps
9033 12:21:12.372642 CH 0, Rank 0
9034 12:21:12.375886 SW Impedance : PASS
9035 12:21:12.375970 DUTY Scan : NO K
9036 12:21:12.379704 ZQ Calibration : PASS
9037 12:21:12.382271 Jitter Meter : NO K
9038 12:21:12.382345 CBT Training : PASS
9039 12:21:12.385627 Write leveling : PASS
9040 12:21:12.389280 RX DQS gating : PASS
9041 12:21:12.389362 RX DQ/DQS(RDDQC) : PASS
9042 12:21:12.392101 TX DQ/DQS : PASS
9043 12:21:12.395737 RX DATLAT : PASS
9044 12:21:12.395818 RX DQ/DQS(Engine): PASS
9045 12:21:12.399068 TX OE : PASS
9046 12:21:12.399149 All Pass.
9047 12:21:12.399253
9048 12:21:12.402216 CH 0, Rank 1
9049 12:21:12.402297 SW Impedance : PASS
9050 12:21:12.405561 DUTY Scan : NO K
9051 12:21:12.408764 ZQ Calibration : PASS
9052 12:21:12.408845 Jitter Meter : NO K
9053 12:21:12.411875 CBT Training : PASS
9054 12:21:12.415053 Write leveling : PASS
9055 12:21:12.415134 RX DQS gating : PASS
9056 12:21:12.419042 RX DQ/DQS(RDDQC) : PASS
9057 12:21:12.422044 TX DQ/DQS : PASS
9058 12:21:12.422126 RX DATLAT : PASS
9059 12:21:12.425258 RX DQ/DQS(Engine): PASS
9060 12:21:12.428676 TX OE : PASS
9061 12:21:12.428758 All Pass.
9062 12:21:12.428822
9063 12:21:12.428881 CH 1, Rank 0
9064 12:21:12.431690 SW Impedance : PASS
9065 12:21:12.435103 DUTY Scan : NO K
9066 12:21:12.435184 ZQ Calibration : PASS
9067 12:21:12.438071 Jitter Meter : NO K
9068 12:21:12.441392 CBT Training : PASS
9069 12:21:12.441473 Write leveling : PASS
9070 12:21:12.445153 RX DQS gating : PASS
9071 12:21:12.448037 RX DQ/DQS(RDDQC) : PASS
9072 12:21:12.448118 TX DQ/DQS : PASS
9073 12:21:12.451369 RX DATLAT : PASS
9074 12:21:12.454634 RX DQ/DQS(Engine): PASS
9075 12:21:12.454715 TX OE : PASS
9076 12:21:12.454780 All Pass.
9077 12:21:12.458111
9078 12:21:12.458193 CH 1, Rank 1
9079 12:21:12.461133 SW Impedance : PASS
9080 12:21:12.461214 DUTY Scan : NO K
9081 12:21:12.464379 ZQ Calibration : PASS
9082 12:21:12.467553 Jitter Meter : NO K
9083 12:21:12.467634 CBT Training : PASS
9084 12:21:12.471040 Write leveling : PASS
9085 12:21:12.474556 RX DQS gating : PASS
9086 12:21:12.474638 RX DQ/DQS(RDDQC) : PASS
9087 12:21:12.477691 TX DQ/DQS : PASS
9088 12:21:12.477772 RX DATLAT : PASS
9089 12:21:12.480620 RX DQ/DQS(Engine): PASS
9090 12:21:12.483819 TX OE : PASS
9091 12:21:12.483907 All Pass.
9092 12:21:12.483987
9093 12:21:12.487498 DramC Write-DBI on
9094 12:21:12.487579 PER_BANK_REFRESH: Hybrid Mode
9095 12:21:12.490911 TX_TRACKING: ON
9096 12:21:12.500416 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9097 12:21:12.507091 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9098 12:21:12.513623 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9099 12:21:12.516569 [FAST_K] Save calibration result to emmc
9100 12:21:12.519898 sync common calibartion params.
9101 12:21:12.523636 sync cbt_mode0:1, 1:1
9102 12:21:12.526694 dram_init: ddr_geometry: 2
9103 12:21:12.526776 dram_init: ddr_geometry: 2
9104 12:21:12.530380 dram_init: ddr_geometry: 2
9105 12:21:12.533058 0:dram_rank_size:100000000
9106 12:21:12.536670 1:dram_rank_size:100000000
9107 12:21:12.540009 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9108 12:21:12.543012 DFS_SHUFFLE_HW_MODE: ON
9109 12:21:12.546324 dramc_set_vcore_voltage set vcore to 725000
9110 12:21:12.549610 Read voltage for 1600, 0
9111 12:21:12.549692 Vio18 = 0
9112 12:21:12.549756 Vcore = 725000
9113 12:21:12.553304 Vdram = 0
9114 12:21:12.553385 Vddq = 0
9115 12:21:12.553449 Vmddr = 0
9116 12:21:12.556265 switch to 3200 Mbps bootup
9117 12:21:12.559617 [DramcRunTimeConfig]
9118 12:21:12.559698 PHYPLL
9119 12:21:12.559762 DPM_CONTROL_AFTERK: ON
9120 12:21:12.562551 PER_BANK_REFRESH: ON
9121 12:21:12.566020 REFRESH_OVERHEAD_REDUCTION: ON
9122 12:21:12.569207 CMD_PICG_NEW_MODE: OFF
9123 12:21:12.569288 XRTWTW_NEW_MODE: ON
9124 12:21:12.572640 XRTRTR_NEW_MODE: ON
9125 12:21:12.572721 TX_TRACKING: ON
9126 12:21:12.575803 RDSEL_TRACKING: OFF
9127 12:21:12.575885 DQS Precalculation for DVFS: ON
9128 12:21:12.579293 RX_TRACKING: OFF
9129 12:21:12.579374 HW_GATING DBG: ON
9130 12:21:12.582300 ZQCS_ENABLE_LP4: ON
9131 12:21:12.585560 RX_PICG_NEW_MODE: ON
9132 12:21:12.585641 TX_PICG_NEW_MODE: ON
9133 12:21:12.589199 ENABLE_RX_DCM_DPHY: ON
9134 12:21:12.592334 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9135 12:21:12.592415 DUMMY_READ_FOR_TRACKING: OFF
9136 12:21:12.596018 !!! SPM_CONTROL_AFTERK: OFF
9137 12:21:12.599045 !!! SPM could not control APHY
9138 12:21:12.602157 IMPEDANCE_TRACKING: ON
9139 12:21:12.602238 TEMP_SENSOR: ON
9140 12:21:12.605603 HW_SAVE_FOR_SR: OFF
9141 12:21:12.609024 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9142 12:21:12.612449 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9143 12:21:12.612530 Read ODT Tracking: ON
9144 12:21:12.616292 Refresh Rate DeBounce: ON
9145 12:21:12.619169 DFS_NO_QUEUE_FLUSH: ON
9146 12:21:12.622417 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9147 12:21:12.622498 ENABLE_DFS_RUNTIME_MRW: OFF
9148 12:21:12.625558 DDR_RESERVE_NEW_MODE: ON
9149 12:21:12.628502 MR_CBT_SWITCH_FREQ: ON
9150 12:21:12.628584 =========================
9151 12:21:12.648910 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9152 12:21:12.652193 dram_init: ddr_geometry: 2
9153 12:21:12.670484 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9154 12:21:12.673702 dram_init: dram init end (result: 0)
9155 12:21:12.680526 DRAM-K: Full calibration passed in 24487 msecs
9156 12:21:12.683600 MRC: failed to locate region type 0.
9157 12:21:12.683681 DRAM rank0 size:0x100000000,
9158 12:21:12.687061 DRAM rank1 size=0x100000000
9159 12:21:12.696707 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9160 12:21:12.703401 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9161 12:21:12.709738 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9162 12:21:12.719954 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9163 12:21:12.720036 DRAM rank0 size:0x100000000,
9164 12:21:12.723284 DRAM rank1 size=0x100000000
9165 12:21:12.723365 CBMEM:
9166 12:21:12.726488 IMD: root @ 0xfffff000 254 entries.
9167 12:21:12.729565 IMD: root @ 0xffffec00 62 entries.
9168 12:21:12.733108 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9169 12:21:12.739618 WARNING: RO_VPD is uninitialized or empty.
9170 12:21:12.742862 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9171 12:21:12.750757 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9172 12:21:12.763005 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9173 12:21:12.774699 BS: romstage times (exec / console): total (unknown) / 24010 ms
9174 12:21:12.774780
9175 12:21:12.774844
9176 12:21:12.784687 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9177 12:21:12.787844 ARM64: Exception handlers installed.
9178 12:21:12.791380 ARM64: Testing exception
9179 12:21:12.794437 ARM64: Done test exception
9180 12:21:12.794518 Enumerating buses...
9181 12:21:12.797636 Show all devs... Before device enumeration.
9182 12:21:12.801523 Root Device: enabled 1
9183 12:21:12.804230 CPU_CLUSTER: 0: enabled 1
9184 12:21:12.804311 CPU: 00: enabled 1
9185 12:21:12.807382 Compare with tree...
9186 12:21:12.807463 Root Device: enabled 1
9187 12:21:12.810766 CPU_CLUSTER: 0: enabled 1
9188 12:21:12.814203 CPU: 00: enabled 1
9189 12:21:12.814285 Root Device scanning...
9190 12:21:12.817576 scan_static_bus for Root Device
9191 12:21:12.820734 CPU_CLUSTER: 0 enabled
9192 12:21:12.824080 scan_static_bus for Root Device done
9193 12:21:12.827382 scan_bus: bus Root Device finished in 8 msecs
9194 12:21:12.827480 done
9195 12:21:12.834071 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9196 12:21:12.837161 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9197 12:21:12.844048 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9198 12:21:12.847281 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9199 12:21:12.850506 Allocating resources...
9200 12:21:12.854228 Reading resources...
9201 12:21:12.857486 Root Device read_resources bus 0 link: 0
9202 12:21:12.860366 DRAM rank0 size:0x100000000,
9203 12:21:12.860448 DRAM rank1 size=0x100000000
9204 12:21:12.866878 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9205 12:21:12.866964 CPU: 00 missing read_resources
9206 12:21:12.873614 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9207 12:21:12.876855 Root Device read_resources bus 0 link: 0 done
9208 12:21:12.879631 Done reading resources.
9209 12:21:12.883165 Show resources in subtree (Root Device)...After reading.
9210 12:21:12.886538 Root Device child on link 0 CPU_CLUSTER: 0
9211 12:21:12.889789 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 12:21:12.899739 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 12:21:12.899822 CPU: 00
9214 12:21:12.906021 Root Device assign_resources, bus 0 link: 0
9215 12:21:12.909261 CPU_CLUSTER: 0 missing set_resources
9216 12:21:12.912994 Root Device assign_resources, bus 0 link: 0 done
9217 12:21:12.916133 Done setting resources.
9218 12:21:12.919021 Show resources in subtree (Root Device)...After assigning values.
9219 12:21:12.925558 Root Device child on link 0 CPU_CLUSTER: 0
9220 12:21:12.929086 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 12:21:12.935642 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 12:21:12.938936 CPU: 00
9223 12:21:12.939017 Done allocating resources.
9224 12:21:12.945539 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9225 12:21:12.948717 Enabling resources...
9226 12:21:12.948799 done.
9227 12:21:12.951856 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9228 12:21:12.954987 Initializing devices...
9229 12:21:12.955068 Root Device init
9230 12:21:12.958413 init hardware done!
9231 12:21:12.961599 0x00000018: ctrlr->caps
9232 12:21:12.961682 52.000 MHz: ctrlr->f_max
9233 12:21:12.965526 0.400 MHz: ctrlr->f_min
9234 12:21:12.968389 0x40ff8080: ctrlr->voltages
9235 12:21:12.968472 sclk: 390625
9236 12:21:12.968537 Bus Width = 1
9237 12:21:12.971940 sclk: 390625
9238 12:21:12.972021 Bus Width = 1
9239 12:21:12.974777 Early init status = 3
9240 12:21:12.978248 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9241 12:21:12.982630 in-header: 03 fb 00 00 01 00 00 00
9242 12:21:12.985900 in-data: 01
9243 12:21:12.989495 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9244 12:21:12.994177 in-header: 03 fb 00 00 01 00 00 00
9245 12:21:12.997090 in-data: 01
9246 12:21:13.000407 [SSUSB] Setting up USB HOST controller...
9247 12:21:13.003617 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9248 12:21:13.006907 [SSUSB] phy power-on done.
9249 12:21:13.010355 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9250 12:21:13.016806 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9251 12:21:13.020128 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9252 12:21:13.026829 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9253 12:21:13.033264 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9254 12:21:13.039766 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9255 12:21:13.046752 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9256 12:21:13.053554 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9257 12:21:13.057046 SPM: binary array size = 0x9dc
9258 12:21:13.062936 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9259 12:21:13.066144 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9260 12:21:13.076177 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9261 12:21:13.079277 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9262 12:21:13.082566 configure_display: Starting display init
9263 12:21:13.117238 anx7625_power_on_init: Init interface.
9264 12:21:13.120484 anx7625_disable_pd_protocol: Disabled PD feature.
9265 12:21:13.124215 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9266 12:21:13.151679 anx7625_start_dp_work: Secure OCM version=00
9267 12:21:13.155420 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9268 12:21:13.170147 sp_tx_get_edid_block: EDID Block = 1
9269 12:21:13.272687 Extracted contents:
9270 12:21:13.275572 header: 00 ff ff ff ff ff ff 00
9271 12:21:13.279161 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9272 12:21:13.282178 version: 01 04
9273 12:21:13.285619 basic params: 95 1f 11 78 0a
9274 12:21:13.289000 chroma info: 76 90 94 55 54 90 27 21 50 54
9275 12:21:13.292434 established: 00 00 00
9276 12:21:13.298510 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9277 12:21:13.305843 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9278 12:21:13.308740 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9279 12:21:13.315229 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9280 12:21:13.321934 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9281 12:21:13.325315 extensions: 00
9282 12:21:13.325397 checksum: fb
9283 12:21:13.325461
9284 12:21:13.331578 Manufacturer: IVO Model 57d Serial Number 0
9285 12:21:13.331661 Made week 0 of 2020
9286 12:21:13.334999 EDID version: 1.4
9287 12:21:13.335080 Digital display
9288 12:21:13.338264 6 bits per primary color channel
9289 12:21:13.341293 DisplayPort interface
9290 12:21:13.341374 Maximum image size: 31 cm x 17 cm
9291 12:21:13.345047 Gamma: 220%
9292 12:21:13.345128 Check DPMS levels
9293 12:21:13.351513 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9294 12:21:13.354713 First detailed timing is preferred timing
9295 12:21:13.357810 Established timings supported:
9296 12:21:13.357892 Standard timings supported:
9297 12:21:13.361357 Detailed timings
9298 12:21:13.364371 Hex of detail: 383680a07038204018303c0035ae10000019
9299 12:21:13.370761 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9300 12:21:13.374167 0780 0798 07c8 0820 hborder 0
9301 12:21:13.377650 0438 043b 0447 0458 vborder 0
9302 12:21:13.380719 -hsync -vsync
9303 12:21:13.380801 Did detailed timing
9304 12:21:13.387227 Hex of detail: 000000000000000000000000000000000000
9305 12:21:13.390857 Manufacturer-specified data, tag 0
9306 12:21:13.394222 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9307 12:21:13.397315 ASCII string: InfoVision
9308 12:21:13.400386 Hex of detail: 000000fe00523134304e574635205248200a
9309 12:21:13.403878 ASCII string: R140NWF5 RH
9310 12:21:13.404003 Checksum
9311 12:21:13.406956 Checksum: 0xfb (valid)
9312 12:21:13.410278 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9313 12:21:13.413761 DSI data_rate: 832800000 bps
9314 12:21:13.420139 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9315 12:21:13.423696 anx7625_parse_edid: pixelclock(138800).
9316 12:21:13.426806 hactive(1920), hsync(48), hfp(24), hbp(88)
9317 12:21:13.430470 vactive(1080), vsync(12), vfp(3), vbp(17)
9318 12:21:13.433303 anx7625_dsi_config: config dsi.
9319 12:21:13.440494 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9320 12:21:13.454430 anx7625_dsi_config: success to config DSI
9321 12:21:13.458199 anx7625_dp_start: MIPI phy setup OK.
9322 12:21:13.460922 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9323 12:21:13.464405 mtk_ddp_mode_set invalid vrefresh 60
9324 12:21:13.467854 main_disp_path_setup
9325 12:21:13.467969 ovl_layer_smi_id_en
9326 12:21:13.471369 ovl_layer_smi_id_en
9327 12:21:13.471450 ccorr_config
9328 12:21:13.471513 aal_config
9329 12:21:13.474358 gamma_config
9330 12:21:13.474438 postmask_config
9331 12:21:13.477950 dither_config
9332 12:21:13.480731 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9333 12:21:13.487261 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9334 12:21:13.490658 Root Device init finished in 531 msecs
9335 12:21:13.493934 CPU_CLUSTER: 0 init
9336 12:21:13.500535 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9337 12:21:13.507121 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9338 12:21:13.507202 APU_MBOX 0x190000b0 = 0x10001
9339 12:21:13.510519 APU_MBOX 0x190001b0 = 0x10001
9340 12:21:13.513842 APU_MBOX 0x190005b0 = 0x10001
9341 12:21:13.516745 APU_MBOX 0x190006b0 = 0x10001
9342 12:21:13.523489 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9343 12:21:13.533925 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9344 12:21:13.546287 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9345 12:21:13.552504 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9346 12:21:13.563926 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9347 12:21:13.573588 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9348 12:21:13.576365 CPU_CLUSTER: 0 init finished in 81 msecs
9349 12:21:13.579587 Devices initialized
9350 12:21:13.583405 Show all devs... After init.
9351 12:21:13.583486 Root Device: enabled 1
9352 12:21:13.586666 CPU_CLUSTER: 0: enabled 1
9353 12:21:13.590390 CPU: 00: enabled 1
9354 12:21:13.592866 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9355 12:21:13.596427 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9356 12:21:13.599505 ELOG: NV offset 0x57f000 size 0x1000
9357 12:21:13.606549 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9358 12:21:13.613201 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9359 12:21:13.616293 ELOG: Event(17) added with size 13 at 2023-08-16 12:21:13 UTC
9360 12:21:13.622877 out: cmd=0x121: 03 db 21 01 00 00 00 00
9361 12:21:13.626674 in-header: 03 04 00 00 2c 00 00 00
9362 12:21:13.636082 in-data: 5b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9363 12:21:13.642387 ELOG: Event(A1) added with size 10 at 2023-08-16 12:21:14 UTC
9364 12:21:13.649287 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9365 12:21:13.655791 ELOG: Event(A0) added with size 9 at 2023-08-16 12:21:14 UTC
9366 12:21:13.659912 elog_add_boot_reason: Logged dev mode boot
9367 12:21:13.666229 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9368 12:21:13.666309 Finalize devices...
9369 12:21:13.668904 Devices finalized
9370 12:21:13.672583 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9371 12:21:13.675504 Writing coreboot table at 0xffe64000
9372 12:21:13.678777 0. 000000000010a000-0000000000113fff: RAMSTAGE
9373 12:21:13.685605 1. 0000000040000000-00000000400fffff: RAM
9374 12:21:13.688659 2. 0000000040100000-000000004032afff: RAMSTAGE
9375 12:21:13.691855 3. 000000004032b000-00000000545fffff: RAM
9376 12:21:13.695250 4. 0000000054600000-000000005465ffff: BL31
9377 12:21:13.698489 5. 0000000054660000-00000000ffe63fff: RAM
9378 12:21:13.705210 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9379 12:21:13.708526 7. 0000000100000000-000000023fffffff: RAM
9380 12:21:13.711798 Passing 5 GPIOs to payload:
9381 12:21:13.715035 NAME | PORT | POLARITY | VALUE
9382 12:21:13.722160 EC in RW | 0x000000aa | low | undefined
9383 12:21:13.725358 EC interrupt | 0x00000005 | low | undefined
9384 12:21:13.728089 TPM interrupt | 0x000000ab | high | undefined
9385 12:21:13.734663 SD card detect | 0x00000011 | high | undefined
9386 12:21:13.738447 speaker enable | 0x00000093 | high | undefined
9387 12:21:13.741184 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9388 12:21:13.745227 in-header: 03 f9 00 00 02 00 00 00
9389 12:21:13.748195 in-data: 02 00
9390 12:21:13.751629 ADC[4]: Raw value=903325 ID=7
9391 12:21:13.754508 ADC[3]: Raw value=213916 ID=1
9392 12:21:13.754588 RAM Code: 0x71
9393 12:21:13.757684 ADC[6]: Raw value=75000 ID=0
9394 12:21:13.761227 ADC[5]: Raw value=213546 ID=1
9395 12:21:13.761306 SKU Code: 0x1
9396 12:21:13.767597 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 953a
9397 12:21:13.767677 coreboot table: 964 bytes.
9398 12:21:13.771303 IMD ROOT 0. 0xfffff000 0x00001000
9399 12:21:13.774299 IMD SMALL 1. 0xffffe000 0x00001000
9400 12:21:13.778086 RO MCACHE 2. 0xffffc000 0x00001104
9401 12:21:13.780824 CONSOLE 3. 0xfff7c000 0x00080000
9402 12:21:13.784150 FMAP 4. 0xfff7b000 0x00000452
9403 12:21:13.787648 TIME STAMP 5. 0xfff7a000 0x00000910
9404 12:21:13.791137 VBOOT WORK 6. 0xfff66000 0x00014000
9405 12:21:13.794196 RAMOOPS 7. 0xffe66000 0x00100000
9406 12:21:13.797719 COREBOOT 8. 0xffe64000 0x00002000
9407 12:21:13.800514 IMD small region:
9408 12:21:13.803946 IMD ROOT 0. 0xffffec00 0x00000400
9409 12:21:13.807523 VPD 1. 0xffffeba0 0x0000004c
9410 12:21:13.810755 MMC STATUS 2. 0xffffeb80 0x00000004
9411 12:21:13.817977 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9412 12:21:13.818083 Probing TPM: done!
9413 12:21:13.824234 Connected to device vid:did:rid of 1ae0:0028:00
9414 12:21:13.831348 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9415 12:21:13.834191 Initialized TPM device CR50 revision 0
9416 12:21:13.837872 Checking cr50 for pending updates
9417 12:21:13.842777 Reading cr50 TPM mode
9418 12:21:13.851724 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9419 12:21:13.858158 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9420 12:21:13.898083 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9421 12:21:13.901604 Checking segment from ROM address 0x40100000
9422 12:21:13.904658 Checking segment from ROM address 0x4010001c
9423 12:21:13.911596 Loading segment from ROM address 0x40100000
9424 12:21:13.911702 code (compression=0)
9425 12:21:13.921119 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9426 12:21:13.927683 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9427 12:21:13.927794 it's not compressed!
9428 12:21:13.934355 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9429 12:21:13.941140 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9430 12:21:13.958485 Loading segment from ROM address 0x4010001c
9431 12:21:13.958569 Entry Point 0x80000000
9432 12:21:13.962157 Loaded segments
9433 12:21:13.965501 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9434 12:21:13.971685 Jumping to boot code at 0x80000000(0xffe64000)
9435 12:21:13.978665 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9436 12:21:13.984991 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9437 12:21:13.993164 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9438 12:21:13.996385 Checking segment from ROM address 0x40100000
9439 12:21:13.999703 Checking segment from ROM address 0x4010001c
9440 12:21:14.006438 Loading segment from ROM address 0x40100000
9441 12:21:14.006519 code (compression=1)
9442 12:21:14.013259 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9443 12:21:14.023354 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9444 12:21:14.023435 using LZMA
9445 12:21:14.031428 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9446 12:21:14.038296 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9447 12:21:14.041260 Loading segment from ROM address 0x4010001c
9448 12:21:14.041366 Entry Point 0x54601000
9449 12:21:14.045072 Loaded segments
9450 12:21:14.047867 NOTICE: MT8192 bl31_setup
9451 12:21:14.055182 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9452 12:21:14.058841 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9453 12:21:14.061732 WARNING: region 0:
9454 12:21:14.064879 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 12:21:14.064958 WARNING: region 1:
9456 12:21:14.071550 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9457 12:21:14.074703 WARNING: region 2:
9458 12:21:14.078253 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9459 12:21:14.081918 WARNING: region 3:
9460 12:21:14.084575 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9461 12:21:14.088137 WARNING: region 4:
9462 12:21:14.094782 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9463 12:21:14.094862 WARNING: region 5:
9464 12:21:14.097718 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 12:21:14.101966 WARNING: region 6:
9466 12:21:14.104682 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 12:21:14.107741 WARNING: region 7:
9468 12:21:14.111037 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 12:21:14.117675 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9470 12:21:14.121450 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9471 12:21:14.127777 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9472 12:21:14.131161 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9473 12:21:14.134374 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9474 12:21:14.140982 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9475 12:21:14.144405 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9476 12:21:14.147822 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9477 12:21:14.154149 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9478 12:21:14.157650 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9479 12:21:14.160923 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9480 12:21:14.167921 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9481 12:21:14.171142 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9482 12:21:14.177829 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9483 12:21:14.181049 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9484 12:21:14.184069 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9485 12:21:14.190969 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9486 12:21:14.194293 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9487 12:21:14.197568 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9488 12:21:14.204288 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9489 12:21:14.207747 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9490 12:21:14.214018 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9491 12:21:14.217337 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9492 12:21:14.220750 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9493 12:21:14.227409 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9494 12:21:14.230732 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9495 12:21:14.237357 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9496 12:21:14.240719 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9497 12:21:14.247120 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9498 12:21:14.250647 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9499 12:21:14.253721 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9500 12:21:14.260539 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9501 12:21:14.263850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9502 12:21:14.267602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9503 12:21:14.270896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9504 12:21:14.277032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9505 12:21:14.280370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9506 12:21:14.283844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9507 12:21:14.287623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9508 12:21:14.293602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9509 12:21:14.297520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9510 12:21:14.300565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9511 12:21:14.303553 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9512 12:21:14.310208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9513 12:21:14.313583 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9514 12:21:14.316855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9515 12:21:14.320368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9516 12:21:14.326676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9517 12:21:14.330225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9518 12:21:14.336990 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9519 12:21:14.340204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9520 12:21:14.343723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9521 12:21:14.350614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9522 12:21:14.353792 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9523 12:21:14.360735 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9524 12:21:14.363806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9525 12:21:14.367070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9526 12:21:14.373717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9527 12:21:14.377312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9528 12:21:14.384051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9529 12:21:14.386865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9530 12:21:14.393691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9531 12:21:14.397127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9532 12:21:14.403592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9533 12:21:14.407036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9534 12:21:14.410256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9535 12:21:14.416646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9536 12:21:14.420445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9537 12:21:14.426710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9538 12:21:14.430147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9539 12:21:14.436646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9540 12:21:14.440292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9541 12:21:14.443378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9542 12:21:14.449928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9543 12:21:14.453276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9544 12:21:14.459829 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9545 12:21:14.463167 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9546 12:21:14.469821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9547 12:21:14.473304 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9548 12:21:14.479752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9549 12:21:14.483386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9550 12:21:14.486896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9551 12:21:14.493500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9552 12:21:14.496576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9553 12:21:14.503690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9554 12:21:14.506613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9555 12:21:14.513014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9556 12:21:14.516494 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9557 12:21:14.519601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9558 12:21:14.526322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9559 12:21:14.530276 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9560 12:21:14.536389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9561 12:21:14.539638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9562 12:21:14.546408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9563 12:21:14.549943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9564 12:21:14.556336 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9565 12:21:14.560133 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9566 12:21:14.562845 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9567 12:21:14.566249 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9568 12:21:14.572876 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9569 12:21:14.576057 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9570 12:21:14.579502 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9571 12:21:14.586234 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9572 12:21:14.589850 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9573 12:21:14.596540 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9574 12:21:14.599174 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9575 12:21:14.602762 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9576 12:21:14.609380 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9577 12:21:14.612443 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9578 12:21:14.619658 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9579 12:21:14.622445 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9580 12:21:14.625868 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9581 12:21:14.632320 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9582 12:21:14.635734 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9583 12:21:14.642435 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9584 12:21:14.646143 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9585 12:21:14.649075 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9586 12:21:14.655739 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9587 12:21:14.658955 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9588 12:21:14.662242 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9589 12:21:14.665446 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9590 12:21:14.672202 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9591 12:21:14.675749 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9592 12:21:14.678943 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9593 12:21:14.682574 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9594 12:21:14.689062 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9595 12:21:14.692430 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9596 12:21:14.698954 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9597 12:21:14.702091 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9598 12:21:14.705840 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9599 12:21:14.712499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9600 12:21:14.715709 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9601 12:21:14.721850 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9602 12:21:14.725440 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9603 12:21:14.729218 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9604 12:21:14.735676 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9605 12:21:14.738786 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9606 12:21:14.745609 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9607 12:21:14.748531 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9608 12:21:14.752249 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9609 12:21:14.758653 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9610 12:21:14.762042 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9611 12:21:14.768555 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9612 12:21:14.772136 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9613 12:21:14.775352 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9614 12:21:14.781999 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9615 12:21:14.785549 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9616 12:21:14.788857 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9617 12:21:14.795027 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9618 12:21:14.798703 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9619 12:21:14.805212 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9620 12:21:14.808460 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9621 12:21:14.811701 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9622 12:21:14.818424 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9623 12:21:14.821851 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9624 12:21:14.828987 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9625 12:21:14.831556 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9626 12:21:14.835268 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9627 12:21:14.841755 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9628 12:21:14.844991 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9629 12:21:14.851571 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9630 12:21:14.854671 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9631 12:21:14.858109 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9632 12:21:14.865355 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9633 12:21:14.868073 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9634 12:21:14.874507 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9635 12:21:14.878174 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9636 12:21:14.881106 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9637 12:21:14.887834 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9638 12:21:14.891229 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9639 12:21:14.897406 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9640 12:21:14.900903 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9641 12:21:14.904052 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9642 12:21:14.910396 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9643 12:21:14.913998 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9644 12:21:14.920461 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9645 12:21:14.923718 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9646 12:21:14.927019 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9647 12:21:14.933554 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9648 12:21:14.937241 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9649 12:21:14.943360 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9650 12:21:14.946839 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9651 12:21:14.950311 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9652 12:21:14.956822 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9653 12:21:14.960085 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9654 12:21:14.966740 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9655 12:21:14.970283 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9656 12:21:14.973573 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9657 12:21:14.979786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9658 12:21:14.982951 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9659 12:21:14.989900 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9660 12:21:14.992850 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9661 12:21:14.999698 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9662 12:21:15.003028 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9663 12:21:15.006137 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9664 12:21:15.012583 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9665 12:21:15.016410 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9666 12:21:15.022549 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9667 12:21:15.026282 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9668 12:21:15.032641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9669 12:21:15.036112 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9670 12:21:15.039241 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9671 12:21:15.045814 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9672 12:21:15.049489 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9673 12:21:15.055634 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9674 12:21:15.058571 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9675 12:21:15.065311 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9676 12:21:15.068529 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9677 12:21:15.071804 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9678 12:21:15.078458 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9679 12:21:15.082273 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9680 12:21:15.088846 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9681 12:21:15.091608 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9682 12:21:15.098664 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9683 12:21:15.101748 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9684 12:21:15.105069 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9685 12:21:15.111403 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9686 12:21:15.115148 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9687 12:21:15.121233 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9688 12:21:15.125024 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9689 12:21:15.131229 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9690 12:21:15.134558 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9691 12:21:15.137947 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9692 12:21:15.144331 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9693 12:21:15.147667 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9694 12:21:15.154687 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9695 12:21:15.157437 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9696 12:21:15.164161 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9697 12:21:15.167176 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9698 12:21:15.170626 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9699 12:21:15.174012 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9700 12:21:15.180650 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9701 12:21:15.184254 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9702 12:21:15.187247 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9703 12:21:15.193719 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9704 12:21:15.197037 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9705 12:21:15.200333 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9706 12:21:15.206962 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9707 12:21:15.210024 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9708 12:21:15.213586 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9709 12:21:15.220707 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9710 12:21:15.223386 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9711 12:21:15.230362 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9712 12:21:15.233591 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9713 12:21:15.236864 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9714 12:21:15.243434 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9715 12:21:15.246971 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9716 12:21:15.253024 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9717 12:21:15.256317 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9718 12:21:15.259742 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9719 12:21:15.266163 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9720 12:21:15.269525 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9721 12:21:15.273055 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9722 12:21:15.279418 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9723 12:21:15.282494 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9724 12:21:15.289128 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9725 12:21:15.292549 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9726 12:21:15.295678 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9727 12:21:15.302286 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9728 12:21:15.305571 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9729 12:21:15.308805 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9730 12:21:15.315927 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9731 12:21:15.318769 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9732 12:21:15.322038 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9733 12:21:15.328551 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9734 12:21:15.331783 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9735 12:21:15.338494 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9736 12:21:15.341595 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9737 12:21:15.344682 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9738 12:21:15.351361 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9739 12:21:15.355000 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9740 12:21:15.358047 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9741 12:21:15.361254 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9742 12:21:15.365050 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9743 12:21:15.371423 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9744 12:21:15.374559 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9745 12:21:15.377597 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9746 12:21:15.384433 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9747 12:21:15.387777 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9748 12:21:15.391028 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9749 12:21:15.397573 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9750 12:21:15.400687 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9751 12:21:15.404080 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9752 12:21:15.411256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9753 12:21:15.414204 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9754 12:21:15.420778 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9755 12:21:15.424369 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9756 12:21:15.427666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9757 12:21:15.433781 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9758 12:21:15.437166 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9759 12:21:15.443920 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9760 12:21:15.446803 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9761 12:21:15.450416 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9762 12:21:15.456766 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9763 12:21:15.460261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9764 12:21:15.466979 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9765 12:21:15.470223 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9766 12:21:15.476861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9767 12:21:15.479798 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9768 12:21:15.483289 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9769 12:21:15.489613 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9770 12:21:15.493075 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9771 12:21:15.499350 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9772 12:21:15.502954 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9773 12:21:15.509441 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9774 12:21:15.512650 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9775 12:21:15.516023 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9776 12:21:15.522914 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9777 12:21:15.525817 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9778 12:21:15.532514 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9779 12:21:15.535447 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9780 12:21:15.542538 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9781 12:21:15.545675 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9782 12:21:15.548981 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9783 12:21:15.555207 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9784 12:21:15.559060 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9785 12:21:15.565069 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9786 12:21:15.568874 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9787 12:21:15.571765 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9788 12:21:15.578310 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9789 12:21:15.581792 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9790 12:21:15.588283 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9791 12:21:15.591670 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9792 12:21:15.598452 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9793 12:21:15.601412 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9794 12:21:15.604926 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9795 12:21:15.611387 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9796 12:21:15.614658 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9797 12:21:15.621396 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9798 12:21:15.624654 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9799 12:21:15.627533 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9800 12:21:15.634832 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9801 12:21:15.638069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9802 12:21:15.644213 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9803 12:21:15.647364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9804 12:21:15.654314 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9805 12:21:15.657396 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9806 12:21:15.660713 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9807 12:21:15.667185 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9808 12:21:15.670884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9809 12:21:15.677299 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9810 12:21:15.680460 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9811 12:21:15.687609 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9812 12:21:15.690062 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9813 12:21:15.693449 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9814 12:21:15.700240 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9815 12:21:15.703342 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9816 12:21:15.709949 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9817 12:21:15.713061 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9818 12:21:15.719866 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9819 12:21:15.723713 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9820 12:21:15.726392 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9821 12:21:15.732773 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9822 12:21:15.736170 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9823 12:21:15.742752 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9824 12:21:15.745985 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9825 12:21:15.752571 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9826 12:21:15.756177 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9827 12:21:15.759344 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9828 12:21:15.765689 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9829 12:21:15.769060 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9830 12:21:15.775627 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9831 12:21:15.779112 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9832 12:21:15.785576 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9833 12:21:15.788756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9834 12:21:15.795593 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9835 12:21:15.799181 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9836 12:21:15.805665 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9837 12:21:15.808851 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9838 12:21:15.812156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9839 12:21:15.818864 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9840 12:21:15.821684 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9841 12:21:15.828678 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9842 12:21:15.831544 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9843 12:21:15.838190 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9844 12:21:15.841429 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9845 12:21:15.848313 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9846 12:21:15.851854 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9847 12:21:15.854652 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9848 12:21:15.861289 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9849 12:21:15.864444 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9850 12:21:15.871299 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9851 12:21:15.874273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9852 12:21:15.880959 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9853 12:21:15.884493 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9854 12:21:15.887819 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9855 12:21:15.894235 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9856 12:21:15.897525 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9857 12:21:15.904240 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9858 12:21:15.907314 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9859 12:21:15.913935 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9860 12:21:15.917295 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9861 12:21:15.923754 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9862 12:21:15.927288 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9863 12:21:15.930276 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9864 12:21:15.937106 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9865 12:21:15.940492 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9866 12:21:15.946686 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9867 12:21:15.950514 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9868 12:21:15.956524 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9869 12:21:15.960343 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9870 12:21:15.966822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9871 12:21:15.969346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9872 12:21:15.972936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9873 12:21:15.979554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9874 12:21:15.983664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9875 12:21:15.989152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9876 12:21:15.992453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9877 12:21:15.999222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9878 12:21:16.002533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9879 12:21:16.009397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9880 12:21:16.012993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9881 12:21:16.019020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9882 12:21:16.022145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9883 12:21:16.028915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9884 12:21:16.032093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9885 12:21:16.038597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9886 12:21:16.041691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9887 12:21:16.048637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9888 12:21:16.051488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9889 12:21:16.058598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9890 12:21:16.061390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9891 12:21:16.068148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9892 12:21:16.071554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9893 12:21:16.078377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9894 12:21:16.081446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9895 12:21:16.087635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9896 12:21:16.094404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9897 12:21:16.097580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9898 12:21:16.104190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9899 12:21:16.107595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9900 12:21:16.113938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9901 12:21:16.117293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9902 12:21:16.124284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9903 12:21:16.127043 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9904 12:21:16.130454 INFO: [APUAPC] vio 0
9905 12:21:16.133828 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9906 12:21:16.137360 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9907 12:21:16.141059 INFO: [APUAPC] D0_APC_0: 0x400510
9908 12:21:16.144304 INFO: [APUAPC] D0_APC_1: 0x0
9909 12:21:16.146811 INFO: [APUAPC] D0_APC_2: 0x1540
9910 12:21:16.150441 INFO: [APUAPC] D0_APC_3: 0x0
9911 12:21:16.153443 INFO: [APUAPC] D1_APC_0: 0xffffffff
9912 12:21:16.157159 INFO: [APUAPC] D1_APC_1: 0xffffffff
9913 12:21:16.159961 INFO: [APUAPC] D1_APC_2: 0x3fffff
9914 12:21:16.163294 INFO: [APUAPC] D1_APC_3: 0x0
9915 12:21:16.166904 INFO: [APUAPC] D2_APC_0: 0xffffffff
9916 12:21:16.170073 INFO: [APUAPC] D2_APC_1: 0xffffffff
9917 12:21:16.173949 INFO: [APUAPC] D2_APC_2: 0x3fffff
9918 12:21:16.176807 INFO: [APUAPC] D2_APC_3: 0x0
9919 12:21:16.179772 INFO: [APUAPC] D3_APC_0: 0xffffffff
9920 12:21:16.183023 INFO: [APUAPC] D3_APC_1: 0xffffffff
9921 12:21:16.186564 INFO: [APUAPC] D3_APC_2: 0x3fffff
9922 12:21:16.189966 INFO: [APUAPC] D3_APC_3: 0x0
9923 12:21:16.193068 INFO: [APUAPC] D4_APC_0: 0xffffffff
9924 12:21:16.196095 INFO: [APUAPC] D4_APC_1: 0xffffffff
9925 12:21:16.199911 INFO: [APUAPC] D4_APC_2: 0x3fffff
9926 12:21:16.203234 INFO: [APUAPC] D4_APC_3: 0x0
9927 12:21:16.206386 INFO: [APUAPC] D5_APC_0: 0xffffffff
9928 12:21:16.209686 INFO: [APUAPC] D5_APC_1: 0xffffffff
9929 12:21:16.212853 INFO: [APUAPC] D5_APC_2: 0x3fffff
9930 12:21:16.216627 INFO: [APUAPC] D5_APC_3: 0x0
9931 12:21:16.219771 INFO: [APUAPC] D6_APC_0: 0xffffffff
9932 12:21:16.222751 INFO: [APUAPC] D6_APC_1: 0xffffffff
9933 12:21:16.226289 INFO: [APUAPC] D6_APC_2: 0x3fffff
9934 12:21:16.229163 INFO: [APUAPC] D6_APC_3: 0x0
9935 12:21:16.233037 INFO: [APUAPC] D7_APC_0: 0xffffffff
9936 12:21:16.236251 INFO: [APUAPC] D7_APC_1: 0xffffffff
9937 12:21:16.239066 INFO: [APUAPC] D7_APC_2: 0x3fffff
9938 12:21:16.242510 INFO: [APUAPC] D7_APC_3: 0x0
9939 12:21:16.245924 INFO: [APUAPC] D8_APC_0: 0xffffffff
9940 12:21:16.248988 INFO: [APUAPC] D8_APC_1: 0xffffffff
9941 12:21:16.252342 INFO: [APUAPC] D8_APC_2: 0x3fffff
9942 12:21:16.255715 INFO: [APUAPC] D8_APC_3: 0x0
9943 12:21:16.258747 INFO: [APUAPC] D9_APC_0: 0xffffffff
9944 12:21:16.262526 INFO: [APUAPC] D9_APC_1: 0xffffffff
9945 12:21:16.265679 INFO: [APUAPC] D9_APC_2: 0x3fffff
9946 12:21:16.268778 INFO: [APUAPC] D9_APC_3: 0x0
9947 12:21:16.271896 INFO: [APUAPC] D10_APC_0: 0xffffffff
9948 12:21:16.275831 INFO: [APUAPC] D10_APC_1: 0xffffffff
9949 12:21:16.278431 INFO: [APUAPC] D10_APC_2: 0x3fffff
9950 12:21:16.281698 INFO: [APUAPC] D10_APC_3: 0x0
9951 12:21:16.285643 INFO: [APUAPC] D11_APC_0: 0xffffffff
9952 12:21:16.288868 INFO: [APUAPC] D11_APC_1: 0xffffffff
9953 12:21:16.291624 INFO: [APUAPC] D11_APC_2: 0x3fffff
9954 12:21:16.295083 INFO: [APUAPC] D11_APC_3: 0x0
9955 12:21:16.298278 INFO: [APUAPC] D12_APC_0: 0xffffffff
9956 12:21:16.301462 INFO: [APUAPC] D12_APC_1: 0xffffffff
9957 12:21:16.304958 INFO: [APUAPC] D12_APC_2: 0x3fffff
9958 12:21:16.308371 INFO: [APUAPC] D12_APC_3: 0x0
9959 12:21:16.311612 INFO: [APUAPC] D13_APC_0: 0xffffffff
9960 12:21:16.314710 INFO: [APUAPC] D13_APC_1: 0xffffffff
9961 12:21:16.318173 INFO: [APUAPC] D13_APC_2: 0x3fffff
9962 12:21:16.321647 INFO: [APUAPC] D13_APC_3: 0x0
9963 12:21:16.324954 INFO: [APUAPC] D14_APC_0: 0xffffffff
9964 12:21:16.328406 INFO: [APUAPC] D14_APC_1: 0xffffffff
9965 12:21:16.331276 INFO: [APUAPC] D14_APC_2: 0x3fffff
9966 12:21:16.334453 INFO: [APUAPC] D14_APC_3: 0x0
9967 12:21:16.337750 INFO: [APUAPC] D15_APC_0: 0xffffffff
9968 12:21:16.341388 INFO: [APUAPC] D15_APC_1: 0xffffffff
9969 12:21:16.344394 INFO: [APUAPC] D15_APC_2: 0x3fffff
9970 12:21:16.347738 INFO: [APUAPC] D15_APC_3: 0x0
9971 12:21:16.350970 INFO: [APUAPC] APC_CON: 0x4
9972 12:21:16.354058 INFO: [NOCDAPC] D0_APC_0: 0x0
9973 12:21:16.357518 INFO: [NOCDAPC] D0_APC_1: 0x0
9974 12:21:16.360984 INFO: [NOCDAPC] D1_APC_0: 0x0
9975 12:21:16.361064 INFO: [NOCDAPC] D1_APC_1: 0xfff
9976 12:21:16.364278 INFO: [NOCDAPC] D2_APC_0: 0x0
9977 12:21:16.367544 INFO: [NOCDAPC] D2_APC_1: 0xfff
9978 12:21:16.371076 INFO: [NOCDAPC] D3_APC_0: 0x0
9979 12:21:16.374501 INFO: [NOCDAPC] D3_APC_1: 0xfff
9980 12:21:16.377471 INFO: [NOCDAPC] D4_APC_0: 0x0
9981 12:21:16.380581 INFO: [NOCDAPC] D4_APC_1: 0xfff
9982 12:21:16.384106 INFO: [NOCDAPC] D5_APC_0: 0x0
9983 12:21:16.387433 INFO: [NOCDAPC] D5_APC_1: 0xfff
9984 12:21:16.390667 INFO: [NOCDAPC] D6_APC_0: 0x0
9985 12:21:16.394135 INFO: [NOCDAPC] D6_APC_1: 0xfff
9986 12:21:16.397515 INFO: [NOCDAPC] D7_APC_0: 0x0
9987 12:21:16.397595 INFO: [NOCDAPC] D7_APC_1: 0xfff
9988 12:21:16.400383 INFO: [NOCDAPC] D8_APC_0: 0x0
9989 12:21:16.403672 INFO: [NOCDAPC] D8_APC_1: 0xfff
9990 12:21:16.407509 INFO: [NOCDAPC] D9_APC_0: 0x0
9991 12:21:16.410283 INFO: [NOCDAPC] D9_APC_1: 0xfff
9992 12:21:16.413733 INFO: [NOCDAPC] D10_APC_0: 0x0
9993 12:21:16.417105 INFO: [NOCDAPC] D10_APC_1: 0xfff
9994 12:21:16.420799 INFO: [NOCDAPC] D11_APC_0: 0x0
9995 12:21:16.423573 INFO: [NOCDAPC] D11_APC_1: 0xfff
9996 12:21:16.427050 INFO: [NOCDAPC] D12_APC_0: 0x0
9997 12:21:16.429963 INFO: [NOCDAPC] D12_APC_1: 0xfff
9998 12:21:16.433647 INFO: [NOCDAPC] D13_APC_0: 0x0
9999 12:21:16.437000 INFO: [NOCDAPC] D13_APC_1: 0xfff
10000 12:21:16.440289 INFO: [NOCDAPC] D14_APC_0: 0x0
10001 12:21:16.443434 INFO: [NOCDAPC] D14_APC_1: 0xfff
10002 12:21:16.443515 INFO: [NOCDAPC] D15_APC_0: 0x0
10003 12:21:16.446639 INFO: [NOCDAPC] D15_APC_1: 0xfff
10004 12:21:16.449754 INFO: [NOCDAPC] APC_CON: 0x4
10005 12:21:16.453515 INFO: [APUAPC] set_apusys_apc done
10006 12:21:16.456245 INFO: [DEVAPC] devapc_init done
10007 12:21:16.462778 INFO: GICv3 without legacy support detected.
10008 12:21:16.466010 INFO: ARM GICv3 driver initialized in EL3
10009 12:21:16.469947 INFO: Maximum SPI INTID supported: 639
10010 12:21:16.472767 INFO: BL31: Initializing runtime services
10011 12:21:16.479381 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10012 12:21:16.482674 INFO: SPM: enable CPC mode
10013 12:21:16.485599 INFO: mcdi ready for mcusys-off-idle and system suspend
10014 12:21:16.492683 INFO: BL31: Preparing for EL3 exit to normal world
10015 12:21:16.495385 INFO: Entry point address = 0x80000000
10016 12:21:16.495466 INFO: SPSR = 0x8
10017 12:21:16.502890
10018 12:21:16.502970
10019 12:21:16.503033
10020 12:21:16.506641 Starting depthcharge on Spherion...
10021 12:21:16.506734
10022 12:21:16.506799 Wipe memory regions:
10023 12:21:16.506858
10024 12:21:16.507508 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10025 12:21:16.507613 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10026 12:21:16.507694 Setting prompt string to ['asurada:']
10027 12:21:16.507772 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10028 12:21:16.509326 [0x00000040000000, 0x00000054600000)
10029 12:21:16.631658
10030 12:21:16.631800 [0x00000054660000, 0x00000080000000)
10031 12:21:16.892241
10032 12:21:16.892375 [0x000000821a7280, 0x000000ffe64000)
10033 12:21:17.637126
10034 12:21:17.637266 [0x00000100000000, 0x00000240000000)
10035 12:21:19.527348
10036 12:21:19.530466 Initializing XHCI USB controller at 0x11200000.
10037 12:21:20.568380
10038 12:21:20.571828 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10039 12:21:20.571921
10040 12:21:20.571985
10041 12:21:20.572045
10042 12:21:20.572323 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10044 12:21:20.672663 asurada: tftpboot 192.168.201.1 11299281/tftp-deploy-fog2iav_/kernel/image.itb 11299281/tftp-deploy-fog2iav_/kernel/cmdline
10045 12:21:20.672788 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 12:21:20.672871 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10047 12:21:20.677336 tftpboot 192.168.201.1 11299281/tftp-deploy-fog2iav_/kernel/image.itbtp-deploy-fog2iav_/kernel/cmdline
10048 12:21:20.677422
10049 12:21:20.677485 Waiting for link
10050 12:21:20.837865
10051 12:21:20.838001 R8152: Initializing
10052 12:21:20.838068
10053 12:21:20.841341 Version 6 (ocp_data = 5c30)
10054 12:21:20.841422
10055 12:21:20.844612 R8152: Done initializing
10056 12:21:20.844693
10057 12:21:20.844755 Adding net device
10058 12:21:22.809785
10059 12:21:22.809930 done.
10060 12:21:22.809996
10061 12:21:22.810056 MAC: 00:24:32:30:7c:7b
10062 12:21:22.810115
10063 12:21:22.812951 Sending DHCP discover... done.
10064 12:21:22.813032
10065 12:21:26.440797 Waiting for reply... done.
10066 12:21:26.440943
10067 12:21:26.441011 Sending DHCP request... done.
10068 12:21:26.444091
10069 12:21:26.448617 Waiting for reply... done.
10070 12:21:26.448697
10071 12:21:26.448760 My ip is 192.168.201.14
10072 12:21:26.448819
10073 12:21:26.452140 The DHCP server ip is 192.168.201.1
10074 12:21:26.452219
10075 12:21:26.458770 TFTP server IP predefined by user: 192.168.201.1
10076 12:21:26.458850
10077 12:21:26.465298 Bootfile predefined by user: 11299281/tftp-deploy-fog2iav_/kernel/image.itb
10078 12:21:26.465379
10079 12:21:26.468391 Sending tftp read request... done.
10080 12:21:26.468483
10081 12:21:26.472646 Waiting for the transfer...
10082 12:21:26.472741
10083 12:21:27.030066 00000000 ################################################################
10084 12:21:27.030204
10085 12:21:27.590158 00080000 ################################################################
10086 12:21:27.590303
10087 12:21:28.140925 00100000 ################################################################
10088 12:21:28.141075
10089 12:21:28.694077 00180000 ################################################################
10090 12:21:28.694222
10091 12:21:29.205722 00200000 ################################################################
10092 12:21:29.205870
10093 12:21:29.745472 00280000 ################################################################
10094 12:21:29.745623
10095 12:21:30.286912 00300000 ################################################################
10096 12:21:30.287061
10097 12:21:30.810884 00380000 ################################################################
10098 12:21:30.811032
10099 12:21:31.332073 00400000 ################################################################
10100 12:21:31.332227
10101 12:21:31.885181 00480000 ################################################################
10102 12:21:31.885317
10103 12:21:32.431759 00500000 ################################################################
10104 12:21:32.431898
10105 12:21:32.985083 00580000 ################################################################
10106 12:21:32.985222
10107 12:21:33.541526 00600000 ################################################################
10108 12:21:33.541670
10109 12:21:34.088551 00680000 ################################################################
10110 12:21:34.088694
10111 12:21:34.655710 00700000 ################################################################
10112 12:21:34.655859
10113 12:21:35.193014 00780000 ################################################################
10114 12:21:35.193160
10115 12:21:35.751809 00800000 ################################################################
10116 12:21:35.752012
10117 12:21:36.304477 00880000 ################################################################
10118 12:21:36.304625
10119 12:21:36.857408 00900000 ################################################################
10120 12:21:36.857539
10121 12:21:37.400552 00980000 ################################################################
10122 12:21:37.400686
10123 12:21:37.957262 00a00000 ################################################################
10124 12:21:37.957394
10125 12:21:38.517864 00a80000 ################################################################
10126 12:21:38.518002
10127 12:21:39.074680 00b00000 ################################################################
10128 12:21:39.074821
10129 12:21:39.605568 00b80000 ################################################################
10130 12:21:39.605705
10131 12:21:40.139895 00c00000 ################################################################
10132 12:21:40.140067
10133 12:21:40.673588 00c80000 ################################################################
10134 12:21:40.673729
10135 12:21:41.233810 00d00000 ################################################################
10136 12:21:41.233949
10137 12:21:41.765831 00d80000 ################################################################
10138 12:21:41.765968
10139 12:21:42.301728 00e00000 ################################################################
10140 12:21:42.301862
10141 12:21:42.837050 00e80000 ################################################################
10142 12:21:42.837190
10143 12:21:43.377724 00f00000 ################################################################
10144 12:21:43.377872
10145 12:21:43.909862 00f80000 ################################################################
10146 12:21:43.910002
10147 12:21:44.460764 01000000 ################################################################
10148 12:21:44.460904
10149 12:21:45.021652 01080000 ################################################################
10150 12:21:45.021796
10151 12:21:45.576517 01100000 ################################################################
10152 12:21:45.576700
10153 12:21:46.129617 01180000 ################################################################
10154 12:21:46.129767
10155 12:21:46.680830 01200000 ################################################################
10156 12:21:46.680968
10157 12:21:47.207762 01280000 ################################################################
10158 12:21:47.207941
10159 12:21:47.757970 01300000 ################################################################
10160 12:21:47.758118
10161 12:21:48.322907 01380000 ################################################################
10162 12:21:48.323040
10163 12:21:48.876631 01400000 ################################################################
10164 12:21:48.876769
10165 12:21:49.435835 01480000 ################################################################
10166 12:21:49.435977
10167 12:21:49.983117 01500000 ################################################################
10168 12:21:49.983257
10169 12:21:50.535243 01580000 ################################################################
10170 12:21:50.535380
10171 12:21:51.074954 01600000 ################################################################
10172 12:21:51.075096
10173 12:21:51.628850 01680000 ################################################################
10174 12:21:51.628996
10175 12:21:52.150478 01700000 ################################################################
10176 12:21:52.150624
10177 12:21:52.689157 01780000 ################################################################
10178 12:21:52.689305
10179 12:21:53.235575 01800000 ################################################################
10180 12:21:53.235723
10181 12:21:53.762951 01880000 ################################################################
10182 12:21:53.763099
10183 12:21:54.313132 01900000 ################################################################
10184 12:21:54.313276
10185 12:21:54.875484 01980000 ################################################################
10186 12:21:54.875630
10187 12:21:55.410124 01a00000 ################################################################
10188 12:21:55.410294
10189 12:21:55.940768 01a80000 ################################################################
10190 12:21:55.940915
10191 12:21:56.468114 01b00000 ################################################################
10192 12:21:56.468266
10193 12:21:56.994004 01b80000 ################################################################
10194 12:21:56.994153
10195 12:21:57.514416 01c00000 ################################################################
10196 12:21:57.514562
10197 12:21:58.032736 01c80000 ################################################################
10198 12:21:58.032875
10199 12:21:58.592515 01d00000 ################################################################
10200 12:21:58.592698
10201 12:21:59.137914 01d80000 ################################################################
10202 12:21:59.138061
10203 12:21:59.688743 01e00000 ################################################################
10204 12:21:59.688892
10205 12:22:00.190065 01e80000 ########################################################## done.
10206 12:22:00.190207
10207 12:22:00.193361 The bootfile was 32448710 bytes long.
10208 12:22:00.193531
10209 12:22:00.197037 Sending tftp read request... done.
10210 12:22:00.197169
10211 12:22:00.197242 Waiting for the transfer...
10212 12:22:00.197312
10213 12:22:00.200182 00000000 # done.
10214 12:22:00.200277
10215 12:22:00.206785 Command line loaded dynamically from TFTP file: 11299281/tftp-deploy-fog2iav_/kernel/cmdline
10216 12:22:00.206896
10217 12:22:00.219880 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10218 12:22:00.223529
10219 12:22:00.223675 Loading FIT.
10220 12:22:00.223789
10221 12:22:00.226514 Image ramdisk-1 has 21359021 bytes.
10222 12:22:00.226681
10223 12:22:00.229743 Image fdt-1 has 47278 bytes.
10224 12:22:00.229910
10225 12:22:00.233238 Image kernel-1 has 11040376 bytes.
10226 12:22:00.233475
10227 12:22:00.239809 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10228 12:22:00.240059
10229 12:22:00.259711 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10230 12:22:00.260300
10231 12:22:00.262907 Choosing best match conf-1 for compat google,spherion-rev2.
10232 12:22:00.268016
10233 12:22:00.272828 Connected to device vid:did:rid of 1ae0:0028:00
10234 12:22:00.281038
10235 12:22:00.284599 tpm_get_response: command 0x17b, return code 0x0
10236 12:22:00.285083
10237 12:22:00.287206 ec_init: CrosEC protocol v3 supported (256, 248)
10238 12:22:00.291178
10239 12:22:00.294893 tpm_cleanup: add release locality here.
10240 12:22:00.295320
10241 12:22:00.295656 Shutting down all USB controllers.
10242 12:22:00.297375
10243 12:22:00.297848 Removing current net device
10244 12:22:00.298188
10245 12:22:00.304003 Exiting depthcharge with code 4 at timestamp: 73084917
10246 12:22:00.304491
10247 12:22:00.307491 LZMA decompressing kernel-1 to 0x821a6718
10248 12:22:00.308015
10249 12:22:00.310763 LZMA decompressing kernel-1 to 0x40000000
10250 12:22:01.698588
10251 12:22:01.699309 jumping to kernel
10252 12:22:01.700702 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10253 12:22:01.701191 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10254 12:22:01.701565 Setting prompt string to ['Linux version [0-9]']
10255 12:22:01.701912 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10256 12:22:01.702255 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10257 12:22:01.780076
10258 12:22:01.783574 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10259 12:22:01.787383 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10260 12:22:01.788000 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10261 12:22:01.788641 Setting prompt string to []
10262 12:22:01.789142 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10263 12:22:01.789563 Using line separator: #'\n'#
10264 12:22:01.789973 No login prompt set.
10265 12:22:01.790322 Parsing kernel messages
10266 12:22:01.790638 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10267 12:22:01.791362 [login-action] Waiting for messages, (timeout 00:03:40)
10268 12:22:01.805952 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j14831-arm64-gcc-10-defconfig-arm64-chromebook-g8jrt) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 16 12:04:53 UTC 2023
10269 12:22:01.809366 [ 0.000000] random: crng init done
10270 12:22:01.816050 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10271 12:22:01.819521 [ 0.000000] efi: UEFI not found.
10272 12:22:01.826683 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10273 12:22:01.835778 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10274 12:22:01.842785 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10275 12:22:01.852527 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10276 12:22:01.858933 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10277 12:22:01.865022 [ 0.000000] printk: bootconsole [mtk8250] enabled
10278 12:22:01.872017 [ 0.000000] NUMA: No NUMA configuration found
10279 12:22:01.878811 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10280 12:22:01.884946 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10281 12:22:01.885036 [ 0.000000] Zone ranges:
10282 12:22:01.891591 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10283 12:22:01.894786 [ 0.000000] DMA32 empty
10284 12:22:01.901629 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10285 12:22:01.905504 [ 0.000000] Movable zone start for each node
10286 12:22:01.908454 [ 0.000000] Early memory node ranges
10287 12:22:01.914651 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10288 12:22:01.921090 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10289 12:22:01.927653 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10290 12:22:01.934318 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10291 12:22:01.941540 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10292 12:22:01.947743 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10293 12:22:02.004397 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10294 12:22:02.011216 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10295 12:22:02.017523 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10296 12:22:02.020456 [ 0.000000] psci: probing for conduit method from DT.
10297 12:22:02.027152 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10298 12:22:02.030343 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10299 12:22:02.037059 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10300 12:22:02.040571 [ 0.000000] psci: SMC Calling Convention v1.2
10301 12:22:02.046894 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10302 12:22:02.050389 [ 0.000000] Detected VIPT I-cache on CPU0
10303 12:22:02.057578 [ 0.000000] CPU features: detected: GIC system register CPU interface
10304 12:22:02.063521 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10305 12:22:02.070672 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10306 12:22:02.076577 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10307 12:22:02.086916 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10308 12:22:02.093699 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10309 12:22:02.096745 [ 0.000000] alternatives: applying boot alternatives
10310 12:22:02.103471 [ 0.000000] Fallback order for Node 0: 0
10311 12:22:02.110242 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10312 12:22:02.113406 [ 0.000000] Policy zone: Normal
10313 12:22:02.127093 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10314 12:22:02.136308 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10315 12:22:02.148987 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10316 12:22:02.158842 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10317 12:22:02.165197 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10318 12:22:02.168759 <6>[ 0.000000] software IO TLB: area num 8.
10319 12:22:02.225808 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10320 12:22:02.374320 <6>[ 0.000000] Memory: 7948700K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 404068K reserved, 32768K cma-reserved)
10321 12:22:02.380961 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10322 12:22:02.387644 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10323 12:22:02.390726 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10324 12:22:02.397412 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10325 12:22:02.404091 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10326 12:22:02.407496 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10327 12:22:02.417429 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10328 12:22:02.424071 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10329 12:22:02.430542 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10330 12:22:02.436786 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10331 12:22:02.440227 <6>[ 0.000000] GICv3: 608 SPIs implemented
10332 12:22:02.443626 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10333 12:22:02.449931 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10334 12:22:02.453931 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10335 12:22:02.459984 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10336 12:22:02.473219 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10337 12:22:02.486159 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10338 12:22:02.492889 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10339 12:22:02.500896 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10340 12:22:02.514536 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10341 12:22:02.520564 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10342 12:22:02.527801 <6>[ 0.009181] Console: colour dummy device 80x25
10343 12:22:02.538351 <6>[ 0.013937] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10344 12:22:02.543938 <6>[ 0.024379] pid_max: default: 32768 minimum: 301
10345 12:22:02.546734 <6>[ 0.029250] LSM: Security Framework initializing
10346 12:22:02.553343 <6>[ 0.034219] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10347 12:22:02.563224 <6>[ 0.042032] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10348 12:22:02.573387 <6>[ 0.051422] cblist_init_generic: Setting adjustable number of callback queues.
10349 12:22:02.579536 <6>[ 0.058868] cblist_init_generic: Setting shift to 3 and lim to 1.
10350 12:22:02.586291 <6>[ 0.065207] cblist_init_generic: Setting adjustable number of callback queues.
10351 12:22:02.593237 <6>[ 0.072633] cblist_init_generic: Setting shift to 3 and lim to 1.
10352 12:22:02.596152 <6>[ 0.079071] rcu: Hierarchical SRCU implementation.
10353 12:22:02.603143 <6>[ 0.084085] rcu: Max phase no-delay instances is 1000.
10354 12:22:02.609737 <6>[ 0.091117] EFI services will not be available.
10355 12:22:02.612897 <6>[ 0.096086] smp: Bringing up secondary CPUs ...
10356 12:22:02.622056 <6>[ 0.101139] Detected VIPT I-cache on CPU1
10357 12:22:02.628599 <6>[ 0.101209] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10358 12:22:02.635486 <6>[ 0.101240] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10359 12:22:02.638104 <6>[ 0.101574] Detected VIPT I-cache on CPU2
10360 12:22:02.647979 <6>[ 0.101626] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10361 12:22:02.654604 <6>[ 0.101641] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10362 12:22:02.657992 <6>[ 0.101901] Detected VIPT I-cache on CPU3
10363 12:22:02.664839 <6>[ 0.101947] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10364 12:22:02.671018 <6>[ 0.101961] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10365 12:22:02.677551 <6>[ 0.102267] CPU features: detected: Spectre-v4
10366 12:22:02.681524 <6>[ 0.102272] CPU features: detected: Spectre-BHB
10367 12:22:02.684668 <6>[ 0.102277] Detected PIPT I-cache on CPU4
10368 12:22:02.690820 <6>[ 0.102333] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10369 12:22:02.697779 <6>[ 0.102351] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10370 12:22:02.704032 <6>[ 0.102643] Detected PIPT I-cache on CPU5
10371 12:22:02.711008 <6>[ 0.102705] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10372 12:22:02.717239 <6>[ 0.102721] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10373 12:22:02.720776 <6>[ 0.103004] Detected PIPT I-cache on CPU6
10374 12:22:02.730378 <6>[ 0.103068] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10375 12:22:02.736987 <6>[ 0.103085] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10376 12:22:02.740092 <6>[ 0.103382] Detected PIPT I-cache on CPU7
10377 12:22:02.747149 <6>[ 0.103446] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10378 12:22:02.753647 <6>[ 0.103462] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10379 12:22:02.756967 <6>[ 0.103510] smp: Brought up 1 node, 8 CPUs
10380 12:22:02.763410 <6>[ 0.244903] SMP: Total of 8 processors activated.
10381 12:22:02.770024 <6>[ 0.249854] CPU features: detected: 32-bit EL0 Support
10382 12:22:02.776757 <6>[ 0.255217] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10383 12:22:02.783211 <6>[ 0.264018] CPU features: detected: Common not Private translations
10384 12:22:02.789563 <6>[ 0.270493] CPU features: detected: CRC32 instructions
10385 12:22:02.796190 <6>[ 0.275845] CPU features: detected: RCpc load-acquire (LDAPR)
10386 12:22:02.800036 <6>[ 0.281805] CPU features: detected: LSE atomic instructions
10387 12:22:02.806542 <6>[ 0.287622] CPU features: detected: Privileged Access Never
10388 12:22:02.812786 <6>[ 0.293438] CPU features: detected: RAS Extension Support
10389 12:22:02.820055 <6>[ 0.299081] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10390 12:22:02.822958 <6>[ 0.306345] CPU: All CPU(s) started at EL2
10391 12:22:02.829288 <6>[ 0.310662] alternatives: applying system-wide alternatives
10392 12:22:02.839700 <6>[ 0.321307] devtmpfs: initialized
10393 12:22:02.852245 <6>[ 0.330199] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10394 12:22:02.861932 <6>[ 0.340163] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10395 12:22:02.868161 <6>[ 0.348176] pinctrl core: initialized pinctrl subsystem
10396 12:22:02.871472 <6>[ 0.354863] DMI not present or invalid.
10397 12:22:02.878638 <6>[ 0.359274] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10398 12:22:02.887959 <6>[ 0.366121] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10399 12:22:02.894468 <6>[ 0.373703] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10400 12:22:02.904344 <6>[ 0.381917] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10401 12:22:02.907319 <6>[ 0.390162] audit: initializing netlink subsys (disabled)
10402 12:22:02.917722 <5>[ 0.395857] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10403 12:22:02.924106 <6>[ 0.396575] thermal_sys: Registered thermal governor 'step_wise'
10404 12:22:02.930737 <6>[ 0.403822] thermal_sys: Registered thermal governor 'power_allocator'
10405 12:22:02.934194 <6>[ 0.410080] cpuidle: using governor menu
10406 12:22:02.940272 <6>[ 0.421039] NET: Registered PF_QIPCRTR protocol family
10407 12:22:02.947187 <6>[ 0.426518] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10408 12:22:02.953904 <6>[ 0.433622] ASID allocator initialised with 32768 entries
10409 12:22:02.957440 <6>[ 0.440191] Serial: AMBA PL011 UART driver
10410 12:22:02.967298 <4>[ 0.448996] Trying to register duplicate clock ID: 134
10411 12:22:03.021469 <6>[ 0.506384] KASLR enabled
10412 12:22:03.035755 <6>[ 0.514119] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10413 12:22:03.042341 <6>[ 0.521134] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10414 12:22:03.048600 <6>[ 0.527626] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10415 12:22:03.055287 <6>[ 0.534630] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10416 12:22:03.061803 <6>[ 0.541115] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10417 12:22:03.068265 <6>[ 0.548119] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10418 12:22:03.075077 <6>[ 0.554605] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10419 12:22:03.081769 <6>[ 0.561611] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10420 12:22:03.085402 <6>[ 0.569106] ACPI: Interpreter disabled.
10421 12:22:03.093920 <6>[ 0.575500] iommu: Default domain type: Translated
10422 12:22:03.100389 <6>[ 0.580612] iommu: DMA domain TLB invalidation policy: strict mode
10423 12:22:03.103443 <5>[ 0.587259] SCSI subsystem initialized
10424 12:22:03.110125 <6>[ 0.591421] usbcore: registered new interface driver usbfs
10425 12:22:03.116694 <6>[ 0.597151] usbcore: registered new interface driver hub
10426 12:22:03.120206 <6>[ 0.602703] usbcore: registered new device driver usb
10427 12:22:03.127300 <6>[ 0.608796] pps_core: LinuxPPS API ver. 1 registered
10428 12:22:03.137143 <6>[ 0.613988] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10429 12:22:03.140294 <6>[ 0.623336] PTP clock support registered
10430 12:22:03.143557 <6>[ 0.627579] EDAC MC: Ver: 3.0.0
10431 12:22:03.150829 <6>[ 0.632730] FPGA manager framework
10432 12:22:03.157531 <6>[ 0.636407] Advanced Linux Sound Architecture Driver Initialized.
10433 12:22:03.161053 <6>[ 0.643174] vgaarb: loaded
10434 12:22:03.166958 <6>[ 0.646343] clocksource: Switched to clocksource arch_sys_counter
10435 12:22:03.170434 <5>[ 0.652774] VFS: Disk quotas dquot_6.6.0
10436 12:22:03.177260 <6>[ 0.656958] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10437 12:22:03.180298 <6>[ 0.664145] pnp: PnP ACPI: disabled
10438 12:22:03.189026 <6>[ 0.670776] NET: Registered PF_INET protocol family
10439 12:22:03.198961 <6>[ 0.676362] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10440 12:22:03.210236 <6>[ 0.688642] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10441 12:22:03.219824 <6>[ 0.697457] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10442 12:22:03.226646 <6>[ 0.705427] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10443 12:22:03.236419 <6>[ 0.714128] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10444 12:22:03.243172 <6>[ 0.723877] TCP: Hash tables configured (established 65536 bind 65536)
10445 12:22:03.249683 <6>[ 0.730735] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10446 12:22:03.259372 <6>[ 0.737932] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10447 12:22:03.266236 <6>[ 0.745631] NET: Registered PF_UNIX/PF_LOCAL protocol family
10448 12:22:03.272916 <6>[ 0.751800] RPC: Registered named UNIX socket transport module.
10449 12:22:03.276336 <6>[ 0.757953] RPC: Registered udp transport module.
10450 12:22:03.282593 <6>[ 0.762885] RPC: Registered tcp transport module.
10451 12:22:03.289325 <6>[ 0.767816] RPC: Registered tcp NFSv4.1 backchannel transport module.
10452 12:22:03.292365 <6>[ 0.774484] PCI: CLS 0 bytes, default 64
10453 12:22:03.295603 <6>[ 0.778889] Unpacking initramfs...
10454 12:22:03.319952 <6>[ 0.798434] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10455 12:22:03.330281 <6>[ 0.807081] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10456 12:22:03.333174 <6>[ 0.815934] kvm [1]: IPA Size Limit: 40 bits
10457 12:22:03.339797 <6>[ 0.820462] kvm [1]: GICv3: no GICV resource entry
10458 12:22:03.343035 <6>[ 0.825486] kvm [1]: disabling GICv2 emulation
10459 12:22:03.349245 <6>[ 0.830172] kvm [1]: GIC system register CPU interface enabled
10460 12:22:03.353031 <6>[ 0.836352] kvm [1]: vgic interrupt IRQ18
10461 12:22:03.359497 <6>[ 0.840704] kvm [1]: VHE mode initialized successfully
10462 12:22:03.365934 <5>[ 0.847119] Initialise system trusted keyrings
10463 12:22:03.372650 <6>[ 0.851896] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10464 12:22:03.379671 <6>[ 0.861853] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10465 12:22:03.386412 <5>[ 0.868252] NFS: Registering the id_resolver key type
10466 12:22:03.389948 <5>[ 0.873552] Key type id_resolver registered
10467 12:22:03.396606 <5>[ 0.877968] Key type id_legacy registered
10468 12:22:03.403017 <6>[ 0.882248] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10469 12:22:03.409988 <6>[ 0.889175] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10470 12:22:03.416332 <6>[ 0.896893] 9p: Installing v9fs 9p2000 file system support
10471 12:22:03.453722 <5>[ 0.935198] Key type asymmetric registered
10472 12:22:03.456731 <5>[ 0.939527] Asymmetric key parser 'x509' registered
10473 12:22:03.467043 <6>[ 0.944674] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10474 12:22:03.469989 <6>[ 0.952294] io scheduler mq-deadline registered
10475 12:22:03.473536 <6>[ 0.957070] io scheduler kyber registered
10476 12:22:03.492373 <6>[ 0.974073] EINJ: ACPI disabled.
10477 12:22:03.524525 <4>[ 0.999712] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10478 12:22:03.534717 <4>[ 1.010355] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10479 12:22:03.549298 <6>[ 1.031291] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10480 12:22:03.558082 <6>[ 1.039479] printk: console [ttyS0] disabled
10481 12:22:03.585828 <6>[ 1.064125] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10482 12:22:03.592441 <6>[ 1.073604] printk: console [ttyS0] enabled
10483 12:22:03.595484 <6>[ 1.073604] printk: console [ttyS0] enabled
10484 12:22:03.602148 <6>[ 1.082501] printk: bootconsole [mtk8250] disabled
10485 12:22:03.605530 <6>[ 1.082501] printk: bootconsole [mtk8250] disabled
10486 12:22:03.612123 <6>[ 1.093777] SuperH (H)SCI(F) driver initialized
10487 12:22:03.615224 <6>[ 1.099068] msm_serial: driver initialized
10488 12:22:03.629516 <6>[ 1.108055] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10489 12:22:03.639861 <6>[ 1.116602] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10490 12:22:03.646436 <6>[ 1.125143] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10491 12:22:03.656207 <6>[ 1.133772] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10492 12:22:03.662840 <6>[ 1.142478] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10493 12:22:03.673133 <6>[ 1.151201] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10494 12:22:03.682866 <6>[ 1.159743] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10495 12:22:03.689107 <6>[ 1.168560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10496 12:22:03.698934 <6>[ 1.177105] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10497 12:22:03.711129 <6>[ 1.192610] loop: module loaded
10498 12:22:03.717620 <6>[ 1.198572] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10499 12:22:03.740624 <4>[ 1.221987] mtk-pmic-keys: Failed to locate of_node [id: -1]
10500 12:22:03.747547 <6>[ 1.228890] megasas: 07.719.03.00-rc1
10501 12:22:03.756665 <6>[ 1.238466] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10502 12:22:03.768322 <6>[ 1.249715] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10503 12:22:03.784887 <6>[ 1.266433] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10504 12:22:03.841470 <6>[ 1.316462] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10505 12:22:04.196071 <6>[ 1.678267] Freeing initrd memory: 20852K
10506 12:22:04.212370 <6>[ 1.693879] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10507 12:22:04.222884 <6>[ 1.704823] tun: Universal TUN/TAP device driver, 1.6
10508 12:22:04.226460 <6>[ 1.710911] thunder_xcv, ver 1.0
10509 12:22:04.230106 <6>[ 1.714413] thunder_bgx, ver 1.0
10510 12:22:04.232921 <6>[ 1.717902] nicpf, ver 1.0
10511 12:22:04.243244 <6>[ 1.721928] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10512 12:22:04.246812 <6>[ 1.729403] hns3: Copyright (c) 2017 Huawei Corporation.
10513 12:22:04.253536 <6>[ 1.734990] hclge is initializing
10514 12:22:04.256721 <6>[ 1.738570] e1000: Intel(R) PRO/1000 Network Driver
10515 12:22:04.263705 <6>[ 1.743699] e1000: Copyright (c) 1999-2006 Intel Corporation.
10516 12:22:04.266436 <6>[ 1.749710] e1000e: Intel(R) PRO/1000 Network Driver
10517 12:22:04.273670 <6>[ 1.754925] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10518 12:22:04.280372 <6>[ 1.761112] igb: Intel(R) Gigabit Ethernet Network Driver
10519 12:22:04.286692 <6>[ 1.766763] igb: Copyright (c) 2007-2014 Intel Corporation.
10520 12:22:04.293384 <6>[ 1.772598] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10521 12:22:04.300012 <6>[ 1.779116] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10522 12:22:04.303075 <6>[ 1.785583] sky2: driver version 1.30
10523 12:22:04.309797 <6>[ 1.790593] VFIO - User Level meta-driver version: 0.3
10524 12:22:04.317099 <6>[ 1.798860] usbcore: registered new interface driver usb-storage
10525 12:22:04.323785 <6>[ 1.805306] usbcore: registered new device driver onboard-usb-hub
10526 12:22:04.333366 <6>[ 1.814448] mt6397-rtc mt6359-rtc: registered as rtc0
10527 12:22:04.342765 <6>[ 1.819911] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-16T12:22:04 UTC (1692188524)
10528 12:22:04.346545 <6>[ 1.829474] i2c_dev: i2c /dev entries driver
10529 12:22:04.363143 <6>[ 1.841197] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10530 12:22:04.383644 <6>[ 1.865184] cpu cpu0: EM: created perf domain
10531 12:22:04.386796 <6>[ 1.870202] cpu cpu4: EM: created perf domain
10532 12:22:04.394601 <6>[ 1.875830] sdhci: Secure Digital Host Controller Interface driver
10533 12:22:04.400617 <6>[ 1.882263] sdhci: Copyright(c) Pierre Ossman
10534 12:22:04.407221 <6>[ 1.887217] Synopsys Designware Multimedia Card Interface Driver
10535 12:22:04.413879 <6>[ 1.893839] sdhci-pltfm: SDHCI platform and OF driver helper
10536 12:22:04.416510 <6>[ 1.893845] mmc0: CQHCI version 5.10
10537 12:22:04.423282 <6>[ 1.904200] ledtrig-cpu: registered to indicate activity on CPUs
10538 12:22:04.429806 <6>[ 1.911300] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10539 12:22:04.437446 <6>[ 1.918376] usbcore: registered new interface driver usbhid
10540 12:22:04.440310 <6>[ 1.924200] usbhid: USB HID core driver
10541 12:22:04.446677 <6>[ 1.928390] spi_master spi0: will run message pump with realtime priority
10542 12:22:04.492141 <6>[ 1.967046] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10543 12:22:04.510803 <6>[ 1.982688] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10544 12:22:04.514173 <6>[ 1.997385] mmc0: Command Queue Engine enabled
10545 12:22:04.521181 <6>[ 1.997394] cros-ec-spi spi0.0: Chrome EC device registered
10546 12:22:04.527426 <6>[ 2.007964] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10547 12:22:04.537619 <6>[ 2.010622] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10548 12:22:04.540610 <6>[ 2.015197] mmcblk0: mmc0:0001 DA4128 116 GiB
10549 12:22:04.547606 <6>[ 2.025044] NET: Registered PF_PACKET protocol family
10550 12:22:04.551070 <6>[ 2.033983] 9pnet: Installing 9P2000 support
10551 12:22:04.557380 <6>[ 2.037220] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10552 12:22:04.560765 <5>[ 2.038561] Key type dns_resolver registered
10553 12:22:04.567328 <6>[ 2.045904] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10554 12:22:04.570674 <6>[ 2.049447] registered taskstats version 1
10555 12:22:04.577836 <6>[ 2.054910] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10556 12:22:04.580773 <5>[ 2.058597] Loading compiled-in X.509 certificates
10557 12:22:04.586931 <6>[ 2.064420] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10558 12:22:04.614613 <4>[ 2.089773] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 12:22:04.624557 <4>[ 2.100458] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10560 12:22:04.631635 <3>[ 2.110986] debugfs: File 'uA_load' in directory '/' already present!
10561 12:22:04.637852 <3>[ 2.117683] debugfs: File 'min_uV' in directory '/' already present!
10562 12:22:04.644569 <3>[ 2.124290] debugfs: File 'max_uV' in directory '/' already present!
10563 12:22:04.651107 <3>[ 2.130897] debugfs: File 'constraint_flags' in directory '/' already present!
10564 12:22:04.662252 <3>[ 2.140402] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10565 12:22:04.671887 <6>[ 2.153502] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10566 12:22:04.678493 <6>[ 2.160362] xhci-mtk 11200000.usb: xHCI Host Controller
10567 12:22:04.684911 <6>[ 2.165853] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10568 12:22:04.695769 <6>[ 2.173798] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10569 12:22:04.702148 <6>[ 2.183232] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10570 12:22:04.708756 <6>[ 2.189299] xhci-mtk 11200000.usb: xHCI Host Controller
10571 12:22:04.715965 <6>[ 2.194776] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10572 12:22:04.721733 <6>[ 2.202436] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10573 12:22:04.728454 <6>[ 2.210270] hub 1-0:1.0: USB hub found
10574 12:22:04.732370 <6>[ 2.214307] hub 1-0:1.0: 1 port detected
10575 12:22:04.741836 <6>[ 2.218584] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10576 12:22:04.745184 <6>[ 2.227344] hub 2-0:1.0: USB hub found
10577 12:22:04.748214 <6>[ 2.231367] hub 2-0:1.0: 1 port detected
10578 12:22:04.757599 <6>[ 2.239570] mtk-msdc 11f70000.mmc: Got CD GPIO
10579 12:22:04.768100 <6>[ 2.246497] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10580 12:22:04.774507 <6>[ 2.254535] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10581 12:22:04.784224 <4>[ 2.262413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10582 12:22:04.794648 <6>[ 2.271937] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10583 12:22:04.801170 <6>[ 2.280014] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10584 12:22:04.807624 <6>[ 2.288039] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10585 12:22:04.817561 <6>[ 2.295955] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10586 12:22:04.824626 <6>[ 2.303772] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10587 12:22:04.834503 <6>[ 2.311589] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10588 12:22:04.844082 <6>[ 2.322043] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10589 12:22:04.850478 <6>[ 2.330408] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10590 12:22:04.860388 <6>[ 2.338758] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10591 12:22:04.866965 <6>[ 2.347098] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10592 12:22:04.877389 <6>[ 2.355436] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10593 12:22:04.883608 <6>[ 2.363798] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10594 12:22:04.894298 <6>[ 2.372139] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10595 12:22:04.903314 <6>[ 2.380477] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10596 12:22:04.910131 <6>[ 2.388815] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10597 12:22:04.919700 <6>[ 2.397155] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10598 12:22:04.926324 <6>[ 2.405494] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10599 12:22:04.936141 <6>[ 2.413832] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10600 12:22:04.943074 <6>[ 2.422171] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10601 12:22:04.953740 <6>[ 2.430508] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10602 12:22:04.959762 <6>[ 2.438845] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10603 12:22:04.965852 <6>[ 2.447594] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10604 12:22:04.972776 <6>[ 2.454754] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10605 12:22:04.979574 <6>[ 2.461514] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10606 12:22:04.989627 <6>[ 2.468287] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10607 12:22:04.996183 <6>[ 2.475227] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10608 12:22:05.003091 <6>[ 2.482067] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10609 12:22:05.013024 <6>[ 2.491198] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10610 12:22:05.023062 <6>[ 2.500323] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10611 12:22:05.032624 <6>[ 2.509618] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10612 12:22:05.042629 <6>[ 2.519086] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10613 12:22:05.049350 <6>[ 2.528554] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10614 12:22:05.059453 <6>[ 2.537674] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10615 12:22:05.068953 <6>[ 2.547140] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10616 12:22:05.078748 <6>[ 2.556260] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10617 12:22:05.088693 <6>[ 2.565555] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10618 12:22:05.098782 <6>[ 2.575715] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10619 12:22:05.108727 <6>[ 2.587598] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10620 12:22:05.164074 <6>[ 2.642613] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10621 12:22:05.318600 <6>[ 2.800370] hub 1-1:1.0: USB hub found
10622 12:22:05.321827 <6>[ 2.804871] hub 1-1:1.0: 4 ports detected
10623 12:22:05.444383 <6>[ 2.922974] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10624 12:22:05.470921 <6>[ 2.952338] hub 2-1:1.0: USB hub found
10625 12:22:05.474099 <6>[ 2.956872] hub 2-1:1.0: 3 ports detected
10626 12:22:05.644108 <6>[ 3.122662] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10627 12:22:05.776453 <6>[ 3.258176] hub 1-1.4:1.0: USB hub found
10628 12:22:05.779367 <6>[ 3.262788] hub 1-1.4:1.0: 2 ports detected
10629 12:22:05.856136 <6>[ 3.334725] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10630 12:22:06.076015 <6>[ 3.554604] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10631 12:22:06.267644 <6>[ 3.746632] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10632 12:22:17.409439 <6>[ 14.895625] ALSA device list:
10633 12:22:17.416017 <6>[ 14.898915] No soundcards found.
10634 12:22:17.423889 <6>[ 14.906892] Freeing unused kernel memory: 8384K
10635 12:22:17.426818 <6>[ 14.911910] Run /init as init process
10636 12:22:17.463282 Starting syslogd: OK
10637 12:22:17.467467 Starting klogd: OK
10638 12:22:17.476911 Running sysctl: OK
10639 12:22:17.483442 Populating /dev using udev: <30>[ 14.968304] udevd[189]: starting version 3.2.9
10640 12:22:17.493336 <27>[ 14.976576] udevd[189]: specified user 'tss' unknown
10641 12:22:17.499717 <27>[ 14.981994] udevd[189]: specified group 'tss' unknown
10642 12:22:17.503347 <30>[ 14.988438] udevd[190]: starting eudev-3.2.9
10643 12:22:17.525288 <27>[ 15.008906] udevd[190]: specified user 'tss' unknown
10644 12:22:17.532165 <27>[ 15.014380] udevd[190]: specified group 'tss' unknown
10645 12:22:17.653228 <6>[ 15.133089] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10646 12:22:17.663606 <6>[ 15.143236] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10647 12:22:17.666280 <6>[ 15.145416] remoteproc remoteproc0: scp is available
10648 12:22:17.673844 <6>[ 15.156767] remoteproc remoteproc0: powering up scp
10649 12:22:17.683833 <6>[ 15.157641] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10650 12:22:17.690317 <6>[ 15.162189] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10651 12:22:17.699898 <6>[ 15.170793] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10652 12:22:17.706266 <6>[ 15.179329] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10653 12:22:17.732005 <3>[ 15.212284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 12:22:17.735499 <6>[ 15.216672] mc: Linux media interface: v0.10
10655 12:22:17.745316 <3>[ 15.220447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 12:22:17.752199 <3>[ 15.220452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 12:22:17.762087 <3>[ 15.220535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 12:22:17.768357 <4>[ 15.220989] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10659 12:22:17.775204 <4>[ 15.221092] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10660 12:22:17.782042 <6>[ 15.221951] usbcore: registered new interface driver r8152
10661 12:22:17.788206 <6>[ 15.264279] videodev: Linux video capture interface: v2.00
10662 12:22:17.794985 <3>[ 15.269658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 12:22:17.804650 <6>[ 15.278983] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10664 12:22:17.814267 <3>[ 15.283458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 12:22:17.820837 <6>[ 15.293840] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10666 12:22:17.831201 <3>[ 15.301588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 12:22:17.838492 <3>[ 15.301591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 12:22:17.847846 <3>[ 15.301613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 12:22:17.854823 <3>[ 15.301684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 12:22:17.860985 <6>[ 15.314954] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10671 12:22:17.867155 <6>[ 15.315770] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10672 12:22:17.873978 <6>[ 15.315780] pci_bus 0000:00: root bus resource [bus 00-ff]
10673 12:22:17.880809 <6>[ 15.315788] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10674 12:22:17.890563 <6>[ 15.315794] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10675 12:22:17.897223 <6>[ 15.315828] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10676 12:22:17.906967 <6>[ 15.315850] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10677 12:22:17.910460 <6>[ 15.315933] pci 0000:00:00.0: supports D1 D2
10678 12:22:17.917022 <6>[ 15.315937] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10679 12:22:17.923467 <6>[ 15.317994] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10680 12:22:17.930170 <6>[ 15.318129] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10681 12:22:17.940059 <6>[ 15.318163] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10682 12:22:17.946445 <6>[ 15.318185] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10683 12:22:17.953336 <6>[ 15.318205] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10684 12:22:17.959752 <6>[ 15.318373] pci 0000:01:00.0: supports D1 D2
10685 12:22:17.966431 <6>[ 15.318378] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10686 12:22:17.972974 <3>[ 15.318806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 12:22:17.979797 <6>[ 15.319113] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10688 12:22:17.989397 <6>[ 15.319182] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10689 12:22:17.996522 <6>[ 15.319195] remoteproc remoteproc0: remote processor scp is now up
10690 12:22:18.004194 <6>[ 15.319194] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10691 12:22:18.011190 <6>[ 15.330619] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10692 12:22:18.020635 <6>[ 15.332258] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10693 12:22:18.027188 <3>[ 15.334944] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 12:22:18.033936 <3>[ 15.334999] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 12:22:18.043832 <6>[ 15.344173] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10696 12:22:18.050779 <3>[ 15.350259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 12:22:18.061082 <4>[ 15.355580] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10698 12:22:18.067261 <4>[ 15.355590] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10699 12:22:18.076923 <6>[ 15.357178] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10700 12:22:18.083548 <3>[ 15.362923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 12:22:18.090228 <6>[ 15.369068] usbcore: registered new interface driver cdc_ether
10702 12:22:18.096896 <6>[ 15.370085] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10703 12:22:18.107671 <3>[ 15.379946] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 12:22:18.113600 <6>[ 15.381125] usbcore: registered new interface driver r8153_ecm
10705 12:22:18.120639 <6>[ 15.386187] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10706 12:22:18.123680 <6>[ 15.386558] Bluetooth: Core ver 2.22
10707 12:22:18.130343 <6>[ 15.386643] NET: Registered PF_BLUETOOTH protocol family
10708 12:22:18.136869 <6>[ 15.386646] Bluetooth: HCI device and connection manager initialized
10709 12:22:18.143651 <6>[ 15.386672] Bluetooth: HCI socket layer initialized
10710 12:22:18.146926 <6>[ 15.386679] Bluetooth: L2CAP socket layer initialized
10711 12:22:18.153690 <6>[ 15.386688] Bluetooth: SCO socket layer initialized
10712 12:22:18.159743 <3>[ 15.393686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 12:22:18.169868 <6>[ 15.398189] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10714 12:22:18.176372 <6>[ 15.403059] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10715 12:22:18.186136 <6>[ 15.404802] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10716 12:22:18.192775 <6>[ 15.404952] usbcore: registered new interface driver uvcvideo
10717 12:22:18.202800 <3>[ 15.405075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 12:22:18.206066 <6>[ 15.413314] pci 0000:00:00.0: PCI bridge to [bus 01]
10719 12:22:18.212757 <6>[ 15.413468] r8152 2-1.3:1.0 eth0: v1.12.13
10720 12:22:18.219559 <6>[ 15.416954] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10721 12:22:18.229551 <6>[ 15.419237] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10722 12:22:18.232292 <6>[ 15.435128] usbcore: registered new interface driver btusb
10723 12:22:18.245793 <4>[ 15.435858] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10724 12:22:18.248632 <3>[ 15.435867] Bluetooth: hci0: Failed to load firmware file (-2)
10725 12:22:18.255632 <3>[ 15.435870] Bluetooth: hci0: Failed to set up firmware (-2)
10726 12:22:18.265458 <4>[ 15.435874] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10727 12:22:18.274702 <6>[ 15.442049] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10728 12:22:18.281628 <6>[ 15.442882] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10729 12:22:18.287799 <4>[ 15.454795] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10730 12:22:18.294520 <4>[ 15.454795] Fallback method does not support PEC.
10731 12:22:18.301151 <6>[ 15.461701] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10732 12:22:18.311061 <3>[ 15.488550] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10733 12:22:18.314418 <6>[ 15.491977] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10734 12:22:18.324509 <3>[ 15.521702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10735 12:22:18.331036 <6>[ 15.524073] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10736 12:22:18.346593 <5>[ 15.826544] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10737 12:22:18.389133 <5>[ 15.869289] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10738 12:22:18.396399 <4>[ 15.876271] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10739 12:22:18.402492 <6>[ 15.885204] cfg80211: failed to load regulatory.db
10740 12:22:18.452955 <6>[ 15.933232] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10741 12:22:18.459372 <6>[ 15.940765] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10742 12:22:18.484509 <6>[ 15.967504] mt7921e 0000:01:00.0: ASIC revision: 79610010
10743 12:22:18.590370 <4>[ 16.066671] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10744 12:22:18.605649 done
10745 12:22:18.613443 Saving random seed: OK
10746 12:22:18.627266 Starting network: OK
10747 12:22:18.667211 Starting dropbear sshd: <6>[ 16.150698] NET: Registered PF_INET6 protocol family
10748 12:22:18.674343 <6>[ 16.157581] Segment Routing with IPv6
10749 12:22:18.677495 <6>[ 16.161528] In-situ OAM (IOAM) with IPv6
10750 12:22:18.681561 OK
10751 12:22:18.698446 /bin/sh: can't access tty; job control turned off
10752 12:22:18.699684 Matched prompt #10: / #
10754 12:22:18.700887 Setting prompt string to ['/ #']
10755 12:22:18.701355 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10757 12:22:18.703001 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10758 12:22:18.703499 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
10759 12:22:18.703894 Setting prompt string to ['/ #']
10760 12:22:18.704275 Forcing a shell prompt, looking for ['/ #']
10762 12:22:18.755084 / # <4>[ 16.1
10763 12:22:18.755742 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10764 12:22:18.756285 Waiting using forced prompt support (timeout 00:02:30)
10765 12:22:18.757052 87444] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 12:22:18.761540
10767 12:22:18.762530 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10768 12:22:18.763170 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
10769 12:22:18.763801 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10770 12:22:18.764505 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
10771 12:22:18.765211 end: 2 depthcharge-action (duration 00:01:37) [common]
10772 12:22:18.765877 start: 3 lava-test-retry (timeout 00:01:00) [common]
10773 12:22:18.766563 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10774 12:22:18.767211 Using namespace: common
10776 12:22:18.868532 / # #
10777 12:22:18.868909 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10778 12:22:18.869270 <4>[ 16.306574] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 12:22:18.874972 #
10780 12:22:18.875471 Using /lava-11299281
10782 12:22:18.976168 / # export SHELL=/bin/sh
10783 12:22:18.977066 export SHELL=/bin/sh<4>[ 16.427302] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 12:22:18.982796
10786 12:22:19.084632 / # . /lava-11299281/environment
10787 12:22:19.085307 . /lava-11299281/environment<4>[ 16.547191] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 12:22:19.090731
10790 12:22:19.192553 / # /lava-11299281/bin/lava-test-runner /lava-11299281/0
10791 12:22:19.193171 Test shell timeout: 10s (minimum of the action and connection timeout)
10792 12:22:19.194824 /lava-11299281/bin/lava-test-runner /lava-11299281/0<4>[ 16.667158] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 12:22:19.199329
10794 12:22:19.240572 + export 'TESTRUN_ID=0_dmesg'
10795 12:22:19.241140 +<8>[ 16.709026] <LAVA_SIGNAL_STARTRUN 0_dmesg 11299281_1.5.2.3.1>
10796 12:22:19.241527 cd /lava-11299281/0/tests/0_dmesg
10797 12:22:19.241870 + cat uuid
10798 12:22:19.242204 + UUID=11299281_1.5.2.3.1
10799 12:22:19.242532 + set +x
10800 12:22:19.243148 Received signal: <STARTRUN> 0_dmesg 11299281_1.5.2.3.1
10801 12:22:19.243522 Starting test lava.0_dmesg (11299281_1.5.2.3.1)
10802 12:22:19.243973 Skipping test definition patterns.
10803 12:22:19.244520 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10804 12:22:19.247599 <8>[ 16.727765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10805 12:22:19.248475 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10807 12:22:19.269061 <8>[ 16.748906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10808 12:22:19.269904 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10810 12:22:19.295076 <8>[ 16.775238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10811 12:22:19.295989 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10813 12:22:19.298653 + set +x
10814 12:22:19.302126 Received signal: <ENDRUN> 0_dmesg 11299281_1.5.2.3.1
10815 12:22:19.302635 Ending use of test pattern.
10816 12:22:19.302996 Ending test lava.0_dmesg (11299281_1.5.2.3.1), duration 0.06
10818 12:22:19.305256 <8>[ 16.785385] <LAVA_SIGNAL_ENDRUN 0_dmesg 11299281_1.5.2.3.1>
10819 12:22:19.314933 <4>[ 16.786799] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 12:22:19.318304 <LAVA_TEST_RUNNER EXIT>
10821 12:22:19.318979 ok: lava_test_shell seems to have completed
10822 12:22:19.319518 alert: pass
crit: pass
emerg: pass
10823 12:22:19.319970 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10824 12:22:19.320431 end: 3 lava-test-retry (duration 00:00:01) [common]
10825 12:22:19.320853 start: 4 lava-test-retry (timeout 00:01:00) [common]
10826 12:22:19.321282 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10827 12:22:19.321610 Using namespace: common
10829 12:22:19.422737 / # #
10830 12:22:19.423381 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10831 12:22:19.423995 Using /lava-11299281
10833 12:22:19.525304 export SHELL=/bin/sh
10834 12:22:19.526092 #<4>[ 16.914904] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10835 12:22:19.526533
10837 12:22:19.628048 / # export SHELL=/bin/sh. /lava-11299281/environment
10838 12:22:19.628835
10839 12:22:19.629345 / # <4>[ 17.035238] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10841 12:22:19.730924 . /lava-11299281/environment/lava-11299281/bin/lava-test-runner /lava-11299281/1
10842 12:22:19.731552 Test shell timeout: 10s (minimum of the action and connection timeout)
10843 12:22:19.732201
10844 12:22:19.732596 / # <4>[ 17.155330] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10845 12:22:19.737897 /lava-11299281/bin/lava-test-runner /lava-11299281/1
10846 12:22:19.780354 + export 'TESTRUN_ID=1_bootrr'
10847 12:22:19.780913 <8>[ 17.244537] <LAVA_SIGNAL_STARTRUN 1_bootrr 11299281_1.5.2.3.5>
10848 12:22:19.781501 + cd /lava-11299281/1/tests/1_bootrr
10849 12:22:19.781908 + cat uuid
10850 12:22:19.782251 + UUID=11299281_1.5.2.3.5
10851 12:22:19.782589 + set +x
10852 12:22:19.783200 Received signal: <STARTRUN> 1_bootrr 11299281_1.5.2.3.5
10853 12:22:19.783568 Starting test lava.1_bootrr (11299281_1.5.2.3.5)
10854 12:22:19.784036 Skipping test definition patterns.
10855 12:22:19.786509 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11299281/1/../bin<8>[ 17.264540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10856 12:22:19.787388 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10858 12:22:19.789077 :/sbin:/usr/sbin:/bin:/usr/bin'
10859 12:22:19.789544 + cd /opt/bootrr/libexec/bootrr
10860 12:22:19.792890 + sh helpers/bootrr-auto
10861 12:22:19.795874 /lava-11299281/1/../bin/lava-test-case
10862 12:22:19.802863 <3>[ 17.286269] mt7921e 0000:01:00.0: hardware init failed
10863 12:22:19.816678 /lava-11299281/1/../bin/lava-test-case
10864 12:22:19.822923 <8>[ 17.303441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10865 12:22:19.823753 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10867 12:22:19.827997 /usr/bin/tpm2_getcap
10868 12:22:19.858927 /lava-11299281/1/../bin/lava-test-case
10869 12:22:19.865159 <8>[ 17.345811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10870 12:22:19.866010 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10872 12:22:19.885934 /lava-11299281/1/../bin/lava-test-case
10873 12:22:19.892523 <8>[ 17.372873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10874 12:22:19.893270 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10876 12:22:19.903210 /lava-11299281/1/../bin/lava-test-case
10877 12:22:19.909365 <8>[ 17.390150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10878 12:22:19.910188 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10880 12:22:19.921377 /lava-11299281/1/../bin/lava-test-case
10881 12:22:19.927741 <8>[ 17.407984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10882 12:22:19.928634 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10884 12:22:19.940827 /lava-11299281/1/../bin/lava-test-case
10885 12:22:19.947339 <8>[ 17.427206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10886 12:22:19.948217 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10888 12:22:19.959990 /lava-11299281/1/../bin/lava-test-case
10889 12:22:19.966138 <8>[ 17.447396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10890 12:22:19.966989 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10892 12:22:19.976126 /lava-11299281/1/../bin/lava-test-case
10893 12:22:19.982214 <8>[ 17.463002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10894 12:22:19.982953 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10896 12:22:19.994288 /lava-11299281/1/../bin/lava-test-case
10897 12:22:20.000877 <8>[ 17.481244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10898 12:22:20.001733 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10900 12:22:20.009373 /lava-11299281/1/../bin/lava-test-case
10901 12:22:20.015349 <8>[ 17.495300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10902 12:22:20.016257 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10904 12:22:20.027640 /lava-11299281/1/../bin/lava-test-case
10905 12:22:20.033885 <8>[ 17.514242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10906 12:22:20.034630 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10908 12:22:20.044869 /lava-11299281/1/../bin/lava-test-case
10909 12:22:20.051856 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10911 12:22:20.054444 <8>[ 17.533074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10912 12:22:20.065496 /lava-11299281/1/../bin/lava-test-case
10913 12:22:20.071860 <8>[ 17.552174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10914 12:22:20.072738 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10916 12:22:20.084509 /lava-11299281/1/../bin/lava-test-case
10917 12:22:20.090376 <8>[ 17.571891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10918 12:22:20.091159 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10920 12:22:20.097488 /lava-11299281/1/../bin/lava-test-case
10921 12:22:20.107588 <8>[ 17.587556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10922 12:22:20.108494 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10924 12:22:20.119566 /lava-11299281/1/../bin/lava-test-case
10925 12:22:20.126490 <8>[ 17.608235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10926 12:22:20.127355 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10928 12:22:20.136214 /lava-11299281/1/../bin/lava-test-case
10929 12:22:20.142553 <8>[ 17.623492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10930 12:22:20.143397 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10932 12:22:20.162092 /lava-11299281/1/../bin/lava-tes<8>[ 17.641474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10933 12:22:20.162621 t-case
10934 12:22:20.163230 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10936 12:22:20.169519 /lava-11299281/1/../bin/lava-test-case
10937 12:22:20.176303 <8>[ 17.656647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10938 12:22:20.177170 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10940 12:22:20.186920 /lava-11299281/1/../bin/lava-test-case
10941 12:22:20.193437 <8>[ 17.674040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10942 12:22:20.194609 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10944 12:22:20.201389 /lava-11299281/1/../bin/lava-test-case
10945 12:22:20.208004 <8>[ 17.688704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10946 12:22:20.208743 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10948 12:22:20.226427 /lava-11299281/1/../bin/lava-tes<8>[ 17.705950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10949 12:22:20.226989 t-case
10950 12:22:20.227670 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10952 12:22:20.241245 /lava-11299281/1/../bin/lava-tes<8>[ 17.720729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10953 12:22:20.241821 t-case
10954 12:22:20.242471 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10956 12:22:20.258055 /lava-11299281/1/../bin/lava-tes<8>[ 17.737475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10957 12:22:20.258784 t-case
10958 12:22:20.259560 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10960 12:22:20.269893 /lava-11299281/1/../bin/lava-test-case
10961 12:22:20.276522 <8>[ 17.756528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10962 12:22:20.277375 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10964 12:22:20.284569 /lava-11299281/1/../bin/lava-test-case
10965 12:22:20.291037 <8>[ 17.772162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10966 12:22:20.291900 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10968 12:22:20.302378 /lava-11299281/1/../bin/lava-test-case
10969 12:22:20.310187 <8>[ 17.789302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10970 12:22:20.311058 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10972 12:22:20.317698 /lava-11299281/1/../bin/lava-test-case
10973 12:22:20.324761 <8>[ 17.805301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10974 12:22:20.325613 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10976 12:22:20.336714 /lava-11299281/1/../bin/lava-test-case
10977 12:22:20.343340 <8>[ 17.823944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10978 12:22:20.344228 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10980 12:22:20.355550 /lava-11299281/1/../bin/lava-test-case
10981 12:22:20.361946 <8>[ 17.843977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10982 12:22:20.362733 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10984 12:22:20.375040 /lava-11299281/1/../bin/lava-test-case
10985 12:22:20.381207 <8>[ 17.862028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10986 12:22:20.382034 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10988 12:22:20.393680 /lava-11299281/1/../bin/lava-test-case
10989 12:22:20.403854 <8>[ 17.883347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10990 12:22:20.404634 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10992 12:22:20.411624 /lava-11299281/1/../bin/lava-test-case
10993 12:22:20.418230 <8>[ 17.899221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10994 12:22:20.419073 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10996 12:22:20.430071 /lava-11299281/1/../bin/lava-test-case
10997 12:22:20.436457 <8>[ 17.917410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10998 12:22:20.437298 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11000 12:22:20.447121 /lava-11299281/1/../bin/lava-test-case
11001 12:22:20.453541 <8>[ 17.934790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11002 12:22:20.454388 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11004 12:22:20.463425 /lava-11299281/1/../bin/lava-test-case
11005 12:22:20.469673 <8>[ 17.951047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11006 12:22:20.470523 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11008 12:22:20.482020 /lava-11299281/1/../bin/lava-test-case
11009 12:22:20.488468 <8>[ 17.969869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11010 12:22:20.489387 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11012 12:22:20.498362 /lava-11299281/1/../bin/lava-test-case
11013 12:22:20.505096 <8>[ 17.985713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11014 12:22:20.506062 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11016 12:22:20.515618 /lava-11299281/1/../bin/lava-test-case
11017 12:22:20.522409 <8>[ 18.003530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11018 12:22:20.523291 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11020 12:22:20.531726 /lava-11299281/1/../bin/lava-test-case
11021 12:22:20.538205 <8>[ 18.019886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11022 12:22:20.539055 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11024 12:22:20.550460 /lava-11299281/1/../bin/lava-test-case
11025 12:22:20.557080 <8>[ 18.038017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11026 12:22:20.557922 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11028 12:22:20.566206 /lava-11299281/1/../bin/lava-test-case
11029 12:22:20.572770 <8>[ 18.053330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11030 12:22:20.573628 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11032 12:22:20.584931 /lava-11299281/1/../bin/lava-test-case
11033 12:22:20.591723 <8>[ 18.071996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11034 12:22:20.592517 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11036 12:22:20.608110 /lava-11299281/1/../bin/lava-tes<8>[ 18.087564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11037 12:22:20.608614 t-case
11038 12:22:20.609207 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11040 12:22:20.620546 /lava-11299281/1/../bin/lava-test-case
11041 12:22:20.627219 <8>[ 18.107822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11042 12:22:20.628046 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11044 12:22:20.634923 /lava-11299281/1/../bin/lava-test-case
11045 12:22:20.646402 <8>[ 18.125820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11046 12:22:20.647167 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11048 12:22:20.656875 /lava-11299281/1/../bin/lava-test-case
11049 12:22:20.663348 <8>[ 18.143497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11050 12:22:20.664139 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11052 12:22:20.670854 /lava-11299281/1/../bin/lava-test-case
11053 12:22:20.677240 <8>[ 18.157947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11054 12:22:20.678088 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11056 12:22:20.689258 /lava-11299281/1/../bin/lava-test-case
11057 12:22:20.696015 <8>[ 18.175790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11058 12:22:20.696845 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11060 12:22:20.705355 /lava-11299281/1/../bin/lava-test-case
11061 12:22:20.712127 <8>[ 18.193648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11062 12:22:20.712860 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11064 12:22:20.721541 /lava-11299281/1/../bin/lava-test-case
11065 12:22:20.728257 <8>[ 18.208624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11066 12:22:20.729189 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11068 12:22:20.739538 /lava-11299281/1/../bin/lava-test-case
11069 12:22:20.745607 <8>[ 18.226234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11070 12:22:20.746486 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11072 12:22:20.754113 /lava-11299281/1/../bin/lava-test-case
11073 12:22:20.760761 <8>[ 18.240909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11074 12:22:20.761603 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11076 12:22:20.771299 /lava-11299281/1/../bin/lava-test-case
11077 12:22:20.777308 <8>[ 18.259141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11078 12:22:20.778171 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11080 12:22:20.789332 /lava-11299281/1/../bin/lava-test-case
11081 12:22:20.796142 <8>[ 18.276636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11082 12:22:20.796976 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11084 12:22:20.806486 /lava-11299281/1/../bin/lava-test-case
11085 12:22:20.813235 <8>[ 18.293805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11086 12:22:20.813978 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11088 12:22:20.824500 /lava-11299281/1/../bin/lava-test-case
11089 12:22:20.831114 <8>[ 18.313560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11090 12:22:20.831954 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11092 12:22:20.843088 /lava-11299281/1/../bin/lava-test-case
11093 12:22:20.850079 <8>[ 18.330225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11094 12:22:20.851039 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11096 12:22:20.857857 /lava-11299281/1/../bin/lava-test-case
11097 12:22:20.864308 <8>[ 18.346673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11098 12:22:20.865137 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11100 12:22:20.876412 /lava-11299281/1/../bin/lava-test-case
11101 12:22:20.882680 <8>[ 18.364056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11102 12:22:20.883487 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11104 12:22:20.892955 /lava-11299281/1/../bin/lava-test-case
11105 12:22:20.899353 <8>[ 18.380107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11106 12:22:20.900096 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11108 12:22:20.907698 /lava-11299281/1/../bin/lava-test-case
11109 12:22:20.913800 <8>[ 18.395173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11110 12:22:20.914480 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11112 12:22:20.924657 /lava-11299281/1/../bin/lava-test-case
11113 12:22:20.935146 <8>[ 18.415527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11114 12:22:20.935887 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11116 12:22:20.943342 /lava-11299281/1/../bin/lava-test-case
11117 12:22:20.950101 <8>[ 18.430594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11118 12:22:20.950893 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11120 12:22:20.961088 /lava-11299281/1/../bin/lava-test-case
11121 12:22:20.971321 <8>[ 18.451169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11122 12:22:20.972166 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11124 12:22:20.979050 /lava-11299281/1/../bin/lava-test-case
11125 12:22:20.985431 <8>[ 18.465977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11126 12:22:20.986245 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11128 12:22:20.997078 /lava-11299281/1/../bin/lava-test-case
11129 12:22:21.003317 <8>[ 18.485086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11130 12:22:21.004041 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11132 12:22:21.014602 /lava-11299281/1/../bin/lava-test-case
11133 12:22:21.020686 <8>[ 18.501841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11134 12:22:21.021415 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11136 12:22:21.031693 /lava-11299281/1/../bin/lava-test-case
11137 12:22:21.038944 <8>[ 18.519208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11138 12:22:21.039837 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11140 12:22:21.051153 /lava-11299281/1/../bin/lava-test-case
11141 12:22:21.057321 <8>[ 18.538932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11142 12:22:21.058261 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11144 12:22:21.076925 /lava-11299281/1/../bin/lava-tes<8>[ 18.556419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11145 12:22:21.077532 t-case
11146 12:22:21.078184 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11148 12:22:21.085542 /lava-11299281/1/../bin/lava-test-case
11149 12:22:21.092494 <8>[ 18.572643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11150 12:22:21.093366 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11152 12:22:21.105696 /lava-11299281/1/../bin/lava-test-case
11153 12:22:21.112637 <8>[ 18.593952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11154 12:22:21.113370 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11156 12:22:21.123041 /lava-11299281/1/../bin/lava-test-case
11157 12:22:21.133202 <8>[ 18.613744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11158 12:22:21.133894 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11160 12:22:21.144885 /lava-11299281/1/../bin/lava-test-case
11161 12:22:21.150973 <8>[ 18.632271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11162 12:22:21.151826 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11164 12:22:21.162129 /lava-11299281/1/../bin/lava-test-case
11165 12:22:21.168852 <8>[ 18.649435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11166 12:22:21.169700 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11168 12:22:21.180666 /lava-11299281/1/../bin/lava-test-case
11169 12:22:21.187026 <8>[ 18.667702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11170 12:22:21.187821 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11172 12:22:21.201235 /lava-11299281/1/../bin/lava-test-case
11173 12:22:21.207961 <8>[ 18.688385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11174 12:22:21.208819 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11176 12:22:21.225063 /lava-11299281/1/../bin/lava-tes<8>[ 18.704561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11177 12:22:21.225609 t-case
11178 12:22:21.226285 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11180 12:22:21.239664 /lava-11299281/1/../bin/lava-test-case
11181 12:22:21.245879 <8>[ 18.726369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11182 12:22:21.246741 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11184 12:22:21.255526 /lava-11299281/1/../bin/lava-test-case
11185 12:22:21.262421 <8>[ 18.743363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11186 12:22:21.263268 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11188 12:22:21.270842 /lava-11299281/1/../bin/lava-test-case
11189 12:22:21.277893 <8>[ 18.759215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11190 12:22:21.278749 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11192 12:22:21.288597 /lava-11299281/1/../bin/lava-test-case
11193 12:22:21.295604 <8>[ 18.776995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11194 12:22:21.296515 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11196 12:22:21.304746 /lava-11299281/1/../bin/lava-test-case
11197 12:22:21.310598 <8>[ 18.791618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11198 12:22:21.311411 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11200 12:22:21.321661 /lava-11299281/1/../bin/lava-test-case
11201 12:22:21.328033 <8>[ 18.808451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11202 12:22:21.328775 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11204 12:22:21.337145 /lava-11299281/1/../bin/lava-test-case
11205 12:22:21.343999 <8>[ 18.823437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11206 12:22:21.344842 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11208 12:22:21.363731 /lava-11299281/1/../bin/lava-tes<8>[ 18.843780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11209 12:22:21.364313 t-case
11210 12:22:21.364908 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11212 12:22:21.372201 /lava-11299281/1/../bin/lava-test-case
11213 12:22:21.379375 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11215 12:22:21.381962 <8>[ 18.860750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11216 12:22:21.392411 /lava-11299281/1/../bin/lava-test-case
11217 12:22:21.398875 <8>[ 18.879190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11218 12:22:21.399691 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11220 12:22:21.407689 /lava-11299281/1/../bin/lava-test-case
11221 12:22:21.414078 <8>[ 18.894362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11222 12:22:21.414925 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11224 12:22:21.426971 /lava-11299281/1/../bin/lava-test-case
11225 12:22:21.433276 <8>[ 18.915236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11226 12:22:21.433973 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11228 12:22:21.443800 /lava-11299281/1/../bin/lava-test-case
11229 12:22:21.450194 <8>[ 18.930839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11230 12:22:21.450957 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11232 12:22:21.461354 /lava-11299281/1/../bin/lava-test-case
11233 12:22:21.467991 <8>[ 18.948517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11234 12:22:21.468827 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11236 12:22:21.478225 /lava-11299281/1/../bin/lava-test-case
11237 12:22:21.488968 <8>[ 18.968772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11238 12:22:21.489738 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11240 12:22:21.496868 /lava-11299281/1/../bin/lava-test-case
11241 12:22:21.503356 <8>[ 18.984244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11242 12:22:21.504024 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11244 12:22:21.515065 /lava-11299281/1/../bin/lava-test-case
11245 12:22:21.522377 <8>[ 19.003203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11246 12:22:21.523211 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11248 12:22:21.530645 /lava-11299281/1/../bin/lava-test-case
11249 12:22:21.537376 <8>[ 19.018876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11250 12:22:21.538219 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11252 12:22:21.548891 /lava-11299281/1/../bin/lava-test-case
11253 12:22:21.555367 <8>[ 19.036015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11254 12:22:21.556110 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11256 12:22:21.564907 /lava-11299281/1/../bin/lava-test-case
11257 12:22:21.571170 <8>[ 19.051373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11258 12:22:21.572095 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11260 12:22:22.584087 /lava-11299281/1/../bin/lava-test-case
11261 12:22:22.590541 <8>[ 20.073063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11262 12:22:22.591307 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11264 12:22:22.599887 /lava-11299281/1/../bin/lava-test-case
11265 12:22:22.606503 <8>[ 20.087352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11266 12:22:22.607179 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11268 12:22:23.621865 /lava-11299281/1/../bin/lava-test-case
11269 12:22:23.628297 <8>[ 21.109181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11270 12:22:23.629147 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11272 12:22:23.636600 /lava-11299281/1/../bin/lava-test-case
11273 12:22:23.647090 <8>[ 21.127389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11274 12:22:23.647984 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11276 12:22:24.661143 /lava-11299281/1/../bin/lava-test-case
11277 12:22:24.667120 <8>[ 22.148334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11278 12:22:24.667806 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11280 12:22:24.676009 /lava-11299281/1/../bin/lava-test-case
11281 12:22:24.685676 <8>[ 22.166830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11282 12:22:24.686390 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11284 12:22:25.698724 /lava-11299281/1/../bin/lava-test-case
11285 12:22:25.705275 <8>[ 23.186210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11286 12:22:25.705969 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11288 12:22:25.712687 /lava-11299281/1/../bin/lava-test-case
11289 12:22:25.723425 <8>[ 23.203936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11290 12:22:25.724105 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11292 12:22:26.735465 /lava-11299281/1/../bin/lava-test-case
11293 12:22:26.742211 <8>[ 24.222893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11294 12:22:26.743032 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11296 12:22:26.751615 /lava-11299281/1/../bin/lava-test-case
11297 12:22:26.761646 <8>[ 24.241215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11298 12:22:26.762412 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11300 12:22:27.774104 /lava-11299281/1/../bin/lava-test-case
11301 12:22:27.780609 <8>[ 25.263345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11302 12:22:27.781342 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11304 12:22:27.791601 /lava-11299281/1/../bin/lava-test-case
11305 12:22:27.798485 <8>[ 25.279418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11306 12:22:27.799423 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11308 12:22:28.814672 /lava-11299281/1/../bin/lava-test-case
11309 12:22:28.821049 <8>[ 26.304176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11310 12:22:28.821739 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11312 12:22:28.831487 /lava-11299281/1/../bin/lava-test-case
11313 12:22:28.838177 <8>[ 26.319864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11314 12:22:28.838525 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11316 12:22:28.846942 /lava-11299281/1/../bin/lava-test-case
11317 12:22:28.853928 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11319 12:22:28.856248 <8>[ 26.336156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11320 12:22:29.868125 /lava-11299281/1/../bin/lava-test-case
11321 12:22:29.874528 <8>[ 27.355969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11322 12:22:29.875390 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11324 12:22:29.883613 /lava-11299281/1/../bin/lava-test-case
11325 12:22:29.893687 <8>[ 27.373474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11326 12:22:29.894597 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11328 12:22:29.902891 /lava-11299281/1/../bin/lava-test-case
11329 12:22:29.909320 <8>[ 27.390675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11330 12:22:29.910158 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11332 12:22:29.925749 /lava-11299281/1/../bin/lava-tes<8>[ 27.406636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11333 12:22:29.926317 t-case
11334 12:22:29.926961 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11336 12:22:29.940026 /lava-11299281/1/../bin/lava-test-case
11337 12:22:29.946868 <8>[ 27.427482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11338 12:22:29.947743 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11340 12:22:29.959238 /lava-11299281/1/../bin/lava-test-case
11341 12:22:29.965718 <8>[ 27.447969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11342 12:22:29.966564 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11344 12:22:29.978945 /lava-11299281/1/../bin/lava-test-case
11345 12:22:29.988874 <8>[ 27.470171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11346 12:22:29.989727 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11348 12:22:29.998927 /lava-11299281/1/../bin/lava-test-case
11349 12:22:30.005354 <8>[ 27.487334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11350 12:22:30.006243 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11352 12:22:30.018263 /lava-11299281/1/../bin/lava-test-case
11353 12:22:30.024824 <8>[ 27.505789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11354 12:22:30.025618 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11356 12:22:30.044000 /lava-11299281/1/../bin/lava-tes<8>[ 27.524685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11357 12:22:30.044748 t-case
11358 12:22:30.045464 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11360 12:22:30.053012 /lava-11299281/1/../bin/lava-test-case
11361 12:22:30.059553 <8>[ 27.541586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11362 12:22:30.060672 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11364 12:22:30.072387 /lava-11299281/1/../bin/lava-test-case
11365 12:22:30.078653 <8>[ 27.560004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11366 12:22:30.079493 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11368 12:22:30.094748 /lava-11299281/1/../bin/lava-tes<8>[ 27.575547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11369 12:22:30.095314 t-case
11370 12:22:30.096046 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11372 12:22:30.105317 /lava-11299281/1/../bin/lava-test-case
11373 12:22:30.111673 <8>[ 27.593987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11374 12:22:30.112543 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11376 12:22:30.120746 /lava-11299281/1/../bin/lava-test-case
11377 12:22:30.127601 <8>[ 27.609987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11378 12:22:30.128416 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11380 12:22:30.139353 /lava-11299281/1/../bin/lava-test-case
11381 12:22:30.146245 <8>[ 27.628351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11382 12:22:30.146990 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11384 12:22:30.154959 /lava-11299281/1/../bin/lava-test-case
11385 12:22:30.161693 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11387 12:22:30.165890 <8>[ 27.644568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11388 12:22:30.174223 /lava-11299281/1/../bin/lava-test-case
11389 12:22:30.181273 <8>[ 27.662926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11390 12:22:30.181555 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11392 12:22:30.189802 /lava-11299281/1/../bin/lava-test-case
11393 12:22:30.196426 <8>[ 27.678472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11394 12:22:30.196684 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11396 12:22:30.208100 /lava-11299281/1/../bin/lava-test-case
11397 12:22:30.214752 <8>[ 27.696277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11398 12:22:30.215009 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11400 12:22:30.225291 /lava-11299281/1/../bin/lava-test-case
11401 12:22:30.231289 <8>[ 27.713704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11402 12:22:30.231549 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11404 12:22:31.245084 /lava-11299281/1/../bin/lava-test-case
11405 12:22:31.251225 <8>[ 28.735199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11406 12:22:31.251498 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11408 12:22:32.266537 /lava-11299281/1/../bin/lava-test-case
11409 12:22:32.273750 <8>[ 29.755133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11410 12:22:32.274545 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11412 12:22:32.283552 /lava-11299281/1/../bin/lava-test-case
11413 12:22:32.290415 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11415 12:22:32.293069 <8>[ 29.773210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11416 12:22:32.308958 /lava-11299281/1/../bin/lava-tes<8>[ 29.790228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11417 12:22:32.309466 t-case
11418 12:22:32.310066 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11420 12:22:32.316563 /lava-11299281/1/../bin/lava-test-case
11421 12:22:32.326985 <8>[ 29.808251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11422 12:22:32.327810 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11424 12:22:32.345213 /lava-11299281/1/../bin/lava-tes<8>[ 29.825772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11425 12:22:32.345726 t-case
11426 12:22:32.346319 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11428 12:22:32.352210 /lava-11299281/1/../bin/lava-test-case
11429 12:22:32.358745 <8>[ 29.841678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11430 12:22:32.359477 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11432 12:22:32.375412 /lava-11299281/1/../bin/lava-tes<8>[ 29.859946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11433 12:22:32.376247 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11435 12:22:32.378944 t-case
11436 12:22:32.386129 /lava-11299281/1/../bin/lava-test-case
11437 12:22:32.393056 <8>[ 29.874092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11438 12:22:32.393844 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11440 12:22:32.404460 /lava-11299281/1/../bin/lava-test-case
11441 12:22:32.411289 <8>[ 29.893557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11442 12:22:32.412071 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11444 12:22:32.420881 /lava-11299281/1/../bin/lava-test-case
11445 12:22:32.427000 <8>[ 29.908847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11446 12:22:32.427788 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11448 12:22:32.437640 /lava-11299281/1/../bin/lava-test-case
11449 12:22:32.443663 <8>[ 29.925639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11450 12:22:32.444427 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11452 12:22:32.451279 /lava-11299281/1/../bin/lava-test-case
11453 12:22:32.462237 <8>[ 29.943594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11454 12:22:32.463028 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11456 12:22:32.472249 /lava-11299281/1/../bin/lava-test-case
11457 12:22:32.480267 <8>[ 29.961327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11458 12:22:32.481059 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11460 12:22:32.487998 /lava-11299281/1/../bin/lava-test-case
11461 12:22:32.495290 <8>[ 29.976572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11462 12:22:32.496084 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11464 12:22:32.505669 /lava-11299281/1/../bin/lava-test-case
11465 12:22:32.512501 <8>[ 29.994200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11466 12:22:32.513284 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11468 12:22:32.520631 /lava-11299281/1/../bin/lava-test-case
11469 12:22:32.527797 <8>[ 30.009223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11470 12:22:32.528616 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11472 12:22:32.539150 /lava-11299281/1/../bin/lava-test-case
11473 12:22:32.545777 <8>[ 30.026752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11474 12:22:32.546456 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11476 12:22:32.556079 /lava-11299281/1/../bin/lava-test-case
11477 12:22:32.561671 <8>[ 30.044545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11478 12:22:32.562494 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11480 12:22:32.579930 /lava-11299281/1/../bin/lava-tes<8>[ 30.064272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11481 12:22:32.580733 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11483 12:22:32.583665 t-case
11484 12:22:32.599240 /lava-11299281/1/../bin/lava-tes<8>[ 30.080056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11485 12:22:32.599769 t-case
11486 12:22:32.600476 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11488 12:22:32.612237 /lava-11299281/1/../bin/lava-test-case
11489 12:22:32.619169 <8>[ 30.100039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11490 12:22:32.619986 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11492 12:22:33.630355 /lava-11299281/1/../bin/lava-test-case
11493 12:22:33.636774 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11495 12:22:33.639728 <8>[ 31.120244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11496 12:22:34.649315 /lava-11299281/1/../bin/lava-test-case
11497 12:22:34.656569 <8>[ 32.137958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11498 12:22:34.657310 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11499 12:22:34.657791 Bad test result: blocked
11500 12:22:34.666933 /lava-11299281/1/../bin/lava-test-case
11501 12:22:34.673075 <8>[ 32.155418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11502 12:22:34.673919 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11504 12:22:35.685824 /lava-11299281/1/../bin/lava-test-case
11505 12:22:35.692597 <8>[ 33.174742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11506 12:22:35.693438 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11508 12:22:35.700515 /lava-11299281/1/../bin/lava-test-case
11509 12:22:35.710739 <8>[ 33.192411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11510 12:22:35.711623 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11512 12:22:35.721246 /lava-11299281/1/../bin/lava-test-case
11513 12:22:35.727375 <8>[ 33.209641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11514 12:22:35.728263 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11516 12:22:35.738310 /lava-11299281/1/../bin/lava-test-case
11517 12:22:35.744137 <8>[ 33.226306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11518 12:22:35.744862 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11520 12:22:35.752171 /lava-11299281/1/../bin/lava-test-case
11521 12:22:35.758623 <8>[ 33.240955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11522 12:22:35.759447 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11524 12:22:35.769810 /lava-11299281/1/../bin/lava-test-case
11525 12:22:35.776484 <8>[ 33.258713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11526 12:22:35.777319 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11528 12:22:35.791765 /lava-11299281/1/../bin/lava-tes<8>[ 33.272720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11529 12:22:35.792390 t-case
11530 12:22:35.793032 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11532 12:22:36.805095 /lava-11299281/1/../bin/lava-test-case
11533 12:22:36.812350 <8>[ 34.294922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11534 12:22:36.813085 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11536 12:22:36.820599 /lava-11299281/1/../bin/lava-test-case
11537 12:22:36.826678 <8>[ 34.310091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11538 12:22:36.827493 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11540 12:22:37.840026 /lava-11299281/1/../bin/lava-test-case
11541 12:22:37.847173 <8>[ 35.328981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11542 12:22:37.848075 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11544 12:22:37.854499 /lava-11299281/1/../bin/lava-test-case
11545 12:22:37.861442 <8>[ 35.345179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11546 12:22:37.862319 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11548 12:22:38.876586 /lava-11299281/1/../bin/lava-test-case
11549 12:22:38.882646 <8>[ 36.366124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11550 12:22:38.882958 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11552 12:22:38.891142 /lava-11299281/1/../bin/lava-test-case
11553 12:22:38.897823 <8>[ 36.380849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11554 12:22:38.898192 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11556 12:22:39.911875 /lava-11299281/1/../bin/lava-test-case
11557 12:22:39.918991 <8>[ 37.401792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11558 12:22:39.919852 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11560 12:22:39.926832 /lava-11299281/1/../bin/lava-test-case
11561 12:22:39.934148 <8>[ 37.417284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11562 12:22:39.935005 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11564 12:22:39.944419 /lava-11299281/1/../bin/lava-test-case
11565 12:22:39.951397 <8>[ 37.433617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11566 12:22:39.952325 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11568 12:22:39.962253 /lava-11299281/1/../bin/lava-test-case
11569 12:22:39.968413 <8>[ 37.452438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11570 12:22:39.969154 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11572 12:22:39.977353 /lava-11299281/1/../bin/lava-test-case
11573 12:22:39.983776 <8>[ 37.466037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11574 12:22:39.984555 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11576 12:22:39.996383 /lava-11299281/1/../bin/lava-test-case
11577 12:22:40.002808 <8>[ 37.485416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11578 12:22:40.003652 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11580 12:22:40.011331 /lava-11299281/1/../bin/lava-test-case
11581 12:22:40.018282 <8>[ 37.500574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11582 12:22:40.019120 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11584 12:22:40.029868 /lava-11299281/1/../bin/lava-test-case
11585 12:22:40.035843 <8>[ 37.518445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11586 12:22:40.036722 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11588 12:22:40.046171 /lava-11299281/1/../bin/lava-test-case
11589 12:22:40.052869 <8>[ 37.536775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11590 12:22:40.053702 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11592 12:22:40.066029 /lava-11299281/1/../bin/lava-test-case
11593 12:22:40.072577 <8>[ 37.554808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11594 12:22:40.073420 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11596 12:22:40.075736 + set +x
11597 12:22:40.079545 Received signal: <ENDRUN> 1_bootrr 11299281_1.5.2.3.5
11598 12:22:40.080171 Ending use of test pattern.
11599 12:22:40.080549 Ending test lava.1_bootrr (11299281_1.5.2.3.5), duration 20.30
11601 12:22:40.082580 <8>[ 37.565021] <LAVA_SIGNAL_ENDRUN 1_bootrr 11299281_1.5.2.3.5>
11602 12:22:40.083292 ok: lava_test_shell seems to have completed
11603 12:22:40.088823 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11604 12:22:40.089793 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11605 12:22:40.090317 end: 4 lava-test-retry (duration 00:00:21) [common]
11606 12:22:40.090813 start: 5 finalize (timeout 00:07:45) [common]
11607 12:22:40.091303 start: 5.1 power-off (timeout 00:00:30) [common]
11608 12:22:40.092198 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11609 12:22:40.217477 >> Command sent successfully.
11610 12:22:40.228240 Returned 0 in 0 seconds
11611 12:22:40.329604 end: 5.1 power-off (duration 00:00:00) [common]
11613 12:22:40.331265 start: 5.2 read-feedback (timeout 00:07:44) [common]
11615 12:22:40.333579 Listened to connection for namespace 'common' for up to 1s
11616 12:22:41.332224 Finalising connection for namespace 'common'
11617 12:22:41.332904 Disconnecting from shell: Finalise
11618 12:22:41.333328 / #
11619 12:22:41.434518 end: 5.2 read-feedback (duration 00:00:01) [common]
11620 12:22:41.435214 end: 5 finalize (duration 00:00:01) [common]
11621 12:22:41.435806 Cleaning after the job
11622 12:22:41.436516 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/ramdisk
11623 12:22:41.452815 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/kernel
11624 12:22:41.480679 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/dtb
11625 12:22:41.481051 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299281/tftp-deploy-fog2iav_/modules
11626 12:22:41.492952 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11299281
11627 12:22:41.541972 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11299281
11628 12:22:41.542150 Job finished correctly