Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 21
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 33
- Errors: 1
1 12:19:30.971890 lava-dispatcher, installed at version: 2023.06
2 12:19:30.972167 start: 0 validate
3 12:19:30.972319 Start time: 2023-08-16 12:19:30.972311+00:00 (UTC)
4 12:19:30.972468 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:19:30.972657 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:19:31.230876 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:19:31.231070 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:20:05.995623 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:20:05.995789 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:20:06.252817 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:20:06.253005 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:20:10.513133 validate duration: 39.54
14 12:20:10.513396 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:20:10.513493 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:20:10.513578 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:20:10.513706 Not decompressing ramdisk as can be used compressed.
18 12:20:10.513792 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 12:20:10.513862 saving as /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/ramdisk/rootfs.cpio.gz
20 12:20:10.513926 total size: 34390042 (32 MB)
21 12:20:10.763081 progress 0 % (0 MB)
22 12:20:10.772571 progress 5 % (1 MB)
23 12:20:10.781792 progress 10 % (3 MB)
24 12:20:10.791284 progress 15 % (4 MB)
25 12:20:10.800549 progress 20 % (6 MB)
26 12:20:10.810175 progress 25 % (8 MB)
27 12:20:10.819800 progress 30 % (9 MB)
28 12:20:10.829370 progress 35 % (11 MB)
29 12:20:10.838283 progress 40 % (13 MB)
30 12:20:10.847599 progress 45 % (14 MB)
31 12:20:10.856733 progress 50 % (16 MB)
32 12:20:10.865872 progress 55 % (18 MB)
33 12:20:10.874751 progress 60 % (19 MB)
34 12:20:10.883864 progress 65 % (21 MB)
35 12:20:10.892866 progress 70 % (22 MB)
36 12:20:10.901890 progress 75 % (24 MB)
37 12:20:10.911176 progress 80 % (26 MB)
38 12:20:10.920667 progress 85 % (27 MB)
39 12:20:10.929807 progress 90 % (29 MB)
40 12:20:10.938857 progress 95 % (31 MB)
41 12:20:10.948046 progress 100 % (32 MB)
42 12:20:10.948277 32 MB downloaded in 0.43 s (75.51 MB/s)
43 12:20:10.948506 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:20:10.948760 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:20:10.948848 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:20:10.948931 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:20:10.949054 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:20:10.949124 saving as /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/kernel/Image
50 12:20:10.949185 total size: 49220096 (46 MB)
51 12:20:10.949246 No compression specified
52 12:20:10.950434 progress 0 % (0 MB)
53 12:20:10.963815 progress 5 % (2 MB)
54 12:20:10.976720 progress 10 % (4 MB)
55 12:20:10.989816 progress 15 % (7 MB)
56 12:20:11.002712 progress 20 % (9 MB)
57 12:20:11.015603 progress 25 % (11 MB)
58 12:20:11.028613 progress 30 % (14 MB)
59 12:20:11.041551 progress 35 % (16 MB)
60 12:20:11.054612 progress 40 % (18 MB)
61 12:20:11.067734 progress 45 % (21 MB)
62 12:20:11.081410 progress 50 % (23 MB)
63 12:20:11.094302 progress 55 % (25 MB)
64 12:20:11.107399 progress 60 % (28 MB)
65 12:20:11.120770 progress 65 % (30 MB)
66 12:20:11.134208 progress 70 % (32 MB)
67 12:20:11.147610 progress 75 % (35 MB)
68 12:20:11.160572 progress 80 % (37 MB)
69 12:20:11.173405 progress 85 % (39 MB)
70 12:20:11.186566 progress 90 % (42 MB)
71 12:20:11.199855 progress 95 % (44 MB)
72 12:20:11.212821 progress 100 % (46 MB)
73 12:20:11.212984 46 MB downloaded in 0.26 s (177.94 MB/s)
74 12:20:11.213138 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:20:11.213364 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:20:11.213450 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:20:11.213567 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:20:11.213771 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:20:11.213841 saving as /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/dtb/mt8192-asurada-spherion-r0.dtb
81 12:20:11.213901 total size: 47278 (0 MB)
82 12:20:11.213962 No compression specified
83 12:20:11.215092 progress 69 % (0 MB)
84 12:20:11.215367 progress 100 % (0 MB)
85 12:20:11.215570 0 MB downloaded in 0.00 s (27.06 MB/s)
86 12:20:11.215695 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:20:11.215916 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:20:11.215999 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:20:11.216080 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:20:11.216194 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:20:11.216261 saving as /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/modules/modules.tar
93 12:20:11.216321 total size: 8615968 (8 MB)
94 12:20:11.216380 Using unxz to decompress xz
95 12:20:11.220616 progress 0 % (0 MB)
96 12:20:11.242377 progress 5 % (0 MB)
97 12:20:11.264816 progress 10 % (0 MB)
98 12:20:11.291566 progress 15 % (1 MB)
99 12:20:11.317513 progress 20 % (1 MB)
100 12:20:11.344987 progress 25 % (2 MB)
101 12:20:11.372324 progress 30 % (2 MB)
102 12:20:11.398985 progress 35 % (2 MB)
103 12:20:11.423913 progress 40 % (3 MB)
104 12:20:11.448355 progress 45 % (3 MB)
105 12:20:11.475075 progress 50 % (4 MB)
106 12:20:11.500704 progress 55 % (4 MB)
107 12:20:11.525309 progress 60 % (4 MB)
108 12:20:11.548232 progress 65 % (5 MB)
109 12:20:11.576371 progress 70 % (5 MB)
110 12:20:11.600810 progress 75 % (6 MB)
111 12:20:11.628172 progress 80 % (6 MB)
112 12:20:11.658368 progress 85 % (7 MB)
113 12:20:11.685420 progress 90 % (7 MB)
114 12:20:11.710734 progress 95 % (7 MB)
115 12:20:11.734626 progress 100 % (8 MB)
116 12:20:11.741215 8 MB downloaded in 0.52 s (15.65 MB/s)
117 12:20:11.741534 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:20:11.741843 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:20:11.741968 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:20:11.742097 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:20:11.742209 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:20:11.742393 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:20:11.742682 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i
125 12:20:11.742856 makedir: /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin
126 12:20:11.742965 makedir: /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/tests
127 12:20:11.743069 makedir: /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/results
128 12:20:11.743188 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-add-keys
129 12:20:11.743336 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-add-sources
130 12:20:11.743540 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-background-process-start
131 12:20:11.743703 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-background-process-stop
132 12:20:11.743863 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-common-functions
133 12:20:11.744027 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-echo-ipv4
134 12:20:11.744243 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-install-packages
135 12:20:11.744429 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-installed-packages
136 12:20:11.744609 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-os-build
137 12:20:11.744741 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-probe-channel
138 12:20:11.744869 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-probe-ip
139 12:20:11.744997 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-target-ip
140 12:20:11.745124 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-target-mac
141 12:20:11.745251 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-target-storage
142 12:20:11.745412 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-test-case
143 12:20:11.745539 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-test-event
144 12:20:11.745664 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-test-feedback
145 12:20:11.745789 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-test-raise
146 12:20:11.745914 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-test-reference
147 12:20:11.746038 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-test-runner
148 12:20:11.746168 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-test-set
149 12:20:11.746295 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-test-shell
150 12:20:11.746426 Updating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-install-packages (oe)
151 12:20:11.746598 Updating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/bin/lava-installed-packages (oe)
152 12:20:11.746773 Creating /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/environment
153 12:20:11.746925 LAVA metadata
154 12:20:11.747038 - LAVA_JOB_ID=11299287
155 12:20:11.747145 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:20:11.747289 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:20:11.747410 skipped lava-vland-overlay
158 12:20:11.747511 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:20:11.747591 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:20:11.747657 skipped lava-multinode-overlay
161 12:20:11.747728 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:20:11.747813 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:20:11.747892 Loading test definitions
164 12:20:11.747981 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:20:11.748056 Using /lava-11299287 at stage 0
166 12:20:11.748437 uuid=11299287_1.5.2.3.1 testdef=None
167 12:20:11.748525 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:20:11.748610 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:20:11.749126 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:20:11.749345 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:20:11.749990 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:20:11.750216 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:20:11.750810 runner path: /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/0/tests/0_cros-ec test_uuid 11299287_1.5.2.3.1
176 12:20:11.750965 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:20:11.751170 Creating lava-test-runner.conf files
179 12:20:11.751250 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11299287/lava-overlay-7n24ks2i/lava-11299287/0 for stage 0
180 12:20:11.751341 - 0_cros-ec
181 12:20:11.751463 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:20:11.751552 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:20:11.758439 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:20:11.758571 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:20:11.758658 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:20:11.758745 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:20:11.758831 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:20:12.764388 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:20:12.764788 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:20:12.764905 extracting modules file /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11299287/extract-overlay-ramdisk-zvo0uffu/ramdisk
191 12:20:13.006162 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:20:13.006332 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:20:13.006432 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299287/compress-overlay-o07k5poj/overlay-1.5.2.4.tar.gz to ramdisk
194 12:20:13.006504 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299287/compress-overlay-o07k5poj/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11299287/extract-overlay-ramdisk-zvo0uffu/ramdisk
195 12:20:13.013194 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:20:13.013315 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:20:13.013405 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:20:13.013499 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:20:13.013620 Building ramdisk /var/lib/lava/dispatcher/tmp/11299287/extract-overlay-ramdisk-zvo0uffu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11299287/extract-overlay-ramdisk-zvo0uffu/ramdisk
200 12:20:13.768748 >> 270880 blocks
201 12:20:18.649201 rename /var/lib/lava/dispatcher/tmp/11299287/extract-overlay-ramdisk-zvo0uffu/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/ramdisk/ramdisk.cpio.gz
202 12:20:18.649673 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 12:20:18.649804 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 12:20:18.649908 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 12:20:18.650015 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/kernel/Image'
206 12:20:31.729825 Returned 0 in 13 seconds
207 12:20:31.830479 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/kernel/image.itb
208 12:20:32.569128 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:20:32.569540 output: Created: Wed Aug 16 13:20:32 2023
210 12:20:32.569649 output: Image 0 (kernel-1)
211 12:20:32.569754 output: Description:
212 12:20:32.569847 output: Created: Wed Aug 16 13:20:32 2023
213 12:20:32.569941 output: Type: Kernel Image
214 12:20:32.570038 output: Compression: lzma compressed
215 12:20:32.570126 output: Data Size: 11040376 Bytes = 10781.62 KiB = 10.53 MiB
216 12:20:32.570223 output: Architecture: AArch64
217 12:20:32.570312 output: OS: Linux
218 12:20:32.570397 output: Load Address: 0x00000000
219 12:20:32.570491 output: Entry Point: 0x00000000
220 12:20:32.570574 output: Hash algo: crc32
221 12:20:32.570655 output: Hash value: 79630449
222 12:20:32.570746 output: Image 1 (fdt-1)
223 12:20:32.570828 output: Description: mt8192-asurada-spherion-r0
224 12:20:32.570949 output: Created: Wed Aug 16 13:20:32 2023
225 12:20:32.571062 output: Type: Flat Device Tree
226 12:20:32.571144 output: Compression: uncompressed
227 12:20:32.571249 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:20:32.571335 output: Architecture: AArch64
229 12:20:32.571448 output: Hash algo: crc32
230 12:20:32.571539 output: Hash value: cc4352de
231 12:20:32.571592 output: Image 2 (ramdisk-1)
232 12:20:32.571644 output: Description: unavailable
233 12:20:32.571729 output: Created: Wed Aug 16 13:20:32 2023
234 12:20:32.571799 output: Type: RAMDisk Image
235 12:20:32.571852 output: Compression: Unknown Compression
236 12:20:32.571904 output: Data Size: 47499707 Bytes = 46386.43 KiB = 45.30 MiB
237 12:20:32.572052 output: Architecture: AArch64
238 12:20:32.572151 output: OS: Linux
239 12:20:32.572287 output: Load Address: unavailable
240 12:20:32.572364 output: Entry Point: unavailable
241 12:20:32.572419 output: Hash algo: crc32
242 12:20:32.572505 output: Hash value: b0aeaf53
243 12:20:32.572561 output: Default Configuration: 'conf-1'
244 12:20:32.572614 output: Configuration 0 (conf-1)
245 12:20:32.572667 output: Description: mt8192-asurada-spherion-r0
246 12:20:32.572751 output: Kernel: kernel-1
247 12:20:32.572838 output: Init Ramdisk: ramdisk-1
248 12:20:32.572891 output: FDT: fdt-1
249 12:20:32.572943 output: Loadables: kernel-1
250 12:20:32.573020 output:
251 12:20:32.573261 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:20:32.573391 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:20:32.573562 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 12:20:32.573693 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 12:20:32.573825 No LXC device requested
256 12:20:32.573995 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:20:32.574116 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 12:20:32.574262 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:20:32.574360 Checking files for TFTP limit of 4294967296 bytes.
260 12:20:32.575104 end: 1 tftp-deploy (duration 00:00:22) [common]
261 12:20:32.575245 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:20:32.575365 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:20:32.575548 substitutions:
264 12:20:32.575618 - {DTB}: 11299287/tftp-deploy-zw2vi42m/dtb/mt8192-asurada-spherion-r0.dtb
265 12:20:32.575695 - {INITRD}: 11299287/tftp-deploy-zw2vi42m/ramdisk/ramdisk.cpio.gz
266 12:20:32.575758 - {KERNEL}: 11299287/tftp-deploy-zw2vi42m/kernel/Image
267 12:20:32.575815 - {LAVA_MAC}: None
268 12:20:32.575871 - {PRESEED_CONFIG}: None
269 12:20:32.575939 - {PRESEED_LOCAL}: None
270 12:20:32.575997 - {RAMDISK}: 11299287/tftp-deploy-zw2vi42m/ramdisk/ramdisk.cpio.gz
271 12:20:32.576052 - {ROOT_PART}: None
272 12:20:32.576105 - {ROOT}: None
273 12:20:32.576200 - {SERVER_IP}: 192.168.201.1
274 12:20:32.576279 - {TEE}: None
275 12:20:32.576347 Parsed boot commands:
276 12:20:32.576399 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:20:32.576593 Parsed boot commands: tftpboot 192.168.201.1 11299287/tftp-deploy-zw2vi42m/kernel/image.itb 11299287/tftp-deploy-zw2vi42m/kernel/cmdline
278 12:20:32.576688 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:20:32.576782 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:20:32.576874 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:20:32.576978 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:20:32.577049 Not connected, no need to disconnect.
283 12:20:32.577123 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:20:32.577220 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:20:32.577289 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 12:20:32.582079 Setting prompt string to ['lava-test: # ']
287 12:20:32.582570 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:20:32.582717 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:20:32.582858 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:20:32.582983 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:20:32.583329 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 12:20:37.717561 >> Command sent successfully.
293 12:20:37.720101 Returned 0 in 5 seconds
294 12:20:37.820448 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:20:37.820798 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:20:37.820895 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:20:37.820991 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:20:37.821058 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:20:37.821126 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:20:37.821464 [Enter `^Ec?' for help]
302 12:20:37.992278
303 12:20:37.992456
304 12:20:37.992554 F0: 102B 0000
305 12:20:37.992656
306 12:20:37.992745 F3: 1001 0000 [0200]
307 12:20:37.992840
308 12:20:37.995640 F3: 1001 0000
309 12:20:37.995724
310 12:20:37.995787 F7: 102D 0000
311 12:20:37.995846
312 12:20:37.998994 F1: 0000 0000
313 12:20:37.999091
314 12:20:37.999188 V0: 0000 0000 [0001]
315 12:20:37.999278
316 12:20:38.001982 00: 0007 8000
317 12:20:38.002083
318 12:20:38.002177 01: 0000 0000
319 12:20:38.002264
320 12:20:38.005857 BP: 0C00 0209 [0000]
321 12:20:38.005956
322 12:20:38.006050 G0: 1182 0000
323 12:20:38.006135
324 12:20:38.008881 EC: 0000 0021 [4000]
325 12:20:38.008951
326 12:20:38.009010 S7: 0000 0000 [0000]
327 12:20:38.009083
328 12:20:38.012627 CC: 0000 0000 [0001]
329 12:20:38.012703
330 12:20:38.012782 T0: 0000 0040 [010F]
331 12:20:38.012844
332 12:20:38.012900 Jump to BL
333 12:20:38.016194
334 12:20:38.038947
335 12:20:38.039075
336 12:20:38.039169
337 12:20:38.045843 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:20:38.049455 ARM64: Exception handlers installed.
339 12:20:38.053479 ARM64: Testing exception
340 12:20:38.056290 ARM64: Done test exception
341 12:20:38.063152 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:20:38.072986 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:20:38.080479 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:20:38.090315 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:20:38.096835 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:20:38.106590 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:20:38.118082 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:20:38.124312 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:20:38.141814 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:20:38.145445 WDT: Last reset was cold boot
351 12:20:38.148685 SPI1(PAD0) initialized at 2873684 Hz
352 12:20:38.152121 SPI5(PAD0) initialized at 992727 Hz
353 12:20:38.155813 VBOOT: Loading verstage.
354 12:20:38.162331 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:20:38.165636 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:20:38.168547 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:20:38.172002 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:20:38.179164 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:20:38.186174 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:20:38.196782 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:20:38.196914
362 12:20:38.197011
363 12:20:38.206657 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:20:38.210261 ARM64: Exception handlers installed.
365 12:20:38.213798 ARM64: Testing exception
366 12:20:38.213876 ARM64: Done test exception
367 12:20:38.221034 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:20:38.224494 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:20:38.238140 Probing TPM: . done!
370 12:20:38.238228 TPM ready after 0 ms
371 12:20:38.244452 Connected to device vid:did:rid of 1ae0:0028:00
372 12:20:38.294720 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:20:38.294826 Initialized TPM device CR50 revision 0
374 12:20:38.305657 tlcl_send_startup: Startup return code is 0
375 12:20:38.305746 TPM: setup succeeded
376 12:20:38.317144 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:20:38.326239 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:20:38.337360 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:20:38.346750 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:20:38.350281 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:20:38.354044 in-header: 03 07 00 00 08 00 00 00
382 12:20:38.357125 in-data: aa e4 47 04 13 02 00 00
383 12:20:38.360827 Chrome EC: UHEPI supported
384 12:20:38.368206 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:20:38.371358 in-header: 03 9d 00 00 08 00 00 00
386 12:20:38.375256 in-data: 10 20 20 08 00 00 00 00
387 12:20:38.375346 Phase 1
388 12:20:38.378882 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:20:38.386741 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:20:38.390303 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:20:38.394361 Recovery requested (1009000e)
392 12:20:38.401461 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:20:38.407096 tlcl_extend: response is 0
394 12:20:38.415603 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:20:38.420597 tlcl_extend: response is 0
396 12:20:38.427384 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:20:38.448442 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:20:38.455333 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:20:38.455443
400 12:20:38.455509
401 12:20:38.462890 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:20:38.466667 ARM64: Exception handlers installed.
403 12:20:38.470699 ARM64: Testing exception
404 12:20:38.473552 ARM64: Done test exception
405 12:20:38.493489 pmic_efuse_setting: Set efuses in 11 msecs
406 12:20:38.497239 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:20:38.500883 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:20:38.508898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:20:38.512754 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:20:38.516368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:20:38.523732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:20:38.527717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:20:38.531684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:20:38.534990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:20:38.541929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:20:38.544936 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:20:38.548194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:20:38.555170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:20:38.558616 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:20:38.565306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:20:38.571601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:20:38.574993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:20:38.581840 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:20:38.588303 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:20:38.592007 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:20:38.599708 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:20:38.603331 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:20:38.610383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:20:38.617264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:20:38.620730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:20:38.627696 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:20:38.631246 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:20:38.637920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:20:38.642252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:20:38.645537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:20:38.652265 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:20:38.656003 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:20:38.663689 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:20:38.667161 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:20:38.670757 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:20:38.678454 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:20:38.682123 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:20:38.689049 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:20:38.691932 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:20:38.695767 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:20:38.702350 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:20:38.705542 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:20:38.708378 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:20:38.715452 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:20:38.718879 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:20:38.721746 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:20:38.725419 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:20:38.732337 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:20:38.735887 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:20:38.738598 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:20:38.745263 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:20:38.749139 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:20:38.755423 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:20:38.765416 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:20:38.768386 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:20:38.778373 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:20:38.785679 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:20:38.788896 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:20:38.795017 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:20:38.798524 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:20:38.805471 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x1
467 12:20:38.812188 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:20:38.815557 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:20:38.818808 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:20:38.830427 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 12:20:38.833696 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 12:20:38.840864 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 12:20:38.843375 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 12:20:38.846812 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 12:20:38.850362 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 12:20:38.853879 ADC[4]: Raw value=898890 ID=7
477 12:20:38.856833 ADC[3]: Raw value=213440 ID=1
478 12:20:38.860313 RAM Code: 0x71
479 12:20:38.863443 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 12:20:38.867030 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 12:20:38.877081 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 12:20:38.884110 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 12:20:38.887063 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 12:20:38.890977 in-header: 03 07 00 00 08 00 00 00
485 12:20:38.894188 in-data: aa e4 47 04 13 02 00 00
486 12:20:38.896993 Chrome EC: UHEPI supported
487 12:20:38.901080 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 12:20:38.905205 in-header: 03 d5 00 00 08 00 00 00
489 12:20:38.909239 in-data: 98 20 60 08 00 00 00 00
490 12:20:38.912676 MRC: failed to locate region type 0.
491 12:20:38.919911 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 12:20:38.923557 DRAM-K: Running full calibration
493 12:20:38.929863 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 12:20:38.929947 header.status = 0x0
495 12:20:38.933131 header.version = 0x6 (expected: 0x6)
496 12:20:38.936746 header.size = 0xd00 (expected: 0xd00)
497 12:20:38.940474 header.flags = 0x0
498 12:20:38.943915 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 12:20:38.962179 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
500 12:20:38.968926 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 12:20:38.972760 dram_init: ddr_geometry: 2
502 12:20:38.975441 [EMI] MDL number = 2
503 12:20:38.975538 [EMI] Get MDL freq = 0
504 12:20:38.979021 dram_init: ddr_type: 0
505 12:20:38.979104 is_discrete_lpddr4: 1
506 12:20:38.982695 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 12:20:38.982779
508 12:20:38.982843
509 12:20:38.985428 [Bian_co] ETT version 0.0.0.1
510 12:20:38.992109 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 12:20:38.992192
512 12:20:38.995700 dramc_set_vcore_voltage set vcore to 650000
513 12:20:38.995783 Read voltage for 800, 4
514 12:20:38.999090 Vio18 = 0
515 12:20:38.999173 Vcore = 650000
516 12:20:38.999237 Vdram = 0
517 12:20:39.002591 Vddq = 0
518 12:20:39.002674 Vmddr = 0
519 12:20:39.005433 dram_init: config_dvfs: 1
520 12:20:39.009129 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 12:20:39.015765 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 12:20:39.019730 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 12:20:39.022885 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 12:20:39.026138 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 12:20:39.029865 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 12:20:39.033285 MEM_TYPE=3, freq_sel=18
527 12:20:39.036676 sv_algorithm_assistance_LP4_1600
528 12:20:39.040777 ============ PULL DRAM RESETB DOWN ============
529 12:20:39.044484 ========== PULL DRAM RESETB DOWN end =========
530 12:20:39.048244 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 12:20:39.051968 ===================================
532 12:20:39.055989 LPDDR4 DRAM CONFIGURATION
533 12:20:39.056087 ===================================
534 12:20:39.059114 EX_ROW_EN[0] = 0x0
535 12:20:39.062843 EX_ROW_EN[1] = 0x0
536 12:20:39.062927 LP4Y_EN = 0x0
537 12:20:39.066390 WORK_FSP = 0x0
538 12:20:39.066474 WL = 0x2
539 12:20:39.070422 RL = 0x2
540 12:20:39.070505 BL = 0x2
541 12:20:39.070571 RPST = 0x0
542 12:20:39.073855 RD_PRE = 0x0
543 12:20:39.073938 WR_PRE = 0x1
544 12:20:39.077366 WR_PST = 0x0
545 12:20:39.077465 DBI_WR = 0x0
546 12:20:39.081499 DBI_RD = 0x0
547 12:20:39.081582 OTF = 0x1
548 12:20:39.085139 ===================================
549 12:20:39.089342 ===================================
550 12:20:39.089426 ANA top config
551 12:20:39.092721 ===================================
552 12:20:39.096373 DLL_ASYNC_EN = 0
553 12:20:39.099799 ALL_SLAVE_EN = 1
554 12:20:39.099881 NEW_RANK_MODE = 1
555 12:20:39.103844 DLL_IDLE_MODE = 1
556 12:20:39.107352 LP45_APHY_COMB_EN = 1
557 12:20:39.107447 TX_ODT_DIS = 1
558 12:20:39.110871 NEW_8X_MODE = 1
559 12:20:39.113860 ===================================
560 12:20:39.117732 ===================================
561 12:20:39.120482 data_rate = 1600
562 12:20:39.124345 CKR = 1
563 12:20:39.127710 DQ_P2S_RATIO = 8
564 12:20:39.130879 ===================================
565 12:20:39.133929 CA_P2S_RATIO = 8
566 12:20:39.134012 DQ_CA_OPEN = 0
567 12:20:39.137164 DQ_SEMI_OPEN = 0
568 12:20:39.140477 CA_SEMI_OPEN = 0
569 12:20:39.143993 CA_FULL_RATE = 0
570 12:20:39.147357 DQ_CKDIV4_EN = 1
571 12:20:39.147480 CA_CKDIV4_EN = 1
572 12:20:39.150631 CA_PREDIV_EN = 0
573 12:20:39.154260 PH8_DLY = 0
574 12:20:39.157560 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 12:20:39.160613 DQ_AAMCK_DIV = 4
576 12:20:39.164369 CA_AAMCK_DIV = 4
577 12:20:39.164457 CA_ADMCK_DIV = 4
578 12:20:39.168107 DQ_TRACK_CA_EN = 0
579 12:20:39.170615 CA_PICK = 800
580 12:20:39.173932 CA_MCKIO = 800
581 12:20:39.177460 MCKIO_SEMI = 0
582 12:20:39.180812 PLL_FREQ = 3068
583 12:20:39.184161 DQ_UI_PI_RATIO = 32
584 12:20:39.184245 CA_UI_PI_RATIO = 0
585 12:20:39.187710 ===================================
586 12:20:39.190744 ===================================
587 12:20:39.194321 memory_type:LPDDR4
588 12:20:39.197546 GP_NUM : 10
589 12:20:39.197629 SRAM_EN : 1
590 12:20:39.200976 MD32_EN : 0
591 12:20:39.204401 ===================================
592 12:20:39.207768 [ANA_INIT] >>>>>>>>>>>>>>
593 12:20:39.207882 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 12:20:39.211359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 12:20:39.214082 ===================================
596 12:20:39.217756 data_rate = 1600,PCW = 0X7600
597 12:20:39.220717 ===================================
598 12:20:39.224065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:20:39.230788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 12:20:39.237327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 12:20:39.241215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 12:20:39.244067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 12:20:39.248213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 12:20:39.251498 [ANA_INIT] flow start
605 12:20:39.251581 [ANA_INIT] PLL >>>>>>>>
606 12:20:39.255064 [ANA_INIT] PLL <<<<<<<<
607 12:20:39.258630 [ANA_INIT] MIDPI >>>>>>>>
608 12:20:39.258712 [ANA_INIT] MIDPI <<<<<<<<
609 12:20:39.261880 [ANA_INIT] DLL >>>>>>>>
610 12:20:39.261962 [ANA_INIT] flow end
611 12:20:39.265924 ============ LP4 DIFF to SE enter ============
612 12:20:39.273053 ============ LP4 DIFF to SE exit ============
613 12:20:39.273143 [ANA_INIT] <<<<<<<<<<<<<
614 12:20:39.277061 [Flow] Enable top DCM control >>>>>
615 12:20:39.280893 [Flow] Enable top DCM control <<<<<
616 12:20:39.284708 Enable DLL master slave shuffle
617 12:20:39.288357 ==============================================================
618 12:20:39.291344 Gating Mode config
619 12:20:39.294840 ==============================================================
620 12:20:39.297975 Config description:
621 12:20:39.308117 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 12:20:39.314830 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 12:20:39.318057 SELPH_MODE 0: By rank 1: By Phase
624 12:20:39.325086 ==============================================================
625 12:20:39.328257 GAT_TRACK_EN = 1
626 12:20:39.331621 RX_GATING_MODE = 2
627 12:20:39.334766 RX_GATING_TRACK_MODE = 2
628 12:20:39.338218 SELPH_MODE = 1
629 12:20:39.338318 PICG_EARLY_EN = 1
630 12:20:39.341666 VALID_LAT_VALUE = 1
631 12:20:39.348619 ==============================================================
632 12:20:39.351532 Enter into Gating configuration >>>>
633 12:20:39.354818 Exit from Gating configuration <<<<
634 12:20:39.358366 Enter into DVFS_PRE_config >>>>>
635 12:20:39.368588 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 12:20:39.371840 Exit from DVFS_PRE_config <<<<<
637 12:20:39.375110 Enter into PICG configuration >>>>
638 12:20:39.377961 Exit from PICG configuration <<<<
639 12:20:39.381371 [RX_INPUT] configuration >>>>>
640 12:20:39.384604 [RX_INPUT] configuration <<<<<
641 12:20:39.387990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 12:20:39.394896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 12:20:39.401583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 12:20:39.408221 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 12:20:39.411817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 12:20:39.418260 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 12:20:39.421749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 12:20:39.428348 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 12:20:39.431845 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 12:20:39.434748 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 12:20:39.438230 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 12:20:39.445172 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 12:20:39.448529 ===================================
654 12:20:39.451805 LPDDR4 DRAM CONFIGURATION
655 12:20:39.454933 ===================================
656 12:20:39.455005 EX_ROW_EN[0] = 0x0
657 12:20:39.458108 EX_ROW_EN[1] = 0x0
658 12:20:39.458184 LP4Y_EN = 0x0
659 12:20:39.461506 WORK_FSP = 0x0
660 12:20:39.461606 WL = 0x2
661 12:20:39.465071 RL = 0x2
662 12:20:39.465166 BL = 0x2
663 12:20:39.468180 RPST = 0x0
664 12:20:39.468257 RD_PRE = 0x0
665 12:20:39.471711 WR_PRE = 0x1
666 12:20:39.471780 WR_PST = 0x0
667 12:20:39.474911 DBI_WR = 0x0
668 12:20:39.475026 DBI_RD = 0x0
669 12:20:39.478188 OTF = 0x1
670 12:20:39.481631 ===================================
671 12:20:39.485148 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 12:20:39.488346 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 12:20:39.495027 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 12:20:39.498611 ===================================
675 12:20:39.498687 LPDDR4 DRAM CONFIGURATION
676 12:20:39.501463 ===================================
677 12:20:39.505342 EX_ROW_EN[0] = 0x10
678 12:20:39.508178 EX_ROW_EN[1] = 0x0
679 12:20:39.508254 LP4Y_EN = 0x0
680 12:20:39.511968 WORK_FSP = 0x0
681 12:20:39.512068 WL = 0x2
682 12:20:39.514598 RL = 0x2
683 12:20:39.514668 BL = 0x2
684 12:20:39.518216 RPST = 0x0
685 12:20:39.518291 RD_PRE = 0x0
686 12:20:39.521533 WR_PRE = 0x1
687 12:20:39.521609 WR_PST = 0x0
688 12:20:39.524846 DBI_WR = 0x0
689 12:20:39.524917 DBI_RD = 0x0
690 12:20:39.528214 OTF = 0x1
691 12:20:39.531673 ===================================
692 12:20:39.535399 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 12:20:39.540946 nWR fixed to 40
694 12:20:39.544653 [ModeRegInit_LP4] CH0 RK0
695 12:20:39.544767 [ModeRegInit_LP4] CH0 RK1
696 12:20:39.548126 [ModeRegInit_LP4] CH1 RK0
697 12:20:39.548208 [ModeRegInit_LP4] CH1 RK1
698 12:20:39.552570 match AC timing 13
699 12:20:39.555700 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 12:20:39.559367 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 12:20:39.566648 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 12:20:39.570386 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 12:20:39.574206 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 12:20:39.574287 [EMI DOE] emi_dcm 0
705 12:20:39.581221 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 12:20:39.581305 ==
707 12:20:39.584393 Dram Type= 6, Freq= 0, CH_0, rank 0
708 12:20:39.588185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 12:20:39.588268 ==
710 12:20:39.592246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 12:20:39.599643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 12:20:39.608215 [CA 0] Center 38 (7~69) winsize 63
713 12:20:39.612211 [CA 1] Center 37 (7~68) winsize 62
714 12:20:39.615840 [CA 2] Center 35 (5~66) winsize 62
715 12:20:39.619886 [CA 3] Center 35 (5~66) winsize 62
716 12:20:39.623689 [CA 4] Center 34 (4~65) winsize 62
717 12:20:39.627025 [CA 5] Center 34 (4~65) winsize 62
718 12:20:39.627107
719 12:20:39.630760 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 12:20:39.630842
721 12:20:39.634689 [CATrainingPosCal] consider 1 rank data
722 12:20:39.634771 u2DelayCellTimex100 = 270/100 ps
723 12:20:39.638398 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 12:20:39.641951 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 12:20:39.645287 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 12:20:39.648669 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 12:20:39.652669 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 12:20:39.656593 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 12:20:39.656675
730 12:20:39.660038 CA PerBit enable=1, Macro0, CA PI delay=34
731 12:20:39.660121
732 12:20:39.663637 [CBTSetCACLKResult] CA Dly = 34
733 12:20:39.667701 CS Dly: 5 (0~36)
734 12:20:39.667781 ==
735 12:20:39.670957 Dram Type= 6, Freq= 0, CH_0, rank 1
736 12:20:39.675046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 12:20:39.675125 ==
738 12:20:39.678601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 12:20:39.685311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 12:20:39.694868 [CA 0] Center 38 (7~69) winsize 63
741 12:20:39.698681 [CA 1] Center 37 (7~68) winsize 62
742 12:20:39.702372 [CA 2] Center 35 (5~66) winsize 62
743 12:20:39.705694 [CA 3] Center 35 (5~66) winsize 62
744 12:20:39.710197 [CA 4] Center 34 (4~65) winsize 62
745 12:20:39.713567 [CA 5] Center 34 (4~65) winsize 62
746 12:20:39.713647
747 12:20:39.716922 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 12:20:39.716999
749 12:20:39.721228 [CATrainingPosCal] consider 2 rank data
750 12:20:39.721306 u2DelayCellTimex100 = 270/100 ps
751 12:20:39.724565 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 12:20:39.728425 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 12:20:39.732426 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 12:20:39.735675 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 12:20:39.739830 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 12:20:39.743262 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 12:20:39.743339
758 12:20:39.747193 CA PerBit enable=1, Macro0, CA PI delay=34
759 12:20:39.747272
760 12:20:39.751084 [CBTSetCACLKResult] CA Dly = 34
761 12:20:39.751172 CS Dly: 5 (0~37)
762 12:20:39.754509
763 12:20:39.754606 ----->DramcWriteLeveling(PI) begin...
764 12:20:39.758233 ==
765 12:20:39.758314 Dram Type= 6, Freq= 0, CH_0, rank 0
766 12:20:39.765533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 12:20:39.765619 ==
768 12:20:39.765684 Write leveling (Byte 0): 32 => 32
769 12:20:39.769256 Write leveling (Byte 1): 30 => 30
770 12:20:39.773092 DramcWriteLeveling(PI) end<-----
771 12:20:39.773174
772 12:20:39.773239 ==
773 12:20:39.777265 Dram Type= 6, Freq= 0, CH_0, rank 0
774 12:20:39.780509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 12:20:39.780624 ==
776 12:20:39.784588 [Gating] SW mode calibration
777 12:20:39.791527 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 12:20:39.795530 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 12:20:39.799216 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 12:20:39.806865 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 12:20:39.810743 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 12:20:39.814367 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 12:20:39.817937 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 12:20:39.821479 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 12:20:39.828990 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 12:20:39.832410 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:20:39.835885 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:20:39.839601 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:20:39.843721 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:20:39.847432 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:20:39.854140 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:20:39.857506 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:20:39.861343 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:20:39.864660 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:20:39.871188 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:20:39.874767 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 12:20:39.878139 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 12:20:39.884595 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 12:20:39.887978 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:20:39.891430 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:20:39.897770 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:20:39.901567 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:20:39.904719 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:20:39.911671 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:20:39.914780 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:20:39.917880 0 9 12 | B1->B0 | 2727 3232 | 0 1 | (0 0) (1 1)
807 12:20:39.924373 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 12:20:39.927803 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 12:20:39.931605 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 12:20:39.938086 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 12:20:39.941364 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:20:39.944409 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:20:39.951289 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
814 12:20:39.954473 0 10 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (1 0)
815 12:20:39.957794 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:20:39.964512 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:20:39.967723 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:20:39.970974 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:20:39.974283 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:20:39.980983 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:20:39.984450 0 11 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
822 12:20:39.987939 0 11 12 | B1->B0 | 3535 3a39 | 1 1 | (0 0) (1 1)
823 12:20:39.994441 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 12:20:39.997981 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 12:20:40.000837 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 12:20:40.007819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 12:20:40.011292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:20:40.014172 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:20:40.020798 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 12:20:40.024504 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 12:20:40.027839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 12:20:40.034223 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 12:20:40.037829 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 12:20:40.040875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:20:40.047724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:20:40.051041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:20:40.054406 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:20:40.060996 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:20:40.064409 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:20:40.067737 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:20:40.071268 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:20:40.077724 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:20:40.080830 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:20:40.084655 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:20:40.091553 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 12:20:40.094542 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:20:40.097931 Total UI for P1: 0, mck2ui 16
848 12:20:40.100950 best dqsien dly found for B0: ( 0, 14, 8)
849 12:20:40.104368 Total UI for P1: 0, mck2ui 16
850 12:20:40.107823 best dqsien dly found for B1: ( 0, 14, 10)
851 12:20:40.111234 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 12:20:40.114271 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 12:20:40.114353
854 12:20:40.117962 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 12:20:40.121106 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 12:20:40.124559 [Gating] SW calibration Done
857 12:20:40.124641 ==
858 12:20:40.127962 Dram Type= 6, Freq= 0, CH_0, rank 0
859 12:20:40.131295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 12:20:40.134492 ==
861 12:20:40.134574 RX Vref Scan: 0
862 12:20:40.134639
863 12:20:40.137812 RX Vref 0 -> 0, step: 1
864 12:20:40.137894
865 12:20:40.141346 RX Delay -130 -> 252, step: 16
866 12:20:40.144332 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 12:20:40.148144 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 12:20:40.151332 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 12:20:40.154269 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 12:20:40.160958 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 12:20:40.164385 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
872 12:20:40.167691 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 12:20:40.171054 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 12:20:40.174492 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 12:20:40.180764 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
876 12:20:40.184148 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 12:20:40.187668 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 12:20:40.190969 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 12:20:40.194562 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 12:20:40.201095 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 12:20:40.204614 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 12:20:40.204691 ==
883 12:20:40.207689 Dram Type= 6, Freq= 0, CH_0, rank 0
884 12:20:40.210876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 12:20:40.210951 ==
886 12:20:40.214269 DQS Delay:
887 12:20:40.214370 DQS0 = 0, DQS1 = 0
888 12:20:40.214436 DQM Delay:
889 12:20:40.218040 DQM0 = 81, DQM1 = 70
890 12:20:40.218115 DQ Delay:
891 12:20:40.220937 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
892 12:20:40.224719 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
893 12:20:40.227483 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 12:20:40.230955 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 12:20:40.231060
896 12:20:40.231152
897 12:20:40.231238 ==
898 12:20:40.234231 Dram Type= 6, Freq= 0, CH_0, rank 0
899 12:20:40.237885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 12:20:40.241156 ==
901 12:20:40.241234
902 12:20:40.241305
903 12:20:40.241368 TX Vref Scan disable
904 12:20:40.244620 == TX Byte 0 ==
905 12:20:40.248057 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
906 12:20:40.251579 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
907 12:20:40.255180 == TX Byte 1 ==
908 12:20:40.258236 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
909 12:20:40.261346 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
910 12:20:40.261451 ==
911 12:20:40.264851 Dram Type= 6, Freq= 0, CH_0, rank 0
912 12:20:40.271333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 12:20:40.271451 ==
914 12:20:40.283381 TX Vref=22, minBit 7, minWin=26, winSum=431
915 12:20:40.286897 TX Vref=24, minBit 7, minWin=26, winSum=436
916 12:20:40.290177 TX Vref=26, minBit 0, minWin=27, winSum=439
917 12:20:40.293530 TX Vref=28, minBit 8, minWin=27, winSum=443
918 12:20:40.296647 TX Vref=30, minBit 9, minWin=27, winSum=442
919 12:20:40.300633 TX Vref=32, minBit 4, minWin=27, winSum=441
920 12:20:40.306775 [TxChooseVref] Worse bit 8, Min win 27, Win sum 443, Final Vref 28
921 12:20:40.306857
922 12:20:40.310031 Final TX Range 1 Vref 28
923 12:20:40.310113
924 12:20:40.310178 ==
925 12:20:40.313158 Dram Type= 6, Freq= 0, CH_0, rank 0
926 12:20:40.316676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 12:20:40.316758 ==
928 12:20:40.316823
929 12:20:40.319959
930 12:20:40.320041 TX Vref Scan disable
931 12:20:40.323282 == TX Byte 0 ==
932 12:20:40.326739 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
933 12:20:40.333577 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
934 12:20:40.333660 == TX Byte 1 ==
935 12:20:40.336469 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 12:20:40.343309 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 12:20:40.343417
938 12:20:40.343482 [DATLAT]
939 12:20:40.343542 Freq=800, CH0 RK0
940 12:20:40.343600
941 12:20:40.346858 DATLAT Default: 0xa
942 12:20:40.346940 0, 0xFFFF, sum = 0
943 12:20:40.350191 1, 0xFFFF, sum = 0
944 12:20:40.350276 2, 0xFFFF, sum = 0
945 12:20:40.353675 3, 0xFFFF, sum = 0
946 12:20:40.353757 4, 0xFFFF, sum = 0
947 12:20:40.356816 5, 0xFFFF, sum = 0
948 12:20:40.356899 6, 0xFFFF, sum = 0
949 12:20:40.360114 7, 0xFFFF, sum = 0
950 12:20:40.363541 8, 0xFFFF, sum = 0
951 12:20:40.363624 9, 0x0, sum = 1
952 12:20:40.363690 10, 0x0, sum = 2
953 12:20:40.367354 11, 0x0, sum = 3
954 12:20:40.367445 12, 0x0, sum = 4
955 12:20:40.370026 best_step = 10
956 12:20:40.370107
957 12:20:40.370171 ==
958 12:20:40.373714 Dram Type= 6, Freq= 0, CH_0, rank 0
959 12:20:40.376717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 12:20:40.376799 ==
961 12:20:40.380186 RX Vref Scan: 1
962 12:20:40.380267
963 12:20:40.380331 Set Vref Range= 32 -> 127
964 12:20:40.380389
965 12:20:40.383252 RX Vref 32 -> 127, step: 1
966 12:20:40.383333
967 12:20:40.386763 RX Delay -111 -> 252, step: 8
968 12:20:40.386845
969 12:20:40.390068 Set Vref, RX VrefLevel [Byte0]: 32
970 12:20:40.393422 [Byte1]: 32
971 12:20:40.393525
972 12:20:40.396934 Set Vref, RX VrefLevel [Byte0]: 33
973 12:20:40.399835 [Byte1]: 33
974 12:20:40.404102
975 12:20:40.404179 Set Vref, RX VrefLevel [Byte0]: 34
976 12:20:40.407334 [Byte1]: 34
977 12:20:40.411580
978 12:20:40.411656 Set Vref, RX VrefLevel [Byte0]: 35
979 12:20:40.414978 [Byte1]: 35
980 12:20:40.419004
981 12:20:40.419081 Set Vref, RX VrefLevel [Byte0]: 36
982 12:20:40.422396 [Byte1]: 36
983 12:20:40.426945
984 12:20:40.427051 Set Vref, RX VrefLevel [Byte0]: 37
985 12:20:40.430117 [Byte1]: 37
986 12:20:40.434220
987 12:20:40.434304 Set Vref, RX VrefLevel [Byte0]: 38
988 12:20:40.437673 [Byte1]: 38
989 12:20:40.442049
990 12:20:40.442154 Set Vref, RX VrefLevel [Byte0]: 39
991 12:20:40.445426 [Byte1]: 39
992 12:20:40.449646
993 12:20:40.449727 Set Vref, RX VrefLevel [Byte0]: 40
994 12:20:40.453197 [Byte1]: 40
995 12:20:40.457269
996 12:20:40.457350 Set Vref, RX VrefLevel [Byte0]: 41
997 12:20:40.460666 [Byte1]: 41
998 12:20:40.465182
999 12:20:40.465267 Set Vref, RX VrefLevel [Byte0]: 42
1000 12:20:40.468433 [Byte1]: 42
1001 12:20:40.472633
1002 12:20:40.472720 Set Vref, RX VrefLevel [Byte0]: 43
1003 12:20:40.475925 [Byte1]: 43
1004 12:20:40.480150
1005 12:20:40.480232 Set Vref, RX VrefLevel [Byte0]: 44
1006 12:20:40.483740 [Byte1]: 44
1007 12:20:40.487801
1008 12:20:40.487880 Set Vref, RX VrefLevel [Byte0]: 45
1009 12:20:40.491441 [Byte1]: 45
1010 12:20:40.495762
1011 12:20:40.495863 Set Vref, RX VrefLevel [Byte0]: 46
1012 12:20:40.499892 [Byte1]: 46
1013 12:20:40.503700
1014 12:20:40.503776 Set Vref, RX VrefLevel [Byte0]: 47
1015 12:20:40.507052 [Byte1]: 47
1016 12:20:40.510887
1017 12:20:40.510971 Set Vref, RX VrefLevel [Byte0]: 48
1018 12:20:40.514416 [Byte1]: 48
1019 12:20:40.519148
1020 12:20:40.519226 Set Vref, RX VrefLevel [Byte0]: 49
1021 12:20:40.522421 [Byte1]: 49
1022 12:20:40.526377
1023 12:20:40.526464 Set Vref, RX VrefLevel [Byte0]: 50
1024 12:20:40.529805 [Byte1]: 50
1025 12:20:40.533913
1026 12:20:40.533989 Set Vref, RX VrefLevel [Byte0]: 51
1027 12:20:40.537141 [Byte1]: 51
1028 12:20:40.541748
1029 12:20:40.541834 Set Vref, RX VrefLevel [Byte0]: 52
1030 12:20:40.544643 [Byte1]: 52
1031 12:20:40.549099
1032 12:20:40.549172 Set Vref, RX VrefLevel [Byte0]: 53
1033 12:20:40.552102 [Byte1]: 53
1034 12:20:40.556755
1035 12:20:40.556832 Set Vref, RX VrefLevel [Byte0]: 54
1036 12:20:40.560634 [Byte1]: 54
1037 12:20:40.564475
1038 12:20:40.564550 Set Vref, RX VrefLevel [Byte0]: 55
1039 12:20:40.567818 [Byte1]: 55
1040 12:20:40.571768
1041 12:20:40.571869 Set Vref, RX VrefLevel [Byte0]: 56
1042 12:20:40.575297 [Byte1]: 56
1043 12:20:40.579806
1044 12:20:40.579881 Set Vref, RX VrefLevel [Byte0]: 57
1045 12:20:40.583088 [Byte1]: 57
1046 12:20:40.587168
1047 12:20:40.587244 Set Vref, RX VrefLevel [Byte0]: 58
1048 12:20:40.590403 [Byte1]: 58
1049 12:20:40.595032
1050 12:20:40.595106 Set Vref, RX VrefLevel [Byte0]: 59
1051 12:20:40.598287 [Byte1]: 59
1052 12:20:40.602400
1053 12:20:40.602478 Set Vref, RX VrefLevel [Byte0]: 60
1054 12:20:40.606161 [Byte1]: 60
1055 12:20:40.610352
1056 12:20:40.610433 Set Vref, RX VrefLevel [Byte0]: 61
1057 12:20:40.613776 [Byte1]: 61
1058 12:20:40.618078
1059 12:20:40.618156 Set Vref, RX VrefLevel [Byte0]: 62
1060 12:20:40.621007 [Byte1]: 62
1061 12:20:40.625753
1062 12:20:40.625831 Set Vref, RX VrefLevel [Byte0]: 63
1063 12:20:40.629069 [Byte1]: 63
1064 12:20:40.632999
1065 12:20:40.633076 Set Vref, RX VrefLevel [Byte0]: 64
1066 12:20:40.636403 [Byte1]: 64
1067 12:20:40.641011
1068 12:20:40.641090 Set Vref, RX VrefLevel [Byte0]: 65
1069 12:20:40.643951 [Byte1]: 65
1070 12:20:40.648244
1071 12:20:40.648320 Set Vref, RX VrefLevel [Byte0]: 66
1072 12:20:40.651717 [Byte1]: 66
1073 12:20:40.656461
1074 12:20:40.656539 Set Vref, RX VrefLevel [Byte0]: 67
1075 12:20:40.659269 [Byte1]: 67
1076 12:20:40.663604
1077 12:20:40.663710 Set Vref, RX VrefLevel [Byte0]: 68
1078 12:20:40.667054 [Byte1]: 68
1079 12:20:40.671681
1080 12:20:40.671761 Set Vref, RX VrefLevel [Byte0]: 69
1081 12:20:40.674756 [Byte1]: 69
1082 12:20:40.679293
1083 12:20:40.679396 Set Vref, RX VrefLevel [Byte0]: 70
1084 12:20:40.682185 [Byte1]: 70
1085 12:20:40.686675
1086 12:20:40.686756 Set Vref, RX VrefLevel [Byte0]: 71
1087 12:20:40.690019 [Byte1]: 71
1088 12:20:40.694417
1089 12:20:40.694497 Set Vref, RX VrefLevel [Byte0]: 72
1090 12:20:40.697460 [Byte1]: 72
1091 12:20:40.702230
1092 12:20:40.702309 Set Vref, RX VrefLevel [Byte0]: 73
1093 12:20:40.705217 [Byte1]: 73
1094 12:20:40.709601
1095 12:20:40.709681 Set Vref, RX VrefLevel [Byte0]: 74
1096 12:20:40.712858 [Byte1]: 74
1097 12:20:40.717617
1098 12:20:40.717698 Set Vref, RX VrefLevel [Byte0]: 75
1099 12:20:40.720844 [Byte1]: 75
1100 12:20:40.724668
1101 12:20:40.724748 Set Vref, RX VrefLevel [Byte0]: 76
1102 12:20:40.727915 [Byte1]: 76
1103 12:20:40.732670
1104 12:20:40.732749 Set Vref, RX VrefLevel [Byte0]: 77
1105 12:20:40.735885 [Byte1]: 77
1106 12:20:40.740077
1107 12:20:40.740156 Set Vref, RX VrefLevel [Byte0]: 78
1108 12:20:40.743522 [Byte1]: 78
1109 12:20:40.747939
1110 12:20:40.748020 Set Vref, RX VrefLevel [Byte0]: 79
1111 12:20:40.751474 [Byte1]: 79
1112 12:20:40.755422
1113 12:20:40.755503 Set Vref, RX VrefLevel [Byte0]: 80
1114 12:20:40.758883 [Byte1]: 80
1115 12:20:40.762864
1116 12:20:40.762944 Final RX Vref Byte 0 = 58 to rank0
1117 12:20:40.766772 Final RX Vref Byte 1 = 55 to rank0
1118 12:20:40.769977 Final RX Vref Byte 0 = 58 to rank1
1119 12:20:40.772887 Final RX Vref Byte 1 = 55 to rank1==
1120 12:20:40.776611 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 12:20:40.783382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 12:20:40.783462 ==
1123 12:20:40.783526 DQS Delay:
1124 12:20:40.783604 DQS0 = 0, DQS1 = 0
1125 12:20:40.786286 DQM Delay:
1126 12:20:40.786366 DQM0 = 82, DQM1 = 68
1127 12:20:40.789778 DQ Delay:
1128 12:20:40.793200 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1129 12:20:40.793280 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1130 12:20:40.796751 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1131 12:20:40.802982 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1132 12:20:40.803063
1133 12:20:40.803127
1134 12:20:40.809509 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1135 12:20:40.813205 CH0 RK0: MR19=606, MR18=2929
1136 12:20:40.820130 CH0_RK0: MR19=0x606, MR18=0x2929, DQSOSC=399, MR23=63, INC=92, DEC=61
1137 12:20:40.820211
1138 12:20:40.823276 ----->DramcWriteLeveling(PI) begin...
1139 12:20:40.823357 ==
1140 12:20:40.826289 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 12:20:40.829781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 12:20:40.829862 ==
1143 12:20:40.833262 Write leveling (Byte 0): 32 => 32
1144 12:20:40.836704 Write leveling (Byte 1): 30 => 30
1145 12:20:40.839485 DramcWriteLeveling(PI) end<-----
1146 12:20:40.839565
1147 12:20:40.839628 ==
1148 12:20:40.843208 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 12:20:40.846744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 12:20:40.846826 ==
1151 12:20:40.849394 [Gating] SW mode calibration
1152 12:20:40.856567 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 12:20:40.863439 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 12:20:40.866360 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 12:20:40.869381 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 12:20:40.876040 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1157 12:20:40.879422 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:20:40.882918 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:20:40.889395 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:20:40.892984 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:20:40.896276 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:20:40.902668 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:20:40.906089 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:20:40.909553 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:20:40.915931 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:20:40.960379 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:20:40.960662 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:20:40.960733 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:20:40.960806 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:20:40.960877 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:20:40.961127 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1172 12:20:40.961598 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1173 12:20:40.961697 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:20:40.961965 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:20:40.962047 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:20:41.004254 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:20:41.004519 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:20:41.004596 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:20:41.004672 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:20:41.005057 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (1 1) (1 1)
1181 12:20:41.005303 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1182 12:20:41.005644 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:20:41.005710 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:20:41.005945 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:20:41.006006 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:20:41.023005 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:20:41.023087 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1188 12:20:41.023330 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (0 0) (0 0)
1189 12:20:41.023457 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1190 12:20:41.026364 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:20:41.029813 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:20:41.033413 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:20:41.036305 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:20:41.043322 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:20:41.046560 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1196 12:20:41.049763 0 11 8 | B1->B0 | 3030 4343 | 0 0 | (0 0) (0 0)
1197 12:20:41.056432 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
1198 12:20:41.059806 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:20:41.063110 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:20:41.070276 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:20:41.073629 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:20:41.077678 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:20:41.081138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1204 12:20:41.084916 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1205 12:20:41.091835 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:20:41.095101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:20:41.098717 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:20:41.105431 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:20:41.108941 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:20:41.112402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:20:41.115364 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:20:41.122432 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:20:41.125764 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:20:41.129467 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:20:41.135756 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:20:41.138704 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:20:41.142262 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:20:41.149111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:20:41.152137 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:20:41.155301 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 12:20:41.162099 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 12:20:41.162182 Total UI for P1: 0, mck2ui 16
1223 12:20:41.168723 best dqsien dly found for B0: ( 0, 14, 8)
1224 12:20:41.171991 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 12:20:41.175654 Total UI for P1: 0, mck2ui 16
1226 12:20:41.178887 best dqsien dly found for B1: ( 0, 14, 12)
1227 12:20:41.182389 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 12:20:41.185737 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1229 12:20:41.185814
1230 12:20:41.189015 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 12:20:41.191996 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1232 12:20:41.195452 [Gating] SW calibration Done
1233 12:20:41.195527 ==
1234 12:20:41.198706 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 12:20:41.202105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 12:20:41.202181 ==
1237 12:20:41.205530 RX Vref Scan: 0
1238 12:20:41.205607
1239 12:20:41.208854 RX Vref 0 -> 0, step: 1
1240 12:20:41.208928
1241 12:20:41.208990 RX Delay -130 -> 252, step: 16
1242 12:20:41.215314 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1243 12:20:41.218866 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1244 12:20:41.222255 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1245 12:20:41.225740 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1246 12:20:41.228560 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1247 12:20:41.235309 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1248 12:20:41.239010 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1249 12:20:41.242389 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1250 12:20:41.245267 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1251 12:20:41.248857 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1252 12:20:41.255408 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1253 12:20:41.258854 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1254 12:20:41.262274 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1255 12:20:41.265444 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1256 12:20:41.268837 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1257 12:20:41.275839 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1258 12:20:41.275921 ==
1259 12:20:41.278909 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 12:20:41.282063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 12:20:41.282144 ==
1262 12:20:41.282208 DQS Delay:
1263 12:20:41.285091 DQS0 = 0, DQS1 = 0
1264 12:20:41.285181 DQM Delay:
1265 12:20:41.288838 DQM0 = 75, DQM1 = 69
1266 12:20:41.288920 DQ Delay:
1267 12:20:41.291945 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1268 12:20:41.295339 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1269 12:20:41.298940 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1270 12:20:41.301970 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1271 12:20:41.302051
1272 12:20:41.302114
1273 12:20:41.302172 ==
1274 12:20:41.305612 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 12:20:41.308914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 12:20:41.308995 ==
1277 12:20:41.312289
1278 12:20:41.312374
1279 12:20:41.312453 TX Vref Scan disable
1280 12:20:41.315230 == TX Byte 0 ==
1281 12:20:41.318949 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1282 12:20:41.321571 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1283 12:20:41.325142 == TX Byte 1 ==
1284 12:20:41.328400 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1285 12:20:41.331822 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1286 12:20:41.335015 ==
1287 12:20:41.335091 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 12:20:41.341882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 12:20:41.341970 ==
1290 12:20:41.354249 TX Vref=22, minBit 11, minWin=26, winSum=436
1291 12:20:41.357100 TX Vref=24, minBit 1, minWin=27, winSum=437
1292 12:20:41.360458 TX Vref=26, minBit 2, minWin=27, winSum=440
1293 12:20:41.364503 TX Vref=28, minBit 2, minWin=27, winSum=438
1294 12:20:41.367474 TX Vref=30, minBit 1, minWin=27, winSum=444
1295 12:20:41.374082 TX Vref=32, minBit 11, minWin=26, winSum=442
1296 12:20:41.377535 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
1297 12:20:41.377616
1298 12:20:41.380426 Final TX Range 1 Vref 30
1299 12:20:41.380507
1300 12:20:41.380569 ==
1301 12:20:41.384033 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 12:20:41.387603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 12:20:41.387684 ==
1304 12:20:41.387748
1305 12:20:41.390835
1306 12:20:41.390914 TX Vref Scan disable
1307 12:20:41.393878 == TX Byte 0 ==
1308 12:20:41.397650 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1309 12:20:41.400951 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1310 12:20:41.403999 == TX Byte 1 ==
1311 12:20:41.407590 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1312 12:20:41.410861 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1313 12:20:41.414739
1314 12:20:41.414855 [DATLAT]
1315 12:20:41.414918 Freq=800, CH0 RK1
1316 12:20:41.414977
1317 12:20:41.417357 DATLAT Default: 0xa
1318 12:20:41.417436 0, 0xFFFF, sum = 0
1319 12:20:41.420793 1, 0xFFFF, sum = 0
1320 12:20:41.420874 2, 0xFFFF, sum = 0
1321 12:20:41.423879 3, 0xFFFF, sum = 0
1322 12:20:41.427279 4, 0xFFFF, sum = 0
1323 12:20:41.427393 5, 0xFFFF, sum = 0
1324 12:20:41.430742 6, 0xFFFF, sum = 0
1325 12:20:41.430823 7, 0xFFFF, sum = 0
1326 12:20:41.434266 8, 0xFFFF, sum = 0
1327 12:20:41.434347 9, 0x0, sum = 1
1328 12:20:41.434411 10, 0x0, sum = 2
1329 12:20:41.437346 11, 0x0, sum = 3
1330 12:20:41.437426 12, 0x0, sum = 4
1331 12:20:41.440773 best_step = 10
1332 12:20:41.440852
1333 12:20:41.440915 ==
1334 12:20:41.443765 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 12:20:41.447356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 12:20:41.447476 ==
1337 12:20:41.450261 RX Vref Scan: 0
1338 12:20:41.450340
1339 12:20:41.450402 RX Vref 0 -> 0, step: 1
1340 12:20:41.453738
1341 12:20:41.453818 RX Delay -111 -> 252, step: 8
1342 12:20:41.460809 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1343 12:20:41.464333 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1344 12:20:41.467339 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1345 12:20:41.470912 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1346 12:20:41.474426 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1347 12:20:41.480692 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1348 12:20:41.484299 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1349 12:20:41.488002 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1350 12:20:41.490807 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1351 12:20:41.494126 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1352 12:20:41.500674 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1353 12:20:41.504299 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1354 12:20:41.507519 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1355 12:20:41.510967 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1356 12:20:41.513992 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1357 12:20:41.521255 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1358 12:20:41.521333 ==
1359 12:20:41.524571 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 12:20:41.527594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 12:20:41.527669 ==
1362 12:20:41.527731 DQS Delay:
1363 12:20:41.530866 DQS0 = 0, DQS1 = 0
1364 12:20:41.530939 DQM Delay:
1365 12:20:41.534259 DQM0 = 78, DQM1 = 69
1366 12:20:41.534333 DQ Delay:
1367 12:20:41.537737 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1368 12:20:41.540631 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1369 12:20:41.544185 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1370 12:20:41.547898 DQ12 =80, DQ13 =72, DQ14 =80, DQ15 =76
1371 12:20:41.547973
1372 12:20:41.548045
1373 12:20:41.554843 [DQSOSCAuto] RK1, (LSB)MR18= 0x4823, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1374 12:20:41.557899 CH0 RK1: MR19=606, MR18=4823
1375 12:20:41.564420 CH0_RK1: MR19=0x606, MR18=0x4823, DQSOSC=391, MR23=63, INC=96, DEC=64
1376 12:20:41.567487 [RxdqsGatingPostProcess] freq 800
1377 12:20:41.574488 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 12:20:41.577949 Pre-setting of DQS Precalculation
1379 12:20:41.580893 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 12:20:41.580965 ==
1381 12:20:41.584400 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 12:20:41.587963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 12:20:41.588039 ==
1384 12:20:41.594132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 12:20:41.600595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 12:20:41.609278 [CA 0] Center 36 (6~67) winsize 62
1387 12:20:41.612142 [CA 1] Center 37 (7~67) winsize 61
1388 12:20:41.615696 [CA 2] Center 34 (4~64) winsize 61
1389 12:20:41.618939 [CA 3] Center 34 (4~64) winsize 61
1390 12:20:41.622915 [CA 4] Center 35 (5~65) winsize 61
1391 12:20:41.626099 [CA 5] Center 34 (4~64) winsize 61
1392 12:20:41.626168
1393 12:20:41.629174 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 12:20:41.629257
1395 12:20:41.632659 [CATrainingPosCal] consider 1 rank data
1396 12:20:41.635783 u2DelayCellTimex100 = 270/100 ps
1397 12:20:41.639356 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 12:20:41.642456 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1399 12:20:41.649177 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 12:20:41.652723 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 12:20:41.655638 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1402 12:20:41.659295 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 12:20:41.659394
1404 12:20:41.662276 CA PerBit enable=1, Macro0, CA PI delay=34
1405 12:20:41.662350
1406 12:20:41.665633 [CBTSetCACLKResult] CA Dly = 34
1407 12:20:41.665710 CS Dly: 5 (0~36)
1408 12:20:41.665772 ==
1409 12:20:41.669241 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 12:20:41.675811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 12:20:41.675888 ==
1412 12:20:41.679269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 12:20:41.685733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 12:20:41.695477 [CA 0] Center 36 (6~67) winsize 62
1415 12:20:41.698437 [CA 1] Center 36 (6~67) winsize 62
1416 12:20:41.701877 [CA 2] Center 35 (5~65) winsize 61
1417 12:20:41.705122 [CA 3] Center 34 (4~64) winsize 61
1418 12:20:41.708405 [CA 4] Center 35 (5~65) winsize 61
1419 12:20:41.711678 [CA 5] Center 33 (3~64) winsize 62
1420 12:20:41.711759
1421 12:20:41.715377 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 12:20:41.715506
1423 12:20:41.718391 [CATrainingPosCal] consider 2 rank data
1424 12:20:41.722021 u2DelayCellTimex100 = 270/100 ps
1425 12:20:41.725371 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 12:20:41.728700 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1427 12:20:41.732222 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1428 12:20:41.736289 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 12:20:41.740319 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 12:20:41.743637 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 12:20:41.743710
1432 12:20:41.747281 CA PerBit enable=1, Macro0, CA PI delay=34
1433 12:20:41.747421
1434 12:20:41.750709 [CBTSetCACLKResult] CA Dly = 34
1435 12:20:41.754291 CS Dly: 6 (0~38)
1436 12:20:41.754398
1437 12:20:41.758434 ----->DramcWriteLeveling(PI) begin...
1438 12:20:41.758516 ==
1439 12:20:41.761974 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 12:20:41.765266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 12:20:41.765381 ==
1442 12:20:41.768791 Write leveling (Byte 0): 27 => 27
1443 12:20:41.772249 Write leveling (Byte 1): 31 => 31
1444 12:20:41.772329 DramcWriteLeveling(PI) end<-----
1445 12:20:41.772392
1446 12:20:41.776192 ==
1447 12:20:41.778713 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 12:20:41.782176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 12:20:41.782257 ==
1450 12:20:41.785732 [Gating] SW mode calibration
1451 12:20:41.792219 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 12:20:41.795759 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 12:20:41.802170 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 12:20:41.805483 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 12:20:41.808892 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 12:20:41.815759 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:20:41.818658 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:20:41.822000 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:20:41.828500 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:20:41.832030 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:20:41.835245 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:20:41.841856 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:20:41.845304 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:20:41.848964 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:20:41.855317 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:20:41.858613 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:20:41.862451 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:20:41.865380 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:20:41.872136 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:20:41.875417 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1471 12:20:41.878336 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1472 12:20:41.885127 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:20:41.888658 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:20:41.892116 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:20:41.898330 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:20:41.901687 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:20:41.905173 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:20:41.912103 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:20:41.915185 0 9 8 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
1480 12:20:41.918398 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1481 12:20:41.925634 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:20:41.928365 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:20:41.931614 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:20:41.938337 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:20:41.942154 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:20:41.945032 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1487 12:20:41.951942 0 10 8 | B1->B0 | 2929 2929 | 0 0 | (0 1) (1 1)
1488 12:20:41.955397 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1489 12:20:41.958311 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:20:41.965240 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:20:41.969034 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:20:41.972085 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:20:41.975262 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:20:41.982072 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:20:41.985029 0 11 8 | B1->B0 | 3737 3939 | 0 1 | (1 1) (0 0)
1496 12:20:41.988805 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:20:41.995154 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:20:41.998391 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:20:42.001909 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:20:42.008345 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:20:42.011840 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:20:42.015345 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1503 12:20:42.022414 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1504 12:20:42.024947 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:20:42.028804 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:20:42.035319 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:20:42.038419 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:20:42.041969 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:20:42.048656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:20:42.051881 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:20:42.055313 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:20:42.062080 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:20:42.065485 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:20:42.068396 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:20:42.072177 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:20:42.078797 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:20:42.081841 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:20:42.085184 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:20:42.091939 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 12:20:42.094908 Total UI for P1: 0, mck2ui 16
1521 12:20:42.098391 best dqsien dly found for B0: ( 0, 14, 6)
1522 12:20:42.101780 Total UI for P1: 0, mck2ui 16
1523 12:20:42.105006 best dqsien dly found for B1: ( 0, 14, 6)
1524 12:20:42.108566 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1525 12:20:42.111837 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1526 12:20:42.111917
1527 12:20:42.115019 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 12:20:42.118380 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 12:20:42.121558 [Gating] SW calibration Done
1530 12:20:42.121638 ==
1531 12:20:42.125002 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 12:20:42.128389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 12:20:42.128470 ==
1534 12:20:42.131930 RX Vref Scan: 0
1535 12:20:42.132011
1536 12:20:42.132074 RX Vref 0 -> 0, step: 1
1537 12:20:42.132133
1538 12:20:42.134966 RX Delay -130 -> 252, step: 16
1539 12:20:42.138514 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1540 12:20:42.144986 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1541 12:20:42.148477 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1542 12:20:42.151593 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1543 12:20:42.155051 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1544 12:20:42.158535 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1545 12:20:42.165122 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1546 12:20:42.168778 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1547 12:20:42.172135 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1548 12:20:42.175300 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1549 12:20:42.178537 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1550 12:20:42.184976 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1551 12:20:42.188435 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1552 12:20:42.191973 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1553 12:20:42.194829 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1554 12:20:42.198338 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1555 12:20:42.201715 ==
1556 12:20:42.205204 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 12:20:42.208175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 12:20:42.208249 ==
1559 12:20:42.208311 DQS Delay:
1560 12:20:42.211772 DQS0 = 0, DQS1 = 0
1561 12:20:42.211844 DQM Delay:
1562 12:20:42.215097 DQM0 = 81, DQM1 = 71
1563 12:20:42.215198 DQ Delay:
1564 12:20:42.218390 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1565 12:20:42.221764 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1566 12:20:42.224989 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1567 12:20:42.228298 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1568 12:20:42.228387
1569 12:20:42.228449
1570 12:20:42.228507 ==
1571 12:20:42.231862 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 12:20:42.235241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 12:20:42.235318 ==
1574 12:20:42.235417
1575 12:20:42.235477
1576 12:20:42.238150 TX Vref Scan disable
1577 12:20:42.241689 == TX Byte 0 ==
1578 12:20:42.245312 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1579 12:20:42.248291 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1580 12:20:42.251999 == TX Byte 1 ==
1581 12:20:42.255343 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1582 12:20:42.258313 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1583 12:20:42.258421 ==
1584 12:20:42.261773 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:20:42.265028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:20:42.265190 ==
1587 12:20:42.279673 TX Vref=22, minBit 0, minWin=27, winSum=440
1588 12:20:42.282880 TX Vref=24, minBit 1, minWin=27, winSum=442
1589 12:20:42.286308 TX Vref=26, minBit 1, minWin=27, winSum=444
1590 12:20:42.289776 TX Vref=28, minBit 5, minWin=27, winSum=449
1591 12:20:42.293343 TX Vref=30, minBit 6, minWin=27, winSum=449
1592 12:20:42.296583 TX Vref=32, minBit 0, minWin=27, winSum=443
1593 12:20:42.303036 [TxChooseVref] Worse bit 5, Min win 27, Win sum 449, Final Vref 28
1594 12:20:42.303132
1595 12:20:42.306519 Final TX Range 1 Vref 28
1596 12:20:42.306623
1597 12:20:42.306712 ==
1598 12:20:42.309925 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 12:20:42.313577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 12:20:42.313662 ==
1601 12:20:42.313747
1602 12:20:42.313827
1603 12:20:42.317436 TX Vref Scan disable
1604 12:20:42.320839 == TX Byte 0 ==
1605 12:20:42.323750 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1606 12:20:42.327279 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1607 12:20:42.330861 == TX Byte 1 ==
1608 12:20:42.333651 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1609 12:20:42.336939 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1610 12:20:42.337021
1611 12:20:42.340338 [DATLAT]
1612 12:20:42.340437 Freq=800, CH1 RK0
1613 12:20:42.340503
1614 12:20:42.343960 DATLAT Default: 0xa
1615 12:20:42.344036 0, 0xFFFF, sum = 0
1616 12:20:42.346968 1, 0xFFFF, sum = 0
1617 12:20:42.347046 2, 0xFFFF, sum = 0
1618 12:20:42.350643 3, 0xFFFF, sum = 0
1619 12:20:42.350718 4, 0xFFFF, sum = 0
1620 12:20:42.354076 5, 0xFFFF, sum = 0
1621 12:20:42.354149 6, 0xFFFF, sum = 0
1622 12:20:42.356977 7, 0xFFFF, sum = 0
1623 12:20:42.357050 8, 0xFFFF, sum = 0
1624 12:20:42.360379 9, 0x0, sum = 1
1625 12:20:42.360452 10, 0x0, sum = 2
1626 12:20:42.363811 11, 0x0, sum = 3
1627 12:20:42.363922 12, 0x0, sum = 4
1628 12:20:42.366787 best_step = 10
1629 12:20:42.366904
1630 12:20:42.367010 ==
1631 12:20:42.370166 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 12:20:42.373617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 12:20:42.373730 ==
1634 12:20:42.373829 RX Vref Scan: 1
1635 12:20:42.376808
1636 12:20:42.376922 Set Vref Range= 32 -> 127
1637 12:20:42.377030
1638 12:20:42.380850 RX Vref 32 -> 127, step: 1
1639 12:20:42.380960
1640 12:20:42.383592 RX Delay -111 -> 252, step: 8
1641 12:20:42.383710
1642 12:20:42.387221 Set Vref, RX VrefLevel [Byte0]: 32
1643 12:20:42.390249 [Byte1]: 32
1644 12:20:42.390352
1645 12:20:42.393893 Set Vref, RX VrefLevel [Byte0]: 33
1646 12:20:42.397554 [Byte1]: 33
1647 12:20:42.397662
1648 12:20:42.401181 Set Vref, RX VrefLevel [Byte0]: 34
1649 12:20:42.403388 [Byte1]: 34
1650 12:20:42.408016
1651 12:20:42.408096 Set Vref, RX VrefLevel [Byte0]: 35
1652 12:20:42.410935 [Byte1]: 35
1653 12:20:42.415585
1654 12:20:42.415668 Set Vref, RX VrefLevel [Byte0]: 36
1655 12:20:42.418964 [Byte1]: 36
1656 12:20:42.423119
1657 12:20:42.423224 Set Vref, RX VrefLevel [Byte0]: 37
1658 12:20:42.426554 [Byte1]: 37
1659 12:20:42.430886
1660 12:20:42.430991 Set Vref, RX VrefLevel [Byte0]: 38
1661 12:20:42.434290 [Byte1]: 38
1662 12:20:42.438261
1663 12:20:42.438338 Set Vref, RX VrefLevel [Byte0]: 39
1664 12:20:42.441705 [Byte1]: 39
1665 12:20:42.445973
1666 12:20:42.446076 Set Vref, RX VrefLevel [Byte0]: 40
1667 12:20:42.449063 [Byte1]: 40
1668 12:20:42.453998
1669 12:20:42.454092 Set Vref, RX VrefLevel [Byte0]: 41
1670 12:20:42.456954 [Byte1]: 41
1671 12:20:42.461382
1672 12:20:42.461485 Set Vref, RX VrefLevel [Byte0]: 42
1673 12:20:42.464903 [Byte1]: 42
1674 12:20:42.468877
1675 12:20:42.468957 Set Vref, RX VrefLevel [Byte0]: 43
1676 12:20:42.472417 [Byte1]: 43
1677 12:20:42.476557
1678 12:20:42.476635 Set Vref, RX VrefLevel [Byte0]: 44
1679 12:20:42.479666 [Byte1]: 44
1680 12:20:42.484224
1681 12:20:42.484303 Set Vref, RX VrefLevel [Byte0]: 45
1682 12:20:42.487591 [Byte1]: 45
1683 12:20:42.491877
1684 12:20:42.491950 Set Vref, RX VrefLevel [Byte0]: 46
1685 12:20:42.495408 [Byte1]: 46
1686 12:20:42.499447
1687 12:20:42.499521 Set Vref, RX VrefLevel [Byte0]: 47
1688 12:20:42.502958 [Byte1]: 47
1689 12:20:42.507366
1690 12:20:42.507518 Set Vref, RX VrefLevel [Byte0]: 48
1691 12:20:42.510641 [Byte1]: 48
1692 12:20:42.514989
1693 12:20:42.515105 Set Vref, RX VrefLevel [Byte0]: 49
1694 12:20:42.517990 [Byte1]: 49
1695 12:20:42.522705
1696 12:20:42.522786 Set Vref, RX VrefLevel [Byte0]: 50
1697 12:20:42.525736 [Byte1]: 50
1698 12:20:42.530360
1699 12:20:42.530428 Set Vref, RX VrefLevel [Byte0]: 51
1700 12:20:42.533414 [Byte1]: 51
1701 12:20:42.537686
1702 12:20:42.537755 Set Vref, RX VrefLevel [Byte0]: 52
1703 12:20:42.541167 [Byte1]: 52
1704 12:20:42.545311
1705 12:20:42.545377 Set Vref, RX VrefLevel [Byte0]: 53
1706 12:20:42.548883 [Byte1]: 53
1707 12:20:42.552955
1708 12:20:42.553026 Set Vref, RX VrefLevel [Byte0]: 54
1709 12:20:42.556364 [Byte1]: 54
1710 12:20:42.561017
1711 12:20:42.561091 Set Vref, RX VrefLevel [Byte0]: 55
1712 12:20:42.564080 [Byte1]: 55
1713 12:20:42.568485
1714 12:20:42.568564 Set Vref, RX VrefLevel [Byte0]: 56
1715 12:20:42.571637 [Byte1]: 56
1716 12:20:42.575843
1717 12:20:42.575917 Set Vref, RX VrefLevel [Byte0]: 57
1718 12:20:42.579566 [Byte1]: 57
1719 12:20:42.583482
1720 12:20:42.583553 Set Vref, RX VrefLevel [Byte0]: 58
1721 12:20:42.586779 [Byte1]: 58
1722 12:20:42.591574
1723 12:20:42.591650 Set Vref, RX VrefLevel [Byte0]: 59
1724 12:20:42.594770 [Byte1]: 59
1725 12:20:42.599157
1726 12:20:42.599229 Set Vref, RX VrefLevel [Byte0]: 60
1727 12:20:42.602484 [Byte1]: 60
1728 12:20:42.606576
1729 12:20:42.606654 Set Vref, RX VrefLevel [Byte0]: 61
1730 12:20:42.610073 [Byte1]: 61
1731 12:20:42.614223
1732 12:20:42.614319 Set Vref, RX VrefLevel [Byte0]: 62
1733 12:20:42.617680 [Byte1]: 62
1734 12:20:42.621828
1735 12:20:42.621933 Set Vref, RX VrefLevel [Byte0]: 63
1736 12:20:42.625152 [Byte1]: 63
1737 12:20:42.629785
1738 12:20:42.629861 Set Vref, RX VrefLevel [Byte0]: 64
1739 12:20:42.632810 [Byte1]: 64
1740 12:20:42.637814
1741 12:20:42.637892 Set Vref, RX VrefLevel [Byte0]: 65
1742 12:20:42.640587 [Byte1]: 65
1743 12:20:42.644673
1744 12:20:42.644766 Set Vref, RX VrefLevel [Byte0]: 66
1745 12:20:42.648089 [Byte1]: 66
1746 12:20:42.652748
1747 12:20:42.652842 Set Vref, RX VrefLevel [Byte0]: 67
1748 12:20:42.655949 [Byte1]: 67
1749 12:20:42.659898
1750 12:20:42.659977 Set Vref, RX VrefLevel [Byte0]: 68
1751 12:20:42.663621 [Byte1]: 68
1752 12:20:42.667794
1753 12:20:42.667874 Set Vref, RX VrefLevel [Byte0]: 69
1754 12:20:42.670971 [Byte1]: 69
1755 12:20:42.675552
1756 12:20:42.675631 Set Vref, RX VrefLevel [Byte0]: 70
1757 12:20:42.678644 [Byte1]: 70
1758 12:20:42.682890
1759 12:20:42.683019 Set Vref, RX VrefLevel [Byte0]: 71
1760 12:20:42.686496 [Byte1]: 71
1761 12:20:42.690567
1762 12:20:42.690646 Set Vref, RX VrefLevel [Byte0]: 72
1763 12:20:42.694266 [Byte1]: 72
1764 12:20:42.698452
1765 12:20:42.698529 Set Vref, RX VrefLevel [Byte0]: 73
1766 12:20:42.701797 [Byte1]: 73
1767 12:20:42.705814
1768 12:20:42.709234 Set Vref, RX VrefLevel [Byte0]: 74
1769 12:20:42.712346 [Byte1]: 74
1770 12:20:42.712420
1771 12:20:42.716084 Set Vref, RX VrefLevel [Byte0]: 75
1772 12:20:42.718861 [Byte1]: 75
1773 12:20:42.718933
1774 12:20:42.722592 Final RX Vref Byte 0 = 61 to rank0
1775 12:20:42.725505 Final RX Vref Byte 1 = 63 to rank0
1776 12:20:42.729210 Final RX Vref Byte 0 = 61 to rank1
1777 12:20:42.732270 Final RX Vref Byte 1 = 63 to rank1==
1778 12:20:42.735692 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 12:20:42.739087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 12:20:42.739171 ==
1781 12:20:42.742411 DQS Delay:
1782 12:20:42.742490 DQS0 = 0, DQS1 = 0
1783 12:20:42.742557 DQM Delay:
1784 12:20:42.745915 DQM0 = 80, DQM1 = 70
1785 12:20:42.746027 DQ Delay:
1786 12:20:42.749281 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1787 12:20:42.752315 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1788 12:20:42.755934 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1789 12:20:42.758908 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
1790 12:20:42.758989
1791 12:20:42.759051
1792 12:20:42.768903 [DQSOSCAuto] RK0, (LSB)MR18= 0x101a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1793 12:20:42.768998 CH1 RK0: MR19=606, MR18=101A
1794 12:20:42.775788 CH1_RK0: MR19=0x606, MR18=0x101A, DQSOSC=403, MR23=63, INC=90, DEC=60
1795 12:20:42.775867
1796 12:20:42.779403 ----->DramcWriteLeveling(PI) begin...
1797 12:20:42.779478 ==
1798 12:20:42.782670 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 12:20:42.789184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 12:20:42.789266 ==
1801 12:20:42.792688 Write leveling (Byte 0): 26 => 26
1802 12:20:42.795925 Write leveling (Byte 1): 30 => 30
1803 12:20:42.796037 DramcWriteLeveling(PI) end<-----
1804 12:20:42.796129
1805 12:20:42.798993 ==
1806 12:20:42.802246 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 12:20:42.805548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 12:20:42.805630 ==
1809 12:20:42.808836 [Gating] SW mode calibration
1810 12:20:42.815631 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 12:20:42.819461 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 12:20:42.825808 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 12:20:42.829048 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1814 12:20:42.832098 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1815 12:20:42.838845 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:20:42.842230 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:20:42.845720 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:20:42.852779 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:20:42.855440 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:20:42.858950 0 7 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1821 12:20:42.865595 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:20:42.868982 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:20:42.871971 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:20:42.878947 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:20:42.882256 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:20:42.885654 0 7 24 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
1827 12:20:42.892354 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:20:42.895461 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:20:42.898786 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1830 12:20:42.905359 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1831 12:20:42.908651 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:20:42.911709 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:20:42.915386 0 8 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1834 12:20:42.921797 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:20:42.925387 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:20:42.928634 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:20:42.935476 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1838 12:20:42.938847 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1839 12:20:42.942131 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 12:20:42.948644 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 12:20:42.952204 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 12:20:42.955841 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 12:20:42.962333 0 9 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1844 12:20:42.965282 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 12:20:42.968788 0 10 4 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (1 1)
1846 12:20:42.975819 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1847 12:20:42.978754 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:20:42.982376 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:20:42.988810 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:20:42.992287 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:20:42.995613 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:20:42.998613 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1853 12:20:43.005713 0 11 4 | B1->B0 | 2c2c 3737 | 0 1 | (0 0) (0 0)
1854 12:20:43.008702 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1855 12:20:43.011871 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 12:20:43.018853 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 12:20:43.022014 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 12:20:43.025657 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 12:20:43.032153 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 12:20:43.035429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 12:20:43.038752 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1862 12:20:43.045977 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:20:43.048899 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:20:43.052474 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:20:43.059247 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:20:43.062490 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:20:43.065467 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:20:43.072028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:20:43.075700 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:20:43.078698 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:20:43.085622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:20:43.088613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:20:43.091968 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:20:43.096206 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:20:43.102368 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:20:43.105195 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:20:43.108649 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1878 12:20:43.115676 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1879 12:20:43.119069 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 12:20:43.122170 Total UI for P1: 0, mck2ui 16
1881 12:20:43.125351 best dqsien dly found for B0: ( 0, 14, 6)
1882 12:20:43.129018 Total UI for P1: 0, mck2ui 16
1883 12:20:43.131876 best dqsien dly found for B1: ( 0, 14, 6)
1884 12:20:43.135482 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1885 12:20:43.139056 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1886 12:20:43.139149
1887 12:20:43.141933 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1888 12:20:43.145183 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1889 12:20:43.149019 [Gating] SW calibration Done
1890 12:20:43.149103 ==
1891 12:20:43.152406 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 12:20:43.155483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 12:20:43.159035 ==
1894 12:20:43.159117 RX Vref Scan: 0
1895 12:20:43.159182
1896 12:20:43.162190 RX Vref 0 -> 0, step: 1
1897 12:20:43.162272
1898 12:20:43.165606 RX Delay -130 -> 252, step: 16
1899 12:20:43.169104 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1900 12:20:43.172036 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1901 12:20:43.175498 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1902 12:20:43.178941 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1903 12:20:43.185674 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1904 12:20:43.189194 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1905 12:20:43.191820 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1906 12:20:43.195342 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1907 12:20:43.198509 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1908 12:20:43.205277 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1909 12:20:43.208479 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1910 12:20:43.212292 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1911 12:20:43.215117 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1912 12:20:43.218882 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1913 12:20:43.225263 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1914 12:20:43.228926 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1915 12:20:43.229036 ==
1916 12:20:43.232130 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 12:20:43.235401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 12:20:43.235486 ==
1919 12:20:43.235551 DQS Delay:
1920 12:20:43.238843 DQS0 = 0, DQS1 = 0
1921 12:20:43.238926 DQM Delay:
1922 12:20:43.241950 DQM0 = 77, DQM1 = 71
1923 12:20:43.242058 DQ Delay:
1924 12:20:43.245348 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1925 12:20:43.248645 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1926 12:20:43.252733 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1927 12:20:43.255647 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1928 12:20:43.255731
1929 12:20:43.255796
1930 12:20:43.255856 ==
1931 12:20:43.258972 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 12:20:43.262255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 12:20:43.265421 ==
1934 12:20:43.265535
1935 12:20:43.265632
1936 12:20:43.265733 TX Vref Scan disable
1937 12:20:43.268921 == TX Byte 0 ==
1938 12:20:43.272312 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1939 12:20:43.275297 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1940 12:20:43.278934 == TX Byte 1 ==
1941 12:20:43.282051 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1942 12:20:43.285356 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1943 12:20:43.285432 ==
1944 12:20:43.288776 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 12:20:43.295772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 12:20:43.295853 ==
1947 12:20:43.307726 TX Vref=22, minBit 1, minWin=28, winSum=453
1948 12:20:43.311197 TX Vref=24, minBit 1, minWin=28, winSum=453
1949 12:20:43.314698 TX Vref=26, minBit 1, minWin=28, winSum=459
1950 12:20:43.318048 TX Vref=28, minBit 1, minWin=28, winSum=459
1951 12:20:43.321153 TX Vref=30, minBit 1, minWin=28, winSum=461
1952 12:20:43.324582 TX Vref=32, minBit 1, minWin=27, winSum=459
1953 12:20:43.331224 [TxChooseVref] Worse bit 1, Min win 28, Win sum 461, Final Vref 30
1954 12:20:43.331325
1955 12:20:43.334738 Final TX Range 1 Vref 30
1956 12:20:43.334836
1957 12:20:43.334933 ==
1958 12:20:43.337612 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 12:20:43.341258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 12:20:43.341357 ==
1961 12:20:43.341452
1962 12:20:43.344559
1963 12:20:43.344634 TX Vref Scan disable
1964 12:20:43.348088 == TX Byte 0 ==
1965 12:20:43.351466 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1966 12:20:43.357979 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1967 12:20:43.358096 == TX Byte 1 ==
1968 12:20:43.361100 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1969 12:20:43.364616 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1970 12:20:43.367637
1971 12:20:43.367738 [DATLAT]
1972 12:20:43.367839 Freq=800, CH1 RK1
1973 12:20:43.367927
1974 12:20:43.371498 DATLAT Default: 0xa
1975 12:20:43.371573 0, 0xFFFF, sum = 0
1976 12:20:43.374820 1, 0xFFFF, sum = 0
1977 12:20:43.374921 2, 0xFFFF, sum = 0
1978 12:20:43.377657 3, 0xFFFF, sum = 0
1979 12:20:43.377763 4, 0xFFFF, sum = 0
1980 12:20:43.381261 5, 0xFFFF, sum = 0
1981 12:20:43.384506 6, 0xFFFF, sum = 0
1982 12:20:43.384591 7, 0xFFFF, sum = 0
1983 12:20:43.388210 8, 0xFFFF, sum = 0
1984 12:20:43.388294 9, 0x0, sum = 1
1985 12:20:43.388361 10, 0x0, sum = 2
1986 12:20:43.390953 11, 0x0, sum = 3
1987 12:20:43.391067 12, 0x0, sum = 4
1988 12:20:43.394738 best_step = 10
1989 12:20:43.394820
1990 12:20:43.394885 ==
1991 12:20:43.397667 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 12:20:43.401252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 12:20:43.401335 ==
1994 12:20:43.404825 RX Vref Scan: 0
1995 12:20:43.404907
1996 12:20:43.404972 RX Vref 0 -> 0, step: 1
1997 12:20:43.405033
1998 12:20:43.407656 RX Delay -111 -> 252, step: 8
1999 12:20:43.414609 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2000 12:20:43.417996 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2001 12:20:43.421255 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2002 12:20:43.424492 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2003 12:20:43.428096 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2004 12:20:43.434740 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2005 12:20:43.438361 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2006 12:20:43.441413 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2007 12:20:43.444822 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
2008 12:20:43.447886 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2009 12:20:43.454487 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2010 12:20:43.458172 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2011 12:20:43.461626 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2012 12:20:43.464647 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2013 12:20:43.468163 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2014 12:20:43.474727 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2015 12:20:43.474838 ==
2016 12:20:43.477955 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 12:20:43.481242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 12:20:43.481355 ==
2019 12:20:43.481451 DQS Delay:
2020 12:20:43.484650 DQS0 = 0, DQS1 = 0
2021 12:20:43.484734 DQM Delay:
2022 12:20:43.487927 DQM0 = 78, DQM1 = 73
2023 12:20:43.488040 DQ Delay:
2024 12:20:43.491348 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2025 12:20:43.494461 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2026 12:20:43.497960 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2027 12:20:43.501210 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
2028 12:20:43.501320
2029 12:20:43.501419
2030 12:20:43.511402 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2031 12:20:43.511516 CH1 RK1: MR19=606, MR18=2139
2032 12:20:43.518121 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2033 12:20:43.521008 [RxdqsGatingPostProcess] freq 800
2034 12:20:43.527568 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 12:20:43.531125 Pre-setting of DQS Precalculation
2036 12:20:43.534090 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 12:20:43.541206 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 12:20:43.547766 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 12:20:43.550931
2040 12:20:43.551039
2041 12:20:43.551130 [Calibration Summary] 1600 Mbps
2042 12:20:43.554587 CH 0, Rank 0
2043 12:20:43.554691 SW Impedance : PASS
2044 12:20:43.557955 DUTY Scan : NO K
2045 12:20:43.560979 ZQ Calibration : PASS
2046 12:20:43.561081 Jitter Meter : NO K
2047 12:20:43.563945 CBT Training : PASS
2048 12:20:43.567881 Write leveling : PASS
2049 12:20:43.567957 RX DQS gating : PASS
2050 12:20:43.571052 RX DQ/DQS(RDDQC) : PASS
2051 12:20:43.573945 TX DQ/DQS : PASS
2052 12:20:43.574045 RX DATLAT : PASS
2053 12:20:43.577460 RX DQ/DQS(Engine): PASS
2054 12:20:43.581036 TX OE : NO K
2055 12:20:43.581139 All Pass.
2056 12:20:43.581239
2057 12:20:43.581329 CH 0, Rank 1
2058 12:20:43.583959 SW Impedance : PASS
2059 12:20:43.587856 DUTY Scan : NO K
2060 12:20:43.587929 ZQ Calibration : PASS
2061 12:20:43.591031 Jitter Meter : NO K
2062 12:20:43.591136 CBT Training : PASS
2063 12:20:43.594424 Write leveling : PASS
2064 12:20:43.597776 RX DQS gating : PASS
2065 12:20:43.597872 RX DQ/DQS(RDDQC) : PASS
2066 12:20:43.600677 TX DQ/DQS : PASS
2067 12:20:43.604580 RX DATLAT : PASS
2068 12:20:43.604662 RX DQ/DQS(Engine): PASS
2069 12:20:43.607619 TX OE : NO K
2070 12:20:43.607701 All Pass.
2071 12:20:43.607764
2072 12:20:43.611051 CH 1, Rank 0
2073 12:20:43.611140 SW Impedance : PASS
2074 12:20:43.613923 DUTY Scan : NO K
2075 12:20:43.617550 ZQ Calibration : PASS
2076 12:20:43.617662 Jitter Meter : NO K
2077 12:20:43.620739 CBT Training : PASS
2078 12:20:43.624007 Write leveling : PASS
2079 12:20:43.624115 RX DQS gating : PASS
2080 12:20:43.627761 RX DQ/DQS(RDDQC) : PASS
2081 12:20:43.630905 TX DQ/DQS : PASS
2082 12:20:43.630986 RX DATLAT : PASS
2083 12:20:43.633788 RX DQ/DQS(Engine): PASS
2084 12:20:43.637202 TX OE : NO K
2085 12:20:43.637281 All Pass.
2086 12:20:43.637345
2087 12:20:43.637414 CH 1, Rank 1
2088 12:20:43.640824 SW Impedance : PASS
2089 12:20:43.644350 DUTY Scan : NO K
2090 12:20:43.644422 ZQ Calibration : PASS
2091 12:20:43.647344 Jitter Meter : NO K
2092 12:20:43.647441 CBT Training : PASS
2093 12:20:43.650911 Write leveling : PASS
2094 12:20:43.653872 RX DQS gating : PASS
2095 12:20:43.653953 RX DQ/DQS(RDDQC) : PASS
2096 12:20:43.657681 TX DQ/DQS : PASS
2097 12:20:43.660956 RX DATLAT : PASS
2098 12:20:43.661063 RX DQ/DQS(Engine): PASS
2099 12:20:43.664274 TX OE : NO K
2100 12:20:43.664355 All Pass.
2101 12:20:43.664419
2102 12:20:43.667150 DramC Write-DBI off
2103 12:20:43.670969 PER_BANK_REFRESH: Hybrid Mode
2104 12:20:43.671058 TX_TRACKING: ON
2105 12:20:43.673901 [GetDramInforAfterCalByMRR] Vendor 6.
2106 12:20:43.677406 [GetDramInforAfterCalByMRR] Revision 606.
2107 12:20:43.680873 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 12:20:43.683865 MR0 0x3b3b
2109 12:20:43.683950 MR8 0x5151
2110 12:20:43.687211 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 12:20:43.687319
2112 12:20:43.687428 MR0 0x3b3b
2113 12:20:43.690524 MR8 0x5151
2114 12:20:43.693957 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 12:20:43.694056
2116 12:20:43.704246 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 12:20:43.707312 [FAST_K] Save calibration result to emmc
2118 12:20:43.710981 [FAST_K] Save calibration result to emmc
2119 12:20:43.711057 dram_init: config_dvfs: 1
2120 12:20:43.717386 dramc_set_vcore_voltage set vcore to 662500
2121 12:20:43.717467 Read voltage for 1200, 2
2122 12:20:43.721143 Vio18 = 0
2123 12:20:43.721247 Vcore = 662500
2124 12:20:43.721341 Vdram = 0
2125 12:20:43.723805 Vddq = 0
2126 12:20:43.723881 Vmddr = 0
2127 12:20:43.727840 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 12:20:43.733676 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 12:20:43.737409 MEM_TYPE=3, freq_sel=15
2130 12:20:43.737515 sv_algorithm_assistance_LP4_1600
2131 12:20:43.744369 ============ PULL DRAM RESETB DOWN ============
2132 12:20:43.747451 ========== PULL DRAM RESETB DOWN end =========
2133 12:20:43.750340 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 12:20:43.753999 ===================================
2135 12:20:43.757092 LPDDR4 DRAM CONFIGURATION
2136 12:20:43.760635 ===================================
2137 12:20:43.764168 EX_ROW_EN[0] = 0x0
2138 12:20:43.764252 EX_ROW_EN[1] = 0x0
2139 12:20:43.767231 LP4Y_EN = 0x0
2140 12:20:43.767313 WORK_FSP = 0x0
2141 12:20:43.770465 WL = 0x4
2142 12:20:43.770573 RL = 0x4
2143 12:20:43.774054 BL = 0x2
2144 12:20:43.774166 RPST = 0x0
2145 12:20:43.777620 RD_PRE = 0x0
2146 12:20:43.777703 WR_PRE = 0x1
2147 12:20:43.780540 WR_PST = 0x0
2148 12:20:43.780648 DBI_WR = 0x0
2149 12:20:43.783831 DBI_RD = 0x0
2150 12:20:43.783913 OTF = 0x1
2151 12:20:43.787048 ===================================
2152 12:20:43.791002 ===================================
2153 12:20:43.794101 ANA top config
2154 12:20:43.797149 ===================================
2155 12:20:43.800447 DLL_ASYNC_EN = 0
2156 12:20:43.800565 ALL_SLAVE_EN = 0
2157 12:20:43.804010 NEW_RANK_MODE = 1
2158 12:20:43.806887 DLL_IDLE_MODE = 1
2159 12:20:43.810661 LP45_APHY_COMB_EN = 1
2160 12:20:43.810773 TX_ODT_DIS = 1
2161 12:20:43.814114 NEW_8X_MODE = 1
2162 12:20:43.817367 ===================================
2163 12:20:43.820449 ===================================
2164 12:20:43.824135 data_rate = 2400
2165 12:20:43.827500 CKR = 1
2166 12:20:43.830615 DQ_P2S_RATIO = 8
2167 12:20:43.833765 ===================================
2168 12:20:43.837320 CA_P2S_RATIO = 8
2169 12:20:43.837431 DQ_CA_OPEN = 0
2170 12:20:43.840256 DQ_SEMI_OPEN = 0
2171 12:20:43.843746 CA_SEMI_OPEN = 0
2172 12:20:43.847244 CA_FULL_RATE = 0
2173 12:20:43.850177 DQ_CKDIV4_EN = 0
2174 12:20:43.853913 CA_CKDIV4_EN = 0
2175 12:20:43.854017 CA_PREDIV_EN = 0
2176 12:20:43.856843 PH8_DLY = 17
2177 12:20:43.860582 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 12:20:43.863762 DQ_AAMCK_DIV = 4
2179 12:20:43.867334 CA_AAMCK_DIV = 4
2180 12:20:43.870068 CA_ADMCK_DIV = 4
2181 12:20:43.870172 DQ_TRACK_CA_EN = 0
2182 12:20:43.873615 CA_PICK = 1200
2183 12:20:43.876981 CA_MCKIO = 1200
2184 12:20:43.880391 MCKIO_SEMI = 0
2185 12:20:43.883850 PLL_FREQ = 2366
2186 12:20:43.886718 DQ_UI_PI_RATIO = 32
2187 12:20:43.890376 CA_UI_PI_RATIO = 0
2188 12:20:43.893356 ===================================
2189 12:20:43.896882 ===================================
2190 12:20:43.896989 memory_type:LPDDR4
2191 12:20:43.900264 GP_NUM : 10
2192 12:20:43.903909 SRAM_EN : 1
2193 12:20:43.904013 MD32_EN : 0
2194 12:20:43.906803 ===================================
2195 12:20:43.910461 [ANA_INIT] >>>>>>>>>>>>>>
2196 12:20:43.913951 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 12:20:43.916914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 12:20:43.920317 ===================================
2199 12:20:43.923300 data_rate = 2400,PCW = 0X5b00
2200 12:20:43.926804 ===================================
2201 12:20:43.930302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 12:20:43.933539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 12:20:43.940322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 12:20:43.943602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 12:20:43.946601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 12:20:43.950082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 12:20:43.953721 [ANA_INIT] flow start
2208 12:20:43.956680 [ANA_INIT] PLL >>>>>>>>
2209 12:20:43.956786 [ANA_INIT] PLL <<<<<<<<
2210 12:20:43.960373 [ANA_INIT] MIDPI >>>>>>>>
2211 12:20:43.963298 [ANA_INIT] MIDPI <<<<<<<<
2212 12:20:43.963409 [ANA_INIT] DLL >>>>>>>>
2213 12:20:43.966562 [ANA_INIT] DLL <<<<<<<<
2214 12:20:43.970595 [ANA_INIT] flow end
2215 12:20:43.973261 ============ LP4 DIFF to SE enter ============
2216 12:20:43.976715 ============ LP4 DIFF to SE exit ============
2217 12:20:43.979809 [ANA_INIT] <<<<<<<<<<<<<
2218 12:20:43.983809 [Flow] Enable top DCM control >>>>>
2219 12:20:43.986389 [Flow] Enable top DCM control <<<<<
2220 12:20:43.989782 Enable DLL master slave shuffle
2221 12:20:43.993297 ==============================================================
2222 12:20:43.996961 Gating Mode config
2223 12:20:44.003330 ==============================================================
2224 12:20:44.003436 Config description:
2225 12:20:44.013295 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 12:20:44.019957 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 12:20:44.026497 SELPH_MODE 0: By rank 1: By Phase
2228 12:20:44.029950 ==============================================================
2229 12:20:44.033607 GAT_TRACK_EN = 1
2230 12:20:44.036463 RX_GATING_MODE = 2
2231 12:20:44.039782 RX_GATING_TRACK_MODE = 2
2232 12:20:44.043227 SELPH_MODE = 1
2233 12:20:44.046822 PICG_EARLY_EN = 1
2234 12:20:44.049744 VALID_LAT_VALUE = 1
2235 12:20:44.053450 ==============================================================
2236 12:20:44.056415 Enter into Gating configuration >>>>
2237 12:20:44.060109 Exit from Gating configuration <<<<
2238 12:20:44.063107 Enter into DVFS_PRE_config >>>>>
2239 12:20:44.076226 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 12:20:44.076312 Exit from DVFS_PRE_config <<<<<
2241 12:20:44.079997 Enter into PICG configuration >>>>
2242 12:20:44.083249 Exit from PICG configuration <<<<
2243 12:20:44.086455 [RX_INPUT] configuration >>>>>
2244 12:20:44.089757 [RX_INPUT] configuration <<<<<
2245 12:20:44.096688 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 12:20:44.099676 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 12:20:44.106768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 12:20:44.113687 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 12:20:44.120246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 12:20:44.126615 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 12:20:44.129775 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 12:20:44.133102 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 12:20:44.136770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 12:20:44.143113 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 12:20:44.146934 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 12:20:44.150097 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 12:20:44.153363 ===================================
2258 12:20:44.156680 LPDDR4 DRAM CONFIGURATION
2259 12:20:44.160547 ===================================
2260 12:20:44.160629 EX_ROW_EN[0] = 0x0
2261 12:20:44.163242 EX_ROW_EN[1] = 0x0
2262 12:20:44.163341 LP4Y_EN = 0x0
2263 12:20:44.166811 WORK_FSP = 0x0
2264 12:20:44.169724 WL = 0x4
2265 12:20:44.169825 RL = 0x4
2266 12:20:44.173208 BL = 0x2
2267 12:20:44.173305 RPST = 0x0
2268 12:20:44.177018 RD_PRE = 0x0
2269 12:20:44.177127 WR_PRE = 0x1
2270 12:20:44.179774 WR_PST = 0x0
2271 12:20:44.179845 DBI_WR = 0x0
2272 12:20:44.183161 DBI_RD = 0x0
2273 12:20:44.183242 OTF = 0x1
2274 12:20:44.186860 ===================================
2275 12:20:44.190039 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 12:20:44.196589 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 12:20:44.199970 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 12:20:44.203446 ===================================
2279 12:20:44.206421 LPDDR4 DRAM CONFIGURATION
2280 12:20:44.209828 ===================================
2281 12:20:44.209909 EX_ROW_EN[0] = 0x10
2282 12:20:44.213090 EX_ROW_EN[1] = 0x0
2283 12:20:44.213173 LP4Y_EN = 0x0
2284 12:20:44.216711 WORK_FSP = 0x0
2285 12:20:44.216794 WL = 0x4
2286 12:20:44.220104 RL = 0x4
2287 12:20:44.220215 BL = 0x2
2288 12:20:44.223202 RPST = 0x0
2289 12:20:44.223288 RD_PRE = 0x0
2290 12:20:44.226476 WR_PRE = 0x1
2291 12:20:44.226559 WR_PST = 0x0
2292 12:20:44.230008 DBI_WR = 0x0
2293 12:20:44.232879 DBI_RD = 0x0
2294 12:20:44.232982 OTF = 0x1
2295 12:20:44.236572 ===================================
2296 12:20:44.243221 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 12:20:44.243332 ==
2298 12:20:44.246462 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 12:20:44.250253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 12:20:44.250335 ==
2301 12:20:44.253336 [Duty_Offset_Calibration]
2302 12:20:44.253430 B0:2 B1:0 CA:3
2303 12:20:44.253496
2304 12:20:44.256814 [DutyScan_Calibration_Flow] k_type=0
2305 12:20:44.267461
2306 12:20:44.267576 ==CLK 0==
2307 12:20:44.270590 Final CLK duty delay cell = 0
2308 12:20:44.274101 [0] MAX Duty = 5062%(X100), DQS PI = 28
2309 12:20:44.277635 [0] MIN Duty = 4906%(X100), DQS PI = 54
2310 12:20:44.277741 [0] AVG Duty = 4984%(X100)
2311 12:20:44.280671
2312 12:20:44.283672 CH0 CLK Duty spec in!! Max-Min= 156%
2313 12:20:44.287301 [DutyScan_Calibration_Flow] ====Done====
2314 12:20:44.287414
2315 12:20:44.290310 [DutyScan_Calibration_Flow] k_type=1
2316 12:20:44.306031
2317 12:20:44.306145 ==DQS 0 ==
2318 12:20:44.308987 Final DQS duty delay cell = 0
2319 12:20:44.312567 [0] MAX Duty = 5062%(X100), DQS PI = 16
2320 12:20:44.315713 [0] MIN Duty = 4907%(X100), DQS PI = 2
2321 12:20:44.315814 [0] AVG Duty = 4984%(X100)
2322 12:20:44.319589
2323 12:20:44.319664 ==DQS 1 ==
2324 12:20:44.323108 Final DQS duty delay cell = -4
2325 12:20:44.325937 [-4] MAX Duty = 4969%(X100), DQS PI = 24
2326 12:20:44.329286 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2327 12:20:44.332675 [-4] AVG Duty = 4922%(X100)
2328 12:20:44.332751
2329 12:20:44.336265 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2330 12:20:44.336339
2331 12:20:44.339634 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2332 12:20:44.342437 [DutyScan_Calibration_Flow] ====Done====
2333 12:20:44.342545
2334 12:20:44.345958 [DutyScan_Calibration_Flow] k_type=3
2335 12:20:44.363411
2336 12:20:44.363521 ==DQM 0 ==
2337 12:20:44.366401 Final DQM duty delay cell = 0
2338 12:20:44.369840 [0] MAX Duty = 5124%(X100), DQS PI = 28
2339 12:20:44.373297 [0] MIN Duty = 4876%(X100), DQS PI = 0
2340 12:20:44.373380 [0] AVG Duty = 5000%(X100)
2341 12:20:44.376729
2342 12:20:44.376831 ==DQM 1 ==
2343 12:20:44.380154 Final DQM duty delay cell = 4
2344 12:20:44.383399 [4] MAX Duty = 5124%(X100), DQS PI = 0
2345 12:20:44.386718 [4] MIN Duty = 5031%(X100), DQS PI = 10
2346 12:20:44.386823 [4] AVG Duty = 5077%(X100)
2347 12:20:44.389628
2348 12:20:44.393287 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2349 12:20:44.393385
2350 12:20:44.396621 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2351 12:20:44.399731 [DutyScan_Calibration_Flow] ====Done====
2352 12:20:44.399812
2353 12:20:44.403006 [DutyScan_Calibration_Flow] k_type=2
2354 12:20:44.418084
2355 12:20:44.418191 ==DQ 0 ==
2356 12:20:44.421731 Final DQ duty delay cell = -4
2357 12:20:44.424540 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2358 12:20:44.428155 [-4] MIN Duty = 4907%(X100), DQS PI = 52
2359 12:20:44.431762 [-4] AVG Duty = 4969%(X100)
2360 12:20:44.431869
2361 12:20:44.431960 ==DQ 1 ==
2362 12:20:44.435002 Final DQ duty delay cell = -4
2363 12:20:44.438072 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2364 12:20:44.441221 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2365 12:20:44.444787 [-4] AVG Duty = 4938%(X100)
2366 12:20:44.444873
2367 12:20:44.448368 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2368 12:20:44.448473
2369 12:20:44.451745 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2370 12:20:44.454780 [DutyScan_Calibration_Flow] ====Done====
2371 12:20:44.454882 ==
2372 12:20:44.457654 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 12:20:44.461432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 12:20:44.461536 ==
2375 12:20:44.464758 [Duty_Offset_Calibration]
2376 12:20:44.464832 B0:1 B1:-2 CA:0
2377 12:20:44.464895
2378 12:20:44.468034 [DutyScan_Calibration_Flow] k_type=0
2379 12:20:44.478979
2380 12:20:44.479055 ==CLK 0==
2381 12:20:44.482346 Final CLK duty delay cell = 0
2382 12:20:44.485268 [0] MAX Duty = 5062%(X100), DQS PI = 30
2383 12:20:44.488892 [0] MIN Duty = 4876%(X100), DQS PI = 2
2384 12:20:44.488975 [0] AVG Duty = 4969%(X100)
2385 12:20:44.489039
2386 12:20:44.492451 CH1 CLK Duty spec in!! Max-Min= 186%
2387 12:20:44.498932 [DutyScan_Calibration_Flow] ====Done====
2388 12:20:44.499010
2389 12:20:44.501858 [DutyScan_Calibration_Flow] k_type=1
2390 12:20:44.517189
2391 12:20:44.517290 ==DQS 0 ==
2392 12:20:44.520645 Final DQS duty delay cell = -4
2393 12:20:44.523868 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2394 12:20:44.527745 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2395 12:20:44.530404 [-4] AVG Duty = 4953%(X100)
2396 12:20:44.530498
2397 12:20:44.530585 ==DQS 1 ==
2398 12:20:44.533892 Final DQS duty delay cell = 0
2399 12:20:44.537435 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 12:20:44.540380 [0] MIN Duty = 4875%(X100), DQS PI = 26
2401 12:20:44.543890 [0] AVG Duty = 4984%(X100)
2402 12:20:44.543985
2403 12:20:44.547121 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2404 12:20:44.547218
2405 12:20:44.550344 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2406 12:20:44.554004 [DutyScan_Calibration_Flow] ====Done====
2407 12:20:44.554106
2408 12:20:44.557475 [DutyScan_Calibration_Flow] k_type=3
2409 12:20:44.573447
2410 12:20:44.573528 ==DQM 0 ==
2411 12:20:44.576913 Final DQM duty delay cell = 0
2412 12:20:44.580438 [0] MAX Duty = 5000%(X100), DQS PI = 22
2413 12:20:44.583788 [0] MIN Duty = 4876%(X100), DQS PI = 4
2414 12:20:44.583867 [0] AVG Duty = 4938%(X100)
2415 12:20:44.587062
2416 12:20:44.587143 ==DQM 1 ==
2417 12:20:44.590420 Final DQM duty delay cell = 0
2418 12:20:44.593704 [0] MAX Duty = 5031%(X100), DQS PI = 36
2419 12:20:44.597021 [0] MIN Duty = 4907%(X100), DQS PI = 2
2420 12:20:44.597101 [0] AVG Duty = 4969%(X100)
2421 12:20:44.600050
2422 12:20:44.603610 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2423 12:20:44.603689
2424 12:20:44.607127 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2425 12:20:44.610484 [DutyScan_Calibration_Flow] ====Done====
2426 12:20:44.610563
2427 12:20:44.613491 [DutyScan_Calibration_Flow] k_type=2
2428 12:20:44.630289
2429 12:20:44.630371 ==DQ 0 ==
2430 12:20:44.633471 Final DQ duty delay cell = 0
2431 12:20:44.637296 [0] MAX Duty = 5062%(X100), DQS PI = 12
2432 12:20:44.639934 [0] MIN Duty = 4938%(X100), DQS PI = 54
2433 12:20:44.640014 [0] AVG Duty = 5000%(X100)
2434 12:20:44.643518
2435 12:20:44.643597 ==DQ 1 ==
2436 12:20:44.646406 Final DQ duty delay cell = 0
2437 12:20:44.649973 [0] MAX Duty = 5093%(X100), DQS PI = 16
2438 12:20:44.653236 [0] MIN Duty = 4969%(X100), DQS PI = 26
2439 12:20:44.653317 [0] AVG Duty = 5031%(X100)
2440 12:20:44.653380
2441 12:20:44.659659 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 12:20:44.659739
2443 12:20:44.663216 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2444 12:20:44.666688 [DutyScan_Calibration_Flow] ====Done====
2445 12:20:44.669580 nWR fixed to 30
2446 12:20:44.669673 [ModeRegInit_LP4] CH0 RK0
2447 12:20:44.673487 [ModeRegInit_LP4] CH0 RK1
2448 12:20:44.676937 [ModeRegInit_LP4] CH1 RK0
2449 12:20:44.679725 [ModeRegInit_LP4] CH1 RK1
2450 12:20:44.679804 match AC timing 7
2451 12:20:44.683214 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 12:20:44.689935 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 12:20:44.693399 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 12:20:44.696469 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 12:20:44.703156 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 12:20:44.703236 ==
2457 12:20:44.706622 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 12:20:44.710202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 12:20:44.710282 ==
2460 12:20:44.716578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 12:20:44.719890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2462 12:20:44.730450 [CA 0] Center 40 (10~71) winsize 62
2463 12:20:44.733439 [CA 1] Center 39 (9~70) winsize 62
2464 12:20:44.736981 [CA 2] Center 36 (6~66) winsize 61
2465 12:20:44.739903 [CA 3] Center 35 (5~66) winsize 62
2466 12:20:44.743443 [CA 4] Center 34 (4~65) winsize 62
2467 12:20:44.746959 [CA 5] Center 33 (3~63) winsize 61
2468 12:20:44.747040
2469 12:20:44.749853 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2470 12:20:44.749982
2471 12:20:44.753506 [CATrainingPosCal] consider 1 rank data
2472 12:20:44.756906 u2DelayCellTimex100 = 270/100 ps
2473 12:20:44.760324 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2474 12:20:44.766894 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2475 12:20:44.770597 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2476 12:20:44.773590 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 12:20:44.776962 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2478 12:20:44.779998 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 12:20:44.780079
2480 12:20:44.783554 CA PerBit enable=1, Macro0, CA PI delay=33
2481 12:20:44.783634
2482 12:20:44.787118 [CBTSetCACLKResult] CA Dly = 33
2483 12:20:44.787199 CS Dly: 7 (0~38)
2484 12:20:44.789957 ==
2485 12:20:44.793796 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 12:20:44.796793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 12:20:44.796875 ==
2488 12:20:44.799918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 12:20:44.806552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2490 12:20:44.816306 [CA 0] Center 40 (10~71) winsize 62
2491 12:20:44.819744 [CA 1] Center 39 (9~70) winsize 62
2492 12:20:44.822985 [CA 2] Center 35 (5~66) winsize 62
2493 12:20:44.825974 [CA 3] Center 35 (5~66) winsize 62
2494 12:20:44.829437 [CA 4] Center 34 (4~65) winsize 62
2495 12:20:44.832824 [CA 5] Center 33 (3~63) winsize 61
2496 12:20:44.832935
2497 12:20:44.836205 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2498 12:20:44.836330
2499 12:20:44.839299 [CATrainingPosCal] consider 2 rank data
2500 12:20:44.842732 u2DelayCellTimex100 = 270/100 ps
2501 12:20:44.846056 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2502 12:20:44.849882 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2503 12:20:44.856512 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2504 12:20:44.859760 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 12:20:44.863059 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 12:20:44.866476 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2507 12:20:44.866556
2508 12:20:44.870067 CA PerBit enable=1, Macro0, CA PI delay=33
2509 12:20:44.870147
2510 12:20:44.872924 [CBTSetCACLKResult] CA Dly = 33
2511 12:20:44.873003 CS Dly: 8 (0~40)
2512 12:20:44.873081
2513 12:20:44.876532 ----->DramcWriteLeveling(PI) begin...
2514 12:20:44.879997 ==
2515 12:20:44.883237 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 12:20:44.886400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 12:20:44.886480 ==
2518 12:20:44.890080 Write leveling (Byte 0): 34 => 34
2519 12:20:44.892933 Write leveling (Byte 1): 29 => 29
2520 12:20:44.896371 DramcWriteLeveling(PI) end<-----
2521 12:20:44.896457
2522 12:20:44.896524 ==
2523 12:20:44.899488 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 12:20:44.902963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 12:20:44.903043 ==
2526 12:20:44.906394 [Gating] SW mode calibration
2527 12:20:44.913116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 12:20:44.916483 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 12:20:44.922972 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 12:20:44.926409 0 15 4 | B1->B0 | 2828 3434 | 1 0 | (0 0) (0 0)
2531 12:20:44.929502 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 12:20:44.936284 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 12:20:44.939871 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 12:20:44.942604 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 12:20:44.949361 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 12:20:44.952612 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2537 12:20:44.955751 1 0 0 | B1->B0 | 3232 2929 | 1 0 | (1 1) (1 0)
2538 12:20:44.962923 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
2539 12:20:44.965813 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 12:20:44.969531 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 12:20:44.976081 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 12:20:44.979610 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 12:20:44.982515 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 12:20:44.989511 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2545 12:20:44.992526 1 1 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2546 12:20:44.996086 1 1 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2547 12:20:45.002646 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 12:20:45.006040 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 12:20:45.009460 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 12:20:45.016312 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 12:20:45.019187 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 12:20:45.022799 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 12:20:45.029595 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 12:20:45.032597 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 12:20:45.036126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:20:45.039739 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:20:45.046050 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:20:45.049124 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:20:45.052910 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:20:45.059530 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:20:45.062457 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:20:45.066154 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:20:45.072656 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:20:45.075852 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:20:45.079462 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:20:45.086326 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:20:45.089250 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:20:45.092762 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:20:45.099354 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 12:20:45.099444 Total UI for P1: 0, mck2ui 16
2571 12:20:45.106277 best dqsien dly found for B0: ( 1, 3, 30)
2572 12:20:45.109165 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 12:20:45.112653 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 12:20:45.115999 Total UI for P1: 0, mck2ui 16
2575 12:20:45.119628 best dqsien dly found for B1: ( 1, 4, 2)
2576 12:20:45.122784 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2577 12:20:45.126312 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2578 12:20:45.126446
2579 12:20:45.129785 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2580 12:20:45.132861 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2581 12:20:45.135995 [Gating] SW calibration Done
2582 12:20:45.136102 ==
2583 12:20:45.139614 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 12:20:45.145976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 12:20:45.146078 ==
2586 12:20:45.146171 RX Vref Scan: 0
2587 12:20:45.146329
2588 12:20:45.149771 RX Vref 0 -> 0, step: 1
2589 12:20:45.149871
2590 12:20:45.153164 RX Delay -40 -> 252, step: 8
2591 12:20:45.155894 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2592 12:20:45.159350 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2593 12:20:45.162781 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2594 12:20:45.166283 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2595 12:20:45.172759 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2596 12:20:45.175991 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2597 12:20:45.179459 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2598 12:20:45.182836 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2599 12:20:45.185857 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2600 12:20:45.192560 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2601 12:20:45.196207 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2602 12:20:45.199729 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2603 12:20:45.202905 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2604 12:20:45.205879 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2605 12:20:45.212454 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2606 12:20:45.215819 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2607 12:20:45.215919 ==
2608 12:20:45.219243 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 12:20:45.222538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 12:20:45.222644 ==
2611 12:20:45.225853 DQS Delay:
2612 12:20:45.225926 DQS0 = 0, DQS1 = 0
2613 12:20:45.225987 DQM Delay:
2614 12:20:45.229343 DQM0 = 113, DQM1 = 102
2615 12:20:45.229418 DQ Delay:
2616 12:20:45.233096 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2617 12:20:45.235718 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2618 12:20:45.239387 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2619 12:20:45.242600 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2620 12:20:45.242701
2621 12:20:45.245897
2622 12:20:45.245995 ==
2623 12:20:45.249581 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 12:20:45.252592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 12:20:45.252697 ==
2626 12:20:45.252790
2627 12:20:45.252879
2628 12:20:45.255889 TX Vref Scan disable
2629 12:20:45.256003 == TX Byte 0 ==
2630 12:20:45.259588 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2631 12:20:45.265784 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2632 12:20:45.265874 == TX Byte 1 ==
2633 12:20:45.269325 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2634 12:20:45.276185 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2635 12:20:45.276267 ==
2636 12:20:45.279524 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 12:20:45.282773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 12:20:45.282903 ==
2639 12:20:45.295220 TX Vref=22, minBit 1, minWin=25, winSum=417
2640 12:20:45.298357 TX Vref=24, minBit 12, minWin=25, winSum=419
2641 12:20:45.301504 TX Vref=26, minBit 7, minWin=25, winSum=425
2642 12:20:45.304885 TX Vref=28, minBit 1, minWin=26, winSum=433
2643 12:20:45.308844 TX Vref=30, minBit 6, minWin=26, winSum=431
2644 12:20:45.314953 TX Vref=32, minBit 1, minWin=26, winSum=423
2645 12:20:45.318860 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
2646 12:20:45.318993
2647 12:20:45.321796 Final TX Range 1 Vref 28
2648 12:20:45.321875
2649 12:20:45.321938 ==
2650 12:20:45.324872 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 12:20:45.328168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 12:20:45.328248 ==
2653 12:20:45.331804
2654 12:20:45.331882
2655 12:20:45.331943 TX Vref Scan disable
2656 12:20:45.335181 == TX Byte 0 ==
2657 12:20:45.338023 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2658 12:20:45.341807 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2659 12:20:45.345048 == TX Byte 1 ==
2660 12:20:45.348452 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2661 12:20:45.351706 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2662 12:20:45.351786
2663 12:20:45.355188 [DATLAT]
2664 12:20:45.355292 Freq=1200, CH0 RK0
2665 12:20:45.355418
2666 12:20:45.358336 DATLAT Default: 0xd
2667 12:20:45.358415 0, 0xFFFF, sum = 0
2668 12:20:45.361647 1, 0xFFFF, sum = 0
2669 12:20:45.361752 2, 0xFFFF, sum = 0
2670 12:20:45.365247 3, 0xFFFF, sum = 0
2671 12:20:45.365354 4, 0xFFFF, sum = 0
2672 12:20:45.368555 5, 0xFFFF, sum = 0
2673 12:20:45.368636 6, 0xFFFF, sum = 0
2674 12:20:45.372053 7, 0xFFFF, sum = 0
2675 12:20:45.375000 8, 0xFFFF, sum = 0
2676 12:20:45.375080 9, 0xFFFF, sum = 0
2677 12:20:45.378403 10, 0xFFFF, sum = 0
2678 12:20:45.378483 11, 0xFFFF, sum = 0
2679 12:20:45.381851 12, 0x0, sum = 1
2680 12:20:45.381931 13, 0x0, sum = 2
2681 12:20:45.385214 14, 0x0, sum = 3
2682 12:20:45.385294 15, 0x0, sum = 4
2683 12:20:45.385357 best_step = 13
2684 12:20:45.385415
2685 12:20:45.388548 ==
2686 12:20:45.392174 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 12:20:45.394843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 12:20:45.394948 ==
2689 12:20:45.395039 RX Vref Scan: 1
2690 12:20:45.395125
2691 12:20:45.398464 Set Vref Range= 32 -> 127
2692 12:20:45.398544
2693 12:20:45.401925 RX Vref 32 -> 127, step: 1
2694 12:20:45.402005
2695 12:20:45.405325 RX Delay -37 -> 252, step: 4
2696 12:20:45.405405
2697 12:20:45.408731 Set Vref, RX VrefLevel [Byte0]: 32
2698 12:20:45.411911 [Byte1]: 32
2699 12:20:45.411992
2700 12:20:45.415270 Set Vref, RX VrefLevel [Byte0]: 33
2701 12:20:45.418785 [Byte1]: 33
2702 12:20:45.418867
2703 12:20:45.421848 Set Vref, RX VrefLevel [Byte0]: 34
2704 12:20:45.425370 [Byte1]: 34
2705 12:20:45.429421
2706 12:20:45.429500 Set Vref, RX VrefLevel [Byte0]: 35
2707 12:20:45.433309 [Byte1]: 35
2708 12:20:45.437980
2709 12:20:45.438060 Set Vref, RX VrefLevel [Byte0]: 36
2710 12:20:45.440827 [Byte1]: 36
2711 12:20:45.445539
2712 12:20:45.445618 Set Vref, RX VrefLevel [Byte0]: 37
2713 12:20:45.449182 [Byte1]: 37
2714 12:20:45.453737
2715 12:20:45.453817 Set Vref, RX VrefLevel [Byte0]: 38
2716 12:20:45.456816 [Byte1]: 38
2717 12:20:45.461685
2718 12:20:45.461764 Set Vref, RX VrefLevel [Byte0]: 39
2719 12:20:45.464947 [Byte1]: 39
2720 12:20:45.469715
2721 12:20:45.469785 Set Vref, RX VrefLevel [Byte0]: 40
2722 12:20:45.473044 [Byte1]: 40
2723 12:20:45.477785
2724 12:20:45.477863 Set Vref, RX VrefLevel [Byte0]: 41
2725 12:20:45.481473 [Byte1]: 41
2726 12:20:45.486016
2727 12:20:45.486095 Set Vref, RX VrefLevel [Byte0]: 42
2728 12:20:45.489400 [Byte1]: 42
2729 12:20:45.493520
2730 12:20:45.493608 Set Vref, RX VrefLevel [Byte0]: 43
2731 12:20:45.496838 [Byte1]: 43
2732 12:20:45.501537
2733 12:20:45.501616 Set Vref, RX VrefLevel [Byte0]: 44
2734 12:20:45.505069 [Byte1]: 44
2735 12:20:45.509448
2736 12:20:45.509528 Set Vref, RX VrefLevel [Byte0]: 45
2737 12:20:45.512739 [Byte1]: 45
2738 12:20:45.517595
2739 12:20:45.517716 Set Vref, RX VrefLevel [Byte0]: 46
2740 12:20:45.520947 [Byte1]: 46
2741 12:20:45.525534
2742 12:20:45.525613 Set Vref, RX VrefLevel [Byte0]: 47
2743 12:20:45.528771 [Byte1]: 47
2744 12:20:45.533493
2745 12:20:45.533572 Set Vref, RX VrefLevel [Byte0]: 48
2746 12:20:45.536976 [Byte1]: 48
2747 12:20:45.541609
2748 12:20:45.541689 Set Vref, RX VrefLevel [Byte0]: 49
2749 12:20:45.545316 [Byte1]: 49
2750 12:20:45.549517
2751 12:20:45.549596 Set Vref, RX VrefLevel [Byte0]: 50
2752 12:20:45.552816 [Byte1]: 50
2753 12:20:45.557806
2754 12:20:45.557885 Set Vref, RX VrefLevel [Byte0]: 51
2755 12:20:45.560853 [Byte1]: 51
2756 12:20:45.565886
2757 12:20:45.565964 Set Vref, RX VrefLevel [Byte0]: 52
2758 12:20:45.568759 [Byte1]: 52
2759 12:20:45.574342
2760 12:20:45.574420 Set Vref, RX VrefLevel [Byte0]: 53
2761 12:20:45.576930 [Byte1]: 53
2762 12:20:45.581851
2763 12:20:45.581929 Set Vref, RX VrefLevel [Byte0]: 54
2764 12:20:45.585186 [Byte1]: 54
2765 12:20:45.589486
2766 12:20:45.589565 Set Vref, RX VrefLevel [Byte0]: 55
2767 12:20:45.593245 [Byte1]: 55
2768 12:20:45.597441
2769 12:20:45.597519 Set Vref, RX VrefLevel [Byte0]: 56
2770 12:20:45.601560 [Byte1]: 56
2771 12:20:45.605947
2772 12:20:45.606027 Set Vref, RX VrefLevel [Byte0]: 57
2773 12:20:45.609298 [Byte1]: 57
2774 12:20:45.613957
2775 12:20:45.614036 Set Vref, RX VrefLevel [Byte0]: 58
2776 12:20:45.616833 [Byte1]: 58
2777 12:20:45.621557
2778 12:20:45.621636 Set Vref, RX VrefLevel [Byte0]: 59
2779 12:20:45.624944 [Byte1]: 59
2780 12:20:45.629506
2781 12:20:45.629585 Set Vref, RX VrefLevel [Byte0]: 60
2782 12:20:45.633206 [Byte1]: 60
2783 12:20:45.637683
2784 12:20:45.637763 Set Vref, RX VrefLevel [Byte0]: 61
2785 12:20:45.640677 [Byte1]: 61
2786 12:20:45.645513
2787 12:20:45.645592 Set Vref, RX VrefLevel [Byte0]: 62
2788 12:20:45.649183 [Byte1]: 62
2789 12:20:45.653502
2790 12:20:45.653581 Set Vref, RX VrefLevel [Byte0]: 63
2791 12:20:45.656912 [Byte1]: 63
2792 12:20:45.661457
2793 12:20:45.661535 Set Vref, RX VrefLevel [Byte0]: 64
2794 12:20:45.664707 [Byte1]: 64
2795 12:20:45.669681
2796 12:20:45.669751 Set Vref, RX VrefLevel [Byte0]: 65
2797 12:20:45.672914 [Byte1]: 65
2798 12:20:45.677915
2799 12:20:45.677994 Set Vref, RX VrefLevel [Byte0]: 66
2800 12:20:45.681222 [Byte1]: 66
2801 12:20:45.685703
2802 12:20:45.685781 Set Vref, RX VrefLevel [Byte0]: 67
2803 12:20:45.689176 [Byte1]: 67
2804 12:20:45.693906
2805 12:20:45.693987 Set Vref, RX VrefLevel [Byte0]: 68
2806 12:20:45.696970 [Byte1]: 68
2807 12:20:45.702032
2808 12:20:45.702112 Set Vref, RX VrefLevel [Byte0]: 69
2809 12:20:45.705081 [Byte1]: 69
2810 12:20:45.709911
2811 12:20:45.709991 Set Vref, RX VrefLevel [Byte0]: 70
2812 12:20:45.712931 [Byte1]: 70
2813 12:20:45.717599
2814 12:20:45.717680 Set Vref, RX VrefLevel [Byte0]: 71
2815 12:20:45.721222 [Byte1]: 71
2816 12:20:45.725860
2817 12:20:45.725941 Set Vref, RX VrefLevel [Byte0]: 72
2818 12:20:45.728767 [Byte1]: 72
2819 12:20:45.734034
2820 12:20:45.734115 Set Vref, RX VrefLevel [Byte0]: 73
2821 12:20:45.737138 [Byte1]: 73
2822 12:20:45.741874
2823 12:20:45.741954 Set Vref, RX VrefLevel [Byte0]: 74
2824 12:20:45.744946 [Byte1]: 74
2825 12:20:45.750034
2826 12:20:45.750114 Set Vref, RX VrefLevel [Byte0]: 75
2827 12:20:45.752905 [Byte1]: 75
2828 12:20:45.757723
2829 12:20:45.757804 Final RX Vref Byte 0 = 63 to rank0
2830 12:20:45.761286 Final RX Vref Byte 1 = 47 to rank0
2831 12:20:45.764601 Final RX Vref Byte 0 = 63 to rank1
2832 12:20:45.767969 Final RX Vref Byte 1 = 47 to rank1==
2833 12:20:45.770756 Dram Type= 6, Freq= 0, CH_0, rank 0
2834 12:20:45.777749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 12:20:45.777830 ==
2836 12:20:45.777895 DQS Delay:
2837 12:20:45.777954 DQS0 = 0, DQS1 = 0
2838 12:20:45.780820 DQM Delay:
2839 12:20:45.780901 DQM0 = 112, DQM1 = 98
2840 12:20:45.783969 DQ Delay:
2841 12:20:45.787755 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2842 12:20:45.790979 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2843 12:20:45.794700 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2844 12:20:45.797446 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =108
2845 12:20:45.797528
2846 12:20:45.797591
2847 12:20:45.804372 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2848 12:20:45.807305 CH0 RK0: MR19=303, MR18=FEFE
2849 12:20:45.814047 CH0_RK0: MR19=0x303, MR18=0xFEFE, DQSOSC=410, MR23=63, INC=39, DEC=26
2850 12:20:45.814128
2851 12:20:45.817682 ----->DramcWriteLeveling(PI) begin...
2852 12:20:45.817765 ==
2853 12:20:45.820748 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 12:20:45.824345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 12:20:45.824426 ==
2856 12:20:45.827516 Write leveling (Byte 0): 31 => 31
2857 12:20:45.830681 Write leveling (Byte 1): 30 => 30
2858 12:20:45.834428 DramcWriteLeveling(PI) end<-----
2859 12:20:45.834509
2860 12:20:45.834571 ==
2861 12:20:45.837741 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 12:20:45.844097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 12:20:45.844178 ==
2864 12:20:45.844242 [Gating] SW mode calibration
2865 12:20:45.853980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2866 12:20:45.857897 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2867 12:20:45.861052 0 15 0 | B1->B0 | 2525 3333 | 0 1 | (1 1) (1 1)
2868 12:20:45.867811 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 12:20:45.870724 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 12:20:45.874148 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 12:20:45.881141 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 12:20:45.883994 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 12:20:45.887330 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2874 12:20:45.894544 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
2875 12:20:45.897797 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2876 12:20:45.901253 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 12:20:45.907596 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 12:20:45.911075 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 12:20:45.913989 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 12:20:45.920898 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 12:20:45.924206 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2882 12:20:45.927407 1 0 28 | B1->B0 | 2626 4444 | 0 0 | (1 1) (0 0)
2883 12:20:45.934003 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2884 12:20:45.937523 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 12:20:45.941198 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 12:20:45.944157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 12:20:45.950737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 12:20:45.954325 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 12:20:45.957493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2890 12:20:45.964272 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2891 12:20:45.967567 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2892 12:20:45.970669 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:20:45.977412 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:20:45.980655 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:20:45.983963 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:20:45.990896 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:20:45.993861 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 12:20:45.997607 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 12:20:46.003821 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 12:20:46.007785 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 12:20:46.010674 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 12:20:46.017248 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 12:20:46.020880 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 12:20:46.023897 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 12:20:46.030562 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 12:20:46.034146 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2907 12:20:46.037546 Total UI for P1: 0, mck2ui 16
2908 12:20:46.040455 best dqsien dly found for B0: ( 1, 3, 26)
2909 12:20:46.043983 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 12:20:46.047499 Total UI for P1: 0, mck2ui 16
2911 12:20:46.050485 best dqsien dly found for B1: ( 1, 3, 30)
2912 12:20:46.053726 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2913 12:20:46.057753 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2914 12:20:46.057833
2915 12:20:46.060773 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2916 12:20:46.067683 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2917 12:20:46.067763 [Gating] SW calibration Done
2918 12:20:46.067826 ==
2919 12:20:46.070534 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 12:20:46.077190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 12:20:46.077273 ==
2922 12:20:46.077335 RX Vref Scan: 0
2923 12:20:46.077393
2924 12:20:46.080363 RX Vref 0 -> 0, step: 1
2925 12:20:46.080442
2926 12:20:46.083735 RX Delay -40 -> 252, step: 8
2927 12:20:46.087673 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2928 12:20:46.090750 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2929 12:20:46.094097 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2930 12:20:46.100523 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2931 12:20:46.104265 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2932 12:20:46.106996 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2933 12:20:46.110560 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2934 12:20:46.114237 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2935 12:20:46.117490 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2936 12:20:46.123737 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2937 12:20:46.127225 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2938 12:20:46.130667 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2939 12:20:46.134043 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2940 12:20:46.137032 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2941 12:20:46.144099 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2942 12:20:46.147546 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2943 12:20:46.147627 ==
2944 12:20:46.150421 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 12:20:46.153843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 12:20:46.153928 ==
2947 12:20:46.157577 DQS Delay:
2948 12:20:46.157657 DQS0 = 0, DQS1 = 0
2949 12:20:46.157720 DQM Delay:
2950 12:20:46.160389 DQM0 = 111, DQM1 = 101
2951 12:20:46.160469 DQ Delay:
2952 12:20:46.164322 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2953 12:20:46.167523 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2954 12:20:46.170649 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2955 12:20:46.173974 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2956 12:20:46.177170
2957 12:20:46.177251
2958 12:20:46.177314 ==
2959 12:20:46.180652 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 12:20:46.183683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 12:20:46.183764 ==
2962 12:20:46.183827
2963 12:20:46.183886
2964 12:20:46.187331 TX Vref Scan disable
2965 12:20:46.187437 == TX Byte 0 ==
2966 12:20:46.194073 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2967 12:20:46.196925 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2968 12:20:46.197008 == TX Byte 1 ==
2969 12:20:46.203895 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2970 12:20:46.207137 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2971 12:20:46.207218 ==
2972 12:20:46.210374 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 12:20:46.213965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 12:20:46.214046 ==
2975 12:20:46.225978 TX Vref=22, minBit 2, minWin=26, winSum=426
2976 12:20:46.229834 TX Vref=24, minBit 0, minWin=26, winSum=433
2977 12:20:46.233091 TX Vref=26, minBit 1, minWin=26, winSum=435
2978 12:20:46.236330 TX Vref=28, minBit 0, minWin=27, winSum=442
2979 12:20:46.239345 TX Vref=30, minBit 2, minWin=27, winSum=445
2980 12:20:46.242950 TX Vref=32, minBit 10, minWin=26, winSum=441
2981 12:20:46.249350 [TxChooseVref] Worse bit 2, Min win 27, Win sum 445, Final Vref 30
2982 12:20:46.249432
2983 12:20:46.252844 Final TX Range 1 Vref 30
2984 12:20:46.252925
2985 12:20:46.252988 ==
2986 12:20:46.256495 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 12:20:46.259761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 12:20:46.259843 ==
2989 12:20:46.259907
2990 12:20:46.263139
2991 12:20:46.263219 TX Vref Scan disable
2992 12:20:46.265932 == TX Byte 0 ==
2993 12:20:46.269493 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2994 12:20:46.272476 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2995 12:20:46.275999 == TX Byte 1 ==
2996 12:20:46.279394 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2997 12:20:46.282859 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2998 12:20:46.282942
2999 12:20:46.286210 [DATLAT]
3000 12:20:46.286291 Freq=1200, CH0 RK1
3001 12:20:46.286355
3002 12:20:46.289382 DATLAT Default: 0xd
3003 12:20:46.289464 0, 0xFFFF, sum = 0
3004 12:20:46.292676 1, 0xFFFF, sum = 0
3005 12:20:46.292759 2, 0xFFFF, sum = 0
3006 12:20:46.296041 3, 0xFFFF, sum = 0
3007 12:20:46.296139 4, 0xFFFF, sum = 0
3008 12:20:46.299585 5, 0xFFFF, sum = 0
3009 12:20:46.299667 6, 0xFFFF, sum = 0
3010 12:20:46.302482 7, 0xFFFF, sum = 0
3011 12:20:46.306173 8, 0xFFFF, sum = 0
3012 12:20:46.306273 9, 0xFFFF, sum = 0
3013 12:20:46.309192 10, 0xFFFF, sum = 0
3014 12:20:46.309274 11, 0xFFFF, sum = 0
3015 12:20:46.312350 12, 0x0, sum = 1
3016 12:20:46.312434 13, 0x0, sum = 2
3017 12:20:46.315926 14, 0x0, sum = 3
3018 12:20:46.316009 15, 0x0, sum = 4
3019 12:20:46.316074 best_step = 13
3020 12:20:46.319312
3021 12:20:46.319448 ==
3022 12:20:46.322317 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 12:20:46.325483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 12:20:46.325564 ==
3025 12:20:46.325629 RX Vref Scan: 0
3026 12:20:46.325688
3027 12:20:46.328805 RX Vref 0 -> 0, step: 1
3028 12:20:46.328886
3029 12:20:46.332316 RX Delay -37 -> 252, step: 4
3030 12:20:46.336021 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3031 12:20:46.342443 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3032 12:20:46.345845 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3033 12:20:46.349206 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3034 12:20:46.352254 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3035 12:20:46.355878 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3036 12:20:46.362494 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3037 12:20:46.365836 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3038 12:20:46.369190 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3039 12:20:46.372638 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3040 12:20:46.375315 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3041 12:20:46.382415 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3042 12:20:46.385970 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3043 12:20:46.388841 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3044 12:20:46.392168 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3045 12:20:46.395490 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3046 12:20:46.398806 ==
3047 12:20:46.398888 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 12:20:46.405480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 12:20:46.405564 ==
3050 12:20:46.405663 DQS Delay:
3051 12:20:46.409267 DQS0 = 0, DQS1 = 0
3052 12:20:46.409348 DQM Delay:
3053 12:20:46.412207 DQM0 = 110, DQM1 = 99
3054 12:20:46.412287 DQ Delay:
3055 12:20:46.415731 DQ0 =108, DQ1 =112, DQ2 =106, DQ3 =108
3056 12:20:46.418989 DQ4 =110, DQ5 =100, DQ6 =120, DQ7 =120
3057 12:20:46.422185 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3058 12:20:46.425428 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3059 12:20:46.425509
3060 12:20:46.425588
3061 12:20:46.435408 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3062 12:20:46.435505 CH0 RK1: MR19=403, MR18=12FA
3063 12:20:46.442053 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3064 12:20:46.445459 [RxdqsGatingPostProcess] freq 1200
3065 12:20:46.452015 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3066 12:20:46.455513 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 12:20:46.459189 best DQS1 dly(2T, 0.5T) = (0, 12)
3068 12:20:46.462100 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 12:20:46.465723 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3070 12:20:46.465805 best DQS0 dly(2T, 0.5T) = (0, 11)
3071 12:20:46.468702 best DQS1 dly(2T, 0.5T) = (0, 11)
3072 12:20:46.472179 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3073 12:20:46.475436 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3074 12:20:46.479002 Pre-setting of DQS Precalculation
3075 12:20:46.485702 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3076 12:20:46.485815 ==
3077 12:20:46.488962 Dram Type= 6, Freq= 0, CH_1, rank 0
3078 12:20:46.492432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 12:20:46.492513 ==
3080 12:20:46.498665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 12:20:46.502078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3082 12:20:46.512128 [CA 0] Center 37 (7~67) winsize 61
3083 12:20:46.515099 [CA 1] Center 37 (7~68) winsize 62
3084 12:20:46.518718 [CA 2] Center 34 (4~64) winsize 61
3085 12:20:46.522214 [CA 3] Center 34 (4~64) winsize 61
3086 12:20:46.525312 [CA 4] Center 34 (4~64) winsize 61
3087 12:20:46.528588 [CA 5] Center 33 (3~63) winsize 61
3088 12:20:46.528669
3089 12:20:46.532353 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3090 12:20:46.532434
3091 12:20:46.535738 [CATrainingPosCal] consider 1 rank data
3092 12:20:46.538855 u2DelayCellTimex100 = 270/100 ps
3093 12:20:46.542308 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3094 12:20:46.545759 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 12:20:46.552197 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 12:20:46.556043 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 12:20:46.558836 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 12:20:46.562850 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3099 12:20:46.562963
3100 12:20:46.565265 CA PerBit enable=1, Macro0, CA PI delay=33
3101 12:20:46.565344
3102 12:20:46.568549 [CBTSetCACLKResult] CA Dly = 33
3103 12:20:46.568628 CS Dly: 5 (0~36)
3104 12:20:46.568690 ==
3105 12:20:46.572012 Dram Type= 6, Freq= 0, CH_1, rank 1
3106 12:20:46.578615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 12:20:46.578695 ==
3108 12:20:46.581992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 12:20:46.588385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3110 12:20:46.597691 [CA 0] Center 37 (7~67) winsize 61
3111 12:20:46.600843 [CA 1] Center 37 (7~68) winsize 62
3112 12:20:46.604449 [CA 2] Center 34 (4~65) winsize 62
3113 12:20:46.607897 [CA 3] Center 33 (3~64) winsize 62
3114 12:20:46.611348 [CA 4] Center 34 (4~64) winsize 61
3115 12:20:46.614254 [CA 5] Center 33 (3~63) winsize 61
3116 12:20:46.614333
3117 12:20:46.617738 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3118 12:20:46.617818
3119 12:20:46.621199 [CATrainingPosCal] consider 2 rank data
3120 12:20:46.624158 u2DelayCellTimex100 = 270/100 ps
3121 12:20:46.627999 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3122 12:20:46.630800 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 12:20:46.637971 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 12:20:46.640955 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 12:20:46.644432 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 12:20:46.647670 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3127 12:20:46.647750
3128 12:20:46.650882 CA PerBit enable=1, Macro0, CA PI delay=33
3129 12:20:46.650962
3130 12:20:46.654429 [CBTSetCACLKResult] CA Dly = 33
3131 12:20:46.654508 CS Dly: 6 (0~39)
3132 12:20:46.654571
3133 12:20:46.657924 ----->DramcWriteLeveling(PI) begin...
3134 12:20:46.658004 ==
3135 12:20:46.661485 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 12:20:46.667942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 12:20:46.668023 ==
3138 12:20:46.671233 Write leveling (Byte 0): 26 => 26
3139 12:20:46.674517 Write leveling (Byte 1): 26 => 26
3140 12:20:46.674597 DramcWriteLeveling(PI) end<-----
3141 12:20:46.677841
3142 12:20:46.677920 ==
3143 12:20:46.680850 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 12:20:46.684386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 12:20:46.684465 ==
3146 12:20:46.687924 [Gating] SW mode calibration
3147 12:20:46.694298 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3148 12:20:46.697727 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3149 12:20:46.704495 0 15 0 | B1->B0 | 2b2b 2828 | 1 0 | (0 0) (0 0)
3150 12:20:46.707919 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 12:20:46.711237 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 12:20:46.717533 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 12:20:46.721261 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 12:20:46.724383 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 12:20:46.730853 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 12:20:46.734390 0 15 28 | B1->B0 | 2c2c 3030 | 1 0 | (1 0) (0 0)
3157 12:20:46.737484 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 12:20:46.744459 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 12:20:46.747293 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 12:20:46.750868 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 12:20:46.757560 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 12:20:46.760929 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3163 12:20:46.764261 1 0 24 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
3164 12:20:46.771151 1 0 28 | B1->B0 | 3a3a 3838 | 1 1 | (0 0) (0 0)
3165 12:20:46.774293 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3166 12:20:46.777811 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 12:20:46.784242 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 12:20:46.787736 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 12:20:46.790723 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 12:20:46.794186 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 12:20:46.800516 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 12:20:46.803923 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3173 12:20:46.807200 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3174 12:20:46.813901 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:20:46.817142 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:20:46.820679 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:20:46.827351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:20:46.830625 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:20:46.834130 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:20:46.840991 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 12:20:46.844079 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 12:20:46.847784 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 12:20:46.854060 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 12:20:46.857479 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 12:20:46.860415 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 12:20:46.867170 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 12:20:46.870392 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 12:20:46.873943 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3189 12:20:46.880440 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 12:20:46.880537 Total UI for P1: 0, mck2ui 16
3191 12:20:46.887685 best dqsien dly found for B0: ( 1, 3, 28)
3192 12:20:46.887765 Total UI for P1: 0, mck2ui 16
3193 12:20:46.890437 best dqsien dly found for B1: ( 1, 3, 28)
3194 12:20:46.897045 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3195 12:20:46.900810 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3196 12:20:46.900890
3197 12:20:46.904192 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3198 12:20:46.907149 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3199 12:20:46.910524 [Gating] SW calibration Done
3200 12:20:46.910603 ==
3201 12:20:46.913771 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 12:20:46.917079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 12:20:46.917163 ==
3204 12:20:46.920415 RX Vref Scan: 0
3205 12:20:46.920498
3206 12:20:46.920561 RX Vref 0 -> 0, step: 1
3207 12:20:46.920650
3208 12:20:46.923586 RX Delay -40 -> 252, step: 8
3209 12:20:46.927323 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3210 12:20:46.934044 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3211 12:20:46.936969 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3212 12:20:46.940981 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3213 12:20:46.944095 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3214 12:20:46.947146 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3215 12:20:46.950708 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3216 12:20:46.957080 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3217 12:20:46.960335 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3218 12:20:46.964114 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3219 12:20:46.967108 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3220 12:20:46.970481 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3221 12:20:46.977144 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3222 12:20:46.980604 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3223 12:20:46.983592 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3224 12:20:46.987171 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3225 12:20:46.987250 ==
3226 12:20:46.990382 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 12:20:46.997244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 12:20:46.997330 ==
3229 12:20:46.997403 DQS Delay:
3230 12:20:47.000488 DQS0 = 0, DQS1 = 0
3231 12:20:47.000567 DQM Delay:
3232 12:20:47.000628 DQM0 = 113, DQM1 = 106
3233 12:20:47.003802 DQ Delay:
3234 12:20:47.006835 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3235 12:20:47.010332 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3236 12:20:47.013608 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3237 12:20:47.017142 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3238 12:20:47.017226
3239 12:20:47.017288
3240 12:20:47.017345 ==
3241 12:20:47.020182 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 12:20:47.023605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 12:20:47.023685 ==
3244 12:20:47.026857
3245 12:20:47.026936
3246 12:20:47.026998 TX Vref Scan disable
3247 12:20:47.030177 == TX Byte 0 ==
3248 12:20:47.033653 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3249 12:20:47.037186 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3250 12:20:47.040508 == TX Byte 1 ==
3251 12:20:47.043965 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3252 12:20:47.046831 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3253 12:20:47.046910 ==
3254 12:20:47.050663 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 12:20:47.056679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 12:20:47.056759 ==
3257 12:20:47.068306 TX Vref=22, minBit 8, minWin=24, winSum=405
3258 12:20:47.071019 TX Vref=24, minBit 10, minWin=24, winSum=409
3259 12:20:47.074369 TX Vref=26, minBit 13, minWin=24, winSum=414
3260 12:20:47.077936 TX Vref=28, minBit 9, minWin=25, winSum=417
3261 12:20:47.080932 TX Vref=30, minBit 9, minWin=25, winSum=419
3262 12:20:47.084454 TX Vref=32, minBit 9, minWin=24, winSum=416
3263 12:20:47.091079 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 30
3264 12:20:47.091160
3265 12:20:47.094628 Final TX Range 1 Vref 30
3266 12:20:47.094712
3267 12:20:47.094787 ==
3268 12:20:47.098112 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 12:20:47.101332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 12:20:47.101413 ==
3271 12:20:47.104297
3272 12:20:47.104376
3273 12:20:47.104439 TX Vref Scan disable
3274 12:20:47.108136 == TX Byte 0 ==
3275 12:20:47.110861 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3276 12:20:47.114139 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3277 12:20:47.117578 == TX Byte 1 ==
3278 12:20:47.120885 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3279 12:20:47.124368 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3280 12:20:47.124450
3281 12:20:47.127310 [DATLAT]
3282 12:20:47.127442 Freq=1200, CH1 RK0
3283 12:20:47.127506
3284 12:20:47.131345 DATLAT Default: 0xd
3285 12:20:47.131453 0, 0xFFFF, sum = 0
3286 12:20:47.134264 1, 0xFFFF, sum = 0
3287 12:20:47.134348 2, 0xFFFF, sum = 0
3288 12:20:47.137881 3, 0xFFFF, sum = 0
3289 12:20:47.137964 4, 0xFFFF, sum = 0
3290 12:20:47.141078 5, 0xFFFF, sum = 0
3291 12:20:47.144308 6, 0xFFFF, sum = 0
3292 12:20:47.144389 7, 0xFFFF, sum = 0
3293 12:20:47.147921 8, 0xFFFF, sum = 0
3294 12:20:47.148001 9, 0xFFFF, sum = 0
3295 12:20:47.151159 10, 0xFFFF, sum = 0
3296 12:20:47.151240 11, 0xFFFF, sum = 0
3297 12:20:47.154060 12, 0x0, sum = 1
3298 12:20:47.154141 13, 0x0, sum = 2
3299 12:20:47.157672 14, 0x0, sum = 3
3300 12:20:47.157752 15, 0x0, sum = 4
3301 12:20:47.157815 best_step = 13
3302 12:20:47.157874
3303 12:20:47.161169 ==
3304 12:20:47.164102 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 12:20:47.167591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 12:20:47.167685 ==
3307 12:20:47.167747 RX Vref Scan: 1
3308 12:20:47.167805
3309 12:20:47.171219 Set Vref Range= 32 -> 127
3310 12:20:47.171298
3311 12:20:47.174310 RX Vref 32 -> 127, step: 1
3312 12:20:47.174389
3313 12:20:47.177379 RX Delay -21 -> 252, step: 4
3314 12:20:47.177458
3315 12:20:47.180814 Set Vref, RX VrefLevel [Byte0]: 32
3316 12:20:47.184297 [Byte1]: 32
3317 12:20:47.184376
3318 12:20:47.187830 Set Vref, RX VrefLevel [Byte0]: 33
3319 12:20:47.190821 [Byte1]: 33
3320 12:20:47.190900
3321 12:20:47.194496 Set Vref, RX VrefLevel [Byte0]: 34
3322 12:20:47.197373 [Byte1]: 34
3323 12:20:47.202052
3324 12:20:47.202131 Set Vref, RX VrefLevel [Byte0]: 35
3325 12:20:47.205418 [Byte1]: 35
3326 12:20:47.209622
3327 12:20:47.209701 Set Vref, RX VrefLevel [Byte0]: 36
3328 12:20:47.213107 [Byte1]: 36
3329 12:20:47.217778
3330 12:20:47.217857 Set Vref, RX VrefLevel [Byte0]: 37
3331 12:20:47.220804 [Byte1]: 37
3332 12:20:47.225596
3333 12:20:47.225674 Set Vref, RX VrefLevel [Byte0]: 38
3334 12:20:47.229022 [Byte1]: 38
3335 12:20:47.233398
3336 12:20:47.233478 Set Vref, RX VrefLevel [Byte0]: 39
3337 12:20:47.237032 [Byte1]: 39
3338 12:20:47.241402
3339 12:20:47.241485 Set Vref, RX VrefLevel [Byte0]: 40
3340 12:20:47.244518 [Byte1]: 40
3341 12:20:47.249443
3342 12:20:47.249522 Set Vref, RX VrefLevel [Byte0]: 41
3343 12:20:47.252891 [Byte1]: 41
3344 12:20:47.257261
3345 12:20:47.257341 Set Vref, RX VrefLevel [Byte0]: 42
3346 12:20:47.260550 [Byte1]: 42
3347 12:20:47.265170
3348 12:20:47.265249 Set Vref, RX VrefLevel [Byte0]: 43
3349 12:20:47.268499 [Byte1]: 43
3350 12:20:47.273052
3351 12:20:47.273131 Set Vref, RX VrefLevel [Byte0]: 44
3352 12:20:47.276464 [Byte1]: 44
3353 12:20:47.281133
3354 12:20:47.281213 Set Vref, RX VrefLevel [Byte0]: 45
3355 12:20:47.284631 [Byte1]: 45
3356 12:20:47.288784
3357 12:20:47.288866 Set Vref, RX VrefLevel [Byte0]: 46
3358 12:20:47.292202 [Byte1]: 46
3359 12:20:47.297364
3360 12:20:47.297443 Set Vref, RX VrefLevel [Byte0]: 47
3361 12:20:47.300064 [Byte1]: 47
3362 12:20:47.304693
3363 12:20:47.304772 Set Vref, RX VrefLevel [Byte0]: 48
3364 12:20:47.308248 [Byte1]: 48
3365 12:20:47.313108
3366 12:20:47.313187 Set Vref, RX VrefLevel [Byte0]: 49
3367 12:20:47.316426 [Byte1]: 49
3368 12:20:47.320973
3369 12:20:47.321052 Set Vref, RX VrefLevel [Byte0]: 50
3370 12:20:47.323811 [Byte1]: 50
3371 12:20:47.328687
3372 12:20:47.328767 Set Vref, RX VrefLevel [Byte0]: 51
3373 12:20:47.331882 [Byte1]: 51
3374 12:20:47.336775
3375 12:20:47.336855 Set Vref, RX VrefLevel [Byte0]: 52
3376 12:20:47.340115 [Byte1]: 52
3377 12:20:47.344735
3378 12:20:47.344815 Set Vref, RX VrefLevel [Byte0]: 53
3379 12:20:47.348019 [Byte1]: 53
3380 12:20:47.352338
3381 12:20:47.352417 Set Vref, RX VrefLevel [Byte0]: 54
3382 12:20:47.355889 [Byte1]: 54
3383 12:20:47.360025
3384 12:20:47.360105 Set Vref, RX VrefLevel [Byte0]: 55
3385 12:20:47.363649 [Byte1]: 55
3386 12:20:47.368248
3387 12:20:47.368328 Set Vref, RX VrefLevel [Byte0]: 56
3388 12:20:47.371414 [Byte1]: 56
3389 12:20:47.376449
3390 12:20:47.376529 Set Vref, RX VrefLevel [Byte0]: 57
3391 12:20:47.379496 [Byte1]: 57
3392 12:20:47.383842
3393 12:20:47.383922 Set Vref, RX VrefLevel [Byte0]: 58
3394 12:20:47.387523 [Byte1]: 58
3395 12:20:47.392157
3396 12:20:47.392258 Set Vref, RX VrefLevel [Byte0]: 59
3397 12:20:47.395128 [Byte1]: 59
3398 12:20:47.399896
3399 12:20:47.400002 Set Vref, RX VrefLevel [Byte0]: 60
3400 12:20:47.403359 [Byte1]: 60
3401 12:20:47.408158
3402 12:20:47.408283 Set Vref, RX VrefLevel [Byte0]: 61
3403 12:20:47.410995 [Byte1]: 61
3404 12:20:47.416025
3405 12:20:47.416120 Set Vref, RX VrefLevel [Byte0]: 62
3406 12:20:47.419280 [Byte1]: 62
3407 12:20:47.423480
3408 12:20:47.423560 Set Vref, RX VrefLevel [Byte0]: 63
3409 12:20:47.427119 [Byte1]: 63
3410 12:20:47.431961
3411 12:20:47.432041 Set Vref, RX VrefLevel [Byte0]: 64
3412 12:20:47.434803 [Byte1]: 64
3413 12:20:47.439755
3414 12:20:47.439834 Set Vref, RX VrefLevel [Byte0]: 65
3415 12:20:47.443149 [Byte1]: 65
3416 12:20:47.447661
3417 12:20:47.447741 Set Vref, RX VrefLevel [Byte0]: 66
3418 12:20:47.450632 [Byte1]: 66
3419 12:20:47.455278
3420 12:20:47.455408 Set Vref, RX VrefLevel [Byte0]: 67
3421 12:20:47.459022 [Byte1]: 67
3422 12:20:47.463303
3423 12:20:47.463407 Set Vref, RX VrefLevel [Byte0]: 68
3424 12:20:47.466643 [Byte1]: 68
3425 12:20:47.471327
3426 12:20:47.471444 Set Vref, RX VrefLevel [Byte0]: 69
3427 12:20:47.474741 [Byte1]: 69
3428 12:20:47.479722
3429 12:20:47.479803 Final RX Vref Byte 0 = 61 to rank0
3430 12:20:47.482363 Final RX Vref Byte 1 = 49 to rank0
3431 12:20:47.486121 Final RX Vref Byte 0 = 61 to rank1
3432 12:20:47.488939 Final RX Vref Byte 1 = 49 to rank1==
3433 12:20:47.492554 Dram Type= 6, Freq= 0, CH_1, rank 0
3434 12:20:47.498933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 12:20:47.499024 ==
3436 12:20:47.499106 DQS Delay:
3437 12:20:47.499185 DQS0 = 0, DQS1 = 0
3438 12:20:47.502132 DQM Delay:
3439 12:20:47.502205 DQM0 = 114, DQM1 = 105
3440 12:20:47.506045 DQ Delay:
3441 12:20:47.509272 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3442 12:20:47.512288 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3443 12:20:47.515775 DQ8 =94, DQ9 =100, DQ10 =104, DQ11 =100
3444 12:20:47.519283 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3445 12:20:47.519440
3446 12:20:47.519526
3447 12:20:47.525706 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3448 12:20:47.528837 CH1 RK0: MR19=303, MR18=EEF5
3449 12:20:47.536242 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3450 12:20:47.536325
3451 12:20:47.538823 ----->DramcWriteLeveling(PI) begin...
3452 12:20:47.538906 ==
3453 12:20:47.542296 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 12:20:47.545666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 12:20:47.549002 ==
3456 12:20:47.552492 Write leveling (Byte 0): 24 => 24
3457 12:20:47.552579 Write leveling (Byte 1): 30 => 30
3458 12:20:47.555527 DramcWriteLeveling(PI) end<-----
3459 12:20:47.555609
3460 12:20:47.555692 ==
3461 12:20:47.558996 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 12:20:47.565338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 12:20:47.565421 ==
3464 12:20:47.568582 [Gating] SW mode calibration
3465 12:20:47.575811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3466 12:20:47.578771 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3467 12:20:47.585703 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 12:20:47.589095 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 12:20:47.592090 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 12:20:47.595898 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 12:20:47.602177 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 12:20:47.605318 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 12:20:47.608740 0 15 24 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
3474 12:20:47.615567 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3475 12:20:47.618874 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 12:20:47.622332 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 12:20:47.628672 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 12:20:47.632156 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 12:20:47.635486 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 12:20:47.641805 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3481 12:20:47.645319 1 0 24 | B1->B0 | 2a2a 4545 | 1 0 | (0 0) (0 0)
3482 12:20:47.648525 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 12:20:47.655278 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 12:20:47.658812 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 12:20:47.661722 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 12:20:47.668338 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 12:20:47.671634 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 12:20:47.675041 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 12:20:47.681558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3490 12:20:47.685034 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3491 12:20:47.688819 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:20:47.695033 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:20:47.698226 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:20:47.701769 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:20:47.708550 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 12:20:47.711794 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 12:20:47.714866 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:20:47.721771 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:20:47.725199 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:20:47.728577 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 12:20:47.734706 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 12:20:47.738165 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 12:20:47.741320 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 12:20:47.748429 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 12:20:47.751717 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3506 12:20:47.754978 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3507 12:20:47.758555 Total UI for P1: 0, mck2ui 16
3508 12:20:47.761480 best dqsien dly found for B0: ( 1, 3, 24)
3509 12:20:47.764660 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 12:20:47.767877 Total UI for P1: 0, mck2ui 16
3511 12:20:47.771498 best dqsien dly found for B1: ( 1, 3, 28)
3512 12:20:47.774566 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3513 12:20:47.781441 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3514 12:20:47.781521
3515 12:20:47.784950 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3516 12:20:47.787992 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3517 12:20:47.791516 [Gating] SW calibration Done
3518 12:20:47.791597 ==
3519 12:20:47.794474 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 12:20:47.797877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 12:20:47.797958 ==
3522 12:20:47.798023 RX Vref Scan: 0
3523 12:20:47.801461
3524 12:20:47.801541 RX Vref 0 -> 0, step: 1
3525 12:20:47.801604
3526 12:20:47.804853 RX Delay -40 -> 252, step: 8
3527 12:20:47.807859 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3528 12:20:47.811347 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3529 12:20:47.817723 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3530 12:20:47.821476 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3531 12:20:47.824441 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3532 12:20:47.827905 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3533 12:20:47.830798 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3534 12:20:47.838219 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3535 12:20:47.840931 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3536 12:20:47.844257 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3537 12:20:47.847553 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3538 12:20:47.851046 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3539 12:20:47.857334 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3540 12:20:47.860709 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3541 12:20:47.864122 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3542 12:20:47.867600 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3543 12:20:47.867682 ==
3544 12:20:47.870902 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 12:20:47.877782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 12:20:47.877864 ==
3547 12:20:47.877929 DQS Delay:
3548 12:20:47.880880 DQS0 = 0, DQS1 = 0
3549 12:20:47.880961 DQM Delay:
3550 12:20:47.881024 DQM0 = 110, DQM1 = 108
3551 12:20:47.883933 DQ Delay:
3552 12:20:47.887755 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3553 12:20:47.890856 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =111
3554 12:20:47.893823 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3555 12:20:47.897332 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3556 12:20:47.897414
3557 12:20:47.897497
3558 12:20:47.897576 ==
3559 12:20:47.900668 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 12:20:47.903921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 12:20:47.907529 ==
3562 12:20:47.907611
3563 12:20:47.907694
3564 12:20:47.907773 TX Vref Scan disable
3565 12:20:47.910477 == TX Byte 0 ==
3566 12:20:47.914143 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3567 12:20:47.916949 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3568 12:20:47.920463 == TX Byte 1 ==
3569 12:20:47.923551 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3570 12:20:47.927133 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3571 12:20:47.927215 ==
3572 12:20:47.930503 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 12:20:47.937156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 12:20:47.937238 ==
3575 12:20:47.948206 TX Vref=22, minBit 0, minWin=26, winSum=428
3576 12:20:47.951394 TX Vref=24, minBit 0, minWin=26, winSum=434
3577 12:20:47.954725 TX Vref=26, minBit 1, minWin=26, winSum=437
3578 12:20:47.958101 TX Vref=28, minBit 0, minWin=27, winSum=438
3579 12:20:47.961399 TX Vref=30, minBit 1, minWin=26, winSum=437
3580 12:20:47.967996 TX Vref=32, minBit 3, minWin=26, winSum=431
3581 12:20:47.971349 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 28
3582 12:20:47.971457
3583 12:20:47.974905 Final TX Range 1 Vref 28
3584 12:20:47.974985
3585 12:20:47.975049 ==
3586 12:20:47.977739 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 12:20:47.981670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 12:20:47.984373 ==
3589 12:20:47.984454
3590 12:20:47.984517
3591 12:20:47.984575 TX Vref Scan disable
3592 12:20:47.988155 == TX Byte 0 ==
3593 12:20:47.991690 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3594 12:20:47.998052 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3595 12:20:47.998133 == TX Byte 1 ==
3596 12:20:48.001322 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3597 12:20:48.007946 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3598 12:20:48.008028
3599 12:20:48.008109 [DATLAT]
3600 12:20:48.008184 Freq=1200, CH1 RK1
3601 12:20:48.008241
3602 12:20:48.011319 DATLAT Default: 0xd
3603 12:20:48.011421 0, 0xFFFF, sum = 0
3604 12:20:48.014379 1, 0xFFFF, sum = 0
3605 12:20:48.014460 2, 0xFFFF, sum = 0
3606 12:20:48.017730 3, 0xFFFF, sum = 0
3607 12:20:48.021379 4, 0xFFFF, sum = 0
3608 12:20:48.021462 5, 0xFFFF, sum = 0
3609 12:20:48.024427 6, 0xFFFF, sum = 0
3610 12:20:48.024509 7, 0xFFFF, sum = 0
3611 12:20:48.027768 8, 0xFFFF, sum = 0
3612 12:20:48.027852 9, 0xFFFF, sum = 0
3613 12:20:48.031592 10, 0xFFFF, sum = 0
3614 12:20:48.031674 11, 0xFFFF, sum = 0
3615 12:20:48.034819 12, 0x0, sum = 1
3616 12:20:48.034901 13, 0x0, sum = 2
3617 12:20:48.037841 14, 0x0, sum = 3
3618 12:20:48.037924 15, 0x0, sum = 4
3619 12:20:48.037988 best_step = 13
3620 12:20:48.041360
3621 12:20:48.041439 ==
3622 12:20:48.044955 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 12:20:48.047851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 12:20:48.047932 ==
3625 12:20:48.047996 RX Vref Scan: 0
3626 12:20:48.048055
3627 12:20:48.051320 RX Vref 0 -> 0, step: 1
3628 12:20:48.051422
3629 12:20:48.054626 RX Delay -21 -> 252, step: 4
3630 12:20:48.057651 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3631 12:20:48.064182 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3632 12:20:48.067631 iDelay=195, Bit 2, Center 104 (35 ~ 174) 140
3633 12:20:48.071219 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3634 12:20:48.074564 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3635 12:20:48.077584 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3636 12:20:48.084046 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3637 12:20:48.087199 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3638 12:20:48.090924 iDelay=195, Bit 8, Center 96 (35 ~ 158) 124
3639 12:20:48.093956 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3640 12:20:48.097326 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3641 12:20:48.103728 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3642 12:20:48.107509 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3643 12:20:48.110387 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3644 12:20:48.113887 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3645 12:20:48.120241 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3646 12:20:48.120323 ==
3647 12:20:48.123888 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 12:20:48.127118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 12:20:48.127200 ==
3650 12:20:48.127263 DQS Delay:
3651 12:20:48.130090 DQS0 = 0, DQS1 = 0
3652 12:20:48.130172 DQM Delay:
3653 12:20:48.133342 DQM0 = 112, DQM1 = 109
3654 12:20:48.133422 DQ Delay:
3655 12:20:48.137244 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =110
3656 12:20:48.140166 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3657 12:20:48.143667 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3658 12:20:48.146981 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3659 12:20:48.149892
3660 12:20:48.149972
3661 12:20:48.156881 [DQSOSCAuto] RK1, (LSB)MR18= 0xf505, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 414 ps
3662 12:20:48.159755 CH1 RK1: MR19=304, MR18=F505
3663 12:20:48.166281 CH1_RK1: MR19=0x304, MR18=0xF505, DQSOSC=408, MR23=63, INC=39, DEC=26
3664 12:20:48.170123 [RxdqsGatingPostProcess] freq 1200
3665 12:20:48.172993 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3666 12:20:48.176279 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 12:20:48.179888 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 12:20:48.182734 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 12:20:48.186130 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 12:20:48.189708 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 12:20:48.193081 best DQS1 dly(2T, 0.5T) = (0, 11)
3672 12:20:48.196733 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 12:20:48.199406 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3674 12:20:48.203003 Pre-setting of DQS Precalculation
3675 12:20:48.206205 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3676 12:20:48.216013 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3677 12:20:48.222491 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3678 12:20:48.222573
3679 12:20:48.222636
3680 12:20:48.225990 [Calibration Summary] 2400 Mbps
3681 12:20:48.226072 CH 0, Rank 0
3682 12:20:48.229602 SW Impedance : PASS
3683 12:20:48.229684 DUTY Scan : NO K
3684 12:20:48.232642 ZQ Calibration : PASS
3685 12:20:48.235842 Jitter Meter : NO K
3686 12:20:48.235925 CBT Training : PASS
3687 12:20:48.239105 Write leveling : PASS
3688 12:20:48.242471 RX DQS gating : PASS
3689 12:20:48.242546 RX DQ/DQS(RDDQC) : PASS
3690 12:20:48.245702 TX DQ/DQS : PASS
3691 12:20:48.249041 RX DATLAT : PASS
3692 12:20:48.249123 RX DQ/DQS(Engine): PASS
3693 12:20:48.252461 TX OE : NO K
3694 12:20:48.252543 All Pass.
3695 12:20:48.252626
3696 12:20:48.255933 CH 0, Rank 1
3697 12:20:48.256015 SW Impedance : PASS
3698 12:20:48.258834 DUTY Scan : NO K
3699 12:20:48.262130 ZQ Calibration : PASS
3700 12:20:48.262212 Jitter Meter : NO K
3701 12:20:48.265694 CBT Training : PASS
3702 12:20:48.265777 Write leveling : PASS
3703 12:20:48.269215 RX DQS gating : PASS
3704 12:20:48.272136 RX DQ/DQS(RDDQC) : PASS
3705 12:20:48.272218 TX DQ/DQS : PASS
3706 12:20:48.275707 RX DATLAT : PASS
3707 12:20:48.279094 RX DQ/DQS(Engine): PASS
3708 12:20:48.279200 TX OE : NO K
3709 12:20:48.282319 All Pass.
3710 12:20:48.282401
3711 12:20:48.282483 CH 1, Rank 0
3712 12:20:48.285816 SW Impedance : PASS
3713 12:20:48.285898 DUTY Scan : NO K
3714 12:20:48.288624 ZQ Calibration : PASS
3715 12:20:48.292352 Jitter Meter : NO K
3716 12:20:48.292433 CBT Training : PASS
3717 12:20:48.295201 Write leveling : PASS
3718 12:20:48.298505 RX DQS gating : PASS
3719 12:20:48.298587 RX DQ/DQS(RDDQC) : PASS
3720 12:20:48.301882 TX DQ/DQS : PASS
3721 12:20:48.305321 RX DATLAT : PASS
3722 12:20:48.305406 RX DQ/DQS(Engine): PASS
3723 12:20:48.308795 TX OE : NO K
3724 12:20:48.308870 All Pass.
3725 12:20:48.308948
3726 12:20:48.311694 CH 1, Rank 1
3727 12:20:48.311786 SW Impedance : PASS
3728 12:20:48.315191 DUTY Scan : NO K
3729 12:20:48.318806 ZQ Calibration : PASS
3730 12:20:48.318888 Jitter Meter : NO K
3731 12:20:48.321734 CBT Training : PASS
3732 12:20:48.325113 Write leveling : PASS
3733 12:20:48.325229 RX DQS gating : PASS
3734 12:20:48.328132 RX DQ/DQS(RDDQC) : PASS
3735 12:20:48.328215 TX DQ/DQS : PASS
3736 12:20:48.331739 RX DATLAT : PASS
3737 12:20:48.334936 RX DQ/DQS(Engine): PASS
3738 12:20:48.335018 TX OE : NO K
3739 12:20:48.338498 All Pass.
3740 12:20:48.338580
3741 12:20:48.338662 DramC Write-DBI off
3742 12:20:48.341346 PER_BANK_REFRESH: Hybrid Mode
3743 12:20:48.344954 TX_TRACKING: ON
3744 12:20:48.351235 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3745 12:20:48.354391 [FAST_K] Save calibration result to emmc
3746 12:20:48.361256 dramc_set_vcore_voltage set vcore to 650000
3747 12:20:48.361340 Read voltage for 600, 5
3748 12:20:48.364361 Vio18 = 0
3749 12:20:48.364471 Vcore = 650000
3750 12:20:48.364561 Vdram = 0
3751 12:20:48.364623 Vddq = 0
3752 12:20:48.367705 Vmddr = 0
3753 12:20:48.371292 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3754 12:20:48.377677 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3755 12:20:48.380816 MEM_TYPE=3, freq_sel=19
3756 12:20:48.384423 sv_algorithm_assistance_LP4_1600
3757 12:20:48.387269 ============ PULL DRAM RESETB DOWN ============
3758 12:20:48.390820 ========== PULL DRAM RESETB DOWN end =========
3759 12:20:48.394362 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3760 12:20:48.397682 ===================================
3761 12:20:48.400899 LPDDR4 DRAM CONFIGURATION
3762 12:20:48.404339 ===================================
3763 12:20:48.407436 EX_ROW_EN[0] = 0x0
3764 12:20:48.407518 EX_ROW_EN[1] = 0x0
3765 12:20:48.410642 LP4Y_EN = 0x0
3766 12:20:48.410724 WORK_FSP = 0x0
3767 12:20:48.414114 WL = 0x2
3768 12:20:48.414189 RL = 0x2
3769 12:20:48.417254 BL = 0x2
3770 12:20:48.417336 RPST = 0x0
3771 12:20:48.420513 RD_PRE = 0x0
3772 12:20:48.424045 WR_PRE = 0x1
3773 12:20:48.424127 WR_PST = 0x0
3774 12:20:48.427520 DBI_WR = 0x0
3775 12:20:48.427602 DBI_RD = 0x0
3776 12:20:48.430348 OTF = 0x1
3777 12:20:48.433992 ===================================
3778 12:20:48.436954 ===================================
3779 12:20:48.437037 ANA top config
3780 12:20:48.440456 ===================================
3781 12:20:48.443820 DLL_ASYNC_EN = 0
3782 12:20:48.446796 ALL_SLAVE_EN = 1
3783 12:20:48.446892 NEW_RANK_MODE = 1
3784 12:20:48.450058 DLL_IDLE_MODE = 1
3785 12:20:48.453545 LP45_APHY_COMB_EN = 1
3786 12:20:48.457003 TX_ODT_DIS = 1
3787 12:20:48.457086 NEW_8X_MODE = 1
3788 12:20:48.460498 ===================================
3789 12:20:48.463429 ===================================
3790 12:20:48.466900 data_rate = 1200
3791 12:20:48.469799 CKR = 1
3792 12:20:48.473253 DQ_P2S_RATIO = 8
3793 12:20:48.476367 ===================================
3794 12:20:48.479868 CA_P2S_RATIO = 8
3795 12:20:48.483408 DQ_CA_OPEN = 0
3796 12:20:48.486523 DQ_SEMI_OPEN = 0
3797 12:20:48.486604 CA_SEMI_OPEN = 0
3798 12:20:48.489726 CA_FULL_RATE = 0
3799 12:20:48.493243 DQ_CKDIV4_EN = 1
3800 12:20:48.497026 CA_CKDIV4_EN = 1
3801 12:20:48.500015 CA_PREDIV_EN = 0
3802 12:20:48.503302 PH8_DLY = 0
3803 12:20:48.503410 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3804 12:20:48.506694 DQ_AAMCK_DIV = 4
3805 12:20:48.509838 CA_AAMCK_DIV = 4
3806 12:20:48.512694 CA_ADMCK_DIV = 4
3807 12:20:48.516261 DQ_TRACK_CA_EN = 0
3808 12:20:48.519451 CA_PICK = 600
3809 12:20:48.523043 CA_MCKIO = 600
3810 12:20:48.523142 MCKIO_SEMI = 0
3811 12:20:48.526014 PLL_FREQ = 2288
3812 12:20:48.529873 DQ_UI_PI_RATIO = 32
3813 12:20:48.532748 CA_UI_PI_RATIO = 0
3814 12:20:48.536089 ===================================
3815 12:20:48.539774 ===================================
3816 12:20:48.542925 memory_type:LPDDR4
3817 12:20:48.543006 GP_NUM : 10
3818 12:20:48.546232 SRAM_EN : 1
3819 12:20:48.549401 MD32_EN : 0
3820 12:20:48.552659 ===================================
3821 12:20:48.552741 [ANA_INIT] >>>>>>>>>>>>>>
3822 12:20:48.555874 <<<<<< [CONFIGURE PHASE]: ANA_TX
3823 12:20:48.559029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3824 12:20:48.562357 ===================================
3825 12:20:48.565973 data_rate = 1200,PCW = 0X5800
3826 12:20:48.569401 ===================================
3827 12:20:48.573027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3828 12:20:48.579073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 12:20:48.582323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 12:20:48.589044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3831 12:20:48.592114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3832 12:20:48.596145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3833 12:20:48.596247 [ANA_INIT] flow start
3834 12:20:48.598816 [ANA_INIT] PLL >>>>>>>>
3835 12:20:48.602357 [ANA_INIT] PLL <<<<<<<<
3836 12:20:48.605235 [ANA_INIT] MIDPI >>>>>>>>
3837 12:20:48.605311 [ANA_INIT] MIDPI <<<<<<<<
3838 12:20:48.608800 [ANA_INIT] DLL >>>>>>>>
3839 12:20:48.608869 [ANA_INIT] flow end
3840 12:20:48.615043 ============ LP4 DIFF to SE enter ============
3841 12:20:48.618615 ============ LP4 DIFF to SE exit ============
3842 12:20:48.621640 [ANA_INIT] <<<<<<<<<<<<<
3843 12:20:48.625516 [Flow] Enable top DCM control >>>>>
3844 12:20:48.628942 [Flow] Enable top DCM control <<<<<
3845 12:20:48.631902 Enable DLL master slave shuffle
3846 12:20:48.634837 ==============================================================
3847 12:20:48.638273 Gating Mode config
3848 12:20:48.641750 ==============================================================
3849 12:20:48.644759 Config description:
3850 12:20:48.655546 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3851 12:20:48.661645 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3852 12:20:48.664951 SELPH_MODE 0: By rank 1: By Phase
3853 12:20:48.671920 ==============================================================
3854 12:20:48.675090 GAT_TRACK_EN = 1
3855 12:20:48.678424 RX_GATING_MODE = 2
3856 12:20:48.681687 RX_GATING_TRACK_MODE = 2
3857 12:20:48.684760 SELPH_MODE = 1
3858 12:20:48.687805 PICG_EARLY_EN = 1
3859 12:20:48.691169 VALID_LAT_VALUE = 1
3860 12:20:48.695051 ==============================================================
3861 12:20:48.698082 Enter into Gating configuration >>>>
3862 12:20:48.701240 Exit from Gating configuration <<<<
3863 12:20:48.704666 Enter into DVFS_PRE_config >>>>>
3864 12:20:48.717838 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3865 12:20:48.720966 Exit from DVFS_PRE_config <<<<<
3866 12:20:48.721049 Enter into PICG configuration >>>>
3867 12:20:48.724299 Exit from PICG configuration <<<<
3868 12:20:48.727736 [RX_INPUT] configuration >>>>>
3869 12:20:48.730780 [RX_INPUT] configuration <<<<<
3870 12:20:48.737704 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3871 12:20:48.741124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3872 12:20:48.747583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 12:20:48.754130 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 12:20:48.760518 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 12:20:48.767210 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 12:20:48.770481 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3877 12:20:48.773998 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3878 12:20:48.777006 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3879 12:20:48.783597 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3880 12:20:48.787208 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3881 12:20:48.790344 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 12:20:48.793954 ===================================
3883 12:20:48.796903 LPDDR4 DRAM CONFIGURATION
3884 12:20:48.800524 ===================================
3885 12:20:48.803600 EX_ROW_EN[0] = 0x0
3886 12:20:48.803681 EX_ROW_EN[1] = 0x0
3887 12:20:48.807049 LP4Y_EN = 0x0
3888 12:20:48.807129 WORK_FSP = 0x0
3889 12:20:48.810101 WL = 0x2
3890 12:20:48.810182 RL = 0x2
3891 12:20:48.813616 BL = 0x2
3892 12:20:48.813718 RPST = 0x0
3893 12:20:48.816974 RD_PRE = 0x0
3894 12:20:48.817055 WR_PRE = 0x1
3895 12:20:48.820444 WR_PST = 0x0
3896 12:20:48.820525 DBI_WR = 0x0
3897 12:20:48.823250 DBI_RD = 0x0
3898 12:20:48.823331 OTF = 0x1
3899 12:20:48.826697 ===================================
3900 12:20:48.833640 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3901 12:20:48.836888 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3902 12:20:48.839919 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 12:20:48.843493 ===================================
3904 12:20:48.846639 LPDDR4 DRAM CONFIGURATION
3905 12:20:48.849839 ===================================
3906 12:20:48.853346 EX_ROW_EN[0] = 0x10
3907 12:20:48.853428 EX_ROW_EN[1] = 0x0
3908 12:20:48.856295 LP4Y_EN = 0x0
3909 12:20:48.856377 WORK_FSP = 0x0
3910 12:20:48.859845 WL = 0x2
3911 12:20:48.859926 RL = 0x2
3912 12:20:48.863637 BL = 0x2
3913 12:20:48.863742 RPST = 0x0
3914 12:20:48.866179 RD_PRE = 0x0
3915 12:20:48.866260 WR_PRE = 0x1
3916 12:20:48.869494 WR_PST = 0x0
3917 12:20:48.869575 DBI_WR = 0x0
3918 12:20:48.873058 DBI_RD = 0x0
3919 12:20:48.873138 OTF = 0x1
3920 12:20:48.876288 ===================================
3921 12:20:48.882662 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3922 12:20:48.887720 nWR fixed to 30
3923 12:20:48.891207 [ModeRegInit_LP4] CH0 RK0
3924 12:20:48.891287 [ModeRegInit_LP4] CH0 RK1
3925 12:20:48.894506 [ModeRegInit_LP4] CH1 RK0
3926 12:20:48.897627 [ModeRegInit_LP4] CH1 RK1
3927 12:20:48.897708 match AC timing 17
3928 12:20:48.904537 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3929 12:20:48.907896 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3930 12:20:48.911436 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3931 12:20:48.917835 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3932 12:20:48.921040 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3933 12:20:48.921121 ==
3934 12:20:48.924270 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 12:20:48.927522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 12:20:48.927604 ==
3937 12:20:48.934577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 12:20:48.941058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3939 12:20:48.944610 [CA 0] Center 37 (7~67) winsize 61
3940 12:20:48.947665 [CA 1] Center 37 (7~67) winsize 61
3941 12:20:48.951166 [CA 2] Center 35 (5~65) winsize 61
3942 12:20:48.954382 [CA 3] Center 35 (5~65) winsize 61
3943 12:20:48.957501 [CA 4] Center 34 (4~65) winsize 62
3944 12:20:48.961172 [CA 5] Center 34 (4~64) winsize 61
3945 12:20:48.961253
3946 12:20:48.964104 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3947 12:20:48.964185
3948 12:20:48.967666 [CATrainingPosCal] consider 1 rank data
3949 12:20:48.970885 u2DelayCellTimex100 = 270/100 ps
3950 12:20:48.974215 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3951 12:20:48.977768 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3952 12:20:48.980997 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3953 12:20:48.983881 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3954 12:20:48.987514 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3955 12:20:48.994488 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3956 12:20:48.994589
3957 12:20:48.997347 CA PerBit enable=1, Macro0, CA PI delay=34
3958 12:20:48.997419
3959 12:20:49.000631 [CBTSetCACLKResult] CA Dly = 34
3960 12:20:49.000732 CS Dly: 5 (0~36)
3961 12:20:49.000821 ==
3962 12:20:49.003910 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 12:20:49.007304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 12:20:49.010289 ==
3965 12:20:49.013919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 12:20:49.020343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3967 12:20:49.023950 [CA 0] Center 37 (7~67) winsize 61
3968 12:20:49.026770 [CA 1] Center 36 (6~67) winsize 62
3969 12:20:49.030434 [CA 2] Center 35 (5~65) winsize 61
3970 12:20:49.033845 [CA 3] Center 35 (5~65) winsize 61
3971 12:20:49.037059 [CA 4] Center 34 (4~65) winsize 62
3972 12:20:49.040449 [CA 5] Center 33 (3~64) winsize 62
3973 12:20:49.040556
3974 12:20:49.043591 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3975 12:20:49.043689
3976 12:20:49.047449 [CATrainingPosCal] consider 2 rank data
3977 12:20:49.050517 u2DelayCellTimex100 = 270/100 ps
3978 12:20:49.053513 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3979 12:20:49.057142 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3980 12:20:49.060423 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3981 12:20:49.066651 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3982 12:20:49.070292 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3983 12:20:49.073191 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3984 12:20:49.073299
3985 12:20:49.076673 CA PerBit enable=1, Macro0, CA PI delay=34
3986 12:20:49.076780
3987 12:20:49.080073 [CBTSetCACLKResult] CA Dly = 34
3988 12:20:49.080171 CS Dly: 5 (0~37)
3989 12:20:49.080278
3990 12:20:49.083703 ----->DramcWriteLeveling(PI) begin...
3991 12:20:49.086646 ==
3992 12:20:49.086722 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 12:20:49.093413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 12:20:49.093516 ==
3995 12:20:49.097112 Write leveling (Byte 0): 34 => 34
3996 12:20:49.099806 Write leveling (Byte 1): 29 => 29
3997 12:20:49.103173 DramcWriteLeveling(PI) end<-----
3998 12:20:49.103271
3999 12:20:49.103364 ==
4000 12:20:49.106691 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 12:20:49.109723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 12:20:49.109797 ==
4003 12:20:49.113592 [Gating] SW mode calibration
4004 12:20:49.119827 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4005 12:20:49.123243 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4006 12:20:49.129672 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 12:20:49.133454 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 12:20:49.136470 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 12:20:49.143031 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4010 12:20:49.146547 0 9 16 | B1->B0 | 3232 2929 | 1 0 | (1 1) (1 1)
4011 12:20:49.149729 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4012 12:20:49.156144 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 12:20:49.159347 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 12:20:49.162963 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 12:20:49.169342 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 12:20:49.172892 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 12:20:49.175750 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4018 12:20:49.182437 0 10 16 | B1->B0 | 3232 3838 | 0 1 | (0 0) (0 0)
4019 12:20:49.186029 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 12:20:49.189238 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 12:20:49.195658 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 12:20:49.199215 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 12:20:49.202620 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 12:20:49.209030 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 12:20:49.212558 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 12:20:49.216114 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:20:49.222594 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:20:49.225845 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:20:49.229003 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:20:49.235547 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:20:49.238973 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:20:49.242507 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:20:49.248893 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:20:49.251882 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:20:49.255356 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:20:49.262284 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:20:49.265226 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 12:20:49.268704 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 12:20:49.275509 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 12:20:49.278668 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 12:20:49.282136 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4042 12:20:49.288550 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4043 12:20:49.291853 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 12:20:49.295757 Total UI for P1: 0, mck2ui 16
4045 12:20:49.298387 best dqsien dly found for B0: ( 0, 13, 14)
4046 12:20:49.301962 Total UI for P1: 0, mck2ui 16
4047 12:20:49.305150 best dqsien dly found for B1: ( 0, 13, 18)
4048 12:20:49.308220 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4049 12:20:49.312055 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4050 12:20:49.312133
4051 12:20:49.314980 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4052 12:20:49.318522 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4053 12:20:49.321648 [Gating] SW calibration Done
4054 12:20:49.321750 ==
4055 12:20:49.325094 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 12:20:49.328227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 12:20:49.331327 ==
4058 12:20:49.331460 RX Vref Scan: 0
4059 12:20:49.331529
4060 12:20:49.334845 RX Vref 0 -> 0, step: 1
4061 12:20:49.334950
4062 12:20:49.338181 RX Delay -230 -> 252, step: 16
4063 12:20:49.341536 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4064 12:20:49.344739 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4065 12:20:49.348131 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4066 12:20:49.354792 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4067 12:20:49.357651 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4068 12:20:49.361496 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4069 12:20:49.364644 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4070 12:20:49.368038 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4071 12:20:49.374610 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4072 12:20:49.377650 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4073 12:20:49.381086 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4074 12:20:49.384633 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4075 12:20:49.391021 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4076 12:20:49.394508 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4077 12:20:49.397358 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4078 12:20:49.400649 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4079 12:20:49.404299 ==
4080 12:20:49.404398 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 12:20:49.410732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 12:20:49.410809 ==
4083 12:20:49.410887 DQS Delay:
4084 12:20:49.414134 DQS0 = 0, DQS1 = 0
4085 12:20:49.414224 DQM Delay:
4086 12:20:49.417586 DQM0 = 38, DQM1 = 32
4087 12:20:49.417656 DQ Delay:
4088 12:20:49.420965 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4089 12:20:49.423764 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4090 12:20:49.427030 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4091 12:20:49.430996 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4092 12:20:49.431094
4093 12:20:49.431182
4094 12:20:49.431270 ==
4095 12:20:49.434015 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 12:20:49.436982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 12:20:49.437056 ==
4098 12:20:49.437146
4099 12:20:49.437231
4100 12:20:49.440424 TX Vref Scan disable
4101 12:20:49.443653 == TX Byte 0 ==
4102 12:20:49.447212 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4103 12:20:49.450356 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4104 12:20:49.453760 == TX Byte 1 ==
4105 12:20:49.457263 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4106 12:20:49.460170 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4107 12:20:49.460244 ==
4108 12:20:49.463669 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 12:20:49.470194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 12:20:49.470269 ==
4111 12:20:49.470340
4112 12:20:49.470426
4113 12:20:49.470512 TX Vref Scan disable
4114 12:20:49.474975 == TX Byte 0 ==
4115 12:20:49.477860 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4116 12:20:49.484963 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4117 12:20:49.485068 == TX Byte 1 ==
4118 12:20:49.487878 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4119 12:20:49.495094 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4120 12:20:49.495199
4121 12:20:49.495290 [DATLAT]
4122 12:20:49.495384 Freq=600, CH0 RK0
4123 12:20:49.495450
4124 12:20:49.497945 DATLAT Default: 0x9
4125 12:20:49.498047 0, 0xFFFF, sum = 0
4126 12:20:49.501844 1, 0xFFFF, sum = 0
4127 12:20:49.501950 2, 0xFFFF, sum = 0
4128 12:20:49.504477 3, 0xFFFF, sum = 0
4129 12:20:49.507880 4, 0xFFFF, sum = 0
4130 12:20:49.507963 5, 0xFFFF, sum = 0
4131 12:20:49.511055 6, 0xFFFF, sum = 0
4132 12:20:49.511156 7, 0xFFFF, sum = 0
4133 12:20:49.514339 8, 0x0, sum = 1
4134 12:20:49.514444 9, 0x0, sum = 2
4135 12:20:49.514539 10, 0x0, sum = 3
4136 12:20:49.517762 11, 0x0, sum = 4
4137 12:20:49.517864 best_step = 9
4138 12:20:49.517955
4139 12:20:49.518042 ==
4140 12:20:49.521317 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 12:20:49.527563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 12:20:49.527672 ==
4143 12:20:49.527771 RX Vref Scan: 1
4144 12:20:49.527855
4145 12:20:49.531075 RX Vref 0 -> 0, step: 1
4146 12:20:49.531184
4147 12:20:49.534599 RX Delay -195 -> 252, step: 8
4148 12:20:49.534686
4149 12:20:49.537865 Set Vref, RX VrefLevel [Byte0]: 63
4150 12:20:49.541303 [Byte1]: 47
4151 12:20:49.541406
4152 12:20:49.544164 Final RX Vref Byte 0 = 63 to rank0
4153 12:20:49.547520 Final RX Vref Byte 1 = 47 to rank0
4154 12:20:49.551226 Final RX Vref Byte 0 = 63 to rank1
4155 12:20:49.554337 Final RX Vref Byte 1 = 47 to rank1==
4156 12:20:49.557740 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 12:20:49.560835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 12:20:49.560934 ==
4159 12:20:49.564004 DQS Delay:
4160 12:20:49.564084 DQS0 = 0, DQS1 = 0
4161 12:20:49.567855 DQM Delay:
4162 12:20:49.567958 DQM0 = 35, DQM1 = 29
4163 12:20:49.568048 DQ Delay:
4164 12:20:49.570901 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4165 12:20:49.574368 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4166 12:20:49.577259 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4167 12:20:49.580852 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4168 12:20:49.580956
4169 12:20:49.581052
4170 12:20:49.590494 [DQSOSCAuto] RK0, (LSB)MR18= 0x4040, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4171 12:20:49.594103 CH0 RK0: MR19=808, MR18=4040
4172 12:20:49.600859 CH0_RK0: MR19=0x808, MR18=0x4040, DQSOSC=397, MR23=63, INC=166, DEC=110
4173 12:20:49.600965
4174 12:20:49.604133 ----->DramcWriteLeveling(PI) begin...
4175 12:20:49.604234 ==
4176 12:20:49.607283 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 12:20:49.610911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 12:20:49.611019 ==
4179 12:20:49.613810 Write leveling (Byte 0): 36 => 36
4180 12:20:49.617099 Write leveling (Byte 1): 30 => 30
4181 12:20:49.620831 DramcWriteLeveling(PI) end<-----
4182 12:20:49.620933
4183 12:20:49.621026 ==
4184 12:20:49.624196 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 12:20:49.627413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 12:20:49.627507 ==
4187 12:20:49.630505 [Gating] SW mode calibration
4188 12:20:49.637237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4189 12:20:49.643561 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4190 12:20:49.647036 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 12:20:49.650561 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 12:20:49.657262 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 12:20:49.660809 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4194 12:20:49.664102 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
4195 12:20:49.670148 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 12:20:49.673958 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 12:20:49.677308 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 12:20:49.683432 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 12:20:49.687223 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 12:20:49.690441 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4201 12:20:49.696672 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4202 12:20:49.700501 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4203 12:20:49.703361 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 12:20:49.709812 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 12:20:49.713407 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 12:20:49.716911 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 12:20:49.723522 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 12:20:49.726867 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 12:20:49.729960 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4210 12:20:49.736634 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:20:49.739793 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:20:49.743268 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:20:49.746634 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:20:49.753314 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 12:20:49.756523 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:20:49.759597 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:20:49.766449 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:20:49.769482 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:20:49.773199 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 12:20:49.779761 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 12:20:49.782720 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 12:20:49.786166 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 12:20:49.792741 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 12:20:49.796560 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 12:20:49.799590 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4226 12:20:49.806174 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4227 12:20:49.809917 Total UI for P1: 0, mck2ui 16
4228 12:20:49.813406 best dqsien dly found for B0: ( 0, 13, 12)
4229 12:20:49.816283 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 12:20:49.819732 Total UI for P1: 0, mck2ui 16
4231 12:20:49.822674 best dqsien dly found for B1: ( 0, 13, 14)
4232 12:20:49.826251 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4233 12:20:49.829221 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4234 12:20:49.829306
4235 12:20:49.833100 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4236 12:20:49.836209 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 12:20:49.839888 [Gating] SW calibration Done
4238 12:20:49.839967 ==
4239 12:20:49.842894 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 12:20:49.849329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 12:20:49.849409 ==
4242 12:20:49.849471 RX Vref Scan: 0
4243 12:20:49.849529
4244 12:20:49.852713 RX Vref 0 -> 0, step: 1
4245 12:20:49.852793
4246 12:20:49.855614 RX Delay -230 -> 252, step: 16
4247 12:20:49.858871 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4248 12:20:49.862309 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4249 12:20:49.865678 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4250 12:20:49.871967 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4251 12:20:49.875573 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4252 12:20:49.879055 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4253 12:20:49.881886 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4254 12:20:49.889283 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4255 12:20:49.891878 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4256 12:20:49.895693 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4257 12:20:49.898596 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4258 12:20:49.904969 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4259 12:20:49.908247 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4260 12:20:49.912210 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4261 12:20:49.915215 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4262 12:20:49.921576 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4263 12:20:49.921656 ==
4264 12:20:49.925487 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 12:20:49.928801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 12:20:49.928881 ==
4267 12:20:49.928943 DQS Delay:
4268 12:20:49.931744 DQS0 = 0, DQS1 = 0
4269 12:20:49.931823 DQM Delay:
4270 12:20:49.935628 DQM0 = 35, DQM1 = 27
4271 12:20:49.935707 DQ Delay:
4272 12:20:49.938242 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4273 12:20:49.942108 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4274 12:20:49.944802 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4275 12:20:49.948317 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4276 12:20:49.948395
4277 12:20:49.948457
4278 12:20:49.948515 ==
4279 12:20:49.951822 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 12:20:49.955000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 12:20:49.955104 ==
4282 12:20:49.955228
4283 12:20:49.955313
4284 12:20:49.958177 TX Vref Scan disable
4285 12:20:49.961597 == TX Byte 0 ==
4286 12:20:49.964581 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4287 12:20:49.968202 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4288 12:20:49.971059 == TX Byte 1 ==
4289 12:20:49.974747 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4290 12:20:49.977837 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4291 12:20:49.977917 ==
4292 12:20:49.981632 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 12:20:49.987876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 12:20:49.987957 ==
4295 12:20:49.988018
4296 12:20:49.988075
4297 12:20:49.988130 TX Vref Scan disable
4298 12:20:49.992836 == TX Byte 0 ==
4299 12:20:49.996046 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4300 12:20:50.002376 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4301 12:20:50.002458 == TX Byte 1 ==
4302 12:20:50.006128 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4303 12:20:50.012752 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4304 12:20:50.012831
4305 12:20:50.012910 [DATLAT]
4306 12:20:50.013012 Freq=600, CH0 RK1
4307 12:20:50.013070
4308 12:20:50.015816 DATLAT Default: 0x9
4309 12:20:50.015895 0, 0xFFFF, sum = 0
4310 12:20:50.018928 1, 0xFFFF, sum = 0
4311 12:20:50.022304 2, 0xFFFF, sum = 0
4312 12:20:50.022385 3, 0xFFFF, sum = 0
4313 12:20:50.025815 4, 0xFFFF, sum = 0
4314 12:20:50.025895 5, 0xFFFF, sum = 0
4315 12:20:50.029284 6, 0xFFFF, sum = 0
4316 12:20:50.029399 7, 0xFFFF, sum = 0
4317 12:20:50.031992 8, 0x0, sum = 1
4318 12:20:50.032074 9, 0x0, sum = 2
4319 12:20:50.035363 10, 0x0, sum = 3
4320 12:20:50.035490 11, 0x0, sum = 4
4321 12:20:50.035554 best_step = 9
4322 12:20:50.035613
4323 12:20:50.038785 ==
4324 12:20:50.038865 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 12:20:50.045500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 12:20:50.045580 ==
4327 12:20:50.045643 RX Vref Scan: 0
4328 12:20:50.045701
4329 12:20:50.048986 RX Vref 0 -> 0, step: 1
4330 12:20:50.049066
4331 12:20:50.051983 RX Delay -195 -> 252, step: 8
4332 12:20:50.058952 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4333 12:20:50.061894 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4334 12:20:50.065300 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4335 12:20:50.068621 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4336 12:20:50.072390 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4337 12:20:50.078619 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4338 12:20:50.081721 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4339 12:20:50.085459 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4340 12:20:50.088630 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4341 12:20:50.095561 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4342 12:20:50.098465 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4343 12:20:50.101790 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4344 12:20:50.105097 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4345 12:20:50.112136 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4346 12:20:50.115340 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4347 12:20:50.118313 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4348 12:20:50.118393 ==
4349 12:20:50.121550 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 12:20:50.124860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 12:20:50.124941 ==
4352 12:20:50.128464 DQS Delay:
4353 12:20:50.128543 DQS0 = 0, DQS1 = 0
4354 12:20:50.131833 DQM Delay:
4355 12:20:50.131913 DQM0 = 33, DQM1 = 27
4356 12:20:50.131976 DQ Delay:
4357 12:20:50.134882 DQ0 =32, DQ1 =32, DQ2 =32, DQ3 =28
4358 12:20:50.138537 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4359 12:20:50.141528 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4360 12:20:50.145128 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4361 12:20:50.145209
4362 12:20:50.145272
4363 12:20:50.154759 [DQSOSCAuto] RK1, (LSB)MR18= 0x6635, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4364 12:20:50.158325 CH0 RK1: MR19=808, MR18=6635
4365 12:20:50.164810 CH0_RK1: MR19=0x808, MR18=0x6635, DQSOSC=390, MR23=63, INC=172, DEC=114
4366 12:20:50.164892 [RxdqsGatingPostProcess] freq 600
4367 12:20:50.171524 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4368 12:20:50.174922 Pre-setting of DQS Precalculation
4369 12:20:50.177863 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4370 12:20:50.181350 ==
4371 12:20:50.184796 Dram Type= 6, Freq= 0, CH_1, rank 0
4372 12:20:50.188141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 12:20:50.188271 ==
4374 12:20:50.191023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 12:20:50.198042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4376 12:20:50.201543 [CA 0] Center 36 (6~66) winsize 61
4377 12:20:50.205151 [CA 1] Center 36 (6~66) winsize 61
4378 12:20:50.208203 [CA 2] Center 34 (4~65) winsize 62
4379 12:20:50.211893 [CA 3] Center 34 (4~65) winsize 62
4380 12:20:50.215004 [CA 4] Center 34 (4~65) winsize 62
4381 12:20:50.218243 [CA 5] Center 34 (4~64) winsize 61
4382 12:20:50.218324
4383 12:20:50.221409 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4384 12:20:50.221516
4385 12:20:50.224674 [CATrainingPosCal] consider 1 rank data
4386 12:20:50.228368 u2DelayCellTimex100 = 270/100 ps
4387 12:20:50.231698 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4388 12:20:50.238143 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4389 12:20:50.241656 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 12:20:50.244660 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 12:20:50.248231 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 12:20:50.251176 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4393 12:20:50.251283
4394 12:20:50.254749 CA PerBit enable=1, Macro0, CA PI delay=34
4395 12:20:50.254831
4396 12:20:50.258031 [CBTSetCACLKResult] CA Dly = 34
4397 12:20:50.261218 CS Dly: 4 (0~35)
4398 12:20:50.261298 ==
4399 12:20:50.264262 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 12:20:50.267692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 12:20:50.267783 ==
4402 12:20:50.274303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 12:20:50.277620 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4404 12:20:50.281587 [CA 0] Center 36 (6~66) winsize 61
4405 12:20:50.285091 [CA 1] Center 36 (6~66) winsize 61
4406 12:20:50.288210 [CA 2] Center 34 (4~65) winsize 62
4407 12:20:50.291951 [CA 3] Center 33 (3~64) winsize 62
4408 12:20:50.295097 [CA 4] Center 34 (4~65) winsize 62
4409 12:20:50.298118 [CA 5] Center 33 (3~64) winsize 62
4410 12:20:50.298199
4411 12:20:50.301586 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4412 12:20:50.301667
4413 12:20:50.304979 [CATrainingPosCal] consider 2 rank data
4414 12:20:50.308257 u2DelayCellTimex100 = 270/100 ps
4415 12:20:50.311266 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4416 12:20:50.318350 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4417 12:20:50.321228 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 12:20:50.324738 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4419 12:20:50.328057 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 12:20:50.331650 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4421 12:20:50.331769
4422 12:20:50.334411 CA PerBit enable=1, Macro0, CA PI delay=34
4423 12:20:50.334509
4424 12:20:50.337793 [CBTSetCACLKResult] CA Dly = 34
4425 12:20:50.341135 CS Dly: 4 (0~36)
4426 12:20:50.341214
4427 12:20:50.344268 ----->DramcWriteLeveling(PI) begin...
4428 12:20:50.344343 ==
4429 12:20:50.347884 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 12:20:50.350836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 12:20:50.350909 ==
4432 12:20:50.354469 Write leveling (Byte 0): 27 => 27
4433 12:20:50.358006 Write leveling (Byte 1): 31 => 31
4434 12:20:50.360882 DramcWriteLeveling(PI) end<-----
4435 12:20:50.360963
4436 12:20:50.361026 ==
4437 12:20:50.364236 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 12:20:50.368075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 12:20:50.368157 ==
4440 12:20:50.371239 [Gating] SW mode calibration
4441 12:20:50.377557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4442 12:20:50.384071 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4443 12:20:50.387499 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 12:20:50.390645 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 12:20:50.397416 0 9 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
4446 12:20:50.400915 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
4447 12:20:50.403896 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
4448 12:20:50.410405 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 12:20:50.413947 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 12:20:50.417034 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 12:20:50.423973 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 12:20:50.427459 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 12:20:50.430314 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 12:20:50.436828 0 10 12 | B1->B0 | 2929 3030 | 0 0 | (0 0) (1 1)
4455 12:20:50.440309 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
4456 12:20:50.443810 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 12:20:50.450432 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 12:20:50.453504 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 12:20:50.456784 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 12:20:50.463485 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 12:20:50.467109 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 12:20:50.470269 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4463 12:20:50.476764 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4464 12:20:50.480256 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:20:50.483091 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:20:50.490149 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:20:50.493462 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:20:50.496556 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:20:50.503263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:20:50.506607 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:20:50.509978 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 12:20:50.516723 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 12:20:50.519662 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 12:20:50.523054 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 12:20:50.529541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 12:20:50.533027 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:20:50.536473 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:20:50.542927 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4479 12:20:50.545963 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 12:20:50.549538 Total UI for P1: 0, mck2ui 16
4481 12:20:50.552590 best dqsien dly found for B0: ( 0, 13, 12)
4482 12:20:50.556016 Total UI for P1: 0, mck2ui 16
4483 12:20:50.559302 best dqsien dly found for B1: ( 0, 13, 14)
4484 12:20:50.562590 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4485 12:20:50.566012 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4486 12:20:50.566094
4487 12:20:50.569075 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4488 12:20:50.572361 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4489 12:20:50.576036 [Gating] SW calibration Done
4490 12:20:50.576117 ==
4491 12:20:50.578973 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 12:20:50.582476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 12:20:50.586011 ==
4494 12:20:50.586092 RX Vref Scan: 0
4495 12:20:50.586155
4496 12:20:50.589255 RX Vref 0 -> 0, step: 1
4497 12:20:50.589336
4498 12:20:50.592552 RX Delay -230 -> 252, step: 16
4499 12:20:50.595864 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4500 12:20:50.599084 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4501 12:20:50.602509 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4502 12:20:50.605703 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4503 12:20:50.612692 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4504 12:20:50.615810 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4505 12:20:50.619082 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4506 12:20:50.622438 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4507 12:20:50.629065 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4508 12:20:50.632175 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4509 12:20:50.635350 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4510 12:20:50.639133 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4511 12:20:50.645898 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4512 12:20:50.648847 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4513 12:20:50.652369 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4514 12:20:50.655287 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4515 12:20:50.655379 ==
4516 12:20:50.658859 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 12:20:50.665326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 12:20:50.665432 ==
4519 12:20:50.665507 DQS Delay:
4520 12:20:50.669043 DQS0 = 0, DQS1 = 0
4521 12:20:50.669116 DQM Delay:
4522 12:20:50.669176 DQM0 = 38, DQM1 = 29
4523 12:20:50.672285 DQ Delay:
4524 12:20:50.675100 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4525 12:20:50.678916 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4526 12:20:50.682027 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4527 12:20:50.685177 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4528 12:20:50.685254
4529 12:20:50.685313
4530 12:20:50.685370 ==
4531 12:20:50.688981 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 12:20:50.692090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 12:20:50.692168 ==
4534 12:20:50.692232
4535 12:20:50.692292
4536 12:20:50.695640 TX Vref Scan disable
4537 12:20:50.695714 == TX Byte 0 ==
4538 12:20:50.702254 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4539 12:20:50.705559 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4540 12:20:50.708472 == TX Byte 1 ==
4541 12:20:50.711931 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4542 12:20:50.715386 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4543 12:20:50.715463 ==
4544 12:20:50.718697 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 12:20:50.721501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 12:20:50.725253 ==
4547 12:20:50.725330
4548 12:20:50.725395
4549 12:20:50.725456 TX Vref Scan disable
4550 12:20:50.728858 == TX Byte 0 ==
4551 12:20:50.732106 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4552 12:20:50.738694 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4553 12:20:50.738772 == TX Byte 1 ==
4554 12:20:50.742158 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4555 12:20:50.748524 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4556 12:20:50.748602
4557 12:20:50.748664 [DATLAT]
4558 12:20:50.748722 Freq=600, CH1 RK0
4559 12:20:50.748777
4560 12:20:50.752067 DATLAT Default: 0x9
4561 12:20:50.752135 0, 0xFFFF, sum = 0
4562 12:20:50.755535 1, 0xFFFF, sum = 0
4563 12:20:50.755669 2, 0xFFFF, sum = 0
4564 12:20:50.758604 3, 0xFFFF, sum = 0
4565 12:20:50.762262 4, 0xFFFF, sum = 0
4566 12:20:50.762362 5, 0xFFFF, sum = 0
4567 12:20:50.765595 6, 0xFFFF, sum = 0
4568 12:20:50.765684 7, 0xFFFF, sum = 0
4569 12:20:50.768651 8, 0x0, sum = 1
4570 12:20:50.768729 9, 0x0, sum = 2
4571 12:20:50.768790 10, 0x0, sum = 3
4572 12:20:50.772136 11, 0x0, sum = 4
4573 12:20:50.772267 best_step = 9
4574 12:20:50.772362
4575 12:20:50.772455 ==
4576 12:20:50.774956 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 12:20:50.782161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 12:20:50.782329 ==
4579 12:20:50.782453 RX Vref Scan: 1
4580 12:20:50.782572
4581 12:20:50.784992 RX Vref 0 -> 0, step: 1
4582 12:20:50.785106
4583 12:20:50.788292 RX Delay -195 -> 252, step: 8
4584 12:20:50.788444
4585 12:20:50.791577 Set Vref, RX VrefLevel [Byte0]: 61
4586 12:20:50.795254 [Byte1]: 49
4587 12:20:50.795392
4588 12:20:50.798429 Final RX Vref Byte 0 = 61 to rank0
4589 12:20:50.801606 Final RX Vref Byte 1 = 49 to rank0
4590 12:20:50.805502 Final RX Vref Byte 0 = 61 to rank1
4591 12:20:50.808012 Final RX Vref Byte 1 = 49 to rank1==
4592 12:20:50.811486 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 12:20:50.815132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 12:20:50.815241 ==
4595 12:20:50.818125 DQS Delay:
4596 12:20:50.818203 DQS0 = 0, DQS1 = 0
4597 12:20:50.821579 DQM Delay:
4598 12:20:50.821649 DQM0 = 38, DQM1 = 29
4599 12:20:50.821712 DQ Delay:
4600 12:20:50.824916 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4601 12:20:50.828199 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4602 12:20:50.831734 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =24
4603 12:20:50.835052 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4604 12:20:50.835147
4605 12:20:50.835238
4606 12:20:50.844970 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4607 12:20:50.848409 CH1 RK0: MR19=808, MR18=1E2B
4608 12:20:50.854667 CH1_RK0: MR19=0x808, MR18=0x1E2B, DQSOSC=401, MR23=63, INC=163, DEC=108
4609 12:20:50.854744
4610 12:20:50.858033 ----->DramcWriteLeveling(PI) begin...
4611 12:20:50.858105 ==
4612 12:20:50.861292 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 12:20:50.864407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 12:20:50.864556 ==
4615 12:20:50.867641 Write leveling (Byte 0): 31 => 31
4616 12:20:50.871229 Write leveling (Byte 1): 31 => 31
4617 12:20:50.874208 DramcWriteLeveling(PI) end<-----
4618 12:20:50.874282
4619 12:20:50.874361 ==
4620 12:20:50.877626 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 12:20:50.881374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 12:20:50.881456 ==
4623 12:20:50.884394 [Gating] SW mode calibration
4624 12:20:50.890833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4625 12:20:50.897785 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4626 12:20:50.901187 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 12:20:50.904342 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 12:20:50.910800 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 12:20:50.957815 0 9 12 | B1->B0 | 3232 2b2b | 1 1 | (1 0) (1 0)
4630 12:20:50.957932 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
4631 12:20:50.958003 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 12:20:50.958066 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 12:20:50.958125 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 12:20:50.958182 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 12:20:50.958254 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 12:20:50.958309 0 10 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
4637 12:20:50.958363 0 10 12 | B1->B0 | 3030 3b3b | 0 1 | (0 0) (0 0)
4638 12:20:50.958418 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4639 12:20:50.958471 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 12:20:50.964341 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 12:20:50.967474 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 12:20:50.970950 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 12:20:50.977169 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 12:20:50.980677 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4645 12:20:50.983950 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:20:50.990759 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:20:50.993674 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:20:50.997463 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:20:51.003596 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:20:51.007272 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:20:51.010214 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:20:51.016922 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:20:51.020389 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 12:20:51.023650 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 12:20:51.027333 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 12:20:51.033531 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 12:20:51.036922 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 12:20:51.040449 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 12:20:51.046674 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 12:20:51.050353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 12:20:51.053182 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4662 12:20:51.060194 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 12:20:51.063142 Total UI for P1: 0, mck2ui 16
4664 12:20:51.066746 best dqsien dly found for B0: ( 0, 13, 12)
4665 12:20:51.070292 Total UI for P1: 0, mck2ui 16
4666 12:20:51.073347 best dqsien dly found for B1: ( 0, 13, 12)
4667 12:20:51.076461 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4668 12:20:51.080165 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4669 12:20:51.080246
4670 12:20:51.083279 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4671 12:20:51.086457 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4672 12:20:51.089859 [Gating] SW calibration Done
4673 12:20:51.089939 ==
4674 12:20:51.093700 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 12:20:51.096290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 12:20:51.096371 ==
4677 12:20:51.099734 RX Vref Scan: 0
4678 12:20:51.099814
4679 12:20:51.103073 RX Vref 0 -> 0, step: 1
4680 12:20:51.103153
4681 12:20:51.103216 RX Delay -230 -> 252, step: 16
4682 12:20:51.109909 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4683 12:20:51.113061 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4684 12:20:51.116098 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4685 12:20:51.119540 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4686 12:20:51.126060 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4687 12:20:51.129821 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4688 12:20:51.133284 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4689 12:20:51.136310 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4690 12:20:51.139484 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4691 12:20:51.146484 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4692 12:20:51.149711 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4693 12:20:51.152732 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4694 12:20:51.156075 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4695 12:20:51.162940 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4696 12:20:51.166053 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4697 12:20:51.169593 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4698 12:20:51.169694 ==
4699 12:20:51.172391 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 12:20:51.179448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 12:20:51.179533 ==
4702 12:20:51.179597 DQS Delay:
4703 12:20:51.179655 DQS0 = 0, DQS1 = 0
4704 12:20:51.182914 DQM Delay:
4705 12:20:51.182993 DQM0 = 36, DQM1 = 29
4706 12:20:51.185882 DQ Delay:
4707 12:20:51.189548 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4708 12:20:51.192480 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4709 12:20:51.195830 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4710 12:20:51.199225 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4711 12:20:51.199337
4712 12:20:51.199450
4713 12:20:51.199530 ==
4714 12:20:51.202803 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 12:20:51.205671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 12:20:51.205751 ==
4717 12:20:51.205814
4718 12:20:51.205872
4719 12:20:51.209170 TX Vref Scan disable
4720 12:20:51.209270 == TX Byte 0 ==
4721 12:20:51.215460 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4722 12:20:51.219194 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4723 12:20:51.219294 == TX Byte 1 ==
4724 12:20:51.225787 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4725 12:20:51.229175 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4726 12:20:51.229249 ==
4727 12:20:51.232009 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 12:20:51.235688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 12:20:51.235764 ==
4730 12:20:51.235828
4731 12:20:51.235886
4732 12:20:51.238647 TX Vref Scan disable
4733 12:20:51.242276 == TX Byte 0 ==
4734 12:20:51.245419 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4735 12:20:51.252086 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4736 12:20:51.252167 == TX Byte 1 ==
4737 12:20:51.255617 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4738 12:20:51.262313 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4739 12:20:51.262393
4740 12:20:51.262455 [DATLAT]
4741 12:20:51.262513 Freq=600, CH1 RK1
4742 12:20:51.262571
4743 12:20:51.265317 DATLAT Default: 0x9
4744 12:20:51.265396 0, 0xFFFF, sum = 0
4745 12:20:51.268796 1, 0xFFFF, sum = 0
4746 12:20:51.271770 2, 0xFFFF, sum = 0
4747 12:20:51.271850 3, 0xFFFF, sum = 0
4748 12:20:51.275232 4, 0xFFFF, sum = 0
4749 12:20:51.275329 5, 0xFFFF, sum = 0
4750 12:20:51.279154 6, 0xFFFF, sum = 0
4751 12:20:51.279251 7, 0xFFFF, sum = 0
4752 12:20:51.281660 8, 0x0, sum = 1
4753 12:20:51.281741 9, 0x0, sum = 2
4754 12:20:51.285232 10, 0x0, sum = 3
4755 12:20:51.285312 11, 0x0, sum = 4
4756 12:20:51.285375 best_step = 9
4757 12:20:51.285433
4758 12:20:51.288531 ==
4759 12:20:51.288611 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 12:20:51.295312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 12:20:51.295449 ==
4762 12:20:51.295513 RX Vref Scan: 0
4763 12:20:51.295571
4764 12:20:51.298284 RX Vref 0 -> 0, step: 1
4765 12:20:51.298363
4766 12:20:51.301871 RX Delay -195 -> 252, step: 8
4767 12:20:51.308137 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4768 12:20:51.311918 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4769 12:20:51.314911 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4770 12:20:51.318385 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4771 12:20:51.322189 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4772 12:20:51.328477 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4773 12:20:51.331655 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4774 12:20:51.334649 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4775 12:20:51.337961 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4776 12:20:51.344855 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4777 12:20:51.347983 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4778 12:20:51.351679 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4779 12:20:51.354677 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4780 12:20:51.361101 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4781 12:20:51.364871 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4782 12:20:51.367665 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4783 12:20:51.367744 ==
4784 12:20:51.371282 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 12:20:51.374661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 12:20:51.374766 ==
4787 12:20:51.377625 DQS Delay:
4788 12:20:51.377720 DQS0 = 0, DQS1 = 0
4789 12:20:51.381104 DQM Delay:
4790 12:20:51.381183 DQM0 = 36, DQM1 = 29
4791 12:20:51.381245 DQ Delay:
4792 12:20:51.384849 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4793 12:20:51.387691 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4794 12:20:51.391277 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4795 12:20:51.394135 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4796 12:20:51.394228
4797 12:20:51.394290
4798 12:20:51.404373 [DQSOSCAuto] RK1, (LSB)MR18= 0x3857, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4799 12:20:51.407443 CH1 RK1: MR19=808, MR18=3857
4800 12:20:51.414453 CH1_RK1: MR19=0x808, MR18=0x3857, DQSOSC=393, MR23=63, INC=169, DEC=113
4801 12:20:51.417712 [RxdqsGatingPostProcess] freq 600
4802 12:20:51.420623 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4803 12:20:51.424174 Pre-setting of DQS Precalculation
4804 12:20:51.430945 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4805 12:20:51.437024 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4806 12:20:51.443905 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4807 12:20:51.443985
4808 12:20:51.444048
4809 12:20:51.447559 [Calibration Summary] 1200 Mbps
4810 12:20:51.447639 CH 0, Rank 0
4811 12:20:51.450384 SW Impedance : PASS
4812 12:20:51.453907 DUTY Scan : NO K
4813 12:20:51.453986 ZQ Calibration : PASS
4814 12:20:51.457234 Jitter Meter : NO K
4815 12:20:51.457313 CBT Training : PASS
4816 12:20:51.460810 Write leveling : PASS
4817 12:20:51.463997 RX DQS gating : PASS
4818 12:20:51.464077 RX DQ/DQS(RDDQC) : PASS
4819 12:20:51.467412 TX DQ/DQS : PASS
4820 12:20:51.470438 RX DATLAT : PASS
4821 12:20:51.470517 RX DQ/DQS(Engine): PASS
4822 12:20:51.473829 TX OE : NO K
4823 12:20:51.473908 All Pass.
4824 12:20:51.473971
4825 12:20:51.477088 CH 0, Rank 1
4826 12:20:51.477167 SW Impedance : PASS
4827 12:20:51.480310 DUTY Scan : NO K
4828 12:20:51.483844 ZQ Calibration : PASS
4829 12:20:51.483923 Jitter Meter : NO K
4830 12:20:51.486836 CBT Training : PASS
4831 12:20:51.490260 Write leveling : PASS
4832 12:20:51.490340 RX DQS gating : PASS
4833 12:20:51.493721 RX DQ/DQS(RDDQC) : PASS
4834 12:20:51.496755 TX DQ/DQS : PASS
4835 12:20:51.496835 RX DATLAT : PASS
4836 12:20:51.500266 RX DQ/DQS(Engine): PASS
4837 12:20:51.503326 TX OE : NO K
4838 12:20:51.503441 All Pass.
4839 12:20:51.503505
4840 12:20:51.503562 CH 1, Rank 0
4841 12:20:51.506581 SW Impedance : PASS
4842 12:20:51.509872 DUTY Scan : NO K
4843 12:20:51.509951 ZQ Calibration : PASS
4844 12:20:51.513467 Jitter Meter : NO K
4845 12:20:51.516853 CBT Training : PASS
4846 12:20:51.516932 Write leveling : PASS
4847 12:20:51.519732 RX DQS gating : PASS
4848 12:20:51.519812 RX DQ/DQS(RDDQC) : PASS
4849 12:20:51.523143 TX DQ/DQS : PASS
4850 12:20:51.526825 RX DATLAT : PASS
4851 12:20:51.526927 RX DQ/DQS(Engine): PASS
4852 12:20:51.530097 TX OE : NO K
4853 12:20:51.530176 All Pass.
4854 12:20:51.530238
4855 12:20:51.533238 CH 1, Rank 1
4856 12:20:51.533318 SW Impedance : PASS
4857 12:20:51.536474 DUTY Scan : NO K
4858 12:20:51.540228 ZQ Calibration : PASS
4859 12:20:51.540307 Jitter Meter : NO K
4860 12:20:51.543284 CBT Training : PASS
4861 12:20:51.546704 Write leveling : PASS
4862 12:20:51.546784 RX DQS gating : PASS
4863 12:20:51.549991 RX DQ/DQS(RDDQC) : PASS
4864 12:20:51.552999 TX DQ/DQS : PASS
4865 12:20:51.553078 RX DATLAT : PASS
4866 12:20:51.556471 RX DQ/DQS(Engine): PASS
4867 12:20:51.560119 TX OE : NO K
4868 12:20:51.560199 All Pass.
4869 12:20:51.560260
4870 12:20:51.560317 DramC Write-DBI off
4871 12:20:51.562995 PER_BANK_REFRESH: Hybrid Mode
4872 12:20:51.566485 TX_TRACKING: ON
4873 12:20:51.572836 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4874 12:20:51.576359 [FAST_K] Save calibration result to emmc
4875 12:20:51.583065 dramc_set_vcore_voltage set vcore to 662500
4876 12:20:51.583145 Read voltage for 933, 3
4877 12:20:51.586411 Vio18 = 0
4878 12:20:51.586490 Vcore = 662500
4879 12:20:51.586552 Vdram = 0
4880 12:20:51.589494 Vddq = 0
4881 12:20:51.589612 Vmddr = 0
4882 12:20:51.593135 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4883 12:20:51.599929 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4884 12:20:51.603135 MEM_TYPE=3, freq_sel=17
4885 12:20:51.606367 sv_algorithm_assistance_LP4_1600
4886 12:20:51.609657 ============ PULL DRAM RESETB DOWN ============
4887 12:20:51.613029 ========== PULL DRAM RESETB DOWN end =========
4888 12:20:51.616250 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4889 12:20:51.619527 ===================================
4890 12:20:51.622814 LPDDR4 DRAM CONFIGURATION
4891 12:20:51.626351 ===================================
4892 12:20:51.629211 EX_ROW_EN[0] = 0x0
4893 12:20:51.629291 EX_ROW_EN[1] = 0x0
4894 12:20:51.632725 LP4Y_EN = 0x0
4895 12:20:51.632805 WORK_FSP = 0x0
4896 12:20:51.636142 WL = 0x3
4897 12:20:51.636222 RL = 0x3
4898 12:20:51.639288 BL = 0x2
4899 12:20:51.639378 RPST = 0x0
4900 12:20:51.642416 RD_PRE = 0x0
4901 12:20:51.642495 WR_PRE = 0x1
4902 12:20:51.645955 WR_PST = 0x0
4903 12:20:51.649041 DBI_WR = 0x0
4904 12:20:51.649124 DBI_RD = 0x0
4905 12:20:51.652617 OTF = 0x1
4906 12:20:51.656064 ===================================
4907 12:20:51.658967 ===================================
4908 12:20:51.659047 ANA top config
4909 12:20:51.662465 ===================================
4910 12:20:51.665658 DLL_ASYNC_EN = 0
4911 12:20:51.665738 ALL_SLAVE_EN = 1
4912 12:20:51.669365 NEW_RANK_MODE = 1
4913 12:20:51.672128 DLL_IDLE_MODE = 1
4914 12:20:51.675655 LP45_APHY_COMB_EN = 1
4915 12:20:51.679085 TX_ODT_DIS = 1
4916 12:20:51.679164 NEW_8X_MODE = 1
4917 12:20:51.682301 ===================================
4918 12:20:51.686170 ===================================
4919 12:20:51.688777 data_rate = 1866
4920 12:20:51.692290 CKR = 1
4921 12:20:51.695834 DQ_P2S_RATIO = 8
4922 12:20:51.698688 ===================================
4923 12:20:51.702468 CA_P2S_RATIO = 8
4924 12:20:51.705589 DQ_CA_OPEN = 0
4925 12:20:51.705713 DQ_SEMI_OPEN = 0
4926 12:20:51.708792 CA_SEMI_OPEN = 0
4927 12:20:51.712042 CA_FULL_RATE = 0
4928 12:20:51.715325 DQ_CKDIV4_EN = 1
4929 12:20:51.718914 CA_CKDIV4_EN = 1
4930 12:20:51.722388 CA_PREDIV_EN = 0
4931 12:20:51.722469 PH8_DLY = 0
4932 12:20:51.725270 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4933 12:20:51.728673 DQ_AAMCK_DIV = 4
4934 12:20:51.732339 CA_AAMCK_DIV = 4
4935 12:20:51.735256 CA_ADMCK_DIV = 4
4936 12:20:51.738776 DQ_TRACK_CA_EN = 0
4937 12:20:51.738856 CA_PICK = 933
4938 12:20:51.741813 CA_MCKIO = 933
4939 12:20:51.745425 MCKIO_SEMI = 0
4940 12:20:51.748982 PLL_FREQ = 3732
4941 12:20:51.752115 DQ_UI_PI_RATIO = 32
4942 12:20:51.755349 CA_UI_PI_RATIO = 0
4943 12:20:51.758540 ===================================
4944 12:20:51.761719 ===================================
4945 12:20:51.761799 memory_type:LPDDR4
4946 12:20:51.765106 GP_NUM : 10
4947 12:20:51.768807 SRAM_EN : 1
4948 12:20:51.768888 MD32_EN : 0
4949 12:20:51.771880 ===================================
4950 12:20:51.774905 [ANA_INIT] >>>>>>>>>>>>>>
4951 12:20:51.778451 <<<<<< [CONFIGURE PHASE]: ANA_TX
4952 12:20:51.781436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4953 12:20:51.784852 ===================================
4954 12:20:51.788260 data_rate = 1866,PCW = 0X8f00
4955 12:20:51.791797 ===================================
4956 12:20:51.795434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4957 12:20:51.798229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 12:20:51.804824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 12:20:51.808269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4960 12:20:51.814622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4961 12:20:51.818281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4962 12:20:51.818362 [ANA_INIT] flow start
4963 12:20:51.821182 [ANA_INIT] PLL >>>>>>>>
4964 12:20:51.824672 [ANA_INIT] PLL <<<<<<<<
4965 12:20:51.824753 [ANA_INIT] MIDPI >>>>>>>>
4966 12:20:51.827882 [ANA_INIT] MIDPI <<<<<<<<
4967 12:20:51.831548 [ANA_INIT] DLL >>>>>>>>
4968 12:20:51.831632 [ANA_INIT] flow end
4969 12:20:51.837758 ============ LP4 DIFF to SE enter ============
4970 12:20:51.841109 ============ LP4 DIFF to SE exit ============
4971 12:20:51.841190 [ANA_INIT] <<<<<<<<<<<<<
4972 12:20:51.844705 [Flow] Enable top DCM control >>>>>
4973 12:20:51.848580 [Flow] Enable top DCM control <<<<<
4974 12:20:51.851123 Enable DLL master slave shuffle
4975 12:20:51.858174 ==============================================================
4976 12:20:51.861295 Gating Mode config
4977 12:20:51.864441 ==============================================================
4978 12:20:51.867751 Config description:
4979 12:20:51.878052 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4980 12:20:51.884620 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4981 12:20:51.887785 SELPH_MODE 0: By rank 1: By Phase
4982 12:20:51.894426 ==============================================================
4983 12:20:51.897848 GAT_TRACK_EN = 1
4984 12:20:51.901066 RX_GATING_MODE = 2
4985 12:20:51.904332 RX_GATING_TRACK_MODE = 2
4986 12:20:51.904413 SELPH_MODE = 1
4987 12:20:51.907488 PICG_EARLY_EN = 1
4988 12:20:51.910721 VALID_LAT_VALUE = 1
4989 12:20:51.918092 ==============================================================
4990 12:20:51.920784 Enter into Gating configuration >>>>
4991 12:20:51.924578 Exit from Gating configuration <<<<
4992 12:20:51.927191 Enter into DVFS_PRE_config >>>>>
4993 12:20:51.937290 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4994 12:20:51.940871 Exit from DVFS_PRE_config <<<<<
4995 12:20:51.944595 Enter into PICG configuration >>>>
4996 12:20:51.947341 Exit from PICG configuration <<<<
4997 12:20:51.950638 [RX_INPUT] configuration >>>>>
4998 12:20:51.954225 [RX_INPUT] configuration <<<<<
4999 12:20:51.957221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5000 12:20:51.964241 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5001 12:20:51.970301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 12:20:51.976870 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 12:20:51.983899 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5004 12:20:51.987013 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5005 12:20:51.993572 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5006 12:20:51.996893 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5007 12:20:52.000474 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5008 12:20:52.003529 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5009 12:20:52.010291 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5010 12:20:52.013473 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 12:20:52.016499 ===================================
5012 12:20:52.019939 LPDDR4 DRAM CONFIGURATION
5013 12:20:52.023549 ===================================
5014 12:20:52.023630 EX_ROW_EN[0] = 0x0
5015 12:20:52.026471 EX_ROW_EN[1] = 0x0
5016 12:20:52.026552 LP4Y_EN = 0x0
5017 12:20:52.030101 WORK_FSP = 0x0
5018 12:20:52.030182 WL = 0x3
5019 12:20:52.033476 RL = 0x3
5020 12:20:52.033556 BL = 0x2
5021 12:20:52.036875 RPST = 0x0
5022 12:20:52.040086 RD_PRE = 0x0
5023 12:20:52.040167 WR_PRE = 0x1
5024 12:20:52.043108 WR_PST = 0x0
5025 12:20:52.043189 DBI_WR = 0x0
5026 12:20:52.046599 DBI_RD = 0x0
5027 12:20:52.046680 OTF = 0x1
5028 12:20:52.049495 ===================================
5029 12:20:52.053302 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5030 12:20:52.059906 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5031 12:20:52.063246 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 12:20:52.066097 ===================================
5033 12:20:52.069759 LPDDR4 DRAM CONFIGURATION
5034 12:20:52.072760 ===================================
5035 12:20:52.072842 EX_ROW_EN[0] = 0x10
5036 12:20:52.076076 EX_ROW_EN[1] = 0x0
5037 12:20:52.076158 LP4Y_EN = 0x0
5038 12:20:52.079723 WORK_FSP = 0x0
5039 12:20:52.079804 WL = 0x3
5040 12:20:52.082649 RL = 0x3
5041 12:20:52.082728 BL = 0x2
5042 12:20:52.085979 RPST = 0x0
5043 12:20:52.089486 RD_PRE = 0x0
5044 12:20:52.089567 WR_PRE = 0x1
5045 12:20:52.092640 WR_PST = 0x0
5046 12:20:52.092720 DBI_WR = 0x0
5047 12:20:52.095834 DBI_RD = 0x0
5048 12:20:52.095914 OTF = 0x1
5049 12:20:52.099398 ===================================
5050 12:20:52.105525 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5051 12:20:52.109752 nWR fixed to 30
5052 12:20:52.112725 [ModeRegInit_LP4] CH0 RK0
5053 12:20:52.112806 [ModeRegInit_LP4] CH0 RK1
5054 12:20:52.116136 [ModeRegInit_LP4] CH1 RK0
5055 12:20:52.119688 [ModeRegInit_LP4] CH1 RK1
5056 12:20:52.119769 match AC timing 9
5057 12:20:52.126069 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5058 12:20:52.129690 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5059 12:20:52.132597 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5060 12:20:52.139080 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5061 12:20:52.142450 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5062 12:20:52.142531 ==
5063 12:20:52.145852 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 12:20:52.149039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 12:20:52.149120 ==
5066 12:20:52.155678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 12:20:52.162539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5068 12:20:52.165614 [CA 0] Center 38 (8~69) winsize 62
5069 12:20:52.168941 [CA 1] Center 37 (7~68) winsize 62
5070 12:20:52.172396 [CA 2] Center 35 (5~65) winsize 61
5071 12:20:52.175563 [CA 3] Center 35 (5~65) winsize 61
5072 12:20:52.179166 [CA 4] Center 34 (4~65) winsize 62
5073 12:20:52.182354 [CA 5] Center 33 (3~64) winsize 62
5074 12:20:52.182435
5075 12:20:52.185680 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5076 12:20:52.185761
5077 12:20:52.189165 [CATrainingPosCal] consider 1 rank data
5078 12:20:52.192002 u2DelayCellTimex100 = 270/100 ps
5079 12:20:52.195698 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5080 12:20:52.198820 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5081 12:20:52.201910 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5082 12:20:52.205610 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5083 12:20:52.212217 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5084 12:20:52.215506 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5085 12:20:52.215587
5086 12:20:52.218487 CA PerBit enable=1, Macro0, CA PI delay=33
5087 12:20:52.218568
5088 12:20:52.221930 [CBTSetCACLKResult] CA Dly = 33
5089 12:20:52.222011 CS Dly: 7 (0~38)
5090 12:20:52.222075 ==
5091 12:20:52.225633 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 12:20:52.231958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 12:20:52.232039 ==
5094 12:20:52.234966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 12:20:52.241565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5096 12:20:52.245001 [CA 0] Center 38 (8~69) winsize 62
5097 12:20:52.248444 [CA 1] Center 38 (7~69) winsize 63
5098 12:20:52.251896 [CA 2] Center 35 (5~66) winsize 62
5099 12:20:52.255153 [CA 3] Center 35 (5~66) winsize 62
5100 12:20:52.258960 [CA 4] Center 34 (3~65) winsize 63
5101 12:20:52.261903 [CA 5] Center 33 (3~64) winsize 62
5102 12:20:52.261987
5103 12:20:52.265259 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5104 12:20:52.265340
5105 12:20:52.268165 [CATrainingPosCal] consider 2 rank data
5106 12:20:52.271696 u2DelayCellTimex100 = 270/100 ps
5107 12:20:52.274806 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5108 12:20:52.278520 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5109 12:20:52.284885 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5110 12:20:52.288230 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5111 12:20:52.291549 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5112 12:20:52.294792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5113 12:20:52.294873
5114 12:20:52.297793 CA PerBit enable=1, Macro0, CA PI delay=33
5115 12:20:52.297900
5116 12:20:52.301476 [CBTSetCACLKResult] CA Dly = 33
5117 12:20:52.301557 CS Dly: 7 (0~38)
5118 12:20:52.304916
5119 12:20:52.307785 ----->DramcWriteLeveling(PI) begin...
5120 12:20:52.307867 ==
5121 12:20:52.311235 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 12:20:52.314895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 12:20:52.314976 ==
5124 12:20:52.317752 Write leveling (Byte 0): 33 => 33
5125 12:20:52.321312 Write leveling (Byte 1): 33 => 33
5126 12:20:52.324418 DramcWriteLeveling(PI) end<-----
5127 12:20:52.324499
5128 12:20:52.324562 ==
5129 12:20:52.327683 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 12:20:52.331234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 12:20:52.331340 ==
5132 12:20:52.334578 [Gating] SW mode calibration
5133 12:20:52.341357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5134 12:20:52.348064 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5135 12:20:52.351257 0 14 0 | B1->B0 | 2322 2c2c | 1 1 | (0 0) (1 1)
5136 12:20:52.354199 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5137 12:20:52.361204 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 12:20:52.364260 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 12:20:52.368016 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 12:20:52.374251 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 12:20:52.377633 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 12:20:52.380823 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5143 12:20:52.387326 0 15 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
5144 12:20:52.390723 0 15 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5145 12:20:52.394090 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 12:20:52.400605 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 12:20:52.404070 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 12:20:52.407423 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 12:20:52.413719 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 12:20:52.417160 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 12:20:52.420413 1 0 0 | B1->B0 | 2727 3d3d | 0 0 | (0 0) (0 0)
5152 12:20:52.427283 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5153 12:20:52.430713 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 12:20:52.433789 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 12:20:52.440381 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 12:20:52.443708 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 12:20:52.446917 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 12:20:52.453675 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 12:20:52.457108 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5160 12:20:52.460140 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5161 12:20:52.467072 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:20:52.470355 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:20:52.473808 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:20:52.477020 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:20:52.483543 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:20:52.486680 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:20:52.490122 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 12:20:52.497039 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 12:20:52.499982 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 12:20:52.503399 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 12:20:52.509907 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 12:20:52.513717 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 12:20:52.516866 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 12:20:52.523143 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5175 12:20:52.526582 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5176 12:20:52.529580 Total UI for P1: 0, mck2ui 16
5177 12:20:52.533028 best dqsien dly found for B0: ( 1, 2, 28)
5178 12:20:52.536639 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5179 12:20:52.543233 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 12:20:52.543341 Total UI for P1: 0, mck2ui 16
5181 12:20:52.549909 best dqsien dly found for B1: ( 1, 3, 4)
5182 12:20:52.553124 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5183 12:20:52.556346 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5184 12:20:52.556427
5185 12:20:52.559467 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5186 12:20:52.563190 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5187 12:20:52.566031 [Gating] SW calibration Done
5188 12:20:52.566112 ==
5189 12:20:52.569989 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 12:20:52.573150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 12:20:52.573231 ==
5192 12:20:52.576038 RX Vref Scan: 0
5193 12:20:52.576135
5194 12:20:52.576231 RX Vref 0 -> 0, step: 1
5195 12:20:52.576307
5196 12:20:52.579747 RX Delay -80 -> 252, step: 8
5197 12:20:52.582683 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5198 12:20:52.589696 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5199 12:20:52.592928 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5200 12:20:52.596101 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5201 12:20:52.599292 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5202 12:20:52.602627 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5203 12:20:52.606212 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5204 12:20:52.612900 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5205 12:20:52.615723 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5206 12:20:52.619601 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5207 12:20:52.622475 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5208 12:20:52.625624 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5209 12:20:52.632312 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5210 12:20:52.635949 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5211 12:20:52.638986 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5212 12:20:52.642391 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5213 12:20:52.642472 ==
5214 12:20:52.645847 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 12:20:52.652175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 12:20:52.652256 ==
5217 12:20:52.652321 DQS Delay:
5218 12:20:52.652380 DQS0 = 0, DQS1 = 0
5219 12:20:52.655576 DQM Delay:
5220 12:20:52.655656 DQM0 = 94, DQM1 = 83
5221 12:20:52.659252 DQ Delay:
5222 12:20:52.662146 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5223 12:20:52.665577 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5224 12:20:52.665658 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5225 12:20:52.672257 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5226 12:20:52.672338
5227 12:20:52.672401
5228 12:20:52.672459 ==
5229 12:20:52.675355 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 12:20:52.678850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 12:20:52.678931 ==
5232 12:20:52.678995
5233 12:20:52.679053
5234 12:20:52.682408 TX Vref Scan disable
5235 12:20:52.682489 == TX Byte 0 ==
5236 12:20:52.688982 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5237 12:20:52.692209 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5238 12:20:52.692291 == TX Byte 1 ==
5239 12:20:52.698765 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5240 12:20:52.702372 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5241 12:20:52.702453 ==
5242 12:20:52.705987 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 12:20:52.709276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 12:20:52.709357 ==
5245 12:20:52.709420
5246 12:20:52.709479
5247 12:20:52.711963 TX Vref Scan disable
5248 12:20:52.715312 == TX Byte 0 ==
5249 12:20:52.719096 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5250 12:20:52.721996 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5251 12:20:52.725483 == TX Byte 1 ==
5252 12:20:52.728925 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5253 12:20:52.732303 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5254 12:20:52.732384
5255 12:20:52.735407 [DATLAT]
5256 12:20:52.735488 Freq=933, CH0 RK0
5257 12:20:52.735552
5258 12:20:52.738930 DATLAT Default: 0xd
5259 12:20:52.739011 0, 0xFFFF, sum = 0
5260 12:20:52.742145 1, 0xFFFF, sum = 0
5261 12:20:52.742226 2, 0xFFFF, sum = 0
5262 12:20:52.745046 3, 0xFFFF, sum = 0
5263 12:20:52.745128 4, 0xFFFF, sum = 0
5264 12:20:52.748626 5, 0xFFFF, sum = 0
5265 12:20:52.748708 6, 0xFFFF, sum = 0
5266 12:20:52.751778 7, 0xFFFF, sum = 0
5267 12:20:52.751860 8, 0xFFFF, sum = 0
5268 12:20:52.755103 9, 0xFFFF, sum = 0
5269 12:20:52.755185 10, 0x0, sum = 1
5270 12:20:52.758351 11, 0x0, sum = 2
5271 12:20:52.758432 12, 0x0, sum = 3
5272 12:20:52.761976 13, 0x0, sum = 4
5273 12:20:52.762058 best_step = 11
5274 12:20:52.762121
5275 12:20:52.762180 ==
5276 12:20:52.765174 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 12:20:52.771864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 12:20:52.771946 ==
5279 12:20:52.772010 RX Vref Scan: 1
5280 12:20:52.772069
5281 12:20:52.775284 RX Vref 0 -> 0, step: 1
5282 12:20:52.775365
5283 12:20:52.778454 RX Delay -69 -> 252, step: 4
5284 12:20:52.778535
5285 12:20:52.781537 Set Vref, RX VrefLevel [Byte0]: 63
5286 12:20:52.784826 [Byte1]: 47
5287 12:20:52.784907
5288 12:20:52.788249 Final RX Vref Byte 0 = 63 to rank0
5289 12:20:52.791967 Final RX Vref Byte 1 = 47 to rank0
5290 12:20:52.794887 Final RX Vref Byte 0 = 63 to rank1
5291 12:20:52.798314 Final RX Vref Byte 1 = 47 to rank1==
5292 12:20:52.801605 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 12:20:52.805036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 12:20:52.805143 ==
5295 12:20:52.808086 DQS Delay:
5296 12:20:52.808166 DQS0 = 0, DQS1 = 0
5297 12:20:52.811848 DQM Delay:
5298 12:20:52.811928 DQM0 = 95, DQM1 = 82
5299 12:20:52.811991 DQ Delay:
5300 12:20:52.814670 DQ0 =92, DQ1 =98, DQ2 =92, DQ3 =92
5301 12:20:52.818110 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =108
5302 12:20:52.821602 DQ8 =74, DQ9 =70, DQ10 =84, DQ11 =76
5303 12:20:52.824945 DQ12 =86, DQ13 =86, DQ14 =92, DQ15 =88
5304 12:20:52.825025
5305 12:20:52.825087
5306 12:20:52.834882 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5307 12:20:52.838310 CH0 RK0: MR19=505, MR18=1212
5308 12:20:52.844688 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5309 12:20:52.844769
5310 12:20:52.847902 ----->DramcWriteLeveling(PI) begin...
5311 12:20:52.847984 ==
5312 12:20:52.851315 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 12:20:52.854510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 12:20:52.854591 ==
5315 12:20:52.857807 Write leveling (Byte 0): 31 => 31
5316 12:20:52.861224 Write leveling (Byte 1): 28 => 28
5317 12:20:52.864659 DramcWriteLeveling(PI) end<-----
5318 12:20:52.864739
5319 12:20:52.864802 ==
5320 12:20:52.867886 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 12:20:52.871110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 12:20:52.871216 ==
5323 12:20:52.874382 [Gating] SW mode calibration
5324 12:20:52.881208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5325 12:20:52.887586 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5326 12:20:52.891100 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5327 12:20:52.894318 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 12:20:52.901154 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 12:20:52.904414 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 12:20:52.907491 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 12:20:52.914071 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 12:20:52.917538 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 12:20:52.920857 0 14 28 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
5334 12:20:52.927732 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5335 12:20:52.930679 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 12:20:52.934471 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 12:20:52.940871 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 12:20:52.944368 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 12:20:52.947158 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 12:20:52.953806 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 12:20:52.957134 0 15 28 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5342 12:20:52.960740 1 0 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5343 12:20:52.967313 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 12:20:52.970343 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 12:20:52.973852 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 12:20:52.980431 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 12:20:52.983921 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 12:20:52.987311 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 12:20:52.993740 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5350 12:20:52.996885 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5351 12:20:53.000441 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 12:20:53.007032 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:20:53.010363 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:20:53.013790 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:20:53.017177 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:20:53.023561 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 12:20:53.026640 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 12:20:53.029962 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 12:20:53.036905 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 12:20:53.040456 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 12:20:53.043322 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 12:20:53.050516 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 12:20:53.053436 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 12:20:53.056798 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 12:20:53.063318 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 12:20:53.066550 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5367 12:20:53.070131 Total UI for P1: 0, mck2ui 16
5368 12:20:53.073736 best dqsien dly found for B0: ( 1, 2, 30)
5369 12:20:53.076631 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 12:20:53.080080 Total UI for P1: 0, mck2ui 16
5371 12:20:53.083311 best dqsien dly found for B1: ( 1, 3, 0)
5372 12:20:53.086593 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5373 12:20:53.090106 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5374 12:20:53.090187
5375 12:20:53.096663 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5376 12:20:53.099873 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5377 12:20:53.099955 [Gating] SW calibration Done
5378 12:20:53.103265 ==
5379 12:20:53.106473 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 12:20:53.109939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 12:20:53.110020 ==
5382 12:20:53.110084 RX Vref Scan: 0
5383 12:20:53.110143
5384 12:20:53.113054 RX Vref 0 -> 0, step: 1
5385 12:20:53.113135
5386 12:20:53.116239 RX Delay -80 -> 252, step: 8
5387 12:20:53.119783 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5388 12:20:53.123086 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5389 12:20:53.126507 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5390 12:20:53.132955 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5391 12:20:53.136275 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5392 12:20:53.139733 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5393 12:20:53.142793 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5394 12:20:53.146022 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5395 12:20:53.152577 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5396 12:20:53.156164 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5397 12:20:53.159108 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5398 12:20:53.162729 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5399 12:20:53.165556 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5400 12:20:53.172129 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5401 12:20:53.175332 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5402 12:20:53.178888 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5403 12:20:53.178968 ==
5404 12:20:53.182703 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 12:20:53.185763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 12:20:53.188791 ==
5407 12:20:53.188873 DQS Delay:
5408 12:20:53.188936 DQS0 = 0, DQS1 = 0
5409 12:20:53.192673 DQM Delay:
5410 12:20:53.192753 DQM0 = 92, DQM1 = 81
5411 12:20:53.196139 DQ Delay:
5412 12:20:53.196221 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5413 12:20:53.198738 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5414 12:20:53.202209 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =75
5415 12:20:53.205749 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5416 12:20:53.208617
5417 12:20:53.208697
5418 12:20:53.208761 ==
5419 12:20:53.211817 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 12:20:53.215275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 12:20:53.215388 ==
5422 12:20:53.215455
5423 12:20:53.215514
5424 12:20:53.218780 TX Vref Scan disable
5425 12:20:53.218861 == TX Byte 0 ==
5426 12:20:53.225243 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5427 12:20:53.229028 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5428 12:20:53.229110 == TX Byte 1 ==
5429 12:20:53.235206 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5430 12:20:53.238555 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5431 12:20:53.238636 ==
5432 12:20:53.241838 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 12:20:53.245221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 12:20:53.245313 ==
5435 12:20:53.245379
5436 12:20:53.245438
5437 12:20:53.248589 TX Vref Scan disable
5438 12:20:53.251775 == TX Byte 0 ==
5439 12:20:53.255327 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5440 12:20:53.258183 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5441 12:20:53.261638 == TX Byte 1 ==
5442 12:20:53.264873 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5443 12:20:53.268492 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5444 12:20:53.268598
5445 12:20:53.271345 [DATLAT]
5446 12:20:53.271468 Freq=933, CH0 RK1
5447 12:20:53.271533
5448 12:20:53.274898 DATLAT Default: 0xb
5449 12:20:53.274999 0, 0xFFFF, sum = 0
5450 12:20:53.278238 1, 0xFFFF, sum = 0
5451 12:20:53.278342 2, 0xFFFF, sum = 0
5452 12:20:53.281505 3, 0xFFFF, sum = 0
5453 12:20:53.281622 4, 0xFFFF, sum = 0
5454 12:20:53.284847 5, 0xFFFF, sum = 0
5455 12:20:53.284948 6, 0xFFFF, sum = 0
5456 12:20:53.288354 7, 0xFFFF, sum = 0
5457 12:20:53.288428 8, 0xFFFF, sum = 0
5458 12:20:53.291265 9, 0xFFFF, sum = 0
5459 12:20:53.291363 10, 0x0, sum = 1
5460 12:20:53.294836 11, 0x0, sum = 2
5461 12:20:53.294933 12, 0x0, sum = 3
5462 12:20:53.297940 13, 0x0, sum = 4
5463 12:20:53.298037 best_step = 11
5464 12:20:53.298200
5465 12:20:53.298300 ==
5466 12:20:53.301419 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 12:20:53.307959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 12:20:53.308062 ==
5469 12:20:53.308161 RX Vref Scan: 0
5470 12:20:53.308253
5471 12:20:53.311467 RX Vref 0 -> 0, step: 1
5472 12:20:53.311543
5473 12:20:53.314883 RX Delay -77 -> 252, step: 4
5474 12:20:53.317914 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5475 12:20:53.324442 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5476 12:20:53.327700 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5477 12:20:53.331321 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5478 12:20:53.334651 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5479 12:20:53.337958 iDelay=199, Bit 5, Center 78 (-13 ~ 170) 184
5480 12:20:53.341227 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5481 12:20:53.347657 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5482 12:20:53.351204 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5483 12:20:53.354073 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5484 12:20:53.357439 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5485 12:20:53.361119 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5486 12:20:53.367680 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5487 12:20:53.370800 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5488 12:20:53.374011 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5489 12:20:53.377578 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5490 12:20:53.377660 ==
5491 12:20:53.381023 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 12:20:53.387595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 12:20:53.387680 ==
5494 12:20:53.387743 DQS Delay:
5495 12:20:53.387801 DQS0 = 0, DQS1 = 0
5496 12:20:53.390700 DQM Delay:
5497 12:20:53.390779 DQM0 = 92, DQM1 = 84
5498 12:20:53.394171 DQ Delay:
5499 12:20:53.397514 DQ0 =88, DQ1 =94, DQ2 =86, DQ3 =90
5500 12:20:53.400655 DQ4 =90, DQ5 =78, DQ6 =106, DQ7 =104
5501 12:20:53.404188 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5502 12:20:53.407070 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =92
5503 12:20:53.407149
5504 12:20:53.407210
5505 12:20:53.414085 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5506 12:20:53.417344 CH0 RK1: MR19=505, MR18=2E0F
5507 12:20:53.423583 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5508 12:20:53.427055 [RxdqsGatingPostProcess] freq 933
5509 12:20:53.430424 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5510 12:20:53.433770 best DQS0 dly(2T, 0.5T) = (0, 10)
5511 12:20:53.436921 best DQS1 dly(2T, 0.5T) = (0, 11)
5512 12:20:53.440301 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5513 12:20:53.443627 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5514 12:20:53.446959 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 12:20:53.450272 best DQS1 dly(2T, 0.5T) = (0, 11)
5516 12:20:53.453756 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 12:20:53.457159 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5518 12:20:53.460092 Pre-setting of DQS Precalculation
5519 12:20:53.463479 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5520 12:20:53.463558 ==
5521 12:20:53.466820 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 12:20:53.473163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 12:20:53.473278 ==
5524 12:20:53.476816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 12:20:53.483250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 12:20:53.486796 [CA 0] Center 36 (7~66) winsize 60
5527 12:20:53.490041 [CA 1] Center 37 (7~67) winsize 61
5528 12:20:53.493393 [CA 2] Center 34 (5~64) winsize 60
5529 12:20:53.496625 [CA 3] Center 34 (5~64) winsize 60
5530 12:20:53.499856 [CA 4] Center 34 (5~64) winsize 60
5531 12:20:53.503320 [CA 5] Center 33 (4~63) winsize 60
5532 12:20:53.503440
5533 12:20:53.506986 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 12:20:53.507070
5535 12:20:53.509854 [CATrainingPosCal] consider 1 rank data
5536 12:20:53.513304 u2DelayCellTimex100 = 270/100 ps
5537 12:20:53.516898 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5538 12:20:53.520591 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5539 12:20:53.526446 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5540 12:20:53.529944 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5541 12:20:53.533573 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5542 12:20:53.536912 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5543 12:20:53.536995
5544 12:20:53.539784 CA PerBit enable=1, Macro0, CA PI delay=33
5545 12:20:53.539867
5546 12:20:53.543375 [CBTSetCACLKResult] CA Dly = 33
5547 12:20:53.543491 CS Dly: 6 (0~37)
5548 12:20:53.546346 ==
5549 12:20:53.550087 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 12:20:53.553408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 12:20:53.553490 ==
5552 12:20:53.556780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 12:20:53.563199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5554 12:20:53.566617 [CA 0] Center 37 (7~67) winsize 61
5555 12:20:53.570505 [CA 1] Center 37 (7~68) winsize 62
5556 12:20:53.573640 [CA 2] Center 35 (5~65) winsize 61
5557 12:20:53.576834 [CA 3] Center 34 (4~64) winsize 61
5558 12:20:53.580081 [CA 4] Center 34 (5~64) winsize 60
5559 12:20:53.583508 [CA 5] Center 33 (3~64) winsize 62
5560 12:20:53.583589
5561 12:20:53.586877 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5562 12:20:53.586959
5563 12:20:53.589703 [CATrainingPosCal] consider 2 rank data
5564 12:20:53.593285 u2DelayCellTimex100 = 270/100 ps
5565 12:20:53.596227 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5566 12:20:53.603268 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5567 12:20:53.606265 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5568 12:20:53.609635 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5569 12:20:53.613276 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5570 12:20:53.616365 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5571 12:20:53.616446
5572 12:20:53.619749 CA PerBit enable=1, Macro0, CA PI delay=33
5573 12:20:53.619831
5574 12:20:53.623260 [CBTSetCACLKResult] CA Dly = 33
5575 12:20:53.626580 CS Dly: 7 (0~39)
5576 12:20:53.626661
5577 12:20:53.629982 ----->DramcWriteLeveling(PI) begin...
5578 12:20:53.630085 ==
5579 12:20:53.633066 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 12:20:53.636378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 12:20:53.636461 ==
5582 12:20:53.639491 Write leveling (Byte 0): 28 => 28
5583 12:20:53.642765 Write leveling (Byte 1): 30 => 30
5584 12:20:53.646308 DramcWriteLeveling(PI) end<-----
5585 12:20:53.646390
5586 12:20:53.646473 ==
5587 12:20:53.649825 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 12:20:53.652964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 12:20:53.653047 ==
5590 12:20:53.656071 [Gating] SW mode calibration
5591 12:20:53.662826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 12:20:53.669365 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5593 12:20:53.672958 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5594 12:20:53.675829 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 12:20:53.682630 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 12:20:53.686507 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 12:20:53.689324 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 12:20:53.695888 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 12:20:53.699375 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 12:20:53.702380 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
5601 12:20:53.708765 0 15 0 | B1->B0 | 2a2a 2d2d | 1 1 | (1 0) (1 0)
5602 12:20:53.712342 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 12:20:53.715339 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 12:20:53.722486 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 12:20:53.725716 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 12:20:53.728879 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 12:20:53.735916 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 12:20:53.738621 0 15 28 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
5609 12:20:53.742258 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 12:20:53.748590 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 12:20:53.751826 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 12:20:53.755576 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:20:53.761853 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 12:20:53.765284 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 12:20:53.768226 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 12:20:53.775477 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5617 12:20:53.778143 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5618 12:20:53.781440 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:20:53.788182 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:20:53.791649 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:20:53.794735 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:20:53.801232 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:20:53.804696 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:20:53.807719 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 12:20:53.814568 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:20:53.817775 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:20:53.821304 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:20:53.827889 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 12:20:53.831482 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:20:53.834330 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 12:20:53.841239 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 12:20:53.844202 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 12:20:53.848085 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 12:20:53.850849 Total UI for P1: 0, mck2ui 16
5635 12:20:53.854586 best dqsien dly found for B0: ( 1, 2, 30)
5636 12:20:53.857644 Total UI for P1: 0, mck2ui 16
5637 12:20:53.860747 best dqsien dly found for B1: ( 1, 2, 30)
5638 12:20:53.863970 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5639 12:20:53.867121 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5640 12:20:53.867204
5641 12:20:53.871150 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5642 12:20:53.877804 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5643 12:20:53.877891 [Gating] SW calibration Done
5644 12:20:53.880707 ==
5645 12:20:53.880788 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 12:20:53.887262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 12:20:53.887404 ==
5648 12:20:53.887488 RX Vref Scan: 0
5649 12:20:53.887549
5650 12:20:53.890616 RX Vref 0 -> 0, step: 1
5651 12:20:53.890695
5652 12:20:53.894055 RX Delay -80 -> 252, step: 8
5653 12:20:53.897615 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5654 12:20:53.900838 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5655 12:20:53.903802 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5656 12:20:53.910552 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5657 12:20:53.914139 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5658 12:20:53.917015 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5659 12:20:53.920730 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5660 12:20:53.924153 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5661 12:20:53.927057 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5662 12:20:53.933591 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5663 12:20:53.937138 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5664 12:20:53.940508 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5665 12:20:53.943518 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5666 12:20:53.947494 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5667 12:20:53.950430 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5668 12:20:53.956681 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5669 12:20:53.956762 ==
5670 12:20:53.960164 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 12:20:53.963669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 12:20:53.963750 ==
5673 12:20:53.963813 DQS Delay:
5674 12:20:53.966708 DQS0 = 0, DQS1 = 0
5675 12:20:53.966788 DQM Delay:
5676 12:20:53.970420 DQM0 = 95, DQM1 = 90
5677 12:20:53.970500 DQ Delay:
5678 12:20:53.973406 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5679 12:20:53.976792 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5680 12:20:53.980064 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5681 12:20:53.983656 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5682 12:20:53.983737
5683 12:20:53.983799
5684 12:20:53.983856 ==
5685 12:20:53.987016 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 12:20:53.990134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 12:20:53.990215 ==
5688 12:20:53.993345
5689 12:20:53.993424
5690 12:20:53.993537 TX Vref Scan disable
5691 12:20:53.996475 == TX Byte 0 ==
5692 12:20:54.000169 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5693 12:20:54.003231 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5694 12:20:54.007011 == TX Byte 1 ==
5695 12:20:54.010059 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5696 12:20:54.013186 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5697 12:20:54.013271 ==
5698 12:20:54.016627 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 12:20:54.023163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 12:20:54.023245 ==
5701 12:20:54.023308
5702 12:20:54.023367
5703 12:20:54.023461 TX Vref Scan disable
5704 12:20:54.027317 == TX Byte 0 ==
5705 12:20:54.030818 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5706 12:20:54.037982 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5707 12:20:54.038066 == TX Byte 1 ==
5708 12:20:54.041205 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5709 12:20:54.047247 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5710 12:20:54.047328
5711 12:20:54.047413 [DATLAT]
5712 12:20:54.047503 Freq=933, CH1 RK0
5713 12:20:54.047592
5714 12:20:54.050735 DATLAT Default: 0xd
5715 12:20:54.050815 0, 0xFFFF, sum = 0
5716 12:20:54.054264 1, 0xFFFF, sum = 0
5717 12:20:54.054345 2, 0xFFFF, sum = 0
5718 12:20:54.057281 3, 0xFFFF, sum = 0
5719 12:20:54.060861 4, 0xFFFF, sum = 0
5720 12:20:54.060942 5, 0xFFFF, sum = 0
5721 12:20:54.063801 6, 0xFFFF, sum = 0
5722 12:20:54.063881 7, 0xFFFF, sum = 0
5723 12:20:54.067201 8, 0xFFFF, sum = 0
5724 12:20:54.067281 9, 0xFFFF, sum = 0
5725 12:20:54.070813 10, 0x0, sum = 1
5726 12:20:54.070893 11, 0x0, sum = 2
5727 12:20:54.073700 12, 0x0, sum = 3
5728 12:20:54.073780 13, 0x0, sum = 4
5729 12:20:54.073844 best_step = 11
5730 12:20:54.073901
5731 12:20:54.077182 ==
5732 12:20:54.080684 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 12:20:54.083567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 12:20:54.083646 ==
5735 12:20:54.083709 RX Vref Scan: 1
5736 12:20:54.083766
5737 12:20:54.086904 RX Vref 0 -> 0, step: 1
5738 12:20:54.086983
5739 12:20:54.090317 RX Delay -53 -> 252, step: 4
5740 12:20:54.090397
5741 12:20:54.093705 Set Vref, RX VrefLevel [Byte0]: 61
5742 12:20:54.097088 [Byte1]: 49
5743 12:20:54.097168
5744 12:20:54.100560 Final RX Vref Byte 0 = 61 to rank0
5745 12:20:54.103835 Final RX Vref Byte 1 = 49 to rank0
5746 12:20:54.107398 Final RX Vref Byte 0 = 61 to rank1
5747 12:20:54.110131 Final RX Vref Byte 1 = 49 to rank1==
5748 12:20:54.113591 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 12:20:54.116792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 12:20:54.120543 ==
5751 12:20:54.120622 DQS Delay:
5752 12:20:54.120685 DQS0 = 0, DQS1 = 0
5753 12:20:54.123962 DQM Delay:
5754 12:20:54.124040 DQM0 = 95, DQM1 = 87
5755 12:20:54.126965 DQ Delay:
5756 12:20:54.130114 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
5757 12:20:54.133618 DQ4 =94, DQ5 =104, DQ6 =104, DQ7 =92
5758 12:20:54.136545 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =82
5759 12:20:54.140507 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5760 12:20:54.140587
5761 12:20:54.140649
5762 12:20:54.146542 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc04, (MSB)MR19= 0x405, tDQSOscB0 = 420 ps tDQSOscB1 = 423 ps
5763 12:20:54.150492 CH1 RK0: MR19=405, MR18=FC04
5764 12:20:54.156902 CH1_RK0: MR19=0x405, MR18=0xFC04, DQSOSC=420, MR23=63, INC=61, DEC=40
5765 12:20:54.156982
5766 12:20:54.159966 ----->DramcWriteLeveling(PI) begin...
5767 12:20:54.160047 ==
5768 12:20:54.163451 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 12:20:54.166806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 12:20:54.166888 ==
5771 12:20:54.169800 Write leveling (Byte 0): 27 => 27
5772 12:20:54.173245 Write leveling (Byte 1): 28 => 28
5773 12:20:54.176583 DramcWriteLeveling(PI) end<-----
5774 12:20:54.176661
5775 12:20:54.176723 ==
5776 12:20:54.179814 Dram Type= 6, Freq= 0, CH_1, rank 1
5777 12:20:54.183223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 12:20:54.183303 ==
5779 12:20:54.186781 [Gating] SW mode calibration
5780 12:20:54.192885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5781 12:20:54.199648 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5782 12:20:54.203102 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 12:20:54.209801 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 12:20:54.213298 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 12:20:54.216423 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 12:20:54.220030 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 12:20:54.226665 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 12:20:54.230037 0 14 24 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 1)
5789 12:20:54.233010 0 14 28 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (1 0)
5790 12:20:54.239648 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 12:20:54.242977 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 12:20:54.246332 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 12:20:54.252735 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 12:20:54.256285 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 12:20:54.259660 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 12:20:54.266157 0 15 24 | B1->B0 | 2e2d 3333 | 1 1 | (0 0) (0 0)
5797 12:20:54.269275 0 15 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5798 12:20:54.272790 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 12:20:54.279162 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 12:20:54.282336 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 12:20:54.285959 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 12:20:54.292222 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 12:20:54.295696 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 12:20:54.299246 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5805 12:20:54.306117 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5806 12:20:54.309664 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 12:20:54.312185 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:20:54.318677 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:20:54.321900 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:20:54.325210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:20:54.332113 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 12:20:54.335308 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 12:20:54.338825 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 12:20:54.345279 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 12:20:54.348610 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:20:54.352112 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:20:54.358548 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 12:20:54.362330 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 12:20:54.364947 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 12:20:54.371975 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5821 12:20:54.375071 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 12:20:54.378531 Total UI for P1: 0, mck2ui 16
5823 12:20:54.381880 best dqsien dly found for B0: ( 1, 2, 24)
5824 12:20:54.384579 Total UI for P1: 0, mck2ui 16
5825 12:20:54.388075 best dqsien dly found for B1: ( 1, 2, 24)
5826 12:20:54.391341 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5827 12:20:54.394548 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5828 12:20:54.394618
5829 12:20:54.398146 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5830 12:20:54.401798 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5831 12:20:54.404525 [Gating] SW calibration Done
5832 12:20:54.404598 ==
5833 12:20:54.407624 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 12:20:54.414582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 12:20:54.414660 ==
5836 12:20:54.414730 RX Vref Scan: 0
5837 12:20:54.414790
5838 12:20:54.417546 RX Vref 0 -> 0, step: 1
5839 12:20:54.417617
5840 12:20:54.420967 RX Delay -80 -> 252, step: 8
5841 12:20:54.424313 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5842 12:20:54.427625 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5843 12:20:54.430767 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5844 12:20:54.434694 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5845 12:20:54.441281 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5846 12:20:54.444212 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5847 12:20:54.447825 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5848 12:20:54.450675 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5849 12:20:54.454496 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5850 12:20:54.460675 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5851 12:20:54.464267 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5852 12:20:54.467645 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5853 12:20:54.470622 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5854 12:20:54.474052 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5855 12:20:54.477142 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5856 12:20:54.484019 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5857 12:20:54.484107 ==
5858 12:20:54.487449 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 12:20:54.490684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 12:20:54.490764 ==
5861 12:20:54.490828 DQS Delay:
5862 12:20:54.494049 DQS0 = 0, DQS1 = 0
5863 12:20:54.494121 DQM Delay:
5864 12:20:54.496989 DQM0 = 94, DQM1 = 88
5865 12:20:54.497070 DQ Delay:
5866 12:20:54.500314 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =91
5867 12:20:54.503810 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5868 12:20:54.506779 DQ8 =75, DQ9 =75, DQ10 =95, DQ11 =87
5869 12:20:54.510181 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5870 12:20:54.510262
5871 12:20:54.510325
5872 12:20:54.510384 ==
5873 12:20:54.513394 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 12:20:54.517007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 12:20:54.520528 ==
5876 12:20:54.520609
5877 12:20:54.520672
5878 12:20:54.520731 TX Vref Scan disable
5879 12:20:54.523381 == TX Byte 0 ==
5880 12:20:54.526886 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5881 12:20:54.530410 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5882 12:20:54.533219 == TX Byte 1 ==
5883 12:20:54.536963 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5884 12:20:54.540137 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5885 12:20:54.543349 ==
5886 12:20:54.546795 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 12:20:54.549916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 12:20:54.549995 ==
5889 12:20:54.550062
5890 12:20:54.550120
5891 12:20:54.553166 TX Vref Scan disable
5892 12:20:54.553250 == TX Byte 0 ==
5893 12:20:54.560027 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5894 12:20:54.563833 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5895 12:20:54.563911 == TX Byte 1 ==
5896 12:20:54.570063 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5897 12:20:54.573501 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5898 12:20:54.573630
5899 12:20:54.573723 [DATLAT]
5900 12:20:54.576798 Freq=933, CH1 RK1
5901 12:20:54.576911
5902 12:20:54.577002 DATLAT Default: 0xb
5903 12:20:54.580060 0, 0xFFFF, sum = 0
5904 12:20:54.580175 1, 0xFFFF, sum = 0
5905 12:20:54.582982 2, 0xFFFF, sum = 0
5906 12:20:54.583089 3, 0xFFFF, sum = 0
5907 12:20:54.586283 4, 0xFFFF, sum = 0
5908 12:20:54.586406 5, 0xFFFF, sum = 0
5909 12:20:54.589564 6, 0xFFFF, sum = 0
5910 12:20:54.592981 7, 0xFFFF, sum = 0
5911 12:20:54.593093 8, 0xFFFF, sum = 0
5912 12:20:54.596189 9, 0xFFFF, sum = 0
5913 12:20:54.596309 10, 0x0, sum = 1
5914 12:20:54.596410 11, 0x0, sum = 2
5915 12:20:54.599415 12, 0x0, sum = 3
5916 12:20:54.599527 13, 0x0, sum = 4
5917 12:20:54.602814 best_step = 11
5918 12:20:54.602922
5919 12:20:54.603028 ==
5920 12:20:54.606060 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 12:20:54.609763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 12:20:54.609883 ==
5923 12:20:54.612724 RX Vref Scan: 0
5924 12:20:54.612842
5925 12:20:54.612937 RX Vref 0 -> 0, step: 1
5926 12:20:54.615937
5927 12:20:54.616055 RX Delay -69 -> 252, step: 4
5928 12:20:54.623809 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5929 12:20:54.627358 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5930 12:20:54.630261 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5931 12:20:54.633524 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5932 12:20:54.637032 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5933 12:20:54.643541 iDelay=203, Bit 5, Center 104 (11 ~ 198) 188
5934 12:20:54.646980 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5935 12:20:54.650326 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5936 12:20:54.653807 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5937 12:20:54.657076 iDelay=203, Bit 9, Center 80 (-17 ~ 178) 196
5938 12:20:54.660163 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5939 12:20:54.666935 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5940 12:20:54.670245 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5941 12:20:54.673190 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5942 12:20:54.676547 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5943 12:20:54.680225 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5944 12:20:54.683549 ==
5945 12:20:54.683633 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 12:20:54.689966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 12:20:54.690050 ==
5948 12:20:54.690135 DQS Delay:
5949 12:20:54.693355 DQS0 = 0, DQS1 = 0
5950 12:20:54.693437 DQM Delay:
5951 12:20:54.696767 DQM0 = 93, DQM1 = 90
5952 12:20:54.696849 DQ Delay:
5953 12:20:54.699976 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =90
5954 12:20:54.702874 DQ4 =90, DQ5 =104, DQ6 =104, DQ7 =92
5955 12:20:54.706505 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =82
5956 12:20:54.709442 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5957 12:20:54.709525
5958 12:20:54.709609
5959 12:20:54.716263 [DQSOSCAuto] RK1, (LSB)MR18= 0x91d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 419 ps
5960 12:20:54.719750 CH1 RK1: MR19=505, MR18=91D
5961 12:20:54.726281 CH1_RK1: MR19=0x505, MR18=0x91D, DQSOSC=412, MR23=63, INC=63, DEC=42
5962 12:20:54.729439 [RxdqsGatingPostProcess] freq 933
5963 12:20:54.736081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5964 12:20:54.736228 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 12:20:54.739581 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 12:20:54.742564 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 12:20:54.745979 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 12:20:54.749329 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 12:20:54.753085 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 12:20:54.755854 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 12:20:54.759334 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 12:20:54.762703 Pre-setting of DQS Precalculation
5973 12:20:54.769452 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5974 12:20:54.775827 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5975 12:20:54.782503 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5976 12:20:54.782595
5977 12:20:54.782660
5978 12:20:54.786050 [Calibration Summary] 1866 Mbps
5979 12:20:54.786134 CH 0, Rank 0
5980 12:20:54.788963 SW Impedance : PASS
5981 12:20:54.792530 DUTY Scan : NO K
5982 12:20:54.792615 ZQ Calibration : PASS
5983 12:20:54.795507 Jitter Meter : NO K
5984 12:20:54.795607 CBT Training : PASS
5985 12:20:54.798994 Write leveling : PASS
5986 12:20:54.802721 RX DQS gating : PASS
5987 12:20:54.802829 RX DQ/DQS(RDDQC) : PASS
5988 12:20:54.806024 TX DQ/DQS : PASS
5989 12:20:54.809029 RX DATLAT : PASS
5990 12:20:54.809174 RX DQ/DQS(Engine): PASS
5991 12:20:54.812361 TX OE : NO K
5992 12:20:54.812470 All Pass.
5993 12:20:54.812570
5994 12:20:54.815605 CH 0, Rank 1
5995 12:20:54.815712 SW Impedance : PASS
5996 12:20:54.818653 DUTY Scan : NO K
5997 12:20:54.822286 ZQ Calibration : PASS
5998 12:20:54.822396 Jitter Meter : NO K
5999 12:20:54.825847 CBT Training : PASS
6000 12:20:54.828593 Write leveling : PASS
6001 12:20:54.828701 RX DQS gating : PASS
6002 12:20:54.832049 RX DQ/DQS(RDDQC) : PASS
6003 12:20:54.835822 TX DQ/DQS : PASS
6004 12:20:54.835940 RX DATLAT : PASS
6005 12:20:54.838841 RX DQ/DQS(Engine): PASS
6006 12:20:54.842689 TX OE : NO K
6007 12:20:54.842801 All Pass.
6008 12:20:54.842908
6009 12:20:54.843006 CH 1, Rank 0
6010 12:20:54.845183 SW Impedance : PASS
6011 12:20:54.848625 DUTY Scan : NO K
6012 12:20:54.848743 ZQ Calibration : PASS
6013 12:20:54.852161 Jitter Meter : NO K
6014 12:20:54.852275 CBT Training : PASS
6015 12:20:54.855688 Write leveling : PASS
6016 12:20:54.858785 RX DQS gating : PASS
6017 12:20:54.858938 RX DQ/DQS(RDDQC) : PASS
6018 12:20:54.862014 TX DQ/DQS : PASS
6019 12:20:54.865307 RX DATLAT : PASS
6020 12:20:54.865430 RX DQ/DQS(Engine): PASS
6021 12:20:54.869155 TX OE : NO K
6022 12:20:54.869260 All Pass.
6023 12:20:54.869357
6024 12:20:54.872331 CH 1, Rank 1
6025 12:20:54.872437 SW Impedance : PASS
6026 12:20:54.875196 DUTY Scan : NO K
6027 12:20:54.878432 ZQ Calibration : PASS
6028 12:20:54.878551 Jitter Meter : NO K
6029 12:20:54.881784 CBT Training : PASS
6030 12:20:54.885549 Write leveling : PASS
6031 12:20:54.885664 RX DQS gating : PASS
6032 12:20:54.888493 RX DQ/DQS(RDDQC) : PASS
6033 12:20:54.892163 TX DQ/DQS : PASS
6034 12:20:54.892270 RX DATLAT : PASS
6035 12:20:54.895034 RX DQ/DQS(Engine): PASS
6036 12:20:54.895137 TX OE : NO K
6037 12:20:54.898603 All Pass.
6038 12:20:54.898708
6039 12:20:54.898799 DramC Write-DBI off
6040 12:20:54.902257 PER_BANK_REFRESH: Hybrid Mode
6041 12:20:54.905160 TX_TRACKING: ON
6042 12:20:54.911610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6043 12:20:54.915335 [FAST_K] Save calibration result to emmc
6044 12:20:54.922098 dramc_set_vcore_voltage set vcore to 650000
6045 12:20:54.922204 Read voltage for 400, 6
6046 12:20:54.922304 Vio18 = 0
6047 12:20:54.925234 Vcore = 650000
6048 12:20:54.925338 Vdram = 0
6049 12:20:54.925433 Vddq = 0
6050 12:20:54.928606 Vmddr = 0
6051 12:20:54.931628 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6052 12:20:54.938714 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6053 12:20:54.941673 MEM_TYPE=3, freq_sel=20
6054 12:20:54.941786 sv_algorithm_assistance_LP4_800
6055 12:20:54.948424 ============ PULL DRAM RESETB DOWN ============
6056 12:20:54.951824 ========== PULL DRAM RESETB DOWN end =========
6057 12:20:54.955092 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6058 12:20:54.957974 ===================================
6059 12:20:54.961611 LPDDR4 DRAM CONFIGURATION
6060 12:20:54.965202 ===================================
6061 12:20:54.967928 EX_ROW_EN[0] = 0x0
6062 12:20:54.968033 EX_ROW_EN[1] = 0x0
6063 12:20:54.971607 LP4Y_EN = 0x0
6064 12:20:54.971711 WORK_FSP = 0x0
6065 12:20:54.974753 WL = 0x2
6066 12:20:54.974866 RL = 0x2
6067 12:20:54.977895 BL = 0x2
6068 12:20:54.978005 RPST = 0x0
6069 12:20:54.981101 RD_PRE = 0x0
6070 12:20:54.981205 WR_PRE = 0x1
6071 12:20:54.984618 WR_PST = 0x0
6072 12:20:54.984723 DBI_WR = 0x0
6073 12:20:54.987950 DBI_RD = 0x0
6074 12:20:54.991084 OTF = 0x1
6075 12:20:54.991198 ===================================
6076 12:20:54.994493 ===================================
6077 12:20:54.997720 ANA top config
6078 12:20:55.001315 ===================================
6079 12:20:55.004683 DLL_ASYNC_EN = 0
6080 12:20:55.004801 ALL_SLAVE_EN = 1
6081 12:20:55.007766 NEW_RANK_MODE = 1
6082 12:20:55.011266 DLL_IDLE_MODE = 1
6083 12:20:55.014150 LP45_APHY_COMB_EN = 1
6084 12:20:55.017779 TX_ODT_DIS = 1
6085 12:20:55.017885 NEW_8X_MODE = 1
6086 12:20:55.021152 ===================================
6087 12:20:55.024412 ===================================
6088 12:20:55.028071 data_rate = 800
6089 12:20:55.030729 CKR = 1
6090 12:20:55.034243 DQ_P2S_RATIO = 4
6091 12:20:55.037731 ===================================
6092 12:20:55.040615 CA_P2S_RATIO = 4
6093 12:20:55.044211 DQ_CA_OPEN = 0
6094 12:20:55.044291 DQ_SEMI_OPEN = 1
6095 12:20:55.047705 CA_SEMI_OPEN = 1
6096 12:20:55.050865 CA_FULL_RATE = 0
6097 12:20:55.054185 DQ_CKDIV4_EN = 0
6098 12:20:55.057088 CA_CKDIV4_EN = 1
6099 12:20:55.060561 CA_PREDIV_EN = 0
6100 12:20:55.060641 PH8_DLY = 0
6101 12:20:55.064112 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6102 12:20:55.067086 DQ_AAMCK_DIV = 0
6103 12:20:55.070348 CA_AAMCK_DIV = 0
6104 12:20:55.074536 CA_ADMCK_DIV = 4
6105 12:20:55.077041 DQ_TRACK_CA_EN = 0
6106 12:20:55.077150 CA_PICK = 800
6107 12:20:55.080493 CA_MCKIO = 400
6108 12:20:55.083972 MCKIO_SEMI = 400
6109 12:20:55.087083 PLL_FREQ = 3016
6110 12:20:55.090218 DQ_UI_PI_RATIO = 32
6111 12:20:55.094160 CA_UI_PI_RATIO = 32
6112 12:20:55.097059 ===================================
6113 12:20:55.100534 ===================================
6114 12:20:55.103595 memory_type:LPDDR4
6115 12:20:55.103676 GP_NUM : 10
6116 12:20:55.107260 SRAM_EN : 1
6117 12:20:55.107409 MD32_EN : 0
6118 12:20:55.110136 ===================================
6119 12:20:55.113872 [ANA_INIT] >>>>>>>>>>>>>>
6120 12:20:55.116577 <<<<<< [CONFIGURE PHASE]: ANA_TX
6121 12:20:55.120718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6122 12:20:55.123585 ===================================
6123 12:20:55.126942 data_rate = 800,PCW = 0X7400
6124 12:20:55.130177 ===================================
6125 12:20:55.133271 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6126 12:20:55.139967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 12:20:55.149818 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 12:20:55.153453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6129 12:20:55.156452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6130 12:20:55.163163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6131 12:20:55.163248 [ANA_INIT] flow start
6132 12:20:55.166606 [ANA_INIT] PLL >>>>>>>>
6133 12:20:55.166687 [ANA_INIT] PLL <<<<<<<<
6134 12:20:55.169695 [ANA_INIT] MIDPI >>>>>>>>
6135 12:20:55.173166 [ANA_INIT] MIDPI <<<<<<<<
6136 12:20:55.176684 [ANA_INIT] DLL >>>>>>>>
6137 12:20:55.176765 [ANA_INIT] flow end
6138 12:20:55.179648 ============ LP4 DIFF to SE enter ============
6139 12:20:55.186652 ============ LP4 DIFF to SE exit ============
6140 12:20:55.186736 [ANA_INIT] <<<<<<<<<<<<<
6141 12:20:55.189593 [Flow] Enable top DCM control >>>>>
6142 12:20:55.193074 [Flow] Enable top DCM control <<<<<
6143 12:20:55.196194 Enable DLL master slave shuffle
6144 12:20:55.202977 ==============================================================
6145 12:20:55.203059 Gating Mode config
6146 12:20:55.209267 ==============================================================
6147 12:20:55.212663 Config description:
6148 12:20:55.222817 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6149 12:20:55.229295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6150 12:20:55.232540 SELPH_MODE 0: By rank 1: By Phase
6151 12:20:55.238939 ==============================================================
6152 12:20:55.242785 GAT_TRACK_EN = 0
6153 12:20:55.245890 RX_GATING_MODE = 2
6154 12:20:55.249207 RX_GATING_TRACK_MODE = 2
6155 12:20:55.249288 SELPH_MODE = 1
6156 12:20:55.252287 PICG_EARLY_EN = 1
6157 12:20:55.255756 VALID_LAT_VALUE = 1
6158 12:20:55.262161 ==============================================================
6159 12:20:55.265505 Enter into Gating configuration >>>>
6160 12:20:55.269172 Exit from Gating configuration <<<<
6161 12:20:55.272122 Enter into DVFS_PRE_config >>>>>
6162 12:20:55.282036 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6163 12:20:55.285515 Exit from DVFS_PRE_config <<<<<
6164 12:20:55.288847 Enter into PICG configuration >>>>
6165 12:20:55.292298 Exit from PICG configuration <<<<
6166 12:20:55.295298 [RX_INPUT] configuration >>>>>
6167 12:20:55.298755 [RX_INPUT] configuration <<<<<
6168 12:20:55.301746 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6169 12:20:55.308553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6170 12:20:55.315738 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 12:20:55.321518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 12:20:55.328576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 12:20:55.331987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 12:20:55.338328 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6175 12:20:55.341271 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6176 12:20:55.345120 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6177 12:20:55.348030 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6178 12:20:55.354751 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6179 12:20:55.357877 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 12:20:55.361576 ===================================
6181 12:20:55.364752 LPDDR4 DRAM CONFIGURATION
6182 12:20:55.367807 ===================================
6183 12:20:55.367888 EX_ROW_EN[0] = 0x0
6184 12:20:55.371446 EX_ROW_EN[1] = 0x0
6185 12:20:55.371526 LP4Y_EN = 0x0
6186 12:20:55.374743 WORK_FSP = 0x0
6187 12:20:55.374824 WL = 0x2
6188 12:20:55.377672 RL = 0x2
6189 12:20:55.381266 BL = 0x2
6190 12:20:55.381347 RPST = 0x0
6191 12:20:55.384202 RD_PRE = 0x0
6192 12:20:55.384282 WR_PRE = 0x1
6193 12:20:55.387753 WR_PST = 0x0
6194 12:20:55.387834 DBI_WR = 0x0
6195 12:20:55.391197 DBI_RD = 0x0
6196 12:20:55.391277 OTF = 0x1
6197 12:20:55.394619 ===================================
6198 12:20:55.397573 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6199 12:20:55.404859 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6200 12:20:55.407566 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 12:20:55.410716 ===================================
6202 12:20:55.414122 LPDDR4 DRAM CONFIGURATION
6203 12:20:55.417696 ===================================
6204 12:20:55.417780 EX_ROW_EN[0] = 0x10
6205 12:20:55.420916 EX_ROW_EN[1] = 0x0
6206 12:20:55.421040 LP4Y_EN = 0x0
6207 12:20:55.424457 WORK_FSP = 0x0
6208 12:20:55.424540 WL = 0x2
6209 12:20:55.427264 RL = 0x2
6210 12:20:55.430820 BL = 0x2
6211 12:20:55.430903 RPST = 0x0
6212 12:20:55.433823 RD_PRE = 0x0
6213 12:20:55.433906 WR_PRE = 0x1
6214 12:20:55.437344 WR_PST = 0x0
6215 12:20:55.437427 DBI_WR = 0x0
6216 12:20:55.440795 DBI_RD = 0x0
6217 12:20:55.440878 OTF = 0x1
6218 12:20:55.443965 ===================================
6219 12:20:55.450284 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6220 12:20:55.454509 nWR fixed to 30
6221 12:20:55.457619 [ModeRegInit_LP4] CH0 RK0
6222 12:20:55.457702 [ModeRegInit_LP4] CH0 RK1
6223 12:20:55.461118 [ModeRegInit_LP4] CH1 RK0
6224 12:20:55.464523 [ModeRegInit_LP4] CH1 RK1
6225 12:20:55.464606 match AC timing 19
6226 12:20:55.470856 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6227 12:20:55.474079 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6228 12:20:55.477627 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6229 12:20:55.483941 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6230 12:20:55.487204 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6231 12:20:55.487305 ==
6232 12:20:55.490873 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 12:20:55.494180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 12:20:55.494290 ==
6235 12:20:55.500805 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 12:20:55.507004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6237 12:20:55.510565 [CA 0] Center 36 (8~64) winsize 57
6238 12:20:55.513988 [CA 1] Center 36 (8~64) winsize 57
6239 12:20:55.517196 [CA 2] Center 36 (8~64) winsize 57
6240 12:20:55.520201 [CA 3] Center 36 (8~64) winsize 57
6241 12:20:55.523622 [CA 4] Center 36 (8~64) winsize 57
6242 12:20:55.523710 [CA 5] Center 36 (8~64) winsize 57
6243 12:20:55.527066
6244 12:20:55.530321 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6245 12:20:55.530407
6246 12:20:55.533874 [CATrainingPosCal] consider 1 rank data
6247 12:20:55.536768 u2DelayCellTimex100 = 270/100 ps
6248 12:20:55.540300 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:20:55.543852 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 12:20:55.546792 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 12:20:55.550215 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:20:55.553869 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:20:55.556843 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 12:20:55.556927
6255 12:20:55.560199 CA PerBit enable=1, Macro0, CA PI delay=36
6256 12:20:55.560283
6257 12:20:55.563785 [CBTSetCACLKResult] CA Dly = 36
6258 12:20:55.567076 CS Dly: 1 (0~32)
6259 12:20:55.567161 ==
6260 12:20:55.570842 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 12:20:55.573308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 12:20:55.573393 ==
6263 12:20:55.580479 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 12:20:55.586627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6265 12:20:55.590099 [CA 0] Center 36 (8~64) winsize 57
6266 12:20:55.590184 [CA 1] Center 36 (8~64) winsize 57
6267 12:20:55.593171 [CA 2] Center 36 (8~64) winsize 57
6268 12:20:55.596993 [CA 3] Center 36 (8~64) winsize 57
6269 12:20:55.599961 [CA 4] Center 36 (8~64) winsize 57
6270 12:20:55.603270 [CA 5] Center 36 (8~64) winsize 57
6271 12:20:55.603354
6272 12:20:55.606535 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6273 12:20:55.606618
6274 12:20:55.613365 [CATrainingPosCal] consider 2 rank data
6275 12:20:55.613449 u2DelayCellTimex100 = 270/100 ps
6276 12:20:55.616484 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 12:20:55.623053 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 12:20:55.626406 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 12:20:55.630065 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:20:55.633415 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:20:55.636489 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:20:55.636592
6283 12:20:55.639718 CA PerBit enable=1, Macro0, CA PI delay=36
6284 12:20:55.639802
6285 12:20:55.642927 [CBTSetCACLKResult] CA Dly = 36
6286 12:20:55.646181 CS Dly: 1 (0~32)
6287 12:20:55.646265
6288 12:20:55.649805 ----->DramcWriteLeveling(PI) begin...
6289 12:20:55.649891 ==
6290 12:20:55.652743 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 12:20:55.656154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 12:20:55.656239 ==
6293 12:20:55.659487 Write leveling (Byte 0): 40 => 8
6294 12:20:55.663126 Write leveling (Byte 1): 40 => 8
6295 12:20:55.666153 DramcWriteLeveling(PI) end<-----
6296 12:20:55.666234
6297 12:20:55.666296 ==
6298 12:20:55.669278 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 12:20:55.673123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 12:20:55.673254 ==
6301 12:20:55.675765 [Gating] SW mode calibration
6302 12:20:55.682391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6303 12:20:55.689419 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6304 12:20:55.692636 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 12:20:55.695741 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 12:20:55.702307 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 12:20:55.705912 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 12:20:55.708916 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 12:20:55.715641 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 12:20:55.719218 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 12:20:55.722306 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 12:20:55.728825 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 12:20:55.728907 Total UI for P1: 0, mck2ui 16
6314 12:20:55.735615 best dqsien dly found for B0: ( 0, 14, 24)
6315 12:20:55.735696 Total UI for P1: 0, mck2ui 16
6316 12:20:55.742569 best dqsien dly found for B1: ( 0, 14, 24)
6317 12:20:55.745605 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6318 12:20:55.748756 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6319 12:20:55.748837
6320 12:20:55.752554 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 12:20:55.755748 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 12:20:55.758698 [Gating] SW calibration Done
6323 12:20:55.758778 ==
6324 12:20:55.762539 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 12:20:55.765193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 12:20:55.765273 ==
6327 12:20:55.768765 RX Vref Scan: 0
6328 12:20:55.768852
6329 12:20:55.768917 RX Vref 0 -> 0, step: 1
6330 12:20:55.772239
6331 12:20:55.772318 RX Delay -410 -> 252, step: 16
6332 12:20:55.778721 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6333 12:20:55.781771 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6334 12:20:55.785225 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6335 12:20:55.788223 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6336 12:20:55.795181 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6337 12:20:55.798605 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6338 12:20:55.801392 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6339 12:20:55.804953 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6340 12:20:55.811582 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6341 12:20:55.814907 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6342 12:20:55.817940 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6343 12:20:55.821554 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6344 12:20:55.828247 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6345 12:20:55.831254 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6346 12:20:55.834687 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6347 12:20:55.841247 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6348 12:20:55.841329 ==
6349 12:20:55.844834 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 12:20:55.847766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 12:20:55.847850 ==
6352 12:20:55.847935 DQS Delay:
6353 12:20:55.851272 DQS0 = 59, DQS1 = 59
6354 12:20:55.851356 DQM Delay:
6355 12:20:55.854576 DQM0 = 18, DQM1 = 9
6356 12:20:55.854660 DQ Delay:
6357 12:20:55.857887 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6358 12:20:55.861296 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6359 12:20:55.864575 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6360 12:20:55.868090 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6361 12:20:55.868174
6362 12:20:55.868258
6363 12:20:55.868337 ==
6364 12:20:55.871099 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 12:20:55.874606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 12:20:55.874692 ==
6367 12:20:55.874776
6368 12:20:55.874856
6369 12:20:55.878050 TX Vref Scan disable
6370 12:20:55.881309 == TX Byte 0 ==
6371 12:20:55.884087 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 12:20:55.887762 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 12:20:55.890893 == TX Byte 1 ==
6374 12:20:55.894290 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 12:20:55.897870 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 12:20:55.897951 ==
6377 12:20:55.900910 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 12:20:55.904196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 12:20:55.904278 ==
6380 12:20:55.904341
6381 12:20:55.907704
6382 12:20:55.907787 TX Vref Scan disable
6383 12:20:55.910648 == TX Byte 0 ==
6384 12:20:55.914116 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 12:20:55.917566 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 12:20:55.920639 == TX Byte 1 ==
6387 12:20:55.924108 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 12:20:55.927569 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 12:20:55.927651
6390 12:20:55.927715 [DATLAT]
6391 12:20:55.930473 Freq=400, CH0 RK0
6392 12:20:55.930553
6393 12:20:55.930615 DATLAT Default: 0xf
6394 12:20:55.933973 0, 0xFFFF, sum = 0
6395 12:20:55.937448 1, 0xFFFF, sum = 0
6396 12:20:55.937530 2, 0xFFFF, sum = 0
6397 12:20:55.940397 3, 0xFFFF, sum = 0
6398 12:20:55.940479 4, 0xFFFF, sum = 0
6399 12:20:55.943755 5, 0xFFFF, sum = 0
6400 12:20:55.943837 6, 0xFFFF, sum = 0
6401 12:20:55.947196 7, 0xFFFF, sum = 0
6402 12:20:55.947304 8, 0xFFFF, sum = 0
6403 12:20:55.950586 9, 0xFFFF, sum = 0
6404 12:20:55.950666 10, 0xFFFF, sum = 0
6405 12:20:55.953898 11, 0xFFFF, sum = 0
6406 12:20:55.953980 12, 0xFFFF, sum = 0
6407 12:20:55.957199 13, 0x0, sum = 1
6408 12:20:55.957280 14, 0x0, sum = 2
6409 12:20:55.960737 15, 0x0, sum = 3
6410 12:20:55.960818 16, 0x0, sum = 4
6411 12:20:55.963931 best_step = 14
6412 12:20:55.964012
6413 12:20:55.964075 ==
6414 12:20:55.967522 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 12:20:55.970386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 12:20:55.970467 ==
6417 12:20:55.973837 RX Vref Scan: 1
6418 12:20:55.973918
6419 12:20:55.973981 RX Vref 0 -> 0, step: 1
6420 12:20:55.974041
6421 12:20:55.977063 RX Delay -359 -> 252, step: 8
6422 12:20:55.977144
6423 12:20:55.980529 Set Vref, RX VrefLevel [Byte0]: 63
6424 12:20:55.983468 [Byte1]: 47
6425 12:20:55.988370
6426 12:20:55.988478 Final RX Vref Byte 0 = 63 to rank0
6427 12:20:55.991916 Final RX Vref Byte 1 = 47 to rank0
6428 12:20:55.994938 Final RX Vref Byte 0 = 63 to rank1
6429 12:20:55.998291 Final RX Vref Byte 1 = 47 to rank1==
6430 12:20:56.001122 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 12:20:56.008192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 12:20:56.008298 ==
6433 12:20:56.008390 DQS Delay:
6434 12:20:56.011192 DQS0 = 60, DQS1 = 68
6435 12:20:56.011271 DQM Delay:
6436 12:20:56.011333 DQM0 = 14, DQM1 = 13
6437 12:20:56.014778 DQ Delay:
6438 12:20:56.017776 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =8
6439 12:20:56.021307 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6440 12:20:56.021388 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6441 12:20:56.027845 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6442 12:20:56.027927
6443 12:20:56.028071
6444 12:20:56.034642 [DQSOSCAuto] RK0, (LSB)MR18= 0x8180, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6445 12:20:56.037709 CH0 RK0: MR19=C0C, MR18=8180
6446 12:20:56.044077 CH0_RK0: MR19=0xC0C, MR18=0x8180, DQSOSC=393, MR23=63, INC=382, DEC=254
6447 12:20:56.044184 ==
6448 12:20:56.048071 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 12:20:56.051385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 12:20:56.051480 ==
6451 12:20:56.054221 [Gating] SW mode calibration
6452 12:20:56.061055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6453 12:20:56.067703 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6454 12:20:56.071316 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 12:20:56.074082 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 12:20:56.080906 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 12:20:56.084471 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 12:20:56.087299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 12:20:56.094362 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 12:20:56.097167 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 12:20:56.100380 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 12:20:56.107665 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 12:20:56.107754 Total UI for P1: 0, mck2ui 16
6464 12:20:56.113785 best dqsien dly found for B0: ( 0, 14, 24)
6465 12:20:56.113871 Total UI for P1: 0, mck2ui 16
6466 12:20:56.120700 best dqsien dly found for B1: ( 0, 14, 24)
6467 12:20:56.123852 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6468 12:20:56.127265 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6469 12:20:56.127363
6470 12:20:56.130148 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 12:20:56.133528 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 12:20:56.136789 [Gating] SW calibration Done
6473 12:20:56.136870 ==
6474 12:20:56.140358 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 12:20:56.143843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 12:20:56.143926 ==
6477 12:20:56.147008 RX Vref Scan: 0
6478 12:20:56.147129
6479 12:20:56.147225 RX Vref 0 -> 0, step: 1
6480 12:20:56.147314
6481 12:20:56.150333 RX Delay -410 -> 252, step: 16
6482 12:20:56.156776 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6483 12:20:56.160369 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6484 12:20:56.163280 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6485 12:20:56.166812 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6486 12:20:56.173306 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6487 12:20:56.176807 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6488 12:20:56.179774 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6489 12:20:56.183218 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6490 12:20:56.189912 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6491 12:20:56.193086 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6492 12:20:56.196448 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6493 12:20:56.199694 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6494 12:20:56.206553 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6495 12:20:56.209551 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6496 12:20:56.212948 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6497 12:20:56.219769 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6498 12:20:56.219855 ==
6499 12:20:56.223247 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 12:20:56.226179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 12:20:56.226260 ==
6502 12:20:56.226324 DQS Delay:
6503 12:20:56.229687 DQS0 = 59, DQS1 = 59
6504 12:20:56.229768 DQM Delay:
6505 12:20:56.233065 DQM0 = 16, DQM1 = 10
6506 12:20:56.233146 DQ Delay:
6507 12:20:56.236372 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6508 12:20:56.239444 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6509 12:20:56.242964 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6510 12:20:56.246387 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6511 12:20:56.246469
6512 12:20:56.246533
6513 12:20:56.246590 ==
6514 12:20:56.249336 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 12:20:56.252612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 12:20:56.252694 ==
6517 12:20:56.252769
6518 12:20:56.252828
6519 12:20:56.256140 TX Vref Scan disable
6520 12:20:56.256221 == TX Byte 0 ==
6521 12:20:56.262650 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6522 12:20:56.266331 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6523 12:20:56.266425 == TX Byte 1 ==
6524 12:20:56.272831 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6525 12:20:56.276312 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6526 12:20:56.276449 ==
6527 12:20:56.279325 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 12:20:56.282811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 12:20:56.282897 ==
6530 12:20:56.282960
6531 12:20:56.283051
6532 12:20:56.286125 TX Vref Scan disable
6533 12:20:56.289724 == TX Byte 0 ==
6534 12:20:56.292975 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6535 12:20:56.295903 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6536 12:20:56.296007 == TX Byte 1 ==
6537 12:20:56.302389 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6538 12:20:56.305630 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6539 12:20:56.305742
6540 12:20:56.305823 [DATLAT]
6541 12:20:56.309215 Freq=400, CH0 RK1
6542 12:20:56.309298
6543 12:20:56.309362 DATLAT Default: 0xe
6544 12:20:56.312676 0, 0xFFFF, sum = 0
6545 12:20:56.312762 1, 0xFFFF, sum = 0
6546 12:20:56.315557 2, 0xFFFF, sum = 0
6547 12:20:56.315669 3, 0xFFFF, sum = 0
6548 12:20:56.318986 4, 0xFFFF, sum = 0
6549 12:20:56.322721 5, 0xFFFF, sum = 0
6550 12:20:56.322829 6, 0xFFFF, sum = 0
6551 12:20:56.325751 7, 0xFFFF, sum = 0
6552 12:20:56.325824 8, 0xFFFF, sum = 0
6553 12:20:56.329135 9, 0xFFFF, sum = 0
6554 12:20:56.329251 10, 0xFFFF, sum = 0
6555 12:20:56.332736 11, 0xFFFF, sum = 0
6556 12:20:56.332820 12, 0xFFFF, sum = 0
6557 12:20:56.336378 13, 0x0, sum = 1
6558 12:20:56.336453 14, 0x0, sum = 2
6559 12:20:56.339109 15, 0x0, sum = 3
6560 12:20:56.339219 16, 0x0, sum = 4
6561 12:20:56.342423 best_step = 14
6562 12:20:56.342503
6563 12:20:56.342564 ==
6564 12:20:56.345873 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 12:20:56.348893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 12:20:56.348966 ==
6567 12:20:56.349027 RX Vref Scan: 0
6568 12:20:56.349093
6569 12:20:56.352664 RX Vref 0 -> 0, step: 1
6570 12:20:56.352782
6571 12:20:56.355752 RX Delay -359 -> 252, step: 8
6572 12:20:56.362727 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6573 12:20:56.365905 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6574 12:20:56.369545 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6575 12:20:56.373083 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6576 12:20:56.379412 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6577 12:20:56.382749 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6578 12:20:56.386037 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6579 12:20:56.389570 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6580 12:20:56.395881 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6581 12:20:56.399499 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6582 12:20:56.402459 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6583 12:20:56.409399 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6584 12:20:56.412477 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6585 12:20:56.416151 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6586 12:20:56.419457 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6587 12:20:56.425847 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6588 12:20:56.425944 ==
6589 12:20:56.429215 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 12:20:56.432811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 12:20:56.432926 ==
6592 12:20:56.433005 DQS Delay:
6593 12:20:56.435624 DQS0 = 60, DQS1 = 72
6594 12:20:56.435705 DQM Delay:
6595 12:20:56.439294 DQM0 = 12, DQM1 = 16
6596 12:20:56.439433 DQ Delay:
6597 12:20:56.442392 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6598 12:20:56.445910 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6599 12:20:56.449172 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6600 12:20:56.452359 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6601 12:20:56.452439
6602 12:20:56.452502
6603 12:20:56.459002 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6604 12:20:56.462422 CH0 RK1: MR19=C0C, MR18=C77C
6605 12:20:56.469192 CH0_RK1: MR19=0xC0C, MR18=0xC77C, DQSOSC=385, MR23=63, INC=398, DEC=265
6606 12:20:56.472243 [RxdqsGatingPostProcess] freq 400
6607 12:20:56.478863 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6608 12:20:56.481916 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 12:20:56.485257 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 12:20:56.488640 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 12:20:56.492115 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 12:20:56.492214 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 12:20:56.495126 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 12:20:56.498477 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 12:20:56.502060 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 12:20:56.505269 Pre-setting of DQS Precalculation
6617 12:20:56.511357 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6618 12:20:56.511468 ==
6619 12:20:56.514843 Dram Type= 6, Freq= 0, CH_1, rank 0
6620 12:20:56.518375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 12:20:56.518456 ==
6622 12:20:56.525151 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 12:20:56.531271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6624 12:20:56.534975 [CA 0] Center 36 (8~64) winsize 57
6625 12:20:56.535056 [CA 1] Center 36 (8~64) winsize 57
6626 12:20:56.538386 [CA 2] Center 36 (8~64) winsize 57
6627 12:20:56.541584 [CA 3] Center 36 (8~64) winsize 57
6628 12:20:56.544795 [CA 4] Center 36 (8~64) winsize 57
6629 12:20:56.547832 [CA 5] Center 36 (8~64) winsize 57
6630 12:20:56.547917
6631 12:20:56.551528 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6632 12:20:56.551609
6633 12:20:56.554712 [CATrainingPosCal] consider 1 rank data
6634 12:20:56.558111 u2DelayCellTimex100 = 270/100 ps
6635 12:20:56.561063 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:20:56.567844 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 12:20:56.571342 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 12:20:56.574626 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:20:56.577810 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:20:56.581752 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 12:20:56.581834
6642 12:20:56.584681 CA PerBit enable=1, Macro0, CA PI delay=36
6643 12:20:56.584762
6644 12:20:56.587978 [CBTSetCACLKResult] CA Dly = 36
6645 12:20:56.588060 CS Dly: 1 (0~32)
6646 12:20:56.591161 ==
6647 12:20:56.594676 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 12:20:56.597646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 12:20:56.597731 ==
6650 12:20:56.601150 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 12:20:56.607436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6652 12:20:56.611501 [CA 0] Center 36 (8~64) winsize 57
6653 12:20:56.614721 [CA 1] Center 36 (8~64) winsize 57
6654 12:20:56.617729 [CA 2] Center 36 (8~64) winsize 57
6655 12:20:56.621226 [CA 3] Center 36 (8~64) winsize 57
6656 12:20:56.624148 [CA 4] Center 36 (8~64) winsize 57
6657 12:20:56.627670 [CA 5] Center 36 (8~64) winsize 57
6658 12:20:56.627750
6659 12:20:56.630662 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6660 12:20:56.630742
6661 12:20:56.634063 [CATrainingPosCal] consider 2 rank data
6662 12:20:56.637658 u2DelayCellTimex100 = 270/100 ps
6663 12:20:56.640636 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 12:20:56.644312 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 12:20:56.647791 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 12:20:56.650561 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:20:56.657599 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:20:56.660591 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:20:56.660672
6670 12:20:56.663924 CA PerBit enable=1, Macro0, CA PI delay=36
6671 12:20:56.664004
6672 12:20:56.667890 [CBTSetCACLKResult] CA Dly = 36
6673 12:20:56.667971 CS Dly: 1 (0~32)
6674 12:20:56.668035
6675 12:20:56.670666 ----->DramcWriteLeveling(PI) begin...
6676 12:20:56.670748 ==
6677 12:20:56.674393 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 12:20:56.680629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 12:20:56.680710 ==
6680 12:20:56.684101 Write leveling (Byte 0): 40 => 8
6681 12:20:56.684228 Write leveling (Byte 1): 40 => 8
6682 12:20:56.687513 DramcWriteLeveling(PI) end<-----
6683 12:20:56.687594
6684 12:20:56.690537 ==
6685 12:20:56.690617 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 12:20:56.697092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 12:20:56.697203 ==
6688 12:20:56.700414 [Gating] SW mode calibration
6689 12:20:56.706954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6690 12:20:56.710270 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6691 12:20:56.717010 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 12:20:56.720488 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 12:20:56.723877 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 12:20:56.730328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 12:20:56.733204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 12:20:56.736904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 12:20:56.743804 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 12:20:56.747049 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 12:20:56.750418 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 12:20:56.753099 Total UI for P1: 0, mck2ui 16
6701 12:20:56.756392 best dqsien dly found for B0: ( 0, 14, 24)
6702 12:20:56.759978 Total UI for P1: 0, mck2ui 16
6703 12:20:56.763535 best dqsien dly found for B1: ( 0, 14, 24)
6704 12:20:56.766346 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6705 12:20:56.769961 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6706 12:20:56.770043
6707 12:20:56.776715 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 12:20:56.780108 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 12:20:56.782844 [Gating] SW calibration Done
6710 12:20:56.782937 ==
6711 12:20:56.786236 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 12:20:56.789837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 12:20:56.789920 ==
6714 12:20:56.789984 RX Vref Scan: 0
6715 12:20:56.790044
6716 12:20:56.793111 RX Vref 0 -> 0, step: 1
6717 12:20:56.793192
6718 12:20:56.796368 RX Delay -410 -> 252, step: 16
6719 12:20:56.799298 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6720 12:20:56.806248 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6721 12:20:56.809514 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6722 12:20:56.812730 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6723 12:20:56.816204 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6724 12:20:56.822623 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6725 12:20:56.825951 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6726 12:20:56.829423 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6727 12:20:56.832621 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6728 12:20:56.839380 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6729 12:20:56.842797 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6730 12:20:56.845995 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6731 12:20:56.849403 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6732 12:20:56.855769 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6733 12:20:56.859204 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6734 12:20:56.862331 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6735 12:20:56.862412 ==
6736 12:20:56.865930 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 12:20:56.872681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 12:20:56.872765 ==
6739 12:20:56.872829 DQS Delay:
6740 12:20:56.875574 DQS0 = 51, DQS1 = 67
6741 12:20:56.875655 DQM Delay:
6742 12:20:56.875718 DQM0 = 13, DQM1 = 17
6743 12:20:56.879235 DQ Delay:
6744 12:20:56.883071 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6745 12:20:56.883152 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6746 12:20:56.885880 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6747 12:20:56.889537 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6748 12:20:56.889623
6749 12:20:56.892670
6750 12:20:56.892750 ==
6751 12:20:56.895689 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 12:20:56.898808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 12:20:56.898889 ==
6754 12:20:56.898952
6755 12:20:56.899011
6756 12:20:56.902189 TX Vref Scan disable
6757 12:20:56.902270 == TX Byte 0 ==
6758 12:20:56.905689 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 12:20:56.912192 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 12:20:56.912279 == TX Byte 1 ==
6761 12:20:56.915547 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 12:20:56.922001 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 12:20:56.922085 ==
6764 12:20:56.925150 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 12:20:56.929208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 12:20:56.929293 ==
6767 12:20:56.929357
6768 12:20:56.929416
6769 12:20:56.932215 TX Vref Scan disable
6770 12:20:56.932296 == TX Byte 0 ==
6771 12:20:56.938657 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 12:20:56.941965 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 12:20:56.942047 == TX Byte 1 ==
6774 12:20:56.945024 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 12:20:56.951863 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 12:20:56.951974
6777 12:20:56.952071 [DATLAT]
6778 12:20:56.955784 Freq=400, CH1 RK0
6779 12:20:56.955867
6780 12:20:56.955930 DATLAT Default: 0xf
6781 12:20:56.958227 0, 0xFFFF, sum = 0
6782 12:20:56.958338 1, 0xFFFF, sum = 0
6783 12:20:56.961473 2, 0xFFFF, sum = 0
6784 12:20:56.961556 3, 0xFFFF, sum = 0
6785 12:20:56.964756 4, 0xFFFF, sum = 0
6786 12:20:56.964867 5, 0xFFFF, sum = 0
6787 12:20:56.968180 6, 0xFFFF, sum = 0
6788 12:20:56.968262 7, 0xFFFF, sum = 0
6789 12:20:56.971668 8, 0xFFFF, sum = 0
6790 12:20:56.971750 9, 0xFFFF, sum = 0
6791 12:20:56.975203 10, 0xFFFF, sum = 0
6792 12:20:56.975306 11, 0xFFFF, sum = 0
6793 12:20:56.978093 12, 0xFFFF, sum = 0
6794 12:20:56.978174 13, 0x0, sum = 1
6795 12:20:56.981458 14, 0x0, sum = 2
6796 12:20:56.981540 15, 0x0, sum = 3
6797 12:20:56.985087 16, 0x0, sum = 4
6798 12:20:56.985168 best_step = 14
6799 12:20:56.985232
6800 12:20:56.985294 ==
6801 12:20:56.988060 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 12:20:56.994600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 12:20:56.994710 ==
6804 12:20:56.994803 RX Vref Scan: 1
6805 12:20:56.994890
6806 12:20:56.998075 RX Vref 0 -> 0, step: 1
6807 12:20:56.998181
6808 12:20:57.001164 RX Delay -375 -> 252, step: 8
6809 12:20:57.001244
6810 12:20:57.004673 Set Vref, RX VrefLevel [Byte0]: 61
6811 12:20:57.007965 [Byte1]: 49
6812 12:20:57.011304
6813 12:20:57.011413 Final RX Vref Byte 0 = 61 to rank0
6814 12:20:57.014985 Final RX Vref Byte 1 = 49 to rank0
6815 12:20:57.017860 Final RX Vref Byte 0 = 61 to rank1
6816 12:20:57.021393 Final RX Vref Byte 1 = 49 to rank1==
6817 12:20:57.024916 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 12:20:57.031362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 12:20:57.031491 ==
6820 12:20:57.031560 DQS Delay:
6821 12:20:57.034606 DQS0 = 56, DQS1 = 64
6822 12:20:57.034715 DQM Delay:
6823 12:20:57.034810 DQM0 = 12, DQM1 = 11
6824 12:20:57.038175 DQ Delay:
6825 12:20:57.041713 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6826 12:20:57.041820 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6827 12:20:57.044677 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6828 12:20:57.048260 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6829 12:20:57.048345
6830 12:20:57.048409
6831 12:20:57.058036 [DQSOSCAuto] RK0, (LSB)MR18= 0x5467, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6832 12:20:57.061738 CH1 RK0: MR19=C0C, MR18=5467
6833 12:20:57.067835 CH1_RK0: MR19=0xC0C, MR18=0x5467, DQSOSC=396, MR23=63, INC=376, DEC=251
6834 12:20:57.067918 ==
6835 12:20:57.071282 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 12:20:57.074838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 12:20:57.074921 ==
6838 12:20:57.077624 [Gating] SW mode calibration
6839 12:20:57.084479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6840 12:20:57.090954 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6841 12:20:57.094414 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 12:20:57.097953 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 12:20:57.100977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 12:20:57.107477 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 12:20:57.110951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 12:20:57.114769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 12:20:57.120931 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 12:20:57.124276 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 12:20:57.127406 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 12:20:57.130865 Total UI for P1: 0, mck2ui 16
6851 12:20:57.134268 best dqsien dly found for B0: ( 0, 14, 24)
6852 12:20:57.137593 Total UI for P1: 0, mck2ui 16
6853 12:20:57.140699 best dqsien dly found for B1: ( 0, 14, 24)
6854 12:20:57.144240 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6855 12:20:57.150879 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6856 12:20:57.150975
6857 12:20:57.154306 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 12:20:57.157421 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 12:20:57.160908 [Gating] SW calibration Done
6860 12:20:57.160989 ==
6861 12:20:57.164207 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 12:20:57.167331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 12:20:57.167459 ==
6864 12:20:57.170576 RX Vref Scan: 0
6865 12:20:57.170655
6866 12:20:57.170717 RX Vref 0 -> 0, step: 1
6867 12:20:57.170775
6868 12:20:57.174183 RX Delay -410 -> 252, step: 16
6869 12:20:57.176956 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6870 12:20:57.184266 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6871 12:20:57.187222 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6872 12:20:57.190625 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6873 12:20:57.193909 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6874 12:20:57.200377 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6875 12:20:57.203899 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6876 12:20:57.206934 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6877 12:20:57.210791 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6878 12:20:57.217101 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6879 12:20:57.220757 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6880 12:20:57.223493 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6881 12:20:57.230457 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6882 12:20:57.233807 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6883 12:20:57.236939 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6884 12:20:57.240339 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6885 12:20:57.240421 ==
6886 12:20:57.243297 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 12:20:57.249992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 12:20:57.250077 ==
6889 12:20:57.250141 DQS Delay:
6890 12:20:57.253110 DQS0 = 51, DQS1 = 59
6891 12:20:57.253194 DQM Delay:
6892 12:20:57.256499 DQM0 = 12, DQM1 = 13
6893 12:20:57.256578 DQ Delay:
6894 12:20:57.260108 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6895 12:20:57.263054 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6896 12:20:57.266441 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6897 12:20:57.270026 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6898 12:20:57.270107
6899 12:20:57.270170
6900 12:20:57.270229 ==
6901 12:20:57.273031 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 12:20:57.276379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 12:20:57.276463 ==
6904 12:20:57.276527
6905 12:20:57.276586
6906 12:20:57.279931 TX Vref Scan disable
6907 12:20:57.280012 == TX Byte 0 ==
6908 12:20:57.282898 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6909 12:20:57.290127 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6910 12:20:57.290212 == TX Byte 1 ==
6911 12:20:57.292819 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6912 12:20:57.299499 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6913 12:20:57.299583 ==
6914 12:20:57.302951 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 12:20:57.306157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 12:20:57.306240 ==
6917 12:20:57.306304
6918 12:20:57.306363
6919 12:20:57.309179 TX Vref Scan disable
6920 12:20:57.309260 == TX Byte 0 ==
6921 12:20:57.315694 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6922 12:20:57.319121 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6923 12:20:57.319204 == TX Byte 1 ==
6924 12:20:57.325691 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6925 12:20:57.329084 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6926 12:20:57.329168
6927 12:20:57.329232 [DATLAT]
6928 12:20:57.332678 Freq=400, CH1 RK1
6929 12:20:57.332760
6930 12:20:57.332823 DATLAT Default: 0xe
6931 12:20:57.336186 0, 0xFFFF, sum = 0
6932 12:20:57.336267 1, 0xFFFF, sum = 0
6933 12:20:57.339391 2, 0xFFFF, sum = 0
6934 12:20:57.339486 3, 0xFFFF, sum = 0
6935 12:20:57.342538 4, 0xFFFF, sum = 0
6936 12:20:57.342620 5, 0xFFFF, sum = 0
6937 12:20:57.345715 6, 0xFFFF, sum = 0
6938 12:20:57.345798 7, 0xFFFF, sum = 0
6939 12:20:57.349541 8, 0xFFFF, sum = 0
6940 12:20:57.349623 9, 0xFFFF, sum = 0
6941 12:20:57.352292 10, 0xFFFF, sum = 0
6942 12:20:57.355387 11, 0xFFFF, sum = 0
6943 12:20:57.355482 12, 0xFFFF, sum = 0
6944 12:20:57.358982 13, 0x0, sum = 1
6945 12:20:57.359080 14, 0x0, sum = 2
6946 12:20:57.359160 15, 0x0, sum = 3
6947 12:20:57.362194 16, 0x0, sum = 4
6948 12:20:57.362278 best_step = 14
6949 12:20:57.362342
6950 12:20:57.365662 ==
6951 12:20:57.365743 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 12:20:57.372364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 12:20:57.372448 ==
6954 12:20:57.372511 RX Vref Scan: 0
6955 12:20:57.372571
6956 12:20:57.375796 RX Vref 0 -> 0, step: 1
6957 12:20:57.375878
6958 12:20:57.378651 RX Delay -359 -> 252, step: 8
6959 12:20:57.386115 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6960 12:20:57.389303 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6961 12:20:57.392170 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6962 12:20:57.395954 iDelay=217, Bit 3, Center -48 (-303 ~ 208) 512
6963 12:20:57.402093 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6964 12:20:57.405563 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6965 12:20:57.408778 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6966 12:20:57.412365 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6967 12:20:57.418856 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6968 12:20:57.422302 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6969 12:20:57.425508 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6970 12:20:57.432193 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6971 12:20:57.435613 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6972 12:20:57.438754 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6973 12:20:57.441796 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6974 12:20:57.448793 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6975 12:20:57.448878 ==
6976 12:20:57.452031 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 12:20:57.455224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 12:20:57.455306 ==
6979 12:20:57.455394 DQS Delay:
6980 12:20:57.458455 DQS0 = 60, DQS1 = 64
6981 12:20:57.458537 DQM Delay:
6982 12:20:57.461937 DQM0 = 13, DQM1 = 10
6983 12:20:57.462018 DQ Delay:
6984 12:20:57.464817 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6985 12:20:57.468056 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =12
6986 12:20:57.472115 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6987 12:20:57.475148 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6988 12:20:57.475231
6989 12:20:57.475294
6990 12:20:57.481926 [DQSOSCAuto] RK1, (LSB)MR18= 0x76a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
6991 12:20:57.484902 CH1 RK1: MR19=C0C, MR18=76A4
6992 12:20:57.491951 CH1_RK1: MR19=0xC0C, MR18=0x76A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6993 12:20:57.495253 [RxdqsGatingPostProcess] freq 400
6994 12:20:57.501798 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6995 12:20:57.505091 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 12:20:57.505177 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 12:20:57.508448 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 12:20:57.511410 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 12:20:57.514833 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 12:20:57.518359 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 12:20:57.521461 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 12:20:57.524690 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 12:20:57.528174 Pre-setting of DQS Precalculation
7004 12:20:57.534834 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7005 12:20:57.541314 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7006 12:20:57.547947 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7007 12:20:57.548039
7008 12:20:57.548104
7009 12:20:57.551019 [Calibration Summary] 800 Mbps
7010 12:20:57.551101 CH 0, Rank 0
7011 12:20:57.554649 SW Impedance : PASS
7012 12:20:57.558004 DUTY Scan : NO K
7013 12:20:57.558086 ZQ Calibration : PASS
7014 12:20:57.561196 Jitter Meter : NO K
7015 12:20:57.564450 CBT Training : PASS
7016 12:20:57.564533 Write leveling : PASS
7017 12:20:57.567646 RX DQS gating : PASS
7018 12:20:57.571192 RX DQ/DQS(RDDQC) : PASS
7019 12:20:57.571273 TX DQ/DQS : PASS
7020 12:20:57.574607 RX DATLAT : PASS
7021 12:20:57.577523 RX DQ/DQS(Engine): PASS
7022 12:20:57.577605 TX OE : NO K
7023 12:20:57.577669 All Pass.
7024 12:20:57.581112
7025 12:20:57.581194 CH 0, Rank 1
7026 12:20:57.584130 SW Impedance : PASS
7027 12:20:57.584212 DUTY Scan : NO K
7028 12:20:57.587241 ZQ Calibration : PASS
7029 12:20:57.587349 Jitter Meter : NO K
7030 12:20:57.591023 CBT Training : PASS
7031 12:20:57.593956 Write leveling : NO K
7032 12:20:57.594038 RX DQS gating : PASS
7033 12:20:57.597547 RX DQ/DQS(RDDQC) : PASS
7034 12:20:57.601152 TX DQ/DQS : PASS
7035 12:20:57.601234 RX DATLAT : PASS
7036 12:20:57.603952 RX DQ/DQS(Engine): PASS
7037 12:20:57.607361 TX OE : NO K
7038 12:20:57.607500 All Pass.
7039 12:20:57.607591
7040 12:20:57.607677 CH 1, Rank 0
7041 12:20:57.610913 SW Impedance : PASS
7042 12:20:57.613966 DUTY Scan : NO K
7043 12:20:57.614048 ZQ Calibration : PASS
7044 12:20:57.618025 Jitter Meter : NO K
7045 12:20:57.621083 CBT Training : PASS
7046 12:20:57.621164 Write leveling : PASS
7047 12:20:57.623983 RX DQS gating : PASS
7048 12:20:57.627525 RX DQ/DQS(RDDQC) : PASS
7049 12:20:57.627641 TX DQ/DQS : PASS
7050 12:20:57.630653 RX DATLAT : PASS
7051 12:20:57.630767 RX DQ/DQS(Engine): PASS
7052 12:20:57.634243 TX OE : NO K
7053 12:20:57.634325 All Pass.
7054 12:20:57.634388
7055 12:20:57.637236 CH 1, Rank 1
7056 12:20:57.637317 SW Impedance : PASS
7057 12:20:57.640491 DUTY Scan : NO K
7058 12:20:57.643776 ZQ Calibration : PASS
7059 12:20:57.643856 Jitter Meter : NO K
7060 12:20:57.647357 CBT Training : PASS
7061 12:20:57.650725 Write leveling : NO K
7062 12:20:57.650799 RX DQS gating : PASS
7063 12:20:57.653999 RX DQ/DQS(RDDQC) : PASS
7064 12:20:57.657342 TX DQ/DQS : PASS
7065 12:20:57.657425 RX DATLAT : PASS
7066 12:20:57.660509 RX DQ/DQS(Engine): PASS
7067 12:20:57.663946 TX OE : NO K
7068 12:20:57.664026 All Pass.
7069 12:20:57.664089
7070 12:20:57.667305 DramC Write-DBI off
7071 12:20:57.667410 PER_BANK_REFRESH: Hybrid Mode
7072 12:20:57.670764 TX_TRACKING: ON
7073 12:20:57.677319 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7074 12:20:57.683671 [FAST_K] Save calibration result to emmc
7075 12:20:57.687002 dramc_set_vcore_voltage set vcore to 725000
7076 12:20:57.687104 Read voltage for 1600, 0
7077 12:20:57.690162 Vio18 = 0
7078 12:20:57.690237 Vcore = 725000
7079 12:20:57.690302 Vdram = 0
7080 12:20:57.693818 Vddq = 0
7081 12:20:57.693917 Vmddr = 0
7082 12:20:57.696857 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7083 12:20:57.703823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7084 12:20:57.707224 MEM_TYPE=3, freq_sel=13
7085 12:20:57.710093 sv_algorithm_assistance_LP4_3733
7086 12:20:57.713524 ============ PULL DRAM RESETB DOWN ============
7087 12:20:57.716887 ========== PULL DRAM RESETB DOWN end =========
7088 12:20:57.723587 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7089 12:20:57.726864 ===================================
7090 12:20:57.726942 LPDDR4 DRAM CONFIGURATION
7091 12:20:57.729800 ===================================
7092 12:20:57.733462 EX_ROW_EN[0] = 0x0
7093 12:20:57.733568 EX_ROW_EN[1] = 0x0
7094 12:20:57.736957 LP4Y_EN = 0x0
7095 12:20:57.739871 WORK_FSP = 0x1
7096 12:20:57.739965 WL = 0x5
7097 12:20:57.743308 RL = 0x5
7098 12:20:57.743449 BL = 0x2
7099 12:20:57.746350 RPST = 0x0
7100 12:20:57.746424 RD_PRE = 0x0
7101 12:20:57.749827 WR_PRE = 0x1
7102 12:20:57.749898 WR_PST = 0x1
7103 12:20:57.753422 DBI_WR = 0x0
7104 12:20:57.753492 DBI_RD = 0x0
7105 12:20:57.756374 OTF = 0x1
7106 12:20:57.760195 ===================================
7107 12:20:57.763001 ===================================
7108 12:20:57.763101 ANA top config
7109 12:20:57.766214 ===================================
7110 12:20:57.769483 DLL_ASYNC_EN = 0
7111 12:20:57.773148 ALL_SLAVE_EN = 0
7112 12:20:57.776350 NEW_RANK_MODE = 1
7113 12:20:57.776431 DLL_IDLE_MODE = 1
7114 12:20:57.779712 LP45_APHY_COMB_EN = 1
7115 12:20:57.782679 TX_ODT_DIS = 0
7116 12:20:57.786471 NEW_8X_MODE = 1
7117 12:20:57.789592 ===================================
7118 12:20:57.793280 ===================================
7119 12:20:57.793361 data_rate = 3200
7120 12:20:57.796379 CKR = 1
7121 12:20:57.799443 DQ_P2S_RATIO = 8
7122 12:20:57.802878 ===================================
7123 12:20:57.806286 CA_P2S_RATIO = 8
7124 12:20:57.809206 DQ_CA_OPEN = 0
7125 12:20:57.812652 DQ_SEMI_OPEN = 0
7126 12:20:57.812726 CA_SEMI_OPEN = 0
7127 12:20:57.815674 CA_FULL_RATE = 0
7128 12:20:57.819031 DQ_CKDIV4_EN = 0
7129 12:20:57.822429 CA_CKDIV4_EN = 0
7130 12:20:57.826647 CA_PREDIV_EN = 0
7131 12:20:57.829375 PH8_DLY = 12
7132 12:20:57.832963 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7133 12:20:57.833044 DQ_AAMCK_DIV = 4
7134 12:20:57.836106 CA_AAMCK_DIV = 4
7135 12:20:57.839364 CA_ADMCK_DIV = 4
7136 12:20:57.842411 DQ_TRACK_CA_EN = 0
7137 12:20:57.845559 CA_PICK = 1600
7138 12:20:57.848849 CA_MCKIO = 1600
7139 12:20:57.851995 MCKIO_SEMI = 0
7140 12:20:57.852077 PLL_FREQ = 3068
7141 12:20:57.855525 DQ_UI_PI_RATIO = 32
7142 12:20:57.858935 CA_UI_PI_RATIO = 0
7143 12:20:57.861941 ===================================
7144 12:20:57.865420 ===================================
7145 12:20:57.868820 memory_type:LPDDR4
7146 12:20:57.868895 GP_NUM : 10
7147 12:20:57.872397 SRAM_EN : 1
7148 12:20:57.875218 MD32_EN : 0
7149 12:20:57.879042 ===================================
7150 12:20:57.879146 [ANA_INIT] >>>>>>>>>>>>>>
7151 12:20:57.881853 <<<<<< [CONFIGURE PHASE]: ANA_TX
7152 12:20:57.885451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7153 12:20:57.889125 ===================================
7154 12:20:57.891727 data_rate = 3200,PCW = 0X7600
7155 12:20:57.895255 ===================================
7156 12:20:57.898247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7157 12:20:57.905310 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 12:20:57.911667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 12:20:57.914963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7160 12:20:57.918443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7161 12:20:57.922168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7162 12:20:57.925369 [ANA_INIT] flow start
7163 12:20:57.925445 [ANA_INIT] PLL >>>>>>>>
7164 12:20:57.928583 [ANA_INIT] PLL <<<<<<<<
7165 12:20:57.932034 [ANA_INIT] MIDPI >>>>>>>>
7166 12:20:57.932136 [ANA_INIT] MIDPI <<<<<<<<
7167 12:20:57.935560 [ANA_INIT] DLL >>>>>>>>
7168 12:20:57.938625 [ANA_INIT] DLL <<<<<<<<
7169 12:20:57.938699 [ANA_INIT] flow end
7170 12:20:57.944938 ============ LP4 DIFF to SE enter ============
7171 12:20:57.948460 ============ LP4 DIFF to SE exit ============
7172 12:20:57.948539 [ANA_INIT] <<<<<<<<<<<<<
7173 12:20:57.952276 [Flow] Enable top DCM control >>>>>
7174 12:20:57.954961 [Flow] Enable top DCM control <<<<<
7175 12:20:57.958545 Enable DLL master slave shuffle
7176 12:20:57.964860 ==============================================================
7177 12:20:57.968426 Gating Mode config
7178 12:20:57.971926 ==============================================================
7179 12:20:57.975149 Config description:
7180 12:20:57.985089 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7181 12:20:57.991681 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7182 12:20:57.995039 SELPH_MODE 0: By rank 1: By Phase
7183 12:20:58.001582 ==============================================================
7184 12:20:58.004850 GAT_TRACK_EN = 1
7185 12:20:58.008182 RX_GATING_MODE = 2
7186 12:20:58.008262 RX_GATING_TRACK_MODE = 2
7187 12:20:58.011631 SELPH_MODE = 1
7188 12:20:58.015176 PICG_EARLY_EN = 1
7189 12:20:58.018598 VALID_LAT_VALUE = 1
7190 12:20:58.024852 ==============================================================
7191 12:20:58.028240 Enter into Gating configuration >>>>
7192 12:20:58.031807 Exit from Gating configuration <<<<
7193 12:20:58.034748 Enter into DVFS_PRE_config >>>>>
7194 12:20:58.044711 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7195 12:20:58.047826 Exit from DVFS_PRE_config <<<<<
7196 12:20:58.051527 Enter into PICG configuration >>>>
7197 12:20:58.054553 Exit from PICG configuration <<<<
7198 12:20:58.057762 [RX_INPUT] configuration >>>>>
7199 12:20:58.061235 [RX_INPUT] configuration <<<<<
7200 12:20:58.065011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7201 12:20:58.070911 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7202 12:20:58.077959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 12:20:58.084301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 12:20:58.091035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 12:20:58.094215 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 12:20:58.101024 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7207 12:20:58.104201 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7208 12:20:58.107297 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7209 12:20:58.110967 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7210 12:20:58.114034 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7211 12:20:58.120821 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 12:20:58.124290 ===================================
7213 12:20:58.127258 LPDDR4 DRAM CONFIGURATION
7214 12:20:58.130726 ===================================
7215 12:20:58.130827 EX_ROW_EN[0] = 0x0
7216 12:20:58.134173 EX_ROW_EN[1] = 0x0
7217 12:20:58.134271 LP4Y_EN = 0x0
7218 12:20:58.137546 WORK_FSP = 0x1
7219 12:20:58.137619 WL = 0x5
7220 12:20:58.140607 RL = 0x5
7221 12:20:58.140686 BL = 0x2
7222 12:20:58.144218 RPST = 0x0
7223 12:20:58.144292 RD_PRE = 0x0
7224 12:20:58.147381 WR_PRE = 0x1
7225 12:20:58.147485 WR_PST = 0x1
7226 12:20:58.151098 DBI_WR = 0x0
7227 12:20:58.151191 DBI_RD = 0x0
7228 12:20:58.153999 OTF = 0x1
7229 12:20:58.157455 ===================================
7230 12:20:58.160925 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7231 12:20:58.164128 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7232 12:20:58.170945 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 12:20:58.173740 ===================================
7234 12:20:58.173871 LPDDR4 DRAM CONFIGURATION
7235 12:20:58.176982 ===================================
7236 12:20:58.180315 EX_ROW_EN[0] = 0x10
7237 12:20:58.183921 EX_ROW_EN[1] = 0x0
7238 12:20:58.184028 LP4Y_EN = 0x0
7239 12:20:58.186881 WORK_FSP = 0x1
7240 12:20:58.186991 WL = 0x5
7241 12:20:58.190396 RL = 0x5
7242 12:20:58.190473 BL = 0x2
7243 12:20:58.193925 RPST = 0x0
7244 12:20:58.194032 RD_PRE = 0x0
7245 12:20:58.196852 WR_PRE = 0x1
7246 12:20:58.196933 WR_PST = 0x1
7247 12:20:58.200332 DBI_WR = 0x0
7248 12:20:58.200412 DBI_RD = 0x0
7249 12:20:58.203592 OTF = 0x1
7250 12:20:58.206825 ===================================
7251 12:20:58.214095 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7252 12:20:58.214178 ==
7253 12:20:58.216892 Dram Type= 6, Freq= 0, CH_0, rank 0
7254 12:20:58.220663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7255 12:20:58.220737 ==
7256 12:20:58.223253 [Duty_Offset_Calibration]
7257 12:20:58.223350 B0:2 B1:0 CA:3
7258 12:20:58.223454
7259 12:20:58.226726 [DutyScan_Calibration_Flow] k_type=0
7260 12:20:58.237734
7261 12:20:58.237817 ==CLK 0==
7262 12:20:58.241316 Final CLK duty delay cell = 0
7263 12:20:58.244777 [0] MAX Duty = 5031%(X100), DQS PI = 12
7264 12:20:58.247898 [0] MIN Duty = 4875%(X100), DQS PI = 54
7265 12:20:58.251587 [0] AVG Duty = 4953%(X100)
7266 12:20:58.251668
7267 12:20:58.254861 CH0 CLK Duty spec in!! Max-Min= 156%
7268 12:20:58.257690 [DutyScan_Calibration_Flow] ====Done====
7269 12:20:58.257771
7270 12:20:58.260832 [DutyScan_Calibration_Flow] k_type=1
7271 12:20:58.278176
7272 12:20:58.278278 ==DQS 0 ==
7273 12:20:58.281345 Final DQS duty delay cell = 0
7274 12:20:58.284578 [0] MAX Duty = 5094%(X100), DQS PI = 30
7275 12:20:58.287906 [0] MIN Duty = 4875%(X100), DQS PI = 48
7276 12:20:58.291343 [0] AVG Duty = 4984%(X100)
7277 12:20:58.291463
7278 12:20:58.291531 ==DQS 1 ==
7279 12:20:58.294559 Final DQS duty delay cell = 0
7280 12:20:58.298073 [0] MAX Duty = 5156%(X100), DQS PI = 32
7281 12:20:58.301522 [0] MIN Duty = 5031%(X100), DQS PI = 12
7282 12:20:58.304330 [0] AVG Duty = 5093%(X100)
7283 12:20:58.304403
7284 12:20:58.307907 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7285 12:20:58.308006
7286 12:20:58.311195 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7287 12:20:58.314449 [DutyScan_Calibration_Flow] ====Done====
7288 12:20:58.314525
7289 12:20:58.317273 [DutyScan_Calibration_Flow] k_type=3
7290 12:20:58.336231
7291 12:20:58.336327 ==DQM 0 ==
7292 12:20:58.339244 Final DQM duty delay cell = 0
7293 12:20:58.342726 [0] MAX Duty = 5156%(X100), DQS PI = 30
7294 12:20:58.346688 [0] MIN Duty = 4875%(X100), DQS PI = 0
7295 12:20:58.346771 [0] AVG Duty = 5015%(X100)
7296 12:20:58.349201
7297 12:20:58.349281 ==DQM 1 ==
7298 12:20:58.352676 Final DQM duty delay cell = 4
7299 12:20:58.356146 [4] MAX Duty = 5187%(X100), DQS PI = 60
7300 12:20:58.359216 [4] MIN Duty = 5031%(X100), DQS PI = 14
7301 12:20:58.362620 [4] AVG Duty = 5109%(X100)
7302 12:20:58.362700
7303 12:20:58.366042 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7304 12:20:58.366122
7305 12:20:58.369374 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7306 12:20:58.372742 [DutyScan_Calibration_Flow] ====Done====
7307 12:20:58.372827
7308 12:20:58.375739 [DutyScan_Calibration_Flow] k_type=2
7309 12:20:58.392241
7310 12:20:58.392331 ==DQ 0 ==
7311 12:20:58.395969 Final DQ duty delay cell = -4
7312 12:20:58.399048 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7313 12:20:58.402570 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7314 12:20:58.405557 [-4] AVG Duty = 4938%(X100)
7315 12:20:58.405637
7316 12:20:58.405700 ==DQ 1 ==
7317 12:20:58.408952 Final DQ duty delay cell = 0
7318 12:20:58.412242 [0] MAX Duty = 5156%(X100), DQS PI = 58
7319 12:20:58.415776 [0] MIN Duty = 5000%(X100), DQS PI = 16
7320 12:20:58.418646 [0] AVG Duty = 5078%(X100)
7321 12:20:58.418726
7322 12:20:58.422267 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7323 12:20:58.422401
7324 12:20:58.425460 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7325 12:20:58.429069 [DutyScan_Calibration_Flow] ====Done====
7326 12:20:58.429150 ==
7327 12:20:58.432257 Dram Type= 6, Freq= 0, CH_1, rank 0
7328 12:20:58.435630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7329 12:20:58.435711 ==
7330 12:20:58.438965 [Duty_Offset_Calibration]
7331 12:20:58.439043 B0:1 B1:-2 CA:0
7332 12:20:58.439106
7333 12:20:58.442530 [DutyScan_Calibration_Flow] k_type=0
7334 12:20:58.452992
7335 12:20:58.453074 ==CLK 0==
7336 12:20:58.456492 Final CLK duty delay cell = 0
7337 12:20:58.459508 [0] MAX Duty = 5093%(X100), DQS PI = 30
7338 12:20:58.462813 [0] MIN Duty = 4813%(X100), DQS PI = 60
7339 12:20:58.466099 [0] AVG Duty = 4953%(X100)
7340 12:20:58.466174
7341 12:20:58.469684 CH1 CLK Duty spec in!! Max-Min= 280%
7342 12:20:58.472767 [DutyScan_Calibration_Flow] ====Done====
7343 12:20:58.472841
7344 12:20:58.475884 [DutyScan_Calibration_Flow] k_type=1
7345 12:20:58.491795
7346 12:20:58.491882 ==DQS 0 ==
7347 12:20:58.495608 Final DQS duty delay cell = -4
7348 12:20:58.498650 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7349 12:20:58.501833 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7350 12:20:58.505157 [-4] AVG Duty = 4906%(X100)
7351 12:20:58.505236
7352 12:20:58.505299 ==DQS 1 ==
7353 12:20:58.508188 Final DQS duty delay cell = 0
7354 12:20:58.511738 [0] MAX Duty = 5093%(X100), DQS PI = 60
7355 12:20:58.514793 [0] MIN Duty = 4844%(X100), DQS PI = 26
7356 12:20:58.518552 [0] AVG Duty = 4968%(X100)
7357 12:20:58.518633
7358 12:20:58.521590 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7359 12:20:58.521674
7360 12:20:58.524857 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7361 12:20:58.528078 [DutyScan_Calibration_Flow] ====Done====
7362 12:20:58.528184
7363 12:20:58.531253 [DutyScan_Calibration_Flow] k_type=3
7364 12:20:58.549075
7365 12:20:58.549180 ==DQM 0 ==
7366 12:20:58.552553 Final DQM duty delay cell = 0
7367 12:20:58.556103 [0] MAX Duty = 5031%(X100), DQS PI = 24
7368 12:20:58.558922 [0] MIN Duty = 4813%(X100), DQS PI = 56
7369 12:20:58.562593 [0] AVG Duty = 4922%(X100)
7370 12:20:58.562675
7371 12:20:58.562738 ==DQM 1 ==
7372 12:20:58.566048 Final DQM duty delay cell = 0
7373 12:20:58.568978 [0] MAX Duty = 5062%(X100), DQS PI = 34
7374 12:20:58.572860 [0] MIN Duty = 4875%(X100), DQS PI = 26
7375 12:20:58.576097 [0] AVG Duty = 4968%(X100)
7376 12:20:58.576177
7377 12:20:58.579006 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7378 12:20:58.579086
7379 12:20:58.582366 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7380 12:20:58.585478 [DutyScan_Calibration_Flow] ====Done====
7381 12:20:58.585558
7382 12:20:58.588766 [DutyScan_Calibration_Flow] k_type=2
7383 12:20:58.606370
7384 12:20:58.606474 ==DQ 0 ==
7385 12:20:58.609387 Final DQ duty delay cell = 0
7386 12:20:58.613281 [0] MAX Duty = 5093%(X100), DQS PI = 22
7387 12:20:58.616377 [0] MIN Duty = 4907%(X100), DQS PI = 60
7388 12:20:58.616460 [0] AVG Duty = 5000%(X100)
7389 12:20:58.619552
7390 12:20:58.619632 ==DQ 1 ==
7391 12:20:58.622759 Final DQ duty delay cell = 0
7392 12:20:58.626343 [0] MAX Duty = 5156%(X100), DQS PI = 34
7393 12:20:58.629063 [0] MIN Duty = 4969%(X100), DQS PI = 24
7394 12:20:58.629145 [0] AVG Duty = 5062%(X100)
7395 12:20:58.632674
7396 12:20:58.635935 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7397 12:20:58.636017
7398 12:20:58.639116 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7399 12:20:58.642618 [DutyScan_Calibration_Flow] ====Done====
7400 12:20:58.645900 nWR fixed to 30
7401 12:20:58.645982 [ModeRegInit_LP4] CH0 RK0
7402 12:20:58.649520 [ModeRegInit_LP4] CH0 RK1
7403 12:20:58.652608 [ModeRegInit_LP4] CH1 RK0
7404 12:20:58.655744 [ModeRegInit_LP4] CH1 RK1
7405 12:20:58.655825 match AC timing 5
7406 12:20:58.658987 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7407 12:20:58.665924 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7408 12:20:58.669006 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7409 12:20:58.675595 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7410 12:20:58.679009 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7411 12:20:58.679091 [MiockJmeterHQA]
7412 12:20:58.679154
7413 12:20:58.682655 [DramcMiockJmeter] u1RxGatingPI = 0
7414 12:20:58.685580 0 : 4252, 4026
7415 12:20:58.685663 4 : 4258, 4029
7416 12:20:58.689323 8 : 4363, 4138
7417 12:20:58.689407 12 : 4363, 4138
7418 12:20:58.689473 16 : 4252, 4027
7419 12:20:58.692857 20 : 4363, 4137
7420 12:20:58.692939 24 : 4252, 4027
7421 12:20:58.695548 28 : 4253, 4027
7422 12:20:58.695629 32 : 4252, 4027
7423 12:20:58.698992 36 : 4254, 4029
7424 12:20:58.699073 40 : 4363, 4138
7425 12:20:58.701863 44 : 4250, 4027
7426 12:20:58.701967 48 : 4363, 4137
7427 12:20:58.702045 52 : 4250, 4027
7428 12:20:58.705701 56 : 4250, 4027
7429 12:20:58.705800 60 : 4250, 4027
7430 12:20:58.708990 64 : 4360, 4138
7431 12:20:58.709071 68 : 4250, 4026
7432 12:20:58.712059 72 : 4360, 4138
7433 12:20:58.712141 76 : 4250, 4027
7434 12:20:58.715488 80 : 4250, 4027
7435 12:20:58.715570 84 : 4250, 4027
7436 12:20:58.715633 88 : 4253, 4029
7437 12:20:58.718457 92 : 4360, 4138
7438 12:20:58.718539 96 : 4249, 4027
7439 12:20:58.721914 100 : 4361, 4137
7440 12:20:58.721995 104 : 4250, 3705
7441 12:20:58.725286 108 : 4250, 2
7442 12:20:58.725368 112 : 4250, 0
7443 12:20:58.725433 116 : 4253, 0
7444 12:20:58.728948 120 : 4252, 0
7445 12:20:58.729029 124 : 4250, 0
7446 12:20:58.731956 128 : 4253, 0
7447 12:20:58.732037 132 : 4361, 0
7448 12:20:58.732102 136 : 4361, 0
7449 12:20:58.735338 140 : 4250, 0
7450 12:20:58.735461 144 : 4249, 0
7451 12:20:58.739206 148 : 4361, 0
7452 12:20:58.739303 152 : 4250, 0
7453 12:20:58.739375 156 : 4250, 0
7454 12:20:58.741838 160 : 4250, 0
7455 12:20:58.741920 164 : 4250, 0
7456 12:20:58.741984 168 : 4252, 0
7457 12:20:58.745181 172 : 4360, 0
7458 12:20:58.745263 176 : 4250, 0
7459 12:20:58.748815 180 : 4250, 0
7460 12:20:58.748897 184 : 4250, 0
7461 12:20:58.748961 188 : 4361, 0
7462 12:20:58.751716 192 : 4360, 0
7463 12:20:58.751797 196 : 4250, 0
7464 12:20:58.755150 200 : 4250, 0
7465 12:20:58.755283 204 : 4363, 0
7466 12:20:58.755387 208 : 4250, 0
7467 12:20:58.758551 212 : 4250, 0
7468 12:20:58.758633 216 : 4250, 0
7469 12:20:58.761708 220 : 4252, 0
7470 12:20:58.761789 224 : 4361, 0
7471 12:20:58.761853 228 : 4250, 0
7472 12:20:58.765088 232 : 4250, 3
7473 12:20:58.765172 236 : 4250, 1462
7474 12:20:58.768546 240 : 4252, 4029
7475 12:20:58.768648 244 : 4250, 4026
7476 12:20:58.771513 248 : 4363, 4140
7477 12:20:58.771588 252 : 4360, 4138
7478 12:20:58.774905 256 : 4250, 4027
7479 12:20:58.774986 260 : 4363, 4140
7480 12:20:58.775048 264 : 4360, 4138
7481 12:20:58.778238 268 : 4250, 4027
7482 12:20:58.778339 272 : 4250, 4027
7483 12:20:58.781447 276 : 4252, 4029
7484 12:20:58.781532 280 : 4250, 4027
7485 12:20:58.785362 284 : 4250, 4027
7486 12:20:58.785445 288 : 4250, 4027
7487 12:20:58.788070 292 : 4252, 4029
7488 12:20:58.788153 296 : 4250, 4026
7489 12:20:58.791492 300 : 4361, 4137
7490 12:20:58.791576 304 : 4360, 4138
7491 12:20:58.794572 308 : 4250, 4027
7492 12:20:58.794654 312 : 4363, 4140
7493 12:20:58.797925 316 : 4250, 4026
7494 12:20:58.798007 320 : 4250, 4027
7495 12:20:58.801521 324 : 4250, 4027
7496 12:20:58.801633 328 : 4252, 4029
7497 12:20:58.801727 332 : 4250, 4026
7498 12:20:58.804409 336 : 4250, 4026
7499 12:20:58.804482 340 : 4250, 4027
7500 12:20:58.808289 344 : 4252, 4029
7501 12:20:58.808395 348 : 4250, 4026
7502 12:20:58.811283 352 : 4361, 4130
7503 12:20:58.811390 356 : 4360, 2995
7504 12:20:58.814791 360 : 4250, 5
7505 12:20:58.814865
7506 12:20:58.814926 MIOCK jitter meter ch=0
7507 12:20:58.814988
7508 12:20:58.817732 1T = (360-108) = 252 dly cells
7509 12:20:58.824461 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7510 12:20:58.824554 ==
7511 12:20:58.827834 Dram Type= 6, Freq= 0, CH_0, rank 0
7512 12:20:58.831399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7513 12:20:58.831492 ==
7514 12:20:58.837995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7515 12:20:58.841322 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7516 12:20:58.847546 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7517 12:20:58.850755 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7518 12:20:58.861290 [CA 0] Center 43 (13~74) winsize 62
7519 12:20:58.864676 [CA 1] Center 43 (13~74) winsize 62
7520 12:20:58.867612 [CA 2] Center 39 (10~68) winsize 59
7521 12:20:58.870914 [CA 3] Center 38 (9~68) winsize 60
7522 12:20:58.874439 [CA 4] Center 36 (7~66) winsize 60
7523 12:20:58.877474 [CA 5] Center 36 (7~66) winsize 60
7524 12:20:58.877548
7525 12:20:58.880629 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7526 12:20:58.880705
7527 12:20:58.887401 [CATrainingPosCal] consider 1 rank data
7528 12:20:58.887494 u2DelayCellTimex100 = 258/100 ps
7529 12:20:58.893962 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7530 12:20:58.897526 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7531 12:20:58.900584 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7532 12:20:58.903713 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7533 12:20:58.907611 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7534 12:20:58.910563 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7535 12:20:58.910644
7536 12:20:58.913966 CA PerBit enable=1, Macro0, CA PI delay=36
7537 12:20:58.914069
7538 12:20:58.917325 [CBTSetCACLKResult] CA Dly = 36
7539 12:20:58.920327 CS Dly: 11 (0~42)
7540 12:20:58.923842 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7541 12:20:58.926693 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7542 12:20:58.926768 ==
7543 12:20:58.930299 Dram Type= 6, Freq= 0, CH_0, rank 1
7544 12:20:58.937026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 12:20:58.937107 ==
7546 12:20:58.940624 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7547 12:20:58.946822 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7548 12:20:58.950341 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7549 12:20:58.957314 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7550 12:20:58.965404 [CA 0] Center 43 (13~74) winsize 62
7551 12:20:58.967914 [CA 1] Center 43 (13~74) winsize 62
7552 12:20:58.971665 [CA 2] Center 39 (10~68) winsize 59
7553 12:20:58.974779 [CA 3] Center 39 (10~68) winsize 59
7554 12:20:58.978654 [CA 4] Center 36 (6~66) winsize 61
7555 12:20:58.981535 [CA 5] Center 36 (6~66) winsize 61
7556 12:20:58.981617
7557 12:20:58.984799 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7558 12:20:58.984882
7559 12:20:58.991232 [CATrainingPosCal] consider 2 rank data
7560 12:20:58.991316 u2DelayCellTimex100 = 258/100 ps
7561 12:20:58.998199 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7562 12:20:59.001054 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7563 12:20:59.004469 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7564 12:20:59.007888 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7565 12:20:59.011177 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7566 12:20:59.014662 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7567 12:20:59.014746
7568 12:20:59.017633 CA PerBit enable=1, Macro0, CA PI delay=36
7569 12:20:59.017715
7570 12:20:59.021288 [CBTSetCACLKResult] CA Dly = 36
7571 12:20:59.024426 CS Dly: 11 (0~43)
7572 12:20:59.027381 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7573 12:20:59.031209 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7574 12:20:59.031293
7575 12:20:59.034201 ----->DramcWriteLeveling(PI) begin...
7576 12:20:59.037925 ==
7577 12:20:59.038008 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 12:20:59.044680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 12:20:59.044766 ==
7580 12:20:59.047558 Write leveling (Byte 0): 36 => 36
7581 12:20:59.050659 Write leveling (Byte 1): 29 => 29
7582 12:20:59.053983 DramcWriteLeveling(PI) end<-----
7583 12:20:59.054065
7584 12:20:59.054129 ==
7585 12:20:59.057559 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 12:20:59.060566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 12:20:59.060648 ==
7588 12:20:59.064060 [Gating] SW mode calibration
7589 12:20:59.070795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7590 12:20:59.077138 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7591 12:20:59.080549 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 12:20:59.083796 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 12:20:59.087364 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 12:20:59.093988 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 12:20:59.097104 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7596 12:20:59.100438 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7597 12:20:59.106872 1 4 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7598 12:20:59.110186 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 12:20:59.113797 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 12:20:59.119982 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 12:20:59.123363 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 12:20:59.127192 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7603 12:20:59.133286 1 5 16 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
7604 12:20:59.136710 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7605 12:20:59.140035 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7606 12:20:59.146631 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 12:20:59.149687 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 12:20:59.152984 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 12:20:59.160098 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 12:20:59.163338 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 12:20:59.166333 1 6 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7612 12:20:59.173338 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (1 1) (0 0)
7613 12:20:59.176725 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7614 12:20:59.179582 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 12:20:59.186052 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 12:20:59.189474 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 12:20:59.193025 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 12:20:59.199685 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7619 12:20:59.202658 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7620 12:20:59.206204 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7621 12:20:59.212609 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7622 12:20:59.215862 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:20:59.219099 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:20:59.226102 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:20:59.229018 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:20:59.232827 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:20:59.239265 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:20:59.242367 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:20:59.245697 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 12:20:59.252265 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 12:20:59.255678 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 12:20:59.259007 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 12:20:59.265326 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 12:20:59.268920 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7635 12:20:59.272095 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7636 12:20:59.278576 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7637 12:20:59.278660 Total UI for P1: 0, mck2ui 16
7638 12:20:59.285792 best dqsien dly found for B0: ( 1, 9, 14)
7639 12:20:59.288784 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7640 12:20:59.291871 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 12:20:59.295595 Total UI for P1: 0, mck2ui 16
7642 12:20:59.298892 best dqsien dly found for B1: ( 1, 9, 22)
7643 12:20:59.301845 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7644 12:20:59.305419 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7645 12:20:59.305500
7646 12:20:59.311879 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7647 12:20:59.315343 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7648 12:20:59.318256 [Gating] SW calibration Done
7649 12:20:59.318336 ==
7650 12:20:59.321707 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 12:20:59.325007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 12:20:59.325089 ==
7653 12:20:59.325153 RX Vref Scan: 0
7654 12:20:59.325243
7655 12:20:59.328410 RX Vref 0 -> 0, step: 1
7656 12:20:59.328489
7657 12:20:59.331573 RX Delay 0 -> 252, step: 8
7658 12:20:59.334942 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7659 12:20:59.338229 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7660 12:20:59.345236 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7661 12:20:59.348283 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7662 12:20:59.351675 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7663 12:20:59.354976 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7664 12:20:59.358363 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7665 12:20:59.364807 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7666 12:20:59.368645 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7667 12:20:59.371247 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7668 12:20:59.374602 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7669 12:20:59.378238 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7670 12:20:59.384882 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7671 12:20:59.387928 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7672 12:20:59.391256 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7673 12:20:59.394394 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7674 12:20:59.394491 ==
7675 12:20:59.397637 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 12:20:59.404589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 12:20:59.404673 ==
7678 12:20:59.404737 DQS Delay:
7679 12:20:59.407523 DQS0 = 0, DQS1 = 0
7680 12:20:59.407607 DQM Delay:
7681 12:20:59.407669 DQM0 = 128, DQM1 = 124
7682 12:20:59.411020 DQ Delay:
7683 12:20:59.414655 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7684 12:20:59.417594 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7685 12:20:59.421091 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7686 12:20:59.424240 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7687 12:20:59.424321
7688 12:20:59.424383
7689 12:20:59.424441 ==
7690 12:20:59.427737 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 12:20:59.434207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 12:20:59.434291 ==
7693 12:20:59.434354
7694 12:20:59.434412
7695 12:20:59.434467 TX Vref Scan disable
7696 12:20:59.437616 == TX Byte 0 ==
7697 12:20:59.440811 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7698 12:20:59.444357 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7699 12:20:59.447732 == TX Byte 1 ==
7700 12:20:59.450756 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7701 12:20:59.453971 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7702 12:20:59.457840 ==
7703 12:20:59.460521 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 12:20:59.463878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 12:20:59.463956 ==
7706 12:20:59.476822
7707 12:20:59.480348 TX Vref early break, caculate TX vref
7708 12:20:59.483534 TX Vref=16, minBit 8, minWin=21, winSum=365
7709 12:20:59.487013 TX Vref=18, minBit 8, minWin=22, winSum=374
7710 12:20:59.490891 TX Vref=20, minBit 4, minWin=23, winSum=383
7711 12:20:59.493590 TX Vref=22, minBit 4, minWin=24, winSum=393
7712 12:20:59.497215 TX Vref=24, minBit 4, minWin=24, winSum=401
7713 12:20:59.503696 TX Vref=26, minBit 8, minWin=24, winSum=412
7714 12:20:59.507040 TX Vref=28, minBit 4, minWin=25, winSum=413
7715 12:20:59.510039 TX Vref=30, minBit 8, minWin=24, winSum=404
7716 12:20:59.513420 TX Vref=32, minBit 8, minWin=24, winSum=398
7717 12:20:59.516566 TX Vref=34, minBit 8, minWin=22, winSum=390
7718 12:20:59.523295 [TxChooseVref] Worse bit 4, Min win 25, Win sum 413, Final Vref 28
7719 12:20:59.523420
7720 12:20:59.526345 Final TX Range 0 Vref 28
7721 12:20:59.526446
7722 12:20:59.526535 ==
7723 12:20:59.529981 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 12:20:59.533299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 12:20:59.533401 ==
7726 12:20:59.533498
7727 12:20:59.533591
7728 12:20:59.536496 TX Vref Scan disable
7729 12:20:59.543059 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7730 12:20:59.543165 == TX Byte 0 ==
7731 12:20:59.546267 u2DelayCellOfst[0]=15 cells (4 PI)
7732 12:20:59.549746 u2DelayCellOfst[1]=22 cells (6 PI)
7733 12:20:59.553290 u2DelayCellOfst[2]=15 cells (4 PI)
7734 12:20:59.556265 u2DelayCellOfst[3]=15 cells (4 PI)
7735 12:20:59.559724 u2DelayCellOfst[4]=11 cells (3 PI)
7736 12:20:59.563202 u2DelayCellOfst[5]=0 cells (0 PI)
7737 12:20:59.566683 u2DelayCellOfst[6]=22 cells (6 PI)
7738 12:20:59.569586 u2DelayCellOfst[7]=18 cells (5 PI)
7739 12:20:59.573246 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7740 12:20:59.576213 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7741 12:20:59.579681 == TX Byte 1 ==
7742 12:20:59.583265 u2DelayCellOfst[8]=0 cells (0 PI)
7743 12:20:59.583395 u2DelayCellOfst[9]=0 cells (0 PI)
7744 12:20:59.586038 u2DelayCellOfst[10]=3 cells (1 PI)
7745 12:20:59.589464 u2DelayCellOfst[11]=3 cells (1 PI)
7746 12:20:59.592977 u2DelayCellOfst[12]=11 cells (3 PI)
7747 12:20:59.596507 u2DelayCellOfst[13]=7 cells (2 PI)
7748 12:20:59.599381 u2DelayCellOfst[14]=11 cells (3 PI)
7749 12:20:59.602871 u2DelayCellOfst[15]=11 cells (3 PI)
7750 12:20:59.606387 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7751 12:20:59.613279 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7752 12:20:59.613364 DramC Write-DBI on
7753 12:20:59.613428 ==
7754 12:20:59.616488 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 12:20:59.622996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 12:20:59.623078 ==
7757 12:20:59.623143
7758 12:20:59.623202
7759 12:20:59.623259 TX Vref Scan disable
7760 12:20:59.626595 == TX Byte 0 ==
7761 12:20:59.629669 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7762 12:20:59.633040 == TX Byte 1 ==
7763 12:20:59.636453 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7764 12:20:59.639873 DramC Write-DBI off
7765 12:20:59.639956
7766 12:20:59.640020 [DATLAT]
7767 12:20:59.640079 Freq=1600, CH0 RK0
7768 12:20:59.640138
7769 12:20:59.643597 DATLAT Default: 0xf
7770 12:20:59.646392 0, 0xFFFF, sum = 0
7771 12:20:59.646474 1, 0xFFFF, sum = 0
7772 12:20:59.649748 2, 0xFFFF, sum = 0
7773 12:20:59.649831 3, 0xFFFF, sum = 0
7774 12:20:59.653023 4, 0xFFFF, sum = 0
7775 12:20:59.653107 5, 0xFFFF, sum = 0
7776 12:20:59.656610 6, 0xFFFF, sum = 0
7777 12:20:59.656698 7, 0xFFFF, sum = 0
7778 12:20:59.659423 8, 0xFFFF, sum = 0
7779 12:20:59.659533 9, 0xFFFF, sum = 0
7780 12:20:59.663142 10, 0xFFFF, sum = 0
7781 12:20:59.663226 11, 0xFFFF, sum = 0
7782 12:20:59.665875 12, 0xFFFF, sum = 0
7783 12:20:59.665958 13, 0xEFFF, sum = 0
7784 12:20:59.669270 14, 0x0, sum = 1
7785 12:20:59.669355 15, 0x0, sum = 2
7786 12:20:59.672807 16, 0x0, sum = 3
7787 12:20:59.672890 17, 0x0, sum = 4
7788 12:20:59.675853 best_step = 15
7789 12:20:59.675966
7790 12:20:59.676030 ==
7791 12:20:59.679361 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 12:20:59.682677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 12:20:59.682759 ==
7794 12:20:59.685982 RX Vref Scan: 1
7795 12:20:59.686086
7796 12:20:59.686152 Set Vref Range= 24 -> 127
7797 12:20:59.686214
7798 12:20:59.689301 RX Vref 24 -> 127, step: 1
7799 12:20:59.689398
7800 12:20:59.692747 RX Delay 11 -> 252, step: 4
7801 12:20:59.692840
7802 12:20:59.695698 Set Vref, RX VrefLevel [Byte0]: 24
7803 12:20:59.699222 [Byte1]: 24
7804 12:20:59.699304
7805 12:20:59.702804 Set Vref, RX VrefLevel [Byte0]: 25
7806 12:20:59.705734 [Byte1]: 25
7807 12:20:59.709286
7808 12:20:59.709398 Set Vref, RX VrefLevel [Byte0]: 26
7809 12:20:59.712681 [Byte1]: 26
7810 12:20:59.717113
7811 12:20:59.717202 Set Vref, RX VrefLevel [Byte0]: 27
7812 12:20:59.720570 [Byte1]: 27
7813 12:20:59.724565
7814 12:20:59.724648 Set Vref, RX VrefLevel [Byte0]: 28
7815 12:20:59.727908 [Byte1]: 28
7816 12:20:59.732280
7817 12:20:59.732363 Set Vref, RX VrefLevel [Byte0]: 29
7818 12:20:59.735574 [Byte1]: 29
7819 12:20:59.739980
7820 12:20:59.740072 Set Vref, RX VrefLevel [Byte0]: 30
7821 12:20:59.743042 [Byte1]: 30
7822 12:20:59.747333
7823 12:20:59.747457 Set Vref, RX VrefLevel [Byte0]: 31
7824 12:20:59.751216 [Byte1]: 31
7825 12:20:59.754932
7826 12:20:59.755023 Set Vref, RX VrefLevel [Byte0]: 32
7827 12:20:59.758194 [Byte1]: 32
7828 12:20:59.762865
7829 12:20:59.762938 Set Vref, RX VrefLevel [Byte0]: 33
7830 12:20:59.765987 [Byte1]: 33
7831 12:20:59.770716
7832 12:20:59.770794 Set Vref, RX VrefLevel [Byte0]: 34
7833 12:20:59.773277 [Byte1]: 34
7834 12:20:59.777825
7835 12:20:59.777901 Set Vref, RX VrefLevel [Byte0]: 35
7836 12:20:59.781329 [Byte1]: 35
7837 12:20:59.785553
7838 12:20:59.785629 Set Vref, RX VrefLevel [Byte0]: 36
7839 12:20:59.788984 [Byte1]: 36
7840 12:20:59.793094
7841 12:20:59.793175 Set Vref, RX VrefLevel [Byte0]: 37
7842 12:20:59.796511 [Byte1]: 37
7843 12:20:59.800648
7844 12:20:59.800720 Set Vref, RX VrefLevel [Byte0]: 38
7845 12:20:59.804187 [Byte1]: 38
7846 12:20:59.808333
7847 12:20:59.808415 Set Vref, RX VrefLevel [Byte0]: 39
7848 12:20:59.812236 [Byte1]: 39
7849 12:20:59.816216
7850 12:20:59.816293 Set Vref, RX VrefLevel [Byte0]: 40
7851 12:20:59.819594 [Byte1]: 40
7852 12:20:59.823654
7853 12:20:59.823725 Set Vref, RX VrefLevel [Byte0]: 41
7854 12:20:59.826682 [Byte1]: 41
7855 12:20:59.831145
7856 12:20:59.831220 Set Vref, RX VrefLevel [Byte0]: 42
7857 12:20:59.834406 [Byte1]: 42
7858 12:20:59.838673
7859 12:20:59.838750 Set Vref, RX VrefLevel [Byte0]: 43
7860 12:20:59.842322 [Byte1]: 43
7861 12:20:59.846469
7862 12:20:59.846573 Set Vref, RX VrefLevel [Byte0]: 44
7863 12:20:59.849483 [Byte1]: 44
7864 12:20:59.854246
7865 12:20:59.854318 Set Vref, RX VrefLevel [Byte0]: 45
7866 12:20:59.857619 [Byte1]: 45
7867 12:20:59.861443
7868 12:20:59.861517 Set Vref, RX VrefLevel [Byte0]: 46
7869 12:20:59.865036 [Byte1]: 46
7870 12:20:59.869625
7871 12:20:59.869695 Set Vref, RX VrefLevel [Byte0]: 47
7872 12:20:59.872655 [Byte1]: 47
7873 12:20:59.876769
7874 12:20:59.876842 Set Vref, RX VrefLevel [Byte0]: 48
7875 12:20:59.880085 [Byte1]: 48
7876 12:20:59.884646
7877 12:20:59.884727 Set Vref, RX VrefLevel [Byte0]: 49
7878 12:20:59.887607 [Byte1]: 49
7879 12:20:59.891960
7880 12:20:59.892045 Set Vref, RX VrefLevel [Byte0]: 50
7881 12:20:59.895715 [Byte1]: 50
7882 12:20:59.899808
7883 12:20:59.899882 Set Vref, RX VrefLevel [Byte0]: 51
7884 12:20:59.903161 [Byte1]: 51
7885 12:20:59.907641
7886 12:20:59.907711 Set Vref, RX VrefLevel [Byte0]: 52
7887 12:20:59.910298 [Byte1]: 52
7888 12:20:59.914986
7889 12:20:59.915062 Set Vref, RX VrefLevel [Byte0]: 53
7890 12:20:59.917927 [Byte1]: 53
7891 12:20:59.922714
7892 12:20:59.922814 Set Vref, RX VrefLevel [Byte0]: 54
7893 12:20:59.926090 [Byte1]: 54
7894 12:20:59.930141
7895 12:20:59.930226 Set Vref, RX VrefLevel [Byte0]: 55
7896 12:20:59.933429 [Byte1]: 55
7897 12:20:59.937921
7898 12:20:59.938003 Set Vref, RX VrefLevel [Byte0]: 56
7899 12:20:59.940967 [Byte1]: 56
7900 12:20:59.945233
7901 12:20:59.945311 Set Vref, RX VrefLevel [Byte0]: 57
7902 12:20:59.948452 [Byte1]: 57
7903 12:20:59.953016
7904 12:20:59.953088 Set Vref, RX VrefLevel [Byte0]: 58
7905 12:20:59.956426 [Byte1]: 58
7906 12:20:59.961051
7907 12:20:59.961125 Set Vref, RX VrefLevel [Byte0]: 59
7908 12:20:59.963716 [Byte1]: 59
7909 12:20:59.968477
7910 12:20:59.968549 Set Vref, RX VrefLevel [Byte0]: 60
7911 12:20:59.971351 [Byte1]: 60
7912 12:20:59.976001
7913 12:20:59.976074 Set Vref, RX VrefLevel [Byte0]: 61
7914 12:20:59.979260 [Byte1]: 61
7915 12:20:59.983209
7916 12:20:59.983292 Set Vref, RX VrefLevel [Byte0]: 62
7917 12:20:59.986985 [Byte1]: 62
7918 12:20:59.991359
7919 12:20:59.991480 Set Vref, RX VrefLevel [Byte0]: 63
7920 12:20:59.994232 [Byte1]: 63
7921 12:20:59.998597
7922 12:20:59.998671 Set Vref, RX VrefLevel [Byte0]: 64
7923 12:21:00.002053 [Byte1]: 64
7924 12:21:00.006357
7925 12:21:00.006455 Set Vref, RX VrefLevel [Byte0]: 65
7926 12:21:00.009686 [Byte1]: 65
7927 12:21:00.013946
7928 12:21:00.014053 Set Vref, RX VrefLevel [Byte0]: 66
7929 12:21:00.017393 [Byte1]: 66
7930 12:21:00.021456
7931 12:21:00.021552 Set Vref, RX VrefLevel [Byte0]: 67
7932 12:21:00.025107 [Byte1]: 67
7933 12:21:00.029239
7934 12:21:00.029350 Set Vref, RX VrefLevel [Byte0]: 68
7935 12:21:00.032475 [Byte1]: 68
7936 12:21:00.036954
7937 12:21:00.037030 Set Vref, RX VrefLevel [Byte0]: 69
7938 12:21:00.039825 [Byte1]: 69
7939 12:21:00.044157
7940 12:21:00.044231 Set Vref, RX VrefLevel [Byte0]: 70
7941 12:21:00.047778 [Byte1]: 70
7942 12:21:00.052020
7943 12:21:00.052102 Set Vref, RX VrefLevel [Byte0]: 71
7944 12:21:00.055454 [Byte1]: 71
7945 12:21:00.059664
7946 12:21:00.059760 Set Vref, RX VrefLevel [Byte0]: 72
7947 12:21:00.062577 [Byte1]: 72
7948 12:21:00.066946
7949 12:21:00.067019 Set Vref, RX VrefLevel [Byte0]: 73
7950 12:21:00.070168 [Byte1]: 73
7951 12:21:00.074877
7952 12:21:00.074982 Set Vref, RX VrefLevel [Byte0]: 74
7953 12:21:00.077936 [Byte1]: 74
7954 12:21:00.082173
7955 12:21:00.082251 Set Vref, RX VrefLevel [Byte0]: 75
7956 12:21:00.085612 [Byte1]: 75
7957 12:21:00.089961
7958 12:21:00.090040 Set Vref, RX VrefLevel [Byte0]: 76
7959 12:21:00.093301 [Byte1]: 76
7960 12:21:00.097806
7961 12:21:00.097909 Final RX Vref Byte 0 = 64 to rank0
7962 12:21:00.101226 Final RX Vref Byte 1 = 58 to rank0
7963 12:21:00.104690 Final RX Vref Byte 0 = 64 to rank1
7964 12:21:00.107737 Final RX Vref Byte 1 = 58 to rank1==
7965 12:21:00.110871 Dram Type= 6, Freq= 0, CH_0, rank 0
7966 12:21:00.117680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 12:21:00.117764 ==
7968 12:21:00.117844 DQS Delay:
7969 12:21:00.117905 DQS0 = 0, DQS1 = 0
7970 12:21:00.120561 DQM Delay:
7971 12:21:00.120634 DQM0 = 126, DQM1 = 120
7972 12:21:00.123730 DQ Delay:
7973 12:21:00.127665 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7974 12:21:00.130570 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7975 12:21:00.133951 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7976 12:21:00.137308 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
7977 12:21:00.137395
7978 12:21:00.137458
7979 12:21:00.137516
7980 12:21:00.140472 [DramC_TX_OE_Calibration] TA2
7981 12:21:00.143496 Original DQ_B0 (3 6) =30, OEN = 27
7982 12:21:00.147012 Original DQ_B1 (3 6) =30, OEN = 27
7983 12:21:00.150557 24, 0x0, End_B0=24 End_B1=24
7984 12:21:00.150659 25, 0x0, End_B0=25 End_B1=25
7985 12:21:00.153825 26, 0x0, End_B0=26 End_B1=26
7986 12:21:00.157163 27, 0x0, End_B0=27 End_B1=27
7987 12:21:00.160481 28, 0x0, End_B0=28 End_B1=28
7988 12:21:00.164064 29, 0x0, End_B0=29 End_B1=29
7989 12:21:00.164163 30, 0x0, End_B0=30 End_B1=30
7990 12:21:00.166711 31, 0x5151, End_B0=30 End_B1=30
7991 12:21:00.170153 Byte0 end_step=30 best_step=27
7992 12:21:00.173659 Byte1 end_step=30 best_step=27
7993 12:21:00.176611 Byte0 TX OE(2T, 0.5T) = (3, 3)
7994 12:21:00.180205 Byte1 TX OE(2T, 0.5T) = (3, 3)
7995 12:21:00.180311
7996 12:21:00.180402
7997 12:21:00.186581 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
7998 12:21:00.190045 CH0 RK0: MR19=303, MR18=1111
7999 12:21:00.196608 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
8000 12:21:00.196711
8001 12:21:00.200111 ----->DramcWriteLeveling(PI) begin...
8002 12:21:00.200216 ==
8003 12:21:00.203354 Dram Type= 6, Freq= 0, CH_0, rank 1
8004 12:21:00.206691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 12:21:00.206796 ==
8006 12:21:00.209641 Write leveling (Byte 0): 33 => 33
8007 12:21:00.213228 Write leveling (Byte 1): 28 => 28
8008 12:21:00.216470 DramcWriteLeveling(PI) end<-----
8009 12:21:00.216594
8010 12:21:00.216686 ==
8011 12:21:00.219779 Dram Type= 6, Freq= 0, CH_0, rank 1
8012 12:21:00.222842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 12:21:00.226267 ==
8014 12:21:00.226371 [Gating] SW mode calibration
8015 12:21:00.236368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8016 12:21:00.239492 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8017 12:21:00.242749 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 12:21:00.249572 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 12:21:00.252613 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 12:21:00.256142 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8021 12:21:00.262383 1 4 16 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
8022 12:21:00.265687 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 12:21:00.269097 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 12:21:00.276134 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 12:21:00.278988 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 12:21:00.282558 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 12:21:00.289038 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8028 12:21:00.292659 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8029 12:21:00.295595 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (0 1) (0 0)
8030 12:21:00.302099 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
8031 12:21:00.305311 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 12:21:00.309071 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 12:21:00.315493 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 12:21:00.318651 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 12:21:00.322010 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8036 12:21:00.328431 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8037 12:21:00.331786 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8038 12:21:00.335296 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8039 12:21:00.341704 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 12:21:00.345039 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 12:21:00.348271 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 12:21:00.354750 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 12:21:00.358082 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8044 12:21:00.361273 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 12:21:00.368190 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 12:21:00.371535 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8047 12:21:00.375063 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 12:21:00.381636 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:21:00.384465 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:21:00.387921 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:21:00.394346 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:21:00.397822 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:21:00.401394 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:21:00.408144 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:21:00.411038 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:21:00.414225 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:21:00.420675 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:21:00.424036 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:21:00.427408 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:21:00.433788 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 12:21:00.437145 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8062 12:21:00.440649 Total UI for P1: 0, mck2ui 16
8063 12:21:00.443629 best dqsien dly found for B0: ( 1, 9, 12)
8064 12:21:00.447425 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8065 12:21:00.453616 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 12:21:00.457112 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 12:21:00.460941 Total UI for P1: 0, mck2ui 16
8068 12:21:00.463817 best dqsien dly found for B1: ( 1, 9, 22)
8069 12:21:00.466928 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8070 12:21:00.470533 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8071 12:21:00.470605
8072 12:21:00.473637 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8073 12:21:00.476774 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8074 12:21:00.480451 [Gating] SW calibration Done
8075 12:21:00.480534 ==
8076 12:21:00.483894 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 12:21:00.490401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 12:21:00.490534 ==
8079 12:21:00.490604 RX Vref Scan: 0
8080 12:21:00.490665
8081 12:21:00.493326 RX Vref 0 -> 0, step: 1
8082 12:21:00.493401
8083 12:21:00.496827 RX Delay 0 -> 252, step: 8
8084 12:21:00.499821 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8085 12:21:00.503309 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8086 12:21:00.507020 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8087 12:21:00.510269 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8088 12:21:00.516785 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8089 12:21:00.520256 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8090 12:21:00.523659 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8091 12:21:00.526609 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8092 12:21:00.529909 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8093 12:21:00.536449 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8094 12:21:00.540063 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8095 12:21:00.543243 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8096 12:21:00.546717 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8097 12:21:00.553088 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8098 12:21:00.556116 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8099 12:21:00.559519 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8100 12:21:00.559595 ==
8101 12:21:00.562634 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 12:21:00.566060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 12:21:00.566135 ==
8104 12:21:00.569545 DQS Delay:
8105 12:21:00.569619 DQS0 = 0, DQS1 = 0
8106 12:21:00.573101 DQM Delay:
8107 12:21:00.573176 DQM0 = 128, DQM1 = 120
8108 12:21:00.573238 DQ Delay:
8109 12:21:00.576490 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8110 12:21:00.583099 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8111 12:21:00.585828 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8112 12:21:00.589297 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8113 12:21:00.589373
8114 12:21:00.589435
8115 12:21:00.589493 ==
8116 12:21:00.592620 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 12:21:00.595843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 12:21:00.595920 ==
8119 12:21:00.595983
8120 12:21:00.596050
8121 12:21:00.599241 TX Vref Scan disable
8122 12:21:00.602641 == TX Byte 0 ==
8123 12:21:00.605913 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8124 12:21:00.609212 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8125 12:21:00.612938 == TX Byte 1 ==
8126 12:21:00.615680 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8127 12:21:00.619133 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8128 12:21:00.619204 ==
8129 12:21:00.622260 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 12:21:00.628610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 12:21:00.628691 ==
8132 12:21:00.640882
8133 12:21:00.644303 TX Vref early break, caculate TX vref
8134 12:21:00.647332 TX Vref=16, minBit 0, minWin=22, winSum=362
8135 12:21:00.650618 TX Vref=18, minBit 0, minWin=22, winSum=372
8136 12:21:00.653899 TX Vref=20, minBit 1, minWin=23, winSum=382
8137 12:21:00.657103 TX Vref=22, minBit 9, minWin=23, winSum=394
8138 12:21:00.660583 TX Vref=24, minBit 0, minWin=25, winSum=404
8139 12:21:00.667313 TX Vref=26, minBit 0, minWin=24, winSum=402
8140 12:21:00.670305 TX Vref=28, minBit 8, minWin=24, winSum=410
8141 12:21:00.673994 TX Vref=30, minBit 8, minWin=24, winSum=406
8142 12:21:00.677369 TX Vref=32, minBit 8, minWin=23, winSum=394
8143 12:21:00.680572 TX Vref=34, minBit 8, minWin=22, winSum=385
8144 12:21:00.687140 [TxChooseVref] Worse bit 0, Min win 25, Win sum 404, Final Vref 24
8145 12:21:00.687220
8146 12:21:00.690635 Final TX Range 0 Vref 24
8147 12:21:00.690714
8148 12:21:00.690811 ==
8149 12:21:00.694029 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 12:21:00.697079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 12:21:00.697171 ==
8152 12:21:00.697257
8153 12:21:00.697350
8154 12:21:00.700502 TX Vref Scan disable
8155 12:21:00.707222 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8156 12:21:00.707334 == TX Byte 0 ==
8157 12:21:00.710443 u2DelayCellOfst[0]=15 cells (4 PI)
8158 12:21:00.713617 u2DelayCellOfst[1]=18 cells (5 PI)
8159 12:21:00.717181 u2DelayCellOfst[2]=11 cells (3 PI)
8160 12:21:00.720384 u2DelayCellOfst[3]=11 cells (3 PI)
8161 12:21:00.723622 u2DelayCellOfst[4]=7 cells (2 PI)
8162 12:21:00.727131 u2DelayCellOfst[5]=0 cells (0 PI)
8163 12:21:00.730681 u2DelayCellOfst[6]=18 cells (5 PI)
8164 12:21:00.733534 u2DelayCellOfst[7]=18 cells (5 PI)
8165 12:21:00.736944 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8166 12:21:00.740404 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8167 12:21:00.743945 == TX Byte 1 ==
8168 12:21:00.744017 u2DelayCellOfst[8]=0 cells (0 PI)
8169 12:21:00.746743 u2DelayCellOfst[9]=0 cells (0 PI)
8170 12:21:00.750343 u2DelayCellOfst[10]=7 cells (2 PI)
8171 12:21:00.753256 u2DelayCellOfst[11]=3 cells (1 PI)
8172 12:21:00.756622 u2DelayCellOfst[12]=15 cells (4 PI)
8173 12:21:00.759967 u2DelayCellOfst[13]=15 cells (4 PI)
8174 12:21:00.763512 u2DelayCellOfst[14]=15 cells (4 PI)
8175 12:21:00.766832 u2DelayCellOfst[15]=11 cells (3 PI)
8176 12:21:00.770519 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8177 12:21:00.776409 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8178 12:21:00.776494 DramC Write-DBI on
8179 12:21:00.776558 ==
8180 12:21:00.780200 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 12:21:00.786391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 12:21:00.786469 ==
8183 12:21:00.786533
8184 12:21:00.786591
8185 12:21:00.786649 TX Vref Scan disable
8186 12:21:00.790483 == TX Byte 0 ==
8187 12:21:00.793766 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8188 12:21:00.796698 == TX Byte 1 ==
8189 12:21:00.800068 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8190 12:21:00.803456 DramC Write-DBI off
8191 12:21:00.803527
8192 12:21:00.803591 [DATLAT]
8193 12:21:00.803649 Freq=1600, CH0 RK1
8194 12:21:00.803705
8195 12:21:00.806932 DATLAT Default: 0xf
8196 12:21:00.807031 0, 0xFFFF, sum = 0
8197 12:21:00.810298 1, 0xFFFF, sum = 0
8198 12:21:00.813239 2, 0xFFFF, sum = 0
8199 12:21:00.813331 3, 0xFFFF, sum = 0
8200 12:21:00.816646 4, 0xFFFF, sum = 0
8201 12:21:00.816719 5, 0xFFFF, sum = 0
8202 12:21:00.819894 6, 0xFFFF, sum = 0
8203 12:21:00.819969 7, 0xFFFF, sum = 0
8204 12:21:00.823463 8, 0xFFFF, sum = 0
8205 12:21:00.823536 9, 0xFFFF, sum = 0
8206 12:21:00.826908 10, 0xFFFF, sum = 0
8207 12:21:00.827011 11, 0xFFFF, sum = 0
8208 12:21:00.829951 12, 0xFFFF, sum = 0
8209 12:21:00.830024 13, 0xCFFF, sum = 0
8210 12:21:00.833393 14, 0x0, sum = 1
8211 12:21:00.833468 15, 0x0, sum = 2
8212 12:21:00.836434 16, 0x0, sum = 3
8213 12:21:00.836504 17, 0x0, sum = 4
8214 12:21:00.839899 best_step = 15
8215 12:21:00.839969
8216 12:21:00.840029 ==
8217 12:21:00.843234 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 12:21:00.846642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 12:21:00.846718 ==
8220 12:21:00.849561 RX Vref Scan: 0
8221 12:21:00.849638
8222 12:21:00.849700 RX Vref 0 -> 0, step: 1
8223 12:21:00.849757
8224 12:21:00.853310 RX Delay 3 -> 252, step: 4
8225 12:21:00.859635 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8226 12:21:00.863097 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8227 12:21:00.866534 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8228 12:21:00.869523 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8229 12:21:00.872716 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8230 12:21:00.876140 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8231 12:21:00.883115 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8232 12:21:00.886606 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8233 12:21:00.889522 iDelay=191, Bit 8, Center 110 (51 ~ 170) 120
8234 12:21:00.892705 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8235 12:21:00.896353 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8236 12:21:00.903058 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8237 12:21:00.906246 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8238 12:21:00.909567 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8239 12:21:00.912964 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8240 12:21:00.919292 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8241 12:21:00.919429 ==
8242 12:21:00.922861 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 12:21:00.926260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 12:21:00.926336 ==
8245 12:21:00.926399 DQS Delay:
8246 12:21:00.929797 DQS0 = 0, DQS1 = 0
8247 12:21:00.929896 DQM Delay:
8248 12:21:00.932689 DQM0 = 124, DQM1 = 118
8249 12:21:00.932785 DQ Delay:
8250 12:21:00.936260 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8251 12:21:00.939473 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8252 12:21:00.943034 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8253 12:21:00.945823 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8254 12:21:00.945926
8255 12:21:00.946015
8256 12:21:00.949261
8257 12:21:00.949339 [DramC_TX_OE_Calibration] TA2
8258 12:21:00.952456 Original DQ_B0 (3 6) =30, OEN = 27
8259 12:21:00.955796 Original DQ_B1 (3 6) =30, OEN = 27
8260 12:21:00.958929 24, 0x0, End_B0=24 End_B1=24
8261 12:21:00.962238 25, 0x0, End_B0=25 End_B1=25
8262 12:21:00.965721 26, 0x0, End_B0=26 End_B1=26
8263 12:21:00.965799 27, 0x0, End_B0=27 End_B1=27
8264 12:21:00.969042 28, 0x0, End_B0=28 End_B1=28
8265 12:21:00.972026 29, 0x0, End_B0=29 End_B1=29
8266 12:21:00.975382 30, 0x0, End_B0=30 End_B1=30
8267 12:21:00.978848 31, 0x4141, End_B0=30 End_B1=30
8268 12:21:00.978926 Byte0 end_step=30 best_step=27
8269 12:21:00.982502 Byte1 end_step=30 best_step=27
8270 12:21:00.985139 Byte0 TX OE(2T, 0.5T) = (3, 3)
8271 12:21:00.988561 Byte1 TX OE(2T, 0.5T) = (3, 3)
8272 12:21:00.988638
8273 12:21:00.988700
8274 12:21:00.998802 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8275 12:21:00.998901 CH0 RK1: MR19=303, MR18=210F
8276 12:21:01.005006 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8277 12:21:01.008583 [RxdqsGatingPostProcess] freq 1600
8278 12:21:01.015320 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8279 12:21:01.018755 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 12:21:01.021592 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 12:21:01.025459 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 12:21:01.025533 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 12:21:01.028409 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 12:21:01.031645 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 12:21:01.035311 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 12:21:01.038231 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 12:21:01.041568 Pre-setting of DQS Precalculation
8288 12:21:01.048120 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8289 12:21:01.048216 ==
8290 12:21:01.051745 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 12:21:01.055526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 12:21:01.055626 ==
8293 12:21:01.061829 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 12:21:01.064856 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 12:21:01.068416 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 12:21:01.074744 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 12:21:01.083211 [CA 0] Center 41 (12~71) winsize 60
8298 12:21:01.087072 [CA 1] Center 42 (13~72) winsize 60
8299 12:21:01.089841 [CA 2] Center 37 (9~66) winsize 58
8300 12:21:01.093230 [CA 3] Center 37 (8~66) winsize 59
8301 12:21:01.096831 [CA 4] Center 37 (8~67) winsize 60
8302 12:21:01.099900 [CA 5] Center 36 (7~66) winsize 60
8303 12:21:01.099978
8304 12:21:01.103304 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8305 12:21:01.103437
8306 12:21:01.106797 [CATrainingPosCal] consider 1 rank data
8307 12:21:01.109678 u2DelayCellTimex100 = 258/100 ps
8308 12:21:01.113184 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8309 12:21:01.120102 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8310 12:21:01.123041 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8311 12:21:01.126619 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8312 12:21:01.129984 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8313 12:21:01.133449 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 12:21:01.133524
8315 12:21:01.136588 CA PerBit enable=1, Macro0, CA PI delay=36
8316 12:21:01.136665
8317 12:21:01.139980 [CBTSetCACLKResult] CA Dly = 36
8318 12:21:01.143298 CS Dly: 9 (0~40)
8319 12:21:01.146671 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 12:21:01.149596 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 12:21:01.149669 ==
8322 12:21:01.153048 Dram Type= 6, Freq= 0, CH_1, rank 1
8323 12:21:01.156463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 12:21:01.156538 ==
8325 12:21:01.162954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 12:21:01.166549 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 12:21:01.173015 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 12:21:01.176268 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 12:21:01.186167 [CA 0] Center 42 (13~72) winsize 60
8330 12:21:01.189806 [CA 1] Center 42 (13~72) winsize 60
8331 12:21:01.192828 [CA 2] Center 38 (9~67) winsize 59
8332 12:21:01.196232 [CA 3] Center 36 (7~66) winsize 60
8333 12:21:01.199564 [CA 4] Center 38 (8~68) winsize 61
8334 12:21:01.202934 [CA 5] Center 36 (6~67) winsize 62
8335 12:21:01.203006
8336 12:21:01.206155 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8337 12:21:01.206227
8338 12:21:01.209476 [CATrainingPosCal] consider 2 rank data
8339 12:21:01.213039 u2DelayCellTimex100 = 258/100 ps
8340 12:21:01.215989 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8341 12:21:01.222840 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8342 12:21:01.226356 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8343 12:21:01.229208 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8344 12:21:01.232706 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8345 12:21:01.236238 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8346 12:21:01.236310
8347 12:21:01.239245 CA PerBit enable=1, Macro0, CA PI delay=36
8348 12:21:01.239313
8349 12:21:01.242397 [CBTSetCACLKResult] CA Dly = 36
8350 12:21:01.246131 CS Dly: 10 (0~43)
8351 12:21:01.249117 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 12:21:01.252629 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 12:21:01.252704
8354 12:21:01.255667 ----->DramcWriteLeveling(PI) begin...
8355 12:21:01.255743 ==
8356 12:21:01.259009 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 12:21:01.266145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 12:21:01.266218 ==
8359 12:21:01.269104 Write leveling (Byte 0): 25 => 25
8360 12:21:01.272735 Write leveling (Byte 1): 27 => 27
8361 12:21:01.272804 DramcWriteLeveling(PI) end<-----
8362 12:21:01.272868
8363 12:21:01.275625 ==
8364 12:21:01.278939 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 12:21:01.282183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 12:21:01.282253 ==
8367 12:21:01.285779 [Gating] SW mode calibration
8368 12:21:01.292104 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8369 12:21:01.295497 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8370 12:21:01.301994 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 12:21:01.305427 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:21:01.308985 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 12:21:01.315168 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 12:21:01.318422 1 4 16 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8375 12:21:01.321955 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 12:21:01.328708 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 12:21:01.331652 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:21:01.335197 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:21:01.341749 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 12:21:01.345504 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 12:21:01.348267 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8382 12:21:01.354797 1 5 16 | B1->B0 | 2929 2c2b | 0 1 | (1 0) (1 0)
8383 12:21:01.358342 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 12:21:01.361453 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:21:01.368601 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8386 12:21:01.371492 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:21:01.374969 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 12:21:01.381644 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 12:21:01.385002 1 6 12 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
8390 12:21:01.388336 1 6 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8391 12:21:01.394780 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:21:01.398027 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:21:01.401572 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:21:01.407850 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:21:01.411415 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:21:01.414352 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 12:21:01.421244 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 12:21:01.424482 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 12:21:01.427720 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8400 12:21:01.434308 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:21:01.437806 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:21:01.441347 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:21:01.447941 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:21:01.451325 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:21:01.454273 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:21:01.460958 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:21:01.464436 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:21:01.467523 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:21:01.474005 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:21:01.477795 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:21:01.480815 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:21:01.487570 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:21:01.491008 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8414 12:21:01.494296 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8415 12:21:01.497293 Total UI for P1: 0, mck2ui 16
8416 12:21:01.500747 best dqsien dly found for B1: ( 1, 9, 12)
8417 12:21:01.504206 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 12:21:01.507738 Total UI for P1: 0, mck2ui 16
8419 12:21:01.510987 best dqsien dly found for B0: ( 1, 9, 16)
8420 12:21:01.514434 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8421 12:21:01.517247 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8422 12:21:01.520788
8423 12:21:01.523732 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8424 12:21:01.527110 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8425 12:21:01.530491 [Gating] SW calibration Done
8426 12:21:01.530572 ==
8427 12:21:01.533830 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 12:21:01.537447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 12:21:01.537534 ==
8430 12:21:01.540481 RX Vref Scan: 0
8431 12:21:01.540562
8432 12:21:01.540626 RX Vref 0 -> 0, step: 1
8433 12:21:01.540688
8434 12:21:01.543903 RX Delay 0 -> 252, step: 8
8435 12:21:01.547763 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8436 12:21:01.550564 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8437 12:21:01.557318 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8438 12:21:01.560560 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8439 12:21:01.563820 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8440 12:21:01.567274 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8441 12:21:01.570299 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8442 12:21:01.577097 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8443 12:21:01.580457 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8444 12:21:01.583351 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8445 12:21:01.586937 iDelay=208, Bit 10, Center 127 (80 ~ 175) 96
8446 12:21:01.590198 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8447 12:21:01.597040 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8448 12:21:01.599981 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8449 12:21:01.603431 iDelay=208, Bit 14, Center 131 (80 ~ 183) 104
8450 12:21:01.607311 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8451 12:21:01.607419 ==
8452 12:21:01.609921 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 12:21:01.617166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 12:21:01.617250 ==
8455 12:21:01.617315 DQS Delay:
8456 12:21:01.619792 DQS0 = 0, DQS1 = 0
8457 12:21:01.619900 DQM Delay:
8458 12:21:01.623133 DQM0 = 132, DQM1 = 126
8459 12:21:01.623214 DQ Delay:
8460 12:21:01.626722 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8461 12:21:01.629663 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8462 12:21:01.633167 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8463 12:21:01.636485 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8464 12:21:01.636568
8465 12:21:01.636632
8466 12:21:01.636691 ==
8467 12:21:01.639992 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 12:21:01.646166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 12:21:01.646251 ==
8470 12:21:01.646316
8471 12:21:01.646375
8472 12:21:01.646431 TX Vref Scan disable
8473 12:21:01.650057 == TX Byte 0 ==
8474 12:21:01.652996 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8475 12:21:01.659864 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8476 12:21:01.659952 == TX Byte 1 ==
8477 12:21:01.662791 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8478 12:21:01.669896 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8479 12:21:01.669982 ==
8480 12:21:01.672871 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 12:21:01.676526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 12:21:01.676611 ==
8483 12:21:01.689557
8484 12:21:01.693327 TX Vref early break, caculate TX vref
8485 12:21:01.696464 TX Vref=16, minBit 11, minWin=21, winSum=362
8486 12:21:01.699549 TX Vref=18, minBit 11, minWin=22, winSum=376
8487 12:21:01.702682 TX Vref=20, minBit 13, minWin=23, winSum=385
8488 12:21:01.705967 TX Vref=22, minBit 5, minWin=23, winSum=390
8489 12:21:01.709756 TX Vref=24, minBit 1, minWin=22, winSum=398
8490 12:21:01.716386 TX Vref=26, minBit 5, minWin=24, winSum=413
8491 12:21:01.719496 TX Vref=28, minBit 6, minWin=24, winSum=418
8492 12:21:01.723097 TX Vref=30, minBit 6, minWin=24, winSum=413
8493 12:21:01.725991 TX Vref=32, minBit 0, minWin=23, winSum=405
8494 12:21:01.729581 TX Vref=34, minBit 0, minWin=23, winSum=397
8495 12:21:01.732796 TX Vref=36, minBit 0, minWin=23, winSum=383
8496 12:21:01.739401 [TxChooseVref] Worse bit 6, Min win 24, Win sum 418, Final Vref 28
8497 12:21:01.739521
8498 12:21:01.742717 Final TX Range 0 Vref 28
8499 12:21:01.742807
8500 12:21:01.742871 ==
8501 12:21:01.746264 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 12:21:01.749146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 12:21:01.749234 ==
8504 12:21:01.752648
8505 12:21:01.752732
8506 12:21:01.752796 TX Vref Scan disable
8507 12:21:01.759296 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8508 12:21:01.759446 == TX Byte 0 ==
8509 12:21:01.762633 u2DelayCellOfst[0]=22 cells (6 PI)
8510 12:21:01.765649 u2DelayCellOfst[1]=15 cells (4 PI)
8511 12:21:01.769081 u2DelayCellOfst[2]=0 cells (0 PI)
8512 12:21:01.772525 u2DelayCellOfst[3]=7 cells (2 PI)
8513 12:21:01.776019 u2DelayCellOfst[4]=11 cells (3 PI)
8514 12:21:01.779041 u2DelayCellOfst[5]=26 cells (7 PI)
8515 12:21:01.782692 u2DelayCellOfst[6]=26 cells (7 PI)
8516 12:21:01.785457 u2DelayCellOfst[7]=11 cells (3 PI)
8517 12:21:01.788813 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8518 12:21:01.792667 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8519 12:21:01.795754 == TX Byte 1 ==
8520 12:21:01.799154 u2DelayCellOfst[8]=0 cells (0 PI)
8521 12:21:01.802138 u2DelayCellOfst[9]=3 cells (1 PI)
8522 12:21:01.805865 u2DelayCellOfst[10]=11 cells (3 PI)
8523 12:21:01.809114 u2DelayCellOfst[11]=7 cells (2 PI)
8524 12:21:01.811926 u2DelayCellOfst[12]=15 cells (4 PI)
8525 12:21:01.815250 u2DelayCellOfst[13]=18 cells (5 PI)
8526 12:21:01.815359 u2DelayCellOfst[14]=18 cells (5 PI)
8527 12:21:01.818658 u2DelayCellOfst[15]=18 cells (5 PI)
8528 12:21:01.825234 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8529 12:21:01.829009 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8530 12:21:01.831856 DramC Write-DBI on
8531 12:21:01.831937 ==
8532 12:21:01.835267 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 12:21:01.838691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 12:21:01.838800 ==
8535 12:21:01.838891
8536 12:21:01.838981
8537 12:21:01.841896 TX Vref Scan disable
8538 12:21:01.842002 == TX Byte 0 ==
8539 12:21:01.848459 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8540 12:21:01.848597 == TX Byte 1 ==
8541 12:21:01.852029 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8542 12:21:01.855015 DramC Write-DBI off
8543 12:21:01.855128
8544 12:21:01.855219 [DATLAT]
8545 12:21:01.858040 Freq=1600, CH1 RK0
8546 12:21:01.858126
8547 12:21:01.858190 DATLAT Default: 0xf
8548 12:21:01.861554 0, 0xFFFF, sum = 0
8549 12:21:01.861672 1, 0xFFFF, sum = 0
8550 12:21:01.864812 2, 0xFFFF, sum = 0
8551 12:21:01.868260 3, 0xFFFF, sum = 0
8552 12:21:01.868352 4, 0xFFFF, sum = 0
8553 12:21:01.871641 5, 0xFFFF, sum = 0
8554 12:21:01.871757 6, 0xFFFF, sum = 0
8555 12:21:01.875231 7, 0xFFFF, sum = 0
8556 12:21:01.875346 8, 0xFFFF, sum = 0
8557 12:21:01.878206 9, 0xFFFF, sum = 0
8558 12:21:01.878312 10, 0xFFFF, sum = 0
8559 12:21:01.881448 11, 0xFFFF, sum = 0
8560 12:21:01.881536 12, 0xFFFF, sum = 0
8561 12:21:01.884772 13, 0x8FFF, sum = 0
8562 12:21:01.884860 14, 0x0, sum = 1
8563 12:21:01.888334 15, 0x0, sum = 2
8564 12:21:01.888421 16, 0x0, sum = 3
8565 12:21:01.891220 17, 0x0, sum = 4
8566 12:21:01.891305 best_step = 15
8567 12:21:01.891379
8568 12:21:01.891471 ==
8569 12:21:01.894723 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 12:21:01.897862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 12:21:01.901785 ==
8572 12:21:01.901884 RX Vref Scan: 1
8573 12:21:01.901950
8574 12:21:01.905078 Set Vref Range= 24 -> 127
8575 12:21:01.905166
8576 12:21:01.905232 RX Vref 24 -> 127, step: 1
8577 12:21:01.908443
8578 12:21:01.908526 RX Delay 11 -> 252, step: 4
8579 12:21:01.908590
8580 12:21:01.911326 Set Vref, RX VrefLevel [Byte0]: 24
8581 12:21:01.914804 [Byte1]: 24
8582 12:21:01.918281
8583 12:21:01.918361 Set Vref, RX VrefLevel [Byte0]: 25
8584 12:21:01.922145 [Byte1]: 25
8585 12:21:01.926048
8586 12:21:01.926128 Set Vref, RX VrefLevel [Byte0]: 26
8587 12:21:01.929487 [Byte1]: 26
8588 12:21:01.933756
8589 12:21:01.933835 Set Vref, RX VrefLevel [Byte0]: 27
8590 12:21:01.937037 [Byte1]: 27
8591 12:21:01.941050
8592 12:21:01.941130 Set Vref, RX VrefLevel [Byte0]: 28
8593 12:21:01.944739 [Byte1]: 28
8594 12:21:01.949070
8595 12:21:01.949151 Set Vref, RX VrefLevel [Byte0]: 29
8596 12:21:01.952465 [Byte1]: 29
8597 12:21:01.956561
8598 12:21:01.956647 Set Vref, RX VrefLevel [Byte0]: 30
8599 12:21:01.960057 [Byte1]: 30
8600 12:21:01.964191
8601 12:21:01.964270 Set Vref, RX VrefLevel [Byte0]: 31
8602 12:21:01.967527 [Byte1]: 31
8603 12:21:01.971877
8604 12:21:01.971956 Set Vref, RX VrefLevel [Byte0]: 32
8605 12:21:01.974841 [Byte1]: 32
8606 12:21:01.979286
8607 12:21:01.979426 Set Vref, RX VrefLevel [Byte0]: 33
8608 12:21:01.982810 [Byte1]: 33
8609 12:21:01.986707
8610 12:21:01.986794 Set Vref, RX VrefLevel [Byte0]: 34
8611 12:21:01.990302 [Byte1]: 34
8612 12:21:01.994872
8613 12:21:01.994951 Set Vref, RX VrefLevel [Byte0]: 35
8614 12:21:01.997857 [Byte1]: 35
8615 12:21:02.002061
8616 12:21:02.002167 Set Vref, RX VrefLevel [Byte0]: 36
8617 12:21:02.005763 [Byte1]: 36
8618 12:21:02.010013
8619 12:21:02.010093 Set Vref, RX VrefLevel [Byte0]: 37
8620 12:21:02.013301 [Byte1]: 37
8621 12:21:02.017252
8622 12:21:02.017332 Set Vref, RX VrefLevel [Byte0]: 38
8623 12:21:02.020716 [Byte1]: 38
8624 12:21:02.025401
8625 12:21:02.025487 Set Vref, RX VrefLevel [Byte0]: 39
8626 12:21:02.028314 [Byte1]: 39
8627 12:21:02.032890
8628 12:21:02.032970 Set Vref, RX VrefLevel [Byte0]: 40
8629 12:21:02.036344 [Byte1]: 40
8630 12:21:02.040433
8631 12:21:02.040513 Set Vref, RX VrefLevel [Byte0]: 41
8632 12:21:02.043642 [Byte1]: 41
8633 12:21:02.048027
8634 12:21:02.048109 Set Vref, RX VrefLevel [Byte0]: 42
8635 12:21:02.051448 [Byte1]: 42
8636 12:21:02.055277
8637 12:21:02.055358 Set Vref, RX VrefLevel [Byte0]: 43
8638 12:21:02.058605 [Byte1]: 43
8639 12:21:02.063330
8640 12:21:02.063461 Set Vref, RX VrefLevel [Byte0]: 44
8641 12:21:02.066309 [Byte1]: 44
8642 12:21:02.071016
8643 12:21:02.071097 Set Vref, RX VrefLevel [Byte0]: 45
8644 12:21:02.073766 [Byte1]: 45
8645 12:21:02.078494
8646 12:21:02.078575 Set Vref, RX VrefLevel [Byte0]: 46
8647 12:21:02.081771 [Byte1]: 46
8648 12:21:02.085725
8649 12:21:02.085807 Set Vref, RX VrefLevel [Byte0]: 47
8650 12:21:02.089198 [Byte1]: 47
8651 12:21:02.093399
8652 12:21:02.093480 Set Vref, RX VrefLevel [Byte0]: 48
8653 12:21:02.097263 [Byte1]: 48
8654 12:21:02.100928
8655 12:21:02.101009 Set Vref, RX VrefLevel [Byte0]: 49
8656 12:21:02.104429 [Byte1]: 49
8657 12:21:02.108598
8658 12:21:02.108679 Set Vref, RX VrefLevel [Byte0]: 50
8659 12:21:02.112274 [Byte1]: 50
8660 12:21:02.116426
8661 12:21:02.116506 Set Vref, RX VrefLevel [Byte0]: 51
8662 12:21:02.119544 [Byte1]: 51
8663 12:21:02.124003
8664 12:21:02.124083 Set Vref, RX VrefLevel [Byte0]: 52
8665 12:21:02.127331 [Byte1]: 52
8666 12:21:02.131313
8667 12:21:02.131419 Set Vref, RX VrefLevel [Byte0]: 53
8668 12:21:02.134927 [Byte1]: 53
8669 12:21:02.138896
8670 12:21:02.138977 Set Vref, RX VrefLevel [Byte0]: 54
8671 12:21:02.142272 [Byte1]: 54
8672 12:21:02.146572
8673 12:21:02.146653 Set Vref, RX VrefLevel [Byte0]: 55
8674 12:21:02.149843 [Byte1]: 55
8675 12:21:02.154567
8676 12:21:02.154648 Set Vref, RX VrefLevel [Byte0]: 56
8677 12:21:02.157802 [Byte1]: 56
8678 12:21:02.161802
8679 12:21:02.161882 Set Vref, RX VrefLevel [Byte0]: 57
8680 12:21:02.165224 [Byte1]: 57
8681 12:21:02.169545
8682 12:21:02.169625 Set Vref, RX VrefLevel [Byte0]: 58
8683 12:21:02.172858 [Byte1]: 58
8684 12:21:02.177234
8685 12:21:02.177314 Set Vref, RX VrefLevel [Byte0]: 59
8686 12:21:02.180828 [Byte1]: 59
8687 12:21:02.184690
8688 12:21:02.184794 Set Vref, RX VrefLevel [Byte0]: 60
8689 12:21:02.188253 [Byte1]: 60
8690 12:21:02.192902
8691 12:21:02.192984 Set Vref, RX VrefLevel [Byte0]: 61
8692 12:21:02.195647 [Byte1]: 61
8693 12:21:02.199787
8694 12:21:02.199869 Set Vref, RX VrefLevel [Byte0]: 62
8695 12:21:02.203273 [Byte1]: 62
8696 12:21:02.207957
8697 12:21:02.208039 Set Vref, RX VrefLevel [Byte0]: 63
8698 12:21:02.211251 [Byte1]: 63
8699 12:21:02.215182
8700 12:21:02.215262 Set Vref, RX VrefLevel [Byte0]: 64
8701 12:21:02.218670 [Byte1]: 64
8702 12:21:02.223059
8703 12:21:02.223154 Set Vref, RX VrefLevel [Byte0]: 65
8704 12:21:02.226325 [Byte1]: 65
8705 12:21:02.230917
8706 12:21:02.230997 Set Vref, RX VrefLevel [Byte0]: 66
8707 12:21:02.233781 [Byte1]: 66
8708 12:21:02.238697
8709 12:21:02.238782 Set Vref, RX VrefLevel [Byte0]: 67
8710 12:21:02.241250 [Byte1]: 67
8711 12:21:02.245815
8712 12:21:02.245897 Set Vref, RX VrefLevel [Byte0]: 68
8713 12:21:02.249248 [Byte1]: 68
8714 12:21:02.253175
8715 12:21:02.253258 Set Vref, RX VrefLevel [Byte0]: 69
8716 12:21:02.256698 [Byte1]: 69
8717 12:21:02.261131
8718 12:21:02.261215 Set Vref, RX VrefLevel [Byte0]: 70
8719 12:21:02.264277 [Byte1]: 70
8720 12:21:02.268371
8721 12:21:02.268451 Final RX Vref Byte 0 = 57 to rank0
8722 12:21:02.271954 Final RX Vref Byte 1 = 54 to rank0
8723 12:21:02.275160 Final RX Vref Byte 0 = 57 to rank1
8724 12:21:02.278272 Final RX Vref Byte 1 = 54 to rank1==
8725 12:21:02.281818 Dram Type= 6, Freq= 0, CH_1, rank 0
8726 12:21:02.288299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 12:21:02.288391 ==
8728 12:21:02.288455 DQS Delay:
8729 12:21:02.288514 DQS0 = 0, DQS1 = 0
8730 12:21:02.291680 DQM Delay:
8731 12:21:02.291778 DQM0 = 131, DQM1 = 123
8732 12:21:02.295140 DQ Delay:
8733 12:21:02.298685 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8734 12:21:02.302149 DQ4 =130, DQ5 =140, DQ6 =142, DQ7 =128
8735 12:21:02.305303 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =118
8736 12:21:02.308629 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8737 12:21:02.308709
8738 12:21:02.308772
8739 12:21:02.308830
8740 12:21:02.312084 [DramC_TX_OE_Calibration] TA2
8741 12:21:02.315282 Original DQ_B0 (3 6) =30, OEN = 27
8742 12:21:02.318636 Original DQ_B1 (3 6) =30, OEN = 27
8743 12:21:02.321747 24, 0x0, End_B0=24 End_B1=24
8744 12:21:02.321830 25, 0x0, End_B0=25 End_B1=25
8745 12:21:02.325085 26, 0x0, End_B0=26 End_B1=26
8746 12:21:02.328416 27, 0x0, End_B0=27 End_B1=27
8747 12:21:02.331770 28, 0x0, End_B0=28 End_B1=28
8748 12:21:02.334885 29, 0x0, End_B0=29 End_B1=29
8749 12:21:02.334968 30, 0x0, End_B0=30 End_B1=30
8750 12:21:02.338531 31, 0x4141, End_B0=30 End_B1=30
8751 12:21:02.341682 Byte0 end_step=30 best_step=27
8752 12:21:02.345187 Byte1 end_step=30 best_step=27
8753 12:21:02.348058 Byte0 TX OE(2T, 0.5T) = (3, 3)
8754 12:21:02.351504 Byte1 TX OE(2T, 0.5T) = (3, 3)
8755 12:21:02.351584
8756 12:21:02.351647
8757 12:21:02.358284 [DQSOSCAuto] RK0, (LSB)MR18= 0x60a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8758 12:21:02.361237 CH1 RK0: MR19=303, MR18=60A
8759 12:21:02.368180 CH1_RK0: MR19=0x303, MR18=0x60A, DQSOSC=404, MR23=63, INC=22, DEC=15
8760 12:21:02.368261
8761 12:21:02.371326 ----->DramcWriteLeveling(PI) begin...
8762 12:21:02.371429 ==
8763 12:21:02.374736 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 12:21:02.377858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 12:21:02.377940 ==
8766 12:21:02.381155 Write leveling (Byte 0): 24 => 24
8767 12:21:02.384472 Write leveling (Byte 1): 28 => 28
8768 12:21:02.388066 DramcWriteLeveling(PI) end<-----
8769 12:21:02.388147
8770 12:21:02.388210 ==
8771 12:21:02.391325 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 12:21:02.394468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 12:21:02.394548 ==
8774 12:21:02.398055 [Gating] SW mode calibration
8775 12:21:02.404560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8776 12:21:02.411047 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8777 12:21:02.414353 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 12:21:02.417490 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 12:21:02.424491 1 4 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8780 12:21:02.427311 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8781 12:21:02.430987 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 12:21:02.437819 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 12:21:02.440736 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 12:21:02.444128 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 12:21:02.450976 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 12:21:02.454309 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 12:21:02.457683 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
8788 12:21:02.463892 1 5 12 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
8789 12:21:02.467326 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 12:21:02.470874 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 12:21:02.477400 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 12:21:02.480880 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 12:21:02.484056 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 12:21:02.490352 1 6 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8795 12:21:02.493761 1 6 8 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8796 12:21:02.497025 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 12:21:02.503977 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 12:21:02.506877 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 12:21:02.510290 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 12:21:02.516982 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 12:21:02.520539 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 12:21:02.523381 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 12:21:02.530359 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8804 12:21:02.533442 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8805 12:21:02.536680 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8806 12:21:02.543609 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 12:21:02.546586 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 12:21:02.550249 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 12:21:02.556607 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 12:21:02.559682 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:21:02.563294 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 12:21:02.569953 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:21:02.573181 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:21:02.576436 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:21:02.583261 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:21:02.586570 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:21:02.590349 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:21:02.596521 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:21:02.599661 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8820 12:21:02.603246 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 12:21:02.606461 Total UI for P1: 0, mck2ui 16
8822 12:21:02.609584 best dqsien dly found for B0: ( 1, 9, 8)
8823 12:21:02.612953 Total UI for P1: 0, mck2ui 16
8824 12:21:02.616645 best dqsien dly found for B1: ( 1, 9, 10)
8825 12:21:02.619412 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8826 12:21:02.623020 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8827 12:21:02.623100
8828 12:21:02.626513 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8829 12:21:02.633010 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8830 12:21:02.633090 [Gating] SW calibration Done
8831 12:21:02.633154 ==
8832 12:21:02.636389 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 12:21:02.642707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 12:21:02.642787 ==
8835 12:21:02.642851 RX Vref Scan: 0
8836 12:21:02.642909
8837 12:21:02.646237 RX Vref 0 -> 0, step: 1
8838 12:21:02.646317
8839 12:21:02.649753 RX Delay 0 -> 252, step: 8
8840 12:21:02.652629 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8841 12:21:02.656007 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8842 12:21:02.659620 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8843 12:21:02.663428 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8844 12:21:02.669509 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8845 12:21:02.672630 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8846 12:21:02.676620 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8847 12:21:02.679329 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8848 12:21:02.683002 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8849 12:21:02.689482 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8850 12:21:02.692592 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8851 12:21:02.696504 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8852 12:21:02.699348 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8853 12:21:02.705852 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8854 12:21:02.709382 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8855 12:21:02.712820 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8856 12:21:02.712900 ==
8857 12:21:02.716080 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 12:21:02.719430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 12:21:02.719511 ==
8860 12:21:02.722671 DQS Delay:
8861 12:21:02.722750 DQS0 = 0, DQS1 = 0
8862 12:21:02.725799 DQM Delay:
8863 12:21:02.725878 DQM0 = 129, DQM1 = 127
8864 12:21:02.725941 DQ Delay:
8865 12:21:02.729581 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8866 12:21:02.736202 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =127
8867 12:21:02.739169 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8868 12:21:02.742525 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8869 12:21:02.742649
8870 12:21:02.742716
8871 12:21:02.742775 ==
8872 12:21:02.745908 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 12:21:02.749677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 12:21:02.749763 ==
8875 12:21:02.749828
8876 12:21:02.749886
8877 12:21:02.752597 TX Vref Scan disable
8878 12:21:02.755844 == TX Byte 0 ==
8879 12:21:02.759317 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8880 12:21:02.762162 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8881 12:21:02.765837 == TX Byte 1 ==
8882 12:21:02.768705 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8883 12:21:02.772293 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8884 12:21:02.772373 ==
8885 12:21:02.775729 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 12:21:02.778804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 12:21:02.782404 ==
8888 12:21:02.793559
8889 12:21:02.796675 TX Vref early break, caculate TX vref
8890 12:21:02.800461 TX Vref=16, minBit 0, minWin=22, winSum=383
8891 12:21:02.803342 TX Vref=18, minBit 0, minWin=23, winSum=391
8892 12:21:02.806876 TX Vref=20, minBit 0, minWin=22, winSum=399
8893 12:21:02.810332 TX Vref=22, minBit 0, minWin=24, winSum=410
8894 12:21:02.813166 TX Vref=24, minBit 0, minWin=25, winSum=416
8895 12:21:02.819948 TX Vref=26, minBit 6, minWin=25, winSum=425
8896 12:21:02.823196 TX Vref=28, minBit 0, minWin=25, winSum=427
8897 12:21:02.826523 TX Vref=30, minBit 1, minWin=25, winSum=422
8898 12:21:02.829873 TX Vref=32, minBit 5, minWin=23, winSum=412
8899 12:21:02.833151 TX Vref=34, minBit 5, minWin=23, winSum=403
8900 12:21:02.839706 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28
8901 12:21:02.839792
8902 12:21:02.843211 Final TX Range 0 Vref 28
8903 12:21:02.843294
8904 12:21:02.843357 ==
8905 12:21:02.846661 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 12:21:02.849730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 12:21:02.849810 ==
8908 12:21:02.849873
8909 12:21:02.849931
8910 12:21:02.853070 TX Vref Scan disable
8911 12:21:02.859737 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8912 12:21:02.859817 == TX Byte 0 ==
8913 12:21:02.862994 u2DelayCellOfst[0]=22 cells (6 PI)
8914 12:21:02.866426 u2DelayCellOfst[1]=15 cells (4 PI)
8915 12:21:02.869444 u2DelayCellOfst[2]=0 cells (0 PI)
8916 12:21:02.873092 u2DelayCellOfst[3]=11 cells (3 PI)
8917 12:21:02.876663 u2DelayCellOfst[4]=11 cells (3 PI)
8918 12:21:02.879564 u2DelayCellOfst[5]=22 cells (6 PI)
8919 12:21:02.883133 u2DelayCellOfst[6]=22 cells (6 PI)
8920 12:21:02.886736 u2DelayCellOfst[7]=7 cells (2 PI)
8921 12:21:02.889393 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8922 12:21:02.892725 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8923 12:21:02.896333 == TX Byte 1 ==
8924 12:21:02.899279 u2DelayCellOfst[8]=0 cells (0 PI)
8925 12:21:02.899358 u2DelayCellOfst[9]=7 cells (2 PI)
8926 12:21:02.902706 u2DelayCellOfst[10]=15 cells (4 PI)
8927 12:21:02.905943 u2DelayCellOfst[11]=7 cells (2 PI)
8928 12:21:02.909231 u2DelayCellOfst[12]=18 cells (5 PI)
8929 12:21:02.912666 u2DelayCellOfst[13]=18 cells (5 PI)
8930 12:21:02.915831 u2DelayCellOfst[14]=22 cells (6 PI)
8931 12:21:02.919300 u2DelayCellOfst[15]=22 cells (6 PI)
8932 12:21:02.922547 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8933 12:21:02.929123 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8934 12:21:02.929205 DramC Write-DBI on
8935 12:21:02.929269 ==
8936 12:21:02.932651 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 12:21:02.938847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 12:21:02.938928 ==
8939 12:21:02.938991
8940 12:21:02.939050
8941 12:21:02.939104 TX Vref Scan disable
8942 12:21:02.943220 == TX Byte 0 ==
8943 12:21:02.946227 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8944 12:21:02.949394 == TX Byte 1 ==
8945 12:21:02.953023 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8946 12:21:02.956179 DramC Write-DBI off
8947 12:21:02.956259
8948 12:21:02.956321 [DATLAT]
8949 12:21:02.956379 Freq=1600, CH1 RK1
8950 12:21:02.956435
8951 12:21:02.959819 DATLAT Default: 0xf
8952 12:21:02.963013 0, 0xFFFF, sum = 0
8953 12:21:02.963093 1, 0xFFFF, sum = 0
8954 12:21:02.966411 2, 0xFFFF, sum = 0
8955 12:21:02.966492 3, 0xFFFF, sum = 0
8956 12:21:02.969301 4, 0xFFFF, sum = 0
8957 12:21:02.969382 5, 0xFFFF, sum = 0
8958 12:21:02.972791 6, 0xFFFF, sum = 0
8959 12:21:02.972872 7, 0xFFFF, sum = 0
8960 12:21:02.976344 8, 0xFFFF, sum = 0
8961 12:21:02.976425 9, 0xFFFF, sum = 0
8962 12:21:02.979213 10, 0xFFFF, sum = 0
8963 12:21:02.979293 11, 0xFFFF, sum = 0
8964 12:21:02.982621 12, 0xFFFF, sum = 0
8965 12:21:02.982701 13, 0x8FFF, sum = 0
8966 12:21:02.985800 14, 0x0, sum = 1
8967 12:21:02.985897 15, 0x0, sum = 2
8968 12:21:02.989395 16, 0x0, sum = 3
8969 12:21:02.989476 17, 0x0, sum = 4
8970 12:21:02.992767 best_step = 15
8971 12:21:02.992845
8972 12:21:02.992907 ==
8973 12:21:02.996124 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 12:21:02.999167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 12:21:02.999247 ==
8976 12:21:03.002737 RX Vref Scan: 0
8977 12:21:03.002816
8978 12:21:03.002879 RX Vref 0 -> 0, step: 1
8979 12:21:03.002937
8980 12:21:03.006236 RX Delay 3 -> 252, step: 4
8981 12:21:03.009131 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8982 12:21:03.015698 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8983 12:21:03.019382 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8984 12:21:03.022638 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8985 12:21:03.025701 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8986 12:21:03.029441 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8987 12:21:03.035674 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8988 12:21:03.039009 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8989 12:21:03.042696 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8990 12:21:03.046027 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8991 12:21:03.048873 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8992 12:21:03.055626 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8993 12:21:03.059138 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8994 12:21:03.062117 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8995 12:21:03.065560 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8996 12:21:03.072298 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8997 12:21:03.072378 ==
8998 12:21:03.076081 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 12:21:03.078748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 12:21:03.078828 ==
9001 12:21:03.078891 DQS Delay:
9002 12:21:03.082640 DQS0 = 0, DQS1 = 0
9003 12:21:03.082719 DQM Delay:
9004 12:21:03.085210 DQM0 = 127, DQM1 = 124
9005 12:21:03.085290 DQ Delay:
9006 12:21:03.088693 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =124
9007 12:21:03.092079 DQ4 =124, DQ5 =138, DQ6 =140, DQ7 =124
9008 12:21:03.095616 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9009 12:21:03.098401 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9010 12:21:03.098480
9011 12:21:03.101954
9012 12:21:03.102033
9013 12:21:03.102094 [DramC_TX_OE_Calibration] TA2
9014 12:21:03.105455 Original DQ_B0 (3 6) =30, OEN = 27
9015 12:21:03.108631 Original DQ_B1 (3 6) =30, OEN = 27
9016 12:21:03.111987 24, 0x0, End_B0=24 End_B1=24
9017 12:21:03.114867 25, 0x0, End_B0=25 End_B1=25
9018 12:21:03.118303 26, 0x0, End_B0=26 End_B1=26
9019 12:21:03.118384 27, 0x0, End_B0=27 End_B1=27
9020 12:21:03.121755 28, 0x0, End_B0=28 End_B1=28
9021 12:21:03.125137 29, 0x0, End_B0=29 End_B1=29
9022 12:21:03.128413 30, 0x0, End_B0=30 End_B1=30
9023 12:21:03.131972 31, 0x4141, End_B0=30 End_B1=30
9024 12:21:03.132053 Byte0 end_step=30 best_step=27
9025 12:21:03.134929 Byte1 end_step=30 best_step=27
9026 12:21:03.138251 Byte0 TX OE(2T, 0.5T) = (3, 3)
9027 12:21:03.141707 Byte1 TX OE(2T, 0.5T) = (3, 3)
9028 12:21:03.141787
9029 12:21:03.141849
9030 12:21:03.148078 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9031 12:21:03.151348 CH1 RK1: MR19=303, MR18=F1A
9032 12:21:03.158180 CH1_RK1: MR19=0x303, MR18=0xF1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9033 12:21:03.161371 [RxdqsGatingPostProcess] freq 1600
9034 12:21:03.168021 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9035 12:21:03.171245 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 12:21:03.171324 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 12:21:03.174756 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 12:21:03.178174 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 12:21:03.181288 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 12:21:03.184589 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 12:21:03.187798 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 12:21:03.191076 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 12:21:03.194652 Pre-setting of DQS Precalculation
9044 12:21:03.198033 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9045 12:21:03.207882 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9046 12:21:03.214455 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9047 12:21:03.214536
9048 12:21:03.214598
9049 12:21:03.218286 [Calibration Summary] 3200 Mbps
9050 12:21:03.218366 CH 0, Rank 0
9051 12:21:03.220889 SW Impedance : PASS
9052 12:21:03.220969 DUTY Scan : NO K
9053 12:21:03.224351 ZQ Calibration : PASS
9054 12:21:03.227959 Jitter Meter : NO K
9055 12:21:03.228039 CBT Training : PASS
9056 12:21:03.231763 Write leveling : PASS
9057 12:21:03.234438 RX DQS gating : PASS
9058 12:21:03.234517 RX DQ/DQS(RDDQC) : PASS
9059 12:21:03.237977 TX DQ/DQS : PASS
9060 12:21:03.241362 RX DATLAT : PASS
9061 12:21:03.241441 RX DQ/DQS(Engine): PASS
9062 12:21:03.244210 TX OE : PASS
9063 12:21:03.244290 All Pass.
9064 12:21:03.244353
9065 12:21:03.247765 CH 0, Rank 1
9066 12:21:03.247844 SW Impedance : PASS
9067 12:21:03.251274 DUTY Scan : NO K
9068 12:21:03.254825 ZQ Calibration : PASS
9069 12:21:03.254904 Jitter Meter : NO K
9070 12:21:03.257379 CBT Training : PASS
9071 12:21:03.260783 Write leveling : PASS
9072 12:21:03.260863 RX DQS gating : PASS
9073 12:21:03.264644 RX DQ/DQS(RDDQC) : PASS
9074 12:21:03.267579 TX DQ/DQS : PASS
9075 12:21:03.267659 RX DATLAT : PASS
9076 12:21:03.270680 RX DQ/DQS(Engine): PASS
9077 12:21:03.270759 TX OE : PASS
9078 12:21:03.273977 All Pass.
9079 12:21:03.274056
9080 12:21:03.274119 CH 1, Rank 0
9081 12:21:03.277518 SW Impedance : PASS
9082 12:21:03.277598 DUTY Scan : NO K
9083 12:21:03.280742 ZQ Calibration : PASS
9084 12:21:03.283950 Jitter Meter : NO K
9085 12:21:03.284030 CBT Training : PASS
9086 12:21:03.287445 Write leveling : PASS
9087 12:21:03.290809 RX DQS gating : PASS
9088 12:21:03.290892 RX DQ/DQS(RDDQC) : PASS
9089 12:21:03.293913 TX DQ/DQS : PASS
9090 12:21:03.297453 RX DATLAT : PASS
9091 12:21:03.297536 RX DQ/DQS(Engine): PASS
9092 12:21:03.300499 TX OE : PASS
9093 12:21:03.300582 All Pass.
9094 12:21:03.300665
9095 12:21:03.303735 CH 1, Rank 1
9096 12:21:03.303817 SW Impedance : PASS
9097 12:21:03.307160 DUTY Scan : NO K
9098 12:21:03.311000 ZQ Calibration : PASS
9099 12:21:03.311083 Jitter Meter : NO K
9100 12:21:03.313677 CBT Training : PASS
9101 12:21:03.317278 Write leveling : PASS
9102 12:21:03.317361 RX DQS gating : PASS
9103 12:21:03.320987 RX DQ/DQS(RDDQC) : PASS
9104 12:21:03.323673 TX DQ/DQS : PASS
9105 12:21:03.323756 RX DATLAT : PASS
9106 12:21:03.327137 RX DQ/DQS(Engine): PASS
9107 12:21:03.327220 TX OE : PASS
9108 12:21:03.330660 All Pass.
9109 12:21:03.330743
9110 12:21:03.330827 DramC Write-DBI on
9111 12:21:03.333611 PER_BANK_REFRESH: Hybrid Mode
9112 12:21:03.337246 TX_TRACKING: ON
9113 12:21:03.343496 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9114 12:21:03.353848 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9115 12:21:03.360304 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9116 12:21:03.363866 [FAST_K] Save calibration result to emmc
9117 12:21:03.367215 sync common calibartion params.
9118 12:21:03.367294 sync cbt_mode0:1, 1:1
9119 12:21:03.369921 dram_init: ddr_geometry: 2
9120 12:21:03.373306 dram_init: ddr_geometry: 2
9121 12:21:03.376692 dram_init: ddr_geometry: 2
9122 12:21:03.376772 0:dram_rank_size:100000000
9123 12:21:03.379872 1:dram_rank_size:100000000
9124 12:21:03.386488 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9125 12:21:03.386568 DFS_SHUFFLE_HW_MODE: ON
9126 12:21:03.393123 dramc_set_vcore_voltage set vcore to 725000
9127 12:21:03.393203 Read voltage for 1600, 0
9128 12:21:03.396552 Vio18 = 0
9129 12:21:03.396631 Vcore = 725000
9130 12:21:03.396693 Vdram = 0
9131 12:21:03.400078 Vddq = 0
9132 12:21:03.400171 Vmddr = 0
9133 12:21:03.403034 switch to 3200 Mbps bootup
9134 12:21:03.403113 [DramcRunTimeConfig]
9135 12:21:03.403178 PHYPLL
9136 12:21:03.406477 DPM_CONTROL_AFTERK: ON
9137 12:21:03.409999 PER_BANK_REFRESH: ON
9138 12:21:03.410079 REFRESH_OVERHEAD_REDUCTION: ON
9139 12:21:03.413335 CMD_PICG_NEW_MODE: OFF
9140 12:21:03.416162 XRTWTW_NEW_MODE: ON
9141 12:21:03.416241 XRTRTR_NEW_MODE: ON
9142 12:21:03.419745 TX_TRACKING: ON
9143 12:21:03.419824 RDSEL_TRACKING: OFF
9144 12:21:03.422915 DQS Precalculation for DVFS: ON
9145 12:21:03.422995 RX_TRACKING: OFF
9146 12:21:03.426282 HW_GATING DBG: ON
9147 12:21:03.426361 ZQCS_ENABLE_LP4: ON
9148 12:21:03.429643 RX_PICG_NEW_MODE: ON
9149 12:21:03.433231 TX_PICG_NEW_MODE: ON
9150 12:21:03.433311 ENABLE_RX_DCM_DPHY: ON
9151 12:21:03.436124 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9152 12:21:03.439803 DUMMY_READ_FOR_TRACKING: OFF
9153 12:21:03.442775 !!! SPM_CONTROL_AFTERK: OFF
9154 12:21:03.446386 !!! SPM could not control APHY
9155 12:21:03.446466 IMPEDANCE_TRACKING: ON
9156 12:21:03.449839 TEMP_SENSOR: ON
9157 12:21:03.449945 HW_SAVE_FOR_SR: OFF
9158 12:21:03.452747 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9159 12:21:03.456200 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9160 12:21:03.459711 Read ODT Tracking: ON
9161 12:21:03.459790 Refresh Rate DeBounce: ON
9162 12:21:03.462728 DFS_NO_QUEUE_FLUSH: ON
9163 12:21:03.466217 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9164 12:21:03.469858 ENABLE_DFS_RUNTIME_MRW: OFF
9165 12:21:03.469938 DDR_RESERVE_NEW_MODE: ON
9166 12:21:03.472931 MR_CBT_SWITCH_FREQ: ON
9167 12:21:03.476148 =========================
9168 12:21:03.494500 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9169 12:21:03.497558 dram_init: ddr_geometry: 2
9170 12:21:03.515653 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9171 12:21:03.519180 dram_init: dram init end (result: 0)
9172 12:21:03.525756 DRAM-K: Full calibration passed in 24591 msecs
9173 12:21:03.529229 MRC: failed to locate region type 0.
9174 12:21:03.529309 DRAM rank0 size:0x100000000,
9175 12:21:03.532217 DRAM rank1 size=0x100000000
9176 12:21:03.542333 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9177 12:21:03.548759 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9178 12:21:03.555729 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9179 12:21:03.562260 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9180 12:21:03.565794 DRAM rank0 size:0x100000000,
9181 12:21:03.568738 DRAM rank1 size=0x100000000
9182 12:21:03.568818 CBMEM:
9183 12:21:03.572350 IMD: root @ 0xfffff000 254 entries.
9184 12:21:03.575296 IMD: root @ 0xffffec00 62 entries.
9185 12:21:03.578659 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9186 12:21:03.585358 WARNING: RO_VPD is uninitialized or empty.
9187 12:21:03.588326 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9188 12:21:03.596175 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9189 12:21:03.608834 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9190 12:21:03.620041 BS: romstage times (exec / console): total (unknown) / 24050 ms
9191 12:21:03.620124
9192 12:21:03.620209
9193 12:21:03.629836 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9194 12:21:03.633623 ARM64: Exception handlers installed.
9195 12:21:03.636327 ARM64: Testing exception
9196 12:21:03.639792 ARM64: Done test exception
9197 12:21:03.639875 Enumerating buses...
9198 12:21:03.643090 Show all devs... Before device enumeration.
9199 12:21:03.646826 Root Device: enabled 1
9200 12:21:03.649889 CPU_CLUSTER: 0: enabled 1
9201 12:21:03.649972 CPU: 00: enabled 1
9202 12:21:03.653418 Compare with tree...
9203 12:21:03.653500 Root Device: enabled 1
9204 12:21:03.656476 CPU_CLUSTER: 0: enabled 1
9205 12:21:03.659790 CPU: 00: enabled 1
9206 12:21:03.659872 Root Device scanning...
9207 12:21:03.663279 scan_static_bus for Root Device
9208 12:21:03.666751 CPU_CLUSTER: 0 enabled
9209 12:21:03.669663 scan_static_bus for Root Device done
9210 12:21:03.673309 scan_bus: bus Root Device finished in 8 msecs
9211 12:21:03.673392 done
9212 12:21:03.679824 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9213 12:21:03.683312 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9214 12:21:03.689541 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9215 12:21:03.692989 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9216 12:21:03.696422 Allocating resources...
9217 12:21:03.699287 Reading resources...
9218 12:21:03.702741 Root Device read_resources bus 0 link: 0
9219 12:21:03.702821 DRAM rank0 size:0x100000000,
9220 12:21:03.706155 DRAM rank1 size=0x100000000
9221 12:21:03.709473 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9222 12:21:03.712799 CPU: 00 missing read_resources
9223 12:21:03.719247 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9224 12:21:03.722417 Root Device read_resources bus 0 link: 0 done
9225 12:21:03.722496 Done reading resources.
9226 12:21:03.729405 Show resources in subtree (Root Device)...After reading.
9227 12:21:03.733122 Root Device child on link 0 CPU_CLUSTER: 0
9228 12:21:03.736104 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 12:21:03.745769 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 12:21:03.745857 CPU: 00
9231 12:21:03.749023 Root Device assign_resources, bus 0 link: 0
9232 12:21:03.752637 CPU_CLUSTER: 0 missing set_resources
9233 12:21:03.759098 Root Device assign_resources, bus 0 link: 0 done
9234 12:21:03.759181 Done setting resources.
9235 12:21:03.765645 Show resources in subtree (Root Device)...After assigning values.
9236 12:21:03.769057 Root Device child on link 0 CPU_CLUSTER: 0
9237 12:21:03.772221 CPU_CLUSTER: 0 child on link 0 CPU: 00
9238 12:21:03.782235 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9239 12:21:03.782320 CPU: 00
9240 12:21:03.785335 Done allocating resources.
9241 12:21:03.792229 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9242 12:21:03.792313 Enabling resources...
9243 12:21:03.792396 done.
9244 12:21:03.798765 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9245 12:21:03.798849 Initializing devices...
9246 12:21:03.801764 Root Device init
9247 12:21:03.804995 init hardware done!
9248 12:21:03.805079 0x00000018: ctrlr->caps
9249 12:21:03.808829 52.000 MHz: ctrlr->f_max
9250 12:21:03.811954 0.400 MHz: ctrlr->f_min
9251 12:21:03.812038 0x40ff8080: ctrlr->voltages
9252 12:21:03.815338 sclk: 390625
9253 12:21:03.815463 Bus Width = 1
9254 12:21:03.815547 sclk: 390625
9255 12:21:03.818836 Bus Width = 1
9256 12:21:03.818918 Early init status = 3
9257 12:21:03.825194 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9258 12:21:03.828708 in-header: 03 fb 00 00 01 00 00 00
9259 12:21:03.831715 in-data: 01
9260 12:21:03.834816 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9261 12:21:03.838403 in-header: 03 fb 00 00 01 00 00 00
9262 12:21:03.841776 in-data: 01
9263 12:21:03.844988 [SSUSB] Setting up USB HOST controller...
9264 12:21:03.848209 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9265 12:21:03.851778 [SSUSB] phy power-on done.
9266 12:21:03.854505 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9267 12:21:03.861676 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9268 12:21:03.864553 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9269 12:21:03.871066 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9270 12:21:03.877505 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9271 12:21:03.884501 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9272 12:21:03.890712 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9273 12:21:03.897907 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9274 12:21:03.900774 SPM: binary array size = 0x9dc
9275 12:21:03.904199 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9276 12:21:03.910717 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9277 12:21:03.917247 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9278 12:21:03.924036 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9279 12:21:03.927492 configure_display: Starting display init
9280 12:21:03.961440 anx7625_power_on_init: Init interface.
9281 12:21:03.964971 anx7625_disable_pd_protocol: Disabled PD feature.
9282 12:21:03.967963 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9283 12:21:03.995946 anx7625_start_dp_work: Secure OCM version=00
9284 12:21:03.998969 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9285 12:21:04.014190 sp_tx_get_edid_block: EDID Block = 1
9286 12:21:04.116250 Extracted contents:
9287 12:21:04.119432 header: 00 ff ff ff ff ff ff 00
9288 12:21:04.122850 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9289 12:21:04.126839 version: 01 04
9290 12:21:04.129354 basic params: 95 1f 11 78 0a
9291 12:21:04.132776 chroma info: 76 90 94 55 54 90 27 21 50 54
9292 12:21:04.136322 established: 00 00 00
9293 12:21:04.142893 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9294 12:21:04.149174 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9295 12:21:04.152620 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9296 12:21:04.159035 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9297 12:21:04.165842 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9298 12:21:04.168924 extensions: 00
9299 12:21:04.169003 checksum: fb
9300 12:21:04.169065
9301 12:21:04.172477 Manufacturer: IVO Model 57d Serial Number 0
9302 12:21:04.175975 Made week 0 of 2020
9303 12:21:04.178903 EDID version: 1.4
9304 12:21:04.178982 Digital display
9305 12:21:04.182467 6 bits per primary color channel
9306 12:21:04.182548 DisplayPort interface
9307 12:21:04.185640 Maximum image size: 31 cm x 17 cm
9308 12:21:04.189038 Gamma: 220%
9309 12:21:04.189118 Check DPMS levels
9310 12:21:04.192032 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9311 12:21:04.198626 First detailed timing is preferred timing
9312 12:21:04.198707 Established timings supported:
9313 12:21:04.202302 Standard timings supported:
9314 12:21:04.205781 Detailed timings
9315 12:21:04.208869 Hex of detail: 383680a07038204018303c0035ae10000019
9316 12:21:04.215591 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9317 12:21:04.218427 0780 0798 07c8 0820 hborder 0
9318 12:21:04.222405 0438 043b 0447 0458 vborder 0
9319 12:21:04.225476 -hsync -vsync
9320 12:21:04.225557 Did detailed timing
9321 12:21:04.232026 Hex of detail: 000000000000000000000000000000000000
9322 12:21:04.235159 Manufacturer-specified data, tag 0
9323 12:21:04.238949 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9324 12:21:04.241901 ASCII string: InfoVision
9325 12:21:04.245017 Hex of detail: 000000fe00523134304e574635205248200a
9326 12:21:04.248682 ASCII string: R140NWF5 RH
9327 12:21:04.248789 Checksum
9328 12:21:04.251885 Checksum: 0xfb (valid)
9329 12:21:04.255187 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9330 12:21:04.258545 DSI data_rate: 832800000 bps
9331 12:21:04.265122 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9332 12:21:04.268246 anx7625_parse_edid: pixelclock(138800).
9333 12:21:04.271823 hactive(1920), hsync(48), hfp(24), hbp(88)
9334 12:21:04.275171 vactive(1080), vsync(12), vfp(3), vbp(17)
9335 12:21:04.278360 anx7625_dsi_config: config dsi.
9336 12:21:04.285000 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9337 12:21:04.298493 anx7625_dsi_config: success to config DSI
9338 12:21:04.301984 anx7625_dp_start: MIPI phy setup OK.
9339 12:21:04.305010 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9340 12:21:04.308853 mtk_ddp_mode_set invalid vrefresh 60
9341 12:21:04.311777 main_disp_path_setup
9342 12:21:04.311880 ovl_layer_smi_id_en
9343 12:21:04.315229 ovl_layer_smi_id_en
9344 12:21:04.315337 ccorr_config
9345 12:21:04.315423 aal_config
9346 12:21:04.318323 gamma_config
9347 12:21:04.318403 postmask_config
9348 12:21:04.321181 dither_config
9349 12:21:04.324810 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9350 12:21:04.331582 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9351 12:21:04.335070 Root Device init finished in 529 msecs
9352 12:21:04.337911 CPU_CLUSTER: 0 init
9353 12:21:04.344837 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9354 12:21:04.348147 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9355 12:21:04.351264 APU_MBOX 0x190000b0 = 0x10001
9356 12:21:04.354615 APU_MBOX 0x190001b0 = 0x10001
9357 12:21:04.357776 APU_MBOX 0x190005b0 = 0x10001
9358 12:21:04.361416 APU_MBOX 0x190006b0 = 0x10001
9359 12:21:04.364466 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9360 12:21:04.377307 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9361 12:21:04.389709 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9362 12:21:04.396621 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9363 12:21:04.407966 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9364 12:21:04.417251 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9365 12:21:04.420877 CPU_CLUSTER: 0 init finished in 81 msecs
9366 12:21:04.423913 Devices initialized
9367 12:21:04.427309 Show all devs... After init.
9368 12:21:04.427415 Root Device: enabled 1
9369 12:21:04.430690 CPU_CLUSTER: 0: enabled 1
9370 12:21:04.434127 CPU: 00: enabled 1
9371 12:21:04.437060 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9372 12:21:04.440174 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9373 12:21:04.443750 ELOG: NV offset 0x57f000 size 0x1000
9374 12:21:04.450349 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9375 12:21:04.457326 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9376 12:21:04.460443 ELOG: Event(17) added with size 13 at 2023-08-16 12:21:04 UTC
9377 12:21:04.467096 out: cmd=0x121: 03 db 21 01 00 00 00 00
9378 12:21:04.470440 in-header: 03 5d 00 00 2c 00 00 00
9379 12:21:04.479928 in-data: 01 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9380 12:21:04.486496 ELOG: Event(A1) added with size 10 at 2023-08-16 12:21:04 UTC
9381 12:21:04.493108 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9382 12:21:04.499833 ELOG: Event(A0) added with size 9 at 2023-08-16 12:21:04 UTC
9383 12:21:04.503219 elog_add_boot_reason: Logged dev mode boot
9384 12:21:04.510196 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9385 12:21:04.510278 Finalize devices...
9386 12:21:04.513452 Devices finalized
9387 12:21:04.516793 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9388 12:21:04.520110 Writing coreboot table at 0xffe64000
9389 12:21:04.523571 0. 000000000010a000-0000000000113fff: RAMSTAGE
9390 12:21:04.526195 1. 0000000040000000-00000000400fffff: RAM
9391 12:21:04.532934 2. 0000000040100000-000000004032afff: RAMSTAGE
9392 12:21:04.536412 3. 000000004032b000-00000000545fffff: RAM
9393 12:21:04.539319 4. 0000000054600000-000000005465ffff: BL31
9394 12:21:04.542803 5. 0000000054660000-00000000ffe63fff: RAM
9395 12:21:04.549709 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9396 12:21:04.552785 7. 0000000100000000-000000023fffffff: RAM
9397 12:21:04.556272 Passing 5 GPIOs to payload:
9398 12:21:04.559142 NAME | PORT | POLARITY | VALUE
9399 12:21:04.566483 EC in RW | 0x000000aa | low | undefined
9400 12:21:04.569462 EC interrupt | 0x00000005 | low | undefined
9401 12:21:04.572708 TPM interrupt | 0x000000ab | high | undefined
9402 12:21:04.579297 SD card detect | 0x00000011 | high | undefined
9403 12:21:04.582323 speaker enable | 0x00000093 | high | undefined
9404 12:21:04.585970 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9405 12:21:04.588839 in-header: 03 f9 00 00 02 00 00 00
9406 12:21:04.592615 in-data: 02 00
9407 12:21:04.595939 ADC[4]: Raw value=893711 ID=7
9408 12:21:04.596041 ADC[3]: Raw value=212330 ID=1
9409 12:21:04.599319 RAM Code: 0x71
9410 12:21:04.602283 ADC[6]: Raw value=74722 ID=0
9411 12:21:04.602358 ADC[5]: Raw value=211960 ID=1
9412 12:21:04.605468 SKU Code: 0x1
9413 12:21:04.609260 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2dcf
9414 12:21:04.612594 coreboot table: 964 bytes.
9415 12:21:04.616525 IMD ROOT 0. 0xfffff000 0x00001000
9416 12:21:04.619507 IMD SMALL 1. 0xffffe000 0x00001000
9417 12:21:04.622737 RO MCACHE 2. 0xffffc000 0x00001104
9418 12:21:04.625659 CONSOLE 3. 0xfff7c000 0x00080000
9419 12:21:04.629273 FMAP 4. 0xfff7b000 0x00000452
9420 12:21:04.632744 TIME STAMP 5. 0xfff7a000 0x00000910
9421 12:21:04.635738 VBOOT WORK 6. 0xfff66000 0x00014000
9422 12:21:04.639314 RAMOOPS 7. 0xffe66000 0x00100000
9423 12:21:04.642380 COREBOOT 8. 0xffe64000 0x00002000
9424 12:21:04.645661 IMD small region:
9425 12:21:04.649047 IMD ROOT 0. 0xffffec00 0x00000400
9426 12:21:04.652011 VPD 1. 0xffffeba0 0x0000004c
9427 12:21:04.655466 MMC STATUS 2. 0xffffeb80 0x00000004
9428 12:21:04.658832 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9429 12:21:04.662814 Probing TPM: done!
9430 12:21:04.666034 Connected to device vid:did:rid of 1ae0:0028:00
9431 12:21:04.676107 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9432 12:21:04.679288 Initialized TPM device CR50 revision 0
9433 12:21:04.683659 Checking cr50 for pending updates
9434 12:21:04.687124 Reading cr50 TPM mode
9435 12:21:04.695510 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9436 12:21:04.701841 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9437 12:21:04.742157 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9438 12:21:04.745689 Checking segment from ROM address 0x40100000
9439 12:21:04.748926 Checking segment from ROM address 0x4010001c
9440 12:21:04.755716 Loading segment from ROM address 0x40100000
9441 12:21:04.755799 code (compression=0)
9442 12:21:04.765742 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9443 12:21:04.772387 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9444 12:21:04.772469 it's not compressed!
9445 12:21:04.778840 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9446 12:21:04.781874 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9447 12:21:04.802555 Loading segment from ROM address 0x4010001c
9448 12:21:04.802703 Entry Point 0x80000000
9449 12:21:04.805861 Loaded segments
9450 12:21:04.809088 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9451 12:21:04.815666 Jumping to boot code at 0x80000000(0xffe64000)
9452 12:21:04.822159 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9453 12:21:04.829189 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9454 12:21:04.836725 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9455 12:21:04.840400 Checking segment from ROM address 0x40100000
9456 12:21:04.843322 Checking segment from ROM address 0x4010001c
9457 12:21:04.850029 Loading segment from ROM address 0x40100000
9458 12:21:04.850137 code (compression=1)
9459 12:21:04.856515 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9460 12:21:04.866831 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9461 12:21:04.866945 using LZMA
9462 12:21:04.874988 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9463 12:21:04.882119 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9464 12:21:04.885118 Loading segment from ROM address 0x4010001c
9465 12:21:04.885212 Entry Point 0x54601000
9466 12:21:04.888629 Loaded segments
9467 12:21:04.891674 NOTICE: MT8192 bl31_setup
9468 12:21:04.899285 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9469 12:21:04.902437 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9470 12:21:04.905658 WARNING: region 0:
9471 12:21:04.908915 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 12:21:04.909020 WARNING: region 1:
9473 12:21:04.915499 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9474 12:21:04.918804 WARNING: region 2:
9475 12:21:04.921915 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9476 12:21:04.925748 WARNING: region 3:
9477 12:21:04.928590 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 12:21:04.932221 WARNING: region 4:
9479 12:21:04.938917 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 12:21:04.939049 WARNING: region 5:
9481 12:21:04.942389 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 12:21:04.945391 WARNING: region 6:
9483 12:21:04.948965 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 12:21:04.949046 WARNING: region 7:
9485 12:21:04.955444 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 12:21:04.962061 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9487 12:21:04.965506 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9488 12:21:04.969042 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9489 12:21:04.975871 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9490 12:21:04.978785 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9491 12:21:04.982125 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9492 12:21:04.988562 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9493 12:21:04.992318 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9494 12:21:04.998928 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9495 12:21:05.001933 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9496 12:21:05.005470 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9497 12:21:05.012341 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9498 12:21:05.015210 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9499 12:21:05.018748 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9500 12:21:05.025114 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9501 12:21:05.028633 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9502 12:21:05.035439 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9503 12:21:05.038838 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9504 12:21:05.041912 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9505 12:21:05.048680 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9506 12:21:05.052150 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9507 12:21:05.055185 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9508 12:21:05.061936 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9509 12:21:05.065292 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9510 12:21:05.071912 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9511 12:21:05.075505 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9512 12:21:05.078549 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9513 12:21:05.085392 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9514 12:21:05.088612 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9515 12:21:05.095869 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9516 12:21:05.098778 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9517 12:21:05.102332 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9518 12:21:05.108870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9519 12:21:05.112171 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9520 12:21:05.115438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9521 12:21:05.118524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9522 12:21:05.125892 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9523 12:21:05.128809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9524 12:21:05.132083 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9525 12:21:05.135219 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9526 12:21:05.138933 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9527 12:21:05.145272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9528 12:21:05.149233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9529 12:21:05.151926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9530 12:21:05.158842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9531 12:21:05.161771 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9532 12:21:05.165182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9533 12:21:05.168861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9534 12:21:05.175253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9535 12:21:05.178567 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9536 12:21:05.185263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9537 12:21:05.188949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9538 12:21:05.191926 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9539 12:21:05.199060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9540 12:21:05.201952 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9541 12:21:05.208538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9542 12:21:05.212420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9543 12:21:05.218961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9544 12:21:05.222444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9545 12:21:05.225670 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9546 12:21:05.232033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9547 12:21:05.235615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9548 12:21:05.242000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9549 12:21:05.245339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9550 12:21:05.252577 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9551 12:21:05.255305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9552 12:21:05.258885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9553 12:21:05.265557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9554 12:21:05.268652 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9555 12:21:05.275551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9556 12:21:05.278919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9557 12:21:05.285599 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9558 12:21:05.288777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9559 12:21:05.292077 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9560 12:21:05.298976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9561 12:21:05.302238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9562 12:21:05.309164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9563 12:21:05.312260 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9564 12:21:05.318889 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9565 12:21:05.321936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9566 12:21:05.328867 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9567 12:21:05.332270 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9568 12:21:05.335592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9569 12:21:05.341975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9570 12:21:05.345927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9571 12:21:05.352277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9572 12:21:05.355634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9573 12:21:05.359110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9574 12:21:05.365803 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9575 12:21:05.368808 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9576 12:21:05.375703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9577 12:21:05.378362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9578 12:21:05.385413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9579 12:21:05.388886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9580 12:21:05.395664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9581 12:21:05.398714 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9582 12:21:05.402046 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9583 12:21:05.408310 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9584 12:21:05.411724 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9585 12:21:05.414937 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9586 12:21:05.418721 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9587 12:21:05.425388 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9588 12:21:05.428260 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9589 12:21:05.435253 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9590 12:21:05.438765 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9591 12:21:05.441823 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9592 12:21:05.448360 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9593 12:21:05.451746 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9594 12:21:05.458804 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9595 12:21:05.461605 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9596 12:21:05.465521 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9597 12:21:05.471798 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9598 12:21:05.475272 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9599 12:21:05.481797 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9600 12:21:05.484968 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9601 12:21:05.488634 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9602 12:21:05.491652 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9603 12:21:05.498645 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9604 12:21:05.501885 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9605 12:21:05.505383 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9606 12:21:05.511631 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9607 12:21:05.515127 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9608 12:21:05.518454 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9609 12:21:05.521583 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9610 12:21:05.528281 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9611 12:21:05.531923 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9612 12:21:05.538497 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9613 12:21:05.541631 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9614 12:21:05.545075 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9615 12:21:05.551427 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9616 12:21:05.555035 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9617 12:21:05.558615 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9618 12:21:05.565063 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9619 12:21:05.568195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9620 12:21:05.574900 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9621 12:21:05.578591 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9622 12:21:05.581498 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9623 12:21:05.588416 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9624 12:21:05.592006 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9625 12:21:05.598298 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9626 12:21:05.601500 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9627 12:21:05.605051 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9628 12:21:05.611324 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9629 12:21:05.614995 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9630 12:21:05.621629 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9631 12:21:05.625034 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9632 12:21:05.628359 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9633 12:21:05.634793 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9634 12:21:05.637931 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9635 12:21:05.645135 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9636 12:21:05.648154 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9637 12:21:05.651785 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9638 12:21:05.658141 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9639 12:21:05.661194 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9640 12:21:05.664837 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9641 12:21:05.671472 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9642 12:21:05.674892 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9643 12:21:05.681583 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9644 12:21:05.685214 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9645 12:21:05.688048 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9646 12:21:05.694892 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9647 12:21:05.697807 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9648 12:21:05.704997 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9649 12:21:05.707947 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9650 12:21:05.711543 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9651 12:21:05.717968 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9652 12:21:05.721495 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9653 12:21:05.724487 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9654 12:21:05.731977 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9655 12:21:05.734493 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9656 12:21:05.741502 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9657 12:21:05.744694 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9658 12:21:05.748211 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9659 12:21:05.754612 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9660 12:21:05.757660 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9661 12:21:05.764219 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9662 12:21:05.767685 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9663 12:21:05.771104 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9664 12:21:05.778019 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9665 12:21:05.780878 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9666 12:21:05.787538 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9667 12:21:05.790853 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9668 12:21:05.794249 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9669 12:21:05.800992 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9670 12:21:05.803812 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9671 12:21:05.810676 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9672 12:21:05.814024 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9673 12:21:05.817579 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9674 12:21:05.824103 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9675 12:21:05.827571 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9676 12:21:05.834059 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9677 12:21:05.837057 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9678 12:21:05.843571 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9679 12:21:05.846729 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9680 12:21:05.850610 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9681 12:21:05.856825 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9682 12:21:05.860641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9683 12:21:05.866914 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9684 12:21:05.870171 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9685 12:21:05.876474 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9686 12:21:05.879850 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9687 12:21:05.883273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9688 12:21:05.889930 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9689 12:21:05.893578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9690 12:21:05.900068 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9691 12:21:05.903712 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9692 12:21:05.906811 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9693 12:21:05.913173 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9694 12:21:05.916410 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9695 12:21:05.922887 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9696 12:21:05.926284 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9697 12:21:05.933150 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9698 12:21:05.936468 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9699 12:21:05.939772 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9700 12:21:05.946661 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9701 12:21:05.949915 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9702 12:21:05.956419 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9703 12:21:05.959995 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9704 12:21:05.962686 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9705 12:21:05.969285 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9706 12:21:05.972761 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9707 12:21:05.979227 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9708 12:21:05.982752 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9709 12:21:05.989673 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9710 12:21:05.993007 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9711 12:21:05.996235 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9712 12:21:06.002501 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9713 12:21:06.005651 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9714 12:21:06.012587 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9715 12:21:06.016156 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9716 12:21:06.019054 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9717 12:21:06.022618 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9718 12:21:06.028996 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9719 12:21:06.032050 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9720 12:21:06.035467 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9721 12:21:06.042236 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9722 12:21:06.045526 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9723 12:21:06.048628 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9724 12:21:06.055185 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9725 12:21:06.058957 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9726 12:21:06.062170 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9727 12:21:06.068759 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9728 12:21:06.072168 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9729 12:21:06.075426 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9730 12:21:06.081789 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9731 12:21:06.085467 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9732 12:21:06.091933 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9733 12:21:06.095088 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9734 12:21:06.098905 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9735 12:21:06.105325 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9736 12:21:06.108637 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9737 12:21:06.111825 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9738 12:21:06.118623 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9739 12:21:06.121753 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9740 12:21:06.128314 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9741 12:21:06.131784 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9742 12:21:06.135212 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9743 12:21:06.141582 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9744 12:21:06.145464 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9745 12:21:06.148170 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9746 12:21:06.154681 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9747 12:21:06.158346 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9748 12:21:06.164679 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9749 12:21:06.168348 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9750 12:21:06.171212 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9751 12:21:06.178168 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9752 12:21:06.181315 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9753 12:21:06.184703 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9754 12:21:06.191177 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9755 12:21:06.194553 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9756 12:21:06.197768 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9757 12:21:06.201055 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9758 12:21:06.208150 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9759 12:21:06.211093 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9760 12:21:06.214548 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9761 12:21:06.217577 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9762 12:21:06.224419 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9763 12:21:06.227917 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9764 12:21:06.231008 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9765 12:21:06.234736 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9766 12:21:06.240686 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9767 12:21:06.244313 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9768 12:21:06.247680 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9769 12:21:06.254037 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9770 12:21:06.257513 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9771 12:21:06.264253 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9772 12:21:06.267542 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9773 12:21:06.274612 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9774 12:21:06.277535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9775 12:21:06.280404 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9776 12:21:06.286921 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9777 12:21:06.290512 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9778 12:21:06.297053 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9779 12:21:06.300425 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9780 12:21:06.303861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9781 12:21:06.310165 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9782 12:21:06.313645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9783 12:21:06.320126 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9784 12:21:06.323672 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9785 12:21:06.327211 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9786 12:21:06.333608 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9787 12:21:06.336632 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9788 12:21:06.343064 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9789 12:21:06.346438 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9790 12:21:06.353128 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9791 12:21:06.356680 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9792 12:21:06.360028 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9793 12:21:06.366431 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9794 12:21:06.369844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9795 12:21:06.376265 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9796 12:21:06.379664 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9797 12:21:06.386376 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9798 12:21:06.389639 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9799 12:21:06.393065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9800 12:21:06.399376 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9801 12:21:06.402746 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9802 12:21:06.409483 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9803 12:21:06.412766 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9804 12:21:06.415995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9805 12:21:06.422950 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9806 12:21:06.426284 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9807 12:21:06.432408 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9808 12:21:06.435880 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9809 12:21:06.439075 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9810 12:21:06.446278 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9811 12:21:06.449101 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9812 12:21:06.455798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9813 12:21:06.459310 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9814 12:21:06.465908 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9815 12:21:06.468858 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9816 12:21:06.472178 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9817 12:21:06.478962 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9818 12:21:06.482176 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9819 12:21:06.488995 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9820 12:21:06.492547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9821 12:21:06.495291 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9822 12:21:06.501899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9823 12:21:06.505620 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9824 12:21:06.512263 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9825 12:21:06.515651 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9826 12:21:06.518927 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9827 12:21:06.525519 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9828 12:21:06.528274 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9829 12:21:06.535061 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9830 12:21:06.538320 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9831 12:21:06.542265 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9832 12:21:06.548506 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9833 12:21:06.551799 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9834 12:21:06.558348 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9835 12:21:06.561678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9836 12:21:06.568559 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9837 12:21:06.571529 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9838 12:21:06.575110 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9839 12:21:06.581490 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9840 12:21:06.584571 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9841 12:21:06.591080 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9842 12:21:06.594459 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9843 12:21:06.601329 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9844 12:21:06.604721 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9845 12:21:06.611156 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9846 12:21:06.614632 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9847 12:21:06.617514 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9848 12:21:06.624167 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9849 12:21:06.627609 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9850 12:21:06.634295 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9851 12:21:06.637951 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9852 12:21:06.644027 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9853 12:21:06.647651 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9854 12:21:06.650864 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9855 12:21:06.657644 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9856 12:21:06.660931 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9857 12:21:06.667239 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9858 12:21:06.670646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9859 12:21:06.677174 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9860 12:21:06.680745 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9861 12:21:06.687056 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9862 12:21:06.690746 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9863 12:21:06.694206 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9864 12:21:06.700706 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9865 12:21:06.703752 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9866 12:21:06.710852 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9867 12:21:06.713733 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9868 12:21:06.720682 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9869 12:21:06.723568 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9870 12:21:06.727201 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9871 12:21:06.733746 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9872 12:21:06.737011 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9873 12:21:06.743750 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9874 12:21:06.746903 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9875 12:21:06.753752 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9876 12:21:06.756652 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9877 12:21:06.763695 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9878 12:21:06.766613 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9879 12:21:06.769839 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9880 12:21:06.776525 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9881 12:21:06.779904 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9882 12:21:06.786658 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9883 12:21:06.790038 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9884 12:21:06.796691 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9885 12:21:06.800042 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9886 12:21:06.803573 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9887 12:21:06.809765 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9888 12:21:06.813489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9889 12:21:06.820170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9890 12:21:06.823311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9891 12:21:06.826185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9892 12:21:06.833245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9893 12:21:06.836183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9894 12:21:06.842896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9895 12:21:06.845954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9896 12:21:06.852618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9897 12:21:06.855839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9898 12:21:06.862715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9899 12:21:06.865741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9900 12:21:06.872895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9901 12:21:06.875871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9902 12:21:06.882757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9903 12:21:06.885831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9904 12:21:06.892400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9905 12:21:06.896124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9906 12:21:06.902594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9907 12:21:06.905549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9908 12:21:06.912157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9909 12:21:06.915438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9910 12:21:06.922290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9911 12:21:06.925843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9912 12:21:06.932496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9913 12:21:06.935531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9914 12:21:06.941918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9915 12:21:06.945819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9916 12:21:06.951802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9917 12:21:06.955523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9918 12:21:06.961735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9919 12:21:06.965026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9920 12:21:06.972053 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9921 12:21:06.972169 INFO: [APUAPC] vio 0
9922 12:21:06.978828 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9923 12:21:06.982326 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9924 12:21:06.985319 INFO: [APUAPC] D0_APC_0: 0x400510
9925 12:21:06.988827 INFO: [APUAPC] D0_APC_1: 0x0
9926 12:21:06.992028 INFO: [APUAPC] D0_APC_2: 0x1540
9927 12:21:06.995202 INFO: [APUAPC] D0_APC_3: 0x0
9928 12:21:06.998491 INFO: [APUAPC] D1_APC_0: 0xffffffff
9929 12:21:07.001843 INFO: [APUAPC] D1_APC_1: 0xffffffff
9930 12:21:07.005276 INFO: [APUAPC] D1_APC_2: 0x3fffff
9931 12:21:07.008313 INFO: [APUAPC] D1_APC_3: 0x0
9932 12:21:07.011505 INFO: [APUAPC] D2_APC_0: 0xffffffff
9933 12:21:07.015214 INFO: [APUAPC] D2_APC_1: 0xffffffff
9934 12:21:07.018190 INFO: [APUAPC] D2_APC_2: 0x3fffff
9935 12:21:07.021737 INFO: [APUAPC] D2_APC_3: 0x0
9936 12:21:07.024959 INFO: [APUAPC] D3_APC_0: 0xffffffff
9937 12:21:07.028352 INFO: [APUAPC] D3_APC_1: 0xffffffff
9938 12:21:07.031477 INFO: [APUAPC] D3_APC_2: 0x3fffff
9939 12:21:07.035121 INFO: [APUAPC] D3_APC_3: 0x0
9940 12:21:07.038181 INFO: [APUAPC] D4_APC_0: 0xffffffff
9941 12:21:07.041939 INFO: [APUAPC] D4_APC_1: 0xffffffff
9942 12:21:07.044976 INFO: [APUAPC] D4_APC_2: 0x3fffff
9943 12:21:07.045075 INFO: [APUAPC] D4_APC_3: 0x0
9944 12:21:07.051218 INFO: [APUAPC] D5_APC_0: 0xffffffff
9945 12:21:07.054851 INFO: [APUAPC] D5_APC_1: 0xffffffff
9946 12:21:07.057797 INFO: [APUAPC] D5_APC_2: 0x3fffff
9947 12:21:07.057888 INFO: [APUAPC] D5_APC_3: 0x0
9948 12:21:07.064769 INFO: [APUAPC] D6_APC_0: 0xffffffff
9949 12:21:07.067892 INFO: [APUAPC] D6_APC_1: 0xffffffff
9950 12:21:07.071213 INFO: [APUAPC] D6_APC_2: 0x3fffff
9951 12:21:07.071331 INFO: [APUAPC] D6_APC_3: 0x0
9952 12:21:07.074389 INFO: [APUAPC] D7_APC_0: 0xffffffff
9953 12:21:07.077880 INFO: [APUAPC] D7_APC_1: 0xffffffff
9954 12:21:07.081541 INFO: [APUAPC] D7_APC_2: 0x3fffff
9955 12:21:07.084363 INFO: [APUAPC] D7_APC_3: 0x0
9956 12:21:07.088098 INFO: [APUAPC] D8_APC_0: 0xffffffff
9957 12:21:07.091366 INFO: [APUAPC] D8_APC_1: 0xffffffff
9958 12:21:07.094343 INFO: [APUAPC] D8_APC_2: 0x3fffff
9959 12:21:07.097936 INFO: [APUAPC] D8_APC_3: 0x0
9960 12:21:07.100929 INFO: [APUAPC] D9_APC_0: 0xffffffff
9961 12:21:07.104747 INFO: [APUAPC] D9_APC_1: 0xffffffff
9962 12:21:07.107547 INFO: [APUAPC] D9_APC_2: 0x3fffff
9963 12:21:07.111178 INFO: [APUAPC] D9_APC_3: 0x0
9964 12:21:07.114660 INFO: [APUAPC] D10_APC_0: 0xffffffff
9965 12:21:07.117727 INFO: [APUAPC] D10_APC_1: 0xffffffff
9966 12:21:07.121133 INFO: [APUAPC] D10_APC_2: 0x3fffff
9967 12:21:07.124594 INFO: [APUAPC] D10_APC_3: 0x0
9968 12:21:07.127851 INFO: [APUAPC] D11_APC_0: 0xffffffff
9969 12:21:07.130759 INFO: [APUAPC] D11_APC_1: 0xffffffff
9970 12:21:07.134536 INFO: [APUAPC] D11_APC_2: 0x3fffff
9971 12:21:07.137530 INFO: [APUAPC] D11_APC_3: 0x0
9972 12:21:07.141306 INFO: [APUAPC] D12_APC_0: 0xffffffff
9973 12:21:07.144320 INFO: [APUAPC] D12_APC_1: 0xffffffff
9974 12:21:07.147859 INFO: [APUAPC] D12_APC_2: 0x3fffff
9975 12:21:07.150766 INFO: [APUAPC] D12_APC_3: 0x0
9976 12:21:07.154107 INFO: [APUAPC] D13_APC_0: 0xffffffff
9977 12:21:07.157388 INFO: [APUAPC] D13_APC_1: 0xffffffff
9978 12:21:07.160634 INFO: [APUAPC] D13_APC_2: 0x3fffff
9979 12:21:07.163853 INFO: [APUAPC] D13_APC_3: 0x0
9980 12:21:07.167307 INFO: [APUAPC] D14_APC_0: 0xffffffff
9981 12:21:07.170827 INFO: [APUAPC] D14_APC_1: 0xffffffff
9982 12:21:07.174366 INFO: [APUAPC] D14_APC_2: 0x3fffff
9983 12:21:07.177224 INFO: [APUAPC] D14_APC_3: 0x0
9984 12:21:07.180582 INFO: [APUAPC] D15_APC_0: 0xffffffff
9985 12:21:07.183817 INFO: [APUAPC] D15_APC_1: 0xffffffff
9986 12:21:07.187360 INFO: [APUAPC] D15_APC_2: 0x3fffff
9987 12:21:07.190700 INFO: [APUAPC] D15_APC_3: 0x0
9988 12:21:07.194122 INFO: [APUAPC] APC_CON: 0x4
9989 12:21:07.197132 INFO: [NOCDAPC] D0_APC_0: 0x0
9990 12:21:07.200665 INFO: [NOCDAPC] D0_APC_1: 0x0
9991 12:21:07.204292 INFO: [NOCDAPC] D1_APC_0: 0x0
9992 12:21:07.207240 INFO: [NOCDAPC] D1_APC_1: 0xfff
9993 12:21:07.210840 INFO: [NOCDAPC] D2_APC_0: 0x0
9994 12:21:07.213638 INFO: [NOCDAPC] D2_APC_1: 0xfff
9995 12:21:07.213752 INFO: [NOCDAPC] D3_APC_0: 0x0
9996 12:21:07.217007 INFO: [NOCDAPC] D3_APC_1: 0xfff
9997 12:21:07.220362 INFO: [NOCDAPC] D4_APC_0: 0x0
9998 12:21:07.224040 INFO: [NOCDAPC] D4_APC_1: 0xfff
9999 12:21:07.227050 INFO: [NOCDAPC] D5_APC_0: 0x0
10000 12:21:07.230163 INFO: [NOCDAPC] D5_APC_1: 0xfff
10001 12:21:07.233739 INFO: [NOCDAPC] D6_APC_0: 0x0
10002 12:21:07.236759 INFO: [NOCDAPC] D6_APC_1: 0xfff
10003 12:21:07.240269 INFO: [NOCDAPC] D7_APC_0: 0x0
10004 12:21:07.243794 INFO: [NOCDAPC] D7_APC_1: 0xfff
10005 12:21:07.246904 INFO: [NOCDAPC] D8_APC_0: 0x0
10006 12:21:07.250136 INFO: [NOCDAPC] D8_APC_1: 0xfff
10007 12:21:07.250247 INFO: [NOCDAPC] D9_APC_0: 0x0
10008 12:21:07.253700 INFO: [NOCDAPC] D9_APC_1: 0xfff
10009 12:21:07.257094 INFO: [NOCDAPC] D10_APC_0: 0x0
10010 12:21:07.260022 INFO: [NOCDAPC] D10_APC_1: 0xfff
10011 12:21:07.263273 INFO: [NOCDAPC] D11_APC_0: 0x0
10012 12:21:07.267079 INFO: [NOCDAPC] D11_APC_1: 0xfff
10013 12:21:07.270270 INFO: [NOCDAPC] D12_APC_0: 0x0
10014 12:21:07.273341 INFO: [NOCDAPC] D12_APC_1: 0xfff
10015 12:21:07.276993 INFO: [NOCDAPC] D13_APC_0: 0x0
10016 12:21:07.279849 INFO: [NOCDAPC] D13_APC_1: 0xfff
10017 12:21:07.283309 INFO: [NOCDAPC] D14_APC_0: 0x0
10018 12:21:07.286766 INFO: [NOCDAPC] D14_APC_1: 0xfff
10019 12:21:07.290371 INFO: [NOCDAPC] D15_APC_0: 0x0
10020 12:21:07.293314 INFO: [NOCDAPC] D15_APC_1: 0xfff
10021 12:21:07.293553 INFO: [NOCDAPC] APC_CON: 0x4
10022 12:21:07.296764 INFO: [APUAPC] set_apusys_apc done
10023 12:21:07.300067 INFO: [DEVAPC] devapc_init done
10024 12:21:07.306597 INFO: GICv3 without legacy support detected.
10025 12:21:07.310322 INFO: ARM GICv3 driver initialized in EL3
10026 12:21:07.313612 INFO: Maximum SPI INTID supported: 639
10027 12:21:07.316692 INFO: BL31: Initializing runtime services
10028 12:21:07.323248 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10029 12:21:07.326855 INFO: SPM: enable CPC mode
10030 12:21:07.329951 INFO: mcdi ready for mcusys-off-idle and system suspend
10031 12:21:07.336537 INFO: BL31: Preparing for EL3 exit to normal world
10032 12:21:07.339737 INFO: Entry point address = 0x80000000
10033 12:21:07.339858 INFO: SPSR = 0x8
10034 12:21:07.347043
10035 12:21:07.347175
10036 12:21:07.347271
10037 12:21:07.349993 Starting depthcharge on Spherion...
10038 12:21:07.350096
10039 12:21:07.350186 Wipe memory regions:
10040 12:21:07.350278
10041 12:21:07.351023 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10042 12:21:07.351127 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10043 12:21:07.351211 Setting prompt string to ['asurada:']
10044 12:21:07.351335 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10045 12:21:07.353404 [0x00000040000000, 0x00000054600000)
10046 12:21:07.475777
10047 12:21:07.475928 [0x00000054660000, 0x00000080000000)
10048 12:21:07.736459
10049 12:21:07.736613 [0x000000821a7280, 0x000000ffe64000)
10050 12:21:08.481632
10051 12:21:08.481787 [0x00000100000000, 0x00000240000000)
10052 12:21:10.371545
10053 12:21:10.375352 Initializing XHCI USB controller at 0x11200000.
10054 12:21:11.412744
10055 12:21:11.416121 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10056 12:21:11.416241
10057 12:21:11.416323
10058 12:21:11.416411
10059 12:21:11.416696 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 12:21:11.517086 asurada: tftpboot 192.168.201.1 11299287/tftp-deploy-zw2vi42m/kernel/image.itb 11299287/tftp-deploy-zw2vi42m/kernel/cmdline
10062 12:21:11.517251 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 12:21:11.517336 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10064 12:21:11.521351 tftpboot 192.168.201.1 11299287/tftp-deploy-zw2vi42m/kernel/image.itp-deploy-zw2vi42m/kernel/cmdline
10065 12:21:11.521443
10066 12:21:11.521505 Waiting for link
10067 12:21:11.682299
10068 12:21:11.682456 R8152: Initializing
10069 12:21:11.682524
10070 12:21:11.685199 Version 6 (ocp_data = 5c30)
10071 12:21:11.685283
10072 12:21:11.688485 R8152: Done initializing
10073 12:21:11.688568
10074 12:21:11.688633 Adding net device
10075 12:21:13.592253
10076 12:21:13.592406 done.
10077 12:21:13.592472
10078 12:21:13.592531 MAC: 00:24:32:30:78:ff
10079 12:21:13.592587
10080 12:21:13.595668 Sending DHCP discover... done.
10081 12:21:13.595754
10082 12:21:13.598708 Waiting for reply... done.
10083 12:21:13.598795
10084 12:21:13.602416 Sending DHCP request... done.
10085 12:21:13.602502
10086 12:21:13.608393 Waiting for reply... done.
10087 12:21:13.608489
10088 12:21:13.608554 My ip is 192.168.201.21
10089 12:21:13.608613
10090 12:21:13.611526 The DHCP server ip is 192.168.201.1
10091 12:21:13.611612
10092 12:21:13.618170 TFTP server IP predefined by user: 192.168.201.1
10093 12:21:13.618268
10094 12:21:13.624799 Bootfile predefined by user: 11299287/tftp-deploy-zw2vi42m/kernel/image.itb
10095 12:21:13.624895
10096 12:21:13.627811 Sending tftp read request... done.
10097 12:21:13.627915
10098 12:21:13.631866 Waiting for the transfer...
10099 12:21:13.631954
10100 12:21:14.209182 00000000 ################################################################
10101 12:21:14.209339
10102 12:21:14.736862 00080000 ################################################################
10103 12:21:14.737001
10104 12:21:15.280789 00100000 ################################################################
10105 12:21:15.280928
10106 12:21:15.851289 00180000 ################################################################
10107 12:21:15.851477
10108 12:21:16.428023 00200000 ################################################################
10109 12:21:16.428179
10110 12:21:16.977493 00280000 ################################################################
10111 12:21:16.977646
10112 12:21:17.505228 00300000 ################################################################
10113 12:21:17.505384
10114 12:21:18.092722 00380000 ################################################################
10115 12:21:18.093265
10116 12:21:18.739313 00400000 ################################################################
10117 12:21:18.739502
10118 12:21:19.345618 00480000 ################################################################
10119 12:21:19.345774
10120 12:21:19.974673 00500000 ################################################################
10121 12:21:19.975189
10122 12:21:20.605368 00580000 ################################################################
10123 12:21:20.605500
10124 12:21:21.167547 00600000 ################################################################
10125 12:21:21.167679
10126 12:21:21.758094 00680000 ################################################################
10127 12:21:21.758649
10128 12:21:22.454276 00700000 ################################################################
10129 12:21:22.454823
10130 12:21:23.094783 00780000 ################################################################
10131 12:21:23.094970
10132 12:21:23.635043 00800000 ################################################################
10133 12:21:23.635182
10134 12:21:24.178926 00880000 ################################################################
10135 12:21:24.179131
10136 12:21:24.723777 00900000 ################################################################
10137 12:21:24.723914
10138 12:21:25.274985 00980000 ################################################################
10139 12:21:25.275136
10140 12:21:25.832314 00a00000 ################################################################
10141 12:21:25.832465
10142 12:21:26.366678 00a80000 ################################################################
10143 12:21:26.366816
10144 12:21:26.931507 00b00000 ################################################################
10145 12:21:26.931644
10146 12:21:27.477148 00b80000 ################################################################
10147 12:21:27.477286
10148 12:21:28.018236 00c00000 ################################################################
10149 12:21:28.018412
10150 12:21:28.548482 00c80000 ################################################################
10151 12:21:28.548632
10152 12:21:29.090036 00d00000 ################################################################
10153 12:21:29.090223
10154 12:21:29.613639 00d80000 ################################################################
10155 12:21:29.613792
10156 12:21:30.143127 00e00000 ################################################################
10157 12:21:30.143286
10158 12:21:30.674823 00e80000 ################################################################
10159 12:21:30.674963
10160 12:21:31.211184 00f00000 ################################################################
10161 12:21:31.211359
10162 12:21:31.735286 00f80000 ################################################################
10163 12:21:31.735457
10164 12:21:32.272775 01000000 ################################################################
10165 12:21:32.272935
10166 12:21:32.804764 01080000 ################################################################
10167 12:21:32.804931
10168 12:21:33.334208 01100000 ################################################################
10169 12:21:33.334370
10170 12:21:33.861449 01180000 ################################################################
10171 12:21:33.861609
10172 12:21:34.391207 01200000 ################################################################
10173 12:21:34.391377
10174 12:21:34.914861 01280000 ################################################################
10175 12:21:34.914997
10176 12:21:35.458276 01300000 ################################################################
10177 12:21:35.458414
10178 12:21:35.999647 01380000 ################################################################
10179 12:21:35.999785
10180 12:21:36.518233 01400000 ################################################################
10181 12:21:36.518365
10182 12:21:37.053057 01480000 ################################################################
10183 12:21:37.053192
10184 12:21:37.599743 01500000 ################################################################
10185 12:21:37.599877
10186 12:21:38.147223 01580000 ################################################################
10187 12:21:38.147434
10188 12:21:38.694805 01600000 ################################################################
10189 12:21:38.694945
10190 12:21:39.262559 01680000 ################################################################
10191 12:21:39.262696
10192 12:21:39.848901 01700000 ################################################################
10193 12:21:39.849042
10194 12:21:40.377843 01780000 ################################################################
10195 12:21:40.377990
10196 12:21:40.938049 01800000 ################################################################
10197 12:21:40.938195
10198 12:21:41.503238 01880000 ################################################################
10199 12:21:41.503447
10200 12:21:42.072231 01900000 ################################################################
10201 12:21:42.072421
10202 12:21:42.778661 01980000 ################################################################
10203 12:21:42.779191
10204 12:21:43.481114 01a00000 ################################################################
10205 12:21:43.481625
10206 12:21:44.171663 01a80000 ################################################################
10207 12:21:44.171799
10208 12:21:44.737963 01b00000 ################################################################
10209 12:21:44.738119
10210 12:21:45.306682 01b80000 ################################################################
10211 12:21:45.306817
10212 12:21:45.894779 01c00000 ################################################################
10213 12:21:45.894912
10214 12:21:46.466371 01c80000 ################################################################
10215 12:21:46.466949
10216 12:21:47.131280 01d00000 ################################################################
10217 12:21:47.131801
10218 12:21:47.787188 01d80000 ################################################################
10219 12:21:47.787800
10220 12:21:48.476934 01e00000 ################################################################
10221 12:21:48.477070
10222 12:21:49.120470 01e80000 ################################################################
10223 12:21:49.120615
10224 12:21:49.755152 01f00000 ################################################################
10225 12:21:49.755296
10226 12:21:50.376933 01f80000 ################################################################
10227 12:21:50.377083
10228 12:21:51.003616 02000000 ################################################################
10229 12:21:51.003767
10230 12:21:51.665005 02080000 ################################################################
10231 12:21:51.665528
10232 12:21:52.367588 02100000 ################################################################
10233 12:21:52.368104
10234 12:21:53.062427 02180000 ################################################################
10235 12:21:53.062942
10236 12:21:53.768002 02200000 ################################################################
10237 12:21:53.768517
10238 12:21:54.460535 02280000 ################################################################
10239 12:21:54.461055
10240 12:21:55.153649 02300000 ################################################################
10241 12:21:55.154161
10242 12:21:55.835260 02380000 ################################################################
10243 12:21:55.835834
10244 12:21:56.529541 02400000 ################################################################
10245 12:21:56.530104
10246 12:21:57.217363 02480000 ################################################################
10247 12:21:57.217883
10248 12:21:57.910515 02500000 ################################################################
10249 12:21:57.911067
10250 12:21:58.614999 02580000 ################################################################
10251 12:21:58.615597
10252 12:21:59.306597 02600000 ################################################################
10253 12:21:59.307252
10254 12:22:00.004517 02680000 ################################################################
10255 12:22:00.005081
10256 12:22:00.692407 02700000 ################################################################
10257 12:22:00.693047
10258 12:22:01.334679 02780000 ################################################################
10259 12:22:01.334826
10260 12:22:01.925931 02800000 ################################################################
10261 12:22:01.926135
10262 12:22:02.621558 02880000 ################################################################
10263 12:22:02.622065
10264 12:22:03.316238 02900000 ################################################################
10265 12:22:03.316769
10266 12:22:03.937722 02980000 ################################################################
10267 12:22:03.937870
10268 12:22:04.533717 02a00000 ################################################################
10269 12:22:04.533863
10270 12:22:05.123804 02a80000 ################################################################
10271 12:22:05.123941
10272 12:22:05.797082 02b00000 ################################################################
10273 12:22:05.797594
10274 12:22:06.455389 02b80000 ################################################################
10275 12:22:06.455527
10276 12:22:07.084123 02c00000 ################################################################
10277 12:22:07.084258
10278 12:22:07.707755 02c80000 ################################################################
10279 12:22:07.707904
10280 12:22:08.281733 02d00000 ################################################################
10281 12:22:08.281880
10282 12:22:08.858363 02d80000 ################################################################
10283 12:22:08.858512
10284 12:22:09.451039 02e00000 ################################################################
10285 12:22:09.451174
10286 12:22:10.044376 02e80000 ################################################################
10287 12:22:10.044520
10288 12:22:10.625541 02f00000 ################################################################
10289 12:22:10.625679
10290 12:22:11.224761 02f80000 ################################################################
10291 12:22:11.224896
10292 12:22:11.841146 03000000 ################################################################
10293 12:22:11.841297
10294 12:22:12.502137 03080000 ################################################################
10295 12:22:12.502664
10296 12:22:13.124040 03100000 ################################################################
10297 12:22:13.124195
10298 12:22:13.721160 03180000 ################################################################
10299 12:22:13.721304
10300 12:22:14.308249 03200000 ################################################################
10301 12:22:14.308379
10302 12:22:14.886046 03280000 ################################################################
10303 12:22:14.886202
10304 12:22:15.485893 03300000 ################################################################
10305 12:22:15.486034
10306 12:22:16.087024 03380000 ################################################################
10307 12:22:16.087166
10308 12:22:16.746085 03400000 ################################################################
10309 12:22:16.746601
10310 12:22:17.449078 03480000 ################################################################
10311 12:22:17.449617
10312 12:22:18.153919 03500000 ################################################################
10313 12:22:18.154474
10314 12:22:18.866157 03580000 ################################################################
10315 12:22:18.866670
10316 12:22:19.559973 03600000 ################################################################
10317 12:22:19.560522
10318 12:22:20.264311 03680000 ################################################################
10319 12:22:20.264822
10320 12:22:20.942513 03700000 ################################################################
10321 12:22:20.943023
10322 12:22:21.442297 03780000 ################################################# done.
10323 12:22:21.442844
10324 12:22:21.445282 The bootfile was 58589394 bytes long.
10325 12:22:21.445753
10326 12:22:21.448691 Sending tftp read request... done.
10327 12:22:21.449309
10328 12:22:21.453327 Waiting for the transfer...
10329 12:22:21.453803
10330 12:22:21.454164 00000000 # done.
10331 12:22:21.454516
10332 12:22:21.459807 Command line loaded dynamically from TFTP file: 11299287/tftp-deploy-zw2vi42m/kernel/cmdline
10333 12:22:21.463061
10334 12:22:21.476494 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10335 12:22:21.476968
10336 12:22:21.477329 Loading FIT.
10337 12:22:21.477668
10338 12:22:21.479666 Image ramdisk-1 has 47499707 bytes.
10339 12:22:21.480126
10340 12:22:21.483170 Image fdt-1 has 47278 bytes.
10341 12:22:21.483674
10342 12:22:21.485999 Image kernel-1 has 11040376 bytes.
10343 12:22:21.486457
10344 12:22:21.492934 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10345 12:22:21.493404
10346 12:22:21.513540 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10347 12:22:21.514123
10348 12:22:21.515997 Choosing best match conf-1 for compat google,spherion-rev2.
10349 12:22:21.521218
10350 12:22:21.525888 Connected to device vid:did:rid of 1ae0:0028:00
10351 12:22:21.533837
10352 12:22:21.537445 tpm_get_response: command 0x17b, return code 0x0
10353 12:22:21.538000
10354 12:22:21.540536 ec_init: CrosEC protocol v3 supported (256, 248)
10355 12:22:21.544443
10356 12:22:21.547589 tpm_cleanup: add release locality here.
10357 12:22:21.548050
10358 12:22:21.548410 Shutting down all USB controllers.
10359 12:22:21.551006
10360 12:22:21.551637 Removing current net device
10361 12:22:21.552014
10362 12:22:21.557361 Exiting depthcharge with code 4 at timestamp: 103514078
10363 12:22:21.557899
10364 12:22:21.560993 LZMA decompressing kernel-1 to 0x821a6718
10365 12:22:21.561555
10366 12:22:21.564402 LZMA decompressing kernel-1 to 0x40000000
10367 12:22:22.951340
10368 12:22:22.951990 jumping to kernel
10369 12:22:22.953584 end: 2.2.4 bootloader-commands (duration 00:01:16) [common]
10370 12:22:22.954121 start: 2.2.5 auto-login-action (timeout 00:03:10) [common]
10371 12:22:22.954524 Setting prompt string to ['Linux version [0-9]']
10372 12:22:22.954895 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10373 12:22:22.955267 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10374 12:22:23.034105
10375 12:22:23.037035 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10376 12:22:23.040775 start: 2.2.5.1 login-action (timeout 00:03:10) [common]
10377 12:22:23.041322 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10378 12:22:23.041723 Setting prompt string to []
10379 12:22:23.042155 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10380 12:22:23.042558 Using line separator: #'\n'#
10381 12:22:23.042891 No login prompt set.
10382 12:22:23.043222 Parsing kernel messages
10383 12:22:23.043709 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10384 12:22:23.044287 [login-action] Waiting for messages, (timeout 00:03:10)
10385 12:22:23.060257 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j14831-arm64-gcc-10-defconfig-arm64-chromebook-g8jrt) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 16 12:04:53 UTC 2023
10386 12:22:23.063550 [ 0.000000] random: crng init done
10387 12:22:23.070256 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10388 12:22:23.073654 [ 0.000000] efi: UEFI not found.
10389 12:22:23.080250 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10390 12:22:23.086576 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10391 12:22:23.096531 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10392 12:22:23.106841 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10393 12:22:23.113177 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10394 12:22:23.120157 [ 0.000000] printk: bootconsole [mtk8250] enabled
10395 12:22:23.123196 [ 0.000000] NUMA: No NUMA configuration found
10396 12:22:23.133323 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10397 12:22:23.136170 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10398 12:22:23.139588 [ 0.000000] Zone ranges:
10399 12:22:23.146288 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10400 12:22:23.149635 [ 0.000000] DMA32 empty
10401 12:22:23.156123 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10402 12:22:23.159665 [ 0.000000] Movable zone start for each node
10403 12:22:23.162536 [ 0.000000] Early memory node ranges
10404 12:22:23.169666 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10405 12:22:23.176056 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10406 12:22:23.182876 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10407 12:22:23.189062 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10408 12:22:23.192666 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10409 12:22:23.202540 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10410 12:22:23.257200 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10411 12:22:23.264103 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10412 12:22:23.270917 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10413 12:22:23.274360 [ 0.000000] psci: probing for conduit method from DT.
10414 12:22:23.280716 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10415 12:22:23.283913 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10416 12:22:23.290226 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10417 12:22:23.293886 [ 0.000000] psci: SMC Calling Convention v1.2
10418 12:22:23.300214 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10419 12:22:23.303348 [ 0.000000] Detected VIPT I-cache on CPU0
10420 12:22:23.310136 [ 0.000000] CPU features: detected: GIC system register CPU interface
10421 12:22:23.316622 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10422 12:22:23.323763 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10423 12:22:23.330047 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10424 12:22:23.340059 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10425 12:22:23.346368 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10426 12:22:23.349591 [ 0.000000] alternatives: applying boot alternatives
10427 12:22:23.356390 [ 0.000000] Fallback order for Node 0: 0
10428 12:22:23.362583 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10429 12:22:23.366276 [ 0.000000] Policy zone: Normal
10430 12:22:23.379453 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10431 12:22:23.389809 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10432 12:22:23.402140 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10433 12:22:23.412056 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10434 12:22:23.418392 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10435 12:22:23.421802 <6>[ 0.000000] software IO TLB: area num 8.
10436 12:22:23.477479 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10437 12:22:23.626854 <6>[ 0.000000] Memory: 7923172K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 429596K reserved, 32768K cma-reserved)
10438 12:22:23.633593 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10439 12:22:23.639849 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10440 12:22:23.643327 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10441 12:22:23.649903 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10442 12:22:23.656327 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10443 12:22:23.659981 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10444 12:22:23.669567 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10445 12:22:23.676115 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10446 12:22:23.682463 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10447 12:22:23.689422 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10448 12:22:23.693289 <6>[ 0.000000] GICv3: 608 SPIs implemented
10449 12:22:23.695744 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10450 12:22:23.703298 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10451 12:22:23.706392 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10452 12:22:23.712835 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10453 12:22:23.725923 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10454 12:22:23.736248 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10455 12:22:23.745752 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10456 12:22:23.753356 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10457 12:22:23.766605 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10458 12:22:23.772948 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10459 12:22:23.779935 <6>[ 0.009238] Console: colour dummy device 80x25
10460 12:22:23.789557 <6>[ 0.013965] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10461 12:22:23.796358 <6>[ 0.024473] pid_max: default: 32768 minimum: 301
10462 12:22:23.799917 <6>[ 0.029345] LSM: Security Framework initializing
10463 12:22:23.806074 <6>[ 0.034284] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10464 12:22:23.816228 <6>[ 0.042145] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10465 12:22:23.825879 <6>[ 0.051569] cblist_init_generic: Setting adjustable number of callback queues.
10466 12:22:23.832646 <6>[ 0.059061] cblist_init_generic: Setting shift to 3 and lim to 1.
10467 12:22:23.839232 <6>[ 0.065400] cblist_init_generic: Setting adjustable number of callback queues.
10468 12:22:23.846013 <6>[ 0.072826] cblist_init_generic: Setting shift to 3 and lim to 1.
10469 12:22:23.849105 <6>[ 0.079224] rcu: Hierarchical SRCU implementation.
10470 12:22:23.855903 <6>[ 0.084238] rcu: Max phase no-delay instances is 1000.
10471 12:22:23.862802 <6>[ 0.091265] EFI services will not be available.
10472 12:22:23.865745 <6>[ 0.096265] smp: Bringing up secondary CPUs ...
10473 12:22:23.874507 <6>[ 0.101315] Detected VIPT I-cache on CPU1
10474 12:22:23.880937 <6>[ 0.101388] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10475 12:22:23.887970 <6>[ 0.101419] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10476 12:22:23.891227 <6>[ 0.101751] Detected VIPT I-cache on CPU2
10477 12:22:23.897331 <6>[ 0.101798] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10478 12:22:23.904506 <6>[ 0.101813] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10479 12:22:23.911470 <6>[ 0.102071] Detected VIPT I-cache on CPU3
10480 12:22:23.917459 <6>[ 0.102117] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10481 12:22:23.923950 <6>[ 0.102131] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10482 12:22:23.927590 <6>[ 0.102433] CPU features: detected: Spectre-v4
10483 12:22:23.934186 <6>[ 0.102439] CPU features: detected: Spectre-BHB
10484 12:22:23.937251 <6>[ 0.102444] Detected PIPT I-cache on CPU4
10485 12:22:23.943900 <6>[ 0.102501] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10486 12:22:23.950364 <6>[ 0.102518] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10487 12:22:23.957521 <6>[ 0.102812] Detected PIPT I-cache on CPU5
10488 12:22:23.963809 <6>[ 0.102875] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10489 12:22:23.970367 <6>[ 0.102892] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10490 12:22:23.973649 <6>[ 0.103176] Detected PIPT I-cache on CPU6
10491 12:22:23.980349 <6>[ 0.103241] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10492 12:22:23.986773 <6>[ 0.103258] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10493 12:22:23.993878 <6>[ 0.103555] Detected PIPT I-cache on CPU7
10494 12:22:24.000009 <6>[ 0.103619] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10495 12:22:24.006728 <6>[ 0.103637] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10496 12:22:24.010478 <6>[ 0.103684] smp: Brought up 1 node, 8 CPUs
10497 12:22:24.016581 <6>[ 0.244942] SMP: Total of 8 processors activated.
10498 12:22:24.019959 <6>[ 0.249863] CPU features: detected: 32-bit EL0 Support
10499 12:22:24.029793 <6>[ 0.255260] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10500 12:22:24.036529 <6>[ 0.264060] CPU features: detected: Common not Private translations
10501 12:22:24.039470 <6>[ 0.270536] CPU features: detected: CRC32 instructions
10502 12:22:24.046370 <6>[ 0.275921] CPU features: detected: RCpc load-acquire (LDAPR)
10503 12:22:24.052697 <6>[ 0.281881] CPU features: detected: LSE atomic instructions
10504 12:22:24.059770 <6>[ 0.287698] CPU features: detected: Privileged Access Never
10505 12:22:24.066019 <6>[ 0.293514] CPU features: detected: RAS Extension Support
10506 12:22:24.073023 <6>[ 0.299123] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10507 12:22:24.076497 <6>[ 0.306340] CPU: All CPU(s) started at EL2
10508 12:22:24.082739 <6>[ 0.310657] alternatives: applying system-wide alternatives
10509 12:22:24.091690 <6>[ 0.321385] devtmpfs: initialized
10510 12:22:24.108083 <6>[ 0.330346] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10511 12:22:24.114084 <6>[ 0.340306] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10512 12:22:24.120920 <6>[ 0.348320] pinctrl core: initialized pinctrl subsystem
10513 12:22:24.123849 <6>[ 0.354999] DMI not present or invalid.
10514 12:22:24.130464 <6>[ 0.359411] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10515 12:22:24.140632 <6>[ 0.366265] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10516 12:22:24.147062 <6>[ 0.373832] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10517 12:22:24.156813 <6>[ 0.382044] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10518 12:22:24.160693 <6>[ 0.390287] audit: initializing netlink subsys (disabled)
10519 12:22:24.170411 <5>[ 0.395980] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10520 12:22:24.176714 <6>[ 0.396701] thermal_sys: Registered thermal governor 'step_wise'
10521 12:22:24.183823 <6>[ 0.403946] thermal_sys: Registered thermal governor 'power_allocator'
10522 12:22:24.186977 <6>[ 0.410203] cpuidle: using governor menu
10523 12:22:24.193966 <6>[ 0.421164] NET: Registered PF_QIPCRTR protocol family
10524 12:22:24.199838 <6>[ 0.426643] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10525 12:22:24.203203 <6>[ 0.433749] ASID allocator initialised with 32768 entries
10526 12:22:24.210650 <6>[ 0.440320] Serial: AMBA PL011 UART driver
10527 12:22:24.219268 <4>[ 0.449192] Trying to register duplicate clock ID: 134
10528 12:22:24.276000 <6>[ 0.508712] KASLR enabled
10529 12:22:24.290234 <6>[ 0.516459] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10530 12:22:24.296739 <6>[ 0.523471] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10531 12:22:24.303403 <6>[ 0.529963] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10532 12:22:24.309770 <6>[ 0.536968] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10533 12:22:24.316761 <6>[ 0.543455] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10534 12:22:24.323037 <6>[ 0.550459] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10535 12:22:24.329515 <6>[ 0.556944] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10536 12:22:24.336523 <6>[ 0.563950] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10537 12:22:24.339838 <6>[ 0.571479] ACPI: Interpreter disabled.
10538 12:22:24.348318 <6>[ 0.577913] iommu: Default domain type: Translated
10539 12:22:24.354644 <6>[ 0.583027] iommu: DMA domain TLB invalidation policy: strict mode
10540 12:22:24.358292 <5>[ 0.589679] SCSI subsystem initialized
10541 12:22:24.364648 <6>[ 0.593844] usbcore: registered new interface driver usbfs
10542 12:22:24.371331 <6>[ 0.599575] usbcore: registered new interface driver hub
10543 12:22:24.374790 <6>[ 0.605124] usbcore: registered new device driver usb
10544 12:22:24.381390 <6>[ 0.611229] pps_core: LinuxPPS API ver. 1 registered
10545 12:22:24.391722 <6>[ 0.616421] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10546 12:22:24.395200 <6>[ 0.625768] PTP clock support registered
10547 12:22:24.397905 <6>[ 0.630013] EDAC MC: Ver: 3.0.0
10548 12:22:24.405651 <6>[ 0.635169] FPGA manager framework
10549 12:22:24.409283 <6>[ 0.638849] Advanced Linux Sound Architecture Driver Initialized.
10550 12:22:24.412725 <6>[ 0.645627] vgaarb: loaded
10551 12:22:24.419673 <6>[ 0.648802] clocksource: Switched to clocksource arch_sys_counter
10552 12:22:24.425887 <5>[ 0.655239] VFS: Disk quotas dquot_6.6.0
10553 12:22:24.432689 <6>[ 0.659422] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10554 12:22:24.435902 <6>[ 0.666612] pnp: PnP ACPI: disabled
10555 12:22:24.444009 <6>[ 0.673299] NET: Registered PF_INET protocol family
10556 12:22:24.453691 <6>[ 0.678889] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10557 12:22:24.465165 <6>[ 0.691205] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10558 12:22:24.474728 <6>[ 0.700020] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10559 12:22:24.481561 <6>[ 0.707992] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10560 12:22:24.492053 <6>[ 0.716692] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10561 12:22:24.498622 <6>[ 0.726408] TCP: Hash tables configured (established 65536 bind 65536)
10562 12:22:24.504667 <6>[ 0.733267] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10563 12:22:24.514422 <6>[ 0.740465] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10564 12:22:24.517805 <6>[ 0.748169] NET: Registered PF_UNIX/PF_LOCAL protocol family
10565 12:22:24.524645 <6>[ 0.754350] RPC: Registered named UNIX socket transport module.
10566 12:22:24.531461 <6>[ 0.760506] RPC: Registered udp transport module.
10567 12:22:24.534756 <6>[ 0.765439] RPC: Registered tcp transport module.
10568 12:22:24.541430 <6>[ 0.770370] RPC: Registered tcp NFSv4.1 backchannel transport module.
10569 12:22:24.548367 <6>[ 0.777036] PCI: CLS 0 bytes, default 64
10570 12:22:24.550716 <6>[ 0.781435] Unpacking initramfs...
10571 12:22:24.574692 <6>[ 0.801011] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10572 12:22:24.584777 <6>[ 0.809644] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10573 12:22:24.588182 <6>[ 0.818514] kvm [1]: IPA Size Limit: 40 bits
10574 12:22:24.594804 <6>[ 0.823046] kvm [1]: GICv3: no GICV resource entry
10575 12:22:24.598363 <6>[ 0.828068] kvm [1]: disabling GICv2 emulation
10576 12:22:24.604696 <6>[ 0.832755] kvm [1]: GIC system register CPU interface enabled
10577 12:22:24.607963 <6>[ 0.838941] kvm [1]: vgic interrupt IRQ18
10578 12:22:24.614191 <6>[ 0.843297] kvm [1]: VHE mode initialized successfully
10579 12:22:24.621077 <5>[ 0.849822] Initialise system trusted keyrings
10580 12:22:24.627557 <6>[ 0.854629] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10581 12:22:24.635292 <6>[ 0.864637] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10582 12:22:24.641788 <5>[ 0.871040] NFS: Registering the id_resolver key type
10583 12:22:24.644956 <5>[ 0.876349] Key type id_resolver registered
10584 12:22:24.651497 <5>[ 0.880764] Key type id_legacy registered
10585 12:22:24.658192 <6>[ 0.885043] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10586 12:22:24.665050 <6>[ 0.891964] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10587 12:22:24.671099 <6>[ 0.899679] 9p: Installing v9fs 9p2000 file system support
10588 12:22:24.708100 <5>[ 0.937655] Key type asymmetric registered
10589 12:22:24.711542 <5>[ 0.941987] Asymmetric key parser 'x509' registered
10590 12:22:24.721167 <6>[ 0.947131] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10591 12:22:24.724545 <6>[ 0.954744] io scheduler mq-deadline registered
10592 12:22:24.727943 <6>[ 0.959522] io scheduler kyber registered
10593 12:22:24.746983 <6>[ 0.976778] EINJ: ACPI disabled.
10594 12:22:24.780144 <4>[ 1.003231] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 12:22:24.790411 <4>[ 1.013892] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10596 12:22:24.805676 <6>[ 1.035181] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10597 12:22:24.813584 <6>[ 1.043248] printk: console [ttyS0] disabled
10598 12:22:24.841416 <6>[ 1.067896] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10599 12:22:24.848387 <6>[ 1.077376] printk: console [ttyS0] enabled
10600 12:22:24.851997 <6>[ 1.077376] printk: console [ttyS0] enabled
10601 12:22:24.857935 <6>[ 1.086272] printk: bootconsole [mtk8250] disabled
10602 12:22:24.861203 <6>[ 1.086272] printk: bootconsole [mtk8250] disabled
10603 12:22:24.868181 <6>[ 1.097549] SuperH (H)SCI(F) driver initialized
10604 12:22:24.871572 <6>[ 1.102820] msm_serial: driver initialized
10605 12:22:24.885966 <6>[ 1.111839] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10606 12:22:24.895718 <6>[ 1.120386] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10607 12:22:24.902142 <6>[ 1.128928] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10608 12:22:24.911843 <6>[ 1.137557] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10609 12:22:24.922286 <6>[ 1.146263] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10610 12:22:24.928803 <6>[ 1.154977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10611 12:22:24.938456 <6>[ 1.163516] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10612 12:22:24.945193 <6>[ 1.172319] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10613 12:22:24.954923 <6>[ 1.180862] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10614 12:22:24.966547 <6>[ 1.196265] loop: module loaded
10615 12:22:24.973033 <6>[ 1.202377] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10616 12:22:24.996496 <4>[ 1.225802] mtk-pmic-keys: Failed to locate of_node [id: -1]
10617 12:22:25.003206 <6>[ 1.232673] megasas: 07.719.03.00-rc1
10618 12:22:25.012519 <6>[ 1.242267] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10619 12:22:25.019635 <6>[ 1.248202] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10620 12:22:25.035344 <6>[ 1.264898] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10621 12:22:25.092174 <6>[ 1.314987] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10622 12:22:26.574174 <6>[ 2.803701] Freeing initrd memory: 46380K
10623 12:22:26.584466 <6>[ 2.814028] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10624 12:22:26.595495 <6>[ 2.824845] tun: Universal TUN/TAP device driver, 1.6
10625 12:22:26.598950 <6>[ 2.830907] thunder_xcv, ver 1.0
10626 12:22:26.601562 <6>[ 2.834410] thunder_bgx, ver 1.0
10627 12:22:26.604732 <6>[ 2.837904] nicpf, ver 1.0
10628 12:22:26.615569 <6>[ 2.841930] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10629 12:22:26.618417 <6>[ 2.849405] hns3: Copyright (c) 2017 Huawei Corporation.
10630 12:22:26.625294 <6>[ 2.854992] hclge is initializing
10631 12:22:26.628563 <6>[ 2.858574] e1000: Intel(R) PRO/1000 Network Driver
10632 12:22:26.635550 <6>[ 2.863703] e1000: Copyright (c) 1999-2006 Intel Corporation.
10633 12:22:26.639052 <6>[ 2.869718] e1000e: Intel(R) PRO/1000 Network Driver
10634 12:22:26.645326 <6>[ 2.874933] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10635 12:22:26.651941 <6>[ 2.881122] igb: Intel(R) Gigabit Ethernet Network Driver
10636 12:22:26.658447 <6>[ 2.886772] igb: Copyright (c) 2007-2014 Intel Corporation.
10637 12:22:26.665157 <6>[ 2.892608] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10638 12:22:26.671845 <6>[ 2.899126] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10639 12:22:26.675142 <6>[ 2.905594] sky2: driver version 1.30
10640 12:22:26.681599 <6>[ 2.910594] VFIO - User Level meta-driver version: 0.3
10641 12:22:26.689097 <6>[ 2.918884] usbcore: registered new interface driver usb-storage
10642 12:22:26.695796 <6>[ 2.925328] usbcore: registered new device driver onboard-usb-hub
10643 12:22:26.704638 <6>[ 2.934470] mt6397-rtc mt6359-rtc: registered as rtc0
10644 12:22:26.714604 <6>[ 2.939937] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-16T12:22:26 UTC (1692188546)
10645 12:22:26.717693 <6>[ 2.949504] i2c_dev: i2c /dev entries driver
10646 12:22:26.734605 <6>[ 2.961202] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10647 12:22:26.756053 <6>[ 2.985205] cpu cpu0: EM: created perf domain
10648 12:22:26.758516 <6>[ 2.990208] cpu cpu4: EM: created perf domain
10649 12:22:26.766053 <6>[ 2.995789] sdhci: Secure Digital Host Controller Interface driver
10650 12:22:26.772914 <6>[ 3.002222] sdhci: Copyright(c) Pierre Ossman
10651 12:22:26.779447 <6>[ 3.007180] Synopsys Designware Multimedia Card Interface Driver
10652 12:22:26.786198 <6>[ 3.013817] sdhci-pltfm: SDHCI platform and OF driver helper
10653 12:22:26.788909 <6>[ 3.013935] mmc0: CQHCI version 5.10
10654 12:22:26.796637 <6>[ 3.023941] ledtrig-cpu: registered to indicate activity on CPUs
10655 12:22:26.802532 <6>[ 3.031013] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10656 12:22:26.809601 <6>[ 3.038070] usbcore: registered new interface driver usbhid
10657 12:22:26.812599 <6>[ 3.043892] usbhid: USB HID core driver
10658 12:22:26.818880 <6>[ 3.048099] spi_master spi0: will run message pump with realtime priority
10659 12:22:26.865423 <6>[ 3.088219] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10660 12:22:26.884797 <6>[ 3.104769] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10661 12:22:26.888754 <6>[ 3.118321] mmc0: Command Queue Engine enabled
10662 12:22:26.895487 <6>[ 3.123072] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10663 12:22:26.902567 <6>[ 3.130220] cros-ec-spi spi0.0: Chrome EC device registered
10664 12:22:26.905180 <6>[ 3.130562] mmcblk0: mmc0:0001 DA4128 116 GiB
10665 12:22:26.920585 <6>[ 3.149678] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10666 12:22:26.927709 <6>[ 3.157358] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10667 12:22:26.937569 <6>[ 3.160399] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10668 12:22:26.940582 <6>[ 3.163289] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10669 12:22:26.947127 <6>[ 3.173143] NET: Registered PF_PACKET protocol family
10670 12:22:26.954525 <6>[ 3.177976] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10671 12:22:26.957371 <6>[ 3.182492] 9pnet: Installing 9P2000 support
10672 12:22:26.963916 <5>[ 3.193522] Key type dns_resolver registered
10673 12:22:26.967529 <6>[ 3.198560] registered taskstats version 1
10674 12:22:26.973834 <5>[ 3.202949] Loading compiled-in X.509 certificates
10675 12:22:27.001741 <4>[ 3.224854] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10676 12:22:27.011777 <4>[ 3.235626] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10677 12:22:27.018594 <3>[ 3.246164] debugfs: File 'uA_load' in directory '/' already present!
10678 12:22:27.024902 <3>[ 3.253018] debugfs: File 'min_uV' in directory '/' already present!
10679 12:22:27.031639 <3>[ 3.259642] debugfs: File 'max_uV' in directory '/' already present!
10680 12:22:27.038541 <3>[ 3.266256] debugfs: File 'constraint_flags' in directory '/' already present!
10681 12:22:27.050069 <3>[ 3.276007] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10682 12:22:27.060550 <6>[ 3.289459] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10683 12:22:27.067412 <6>[ 3.296320] xhci-mtk 11200000.usb: xHCI Host Controller
10684 12:22:27.073577 <6>[ 3.301856] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10685 12:22:27.083463 <6>[ 3.309711] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10686 12:22:27.090495 <6>[ 3.319130] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10687 12:22:27.096741 <6>[ 3.325192] xhci-mtk 11200000.usb: xHCI Host Controller
10688 12:22:27.103155 <6>[ 3.330667] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10689 12:22:27.109524 <6>[ 3.338313] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10690 12:22:27.116311 <6>[ 3.346021] hub 1-0:1.0: USB hub found
10691 12:22:27.119665 <6>[ 3.350034] hub 1-0:1.0: 1 port detected
10692 12:22:27.125961 <6>[ 3.354298] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10693 12:22:27.133118 <6>[ 3.362850] hub 2-0:1.0: USB hub found
10694 12:22:27.136145 <6>[ 3.366853] hub 2-0:1.0: 1 port detected
10695 12:22:27.145284 <6>[ 3.375187] mtk-msdc 11f70000.mmc: Got CD GPIO
10696 12:22:27.155343 <6>[ 3.381684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10697 12:22:27.162017 <6>[ 3.389697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10698 12:22:27.172015 <4>[ 3.397597] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10699 12:22:27.182224 <6>[ 3.407120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10700 12:22:27.188417 <6>[ 3.415198] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10701 12:22:27.195113 <6>[ 3.423214] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10702 12:22:27.205386 <6>[ 3.431135] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10703 12:22:27.211504 <6>[ 3.438953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10704 12:22:27.222250 <6>[ 3.446770] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10705 12:22:27.231849 <6>[ 3.457137] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10706 12:22:27.238217 <6>[ 3.465514] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10707 12:22:27.248402 <6>[ 3.473853] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10708 12:22:27.254921 <6>[ 3.482191] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10709 12:22:27.264555 <6>[ 3.490534] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10710 12:22:27.271713 <6>[ 3.498872] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10711 12:22:27.281174 <6>[ 3.507212] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10712 12:22:27.287987 <6>[ 3.515550] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10713 12:22:27.297591 <6>[ 3.523889] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10714 12:22:27.304222 <6>[ 3.532239] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10715 12:22:27.313901 <6>[ 3.540578] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10716 12:22:27.324366 <6>[ 3.548915] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10717 12:22:27.330358 <6>[ 3.557254] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10718 12:22:27.340610 <6>[ 3.565592] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10719 12:22:27.346946 <6>[ 3.573929] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10720 12:22:27.353580 <6>[ 3.582751] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10721 12:22:27.360235 <6>[ 3.590045] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10722 12:22:27.366907 <6>[ 3.596908] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10723 12:22:27.377245 <6>[ 3.603697] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10724 12:22:27.384041 <6>[ 3.610651] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10725 12:22:27.390367 <6>[ 3.617491] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10726 12:22:27.400228 <6>[ 3.626624] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10727 12:22:27.410449 <6>[ 3.635746] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10728 12:22:27.420263 <6>[ 3.645040] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10729 12:22:27.429673 <6>[ 3.654508] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10730 12:22:27.439970 <6>[ 3.663976] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10731 12:22:27.446183 <6>[ 3.673096] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10732 12:22:27.456476 <6>[ 3.682563] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10733 12:22:27.466110 <6>[ 3.691682] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10734 12:22:27.476261 <6>[ 3.700979] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10735 12:22:27.486283 <6>[ 3.711139] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10736 12:22:27.497127 <6>[ 3.723460] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10737 12:22:27.526964 <6>[ 3.753365] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10738 12:22:27.554846 <6>[ 3.784589] hub 2-1:1.0: USB hub found
10739 12:22:27.558301 <6>[ 3.789077] hub 2-1:1.0: 3 ports detected
10740 12:22:27.678399 <6>[ 3.905077] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10741 12:22:27.833472 <6>[ 4.062791] hub 1-1:1.0: USB hub found
10742 12:22:27.836108 <6>[ 4.067287] hub 1-1:1.0: 4 ports detected
10743 12:22:27.911203 <6>[ 4.137385] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10744 12:22:28.158626 <6>[ 4.385124] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10745 12:22:28.290580 <6>[ 4.520348] hub 1-1.4:1.0: USB hub found
10746 12:22:28.294020 <6>[ 4.524959] hub 1-1.4:1.0: 2 ports detected
10747 12:22:28.590579 <6>[ 4.817097] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10748 12:22:28.782531 <6>[ 5.009095] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10749 12:22:39.778967 <6>[ 16.014098] ALSA device list:
10750 12:22:39.785190 <6>[ 16.017389] No soundcards found.
10751 12:22:39.793642 <6>[ 16.025346] Freeing unused kernel memory: 8384K
10752 12:22:39.796778 <6>[ 16.030447] Run /init as init process
10753 12:22:39.846323 <6>[ 16.078059] NET: Registered PF_INET6 protocol family
10754 12:22:39.853275 <6>[ 16.084389] Segment Routing with IPv6
10755 12:22:39.856021 <6>[ 16.088346] In-situ OAM (IOAM) with IPv6
10756 12:22:39.891604 <30>[ 16.103425] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10757 12:22:39.895090 <30>[ 16.127582] systemd[1]: Detected architecture arm64.
10758 12:22:39.898231
10759 12:22:39.901404 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10760 12:22:39.901525
10761 12:22:39.917410 <30>[ 16.149217] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10762 12:22:40.051680 <30>[ 16.280175] systemd[1]: Queued start job for default target Graphical Interface.
10763 12:22:40.077908 <30>[ 16.309817] systemd[1]: Created slice system-getty.slice.
10764 12:22:40.084715 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10765 12:22:40.101406 <30>[ 16.333441] systemd[1]: Created slice system-modprobe.slice.
10766 12:22:40.108337 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10767 12:22:40.125808 <30>[ 16.357602] systemd[1]: Created slice system-serial\x2dgetty.slice.
10768 12:22:40.135574 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10769 12:22:40.151000 <30>[ 16.382657] systemd[1]: Created slice User and Session Slice.
10770 12:22:40.157579 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10771 12:22:40.176810 <30>[ 16.405106] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10772 12:22:40.183662 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10773 12:22:40.200272 <30>[ 16.429043] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10774 12:22:40.207208 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10775 12:22:40.228072 <30>[ 16.453109] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10776 12:22:40.234696 <30>[ 16.465213] systemd[1]: Reached target Local Encrypted Volumes.
10777 12:22:40.241073 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10778 12:22:40.258174 <30>[ 16.489525] systemd[1]: Reached target Paths.
10779 12:22:40.261233 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10780 12:22:40.277260 <30>[ 16.509084] systemd[1]: Reached target Remote File Systems.
10781 12:22:40.284120 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10782 12:22:40.301811 <30>[ 16.533448] systemd[1]: Reached target Slices.
10783 12:22:40.308350 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10784 12:22:40.321332 <30>[ 16.553120] systemd[1]: Reached target Swap.
10785 12:22:40.324393 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10786 12:22:40.344931 <30>[ 16.573563] systemd[1]: Listening on initctl Compatibility Named Pipe.
10787 12:22:40.351723 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10788 12:22:40.358232 <30>[ 16.588682] systemd[1]: Listening on Journal Audit Socket.
10789 12:22:40.364813 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10790 12:22:40.377404 <30>[ 16.609532] systemd[1]: Listening on Journal Socket (/dev/log).
10791 12:22:40.384591 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10792 12:22:40.402519 <30>[ 16.634333] systemd[1]: Listening on Journal Socket.
10793 12:22:40.409381 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10794 12:22:40.425063 <30>[ 16.653781] systemd[1]: Listening on Network Service Netlink Socket.
10795 12:22:40.431936 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10796 12:22:40.446672 <30>[ 16.678300] systemd[1]: Listening on udev Control Socket.
10797 12:22:40.452970 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10798 12:22:40.470630 <30>[ 16.702161] systemd[1]: Listening on udev Kernel Socket.
10799 12:22:40.477014 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10800 12:22:40.533502 <30>[ 16.765329] systemd[1]: Mounting Huge Pages File System...
10801 12:22:40.540503 Mounting [0;1;39mHuge Pages File System[0m...
10802 12:22:40.556806 <30>[ 16.788494] systemd[1]: Mounting POSIX Message Queue File System...
10803 12:22:40.563680 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10804 12:22:40.585082 <30>[ 16.816965] systemd[1]: Mounting Kernel Debug File System...
10805 12:22:40.591648 Mounting [0;1;39mKernel Debug File System[0m...
10806 12:22:40.608498 <30>[ 16.837226] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10807 12:22:40.652786 <30>[ 16.881363] systemd[1]: Starting Create list of static device nodes for the current kernel...
10808 12:22:40.659388 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10809 12:22:40.681781 <30>[ 16.913584] systemd[1]: Starting Load Kernel Module configfs...
10810 12:22:40.688201 Starting [0;1;39mLoad Kernel Module configfs[0m...
10811 12:22:40.705395 <30>[ 16.937019] systemd[1]: Starting Load Kernel Module drm...
10812 12:22:40.711700 Starting [0;1;39mLoad Kernel Module drm[0m...
10813 12:22:40.729041 <30>[ 16.957224] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10814 12:22:40.773663 <30>[ 17.005554] systemd[1]: Starting Journal Service...
10815 12:22:40.777009 Starting [0;1;39mJournal Service[0m...
10816 12:22:40.796594 <30>[ 17.028090] systemd[1]: Starting Load Kernel Modules...
10817 12:22:40.802725 Starting [0;1;39mLoad Kernel Modules[0m...
10818 12:22:40.823305 <30>[ 17.051541] systemd[1]: Starting Remount Root and Kernel File Systems...
10819 12:22:40.829419 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10820 12:22:40.844805 <30>[ 17.076032] systemd[1]: Starting Coldplug All udev Devices...
10821 12:22:40.850692 Starting [0;1;39mColdplug All udev Devices[0m...
10822 12:22:40.868424 <30>[ 17.099925] systemd[1]: Started Journal Service.
10823 12:22:40.874740 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10824 12:22:40.891607 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10825 12:22:40.909957 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10826 12:22:40.925868 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10827 12:22:40.946468 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10828 12:22:40.963322 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10829 12:22:40.979315 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10830 12:22:40.994530 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10831 12:22:41.015118 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10832 12:22:41.029448 See 'systemctl status systemd-remount-fs.service' for details.
10833 12:22:41.081914 Mounting [0;1;39mKernel Configuration File System[0m...
10834 12:22:41.101893 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10835 12:22:41.115954 <46>[ 17.344302] systemd-journald[176]: Received client request to flush runtime journal.
10836 12:22:41.143289 Starting [0;1;39mLoad/Save Random Seed[0m...
10837 12:22:41.160211 Starting [0;1;39mApply Kernel Variables[0m...
10838 12:22:41.178226 Starting [0;1;39mCreate System Users[0m...
10839 12:22:41.198592 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10840 12:22:41.218165 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10841 12:22:41.242710 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10842 12:22:41.255100 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10843 12:22:41.270923 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10844 12:22:41.286998 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10845 12:22:41.322365 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10846 12:22:41.342372 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10847 12:22:41.357777 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10848 12:22:41.377268 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10849 12:22:41.438111 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10850 12:22:41.466167 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10851 12:22:41.489936 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10852 12:22:41.510207 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10853 12:22:41.577679 Starting [0;1;39mNetwork Service[0m...
10854 12:22:41.607114 Starting [0;1;39mNetwork Time Synchronization[0m...
10855 12:22:41.628313 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10856 12:22:41.669550 [[0;32m OK [0m] Started [0;<6>[ 17.897124] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10857 12:22:41.669701 1;39mNetwork Service[0m.
10858 12:22:41.685792 [[0;32m OK [<6>[ 17.918273] remoteproc remoteproc0: scp is available
10859 12:22:41.692230 0m] Started [0;<6>[ 17.924460] remoteproc remoteproc0: powering up scp
10860 12:22:41.702335 1;39mNetwork Tim<6>[ 17.930940] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10861 12:22:41.712215 <6>[ 17.933534] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10862 12:22:41.718585 e Synchronizatio<6>[ 17.940676] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10863 12:22:41.725499 <6>[ 17.948269] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10864 12:22:41.728555 n[0m.
10865 12:22:41.735649 <6>[ 17.963976] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10866 12:22:41.754455 <3>[ 17.982973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 12:22:41.761266 <3>[ 17.991373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 12:22:41.770867 <3>[ 17.991381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 12:22:41.777590 <3>[ 18.002883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 12:22:41.787693 [[0;32m OK [<3>[ 18.016101] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 12:22:41.797220 0m] Found device<3>[ 18.025715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 12:22:41.804012 [0;1;39m/dev/t<6>[ 18.026270] usbcore: registered new interface driver r8152
10873 12:22:41.813915 <3>[ 18.035029] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 12:22:41.814075 tyS0[0m.
10875 12:22:41.824218 <3>[ 18.035034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 12:22:41.830177 <3>[ 18.035091] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 12:22:41.837246 <6>[ 18.045846] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10878 12:22:41.846940 <4>[ 18.045911] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10879 12:22:41.853419 <4>[ 18.046036] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10880 12:22:41.857342 <6>[ 18.054186] mc: Linux media interface: v0.10
10881 12:22:41.866836 <3>[ 18.071300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 12:22:41.873656 <6>[ 18.080778] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10883 12:22:41.879844 <6>[ 18.080778] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10884 12:22:41.890759 <3>[ 18.082522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 12:22:41.894048 <6>[ 18.089822] remoteproc remoteproc0: remote processor scp is now up
10886 12:22:41.903888 <3>[ 18.094214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 12:22:41.910700 <3>[ 18.094426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 12:22:41.917753 <6>[ 18.095072] videodev: Linux video capture interface: v2.00
10889 12:22:41.925060 <6>[ 18.098436] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10890 12:22:41.931730 <6>[ 18.098446] pci_bus 0000:00: root bus resource [bus 00-ff]
10891 12:22:41.938416 <6>[ 18.098451] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10892 12:22:41.948467 <6>[ 18.098455] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10893 12:22:41.955568 <6>[ 18.098503] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10894 12:22:41.962539 <6>[ 18.098539] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10895 12:22:41.965668 <6>[ 18.098609] pci 0000:00:00.0: supports D1 D2
10896 12:22:41.972295 <6>[ 18.098611] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10897 12:22:41.982290 <6>[ 18.099763] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10898 12:22:41.988902 <6>[ 18.099894] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10899 12:22:41.995238 <6>[ 18.099920] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10900 12:22:42.001846 <6>[ 18.099938] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10901 12:22:42.009200 <6>[ 18.099953] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10902 12:22:42.016302 <6>[ 18.100064] pci 0000:01:00.0: supports D1 D2
10903 12:22:42.023278 <6>[ 18.100067] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10904 12:22:42.030002 <6>[ 18.109458] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10905 12:22:42.037046 <3>[ 18.111010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 12:22:42.046998 <4>[ 18.112257] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10907 12:22:42.050635 <4>[ 18.112257] Fallback method does not support PEC.
10908 12:22:42.057062 <6>[ 18.112981] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10909 12:22:42.066857 <6>[ 18.113030] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10910 12:22:42.074122 <6>[ 18.113036] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10911 12:22:42.080910 <6>[ 18.113047] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10912 12:22:42.090595 <6>[ 18.113061] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10913 12:22:42.098314 <6>[ 18.113074] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10914 12:22:42.101585 <6>[ 18.113086] pci 0000:00:00.0: PCI bridge to [bus 01]
10915 12:22:42.111577 <6>[ 18.113093] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10916 12:22:42.118476 <6>[ 18.113417] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10917 12:22:42.121498 <6>[ 18.114777] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10918 12:22:42.128527 <6>[ 18.120125] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10919 12:22:42.138575 <3>[ 18.126258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 12:22:42.145245 <3>[ 18.126270] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 12:22:42.155256 <3>[ 18.128871] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:22:42.161830 <4>[ 18.151292] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10923 12:22:42.172224 <3>[ 18.154601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 12:22:42.179085 <3>[ 18.158891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 12:22:42.186079 <4>[ 18.162254] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10926 12:22:42.196119 <3>[ 18.163908] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:22:42.203167 <3>[ 18.164699] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10928 12:22:42.213702 <6>[ 18.168126] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10929 12:22:42.223736 <6>[ 18.177745] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10930 12:22:42.230799 <6>[ 18.185862] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10931 12:22:42.240803 <6>[ 18.191759] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10932 12:22:42.251046 <6>[ 18.200647] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10933 12:22:42.257240 <3>[ 18.204598] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 12:22:42.260562 <6>[ 18.233595] r8152 2-1.3:1.0 eth0: v1.12.13
10935 12:22:42.270477 <5>[ 18.234614] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10936 12:22:42.273714 <6>[ 18.247790] Bluetooth: Core ver 2.22
10937 12:22:42.280715 <6>[ 18.250369] usbcore: registered new interface driver cdc_ether
10938 12:22:42.287348 <6>[ 18.252162] usbcore: registered new interface driver r8153_ecm
10939 12:22:42.294129 <6>[ 18.253017] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10940 12:22:42.307055 <6>[ 18.254218] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10941 12:22:42.310608 <6>[ 18.254395] usbcore: registered new interface driver uvcvideo
10942 12:22:42.316648 <5>[ 18.257211] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10943 12:22:42.326608 <4>[ 18.257326] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10944 12:22:42.333517 <6>[ 18.257335] cfg80211: failed to load regulatory.db
10945 12:22:42.336940 <6>[ 18.258643] NET: Registered PF_BLUETOOTH protocol family
10946 12:22:42.346459 <3>[ 18.261558] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 12:22:42.356410 <3>[ 18.263773] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 12:22:42.363014 <6>[ 18.280405] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10949 12:22:42.369613 <3>[ 18.282161] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 12:22:42.376275 <6>[ 18.287623] Bluetooth: HCI device and connection manager initialized
10951 12:22:42.382980 <6>[ 18.303244] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10952 12:22:42.389310 <6>[ 18.310418] Bluetooth: HCI socket layer initialized
10953 12:22:42.396179 <3>[ 18.311863] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 12:22:42.406199 <3>[ 18.334633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 12:22:42.412480 <6>[ 18.339605] Bluetooth: L2CAP socket layer initialized
10956 12:22:42.415825 <6>[ 18.339634] Bluetooth: SCO socket layer initialized
10957 12:22:42.422342 <6>[ 18.361378] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10958 12:22:42.432484 <3>[ 18.369570] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 12:22:42.439020 <6>[ 18.374177] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10960 12:22:42.445513 <6>[ 18.416691] usbcore: registered new interface driver btusb
10961 12:22:42.455315 <4>[ 18.417574] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10962 12:22:42.462077 <3>[ 18.417590] Bluetooth: hci0: Failed to load firmware file (-2)
10963 12:22:42.465237 <3>[ 18.417597] Bluetooth: hci0: Failed to set up firmware (-2)
10964 12:22:42.478665 <4>[ 18.417604] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10965 12:22:42.482042 <6>[ 18.440971] mt7921e 0000:01:00.0: ASIC revision: 79610010
10966 12:22:42.492081 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10967 12:22:42.590009 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbac<4>[ 18.813598] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10968 12:22:42.590167 klight.slice[0m.
10969 12:22:42.596914 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10970 12:22:42.613248 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10971 12:22:42.629832 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10972 12:22:42.648229 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10973 12:22:42.705617 <4>[ 18.931227] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 12:22:42.716465 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10975 12:22:42.741202 Starting [0;1;39mNetwork Name Resolution[0m...
10976 12:22:42.765989 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10977 12:22:42.786621 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10978 12:22:42.804925 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10979 12:22:42.829601 [[0;32m OK [0m] Started [0;<4>[ 19.053398] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10980 12:22:42.832539 1;39mDaily Cleanup of Temporary Directories[0m.
10981 12:22:42.852529 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10982 12:22:42.869564 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10983 12:22:42.885013 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10984 12:22:42.905707 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10985 12:22:42.953697 <4>[ 19.179043] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10986 12:22:42.965471 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10987 12:22:43.022173 Starting [0;1;39mUser Login Management[0m...
10988 12:22:43.041582 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10989 12:22:43.077165 [[0;32m OK [0m] Started [0;<4>[ 19.301966] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10990 12:22:43.081071 1;39mNetwork Name Resolution[0m.
10991 12:22:43.102685 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10992 12:22:43.121517 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10993 12:22:43.144276 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10994 12:22:43.189073 Starting [0;1;39mPermit User Sessions[0m...
10995 12:22:43.203569 <4>[ 19.429119] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 12:22:43.217588 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10997 12:22:43.224766 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10998 12:22:43.259442 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10999 12:22:43.279425 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11000 12:22:43.297881 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11001 12:22:43.321241 [[0;32m OK [<4>[ 19.547595] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11002 12:22:43.327843 0m] Reached target [0;1;39mMulti-User System[0m.
11003 12:22:43.342889 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11004 12:22:43.386986 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11005 12:22:43.428973 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11006 12:22:43.442539 <4>[ 19.668097] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11007 12:22:43.492311
11008 12:22:43.492464
11009 12:22:43.495742 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11010 12:22:43.495830
11011 12:22:43.498753 debian-bullseye-arm64 login: root (automatic login)
11012 12:22:43.498837
11013 12:22:43.498902
11014 12:22:43.528241 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Wed Aug 16 12:04:53 UTC 2023 aarch64
11015 12:22:43.528391
11016 12:22:43.535069 The programs included with the Debian GNU/Linux system are free software;
11017 12:22:43.541973 the exact distribution terms for each program are described in the
11018 12:22:43.544791 individual files in /usr/share/doc/*/copyright.
11019 12:22:43.544889
11020 12:22:43.561493 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the exte<4>[ 19.787373] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11021 12:22:43.561634 nt
11022 12:22:43.564954 permitted by applicable law.
11023 12:22:43.565306 Matched prompt #10: / #
11025 12:22:43.565534 Setting prompt string to ['/ #']
11026 12:22:43.565625 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11028 12:22:43.565814 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11029 12:22:43.565897 start: 2.2.6 expect-shell-connection (timeout 00:02:49) [common]
11030 12:22:43.565966 Setting prompt string to ['/ #']
11031 12:22:43.566025 Forcing a shell prompt, looking for ['/ #']
11033 12:22:43.616262 / #
11034 12:22:43.616447 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11035 12:22:43.616532 Waiting using forced prompt support (timeout 00:02:30)
11036 12:22:43.621744
11037 12:22:43.622046 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11038 12:22:43.622147 start: 2.2.7 export-device-env (timeout 00:02:49) [common]
11039 12:22:43.622243 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11040 12:22:43.622328 end: 2.2 depthcharge-retry (duration 00:02:11) [common]
11041 12:22:43.622410 end: 2 depthcharge-action (duration 00:02:11) [common]
11042 12:22:43.622496 start: 3 lava-test-retry (timeout 00:05:00) [common]
11043 12:22:43.622576 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11044 12:22:43.622650 Using namespace: common
11046 12:22:43.723027 / # #
11047 12:22:43.723210 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11048 12:22:43.723338 <6>[ 19.860586] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11049 12:22:43.723416 <6>[ 19.868582] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11050 12:22:43.723478 <4>[ 19.907777] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11051 12:22:43.728529 #
11052 12:22:43.728808 Using /lava-11299287
11054 12:22:43.829192 / # export SHELL=/bin/sh
11055 12:22:43.829437 export SHELL=/bin/sh<3>[ 20.025076] mt7921e 0000:01:00.0: hardware init failed
11056 12:22:43.834570
11058 12:22:43.935177 / # . /lava-11299287/environment
11059 12:22:43.940526 . /lava-11299287/environment
11061 12:22:44.041142 / # /lava-11299287/bin/lava-test-runner /lava-11299287/0
11062 12:22:44.041345 Test shell timeout: 10s (minimum of the action and connection timeout)
11063 12:22:44.046364 /lava-11299287/bin/lava-test-runner /lava-11299287/0
11064 12:22:44.073925 + export TESTRUN<8>[ 20.304361] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11299287_1.5.2.3.1>
11065 12:22:44.074137 _ID=0_cros-ec
11066 12:22:44.074401 Received signal: <STARTRUN> 0_cros-ec 11299287_1.5.2.3.1
11067 12:22:44.074492 Starting test lava.0_cros-ec (11299287_1.5.2.3.1)
11068 12:22:44.074589 Skipping test definition patterns.
11069 12:22:44.077235 + cd /lava-11299287/0/tests/0_cros-ec
11070 12:22:44.081006 + cat uuid
11071 12:22:44.081095 + UUID=11299287_1.5.2.3.1
11072 12:22:44.081161 + set +x
11073 12:22:44.087186 + python3 -m cros.runners.lava_runner -v
11074 12:22:44.450980 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11075 12:22:44.457211 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11076 12:22:44.457332
11077 12:22:44.463914 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11079 12:22:44.467111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11080 12:22:44.473867 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11081 12:22:44.480475 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11082 12:22:44.480603
11083 12:22:44.487875 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
11084 12:22:44.488010 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
11085 12:22:44.493889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 20.724681] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11299287_1.5.2.3.1>
11086 12:22:44.494177 Received signal: <ENDRUN> 0_cros-ec 11299287_1.5.2.3.1
11087 12:22:44.494265 Ending use of test pattern.
11088 12:22:44.494329 Ending test lava.0_cros-ec (11299287_1.5.2.3.1), duration 0.42
11090 12:22:44.497093 valid RESULT=skip>
11091 12:22:44.500349 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11092 12:22:44.506993 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11093 12:22:44.507148
11094 12:22:44.513564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11095 12:22:44.513856 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11097 12:22:44.520383 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11098 12:22:44.527452 Checks the standard ABI for the main Embedded Controller. ... ok
11099 12:22:44.527571
11100 12:22:44.529899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11101 12:22:44.530161 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11103 12:22:44.537046 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11104 12:22:44.543240 Checks the main Embedded controller character device. ... ok
11105 12:22:44.543406
11106 12:22:44.547041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11107 12:22:44.547332 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11109 12:22:44.553230 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11110 12:22:44.559668 Checks basic comunication with the main Embedded controller. ... ok
11111 12:22:44.559781
11112 12:22:44.566713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11113 12:22:44.567000 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11115 12:22:44.569610 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11116 12:22:44.579565 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11117 12:22:44.579692
11118 12:22:44.582791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11119 12:22:44.583057 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11121 12:22:44.589520 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11122 12:22:44.595815 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11123 12:22:44.595931
11124 12:22:44.602765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11125 12:22:44.603053 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11127 12:22:44.609139 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11128 12:22:44.615391 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11129 12:22:44.615519
11130 12:22:44.622647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11131 12:22:44.622941 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11133 12:22:44.625506 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11134 12:22:44.635350 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11135 12:22:44.635533
11136 12:22:44.638725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11137 12:22:44.639002 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11139 12:22:44.645365 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11140 12:22:44.655251 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11141 12:22:44.655414
11142 12:22:44.658491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11143 12:22:44.658754 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11145 12:22:44.665389 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11146 12:22:44.671794 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11147 12:22:44.671908
11148 12:22:44.678314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11149 12:22:44.678603 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11151 12:22:44.684997 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11152 12:22:44.691690 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11153 12:22:44.691807
11154 12:22:44.698381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11155 12:22:44.698668 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11157 12:22:44.704925 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11158 12:22:44.711599 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11159 12:22:44.711775
11160 12:22:44.717904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11161 12:22:44.718190 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11163 12:22:44.724595 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11164 12:22:44.731082 Check the cros battery ABI. ... skipped 'No BAT found'
11165 12:22:44.731195
11166 12:22:44.737681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11167 12:22:44.737969 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11169 12:22:44.744454 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11170 12:22:44.751329 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11171 12:22:44.751485
11172 12:22:44.757436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11173 12:22:44.757722 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11175 12:22:44.761117 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11176 12:22:44.770715 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11177 12:22:44.770846
11178 12:22:44.774002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11179 12:22:44.774266 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11181 12:22:44.780557 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11182 12:22:44.787223 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11183 12:22:44.787364
11184 12:22:44.794016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11185 12:22:44.794137
11186 12:22:44.794402 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11188 12:22:44.800459 ----------------------------------------------------------------------
11189 12:22:44.804135 Ran 18 tests in 0.007s
11190 12:22:44.804236
11191 12:22:44.804300 OK (skipped=15)
11192 12:22:44.807224 + set +x
11193 12:22:44.807324 <LAVA_TEST_RUNNER EXIT>
11194 12:22:44.807590 ok: lava_test_shell seems to have completed
11195 12:22:44.807759 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11196 12:22:44.807857 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11197 12:22:44.807940 end: 3 lava-test-retry (duration 00:00:01) [common]
11198 12:22:44.808025 start: 4 finalize (timeout 00:07:26) [common]
11199 12:22:44.808110 start: 4.1 power-off (timeout 00:00:30) [common]
11200 12:22:44.808260 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11201 12:22:44.885354 >> Command sent successfully.
11202 12:22:44.887842 Returned 0 in 0 seconds
11203 12:22:44.988274 end: 4.1 power-off (duration 00:00:00) [common]
11205 12:22:44.988618 start: 4.2 read-feedback (timeout 00:07:26) [common]
11206 12:22:44.988896 Listened to connection for namespace 'common' for up to 1s
11207 12:22:45.989845 Finalising connection for namespace 'common'
11208 12:22:45.990015 Disconnecting from shell: Finalise
11209 12:22:45.990097 / #
11210 12:22:46.090445 end: 4.2 read-feedback (duration 00:00:01) [common]
11211 12:22:46.090628 end: 4 finalize (duration 00:00:01) [common]
11212 12:22:46.090744 Cleaning after the job
11213 12:22:46.090847 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/ramdisk
11214 12:22:46.097438 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/kernel
11215 12:22:46.105980 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/dtb
11216 12:22:46.106213 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299287/tftp-deploy-zw2vi42m/modules
11217 12:22:46.113340 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11299287
11218 12:22:46.231754 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11299287
11219 12:22:46.231935 Job finished correctly