Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 23
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 133
- Errors: 0
1 12:20:41.120444 lava-dispatcher, installed at version: 2023.06
2 12:20:41.120683 start: 0 validate
3 12:20:41.120835 Start time: 2023-08-16 12:20:41.120827+00:00 (UTC)
4 12:20:41.121003 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:20:41.121155 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:20:41.383999 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:20:41.384183 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:21:11.906279 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:21:11.906526 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:21:12.156166 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:21:12.156812 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:21:18.405318 validate duration: 37.28
14 12:21:18.405661 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:21:18.405793 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:21:18.405918 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:21:18.406073 Not decompressing ramdisk as can be used compressed.
18 12:21:18.406192 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 12:21:18.406286 saving as /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/ramdisk/rootfs.cpio.gz
20 12:21:18.406383 total size: 84918747 (80 MB)
21 12:21:18.665865 progress 0 % (0 MB)
22 12:21:18.691103 progress 5 % (4 MB)
23 12:21:18.715683 progress 10 % (8 MB)
24 12:21:18.740142 progress 15 % (12 MB)
25 12:21:18.764171 progress 20 % (16 MB)
26 12:21:18.793517 progress 25 % (20 MB)
27 12:21:18.822027 progress 30 % (24 MB)
28 12:21:18.846633 progress 35 % (28 MB)
29 12:21:18.871076 progress 40 % (32 MB)
30 12:21:18.895913 progress 45 % (36 MB)
31 12:21:18.925948 progress 50 % (40 MB)
32 12:21:18.956440 progress 55 % (44 MB)
33 12:21:18.981264 progress 60 % (48 MB)
34 12:21:19.006418 progress 65 % (52 MB)
35 12:21:19.031285 progress 70 % (56 MB)
36 12:21:19.056098 progress 75 % (60 MB)
37 12:21:19.087822 progress 80 % (64 MB)
38 12:21:19.115370 progress 85 % (68 MB)
39 12:21:19.140123 progress 90 % (72 MB)
40 12:21:19.164114 progress 95 % (76 MB)
41 12:21:19.188754 progress 100 % (80 MB)
42 12:21:19.189013 80 MB downloaded in 0.78 s (103.48 MB/s)
43 12:21:19.189208 end: 1.1.1 http-download (duration 00:00:01) [common]
45 12:21:19.189506 end: 1.1 download-retry (duration 00:00:01) [common]
46 12:21:19.189610 start: 1.2 download-retry (timeout 00:09:59) [common]
47 12:21:19.189747 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 12:21:19.189925 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:21:19.190006 saving as /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/kernel/Image
50 12:21:19.190101 total size: 49220096 (46 MB)
51 12:21:19.190212 No compression specified
52 12:21:19.191626 progress 0 % (0 MB)
53 12:21:19.206295 progress 5 % (2 MB)
54 12:21:19.220936 progress 10 % (4 MB)
55 12:21:19.238403 progress 15 % (7 MB)
56 12:21:19.257134 progress 20 % (9 MB)
57 12:21:19.275479 progress 25 % (11 MB)
58 12:21:19.289218 progress 30 % (14 MB)
59 12:21:19.303408 progress 35 % (16 MB)
60 12:21:19.317782 progress 40 % (18 MB)
61 12:21:19.332702 progress 45 % (21 MB)
62 12:21:19.347831 progress 50 % (23 MB)
63 12:21:19.363026 progress 55 % (25 MB)
64 12:21:19.377561 progress 60 % (28 MB)
65 12:21:19.393478 progress 65 % (30 MB)
66 12:21:19.413056 progress 70 % (32 MB)
67 12:21:19.432425 progress 75 % (35 MB)
68 12:21:19.447487 progress 80 % (37 MB)
69 12:21:19.461584 progress 85 % (39 MB)
70 12:21:19.475724 progress 90 % (42 MB)
71 12:21:19.489176 progress 95 % (44 MB)
72 12:21:19.502574 progress 100 % (46 MB)
73 12:21:19.502763 46 MB downloaded in 0.31 s (150.13 MB/s)
74 12:21:19.502984 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:21:19.503383 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:21:19.503515 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:21:19.503679 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:21:19.503844 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:21:19.503953 saving as /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/dtb/mt8192-asurada-spherion-r0.dtb
81 12:21:19.504058 total size: 47278 (0 MB)
82 12:21:19.504153 No compression specified
83 12:21:19.505379 progress 69 % (0 MB)
84 12:21:19.505677 progress 100 % (0 MB)
85 12:21:19.505884 0 MB downloaded in 0.00 s (24.72 MB/s)
86 12:21:19.506063 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:21:19.506451 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:21:19.506576 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:21:19.506696 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:21:19.506845 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:21:19.506956 saving as /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/modules/modules.tar
93 12:21:19.507052 total size: 8615968 (8 MB)
94 12:21:19.507138 Using unxz to decompress xz
95 12:21:19.511473 progress 0 % (0 MB)
96 12:21:19.534429 progress 5 % (0 MB)
97 12:21:19.558863 progress 10 % (0 MB)
98 12:21:19.588083 progress 15 % (1 MB)
99 12:21:19.615237 progress 20 % (1 MB)
100 12:21:19.643179 progress 25 % (2 MB)
101 12:21:19.670543 progress 30 % (2 MB)
102 12:21:19.698256 progress 35 % (2 MB)
103 12:21:19.726531 progress 40 % (3 MB)
104 12:21:19.752388 progress 45 % (3 MB)
105 12:21:19.781133 progress 50 % (4 MB)
106 12:21:19.807745 progress 55 % (4 MB)
107 12:21:19.833186 progress 60 % (4 MB)
108 12:21:19.863907 progress 65 % (5 MB)
109 12:21:19.900612 progress 70 % (5 MB)
110 12:21:19.925634 progress 75 % (6 MB)
111 12:21:19.953890 progress 80 % (6 MB)
112 12:21:19.985365 progress 85 % (7 MB)
113 12:21:20.014607 progress 90 % (7 MB)
114 12:21:20.042488 progress 95 % (7 MB)
115 12:21:20.069185 progress 100 % (8 MB)
116 12:21:20.076151 8 MB downloaded in 0.57 s (14.44 MB/s)
117 12:21:20.076552 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:21:20.076992 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:21:20.077123 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 12:21:20.077270 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 12:21:20.077388 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:21:20.077527 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 12:21:20.077796 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote
125 12:21:20.077989 makedir: /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin
126 12:21:20.078140 makedir: /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/tests
127 12:21:20.078302 makedir: /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/results
128 12:21:20.078472 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-add-keys
129 12:21:20.078677 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-add-sources
130 12:21:20.078898 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-background-process-start
131 12:21:20.079122 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-background-process-stop
132 12:21:20.079330 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-common-functions
133 12:21:20.079500 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-echo-ipv4
134 12:21:20.079694 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-install-packages
135 12:21:20.079867 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-installed-packages
136 12:21:20.080047 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-os-build
137 12:21:20.080225 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-probe-channel
138 12:21:20.080397 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-probe-ip
139 12:21:20.080580 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-target-ip
140 12:21:20.080798 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-target-mac
141 12:21:20.081011 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-target-storage
142 12:21:20.081202 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-test-case
143 12:21:20.081380 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-test-event
144 12:21:20.081569 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-test-feedback
145 12:21:20.081760 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-test-raise
146 12:21:20.082035 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-test-reference
147 12:21:20.082254 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-test-runner
148 12:21:20.082424 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-test-set
149 12:21:20.082597 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-test-shell
150 12:21:20.082775 Updating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-install-packages (oe)
151 12:21:20.192254 Updating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/bin/lava-installed-packages (oe)
152 12:21:20.192540 Creating /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/environment
153 12:21:20.192733 LAVA metadata
154 12:21:20.192873 - LAVA_JOB_ID=11299254
155 12:21:20.192999 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:21:20.193196 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 12:21:20.193322 skipped lava-vland-overlay
158 12:21:20.193463 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:21:20.193611 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 12:21:20.193738 skipped lava-multinode-overlay
161 12:21:20.193882 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:21:20.194034 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 12:21:20.194178 Loading test definitions
164 12:21:20.194344 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 12:21:20.194486 Using /lava-11299254 at stage 0
166 12:21:20.194667 Fetching tests from https://github.com/kernelci/kernelci-core
167 12:21:20.194817 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/0/tests/0_sleep'
168 12:21:21.019719 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/0/tests/0_sleep
169 12:21:21.021259 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 12:21:21.021715 uuid=11299254_1.5.2.3.1 testdef=None
171 12:21:21.021914 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 12:21:21.022336 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
174 12:21:21.023159 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 12:21:21.023407 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
177 12:21:21.024494 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 12:21:21.024888 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
180 12:21:21.025723 runner path: /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/0/tests/0_sleep test_uuid 11299254_1.5.2.3.1
181 12:21:21.025815 sleep_params='mem freeze'
182 12:21:21.025968 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 12:21:21.026187 Creating lava-test-runner.conf files
185 12:21:21.026254 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11299254/lava-overlay-n5lqvote/lava-11299254/0 for stage 0
186 12:21:21.026352 - 0_sleep
187 12:21:21.026470 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 12:21:21.026564 start: 1.5.2.4 compress-overlay (timeout 00:09:57) [common]
189 12:21:21.164466 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 12:21:21.164620 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
191 12:21:21.164719 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 12:21:21.164822 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 12:21:21.164913 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
194 12:21:23.844427 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 12:21:23.844972 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 12:21:23.845168 extracting modules file /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11299254/extract-overlay-ramdisk-skvcjrsc/ramdisk
197 12:21:24.178690 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 12:21:24.178911 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
199 12:21:24.179035 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299254/compress-overlay-mmgsn_4r/overlay-1.5.2.4.tar.gz to ramdisk
200 12:21:24.179140 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299254/compress-overlay-mmgsn_4r/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11299254/extract-overlay-ramdisk-skvcjrsc/ramdisk
201 12:21:24.303430 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 12:21:24.303658 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
203 12:21:24.303782 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 12:21:24.303880 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
205 12:21:24.303986 Building ramdisk /var/lib/lava/dispatcher/tmp/11299254/extract-overlay-ramdisk-skvcjrsc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11299254/extract-overlay-ramdisk-skvcjrsc/ramdisk
206 12:21:25.937716 >> 563300 blocks
207 12:21:36.572551 rename /var/lib/lava/dispatcher/tmp/11299254/extract-overlay-ramdisk-skvcjrsc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/ramdisk/ramdisk.cpio.gz
208 12:21:36.573132 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 12:21:36.573322 start: 1.5.8 prepare-kernel (timeout 00:09:42) [common]
210 12:21:36.573473 start: 1.5.8.1 prepare-fit (timeout 00:09:42) [common]
211 12:21:36.573647 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/kernel/Image'
212 12:21:49.858209 Returned 0 in 13 seconds
213 12:21:49.958827 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/kernel/image.itb
214 12:21:51.269264 output: FIT description: Kernel Image image with one or more FDT blobs
215 12:21:51.269650 output: Created: Wed Aug 16 13:21:51 2023
216 12:21:51.269739 output: Image 0 (kernel-1)
217 12:21:51.269810 output: Description:
218 12:21:51.269879 output: Created: Wed Aug 16 13:21:51 2023
219 12:21:51.269957 output: Type: Kernel Image
220 12:21:51.270022 output: Compression: lzma compressed
221 12:21:51.270090 output: Data Size: 11040376 Bytes = 10781.62 KiB = 10.53 MiB
222 12:21:51.270158 output: Architecture: AArch64
223 12:21:51.270224 output: OS: Linux
224 12:21:51.270290 output: Load Address: 0x00000000
225 12:21:51.270354 output: Entry Point: 0x00000000
226 12:21:51.270434 output: Hash algo: crc32
227 12:21:51.270521 output: Hash value: 79630449
228 12:21:51.270610 output: Image 1 (fdt-1)
229 12:21:51.270703 output: Description: mt8192-asurada-spherion-r0
230 12:21:51.270790 output: Created: Wed Aug 16 13:21:51 2023
231 12:21:51.270881 output: Type: Flat Device Tree
232 12:21:51.270968 output: Compression: uncompressed
233 12:21:51.271062 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 12:21:51.271149 output: Architecture: AArch64
235 12:21:51.271235 output: Hash algo: crc32
236 12:21:51.271324 output: Hash value: cc4352de
237 12:21:51.271415 output: Image 2 (ramdisk-1)
238 12:21:51.271501 output: Description: unavailable
239 12:21:51.271598 output: Created: Wed Aug 16 13:21:51 2023
240 12:21:51.271693 output: Type: RAMDisk Image
241 12:21:51.271784 output: Compression: Unknown Compression
242 12:21:51.271870 output: Data Size: 98307568 Bytes = 96003.48 KiB = 93.75 MiB
243 12:21:51.271956 output: Architecture: AArch64
244 12:21:51.272050 output: OS: Linux
245 12:21:51.272137 output: Load Address: unavailable
246 12:21:51.272222 output: Entry Point: unavailable
247 12:21:51.272310 output: Hash algo: crc32
248 12:21:51.272402 output: Hash value: b87432ef
249 12:21:51.272487 output: Default Configuration: 'conf-1'
250 12:21:51.272575 output: Configuration 0 (conf-1)
251 12:21:51.272667 output: Description: mt8192-asurada-spherion-r0
252 12:21:51.272752 output: Kernel: kernel-1
253 12:21:51.272841 output: Init Ramdisk: ramdisk-1
254 12:21:51.272931 output: FDT: fdt-1
255 12:21:51.273017 output: Loadables: kernel-1
256 12:21:51.273106 output:
257 12:21:51.273352 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 12:21:51.273482 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 12:21:51.273631 end: 1.5 prepare-tftp-overlay (duration 00:00:31) [common]
260 12:21:51.273762 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
261 12:21:51.273880 No LXC device requested
262 12:21:51.274004 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 12:21:51.274132 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
264 12:21:51.274252 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 12:21:51.274349 Checking files for TFTP limit of 4294967296 bytes.
266 12:21:51.275026 end: 1 tftp-deploy (duration 00:00:33) [common]
267 12:21:51.275185 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 12:21:51.275317 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 12:21:51.275499 substitutions:
270 12:21:51.275610 - {DTB}: 11299254/tftp-deploy-u8xrdn7k/dtb/mt8192-asurada-spherion-r0.dtb
271 12:21:51.275718 - {INITRD}: 11299254/tftp-deploy-u8xrdn7k/ramdisk/ramdisk.cpio.gz
272 12:21:51.275828 - {KERNEL}: 11299254/tftp-deploy-u8xrdn7k/kernel/Image
273 12:21:51.275927 - {LAVA_MAC}: None
274 12:21:51.276025 - {PRESEED_CONFIG}: None
275 12:21:51.276119 - {PRESEED_LOCAL}: None
276 12:21:51.276220 - {RAMDISK}: 11299254/tftp-deploy-u8xrdn7k/ramdisk/ramdisk.cpio.gz
277 12:21:51.276299 - {ROOT_PART}: None
278 12:21:51.276373 - {ROOT}: None
279 12:21:51.276469 - {SERVER_IP}: 192.168.201.1
280 12:21:51.276562 - {TEE}: None
281 12:21:51.276657 Parsed boot commands:
282 12:21:51.276764 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 12:21:51.276995 Parsed boot commands: tftpboot 192.168.201.1 11299254/tftp-deploy-u8xrdn7k/kernel/image.itb 11299254/tftp-deploy-u8xrdn7k/kernel/cmdline
284 12:21:51.277131 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 12:21:51.277264 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 12:21:51.277401 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 12:21:51.277534 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 12:21:51.277649 Not connected, no need to disconnect.
289 12:21:51.277774 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 12:21:51.277895 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 12:21:51.278006 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 12:21:51.282319 Setting prompt string to ['lava-test: # ']
293 12:21:51.282716 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 12:21:51.282832 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 12:21:51.282943 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 12:21:51.283039 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 12:21:51.283383 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 12:21:56.419361 >> Command sent successfully.
299 12:21:56.421922 Returned 0 in 5 seconds
300 12:21:56.522320 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 12:21:56.522697 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 12:21:56.522817 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 12:21:56.522921 Setting prompt string to 'Starting depthcharge on Spherion...'
305 12:21:56.523002 Changing prompt to 'Starting depthcharge on Spherion...'
306 12:21:56.523073 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 12:21:56.523364 [Enter `^Ec?' for help]
308 12:21:56.699901
309 12:21:56.700044
310 12:21:56.700119 F0: 102B 0000
311 12:21:56.700185
312 12:21:56.700251 F3: 1001 0000 [0200]
313 12:21:56.702924
314 12:21:56.703046 F3: 1001 0000
315 12:21:56.703153
316 12:21:56.703248 F7: 102D 0000
317 12:21:56.703349
318 12:21:56.706491 F1: 0000 0000
319 12:21:56.706605
320 12:21:56.706713 V0: 0000 0000 [0001]
321 12:21:56.706817
322 12:21:56.709568 00: 0007 8000
323 12:21:56.709656
324 12:21:56.709723 01: 0000 0000
325 12:21:56.709787
326 12:21:56.712796 BP: 0C00 0209 [0000]
327 12:21:56.712887
328 12:21:56.712957 G0: 1182 0000
329 12:21:56.713020
330 12:21:56.716475 EC: 0000 0021 [4000]
331 12:21:56.716554
332 12:21:56.716623 S7: 0000 0000 [0000]
333 12:21:56.716685
334 12:21:56.720127 CC: 0000 0000 [0001]
335 12:21:56.720210
336 12:21:56.720281 T0: 0000 0040 [010F]
337 12:21:56.720348
338 12:21:56.722976 Jump to BL
339 12:21:56.723056
340 12:21:56.746549
341 12:21:56.746664
342 12:21:56.746735
343 12:21:56.754119 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 12:21:56.757821 ARM64: Exception handlers installed.
345 12:21:56.761392 ARM64: Testing exception
346 12:21:56.764598 ARM64: Done test exception
347 12:21:56.771187 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 12:21:56.781542 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 12:21:56.788260 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 12:21:56.798306 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 12:21:56.804511 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 12:21:56.811125 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 12:21:56.823436 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 12:21:56.830046 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 12:21:56.849782 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 12:21:56.852889 WDT: Last reset was cold boot
357 12:21:56.856694 SPI1(PAD0) initialized at 2873684 Hz
358 12:21:56.859626 SPI5(PAD0) initialized at 992727 Hz
359 12:21:56.863289 VBOOT: Loading verstage.
360 12:21:56.869475 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 12:21:56.873033 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 12:21:56.876490 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 12:21:56.879509 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 12:21:56.887316 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 12:21:56.893637 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 12:21:56.904631 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 12:21:56.904820
368 12:21:56.904955
369 12:21:56.915140 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 12:21:56.918734 ARM64: Exception handlers installed.
371 12:21:56.918854 ARM64: Testing exception
372 12:21:56.922354 ARM64: Done test exception
373 12:21:56.925562 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 12:21:56.932100 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 12:21:56.945447 Probing TPM: . done!
376 12:21:56.945549 TPM ready after 0 ms
377 12:21:56.952740 Connected to device vid:did:rid of 1ae0:0028:00
378 12:21:56.960033 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 12:21:57.021587 Initialized TPM device CR50 revision 0
380 12:21:57.030814 tlcl_send_startup: Startup return code is 0
381 12:21:57.030921 TPM: setup succeeded
382 12:21:57.042651 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 12:21:57.051332 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 12:21:57.065379 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 12:21:57.072216 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 12:21:57.075899 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 12:21:57.080172 in-header: 03 07 00 00 08 00 00 00
388 12:21:57.083817 in-data: aa e4 47 04 13 02 00 00
389 12:21:57.083954 Chrome EC: UHEPI supported
390 12:21:57.090744 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 12:21:57.093954 in-header: 03 95 00 00 08 00 00 00
392 12:21:57.098145 in-data: 18 20 20 08 00 00 00 00
393 12:21:57.098260 Phase 1
394 12:21:57.101799 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 12:21:57.109298 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 12:21:57.116455 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 12:21:57.116553 Recovery requested (1009000e)
398 12:21:57.127967 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 12:21:57.132515 tlcl_extend: response is 0
400 12:21:57.143893 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 12:21:57.147279 tlcl_extend: response is 0
402 12:21:57.154693 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 12:21:57.174073 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 12:21:57.180801 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 12:21:57.180888
406 12:21:57.180960
407 12:21:57.191003 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 12:21:57.194119 ARM64: Exception handlers installed.
409 12:21:57.197932 ARM64: Testing exception
410 12:21:57.198012 ARM64: Done test exception
411 12:21:57.220019 pmic_efuse_setting: Set efuses in 11 msecs
412 12:21:57.223036 pmwrap_interface_init: Select PMIF_VLD_RDY
413 12:21:57.230108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 12:21:57.233249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 12:21:57.240533 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 12:21:57.244022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 12:21:57.248105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 12:21:57.251496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 12:21:57.259078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 12:21:57.263114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 12:21:57.266628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 12:21:57.274328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 12:21:57.277929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 12:21:57.281206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 12:21:57.284947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 12:21:57.292369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 12:21:57.299387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 12:21:57.303129 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 12:21:57.310556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 12:21:57.314281 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 12:21:57.321615 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 12:21:57.325188 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 12:21:57.331956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 12:21:57.336230 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 12:21:57.343521 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 12:21:57.347169 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 12:21:57.354358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 12:21:57.357970 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 12:21:57.365261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 12:21:57.369027 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 12:21:57.372730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 12:21:57.380042 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 12:21:57.384066 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 12:21:57.387808 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 12:21:57.394404 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 12:21:57.398673 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 12:21:57.402039 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 12:21:57.409826 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 12:21:57.413527 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 12:21:57.417811 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 12:21:57.425122 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 12:21:57.428661 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 12:21:57.432267 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 12:21:57.435790 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 12:21:57.439346 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 12:21:57.446575 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 12:21:57.450815 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 12:21:57.454524 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 12:21:57.458124 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 12:21:57.461812 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 12:21:57.465391 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 12:21:57.469496 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 12:21:57.473047 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 12:21:57.484585 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 12:21:57.491612 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 12:21:57.495973 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 12:21:57.503101 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 12:21:57.514331 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 12:21:57.517928 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 12:21:57.521398 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 12:21:57.525000 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 12:21:57.532969 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x39
473 12:21:57.536828 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 12:21:57.545128 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 12:21:57.548901 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 12:21:57.557279 [RTC]rtc_get_frequency_meter,154: input=15, output=759
477 12:21:57.567161 [RTC]rtc_get_frequency_meter,154: input=23, output=939
478 12:21:57.576564 [RTC]rtc_get_frequency_meter,154: input=19, output=851
479 12:21:57.585731 [RTC]rtc_get_frequency_meter,154: input=17, output=804
480 12:21:57.596173 [RTC]rtc_get_frequency_meter,154: input=16, output=782
481 12:21:57.605140 [RTC]rtc_get_frequency_meter,154: input=16, output=781
482 12:21:57.615206 [RTC]rtc_get_frequency_meter,154: input=17, output=804
483 12:21:57.618228 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 12:21:57.625281 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 12:21:57.629547 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 12:21:57.632724 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 12:21:57.636340 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 12:21:57.639810 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 12:21:57.643835 ADC[4]: Raw value=906942 ID=7
490 12:21:57.647571 ADC[3]: Raw value=213441 ID=1
491 12:21:57.647666 RAM Code: 0x71
492 12:21:57.651364 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 12:21:57.658455 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 12:21:57.665672 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 12:21:57.673655 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 12:21:57.677170 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 12:21:57.681170 in-header: 03 07 00 00 08 00 00 00
498 12:21:57.681279 in-data: aa e4 47 04 13 02 00 00
499 12:21:57.684661 Chrome EC: UHEPI supported
500 12:21:57.691778 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 12:21:57.695238 in-header: 03 95 00 00 08 00 00 00
502 12:21:57.699209 in-data: 18 20 20 08 00 00 00 00
503 12:21:57.703392 MRC: failed to locate region type 0.
504 12:21:57.710290 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 12:21:57.710382 DRAM-K: Running full calibration
506 12:21:57.717812 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 12:21:57.721678 header.status = 0x0
508 12:21:57.721763 header.version = 0x6 (expected: 0x6)
509 12:21:57.725571 header.size = 0xd00 (expected: 0xd00)
510 12:21:57.729633 header.flags = 0x0
511 12:21:57.733301 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 12:21:57.753264 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
513 12:21:57.760614 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 12:21:57.760707 dram_init: ddr_geometry: 2
515 12:21:57.764298 [EMI] MDL number = 2
516 12:21:57.767596 [EMI] Get MDL freq = 0
517 12:21:57.767682 dram_init: ddr_type: 0
518 12:21:57.771989 is_discrete_lpddr4: 1
519 12:21:57.775465 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 12:21:57.775571
521 12:21:57.775683
522 12:21:57.775787 [Bian_co] ETT version 0.0.0.1
523 12:21:57.783156 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 12:21:57.783247
525 12:21:57.786762 dramc_set_vcore_voltage set vcore to 650000
526 12:21:57.786854 Read voltage for 800, 4
527 12:21:57.786960 Vio18 = 0
528 12:21:57.790389 Vcore = 650000
529 12:21:57.790503 Vdram = 0
530 12:21:57.790610 Vddq = 0
531 12:21:57.793952 Vmddr = 0
532 12:21:57.794041 dram_init: config_dvfs: 1
533 12:21:57.801899 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 12:21:57.805117 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 12:21:57.809004 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 12:21:57.813249 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 12:21:57.816701 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 12:21:57.820605 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 12:21:57.824256 MEM_TYPE=3, freq_sel=18
540 12:21:57.824371 sv_algorithm_assistance_LP4_1600
541 12:21:57.831033 ============ PULL DRAM RESETB DOWN ============
542 12:21:57.834582 ========== PULL DRAM RESETB DOWN end =========
543 12:21:57.837456 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 12:21:57.840846 ===================================
545 12:21:57.844996 LPDDR4 DRAM CONFIGURATION
546 12:21:57.848714 ===================================
547 12:21:57.848797 EX_ROW_EN[0] = 0x0
548 12:21:57.852237 EX_ROW_EN[1] = 0x0
549 12:21:57.852343 LP4Y_EN = 0x0
550 12:21:57.856112 WORK_FSP = 0x0
551 12:21:57.856195 WL = 0x2
552 12:21:57.860488 RL = 0x2
553 12:21:57.860575 BL = 0x2
554 12:21:57.860645 RPST = 0x0
555 12:21:57.864196 RD_PRE = 0x0
556 12:21:57.864282 WR_PRE = 0x1
557 12:21:57.867602 WR_PST = 0x0
558 12:21:57.867690 DBI_WR = 0x0
559 12:21:57.870544 DBI_RD = 0x0
560 12:21:57.870624 OTF = 0x1
561 12:21:57.873719 ===================================
562 12:21:57.877603 ===================================
563 12:21:57.880526 ANA top config
564 12:21:57.883936 ===================================
565 12:21:57.887285 DLL_ASYNC_EN = 0
566 12:21:57.887395 ALL_SLAVE_EN = 1
567 12:21:57.890325 NEW_RANK_MODE = 1
568 12:21:57.894133 DLL_IDLE_MODE = 1
569 12:21:57.897080 LP45_APHY_COMB_EN = 1
570 12:21:57.897197 TX_ODT_DIS = 1
571 12:21:57.900607 NEW_8X_MODE = 1
572 12:21:57.904295 ===================================
573 12:21:57.908243 ===================================
574 12:21:57.911390 data_rate = 1600
575 12:21:57.915096 CKR = 1
576 12:21:57.915203 DQ_P2S_RATIO = 8
577 12:21:57.917953 ===================================
578 12:21:57.921162 CA_P2S_RATIO = 8
579 12:21:57.924724 DQ_CA_OPEN = 0
580 12:21:57.928446 DQ_SEMI_OPEN = 0
581 12:21:57.931647 CA_SEMI_OPEN = 0
582 12:21:57.934726 CA_FULL_RATE = 0
583 12:21:57.934828 DQ_CKDIV4_EN = 1
584 12:21:57.938139 CA_CKDIV4_EN = 1
585 12:21:57.941574 CA_PREDIV_EN = 0
586 12:21:57.945004 PH8_DLY = 0
587 12:21:57.948294 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 12:21:57.951353 DQ_AAMCK_DIV = 4
589 12:21:57.951467 CA_AAMCK_DIV = 4
590 12:21:57.955077 CA_ADMCK_DIV = 4
591 12:21:57.957992 DQ_TRACK_CA_EN = 0
592 12:21:57.961646 CA_PICK = 800
593 12:21:57.965234 CA_MCKIO = 800
594 12:21:57.965338 MCKIO_SEMI = 0
595 12:21:57.969436 PLL_FREQ = 3068
596 12:21:57.972983 DQ_UI_PI_RATIO = 32
597 12:21:57.976561 CA_UI_PI_RATIO = 0
598 12:21:57.980586 ===================================
599 12:21:57.980673 ===================================
600 12:21:57.983833 memory_type:LPDDR4
601 12:21:57.987379 GP_NUM : 10
602 12:21:57.987490 SRAM_EN : 1
603 12:21:57.990839 MD32_EN : 0
604 12:21:57.995249 ===================================
605 12:21:57.995367 [ANA_INIT] >>>>>>>>>>>>>>
606 12:21:57.998235 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 12:21:58.002431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 12:21:58.005574 ===================================
609 12:21:58.009179 data_rate = 1600,PCW = 0X7600
610 12:21:58.012123 ===================================
611 12:21:58.015680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 12:21:58.022428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 12:21:58.025397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 12:21:58.032175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 12:21:58.035536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 12:21:58.039123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 12:21:58.039210 [ANA_INIT] flow start
618 12:21:58.042168 [ANA_INIT] PLL >>>>>>>>
619 12:21:58.045856 [ANA_INIT] PLL <<<<<<<<
620 12:21:58.045966 [ANA_INIT] MIDPI >>>>>>>>
621 12:21:58.048951 [ANA_INIT] MIDPI <<<<<<<<
622 12:21:58.052625 [ANA_INIT] DLL >>>>>>>>
623 12:21:58.052734 [ANA_INIT] flow end
624 12:21:58.055732 ============ LP4 DIFF to SE enter ============
625 12:21:58.062889 ============ LP4 DIFF to SE exit ============
626 12:21:58.062974 [ANA_INIT] <<<<<<<<<<<<<
627 12:21:58.065984 [Flow] Enable top DCM control >>>>>
628 12:21:58.069021 [Flow] Enable top DCM control <<<<<
629 12:21:58.072594 Enable DLL master slave shuffle
630 12:21:58.079238 ==============================================================
631 12:21:58.079349 Gating Mode config
632 12:21:58.086284 ==============================================================
633 12:21:58.089090 Config description:
634 12:21:58.096124 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 12:21:58.102953 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 12:21:58.109272 SELPH_MODE 0: By rank 1: By Phase
637 12:21:58.116535 ==============================================================
638 12:21:58.116624 GAT_TRACK_EN = 1
639 12:21:58.119483 RX_GATING_MODE = 2
640 12:21:58.122861 RX_GATING_TRACK_MODE = 2
641 12:21:58.125920 SELPH_MODE = 1
642 12:21:58.129692 PICG_EARLY_EN = 1
643 12:21:58.132537 VALID_LAT_VALUE = 1
644 12:21:58.139299 ==============================================================
645 12:21:58.142803 Enter into Gating configuration >>>>
646 12:21:58.146414 Exit from Gating configuration <<<<
647 12:21:58.149264 Enter into DVFS_PRE_config >>>>>
648 12:21:58.159474 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 12:21:58.162923 Exit from DVFS_PRE_config <<<<<
650 12:21:58.166309 Enter into PICG configuration >>>>
651 12:21:58.169955 Exit from PICG configuration <<<<
652 12:21:58.170042 [RX_INPUT] configuration >>>>>
653 12:21:58.173341 [RX_INPUT] configuration <<<<<
654 12:21:58.179954 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 12:21:58.183496 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 12:21:58.190236 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 12:21:58.196918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 12:21:58.203527 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 12:21:58.209931 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 12:21:58.213455 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 12:21:58.216887 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 12:21:58.223320 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 12:21:58.226916 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 12:21:58.230011 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 12:21:58.233552 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 12:21:58.236551 ===================================
667 12:21:58.239839 LPDDR4 DRAM CONFIGURATION
668 12:21:58.243234 ===================================
669 12:21:58.246719 EX_ROW_EN[0] = 0x0
670 12:21:58.246837 EX_ROW_EN[1] = 0x0
671 12:21:58.249810 LP4Y_EN = 0x0
672 12:21:58.249920 WORK_FSP = 0x0
673 12:21:58.253245 WL = 0x2
674 12:21:58.253340 RL = 0x2
675 12:21:58.256844 BL = 0x2
676 12:21:58.256952 RPST = 0x0
677 12:21:58.260248 RD_PRE = 0x0
678 12:21:58.260327 WR_PRE = 0x1
679 12:21:58.263301 WR_PST = 0x0
680 12:21:58.263383 DBI_WR = 0x0
681 12:21:58.266771 DBI_RD = 0x0
682 12:21:58.266874 OTF = 0x1
683 12:21:58.269932 ===================================
684 12:21:58.273497 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 12:21:58.280233 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 12:21:58.283390 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 12:21:58.286605 ===================================
688 12:21:58.289899 LPDDR4 DRAM CONFIGURATION
689 12:21:58.293536 ===================================
690 12:21:58.293651 EX_ROW_EN[0] = 0x10
691 12:21:58.297087 EX_ROW_EN[1] = 0x0
692 12:21:58.297194 LP4Y_EN = 0x0
693 12:21:58.299999 WORK_FSP = 0x0
694 12:21:58.303524 WL = 0x2
695 12:21:58.303638 RL = 0x2
696 12:21:58.306958 BL = 0x2
697 12:21:58.307075 RPST = 0x0
698 12:21:58.310025 RD_PRE = 0x0
699 12:21:58.310113 WR_PRE = 0x1
700 12:21:58.313467 WR_PST = 0x0
701 12:21:58.313553 DBI_WR = 0x0
702 12:21:58.317178 DBI_RD = 0x0
703 12:21:58.317264 OTF = 0x1
704 12:21:58.320049 ===================================
705 12:21:58.326746 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 12:21:58.330382 nWR fixed to 40
707 12:21:58.333953 [ModeRegInit_LP4] CH0 RK0
708 12:21:58.334039 [ModeRegInit_LP4] CH0 RK1
709 12:21:58.337598 [ModeRegInit_LP4] CH1 RK0
710 12:21:58.340939 [ModeRegInit_LP4] CH1 RK1
711 12:21:58.341025 match AC timing 13
712 12:21:58.347466 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 12:21:58.350686 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 12:21:58.353979 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 12:21:58.360537 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 12:21:58.364025 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 12:21:58.364106 [EMI DOE] emi_dcm 0
718 12:21:58.370925 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 12:21:58.371014 ==
720 12:21:58.374034 Dram Type= 6, Freq= 0, CH_0, rank 0
721 12:21:58.377641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 12:21:58.377717 ==
723 12:21:58.384153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 12:21:58.387666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 12:21:58.398045 [CA 0] Center 36 (6~67) winsize 62
726 12:21:58.401648 [CA 1] Center 36 (6~67) winsize 62
727 12:21:58.404868 [CA 2] Center 34 (4~65) winsize 62
728 12:21:58.407970 [CA 3] Center 33 (3~64) winsize 62
729 12:21:58.411502 [CA 4] Center 33 (3~64) winsize 62
730 12:21:58.414804 [CA 5] Center 32 (2~62) winsize 61
731 12:21:58.414891
732 12:21:58.418098 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 12:21:58.418185
734 12:21:58.421995 [CATrainingPosCal] consider 1 rank data
735 12:21:58.424684 u2DelayCellTimex100 = 270/100 ps
736 12:21:58.428120 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 12:21:58.431166 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
738 12:21:58.438326 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 12:21:58.441331 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
740 12:21:58.444990 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
741 12:21:58.448110 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
742 12:21:58.448197
743 12:21:58.451170 CA PerBit enable=1, Macro0, CA PI delay=32
744 12:21:58.451256
745 12:21:58.454665 [CBTSetCACLKResult] CA Dly = 32
746 12:21:58.454751 CS Dly: 4 (0~35)
747 12:21:58.454820 ==
748 12:21:58.458079 Dram Type= 6, Freq= 0, CH_0, rank 1
749 12:21:58.464815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 12:21:58.464910 ==
751 12:21:58.467862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 12:21:58.474572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 12:21:58.484144 [CA 0] Center 36 (6~67) winsize 62
754 12:21:58.487806 [CA 1] Center 36 (6~67) winsize 62
755 12:21:58.490727 [CA 2] Center 34 (4~65) winsize 62
756 12:21:58.494348 [CA 3] Center 34 (3~65) winsize 63
757 12:21:58.497969 [CA 4] Center 33 (2~64) winsize 63
758 12:21:58.500708 [CA 5] Center 32 (2~63) winsize 62
759 12:21:58.500815
760 12:21:58.504120 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 12:21:58.504204
762 12:21:58.507771 [CATrainingPosCal] consider 2 rank data
763 12:21:58.511018 u2DelayCellTimex100 = 270/100 ps
764 12:21:58.514520 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 12:21:58.517914 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
766 12:21:58.524168 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 12:21:58.528006 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
768 12:21:58.530835 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
769 12:21:58.534603 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
770 12:21:58.534690
771 12:21:58.537873 CA PerBit enable=1, Macro0, CA PI delay=32
772 12:21:58.537960
773 12:21:58.541053 [CBTSetCACLKResult] CA Dly = 32
774 12:21:58.541140 CS Dly: 5 (0~37)
775 12:21:58.541209
776 12:21:58.544307 ----->DramcWriteLeveling(PI) begin...
777 12:21:58.544424 ==
778 12:21:58.548733 Dram Type= 6, Freq= 0, CH_0, rank 0
779 12:21:58.552057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 12:21:58.555495 ==
781 12:21:58.555620 Write leveling (Byte 0): 34 => 34
782 12:21:58.559703 Write leveling (Byte 1): 30 => 30
783 12:21:58.562969 DramcWriteLeveling(PI) end<-----
784 12:21:58.563055
785 12:21:58.563123 ==
786 12:21:58.566531 Dram Type= 6, Freq= 0, CH_0, rank 0
787 12:21:58.569585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 12:21:58.569672 ==
789 12:21:58.573015 [Gating] SW mode calibration
790 12:21:58.580183 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 12:21:58.587359 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 12:21:58.590570 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 12:21:58.593523 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 12:21:58.600246 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 12:21:58.603567 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:21:58.607175 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:21:58.610294 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:21:58.617599 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:21:58.620543 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:21:58.623668 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:21:58.630779 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:21:58.633798 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:21:58.637367 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:21:58.644312 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:21:58.647482 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:21:58.650964 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:21:58.657363 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:21:58.660722 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:21:58.663987 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 12:21:58.670754 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
811 12:21:58.674508 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
812 12:21:58.677502 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:21:58.681087 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:21:58.687248 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:21:58.690671 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:21:58.694337 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:21:58.700849 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:21:58.704352 0 9 8 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
819 12:21:58.707854 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
820 12:21:58.714457 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 12:21:58.717468 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 12:21:58.721018 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 12:21:58.727635 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 12:21:58.731317 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 12:21:58.734228 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
826 12:21:58.741322 0 10 8 | B1->B0 | 3030 2525 | 1 0 | (1 1) (0 0)
827 12:21:58.744283 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
828 12:21:58.747798 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:21:58.754333 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:21:58.757936 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:21:58.760960 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 12:21:58.764241 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 12:21:58.770859 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
834 12:21:58.774469 0 11 8 | B1->B0 | 2b2b 3e3e | 0 1 | (0 0) (0 0)
835 12:21:58.777581 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
836 12:21:58.784376 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:21:58.787782 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:21:58.790852 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 12:21:58.797583 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 12:21:58.800815 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 12:21:58.804215 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 12:21:58.810487 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 12:21:58.814192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:21:58.817623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:21:58.824365 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:21:58.827443 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:21:58.831198 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:21:58.837859 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:21:58.840799 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:21:58.844317 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:21:58.851008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:21:58.853927 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:21:58.857434 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:21:58.864514 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:21:58.867537 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:21:58.870584 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:21:58.874173 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 12:21:58.880619 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 12:21:58.883901 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 12:21:58.887541 Total UI for P1: 0, mck2ui 16
861 12:21:58.890604 best dqsien dly found for B0: ( 0, 14, 6)
862 12:21:58.893998 Total UI for P1: 0, mck2ui 16
863 12:21:58.897270 best dqsien dly found for B1: ( 0, 14, 8)
864 12:21:58.901477 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
865 12:21:58.904455 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 12:21:58.904534
867 12:21:58.907887 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
868 12:21:58.911517 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 12:21:58.914827 [Gating] SW calibration Done
870 12:21:58.914931 ==
871 12:21:58.918306 Dram Type= 6, Freq= 0, CH_0, rank 0
872 12:21:58.921161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 12:21:58.921261 ==
874 12:21:58.924860 RX Vref Scan: 0
875 12:21:58.924959
876 12:21:58.927998 RX Vref 0 -> 0, step: 1
877 12:21:58.928104
878 12:21:58.928202 RX Delay -130 -> 252, step: 16
879 12:21:58.935153 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
880 12:21:58.938167 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 12:21:58.941776 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 12:21:58.944762 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 12:21:58.948273 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 12:21:58.952004 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 12:21:58.958614 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
886 12:21:58.962159 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
887 12:21:58.965187 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
888 12:21:58.968634 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
889 12:21:58.971800 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 12:21:58.978316 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 12:21:58.981807 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
892 12:21:58.985356 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
893 12:21:58.988635 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
894 12:21:58.991832 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 12:21:58.995392 ==
896 12:21:58.998557 Dram Type= 6, Freq= 0, CH_0, rank 0
897 12:21:59.001984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 12:21:59.002065 ==
899 12:21:59.002132 DQS Delay:
900 12:21:59.005466 DQS0 = 0, DQS1 = 0
901 12:21:59.005547 DQM Delay:
902 12:21:59.008856 DQM0 = 90, DQM1 = 84
903 12:21:59.008942 DQ Delay:
904 12:21:59.011895 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
905 12:21:59.015502 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
906 12:21:59.018934 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
907 12:21:59.021836 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
908 12:21:59.021954
909 12:21:59.022027
910 12:21:59.022091 ==
911 12:21:59.025417 Dram Type= 6, Freq= 0, CH_0, rank 0
912 12:21:59.028658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 12:21:59.028744 ==
914 12:21:59.028813
915 12:21:59.028875
916 12:21:59.031965 TX Vref Scan disable
917 12:21:59.035210 == TX Byte 0 ==
918 12:21:59.038768 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
919 12:21:59.041850 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
920 12:21:59.045543 == TX Byte 1 ==
921 12:21:59.048695 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
922 12:21:59.052154 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
923 12:21:59.052235 ==
924 12:21:59.055220 Dram Type= 6, Freq= 0, CH_0, rank 0
925 12:21:59.058941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 12:21:59.061798 ==
927 12:21:59.073361 TX Vref=22, minBit 8, minWin=27, winSum=446
928 12:21:59.076957 TX Vref=24, minBit 9, minWin=27, winSum=453
929 12:21:59.080081 TX Vref=26, minBit 8, minWin=27, winSum=451
930 12:21:59.083734 TX Vref=28, minBit 0, minWin=28, winSum=455
931 12:21:59.086699 TX Vref=30, minBit 8, minWin=27, winSum=455
932 12:21:59.090374 TX Vref=32, minBit 10, minWin=27, winSum=454
933 12:21:59.097295 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
934 12:21:59.097381
935 12:21:59.100459 Final TX Range 1 Vref 28
936 12:21:59.100544
937 12:21:59.100612 ==
938 12:21:59.103658 Dram Type= 6, Freq= 0, CH_0, rank 0
939 12:21:59.107285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 12:21:59.107371 ==
941 12:21:59.107444
942 12:21:59.110296
943 12:21:59.110381 TX Vref Scan disable
944 12:21:59.113647 == TX Byte 0 ==
945 12:21:59.116713 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
946 12:21:59.120375 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
947 12:21:59.123780 == TX Byte 1 ==
948 12:21:59.127321 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 12:21:59.130570 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 12:21:59.133649
951 12:21:59.133736 [DATLAT]
952 12:21:59.133812 Freq=800, CH0 RK0
953 12:21:59.133880
954 12:21:59.137072 DATLAT Default: 0xa
955 12:21:59.137150 0, 0xFFFF, sum = 0
956 12:21:59.140226 1, 0xFFFF, sum = 0
957 12:21:59.140304 2, 0xFFFF, sum = 0
958 12:21:59.143918 3, 0xFFFF, sum = 0
959 12:21:59.143998 4, 0xFFFF, sum = 0
960 12:21:59.146870 5, 0xFFFF, sum = 0
961 12:21:59.146948 6, 0xFFFF, sum = 0
962 12:21:59.150147 7, 0xFFFF, sum = 0
963 12:21:59.153502 8, 0xFFFF, sum = 0
964 12:21:59.153589 9, 0x0, sum = 1
965 12:21:59.153658 10, 0x0, sum = 2
966 12:21:59.157118 11, 0x0, sum = 3
967 12:21:59.157194 12, 0x0, sum = 4
968 12:21:59.160238 best_step = 10
969 12:21:59.160317
970 12:21:59.160389 ==
971 12:21:59.163488 Dram Type= 6, Freq= 0, CH_0, rank 0
972 12:21:59.166959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 12:21:59.167047 ==
974 12:21:59.170363 RX Vref Scan: 1
975 12:21:59.170450
976 12:21:59.170517 Set Vref Range= 32 -> 127
977 12:21:59.170581
978 12:21:59.173974 RX Vref 32 -> 127, step: 1
979 12:21:59.174078
980 12:21:59.177025 RX Delay -79 -> 252, step: 8
981 12:21:59.177112
982 12:21:59.180641 Set Vref, RX VrefLevel [Byte0]: 32
983 12:21:59.183573 [Byte1]: 32
984 12:21:59.183664
985 12:21:59.187235 Set Vref, RX VrefLevel [Byte0]: 33
986 12:21:59.190243 [Byte1]: 33
987 12:21:59.193918
988 12:21:59.194001 Set Vref, RX VrefLevel [Byte0]: 34
989 12:21:59.197477 [Byte1]: 34
990 12:21:59.201542
991 12:21:59.201628 Set Vref, RX VrefLevel [Byte0]: 35
992 12:21:59.204569 [Byte1]: 35
993 12:21:59.208894
994 12:21:59.209014 Set Vref, RX VrefLevel [Byte0]: 36
995 12:21:59.212353 [Byte1]: 36
996 12:21:59.216777
997 12:21:59.216864 Set Vref, RX VrefLevel [Byte0]: 37
998 12:21:59.220323 [Byte1]: 37
999 12:21:59.224463
1000 12:21:59.224545 Set Vref, RX VrefLevel [Byte0]: 38
1001 12:21:59.227822 [Byte1]: 38
1002 12:21:59.231993
1003 12:21:59.232076 Set Vref, RX VrefLevel [Byte0]: 39
1004 12:21:59.235436 [Byte1]: 39
1005 12:21:59.239596
1006 12:21:59.239712 Set Vref, RX VrefLevel [Byte0]: 40
1007 12:21:59.242542 [Byte1]: 40
1008 12:21:59.246879
1009 12:21:59.246957 Set Vref, RX VrefLevel [Byte0]: 41
1010 12:21:59.250529 [Byte1]: 41
1011 12:21:59.254159
1012 12:21:59.254238 Set Vref, RX VrefLevel [Byte0]: 42
1013 12:21:59.257252 [Byte1]: 42
1014 12:21:59.262002
1015 12:21:59.262089 Set Vref, RX VrefLevel [Byte0]: 43
1016 12:21:59.264789 [Byte1]: 43
1017 12:21:59.269207
1018 12:21:59.269291 Set Vref, RX VrefLevel [Byte0]: 44
1019 12:21:59.272578 [Byte1]: 44
1020 12:21:59.277016
1021 12:21:59.277099 Set Vref, RX VrefLevel [Byte0]: 45
1022 12:21:59.280185 [Byte1]: 45
1023 12:21:59.284679
1024 12:21:59.284756 Set Vref, RX VrefLevel [Byte0]: 46
1025 12:21:59.287744 [Byte1]: 46
1026 12:21:59.291935
1027 12:21:59.292017 Set Vref, RX VrefLevel [Byte0]: 47
1028 12:21:59.295539 [Byte1]: 47
1029 12:21:59.299582
1030 12:21:59.299705 Set Vref, RX VrefLevel [Byte0]: 48
1031 12:21:59.302690 [Byte1]: 48
1032 12:21:59.307391
1033 12:21:59.307467 Set Vref, RX VrefLevel [Byte0]: 49
1034 12:21:59.310391 [Byte1]: 49
1035 12:21:59.314766
1036 12:21:59.314869 Set Vref, RX VrefLevel [Byte0]: 50
1037 12:21:59.317612 [Byte1]: 50
1038 12:21:59.321980
1039 12:21:59.322056 Set Vref, RX VrefLevel [Byte0]: 51
1040 12:21:59.325536 [Byte1]: 51
1041 12:21:59.329724
1042 12:21:59.329800 Set Vref, RX VrefLevel [Byte0]: 52
1043 12:21:59.332959 [Byte1]: 52
1044 12:21:59.337584
1045 12:21:59.337685 Set Vref, RX VrefLevel [Byte0]: 53
1046 12:21:59.340671 [Byte1]: 53
1047 12:21:59.345130
1048 12:21:59.345246 Set Vref, RX VrefLevel [Byte0]: 54
1049 12:21:59.348403 [Byte1]: 54
1050 12:21:59.352193
1051 12:21:59.352284 Set Vref, RX VrefLevel [Byte0]: 55
1052 12:21:59.355506 [Byte1]: 55
1053 12:21:59.359753
1054 12:21:59.359858 Set Vref, RX VrefLevel [Byte0]: 56
1055 12:21:59.363459 [Byte1]: 56
1056 12:21:59.367686
1057 12:21:59.367771 Set Vref, RX VrefLevel [Byte0]: 57
1058 12:21:59.370654 [Byte1]: 57
1059 12:21:59.375265
1060 12:21:59.375345 Set Vref, RX VrefLevel [Byte0]: 58
1061 12:21:59.378065 [Byte1]: 58
1062 12:21:59.382619
1063 12:21:59.382728 Set Vref, RX VrefLevel [Byte0]: 59
1064 12:21:59.385588 [Byte1]: 59
1065 12:21:59.390374
1066 12:21:59.390451 Set Vref, RX VrefLevel [Byte0]: 60
1067 12:21:59.393200 [Byte1]: 60
1068 12:21:59.397704
1069 12:21:59.397784 Set Vref, RX VrefLevel [Byte0]: 61
1070 12:21:59.404532 [Byte1]: 61
1071 12:21:59.404638
1072 12:21:59.407511 Set Vref, RX VrefLevel [Byte0]: 62
1073 12:21:59.411179 [Byte1]: 62
1074 12:21:59.411257
1075 12:21:59.414148 Set Vref, RX VrefLevel [Byte0]: 63
1076 12:21:59.417558 [Byte1]: 63
1077 12:21:59.417635
1078 12:21:59.421035 Set Vref, RX VrefLevel [Byte0]: 64
1079 12:21:59.424118 [Byte1]: 64
1080 12:21:59.427631
1081 12:21:59.427730 Set Vref, RX VrefLevel [Byte0]: 65
1082 12:21:59.431264 [Byte1]: 65
1083 12:21:59.435509
1084 12:21:59.435625 Set Vref, RX VrefLevel [Byte0]: 66
1085 12:21:59.438994 [Byte1]: 66
1086 12:21:59.442899
1087 12:21:59.442985 Set Vref, RX VrefLevel [Byte0]: 67
1088 12:21:59.446570 [Byte1]: 67
1089 12:21:59.450546
1090 12:21:59.450649 Set Vref, RX VrefLevel [Byte0]: 68
1091 12:21:59.453591 [Byte1]: 68
1092 12:21:59.458254
1093 12:21:59.458369 Set Vref, RX VrefLevel [Byte0]: 69
1094 12:21:59.461283 [Byte1]: 69
1095 12:21:59.465545
1096 12:21:59.465655 Set Vref, RX VrefLevel [Byte0]: 70
1097 12:21:59.469180 [Byte1]: 70
1098 12:21:59.473421
1099 12:21:59.473502 Set Vref, RX VrefLevel [Byte0]: 71
1100 12:21:59.476338 [Byte1]: 71
1101 12:21:59.480563
1102 12:21:59.480641 Set Vref, RX VrefLevel [Byte0]: 72
1103 12:21:59.484163 [Byte1]: 72
1104 12:21:59.488188
1105 12:21:59.488270 Set Vref, RX VrefLevel [Byte0]: 73
1106 12:21:59.491714 [Byte1]: 73
1107 12:21:59.495918
1108 12:21:59.496004 Set Vref, RX VrefLevel [Byte0]: 74
1109 12:21:59.499320 [Byte1]: 74
1110 12:21:59.503154
1111 12:21:59.503260 Set Vref, RX VrefLevel [Byte0]: 75
1112 12:21:59.506494 [Byte1]: 75
1113 12:21:59.511213
1114 12:21:59.511296 Final RX Vref Byte 0 = 58 to rank0
1115 12:21:59.514392 Final RX Vref Byte 1 = 58 to rank0
1116 12:21:59.517395 Final RX Vref Byte 0 = 58 to rank1
1117 12:21:59.520909 Final RX Vref Byte 1 = 58 to rank1==
1118 12:21:59.523997 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 12:21:59.530777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 12:21:59.530900 ==
1121 12:21:59.530998 DQS Delay:
1122 12:21:59.531090 DQS0 = 0, DQS1 = 0
1123 12:21:59.534454 DQM Delay:
1124 12:21:59.534561 DQM0 = 92, DQM1 = 84
1125 12:21:59.537814 DQ Delay:
1126 12:21:59.541126 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 12:21:59.544503 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1128 12:21:59.544583 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1129 12:21:59.551209 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1130 12:21:59.551314
1131 12:21:59.551417
1132 12:21:59.557563 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1133 12:21:59.561029 CH0 RK0: MR19=606, MR18=4D43
1134 12:21:59.567576 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64
1135 12:21:59.567671
1136 12:21:59.571185 ----->DramcWriteLeveling(PI) begin...
1137 12:21:59.571274 ==
1138 12:21:59.574701 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 12:21:59.577618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 12:21:59.577697 ==
1141 12:21:59.581249 Write leveling (Byte 0): 33 => 33
1142 12:21:59.584333 Write leveling (Byte 1): 29 => 29
1143 12:21:59.587821 DramcWriteLeveling(PI) end<-----
1144 12:21:59.587896
1145 12:21:59.587963 ==
1146 12:21:59.591254 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 12:21:59.594277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 12:21:59.594353 ==
1149 12:21:59.597839 [Gating] SW mode calibration
1150 12:21:59.604526 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 12:21:59.611607 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 12:21:59.614417 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 12:21:59.617758 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 12:21:59.661685 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 12:21:59.661994 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:21:59.662077 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:21:59.662145 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:21:59.662206 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:21:59.662291 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:21:59.662356 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:21:59.662437 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:21:59.662516 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:21:59.662607 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:21:59.703509 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:21:59.703866 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:21:59.703950 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:21:59.704016 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:21:59.704078 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:21:59.704142 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:21:59.704217 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 12:21:59.704701 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:21:59.707698 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:21:59.707783 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:21:59.710806 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:21:59.713765 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:21:59.721294 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:21:59.724206 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:21:59.727565 0 9 8 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (1 1)
1179 12:21:59.734044 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 12:21:59.737376 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:21:59.740847 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:21:59.747432 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:21:59.750904 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:21:59.753923 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:21:59.760477 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
1186 12:21:59.764164 0 10 8 | B1->B0 | 2a2a 2b2b | 0 1 | (1 0) (1 1)
1187 12:21:59.767345 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:21:59.774037 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:21:59.777668 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:21:59.780814 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:21:59.784351 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:21:59.791239 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:21:59.794961 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1194 12:21:59.798972 0 11 8 | B1->B0 | 3b3b 3b3b | 1 1 | (0 0) (0 0)
1195 12:21:59.802751 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 12:21:59.806345 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:21:59.813333 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:21:59.816446 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:21:59.820489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:21:59.824107 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:21:59.830582 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:21:59.834022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 12:21:59.837494 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:21:59.844585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:21:59.847441 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:21:59.850970 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:21:59.857495 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:21:59.861099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:21:59.864706 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:21:59.867862 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:21:59.874118 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:21:59.877700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:21:59.880800 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:21:59.887793 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:21:59.891311 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:21:59.894103 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:21:59.901244 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:21:59.904170 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 12:21:59.907750 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 12:21:59.911397 Total UI for P1: 0, mck2ui 16
1221 12:21:59.914490 best dqsien dly found for B0: ( 0, 14, 8)
1222 12:21:59.918066 Total UI for P1: 0, mck2ui 16
1223 12:21:59.921235 best dqsien dly found for B1: ( 0, 14, 8)
1224 12:21:59.924835 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 12:21:59.927885 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 12:21:59.928000
1227 12:21:59.931288 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 12:21:59.938018 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 12:21:59.938128 [Gating] SW calibration Done
1230 12:21:59.938236 ==
1231 12:21:59.941137 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 12:21:59.948147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 12:21:59.948259 ==
1234 12:21:59.948363 RX Vref Scan: 0
1235 12:21:59.948467
1236 12:21:59.951568 RX Vref 0 -> 0, step: 1
1237 12:21:59.951659
1238 12:21:59.954558 RX Delay -130 -> 252, step: 16
1239 12:21:59.958170 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1240 12:21:59.961131 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1241 12:21:59.964892 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1242 12:21:59.968370 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1243 12:21:59.974544 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1244 12:21:59.977912 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1245 12:21:59.981432 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1246 12:21:59.984856 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1247 12:21:59.988336 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1248 12:21:59.994668 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1249 12:21:59.998320 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1250 12:22:00.001258 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 12:22:00.004766 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1252 12:22:00.008115 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1253 12:22:00.014977 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1254 12:22:00.018410 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1255 12:22:00.018490 ==
1256 12:22:00.021548 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 12:22:00.025021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 12:22:00.025109 ==
1259 12:22:00.028022 DQS Delay:
1260 12:22:00.028124 DQS0 = 0, DQS1 = 0
1261 12:22:00.028212 DQM Delay:
1262 12:22:00.031495 DQM0 = 93, DQM1 = 85
1263 12:22:00.031610 DQ Delay:
1264 12:22:00.034507 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1265 12:22:00.038024 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1266 12:22:00.041058 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1267 12:22:00.044699 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1268 12:22:00.044781
1269 12:22:00.044865
1270 12:22:00.044944 ==
1271 12:22:00.048281 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 12:22:00.054586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 12:22:00.054673 ==
1274 12:22:00.054766
1275 12:22:00.054851
1276 12:22:00.054929 TX Vref Scan disable
1277 12:22:00.058675 == TX Byte 0 ==
1278 12:22:00.061702 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1279 12:22:00.068334 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1280 12:22:00.068420 == TX Byte 1 ==
1281 12:22:00.071766 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1282 12:22:00.078422 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1283 12:22:00.078509 ==
1284 12:22:00.081815 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 12:22:00.084790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 12:22:00.084872 ==
1287 12:22:00.098129 TX Vref=22, minBit 8, minWin=27, winSum=446
1288 12:22:00.101569 TX Vref=24, minBit 8, minWin=27, winSum=450
1289 12:22:00.104758 TX Vref=26, minBit 1, minWin=28, winSum=453
1290 12:22:00.107902 TX Vref=28, minBit 12, minWin=27, winSum=454
1291 12:22:00.111218 TX Vref=30, minBit 4, minWin=28, winSum=456
1292 12:22:00.114696 TX Vref=32, minBit 4, minWin=28, winSum=456
1293 12:22:00.121670 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 30
1294 12:22:00.121755
1295 12:22:00.124539 Final TX Range 1 Vref 30
1296 12:22:00.124623
1297 12:22:00.124730 ==
1298 12:22:00.128166 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 12:22:00.131126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 12:22:00.131239 ==
1301 12:22:00.131344
1302 12:22:00.134734
1303 12:22:00.134839 TX Vref Scan disable
1304 12:22:00.138204 == TX Byte 0 ==
1305 12:22:00.141132 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1306 12:22:00.144730 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1307 12:22:00.148161 == TX Byte 1 ==
1308 12:22:00.151168 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1309 12:22:00.154723 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1310 12:22:00.157879
1311 12:22:00.157984 [DATLAT]
1312 12:22:00.158085 Freq=800, CH0 RK1
1313 12:22:00.158181
1314 12:22:00.161436 DATLAT Default: 0xa
1315 12:22:00.161515 0, 0xFFFF, sum = 0
1316 12:22:00.165080 1, 0xFFFF, sum = 0
1317 12:22:00.165160 2, 0xFFFF, sum = 0
1318 12:22:00.167893 3, 0xFFFF, sum = 0
1319 12:22:00.167997 4, 0xFFFF, sum = 0
1320 12:22:00.171714 5, 0xFFFF, sum = 0
1321 12:22:00.171793 6, 0xFFFF, sum = 0
1322 12:22:00.175015 7, 0xFFFF, sum = 0
1323 12:22:00.175096 8, 0xFFFF, sum = 0
1324 12:22:00.178445 9, 0x0, sum = 1
1325 12:22:00.178550 10, 0x0, sum = 2
1326 12:22:00.181456 11, 0x0, sum = 3
1327 12:22:00.181542 12, 0x0, sum = 4
1328 12:22:00.184949 best_step = 10
1329 12:22:00.185025
1330 12:22:00.185087 ==
1331 12:22:00.188472 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 12:22:00.191948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 12:22:00.192060 ==
1334 12:22:00.195035 RX Vref Scan: 0
1335 12:22:00.195140
1336 12:22:00.195239 RX Vref 0 -> 0, step: 1
1337 12:22:00.195331
1338 12:22:00.198116 RX Delay -95 -> 252, step: 8
1339 12:22:00.204714 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1340 12:22:00.208556 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1341 12:22:00.211796 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 12:22:00.215337 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1343 12:22:00.218160 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1344 12:22:00.221599 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1345 12:22:00.228720 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 12:22:00.231522 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 12:22:00.235154 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1348 12:22:00.238135 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1349 12:22:00.241771 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 12:22:00.248458 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 12:22:00.252112 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1352 12:22:00.255236 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1353 12:22:00.258187 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 12:22:00.261575 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1355 12:22:00.265169 ==
1356 12:22:00.268572 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 12:22:00.271699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 12:22:00.271781 ==
1359 12:22:00.271865 DQS Delay:
1360 12:22:00.275211 DQS0 = 0, DQS1 = 0
1361 12:22:00.275291 DQM Delay:
1362 12:22:00.278796 DQM0 = 93, DQM1 = 84
1363 12:22:00.278880 DQ Delay:
1364 12:22:00.281634 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1365 12:22:00.285121 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1366 12:22:00.288082 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1367 12:22:00.291552 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1368 12:22:00.291666
1369 12:22:00.291772
1370 12:22:00.298171 [DQSOSCAuto] RK1, (LSB)MR18= 0x4213, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1371 12:22:00.301868 CH0 RK1: MR19=606, MR18=4213
1372 12:22:00.308451 CH0_RK1: MR19=0x606, MR18=0x4213, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 12:22:00.311510 [RxdqsGatingPostProcess] freq 800
1374 12:22:00.318387 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 12:22:00.318498 Pre-setting of DQS Precalculation
1376 12:22:00.324882 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 12:22:00.324969 ==
1378 12:22:00.328455 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 12:22:00.331841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 12:22:00.331951 ==
1381 12:22:00.338731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 12:22:00.345307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 12:22:00.352978 [CA 0] Center 36 (6~67) winsize 62
1384 12:22:00.356559 [CA 1] Center 36 (6~67) winsize 62
1385 12:22:00.360143 [CA 2] Center 34 (4~65) winsize 62
1386 12:22:00.363142 [CA 3] Center 34 (4~65) winsize 62
1387 12:22:00.366553 [CA 4] Center 34 (4~65) winsize 62
1388 12:22:00.369533 [CA 5] Center 34 (4~65) winsize 62
1389 12:22:00.369643
1390 12:22:00.372944 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 12:22:00.373028
1392 12:22:00.376571 [CATrainingPosCal] consider 1 rank data
1393 12:22:00.379579 u2DelayCellTimex100 = 270/100 ps
1394 12:22:00.383313 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 12:22:00.386212 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 12:22:00.393238 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 12:22:00.396453 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 12:22:00.399725 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 12:22:00.403323 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 12:22:00.403407
1401 12:22:00.406401 CA PerBit enable=1, Macro0, CA PI delay=34
1402 12:22:00.406474
1403 12:22:00.409794 [CBTSetCACLKResult] CA Dly = 34
1404 12:22:00.409891 CS Dly: 5 (0~36)
1405 12:22:00.409989 ==
1406 12:22:00.413560 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 12:22:00.420120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 12:22:00.420230 ==
1409 12:22:00.423114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 12:22:00.429937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 12:22:00.438864 [CA 0] Center 36 (6~67) winsize 62
1412 12:22:00.442519 [CA 1] Center 36 (6~67) winsize 62
1413 12:22:00.445923 [CA 2] Center 35 (5~66) winsize 62
1414 12:22:00.449064 [CA 3] Center 35 (5~65) winsize 61
1415 12:22:00.452501 [CA 4] Center 35 (5~66) winsize 62
1416 12:22:00.456409 [CA 5] Center 34 (4~65) winsize 62
1417 12:22:00.456517
1418 12:22:00.460110 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 12:22:00.460217
1420 12:22:00.463569 [CATrainingPosCal] consider 2 rank data
1421 12:22:00.467118 u2DelayCellTimex100 = 270/100 ps
1422 12:22:00.471275 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 12:22:00.474876 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 12:22:00.478544 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 12:22:00.482701 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1426 12:22:00.486354 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 12:22:00.490011 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 12:22:00.490126
1429 12:22:00.493005 CA PerBit enable=1, Macro0, CA PI delay=34
1430 12:22:00.493124
1431 12:22:00.496674 [CBTSetCACLKResult] CA Dly = 34
1432 12:22:00.496760 CS Dly: 6 (0~38)
1433 12:22:00.496829
1434 12:22:00.500195 ----->DramcWriteLeveling(PI) begin...
1435 12:22:00.500281 ==
1436 12:22:00.502991 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 12:22:00.506517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 12:22:00.509824 ==
1439 12:22:00.509908 Write leveling (Byte 0): 27 => 27
1440 12:22:00.513433 Write leveling (Byte 1): 27 => 27
1441 12:22:00.516500 DramcWriteLeveling(PI) end<-----
1442 12:22:00.516617
1443 12:22:00.516713 ==
1444 12:22:00.520028 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 12:22:00.526615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 12:22:00.526695 ==
1447 12:22:00.529882 [Gating] SW mode calibration
1448 12:22:00.536542 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 12:22:00.540104 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 12:22:00.543474 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 12:22:00.549792 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1452 12:22:00.553266 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:22:00.556694 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:22:00.563573 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:22:00.566651 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:22:00.570137 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:22:00.576883 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:22:00.580285 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:22:00.583341 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:22:00.590341 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:22:00.593233 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:22:00.596806 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:22:00.603363 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:22:00.606377 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:22:00.610064 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:22:00.616902 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:22:00.619976 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1468 12:22:00.623497 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:22:00.630209 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:22:00.633718 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:22:00.636690 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:22:00.640241 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:22:00.646431 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:22:00.649724 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:22:00.653029 0 9 4 | B1->B0 | 2322 2525 | 1 0 | (0 0) (0 0)
1476 12:22:00.660068 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1477 12:22:00.663514 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 12:22:00.666314 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:22:00.672883 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:22:00.676466 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:22:00.679958 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:22:00.686428 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:22:00.690007 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 1)
1484 12:22:00.692994 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1485 12:22:00.699792 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:22:00.703180 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:22:00.706647 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:22:00.713406 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:22:00.716324 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:22:00.719712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:22:00.726848 0 11 4 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
1492 12:22:00.730022 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1493 12:22:00.733506 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:22:00.739797 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:22:00.743371 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:22:00.746461 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:22:00.749849 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:22:00.757137 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 12:22:00.760034 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1500 12:22:00.763268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:22:00.770058 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:22:00.773570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:22:00.777228 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:22:00.783450 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:22:00.786541 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:22:00.790359 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:22:00.796599 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:22:00.800316 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:22:00.803190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:22:00.810369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:22:00.813411 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:22:00.817092 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:22:00.820185 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:22:00.826649 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:22:00.830351 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1516 12:22:00.833709 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 12:22:00.837414 Total UI for P1: 0, mck2ui 16
1518 12:22:00.840442 best dqsien dly found for B0: ( 0, 14, 6)
1519 12:22:00.843829 Total UI for P1: 0, mck2ui 16
1520 12:22:00.847225 best dqsien dly found for B1: ( 0, 14, 4)
1521 12:22:00.850783 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1522 12:22:00.853768 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 12:22:00.853867
1524 12:22:00.857352 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 12:22:00.863881 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 12:22:00.863957 [Gating] SW calibration Done
1527 12:22:00.864023 ==
1528 12:22:00.867599 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 12:22:00.873976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 12:22:00.874084 ==
1531 12:22:00.874179 RX Vref Scan: 0
1532 12:22:00.874274
1533 12:22:00.877192 RX Vref 0 -> 0, step: 1
1534 12:22:00.877288
1535 12:22:00.880422 RX Delay -130 -> 252, step: 16
1536 12:22:00.883695 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 12:22:00.887291 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 12:22:00.890387 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 12:22:00.897326 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 12:22:00.900864 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 12:22:00.903729 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 12:22:00.907299 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1543 12:22:00.910679 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 12:22:00.913845 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 12:22:00.920549 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 12:22:00.924242 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 12:22:00.927200 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 12:22:00.930663 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 12:22:00.937680 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 12:22:00.940700 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 12:22:00.944336 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1552 12:22:00.944408 ==
1553 12:22:00.947248 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 12:22:00.950868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 12:22:00.950966 ==
1556 12:22:00.953804 DQS Delay:
1557 12:22:00.953879 DQS0 = 0, DQS1 = 0
1558 12:22:00.957685 DQM Delay:
1559 12:22:00.957791 DQM0 = 93, DQM1 = 87
1560 12:22:00.957885 DQ Delay:
1561 12:22:00.960690 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1562 12:22:00.964356 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1563 12:22:00.967238 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1564 12:22:00.970782 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1565 12:22:00.970854
1566 12:22:00.970917
1567 12:22:00.970981 ==
1568 12:22:00.973868 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 12:22:00.981117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 12:22:00.981196 ==
1571 12:22:00.981261
1572 12:22:00.981323
1573 12:22:00.981388 TX Vref Scan disable
1574 12:22:00.984645 == TX Byte 0 ==
1575 12:22:00.987963 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 12:22:00.991161 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 12:22:00.994410 == TX Byte 1 ==
1578 12:22:01.007157 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 12:22:01.007290 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 12:22:01.007389 ==
1581 12:22:01.007626 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 12:22:01.010855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 12:22:01.010931 ==
1584 12:22:01.023559 TX Vref=22, minBit 0, minWin=26, winSum=434
1585 12:22:01.026791 TX Vref=24, minBit 3, minWin=26, winSum=441
1586 12:22:01.029999 TX Vref=26, minBit 1, minWin=27, winSum=441
1587 12:22:01.033671 TX Vref=28, minBit 0, minWin=27, winSum=446
1588 12:22:01.037334 TX Vref=30, minBit 1, minWin=27, winSum=448
1589 12:22:01.040995 TX Vref=32, minBit 0, minWin=27, winSum=446
1590 12:22:01.047172 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 30
1591 12:22:01.047280
1592 12:22:01.050650 Final TX Range 1 Vref 30
1593 12:22:01.050748
1594 12:22:01.050841 ==
1595 12:22:01.053940 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 12:22:01.057658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 12:22:01.057758 ==
1598 12:22:01.057851
1599 12:22:01.057941
1600 12:22:01.060631 TX Vref Scan disable
1601 12:22:01.064019 == TX Byte 0 ==
1602 12:22:01.067522 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 12:22:01.071160 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 12:22:01.074042 == TX Byte 1 ==
1605 12:22:01.077744 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 12:22:01.081349 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 12:22:01.081449
1608 12:22:01.084316 [DATLAT]
1609 12:22:01.084414 Freq=800, CH1 RK0
1610 12:22:01.084512
1611 12:22:01.087814 DATLAT Default: 0xa
1612 12:22:01.087889 0, 0xFFFF, sum = 0
1613 12:22:01.090913 1, 0xFFFF, sum = 0
1614 12:22:01.090990 2, 0xFFFF, sum = 0
1615 12:22:01.094251 3, 0xFFFF, sum = 0
1616 12:22:01.094352 4, 0xFFFF, sum = 0
1617 12:22:01.097575 5, 0xFFFF, sum = 0
1618 12:22:01.097686 6, 0xFFFF, sum = 0
1619 12:22:01.100911 7, 0xFFFF, sum = 0
1620 12:22:01.101016 8, 0xFFFF, sum = 0
1621 12:22:01.104239 9, 0x0, sum = 1
1622 12:22:01.104355 10, 0x0, sum = 2
1623 12:22:01.107505 11, 0x0, sum = 3
1624 12:22:01.107633 12, 0x0, sum = 4
1625 12:22:01.107735 best_step = 10
1626 12:22:01.111094
1627 12:22:01.111206 ==
1628 12:22:01.114193 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 12:22:01.117965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 12:22:01.118075 ==
1631 12:22:01.118175 RX Vref Scan: 1
1632 12:22:01.118270
1633 12:22:01.120967 Set Vref Range= 32 -> 127
1634 12:22:01.121074
1635 12:22:01.124280 RX Vref 32 -> 127, step: 1
1636 12:22:01.124386
1637 12:22:01.127769 RX Delay -79 -> 252, step: 8
1638 12:22:01.127878
1639 12:22:01.131278 Set Vref, RX VrefLevel [Byte0]: 32
1640 12:22:01.134296 [Byte1]: 32
1641 12:22:01.134403
1642 12:22:01.137601 Set Vref, RX VrefLevel [Byte0]: 33
1643 12:22:01.141063 [Byte1]: 33
1644 12:22:01.141173
1645 12:22:01.144528 Set Vref, RX VrefLevel [Byte0]: 34
1646 12:22:01.147772 [Byte1]: 34
1647 12:22:01.151015
1648 12:22:01.151124 Set Vref, RX VrefLevel [Byte0]: 35
1649 12:22:01.154504 [Byte1]: 35
1650 12:22:01.158789
1651 12:22:01.158904 Set Vref, RX VrefLevel [Byte0]: 36
1652 12:22:01.161809 [Byte1]: 36
1653 12:22:01.166557
1654 12:22:01.166667 Set Vref, RX VrefLevel [Byte0]: 37
1655 12:22:01.169585 [Byte1]: 37
1656 12:22:01.173639
1657 12:22:01.173747 Set Vref, RX VrefLevel [Byte0]: 38
1658 12:22:01.177232 [Byte1]: 38
1659 12:22:01.181389
1660 12:22:01.181496 Set Vref, RX VrefLevel [Byte0]: 39
1661 12:22:01.184385 [Byte1]: 39
1662 12:22:01.188664
1663 12:22:01.188770 Set Vref, RX VrefLevel [Byte0]: 40
1664 12:22:01.192106 [Byte1]: 40
1665 12:22:01.196174
1666 12:22:01.196292 Set Vref, RX VrefLevel [Byte0]: 41
1667 12:22:01.199859 [Byte1]: 41
1668 12:22:01.204237
1669 12:22:01.204351 Set Vref, RX VrefLevel [Byte0]: 42
1670 12:22:01.207467 [Byte1]: 42
1671 12:22:01.211365
1672 12:22:01.211480 Set Vref, RX VrefLevel [Byte0]: 43
1673 12:22:01.214808 [Byte1]: 43
1674 12:22:01.219094
1675 12:22:01.219207 Set Vref, RX VrefLevel [Byte0]: 44
1676 12:22:01.222509 [Byte1]: 44
1677 12:22:01.226808
1678 12:22:01.226919 Set Vref, RX VrefLevel [Byte0]: 45
1679 12:22:01.229842 [Byte1]: 45
1680 12:22:01.234159
1681 12:22:01.234257 Set Vref, RX VrefLevel [Byte0]: 46
1682 12:22:01.237683 [Byte1]: 46
1683 12:22:01.241982
1684 12:22:01.242095 Set Vref, RX VrefLevel [Byte0]: 47
1685 12:22:01.244678 [Byte1]: 47
1686 12:22:01.249592
1687 12:22:01.249715 Set Vref, RX VrefLevel [Byte0]: 48
1688 12:22:01.252870 [Byte1]: 48
1689 12:22:01.256796
1690 12:22:01.256882 Set Vref, RX VrefLevel [Byte0]: 49
1691 12:22:01.260135 [Byte1]: 49
1692 12:22:01.264327
1693 12:22:01.264441 Set Vref, RX VrefLevel [Byte0]: 50
1694 12:22:01.267659 [Byte1]: 50
1695 12:22:01.272119
1696 12:22:01.272236 Set Vref, RX VrefLevel [Byte0]: 51
1697 12:22:01.274953 [Byte1]: 51
1698 12:22:01.279696
1699 12:22:01.279783 Set Vref, RX VrefLevel [Byte0]: 52
1700 12:22:01.282789 [Byte1]: 52
1701 12:22:01.286935
1702 12:22:01.287056 Set Vref, RX VrefLevel [Byte0]: 53
1703 12:22:01.290572 [Byte1]: 53
1704 12:22:01.294719
1705 12:22:01.294826 Set Vref, RX VrefLevel [Byte0]: 54
1706 12:22:01.297573 [Byte1]: 54
1707 12:22:01.302293
1708 12:22:01.302412 Set Vref, RX VrefLevel [Byte0]: 55
1709 12:22:01.305239 [Byte1]: 55
1710 12:22:01.309370
1711 12:22:01.309459 Set Vref, RX VrefLevel [Byte0]: 56
1712 12:22:01.312840 [Byte1]: 56
1713 12:22:01.317300
1714 12:22:01.317415 Set Vref, RX VrefLevel [Byte0]: 57
1715 12:22:01.320237 [Byte1]: 57
1716 12:22:01.324678
1717 12:22:01.324764 Set Vref, RX VrefLevel [Byte0]: 58
1718 12:22:01.328234 [Byte1]: 58
1719 12:22:01.332126
1720 12:22:01.332212 Set Vref, RX VrefLevel [Byte0]: 59
1721 12:22:01.335732 [Byte1]: 59
1722 12:22:01.340147
1723 12:22:01.340230 Set Vref, RX VrefLevel [Byte0]: 60
1724 12:22:01.343122 [Byte1]: 60
1725 12:22:01.347573
1726 12:22:01.347696 Set Vref, RX VrefLevel [Byte0]: 61
1727 12:22:01.350445 [Byte1]: 61
1728 12:22:01.354856
1729 12:22:01.354984 Set Vref, RX VrefLevel [Byte0]: 62
1730 12:22:01.358421 [Byte1]: 62
1731 12:22:01.362264
1732 12:22:01.362357 Set Vref, RX VrefLevel [Byte0]: 63
1733 12:22:01.365420 [Byte1]: 63
1734 12:22:01.370077
1735 12:22:01.370170 Set Vref, RX VrefLevel [Byte0]: 64
1736 12:22:01.373188 [Byte1]: 64
1737 12:22:01.377701
1738 12:22:01.377792 Set Vref, RX VrefLevel [Byte0]: 65
1739 12:22:01.380953 [Byte1]: 65
1740 12:22:01.384902
1741 12:22:01.388087 Set Vref, RX VrefLevel [Byte0]: 66
1742 12:22:01.391537 [Byte1]: 66
1743 12:22:01.391632
1744 12:22:01.395217 Set Vref, RX VrefLevel [Byte0]: 67
1745 12:22:01.398058 [Byte1]: 67
1746 12:22:01.398165
1747 12:22:01.401667 Set Vref, RX VrefLevel [Byte0]: 68
1748 12:22:01.405207 [Byte1]: 68
1749 12:22:01.405309
1750 12:22:01.408138 Set Vref, RX VrefLevel [Byte0]: 69
1751 12:22:01.411319 [Byte1]: 69
1752 12:22:01.415451
1753 12:22:01.415555 Set Vref, RX VrefLevel [Byte0]: 70
1754 12:22:01.418681 [Byte1]: 70
1755 12:22:01.422885
1756 12:22:01.422967 Final RX Vref Byte 0 = 59 to rank0
1757 12:22:01.426579 Final RX Vref Byte 1 = 56 to rank0
1758 12:22:01.429305 Final RX Vref Byte 0 = 59 to rank1
1759 12:22:01.432983 Final RX Vref Byte 1 = 56 to rank1==
1760 12:22:01.436554 Dram Type= 6, Freq= 0, CH_1, rank 0
1761 12:22:01.439335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1762 12:22:01.442880 ==
1763 12:22:01.442969 DQS Delay:
1764 12:22:01.443037 DQS0 = 0, DQS1 = 0
1765 12:22:01.446366 DQM Delay:
1766 12:22:01.446443 DQM0 = 94, DQM1 = 89
1767 12:22:01.449713 DQ Delay:
1768 12:22:01.452763 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1769 12:22:01.456233 DQ4 =92, DQ5 =104, DQ6 =104, DQ7 =92
1770 12:22:01.456315 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1771 12:22:01.462942 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1772 12:22:01.463039
1773 12:22:01.463108
1774 12:22:01.469918 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1775 12:22:01.472847 CH1 RK0: MR19=606, MR18=2A45
1776 12:22:01.479739 CH1_RK0: MR19=0x606, MR18=0x2A45, DQSOSC=392, MR23=63, INC=96, DEC=64
1777 12:22:01.479872
1778 12:22:01.482920 ----->DramcWriteLeveling(PI) begin...
1779 12:22:01.483007 ==
1780 12:22:01.486261 Dram Type= 6, Freq= 0, CH_1, rank 1
1781 12:22:01.489733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 12:22:01.489815 ==
1783 12:22:01.493594 Write leveling (Byte 0): 25 => 25
1784 12:22:01.496516 Write leveling (Byte 1): 29 => 29
1785 12:22:01.499617 DramcWriteLeveling(PI) end<-----
1786 12:22:01.499706
1787 12:22:01.499781 ==
1788 12:22:01.503181 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 12:22:01.506482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 12:22:01.506567 ==
1791 12:22:01.509527 [Gating] SW mode calibration
1792 12:22:01.516126 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1793 12:22:01.523149 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1794 12:22:01.526147 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1795 12:22:01.529578 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1796 12:22:01.536587 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 12:22:01.539485 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 12:22:01.543132 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 12:22:01.549533 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 12:22:01.553120 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 12:22:01.556450 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 12:22:01.562880 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 12:22:01.566350 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 12:22:01.569606 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 12:22:01.576307 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 12:22:01.579575 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:22:01.582937 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:22:01.589397 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:22:01.592909 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:22:01.596454 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1811 12:22:01.599314 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1812 12:22:01.606407 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:22:01.609814 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:22:01.612722 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:22:01.619759 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:22:01.622860 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:22:01.626103 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:22:01.633009 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:22:01.636476 0 9 4 | B1->B0 | 2626 2323 | 1 0 | (1 1) (0 0)
1820 12:22:01.639329 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1821 12:22:01.646325 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 12:22:01.649351 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 12:22:01.652887 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 12:22:01.659805 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 12:22:01.662755 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 12:22:01.666078 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1827 12:22:01.672722 0 10 4 | B1->B0 | 2828 3232 | 0 1 | (0 0) (0 0)
1828 12:22:01.676451 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1829 12:22:01.679623 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:22:01.686377 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:22:01.689489 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:22:01.693237 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:22:01.696485 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:22:01.703116 0 11 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1835 12:22:01.706142 0 11 4 | B1->B0 | 3c3c 2626 | 0 0 | (0 0) (0 0)
1836 12:22:01.709744 0 11 8 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
1837 12:22:01.716195 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 12:22:01.719813 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 12:22:01.722973 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 12:22:01.729768 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 12:22:01.733351 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 12:22:01.736808 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 12:22:01.743117 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1844 12:22:01.746783 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 12:22:01.749733 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 12:22:01.753294 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 12:22:01.760220 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 12:22:01.763679 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 12:22:01.766466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 12:22:01.773065 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 12:22:01.776629 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 12:22:01.779948 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 12:22:01.786724 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:22:01.790244 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:22:01.793493 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:22:01.799778 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:22:01.803129 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:22:01.806892 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:22:01.813460 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1860 12:22:01.813542 Total UI for P1: 0, mck2ui 16
1861 12:22:01.820426 best dqsien dly found for B1: ( 0, 14, 2)
1862 12:22:01.823325 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 12:22:01.826885 Total UI for P1: 0, mck2ui 16
1864 12:22:01.829909 best dqsien dly found for B0: ( 0, 14, 4)
1865 12:22:01.833401 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1866 12:22:01.836775 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1867 12:22:01.836894
1868 12:22:01.840118 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1869 12:22:01.843777 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1870 12:22:01.846551 [Gating] SW calibration Done
1871 12:22:01.846656 ==
1872 12:22:01.850227 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 12:22:01.853595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 12:22:01.853675 ==
1875 12:22:01.856909 RX Vref Scan: 0
1876 12:22:01.857014
1877 12:22:01.857124 RX Vref 0 -> 0, step: 1
1878 12:22:01.860007
1879 12:22:01.860121 RX Delay -130 -> 252, step: 16
1880 12:22:01.866883 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1881 12:22:01.870208 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1882 12:22:01.873745 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1883 12:22:01.876624 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1884 12:22:01.880137 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1885 12:22:01.883564 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1886 12:22:01.890164 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1887 12:22:01.893333 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1888 12:22:01.896931 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1889 12:22:01.900344 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1890 12:22:01.903440 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1891 12:22:01.910132 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1892 12:22:01.913699 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1893 12:22:01.916679 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1894 12:22:01.920191 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1895 12:22:01.923468 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1896 12:22:01.926876 ==
1897 12:22:01.926953 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 12:22:01.933730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 12:22:01.933811 ==
1900 12:22:01.933875 DQS Delay:
1901 12:22:01.937238 DQS0 = 0, DQS1 = 0
1902 12:22:01.937312 DQM Delay:
1903 12:22:01.940594 DQM0 = 95, DQM1 = 91
1904 12:22:01.940666 DQ Delay:
1905 12:22:01.944081 DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =93
1906 12:22:01.947431 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =101
1907 12:22:01.950325 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1908 12:22:01.953752 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1909 12:22:01.953844
1910 12:22:01.953940
1911 12:22:01.954000 ==
1912 12:22:01.957533 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 12:22:01.960865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 12:22:01.960963 ==
1915 12:22:01.961040
1916 12:22:01.961097
1917 12:22:01.963761 TX Vref Scan disable
1918 12:22:01.967410 == TX Byte 0 ==
1919 12:22:01.971053 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1920 12:22:01.973851 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1921 12:22:01.977180 == TX Byte 1 ==
1922 12:22:01.980597 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1923 12:22:01.984192 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1924 12:22:01.984315 ==
1925 12:22:01.987172 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 12:22:01.990822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 12:22:01.993864 ==
1928 12:22:02.005686 TX Vref=22, minBit 1, minWin=26, winSum=440
1929 12:22:02.008840 TX Vref=24, minBit 1, minWin=26, winSum=442
1930 12:22:02.012232 TX Vref=26, minBit 0, minWin=27, winSum=447
1931 12:22:02.015421 TX Vref=28, minBit 0, minWin=27, winSum=448
1932 12:22:02.018799 TX Vref=30, minBit 0, minWin=27, winSum=452
1933 12:22:02.022563 TX Vref=32, minBit 0, minWin=27, winSum=449
1934 12:22:02.029223 [TxChooseVref] Worse bit 0, Min win 27, Win sum 452, Final Vref 30
1935 12:22:02.029306
1936 12:22:02.032241 Final TX Range 1 Vref 30
1937 12:22:02.032331
1938 12:22:02.032429 ==
1939 12:22:02.035699 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 12:22:02.038939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 12:22:02.039024 ==
1942 12:22:02.039089
1943 12:22:02.042329
1944 12:22:02.042445 TX Vref Scan disable
1945 12:22:02.045426 == TX Byte 0 ==
1946 12:22:02.048762 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1947 12:22:02.052212 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1948 12:22:02.055555 == TX Byte 1 ==
1949 12:22:02.059139 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1950 12:22:02.062073 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1951 12:22:02.065591
1952 12:22:02.065666 [DATLAT]
1953 12:22:02.065746 Freq=800, CH1 RK1
1954 12:22:02.065811
1955 12:22:02.069135 DATLAT Default: 0xa
1956 12:22:02.069253 0, 0xFFFF, sum = 0
1957 12:22:02.072985 1, 0xFFFF, sum = 0
1958 12:22:02.073090 2, 0xFFFF, sum = 0
1959 12:22:02.075893 3, 0xFFFF, sum = 0
1960 12:22:02.075968 4, 0xFFFF, sum = 0
1961 12:22:02.079242 5, 0xFFFF, sum = 0
1962 12:22:02.079312 6, 0xFFFF, sum = 0
1963 12:22:02.082544 7, 0xFFFF, sum = 0
1964 12:22:02.082660 8, 0xFFFF, sum = 0
1965 12:22:02.085890 9, 0x0, sum = 1
1966 12:22:02.086012 10, 0x0, sum = 2
1967 12:22:02.089235 11, 0x0, sum = 3
1968 12:22:02.089334 12, 0x0, sum = 4
1969 12:22:02.092783 best_step = 10
1970 12:22:02.092917
1971 12:22:02.093010 ==
1972 12:22:02.095922 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 12:22:02.099428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 12:22:02.099510 ==
1975 12:22:02.102500 RX Vref Scan: 0
1976 12:22:02.102597
1977 12:22:02.102689 RX Vref 0 -> 0, step: 1
1978 12:22:02.102779
1979 12:22:02.105866 RX Delay -79 -> 252, step: 8
1980 12:22:02.112520 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1981 12:22:02.115849 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1982 12:22:02.119620 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1983 12:22:02.122978 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1984 12:22:02.126538 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1985 12:22:02.129691 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1986 12:22:02.132966 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1987 12:22:02.139565 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1988 12:22:02.142588 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1989 12:22:02.145979 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1990 12:22:02.149219 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1991 12:22:02.152610 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1992 12:22:02.159268 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1993 12:22:02.163126 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1994 12:22:02.165974 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1995 12:22:02.169636 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1996 12:22:02.169737 ==
1997 12:22:02.173060 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 12:22:02.179776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 12:22:02.179856 ==
2000 12:22:02.179920 DQS Delay:
2001 12:22:02.179985 DQS0 = 0, DQS1 = 0
2002 12:22:02.182662 DQM Delay:
2003 12:22:02.182732 DQM0 = 97, DQM1 = 90
2004 12:22:02.186098 DQ Delay:
2005 12:22:02.189422 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2006 12:22:02.192916 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2007 12:22:02.192992 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
2008 12:22:02.199515 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2009 12:22:02.199630
2010 12:22:02.199703
2011 12:22:02.206593 [DQSOSCAuto] RK1, (LSB)MR18= 0x4812, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2012 12:22:02.209412 CH1 RK1: MR19=606, MR18=4812
2013 12:22:02.216582 CH1_RK1: MR19=0x606, MR18=0x4812, DQSOSC=391, MR23=63, INC=96, DEC=64
2014 12:22:02.219463 [RxdqsGatingPostProcess] freq 800
2015 12:22:02.222854 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2016 12:22:02.225924 Pre-setting of DQS Precalculation
2017 12:22:02.233096 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2018 12:22:02.239833 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2019 12:22:02.246269 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2020 12:22:02.246385
2021 12:22:02.246482
2022 12:22:02.249367 [Calibration Summary] 1600 Mbps
2023 12:22:02.249445 CH 0, Rank 0
2024 12:22:02.253043 SW Impedance : PASS
2025 12:22:02.256429 DUTY Scan : NO K
2026 12:22:02.256532 ZQ Calibration : PASS
2027 12:22:02.259325 Jitter Meter : NO K
2028 12:22:02.263161 CBT Training : PASS
2029 12:22:02.263265 Write leveling : PASS
2030 12:22:02.266481 RX DQS gating : PASS
2031 12:22:02.266591 RX DQ/DQS(RDDQC) : PASS
2032 12:22:02.269517 TX DQ/DQS : PASS
2033 12:22:02.272712 RX DATLAT : PASS
2034 12:22:02.272813 RX DQ/DQS(Engine): PASS
2035 12:22:02.276509 TX OE : NO K
2036 12:22:02.276612 All Pass.
2037 12:22:02.276708
2038 12:22:02.279732 CH 0, Rank 1
2039 12:22:02.279807 SW Impedance : PASS
2040 12:22:02.282767 DUTY Scan : NO K
2041 12:22:02.286451 ZQ Calibration : PASS
2042 12:22:02.286523 Jitter Meter : NO K
2043 12:22:02.289788 CBT Training : PASS
2044 12:22:02.292695 Write leveling : PASS
2045 12:22:02.292768 RX DQS gating : PASS
2046 12:22:02.296143 RX DQ/DQS(RDDQC) : PASS
2047 12:22:02.299793 TX DQ/DQS : PASS
2048 12:22:02.299875 RX DATLAT : PASS
2049 12:22:02.303236 RX DQ/DQS(Engine): PASS
2050 12:22:02.303337 TX OE : NO K
2051 12:22:02.306287 All Pass.
2052 12:22:02.306386
2053 12:22:02.306489 CH 1, Rank 0
2054 12:22:02.309933 SW Impedance : PASS
2055 12:22:02.310038 DUTY Scan : NO K
2056 12:22:02.313204 ZQ Calibration : PASS
2057 12:22:02.316252 Jitter Meter : NO K
2058 12:22:02.316332 CBT Training : PASS
2059 12:22:02.319798 Write leveling : PASS
2060 12:22:02.323404 RX DQS gating : PASS
2061 12:22:02.323478 RX DQ/DQS(RDDQC) : PASS
2062 12:22:02.326320 TX DQ/DQS : PASS
2063 12:22:02.329686 RX DATLAT : PASS
2064 12:22:02.329766 RX DQ/DQS(Engine): PASS
2065 12:22:02.333300 TX OE : NO K
2066 12:22:02.333378 All Pass.
2067 12:22:02.333443
2068 12:22:02.336185 CH 1, Rank 1
2069 12:22:02.336256 SW Impedance : PASS
2070 12:22:02.339772 DUTY Scan : NO K
2071 12:22:02.343399 ZQ Calibration : PASS
2072 12:22:02.343500 Jitter Meter : NO K
2073 12:22:02.346289 CBT Training : PASS
2074 12:22:02.346390 Write leveling : PASS
2075 12:22:02.349834 RX DQS gating : PASS
2076 12:22:02.353046 RX DQ/DQS(RDDQC) : PASS
2077 12:22:02.353119 TX DQ/DQS : PASS
2078 12:22:02.356507 RX DATLAT : PASS
2079 12:22:02.360024 RX DQ/DQS(Engine): PASS
2080 12:22:02.360100 TX OE : NO K
2081 12:22:02.363406 All Pass.
2082 12:22:02.363485
2083 12:22:02.363549 DramC Write-DBI off
2084 12:22:02.366255 PER_BANK_REFRESH: Hybrid Mode
2085 12:22:02.366338 TX_TRACKING: ON
2086 12:22:02.370260 [GetDramInforAfterCalByMRR] Vendor 6.
2087 12:22:02.376564 [GetDramInforAfterCalByMRR] Revision 606.
2088 12:22:02.379742 [GetDramInforAfterCalByMRR] Revision 2 0.
2089 12:22:02.379822 MR0 0x3b3b
2090 12:22:02.379886 MR8 0x5151
2091 12:22:02.382868 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2092 12:22:02.386628
2093 12:22:02.386703 MR0 0x3b3b
2094 12:22:02.386767 MR8 0x5151
2095 12:22:02.390012 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2096 12:22:02.390087
2097 12:22:02.399984 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2098 12:22:02.403141 [FAST_K] Save calibration result to emmc
2099 12:22:02.406647 [FAST_K] Save calibration result to emmc
2100 12:22:02.409638 dram_init: config_dvfs: 1
2101 12:22:02.413316 dramc_set_vcore_voltage set vcore to 662500
2102 12:22:02.416277 Read voltage for 1200, 2
2103 12:22:02.416354 Vio18 = 0
2104 12:22:02.416421 Vcore = 662500
2105 12:22:02.420002 Vdram = 0
2106 12:22:02.420075 Vddq = 0
2107 12:22:02.420141 Vmddr = 0
2108 12:22:02.426358 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2109 12:22:02.429735 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2110 12:22:02.433428 MEM_TYPE=3, freq_sel=15
2111 12:22:02.437158 sv_algorithm_assistance_LP4_1600
2112 12:22:02.439806 ============ PULL DRAM RESETB DOWN ============
2113 12:22:02.443536 ========== PULL DRAM RESETB DOWN end =========
2114 12:22:02.449938 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2115 12:22:02.453394 ===================================
2116 12:22:02.453472 LPDDR4 DRAM CONFIGURATION
2117 12:22:02.456931 ===================================
2118 12:22:02.459898 EX_ROW_EN[0] = 0x0
2119 12:22:02.463352 EX_ROW_EN[1] = 0x0
2120 12:22:02.463428 LP4Y_EN = 0x0
2121 12:22:02.466606 WORK_FSP = 0x0
2122 12:22:02.466682 WL = 0x4
2123 12:22:02.469827 RL = 0x4
2124 12:22:02.469902 BL = 0x2
2125 12:22:02.473117 RPST = 0x0
2126 12:22:02.473193 RD_PRE = 0x0
2127 12:22:02.476483 WR_PRE = 0x1
2128 12:22:02.476595 WR_PST = 0x0
2129 12:22:02.480160 DBI_WR = 0x0
2130 12:22:02.480256 DBI_RD = 0x0
2131 12:22:02.483561 OTF = 0x1
2132 12:22:02.486996 ===================================
2133 12:22:02.490534 ===================================
2134 12:22:02.490639 ANA top config
2135 12:22:02.493682 ===================================
2136 12:22:02.497071 DLL_ASYNC_EN = 0
2137 12:22:02.499815 ALL_SLAVE_EN = 0
2138 12:22:02.499895 NEW_RANK_MODE = 1
2139 12:22:02.503237 DLL_IDLE_MODE = 1
2140 12:22:02.506978 LP45_APHY_COMB_EN = 1
2141 12:22:02.510302 TX_ODT_DIS = 1
2142 12:22:02.510403 NEW_8X_MODE = 1
2143 12:22:02.513830 ===================================
2144 12:22:02.516662 ===================================
2145 12:22:02.520159 data_rate = 2400
2146 12:22:02.523159 CKR = 1
2147 12:22:02.526690 DQ_P2S_RATIO = 8
2148 12:22:02.530352 ===================================
2149 12:22:02.533804 CA_P2S_RATIO = 8
2150 12:22:02.536637 DQ_CA_OPEN = 0
2151 12:22:02.536716 DQ_SEMI_OPEN = 0
2152 12:22:02.540299 CA_SEMI_OPEN = 0
2153 12:22:02.543611 CA_FULL_RATE = 0
2154 12:22:02.547176 DQ_CKDIV4_EN = 0
2155 12:22:02.550178 CA_CKDIV4_EN = 0
2156 12:22:02.553767 CA_PREDIV_EN = 0
2157 12:22:02.553843 PH8_DLY = 17
2158 12:22:02.557219 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2159 12:22:02.559993 DQ_AAMCK_DIV = 4
2160 12:22:02.563489 CA_AAMCK_DIV = 4
2161 12:22:02.567145 CA_ADMCK_DIV = 4
2162 12:22:02.570155 DQ_TRACK_CA_EN = 0
2163 12:22:02.570226 CA_PICK = 1200
2164 12:22:02.573371 CA_MCKIO = 1200
2165 12:22:02.576777 MCKIO_SEMI = 0
2166 12:22:02.580363 PLL_FREQ = 2366
2167 12:22:02.583794 DQ_UI_PI_RATIO = 32
2168 12:22:02.586901 CA_UI_PI_RATIO = 0
2169 12:22:02.590121 ===================================
2170 12:22:02.593835 ===================================
2171 12:22:02.593909 memory_type:LPDDR4
2172 12:22:02.596733 GP_NUM : 10
2173 12:22:02.600692 SRAM_EN : 1
2174 12:22:02.600798 MD32_EN : 0
2175 12:22:02.603480 ===================================
2176 12:22:02.606780 [ANA_INIT] >>>>>>>>>>>>>>
2177 12:22:02.610435 <<<<<< [CONFIGURE PHASE]: ANA_TX
2178 12:22:02.613824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2179 12:22:02.617415 ===================================
2180 12:22:02.620287 data_rate = 2400,PCW = 0X5b00
2181 12:22:02.623493 ===================================
2182 12:22:02.627179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2183 12:22:02.630330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2184 12:22:02.637153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2185 12:22:02.640155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2186 12:22:02.643646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2187 12:22:02.647124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2188 12:22:02.650682 [ANA_INIT] flow start
2189 12:22:02.653693 [ANA_INIT] PLL >>>>>>>>
2190 12:22:02.653800 [ANA_INIT] PLL <<<<<<<<
2191 12:22:02.657323 [ANA_INIT] MIDPI >>>>>>>>
2192 12:22:02.660207 [ANA_INIT] MIDPI <<<<<<<<
2193 12:22:02.660280 [ANA_INIT] DLL >>>>>>>>
2194 12:22:02.663614 [ANA_INIT] DLL <<<<<<<<
2195 12:22:02.667233 [ANA_INIT] flow end
2196 12:22:02.670323 ============ LP4 DIFF to SE enter ============
2197 12:22:02.673952 ============ LP4 DIFF to SE exit ============
2198 12:22:02.677275 [ANA_INIT] <<<<<<<<<<<<<
2199 12:22:02.680256 [Flow] Enable top DCM control >>>>>
2200 12:22:02.683819 [Flow] Enable top DCM control <<<<<
2201 12:22:02.687332 Enable DLL master slave shuffle
2202 12:22:02.690188 ==============================================================
2203 12:22:02.693623 Gating Mode config
2204 12:22:02.700568 ==============================================================
2205 12:22:02.700655 Config description:
2206 12:22:02.710592 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2207 12:22:02.717319 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2208 12:22:02.720256 SELPH_MODE 0: By rank 1: By Phase
2209 12:22:02.727098 ==============================================================
2210 12:22:02.730573 GAT_TRACK_EN = 1
2211 12:22:02.734229 RX_GATING_MODE = 2
2212 12:22:02.736951 RX_GATING_TRACK_MODE = 2
2213 12:22:02.740855 SELPH_MODE = 1
2214 12:22:02.743604 PICG_EARLY_EN = 1
2215 12:22:02.747118 VALID_LAT_VALUE = 1
2216 12:22:02.750710 ==============================================================
2217 12:22:02.753648 Enter into Gating configuration >>>>
2218 12:22:02.757314 Exit from Gating configuration <<<<
2219 12:22:02.760190 Enter into DVFS_PRE_config >>>>>
2220 12:22:02.770306 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2221 12:22:02.773633 Exit from DVFS_PRE_config <<<<<
2222 12:22:02.777168 Enter into PICG configuration >>>>
2223 12:22:02.780845 Exit from PICG configuration <<<<
2224 12:22:02.783901 [RX_INPUT] configuration >>>>>
2225 12:22:02.787881 [RX_INPUT] configuration <<<<<
2226 12:22:02.794330 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2227 12:22:02.798011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2228 12:22:02.804162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2229 12:22:02.810940 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2230 12:22:02.817256 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 12:22:02.821039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 12:22:02.827319 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2233 12:22:02.830850 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2234 12:22:02.833867 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2235 12:22:02.837196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2236 12:22:02.844182 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2237 12:22:02.847392 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2238 12:22:02.850759 ===================================
2239 12:22:02.854352 LPDDR4 DRAM CONFIGURATION
2240 12:22:02.857370 ===================================
2241 12:22:02.857451 EX_ROW_EN[0] = 0x0
2242 12:22:02.860885 EX_ROW_EN[1] = 0x0
2243 12:22:02.860988 LP4Y_EN = 0x0
2244 12:22:02.864331 WORK_FSP = 0x0
2245 12:22:02.864426 WL = 0x4
2246 12:22:02.867326 RL = 0x4
2247 12:22:02.867430 BL = 0x2
2248 12:22:02.870767 RPST = 0x0
2249 12:22:02.870878 RD_PRE = 0x0
2250 12:22:02.874348 WR_PRE = 0x1
2251 12:22:02.874437 WR_PST = 0x0
2252 12:22:02.877320 DBI_WR = 0x0
2253 12:22:02.877393 DBI_RD = 0x0
2254 12:22:02.880757 OTF = 0x1
2255 12:22:02.884253 ===================================
2256 12:22:02.887528 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2257 12:22:02.890560 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2258 12:22:02.897720 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 12:22:02.901310 ===================================
2260 12:22:02.901393 LPDDR4 DRAM CONFIGURATION
2261 12:22:02.904001 ===================================
2262 12:22:02.907545 EX_ROW_EN[0] = 0x10
2263 12:22:02.911138 EX_ROW_EN[1] = 0x0
2264 12:22:02.911243 LP4Y_EN = 0x0
2265 12:22:02.914494 WORK_FSP = 0x0
2266 12:22:02.914568 WL = 0x4
2267 12:22:02.918187 RL = 0x4
2268 12:22:02.918268 BL = 0x2
2269 12:22:02.920961 RPST = 0x0
2270 12:22:02.921033 RD_PRE = 0x0
2271 12:22:02.924440 WR_PRE = 0x1
2272 12:22:02.924512 WR_PST = 0x0
2273 12:22:02.928098 DBI_WR = 0x0
2274 12:22:02.928176 DBI_RD = 0x0
2275 12:22:02.931159 OTF = 0x1
2276 12:22:02.934666 ===================================
2277 12:22:02.941350 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2278 12:22:02.941435 ==
2279 12:22:02.944634 Dram Type= 6, Freq= 0, CH_0, rank 0
2280 12:22:02.947748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2281 12:22:02.947829 ==
2282 12:22:02.951134 [Duty_Offset_Calibration]
2283 12:22:02.951236 B0:2 B1:1 CA:1
2284 12:22:02.951331
2285 12:22:02.954336 [DutyScan_Calibration_Flow] k_type=0
2286 12:22:02.964284
2287 12:22:02.964392 ==CLK 0==
2288 12:22:02.967564 Final CLK duty delay cell = 0
2289 12:22:02.971258 [0] MAX Duty = 5218%(X100), DQS PI = 24
2290 12:22:02.974153 [0] MIN Duty = 4875%(X100), DQS PI = 0
2291 12:22:02.974230 [0] AVG Duty = 5046%(X100)
2292 12:22:02.977328
2293 12:22:02.981023 CH0 CLK Duty spec in!! Max-Min= 343%
2294 12:22:02.984470 [DutyScan_Calibration_Flow] ====Done====
2295 12:22:02.984547
2296 12:22:02.987376 [DutyScan_Calibration_Flow] k_type=1
2297 12:22:03.001933
2298 12:22:03.002020 ==DQS 0 ==
2299 12:22:03.005768 Final DQS duty delay cell = -4
2300 12:22:03.008853 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2301 12:22:03.012206 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2302 12:22:03.015279 [-4] AVG Duty = 4953%(X100)
2303 12:22:03.015382
2304 12:22:03.015478 ==DQS 1 ==
2305 12:22:03.018643 Final DQS duty delay cell = -4
2306 12:22:03.022214 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2307 12:22:03.025995 [-4] MIN Duty = 4844%(X100), DQS PI = 30
2308 12:22:03.028682 [-4] AVG Duty = 4906%(X100)
2309 12:22:03.028758
2310 12:22:03.032504 CH0 DQS 0 Duty spec in!! Max-Min= 405%
2311 12:22:03.032580
2312 12:22:03.035343 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2313 12:22:03.038859 [DutyScan_Calibration_Flow] ====Done====
2314 12:22:03.038933
2315 12:22:03.041958 [DutyScan_Calibration_Flow] k_type=3
2316 12:22:03.059250
2317 12:22:03.059360 ==DQM 0 ==
2318 12:22:03.062626 Final DQM duty delay cell = 0
2319 12:22:03.065926 [0] MAX Duty = 5187%(X100), DQS PI = 26
2320 12:22:03.069306 [0] MIN Duty = 4938%(X100), DQS PI = 0
2321 12:22:03.069419 [0] AVG Duty = 5062%(X100)
2322 12:22:03.072838
2323 12:22:03.072916 ==DQM 1 ==
2324 12:22:03.075914 Final DQM duty delay cell = 0
2325 12:22:03.079119 [0] MAX Duty = 5125%(X100), DQS PI = 58
2326 12:22:03.083143 [0] MIN Duty = 5031%(X100), DQS PI = 36
2327 12:22:03.083219 [0] AVG Duty = 5078%(X100)
2328 12:22:03.083281
2329 12:22:03.089445 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2330 12:22:03.089527
2331 12:22:03.092865 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2332 12:22:03.096247 [DutyScan_Calibration_Flow] ====Done====
2333 12:22:03.096322
2334 12:22:03.099095 [DutyScan_Calibration_Flow] k_type=2
2335 12:22:03.115611
2336 12:22:03.115700 ==DQ 0 ==
2337 12:22:03.119185 Final DQ duty delay cell = 0
2338 12:22:03.122241 [0] MAX Duty = 5031%(X100), DQS PI = 24
2339 12:22:03.125551 [0] MIN Duty = 4875%(X100), DQS PI = 62
2340 12:22:03.125630 [0] AVG Duty = 4953%(X100)
2341 12:22:03.125695
2342 12:22:03.128745 ==DQ 1 ==
2343 12:22:03.132075 Final DQ duty delay cell = 0
2344 12:22:03.135471 [0] MAX Duty = 5093%(X100), DQS PI = 10
2345 12:22:03.138795 [0] MIN Duty = 4938%(X100), DQS PI = 36
2346 12:22:03.138874 [0] AVG Duty = 5015%(X100)
2347 12:22:03.138960
2348 12:22:03.142189 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2349 12:22:03.142260
2350 12:22:03.145733 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2351 12:22:03.152745 [DutyScan_Calibration_Flow] ====Done====
2352 12:22:03.152861 ==
2353 12:22:03.155609 Dram Type= 6, Freq= 0, CH_1, rank 0
2354 12:22:03.159355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 12:22:03.159469 ==
2356 12:22:03.162643 [Duty_Offset_Calibration]
2357 12:22:03.162747 B0:1 B1:0 CA:0
2358 12:22:03.162816
2359 12:22:03.165518 [DutyScan_Calibration_Flow] k_type=0
2360 12:22:03.174839
2361 12:22:03.174938 ==CLK 0==
2362 12:22:03.178096 Final CLK duty delay cell = -4
2363 12:22:03.181778 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2364 12:22:03.184725 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2365 12:22:03.188264 [-4] AVG Duty = 4953%(X100)
2366 12:22:03.188344
2367 12:22:03.191366 CH1 CLK Duty spec in!! Max-Min= 93%
2368 12:22:03.194929 [DutyScan_Calibration_Flow] ====Done====
2369 12:22:03.195040
2370 12:22:03.197991 [DutyScan_Calibration_Flow] k_type=1
2371 12:22:03.214442
2372 12:22:03.214566 ==DQS 0 ==
2373 12:22:03.217502 Final DQS duty delay cell = 0
2374 12:22:03.221074 [0] MAX Duty = 5062%(X100), DQS PI = 56
2375 12:22:03.224706 [0] MIN Duty = 4875%(X100), DQS PI = 32
2376 12:22:03.224786 [0] AVG Duty = 4968%(X100)
2377 12:22:03.227558
2378 12:22:03.227662 ==DQS 1 ==
2379 12:22:03.230993 Final DQS duty delay cell = 0
2380 12:22:03.234650 [0] MAX Duty = 5187%(X100), DQS PI = 52
2381 12:22:03.237551 [0] MIN Duty = 4938%(X100), DQS PI = 44
2382 12:22:03.241241 [0] AVG Duty = 5062%(X100)
2383 12:22:03.241318
2384 12:22:03.244976 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2385 12:22:03.245067
2386 12:22:03.247828 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2387 12:22:03.251277 [DutyScan_Calibration_Flow] ====Done====
2388 12:22:03.251380
2389 12:22:03.254215 [DutyScan_Calibration_Flow] k_type=3
2390 12:22:03.271018
2391 12:22:03.271135 ==DQM 0 ==
2392 12:22:03.274548 Final DQM duty delay cell = 0
2393 12:22:03.278022 [0] MAX Duty = 5156%(X100), DQS PI = 2
2394 12:22:03.280982 [0] MIN Duty = 5031%(X100), DQS PI = 28
2395 12:22:03.281061 [0] AVG Duty = 5093%(X100)
2396 12:22:03.284539
2397 12:22:03.284642 ==DQM 1 ==
2398 12:22:03.287579 Final DQM duty delay cell = 0
2399 12:22:03.291428 [0] MAX Duty = 5031%(X100), DQS PI = 10
2400 12:22:03.294532 [0] MIN Duty = 4907%(X100), DQS PI = 2
2401 12:22:03.294634 [0] AVG Duty = 4969%(X100)
2402 12:22:03.294731
2403 12:22:03.297860 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2404 12:22:03.301510
2405 12:22:03.304590 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2406 12:22:03.307703 [DutyScan_Calibration_Flow] ====Done====
2407 12:22:03.307809
2408 12:22:03.311477 [DutyScan_Calibration_Flow] k_type=2
2409 12:22:03.326505
2410 12:22:03.326593 ==DQ 0 ==
2411 12:22:03.330072 Final DQ duty delay cell = -4
2412 12:22:03.333274 [-4] MAX Duty = 5094%(X100), DQS PI = 26
2413 12:22:03.336724 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2414 12:22:03.340283 [-4] AVG Duty = 5016%(X100)
2415 12:22:03.340365
2416 12:22:03.340429 ==DQ 1 ==
2417 12:22:03.343351 Final DQ duty delay cell = 0
2418 12:22:03.346778 [0] MAX Duty = 5093%(X100), DQS PI = 10
2419 12:22:03.349747 [0] MIN Duty = 4969%(X100), DQS PI = 0
2420 12:22:03.349826 [0] AVG Duty = 5031%(X100)
2421 12:22:03.353407
2422 12:22:03.356817 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2423 12:22:03.356909
2424 12:22:03.360278 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2425 12:22:03.363287 [DutyScan_Calibration_Flow] ====Done====
2426 12:22:03.366823 nWR fixed to 30
2427 12:22:03.370195 [ModeRegInit_LP4] CH0 RK0
2428 12:22:03.370283 [ModeRegInit_LP4] CH0 RK1
2429 12:22:03.373197 [ModeRegInit_LP4] CH1 RK0
2430 12:22:03.376511 [ModeRegInit_LP4] CH1 RK1
2431 12:22:03.376612 match AC timing 7
2432 12:22:03.383577 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2433 12:22:03.386468 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2434 12:22:03.390133 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2435 12:22:03.396480 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2436 12:22:03.399723 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2437 12:22:03.399834 ==
2438 12:22:03.403044 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 12:22:03.406481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2440 12:22:03.406618 ==
2441 12:22:03.413389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2442 12:22:03.419923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2443 12:22:03.427433 [CA 0] Center 39 (8~70) winsize 63
2444 12:22:03.430599 [CA 1] Center 39 (8~70) winsize 63
2445 12:22:03.433772 [CA 2] Center 35 (5~66) winsize 62
2446 12:22:03.436817 [CA 3] Center 34 (4~65) winsize 62
2447 12:22:03.440161 [CA 4] Center 33 (3~64) winsize 62
2448 12:22:03.443566 [CA 5] Center 32 (3~62) winsize 60
2449 12:22:03.443761
2450 12:22:03.447217 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2451 12:22:03.447321
2452 12:22:03.450234 [CATrainingPosCal] consider 1 rank data
2453 12:22:03.453589 u2DelayCellTimex100 = 270/100 ps
2454 12:22:03.456693 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2455 12:22:03.460104 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2456 12:22:03.467123 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2457 12:22:03.470255 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2458 12:22:03.473535 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2459 12:22:03.476943 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2460 12:22:03.477021
2461 12:22:03.480287 CA PerBit enable=1, Macro0, CA PI delay=32
2462 12:22:03.480362
2463 12:22:03.483896 [CBTSetCACLKResult] CA Dly = 32
2464 12:22:03.483976 CS Dly: 6 (0~37)
2465 12:22:03.486705 ==
2466 12:22:03.486804 Dram Type= 6, Freq= 0, CH_0, rank 1
2467 12:22:03.493983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 12:22:03.494059 ==
2469 12:22:03.496962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 12:22:03.503467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 12:22:03.512468 [CA 0] Center 38 (8~69) winsize 62
2472 12:22:03.515843 [CA 1] Center 38 (8~69) winsize 62
2473 12:22:03.519421 [CA 2] Center 35 (4~66) winsize 63
2474 12:22:03.523078 [CA 3] Center 34 (4~65) winsize 62
2475 12:22:03.526123 [CA 4] Center 33 (3~64) winsize 62
2476 12:22:03.529350 [CA 5] Center 32 (3~62) winsize 60
2477 12:22:03.529451
2478 12:22:03.532686 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2479 12:22:03.532766
2480 12:22:03.536216 [CATrainingPosCal] consider 2 rank data
2481 12:22:03.539480 u2DelayCellTimex100 = 270/100 ps
2482 12:22:03.542671 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2483 12:22:03.546130 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2484 12:22:03.552920 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2485 12:22:03.555873 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2486 12:22:03.559465 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2487 12:22:03.563107 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2488 12:22:03.563214
2489 12:22:03.565954 CA PerBit enable=1, Macro0, CA PI delay=32
2490 12:22:03.566036
2491 12:22:03.569556 [CBTSetCACLKResult] CA Dly = 32
2492 12:22:03.569669 CS Dly: 6 (0~38)
2493 12:22:03.569755
2494 12:22:03.572402 ----->DramcWriteLeveling(PI) begin...
2495 12:22:03.575952 ==
2496 12:22:03.579462 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 12:22:03.582471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 12:22:03.582552 ==
2499 12:22:03.585919 Write leveling (Byte 0): 35 => 35
2500 12:22:03.589436 Write leveling (Byte 1): 30 => 30
2501 12:22:03.592801 DramcWriteLeveling(PI) end<-----
2502 12:22:03.592908
2503 12:22:03.593001 ==
2504 12:22:03.595894 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 12:22:03.599450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 12:22:03.599548 ==
2507 12:22:03.602503 [Gating] SW mode calibration
2508 12:22:03.609359 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2509 12:22:03.612848 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2510 12:22:03.619434 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2511 12:22:03.622894 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2512 12:22:03.626567 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 12:22:03.632576 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 12:22:03.636491 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 12:22:03.639696 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 12:22:03.646086 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2517 12:22:03.649499 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
2518 12:22:03.652842 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2519 12:22:03.659856 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 12:22:03.663055 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 12:22:03.666585 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 12:22:03.673025 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 12:22:03.676510 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 12:22:03.679468 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2525 12:22:03.682847 1 0 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2526 12:22:03.689995 1 1 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
2527 12:22:03.692736 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 12:22:03.696189 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 12:22:03.703345 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 12:22:03.706244 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 12:22:03.709497 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 12:22:03.716474 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 12:22:03.719495 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2534 12:22:03.722961 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2535 12:22:03.729857 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 12:22:03.732853 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 12:22:03.736464 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 12:22:03.742949 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 12:22:03.746459 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 12:22:03.749698 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 12:22:03.756337 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 12:22:03.760185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 12:22:03.763050 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 12:22:03.766473 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:22:03.773057 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:22:03.776513 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:22:03.779810 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:22:03.786611 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2549 12:22:03.789683 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2550 12:22:03.793311 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2551 12:22:03.796346 Total UI for P1: 0, mck2ui 16
2552 12:22:03.799681 best dqsien dly found for B0: ( 1, 3, 26)
2553 12:22:03.806980 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 12:22:03.807078 Total UI for P1: 0, mck2ui 16
2555 12:22:03.813565 best dqsien dly found for B1: ( 1, 3, 30)
2556 12:22:03.816537 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2557 12:22:03.819963 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2558 12:22:03.820081
2559 12:22:03.823096 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2560 12:22:03.826790 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2561 12:22:03.829675 [Gating] SW calibration Done
2562 12:22:03.829786 ==
2563 12:22:03.833295 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 12:22:03.836385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 12:22:03.836462 ==
2566 12:22:03.839805 RX Vref Scan: 0
2567 12:22:03.839890
2568 12:22:03.839976 RX Vref 0 -> 0, step: 1
2569 12:22:03.840060
2570 12:22:03.843367 RX Delay -40 -> 252, step: 8
2571 12:22:03.846472 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2572 12:22:03.852868 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2573 12:22:03.856495 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2574 12:22:03.859689 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2575 12:22:03.863030 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2576 12:22:03.866628 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2577 12:22:03.873425 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2578 12:22:03.876393 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2579 12:22:03.879682 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2580 12:22:03.883224 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2581 12:22:03.886598 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2582 12:22:03.889836 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2583 12:22:03.896758 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2584 12:22:03.899777 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2585 12:22:03.903308 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2586 12:22:03.906613 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2587 12:22:03.906697 ==
2588 12:22:03.910245 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 12:22:03.916701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 12:22:03.916781 ==
2591 12:22:03.916851 DQS Delay:
2592 12:22:03.919700 DQS0 = 0, DQS1 = 0
2593 12:22:03.919780 DQM Delay:
2594 12:22:03.919846 DQM0 = 121, DQM1 = 113
2595 12:22:03.923673 DQ Delay:
2596 12:22:03.926725 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2597 12:22:03.930219 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2598 12:22:03.933384 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2599 12:22:03.936724 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2600 12:22:03.936806
2601 12:22:03.936869
2602 12:22:03.936929 ==
2603 12:22:03.939997 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 12:22:03.943555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 12:22:03.943650 ==
2606 12:22:03.946647
2607 12:22:03.946716
2608 12:22:03.946780 TX Vref Scan disable
2609 12:22:03.950205 == TX Byte 0 ==
2610 12:22:03.953747 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2611 12:22:03.956776 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2612 12:22:03.960298 == TX Byte 1 ==
2613 12:22:03.963304 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2614 12:22:03.966655 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2615 12:22:03.966762 ==
2616 12:22:03.970225 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 12:22:03.976792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 12:22:03.976872 ==
2619 12:22:03.987842 TX Vref=22, minBit 0, minWin=24, winSum=406
2620 12:22:03.991234 TX Vref=24, minBit 0, minWin=24, winSum=412
2621 12:22:03.994691 TX Vref=26, minBit 7, minWin=25, winSum=417
2622 12:22:03.997905 TX Vref=28, minBit 0, minWin=25, winSum=419
2623 12:22:04.000947 TX Vref=30, minBit 14, minWin=25, winSum=422
2624 12:22:04.004509 TX Vref=32, minBit 3, minWin=25, winSum=422
2625 12:22:04.011673 [TxChooseVref] Worse bit 14, Min win 25, Win sum 422, Final Vref 30
2626 12:22:04.011784
2627 12:22:04.014616 Final TX Range 1 Vref 30
2628 12:22:04.014730
2629 12:22:04.014826 ==
2630 12:22:04.018123 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 12:22:04.021531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 12:22:04.021617 ==
2633 12:22:04.021684
2634 12:22:04.024533
2635 12:22:04.024618 TX Vref Scan disable
2636 12:22:04.027949 == TX Byte 0 ==
2637 12:22:04.031473 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2638 12:22:04.035163 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2639 12:22:04.038031 == TX Byte 1 ==
2640 12:22:04.041657 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2641 12:22:04.045093 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2642 12:22:04.045178
2643 12:22:04.048343 [DATLAT]
2644 12:22:04.048427 Freq=1200, CH0 RK0
2645 12:22:04.048494
2646 12:22:04.051469 DATLAT Default: 0xd
2647 12:22:04.051553 0, 0xFFFF, sum = 0
2648 12:22:04.054897 1, 0xFFFF, sum = 0
2649 12:22:04.054980 2, 0xFFFF, sum = 0
2650 12:22:04.058575 3, 0xFFFF, sum = 0
2651 12:22:04.058658 4, 0xFFFF, sum = 0
2652 12:22:04.061567 5, 0xFFFF, sum = 0
2653 12:22:04.061650 6, 0xFFFF, sum = 0
2654 12:22:04.064676 7, 0xFFFF, sum = 0
2655 12:22:04.064760 8, 0xFFFF, sum = 0
2656 12:22:04.068051 9, 0xFFFF, sum = 0
2657 12:22:04.068134 10, 0xFFFF, sum = 0
2658 12:22:04.071725 11, 0xFFFF, sum = 0
2659 12:22:04.071809 12, 0x0, sum = 1
2660 12:22:04.074983 13, 0x0, sum = 2
2661 12:22:04.075065 14, 0x0, sum = 3
2662 12:22:04.078629 15, 0x0, sum = 4
2663 12:22:04.078712 best_step = 13
2664 12:22:04.078777
2665 12:22:04.078838 ==
2666 12:22:04.081725 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 12:22:04.088319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 12:22:04.088434 ==
2669 12:22:04.088504 RX Vref Scan: 1
2670 12:22:04.088565
2671 12:22:04.091631 Set Vref Range= 32 -> 127
2672 12:22:04.091714
2673 12:22:04.095095 RX Vref 32 -> 127, step: 1
2674 12:22:04.095177
2675 12:22:04.098585 RX Delay -13 -> 252, step: 4
2676 12:22:04.098667
2677 12:22:04.101353 Set Vref, RX VrefLevel [Byte0]: 32
2678 12:22:04.101436 [Byte1]: 32
2679 12:22:04.106115
2680 12:22:04.106197 Set Vref, RX VrefLevel [Byte0]: 33
2681 12:22:04.109470 [Byte1]: 33
2682 12:22:04.114366
2683 12:22:04.114470 Set Vref, RX VrefLevel [Byte0]: 34
2684 12:22:04.117469 [Byte1]: 34
2685 12:22:04.122124
2686 12:22:04.122206 Set Vref, RX VrefLevel [Byte0]: 35
2687 12:22:04.125098 [Byte1]: 35
2688 12:22:04.129720
2689 12:22:04.129802 Set Vref, RX VrefLevel [Byte0]: 36
2690 12:22:04.133295 [Byte1]: 36
2691 12:22:04.137649
2692 12:22:04.137732 Set Vref, RX VrefLevel [Byte0]: 37
2693 12:22:04.141363 [Byte1]: 37
2694 12:22:04.146024
2695 12:22:04.146106 Set Vref, RX VrefLevel [Byte0]: 38
2696 12:22:04.149350 [Byte1]: 38
2697 12:22:04.154061
2698 12:22:04.154143 Set Vref, RX VrefLevel [Byte0]: 39
2699 12:22:04.157027 [Byte1]: 39
2700 12:22:04.161726
2701 12:22:04.161808 Set Vref, RX VrefLevel [Byte0]: 40
2702 12:22:04.164782 [Byte1]: 40
2703 12:22:04.169214
2704 12:22:04.169296 Set Vref, RX VrefLevel [Byte0]: 41
2705 12:22:04.172961 [Byte1]: 41
2706 12:22:04.177625
2707 12:22:04.177707 Set Vref, RX VrefLevel [Byte0]: 42
2708 12:22:04.180470 [Byte1]: 42
2709 12:22:04.185262
2710 12:22:04.185344 Set Vref, RX VrefLevel [Byte0]: 43
2711 12:22:04.188703 [Byte1]: 43
2712 12:22:04.193307
2713 12:22:04.193388 Set Vref, RX VrefLevel [Byte0]: 44
2714 12:22:04.196461 [Byte1]: 44
2715 12:22:04.200910
2716 12:22:04.200992 Set Vref, RX VrefLevel [Byte0]: 45
2717 12:22:04.204204 [Byte1]: 45
2718 12:22:04.208960
2719 12:22:04.209042 Set Vref, RX VrefLevel [Byte0]: 46
2720 12:22:04.212555 [Byte1]: 46
2721 12:22:04.216694
2722 12:22:04.216776 Set Vref, RX VrefLevel [Byte0]: 47
2723 12:22:04.220104 [Byte1]: 47
2724 12:22:04.224909
2725 12:22:04.224991 Set Vref, RX VrefLevel [Byte0]: 48
2726 12:22:04.228193 [Byte1]: 48
2727 12:22:04.232271
2728 12:22:04.232357 Set Vref, RX VrefLevel [Byte0]: 49
2729 12:22:04.235616 [Byte1]: 49
2730 12:22:04.240509
2731 12:22:04.240592 Set Vref, RX VrefLevel [Byte0]: 50
2732 12:22:04.243656 [Byte1]: 50
2733 12:22:04.248435
2734 12:22:04.248522 Set Vref, RX VrefLevel [Byte0]: 51
2735 12:22:04.251859 [Byte1]: 51
2736 12:22:04.256337
2737 12:22:04.256419 Set Vref, RX VrefLevel [Byte0]: 52
2738 12:22:04.259184 [Byte1]: 52
2739 12:22:04.263979
2740 12:22:04.264061 Set Vref, RX VrefLevel [Byte0]: 53
2741 12:22:04.267478 [Byte1]: 53
2742 12:22:04.271740
2743 12:22:04.271821 Set Vref, RX VrefLevel [Byte0]: 54
2744 12:22:04.275220 [Byte1]: 54
2745 12:22:04.279896
2746 12:22:04.279978 Set Vref, RX VrefLevel [Byte0]: 55
2747 12:22:04.283326 [Byte1]: 55
2748 12:22:04.288283
2749 12:22:04.288364 Set Vref, RX VrefLevel [Byte0]: 56
2750 12:22:04.291096 [Byte1]: 56
2751 12:22:04.295277
2752 12:22:04.295359 Set Vref, RX VrefLevel [Byte0]: 57
2753 12:22:04.298648 [Byte1]: 57
2754 12:22:04.303442
2755 12:22:04.303525 Set Vref, RX VrefLevel [Byte0]: 58
2756 12:22:04.306667 [Byte1]: 58
2757 12:22:04.311208
2758 12:22:04.311291 Set Vref, RX VrefLevel [Byte0]: 59
2759 12:22:04.314434 [Byte1]: 59
2760 12:22:04.319222
2761 12:22:04.322240 Set Vref, RX VrefLevel [Byte0]: 60
2762 12:22:04.325683 [Byte1]: 60
2763 12:22:04.325765
2764 12:22:04.329211 Set Vref, RX VrefLevel [Byte0]: 61
2765 12:22:04.332499 [Byte1]: 61
2766 12:22:04.332581
2767 12:22:04.335638 Set Vref, RX VrefLevel [Byte0]: 62
2768 12:22:04.338995 [Byte1]: 62
2769 12:22:04.342698
2770 12:22:04.342780 Set Vref, RX VrefLevel [Byte0]: 63
2771 12:22:04.346156 [Byte1]: 63
2772 12:22:04.351055
2773 12:22:04.351137 Set Vref, RX VrefLevel [Byte0]: 64
2774 12:22:04.354086 [Byte1]: 64
2775 12:22:04.358492
2776 12:22:04.358574 Set Vref, RX VrefLevel [Byte0]: 65
2777 12:22:04.361970 [Byte1]: 65
2778 12:22:04.366410
2779 12:22:04.366492 Set Vref, RX VrefLevel [Byte0]: 66
2780 12:22:04.370122 [Byte1]: 66
2781 12:22:04.374660
2782 12:22:04.374743 Set Vref, RX VrefLevel [Byte0]: 67
2783 12:22:04.377530 [Byte1]: 67
2784 12:22:04.382452
2785 12:22:04.382534 Set Vref, RX VrefLevel [Byte0]: 68
2786 12:22:04.385938 [Byte1]: 68
2787 12:22:04.390706
2788 12:22:04.390788 Set Vref, RX VrefLevel [Byte0]: 69
2789 12:22:04.393545 [Byte1]: 69
2790 12:22:04.398287
2791 12:22:04.398369 Final RX Vref Byte 0 = 57 to rank0
2792 12:22:04.401681 Final RX Vref Byte 1 = 48 to rank0
2793 12:22:04.404680 Final RX Vref Byte 0 = 57 to rank1
2794 12:22:04.407925 Final RX Vref Byte 1 = 48 to rank1==
2795 12:22:04.411612 Dram Type= 6, Freq= 0, CH_0, rank 0
2796 12:22:04.415009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2797 12:22:04.417953 ==
2798 12:22:04.418035 DQS Delay:
2799 12:22:04.418100 DQS0 = 0, DQS1 = 0
2800 12:22:04.421786 DQM Delay:
2801 12:22:04.421869 DQM0 = 120, DQM1 = 112
2802 12:22:04.424625 DQ Delay:
2803 12:22:04.428260 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2804 12:22:04.431861 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2805 12:22:04.434861 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2806 12:22:04.438441 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2807 12:22:04.438524
2808 12:22:04.438588
2809 12:22:04.445093 [DQSOSCAuto] RK0, (LSB)MR18= 0x120c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2810 12:22:04.447990 CH0 RK0: MR19=404, MR18=120C
2811 12:22:04.455320 CH0_RK0: MR19=0x404, MR18=0x120C, DQSOSC=403, MR23=63, INC=40, DEC=26
2812 12:22:04.455430
2813 12:22:04.457802 ----->DramcWriteLeveling(PI) begin...
2814 12:22:04.457886 ==
2815 12:22:04.461056 Dram Type= 6, Freq= 0, CH_0, rank 1
2816 12:22:04.465124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 12:22:04.468173 ==
2818 12:22:04.468255 Write leveling (Byte 0): 33 => 33
2819 12:22:04.471201 Write leveling (Byte 1): 28 => 28
2820 12:22:04.474621 DramcWriteLeveling(PI) end<-----
2821 12:22:04.474703
2822 12:22:04.474768 ==
2823 12:22:04.477929 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 12:22:04.484632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 12:22:04.484715 ==
2826 12:22:04.488143 [Gating] SW mode calibration
2827 12:22:04.494461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2828 12:22:04.498212 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2829 12:22:04.504579 0 15 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
2830 12:22:04.508087 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 12:22:04.511137 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 12:22:04.517949 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 12:22:04.521519 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 12:22:04.524880 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 12:22:04.528153 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 12:22:04.534439 0 15 28 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
2837 12:22:04.538010 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2838 12:22:04.541140 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 12:22:04.547931 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 12:22:04.551208 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 12:22:04.554523 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 12:22:04.561517 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 12:22:04.564909 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2844 12:22:04.568239 1 0 28 | B1->B0 | 3f3f 3f3f | 1 0 | (0 0) (0 0)
2845 12:22:04.575026 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 12:22:04.578540 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 12:22:04.581414 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 12:22:04.588369 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 12:22:04.591621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 12:22:04.594952 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 12:22:04.598316 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2852 12:22:04.604885 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2853 12:22:04.607983 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2854 12:22:04.611788 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 12:22:04.618152 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 12:22:04.621737 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 12:22:04.625243 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 12:22:04.632017 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 12:22:04.635375 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 12:22:04.638710 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 12:22:04.645125 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 12:22:04.648828 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:22:04.651730 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:22:04.658670 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:22:04.661952 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:22:04.665710 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:22:04.668441 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2868 12:22:04.675460 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2869 12:22:04.678461 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2870 12:22:04.682030 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 12:22:04.685235 Total UI for P1: 0, mck2ui 16
2872 12:22:04.688176 best dqsien dly found for B0: ( 1, 3, 30)
2873 12:22:04.691901 Total UI for P1: 0, mck2ui 16
2874 12:22:04.695054 best dqsien dly found for B1: ( 1, 3, 28)
2875 12:22:04.698645 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2876 12:22:04.701778 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2877 12:22:04.701861
2878 12:22:04.708654 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2879 12:22:04.711720 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2880 12:22:04.711866 [Gating] SW calibration Done
2881 12:22:04.715241 ==
2882 12:22:04.718829 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 12:22:04.722194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 12:22:04.722278 ==
2885 12:22:04.722343 RX Vref Scan: 0
2886 12:22:04.722404
2887 12:22:04.725738 RX Vref 0 -> 0, step: 1
2888 12:22:04.725821
2889 12:22:04.728689 RX Delay -40 -> 252, step: 8
2890 12:22:04.732305 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2891 12:22:04.735090 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2892 12:22:04.738620 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2893 12:22:04.745466 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2894 12:22:04.748743 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2895 12:22:04.751756 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2896 12:22:04.755204 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2897 12:22:04.758702 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2898 12:22:04.765560 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2899 12:22:04.768549 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2900 12:22:04.771953 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2901 12:22:04.775829 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2902 12:22:04.778561 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2903 12:22:04.785522 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2904 12:22:04.788945 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2905 12:22:04.792065 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2906 12:22:04.792148 ==
2907 12:22:04.795391 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 12:22:04.798714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 12:22:04.798797 ==
2910 12:22:04.801933 DQS Delay:
2911 12:22:04.802015 DQS0 = 0, DQS1 = 0
2912 12:22:04.805180 DQM Delay:
2913 12:22:04.805263 DQM0 = 122, DQM1 = 112
2914 12:22:04.808506 DQ Delay:
2915 12:22:04.812221 DQ0 =119, DQ1 =119, DQ2 =123, DQ3 =119
2916 12:22:04.815215 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2917 12:22:04.818616 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2918 12:22:04.822188 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2919 12:22:04.822270
2920 12:22:04.822335
2921 12:22:04.822411 ==
2922 12:22:04.825153 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 12:22:04.829000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 12:22:04.829083 ==
2925 12:22:04.829149
2926 12:22:04.829239
2927 12:22:04.831889 TX Vref Scan disable
2928 12:22:04.835498 == TX Byte 0 ==
2929 12:22:04.838995 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2930 12:22:04.841984 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2931 12:22:04.845337 == TX Byte 1 ==
2932 12:22:04.848739 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2933 12:22:04.852321 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2934 12:22:04.852404 ==
2935 12:22:04.855640 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 12:22:04.858683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 12:22:04.858780 ==
2938 12:22:04.872252 TX Vref=22, minBit 1, minWin=25, winSum=413
2939 12:22:04.875580 TX Vref=24, minBit 3, minWin=25, winSum=418
2940 12:22:04.879173 TX Vref=26, minBit 3, minWin=25, winSum=421
2941 12:22:04.882206 TX Vref=28, minBit 0, minWin=26, winSum=424
2942 12:22:04.885924 TX Vref=30, minBit 0, minWin=26, winSum=425
2943 12:22:04.889370 TX Vref=32, minBit 0, minWin=26, winSum=425
2944 12:22:04.895681 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
2945 12:22:04.895789
2946 12:22:04.899263 Final TX Range 1 Vref 30
2947 12:22:04.899367
2948 12:22:04.899457 ==
2949 12:22:04.902706 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 12:22:04.905646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 12:22:04.905729 ==
2952 12:22:04.905795
2953 12:22:04.908766
2954 12:22:04.908848 TX Vref Scan disable
2955 12:22:04.912382 == TX Byte 0 ==
2956 12:22:04.915574 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2957 12:22:04.919636 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2958 12:22:04.922537 == TX Byte 1 ==
2959 12:22:04.926183 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2960 12:22:04.929088 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2961 12:22:04.929170
2962 12:22:04.932469 [DATLAT]
2963 12:22:04.932551 Freq=1200, CH0 RK1
2964 12:22:04.932616
2965 12:22:04.935898 DATLAT Default: 0xd
2966 12:22:04.935980 0, 0xFFFF, sum = 0
2967 12:22:04.939370 1, 0xFFFF, sum = 0
2968 12:22:04.939469 2, 0xFFFF, sum = 0
2969 12:22:04.942321 3, 0xFFFF, sum = 0
2970 12:22:04.942405 4, 0xFFFF, sum = 0
2971 12:22:04.945816 5, 0xFFFF, sum = 0
2972 12:22:04.945916 6, 0xFFFF, sum = 0
2973 12:22:04.949096 7, 0xFFFF, sum = 0
2974 12:22:04.949179 8, 0xFFFF, sum = 0
2975 12:22:04.952666 9, 0xFFFF, sum = 0
2976 12:22:04.955645 10, 0xFFFF, sum = 0
2977 12:22:04.955758 11, 0xFFFF, sum = 0
2978 12:22:04.958985 12, 0x0, sum = 1
2979 12:22:04.959068 13, 0x0, sum = 2
2980 12:22:04.959134 14, 0x0, sum = 3
2981 12:22:04.962398 15, 0x0, sum = 4
2982 12:22:04.962482 best_step = 13
2983 12:22:04.962547
2984 12:22:04.962607 ==
2985 12:22:04.965895 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 12:22:04.972376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 12:22:04.972459 ==
2988 12:22:04.972524 RX Vref Scan: 0
2989 12:22:04.972585
2990 12:22:04.975780 RX Vref 0 -> 0, step: 1
2991 12:22:04.975862
2992 12:22:04.979322 RX Delay -13 -> 252, step: 4
2993 12:22:04.982604 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2994 12:22:04.985730 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2995 12:22:04.992634 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2996 12:22:04.995744 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2997 12:22:04.999151 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
2998 12:22:05.002492 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
2999 12:22:05.005977 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3000 12:22:05.012654 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3001 12:22:05.016012 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3002 12:22:05.019193 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3003 12:22:05.022653 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3004 12:22:05.025996 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3005 12:22:05.032617 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3006 12:22:05.036268 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3007 12:22:05.039528 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3008 12:22:05.043026 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3009 12:22:05.043108 ==
3010 12:22:05.045906 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 12:22:05.049388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 12:22:05.052793 ==
3013 12:22:05.052874 DQS Delay:
3014 12:22:05.052940 DQS0 = 0, DQS1 = 0
3015 12:22:05.056099 DQM Delay:
3016 12:22:05.056211 DQM0 = 120, DQM1 = 110
3017 12:22:05.059123 DQ Delay:
3018 12:22:05.062766 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3019 12:22:05.065996 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3020 12:22:05.069641 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3021 12:22:05.072652 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3022 12:22:05.072735
3023 12:22:05.072801
3024 12:22:05.079607 [DQSOSCAuto] RK1, (LSB)MR18= 0xded, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3025 12:22:05.082585 CH0 RK1: MR19=403, MR18=DED
3026 12:22:05.089599 CH0_RK1: MR19=0x403, MR18=0xDED, DQSOSC=405, MR23=63, INC=39, DEC=26
3027 12:22:05.092594 [RxdqsGatingPostProcess] freq 1200
3028 12:22:05.099245 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3029 12:22:05.099328 best DQS0 dly(2T, 0.5T) = (0, 11)
3030 12:22:05.102737 best DQS1 dly(2T, 0.5T) = (0, 11)
3031 12:22:05.106328 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3032 12:22:05.109749 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3033 12:22:05.112956 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 12:22:05.115994 best DQS1 dly(2T, 0.5T) = (0, 11)
3035 12:22:05.119612 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 12:22:05.123264 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3037 12:22:05.125981 Pre-setting of DQS Precalculation
3038 12:22:05.129263 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3039 12:22:05.133182 ==
3040 12:22:05.133269 Dram Type= 6, Freq= 0, CH_1, rank 0
3041 12:22:05.139556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 12:22:05.139686 ==
3043 12:22:05.142675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3044 12:22:05.149153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3045 12:22:05.158187 [CA 0] Center 37 (7~68) winsize 62
3046 12:22:05.161996 [CA 1] Center 37 (7~68) winsize 62
3047 12:22:05.165194 [CA 2] Center 35 (5~65) winsize 61
3048 12:22:05.168740 [CA 3] Center 34 (4~64) winsize 61
3049 12:22:05.171549 [CA 4] Center 34 (4~64) winsize 61
3050 12:22:05.175016 [CA 5] Center 33 (3~63) winsize 61
3051 12:22:05.175097
3052 12:22:05.178362 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3053 12:22:05.178469
3054 12:22:05.181768 [CATrainingPosCal] consider 1 rank data
3055 12:22:05.185336 u2DelayCellTimex100 = 270/100 ps
3056 12:22:05.188331 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3057 12:22:05.191710 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3058 12:22:05.198882 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3059 12:22:05.202321 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3060 12:22:05.205218 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3061 12:22:05.209121 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3062 12:22:05.209202
3063 12:22:05.211815 CA PerBit enable=1, Macro0, CA PI delay=33
3064 12:22:05.211896
3065 12:22:05.215328 [CBTSetCACLKResult] CA Dly = 33
3066 12:22:05.215434 CS Dly: 8 (0~39)
3067 12:22:05.215526 ==
3068 12:22:05.218616 Dram Type= 6, Freq= 0, CH_1, rank 1
3069 12:22:05.225610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 12:22:05.225693 ==
3071 12:22:05.228586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 12:22:05.235377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3073 12:22:05.244440 [CA 0] Center 37 (7~68) winsize 62
3074 12:22:05.247717 [CA 1] Center 37 (7~68) winsize 62
3075 12:22:05.250639 [CA 2] Center 35 (5~65) winsize 61
3076 12:22:05.254230 [CA 3] Center 34 (4~65) winsize 62
3077 12:22:05.257413 [CA 4] Center 34 (4~65) winsize 62
3078 12:22:05.260720 [CA 5] Center 33 (3~63) winsize 61
3079 12:22:05.260803
3080 12:22:05.264479 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3081 12:22:05.264562
3082 12:22:05.267423 [CATrainingPosCal] consider 2 rank data
3083 12:22:05.270711 u2DelayCellTimex100 = 270/100 ps
3084 12:22:05.274308 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 12:22:05.277820 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 12:22:05.281401 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 12:22:05.287943 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 12:22:05.290834 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 12:22:05.294396 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3090 12:22:05.294477
3091 12:22:05.297760 CA PerBit enable=1, Macro0, CA PI delay=33
3092 12:22:05.297833
3093 12:22:05.300922 [CBTSetCACLKResult] CA Dly = 33
3094 12:22:05.301019 CS Dly: 9 (0~41)
3095 12:22:05.301107
3096 12:22:05.304415 ----->DramcWriteLeveling(PI) begin...
3097 12:22:05.304497 ==
3098 12:22:05.308017 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 12:22:05.314708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 12:22:05.314789 ==
3101 12:22:05.317666 Write leveling (Byte 0): 26 => 26
3102 12:22:05.321285 Write leveling (Byte 1): 28 => 28
3103 12:22:05.321366 DramcWriteLeveling(PI) end<-----
3104 12:22:05.324571
3105 12:22:05.324651 ==
3106 12:22:05.327793 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 12:22:05.331326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 12:22:05.331433 ==
3109 12:22:05.334365 [Gating] SW mode calibration
3110 12:22:05.340923 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3111 12:22:05.344653 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3112 12:22:05.351051 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 12:22:05.354464 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 12:22:05.357744 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 12:22:05.364399 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 12:22:05.367597 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 12:22:05.371066 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 12:22:05.377841 0 15 24 | B1->B0 | 3333 2727 | 0 0 | (1 0) (0 0)
3119 12:22:05.381050 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3120 12:22:05.384560 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 12:22:05.388219 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 12:22:05.394700 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 12:22:05.398105 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 12:22:05.401116 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 12:22:05.408135 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3126 12:22:05.411017 1 0 24 | B1->B0 | 3434 4242 | 0 0 | (0 0) (0 0)
3127 12:22:05.414533 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3128 12:22:05.421184 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 12:22:05.424694 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 12:22:05.428393 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 12:22:05.435305 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 12:22:05.438025 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 12:22:05.441629 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 12:22:05.448079 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 12:22:05.451617 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3136 12:22:05.455042 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 12:22:05.461379 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 12:22:05.464733 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 12:22:05.467906 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 12:22:05.471527 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 12:22:05.478620 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 12:22:05.482023 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 12:22:05.484972 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 12:22:05.491665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 12:22:05.495446 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:22:05.498532 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:22:05.505146 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:22:05.508177 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:22:05.511905 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:22:05.518228 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3151 12:22:05.521807 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 12:22:05.525458 Total UI for P1: 0, mck2ui 16
3153 12:22:05.528441 best dqsien dly found for B0: ( 1, 3, 24)
3154 12:22:05.532115 Total UI for P1: 0, mck2ui 16
3155 12:22:05.535083 best dqsien dly found for B1: ( 1, 3, 24)
3156 12:22:05.538666 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3157 12:22:05.541993 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3158 12:22:05.542074
3159 12:22:05.545339 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3160 12:22:05.548285 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3161 12:22:05.551847 [Gating] SW calibration Done
3162 12:22:05.551929 ==
3163 12:22:05.554886 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 12:22:05.558451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 12:22:05.558533 ==
3166 12:22:05.561570 RX Vref Scan: 0
3167 12:22:05.561677
3168 12:22:05.564997 RX Vref 0 -> 0, step: 1
3169 12:22:05.565079
3170 12:22:05.565143 RX Delay -40 -> 252, step: 8
3171 12:22:05.571973 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3172 12:22:05.575359 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3173 12:22:05.578565 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3174 12:22:05.581634 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3175 12:22:05.585238 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3176 12:22:05.591632 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3177 12:22:05.594963 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3178 12:22:05.598385 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3179 12:22:05.601825 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3180 12:22:05.605179 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3181 12:22:05.608613 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3182 12:22:05.615396 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3183 12:22:05.619152 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3184 12:22:05.622351 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3185 12:22:05.625239 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3186 12:22:05.632072 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3187 12:22:05.632151 ==
3188 12:22:05.635345 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 12:22:05.638567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 12:22:05.638665 ==
3191 12:22:05.638755 DQS Delay:
3192 12:22:05.642008 DQS0 = 0, DQS1 = 0
3193 12:22:05.642105 DQM Delay:
3194 12:22:05.645175 DQM0 = 119, DQM1 = 116
3195 12:22:05.645273 DQ Delay:
3196 12:22:05.648779 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3197 12:22:05.651758 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3198 12:22:05.654968 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3199 12:22:05.658543 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3200 12:22:05.658633
3201 12:22:05.658698
3202 12:22:05.658757 ==
3203 12:22:05.662227 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 12:22:05.668630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 12:22:05.668730 ==
3206 12:22:05.668821
3207 12:22:05.668908
3208 12:22:05.668994 TX Vref Scan disable
3209 12:22:05.672193 == TX Byte 0 ==
3210 12:22:05.675626 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3211 12:22:05.682480 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3212 12:22:05.682584 == TX Byte 1 ==
3213 12:22:05.685533 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3214 12:22:05.689038 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3215 12:22:05.692226 ==
3216 12:22:05.695656 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 12:22:05.698822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 12:22:05.698917 ==
3219 12:22:05.710178 TX Vref=22, minBit 1, minWin=24, winSum=412
3220 12:22:05.713269 TX Vref=24, minBit 1, minWin=25, winSum=416
3221 12:22:05.716839 TX Vref=26, minBit 9, minWin=25, winSum=418
3222 12:22:05.720126 TX Vref=28, minBit 0, minWin=26, winSum=423
3223 12:22:05.723561 TX Vref=30, minBit 10, minWin=25, winSum=426
3224 12:22:05.726719 TX Vref=32, minBit 10, minWin=25, winSum=427
3225 12:22:05.734017 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
3226 12:22:05.734124
3227 12:22:05.736894 Final TX Range 1 Vref 28
3228 12:22:05.736967
3229 12:22:05.737028 ==
3230 12:22:05.740403 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 12:22:05.743884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 12:22:05.743957 ==
3233 12:22:05.744018
3234 12:22:05.744077
3235 12:22:05.746953 TX Vref Scan disable
3236 12:22:05.750519 == TX Byte 0 ==
3237 12:22:05.754308 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3238 12:22:05.757006 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3239 12:22:05.760430 == TX Byte 1 ==
3240 12:22:05.764203 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3241 12:22:05.767124 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3242 12:22:05.767222
3243 12:22:05.770492 [DATLAT]
3244 12:22:05.770564 Freq=1200, CH1 RK0
3245 12:22:05.770625
3246 12:22:05.774231 DATLAT Default: 0xd
3247 12:22:05.774325 0, 0xFFFF, sum = 0
3248 12:22:05.777649 1, 0xFFFF, sum = 0
3249 12:22:05.777731 2, 0xFFFF, sum = 0
3250 12:22:05.780685 3, 0xFFFF, sum = 0
3251 12:22:05.780784 4, 0xFFFF, sum = 0
3252 12:22:05.784009 5, 0xFFFF, sum = 0
3253 12:22:05.784081 6, 0xFFFF, sum = 0
3254 12:22:05.787268 7, 0xFFFF, sum = 0
3255 12:22:05.787364 8, 0xFFFF, sum = 0
3256 12:22:05.790521 9, 0xFFFF, sum = 0
3257 12:22:05.790620 10, 0xFFFF, sum = 0
3258 12:22:05.794671 11, 0xFFFF, sum = 0
3259 12:22:05.794773 12, 0x0, sum = 1
3260 12:22:05.797375 13, 0x0, sum = 2
3261 12:22:05.797446 14, 0x0, sum = 3
3262 12:22:05.801061 15, 0x0, sum = 4
3263 12:22:05.801159 best_step = 13
3264 12:22:05.801246
3265 12:22:05.801334 ==
3266 12:22:05.803975 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 12:22:05.807543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 12:22:05.810989 ==
3269 12:22:05.811063 RX Vref Scan: 1
3270 12:22:05.811124
3271 12:22:05.814260 Set Vref Range= 32 -> 127
3272 12:22:05.814356
3273 12:22:05.817357 RX Vref 32 -> 127, step: 1
3274 12:22:05.817458
3275 12:22:05.817548 RX Delay -5 -> 252, step: 4
3276 12:22:05.817635
3277 12:22:05.820722 Set Vref, RX VrefLevel [Byte0]: 32
3278 12:22:05.823954 [Byte1]: 32
3279 12:22:05.828384
3280 12:22:05.828483 Set Vref, RX VrefLevel [Byte0]: 33
3281 12:22:05.831613 [Byte1]: 33
3282 12:22:05.836133
3283 12:22:05.839114 Set Vref, RX VrefLevel [Byte0]: 34
3284 12:22:05.842410 [Byte1]: 34
3285 12:22:05.842512
3286 12:22:05.845998 Set Vref, RX VrefLevel [Byte0]: 35
3287 12:22:05.849256 [Byte1]: 35
3288 12:22:05.849338
3289 12:22:05.852600 Set Vref, RX VrefLevel [Byte0]: 36
3290 12:22:05.856123 [Byte1]: 36
3291 12:22:05.859771
3292 12:22:05.859852 Set Vref, RX VrefLevel [Byte0]: 37
3293 12:22:05.863452 [Byte1]: 37
3294 12:22:05.867856
3295 12:22:05.867936 Set Vref, RX VrefLevel [Byte0]: 38
3296 12:22:05.870575 [Byte1]: 38
3297 12:22:05.875360
3298 12:22:05.875440 Set Vref, RX VrefLevel [Byte0]: 39
3299 12:22:05.879044 [Byte1]: 39
3300 12:22:05.883272
3301 12:22:05.883356 Set Vref, RX VrefLevel [Byte0]: 40
3302 12:22:05.886543 [Byte1]: 40
3303 12:22:05.891339
3304 12:22:05.891419 Set Vref, RX VrefLevel [Byte0]: 41
3305 12:22:05.894655 [Byte1]: 41
3306 12:22:05.899031
3307 12:22:05.899115 Set Vref, RX VrefLevel [Byte0]: 42
3308 12:22:05.902458 [Byte1]: 42
3309 12:22:05.906662
3310 12:22:05.906769 Set Vref, RX VrefLevel [Byte0]: 43
3311 12:22:05.910217 [Byte1]: 43
3312 12:22:05.914406
3313 12:22:05.914515 Set Vref, RX VrefLevel [Byte0]: 44
3314 12:22:05.917938 [Byte1]: 44
3315 12:22:05.922725
3316 12:22:05.922831 Set Vref, RX VrefLevel [Byte0]: 45
3317 12:22:05.925828 [Byte1]: 45
3318 12:22:05.930097
3319 12:22:05.930191 Set Vref, RX VrefLevel [Byte0]: 46
3320 12:22:05.933487 [Byte1]: 46
3321 12:22:05.938638
3322 12:22:05.938732 Set Vref, RX VrefLevel [Byte0]: 47
3323 12:22:05.941712 [Byte1]: 47
3324 12:22:05.946065
3325 12:22:05.946145 Set Vref, RX VrefLevel [Byte0]: 48
3326 12:22:05.949395 [Byte1]: 48
3327 12:22:05.953557
3328 12:22:05.953637 Set Vref, RX VrefLevel [Byte0]: 49
3329 12:22:05.957086 [Byte1]: 49
3330 12:22:05.961841
3331 12:22:05.961963 Set Vref, RX VrefLevel [Byte0]: 50
3332 12:22:05.964803 [Byte1]: 50
3333 12:22:05.969664
3334 12:22:05.969737 Set Vref, RX VrefLevel [Byte0]: 51
3335 12:22:05.972837 [Byte1]: 51
3336 12:22:05.977379
3337 12:22:05.977451 Set Vref, RX VrefLevel [Byte0]: 52
3338 12:22:05.980757 [Byte1]: 52
3339 12:22:05.985007
3340 12:22:05.985079 Set Vref, RX VrefLevel [Byte0]: 53
3341 12:22:05.988566 [Byte1]: 53
3342 12:22:05.992897
3343 12:22:05.992995 Set Vref, RX VrefLevel [Byte0]: 54
3344 12:22:05.996207 [Byte1]: 54
3345 12:22:06.000946
3346 12:22:06.001020 Set Vref, RX VrefLevel [Byte0]: 55
3347 12:22:06.004364 [Byte1]: 55
3348 12:22:06.008601
3349 12:22:06.008681 Set Vref, RX VrefLevel [Byte0]: 56
3350 12:22:06.012282 [Byte1]: 56
3351 12:22:06.016390
3352 12:22:06.016488 Set Vref, RX VrefLevel [Byte0]: 57
3353 12:22:06.019999 [Byte1]: 57
3354 12:22:06.024820
3355 12:22:06.024927 Set Vref, RX VrefLevel [Byte0]: 58
3356 12:22:06.027856 [Byte1]: 58
3357 12:22:06.032472
3358 12:22:06.032548 Set Vref, RX VrefLevel [Byte0]: 59
3359 12:22:06.035422 [Byte1]: 59
3360 12:22:06.040586
3361 12:22:06.040685 Set Vref, RX VrefLevel [Byte0]: 60
3362 12:22:06.043555 [Byte1]: 60
3363 12:22:06.047945
3364 12:22:06.048020 Set Vref, RX VrefLevel [Byte0]: 61
3365 12:22:06.051453 [Byte1]: 61
3366 12:22:06.055771
3367 12:22:06.055872 Set Vref, RX VrefLevel [Byte0]: 62
3368 12:22:06.059193 [Byte1]: 62
3369 12:22:06.063540
3370 12:22:06.063676 Set Vref, RX VrefLevel [Byte0]: 63
3371 12:22:06.066830 [Byte1]: 63
3372 12:22:06.071657
3373 12:22:06.071741 Set Vref, RX VrefLevel [Byte0]: 64
3374 12:22:06.075272 [Byte1]: 64
3375 12:22:06.079191
3376 12:22:06.079272 Set Vref, RX VrefLevel [Byte0]: 65
3377 12:22:06.082725 [Byte1]: 65
3378 12:22:06.087790
3379 12:22:06.087870 Set Vref, RX VrefLevel [Byte0]: 66
3380 12:22:06.090547 [Byte1]: 66
3381 12:22:06.095416
3382 12:22:06.095524 Set Vref, RX VrefLevel [Byte0]: 67
3383 12:22:06.098333 [Byte1]: 67
3384 12:22:06.102874
3385 12:22:06.102954 Set Vref, RX VrefLevel [Byte0]: 68
3386 12:22:06.106573 [Byte1]: 68
3387 12:22:06.111291
3388 12:22:06.111398 Final RX Vref Byte 0 = 54 to rank0
3389 12:22:06.114024 Final RX Vref Byte 1 = 46 to rank0
3390 12:22:06.117274 Final RX Vref Byte 0 = 54 to rank1
3391 12:22:06.120643 Final RX Vref Byte 1 = 46 to rank1==
3392 12:22:06.124360 Dram Type= 6, Freq= 0, CH_1, rank 0
3393 12:22:06.130641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 12:22:06.130726 ==
3395 12:22:06.130808 DQS Delay:
3396 12:22:06.130872 DQS0 = 0, DQS1 = 0
3397 12:22:06.134312 DQM Delay:
3398 12:22:06.134393 DQM0 = 120, DQM1 = 115
3399 12:22:06.137328 DQ Delay:
3400 12:22:06.140860 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3401 12:22:06.144238 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3402 12:22:06.147309 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3403 12:22:06.150757 DQ12 =122, DQ13 =120, DQ14 =124, DQ15 =124
3404 12:22:06.150838
3405 12:22:06.150903
3406 12:22:06.157403 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3407 12:22:06.161082 CH1 RK0: MR19=404, MR18=13
3408 12:22:06.167738 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3409 12:22:06.167850
3410 12:22:06.170932 ----->DramcWriteLeveling(PI) begin...
3411 12:22:06.171011 ==
3412 12:22:06.174039 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 12:22:06.177844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 12:22:06.177922 ==
3415 12:22:06.180609 Write leveling (Byte 0): 27 => 27
3416 12:22:06.184422 Write leveling (Byte 1): 28 => 28
3417 12:22:06.187525 DramcWriteLeveling(PI) end<-----
3418 12:22:06.187681
3419 12:22:06.187804 ==
3420 12:22:06.190700 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 12:22:06.194126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 12:22:06.197423 ==
3423 12:22:06.197515 [Gating] SW mode calibration
3424 12:22:06.204203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3425 12:22:06.210775 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3426 12:22:06.214006 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 12:22:06.220684 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 12:22:06.224352 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 12:22:06.227774 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 12:22:06.234458 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 12:22:06.237963 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3432 12:22:06.240969 0 15 24 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 1)
3433 12:22:06.244550 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 12:22:06.251238 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 12:22:06.254099 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 12:22:06.257829 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 12:22:06.264308 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 12:22:06.267632 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 12:22:06.271028 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 12:22:06.277883 1 0 24 | B1->B0 | 3f3f 2929 | 0 0 | (1 1) (0 0)
3441 12:22:06.281233 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 12:22:06.284655 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 12:22:06.290840 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 12:22:06.294223 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 12:22:06.297662 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 12:22:06.304213 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3447 12:22:06.307626 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3448 12:22:06.311236 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3449 12:22:06.317925 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3450 12:22:06.321531 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 12:22:06.324520 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 12:22:06.330969 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 12:22:06.334226 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 12:22:06.337709 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 12:22:06.341271 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 12:22:06.348335 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 12:22:06.351109 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 12:22:06.354232 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 12:22:06.361303 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 12:22:06.364337 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 12:22:06.367936 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:22:06.374469 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:22:06.377917 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3464 12:22:06.381173 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3465 12:22:06.387887 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3466 12:22:06.387968 Total UI for P1: 0, mck2ui 16
3467 12:22:06.394329 best dqsien dly found for B1: ( 1, 3, 22)
3468 12:22:06.397676 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 12:22:06.400707 Total UI for P1: 0, mck2ui 16
3470 12:22:06.404242 best dqsien dly found for B0: ( 1, 3, 26)
3471 12:22:06.407879 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3472 12:22:06.410937 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3473 12:22:06.411038
3474 12:22:06.414289 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3475 12:22:06.417605 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3476 12:22:06.420980 [Gating] SW calibration Done
3477 12:22:06.421085 ==
3478 12:22:06.424526 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 12:22:06.427686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 12:22:06.430596 ==
3481 12:22:06.430697 RX Vref Scan: 0
3482 12:22:06.430788
3483 12:22:06.434250 RX Vref 0 -> 0, step: 1
3484 12:22:06.434329
3485 12:22:06.437778 RX Delay -40 -> 252, step: 8
3486 12:22:06.440682 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3487 12:22:06.443929 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3488 12:22:06.447461 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3489 12:22:06.450973 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3490 12:22:06.457703 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3491 12:22:06.460693 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3492 12:22:06.464208 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3493 12:22:06.467327 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3494 12:22:06.470748 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3495 12:22:06.477480 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3496 12:22:06.481147 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3497 12:22:06.483962 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3498 12:22:06.487478 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3499 12:22:06.490888 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3500 12:22:06.497169 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3501 12:22:06.500535 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3502 12:22:06.500620 ==
3503 12:22:06.504061 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 12:22:06.507071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 12:22:06.507156 ==
3506 12:22:06.510460 DQS Delay:
3507 12:22:06.510543 DQS0 = 0, DQS1 = 0
3508 12:22:06.510610 DQM Delay:
3509 12:22:06.513844 DQM0 = 119, DQM1 = 117
3510 12:22:06.513927 DQ Delay:
3511 12:22:06.517252 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3512 12:22:06.520454 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3513 12:22:06.526841 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3514 12:22:06.530367 DQ12 =127, DQ13 =123, DQ14 =119, DQ15 =123
3515 12:22:06.530477
3516 12:22:06.530572
3517 12:22:06.530665 ==
3518 12:22:06.533848 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 12:22:06.536898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 12:22:06.536982 ==
3521 12:22:06.537048
3522 12:22:06.537110
3523 12:22:06.540451 TX Vref Scan disable
3524 12:22:06.540540 == TX Byte 0 ==
3525 12:22:06.546760 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3526 12:22:06.550163 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3527 12:22:06.550246 == TX Byte 1 ==
3528 12:22:06.557212 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3529 12:22:06.560576 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3530 12:22:06.560688 ==
3531 12:22:06.563712 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 12:22:06.567330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 12:22:06.567414 ==
3534 12:22:06.579942 TX Vref=22, minBit 9, minWin=25, winSum=418
3535 12:22:06.582877 TX Vref=24, minBit 9, minWin=25, winSum=421
3536 12:22:06.586119 TX Vref=26, minBit 1, minWin=26, winSum=423
3537 12:22:06.589607 TX Vref=28, minBit 1, minWin=26, winSum=430
3538 12:22:06.592741 TX Vref=30, minBit 10, minWin=26, winSum=431
3539 12:22:06.599855 TX Vref=32, minBit 10, minWin=26, winSum=434
3540 12:22:06.602855 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 32
3541 12:22:06.602939
3542 12:22:06.606186 Final TX Range 1 Vref 32
3543 12:22:06.606270
3544 12:22:06.606336 ==
3545 12:22:06.609543 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 12:22:06.612600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 12:22:06.616413 ==
3548 12:22:06.616505
3549 12:22:06.616574
3550 12:22:06.616643 TX Vref Scan disable
3551 12:22:06.619529 == TX Byte 0 ==
3552 12:22:06.622671 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3553 12:22:06.626351 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3554 12:22:06.629869 == TX Byte 1 ==
3555 12:22:06.633023 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3556 12:22:06.636029 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3557 12:22:06.639321
3558 12:22:06.639404 [DATLAT]
3559 12:22:06.639504 Freq=1200, CH1 RK1
3560 12:22:06.639607
3561 12:22:06.643277 DATLAT Default: 0xd
3562 12:22:06.643360 0, 0xFFFF, sum = 0
3563 12:22:06.646218 1, 0xFFFF, sum = 0
3564 12:22:06.646303 2, 0xFFFF, sum = 0
3565 12:22:06.649386 3, 0xFFFF, sum = 0
3566 12:22:06.652927 4, 0xFFFF, sum = 0
3567 12:22:06.653012 5, 0xFFFF, sum = 0
3568 12:22:06.656533 6, 0xFFFF, sum = 0
3569 12:22:06.656617 7, 0xFFFF, sum = 0
3570 12:22:06.659585 8, 0xFFFF, sum = 0
3571 12:22:06.659710 9, 0xFFFF, sum = 0
3572 12:22:06.662467 10, 0xFFFF, sum = 0
3573 12:22:06.662557 11, 0xFFFF, sum = 0
3574 12:22:06.665915 12, 0x0, sum = 1
3575 12:22:06.665999 13, 0x0, sum = 2
3576 12:22:06.669078 14, 0x0, sum = 3
3577 12:22:06.669162 15, 0x0, sum = 4
3578 12:22:06.669230 best_step = 13
3579 12:22:06.672621
3580 12:22:06.672704 ==
3581 12:22:06.676256 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 12:22:06.679325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 12:22:06.679409 ==
3584 12:22:06.679476 RX Vref Scan: 0
3585 12:22:06.679538
3586 12:22:06.682421 RX Vref 0 -> 0, step: 1
3587 12:22:06.682504
3588 12:22:06.685924 RX Delay -5 -> 252, step: 4
3589 12:22:06.689621 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3590 12:22:06.695612 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3591 12:22:06.699390 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3592 12:22:06.702335 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3593 12:22:06.705801 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3594 12:22:06.708847 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3595 12:22:06.715562 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3596 12:22:06.718990 iDelay=195, Bit 7, Center 118 (55 ~ 182) 128
3597 12:22:06.722664 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3598 12:22:06.725798 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3599 12:22:06.729695 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3600 12:22:06.735806 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3601 12:22:06.739071 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3602 12:22:06.742248 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3603 12:22:06.745379 iDelay=195, Bit 14, Center 120 (63 ~ 178) 116
3604 12:22:06.748718 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3605 12:22:06.752408 ==
3606 12:22:06.755732 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 12:22:06.758742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 12:22:06.758844 ==
3609 12:22:06.758935 DQS Delay:
3610 12:22:06.762142 DQS0 = 0, DQS1 = 0
3611 12:22:06.762225 DQM Delay:
3612 12:22:06.765648 DQM0 = 119, DQM1 = 116
3613 12:22:06.765730 DQ Delay:
3614 12:22:06.769134 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3615 12:22:06.772236 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =118
3616 12:22:06.775633 DQ8 =104, DQ9 =104, DQ10 =116, DQ11 =110
3617 12:22:06.778727 DQ12 =126, DQ13 =124, DQ14 =120, DQ15 =124
3618 12:22:06.778809
3619 12:22:06.778874
3620 12:22:06.788870 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3621 12:22:06.792410 CH1 RK1: MR19=403, MR18=12EF
3622 12:22:06.795545 CH1_RK1: MR19=0x403, MR18=0x12EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3623 12:22:06.799212 [RxdqsGatingPostProcess] freq 1200
3624 12:22:06.805743 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3625 12:22:06.809276 best DQS0 dly(2T, 0.5T) = (0, 11)
3626 12:22:06.812265 best DQS1 dly(2T, 0.5T) = (0, 11)
3627 12:22:06.815720 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3628 12:22:06.818884 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3629 12:22:06.822645 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 12:22:06.825687 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 12:22:06.829292 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 12:22:06.832709 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 12:22:06.832798 Pre-setting of DQS Precalculation
3634 12:22:06.838940 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3635 12:22:06.845502 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3636 12:22:06.852263 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3637 12:22:06.852368
3638 12:22:06.852462
3639 12:22:06.855757 [Calibration Summary] 2400 Mbps
3640 12:22:06.858702 CH 0, Rank 0
3641 12:22:06.858799 SW Impedance : PASS
3642 12:22:06.862498 DUTY Scan : NO K
3643 12:22:06.865609 ZQ Calibration : PASS
3644 12:22:06.865775 Jitter Meter : NO K
3645 12:22:06.868559 CBT Training : PASS
3646 12:22:06.872150 Write leveling : PASS
3647 12:22:06.872266 RX DQS gating : PASS
3648 12:22:06.875445 RX DQ/DQS(RDDQC) : PASS
3649 12:22:06.875574 TX DQ/DQS : PASS
3650 12:22:06.878834 RX DATLAT : PASS
3651 12:22:06.881989 RX DQ/DQS(Engine): PASS
3652 12:22:06.882061 TX OE : NO K
3653 12:22:06.885308 All Pass.
3654 12:22:06.885378
3655 12:22:06.885437 CH 0, Rank 1
3656 12:22:06.888889 SW Impedance : PASS
3657 12:22:06.889022 DUTY Scan : NO K
3658 12:22:06.892073 ZQ Calibration : PASS
3659 12:22:06.895602 Jitter Meter : NO K
3660 12:22:06.895721 CBT Training : PASS
3661 12:22:06.898602 Write leveling : PASS
3662 12:22:06.902190 RX DQS gating : PASS
3663 12:22:06.902261 RX DQ/DQS(RDDQC) : PASS
3664 12:22:06.905748 TX DQ/DQS : PASS
3665 12:22:06.908856 RX DATLAT : PASS
3666 12:22:06.908981 RX DQ/DQS(Engine): PASS
3667 12:22:06.912230 TX OE : NO K
3668 12:22:06.912386 All Pass.
3669 12:22:06.912509
3670 12:22:06.915305 CH 1, Rank 0
3671 12:22:06.915403 SW Impedance : PASS
3672 12:22:06.918976 DUTY Scan : NO K
3673 12:22:06.919101 ZQ Calibration : PASS
3674 12:22:06.922482 Jitter Meter : NO K
3675 12:22:06.925568 CBT Training : PASS
3676 12:22:06.925681 Write leveling : PASS
3677 12:22:06.929082 RX DQS gating : PASS
3678 12:22:06.932068 RX DQ/DQS(RDDQC) : PASS
3679 12:22:06.932183 TX DQ/DQS : PASS
3680 12:22:06.935572 RX DATLAT : PASS
3681 12:22:06.938951 RX DQ/DQS(Engine): PASS
3682 12:22:06.939086 TX OE : NO K
3683 12:22:06.942441 All Pass.
3684 12:22:06.942542
3685 12:22:06.942632 CH 1, Rank 1
3686 12:22:06.945489 SW Impedance : PASS
3687 12:22:06.945574 DUTY Scan : NO K
3688 12:22:06.949121 ZQ Calibration : PASS
3689 12:22:06.952067 Jitter Meter : NO K
3690 12:22:06.952187 CBT Training : PASS
3691 12:22:06.955614 Write leveling : PASS
3692 12:22:06.958883 RX DQS gating : PASS
3693 12:22:06.958988 RX DQ/DQS(RDDQC) : PASS
3694 12:22:06.962354 TX DQ/DQS : PASS
3695 12:22:06.962461 RX DATLAT : PASS
3696 12:22:06.965091 RX DQ/DQS(Engine): PASS
3697 12:22:06.968692 TX OE : NO K
3698 12:22:06.968799 All Pass.
3699 12:22:06.968873
3700 12:22:06.972149 DramC Write-DBI off
3701 12:22:06.972264 PER_BANK_REFRESH: Hybrid Mode
3702 12:22:06.975747 TX_TRACKING: ON
3703 12:22:06.984914 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3704 12:22:06.988650 [FAST_K] Save calibration result to emmc
3705 12:22:06.992089 dramc_set_vcore_voltage set vcore to 650000
3706 12:22:06.992186 Read voltage for 600, 5
3707 12:22:06.995409 Vio18 = 0
3708 12:22:06.995520 Vcore = 650000
3709 12:22:06.995620 Vdram = 0
3710 12:22:06.998439 Vddq = 0
3711 12:22:06.998549 Vmddr = 0
3712 12:22:07.001974 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3713 12:22:07.008578 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3714 12:22:07.011688 MEM_TYPE=3, freq_sel=19
3715 12:22:07.015102 sv_algorithm_assistance_LP4_1600
3716 12:22:07.018674 ============ PULL DRAM RESETB DOWN ============
3717 12:22:07.021745 ========== PULL DRAM RESETB DOWN end =========
3718 12:22:07.028477 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3719 12:22:07.031703 ===================================
3720 12:22:07.031789 LPDDR4 DRAM CONFIGURATION
3721 12:22:07.035189 ===================================
3722 12:22:07.038819 EX_ROW_EN[0] = 0x0
3723 12:22:07.038904 EX_ROW_EN[1] = 0x0
3724 12:22:07.041625 LP4Y_EN = 0x0
3725 12:22:07.045135 WORK_FSP = 0x0
3726 12:22:07.045220 WL = 0x2
3727 12:22:07.048147 RL = 0x2
3728 12:22:07.048232 BL = 0x2
3729 12:22:07.051537 RPST = 0x0
3730 12:22:07.051647 RD_PRE = 0x0
3731 12:22:07.055260 WR_PRE = 0x1
3732 12:22:07.055371 WR_PST = 0x0
3733 12:22:07.058406 DBI_WR = 0x0
3734 12:22:07.058508 DBI_RD = 0x0
3735 12:22:07.061424 OTF = 0x1
3736 12:22:07.065190 ===================================
3737 12:22:07.068118 ===================================
3738 12:22:07.068230 ANA top config
3739 12:22:07.071501 ===================================
3740 12:22:07.075438 DLL_ASYNC_EN = 0
3741 12:22:07.078783 ALL_SLAVE_EN = 1
3742 12:22:07.078867 NEW_RANK_MODE = 1
3743 12:22:07.082069 DLL_IDLE_MODE = 1
3744 12:22:07.085144 LP45_APHY_COMB_EN = 1
3745 12:22:07.088186 TX_ODT_DIS = 1
3746 12:22:07.091899 NEW_8X_MODE = 1
3747 12:22:07.094667 ===================================
3748 12:22:07.098426 ===================================
3749 12:22:07.098512 data_rate = 1200
3750 12:22:07.101533 CKR = 1
3751 12:22:07.104628 DQ_P2S_RATIO = 8
3752 12:22:07.108143 ===================================
3753 12:22:07.111715 CA_P2S_RATIO = 8
3754 12:22:07.114947 DQ_CA_OPEN = 0
3755 12:22:07.117950 DQ_SEMI_OPEN = 0
3756 12:22:07.118066 CA_SEMI_OPEN = 0
3757 12:22:07.121416 CA_FULL_RATE = 0
3758 12:22:07.124772 DQ_CKDIV4_EN = 1
3759 12:22:07.128002 CA_CKDIV4_EN = 1
3760 12:22:07.131237 CA_PREDIV_EN = 0
3761 12:22:07.134441 PH8_DLY = 0
3762 12:22:07.134548 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3763 12:22:07.138131 DQ_AAMCK_DIV = 4
3764 12:22:07.141162 CA_AAMCK_DIV = 4
3765 12:22:07.144720 CA_ADMCK_DIV = 4
3766 12:22:07.147827 DQ_TRACK_CA_EN = 0
3767 12:22:07.151332 CA_PICK = 600
3768 12:22:07.151436 CA_MCKIO = 600
3769 12:22:07.154301 MCKIO_SEMI = 0
3770 12:22:07.157889 PLL_FREQ = 2288
3771 12:22:07.161521 DQ_UI_PI_RATIO = 32
3772 12:22:07.164748 CA_UI_PI_RATIO = 0
3773 12:22:07.167583 ===================================
3774 12:22:07.170842 ===================================
3775 12:22:07.174485 memory_type:LPDDR4
3776 12:22:07.174560 GP_NUM : 10
3777 12:22:07.178018 SRAM_EN : 1
3778 12:22:07.178095 MD32_EN : 0
3779 12:22:07.181030 ===================================
3780 12:22:07.184248 [ANA_INIT] >>>>>>>>>>>>>>
3781 12:22:07.187531 <<<<<< [CONFIGURE PHASE]: ANA_TX
3782 12:22:07.190885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3783 12:22:07.194416 ===================================
3784 12:22:07.197626 data_rate = 1200,PCW = 0X5800
3785 12:22:07.201258 ===================================
3786 12:22:07.204450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3787 12:22:07.211330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3788 12:22:07.214313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3789 12:22:07.221193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3790 12:22:07.224709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3791 12:22:07.227994 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3792 12:22:07.228098 [ANA_INIT] flow start
3793 12:22:07.231471 [ANA_INIT] PLL >>>>>>>>
3794 12:22:07.234127 [ANA_INIT] PLL <<<<<<<<
3795 12:22:07.234225 [ANA_INIT] MIDPI >>>>>>>>
3796 12:22:07.237632 [ANA_INIT] MIDPI <<<<<<<<
3797 12:22:07.241378 [ANA_INIT] DLL >>>>>>>>
3798 12:22:07.241454 [ANA_INIT] flow end
3799 12:22:07.247742 ============ LP4 DIFF to SE enter ============
3800 12:22:07.251241 ============ LP4 DIFF to SE exit ============
3801 12:22:07.254119 [ANA_INIT] <<<<<<<<<<<<<
3802 12:22:07.254270 [Flow] Enable top DCM control >>>>>
3803 12:22:07.258106 [Flow] Enable top DCM control <<<<<
3804 12:22:07.260994 Enable DLL master slave shuffle
3805 12:22:07.267898 ==============================================================
3806 12:22:07.271371 Gating Mode config
3807 12:22:07.274281 ==============================================================
3808 12:22:07.277741 Config description:
3809 12:22:07.287566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3810 12:22:07.294343 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3811 12:22:07.297606 SELPH_MODE 0: By rank 1: By Phase
3812 12:22:07.304213 ==============================================================
3813 12:22:07.307966 GAT_TRACK_EN = 1
3814 12:22:07.310924 RX_GATING_MODE = 2
3815 12:22:07.311051 RX_GATING_TRACK_MODE = 2
3816 12:22:07.314408 SELPH_MODE = 1
3817 12:22:07.317966 PICG_EARLY_EN = 1
3818 12:22:07.321292 VALID_LAT_VALUE = 1
3819 12:22:07.327710 ==============================================================
3820 12:22:07.330814 Enter into Gating configuration >>>>
3821 12:22:07.334402 Exit from Gating configuration <<<<
3822 12:22:07.337535 Enter into DVFS_PRE_config >>>>>
3823 12:22:07.347727 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3824 12:22:07.351076 Exit from DVFS_PRE_config <<<<<
3825 12:22:07.354456 Enter into PICG configuration >>>>
3826 12:22:07.357681 Exit from PICG configuration <<<<
3827 12:22:07.360972 [RX_INPUT] configuration >>>>>
3828 12:22:07.364257 [RX_INPUT] configuration <<<<<
3829 12:22:07.367575 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3830 12:22:07.374354 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3831 12:22:07.380803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 12:22:07.384206 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 12:22:07.391150 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 12:22:07.397645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 12:22:07.401015 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3836 12:22:07.404790 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3837 12:22:07.411318 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3838 12:22:07.414341 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3839 12:22:07.417800 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3840 12:22:07.424760 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3841 12:22:07.427770 ===================================
3842 12:22:07.427854 LPDDR4 DRAM CONFIGURATION
3843 12:22:07.431404 ===================================
3844 12:22:07.434346 EX_ROW_EN[0] = 0x0
3845 12:22:07.434429 EX_ROW_EN[1] = 0x0
3846 12:22:07.437428 LP4Y_EN = 0x0
3847 12:22:07.441273 WORK_FSP = 0x0
3848 12:22:07.441373 WL = 0x2
3849 12:22:07.444342 RL = 0x2
3850 12:22:07.444424 BL = 0x2
3851 12:22:07.447774 RPST = 0x0
3852 12:22:07.447856 RD_PRE = 0x0
3853 12:22:07.450651 WR_PRE = 0x1
3854 12:22:07.450732 WR_PST = 0x0
3855 12:22:07.454188 DBI_WR = 0x0
3856 12:22:07.454270 DBI_RD = 0x0
3857 12:22:07.457336 OTF = 0x1
3858 12:22:07.461001 ===================================
3859 12:22:07.464261 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3860 12:22:07.467177 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3861 12:22:07.473932 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 12:22:07.477470 ===================================
3863 12:22:07.477569 LPDDR4 DRAM CONFIGURATION
3864 12:22:07.480508 ===================================
3865 12:22:07.483776 EX_ROW_EN[0] = 0x10
3866 12:22:07.486906 EX_ROW_EN[1] = 0x0
3867 12:22:07.487021 LP4Y_EN = 0x0
3868 12:22:07.490367 WORK_FSP = 0x0
3869 12:22:07.490455 WL = 0x2
3870 12:22:07.493940 RL = 0x2
3871 12:22:07.494021 BL = 0x2
3872 12:22:07.497413 RPST = 0x0
3873 12:22:07.497494 RD_PRE = 0x0
3874 12:22:07.500280 WR_PRE = 0x1
3875 12:22:07.500382 WR_PST = 0x0
3876 12:22:07.503766 DBI_WR = 0x0
3877 12:22:07.503873 DBI_RD = 0x0
3878 12:22:07.506892 OTF = 0x1
3879 12:22:07.510357 ===================================
3880 12:22:07.516978 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3881 12:22:07.520576 nWR fixed to 30
3882 12:22:07.520658 [ModeRegInit_LP4] CH0 RK0
3883 12:22:07.523473 [ModeRegInit_LP4] CH0 RK1
3884 12:22:07.527143 [ModeRegInit_LP4] CH1 RK0
3885 12:22:07.527250 [ModeRegInit_LP4] CH1 RK1
3886 12:22:07.530211 match AC timing 17
3887 12:22:07.533770 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3888 12:22:07.540271 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3889 12:22:07.543364 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3890 12:22:07.547126 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3891 12:22:07.553217 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3892 12:22:07.553318 ==
3893 12:22:07.556694 Dram Type= 6, Freq= 0, CH_0, rank 0
3894 12:22:07.560093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3895 12:22:07.560193 ==
3896 12:22:07.566890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3897 12:22:07.572944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3898 12:22:07.576365 [CA 0] Center 36 (5~67) winsize 63
3899 12:22:07.579705 [CA 1] Center 36 (5~67) winsize 63
3900 12:22:07.583249 [CA 2] Center 33 (3~64) winsize 62
3901 12:22:07.586789 [CA 3] Center 33 (2~64) winsize 63
3902 12:22:07.589624 [CA 4] Center 33 (2~64) winsize 63
3903 12:22:07.593399 [CA 5] Center 32 (2~63) winsize 62
3904 12:22:07.593500
3905 12:22:07.596489 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3906 12:22:07.596618
3907 12:22:07.599766 [CATrainingPosCal] consider 1 rank data
3908 12:22:07.603339 u2DelayCellTimex100 = 270/100 ps
3909 12:22:07.606574 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3910 12:22:07.609797 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3911 12:22:07.613556 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3912 12:22:07.616324 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3913 12:22:07.619943 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3914 12:22:07.623117 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3915 12:22:07.623203
3916 12:22:07.626775 CA PerBit enable=1, Macro0, CA PI delay=32
3917 12:22:07.629831
3918 12:22:07.629942 [CBTSetCACLKResult] CA Dly = 32
3919 12:22:07.633356 CS Dly: 4 (0~35)
3920 12:22:07.633438 ==
3921 12:22:07.636333 Dram Type= 6, Freq= 0, CH_0, rank 1
3922 12:22:07.639905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 12:22:07.640025 ==
3924 12:22:07.646507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 12:22:07.653200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 12:22:07.656218 [CA 0] Center 35 (5~66) winsize 62
3927 12:22:07.659953 [CA 1] Center 35 (5~66) winsize 62
3928 12:22:07.662828 [CA 2] Center 34 (3~65) winsize 63
3929 12:22:07.666373 [CA 3] Center 33 (3~64) winsize 62
3930 12:22:07.669433 [CA 4] Center 32 (2~63) winsize 62
3931 12:22:07.672963 [CA 5] Center 32 (2~63) winsize 62
3932 12:22:07.673081
3933 12:22:07.676290 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 12:22:07.676388
3935 12:22:07.679727 [CATrainingPosCal] consider 2 rank data
3936 12:22:07.682794 u2DelayCellTimex100 = 270/100 ps
3937 12:22:07.686087 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3938 12:22:07.689396 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3939 12:22:07.692845 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3940 12:22:07.696610 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3941 12:22:07.699477 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3942 12:22:07.703044 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3943 12:22:07.703142
3944 12:22:07.709516 CA PerBit enable=1, Macro0, CA PI delay=32
3945 12:22:07.709600
3946 12:22:07.709666 [CBTSetCACLKResult] CA Dly = 32
3947 12:22:07.713228 CS Dly: 4 (0~35)
3948 12:22:07.713328
3949 12:22:07.715973 ----->DramcWriteLeveling(PI) begin...
3950 12:22:07.716092 ==
3951 12:22:07.719434 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 12:22:07.722474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 12:22:07.722574 ==
3954 12:22:07.726015 Write leveling (Byte 0): 34 => 34
3955 12:22:07.729719 Write leveling (Byte 1): 31 => 31
3956 12:22:07.732882 DramcWriteLeveling(PI) end<-----
3957 12:22:07.732973
3958 12:22:07.733051 ==
3959 12:22:07.736360 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 12:22:07.739547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 12:22:07.743190 ==
3962 12:22:07.743274 [Gating] SW mode calibration
3963 12:22:07.752603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3964 12:22:07.756275 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3965 12:22:07.759206 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 12:22:07.765841 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 12:22:07.769495 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 12:22:07.772499 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (0 1)
3969 12:22:07.778927 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3970 12:22:07.782406 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 12:22:07.785971 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 12:22:07.792761 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 12:22:07.795710 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 12:22:07.799127 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 12:22:07.805610 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 12:22:07.809113 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
3977 12:22:07.812517 0 10 16 | B1->B0 | 2f2f 4646 | 0 0 | (1 1) (0 0)
3978 12:22:07.818782 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 12:22:07.822385 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 12:22:07.825506 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 12:22:07.832128 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 12:22:07.835709 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 12:22:07.838855 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 12:22:07.845887 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3985 12:22:07.849473 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 12:22:07.852622 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 12:22:07.856170 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 12:22:07.862244 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 12:22:07.865912 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 12:22:07.869024 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 12:22:07.875521 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 12:22:07.879047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 12:22:07.882585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:22:07.889295 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 12:22:07.892548 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:22:07.895813 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:22:07.902289 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:22:07.905686 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:22:07.908946 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:22:07.915647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:22:07.919207 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4002 12:22:07.921967 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 12:22:07.925650 Total UI for P1: 0, mck2ui 16
4004 12:22:07.928761 best dqsien dly found for B0: ( 0, 13, 16)
4005 12:22:07.932534 Total UI for P1: 0, mck2ui 16
4006 12:22:07.935618 best dqsien dly found for B1: ( 0, 13, 18)
4007 12:22:07.939147 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4008 12:22:07.941922 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4009 12:22:07.942031
4010 12:22:07.949042 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4011 12:22:07.952376 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4012 12:22:07.952481 [Gating] SW calibration Done
4013 12:22:07.955359 ==
4014 12:22:07.955458 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 12:22:07.961978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 12:22:07.962064 ==
4017 12:22:07.962131 RX Vref Scan: 0
4018 12:22:07.962194
4019 12:22:07.965664 RX Vref 0 -> 0, step: 1
4020 12:22:07.965749
4021 12:22:07.968691 RX Delay -230 -> 252, step: 16
4022 12:22:07.972183 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4023 12:22:07.975162 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4024 12:22:07.981830 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4025 12:22:07.985427 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4026 12:22:07.988614 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4027 12:22:07.992204 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4028 12:22:07.995232 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4029 12:22:08.001984 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4030 12:22:08.005428 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4031 12:22:08.008899 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4032 12:22:08.011788 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4033 12:22:08.018929 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4034 12:22:08.022331 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4035 12:22:08.025657 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4036 12:22:08.028839 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4037 12:22:08.031897 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4038 12:22:08.035453 ==
4039 12:22:08.039225 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 12:22:08.042079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 12:22:08.042189 ==
4042 12:22:08.042286 DQS Delay:
4043 12:22:08.045743 DQS0 = 0, DQS1 = 0
4044 12:22:08.045844 DQM Delay:
4045 12:22:08.048589 DQM0 = 54, DQM1 = 46
4046 12:22:08.048663 DQ Delay:
4047 12:22:08.051961 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4048 12:22:08.055403 DQ4 =49, DQ5 =49, DQ6 =65, DQ7 =65
4049 12:22:08.058584 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4050 12:22:08.061702 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4051 12:22:08.061813
4052 12:22:08.061909
4053 12:22:08.062006 ==
4054 12:22:08.065391 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 12:22:08.068556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 12:22:08.068645 ==
4057 12:22:08.068726
4058 12:22:08.068816
4059 12:22:08.072037 TX Vref Scan disable
4060 12:22:08.075060 == TX Byte 0 ==
4061 12:22:08.078794 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4062 12:22:08.081860 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4063 12:22:08.084870 == TX Byte 1 ==
4064 12:22:08.088458 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4065 12:22:08.092107 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4066 12:22:08.092186 ==
4067 12:22:08.095137 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 12:22:08.101675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 12:22:08.101779 ==
4070 12:22:08.101874
4071 12:22:08.101964
4072 12:22:08.102062 TX Vref Scan disable
4073 12:22:08.106205 == TX Byte 0 ==
4074 12:22:08.109114 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4075 12:22:08.112843 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4076 12:22:08.115740 == TX Byte 1 ==
4077 12:22:08.119504 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4078 12:22:08.123059 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4079 12:22:08.126037
4080 12:22:08.126137 [DATLAT]
4081 12:22:08.126229 Freq=600, CH0 RK0
4082 12:22:08.126322
4083 12:22:08.129441 DATLAT Default: 0x9
4084 12:22:08.129540 0, 0xFFFF, sum = 0
4085 12:22:08.132839 1, 0xFFFF, sum = 0
4086 12:22:08.132940 2, 0xFFFF, sum = 0
4087 12:22:08.135783 3, 0xFFFF, sum = 0
4088 12:22:08.135884 4, 0xFFFF, sum = 0
4089 12:22:08.139010 5, 0xFFFF, sum = 0
4090 12:22:08.142483 6, 0xFFFF, sum = 0
4091 12:22:08.142563 7, 0xFFFF, sum = 0
4092 12:22:08.142634 8, 0x0, sum = 1
4093 12:22:08.145856 9, 0x0, sum = 2
4094 12:22:08.145932 10, 0x0, sum = 3
4095 12:22:08.148992 11, 0x0, sum = 4
4096 12:22:08.149067 best_step = 9
4097 12:22:08.149129
4098 12:22:08.149189 ==
4099 12:22:08.152511 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 12:22:08.159097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 12:22:08.159183 ==
4102 12:22:08.159251 RX Vref Scan: 1
4103 12:22:08.159313
4104 12:22:08.162606 RX Vref 0 -> 0, step: 1
4105 12:22:08.162690
4106 12:22:08.165705 RX Delay -163 -> 252, step: 8
4107 12:22:08.165789
4108 12:22:08.169463 Set Vref, RX VrefLevel [Byte0]: 57
4109 12:22:08.172313 [Byte1]: 48
4110 12:22:08.172424
4111 12:22:08.175477 Final RX Vref Byte 0 = 57 to rank0
4112 12:22:08.178893 Final RX Vref Byte 1 = 48 to rank0
4113 12:22:08.182432 Final RX Vref Byte 0 = 57 to rank1
4114 12:22:08.185912 Final RX Vref Byte 1 = 48 to rank1==
4115 12:22:08.189391 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 12:22:08.192198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 12:22:08.192279 ==
4118 12:22:08.195900 DQS Delay:
4119 12:22:08.196003 DQS0 = 0, DQS1 = 0
4120 12:22:08.196097 DQM Delay:
4121 12:22:08.198992 DQM0 = 52, DQM1 = 45
4122 12:22:08.199089 DQ Delay:
4123 12:22:08.202503 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4124 12:22:08.205448 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4125 12:22:08.209249 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4126 12:22:08.212240 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4127 12:22:08.212344
4128 12:22:08.212437
4129 12:22:08.222100 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4130 12:22:08.225488 CH0 RK0: MR19=808, MR18=7164
4131 12:22:08.229043 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4132 12:22:08.229147
4133 12:22:08.235685 ----->DramcWriteLeveling(PI) begin...
4134 12:22:08.235768 ==
4135 12:22:08.238708 Dram Type= 6, Freq= 0, CH_0, rank 1
4136 12:22:08.241796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 12:22:08.241899 ==
4138 12:22:08.245290 Write leveling (Byte 0): 34 => 34
4139 12:22:08.248613 Write leveling (Byte 1): 31 => 31
4140 12:22:08.251837 DramcWriteLeveling(PI) end<-----
4141 12:22:08.251914
4142 12:22:08.251983 ==
4143 12:22:08.255258 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 12:22:08.258926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 12:22:08.259012 ==
4146 12:22:08.262369 [Gating] SW mode calibration
4147 12:22:08.269017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4148 12:22:08.272551 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4149 12:22:08.278743 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 12:22:08.282469 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 12:22:08.285497 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4152 12:22:08.291931 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4153 12:22:08.295812 0 9 16 | B1->B0 | 2525 2525 | 1 0 | (1 0) (1 1)
4154 12:22:08.298778 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 12:22:08.305384 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 12:22:08.309045 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 12:22:08.312620 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 12:22:08.318736 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 12:22:08.322293 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 12:22:08.325569 0 10 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
4161 12:22:08.332196 0 10 16 | B1->B0 | 4242 4444 | 0 0 | (1 1) (0 0)
4162 12:22:08.335554 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 12:22:08.338788 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 12:22:08.345395 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 12:22:08.348978 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 12:22:08.351949 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 12:22:08.358938 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 12:22:08.362019 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4169 12:22:08.365610 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 12:22:08.372416 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 12:22:08.375299 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 12:22:08.378887 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 12:22:08.382301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 12:22:08.388807 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 12:22:08.392208 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:22:08.395506 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:22:08.401963 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:22:08.405017 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 12:22:08.408587 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 12:22:08.415322 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:22:08.418246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:22:08.421903 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:22:08.428452 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:22:08.432014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4185 12:22:08.434860 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 12:22:08.438376 Total UI for P1: 0, mck2ui 16
4187 12:22:08.441736 best dqsien dly found for B0: ( 0, 13, 12)
4188 12:22:08.444878 Total UI for P1: 0, mck2ui 16
4189 12:22:08.448302 best dqsien dly found for B1: ( 0, 13, 12)
4190 12:22:08.451683 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4191 12:22:08.455187 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4192 12:22:08.458254
4193 12:22:08.461658 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4194 12:22:08.464994 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4195 12:22:08.468645 [Gating] SW calibration Done
4196 12:22:08.468744 ==
4197 12:22:08.471542 Dram Type= 6, Freq= 0, CH_0, rank 1
4198 12:22:08.475335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 12:22:08.475433 ==
4200 12:22:08.475524 RX Vref Scan: 0
4201 12:22:08.475654
4202 12:22:08.478206 RX Vref 0 -> 0, step: 1
4203 12:22:08.478299
4204 12:22:08.481649 RX Delay -230 -> 252, step: 16
4205 12:22:08.485241 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4206 12:22:08.488181 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4207 12:22:08.494796 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4208 12:22:08.498642 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4209 12:22:08.501405 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4210 12:22:08.505239 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4211 12:22:08.511683 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4212 12:22:08.515316 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4213 12:22:08.518082 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4214 12:22:08.521737 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4215 12:22:08.524770 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4216 12:22:08.531450 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4217 12:22:08.534866 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4218 12:22:08.538452 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4219 12:22:08.541601 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4220 12:22:08.548097 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4221 12:22:08.548202 ==
4222 12:22:08.552048 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 12:22:08.555031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 12:22:08.555127 ==
4225 12:22:08.555216 DQS Delay:
4226 12:22:08.558756 DQS0 = 0, DQS1 = 0
4227 12:22:08.558827 DQM Delay:
4228 12:22:08.561901 DQM0 = 50, DQM1 = 42
4229 12:22:08.561998 DQ Delay:
4230 12:22:08.565138 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4231 12:22:08.568397 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4232 12:22:08.571751 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4233 12:22:08.575242 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4234 12:22:08.575339
4235 12:22:08.575430
4236 12:22:08.575517 ==
4237 12:22:08.578204 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 12:22:08.581868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 12:22:08.581963 ==
4240 12:22:08.582052
4241 12:22:08.582137
4242 12:22:08.585452 TX Vref Scan disable
4243 12:22:08.588196 == TX Byte 0 ==
4244 12:22:08.591753 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4245 12:22:08.595069 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4246 12:22:08.598532 == TX Byte 1 ==
4247 12:22:08.601657 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4248 12:22:08.605261 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4249 12:22:08.605362 ==
4250 12:22:08.608851 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 12:22:08.615268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 12:22:08.615372 ==
4253 12:22:08.615465
4254 12:22:08.615553
4255 12:22:08.615659 TX Vref Scan disable
4256 12:22:08.619227 == TX Byte 0 ==
4257 12:22:08.622993 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4258 12:22:08.629454 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4259 12:22:08.629555 == TX Byte 1 ==
4260 12:22:08.632787 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4261 12:22:08.639227 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4262 12:22:08.639333
4263 12:22:08.639426 [DATLAT]
4264 12:22:08.639530 Freq=600, CH0 RK1
4265 12:22:08.639642
4266 12:22:08.642857 DATLAT Default: 0x9
4267 12:22:08.642952 0, 0xFFFF, sum = 0
4268 12:22:08.645999 1, 0xFFFF, sum = 0
4269 12:22:08.646099 2, 0xFFFF, sum = 0
4270 12:22:08.649704 3, 0xFFFF, sum = 0
4271 12:22:08.649802 4, 0xFFFF, sum = 0
4272 12:22:08.652603 5, 0xFFFF, sum = 0
4273 12:22:08.656394 6, 0xFFFF, sum = 0
4274 12:22:08.656559 7, 0xFFFF, sum = 0
4275 12:22:08.656652 8, 0x0, sum = 1
4276 12:22:08.659395 9, 0x0, sum = 2
4277 12:22:08.659490 10, 0x0, sum = 3
4278 12:22:08.662856 11, 0x0, sum = 4
4279 12:22:08.662931 best_step = 9
4280 12:22:08.662991
4281 12:22:08.663065 ==
4282 12:22:08.666052 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 12:22:08.672930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 12:22:08.673035 ==
4285 12:22:08.673127 RX Vref Scan: 0
4286 12:22:08.673214
4287 12:22:08.675909 RX Vref 0 -> 0, step: 1
4288 12:22:08.675978
4289 12:22:08.679161 RX Delay -163 -> 252, step: 8
4290 12:22:08.682846 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4291 12:22:08.685862 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4292 12:22:08.692805 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4293 12:22:08.695803 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4294 12:22:08.699152 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4295 12:22:08.702671 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4296 12:22:08.706286 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4297 12:22:08.712398 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4298 12:22:08.715964 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4299 12:22:08.719177 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4300 12:22:08.722363 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4301 12:22:08.729144 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4302 12:22:08.732231 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4303 12:22:08.735709 iDelay=205, Bit 13, Center 56 (-83 ~ 196) 280
4304 12:22:08.739188 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4305 12:22:08.742474 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4306 12:22:08.745772 ==
4307 12:22:08.745874 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 12:22:08.752541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 12:22:08.752626 ==
4310 12:22:08.752691 DQS Delay:
4311 12:22:08.755574 DQS0 = 0, DQS1 = 0
4312 12:22:08.755669 DQM Delay:
4313 12:22:08.759371 DQM0 = 54, DQM1 = 47
4314 12:22:08.759454 DQ Delay:
4315 12:22:08.762366 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4316 12:22:08.765981 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4317 12:22:08.768927 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4318 12:22:08.772623 DQ12 =52, DQ13 =56, DQ14 =56, DQ15 =52
4319 12:22:08.772707
4320 12:22:08.772773
4321 12:22:08.779362 [DQSOSCAuto] RK1, (LSB)MR18= 0x6829, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4322 12:22:08.782242 CH0 RK1: MR19=808, MR18=6829
4323 12:22:08.788920 CH0_RK1: MR19=0x808, MR18=0x6829, DQSOSC=390, MR23=63, INC=172, DEC=114
4324 12:22:08.792356 [RxdqsGatingPostProcess] freq 600
4325 12:22:08.795880 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4326 12:22:08.799199 Pre-setting of DQS Precalculation
4327 12:22:08.805664 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4328 12:22:08.805748 ==
4329 12:22:08.808965 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 12:22:08.812166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 12:22:08.812251 ==
4332 12:22:08.818515 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4333 12:22:08.825104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4334 12:22:08.828973 [CA 0] Center 35 (5~66) winsize 62
4335 12:22:08.831906 [CA 1] Center 35 (5~66) winsize 62
4336 12:22:08.835354 [CA 2] Center 34 (4~65) winsize 62
4337 12:22:08.838450 [CA 3] Center 34 (3~65) winsize 63
4338 12:22:08.841581 [CA 4] Center 34 (4~65) winsize 62
4339 12:22:08.845145 [CA 5] Center 33 (3~64) winsize 62
4340 12:22:08.845218
4341 12:22:08.848681 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4342 12:22:08.848784
4343 12:22:08.852102 [CATrainingPosCal] consider 1 rank data
4344 12:22:08.855411 u2DelayCellTimex100 = 270/100 ps
4345 12:22:08.858561 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4346 12:22:08.862076 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4347 12:22:08.865141 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4348 12:22:08.868238 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4349 12:22:08.871869 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4350 12:22:08.875526 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4351 12:22:08.875620
4352 12:22:08.881684 CA PerBit enable=1, Macro0, CA PI delay=33
4353 12:22:08.881768
4354 12:22:08.881835 [CBTSetCACLKResult] CA Dly = 33
4355 12:22:08.885309 CS Dly: 6 (0~37)
4356 12:22:08.885393 ==
4357 12:22:08.888331 Dram Type= 6, Freq= 0, CH_1, rank 1
4358 12:22:08.891486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 12:22:08.891574 ==
4360 12:22:08.898515 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4361 12:22:08.904673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4362 12:22:08.907964 [CA 0] Center 36 (5~67) winsize 63
4363 12:22:08.911652 [CA 1] Center 36 (5~67) winsize 63
4364 12:22:08.915119 [CA 2] Center 34 (4~65) winsize 62
4365 12:22:08.917984 [CA 3] Center 34 (4~65) winsize 62
4366 12:22:08.921643 [CA 4] Center 34 (4~65) winsize 62
4367 12:22:08.924761 [CA 5] Center 34 (3~65) winsize 63
4368 12:22:08.924843
4369 12:22:08.927958 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4370 12:22:08.928036
4371 12:22:08.931518 [CATrainingPosCal] consider 2 rank data
4372 12:22:08.934626 u2DelayCellTimex100 = 270/100 ps
4373 12:22:08.938217 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 12:22:08.941285 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4375 12:22:08.944801 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 12:22:08.947947 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 12:22:08.951622 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4378 12:22:08.958258 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 12:22:08.958342
4380 12:22:08.961149 CA PerBit enable=1, Macro0, CA PI delay=33
4381 12:22:08.961233
4382 12:22:08.964647 [CBTSetCACLKResult] CA Dly = 33
4383 12:22:08.964761 CS Dly: 6 (0~38)
4384 12:22:08.964857
4385 12:22:08.967953 ----->DramcWriteLeveling(PI) begin...
4386 12:22:08.968046 ==
4387 12:22:08.971669 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 12:22:08.974434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 12:22:08.978123 ==
4390 12:22:08.978230 Write leveling (Byte 0): 29 => 29
4391 12:22:08.981221 Write leveling (Byte 1): 30 => 30
4392 12:22:08.984340 DramcWriteLeveling(PI) end<-----
4393 12:22:08.984445
4394 12:22:08.984542 ==
4395 12:22:08.988188 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 12:22:08.994455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 12:22:08.994546 ==
4398 12:22:08.998182 [Gating] SW mode calibration
4399 12:22:09.004894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4400 12:22:09.008326 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4401 12:22:09.011319 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 12:22:09.017789 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 12:22:09.021173 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4404 12:22:09.024544 0 9 12 | B1->B0 | 3030 2c2c | 0 1 | (0 1) (1 0)
4405 12:22:09.030971 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 12:22:09.035022 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 12:22:09.037978 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 12:22:09.044385 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 12:22:09.047785 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 12:22:09.051255 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 12:22:09.058052 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4412 12:22:09.061054 0 10 12 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
4413 12:22:09.064823 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 12:22:09.071499 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 12:22:09.074351 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 12:22:09.077850 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 12:22:09.084559 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 12:22:09.087563 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 12:22:09.091330 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4420 12:22:09.098009 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4421 12:22:09.101033 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 12:22:09.104229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 12:22:09.111277 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 12:22:09.114294 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 12:22:09.117805 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 12:22:09.121292 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 12:22:09.127761 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:22:09.131291 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:22:09.134271 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:22:09.140797 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:22:09.144132 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:22:09.147747 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:22:09.154531 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:22:09.157760 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:22:09.161091 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4436 12:22:09.167742 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 12:22:09.167827 Total UI for P1: 0, mck2ui 16
4438 12:22:09.174281 best dqsien dly found for B0: ( 0, 13, 8)
4439 12:22:09.174371 Total UI for P1: 0, mck2ui 16
4440 12:22:09.181386 best dqsien dly found for B1: ( 0, 13, 10)
4441 12:22:09.184244 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4442 12:22:09.187808 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4443 12:22:09.187887
4444 12:22:09.191200 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4445 12:22:09.194225 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4446 12:22:09.197808 [Gating] SW calibration Done
4447 12:22:09.197912 ==
4448 12:22:09.200913 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 12:22:09.203995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 12:22:09.204069 ==
4451 12:22:09.207509 RX Vref Scan: 0
4452 12:22:09.207651
4453 12:22:09.207752 RX Vref 0 -> 0, step: 1
4454 12:22:09.207840
4455 12:22:09.211291 RX Delay -230 -> 252, step: 16
4456 12:22:09.217542 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4457 12:22:09.220460 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4458 12:22:09.224036 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4459 12:22:09.227163 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4460 12:22:09.230880 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4461 12:22:09.237453 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4462 12:22:09.240598 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4463 12:22:09.244265 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4464 12:22:09.247447 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4465 12:22:09.253866 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4466 12:22:09.257234 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4467 12:22:09.260790 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4468 12:22:09.263809 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4469 12:22:09.267078 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4470 12:22:09.273921 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4471 12:22:09.277167 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4472 12:22:09.277250 ==
4473 12:22:09.280649 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 12:22:09.283952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 12:22:09.284035 ==
4476 12:22:09.287138 DQS Delay:
4477 12:22:09.287223 DQS0 = 0, DQS1 = 0
4478 12:22:09.290423 DQM Delay:
4479 12:22:09.290505 DQM0 = 50, DQM1 = 49
4480 12:22:09.290571 DQ Delay:
4481 12:22:09.293534 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4482 12:22:09.297022 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4483 12:22:09.300558 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4484 12:22:09.303306 DQ12 =65, DQ13 =57, DQ14 =49, DQ15 =65
4485 12:22:09.303409
4486 12:22:09.303503
4487 12:22:09.306856 ==
4488 12:22:09.309842 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 12:22:09.313418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 12:22:09.313519 ==
4491 12:22:09.313610
4492 12:22:09.313697
4493 12:22:09.316588 TX Vref Scan disable
4494 12:22:09.316684 == TX Byte 0 ==
4495 12:22:09.323857 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4496 12:22:09.326765 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4497 12:22:09.326835 == TX Byte 1 ==
4498 12:22:09.333107 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4499 12:22:09.336563 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4500 12:22:09.336633 ==
4501 12:22:09.339629 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 12:22:09.343127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 12:22:09.343198 ==
4504 12:22:09.343260
4505 12:22:09.343320
4506 12:22:09.346657 TX Vref Scan disable
4507 12:22:09.350000 == TX Byte 0 ==
4508 12:22:09.353074 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4509 12:22:09.356351 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4510 12:22:09.360398 == TX Byte 1 ==
4511 12:22:09.363361 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 12:22:09.366587 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 12:22:09.366663
4514 12:22:09.370348 [DATLAT]
4515 12:22:09.370434 Freq=600, CH1 RK0
4516 12:22:09.370502
4517 12:22:09.373090 DATLAT Default: 0x9
4518 12:22:09.373181 0, 0xFFFF, sum = 0
4519 12:22:09.376714 1, 0xFFFF, sum = 0
4520 12:22:09.376798 2, 0xFFFF, sum = 0
4521 12:22:09.380174 3, 0xFFFF, sum = 0
4522 12:22:09.380283 4, 0xFFFF, sum = 0
4523 12:22:09.383206 5, 0xFFFF, sum = 0
4524 12:22:09.383290 6, 0xFFFF, sum = 0
4525 12:22:09.386643 7, 0xFFFF, sum = 0
4526 12:22:09.386726 8, 0x0, sum = 1
4527 12:22:09.389878 9, 0x0, sum = 2
4528 12:22:09.389962 10, 0x0, sum = 3
4529 12:22:09.393340 11, 0x0, sum = 4
4530 12:22:09.393456 best_step = 9
4531 12:22:09.393542
4532 12:22:09.393606 ==
4533 12:22:09.396574 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 12:22:09.399714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 12:22:09.399824 ==
4536 12:22:09.403163 RX Vref Scan: 1
4537 12:22:09.403263
4538 12:22:09.406519 RX Vref 0 -> 0, step: 1
4539 12:22:09.406615
4540 12:22:09.406704 RX Delay -163 -> 252, step: 8
4541 12:22:09.409495
4542 12:22:09.409596 Set Vref, RX VrefLevel [Byte0]: 54
4543 12:22:09.413202 [Byte1]: 46
4544 12:22:09.417616
4545 12:22:09.417716 Final RX Vref Byte 0 = 54 to rank0
4546 12:22:09.421213 Final RX Vref Byte 1 = 46 to rank0
4547 12:22:09.424290 Final RX Vref Byte 0 = 54 to rank1
4548 12:22:09.427826 Final RX Vref Byte 1 = 46 to rank1==
4549 12:22:09.430943 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 12:22:09.437600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 12:22:09.437676 ==
4552 12:22:09.437770 DQS Delay:
4553 12:22:09.437829 DQS0 = 0, DQS1 = 0
4554 12:22:09.441208 DQM Delay:
4555 12:22:09.441309 DQM0 = 48, DQM1 = 46
4556 12:22:09.444291 DQ Delay:
4557 12:22:09.448075 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4558 12:22:09.450724 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4559 12:22:09.454203 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4560 12:22:09.457712 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4561 12:22:09.457810
4562 12:22:09.457900
4563 12:22:09.464189 [DQSOSCAuto] RK0, (LSB)MR18= 0x456a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4564 12:22:09.468146 CH1 RK0: MR19=808, MR18=456A
4565 12:22:09.474455 CH1_RK0: MR19=0x808, MR18=0x456A, DQSOSC=389, MR23=63, INC=173, DEC=115
4566 12:22:09.474534
4567 12:22:09.478004 ----->DramcWriteLeveling(PI) begin...
4568 12:22:09.478109 ==
4569 12:22:09.481478 Dram Type= 6, Freq= 0, CH_1, rank 1
4570 12:22:09.484167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 12:22:09.484242 ==
4572 12:22:09.487840 Write leveling (Byte 0): 28 => 28
4573 12:22:09.491013 Write leveling (Byte 1): 30 => 30
4574 12:22:09.494521 DramcWriteLeveling(PI) end<-----
4575 12:22:09.494619
4576 12:22:09.494706 ==
4577 12:22:09.497413 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 12:22:09.500802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 12:22:09.500903 ==
4580 12:22:09.504153 [Gating] SW mode calibration
4581 12:22:09.510912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4582 12:22:09.517305 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4583 12:22:09.520882 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4584 12:22:09.527341 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 12:22:09.530489 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 12:22:09.533942 0 9 12 | B1->B0 | 2a2a 2e2e | 0 1 | (0 0) (1 0)
4587 12:22:09.540614 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 12:22:09.543708 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 12:22:09.547202 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 12:22:09.553767 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 12:22:09.556892 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 12:22:09.560193 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 12:22:09.566663 0 10 8 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
4594 12:22:09.570011 0 10 12 | B1->B0 | 3838 3737 | 0 1 | (1 1) (0 0)
4595 12:22:09.573323 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 12:22:09.580424 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 12:22:09.583948 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 12:22:09.587149 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 12:22:09.590356 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 12:22:09.596814 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 12:22:09.600542 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 12:22:09.603933 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4603 12:22:09.610261 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 12:22:09.613698 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 12:22:09.617147 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 12:22:09.623735 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 12:22:09.626799 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 12:22:09.630044 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 12:22:09.636879 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 12:22:09.640260 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:22:09.643719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:22:09.650333 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:22:09.653465 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:22:09.656958 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 12:22:09.663710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:22:09.666853 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:22:09.670312 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:22:09.673842 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4619 12:22:09.680458 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 12:22:09.683310 Total UI for P1: 0, mck2ui 16
4621 12:22:09.687002 best dqsien dly found for B0: ( 0, 13, 12)
4622 12:22:09.690569 Total UI for P1: 0, mck2ui 16
4623 12:22:09.693374 best dqsien dly found for B1: ( 0, 13, 12)
4624 12:22:09.696666 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4625 12:22:09.700012 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4626 12:22:09.700116
4627 12:22:09.703524 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4628 12:22:09.707261 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4629 12:22:09.710034 [Gating] SW calibration Done
4630 12:22:09.710138 ==
4631 12:22:09.713409 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 12:22:09.716769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 12:22:09.716874 ==
4634 12:22:09.720183 RX Vref Scan: 0
4635 12:22:09.720257
4636 12:22:09.723121 RX Vref 0 -> 0, step: 1
4637 12:22:09.723204
4638 12:22:09.723267 RX Delay -230 -> 252, step: 16
4639 12:22:09.729871 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4640 12:22:09.733607 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4641 12:22:09.736946 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4642 12:22:09.739859 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4643 12:22:09.746548 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4644 12:22:09.750374 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4645 12:22:09.753630 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4646 12:22:09.756645 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4647 12:22:09.759990 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4648 12:22:09.766616 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4649 12:22:09.770074 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4650 12:22:09.773529 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4651 12:22:09.776455 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4652 12:22:09.783495 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4653 12:22:09.786825 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4654 12:22:09.790031 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4655 12:22:09.790137 ==
4656 12:22:09.793698 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 12:22:09.796451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 12:22:09.800238 ==
4659 12:22:09.800364 DQS Delay:
4660 12:22:09.800463 DQS0 = 0, DQS1 = 0
4661 12:22:09.802973 DQM Delay:
4662 12:22:09.803043 DQM0 = 49, DQM1 = 46
4663 12:22:09.806193 DQ Delay:
4664 12:22:09.806289 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4665 12:22:09.810107 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4666 12:22:09.813112 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4667 12:22:09.816507 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4668 12:22:09.816582
4669 12:22:09.819520
4670 12:22:09.819640 ==
4671 12:22:09.822866 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 12:22:09.826286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 12:22:09.826359 ==
4674 12:22:09.826423
4675 12:22:09.826512
4676 12:22:09.829579 TX Vref Scan disable
4677 12:22:09.829661 == TX Byte 0 ==
4678 12:22:09.836296 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4679 12:22:09.839785 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4680 12:22:09.839863 == TX Byte 1 ==
4681 12:22:09.846302 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4682 12:22:09.849770 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4683 12:22:09.849843 ==
4684 12:22:09.852842 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 12:22:09.856700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 12:22:09.856774 ==
4687 12:22:09.856843
4688 12:22:09.856902
4689 12:22:09.860072 TX Vref Scan disable
4690 12:22:09.863029 == TX Byte 0 ==
4691 12:22:09.866385 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4692 12:22:09.869879 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4693 12:22:09.873153 == TX Byte 1 ==
4694 12:22:09.876726 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4695 12:22:09.879712 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4696 12:22:09.879787
4697 12:22:09.883309 [DATLAT]
4698 12:22:09.883383 Freq=600, CH1 RK1
4699 12:22:09.883445
4700 12:22:09.886943 DATLAT Default: 0x9
4701 12:22:09.887016 0, 0xFFFF, sum = 0
4702 12:22:09.889692 1, 0xFFFF, sum = 0
4703 12:22:09.889767 2, 0xFFFF, sum = 0
4704 12:22:09.893158 3, 0xFFFF, sum = 0
4705 12:22:09.893235 4, 0xFFFF, sum = 0
4706 12:22:09.896561 5, 0xFFFF, sum = 0
4707 12:22:09.896633 6, 0xFFFF, sum = 0
4708 12:22:09.899764 7, 0xFFFF, sum = 0
4709 12:22:09.899840 8, 0x0, sum = 1
4710 12:22:09.902785 9, 0x0, sum = 2
4711 12:22:09.902886 10, 0x0, sum = 3
4712 12:22:09.906322 11, 0x0, sum = 4
4713 12:22:09.906421 best_step = 9
4714 12:22:09.906512
4715 12:22:09.906599 ==
4716 12:22:09.909951 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 12:22:09.912686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 12:22:09.916001 ==
4719 12:22:09.916100 RX Vref Scan: 0
4720 12:22:09.916189
4721 12:22:09.919318 RX Vref 0 -> 0, step: 1
4722 12:22:09.919416
4723 12:22:09.922728 RX Delay -163 -> 252, step: 8
4724 12:22:09.925765 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4725 12:22:09.929190 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4726 12:22:09.935927 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4727 12:22:09.939513 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4728 12:22:09.942643 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4729 12:22:09.946177 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4730 12:22:09.949187 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4731 12:22:09.955645 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4732 12:22:09.959200 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4733 12:22:09.962698 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4734 12:22:09.965997 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4735 12:22:09.972288 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4736 12:22:09.975802 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4737 12:22:09.978799 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4738 12:22:09.982616 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4739 12:22:09.985911 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4740 12:22:09.988811 ==
4741 12:22:09.988886 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 12:22:09.996083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 12:22:09.996161 ==
4744 12:22:09.996224 DQS Delay:
4745 12:22:09.999140 DQS0 = 0, DQS1 = 0
4746 12:22:09.999243 DQM Delay:
4747 12:22:10.002639 DQM0 = 48, DQM1 = 44
4748 12:22:10.002742 DQ Delay:
4749 12:22:10.005414 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4750 12:22:10.009207 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4751 12:22:10.012298 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4752 12:22:10.015737 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4753 12:22:10.015807
4754 12:22:10.015906
4755 12:22:10.022309 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4756 12:22:10.025454 CH1 RK1: MR19=808, MR18=6C23
4757 12:22:10.032166 CH1_RK1: MR19=0x808, MR18=0x6C23, DQSOSC=389, MR23=63, INC=173, DEC=115
4758 12:22:10.035625 [RxdqsGatingPostProcess] freq 600
4759 12:22:10.038867 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4760 12:22:10.042286 Pre-setting of DQS Precalculation
4761 12:22:10.048801 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4762 12:22:10.055403 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4763 12:22:10.061964 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4764 12:22:10.062045
4765 12:22:10.062110
4766 12:22:10.065525 [Calibration Summary] 1200 Mbps
4767 12:22:10.065600 CH 0, Rank 0
4768 12:22:10.069114 SW Impedance : PASS
4769 12:22:10.072075 DUTY Scan : NO K
4770 12:22:10.072175 ZQ Calibration : PASS
4771 12:22:10.075544 Jitter Meter : NO K
4772 12:22:10.078905 CBT Training : PASS
4773 12:22:10.078982 Write leveling : PASS
4774 12:22:10.082189 RX DQS gating : PASS
4775 12:22:10.085265 RX DQ/DQS(RDDQC) : PASS
4776 12:22:10.085341 TX DQ/DQS : PASS
4777 12:22:10.089134 RX DATLAT : PASS
4778 12:22:10.091977 RX DQ/DQS(Engine): PASS
4779 12:22:10.092053 TX OE : NO K
4780 12:22:10.095512 All Pass.
4781 12:22:10.095650
4782 12:22:10.095716 CH 0, Rank 1
4783 12:22:10.098636 SW Impedance : PASS
4784 12:22:10.098740 DUTY Scan : NO K
4785 12:22:10.102198 ZQ Calibration : PASS
4786 12:22:10.105659 Jitter Meter : NO K
4787 12:22:10.105760 CBT Training : PASS
4788 12:22:10.109271 Write leveling : PASS
4789 12:22:10.109349 RX DQS gating : PASS
4790 12:22:10.111996 RX DQ/DQS(RDDQC) : PASS
4791 12:22:10.115744 TX DQ/DQS : PASS
4792 12:22:10.115848 RX DATLAT : PASS
4793 12:22:10.119053 RX DQ/DQS(Engine): PASS
4794 12:22:10.122074 TX OE : NO K
4795 12:22:10.122180 All Pass.
4796 12:22:10.122272
4797 12:22:10.122361 CH 1, Rank 0
4798 12:22:10.125711 SW Impedance : PASS
4799 12:22:10.128708 DUTY Scan : NO K
4800 12:22:10.128813 ZQ Calibration : PASS
4801 12:22:10.132192 Jitter Meter : NO K
4802 12:22:10.135552 CBT Training : PASS
4803 12:22:10.135674 Write leveling : PASS
4804 12:22:10.138776 RX DQS gating : PASS
4805 12:22:10.142591 RX DQ/DQS(RDDQC) : PASS
4806 12:22:10.142692 TX DQ/DQS : PASS
4807 12:22:10.145685 RX DATLAT : PASS
4808 12:22:10.145778 RX DQ/DQS(Engine): PASS
4809 12:22:10.149136 TX OE : NO K
4810 12:22:10.149208 All Pass.
4811 12:22:10.149268
4812 12:22:10.152061 CH 1, Rank 1
4813 12:22:10.152130 SW Impedance : PASS
4814 12:22:10.155705 DUTY Scan : NO K
4815 12:22:10.159123 ZQ Calibration : PASS
4816 12:22:10.159216 Jitter Meter : NO K
4817 12:22:10.162269 CBT Training : PASS
4818 12:22:10.165755 Write leveling : PASS
4819 12:22:10.165849 RX DQS gating : PASS
4820 12:22:10.168806 RX DQ/DQS(RDDQC) : PASS
4821 12:22:10.171930 TX DQ/DQS : PASS
4822 12:22:10.172023 RX DATLAT : PASS
4823 12:22:10.175423 RX DQ/DQS(Engine): PASS
4824 12:22:10.179048 TX OE : NO K
4825 12:22:10.179146 All Pass.
4826 12:22:10.179234
4827 12:22:10.179320 DramC Write-DBI off
4828 12:22:10.182026 PER_BANK_REFRESH: Hybrid Mode
4829 12:22:10.185273 TX_TRACKING: ON
4830 12:22:10.191807 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4831 12:22:10.195314 [FAST_K] Save calibration result to emmc
4832 12:22:10.202227 dramc_set_vcore_voltage set vcore to 662500
4833 12:22:10.202325 Read voltage for 933, 3
4834 12:22:10.205626 Vio18 = 0
4835 12:22:10.205728 Vcore = 662500
4836 12:22:10.205828 Vdram = 0
4837 12:22:10.208863 Vddq = 0
4838 12:22:10.208933 Vmddr = 0
4839 12:22:10.212217 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4840 12:22:10.218253 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4841 12:22:10.221587 MEM_TYPE=3, freq_sel=17
4842 12:22:10.225309 sv_algorithm_assistance_LP4_1600
4843 12:22:10.228483 ============ PULL DRAM RESETB DOWN ============
4844 12:22:10.231805 ========== PULL DRAM RESETB DOWN end =========
4845 12:22:10.235352 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4846 12:22:10.238247 ===================================
4847 12:22:10.241700 LPDDR4 DRAM CONFIGURATION
4848 12:22:10.244929 ===================================
4849 12:22:10.248662 EX_ROW_EN[0] = 0x0
4850 12:22:10.248739 EX_ROW_EN[1] = 0x0
4851 12:22:10.251838 LP4Y_EN = 0x0
4852 12:22:10.251916 WORK_FSP = 0x0
4853 12:22:10.255031 WL = 0x3
4854 12:22:10.255106 RL = 0x3
4855 12:22:10.258714 BL = 0x2
4856 12:22:10.258817 RPST = 0x0
4857 12:22:10.261768 RD_PRE = 0x0
4858 12:22:10.261870 WR_PRE = 0x1
4859 12:22:10.265279 WR_PST = 0x0
4860 12:22:10.265357 DBI_WR = 0x0
4861 12:22:10.268237 DBI_RD = 0x0
4862 12:22:10.272111 OTF = 0x1
4863 12:22:10.274934 ===================================
4864 12:22:10.275035 ===================================
4865 12:22:10.278276 ANA top config
4866 12:22:10.281851 ===================================
4867 12:22:10.285446 DLL_ASYNC_EN = 0
4868 12:22:10.285522 ALL_SLAVE_EN = 1
4869 12:22:10.288416 NEW_RANK_MODE = 1
4870 12:22:10.291751 DLL_IDLE_MODE = 1
4871 12:22:10.295360 LP45_APHY_COMB_EN = 1
4872 12:22:10.298441 TX_ODT_DIS = 1
4873 12:22:10.298545 NEW_8X_MODE = 1
4874 12:22:10.301751 ===================================
4875 12:22:10.305314 ===================================
4876 12:22:10.308269 data_rate = 1866
4877 12:22:10.311904 CKR = 1
4878 12:22:10.314939 DQ_P2S_RATIO = 8
4879 12:22:10.318385 ===================================
4880 12:22:10.321829 CA_P2S_RATIO = 8
4881 12:22:10.321931 DQ_CA_OPEN = 0
4882 12:22:10.324979 DQ_SEMI_OPEN = 0
4883 12:22:10.328455 CA_SEMI_OPEN = 0
4884 12:22:10.331810 CA_FULL_RATE = 0
4885 12:22:10.335184 DQ_CKDIV4_EN = 1
4886 12:22:10.338441 CA_CKDIV4_EN = 1
4887 12:22:10.338540 CA_PREDIV_EN = 0
4888 12:22:10.342257 PH8_DLY = 0
4889 12:22:10.345361 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4890 12:22:10.348623 DQ_AAMCK_DIV = 4
4891 12:22:10.351707 CA_AAMCK_DIV = 4
4892 12:22:10.355136 CA_ADMCK_DIV = 4
4893 12:22:10.355207 DQ_TRACK_CA_EN = 0
4894 12:22:10.358419 CA_PICK = 933
4895 12:22:10.361737 CA_MCKIO = 933
4896 12:22:10.364922 MCKIO_SEMI = 0
4897 12:22:10.368323 PLL_FREQ = 3732
4898 12:22:10.371730 DQ_UI_PI_RATIO = 32
4899 12:22:10.374812 CA_UI_PI_RATIO = 0
4900 12:22:10.378426 ===================================
4901 12:22:10.381345 ===================================
4902 12:22:10.381418 memory_type:LPDDR4
4903 12:22:10.384751 GP_NUM : 10
4904 12:22:10.387853 SRAM_EN : 1
4905 12:22:10.387929 MD32_EN : 0
4906 12:22:10.391322 ===================================
4907 12:22:10.394268 [ANA_INIT] >>>>>>>>>>>>>>
4908 12:22:10.397702 <<<<<< [CONFIGURE PHASE]: ANA_TX
4909 12:22:10.401308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4910 12:22:10.404399 ===================================
4911 12:22:10.407833 data_rate = 1866,PCW = 0X8f00
4912 12:22:10.411415 ===================================
4913 12:22:10.414439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4914 12:22:10.418096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 12:22:10.424286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 12:22:10.427992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4917 12:22:10.430869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4918 12:22:10.434213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4919 12:22:10.437927 [ANA_INIT] flow start
4920 12:22:10.440935 [ANA_INIT] PLL >>>>>>>>
4921 12:22:10.441032 [ANA_INIT] PLL <<<<<<<<
4922 12:22:10.444638 [ANA_INIT] MIDPI >>>>>>>>
4923 12:22:10.447851 [ANA_INIT] MIDPI <<<<<<<<
4924 12:22:10.451260 [ANA_INIT] DLL >>>>>>>>
4925 12:22:10.451363 [ANA_INIT] flow end
4926 12:22:10.454305 ============ LP4 DIFF to SE enter ============
4927 12:22:10.461059 ============ LP4 DIFF to SE exit ============
4928 12:22:10.461158 [ANA_INIT] <<<<<<<<<<<<<
4929 12:22:10.464094 [Flow] Enable top DCM control >>>>>
4930 12:22:10.467571 [Flow] Enable top DCM control <<<<<
4931 12:22:10.470660 Enable DLL master slave shuffle
4932 12:22:10.477732 ==============================================================
4933 12:22:10.477811 Gating Mode config
4934 12:22:10.484289 ==============================================================
4935 12:22:10.487903 Config description:
4936 12:22:10.497333 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4937 12:22:10.503963 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4938 12:22:10.507310 SELPH_MODE 0: By rank 1: By Phase
4939 12:22:10.514055 ==============================================================
4940 12:22:10.517458 GAT_TRACK_EN = 1
4941 12:22:10.517531 RX_GATING_MODE = 2
4942 12:22:10.520422 RX_GATING_TRACK_MODE = 2
4943 12:22:10.523932 SELPH_MODE = 1
4944 12:22:10.527318 PICG_EARLY_EN = 1
4945 12:22:10.530199 VALID_LAT_VALUE = 1
4946 12:22:10.537473 ==============================================================
4947 12:22:10.540191 Enter into Gating configuration >>>>
4948 12:22:10.543700 Exit from Gating configuration <<<<
4949 12:22:10.547368 Enter into DVFS_PRE_config >>>>>
4950 12:22:10.556943 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4951 12:22:10.560774 Exit from DVFS_PRE_config <<<<<
4952 12:22:10.563578 Enter into PICG configuration >>>>
4953 12:22:10.566991 Exit from PICG configuration <<<<
4954 12:22:10.570395 [RX_INPUT] configuration >>>>>
4955 12:22:10.573584 [RX_INPUT] configuration <<<<<
4956 12:22:10.577108 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4957 12:22:10.583873 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4958 12:22:10.590456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4959 12:22:10.593555 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4960 12:22:10.599927 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4961 12:22:10.606700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4962 12:22:10.610095 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4963 12:22:10.613658 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4964 12:22:10.620476 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4965 12:22:10.623512 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4966 12:22:10.626972 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4967 12:22:10.633434 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4968 12:22:10.636967 ===================================
4969 12:22:10.637070 LPDDR4 DRAM CONFIGURATION
4970 12:22:10.640152 ===================================
4971 12:22:10.643487 EX_ROW_EN[0] = 0x0
4972 12:22:10.647040 EX_ROW_EN[1] = 0x0
4973 12:22:10.647127 LP4Y_EN = 0x0
4974 12:22:10.649983 WORK_FSP = 0x0
4975 12:22:10.650087 WL = 0x3
4976 12:22:10.653560 RL = 0x3
4977 12:22:10.653632 BL = 0x2
4978 12:22:10.657228 RPST = 0x0
4979 12:22:10.657299 RD_PRE = 0x0
4980 12:22:10.660241 WR_PRE = 0x1
4981 12:22:10.660345 WR_PST = 0x0
4982 12:22:10.663354 DBI_WR = 0x0
4983 12:22:10.663432 DBI_RD = 0x0
4984 12:22:10.666872 OTF = 0x1
4985 12:22:10.669954 ===================================
4986 12:22:10.673647 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4987 12:22:10.676612 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4988 12:22:10.683564 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 12:22:10.686648 ===================================
4990 12:22:10.686729 LPDDR4 DRAM CONFIGURATION
4991 12:22:10.690250 ===================================
4992 12:22:10.693274 EX_ROW_EN[0] = 0x10
4993 12:22:10.693355 EX_ROW_EN[1] = 0x0
4994 12:22:10.697131 LP4Y_EN = 0x0
4995 12:22:10.697212 WORK_FSP = 0x0
4996 12:22:10.700024 WL = 0x3
4997 12:22:10.703382 RL = 0x3
4998 12:22:10.703463 BL = 0x2
4999 12:22:10.706829 RPST = 0x0
5000 12:22:10.706910 RD_PRE = 0x0
5001 12:22:10.710006 WR_PRE = 0x1
5002 12:22:10.710088 WR_PST = 0x0
5003 12:22:10.713412 DBI_WR = 0x0
5004 12:22:10.713517 DBI_RD = 0x0
5005 12:22:10.716800 OTF = 0x1
5006 12:22:10.720221 ===================================
5007 12:22:10.723557 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5008 12:22:10.728749 nWR fixed to 30
5009 12:22:10.731967 [ModeRegInit_LP4] CH0 RK0
5010 12:22:10.732041 [ModeRegInit_LP4] CH0 RK1
5011 12:22:10.735511 [ModeRegInit_LP4] CH1 RK0
5012 12:22:10.739009 [ModeRegInit_LP4] CH1 RK1
5013 12:22:10.739091 match AC timing 9
5014 12:22:10.745428 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5015 12:22:10.749264 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5016 12:22:10.752092 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5017 12:22:10.758865 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5018 12:22:10.762103 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5019 12:22:10.762218 ==
5020 12:22:10.765177 Dram Type= 6, Freq= 0, CH_0, rank 0
5021 12:22:10.768710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5022 12:22:10.768813 ==
5023 12:22:10.775243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5024 12:22:10.781677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5025 12:22:10.785318 [CA 0] Center 37 (6~68) winsize 63
5026 12:22:10.788732 [CA 1] Center 37 (6~68) winsize 63
5027 12:22:10.792252 [CA 2] Center 34 (4~65) winsize 62
5028 12:22:10.795127 [CA 3] Center 34 (3~65) winsize 63
5029 12:22:10.798240 [CA 4] Center 33 (3~64) winsize 62
5030 12:22:10.801892 [CA 5] Center 32 (2~62) winsize 61
5031 12:22:10.801973
5032 12:22:10.805198 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5033 12:22:10.805281
5034 12:22:10.808149 [CATrainingPosCal] consider 1 rank data
5035 12:22:10.811735 u2DelayCellTimex100 = 270/100 ps
5036 12:22:10.815352 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5037 12:22:10.818823 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5038 12:22:10.821996 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5039 12:22:10.825232 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5040 12:22:10.828253 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5041 12:22:10.834901 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5042 12:22:10.835016
5043 12:22:10.838314 CA PerBit enable=1, Macro0, CA PI delay=32
5044 12:22:10.838396
5045 12:22:10.841570 [CBTSetCACLKResult] CA Dly = 32
5046 12:22:10.841652 CS Dly: 5 (0~36)
5047 12:22:10.841717 ==
5048 12:22:10.844964 Dram Type= 6, Freq= 0, CH_0, rank 1
5049 12:22:10.848106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5050 12:22:10.851308 ==
5051 12:22:10.854565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5052 12:22:10.861500 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5053 12:22:10.864776 [CA 0] Center 37 (6~68) winsize 63
5054 12:22:10.868126 [CA 1] Center 37 (7~68) winsize 62
5055 12:22:10.871112 [CA 2] Center 34 (4~65) winsize 62
5056 12:22:10.874639 [CA 3] Center 34 (3~65) winsize 63
5057 12:22:10.878283 [CA 4] Center 33 (2~64) winsize 63
5058 12:22:10.881233 [CA 5] Center 32 (2~62) winsize 61
5059 12:22:10.881316
5060 12:22:10.884823 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5061 12:22:10.884906
5062 12:22:10.887990 [CATrainingPosCal] consider 2 rank data
5063 12:22:10.891499 u2DelayCellTimex100 = 270/100 ps
5064 12:22:10.894411 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5065 12:22:10.898074 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5066 12:22:10.901057 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5067 12:22:10.907722 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5068 12:22:10.911194 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5069 12:22:10.914953 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5070 12:22:10.915034
5071 12:22:10.917838 CA PerBit enable=1, Macro0, CA PI delay=32
5072 12:22:10.917920
5073 12:22:10.921234 [CBTSetCACLKResult] CA Dly = 32
5074 12:22:10.921317 CS Dly: 5 (0~37)
5075 12:22:10.921382
5076 12:22:10.924866 ----->DramcWriteLeveling(PI) begin...
5077 12:22:10.924949 ==
5078 12:22:10.927970 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 12:22:10.934350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 12:22:10.934433 ==
5081 12:22:10.937854 Write leveling (Byte 0): 31 => 31
5082 12:22:10.941459 Write leveling (Byte 1): 29 => 29
5083 12:22:10.941541 DramcWriteLeveling(PI) end<-----
5084 12:22:10.941605
5085 12:22:10.944863 ==
5086 12:22:10.944944 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 12:22:10.951317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 12:22:10.951398 ==
5089 12:22:10.954675 [Gating] SW mode calibration
5090 12:22:10.961750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5091 12:22:10.964595 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5092 12:22:10.971334 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5093 12:22:10.974672 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 12:22:10.977755 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 12:22:10.984571 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 12:22:10.988282 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 12:22:10.991282 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 12:22:10.998350 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5099 12:22:11.001144 0 14 28 | B1->B0 | 3434 2828 | 0 0 | (0 1) (1 1)
5100 12:22:11.004802 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5101 12:22:11.008315 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 12:22:11.014780 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 12:22:11.018052 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 12:22:11.021425 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 12:22:11.028081 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 12:22:11.031327 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5107 12:22:11.034283 0 15 28 | B1->B0 | 2424 3d3c | 0 1 | (0 0) (0 0)
5108 12:22:11.041501 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5109 12:22:11.044886 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 12:22:11.047800 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 12:22:11.055022 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 12:22:11.058044 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 12:22:11.061485 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 12:22:11.068049 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 12:22:11.071086 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5116 12:22:11.074586 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5117 12:22:11.081274 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 12:22:11.084419 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 12:22:11.088216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 12:22:11.094652 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 12:22:11.097948 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 12:22:11.100925 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 12:22:11.107720 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 12:22:11.111216 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 12:22:11.114804 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:22:11.121239 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:22:11.124277 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:22:11.128057 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:22:11.131086 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:22:11.137556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5131 12:22:11.141284 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5132 12:22:11.144168 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 12:22:11.147749 Total UI for P1: 0, mck2ui 16
5134 12:22:11.150640 best dqsien dly found for B0: ( 1, 2, 26)
5135 12:22:11.154535 Total UI for P1: 0, mck2ui 16
5136 12:22:11.157397 best dqsien dly found for B1: ( 1, 2, 30)
5137 12:22:11.161111 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5138 12:22:11.167230 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5139 12:22:11.167313
5140 12:22:11.171091 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5141 12:22:11.174719 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5142 12:22:11.177645 [Gating] SW calibration Done
5143 12:22:11.177728 ==
5144 12:22:11.181254 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 12:22:11.184214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 12:22:11.184297 ==
5147 12:22:11.184362 RX Vref Scan: 0
5148 12:22:11.187733
5149 12:22:11.187815 RX Vref 0 -> 0, step: 1
5150 12:22:11.187881
5151 12:22:11.190674 RX Delay -80 -> 252, step: 8
5152 12:22:11.194112 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5153 12:22:11.197179 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5154 12:22:11.204190 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5155 12:22:11.207366 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5156 12:22:11.210542 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5157 12:22:11.214478 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5158 12:22:11.217209 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5159 12:22:11.220863 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5160 12:22:11.227278 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5161 12:22:11.230688 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5162 12:22:11.233802 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5163 12:22:11.237318 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5164 12:22:11.240215 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5165 12:22:11.243863 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5166 12:22:11.250299 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5167 12:22:11.254047 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5168 12:22:11.254151 ==
5169 12:22:11.256921 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 12:22:11.260481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 12:22:11.260560 ==
5172 12:22:11.263925 DQS Delay:
5173 12:22:11.264012 DQS0 = 0, DQS1 = 0
5174 12:22:11.264075 DQM Delay:
5175 12:22:11.267412 DQM0 = 104, DQM1 = 96
5176 12:22:11.267484 DQ Delay:
5177 12:22:11.270318 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5178 12:22:11.273817 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5179 12:22:11.277160 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5180 12:22:11.280370 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5181 12:22:11.280479
5182 12:22:11.280575
5183 12:22:11.283576 ==
5184 12:22:11.283701 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 12:22:11.290855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 12:22:11.290938 ==
5187 12:22:11.291002
5188 12:22:11.291062
5189 12:22:11.293549 TX Vref Scan disable
5190 12:22:11.293617 == TX Byte 0 ==
5191 12:22:11.297175 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5192 12:22:11.303406 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5193 12:22:11.303480 == TX Byte 1 ==
5194 12:22:11.306709 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5195 12:22:11.313755 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5196 12:22:11.313834 ==
5197 12:22:11.316874 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 12:22:11.320122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 12:22:11.320207 ==
5200 12:22:11.320273
5201 12:22:11.320333
5202 12:22:11.323330 TX Vref Scan disable
5203 12:22:11.326542 == TX Byte 0 ==
5204 12:22:11.330161 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5205 12:22:11.333431 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5206 12:22:11.336756 == TX Byte 1 ==
5207 12:22:11.340376 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5208 12:22:11.343326 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5209 12:22:11.343408
5210 12:22:11.343497 [DATLAT]
5211 12:22:11.346970 Freq=933, CH0 RK0
5212 12:22:11.347052
5213 12:22:11.350532 DATLAT Default: 0xd
5214 12:22:11.350615 0, 0xFFFF, sum = 0
5215 12:22:11.353398 1, 0xFFFF, sum = 0
5216 12:22:11.353482 2, 0xFFFF, sum = 0
5217 12:22:11.356981 3, 0xFFFF, sum = 0
5218 12:22:11.357064 4, 0xFFFF, sum = 0
5219 12:22:11.360116 5, 0xFFFF, sum = 0
5220 12:22:11.360200 6, 0xFFFF, sum = 0
5221 12:22:11.363553 7, 0xFFFF, sum = 0
5222 12:22:11.363660 8, 0xFFFF, sum = 0
5223 12:22:11.366615 9, 0xFFFF, sum = 0
5224 12:22:11.366698 10, 0x0, sum = 1
5225 12:22:11.370109 11, 0x0, sum = 2
5226 12:22:11.370193 12, 0x0, sum = 3
5227 12:22:11.373480 13, 0x0, sum = 4
5228 12:22:11.373564 best_step = 11
5229 12:22:11.373629
5230 12:22:11.373690 ==
5231 12:22:11.376514 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 12:22:11.380069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 12:22:11.383158 ==
5234 12:22:11.383239 RX Vref Scan: 1
5235 12:22:11.383305
5236 12:22:11.386953 RX Vref 0 -> 0, step: 1
5237 12:22:11.387035
5238 12:22:11.390281 RX Delay -45 -> 252, step: 4
5239 12:22:11.390362
5240 12:22:11.390427 Set Vref, RX VrefLevel [Byte0]: 57
5241 12:22:11.393325 [Byte1]: 48
5242 12:22:11.398382
5243 12:22:11.398464 Final RX Vref Byte 0 = 57 to rank0
5244 12:22:11.401394 Final RX Vref Byte 1 = 48 to rank0
5245 12:22:11.405022 Final RX Vref Byte 0 = 57 to rank1
5246 12:22:11.408163 Final RX Vref Byte 1 = 48 to rank1==
5247 12:22:11.411427 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 12:22:11.418168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 12:22:11.418249 ==
5250 12:22:11.418314 DQS Delay:
5251 12:22:11.421502 DQS0 = 0, DQS1 = 0
5252 12:22:11.421575 DQM Delay:
5253 12:22:11.421640 DQM0 = 105, DQM1 = 95
5254 12:22:11.424647 DQ Delay:
5255 12:22:11.428106 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5256 12:22:11.431395 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =112
5257 12:22:11.435058 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5258 12:22:11.438290 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =104
5259 12:22:11.438360
5260 12:22:11.438423
5261 12:22:11.444678 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5262 12:22:11.448322 CH0 RK0: MR19=505, MR18=322A
5263 12:22:11.454992 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5264 12:22:11.455069
5265 12:22:11.458358 ----->DramcWriteLeveling(PI) begin...
5266 12:22:11.458429 ==
5267 12:22:11.461284 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 12:22:11.464818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 12:22:11.464891 ==
5270 12:22:11.468090 Write leveling (Byte 0): 34 => 34
5271 12:22:11.471432 Write leveling (Byte 1): 30 => 30
5272 12:22:11.474333 DramcWriteLeveling(PI) end<-----
5273 12:22:11.474400
5274 12:22:11.474459 ==
5275 12:22:11.477901 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 12:22:11.484454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 12:22:11.484525 ==
5278 12:22:11.484585 [Gating] SW mode calibration
5279 12:22:11.494280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5280 12:22:11.497934 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5281 12:22:11.501083 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 12:22:11.507742 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 12:22:11.510950 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 12:22:11.514182 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 12:22:11.520876 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 12:22:11.524024 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 12:22:11.527709 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 12:22:11.534187 0 14 28 | B1->B0 | 2727 2a2a | 1 0 | (1 0) (0 0)
5289 12:22:11.537749 0 15 0 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
5290 12:22:11.540950 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 12:22:11.547571 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 12:22:11.550750 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 12:22:11.554347 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 12:22:11.561125 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 12:22:11.564505 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5296 12:22:11.567525 0 15 28 | B1->B0 | 3838 3737 | 0 0 | (0 0) (1 1)
5297 12:22:11.574578 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5298 12:22:11.577491 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 12:22:11.580904 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 12:22:11.587501 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 12:22:11.591272 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 12:22:11.594057 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 12:22:11.600629 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 12:22:11.604240 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5305 12:22:11.607727 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 12:22:11.614150 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 12:22:11.617603 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 12:22:11.620598 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 12:22:11.624228 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 12:22:11.630816 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 12:22:11.634322 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 12:22:11.637316 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 12:22:11.644465 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 12:22:11.647661 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:22:11.650742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 12:22:11.657705 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 12:22:11.660860 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:22:11.664155 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:22:11.670807 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:22:11.673835 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5321 12:22:11.677415 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 12:22:11.680882 Total UI for P1: 0, mck2ui 16
5323 12:22:11.683790 best dqsien dly found for B0: ( 1, 2, 28)
5324 12:22:11.687346 Total UI for P1: 0, mck2ui 16
5325 12:22:11.690363 best dqsien dly found for B1: ( 1, 2, 28)
5326 12:22:11.693990 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5327 12:22:11.697589 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5328 12:22:11.697671
5329 12:22:11.704001 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5330 12:22:11.707511 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5331 12:22:11.707616 [Gating] SW calibration Done
5332 12:22:11.710434 ==
5333 12:22:11.710516 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 12:22:11.717619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 12:22:11.717707 ==
5336 12:22:11.717772 RX Vref Scan: 0
5337 12:22:11.717832
5338 12:22:11.720610 RX Vref 0 -> 0, step: 1
5339 12:22:11.720692
5340 12:22:11.723636 RX Delay -80 -> 252, step: 8
5341 12:22:11.726991 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5342 12:22:11.730626 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5343 12:22:11.733854 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5344 12:22:11.740586 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5345 12:22:11.744063 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5346 12:22:11.746843 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5347 12:22:11.750482 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5348 12:22:11.754058 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5349 12:22:11.757315 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5350 12:22:11.763881 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5351 12:22:11.767408 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5352 12:22:11.770657 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5353 12:22:11.773955 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5354 12:22:11.777201 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5355 12:22:11.780396 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5356 12:22:11.787149 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5357 12:22:11.787232 ==
5358 12:22:11.790589 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 12:22:11.793681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 12:22:11.793764 ==
5361 12:22:11.793829 DQS Delay:
5362 12:22:11.796982 DQS0 = 0, DQS1 = 0
5363 12:22:11.797064 DQM Delay:
5364 12:22:11.800479 DQM0 = 105, DQM1 = 92
5365 12:22:11.800561 DQ Delay:
5366 12:22:11.803567 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =103
5367 12:22:11.807080 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5368 12:22:11.810036 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87
5369 12:22:11.813587 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5370 12:22:11.813694
5371 12:22:11.813789
5372 12:22:11.813850 ==
5373 12:22:11.817248 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 12:22:11.823352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 12:22:11.823455 ==
5376 12:22:11.823537
5377 12:22:11.823682
5378 12:22:11.823783 TX Vref Scan disable
5379 12:22:11.826767 == TX Byte 0 ==
5380 12:22:11.830234 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5381 12:22:11.833917 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5382 12:22:11.837052 == TX Byte 1 ==
5383 12:22:11.840427 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5384 12:22:11.843712 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5385 12:22:11.846978 ==
5386 12:22:11.850206 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 12:22:11.853479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 12:22:11.853562 ==
5389 12:22:11.853627
5390 12:22:11.853688
5391 12:22:11.856768 TX Vref Scan disable
5392 12:22:11.856850 == TX Byte 0 ==
5393 12:22:11.863548 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5394 12:22:11.867076 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5395 12:22:11.867158 == TX Byte 1 ==
5396 12:22:11.873532 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5397 12:22:11.877131 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5398 12:22:11.877213
5399 12:22:11.877279 [DATLAT]
5400 12:22:11.879935 Freq=933, CH0 RK1
5401 12:22:11.880018
5402 12:22:11.880083 DATLAT Default: 0xb
5403 12:22:11.883357 0, 0xFFFF, sum = 0
5404 12:22:11.883440 1, 0xFFFF, sum = 0
5405 12:22:11.886885 2, 0xFFFF, sum = 0
5406 12:22:11.886969 3, 0xFFFF, sum = 0
5407 12:22:11.890161 4, 0xFFFF, sum = 0
5408 12:22:11.890244 5, 0xFFFF, sum = 0
5409 12:22:11.893209 6, 0xFFFF, sum = 0
5410 12:22:11.893293 7, 0xFFFF, sum = 0
5411 12:22:11.896790 8, 0xFFFF, sum = 0
5412 12:22:11.900031 9, 0xFFFF, sum = 0
5413 12:22:11.900114 10, 0x0, sum = 1
5414 12:22:11.900181 11, 0x0, sum = 2
5415 12:22:11.903295 12, 0x0, sum = 3
5416 12:22:11.903384 13, 0x0, sum = 4
5417 12:22:11.906692 best_step = 11
5418 12:22:11.906774
5419 12:22:11.906838 ==
5420 12:22:11.909897 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 12:22:11.913525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 12:22:11.913608 ==
5423 12:22:11.916411 RX Vref Scan: 0
5424 12:22:11.916494
5425 12:22:11.916558 RX Vref 0 -> 0, step: 1
5426 12:22:11.920243
5427 12:22:11.920325 RX Delay -53 -> 252, step: 4
5428 12:22:11.927283 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5429 12:22:11.930846 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5430 12:22:11.933678 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5431 12:22:11.937274 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5432 12:22:11.940496 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5433 12:22:11.947490 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5434 12:22:11.950814 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5435 12:22:11.953906 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5436 12:22:11.957285 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5437 12:22:11.960471 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5438 12:22:11.966910 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5439 12:22:11.970509 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5440 12:22:11.973821 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5441 12:22:11.977407 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5442 12:22:11.980158 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5443 12:22:11.986982 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5444 12:22:11.987065 ==
5445 12:22:11.990514 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 12:22:11.993981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 12:22:11.994064 ==
5448 12:22:11.994129 DQS Delay:
5449 12:22:11.997155 DQS0 = 0, DQS1 = 0
5450 12:22:11.997237 DQM Delay:
5451 12:22:12.000574 DQM0 = 104, DQM1 = 93
5452 12:22:12.000657 DQ Delay:
5453 12:22:12.003480 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =100
5454 12:22:12.006993 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5455 12:22:12.010349 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5456 12:22:12.013906 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5457 12:22:12.014017
5458 12:22:12.014084
5459 12:22:12.023512 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5460 12:22:12.023622 CH0 RK1: MR19=505, MR18=2C04
5461 12:22:12.030440 CH0_RK1: MR19=0x505, MR18=0x2C04, DQSOSC=408, MR23=63, INC=65, DEC=43
5462 12:22:12.033390 [RxdqsGatingPostProcess] freq 933
5463 12:22:12.039896 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5464 12:22:12.043508 best DQS0 dly(2T, 0.5T) = (0, 10)
5465 12:22:12.047348 best DQS1 dly(2T, 0.5T) = (0, 10)
5466 12:22:12.050326 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5467 12:22:12.053534 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5468 12:22:12.057000 best DQS0 dly(2T, 0.5T) = (0, 10)
5469 12:22:12.057075 best DQS1 dly(2T, 0.5T) = (0, 10)
5470 12:22:12.059971 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5471 12:22:12.063510 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5472 12:22:12.066651 Pre-setting of DQS Precalculation
5473 12:22:12.073522 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5474 12:22:12.073593 ==
5475 12:22:12.076587 Dram Type= 6, Freq= 0, CH_1, rank 0
5476 12:22:12.080186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 12:22:12.080259 ==
5478 12:22:12.086580 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5479 12:22:12.093741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5480 12:22:12.096743 [CA 0] Center 36 (6~67) winsize 62
5481 12:22:12.100331 [CA 1] Center 36 (6~67) winsize 62
5482 12:22:12.103145 [CA 2] Center 34 (4~65) winsize 62
5483 12:22:12.106739 [CA 3] Center 34 (4~64) winsize 61
5484 12:22:12.109619 [CA 4] Center 34 (4~64) winsize 61
5485 12:22:12.113279 [CA 5] Center 33 (3~64) winsize 62
5486 12:22:12.113347
5487 12:22:12.116379 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5488 12:22:12.116452
5489 12:22:12.119754 [CATrainingPosCal] consider 1 rank data
5490 12:22:12.123271 u2DelayCellTimex100 = 270/100 ps
5491 12:22:12.126396 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5492 12:22:12.129519 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5493 12:22:12.132976 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5494 12:22:12.136364 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5495 12:22:12.139755 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5496 12:22:12.142801 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5497 12:22:12.142885
5498 12:22:12.149906 CA PerBit enable=1, Macro0, CA PI delay=33
5499 12:22:12.149989
5500 12:22:12.150055 [CBTSetCACLKResult] CA Dly = 33
5501 12:22:12.153002 CS Dly: 7 (0~38)
5502 12:22:12.153084 ==
5503 12:22:12.156285 Dram Type= 6, Freq= 0, CH_1, rank 1
5504 12:22:12.159841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 12:22:12.159925 ==
5506 12:22:12.166654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 12:22:12.173068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5508 12:22:12.176432 [CA 0] Center 36 (6~67) winsize 62
5509 12:22:12.179513 [CA 1] Center 37 (6~68) winsize 63
5510 12:22:12.183007 [CA 2] Center 35 (5~66) winsize 62
5511 12:22:12.186555 [CA 3] Center 34 (4~65) winsize 62
5512 12:22:12.190004 [CA 4] Center 34 (4~65) winsize 62
5513 12:22:12.193267 [CA 5] Center 33 (3~64) winsize 62
5514 12:22:12.193349
5515 12:22:12.196217 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5516 12:22:12.196295
5517 12:22:12.199549 [CATrainingPosCal] consider 2 rank data
5518 12:22:12.202838 u2DelayCellTimex100 = 270/100 ps
5519 12:22:12.206199 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 12:22:12.209446 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 12:22:12.213250 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5522 12:22:12.216142 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5523 12:22:12.219408 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 12:22:12.222839 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5525 12:22:12.222923
5526 12:22:12.229230 CA PerBit enable=1, Macro0, CA PI delay=33
5527 12:22:12.229312
5528 12:22:12.232899 [CBTSetCACLKResult] CA Dly = 33
5529 12:22:12.232982 CS Dly: 8 (0~40)
5530 12:22:12.233047
5531 12:22:12.236472 ----->DramcWriteLeveling(PI) begin...
5532 12:22:12.236556 ==
5533 12:22:12.239564 Dram Type= 6, Freq= 0, CH_1, rank 0
5534 12:22:12.242840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 12:22:12.242923 ==
5536 12:22:12.245948 Write leveling (Byte 0): 28 => 28
5537 12:22:12.249290 Write leveling (Byte 1): 29 => 29
5538 12:22:12.252625 DramcWriteLeveling(PI) end<-----
5539 12:22:12.252707
5540 12:22:12.252772 ==
5541 12:22:12.256330 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 12:22:12.262791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 12:22:12.262878 ==
5544 12:22:12.262943 [Gating] SW mode calibration
5545 12:22:12.272982 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5546 12:22:12.275802 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5547 12:22:12.279298 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 12:22:12.286139 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 12:22:12.289104 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 12:22:12.292712 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 12:22:12.299421 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 12:22:12.302825 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 12:22:12.305666 0 14 24 | B1->B0 | 3333 2d2d | 1 1 | (1 0) (1 0)
5554 12:22:12.312377 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5555 12:22:12.315450 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 12:22:12.319001 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 12:22:12.325833 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 12:22:12.329373 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 12:22:12.332894 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 12:22:12.339439 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 12:22:12.342229 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5562 12:22:12.345807 0 15 28 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5563 12:22:12.352506 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 12:22:12.355695 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 12:22:12.359096 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 12:22:12.365808 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 12:22:12.368759 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 12:22:12.372362 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 12:22:12.378955 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5570 12:22:12.382050 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5571 12:22:12.385547 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 12:22:12.392348 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 12:22:12.395259 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 12:22:12.398757 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 12:22:12.405523 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 12:22:12.408484 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 12:22:12.411954 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 12:22:12.418420 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:22:12.421662 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:22:12.425232 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:22:12.428744 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:22:12.434931 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:22:12.438787 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:22:12.441873 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:22:12.448681 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5586 12:22:12.451654 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 12:22:12.455136 Total UI for P1: 0, mck2ui 16
5588 12:22:12.458855 best dqsien dly found for B0: ( 1, 2, 24)
5589 12:22:12.462152 Total UI for P1: 0, mck2ui 16
5590 12:22:12.465387 best dqsien dly found for B1: ( 1, 2, 24)
5591 12:22:12.468453 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5592 12:22:12.471618 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5593 12:22:12.471704
5594 12:22:12.475227 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5595 12:22:12.478824 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5596 12:22:12.481653 [Gating] SW calibration Done
5597 12:22:12.481721 ==
5598 12:22:12.485219 Dram Type= 6, Freq= 0, CH_1, rank 0
5599 12:22:12.488763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 12:22:12.492238 ==
5601 12:22:12.492309 RX Vref Scan: 0
5602 12:22:12.492370
5603 12:22:12.495704 RX Vref 0 -> 0, step: 1
5604 12:22:12.495781
5605 12:22:12.498709 RX Delay -80 -> 252, step: 8
5606 12:22:12.502095 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5607 12:22:12.504976 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5608 12:22:12.508820 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5609 12:22:12.511570 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5610 12:22:12.515336 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5611 12:22:12.521439 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5612 12:22:12.524871 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5613 12:22:12.528325 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5614 12:22:12.531766 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5615 12:22:12.535235 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5616 12:22:12.538335 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5617 12:22:12.545129 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5618 12:22:12.548665 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5619 12:22:12.551814 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5620 12:22:12.554832 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5621 12:22:12.558226 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5622 12:22:12.561669 ==
5623 12:22:12.564819 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 12:22:12.568126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 12:22:12.568200 ==
5626 12:22:12.568262 DQS Delay:
5627 12:22:12.571519 DQS0 = 0, DQS1 = 0
5628 12:22:12.571598 DQM Delay:
5629 12:22:12.574638 DQM0 = 102, DQM1 = 97
5630 12:22:12.574715 DQ Delay:
5631 12:22:12.578329 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5632 12:22:12.581711 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5633 12:22:12.584592 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5634 12:22:12.587946 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5635 12:22:12.588019
5636 12:22:12.588083
5637 12:22:12.588141 ==
5638 12:22:12.591191 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 12:22:12.595153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 12:22:12.597991 ==
5641 12:22:12.598064
5642 12:22:12.598124
5643 12:22:12.598182 TX Vref Scan disable
5644 12:22:12.601361 == TX Byte 0 ==
5645 12:22:12.605211 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5646 12:22:12.608100 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5647 12:22:12.611094 == TX Byte 1 ==
5648 12:22:12.614624 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5649 12:22:12.617933 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5650 12:22:12.618004 ==
5651 12:22:12.621383 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 12:22:12.628066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 12:22:12.628142 ==
5654 12:22:12.628211
5655 12:22:12.628269
5656 12:22:12.628325 TX Vref Scan disable
5657 12:22:12.632027 == TX Byte 0 ==
5658 12:22:12.635346 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5659 12:22:12.638893 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5660 12:22:12.642424 == TX Byte 1 ==
5661 12:22:12.645579 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5662 12:22:12.648843 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5663 12:22:12.652259
5664 12:22:12.652330 [DATLAT]
5665 12:22:12.652397 Freq=933, CH1 RK0
5666 12:22:12.652472
5667 12:22:12.655783 DATLAT Default: 0xd
5668 12:22:12.655854 0, 0xFFFF, sum = 0
5669 12:22:12.658808 1, 0xFFFF, sum = 0
5670 12:22:12.658878 2, 0xFFFF, sum = 0
5671 12:22:12.662107 3, 0xFFFF, sum = 0
5672 12:22:12.662183 4, 0xFFFF, sum = 0
5673 12:22:12.665755 5, 0xFFFF, sum = 0
5674 12:22:12.669155 6, 0xFFFF, sum = 0
5675 12:22:12.669226 7, 0xFFFF, sum = 0
5676 12:22:12.672594 8, 0xFFFF, sum = 0
5677 12:22:12.672667 9, 0xFFFF, sum = 0
5678 12:22:12.675377 10, 0x0, sum = 1
5679 12:22:12.675443 11, 0x0, sum = 2
5680 12:22:12.675503 12, 0x0, sum = 3
5681 12:22:12.679017 13, 0x0, sum = 4
5682 12:22:12.679097 best_step = 11
5683 12:22:12.679158
5684 12:22:12.679217 ==
5685 12:22:12.681944 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 12:22:12.688747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 12:22:12.688825 ==
5688 12:22:12.688889 RX Vref Scan: 1
5689 12:22:12.688956
5690 12:22:12.691933 RX Vref 0 -> 0, step: 1
5691 12:22:12.692001
5692 12:22:12.695309 RX Delay -45 -> 252, step: 4
5693 12:22:12.695374
5694 12:22:12.698551 Set Vref, RX VrefLevel [Byte0]: 54
5695 12:22:12.702128 [Byte1]: 46
5696 12:22:12.702201
5697 12:22:12.705205 Final RX Vref Byte 0 = 54 to rank0
5698 12:22:12.708750 Final RX Vref Byte 1 = 46 to rank0
5699 12:22:12.712328 Final RX Vref Byte 0 = 54 to rank1
5700 12:22:12.715379 Final RX Vref Byte 1 = 46 to rank1==
5701 12:22:12.718894 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 12:22:12.722101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 12:22:12.722174 ==
5704 12:22:12.725566 DQS Delay:
5705 12:22:12.725639 DQS0 = 0, DQS1 = 0
5706 12:22:12.728830 DQM Delay:
5707 12:22:12.728902 DQM0 = 103, DQM1 = 99
5708 12:22:12.728971 DQ Delay:
5709 12:22:12.732284 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5710 12:22:12.735723 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5711 12:22:12.738542 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =94
5712 12:22:12.745549 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =110
5713 12:22:12.745630
5714 12:22:12.745693
5715 12:22:12.751997 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5716 12:22:12.755572 CH1 RK0: MR19=505, MR18=1931
5717 12:22:12.762098 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5718 12:22:12.762170
5719 12:22:12.765527 ----->DramcWriteLeveling(PI) begin...
5720 12:22:12.765597 ==
5721 12:22:12.768432 Dram Type= 6, Freq= 0, CH_1, rank 1
5722 12:22:12.771905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 12:22:12.771976 ==
5724 12:22:12.775252 Write leveling (Byte 0): 27 => 27
5725 12:22:12.778460 Write leveling (Byte 1): 27 => 27
5726 12:22:12.781986 DramcWriteLeveling(PI) end<-----
5727 12:22:12.782065
5728 12:22:12.782127 ==
5729 12:22:12.785137 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 12:22:12.788722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 12:22:12.788794 ==
5732 12:22:12.792148 [Gating] SW mode calibration
5733 12:22:12.798848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5734 12:22:12.805494 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5735 12:22:12.808829 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 12:22:12.812393 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 12:22:12.818591 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 12:22:12.822219 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 12:22:12.825110 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 12:22:12.832134 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 12:22:12.834926 0 14 24 | B1->B0 | 2d2d 3030 | 1 1 | (1 0) (1 1)
5742 12:22:12.838502 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 12:22:12.845129 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 12:22:12.848635 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 12:22:12.851558 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 12:22:12.858006 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 12:22:12.861475 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 12:22:12.864986 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 12:22:12.871685 0 15 24 | B1->B0 | 3b3b 2424 | 0 0 | (0 0) (0 0)
5750 12:22:12.875254 0 15 28 | B1->B0 | 4646 3b3b | 0 1 | (0 0) (1 1)
5751 12:22:12.878068 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 12:22:12.885116 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 12:22:12.888311 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 12:22:12.891309 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 12:22:12.898172 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 12:22:12.901138 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 12:22:12.904408 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5758 12:22:12.911004 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 12:22:12.914336 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 12:22:12.917926 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 12:22:12.924333 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 12:22:12.927818 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 12:22:12.930937 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 12:22:12.937937 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 12:22:12.940817 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 12:22:12.944567 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 12:22:12.950964 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 12:22:12.954410 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 12:22:12.957441 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 12:22:12.964281 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:22:12.967749 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:22:12.970954 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:22:12.977959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5774 12:22:12.980776 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5775 12:22:12.984218 Total UI for P1: 0, mck2ui 16
5776 12:22:12.987809 best dqsien dly found for B1: ( 1, 2, 24)
5777 12:22:12.990744 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 12:22:12.994305 Total UI for P1: 0, mck2ui 16
5779 12:22:12.997592 best dqsien dly found for B0: ( 1, 2, 28)
5780 12:22:13.000809 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5781 12:22:13.004204 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5782 12:22:13.004279
5783 12:22:13.007558 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5784 12:22:13.013917 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5785 12:22:13.013996 [Gating] SW calibration Done
5786 12:22:13.014060 ==
5787 12:22:13.017538 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 12:22:13.024301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 12:22:13.024378 ==
5790 12:22:13.024442 RX Vref Scan: 0
5791 12:22:13.024510
5792 12:22:13.027660 RX Vref 0 -> 0, step: 1
5793 12:22:13.027732
5794 12:22:13.030825 RX Delay -80 -> 252, step: 8
5795 12:22:13.034398 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5796 12:22:13.037336 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5797 12:22:13.040783 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5798 12:22:13.044348 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5799 12:22:13.050501 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5800 12:22:13.054098 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5801 12:22:13.057354 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5802 12:22:13.060901 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5803 12:22:13.064099 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5804 12:22:13.067432 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5805 12:22:13.073773 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5806 12:22:13.077199 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5807 12:22:13.080790 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5808 12:22:13.084018 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5809 12:22:13.090812 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5810 12:22:13.094220 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5811 12:22:13.094296 ==
5812 12:22:13.097241 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 12:22:13.100796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 12:22:13.100870 ==
5815 12:22:13.100930 DQS Delay:
5816 12:22:13.103785 DQS0 = 0, DQS1 = 0
5817 12:22:13.103857 DQM Delay:
5818 12:22:13.107097 DQM0 = 104, DQM1 = 98
5819 12:22:13.107163 DQ Delay:
5820 12:22:13.110661 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103
5821 12:22:13.113945 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5822 12:22:13.117289 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =91
5823 12:22:13.120562 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5824 12:22:13.120644
5825 12:22:13.120707
5826 12:22:13.123748 ==
5827 12:22:13.127245 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 12:22:13.130306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 12:22:13.130378 ==
5830 12:22:13.130446
5831 12:22:13.130504
5832 12:22:13.133668 TX Vref Scan disable
5833 12:22:13.133738 == TX Byte 0 ==
5834 12:22:13.137003 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5835 12:22:13.143806 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5836 12:22:13.143886 == TX Byte 1 ==
5837 12:22:13.147315 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5838 12:22:13.154102 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5839 12:22:13.154176 ==
5840 12:22:13.156938 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 12:22:13.160304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 12:22:13.160375 ==
5843 12:22:13.160435
5844 12:22:13.160505
5845 12:22:13.163879 TX Vref Scan disable
5846 12:22:13.166929 == TX Byte 0 ==
5847 12:22:13.170273 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5848 12:22:13.173675 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5849 12:22:13.177167 == TX Byte 1 ==
5850 12:22:13.180193 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5851 12:22:13.183829 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5852 12:22:13.183902
5853 12:22:13.183963 [DATLAT]
5854 12:22:13.186878 Freq=933, CH1 RK1
5855 12:22:13.186946
5856 12:22:13.190377 DATLAT Default: 0xb
5857 12:22:13.190445 0, 0xFFFF, sum = 0
5858 12:22:13.193914 1, 0xFFFF, sum = 0
5859 12:22:13.193983 2, 0xFFFF, sum = 0
5860 12:22:13.197518 3, 0xFFFF, sum = 0
5861 12:22:13.197585 4, 0xFFFF, sum = 0
5862 12:22:13.200339 5, 0xFFFF, sum = 0
5863 12:22:13.200407 6, 0xFFFF, sum = 0
5864 12:22:13.204076 7, 0xFFFF, sum = 0
5865 12:22:13.204145 8, 0xFFFF, sum = 0
5866 12:22:13.207007 9, 0xFFFF, sum = 0
5867 12:22:13.207072 10, 0x0, sum = 1
5868 12:22:13.210638 11, 0x0, sum = 2
5869 12:22:13.210705 12, 0x0, sum = 3
5870 12:22:13.214050 13, 0x0, sum = 4
5871 12:22:13.214121 best_step = 11
5872 12:22:13.214180
5873 12:22:13.214237 ==
5874 12:22:13.216877 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 12:22:13.220214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 12:22:13.220286 ==
5877 12:22:13.223739 RX Vref Scan: 0
5878 12:22:13.223807
5879 12:22:13.227040 RX Vref 0 -> 0, step: 1
5880 12:22:13.227114
5881 12:22:13.227174 RX Delay -45 -> 252, step: 4
5882 12:22:13.234911 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5883 12:22:13.238183 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5884 12:22:13.241432 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5885 12:22:13.244779 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5886 12:22:13.247809 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5887 12:22:13.254807 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5888 12:22:13.258060 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5889 12:22:13.261633 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5890 12:22:13.264806 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5891 12:22:13.268277 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5892 12:22:13.271270 iDelay=203, Bit 10, Center 98 (15 ~ 182) 168
5893 12:22:13.278389 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5894 12:22:13.281317 iDelay=203, Bit 12, Center 110 (27 ~ 194) 168
5895 12:22:13.285014 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5896 12:22:13.287808 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5897 12:22:13.294911 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5898 12:22:13.294982 ==
5899 12:22:13.298151 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 12:22:13.301676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 12:22:13.301745 ==
5902 12:22:13.301805 DQS Delay:
5903 12:22:13.304558 DQS0 = 0, DQS1 = 0
5904 12:22:13.304692 DQM Delay:
5905 12:22:13.308231 DQM0 = 104, DQM1 = 100
5906 12:22:13.308309 DQ Delay:
5907 12:22:13.311269 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5908 12:22:13.314719 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5909 12:22:13.318117 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =92
5910 12:22:13.321221 DQ12 =110, DQ13 =104, DQ14 =106, DQ15 =110
5911 12:22:13.321294
5912 12:22:13.321363
5913 12:22:13.331364 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5914 12:22:13.331440 CH1 RK1: MR19=505, MR18=2D01
5915 12:22:13.337897 CH1_RK1: MR19=0x505, MR18=0x2D01, DQSOSC=407, MR23=63, INC=65, DEC=43
5916 12:22:13.341304 [RxdqsGatingPostProcess] freq 933
5917 12:22:13.348444 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5918 12:22:13.351813 best DQS0 dly(2T, 0.5T) = (0, 10)
5919 12:22:13.354542 best DQS1 dly(2T, 0.5T) = (0, 10)
5920 12:22:13.357767 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5921 12:22:13.361185 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5922 12:22:13.364595 best DQS0 dly(2T, 0.5T) = (0, 10)
5923 12:22:13.364671 best DQS1 dly(2T, 0.5T) = (0, 10)
5924 12:22:13.368095 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5925 12:22:13.371324 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5926 12:22:13.375092 Pre-setting of DQS Precalculation
5927 12:22:13.381527 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5928 12:22:13.387943 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5929 12:22:13.394601 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5930 12:22:13.394686
5931 12:22:13.394750
5932 12:22:13.398035 [Calibration Summary] 1866 Mbps
5933 12:22:13.398106 CH 0, Rank 0
5934 12:22:13.401187 SW Impedance : PASS
5935 12:22:13.404624 DUTY Scan : NO K
5936 12:22:13.404694 ZQ Calibration : PASS
5937 12:22:13.408388 Jitter Meter : NO K
5938 12:22:13.411219 CBT Training : PASS
5939 12:22:13.411295 Write leveling : PASS
5940 12:22:13.414938 RX DQS gating : PASS
5941 12:22:13.418184 RX DQ/DQS(RDDQC) : PASS
5942 12:22:13.418257 TX DQ/DQS : PASS
5943 12:22:13.421164 RX DATLAT : PASS
5944 12:22:13.424795 RX DQ/DQS(Engine): PASS
5945 12:22:13.424877 TX OE : NO K
5946 12:22:13.427775 All Pass.
5947 12:22:13.427849
5948 12:22:13.427910 CH 0, Rank 1
5949 12:22:13.431344 SW Impedance : PASS
5950 12:22:13.431439 DUTY Scan : NO K
5951 12:22:13.434763 ZQ Calibration : PASS
5952 12:22:13.438053 Jitter Meter : NO K
5953 12:22:13.438123 CBT Training : PASS
5954 12:22:13.441266 Write leveling : PASS
5955 12:22:13.441346 RX DQS gating : PASS
5956 12:22:13.444810 RX DQ/DQS(RDDQC) : PASS
5957 12:22:13.448006 TX DQ/DQS : PASS
5958 12:22:13.448087 RX DATLAT : PASS
5959 12:22:13.451494 RX DQ/DQS(Engine): PASS
5960 12:22:13.454721 TX OE : NO K
5961 12:22:13.454802 All Pass.
5962 12:22:13.454866
5963 12:22:13.454926 CH 1, Rank 0
5964 12:22:13.457732 SW Impedance : PASS
5965 12:22:13.460892 DUTY Scan : NO K
5966 12:22:13.460972 ZQ Calibration : PASS
5967 12:22:13.464449 Jitter Meter : NO K
5968 12:22:13.467489 CBT Training : PASS
5969 12:22:13.467605 Write leveling : PASS
5970 12:22:13.471327 RX DQS gating : PASS
5971 12:22:13.474476 RX DQ/DQS(RDDQC) : PASS
5972 12:22:13.474563 TX DQ/DQS : PASS
5973 12:22:13.477561 RX DATLAT : PASS
5974 12:22:13.481038 RX DQ/DQS(Engine): PASS
5975 12:22:13.481119 TX OE : NO K
5976 12:22:13.481184 All Pass.
5977 12:22:13.484382
5978 12:22:13.484463 CH 1, Rank 1
5979 12:22:13.487881 SW Impedance : PASS
5980 12:22:13.487961 DUTY Scan : NO K
5981 12:22:13.490897 ZQ Calibration : PASS
5982 12:22:13.490978 Jitter Meter : NO K
5983 12:22:13.494307 CBT Training : PASS
5984 12:22:13.497472 Write leveling : PASS
5985 12:22:13.497552 RX DQS gating : PASS
5986 12:22:13.501019 RX DQ/DQS(RDDQC) : PASS
5987 12:22:13.504439 TX DQ/DQS : PASS
5988 12:22:13.504520 RX DATLAT : PASS
5989 12:22:13.507432 RX DQ/DQS(Engine): PASS
5990 12:22:13.511016 TX OE : NO K
5991 12:22:13.511097 All Pass.
5992 12:22:13.511161
5993 12:22:13.514630 DramC Write-DBI off
5994 12:22:13.514710 PER_BANK_REFRESH: Hybrid Mode
5995 12:22:13.517708 TX_TRACKING: ON
5996 12:22:13.524042 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5997 12:22:13.531347 [FAST_K] Save calibration result to emmc
5998 12:22:13.534281 dramc_set_vcore_voltage set vcore to 650000
5999 12:22:13.534362 Read voltage for 400, 6
6000 12:22:13.537657 Vio18 = 0
6001 12:22:13.537738 Vcore = 650000
6002 12:22:13.537802 Vdram = 0
6003 12:22:13.541195 Vddq = 0
6004 12:22:13.541275 Vmddr = 0
6005 12:22:13.544036 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6006 12:22:13.550735 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6007 12:22:13.554405 MEM_TYPE=3, freq_sel=20
6008 12:22:13.557394 sv_algorithm_assistance_LP4_800
6009 12:22:13.560833 ============ PULL DRAM RESETB DOWN ============
6010 12:22:13.564398 ========== PULL DRAM RESETB DOWN end =========
6011 12:22:13.570720 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6012 12:22:13.570824 ===================================
6013 12:22:13.574153 LPDDR4 DRAM CONFIGURATION
6014 12:22:13.577356 ===================================
6015 12:22:13.580897 EX_ROW_EN[0] = 0x0
6016 12:22:13.580970 EX_ROW_EN[1] = 0x0
6017 12:22:13.583735 LP4Y_EN = 0x0
6018 12:22:13.583809 WORK_FSP = 0x0
6019 12:22:13.587441 WL = 0x2
6020 12:22:13.587511 RL = 0x2
6021 12:22:13.590577 BL = 0x2
6022 12:22:13.593772 RPST = 0x0
6023 12:22:13.593847 RD_PRE = 0x0
6024 12:22:13.597455 WR_PRE = 0x1
6025 12:22:13.597527 WR_PST = 0x0
6026 12:22:13.600286 DBI_WR = 0x0
6027 12:22:13.600360 DBI_RD = 0x0
6028 12:22:13.603821 OTF = 0x1
6029 12:22:13.607245 ===================================
6030 12:22:13.610945 ===================================
6031 12:22:13.611015 ANA top config
6032 12:22:13.613838 ===================================
6033 12:22:13.616960 DLL_ASYNC_EN = 0
6034 12:22:13.620369 ALL_SLAVE_EN = 1
6035 12:22:13.620455 NEW_RANK_MODE = 1
6036 12:22:13.623837 DLL_IDLE_MODE = 1
6037 12:22:13.627366 LP45_APHY_COMB_EN = 1
6038 12:22:13.630956 TX_ODT_DIS = 1
6039 12:22:13.631038 NEW_8X_MODE = 1
6040 12:22:13.633808 ===================================
6041 12:22:13.637373 ===================================
6042 12:22:13.640416 data_rate = 800
6043 12:22:13.643877 CKR = 1
6044 12:22:13.647285 DQ_P2S_RATIO = 4
6045 12:22:13.650604 ===================================
6046 12:22:13.653712 CA_P2S_RATIO = 4
6047 12:22:13.657275 DQ_CA_OPEN = 0
6048 12:22:13.657356 DQ_SEMI_OPEN = 1
6049 12:22:13.660215 CA_SEMI_OPEN = 1
6050 12:22:13.663722 CA_FULL_RATE = 0
6051 12:22:13.666924 DQ_CKDIV4_EN = 0
6052 12:22:13.670875 CA_CKDIV4_EN = 1
6053 12:22:13.673595 CA_PREDIV_EN = 0
6054 12:22:13.673675 PH8_DLY = 0
6055 12:22:13.677385 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6056 12:22:13.680569 DQ_AAMCK_DIV = 0
6057 12:22:13.683889 CA_AAMCK_DIV = 0
6058 12:22:13.687262 CA_ADMCK_DIV = 4
6059 12:22:13.690235 DQ_TRACK_CA_EN = 0
6060 12:22:13.690319 CA_PICK = 800
6061 12:22:13.693720 CA_MCKIO = 400
6062 12:22:13.697062 MCKIO_SEMI = 400
6063 12:22:13.700560 PLL_FREQ = 3016
6064 12:22:13.703805 DQ_UI_PI_RATIO = 32
6065 12:22:13.706890 CA_UI_PI_RATIO = 32
6066 12:22:13.710461 ===================================
6067 12:22:13.713778 ===================================
6068 12:22:13.713860 memory_type:LPDDR4
6069 12:22:13.717127 GP_NUM : 10
6070 12:22:13.720420 SRAM_EN : 1
6071 12:22:13.720502 MD32_EN : 0
6072 12:22:13.723688 ===================================
6073 12:22:13.727333 [ANA_INIT] >>>>>>>>>>>>>>
6074 12:22:13.730240 <<<<<< [CONFIGURE PHASE]: ANA_TX
6075 12:22:13.733624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6076 12:22:13.737278 ===================================
6077 12:22:13.740319 data_rate = 800,PCW = 0X7400
6078 12:22:13.743832 ===================================
6079 12:22:13.746893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6080 12:22:13.750674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 12:22:13.763747 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6082 12:22:13.766780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6083 12:22:13.770187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6084 12:22:13.773722 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6085 12:22:13.776708 [ANA_INIT] flow start
6086 12:22:13.780303 [ANA_INIT] PLL >>>>>>>>
6087 12:22:13.780385 [ANA_INIT] PLL <<<<<<<<
6088 12:22:13.783852 [ANA_INIT] MIDPI >>>>>>>>
6089 12:22:13.786847 [ANA_INIT] MIDPI <<<<<<<<
6090 12:22:13.786929 [ANA_INIT] DLL >>>>>>>>
6091 12:22:13.790118 [ANA_INIT] flow end
6092 12:22:13.793489 ============ LP4 DIFF to SE enter ============
6093 12:22:13.799856 ============ LP4 DIFF to SE exit ============
6094 12:22:13.799939 [ANA_INIT] <<<<<<<<<<<<<
6095 12:22:13.803476 [Flow] Enable top DCM control >>>>>
6096 12:22:13.806504 [Flow] Enable top DCM control <<<<<
6097 12:22:13.809978 Enable DLL master slave shuffle
6098 12:22:13.816488 ==============================================================
6099 12:22:13.816572 Gating Mode config
6100 12:22:13.823174 ==============================================================
6101 12:22:13.826129 Config description:
6102 12:22:13.832775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6103 12:22:13.839920 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6104 12:22:13.846210 SELPH_MODE 0: By rank 1: By Phase
6105 12:22:13.853037 ==============================================================
6106 12:22:13.853120 GAT_TRACK_EN = 0
6107 12:22:13.856361 RX_GATING_MODE = 2
6108 12:22:13.859388 RX_GATING_TRACK_MODE = 2
6109 12:22:13.863018 SELPH_MODE = 1
6110 12:22:13.866436 PICG_EARLY_EN = 1
6111 12:22:13.869773 VALID_LAT_VALUE = 1
6112 12:22:13.876468 ==============================================================
6113 12:22:13.879547 Enter into Gating configuration >>>>
6114 12:22:13.882952 Exit from Gating configuration <<<<
6115 12:22:13.885991 Enter into DVFS_PRE_config >>>>>
6116 12:22:13.896351 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6117 12:22:13.899384 Exit from DVFS_PRE_config <<<<<
6118 12:22:13.902857 Enter into PICG configuration >>>>
6119 12:22:13.906055 Exit from PICG configuration <<<<
6120 12:22:13.909417 [RX_INPUT] configuration >>>>>
6121 12:22:13.909500 [RX_INPUT] configuration <<<<<
6122 12:22:13.916262 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6123 12:22:13.922775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6124 12:22:13.926211 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6125 12:22:13.932607 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6126 12:22:13.939229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 12:22:13.946138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 12:22:13.949139 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6129 12:22:13.952604 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6130 12:22:13.959185 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6131 12:22:13.962613 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6132 12:22:13.966294 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6133 12:22:13.972678 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6134 12:22:13.976178 ===================================
6135 12:22:13.976260 LPDDR4 DRAM CONFIGURATION
6136 12:22:13.979457 ===================================
6137 12:22:13.982644 EX_ROW_EN[0] = 0x0
6138 12:22:13.982725 EX_ROW_EN[1] = 0x0
6139 12:22:13.985760 LP4Y_EN = 0x0
6140 12:22:13.985842 WORK_FSP = 0x0
6141 12:22:13.989120 WL = 0x2
6142 12:22:13.992156 RL = 0x2
6143 12:22:13.992238 BL = 0x2
6144 12:22:13.995580 RPST = 0x0
6145 12:22:13.995700 RD_PRE = 0x0
6146 12:22:13.999194 WR_PRE = 0x1
6147 12:22:13.999276 WR_PST = 0x0
6148 12:22:14.002527 DBI_WR = 0x0
6149 12:22:14.002611 DBI_RD = 0x0
6150 12:22:14.005996 OTF = 0x1
6151 12:22:14.008876 ===================================
6152 12:22:14.012117 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6153 12:22:14.015665 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6154 12:22:14.019145 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 12:22:14.022256 ===================================
6156 12:22:14.025198 LPDDR4 DRAM CONFIGURATION
6157 12:22:14.028601 ===================================
6158 12:22:14.032187 EX_ROW_EN[0] = 0x10
6159 12:22:14.032269 EX_ROW_EN[1] = 0x0
6160 12:22:14.035172 LP4Y_EN = 0x0
6161 12:22:14.035254 WORK_FSP = 0x0
6162 12:22:14.038972 WL = 0x2
6163 12:22:14.039054 RL = 0x2
6164 12:22:14.041856 BL = 0x2
6165 12:22:14.045150 RPST = 0x0
6166 12:22:14.045232 RD_PRE = 0x0
6167 12:22:14.048743 WR_PRE = 0x1
6168 12:22:14.048826 WR_PST = 0x0
6169 12:22:14.051842 DBI_WR = 0x0
6170 12:22:14.051923 DBI_RD = 0x0
6171 12:22:14.055135 OTF = 0x1
6172 12:22:14.058910 ===================================
6173 12:22:14.061934 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6174 12:22:14.067543 nWR fixed to 30
6175 12:22:14.070584 [ModeRegInit_LP4] CH0 RK0
6176 12:22:14.070667 [ModeRegInit_LP4] CH0 RK1
6177 12:22:14.074220 [ModeRegInit_LP4] CH1 RK0
6178 12:22:14.077741 [ModeRegInit_LP4] CH1 RK1
6179 12:22:14.077823 match AC timing 19
6180 12:22:14.084116 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6181 12:22:14.087291 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6182 12:22:14.090563 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6183 12:22:14.097117 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6184 12:22:14.100766 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6185 12:22:14.100848 ==
6186 12:22:14.104406 Dram Type= 6, Freq= 0, CH_0, rank 0
6187 12:22:14.107299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6188 12:22:14.107381 ==
6189 12:22:14.114240 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6190 12:22:14.120512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6191 12:22:14.124230 [CA 0] Center 36 (8~64) winsize 57
6192 12:22:14.127569 [CA 1] Center 36 (8~64) winsize 57
6193 12:22:14.127690 [CA 2] Center 36 (8~64) winsize 57
6194 12:22:14.130674 [CA 3] Center 36 (8~64) winsize 57
6195 12:22:14.134382 [CA 4] Center 36 (8~64) winsize 57
6196 12:22:14.137615 [CA 5] Center 36 (8~64) winsize 57
6197 12:22:14.137691
6198 12:22:14.140669 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6199 12:22:14.144202
6200 12:22:14.147164 [CATrainingPosCal] consider 1 rank data
6201 12:22:14.147231 u2DelayCellTimex100 = 270/100 ps
6202 12:22:14.154041 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 12:22:14.157371 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 12:22:14.160681 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 12:22:14.163896 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 12:22:14.167282 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 12:22:14.170468 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 12:22:14.170541
6209 12:22:14.173685 CA PerBit enable=1, Macro0, CA PI delay=36
6210 12:22:14.173754
6211 12:22:14.177095 [CBTSetCACLKResult] CA Dly = 36
6212 12:22:14.180554 CS Dly: 1 (0~32)
6213 12:22:14.180629 ==
6214 12:22:14.184289 Dram Type= 6, Freq= 0, CH_0, rank 1
6215 12:22:14.187222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 12:22:14.187295 ==
6217 12:22:14.193658 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 12:22:14.196911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6219 12:22:14.200386 [CA 0] Center 36 (8~64) winsize 57
6220 12:22:14.203859 [CA 1] Center 36 (8~64) winsize 57
6221 12:22:14.206892 [CA 2] Center 36 (8~64) winsize 57
6222 12:22:14.210468 [CA 3] Center 36 (8~64) winsize 57
6223 12:22:14.213406 [CA 4] Center 36 (8~64) winsize 57
6224 12:22:14.216832 [CA 5] Center 36 (8~64) winsize 57
6225 12:22:14.216914
6226 12:22:14.220334 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6227 12:22:14.220416
6228 12:22:14.223287 [CATrainingPosCal] consider 2 rank data
6229 12:22:14.227360 u2DelayCellTimex100 = 270/100 ps
6230 12:22:14.230409 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:22:14.233525 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:22:14.236911 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:22:14.243492 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 12:22:14.246908 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 12:22:14.250420 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 12:22:14.250502
6237 12:22:14.253502 CA PerBit enable=1, Macro0, CA PI delay=36
6238 12:22:14.253583
6239 12:22:14.257096 [CBTSetCACLKResult] CA Dly = 36
6240 12:22:14.257178 CS Dly: 1 (0~32)
6241 12:22:14.257243
6242 12:22:14.260392 ----->DramcWriteLeveling(PI) begin...
6243 12:22:14.260475 ==
6244 12:22:14.263859 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 12:22:14.270152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 12:22:14.270234 ==
6247 12:22:14.273540 Write leveling (Byte 0): 40 => 8
6248 12:22:14.273622 Write leveling (Byte 1): 40 => 8
6249 12:22:14.276946 DramcWriteLeveling(PI) end<-----
6250 12:22:14.277028
6251 12:22:14.277093 ==
6252 12:22:14.280741 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 12:22:14.286980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 12:22:14.287077 ==
6255 12:22:14.290590 [Gating] SW mode calibration
6256 12:22:14.297124 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6257 12:22:14.300683 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6258 12:22:14.307233 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 12:22:14.310278 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6260 12:22:14.313721 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 12:22:14.320382 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 12:22:14.323803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 12:22:14.327222 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 12:22:14.330201 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 12:22:14.337029 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 12:22:14.340190 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 12:22:14.343850 Total UI for P1: 0, mck2ui 16
6268 12:22:14.347086 best dqsien dly found for B0: ( 0, 14, 24)
6269 12:22:14.350337 Total UI for P1: 0, mck2ui 16
6270 12:22:14.353687 best dqsien dly found for B1: ( 0, 14, 24)
6271 12:22:14.357176 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6272 12:22:14.360084 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6273 12:22:14.360158
6274 12:22:14.363502 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 12:22:14.369987 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6276 12:22:14.370066 [Gating] SW calibration Done
6277 12:22:14.370134 ==
6278 12:22:14.373277 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 12:22:14.380194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 12:22:14.380270 ==
6281 12:22:14.380333 RX Vref Scan: 0
6282 12:22:14.380397
6283 12:22:14.383228 RX Vref 0 -> 0, step: 1
6284 12:22:14.383304
6285 12:22:14.386666 RX Delay -410 -> 252, step: 16
6286 12:22:14.390270 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6287 12:22:14.393695 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6288 12:22:14.399738 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6289 12:22:14.403210 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6290 12:22:14.406940 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6291 12:22:14.409711 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6292 12:22:14.416706 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6293 12:22:14.419824 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6294 12:22:14.423027 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6295 12:22:14.426251 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6296 12:22:14.433331 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6297 12:22:14.436799 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6298 12:22:14.439776 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6299 12:22:14.443296 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6300 12:22:14.449780 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6301 12:22:14.453287 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6302 12:22:14.453368 ==
6303 12:22:14.456253 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 12:22:14.459484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 12:22:14.459613 ==
6306 12:22:14.462778 DQS Delay:
6307 12:22:14.462858 DQS0 = 27, DQS1 = 35
6308 12:22:14.466558 DQM Delay:
6309 12:22:14.466639 DQM0 = 14, DQM1 = 16
6310 12:22:14.466703 DQ Delay:
6311 12:22:14.470012 DQ0 =16, DQ1 =24, DQ2 =0, DQ3 =8
6312 12:22:14.472836 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6313 12:22:14.476280 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6314 12:22:14.479705 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6315 12:22:14.479811
6316 12:22:14.479913
6317 12:22:14.480013 ==
6318 12:22:14.483252 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 12:22:14.486108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 12:22:14.489618 ==
6321 12:22:14.489699
6322 12:22:14.489763
6323 12:22:14.489822 TX Vref Scan disable
6324 12:22:14.493115 == TX Byte 0 ==
6325 12:22:14.496125 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6326 12:22:14.499824 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6327 12:22:14.502800 == TX Byte 1 ==
6328 12:22:14.506296 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 12:22:14.509800 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 12:22:14.509880 ==
6331 12:22:14.512840 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 12:22:14.519640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 12:22:14.519736 ==
6334 12:22:14.519800
6335 12:22:14.519859
6336 12:22:14.519916 TX Vref Scan disable
6337 12:22:14.522932 == TX Byte 0 ==
6338 12:22:14.525887 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 12:22:14.529428 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 12:22:14.532808 == TX Byte 1 ==
6341 12:22:14.536284 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 12:22:14.539790 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 12:22:14.539872
6344 12:22:14.542971 [DATLAT]
6345 12:22:14.543051 Freq=400, CH0 RK0
6346 12:22:14.543115
6347 12:22:14.545882 DATLAT Default: 0xf
6348 12:22:14.545962 0, 0xFFFF, sum = 0
6349 12:22:14.549463 1, 0xFFFF, sum = 0
6350 12:22:14.549545 2, 0xFFFF, sum = 0
6351 12:22:14.552603 3, 0xFFFF, sum = 0
6352 12:22:14.552686 4, 0xFFFF, sum = 0
6353 12:22:14.556005 5, 0xFFFF, sum = 0
6354 12:22:14.556088 6, 0xFFFF, sum = 0
6355 12:22:14.559287 7, 0xFFFF, sum = 0
6356 12:22:14.559396 8, 0xFFFF, sum = 0
6357 12:22:14.562513 9, 0xFFFF, sum = 0
6358 12:22:14.562595 10, 0xFFFF, sum = 0
6359 12:22:14.566281 11, 0xFFFF, sum = 0
6360 12:22:14.569262 12, 0xFFFF, sum = 0
6361 12:22:14.569344 13, 0x0, sum = 1
6362 12:22:14.569410 14, 0x0, sum = 2
6363 12:22:14.572457 15, 0x0, sum = 3
6364 12:22:14.572540 16, 0x0, sum = 4
6365 12:22:14.576084 best_step = 14
6366 12:22:14.576165
6367 12:22:14.576229 ==
6368 12:22:14.579482 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 12:22:14.582578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 12:22:14.582660 ==
6371 12:22:14.586216 RX Vref Scan: 1
6372 12:22:14.586298
6373 12:22:14.586362 RX Vref 0 -> 0, step: 1
6374 12:22:14.586423
6375 12:22:14.589258 RX Delay -311 -> 252, step: 8
6376 12:22:14.589366
6377 12:22:14.593044 Set Vref, RX VrefLevel [Byte0]: 57
6378 12:22:14.596366 [Byte1]: 48
6379 12:22:14.600579
6380 12:22:14.600660 Final RX Vref Byte 0 = 57 to rank0
6381 12:22:14.604185 Final RX Vref Byte 1 = 48 to rank0
6382 12:22:14.607703 Final RX Vref Byte 0 = 57 to rank1
6383 12:22:14.610669 Final RX Vref Byte 1 = 48 to rank1==
6384 12:22:14.614171 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 12:22:14.620685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 12:22:14.620767 ==
6387 12:22:14.620831 DQS Delay:
6388 12:22:14.624345 DQS0 = 28, DQS1 = 36
6389 12:22:14.624426 DQM Delay:
6390 12:22:14.624521 DQM0 = 11, DQM1 = 13
6391 12:22:14.626976 DQ Delay:
6392 12:22:14.630275 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6393 12:22:14.630356 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6394 12:22:14.633718 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6395 12:22:14.637180 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6396 12:22:14.637262
6397 12:22:14.637326
6398 12:22:14.647102 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6399 12:22:14.650627 CH0 RK0: MR19=C0C, MR18=CBB7
6400 12:22:14.657246 CH0_RK0: MR19=0xC0C, MR18=0xCBB7, DQSOSC=384, MR23=63, INC=400, DEC=267
6401 12:22:14.657328 ==
6402 12:22:14.660761 Dram Type= 6, Freq= 0, CH_0, rank 1
6403 12:22:14.664173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 12:22:14.664255 ==
6405 12:22:14.667102 [Gating] SW mode calibration
6406 12:22:14.674194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6407 12:22:14.677409 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6408 12:22:14.684088 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 12:22:14.687551 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6410 12:22:14.690542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 12:22:14.697512 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 12:22:14.700634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 12:22:14.704049 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 12:22:14.710227 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 12:22:14.714177 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 12:22:14.717064 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 12:22:14.720691 Total UI for P1: 0, mck2ui 16
6418 12:22:14.723535 best dqsien dly found for B0: ( 0, 14, 24)
6419 12:22:14.727153 Total UI for P1: 0, mck2ui 16
6420 12:22:14.730192 best dqsien dly found for B1: ( 0, 14, 24)
6421 12:22:14.733608 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6422 12:22:14.736896 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6423 12:22:14.736970
6424 12:22:14.743637 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 12:22:14.747089 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6426 12:22:14.750143 [Gating] SW calibration Done
6427 12:22:14.750216 ==
6428 12:22:14.753367 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 12:22:14.756701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 12:22:14.756777 ==
6431 12:22:14.756839 RX Vref Scan: 0
6432 12:22:14.756899
6433 12:22:14.760338 RX Vref 0 -> 0, step: 1
6434 12:22:14.760407
6435 12:22:14.763301 RX Delay -410 -> 252, step: 16
6436 12:22:14.766831 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6437 12:22:14.773723 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6438 12:22:14.776594 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6439 12:22:14.780359 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6440 12:22:14.783521 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6441 12:22:14.786822 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6442 12:22:14.793815 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6443 12:22:14.797105 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6444 12:22:14.800748 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6445 12:22:14.803567 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6446 12:22:14.810146 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6447 12:22:14.813839 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6448 12:22:14.817056 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6449 12:22:14.820478 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6450 12:22:14.827111 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6451 12:22:14.830081 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6452 12:22:14.830158 ==
6453 12:22:14.833534 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 12:22:14.837263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 12:22:14.837359 ==
6456 12:22:14.839979 DQS Delay:
6457 12:22:14.840050 DQS0 = 19, DQS1 = 35
6458 12:22:14.843867 DQM Delay:
6459 12:22:14.843934 DQM0 = 10, DQM1 = 15
6460 12:22:14.843993 DQ Delay:
6461 12:22:14.847017 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6462 12:22:14.850460 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6463 12:22:14.853576 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6464 12:22:14.857075 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6465 12:22:14.857168
6466 12:22:14.857258
6467 12:22:14.857343 ==
6468 12:22:14.860114 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 12:22:14.866900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 12:22:14.867002 ==
6471 12:22:14.867092
6472 12:22:14.867182
6473 12:22:14.867267 TX Vref Scan disable
6474 12:22:14.870333 == TX Byte 0 ==
6475 12:22:14.873399 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6476 12:22:14.876841 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6477 12:22:14.880175 == TX Byte 1 ==
6478 12:22:14.883970 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6479 12:22:14.887230 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6480 12:22:14.887329 ==
6481 12:22:14.890202 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 12:22:14.893771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 12:22:14.897213 ==
6484 12:22:14.897310
6485 12:22:14.897400
6486 12:22:14.897489 TX Vref Scan disable
6487 12:22:14.900051 == TX Byte 0 ==
6488 12:22:14.903231 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6489 12:22:14.906882 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6490 12:22:14.909953 == TX Byte 1 ==
6491 12:22:14.913552 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6492 12:22:14.916588 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6493 12:22:14.916665
6494 12:22:14.920146 [DATLAT]
6495 12:22:14.920223 Freq=400, CH0 RK1
6496 12:22:14.920288
6497 12:22:14.923211 DATLAT Default: 0xe
6498 12:22:14.923309 0, 0xFFFF, sum = 0
6499 12:22:14.926574 1, 0xFFFF, sum = 0
6500 12:22:14.926655 2, 0xFFFF, sum = 0
6501 12:22:14.929998 3, 0xFFFF, sum = 0
6502 12:22:14.930098 4, 0xFFFF, sum = 0
6503 12:22:14.933061 5, 0xFFFF, sum = 0
6504 12:22:14.933159 6, 0xFFFF, sum = 0
6505 12:22:14.936793 7, 0xFFFF, sum = 0
6506 12:22:14.936867 8, 0xFFFF, sum = 0
6507 12:22:14.939790 9, 0xFFFF, sum = 0
6508 12:22:14.939862 10, 0xFFFF, sum = 0
6509 12:22:14.943140 11, 0xFFFF, sum = 0
6510 12:22:14.943244 12, 0xFFFF, sum = 0
6511 12:22:14.946766 13, 0x0, sum = 1
6512 12:22:14.946846 14, 0x0, sum = 2
6513 12:22:14.950075 15, 0x0, sum = 3
6514 12:22:14.950178 16, 0x0, sum = 4
6515 12:22:14.953270 best_step = 14
6516 12:22:14.953342
6517 12:22:14.953416 ==
6518 12:22:14.956441 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 12:22:14.959860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 12:22:14.959959 ==
6521 12:22:14.963276 RX Vref Scan: 0
6522 12:22:14.963348
6523 12:22:14.963413 RX Vref 0 -> 0, step: 1
6524 12:22:14.963472
6525 12:22:14.966528 RX Delay -311 -> 252, step: 8
6526 12:22:14.974553 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6527 12:22:14.977560 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6528 12:22:14.981233 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6529 12:22:14.984440 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6530 12:22:14.990922 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6531 12:22:14.994426 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6532 12:22:14.997971 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6533 12:22:15.000924 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6534 12:22:15.007974 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6535 12:22:15.011234 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6536 12:22:15.014289 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6537 12:22:15.017911 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6538 12:22:15.024418 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6539 12:22:15.027683 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6540 12:22:15.031041 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6541 12:22:15.037489 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6542 12:22:15.037591 ==
6543 12:22:15.041062 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 12:22:15.044048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 12:22:15.044122 ==
6546 12:22:15.044186 DQS Delay:
6547 12:22:15.047978 DQS0 = 24, DQS1 = 32
6548 12:22:15.048058 DQM Delay:
6549 12:22:15.051063 DQM0 = 8, DQM1 = 10
6550 12:22:15.051138 DQ Delay:
6551 12:22:15.054469 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6552 12:22:15.057715 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6553 12:22:15.060920 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6554 12:22:15.064512 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6555 12:22:15.064624
6556 12:22:15.064725
6557 12:22:15.070886 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6558 12:22:15.074534 CH0 RK1: MR19=C0C, MR18=BB5B
6559 12:22:15.081457 CH0_RK1: MR19=0xC0C, MR18=0xBB5B, DQSOSC=386, MR23=63, INC=396, DEC=264
6560 12:22:15.084278 [RxdqsGatingPostProcess] freq 400
6561 12:22:15.087734 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6562 12:22:15.091102 best DQS0 dly(2T, 0.5T) = (0, 10)
6563 12:22:15.094133 best DQS1 dly(2T, 0.5T) = (0, 10)
6564 12:22:15.097659 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6565 12:22:15.101198 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6566 12:22:15.104324 best DQS0 dly(2T, 0.5T) = (0, 10)
6567 12:22:15.107393 best DQS1 dly(2T, 0.5T) = (0, 10)
6568 12:22:15.110967 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6569 12:22:15.114300 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6570 12:22:15.117728 Pre-setting of DQS Precalculation
6571 12:22:15.121034 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6572 12:22:15.121137 ==
6573 12:22:15.124046 Dram Type= 6, Freq= 0, CH_1, rank 0
6574 12:22:15.130865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 12:22:15.130966 ==
6576 12:22:15.134000 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6577 12:22:15.140900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6578 12:22:15.144392 [CA 0] Center 36 (8~64) winsize 57
6579 12:22:15.147428 [CA 1] Center 36 (8~64) winsize 57
6580 12:22:15.151070 [CA 2] Center 36 (8~64) winsize 57
6581 12:22:15.154592 [CA 3] Center 36 (8~64) winsize 57
6582 12:22:15.157523 [CA 4] Center 36 (8~64) winsize 57
6583 12:22:15.161074 [CA 5] Center 36 (8~64) winsize 57
6584 12:22:15.161142
6585 12:22:15.164047 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6586 12:22:15.164113
6587 12:22:15.167473 [CATrainingPosCal] consider 1 rank data
6588 12:22:15.171019 u2DelayCellTimex100 = 270/100 ps
6589 12:22:15.173904 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 12:22:15.177553 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 12:22:15.180955 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 12:22:15.184373 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 12:22:15.187250 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 12:22:15.190852 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 12:22:15.194058
6596 12:22:15.197183 CA PerBit enable=1, Macro0, CA PI delay=36
6597 12:22:15.197256
6598 12:22:15.200660 [CBTSetCACLKResult] CA Dly = 36
6599 12:22:15.200731 CS Dly: 1 (0~32)
6600 12:22:15.200798 ==
6601 12:22:15.204161 Dram Type= 6, Freq= 0, CH_1, rank 1
6602 12:22:15.207516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 12:22:15.207646 ==
6604 12:22:15.214120 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 12:22:15.220700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6606 12:22:15.224182 [CA 0] Center 36 (8~64) winsize 57
6607 12:22:15.227693 [CA 1] Center 36 (8~64) winsize 57
6608 12:22:15.230563 [CA 2] Center 36 (8~64) winsize 57
6609 12:22:15.234025 [CA 3] Center 36 (8~64) winsize 57
6610 12:22:15.237071 [CA 4] Center 36 (8~64) winsize 57
6611 12:22:15.240726 [CA 5] Center 36 (8~64) winsize 57
6612 12:22:15.240798
6613 12:22:15.243746 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6614 12:22:15.243815
6615 12:22:15.247112 [CATrainingPosCal] consider 2 rank data
6616 12:22:15.250578 u2DelayCellTimex100 = 270/100 ps
6617 12:22:15.254077 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:22:15.257191 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:22:15.260594 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:22:15.264195 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 12:22:15.267105 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 12:22:15.270525 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 12:22:15.270628
6624 12:22:15.273528 CA PerBit enable=1, Macro0, CA PI delay=36
6625 12:22:15.273609
6626 12:22:15.277153 [CBTSetCACLKResult] CA Dly = 36
6627 12:22:15.280173 CS Dly: 1 (0~32)
6628 12:22:15.280282
6629 12:22:15.283821 ----->DramcWriteLeveling(PI) begin...
6630 12:22:15.283927 ==
6631 12:22:15.286734 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 12:22:15.290388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 12:22:15.290488 ==
6634 12:22:15.293847 Write leveling (Byte 0): 40 => 8
6635 12:22:15.297207 Write leveling (Byte 1): 40 => 8
6636 12:22:15.300416 DramcWriteLeveling(PI) end<-----
6637 12:22:15.300490
6638 12:22:15.300551 ==
6639 12:22:15.303881 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 12:22:15.307227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 12:22:15.307322 ==
6642 12:22:15.309976 [Gating] SW mode calibration
6643 12:22:15.317017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6644 12:22:15.323563 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6645 12:22:15.326880 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 12:22:15.329873 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6647 12:22:15.336997 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 12:22:15.340447 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 12:22:15.343641 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 12:22:15.350362 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 12:22:15.353638 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 12:22:15.356722 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 12:22:15.363381 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 12:22:15.366905 Total UI for P1: 0, mck2ui 16
6655 12:22:15.369883 best dqsien dly found for B0: ( 0, 14, 24)
6656 12:22:15.369954 Total UI for P1: 0, mck2ui 16
6657 12:22:15.376451 best dqsien dly found for B1: ( 0, 14, 24)
6658 12:22:15.379934 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6659 12:22:15.383567 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6660 12:22:15.383706
6661 12:22:15.386675 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 12:22:15.389942 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6663 12:22:15.393534 [Gating] SW calibration Done
6664 12:22:15.393604 ==
6665 12:22:15.396517 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 12:22:15.400124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 12:22:15.400192 ==
6668 12:22:15.403184 RX Vref Scan: 0
6669 12:22:15.403276
6670 12:22:15.403362 RX Vref 0 -> 0, step: 1
6671 12:22:15.406454
6672 12:22:15.406549 RX Delay -410 -> 252, step: 16
6673 12:22:15.413340 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6674 12:22:15.416811 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6675 12:22:15.419748 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6676 12:22:15.423194 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6677 12:22:15.430019 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6678 12:22:15.433580 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6679 12:22:15.437080 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6680 12:22:15.440615 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6681 12:22:15.446782 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6682 12:22:15.449723 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6683 12:22:15.453369 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6684 12:22:15.456269 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6685 12:22:15.463230 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6686 12:22:15.466769 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6687 12:22:15.469803 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6688 12:22:15.473263 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6689 12:22:15.473335 ==
6690 12:22:15.476592 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 12:22:15.483119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 12:22:15.483221 ==
6693 12:22:15.483323 DQS Delay:
6694 12:22:15.486623 DQS0 = 27, DQS1 = 35
6695 12:22:15.486726 DQM Delay:
6696 12:22:15.490241 DQM0 = 10, DQM1 = 13
6697 12:22:15.490348 DQ Delay:
6698 12:22:15.493132 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6699 12:22:15.496872 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6700 12:22:15.496945 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6701 12:22:15.503421 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6702 12:22:15.503522
6703 12:22:15.503623
6704 12:22:15.503685 ==
6705 12:22:15.506343 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 12:22:15.509975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 12:22:15.510071 ==
6708 12:22:15.510160
6709 12:22:15.510245
6710 12:22:15.513343 TX Vref Scan disable
6711 12:22:15.513438 == TX Byte 0 ==
6712 12:22:15.516614 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6713 12:22:15.522991 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6714 12:22:15.523096 == TX Byte 1 ==
6715 12:22:15.526524 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 12:22:15.533027 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 12:22:15.533125 ==
6718 12:22:15.536559 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 12:22:15.540126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 12:22:15.540198 ==
6721 12:22:15.540264
6722 12:22:15.540356
6723 12:22:15.543033 TX Vref Scan disable
6724 12:22:15.543127 == TX Byte 0 ==
6725 12:22:15.546590 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 12:22:15.553085 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 12:22:15.553172 == TX Byte 1 ==
6728 12:22:15.556325 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 12:22:15.563489 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 12:22:15.563614
6731 12:22:15.563694 [DATLAT]
6732 12:22:15.563754 Freq=400, CH1 RK0
6733 12:22:15.566455
6734 12:22:15.566554 DATLAT Default: 0xf
6735 12:22:15.570148 0, 0xFFFF, sum = 0
6736 12:22:15.570223 1, 0xFFFF, sum = 0
6737 12:22:15.572956 2, 0xFFFF, sum = 0
6738 12:22:15.573058 3, 0xFFFF, sum = 0
6739 12:22:15.576520 4, 0xFFFF, sum = 0
6740 12:22:15.576617 5, 0xFFFF, sum = 0
6741 12:22:15.579494 6, 0xFFFF, sum = 0
6742 12:22:15.579613 7, 0xFFFF, sum = 0
6743 12:22:15.583129 8, 0xFFFF, sum = 0
6744 12:22:15.583204 9, 0xFFFF, sum = 0
6745 12:22:15.586109 10, 0xFFFF, sum = 0
6746 12:22:15.586181 11, 0xFFFF, sum = 0
6747 12:22:15.589967 12, 0xFFFF, sum = 0
6748 12:22:15.590044 13, 0x0, sum = 1
6749 12:22:15.593367 14, 0x0, sum = 2
6750 12:22:15.593466 15, 0x0, sum = 3
6751 12:22:15.596651 16, 0x0, sum = 4
6752 12:22:15.596724 best_step = 14
6753 12:22:15.596805
6754 12:22:15.596864 ==
6755 12:22:15.599529 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 12:22:15.606783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 12:22:15.606882 ==
6758 12:22:15.606982 RX Vref Scan: 1
6759 12:22:15.607070
6760 12:22:15.609825 RX Vref 0 -> 0, step: 1
6761 12:22:15.609911
6762 12:22:15.612834 RX Delay -311 -> 252, step: 8
6763 12:22:15.612928
6764 12:22:15.616288 Set Vref, RX VrefLevel [Byte0]: 54
6765 12:22:15.619998 [Byte1]: 46
6766 12:22:15.620079
6767 12:22:15.623057 Final RX Vref Byte 0 = 54 to rank0
6768 12:22:15.625992 Final RX Vref Byte 1 = 46 to rank0
6769 12:22:15.629288 Final RX Vref Byte 0 = 54 to rank1
6770 12:22:15.632888 Final RX Vref Byte 1 = 46 to rank1==
6771 12:22:15.636111 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 12:22:15.639365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 12:22:15.642428 ==
6774 12:22:15.642524 DQS Delay:
6775 12:22:15.642650 DQS0 = 32, DQS1 = 36
6776 12:22:15.646080 DQM Delay:
6777 12:22:15.646177 DQM0 = 13, DQM1 = 14
6778 12:22:15.649495 DQ Delay:
6779 12:22:15.649590 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6780 12:22:15.652595 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6781 12:22:15.656261 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6782 12:22:15.659198 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6783 12:22:15.659295
6784 12:22:15.659386
6785 12:22:15.669469 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6786 12:22:15.672357 CH1 RK0: MR19=C0C, MR18=90C6
6787 12:22:15.679138 CH1_RK0: MR19=0xC0C, MR18=0x90C6, DQSOSC=385, MR23=63, INC=398, DEC=265
6788 12:22:15.679240 ==
6789 12:22:15.682686 Dram Type= 6, Freq= 0, CH_1, rank 1
6790 12:22:15.686056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 12:22:15.686152 ==
6792 12:22:15.689721 [Gating] SW mode calibration
6793 12:22:15.695906 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6794 12:22:15.699196 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6795 12:22:15.705982 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 12:22:15.708914 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6797 12:22:15.712284 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 12:22:15.719294 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6799 12:22:15.722178 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 12:22:15.725994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 12:22:15.732119 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 12:22:15.735316 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 12:22:15.738710 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 12:22:15.742293 Total UI for P1: 0, mck2ui 16
6805 12:22:15.745324 best dqsien dly found for B0: ( 0, 14, 24)
6806 12:22:15.748955 Total UI for P1: 0, mck2ui 16
6807 12:22:15.751940 best dqsien dly found for B1: ( 0, 14, 24)
6808 12:22:15.755451 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6809 12:22:15.759082 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6810 12:22:15.762208
6811 12:22:15.765343 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 12:22:15.768583 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6813 12:22:15.771951 [Gating] SW calibration Done
6814 12:22:15.772045 ==
6815 12:22:15.775529 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 12:22:15.778585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 12:22:15.778679 ==
6818 12:22:15.778768 RX Vref Scan: 0
6819 12:22:15.778852
6820 12:22:15.781873 RX Vref 0 -> 0, step: 1
6821 12:22:15.781974
6822 12:22:15.785216 RX Delay -410 -> 252, step: 16
6823 12:22:15.788440 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6824 12:22:15.795169 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6825 12:22:15.798441 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6826 12:22:15.802028 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6827 12:22:15.805554 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6828 12:22:15.812056 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6829 12:22:15.814953 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6830 12:22:15.818316 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6831 12:22:15.821664 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6832 12:22:15.828202 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6833 12:22:15.832159 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6834 12:22:15.835188 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6835 12:22:15.838298 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6836 12:22:15.845248 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6837 12:22:15.848405 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6838 12:22:15.851896 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6839 12:22:15.851995 ==
6840 12:22:15.854860 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 12:22:15.858600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 12:22:15.861587 ==
6843 12:22:15.861682 DQS Delay:
6844 12:22:15.861771 DQS0 = 27, DQS1 = 35
6845 12:22:15.865080 DQM Delay:
6846 12:22:15.865174 DQM0 = 11, DQM1 = 13
6847 12:22:15.868518 DQ Delay:
6848 12:22:15.868586 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6849 12:22:15.871820 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6850 12:22:15.874992 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6851 12:22:15.878452 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6852 12:22:15.878553
6853 12:22:15.878641
6854 12:22:15.878702 ==
6855 12:22:15.881491 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 12:22:15.888223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 12:22:15.888302 ==
6858 12:22:15.888365
6859 12:22:15.888432
6860 12:22:15.888490 TX Vref Scan disable
6861 12:22:15.891783 == TX Byte 0 ==
6862 12:22:15.894911 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6863 12:22:15.898202 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6864 12:22:15.901555 == TX Byte 1 ==
6865 12:22:15.905067 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6866 12:22:15.908482 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6867 12:22:15.908588 ==
6868 12:22:15.911893 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 12:22:15.918379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 12:22:15.918476 ==
6871 12:22:15.918571
6872 12:22:15.918652
6873 12:22:15.918729 TX Vref Scan disable
6874 12:22:15.921329 == TX Byte 0 ==
6875 12:22:15.924813 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6876 12:22:15.928036 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6877 12:22:15.931286 == TX Byte 1 ==
6878 12:22:15.934805 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6879 12:22:15.938150 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6880 12:22:15.938248
6881 12:22:15.941655 [DATLAT]
6882 12:22:15.941754 Freq=400, CH1 RK1
6883 12:22:15.941852
6884 12:22:15.944552 DATLAT Default: 0xe
6885 12:22:15.944650 0, 0xFFFF, sum = 0
6886 12:22:15.948273 1, 0xFFFF, sum = 0
6887 12:22:15.948349 2, 0xFFFF, sum = 0
6888 12:22:15.951705 3, 0xFFFF, sum = 0
6889 12:22:15.951805 4, 0xFFFF, sum = 0
6890 12:22:15.954781 5, 0xFFFF, sum = 0
6891 12:22:15.954886 6, 0xFFFF, sum = 0
6892 12:22:15.958313 7, 0xFFFF, sum = 0
6893 12:22:15.958393 8, 0xFFFF, sum = 0
6894 12:22:15.961215 9, 0xFFFF, sum = 0
6895 12:22:15.965024 10, 0xFFFF, sum = 0
6896 12:22:15.965100 11, 0xFFFF, sum = 0
6897 12:22:15.967833 12, 0xFFFF, sum = 0
6898 12:22:15.967940 13, 0x0, sum = 1
6899 12:22:15.971359 14, 0x0, sum = 2
6900 12:22:15.971459 15, 0x0, sum = 3
6901 12:22:15.974911 16, 0x0, sum = 4
6902 12:22:15.975020 best_step = 14
6903 12:22:15.975100
6904 12:22:15.975176 ==
6905 12:22:15.977779 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 12:22:15.981333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 12:22:15.981446 ==
6908 12:22:15.984607 RX Vref Scan: 0
6909 12:22:15.984683
6910 12:22:15.987754 RX Vref 0 -> 0, step: 1
6911 12:22:15.987825
6912 12:22:15.987884 RX Delay -311 -> 252, step: 8
6913 12:22:15.996371 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6914 12:22:15.999888 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6915 12:22:16.003029 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6916 12:22:16.006322 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6917 12:22:16.012877 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6918 12:22:16.016590 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6919 12:22:16.019662 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6920 12:22:16.022870 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6921 12:22:16.029430 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6922 12:22:16.033008 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6923 12:22:16.036131 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6924 12:22:16.039726 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6925 12:22:16.046239 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6926 12:22:16.049796 iDelay=217, Bit 13, Center -12 (-231 ~ 208) 440
6927 12:22:16.052991 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6928 12:22:16.059449 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6929 12:22:16.059551 ==
6930 12:22:16.062935 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 12:22:16.066194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 12:22:16.066295 ==
6933 12:22:16.066385 DQS Delay:
6934 12:22:16.069453 DQS0 = 28, DQS1 = 32
6935 12:22:16.069520 DQM Delay:
6936 12:22:16.072727 DQM0 = 11, DQM1 = 11
6937 12:22:16.072823 DQ Delay:
6938 12:22:16.075732 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6939 12:22:16.079320 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6940 12:22:16.082289 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6941 12:22:16.086417 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6942 12:22:16.086489
6943 12:22:16.086549
6944 12:22:16.092675 [DQSOSCAuto] RK1, (LSB)MR18= 0xc85a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6945 12:22:16.095912 CH1 RK1: MR19=C0C, MR18=C85A
6946 12:22:16.102744 CH1_RK1: MR19=0xC0C, MR18=0xC85A, DQSOSC=385, MR23=63, INC=398, DEC=265
6947 12:22:16.105684 [RxdqsGatingPostProcess] freq 400
6948 12:22:16.112768 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6949 12:22:16.112856 best DQS0 dly(2T, 0.5T) = (0, 10)
6950 12:22:16.116502 best DQS1 dly(2T, 0.5T) = (0, 10)
6951 12:22:16.119223 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6952 12:22:16.122801 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6953 12:22:16.125685 best DQS0 dly(2T, 0.5T) = (0, 10)
6954 12:22:16.129384 best DQS1 dly(2T, 0.5T) = (0, 10)
6955 12:22:16.132590 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6956 12:22:16.136070 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6957 12:22:16.139202 Pre-setting of DQS Precalculation
6958 12:22:16.142619 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6959 12:22:16.152272 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6960 12:22:16.159363 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6961 12:22:16.159474
6962 12:22:16.159565
6963 12:22:16.162292 [Calibration Summary] 800 Mbps
6964 12:22:16.162366 CH 0, Rank 0
6965 12:22:16.165599 SW Impedance : PASS
6966 12:22:16.165666 DUTY Scan : NO K
6967 12:22:16.168909 ZQ Calibration : PASS
6968 12:22:16.172132 Jitter Meter : NO K
6969 12:22:16.172200 CBT Training : PASS
6970 12:22:16.175835 Write leveling : PASS
6971 12:22:16.179265 RX DQS gating : PASS
6972 12:22:16.179359 RX DQ/DQS(RDDQC) : PASS
6973 12:22:16.182073 TX DQ/DQS : PASS
6974 12:22:16.185363 RX DATLAT : PASS
6975 12:22:16.185432 RX DQ/DQS(Engine): PASS
6976 12:22:16.188733 TX OE : NO K
6977 12:22:16.188799 All Pass.
6978 12:22:16.188858
6979 12:22:16.192316 CH 0, Rank 1
6980 12:22:16.192384 SW Impedance : PASS
6981 12:22:16.195579 DUTY Scan : NO K
6982 12:22:16.198613 ZQ Calibration : PASS
6983 12:22:16.198707 Jitter Meter : NO K
6984 12:22:16.202008 CBT Training : PASS
6985 12:22:16.205468 Write leveling : NO K
6986 12:22:16.205540 RX DQS gating : PASS
6987 12:22:16.208525 RX DQ/DQS(RDDQC) : PASS
6988 12:22:16.212062 TX DQ/DQS : PASS
6989 12:22:16.212158 RX DATLAT : PASS
6990 12:22:16.215221 RX DQ/DQS(Engine): PASS
6991 12:22:16.215320 TX OE : NO K
6992 12:22:16.218780 All Pass.
6993 12:22:16.218850
6994 12:22:16.218911 CH 1, Rank 0
6995 12:22:16.222515 SW Impedance : PASS
6996 12:22:16.222593 DUTY Scan : NO K
6997 12:22:16.225215 ZQ Calibration : PASS
6998 12:22:16.228761 Jitter Meter : NO K
6999 12:22:16.228834 CBT Training : PASS
7000 12:22:16.231952 Write leveling : PASS
7001 12:22:16.235162 RX DQS gating : PASS
7002 12:22:16.235256 RX DQ/DQS(RDDQC) : PASS
7003 12:22:16.238474 TX DQ/DQS : PASS
7004 12:22:16.241647 RX DATLAT : PASS
7005 12:22:16.241747 RX DQ/DQS(Engine): PASS
7006 12:22:16.245603 TX OE : NO K
7007 12:22:16.245677 All Pass.
7008 12:22:16.245738
7009 12:22:16.248369 CH 1, Rank 1
7010 12:22:16.248462 SW Impedance : PASS
7011 12:22:16.251894 DUTY Scan : NO K
7012 12:22:16.254911 ZQ Calibration : PASS
7013 12:22:16.255004 Jitter Meter : NO K
7014 12:22:16.258605 CBT Training : PASS
7015 12:22:16.262133 Write leveling : NO K
7016 12:22:16.262226 RX DQS gating : PASS
7017 12:22:16.265481 RX DQ/DQS(RDDQC) : PASS
7018 12:22:16.265548 TX DQ/DQS : PASS
7019 12:22:16.268567 RX DATLAT : PASS
7020 12:22:16.271500 RX DQ/DQS(Engine): PASS
7021 12:22:16.271607 TX OE : NO K
7022 12:22:16.275240 All Pass.
7023 12:22:16.275331
7024 12:22:16.275420 DramC Write-DBI off
7025 12:22:16.278305 PER_BANK_REFRESH: Hybrid Mode
7026 12:22:16.281786 TX_TRACKING: ON
7027 12:22:16.288126 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7028 12:22:16.291902 [FAST_K] Save calibration result to emmc
7029 12:22:16.298105 dramc_set_vcore_voltage set vcore to 725000
7030 12:22:16.298177 Read voltage for 1600, 0
7031 12:22:16.298239 Vio18 = 0
7032 12:22:16.301461 Vcore = 725000
7033 12:22:16.301532 Vdram = 0
7034 12:22:16.301591 Vddq = 0
7035 12:22:16.304726 Vmddr = 0
7036 12:22:16.308041 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7037 12:22:16.315093 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7038 12:22:16.318081 MEM_TYPE=3, freq_sel=13
7039 12:22:16.318183 sv_algorithm_assistance_LP4_3733
7040 12:22:16.324698 ============ PULL DRAM RESETB DOWN ============
7041 12:22:16.328314 ========== PULL DRAM RESETB DOWN end =========
7042 12:22:16.331836 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7043 12:22:16.334714 ===================================
7044 12:22:16.338362 LPDDR4 DRAM CONFIGURATION
7045 12:22:16.341769 ===================================
7046 12:22:16.344774 EX_ROW_EN[0] = 0x0
7047 12:22:16.344849 EX_ROW_EN[1] = 0x0
7048 12:22:16.348314 LP4Y_EN = 0x0
7049 12:22:16.348385 WORK_FSP = 0x1
7050 12:22:16.351907 WL = 0x5
7051 12:22:16.352046 RL = 0x5
7052 12:22:16.354862 BL = 0x2
7053 12:22:16.354964 RPST = 0x0
7054 12:22:16.358304 RD_PRE = 0x0
7055 12:22:16.358405 WR_PRE = 0x1
7056 12:22:16.361272 WR_PST = 0x1
7057 12:22:16.361368 DBI_WR = 0x0
7058 12:22:16.364823 DBI_RD = 0x0
7059 12:22:16.364920 OTF = 0x1
7060 12:22:16.368373 ===================================
7061 12:22:16.371848 ===================================
7062 12:22:16.374822 ANA top config
7063 12:22:16.378396 ===================================
7064 12:22:16.381846 DLL_ASYNC_EN = 0
7065 12:22:16.381948 ALL_SLAVE_EN = 0
7066 12:22:16.385066 NEW_RANK_MODE = 1
7067 12:22:16.388454 DLL_IDLE_MODE = 1
7068 12:22:16.391336 LP45_APHY_COMB_EN = 1
7069 12:22:16.391434 TX_ODT_DIS = 0
7070 12:22:16.394827 NEW_8X_MODE = 1
7071 12:22:16.398328 ===================================
7072 12:22:16.401839 ===================================
7073 12:22:16.404992 data_rate = 3200
7074 12:22:16.407826 CKR = 1
7075 12:22:16.411505 DQ_P2S_RATIO = 8
7076 12:22:16.414924 ===================================
7077 12:22:16.418012 CA_P2S_RATIO = 8
7078 12:22:16.418111 DQ_CA_OPEN = 0
7079 12:22:16.421146 DQ_SEMI_OPEN = 0
7080 12:22:16.424643 CA_SEMI_OPEN = 0
7081 12:22:16.427990 CA_FULL_RATE = 0
7082 12:22:16.430989 DQ_CKDIV4_EN = 0
7083 12:22:16.434471 CA_CKDIV4_EN = 0
7084 12:22:16.434571 CA_PREDIV_EN = 0
7085 12:22:16.438127 PH8_DLY = 12
7086 12:22:16.441094 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7087 12:22:16.444702 DQ_AAMCK_DIV = 4
7088 12:22:16.447623 CA_AAMCK_DIV = 4
7089 12:22:16.451391 CA_ADMCK_DIV = 4
7090 12:22:16.451494 DQ_TRACK_CA_EN = 0
7091 12:22:16.454327 CA_PICK = 1600
7092 12:22:16.457794 CA_MCKIO = 1600
7093 12:22:16.461161 MCKIO_SEMI = 0
7094 12:22:16.464576 PLL_FREQ = 3068
7095 12:22:16.467940 DQ_UI_PI_RATIO = 32
7096 12:22:16.471216 CA_UI_PI_RATIO = 0
7097 12:22:16.474444 ===================================
7098 12:22:16.477807 ===================================
7099 12:22:16.477907 memory_type:LPDDR4
7100 12:22:16.481200 GP_NUM : 10
7101 12:22:16.484244 SRAM_EN : 1
7102 12:22:16.484347 MD32_EN : 0
7103 12:22:16.487856 ===================================
7104 12:22:16.491348 [ANA_INIT] >>>>>>>>>>>>>>
7105 12:22:16.494514 <<<<<< [CONFIGURE PHASE]: ANA_TX
7106 12:22:16.498117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7107 12:22:16.500973 ===================================
7108 12:22:16.504412 data_rate = 3200,PCW = 0X7600
7109 12:22:16.507793 ===================================
7110 12:22:16.510906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7111 12:22:16.514579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 12:22:16.521190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7113 12:22:16.524932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7114 12:22:16.528087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7115 12:22:16.531198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7116 12:22:16.534837 [ANA_INIT] flow start
7117 12:22:16.538105 [ANA_INIT] PLL >>>>>>>>
7118 12:22:16.538204 [ANA_INIT] PLL <<<<<<<<
7119 12:22:16.541035 [ANA_INIT] MIDPI >>>>>>>>
7120 12:22:16.544557 [ANA_INIT] MIDPI <<<<<<<<
7121 12:22:16.544630 [ANA_INIT] DLL >>>>>>>>
7122 12:22:16.548183 [ANA_INIT] DLL <<<<<<<<
7123 12:22:16.551109 [ANA_INIT] flow end
7124 12:22:16.554786 ============ LP4 DIFF to SE enter ============
7125 12:22:16.557759 ============ LP4 DIFF to SE exit ============
7126 12:22:16.561467 [ANA_INIT] <<<<<<<<<<<<<
7127 12:22:16.564549 [Flow] Enable top DCM control >>>>>
7128 12:22:16.568290 [Flow] Enable top DCM control <<<<<
7129 12:22:16.571118 Enable DLL master slave shuffle
7130 12:22:16.574416 ==============================================================
7131 12:22:16.577998 Gating Mode config
7132 12:22:16.584525 ==============================================================
7133 12:22:16.584629 Config description:
7134 12:22:16.594658 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7135 12:22:16.601351 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7136 12:22:16.604673 SELPH_MODE 0: By rank 1: By Phase
7137 12:22:16.611452 ==============================================================
7138 12:22:16.614475 GAT_TRACK_EN = 1
7139 12:22:16.617598 RX_GATING_MODE = 2
7140 12:22:16.621173 RX_GATING_TRACK_MODE = 2
7141 12:22:16.624545 SELPH_MODE = 1
7142 12:22:16.628034 PICG_EARLY_EN = 1
7143 12:22:16.628123 VALID_LAT_VALUE = 1
7144 12:22:16.634201 ==============================================================
7145 12:22:16.637991 Enter into Gating configuration >>>>
7146 12:22:16.640932 Exit from Gating configuration <<<<
7147 12:22:16.644532 Enter into DVFS_PRE_config >>>>>
7148 12:22:16.654123 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7149 12:22:16.657714 Exit from DVFS_PRE_config <<<<<
7150 12:22:16.661193 Enter into PICG configuration >>>>
7151 12:22:16.664271 Exit from PICG configuration <<<<
7152 12:22:16.667889 [RX_INPUT] configuration >>>>>
7153 12:22:16.671517 [RX_INPUT] configuration <<<<<
7154 12:22:16.674398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7155 12:22:16.680875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7156 12:22:16.687614 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7157 12:22:16.694299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7158 12:22:16.701194 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 12:22:16.707251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 12:22:16.710837 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7161 12:22:16.714172 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7162 12:22:16.717609 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7163 12:22:16.724465 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7164 12:22:16.727742 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7165 12:22:16.730988 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 12:22:16.733986 ===================================
7167 12:22:16.737563 LPDDR4 DRAM CONFIGURATION
7168 12:22:16.740877 ===================================
7169 12:22:16.740951 EX_ROW_EN[0] = 0x0
7170 12:22:16.744113 EX_ROW_EN[1] = 0x0
7171 12:22:16.744205 LP4Y_EN = 0x0
7172 12:22:16.747553 WORK_FSP = 0x1
7173 12:22:16.747683 WL = 0x5
7174 12:22:16.750499 RL = 0x5
7175 12:22:16.754326 BL = 0x2
7176 12:22:16.754426 RPST = 0x0
7177 12:22:16.757107 RD_PRE = 0x0
7178 12:22:16.757179 WR_PRE = 0x1
7179 12:22:16.760894 WR_PST = 0x1
7180 12:22:16.760965 DBI_WR = 0x0
7181 12:22:16.764199 DBI_RD = 0x0
7182 12:22:16.764294 OTF = 0x1
7183 12:22:16.767158 ===================================
7184 12:22:16.770874 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7185 12:22:16.777280 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7186 12:22:16.780423 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 12:22:16.783843 ===================================
7188 12:22:16.787567 LPDDR4 DRAM CONFIGURATION
7189 12:22:16.790758 ===================================
7190 12:22:16.790869 EX_ROW_EN[0] = 0x10
7191 12:22:16.793859 EX_ROW_EN[1] = 0x0
7192 12:22:16.793939 LP4Y_EN = 0x0
7193 12:22:16.797415 WORK_FSP = 0x1
7194 12:22:16.797517 WL = 0x5
7195 12:22:16.800762 RL = 0x5
7196 12:22:16.800838 BL = 0x2
7197 12:22:16.803868 RPST = 0x0
7198 12:22:16.803950 RD_PRE = 0x0
7199 12:22:16.807465 WR_PRE = 0x1
7200 12:22:16.807582 WR_PST = 0x1
7201 12:22:16.810777 DBI_WR = 0x0
7202 12:22:16.814105 DBI_RD = 0x0
7203 12:22:16.814182 OTF = 0x1
7204 12:22:16.817395 ===================================
7205 12:22:16.823806 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7206 12:22:16.823887 ==
7207 12:22:16.827040 Dram Type= 6, Freq= 0, CH_0, rank 0
7208 12:22:16.830531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7209 12:22:16.830634 ==
7210 12:22:16.833605 [Duty_Offset_Calibration]
7211 12:22:16.833680 B0:2 B1:1 CA:1
7212 12:22:16.836988
7213 12:22:16.837061 [DutyScan_Calibration_Flow] k_type=0
7214 12:22:16.848755
7215 12:22:16.848867 ==CLK 0==
7216 12:22:16.851805 Final CLK duty delay cell = 0
7217 12:22:16.855018 [0] MAX Duty = 5187%(X100), DQS PI = 24
7218 12:22:16.858180 [0] MIN Duty = 4876%(X100), DQS PI = 48
7219 12:22:16.861518 [0] AVG Duty = 5031%(X100)
7220 12:22:16.861593
7221 12:22:16.864791 CH0 CLK Duty spec in!! Max-Min= 311%
7222 12:22:16.868453 [DutyScan_Calibration_Flow] ====Done====
7223 12:22:16.868552
7224 12:22:16.871336 [DutyScan_Calibration_Flow] k_type=1
7225 12:22:16.887551
7226 12:22:16.887696 ==DQS 0 ==
7227 12:22:16.891070 Final DQS duty delay cell = -4
7228 12:22:16.894371 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7229 12:22:16.897526 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7230 12:22:16.900868 [-4] AVG Duty = 4906%(X100)
7231 12:22:16.900973
7232 12:22:16.901065 ==DQS 1 ==
7233 12:22:16.904151 Final DQS duty delay cell = 0
7234 12:22:16.907520 [0] MAX Duty = 5187%(X100), DQS PI = 4
7235 12:22:16.911069 [0] MIN Duty = 5062%(X100), DQS PI = 32
7236 12:22:16.914669 [0] AVG Duty = 5124%(X100)
7237 12:22:16.914769
7238 12:22:16.917791 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7239 12:22:16.917886
7240 12:22:16.920786 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7241 12:22:16.924316 [DutyScan_Calibration_Flow] ====Done====
7242 12:22:16.924416
7243 12:22:16.927892 [DutyScan_Calibration_Flow] k_type=3
7244 12:22:16.944374
7245 12:22:16.944447 ==DQM 0 ==
7246 12:22:16.947389 Final DQM duty delay cell = 0
7247 12:22:16.950600 [0] MAX Duty = 5218%(X100), DQS PI = 32
7248 12:22:16.954064 [0] MIN Duty = 4907%(X100), DQS PI = 56
7249 12:22:16.957514 [0] AVG Duty = 5062%(X100)
7250 12:22:16.957611
7251 12:22:16.957699 ==DQM 1 ==
7252 12:22:16.960881 Final DQM duty delay cell = -4
7253 12:22:16.964108 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7254 12:22:16.967486 [-4] MIN Duty = 4813%(X100), DQS PI = 34
7255 12:22:16.970709 [-4] AVG Duty = 4875%(X100)
7256 12:22:16.970778
7257 12:22:16.974240 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7258 12:22:16.974320
7259 12:22:16.977454 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7260 12:22:16.980607 [DutyScan_Calibration_Flow] ====Done====
7261 12:22:16.980679
7262 12:22:16.984098 [DutyScan_Calibration_Flow] k_type=2
7263 12:22:17.001812
7264 12:22:17.001895 ==DQ 0 ==
7265 12:22:17.004944 Final DQ duty delay cell = 0
7266 12:22:17.008255 [0] MAX Duty = 5093%(X100), DQS PI = 28
7267 12:22:17.011542 [0] MIN Duty = 4907%(X100), DQS PI = 0
7268 12:22:17.011666 [0] AVG Duty = 5000%(X100)
7269 12:22:17.014879
7270 12:22:17.014952 ==DQ 1 ==
7271 12:22:17.018315 Final DQ duty delay cell = 0
7272 12:22:17.021526 [0] MAX Duty = 5125%(X100), DQS PI = 6
7273 12:22:17.024993 [0] MIN Duty = 4938%(X100), DQS PI = 34
7274 12:22:17.025069 [0] AVG Duty = 5031%(X100)
7275 12:22:17.025131
7276 12:22:17.028354 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7277 12:22:17.031408
7278 12:22:17.034972 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7279 12:22:17.037905 [DutyScan_Calibration_Flow] ====Done====
7280 12:22:17.038002 ==
7281 12:22:17.041567 Dram Type= 6, Freq= 0, CH_1, rank 0
7282 12:22:17.045115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 12:22:17.045184 ==
7284 12:22:17.048167 [Duty_Offset_Calibration]
7285 12:22:17.048246 B0:1 B1:0 CA:0
7286 12:22:17.048307
7287 12:22:17.051516 [DutyScan_Calibration_Flow] k_type=0
7288 12:22:17.060869
7289 12:22:17.060943 ==CLK 0==
7290 12:22:17.064405 Final CLK duty delay cell = -4
7291 12:22:17.067679 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7292 12:22:17.070840 [-4] MIN Duty = 4875%(X100), DQS PI = 2
7293 12:22:17.074362 [-4] AVG Duty = 4937%(X100)
7294 12:22:17.074472
7295 12:22:17.077639 CH1 CLK Duty spec in!! Max-Min= 125%
7296 12:22:17.080437 [DutyScan_Calibration_Flow] ====Done====
7297 12:22:17.080509
7298 12:22:17.083752 [DutyScan_Calibration_Flow] k_type=1
7299 12:22:17.100774
7300 12:22:17.100866 ==DQS 0 ==
7301 12:22:17.104181 Final DQS duty delay cell = 0
7302 12:22:17.107512 [0] MAX Duty = 5094%(X100), DQS PI = 10
7303 12:22:17.111104 [0] MIN Duty = 4875%(X100), DQS PI = 0
7304 12:22:17.111205 [0] AVG Duty = 4984%(X100)
7305 12:22:17.114094
7306 12:22:17.114193 ==DQS 1 ==
7307 12:22:17.117443 Final DQS duty delay cell = 0
7308 12:22:17.120798 [0] MAX Duty = 5249%(X100), DQS PI = 16
7309 12:22:17.124542 [0] MIN Duty = 4969%(X100), DQS PI = 6
7310 12:22:17.124620 [0] AVG Duty = 5109%(X100)
7311 12:22:17.127427
7312 12:22:17.130796 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7313 12:22:17.130871
7314 12:22:17.134295 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7315 12:22:17.137379 [DutyScan_Calibration_Flow] ====Done====
7316 12:22:17.137476
7317 12:22:17.140661 [DutyScan_Calibration_Flow] k_type=3
7318 12:22:17.157568
7319 12:22:17.157647 ==DQM 0 ==
7320 12:22:17.161352 Final DQM duty delay cell = 0
7321 12:22:17.164378 [0] MAX Duty = 5218%(X100), DQS PI = 20
7322 12:22:17.167946 [0] MIN Duty = 4969%(X100), DQS PI = 48
7323 12:22:17.170916 [0] AVG Duty = 5093%(X100)
7324 12:22:17.170986
7325 12:22:17.171051 ==DQM 1 ==
7326 12:22:17.174324 Final DQM duty delay cell = 0
7327 12:22:17.177818 [0] MAX Duty = 5093%(X100), DQS PI = 40
7328 12:22:17.181129 [0] MIN Duty = 4907%(X100), DQS PI = 52
7329 12:22:17.184144 [0] AVG Duty = 5000%(X100)
7330 12:22:17.184213
7331 12:22:17.187611 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7332 12:22:17.187746
7333 12:22:17.190786 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7334 12:22:17.194293 [DutyScan_Calibration_Flow] ====Done====
7335 12:22:17.194365
7336 12:22:17.197626 [DutyScan_Calibration_Flow] k_type=2
7337 12:22:17.213900
7338 12:22:17.214000 ==DQ 0 ==
7339 12:22:17.217561 Final DQ duty delay cell = -4
7340 12:22:17.220890 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7341 12:22:17.223566 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7342 12:22:17.227295 [-4] AVG Duty = 4968%(X100)
7343 12:22:17.227397
7344 12:22:17.227499 ==DQ 1 ==
7345 12:22:17.230357 Final DQ duty delay cell = 0
7346 12:22:17.233897 [0] MAX Duty = 5124%(X100), DQS PI = 18
7347 12:22:17.237251 [0] MIN Duty = 4938%(X100), DQS PI = 8
7348 12:22:17.237354 [0] AVG Duty = 5031%(X100)
7349 12:22:17.240231
7350 12:22:17.243855 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7351 12:22:17.243931
7352 12:22:17.247392 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7353 12:22:17.250552 [DutyScan_Calibration_Flow] ====Done====
7354 12:22:17.253538 nWR fixed to 30
7355 12:22:17.253640 [ModeRegInit_LP4] CH0 RK0
7356 12:22:17.257114 [ModeRegInit_LP4] CH0 RK1
7357 12:22:17.260490 [ModeRegInit_LP4] CH1 RK0
7358 12:22:17.263551 [ModeRegInit_LP4] CH1 RK1
7359 12:22:17.263686 match AC timing 5
7360 12:22:17.270579 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7361 12:22:17.273642 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7362 12:22:17.277275 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7363 12:22:17.283727 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7364 12:22:17.286603 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7365 12:22:17.286701 [MiockJmeterHQA]
7366 12:22:17.286780
7367 12:22:17.290287 [DramcMiockJmeter] u1RxGatingPI = 0
7368 12:22:17.293503 0 : 4254, 4029
7369 12:22:17.293576 4 : 4252, 4027
7370 12:22:17.296603 8 : 4252, 4027
7371 12:22:17.296678 12 : 4252, 4027
7372 12:22:17.296757 16 : 4255, 4029
7373 12:22:17.299968 20 : 4252, 4027
7374 12:22:17.300068 24 : 4252, 4027
7375 12:22:17.303699 28 : 4363, 4138
7376 12:22:17.303772 32 : 4253, 4026
7377 12:22:17.306735 36 : 4252, 4027
7378 12:22:17.306848 40 : 4252, 4027
7379 12:22:17.310435 44 : 4255, 4029
7380 12:22:17.310534 48 : 4252, 4027
7381 12:22:17.310615 52 : 4363, 4137
7382 12:22:17.313644 56 : 4363, 4138
7383 12:22:17.313756 60 : 4250, 4027
7384 12:22:17.316628 64 : 4252, 4027
7385 12:22:17.316726 68 : 4252, 4027
7386 12:22:17.320105 72 : 4252, 4027
7387 12:22:17.320203 76 : 4253, 4029
7388 12:22:17.323577 80 : 4361, 4138
7389 12:22:17.323680 84 : 4250, 4027
7390 12:22:17.323763 88 : 4250, 46
7391 12:22:17.326663 92 : 4250, 0
7392 12:22:17.326738 96 : 4360, 0
7393 12:22:17.326817 100 : 4250, 0
7394 12:22:17.329981 104 : 4250, 0
7395 12:22:17.330082 108 : 4250, 0
7396 12:22:17.333224 112 : 4250, 0
7397 12:22:17.333333 116 : 4250, 0
7398 12:22:17.333435 120 : 4252, 0
7399 12:22:17.336759 124 : 4250, 0
7400 12:22:17.336860 128 : 4250, 0
7401 12:22:17.339909 132 : 4252, 0
7402 12:22:17.339983 136 : 4360, 0
7403 12:22:17.340066 140 : 4361, 0
7404 12:22:17.343514 144 : 4363, 0
7405 12:22:17.343635 148 : 4250, 0
7406 12:22:17.346818 152 : 4250, 0
7407 12:22:17.346913 156 : 4250, 0
7408 12:22:17.346992 160 : 4250, 0
7409 12:22:17.349732 164 : 4249, 0
7410 12:22:17.349811 168 : 4250, 0
7411 12:22:17.349900 172 : 4253, 0
7412 12:22:17.353245 176 : 4250, 0
7413 12:22:17.353345 180 : 4250, 0
7414 12:22:17.356927 184 : 4250, 0
7415 12:22:17.357006 188 : 4360, 0
7416 12:22:17.357088 192 : 4361, 0
7417 12:22:17.360131 196 : 4250, 0
7418 12:22:17.360206 200 : 4252, 0
7419 12:22:17.363365 204 : 4249, 1545
7420 12:22:17.363466 208 : 4250, 4019
7421 12:22:17.366288 212 : 4250, 4027
7422 12:22:17.366388 216 : 4250, 4026
7423 12:22:17.369915 220 : 4361, 4137
7424 12:22:17.370014 224 : 4361, 4138
7425 12:22:17.370114 228 : 4248, 4024
7426 12:22:17.373447 232 : 4360, 4137
7427 12:22:17.373556 236 : 4361, 4137
7428 12:22:17.376624 240 : 4250, 4027
7429 12:22:17.376698 244 : 4250, 4027
7430 12:22:17.380128 248 : 4363, 4140
7431 12:22:17.380228 252 : 4250, 4027
7432 12:22:17.383080 256 : 4250, 4027
7433 12:22:17.383179 260 : 4252, 4030
7434 12:22:17.386560 264 : 4252, 4029
7435 12:22:17.386663 268 : 4250, 4027
7436 12:22:17.389661 272 : 4250, 4027
7437 12:22:17.389768 276 : 4361, 4138
7438 12:22:17.392781 280 : 4250, 4027
7439 12:22:17.392865 284 : 4250, 4027
7440 12:22:17.396252 288 : 4361, 4138
7441 12:22:17.396360 292 : 4250, 4027
7442 12:22:17.396442 296 : 4250, 4027
7443 12:22:17.399682 300 : 4360, 4137
7444 12:22:17.399754 304 : 4250, 4027
7445 12:22:17.403152 308 : 4250, 3844
7446 12:22:17.403249 312 : 4250, 1565
7447 12:22:17.403335
7448 12:22:17.406105 MIOCK jitter meter ch=0
7449 12:22:17.406200
7450 12:22:17.409374 1T = (312-88) = 224 dly cells
7451 12:22:17.415934 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7452 12:22:17.416010 ==
7453 12:22:17.419487 Dram Type= 6, Freq= 0, CH_0, rank 0
7454 12:22:17.422971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7455 12:22:17.423058 ==
7456 12:22:17.429444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7457 12:22:17.432925 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7458 12:22:17.436271 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7459 12:22:17.442688 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7460 12:22:17.451489 [CA 0] Center 42 (12~73) winsize 62
7461 12:22:17.454675 [CA 1] Center 42 (12~73) winsize 62
7462 12:22:17.458379 [CA 2] Center 37 (8~67) winsize 60
7463 12:22:17.461319 [CA 3] Center 37 (7~67) winsize 61
7464 12:22:17.464711 [CA 4] Center 36 (6~66) winsize 61
7465 12:22:17.468326 [CA 5] Center 34 (5~64) winsize 60
7466 12:22:17.468435
7467 12:22:17.471177 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7468 12:22:17.471251
7469 12:22:17.474849 [CATrainingPosCal] consider 1 rank data
7470 12:22:17.477718 u2DelayCellTimex100 = 290/100 ps
7471 12:22:17.481290 CA0 delay=42 (12~73),Diff = 8 PI (26 cell)
7472 12:22:17.487790 CA1 delay=42 (12~73),Diff = 8 PI (26 cell)
7473 12:22:17.491365 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7474 12:22:17.494966 CA3 delay=37 (7~67),Diff = 3 PI (10 cell)
7475 12:22:17.498101 CA4 delay=36 (6~66),Diff = 2 PI (6 cell)
7476 12:22:17.501499 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
7477 12:22:17.501571
7478 12:22:17.504838 CA PerBit enable=1, Macro0, CA PI delay=34
7479 12:22:17.504909
7480 12:22:17.507945 [CBTSetCACLKResult] CA Dly = 34
7481 12:22:17.511366 CS Dly: 9 (0~40)
7482 12:22:17.514696 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7483 12:22:17.517763 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7484 12:22:17.517860 ==
7485 12:22:17.521289 Dram Type= 6, Freq= 0, CH_0, rank 1
7486 12:22:17.524754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 12:22:17.524872 ==
7488 12:22:17.531582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 12:22:17.534816 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 12:22:17.540951 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 12:22:17.544630 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 12:22:17.554815 [CA 0] Center 42 (12~73) winsize 62
7493 12:22:17.557983 [CA 1] Center 42 (12~73) winsize 62
7494 12:22:17.561545 [CA 2] Center 37 (8~67) winsize 60
7495 12:22:17.565077 [CA 3] Center 37 (8~67) winsize 60
7496 12:22:17.567871 [CA 4] Center 36 (6~66) winsize 61
7497 12:22:17.571251 [CA 5] Center 35 (5~65) winsize 61
7498 12:22:17.571327
7499 12:22:17.574758 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 12:22:17.574866
7501 12:22:17.578118 [CATrainingPosCal] consider 2 rank data
7502 12:22:17.581497 u2DelayCellTimex100 = 290/100 ps
7503 12:22:17.584819 CA0 delay=42 (12~73),Diff = 8 PI (26 cell)
7504 12:22:17.591174 CA1 delay=42 (12~73),Diff = 8 PI (26 cell)
7505 12:22:17.594915 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7506 12:22:17.598413 CA3 delay=37 (8~67),Diff = 3 PI (10 cell)
7507 12:22:17.601299 CA4 delay=36 (6~66),Diff = 2 PI (6 cell)
7508 12:22:17.604975 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
7509 12:22:17.605052
7510 12:22:17.607760 CA PerBit enable=1, Macro0, CA PI delay=34
7511 12:22:17.607837
7512 12:22:17.611246 [CBTSetCACLKResult] CA Dly = 34
7513 12:22:17.614875 CS Dly: 10 (0~42)
7514 12:22:17.617890 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 12:22:17.621198 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 12:22:17.621295
7517 12:22:17.624186 ----->DramcWriteLeveling(PI) begin...
7518 12:22:17.624263 ==
7519 12:22:17.627805 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 12:22:17.634268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 12:22:17.634370 ==
7522 12:22:17.637834 Write leveling (Byte 0): 36 => 36
7523 12:22:17.637931 Write leveling (Byte 1): 26 => 26
7524 12:22:17.641595 DramcWriteLeveling(PI) end<-----
7525 12:22:17.641692
7526 12:22:17.641791 ==
7527 12:22:17.644509 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 12:22:17.650838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 12:22:17.650940 ==
7530 12:22:17.654405 [Gating] SW mode calibration
7531 12:22:17.661351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7532 12:22:17.664370 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7533 12:22:17.671122 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 12:22:17.674897 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 12:22:17.677758 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7536 12:22:17.684132 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
7537 12:22:17.687826 1 4 16 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
7538 12:22:17.691163 1 4 20 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7539 12:22:17.694642 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 12:22:17.701195 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 12:22:17.704764 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7542 12:22:17.707715 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7543 12:22:17.714543 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7544 12:22:17.717663 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7545 12:22:17.721086 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7546 12:22:17.727529 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7547 12:22:17.731159 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7548 12:22:17.734183 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7549 12:22:17.741162 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 12:22:17.744217 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 12:22:17.747520 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7552 12:22:17.754758 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7553 12:22:17.757430 1 6 16 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
7554 12:22:17.761031 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 12:22:17.767481 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 12:22:17.770899 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 12:22:17.774257 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 12:22:17.781090 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 12:22:17.784536 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 12:22:17.787524 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7561 12:22:17.794536 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7562 12:22:17.797483 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7563 12:22:17.800779 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7564 12:22:17.807427 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 12:22:17.810994 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 12:22:17.814230 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 12:22:17.817281 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 12:22:17.824087 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 12:22:17.827620 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 12:22:17.831009 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 12:22:17.837446 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 12:22:17.841244 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 12:22:17.844104 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 12:22:17.850718 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 12:22:17.854333 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7576 12:22:17.857700 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7577 12:22:17.864126 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7578 12:22:17.867365 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 12:22:17.870681 Total UI for P1: 0, mck2ui 16
7580 12:22:17.873959 best dqsien dly found for B0: ( 1, 9, 12)
7581 12:22:17.877540 Total UI for P1: 0, mck2ui 16
7582 12:22:17.880844 best dqsien dly found for B1: ( 1, 9, 16)
7583 12:22:17.884192 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7584 12:22:17.887329 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7585 12:22:17.887400
7586 12:22:17.890876 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7587 12:22:17.894413 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7588 12:22:17.897224 [Gating] SW calibration Done
7589 12:22:17.897319 ==
7590 12:22:17.900640 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 12:22:17.904412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 12:22:17.907994 ==
7593 12:22:17.908102 RX Vref Scan: 0
7594 12:22:17.908186
7595 12:22:17.911050 RX Vref 0 -> 0, step: 1
7596 12:22:17.911153
7597 12:22:17.911257 RX Delay 0 -> 252, step: 8
7598 12:22:17.917328 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7599 12:22:17.920955 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7600 12:22:17.924306 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7601 12:22:17.927536 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7602 12:22:17.930943 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7603 12:22:17.937493 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7604 12:22:17.941162 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7605 12:22:17.944134 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7606 12:22:17.947359 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7607 12:22:17.950671 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7608 12:22:17.957265 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7609 12:22:17.960717 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7610 12:22:17.963860 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7611 12:22:17.967228 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7612 12:22:17.970787 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7613 12:22:17.977349 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7614 12:22:17.977454 ==
7615 12:22:17.980487 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 12:22:17.983832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 12:22:17.983903 ==
7618 12:22:17.983982 DQS Delay:
7619 12:22:17.987308 DQS0 = 0, DQS1 = 0
7620 12:22:17.987401 DQM Delay:
7621 12:22:17.990503 DQM0 = 136, DQM1 = 130
7622 12:22:17.990599 DQ Delay:
7623 12:22:17.993510 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7624 12:22:17.996844 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7625 12:22:18.000540 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7626 12:22:18.004010 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7627 12:22:18.006944
7628 12:22:18.007039
7629 12:22:18.007127 ==
7630 12:22:18.010558 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 12:22:18.013449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 12:22:18.013520 ==
7633 12:22:18.013580
7634 12:22:18.013667
7635 12:22:18.016902 TX Vref Scan disable
7636 12:22:18.016968 == TX Byte 0 ==
7637 12:22:18.023770 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7638 12:22:18.026730 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7639 12:22:18.026832 == TX Byte 1 ==
7640 12:22:18.033513 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7641 12:22:18.037082 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7642 12:22:18.037180 ==
7643 12:22:18.039904 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 12:22:18.043451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 12:22:18.043546 ==
7646 12:22:18.058215
7647 12:22:18.061310 TX Vref early break, caculate TX vref
7648 12:22:18.064797 TX Vref=16, minBit 7, minWin=22, winSum=377
7649 12:22:18.068499 TX Vref=18, minBit 0, minWin=23, winSum=385
7650 12:22:18.071386 TX Vref=20, minBit 0, minWin=24, winSum=400
7651 12:22:18.074831 TX Vref=22, minBit 0, minWin=24, winSum=404
7652 12:22:18.078258 TX Vref=24, minBit 2, minWin=25, winSum=415
7653 12:22:18.085057 TX Vref=26, minBit 1, minWin=25, winSum=425
7654 12:22:18.088474 TX Vref=28, minBit 2, minWin=24, winSum=423
7655 12:22:18.091273 TX Vref=30, minBit 1, minWin=24, winSum=410
7656 12:22:18.094590 TX Vref=32, minBit 6, minWin=23, winSum=403
7657 12:22:18.097781 TX Vref=34, minBit 0, minWin=24, winSum=398
7658 12:22:18.104746 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 26
7659 12:22:18.104821
7660 12:22:18.108274 Final TX Range 0 Vref 26
7661 12:22:18.108376
7662 12:22:18.108466 ==
7663 12:22:18.111152 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 12:22:18.114806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 12:22:18.114912 ==
7666 12:22:18.115002
7667 12:22:18.115097
7668 12:22:18.117798 TX Vref Scan disable
7669 12:22:18.124723 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7670 12:22:18.124825 == TX Byte 0 ==
7671 12:22:18.128160 u2DelayCellOfst[0]=10 cells (3 PI)
7672 12:22:18.131050 u2DelayCellOfst[1]=13 cells (4 PI)
7673 12:22:18.134739 u2DelayCellOfst[2]=10 cells (3 PI)
7674 12:22:18.138255 u2DelayCellOfst[3]=10 cells (3 PI)
7675 12:22:18.141903 u2DelayCellOfst[4]=6 cells (2 PI)
7676 12:22:18.144528 u2DelayCellOfst[5]=0 cells (0 PI)
7677 12:22:18.147833 u2DelayCellOfst[6]=13 cells (4 PI)
7678 12:22:18.147903 u2DelayCellOfst[7]=13 cells (4 PI)
7679 12:22:18.154257 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7680 12:22:18.157901 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7681 12:22:18.158004 == TX Byte 1 ==
7682 12:22:18.161368 u2DelayCellOfst[8]=3 cells (1 PI)
7683 12:22:18.164318 u2DelayCellOfst[9]=0 cells (0 PI)
7684 12:22:18.167895 u2DelayCellOfst[10]=6 cells (2 PI)
7685 12:22:18.171507 u2DelayCellOfst[11]=6 cells (2 PI)
7686 12:22:18.174685 u2DelayCellOfst[12]=10 cells (3 PI)
7687 12:22:18.177977 u2DelayCellOfst[13]=13 cells (4 PI)
7688 12:22:18.180836 u2DelayCellOfst[14]=13 cells (4 PI)
7689 12:22:18.184166 u2DelayCellOfst[15]=10 cells (3 PI)
7690 12:22:18.188120 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7691 12:22:18.194264 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7692 12:22:18.194367 DramC Write-DBI on
7693 12:22:18.194460 ==
7694 12:22:18.197699 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 12:22:18.200741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 12:22:18.200838 ==
7697 12:22:18.204251
7698 12:22:18.204342
7699 12:22:18.204431 TX Vref Scan disable
7700 12:22:18.207858 == TX Byte 0 ==
7701 12:22:18.211080 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7702 12:22:18.214170 == TX Byte 1 ==
7703 12:22:18.217302 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7704 12:22:18.220726 DramC Write-DBI off
7705 12:22:18.220796
7706 12:22:18.220857 [DATLAT]
7707 12:22:18.220921 Freq=1600, CH0 RK0
7708 12:22:18.220979
7709 12:22:18.224320 DATLAT Default: 0xf
7710 12:22:18.224392 0, 0xFFFF, sum = 0
7711 12:22:18.227774 1, 0xFFFF, sum = 0
7712 12:22:18.227849 2, 0xFFFF, sum = 0
7713 12:22:18.230813 3, 0xFFFF, sum = 0
7714 12:22:18.234388 4, 0xFFFF, sum = 0
7715 12:22:18.234489 5, 0xFFFF, sum = 0
7716 12:22:18.237891 6, 0xFFFF, sum = 0
7717 12:22:18.237987 7, 0xFFFF, sum = 0
7718 12:22:18.241134 8, 0xFFFF, sum = 0
7719 12:22:18.241234 9, 0xFFFF, sum = 0
7720 12:22:18.244386 10, 0xFFFF, sum = 0
7721 12:22:18.244492 11, 0xFFFF, sum = 0
7722 12:22:18.247406 12, 0xFFFF, sum = 0
7723 12:22:18.247503 13, 0xFFFF, sum = 0
7724 12:22:18.250913 14, 0x0, sum = 1
7725 12:22:18.251019 15, 0x0, sum = 2
7726 12:22:18.254397 16, 0x0, sum = 3
7727 12:22:18.254501 17, 0x0, sum = 4
7728 12:22:18.257473 best_step = 15
7729 12:22:18.257543
7730 12:22:18.257603 ==
7731 12:22:18.260750 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 12:22:18.264474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 12:22:18.264544 ==
7734 12:22:18.264604 RX Vref Scan: 1
7735 12:22:18.264662
7736 12:22:18.267307 Set Vref Range= 24 -> 127
7737 12:22:18.267408
7738 12:22:18.270839 RX Vref 24 -> 127, step: 1
7739 12:22:18.270934
7740 12:22:18.274401 RX Delay 27 -> 252, step: 4
7741 12:22:18.274503
7742 12:22:18.277542 Set Vref, RX VrefLevel [Byte0]: 24
7743 12:22:18.281022 [Byte1]: 24
7744 12:22:18.281116
7745 12:22:18.284037 Set Vref, RX VrefLevel [Byte0]: 25
7746 12:22:18.287126 [Byte1]: 25
7747 12:22:18.287222
7748 12:22:18.290483 Set Vref, RX VrefLevel [Byte0]: 26
7749 12:22:18.294047 [Byte1]: 26
7750 12:22:18.297850
7751 12:22:18.297944 Set Vref, RX VrefLevel [Byte0]: 27
7752 12:22:18.301116 [Byte1]: 27
7753 12:22:18.305138
7754 12:22:18.305235 Set Vref, RX VrefLevel [Byte0]: 28
7755 12:22:18.308463 [Byte1]: 28
7756 12:22:18.312789
7757 12:22:18.312861 Set Vref, RX VrefLevel [Byte0]: 29
7758 12:22:18.315766 [Byte1]: 29
7759 12:22:18.320086
7760 12:22:18.320184 Set Vref, RX VrefLevel [Byte0]: 30
7761 12:22:18.323317 [Byte1]: 30
7762 12:22:18.328165
7763 12:22:18.328275 Set Vref, RX VrefLevel [Byte0]: 31
7764 12:22:18.331308 [Byte1]: 31
7765 12:22:18.335154
7766 12:22:18.335230 Set Vref, RX VrefLevel [Byte0]: 32
7767 12:22:18.338870 [Byte1]: 32
7768 12:22:18.342925
7769 12:22:18.343019 Set Vref, RX VrefLevel [Byte0]: 33
7770 12:22:18.346412 [Byte1]: 33
7771 12:22:18.350674
7772 12:22:18.350776 Set Vref, RX VrefLevel [Byte0]: 34
7773 12:22:18.353754 [Byte1]: 34
7774 12:22:18.357729
7775 12:22:18.357827 Set Vref, RX VrefLevel [Byte0]: 35
7776 12:22:18.361295 [Byte1]: 35
7777 12:22:18.365480
7778 12:22:18.365550 Set Vref, RX VrefLevel [Byte0]: 36
7779 12:22:18.368747 [Byte1]: 36
7780 12:22:18.373301
7781 12:22:18.373383 Set Vref, RX VrefLevel [Byte0]: 37
7782 12:22:18.376284 [Byte1]: 37
7783 12:22:18.380424
7784 12:22:18.380492 Set Vref, RX VrefLevel [Byte0]: 38
7785 12:22:18.384177 [Byte1]: 38
7786 12:22:18.388075
7787 12:22:18.388148 Set Vref, RX VrefLevel [Byte0]: 39
7788 12:22:18.391523 [Byte1]: 39
7789 12:22:18.395694
7790 12:22:18.395769 Set Vref, RX VrefLevel [Byte0]: 40
7791 12:22:18.399297 [Byte1]: 40
7792 12:22:18.403357
7793 12:22:18.403455 Set Vref, RX VrefLevel [Byte0]: 41
7794 12:22:18.406580 [Byte1]: 41
7795 12:22:18.410519
7796 12:22:18.410618 Set Vref, RX VrefLevel [Byte0]: 42
7797 12:22:18.414506 [Byte1]: 42
7798 12:22:18.418103
7799 12:22:18.418200 Set Vref, RX VrefLevel [Byte0]: 43
7800 12:22:18.421721 [Byte1]: 43
7801 12:22:18.425808
7802 12:22:18.425909 Set Vref, RX VrefLevel [Byte0]: 44
7803 12:22:18.429309 [Byte1]: 44
7804 12:22:18.433191
7805 12:22:18.433293 Set Vref, RX VrefLevel [Byte0]: 45
7806 12:22:18.436602 [Byte1]: 45
7807 12:22:18.440645
7808 12:22:18.440747 Set Vref, RX VrefLevel [Byte0]: 46
7809 12:22:18.443978 [Byte1]: 46
7810 12:22:18.448066
7811 12:22:18.448177 Set Vref, RX VrefLevel [Byte0]: 47
7812 12:22:18.451503 [Byte1]: 47
7813 12:22:18.456164
7814 12:22:18.456241 Set Vref, RX VrefLevel [Byte0]: 48
7815 12:22:18.459310 [Byte1]: 48
7816 12:22:18.463622
7817 12:22:18.463715 Set Vref, RX VrefLevel [Byte0]: 49
7818 12:22:18.466625 [Byte1]: 49
7819 12:22:18.471300
7820 12:22:18.471398 Set Vref, RX VrefLevel [Byte0]: 50
7821 12:22:18.474588 [Byte1]: 50
7822 12:22:18.478539
7823 12:22:18.478607 Set Vref, RX VrefLevel [Byte0]: 51
7824 12:22:18.481855 [Byte1]: 51
7825 12:22:18.486025
7826 12:22:18.486099 Set Vref, RX VrefLevel [Byte0]: 52
7827 12:22:18.489096 [Byte1]: 52
7828 12:22:18.493301
7829 12:22:18.493372 Set Vref, RX VrefLevel [Byte0]: 53
7830 12:22:18.496936 [Byte1]: 53
7831 12:22:18.500836
7832 12:22:18.500931 Set Vref, RX VrefLevel [Byte0]: 54
7833 12:22:18.504517 [Byte1]: 54
7834 12:22:18.508608
7835 12:22:18.508707 Set Vref, RX VrefLevel [Byte0]: 55
7836 12:22:18.512259 [Byte1]: 55
7837 12:22:18.515903
7838 12:22:18.515981 Set Vref, RX VrefLevel [Byte0]: 56
7839 12:22:18.519132 [Byte1]: 56
7840 12:22:18.523700
7841 12:22:18.523803 Set Vref, RX VrefLevel [Byte0]: 57
7842 12:22:18.527183 [Byte1]: 57
7843 12:22:18.531221
7844 12:22:18.531330 Set Vref, RX VrefLevel [Byte0]: 58
7845 12:22:18.534618 [Byte1]: 58
7846 12:22:18.538848
7847 12:22:18.538970 Set Vref, RX VrefLevel [Byte0]: 59
7848 12:22:18.541811 [Byte1]: 59
7849 12:22:18.546495
7850 12:22:18.546608 Set Vref, RX VrefLevel [Byte0]: 60
7851 12:22:18.549688 [Byte1]: 60
7852 12:22:18.553571
7853 12:22:18.553669 Set Vref, RX VrefLevel [Byte0]: 61
7854 12:22:18.557077 [Byte1]: 61
7855 12:22:18.561011
7856 12:22:18.561079 Set Vref, RX VrefLevel [Byte0]: 62
7857 12:22:18.564597 [Byte1]: 62
7858 12:22:18.569078
7859 12:22:18.569179 Set Vref, RX VrefLevel [Byte0]: 63
7860 12:22:18.572339 [Byte1]: 63
7861 12:22:18.576635
7862 12:22:18.576721 Set Vref, RX VrefLevel [Byte0]: 64
7863 12:22:18.579493 [Byte1]: 64
7864 12:22:18.584074
7865 12:22:18.584180 Set Vref, RX VrefLevel [Byte0]: 65
7866 12:22:18.586930 [Byte1]: 65
7867 12:22:18.591739
7868 12:22:18.591843 Set Vref, RX VrefLevel [Byte0]: 66
7869 12:22:18.594919 [Byte1]: 66
7870 12:22:18.599156
7871 12:22:18.599252 Set Vref, RX VrefLevel [Byte0]: 67
7872 12:22:18.602583 [Byte1]: 67
7873 12:22:18.606565
7874 12:22:18.606667 Set Vref, RX VrefLevel [Byte0]: 68
7875 12:22:18.610016 [Byte1]: 68
7876 12:22:18.614172
7877 12:22:18.614279 Set Vref, RX VrefLevel [Byte0]: 69
7878 12:22:18.617263 [Byte1]: 69
7879 12:22:18.621319
7880 12:22:18.621422 Set Vref, RX VrefLevel [Byte0]: 70
7881 12:22:18.624563 [Byte1]: 70
7882 12:22:18.628836
7883 12:22:18.628937 Set Vref, RX VrefLevel [Byte0]: 71
7884 12:22:18.632642 [Byte1]: 71
7885 12:22:18.636524
7886 12:22:18.636614 Set Vref, RX VrefLevel [Byte0]: 72
7887 12:22:18.640013 [Byte1]: 72
7888 12:22:18.643968
7889 12:22:18.644066 Set Vref, RX VrefLevel [Byte0]: 73
7890 12:22:18.647504 [Byte1]: 73
7891 12:22:18.651764
7892 12:22:18.651839 Final RX Vref Byte 0 = 57 to rank0
7893 12:22:18.655126 Final RX Vref Byte 1 = 62 to rank0
7894 12:22:18.658570 Final RX Vref Byte 0 = 57 to rank1
7895 12:22:18.661398 Final RX Vref Byte 1 = 62 to rank1==
7896 12:22:18.664775 Dram Type= 6, Freq= 0, CH_0, rank 0
7897 12:22:18.671694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7898 12:22:18.671791 ==
7899 12:22:18.671890 DQS Delay:
7900 12:22:18.671978 DQS0 = 0, DQS1 = 0
7901 12:22:18.675228 DQM Delay:
7902 12:22:18.675332 DQM0 = 133, DQM1 = 127
7903 12:22:18.678500 DQ Delay:
7904 12:22:18.682024 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7905 12:22:18.685233 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7906 12:22:18.688140 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7907 12:22:18.691711 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7908 12:22:18.691781
7909 12:22:18.691842
7910 12:22:18.691918
7911 12:22:18.695165 [DramC_TX_OE_Calibration] TA2
7912 12:22:18.698041 Original DQ_B0 (3 6) =30, OEN = 27
7913 12:22:18.701762 Original DQ_B1 (3 6) =30, OEN = 27
7914 12:22:18.704759 24, 0x0, End_B0=24 End_B1=24
7915 12:22:18.704830 25, 0x0, End_B0=25 End_B1=25
7916 12:22:18.708335 26, 0x0, End_B0=26 End_B1=26
7917 12:22:18.711677 27, 0x0, End_B0=27 End_B1=27
7918 12:22:18.714755 28, 0x0, End_B0=28 End_B1=28
7919 12:22:18.714856 29, 0x0, End_B0=29 End_B1=29
7920 12:22:18.718185 30, 0x0, End_B0=30 End_B1=30
7921 12:22:18.721840 31, 0x5151, End_B0=30 End_B1=30
7922 12:22:18.724919 Byte0 end_step=30 best_step=27
7923 12:22:18.728331 Byte1 end_step=30 best_step=27
7924 12:22:18.731718 Byte0 TX OE(2T, 0.5T) = (3, 3)
7925 12:22:18.731789 Byte1 TX OE(2T, 0.5T) = (3, 3)
7926 12:22:18.731853
7927 12:22:18.734848
7928 12:22:18.741364 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7929 12:22:18.744653 CH0 RK0: MR19=303, MR18=2420
7930 12:22:18.751534 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7931 12:22:18.751699
7932 12:22:18.754587 ----->DramcWriteLeveling(PI) begin...
7933 12:22:18.754692 ==
7934 12:22:18.758038 Dram Type= 6, Freq= 0, CH_0, rank 1
7935 12:22:18.761463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7936 12:22:18.761570 ==
7937 12:22:18.764918 Write leveling (Byte 0): 37 => 37
7938 12:22:18.768441 Write leveling (Byte 1): 29 => 29
7939 12:22:18.771223 DramcWriteLeveling(PI) end<-----
7940 12:22:18.771327
7941 12:22:18.771417 ==
7942 12:22:18.774739 Dram Type= 6, Freq= 0, CH_0, rank 1
7943 12:22:18.778282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 12:22:18.778385 ==
7945 12:22:18.781202 [Gating] SW mode calibration
7946 12:22:18.787849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7947 12:22:18.794695 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7948 12:22:18.797813 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7949 12:22:18.801527 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7950 12:22:18.807954 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7951 12:22:18.811485 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7952 12:22:18.814308 1 4 16 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (1 1)
7953 12:22:18.820862 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7954 12:22:18.824367 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7955 12:22:18.827907 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7956 12:22:18.834244 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7957 12:22:18.837482 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7958 12:22:18.840850 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7959 12:22:18.847584 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)
7960 12:22:18.850734 1 5 16 | B1->B0 | 2d2d 2423 | 0 1 | (0 1) (1 0)
7961 12:22:18.853873 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7962 12:22:18.860545 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7963 12:22:18.864278 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7964 12:22:18.867509 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 12:22:18.874208 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 12:22:18.877588 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 12:22:18.880531 1 6 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
7968 12:22:18.887089 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7969 12:22:18.890692 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7970 12:22:18.894328 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7971 12:22:18.900593 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7972 12:22:18.904220 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7973 12:22:18.907511 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7974 12:22:18.914096 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7975 12:22:18.917294 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7976 12:22:18.920937 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7977 12:22:18.927500 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7978 12:22:18.930398 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7979 12:22:18.934032 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7980 12:22:18.937519 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7981 12:22:18.944189 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7982 12:22:18.947140 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 12:22:18.950657 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 12:22:18.957165 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 12:22:18.960624 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 12:22:18.963915 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 12:22:18.970280 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 12:22:18.973918 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 12:22:18.977300 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 12:22:18.983649 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 12:22:18.987549 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7992 12:22:18.990841 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7993 12:22:18.996954 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 12:22:18.997029 Total UI for P1: 0, mck2ui 16
7995 12:22:19.003972 best dqsien dly found for B0: ( 1, 9, 14)
7996 12:22:19.004050 Total UI for P1: 0, mck2ui 16
7997 12:22:19.010598 best dqsien dly found for B1: ( 1, 9, 14)
7998 12:22:19.013697 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7999 12:22:19.017386 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8000 12:22:19.017458
8001 12:22:19.020288 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8002 12:22:19.023814 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8003 12:22:19.027323 [Gating] SW calibration Done
8004 12:22:19.027400 ==
8005 12:22:19.030297 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 12:22:19.034041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 12:22:19.034155 ==
8008 12:22:19.036910 RX Vref Scan: 0
8009 12:22:19.037002
8010 12:22:19.037126 RX Vref 0 -> 0, step: 1
8011 12:22:19.037212
8012 12:22:19.040352 RX Delay 0 -> 252, step: 8
8013 12:22:19.043828 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8014 12:22:19.050333 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8015 12:22:19.053872 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8016 12:22:19.056940 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8017 12:22:19.060501 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8018 12:22:19.063478 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8019 12:22:19.070251 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8020 12:22:19.073942 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8021 12:22:19.076850 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8022 12:22:19.080286 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8023 12:22:19.083716 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8024 12:22:19.087074 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8025 12:22:19.093819 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8026 12:22:19.096976 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8027 12:22:19.100334 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8028 12:22:19.103571 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8029 12:22:19.103703 ==
8030 12:22:19.106630 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 12:22:19.113655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 12:22:19.113733 ==
8033 12:22:19.113825 DQS Delay:
8034 12:22:19.116600 DQS0 = 0, DQS1 = 0
8035 12:22:19.116672 DQM Delay:
8036 12:22:19.120352 DQM0 = 137, DQM1 = 130
8037 12:22:19.120444 DQ Delay:
8038 12:22:19.123245 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8039 12:22:19.127035 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8040 12:22:19.130142 DQ8 =123, DQ9 =119, DQ10 =127, DQ11 =123
8041 12:22:19.133471 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8042 12:22:19.133572
8043 12:22:19.133660
8044 12:22:19.133757 ==
8045 12:22:19.136942 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 12:22:19.143518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 12:22:19.143651 ==
8048 12:22:19.143732
8049 12:22:19.143792
8050 12:22:19.143849 TX Vref Scan disable
8051 12:22:19.147192 == TX Byte 0 ==
8052 12:22:19.150783 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8053 12:22:19.153630 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8054 12:22:19.156724 == TX Byte 1 ==
8055 12:22:19.160190 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8056 12:22:19.163871 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8057 12:22:19.166810 ==
8058 12:22:19.170337 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 12:22:19.174134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 12:22:19.174206 ==
8061 12:22:19.187883
8062 12:22:19.191200 TX Vref early break, caculate TX vref
8063 12:22:19.194659 TX Vref=16, minBit 1, minWin=23, winSum=385
8064 12:22:19.198239 TX Vref=18, minBit 1, minWin=23, winSum=395
8065 12:22:19.201038 TX Vref=20, minBit 1, minWin=24, winSum=402
8066 12:22:19.204455 TX Vref=22, minBit 3, minWin=24, winSum=412
8067 12:22:19.207772 TX Vref=24, minBit 1, minWin=25, winSum=417
8068 12:22:19.214738 TX Vref=26, minBit 1, minWin=24, winSum=422
8069 12:22:19.217515 TX Vref=28, minBit 3, minWin=25, winSum=424
8070 12:22:19.221176 TX Vref=30, minBit 4, minWin=24, winSum=417
8071 12:22:19.224519 TX Vref=32, minBit 2, minWin=25, winSum=411
8072 12:22:19.227872 TX Vref=34, minBit 0, minWin=24, winSum=404
8073 12:22:19.231326 TX Vref=36, minBit 8, minWin=23, winSum=392
8074 12:22:19.237481 [TxChooseVref] Worse bit 3, Min win 25, Win sum 424, Final Vref 28
8075 12:22:19.237553
8076 12:22:19.241483 Final TX Range 0 Vref 28
8077 12:22:19.241551
8078 12:22:19.241610 ==
8079 12:22:19.244354 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 12:22:19.247678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 12:22:19.247764 ==
8082 12:22:19.247825
8083 12:22:19.247882
8084 12:22:19.250847 TX Vref Scan disable
8085 12:22:19.257365 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8086 12:22:19.257439 == TX Byte 0 ==
8087 12:22:19.260958 u2DelayCellOfst[0]=16 cells (5 PI)
8088 12:22:19.263935 u2DelayCellOfst[1]=20 cells (6 PI)
8089 12:22:19.267580 u2DelayCellOfst[2]=13 cells (4 PI)
8090 12:22:19.270534 u2DelayCellOfst[3]=13 cells (4 PI)
8091 12:22:19.274218 u2DelayCellOfst[4]=10 cells (3 PI)
8092 12:22:19.277739 u2DelayCellOfst[5]=0 cells (0 PI)
8093 12:22:19.280694 u2DelayCellOfst[6]=16 cells (5 PI)
8094 12:22:19.284284 u2DelayCellOfst[7]=16 cells (5 PI)
8095 12:22:19.287395 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8096 12:22:19.290488 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8097 12:22:19.293734 == TX Byte 1 ==
8098 12:22:19.297059 u2DelayCellOfst[8]=0 cells (0 PI)
8099 12:22:19.300701 u2DelayCellOfst[9]=0 cells (0 PI)
8100 12:22:19.303680 u2DelayCellOfst[10]=6 cells (2 PI)
8101 12:22:19.303753 u2DelayCellOfst[11]=3 cells (1 PI)
8102 12:22:19.307089 u2DelayCellOfst[12]=13 cells (4 PI)
8103 12:22:19.310720 u2DelayCellOfst[13]=10 cells (3 PI)
8104 12:22:19.314083 u2DelayCellOfst[14]=13 cells (4 PI)
8105 12:22:19.317451 u2DelayCellOfst[15]=10 cells (3 PI)
8106 12:22:19.324170 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8107 12:22:19.327312 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8108 12:22:19.327387 DramC Write-DBI on
8109 12:22:19.327449 ==
8110 12:22:19.330841 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 12:22:19.336909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 12:22:19.336981 ==
8113 12:22:19.337042
8114 12:22:19.337099
8115 12:22:19.337159 TX Vref Scan disable
8116 12:22:19.341579 == TX Byte 0 ==
8117 12:22:19.344597 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8118 12:22:19.348343 == TX Byte 1 ==
8119 12:22:19.351528 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8120 12:22:19.351646 DramC Write-DBI off
8121 12:22:19.354739
8122 12:22:19.354830 [DATLAT]
8123 12:22:19.354918 Freq=1600, CH0 RK1
8124 12:22:19.355004
8125 12:22:19.358344 DATLAT Default: 0xf
8126 12:22:19.358411 0, 0xFFFF, sum = 0
8127 12:22:19.361295 1, 0xFFFF, sum = 0
8128 12:22:19.361361 2, 0xFFFF, sum = 0
8129 12:22:19.364845 3, 0xFFFF, sum = 0
8130 12:22:19.368386 4, 0xFFFF, sum = 0
8131 12:22:19.368453 5, 0xFFFF, sum = 0
8132 12:22:19.371267 6, 0xFFFF, sum = 0
8133 12:22:19.371361 7, 0xFFFF, sum = 0
8134 12:22:19.374738 8, 0xFFFF, sum = 0
8135 12:22:19.374813 9, 0xFFFF, sum = 0
8136 12:22:19.377795 10, 0xFFFF, sum = 0
8137 12:22:19.377878 11, 0xFFFF, sum = 0
8138 12:22:19.381357 12, 0xFFFF, sum = 0
8139 12:22:19.381452 13, 0xFFFF, sum = 0
8140 12:22:19.384375 14, 0x0, sum = 1
8141 12:22:19.384455 15, 0x0, sum = 2
8142 12:22:19.387914 16, 0x0, sum = 3
8143 12:22:19.388011 17, 0x0, sum = 4
8144 12:22:19.391374 best_step = 15
8145 12:22:19.391447
8146 12:22:19.391543 ==
8147 12:22:19.394348 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 12:22:19.398111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 12:22:19.398225 ==
8150 12:22:19.400979 RX Vref Scan: 0
8151 12:22:19.401074
8152 12:22:19.401136 RX Vref 0 -> 0, step: 1
8153 12:22:19.401194
8154 12:22:19.404472 RX Delay 19 -> 252, step: 4
8155 12:22:19.407687 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8156 12:22:19.414202 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8157 12:22:19.417660 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8158 12:22:19.420789 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8159 12:22:19.423986 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8160 12:22:19.427886 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8161 12:22:19.434145 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8162 12:22:19.437469 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8163 12:22:19.441257 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8164 12:22:19.444319 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8165 12:22:19.447370 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8166 12:22:19.454237 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8167 12:22:19.457815 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8168 12:22:19.460570 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8169 12:22:19.464299 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8170 12:22:19.470662 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8171 12:22:19.470743 ==
8172 12:22:19.473971 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 12:22:19.477489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 12:22:19.477574 ==
8175 12:22:19.477639 DQS Delay:
8176 12:22:19.480604 DQS0 = 0, DQS1 = 0
8177 12:22:19.480710 DQM Delay:
8178 12:22:19.484215 DQM0 = 134, DQM1 = 127
8179 12:22:19.484295 DQ Delay:
8180 12:22:19.487351 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8181 12:22:19.491024 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8182 12:22:19.493902 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8183 12:22:19.497604 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8184 12:22:19.497686
8185 12:22:19.497759
8186 12:22:19.497819
8187 12:22:19.500618 [DramC_TX_OE_Calibration] TA2
8188 12:22:19.503846 Original DQ_B0 (3 6) =30, OEN = 27
8189 12:22:19.507052 Original DQ_B1 (3 6) =30, OEN = 27
8190 12:22:19.510536 24, 0x0, End_B0=24 End_B1=24
8191 12:22:19.514219 25, 0x0, End_B0=25 End_B1=25
8192 12:22:19.514302 26, 0x0, End_B0=26 End_B1=26
8193 12:22:19.517477 27, 0x0, End_B0=27 End_B1=27
8194 12:22:19.520438 28, 0x0, End_B0=28 End_B1=28
8195 12:22:19.523798 29, 0x0, End_B0=29 End_B1=29
8196 12:22:19.527320 30, 0x0, End_B0=30 End_B1=30
8197 12:22:19.527402 31, 0x4141, End_B0=30 End_B1=30
8198 12:22:19.530300 Byte0 end_step=30 best_step=27
8199 12:22:19.533826 Byte1 end_step=30 best_step=27
8200 12:22:19.537194 Byte0 TX OE(2T, 0.5T) = (3, 3)
8201 12:22:19.540468 Byte1 TX OE(2T, 0.5T) = (3, 3)
8202 12:22:19.540549
8203 12:22:19.540613
8204 12:22:19.547381 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8205 12:22:19.550760 CH0 RK1: MR19=303, MR18=1F07
8206 12:22:19.557401 CH0_RK1: MR19=0x303, MR18=0x1F07, DQSOSC=394, MR23=63, INC=23, DEC=15
8207 12:22:19.560321 [RxdqsGatingPostProcess] freq 1600
8208 12:22:19.567414 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8209 12:22:19.567495 best DQS0 dly(2T, 0.5T) = (1, 1)
8210 12:22:19.570794 best DQS1 dly(2T, 0.5T) = (1, 1)
8211 12:22:19.574264 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8212 12:22:19.577045 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8213 12:22:19.580627 best DQS0 dly(2T, 0.5T) = (1, 1)
8214 12:22:19.584210 best DQS1 dly(2T, 0.5T) = (1, 1)
8215 12:22:19.587085 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8216 12:22:19.590749 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8217 12:22:19.594187 Pre-setting of DQS Precalculation
8218 12:22:19.597236 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8219 12:22:19.597316 ==
8220 12:22:19.600836 Dram Type= 6, Freq= 0, CH_1, rank 0
8221 12:22:19.607284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 12:22:19.607366 ==
8223 12:22:19.610390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8224 12:22:19.613679 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8225 12:22:19.620387 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8226 12:22:19.627149 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8227 12:22:19.634658 [CA 0] Center 42 (12~72) winsize 61
8228 12:22:19.637574 [CA 1] Center 42 (13~72) winsize 60
8229 12:22:19.641219 [CA 2] Center 38 (9~68) winsize 60
8230 12:22:19.644691 [CA 3] Center 38 (9~67) winsize 59
8231 12:22:19.647769 [CA 4] Center 38 (9~68) winsize 60
8232 12:22:19.650891 [CA 5] Center 37 (8~67) winsize 60
8233 12:22:19.650972
8234 12:22:19.654262 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8235 12:22:19.654343
8236 12:22:19.658031 [CATrainingPosCal] consider 1 rank data
8237 12:22:19.660988 u2DelayCellTimex100 = 290/100 ps
8238 12:22:19.664177 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8239 12:22:19.670821 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8240 12:22:19.674549 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8241 12:22:19.677952 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8242 12:22:19.681509 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8243 12:22:19.684283 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8244 12:22:19.684374
8245 12:22:19.687512 CA PerBit enable=1, Macro0, CA PI delay=37
8246 12:22:19.687599
8247 12:22:19.690843 [CBTSetCACLKResult] CA Dly = 37
8248 12:22:19.694330 CS Dly: 10 (0~41)
8249 12:22:19.698235 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8250 12:22:19.700862 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8251 12:22:19.700943 ==
8252 12:22:19.704525 Dram Type= 6, Freq= 0, CH_1, rank 1
8253 12:22:19.707409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 12:22:19.707490 ==
8255 12:22:19.713897 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8256 12:22:19.717326 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8257 12:22:19.724276 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8258 12:22:19.727422 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8259 12:22:19.737999 [CA 0] Center 42 (12~72) winsize 61
8260 12:22:19.741039 [CA 1] Center 41 (12~71) winsize 60
8261 12:22:19.744543 [CA 2] Center 38 (9~68) winsize 60
8262 12:22:19.747450 [CA 3] Center 38 (8~68) winsize 61
8263 12:22:19.751104 [CA 4] Center 38 (8~68) winsize 61
8264 12:22:19.754631 [CA 5] Center 37 (8~66) winsize 59
8265 12:22:19.754712
8266 12:22:19.757491 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8267 12:22:19.757572
8268 12:22:19.760725 [CATrainingPosCal] consider 2 rank data
8269 12:22:19.764209 u2DelayCellTimex100 = 290/100 ps
8270 12:22:19.767774 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8271 12:22:19.774097 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8272 12:22:19.777668 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8273 12:22:19.780751 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8274 12:22:19.784238 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8275 12:22:19.787497 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8276 12:22:19.787578
8277 12:22:19.790569 CA PerBit enable=1, Macro0, CA PI delay=37
8278 12:22:19.790649
8279 12:22:19.794229 [CBTSetCACLKResult] CA Dly = 37
8280 12:22:19.797697 CS Dly: 12 (0~45)
8281 12:22:19.800702 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8282 12:22:19.803831 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8283 12:22:19.803912
8284 12:22:19.807244 ----->DramcWriteLeveling(PI) begin...
8285 12:22:19.807326 ==
8286 12:22:19.810443 Dram Type= 6, Freq= 0, CH_1, rank 0
8287 12:22:19.814060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 12:22:19.817123 ==
8289 12:22:19.820458 Write leveling (Byte 0): 26 => 26
8290 12:22:19.820544 Write leveling (Byte 1): 29 => 29
8291 12:22:19.823775 DramcWriteLeveling(PI) end<-----
8292 12:22:19.823860
8293 12:22:19.823946 ==
8294 12:22:19.827256 Dram Type= 6, Freq= 0, CH_1, rank 0
8295 12:22:19.834237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 12:22:19.834323 ==
8297 12:22:19.837198 [Gating] SW mode calibration
8298 12:22:19.843991 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8299 12:22:19.847232 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8300 12:22:19.854091 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8301 12:22:19.857057 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8302 12:22:19.860563 1 4 8 | B1->B0 | 2323 3030 | 1 1 | (1 1) (1 1)
8303 12:22:19.867007 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8304 12:22:19.870528 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8305 12:22:19.873934 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8306 12:22:19.877363 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8307 12:22:19.883596 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8308 12:22:19.887357 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8309 12:22:19.890648 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 12:22:19.897158 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8311 12:22:19.900594 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8312 12:22:19.903690 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 12:22:19.910230 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 12:22:19.913941 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 12:22:19.917070 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 12:22:19.923885 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 12:22:19.927037 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 12:22:19.930337 1 6 8 | B1->B0 | 2b2b 4242 | 0 0 | (0 0) (0 0)
8319 12:22:19.936837 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8320 12:22:19.940106 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8321 12:22:19.943505 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8322 12:22:19.950574 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8323 12:22:19.954030 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8324 12:22:19.956963 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 12:22:19.963526 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 12:22:19.966915 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8327 12:22:19.970581 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8328 12:22:19.976556 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8329 12:22:19.980122 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8330 12:22:19.983478 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8331 12:22:19.990243 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8332 12:22:19.993586 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 12:22:19.996618 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 12:22:20.003549 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 12:22:20.006607 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 12:22:20.009914 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 12:22:20.016613 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 12:22:20.019954 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 12:22:20.023408 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 12:22:20.026771 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 12:22:20.033355 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 12:22:20.036538 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 12:22:20.040177 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8344 12:22:20.046499 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 12:22:20.049572 Total UI for P1: 0, mck2ui 16
8346 12:22:20.053068 best dqsien dly found for B0: ( 1, 9, 12)
8347 12:22:20.056690 Total UI for P1: 0, mck2ui 16
8348 12:22:20.059545 best dqsien dly found for B1: ( 1, 9, 12)
8349 12:22:20.062751 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8350 12:22:20.066775 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8351 12:22:20.066861
8352 12:22:20.069500 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8353 12:22:20.072735 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8354 12:22:20.076145 [Gating] SW calibration Done
8355 12:22:20.076254 ==
8356 12:22:20.079466 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 12:22:20.082885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 12:22:20.082970 ==
8359 12:22:20.086083 RX Vref Scan: 0
8360 12:22:20.086168
8361 12:22:20.089685 RX Vref 0 -> 0, step: 1
8362 12:22:20.089774
8363 12:22:20.089865 RX Delay 0 -> 252, step: 8
8364 12:22:20.096211 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8365 12:22:20.099853 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8366 12:22:20.102944 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8367 12:22:20.106372 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8368 12:22:20.109340 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8369 12:22:20.112829 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8370 12:22:20.119829 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8371 12:22:20.122595 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8372 12:22:20.126064 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8373 12:22:20.129461 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8374 12:22:20.132918 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8375 12:22:20.139331 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8376 12:22:20.142774 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8377 12:22:20.146117 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8378 12:22:20.149418 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8379 12:22:20.155941 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8380 12:22:20.156026 ==
8381 12:22:20.159372 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 12:22:20.162375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 12:22:20.162458 ==
8384 12:22:20.162524 DQS Delay:
8385 12:22:20.165796 DQS0 = 0, DQS1 = 0
8386 12:22:20.165878 DQM Delay:
8387 12:22:20.169227 DQM0 = 137, DQM1 = 132
8388 12:22:20.169309 DQ Delay:
8389 12:22:20.172491 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8390 12:22:20.175522 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8391 12:22:20.179365 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8392 12:22:20.182453 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8393 12:22:20.182553
8394 12:22:20.182624
8395 12:22:20.182685 ==
8396 12:22:20.185728 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 12:22:20.192645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 12:22:20.192728 ==
8399 12:22:20.192794
8400 12:22:20.192855
8401 12:22:20.192914 TX Vref Scan disable
8402 12:22:20.196415 == TX Byte 0 ==
8403 12:22:20.199842 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8404 12:22:20.202811 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8405 12:22:20.206410 == TX Byte 1 ==
8406 12:22:20.209411 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8407 12:22:20.216383 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8408 12:22:20.216465 ==
8409 12:22:20.219334 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 12:22:20.222585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 12:22:20.222675 ==
8412 12:22:20.234908
8413 12:22:20.238373 TX Vref early break, caculate TX vref
8414 12:22:20.241878 TX Vref=16, minBit 0, minWin=22, winSum=370
8415 12:22:20.245309 TX Vref=18, minBit 0, minWin=23, winSum=385
8416 12:22:20.248367 TX Vref=20, minBit 1, minWin=23, winSum=393
8417 12:22:20.251903 TX Vref=22, minBit 1, minWin=23, winSum=403
8418 12:22:20.254803 TX Vref=24, minBit 1, minWin=24, winSum=414
8419 12:22:20.261526 TX Vref=26, minBit 0, minWin=25, winSum=421
8420 12:22:20.265078 TX Vref=28, minBit 1, minWin=25, winSum=425
8421 12:22:20.268201 TX Vref=30, minBit 1, minWin=25, winSum=417
8422 12:22:20.271237 TX Vref=32, minBit 0, minWin=24, winSum=410
8423 12:22:20.275250 TX Vref=34, minBit 2, minWin=23, winSum=398
8424 12:22:20.281628 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28
8425 12:22:20.281716
8426 12:22:20.285045 Final TX Range 0 Vref 28
8427 12:22:20.285127
8428 12:22:20.285191 ==
8429 12:22:20.288213 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 12:22:20.291504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 12:22:20.291587 ==
8432 12:22:20.291692
8433 12:22:20.291753
8434 12:22:20.294662 TX Vref Scan disable
8435 12:22:20.301515 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8436 12:22:20.301597 == TX Byte 0 ==
8437 12:22:20.305043 u2DelayCellOfst[0]=23 cells (7 PI)
8438 12:22:20.308069 u2DelayCellOfst[1]=13 cells (4 PI)
8439 12:22:20.311625 u2DelayCellOfst[2]=0 cells (0 PI)
8440 12:22:20.314663 u2DelayCellOfst[3]=10 cells (3 PI)
8441 12:22:20.318081 u2DelayCellOfst[4]=13 cells (4 PI)
8442 12:22:20.321646 u2DelayCellOfst[5]=23 cells (7 PI)
8443 12:22:20.324933 u2DelayCellOfst[6]=23 cells (7 PI)
8444 12:22:20.328369 u2DelayCellOfst[7]=10 cells (3 PI)
8445 12:22:20.331331 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8446 12:22:20.334620 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8447 12:22:20.338354 == TX Byte 1 ==
8448 12:22:20.338436 u2DelayCellOfst[8]=0 cells (0 PI)
8449 12:22:20.341247 u2DelayCellOfst[9]=3 cells (1 PI)
8450 12:22:20.344820 u2DelayCellOfst[10]=10 cells (3 PI)
8451 12:22:20.347819 u2DelayCellOfst[11]=6 cells (2 PI)
8452 12:22:20.351191 u2DelayCellOfst[12]=13 cells (4 PI)
8453 12:22:20.354818 u2DelayCellOfst[13]=16 cells (5 PI)
8454 12:22:20.358449 u2DelayCellOfst[14]=16 cells (5 PI)
8455 12:22:20.361297 u2DelayCellOfst[15]=16 cells (5 PI)
8456 12:22:20.364294 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8457 12:22:20.371179 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8458 12:22:20.371262 DramC Write-DBI on
8459 12:22:20.371327 ==
8460 12:22:20.374332 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 12:22:20.377882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 12:22:20.380918 ==
8463 12:22:20.381000
8464 12:22:20.381065
8465 12:22:20.381124 TX Vref Scan disable
8466 12:22:20.384934 == TX Byte 0 ==
8467 12:22:20.387802 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8468 12:22:20.391140 == TX Byte 1 ==
8469 12:22:20.394590 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8470 12:22:20.394677 DramC Write-DBI off
8471 12:22:20.397808
8472 12:22:20.397890 [DATLAT]
8473 12:22:20.397955 Freq=1600, CH1 RK0
8474 12:22:20.398016
8475 12:22:20.401099 DATLAT Default: 0xf
8476 12:22:20.401181 0, 0xFFFF, sum = 0
8477 12:22:20.404362 1, 0xFFFF, sum = 0
8478 12:22:20.404445 2, 0xFFFF, sum = 0
8479 12:22:20.407736 3, 0xFFFF, sum = 0
8480 12:22:20.411133 4, 0xFFFF, sum = 0
8481 12:22:20.411217 5, 0xFFFF, sum = 0
8482 12:22:20.414740 6, 0xFFFF, sum = 0
8483 12:22:20.414823 7, 0xFFFF, sum = 0
8484 12:22:20.418313 8, 0xFFFF, sum = 0
8485 12:22:20.418482 9, 0xFFFF, sum = 0
8486 12:22:20.421401 10, 0xFFFF, sum = 0
8487 12:22:20.421530 11, 0xFFFF, sum = 0
8488 12:22:20.424957 12, 0xFFFF, sum = 0
8489 12:22:20.425131 13, 0xFFFF, sum = 0
8490 12:22:20.428136 14, 0x0, sum = 1
8491 12:22:20.428316 15, 0x0, sum = 2
8492 12:22:20.431602 16, 0x0, sum = 3
8493 12:22:20.431753 17, 0x0, sum = 4
8494 12:22:20.434632 best_step = 15
8495 12:22:20.434742
8496 12:22:20.434831 ==
8497 12:22:20.438012 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 12:22:20.441453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 12:22:20.441590 ==
8500 12:22:20.441699 RX Vref Scan: 1
8501 12:22:20.441800
8502 12:22:20.445065 Set Vref Range= 24 -> 127
8503 12:22:20.445201
8504 12:22:20.447967 RX Vref 24 -> 127, step: 1
8505 12:22:20.448119
8506 12:22:20.451561 RX Delay 27 -> 252, step: 4
8507 12:22:20.451843
8508 12:22:20.454828 Set Vref, RX VrefLevel [Byte0]: 24
8509 12:22:20.457939 [Byte1]: 24
8510 12:22:20.458251
8511 12:22:20.461369 Set Vref, RX VrefLevel [Byte0]: 25
8512 12:22:20.465293 [Byte1]: 25
8513 12:22:20.465647
8514 12:22:20.468001 Set Vref, RX VrefLevel [Byte0]: 26
8515 12:22:20.472110 [Byte1]: 26
8516 12:22:20.475356
8517 12:22:20.475792 Set Vref, RX VrefLevel [Byte0]: 27
8518 12:22:20.478850 [Byte1]: 27
8519 12:22:20.483023
8520 12:22:20.483649 Set Vref, RX VrefLevel [Byte0]: 28
8521 12:22:20.486128 [Byte1]: 28
8522 12:22:20.490648
8523 12:22:20.491246 Set Vref, RX VrefLevel [Byte0]: 29
8524 12:22:20.493637 [Byte1]: 29
8525 12:22:20.497841
8526 12:22:20.498280 Set Vref, RX VrefLevel [Byte0]: 30
8527 12:22:20.501146 [Byte1]: 30
8528 12:22:20.505034
8529 12:22:20.505467 Set Vref, RX VrefLevel [Byte0]: 31
8530 12:22:20.508478 [Byte1]: 31
8531 12:22:20.513089
8532 12:22:20.513640 Set Vref, RX VrefLevel [Byte0]: 32
8533 12:22:20.516254 [Byte1]: 32
8534 12:22:20.520497
8535 12:22:20.521041 Set Vref, RX VrefLevel [Byte0]: 33
8536 12:22:20.523976 [Byte1]: 33
8537 12:22:20.527860
8538 12:22:20.528303 Set Vref, RX VrefLevel [Byte0]: 34
8539 12:22:20.531315 [Byte1]: 34
8540 12:22:20.535966
8541 12:22:20.536403 Set Vref, RX VrefLevel [Byte0]: 35
8542 12:22:20.538860 [Byte1]: 35
8543 12:22:20.542941
8544 12:22:20.543485 Set Vref, RX VrefLevel [Byte0]: 36
8545 12:22:20.546188 [Byte1]: 36
8546 12:22:20.550400
8547 12:22:20.550948 Set Vref, RX VrefLevel [Byte0]: 37
8548 12:22:20.553823 [Byte1]: 37
8549 12:22:20.558351
8550 12:22:20.558906 Set Vref, RX VrefLevel [Byte0]: 38
8551 12:22:20.561585 [Byte1]: 38
8552 12:22:20.566071
8553 12:22:20.566627 Set Vref, RX VrefLevel [Byte0]: 39
8554 12:22:20.571925 [Byte1]: 39
8555 12:22:20.572383
8556 12:22:20.575356 Set Vref, RX VrefLevel [Byte0]: 40
8557 12:22:20.578302 [Byte1]: 40
8558 12:22:20.578743
8559 12:22:20.581779 Set Vref, RX VrefLevel [Byte0]: 41
8560 12:22:20.585309 [Byte1]: 41
8561 12:22:20.585749
8562 12:22:20.588311 Set Vref, RX VrefLevel [Byte0]: 42
8563 12:22:20.591762 [Byte1]: 42
8564 12:22:20.595866
8565 12:22:20.596405 Set Vref, RX VrefLevel [Byte0]: 43
8566 12:22:20.599129 [Byte1]: 43
8567 12:22:20.603028
8568 12:22:20.603464 Set Vref, RX VrefLevel [Byte0]: 44
8569 12:22:20.606865 [Byte1]: 44
8570 12:22:20.610596
8571 12:22:20.611035 Set Vref, RX VrefLevel [Byte0]: 45
8572 12:22:20.614006 [Byte1]: 45
8573 12:22:20.618361
8574 12:22:20.618796 Set Vref, RX VrefLevel [Byte0]: 46
8575 12:22:20.621339 [Byte1]: 46
8576 12:22:20.625573
8577 12:22:20.626010 Set Vref, RX VrefLevel [Byte0]: 47
8578 12:22:20.628997 [Byte1]: 47
8579 12:22:20.633167
8580 12:22:20.633602 Set Vref, RX VrefLevel [Byte0]: 48
8581 12:22:20.637061 [Byte1]: 48
8582 12:22:20.641032
8583 12:22:20.641520 Set Vref, RX VrefLevel [Byte0]: 49
8584 12:22:20.644394 [Byte1]: 49
8585 12:22:20.648555
8586 12:22:20.648998 Set Vref, RX VrefLevel [Byte0]: 50
8587 12:22:20.651879 [Byte1]: 50
8588 12:22:20.655938
8589 12:22:20.656378 Set Vref, RX VrefLevel [Byte0]: 51
8590 12:22:20.659547 [Byte1]: 51
8591 12:22:20.663867
8592 12:22:20.664307 Set Vref, RX VrefLevel [Byte0]: 52
8593 12:22:20.666559 [Byte1]: 52
8594 12:22:20.671158
8595 12:22:20.671624 Set Vref, RX VrefLevel [Byte0]: 53
8596 12:22:20.674596 [Byte1]: 53
8597 12:22:20.678381
8598 12:22:20.678815 Set Vref, RX VrefLevel [Byte0]: 54
8599 12:22:20.681716 [Byte1]: 54
8600 12:22:20.685810
8601 12:22:20.686226 Set Vref, RX VrefLevel [Byte0]: 55
8602 12:22:20.689298 [Byte1]: 55
8603 12:22:20.693482
8604 12:22:20.693900 Set Vref, RX VrefLevel [Byte0]: 56
8605 12:22:20.696928 [Byte1]: 56
8606 12:22:20.701091
8607 12:22:20.701574 Set Vref, RX VrefLevel [Byte0]: 57
8608 12:22:20.704526 [Byte1]: 57
8609 12:22:20.708701
8610 12:22:20.709118 Set Vref, RX VrefLevel [Byte0]: 58
8611 12:22:20.712080 [Byte1]: 58
8612 12:22:20.715907
8613 12:22:20.716325 Set Vref, RX VrefLevel [Byte0]: 59
8614 12:22:20.719317 [Byte1]: 59
8615 12:22:20.723537
8616 12:22:20.724018 Set Vref, RX VrefLevel [Byte0]: 60
8617 12:22:20.727174 [Byte1]: 60
8618 12:22:20.731338
8619 12:22:20.731826 Set Vref, RX VrefLevel [Byte0]: 61
8620 12:22:20.734205 [Byte1]: 61
8621 12:22:20.738474
8622 12:22:20.738893 Set Vref, RX VrefLevel [Byte0]: 62
8623 12:22:20.741865 [Byte1]: 62
8624 12:22:20.746213
8625 12:22:20.746633 Set Vref, RX VrefLevel [Byte0]: 63
8626 12:22:20.749492 [Byte1]: 63
8627 12:22:20.754205
8628 12:22:20.754624 Set Vref, RX VrefLevel [Byte0]: 64
8629 12:22:20.757013 [Byte1]: 64
8630 12:22:20.761130
8631 12:22:20.761549 Set Vref, RX VrefLevel [Byte0]: 65
8632 12:22:20.764770 [Byte1]: 65
8633 12:22:20.768751
8634 12:22:20.769168 Set Vref, RX VrefLevel [Byte0]: 66
8635 12:22:20.772587 [Byte1]: 66
8636 12:22:20.776227
8637 12:22:20.776649 Set Vref, RX VrefLevel [Byte0]: 67
8638 12:22:20.779544 [Byte1]: 67
8639 12:22:20.783687
8640 12:22:20.784112 Set Vref, RX VrefLevel [Byte0]: 68
8641 12:22:20.787276 [Byte1]: 68
8642 12:22:20.791402
8643 12:22:20.791863 Set Vref, RX VrefLevel [Byte0]: 69
8644 12:22:20.794957 [Byte1]: 69
8645 12:22:20.799206
8646 12:22:20.799667 Set Vref, RX VrefLevel [Byte0]: 70
8647 12:22:20.803169 [Byte1]: 70
8648 12:22:20.806426
8649 12:22:20.806842 Set Vref, RX VrefLevel [Byte0]: 71
8650 12:22:20.809915 [Byte1]: 71
8651 12:22:20.813948
8652 12:22:20.814368 Set Vref, RX VrefLevel [Byte0]: 72
8653 12:22:20.817384 [Byte1]: 72
8654 12:22:20.821550
8655 12:22:20.821848 Set Vref, RX VrefLevel [Byte0]: 73
8656 12:22:20.824973 [Byte1]: 73
8657 12:22:20.829296
8658 12:22:20.829521 Set Vref, RX VrefLevel [Byte0]: 74
8659 12:22:20.835488 [Byte1]: 74
8660 12:22:20.835692
8661 12:22:20.838524 Set Vref, RX VrefLevel [Byte0]: 75
8662 12:22:20.841943 [Byte1]: 75
8663 12:22:20.842074
8664 12:22:20.845692 Final RX Vref Byte 0 = 57 to rank0
8665 12:22:20.848806 Final RX Vref Byte 1 = 58 to rank0
8666 12:22:20.851719 Final RX Vref Byte 0 = 57 to rank1
8667 12:22:20.855438 Final RX Vref Byte 1 = 58 to rank1==
8668 12:22:20.858603 Dram Type= 6, Freq= 0, CH_1, rank 0
8669 12:22:20.861954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8670 12:22:20.862051 ==
8671 12:22:20.865247 DQS Delay:
8672 12:22:20.865365 DQS0 = 0, DQS1 = 0
8673 12:22:20.865463 DQM Delay:
8674 12:22:20.868684 DQM0 = 134, DQM1 = 131
8675 12:22:20.868776 DQ Delay:
8676 12:22:20.872152 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8677 12:22:20.875148 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8678 12:22:20.878215 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8679 12:22:20.885284 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8680 12:22:20.885375
8681 12:22:20.885441
8682 12:22:20.885502
8683 12:22:20.888133 [DramC_TX_OE_Calibration] TA2
8684 12:22:20.888215 Original DQ_B0 (3 6) =30, OEN = 27
8685 12:22:20.891517 Original DQ_B1 (3 6) =30, OEN = 27
8686 12:22:20.895132 24, 0x0, End_B0=24 End_B1=24
8687 12:22:20.898473 25, 0x0, End_B0=25 End_B1=25
8688 12:22:20.901396 26, 0x0, End_B0=26 End_B1=26
8689 12:22:20.905014 27, 0x0, End_B0=27 End_B1=27
8690 12:22:20.905099 28, 0x0, End_B0=28 End_B1=28
8691 12:22:20.908608 29, 0x0, End_B0=29 End_B1=29
8692 12:22:20.911907 30, 0x0, End_B0=30 End_B1=30
8693 12:22:20.915241 31, 0x4545, End_B0=30 End_B1=30
8694 12:22:20.918306 Byte0 end_step=30 best_step=27
8695 12:22:20.918396 Byte1 end_step=30 best_step=27
8696 12:22:20.921828 Byte0 TX OE(2T, 0.5T) = (3, 3)
8697 12:22:20.925300 Byte1 TX OE(2T, 0.5T) = (3, 3)
8698 12:22:20.925387
8699 12:22:20.925452
8700 12:22:20.935352 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8701 12:22:20.935482 CH1 RK0: MR19=303, MR18=1825
8702 12:22:20.941750 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8703 12:22:20.941837
8704 12:22:20.945179 ----->DramcWriteLeveling(PI) begin...
8705 12:22:20.945264 ==
8706 12:22:20.948356 Dram Type= 6, Freq= 0, CH_1, rank 1
8707 12:22:20.955104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8708 12:22:20.955202 ==
8709 12:22:20.958371 Write leveling (Byte 0): 25 => 25
8710 12:22:20.958475 Write leveling (Byte 1): 29 => 29
8711 12:22:20.961855 DramcWriteLeveling(PI) end<-----
8712 12:22:20.961964
8713 12:22:20.965020 ==
8714 12:22:20.965110 Dram Type= 6, Freq= 0, CH_1, rank 1
8715 12:22:20.971738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 12:22:20.971847 ==
8717 12:22:20.975092 [Gating] SW mode calibration
8718 12:22:20.982119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8719 12:22:20.985036 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8720 12:22:20.991938 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8721 12:22:20.995446 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8722 12:22:20.998410 1 4 8 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8723 12:22:21.005333 1 4 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8724 12:22:21.008255 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8725 12:22:21.011876 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8726 12:22:21.018505 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8727 12:22:21.022136 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8728 12:22:21.025268 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8729 12:22:21.028279 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8730 12:22:21.034862 1 5 8 | B1->B0 | 2626 3434 | 0 1 | (0 1) (1 0)
8731 12:22:21.038454 1 5 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
8732 12:22:21.041386 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 12:22:21.048530 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 12:22:21.051436 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8735 12:22:21.055061 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 12:22:21.061763 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 12:22:21.065002 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 12:22:21.068301 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8739 12:22:21.074917 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8740 12:22:21.078229 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8741 12:22:21.081408 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8742 12:22:21.088009 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8743 12:22:21.091540 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8744 12:22:21.095014 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8745 12:22:21.101517 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8746 12:22:21.104804 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8747 12:22:21.108507 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8748 12:22:21.115178 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8749 12:22:21.118460 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 12:22:21.122036 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 12:22:21.128435 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 12:22:21.131678 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 12:22:21.135132 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 12:22:21.138635 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 12:22:21.145340 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 12:22:21.148365 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 12:22:21.151751 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 12:22:21.158229 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 12:22:21.161819 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 12:22:21.165456 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 12:22:21.171819 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 12:22:21.175172 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8763 12:22:21.178554 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8764 12:22:21.181516 Total UI for P1: 0, mck2ui 16
8765 12:22:21.184865 best dqsien dly found for B1: ( 1, 9, 8)
8766 12:22:21.191702 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 12:22:21.192126 Total UI for P1: 0, mck2ui 16
8768 12:22:21.198258 best dqsien dly found for B0: ( 1, 9, 10)
8769 12:22:21.201886 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8770 12:22:21.205227 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8771 12:22:21.205648
8772 12:22:21.208406 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8773 12:22:21.211469 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8774 12:22:21.214950 [Gating] SW calibration Done
8775 12:22:21.215369 ==
8776 12:22:21.218218 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 12:22:21.221474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 12:22:21.221896 ==
8779 12:22:21.225171 RX Vref Scan: 0
8780 12:22:21.225589
8781 12:22:21.225922 RX Vref 0 -> 0, step: 1
8782 12:22:21.226232
8783 12:22:21.228652 RX Delay 0 -> 252, step: 8
8784 12:22:21.231578 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8785 12:22:21.238507 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8786 12:22:21.241692 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8787 12:22:21.245147 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8788 12:22:21.248077 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8789 12:22:21.251771 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8790 12:22:21.258362 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8791 12:22:21.261675 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8792 12:22:21.264813 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8793 12:22:21.268225 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8794 12:22:21.271140 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8795 12:22:21.278308 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8796 12:22:21.281654 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8797 12:22:21.284548 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8798 12:22:21.288045 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8799 12:22:21.291385 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8800 12:22:21.294790 ==
8801 12:22:21.295240 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 12:22:21.301253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 12:22:21.301785 ==
8804 12:22:21.302254 DQS Delay:
8805 12:22:21.304565 DQS0 = 0, DQS1 = 0
8806 12:22:21.304987 DQM Delay:
8807 12:22:21.308201 DQM0 = 136, DQM1 = 133
8808 12:22:21.308620 DQ Delay:
8809 12:22:21.311683 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8810 12:22:21.314660 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8811 12:22:21.317923 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8812 12:22:21.321667 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8813 12:22:21.322186
8814 12:22:21.322521
8815 12:22:21.322833 ==
8816 12:22:21.324913 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 12:22:21.331415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 12:22:21.331974 ==
8819 12:22:21.332313
8820 12:22:21.332621
8821 12:22:21.332919 TX Vref Scan disable
8822 12:22:21.335198 == TX Byte 0 ==
8823 12:22:21.338374 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8824 12:22:21.341851 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8825 12:22:21.345109 == TX Byte 1 ==
8826 12:22:21.348032 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8827 12:22:21.351540 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8828 12:22:21.355068 ==
8829 12:22:21.358751 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 12:22:21.361336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 12:22:21.361877 ==
8832 12:22:21.375027
8833 12:22:21.378448 TX Vref early break, caculate TX vref
8834 12:22:21.382013 TX Vref=16, minBit 0, minWin=22, winSum=382
8835 12:22:21.384839 TX Vref=18, minBit 2, minWin=23, winSum=389
8836 12:22:21.388203 TX Vref=20, minBit 10, minWin=23, winSum=394
8837 12:22:21.391714 TX Vref=22, minBit 0, minWin=24, winSum=405
8838 12:22:21.394894 TX Vref=24, minBit 1, minWin=25, winSum=414
8839 12:22:21.401924 TX Vref=26, minBit 1, minWin=25, winSum=423
8840 12:22:21.405358 TX Vref=28, minBit 0, minWin=25, winSum=423
8841 12:22:21.407883 TX Vref=30, minBit 0, minWin=25, winSum=419
8842 12:22:21.411489 TX Vref=32, minBit 0, minWin=24, winSum=411
8843 12:22:21.414395 TX Vref=34, minBit 0, minWin=24, winSum=405
8844 12:22:21.418009 TX Vref=36, minBit 0, minWin=23, winSum=393
8845 12:22:21.424638 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 26
8846 12:22:21.425105
8847 12:22:21.428199 Final TX Range 0 Vref 26
8848 12:22:21.428664
8849 12:22:21.429028 ==
8850 12:22:21.431042 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 12:22:21.434709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 12:22:21.435195 ==
8853 12:22:21.435567
8854 12:22:21.436094
8855 12:22:21.438258 TX Vref Scan disable
8856 12:22:21.445003 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8857 12:22:21.445744 == TX Byte 0 ==
8858 12:22:21.448112 u2DelayCellOfst[0]=16 cells (5 PI)
8859 12:22:21.451030 u2DelayCellOfst[1]=13 cells (4 PI)
8860 12:22:21.454438 u2DelayCellOfst[2]=0 cells (0 PI)
8861 12:22:21.457973 u2DelayCellOfst[3]=10 cells (3 PI)
8862 12:22:21.461480 u2DelayCellOfst[4]=10 cells (3 PI)
8863 12:22:21.464569 u2DelayCellOfst[5]=20 cells (6 PI)
8864 12:22:21.468058 u2DelayCellOfst[6]=20 cells (6 PI)
8865 12:22:21.470911 u2DelayCellOfst[7]=6 cells (2 PI)
8866 12:22:21.474788 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8867 12:22:21.478315 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8868 12:22:21.481033 == TX Byte 1 ==
8869 12:22:21.484691 u2DelayCellOfst[8]=0 cells (0 PI)
8870 12:22:21.487527 u2DelayCellOfst[9]=6 cells (2 PI)
8871 12:22:21.488055 u2DelayCellOfst[10]=13 cells (4 PI)
8872 12:22:21.491251 u2DelayCellOfst[11]=6 cells (2 PI)
8873 12:22:21.494555 u2DelayCellOfst[12]=16 cells (5 PI)
8874 12:22:21.497845 u2DelayCellOfst[13]=16 cells (5 PI)
8875 12:22:21.501364 u2DelayCellOfst[14]=20 cells (6 PI)
8876 12:22:21.504300 u2DelayCellOfst[15]=20 cells (6 PI)
8877 12:22:21.510814 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8878 12:22:21.514157 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8879 12:22:21.514577 DramC Write-DBI on
8880 12:22:21.514916 ==
8881 12:22:21.517635 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 12:22:21.524307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 12:22:21.524728 ==
8884 12:22:21.525060
8885 12:22:21.525365
8886 12:22:21.525661 TX Vref Scan disable
8887 12:22:21.528250 == TX Byte 0 ==
8888 12:22:21.531631 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8889 12:22:21.534598 == TX Byte 1 ==
8890 12:22:21.538241 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8891 12:22:21.541574 DramC Write-DBI off
8892 12:22:21.542014
8893 12:22:21.542344 [DATLAT]
8894 12:22:21.542649 Freq=1600, CH1 RK1
8895 12:22:21.542945
8896 12:22:21.544689 DATLAT Default: 0xf
8897 12:22:21.545109 0, 0xFFFF, sum = 0
8898 12:22:21.547710 1, 0xFFFF, sum = 0
8899 12:22:21.551672 2, 0xFFFF, sum = 0
8900 12:22:21.552118 3, 0xFFFF, sum = 0
8901 12:22:21.554474 4, 0xFFFF, sum = 0
8902 12:22:21.554897 5, 0xFFFF, sum = 0
8903 12:22:21.558495 6, 0xFFFF, sum = 0
8904 12:22:21.558927 7, 0xFFFF, sum = 0
8905 12:22:21.561631 8, 0xFFFF, sum = 0
8906 12:22:21.562054 9, 0xFFFF, sum = 0
8907 12:22:21.564494 10, 0xFFFF, sum = 0
8908 12:22:21.565095 11, 0xFFFF, sum = 0
8909 12:22:21.568003 12, 0xFFFF, sum = 0
8910 12:22:21.568513 13, 0xFFFF, sum = 0
8911 12:22:21.571757 14, 0x0, sum = 1
8912 12:22:21.572348 15, 0x0, sum = 2
8913 12:22:21.574408 16, 0x0, sum = 3
8914 12:22:21.574996 17, 0x0, sum = 4
8915 12:22:21.578136 best_step = 15
8916 12:22:21.578217
8917 12:22:21.578283 ==
8918 12:22:21.581144 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 12:22:21.584103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 12:22:21.584211 ==
8921 12:22:21.584296 RX Vref Scan: 0
8922 12:22:21.587584
8923 12:22:21.587724 RX Vref 0 -> 0, step: 1
8924 12:22:21.587810
8925 12:22:21.590658 RX Delay 19 -> 252, step: 4
8926 12:22:21.594276 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8927 12:22:21.600794 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8928 12:22:21.604368 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8929 12:22:21.608174 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8930 12:22:21.611091 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8931 12:22:21.614129 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8932 12:22:21.617443 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8933 12:22:21.624227 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8934 12:22:21.627765 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8935 12:22:21.631366 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8936 12:22:21.634166 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8937 12:22:21.637883 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8938 12:22:21.644531 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8939 12:22:21.647338 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8940 12:22:21.650978 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8941 12:22:21.654086 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8942 12:22:21.654287 ==
8943 12:22:21.657710 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 12:22:21.664545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 12:22:21.664976 ==
8946 12:22:21.665356 DQS Delay:
8947 12:22:21.667367 DQS0 = 0, DQS1 = 0
8948 12:22:21.667802 DQM Delay:
8949 12:22:21.670910 DQM0 = 133, DQM1 = 130
8950 12:22:21.671226 DQ Delay:
8951 12:22:21.674447 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
8952 12:22:21.677555 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8953 12:22:21.681403 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8954 12:22:21.684714 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8955 12:22:21.685033
8956 12:22:21.685271
8957 12:22:21.685502
8958 12:22:21.687880 [DramC_TX_OE_Calibration] TA2
8959 12:22:21.691094 Original DQ_B0 (3 6) =30, OEN = 27
8960 12:22:21.694269 Original DQ_B1 (3 6) =30, OEN = 27
8961 12:22:21.697914 24, 0x0, End_B0=24 End_B1=24
8962 12:22:21.698325 25, 0x0, End_B0=25 End_B1=25
8963 12:22:21.700816 26, 0x0, End_B0=26 End_B1=26
8964 12:22:21.704453 27, 0x0, End_B0=27 End_B1=27
8965 12:22:21.708056 28, 0x0, End_B0=28 End_B1=28
8966 12:22:21.710981 29, 0x0, End_B0=29 End_B1=29
8967 12:22:21.711284 30, 0x0, End_B0=30 End_B1=30
8968 12:22:21.714053 31, 0x4141, End_B0=30 End_B1=30
8969 12:22:21.717952 Byte0 end_step=30 best_step=27
8970 12:22:21.720996 Byte1 end_step=30 best_step=27
8971 12:22:21.723987 Byte0 TX OE(2T, 0.5T) = (3, 3)
8972 12:22:21.727579 Byte1 TX OE(2T, 0.5T) = (3, 3)
8973 12:22:21.727910
8974 12:22:21.728148
8975 12:22:21.734318 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8976 12:22:21.737426 CH1 RK1: MR19=303, MR18=2106
8977 12:22:21.744248 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
8978 12:22:21.747637 [RxdqsGatingPostProcess] freq 1600
8979 12:22:21.750798 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8980 12:22:21.754136 best DQS0 dly(2T, 0.5T) = (1, 1)
8981 12:22:21.757872 best DQS1 dly(2T, 0.5T) = (1, 1)
8982 12:22:21.761248 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8983 12:22:21.764321 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8984 12:22:21.768132 best DQS0 dly(2T, 0.5T) = (1, 1)
8985 12:22:21.771407 best DQS1 dly(2T, 0.5T) = (1, 1)
8986 12:22:21.774460 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8987 12:22:21.777939 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8988 12:22:21.781033 Pre-setting of DQS Precalculation
8989 12:22:21.784556 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8990 12:22:21.791331 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8991 12:22:21.798398 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8992 12:22:21.798803
8993 12:22:21.799052
8994 12:22:21.801429 [Calibration Summary] 3200 Mbps
8995 12:22:21.804596 CH 0, Rank 0
8996 12:22:21.804907 SW Impedance : PASS
8997 12:22:21.807674 DUTY Scan : NO K
8998 12:22:21.811203 ZQ Calibration : PASS
8999 12:22:21.811501 Jitter Meter : NO K
9000 12:22:21.814605 CBT Training : PASS
9001 12:22:21.817970 Write leveling : PASS
9002 12:22:21.818279 RX DQS gating : PASS
9003 12:22:21.821643 RX DQ/DQS(RDDQC) : PASS
9004 12:22:21.822030 TX DQ/DQS : PASS
9005 12:22:21.825129 RX DATLAT : PASS
9006 12:22:21.827820 RX DQ/DQS(Engine): PASS
9007 12:22:21.828385 TX OE : PASS
9008 12:22:21.831387 All Pass.
9009 12:22:21.831855
9010 12:22:21.832192 CH 0, Rank 1
9011 12:22:21.834900 SW Impedance : PASS
9012 12:22:21.835321 DUTY Scan : NO K
9013 12:22:21.838426 ZQ Calibration : PASS
9014 12:22:21.841814 Jitter Meter : NO K
9015 12:22:21.842342 CBT Training : PASS
9016 12:22:21.845026 Write leveling : PASS
9017 12:22:21.848362 RX DQS gating : PASS
9018 12:22:21.848784 RX DQ/DQS(RDDQC) : PASS
9019 12:22:21.851650 TX DQ/DQS : PASS
9020 12:22:21.854755 RX DATLAT : PASS
9021 12:22:21.855225 RX DQ/DQS(Engine): PASS
9022 12:22:21.858055 TX OE : PASS
9023 12:22:21.858480 All Pass.
9024 12:22:21.858813
9025 12:22:21.861332 CH 1, Rank 0
9026 12:22:21.861978 SW Impedance : PASS
9027 12:22:21.864430 DUTY Scan : NO K
9028 12:22:21.868306 ZQ Calibration : PASS
9029 12:22:21.868869 Jitter Meter : NO K
9030 12:22:21.871272 CBT Training : PASS
9031 12:22:21.871911 Write leveling : PASS
9032 12:22:21.874251 RX DQS gating : PASS
9033 12:22:21.878001 RX DQ/DQS(RDDQC) : PASS
9034 12:22:21.878570 TX DQ/DQS : PASS
9035 12:22:21.881356 RX DATLAT : PASS
9036 12:22:21.884230 RX DQ/DQS(Engine): PASS
9037 12:22:21.884785 TX OE : PASS
9038 12:22:21.887702 All Pass.
9039 12:22:21.888305
9040 12:22:21.888835 CH 1, Rank 1
9041 12:22:21.891269 SW Impedance : PASS
9042 12:22:21.891903 DUTY Scan : NO K
9043 12:22:21.894373 ZQ Calibration : PASS
9044 12:22:21.898144 Jitter Meter : NO K
9045 12:22:21.898438 CBT Training : PASS
9046 12:22:21.900943 Write leveling : PASS
9047 12:22:21.904652 RX DQS gating : PASS
9048 12:22:21.904947 RX DQ/DQS(RDDQC) : PASS
9049 12:22:21.907724 TX DQ/DQS : PASS
9050 12:22:21.911275 RX DATLAT : PASS
9051 12:22:21.911570 RX DQ/DQS(Engine): PASS
9052 12:22:21.914152 TX OE : PASS
9053 12:22:21.914449 All Pass.
9054 12:22:21.914710
9055 12:22:21.917319 DramC Write-DBI on
9056 12:22:21.920614 PER_BANK_REFRESH: Hybrid Mode
9057 12:22:21.920909 TX_TRACKING: ON
9058 12:22:21.930875 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9059 12:22:21.937579 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9060 12:22:21.944067 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 12:22:21.947731 [FAST_K] Save calibration result to emmc
9062 12:22:21.950704 sync common calibartion params.
9063 12:22:21.954097 sync cbt_mode0:1, 1:1
9064 12:22:21.954395 dram_init: ddr_geometry: 2
9065 12:22:21.957651 dram_init: ddr_geometry: 2
9066 12:22:21.960641 dram_init: ddr_geometry: 2
9067 12:22:21.964275 0:dram_rank_size:100000000
9068 12:22:21.964580 1:dram_rank_size:100000000
9069 12:22:21.970799 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9070 12:22:21.974467 DFS_SHUFFLE_HW_MODE: ON
9071 12:22:21.977561 dramc_set_vcore_voltage set vcore to 725000
9072 12:22:21.981098 Read voltage for 1600, 0
9073 12:22:21.981638 Vio18 = 0
9074 12:22:21.982125 Vcore = 725000
9075 12:22:21.983856 Vdram = 0
9076 12:22:21.984385 Vddq = 0
9077 12:22:21.984853 Vmddr = 0
9078 12:22:21.987330 switch to 3200 Mbps bootup
9079 12:22:21.987876 [DramcRunTimeConfig]
9080 12:22:21.990827 PHYPLL
9081 12:22:21.991344 DPM_CONTROL_AFTERK: ON
9082 12:22:21.994277 PER_BANK_REFRESH: ON
9083 12:22:21.997304 REFRESH_OVERHEAD_REDUCTION: ON
9084 12:22:21.997809 CMD_PICG_NEW_MODE: OFF
9085 12:22:22.000681 XRTWTW_NEW_MODE: ON
9086 12:22:22.001223 XRTRTR_NEW_MODE: ON
9087 12:22:22.004132 TX_TRACKING: ON
9088 12:22:22.004550 RDSEL_TRACKING: OFF
9089 12:22:22.007688 DQS Precalculation for DVFS: ON
9090 12:22:22.010602 RX_TRACKING: OFF
9091 12:22:22.011123 HW_GATING DBG: ON
9092 12:22:22.013743 ZQCS_ENABLE_LP4: ON
9093 12:22:22.014273 RX_PICG_NEW_MODE: ON
9094 12:22:22.017225 TX_PICG_NEW_MODE: ON
9095 12:22:22.017596 ENABLE_RX_DCM_DPHY: ON
9096 12:22:22.020356 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9097 12:22:22.023967 DUMMY_READ_FOR_TRACKING: OFF
9098 12:22:22.026725 !!! SPM_CONTROL_AFTERK: OFF
9099 12:22:22.030528 !!! SPM could not control APHY
9100 12:22:22.030765 IMPEDANCE_TRACKING: ON
9101 12:22:22.033686 TEMP_SENSOR: ON
9102 12:22:22.033926 HW_SAVE_FOR_SR: OFF
9103 12:22:22.036926 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9104 12:22:22.040599 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9105 12:22:22.043687 Read ODT Tracking: ON
9106 12:22:22.046898 Refresh Rate DeBounce: ON
9107 12:22:22.047071 DFS_NO_QUEUE_FLUSH: ON
9108 12:22:22.050522 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9109 12:22:22.053563 ENABLE_DFS_RUNTIME_MRW: OFF
9110 12:22:22.057063 DDR_RESERVE_NEW_MODE: ON
9111 12:22:22.057286 MR_CBT_SWITCH_FREQ: ON
9112 12:22:22.060470 =========================
9113 12:22:22.078972 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9114 12:22:22.082540 dram_init: ddr_geometry: 2
9115 12:22:22.100351 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9116 12:22:22.103996 dram_init: dram init end (result: 0)
9117 12:22:22.110663 DRAM-K: Full calibration passed in 24386 msecs
9118 12:22:22.113644 MRC: failed to locate region type 0.
9119 12:22:22.113776 DRAM rank0 size:0x100000000,
9120 12:22:22.117480 DRAM rank1 size=0x100000000
9121 12:22:22.126964 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9122 12:22:22.133562 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9123 12:22:22.140310 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9124 12:22:22.147013 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9125 12:22:22.150048 DRAM rank0 size:0x100000000,
9126 12:22:22.153689 DRAM rank1 size=0x100000000
9127 12:22:22.153793 CBMEM:
9128 12:22:22.156704 IMD: root @ 0xfffff000 254 entries.
9129 12:22:22.160337 IMD: root @ 0xffffec00 62 entries.
9130 12:22:22.163405 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9131 12:22:22.167198 WARNING: RO_VPD is uninitialized or empty.
9132 12:22:22.173263 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9133 12:22:22.180370 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9134 12:22:22.193410 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9135 12:22:22.204845 BS: romstage times (exec / console): total (unknown) / 23928 ms
9136 12:22:22.204978
9137 12:22:22.205079
9138 12:22:22.214730 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9139 12:22:22.218116 ARM64: Exception handlers installed.
9140 12:22:22.221336 ARM64: Testing exception
9141 12:22:22.225018 ARM64: Done test exception
9142 12:22:22.225126 Enumerating buses...
9143 12:22:22.227962 Show all devs... Before device enumeration.
9144 12:22:22.231625 Root Device: enabled 1
9145 12:22:22.234686 CPU_CLUSTER: 0: enabled 1
9146 12:22:22.234806 CPU: 00: enabled 1
9147 12:22:22.237723 Compare with tree...
9148 12:22:22.237833 Root Device: enabled 1
9149 12:22:22.241261 CPU_CLUSTER: 0: enabled 1
9150 12:22:22.244926 CPU: 00: enabled 1
9151 12:22:22.245010 Root Device scanning...
9152 12:22:22.247910 scan_static_bus for Root Device
9153 12:22:22.251649 CPU_CLUSTER: 0 enabled
9154 12:22:22.254499 scan_static_bus for Root Device done
9155 12:22:22.258217 scan_bus: bus Root Device finished in 8 msecs
9156 12:22:22.258332 done
9157 12:22:22.264391 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9158 12:22:22.268554 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9159 12:22:22.274701 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9160 12:22:22.277881 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9161 12:22:22.281200 Allocating resources...
9162 12:22:22.281284 Reading resources...
9163 12:22:22.288095 Root Device read_resources bus 0 link: 0
9164 12:22:22.288181 DRAM rank0 size:0x100000000,
9165 12:22:22.291120 DRAM rank1 size=0x100000000
9166 12:22:22.294535 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9167 12:22:22.297855 CPU: 00 missing read_resources
9168 12:22:22.301311 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9169 12:22:22.308220 Root Device read_resources bus 0 link: 0 done
9170 12:22:22.308320 Done reading resources.
9171 12:22:22.314659 Show resources in subtree (Root Device)...After reading.
9172 12:22:22.318077 Root Device child on link 0 CPU_CLUSTER: 0
9173 12:22:22.321094 CPU_CLUSTER: 0 child on link 0 CPU: 00
9174 12:22:22.331376 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9175 12:22:22.331468 CPU: 00
9176 12:22:22.334479 Root Device assign_resources, bus 0 link: 0
9177 12:22:22.337925 CPU_CLUSTER: 0 missing set_resources
9178 12:22:22.340956 Root Device assign_resources, bus 0 link: 0 done
9179 12:22:22.344616 Done setting resources.
9180 12:22:22.350971 Show resources in subtree (Root Device)...After assigning values.
9181 12:22:22.354454 Root Device child on link 0 CPU_CLUSTER: 0
9182 12:22:22.357522 CPU_CLUSTER: 0 child on link 0 CPU: 00
9183 12:22:22.367877 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9184 12:22:22.367974 CPU: 00
9185 12:22:22.371365 Done allocating resources.
9186 12:22:22.374406 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9187 12:22:22.377894 Enabling resources...
9188 12:22:22.377979 done.
9189 12:22:22.384201 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9190 12:22:22.384288 Initializing devices...
9191 12:22:22.387531 Root Device init
9192 12:22:22.387642 init hardware done!
9193 12:22:22.390535 0x00000018: ctrlr->caps
9194 12:22:22.394196 52.000 MHz: ctrlr->f_max
9195 12:22:22.394284 0.400 MHz: ctrlr->f_min
9196 12:22:22.397357 0x40ff8080: ctrlr->voltages
9197 12:22:22.397448 sclk: 390625
9198 12:22:22.400408 Bus Width = 1
9199 12:22:22.400493 sclk: 390625
9200 12:22:22.403605 Bus Width = 1
9201 12:22:22.403689 Early init status = 3
9202 12:22:22.410261 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9203 12:22:22.413509 in-header: 03 fb 00 00 01 00 00 00
9204 12:22:22.417213 in-data: 01
9205 12:22:22.420402 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9206 12:22:22.424581 in-header: 03 fb 00 00 01 00 00 00
9207 12:22:22.428065 in-data: 01
9208 12:22:22.431412 [SSUSB] Setting up USB HOST controller...
9209 12:22:22.434712 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9210 12:22:22.437755 [SSUSB] phy power-on done.
9211 12:22:22.440775 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9212 12:22:22.447651 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9213 12:22:22.451167 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9214 12:22:22.457472 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9215 12:22:22.464155 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9216 12:22:22.470971 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9217 12:22:22.477652 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9218 12:22:22.484057 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9219 12:22:22.487658 SPM: binary array size = 0x9dc
9220 12:22:22.490960 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9221 12:22:22.497285 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9222 12:22:22.503820 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9223 12:22:22.510777 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9224 12:22:22.513805 configure_display: Starting display init
9225 12:22:22.547876 anx7625_power_on_init: Init interface.
9226 12:22:22.551183 anx7625_disable_pd_protocol: Disabled PD feature.
9227 12:22:22.554466 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9228 12:22:22.582559 anx7625_start_dp_work: Secure OCM version=00
9229 12:22:22.585542 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9230 12:22:22.600390 sp_tx_get_edid_block: EDID Block = 1
9231 12:22:22.703225 Extracted contents:
9232 12:22:22.706620 header: 00 ff ff ff ff ff ff 00
9233 12:22:22.709602 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9234 12:22:22.713183 version: 01 04
9235 12:22:22.716334 basic params: 95 1f 11 78 0a
9236 12:22:22.719797 chroma info: 76 90 94 55 54 90 27 21 50 54
9237 12:22:22.722788 established: 00 00 00
9238 12:22:22.729387 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9239 12:22:22.732910 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9240 12:22:22.739348 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9241 12:22:22.746202 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9242 12:22:22.752819 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9243 12:22:22.755944 extensions: 00
9244 12:22:22.756032 checksum: fb
9245 12:22:22.756101
9246 12:22:22.759506 Manufacturer: IVO Model 57d Serial Number 0
9247 12:22:22.762484 Made week 0 of 2020
9248 12:22:22.762588 EDID version: 1.4
9249 12:22:22.765838 Digital display
9250 12:22:22.769247 6 bits per primary color channel
9251 12:22:22.769335 DisplayPort interface
9252 12:22:22.772554 Maximum image size: 31 cm x 17 cm
9253 12:22:22.775963 Gamma: 220%
9254 12:22:22.776045 Check DPMS levels
9255 12:22:22.779171 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9256 12:22:22.785990 First detailed timing is preferred timing
9257 12:22:22.786074 Established timings supported:
9258 12:22:22.789125 Standard timings supported:
9259 12:22:22.792610 Detailed timings
9260 12:22:22.796198 Hex of detail: 383680a07038204018303c0035ae10000019
9261 12:22:22.799190 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9262 12:22:22.805871 0780 0798 07c8 0820 hborder 0
9263 12:22:22.809288 0438 043b 0447 0458 vborder 0
9264 12:22:22.812869 -hsync -vsync
9265 12:22:22.812954 Did detailed timing
9266 12:22:22.819191 Hex of detail: 000000000000000000000000000000000000
9267 12:22:22.819275 Manufacturer-specified data, tag 0
9268 12:22:22.825916 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9269 12:22:22.826004 ASCII string: InfoVision
9270 12:22:22.832450 Hex of detail: 000000fe00523134304e574635205248200a
9271 12:22:22.835586 ASCII string: R140NWF5 RH
9272 12:22:22.835712 Checksum
9273 12:22:22.835821 Checksum: 0xfb (valid)
9274 12:22:22.842387 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9275 12:22:22.845741 DSI data_rate: 832800000 bps
9276 12:22:22.849103 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9277 12:22:22.856089 anx7625_parse_edid: pixelclock(138800).
9278 12:22:22.859226 hactive(1920), hsync(48), hfp(24), hbp(88)
9279 12:22:22.862270 vactive(1080), vsync(12), vfp(3), vbp(17)
9280 12:22:22.865815 anx7625_dsi_config: config dsi.
9281 12:22:22.872474 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9282 12:22:22.885344 anx7625_dsi_config: success to config DSI
9283 12:22:22.888754 anx7625_dp_start: MIPI phy setup OK.
9284 12:22:22.892163 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9285 12:22:22.894991 mtk_ddp_mode_set invalid vrefresh 60
9286 12:22:22.898584 main_disp_path_setup
9287 12:22:22.898668 ovl_layer_smi_id_en
9288 12:22:22.901716 ovl_layer_smi_id_en
9289 12:22:22.901810 ccorr_config
9290 12:22:22.901877 aal_config
9291 12:22:22.905328 gamma_config
9292 12:22:22.905444 postmask_config
9293 12:22:22.908304 dither_config
9294 12:22:22.911886 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9295 12:22:22.918464 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9296 12:22:22.922018 Root Device init finished in 531 msecs
9297 12:22:22.925139 CPU_CLUSTER: 0 init
9298 12:22:22.932220 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9299 12:22:22.934946 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9300 12:22:22.938531 APU_MBOX 0x190000b0 = 0x10001
9301 12:22:22.941781 APU_MBOX 0x190001b0 = 0x10001
9302 12:22:22.944880 APU_MBOX 0x190005b0 = 0x10001
9303 12:22:22.948272 APU_MBOX 0x190006b0 = 0x10001
9304 12:22:22.951464 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9305 12:22:22.964024 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9306 12:22:22.976562 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9307 12:22:22.983300 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9308 12:22:22.994705 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9309 12:22:23.004393 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9310 12:22:23.007311 CPU_CLUSTER: 0 init finished in 81 msecs
9311 12:22:23.010459 Devices initialized
9312 12:22:23.013921 Show all devs... After init.
9313 12:22:23.014035 Root Device: enabled 1
9314 12:22:23.017516 CPU_CLUSTER: 0: enabled 1
9315 12:22:23.020590 CPU: 00: enabled 1
9316 12:22:23.024267 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9317 12:22:23.027455 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9318 12:22:23.030992 ELOG: NV offset 0x57f000 size 0x1000
9319 12:22:23.037531 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9320 12:22:23.043888 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9321 12:22:23.047346 ELOG: Event(17) added with size 13 at 2023-08-16 12:21:17 UTC
9322 12:22:23.050786 out: cmd=0x121: 03 db 21 01 00 00 00 00
9323 12:22:23.054384 in-header: 03 3a 00 00 2c 00 00 00
9324 12:22:23.067495 in-data: 25 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9325 12:22:23.074419 ELOG: Event(A1) added with size 10 at 2023-08-16 12:21:17 UTC
9326 12:22:23.080680 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9327 12:22:23.087372 ELOG: Event(A0) added with size 9 at 2023-08-16 12:21:17 UTC
9328 12:22:23.090789 elog_add_boot_reason: Logged dev mode boot
9329 12:22:23.094276 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9330 12:22:23.097848 Finalize devices...
9331 12:22:23.097935 Devices finalized
9332 12:22:23.104091 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9333 12:22:23.107903 Writing coreboot table at 0xffe64000
9334 12:22:23.110803 0. 000000000010a000-0000000000113fff: RAMSTAGE
9335 12:22:23.114270 1. 0000000040000000-00000000400fffff: RAM
9336 12:22:23.117672 2. 0000000040100000-000000004032afff: RAMSTAGE
9337 12:22:23.124038 3. 000000004032b000-00000000545fffff: RAM
9338 12:22:23.127581 4. 0000000054600000-000000005465ffff: BL31
9339 12:22:23.130502 5. 0000000054660000-00000000ffe63fff: RAM
9340 12:22:23.137674 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9341 12:22:23.140723 7. 0000000100000000-000000023fffffff: RAM
9342 12:22:23.140816 Passing 5 GPIOs to payload:
9343 12:22:23.147421 NAME | PORT | POLARITY | VALUE
9344 12:22:23.150407 EC in RW | 0x000000aa | low | undefined
9345 12:22:23.157135 EC interrupt | 0x00000005 | low | undefined
9346 12:22:23.160884 TPM interrupt | 0x000000ab | high | undefined
9347 12:22:23.164096 SD card detect | 0x00000011 | high | undefined
9348 12:22:23.170639 speaker enable | 0x00000093 | high | undefined
9349 12:22:23.173800 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9350 12:22:23.177437 in-header: 03 f9 00 00 02 00 00 00
9351 12:22:23.177522 in-data: 02 00
9352 12:22:23.180604 ADC[4]: Raw value=904726 ID=7
9353 12:22:23.183887 ADC[3]: Raw value=213441 ID=1
9354 12:22:23.187429 RAM Code: 0x71
9355 12:22:23.187514 ADC[6]: Raw value=75332 ID=0
9356 12:22:23.190394 ADC[5]: Raw value=212703 ID=1
9357 12:22:23.190477 SKU Code: 0x1
9358 12:22:23.197274 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b78f
9359 12:22:23.200266 coreboot table: 964 bytes.
9360 12:22:23.203805 IMD ROOT 0. 0xfffff000 0x00001000
9361 12:22:23.207274 IMD SMALL 1. 0xffffe000 0x00001000
9362 12:22:23.210370 RO MCACHE 2. 0xffffc000 0x00001104
9363 12:22:23.213866 CONSOLE 3. 0xfff7c000 0x00080000
9364 12:22:23.217026 FMAP 4. 0xfff7b000 0x00000452
9365 12:22:23.220363 TIME STAMP 5. 0xfff7a000 0x00000910
9366 12:22:23.224110 VBOOT WORK 6. 0xfff66000 0x00014000
9367 12:22:23.226684 RAMOOPS 7. 0xffe66000 0x00100000
9368 12:22:23.230232 COREBOOT 8. 0xffe64000 0x00002000
9369 12:22:23.230316 IMD small region:
9370 12:22:23.233809 IMD ROOT 0. 0xffffec00 0x00000400
9371 12:22:23.237120 VPD 1. 0xffffeba0 0x0000004c
9372 12:22:23.240540 MMC STATUS 2. 0xffffeb80 0x00000004
9373 12:22:23.247032 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9374 12:22:23.250134 Probing TPM: done!
9375 12:22:23.254027 Connected to device vid:did:rid of 1ae0:0028:00
9376 12:22:23.263451 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9377 12:22:23.267028 Initialized TPM device CR50 revision 0
9378 12:22:23.270780 Checking cr50 for pending updates
9379 12:22:23.274176 Reading cr50 TPM mode
9380 12:22:23.282794 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9381 12:22:23.289451 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9382 12:22:23.329657 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9383 12:22:23.333011 Checking segment from ROM address 0x40100000
9384 12:22:23.336063 Checking segment from ROM address 0x4010001c
9385 12:22:23.343074 Loading segment from ROM address 0x40100000
9386 12:22:23.343163 code (compression=0)
9387 12:22:23.352637 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9388 12:22:23.359562 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9389 12:22:23.359706 it's not compressed!
9390 12:22:23.366166 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9391 12:22:23.369545 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9392 12:22:23.390298 Loading segment from ROM address 0x4010001c
9393 12:22:23.390394 Entry Point 0x80000000
9394 12:22:23.393253 Loaded segments
9395 12:22:23.396798 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9396 12:22:23.403231 Jumping to boot code at 0x80000000(0xffe64000)
9397 12:22:23.410147 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9398 12:22:23.416470 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9399 12:22:23.424310 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9400 12:22:23.427852 Checking segment from ROM address 0x40100000
9401 12:22:23.431362 Checking segment from ROM address 0x4010001c
9402 12:22:23.437656 Loading segment from ROM address 0x40100000
9403 12:22:23.437744 code (compression=1)
9404 12:22:23.444575 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9405 12:22:23.454415 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9406 12:22:23.454531 using LZMA
9407 12:22:23.462536 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9408 12:22:23.469424 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9409 12:22:23.472957 Loading segment from ROM address 0x4010001c
9410 12:22:23.473043 Entry Point 0x54601000
9411 12:22:23.475837 Loaded segments
9412 12:22:23.479716 NOTICE: MT8192 bl31_setup
9413 12:22:23.486681 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9414 12:22:23.489653 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9415 12:22:23.493295 WARNING: region 0:
9416 12:22:23.496551 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9417 12:22:23.496637 WARNING: region 1:
9418 12:22:23.502995 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9419 12:22:23.503081 WARNING: region 2:
9420 12:22:23.509822 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9421 12:22:23.512929 WARNING: region 3:
9422 12:22:23.516508 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9423 12:22:23.520187 WARNING: region 4:
9424 12:22:23.523312 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9425 12:22:23.526529 WARNING: region 5:
9426 12:22:23.530134 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9427 12:22:23.533245 WARNING: region 6:
9428 12:22:23.536705 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9429 12:22:23.536825 WARNING: region 7:
9430 12:22:23.543027 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9431 12:22:23.550207 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9432 12:22:23.553312 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9433 12:22:23.556979 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9434 12:22:23.559979 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9435 12:22:23.566528 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9436 12:22:23.570114 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9437 12:22:23.576632 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9438 12:22:23.580098 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9439 12:22:23.583546 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9440 12:22:23.590339 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9441 12:22:23.593291 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9442 12:22:23.596942 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9443 12:22:23.603319 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9444 12:22:23.606710 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9445 12:22:23.613812 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9446 12:22:23.616969 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9447 12:22:23.619993 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9448 12:22:23.626650 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9449 12:22:23.630115 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9450 12:22:23.633338 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9451 12:22:23.640309 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9452 12:22:23.643386 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9453 12:22:23.649963 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9454 12:22:23.653670 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9455 12:22:23.656677 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9456 12:22:23.663841 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9457 12:22:23.666777 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9458 12:22:23.673502 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9459 12:22:23.676971 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9460 12:22:23.680651 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9461 12:22:23.687004 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9462 12:22:23.690545 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9463 12:22:23.693535 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9464 12:22:23.700108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9465 12:22:23.703586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9466 12:22:23.706837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9467 12:22:23.710472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9468 12:22:23.717447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9469 12:22:23.720567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9470 12:22:23.723551 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9471 12:22:23.727350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9472 12:22:23.730483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9473 12:22:23.737015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9474 12:22:23.740497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9475 12:22:23.743850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9476 12:22:23.750316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9477 12:22:23.753678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9478 12:22:23.757311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9479 12:22:23.760668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9480 12:22:23.767081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9481 12:22:23.770546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9482 12:22:23.777183 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9483 12:22:23.780644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9484 12:22:23.787273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9485 12:22:23.790983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9486 12:22:23.794378 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9487 12:22:23.800769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9488 12:22:23.803948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9489 12:22:23.810606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9490 12:22:23.813769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9491 12:22:23.820882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9492 12:22:23.823881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9493 12:22:23.827384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9494 12:22:23.833754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9495 12:22:23.837438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9496 12:22:23.843926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9497 12:22:23.847311 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9498 12:22:23.853754 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9499 12:22:23.857406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9500 12:22:23.860441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9501 12:22:23.867307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9502 12:22:23.870375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9503 12:22:23.877552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9504 12:22:23.880837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9505 12:22:23.887154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9506 12:22:23.890451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9507 12:22:23.893957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9508 12:22:23.900696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9509 12:22:23.904157 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9510 12:22:23.910632 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9511 12:22:23.913972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9512 12:22:23.920882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9513 12:22:23.924289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9514 12:22:23.927701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9515 12:22:23.934092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9516 12:22:23.936976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9517 12:22:23.944192 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9518 12:22:23.947163 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9519 12:22:23.953768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9520 12:22:23.957299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9521 12:22:23.960340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9522 12:22:23.967247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9523 12:22:23.970222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9524 12:22:23.977315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9525 12:22:23.980279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9526 12:22:23.987317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9527 12:22:23.990454 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9528 12:22:23.993559 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9529 12:22:23.997120 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9530 12:22:24.003715 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9531 12:22:24.007284 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9532 12:22:24.010368 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9533 12:22:24.016918 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9534 12:22:24.020467 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9535 12:22:24.027303 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9536 12:22:24.030565 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9537 12:22:24.034236 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9538 12:22:24.040585 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9539 12:22:24.044174 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9540 12:22:24.050889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9541 12:22:24.053977 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9542 12:22:24.057500 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9543 12:22:24.064336 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9544 12:22:24.067328 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9545 12:22:24.070775 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9546 12:22:24.077511 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9547 12:22:24.080962 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9548 12:22:24.084351 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9549 12:22:24.090991 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9550 12:22:24.094522 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9551 12:22:24.097614 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9552 12:22:24.101266 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9553 12:22:24.107466 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9554 12:22:24.110796 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9555 12:22:24.114897 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9556 12:22:24.120788 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9557 12:22:24.124380 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9558 12:22:24.127629 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9559 12:22:24.134561 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9560 12:22:24.137996 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9561 12:22:24.140979 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9562 12:22:24.147730 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9563 12:22:24.151101 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9564 12:22:24.157640 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9565 12:22:24.160917 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9566 12:22:24.164007 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9567 12:22:24.171161 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9568 12:22:24.174458 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9569 12:22:24.181150 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9570 12:22:24.184177 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9571 12:22:24.187815 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9572 12:22:24.194301 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9573 12:22:24.197314 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9574 12:22:24.204697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9575 12:22:24.207683 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9576 12:22:24.210663 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9577 12:22:24.217726 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9578 12:22:24.221096 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9579 12:22:24.227736 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9580 12:22:24.230789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9581 12:22:24.234139 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9582 12:22:24.241046 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9583 12:22:24.244502 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9584 12:22:24.247552 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9585 12:22:24.254261 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9586 12:22:24.257879 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9587 12:22:24.264549 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9588 12:22:24.267484 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9589 12:22:24.270882 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9590 12:22:24.277744 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9591 12:22:24.280667 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9592 12:22:24.284345 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9593 12:22:24.290775 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9594 12:22:24.294361 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9595 12:22:24.301049 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9596 12:22:24.303882 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9597 12:22:24.307419 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9598 12:22:24.313968 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9599 12:22:24.317485 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9600 12:22:24.323872 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9601 12:22:24.327122 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9602 12:22:24.330650 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9603 12:22:24.337653 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9604 12:22:24.340393 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9605 12:22:24.347352 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9606 12:22:24.350485 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9607 12:22:24.353982 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9608 12:22:24.360663 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9609 12:22:24.363731 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9610 12:22:24.370844 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9611 12:22:24.373737 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9612 12:22:24.377203 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9613 12:22:24.384128 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9614 12:22:24.387241 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9615 12:22:24.394183 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9616 12:22:24.396996 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9617 12:22:24.400424 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9618 12:22:24.406931 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9619 12:22:24.410401 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9620 12:22:24.417397 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9621 12:22:24.420256 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9622 12:22:24.423685 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9623 12:22:24.430391 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9624 12:22:24.433358 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9625 12:22:24.440188 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9626 12:22:24.443550 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9627 12:22:24.447253 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9628 12:22:24.453581 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9629 12:22:24.456809 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9630 12:22:24.463281 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9631 12:22:24.466975 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9632 12:22:24.473366 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9633 12:22:24.476938 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9634 12:22:24.480013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9635 12:22:24.486744 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9636 12:22:24.490281 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9637 12:22:24.496610 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9638 12:22:24.500146 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9639 12:22:24.503647 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9640 12:22:24.509929 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9641 12:22:24.513417 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9642 12:22:24.520128 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9643 12:22:24.523009 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9644 12:22:24.529910 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9645 12:22:24.532962 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9646 12:22:24.536531 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9647 12:22:24.542989 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9648 12:22:24.546521 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9649 12:22:24.552943 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9650 12:22:24.556435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9651 12:22:24.560034 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9652 12:22:24.566444 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9653 12:22:24.570105 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9654 12:22:24.576253 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9655 12:22:24.579713 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9656 12:22:24.586467 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9657 12:22:24.590097 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9658 12:22:24.592895 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9659 12:22:24.599332 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9660 12:22:24.602641 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9661 12:22:24.606117 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9662 12:22:24.609196 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9663 12:22:24.616279 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9664 12:22:24.619909 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9665 12:22:24.622857 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9666 12:22:24.629207 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9667 12:22:24.632629 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9668 12:22:24.635815 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9669 12:22:24.642836 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9670 12:22:24.645848 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9671 12:22:24.652443 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9672 12:22:24.655857 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9673 12:22:24.659313 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9674 12:22:24.665744 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9675 12:22:24.669155 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9676 12:22:24.672640 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9677 12:22:24.679253 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9678 12:22:24.682777 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9679 12:22:24.685586 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9680 12:22:24.692509 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9681 12:22:24.695447 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9682 12:22:24.702524 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9683 12:22:24.705864 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9684 12:22:24.708663 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9685 12:22:24.715461 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9686 12:22:24.718856 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9687 12:22:24.722371 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9688 12:22:24.728972 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9689 12:22:24.731915 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9690 12:22:24.735494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9691 12:22:24.741862 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9692 12:22:24.745527 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9693 12:22:24.751976 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9694 12:22:24.755480 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9695 12:22:24.758691 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9696 12:22:24.765260 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9697 12:22:24.768573 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9698 12:22:24.772094 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9699 12:22:24.778630 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9700 12:22:24.782061 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9701 12:22:24.784891 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9702 12:22:24.788209 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9703 12:22:24.795095 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9704 12:22:24.798325 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9705 12:22:24.801739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9706 12:22:24.804806 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9707 12:22:24.811458 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9708 12:22:24.814917 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9709 12:22:24.818449 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9710 12:22:24.821215 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9711 12:22:24.828449 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9712 12:22:24.831390 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9713 12:22:24.835074 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9714 12:22:24.841192 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9715 12:22:24.844690 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9716 12:22:24.851152 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9717 12:22:24.854524 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9718 12:22:24.861728 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9719 12:22:24.864610 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9720 12:22:24.867967 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9721 12:22:24.874410 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9722 12:22:24.877840 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9723 12:22:24.884414 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9724 12:22:24.887971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9725 12:22:24.891576 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9726 12:22:24.898121 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9727 12:22:24.901498 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9728 12:22:24.904466 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9729 12:22:24.911193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9730 12:22:24.914481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9731 12:22:24.921455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9732 12:22:24.924802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9733 12:22:24.931509 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9734 12:22:24.934497 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9735 12:22:24.937665 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9736 12:22:24.944810 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9737 12:22:24.947989 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9738 12:22:24.954764 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9739 12:22:24.957640 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9740 12:22:24.961255 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9741 12:22:24.967922 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9742 12:22:24.971403 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9743 12:22:24.977875 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9744 12:22:24.981088 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9745 12:22:24.984515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9746 12:22:24.991105 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9747 12:22:24.994452 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9748 12:22:25.001278 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9749 12:22:25.004219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9750 12:22:25.007738 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9751 12:22:25.014233 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9752 12:22:25.017903 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9753 12:22:25.024640 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9754 12:22:25.027583 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9755 12:22:25.031280 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9756 12:22:25.037880 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9757 12:22:25.041302 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9758 12:22:25.048085 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9759 12:22:25.051246 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9760 12:22:25.054100 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9761 12:22:25.061103 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9762 12:22:25.064425 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9763 12:22:25.071190 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9764 12:22:25.074135 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9765 12:22:25.080932 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9766 12:22:25.084064 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9767 12:22:25.088037 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9768 12:22:25.094485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9769 12:22:25.097403 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9770 12:22:25.101078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9771 12:22:25.107501 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9772 12:22:25.111081 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9773 12:22:25.117591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9774 12:22:25.121339 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9775 12:22:25.127656 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9776 12:22:25.130908 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9777 12:22:25.134520 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9778 12:22:25.141136 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9779 12:22:25.144278 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9780 12:22:25.150680 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9781 12:22:25.154275 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9782 12:22:25.157352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9783 12:22:25.163793 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9784 12:22:25.167451 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9785 12:22:25.174351 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9786 12:22:25.177348 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9787 12:22:25.183905 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9788 12:22:25.187126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9789 12:22:25.190755 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9790 12:22:25.197458 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9791 12:22:25.200620 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9792 12:22:25.207016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9793 12:22:25.210450 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9794 12:22:25.217226 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9795 12:22:25.220418 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9796 12:22:25.223615 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9797 12:22:25.230612 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9798 12:22:25.233906 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9799 12:22:25.240209 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9800 12:22:25.243572 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9801 12:22:25.250287 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9802 12:22:25.253708 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9803 12:22:25.257076 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9804 12:22:25.263432 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9805 12:22:25.266905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9806 12:22:25.273736 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9807 12:22:25.277228 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9808 12:22:25.283388 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9809 12:22:25.287039 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9810 12:22:25.290073 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9811 12:22:25.296857 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9812 12:22:25.300000 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9813 12:22:25.307067 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9814 12:22:25.310155 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9815 12:22:25.316907 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9816 12:22:25.319763 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9817 12:22:25.326983 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9818 12:22:25.329863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9819 12:22:25.333548 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9820 12:22:25.339768 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9821 12:22:25.342967 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9822 12:22:25.349493 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9823 12:22:25.353128 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9824 12:22:25.359527 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9825 12:22:25.363338 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9826 12:22:25.366460 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9827 12:22:25.373049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9828 12:22:25.376530 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9829 12:22:25.382959 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9830 12:22:25.386309 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9831 12:22:25.393198 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9832 12:22:25.396143 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9833 12:22:25.399659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9834 12:22:25.406237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9835 12:22:25.409961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9836 12:22:25.416017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9837 12:22:25.419523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9838 12:22:25.426172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9839 12:22:25.429618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9840 12:22:25.435953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9841 12:22:25.439087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9842 12:22:25.446126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9843 12:22:25.449691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9844 12:22:25.456370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9845 12:22:25.459226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9846 12:22:25.466352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9847 12:22:25.469042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9848 12:22:25.476205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9849 12:22:25.478944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9850 12:22:25.482262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9851 12:22:25.489334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9852 12:22:25.492200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9853 12:22:25.498859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9854 12:22:25.502307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9855 12:22:25.509408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9856 12:22:25.515389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9857 12:22:25.519272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9858 12:22:25.525779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9859 12:22:25.529127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9860 12:22:25.532675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9861 12:22:25.539095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9862 12:22:25.545616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9863 12:22:25.549152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9864 12:22:25.555743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9865 12:22:25.558744 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9866 12:22:25.558828 INFO: [APUAPC] vio 0
9867 12:22:25.565996 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9868 12:22:25.569370 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9869 12:22:25.573099 INFO: [APUAPC] D0_APC_0: 0x400510
9870 12:22:25.575954 INFO: [APUAPC] D0_APC_1: 0x0
9871 12:22:25.579449 INFO: [APUAPC] D0_APC_2: 0x1540
9872 12:22:25.583087 INFO: [APUAPC] D0_APC_3: 0x0
9873 12:22:25.586188 INFO: [APUAPC] D1_APC_0: 0xffffffff
9874 12:22:25.589410 INFO: [APUAPC] D1_APC_1: 0xffffffff
9875 12:22:25.592504 INFO: [APUAPC] D1_APC_2: 0x3fffff
9876 12:22:25.596106 INFO: [APUAPC] D1_APC_3: 0x0
9877 12:22:25.599161 INFO: [APUAPC] D2_APC_0: 0xffffffff
9878 12:22:25.602751 INFO: [APUAPC] D2_APC_1: 0xffffffff
9879 12:22:25.605750 INFO: [APUAPC] D2_APC_2: 0x3fffff
9880 12:22:25.609191 INFO: [APUAPC] D2_APC_3: 0x0
9881 12:22:25.612508 INFO: [APUAPC] D3_APC_0: 0xffffffff
9882 12:22:25.615819 INFO: [APUAPC] D3_APC_1: 0xffffffff
9883 12:22:25.619340 INFO: [APUAPC] D3_APC_2: 0x3fffff
9884 12:22:25.622682 INFO: [APUAPC] D3_APC_3: 0x0
9885 12:22:25.625731 INFO: [APUAPC] D4_APC_0: 0xffffffff
9886 12:22:25.629350 INFO: [APUAPC] D4_APC_1: 0xffffffff
9887 12:22:25.632901 INFO: [APUAPC] D4_APC_2: 0x3fffff
9888 12:22:25.632985 INFO: [APUAPC] D4_APC_3: 0x0
9889 12:22:25.636284 INFO: [APUAPC] D5_APC_0: 0xffffffff
9890 12:22:25.642485 INFO: [APUAPC] D5_APC_1: 0xffffffff
9891 12:22:25.642574 INFO: [APUAPC] D5_APC_2: 0x3fffff
9892 12:22:25.646026 INFO: [APUAPC] D5_APC_3: 0x0
9893 12:22:25.648959 INFO: [APUAPC] D6_APC_0: 0xffffffff
9894 12:22:25.652620 INFO: [APUAPC] D6_APC_1: 0xffffffff
9895 12:22:25.655755 INFO: [APUAPC] D6_APC_2: 0x3fffff
9896 12:22:25.659122 INFO: [APUAPC] D6_APC_3: 0x0
9897 12:22:25.662627 INFO: [APUAPC] D7_APC_0: 0xffffffff
9898 12:22:25.665982 INFO: [APUAPC] D7_APC_1: 0xffffffff
9899 12:22:25.669231 INFO: [APUAPC] D7_APC_2: 0x3fffff
9900 12:22:25.672578 INFO: [APUAPC] D7_APC_3: 0x0
9901 12:22:25.675963 INFO: [APUAPC] D8_APC_0: 0xffffffff
9902 12:22:25.679024 INFO: [APUAPC] D8_APC_1: 0xffffffff
9903 12:22:25.682555 INFO: [APUAPC] D8_APC_2: 0x3fffff
9904 12:22:25.686238 INFO: [APUAPC] D8_APC_3: 0x0
9905 12:22:25.689030 INFO: [APUAPC] D9_APC_0: 0xffffffff
9906 12:22:25.692427 INFO: [APUAPC] D9_APC_1: 0xffffffff
9907 12:22:25.695987 INFO: [APUAPC] D9_APC_2: 0x3fffff
9908 12:22:25.699636 INFO: [APUAPC] D9_APC_3: 0x0
9909 12:22:25.702415 INFO: [APUAPC] D10_APC_0: 0xffffffff
9910 12:22:25.705820 INFO: [APUAPC] D10_APC_1: 0xffffffff
9911 12:22:25.708828 INFO: [APUAPC] D10_APC_2: 0x3fffff
9912 12:22:25.712376 INFO: [APUAPC] D10_APC_3: 0x0
9913 12:22:25.715346 INFO: [APUAPC] D11_APC_0: 0xffffffff
9914 12:22:25.719078 INFO: [APUAPC] D11_APC_1: 0xffffffff
9915 12:22:25.721920 INFO: [APUAPC] D11_APC_2: 0x3fffff
9916 12:22:25.725520 INFO: [APUAPC] D11_APC_3: 0x0
9917 12:22:25.729040 INFO: [APUAPC] D12_APC_0: 0xffffffff
9918 12:22:25.731977 INFO: [APUAPC] D12_APC_1: 0xffffffff
9919 12:22:25.736176 INFO: [APUAPC] D12_APC_2: 0x3fffff
9920 12:22:25.739260 INFO: [APUAPC] D12_APC_3: 0x0
9921 12:22:25.742220 INFO: [APUAPC] D13_APC_0: 0xffffffff
9922 12:22:25.745678 INFO: [APUAPC] D13_APC_1: 0xffffffff
9923 12:22:25.748743 INFO: [APUAPC] D13_APC_2: 0x3fffff
9924 12:22:25.752307 INFO: [APUAPC] D13_APC_3: 0x0
9925 12:22:25.755368 INFO: [APUAPC] D14_APC_0: 0xffffffff
9926 12:22:25.759183 INFO: [APUAPC] D14_APC_1: 0xffffffff
9927 12:22:25.762164 INFO: [APUAPC] D14_APC_2: 0x3fffff
9928 12:22:25.765162 INFO: [APUAPC] D14_APC_3: 0x0
9929 12:22:25.768723 INFO: [APUAPC] D15_APC_0: 0xffffffff
9930 12:22:25.771988 INFO: [APUAPC] D15_APC_1: 0xffffffff
9931 12:22:25.775253 INFO: [APUAPC] D15_APC_2: 0x3fffff
9932 12:22:25.779035 INFO: [APUAPC] D15_APC_3: 0x0
9933 12:22:25.782395 INFO: [APUAPC] APC_CON: 0x4
9934 12:22:25.785335 INFO: [NOCDAPC] D0_APC_0: 0x0
9935 12:22:25.788946 INFO: [NOCDAPC] D0_APC_1: 0x0
9936 12:22:25.791865 INFO: [NOCDAPC] D1_APC_0: 0x0
9937 12:22:25.791974 INFO: [NOCDAPC] D1_APC_1: 0xfff
9938 12:22:25.795246 INFO: [NOCDAPC] D2_APC_0: 0x0
9939 12:22:25.799145 INFO: [NOCDAPC] D2_APC_1: 0xfff
9940 12:22:25.801901 INFO: [NOCDAPC] D3_APC_0: 0x0
9941 12:22:25.805866 INFO: [NOCDAPC] D3_APC_1: 0xfff
9942 12:22:25.808701 INFO: [NOCDAPC] D4_APC_0: 0x0
9943 12:22:25.811722 INFO: [NOCDAPC] D4_APC_1: 0xfff
9944 12:22:25.815146 INFO: [NOCDAPC] D5_APC_0: 0x0
9945 12:22:25.818817 INFO: [NOCDAPC] D5_APC_1: 0xfff
9946 12:22:25.821756 INFO: [NOCDAPC] D6_APC_0: 0x0
9947 12:22:25.825171 INFO: [NOCDAPC] D6_APC_1: 0xfff
9948 12:22:25.825254 INFO: [NOCDAPC] D7_APC_0: 0x0
9949 12:22:25.828935 INFO: [NOCDAPC] D7_APC_1: 0xfff
9950 12:22:25.832346 INFO: [NOCDAPC] D8_APC_0: 0x0
9951 12:22:25.835163 INFO: [NOCDAPC] D8_APC_1: 0xfff
9952 12:22:25.838715 INFO: [NOCDAPC] D9_APC_0: 0x0
9953 12:22:25.841815 INFO: [NOCDAPC] D9_APC_1: 0xfff
9954 12:22:25.845302 INFO: [NOCDAPC] D10_APC_0: 0x0
9955 12:22:25.848740 INFO: [NOCDAPC] D10_APC_1: 0xfff
9956 12:22:25.851759 INFO: [NOCDAPC] D11_APC_0: 0x0
9957 12:22:25.855263 INFO: [NOCDAPC] D11_APC_1: 0xfff
9958 12:22:25.858658 INFO: [NOCDAPC] D12_APC_0: 0x0
9959 12:22:25.861968 INFO: [NOCDAPC] D12_APC_1: 0xfff
9960 12:22:25.862055 INFO: [NOCDAPC] D13_APC_0: 0x0
9961 12:22:25.865286 INFO: [NOCDAPC] D13_APC_1: 0xfff
9962 12:22:25.868763 INFO: [NOCDAPC] D14_APC_0: 0x0
9963 12:22:25.871690 INFO: [NOCDAPC] D14_APC_1: 0xfff
9964 12:22:25.875217 INFO: [NOCDAPC] D15_APC_0: 0x0
9965 12:22:25.878844 INFO: [NOCDAPC] D15_APC_1: 0xfff
9966 12:22:25.881839 INFO: [NOCDAPC] APC_CON: 0x4
9967 12:22:25.885212 INFO: [APUAPC] set_apusys_apc done
9968 12:22:25.888669 INFO: [DEVAPC] devapc_init done
9969 12:22:25.892279 INFO: GICv3 without legacy support detected.
9970 12:22:25.895074 INFO: ARM GICv3 driver initialized in EL3
9971 12:22:25.902265 INFO: Maximum SPI INTID supported: 639
9972 12:22:25.905289 INFO: BL31: Initializing runtime services
9973 12:22:25.911911 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9974 12:22:25.911994 INFO: SPM: enable CPC mode
9975 12:22:25.918744 INFO: mcdi ready for mcusys-off-idle and system suspend
9976 12:22:25.921707 INFO: BL31: Preparing for EL3 exit to normal world
9977 12:22:25.925113 INFO: Entry point address = 0x80000000
9978 12:22:25.928986 INFO: SPSR = 0x8
9979 12:22:25.934061
9980 12:22:25.934169
9981 12:22:25.934262
9982 12:22:25.937538 Starting depthcharge on Spherion...
9983 12:22:25.937621
9984 12:22:25.937687 Wipe memory regions:
9985 12:22:25.937749
9986 12:22:25.938376 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9987 12:22:25.938478 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9988 12:22:25.938560 Setting prompt string to ['asurada:']
9989 12:22:25.938641 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9990 12:22:25.940583 [0x00000040000000, 0x00000054600000)
9991 12:22:26.063474
9992 12:22:26.063668 [0x00000054660000, 0x00000080000000)
9993 12:22:26.323979
9994 12:22:26.324119 [0x000000821a7280, 0x000000ffe64000)
9995 12:22:27.068932
9996 12:22:27.069072 [0x00000100000000, 0x00000240000000)
9997 12:22:28.959384
9998 12:22:28.962586 Initializing XHCI USB controller at 0x11200000.
9999 12:22:30.001120
10000 12:22:30.004620 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10001 12:22:30.004707
10002 12:22:30.004772
10003 12:22:30.004831
10004 12:22:30.005110 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10006 12:22:30.105456 asurada: tftpboot 192.168.201.1 11299254/tftp-deploy-u8xrdn7k/kernel/image.itb 11299254/tftp-deploy-u8xrdn7k/kernel/cmdline
10007 12:22:30.105602 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10008 12:22:30.105718 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10009 12:22:30.110126 tftpboot 192.168.201.1 11299254/tftp-deploy-u8xrdn7k/kernel/image.ittp-deploy-u8xrdn7k/kernel/cmdline
10010 12:22:30.110211
10011 12:22:30.110277 Waiting for link
10012 12:22:30.271000
10013 12:22:30.271151 R8152: Initializing
10014 12:22:30.271218
10015 12:22:30.274197 Version 9 (ocp_data = 6010)
10016 12:22:30.274279
10017 12:22:30.277419 R8152: Done initializing
10018 12:22:30.277501
10019 12:22:30.277565 Adding net device
10020 12:22:32.149206
10021 12:22:32.149392 done.
10022 12:22:32.149497
10023 12:22:32.149589 MAC: 00:e0:4c:78:7a:aa
10024 12:22:32.149680
10025 12:22:32.152487 Sending DHCP discover... done.
10026 12:22:32.152598
10027 12:22:32.156069 Waiting for reply... done.
10028 12:22:32.156203
10029 12:22:32.159051 Sending DHCP request... done.
10030 12:22:32.159135
10031 12:22:32.170292 Waiting for reply... done.
10032 12:22:32.170375
10033 12:22:32.170441 My ip is 192.168.201.12
10034 12:22:32.170501
10035 12:22:32.173962 The DHCP server ip is 192.168.201.1
10036 12:22:32.174044
10037 12:22:32.180643 TFTP server IP predefined by user: 192.168.201.1
10038 12:22:32.180725
10039 12:22:32.187372 Bootfile predefined by user: 11299254/tftp-deploy-u8xrdn7k/kernel/image.itb
10040 12:22:32.187454
10041 12:22:32.187519 Sending tftp read request... done.
10042 12:22:32.190368
10043 12:22:32.193658 Waiting for the transfer...
10044 12:22:32.193762
10045 12:22:32.466412 00000000 ################################################################
10046 12:22:32.466558
10047 12:22:32.738931 00080000 ################################################################
10048 12:22:32.739077
10049 12:22:32.995838 00100000 ################################################################
10050 12:22:32.995969
10051 12:22:33.256920 00180000 ################################################################
10052 12:22:33.257052
10053 12:22:33.508384 00200000 ################################################################
10054 12:22:33.508548
10055 12:22:33.766601 00280000 ################################################################
10056 12:22:33.766754
10057 12:22:34.021436 00300000 ################################################################
10058 12:22:34.021597
10059 12:22:34.274171 00380000 ################################################################
10060 12:22:34.274308
10061 12:22:34.524959 00400000 ################################################################
10062 12:22:34.525101
10063 12:22:34.796356 00480000 ################################################################
10064 12:22:34.796499
10065 12:22:35.086909 00500000 ################################################################
10066 12:22:35.087049
10067 12:22:35.378778 00580000 ################################################################
10068 12:22:35.378920
10069 12:22:35.648943 00600000 ################################################################
10070 12:22:35.649081
10071 12:22:35.921275 00680000 ################################################################
10072 12:22:35.921431
10073 12:22:36.193327 00700000 ################################################################
10074 12:22:36.193465
10075 12:22:36.456321 00780000 ################################################################
10076 12:22:36.456488
10077 12:22:36.719576 00800000 ################################################################
10078 12:22:36.719745
10079 12:22:36.994595 00880000 ################################################################
10080 12:22:36.994730
10081 12:22:37.257438 00900000 ################################################################
10082 12:22:37.257576
10083 12:22:37.553159 00980000 ################################################################
10084 12:22:37.553298
10085 12:22:37.822832 00a00000 ################################################################
10086 12:22:37.822980
10087 12:22:38.080571 00a80000 ################################################################
10088 12:22:38.080703
10089 12:22:38.337756 00b00000 ################################################################
10090 12:22:38.337895
10091 12:22:38.603956 00b80000 ################################################################
10092 12:22:38.604094
10093 12:22:38.875210 00c00000 ################################################################
10094 12:22:38.875347
10095 12:22:39.147985 00c80000 ################################################################
10096 12:22:39.148128
10097 12:22:39.405341 00d00000 ################################################################
10098 12:22:39.405472
10099 12:22:39.684683 00d80000 ################################################################
10100 12:22:39.684815
10101 12:22:39.936306 00e00000 ################################################################
10102 12:22:39.936449
10103 12:22:40.206391 00e80000 ################################################################
10104 12:22:40.206522
10105 12:22:40.479874 00f00000 ################################################################
10106 12:22:40.480020
10107 12:22:40.764396 00f80000 ################################################################
10108 12:22:40.764535
10109 12:22:41.014899 01000000 ################################################################
10110 12:22:41.015030
10111 12:22:41.264253 01080000 ################################################################
10112 12:22:41.264387
10113 12:22:41.519920 01100000 ################################################################
10114 12:22:41.520050
10115 12:22:41.789007 01180000 ################################################################
10116 12:22:41.789142
10117 12:22:42.043532 01200000 ################################################################
10118 12:22:42.043714
10119 12:22:42.299002 01280000 ################################################################
10120 12:22:42.299134
10121 12:22:42.563485 01300000 ################################################################
10122 12:22:42.563667
10123 12:22:42.818161 01380000 ################################################################
10124 12:22:42.818296
10125 12:22:43.072484 01400000 ################################################################
10126 12:22:43.072618
10127 12:22:43.337209 01480000 ################################################################
10128 12:22:43.337346
10129 12:22:43.618217 01500000 ################################################################
10130 12:22:43.618353
10131 12:22:43.907355 01580000 ################################################################
10132 12:22:43.907507
10133 12:22:44.192167 01600000 ################################################################
10134 12:22:44.192311
10135 12:22:44.465280 01680000 ################################################################
10136 12:22:44.465415
10137 12:22:44.718099 01700000 ################################################################
10138 12:22:44.718232
10139 12:22:44.968137 01780000 ################################################################
10140 12:22:44.968270
10141 12:22:45.241162 01800000 ################################################################
10142 12:22:45.241294
10143 12:22:45.508053 01880000 ################################################################
10144 12:22:45.508189
10145 12:22:45.793903 01900000 ################################################################
10146 12:22:45.794043
10147 12:22:46.044136 01980000 ################################################################
10148 12:22:46.044264
10149 12:22:46.311448 01a00000 ################################################################
10150 12:22:46.311580
10151 12:22:46.575453 01a80000 ################################################################
10152 12:22:46.575638
10153 12:22:46.839869 01b00000 ################################################################
10154 12:22:46.840022
10155 12:22:47.128688 01b80000 ################################################################
10156 12:22:47.128837
10157 12:22:47.421172 01c00000 ################################################################
10158 12:22:47.421324
10159 12:22:47.682225 01c80000 ################################################################
10160 12:22:47.682394
10161 12:22:47.944510 01d00000 ################################################################
10162 12:22:47.944674
10163 12:22:48.202559 01d80000 ################################################################
10164 12:22:48.202694
10165 12:22:48.455209 01e00000 ################################################################
10166 12:22:48.455341
10167 12:22:48.706805 01e80000 ################################################################
10168 12:22:48.706937
10169 12:22:48.963882 01f00000 ################################################################
10170 12:22:48.964014
10171 12:22:49.243309 01f80000 ################################################################
10172 12:22:49.243471
10173 12:22:49.502747 02000000 ################################################################
10174 12:22:49.502919
10175 12:22:49.750778 02080000 ################################################################
10176 12:22:49.750915
10177 12:22:50.000067 02100000 ################################################################
10178 12:22:50.000205
10179 12:22:50.247891 02180000 ################################################################
10180 12:22:50.248027
10181 12:22:50.501717 02200000 ################################################################
10182 12:22:50.501868
10183 12:22:50.759583 02280000 ################################################################
10184 12:22:50.759757
10185 12:22:51.018227 02300000 ################################################################
10186 12:22:51.018441
10187 12:22:51.265393 02380000 ################################################################
10188 12:22:51.265545
10189 12:22:51.514813 02400000 ################################################################
10190 12:22:51.514960
10191 12:22:51.772926 02480000 ################################################################
10192 12:22:51.773100
10193 12:22:52.028429 02500000 ################################################################
10194 12:22:52.028573
10195 12:22:52.275111 02580000 ################################################################
10196 12:22:52.275263
10197 12:22:52.525125 02600000 ################################################################
10198 12:22:52.525272
10199 12:22:52.772551 02680000 ################################################################
10200 12:22:52.772698
10201 12:22:53.018415 02700000 ################################################################
10202 12:22:53.018560
10203 12:22:53.267307 02780000 ################################################################
10204 12:22:53.267484
10205 12:22:53.497971 02800000 ################################################################
10206 12:22:53.498132
10207 12:22:53.736261 02880000 ################################################################
10208 12:22:53.736409
10209 12:22:53.983006 02900000 ################################################################
10210 12:22:53.983168
10211 12:22:54.252365 02980000 ################################################################
10212 12:22:54.252495
10213 12:22:54.504811 02a00000 ################################################################
10214 12:22:54.504980
10215 12:22:54.769465 02a80000 ################################################################
10216 12:22:54.769628
10217 12:22:55.027831 02b00000 ################################################################
10218 12:22:55.027996
10219 12:22:55.288624 02b80000 ################################################################
10220 12:22:55.288792
10221 12:22:55.547807 02c00000 ################################################################
10222 12:22:55.547970
10223 12:22:55.810420 02c80000 ################################################################
10224 12:22:55.810556
10225 12:22:56.065128 02d00000 ################################################################
10226 12:22:56.065263
10227 12:22:56.324579 02d80000 ################################################################
10228 12:22:56.324716
10229 12:22:56.574059 02e00000 ################################################################
10230 12:22:56.574193
10231 12:22:56.824647 02e80000 ################################################################
10232 12:22:56.824783
10233 12:22:57.079511 02f00000 ################################################################
10234 12:22:57.079670
10235 12:22:57.330647 02f80000 ################################################################
10236 12:22:57.330784
10237 12:22:57.582116 03000000 ################################################################
10238 12:22:57.582252
10239 12:22:57.858468 03080000 ################################################################
10240 12:22:57.858602
10241 12:22:58.114568 03100000 ################################################################
10242 12:22:58.114705
10243 12:22:58.399032 03180000 ################################################################
10244 12:22:58.399180
10245 12:22:58.667030 03200000 ################################################################
10246 12:22:58.667174
10247 12:22:58.934160 03280000 ################################################################
10248 12:22:58.934290
10249 12:22:59.195985 03300000 ################################################################
10250 12:22:59.196119
10251 12:22:59.481848 03380000 ################################################################
10252 12:22:59.481992
10253 12:22:59.747064 03400000 ################################################################
10254 12:22:59.747199
10255 12:23:00.012527 03480000 ################################################################
10256 12:23:00.012658
10257 12:23:00.266041 03500000 ################################################################
10258 12:23:00.266167
10259 12:23:00.515844 03580000 ################################################################
10260 12:23:00.515975
10261 12:23:00.774219 03600000 ################################################################
10262 12:23:00.774359
10263 12:23:01.036999 03680000 ################################################################
10264 12:23:01.037136
10265 12:23:01.306571 03700000 ################################################################
10266 12:23:01.306709
10267 12:23:01.560096 03780000 ################################################################
10268 12:23:01.560230
10269 12:23:01.816661 03800000 ################################################################
10270 12:23:01.816800
10271 12:23:02.080405 03880000 ################################################################
10272 12:23:02.080546
10273 12:23:02.347079 03900000 ################################################################
10274 12:23:02.347222
10275 12:23:02.633342 03980000 ################################################################
10276 12:23:02.633479
10277 12:23:02.887827 03a00000 ################################################################
10278 12:23:02.887968
10279 12:23:03.148083 03a80000 ################################################################
10280 12:23:03.148226
10281 12:23:03.435433 03b00000 ################################################################
10282 12:23:03.435575
10283 12:23:03.696038 03b80000 ################################################################
10284 12:23:03.696192
10285 12:23:03.970261 03c00000 ################################################################
10286 12:23:03.970413
10287 12:23:04.204055 03c80000 ################################################################
10288 12:23:04.204213
10289 12:23:04.447065 03d00000 ################################################################
10290 12:23:04.447216
10291 12:23:04.704606 03d80000 ################################################################
10292 12:23:04.704760
10293 12:23:04.987744 03e00000 ################################################################
10294 12:23:04.987896
10295 12:23:05.274507 03e80000 ################################################################
10296 12:23:05.274657
10297 12:23:05.562421 03f00000 ################################################################
10298 12:23:05.562572
10299 12:23:05.858578 03f80000 ################################################################
10300 12:23:05.858713
10301 12:23:06.141830 04000000 ################################################################
10302 12:23:06.141982
10303 12:23:06.420162 04080000 ################################################################
10304 12:23:06.420310
10305 12:23:06.699547 04100000 ################################################################
10306 12:23:06.699739
10307 12:23:06.976490 04180000 ################################################################
10308 12:23:06.976640
10309 12:23:07.245347 04200000 ################################################################
10310 12:23:07.245499
10311 12:23:07.500272 04280000 ################################################################
10312 12:23:07.500408
10313 12:23:07.779024 04300000 ################################################################
10314 12:23:07.779170
10315 12:23:08.063160 04380000 ################################################################
10316 12:23:08.063320
10317 12:23:08.330790 04400000 ################################################################
10318 12:23:08.330940
10319 12:23:08.601200 04480000 ################################################################
10320 12:23:08.601350
10321 12:23:08.892037 04500000 ################################################################
10322 12:23:08.892187
10323 12:23:09.185628 04580000 ################################################################
10324 12:23:09.185760
10325 12:23:09.448304 04600000 ################################################################
10326 12:23:09.448450
10327 12:23:09.703023 04680000 ################################################################
10328 12:23:09.703187
10329 12:23:09.961324 04700000 ################################################################
10330 12:23:09.961454
10331 12:23:10.213205 04780000 ################################################################
10332 12:23:10.213351
10333 12:23:10.475367 04800000 ################################################################
10334 12:23:10.475502
10335 12:23:10.731475 04880000 ################################################################
10336 12:23:10.731682
10337 12:23:10.988682 04900000 ################################################################
10338 12:23:10.988836
10339 12:23:11.245353 04980000 ################################################################
10340 12:23:11.245550
10341 12:23:11.494857 04a00000 ################################################################
10342 12:23:11.495008
10343 12:23:11.751945 04a80000 ################################################################
10344 12:23:11.752093
10345 12:23:12.002389 04b00000 ################################################################
10346 12:23:12.002566
10347 12:23:12.256596 04b80000 ################################################################
10348 12:23:12.256761
10349 12:23:12.530269 04c00000 ################################################################
10350 12:23:12.530414
10351 12:23:12.784089 04c80000 ################################################################
10352 12:23:12.784241
10353 12:23:13.039523 04d00000 ################################################################
10354 12:23:13.039697
10355 12:23:13.296514 04d80000 ################################################################
10356 12:23:13.296651
10357 12:23:13.558946 04e00000 ################################################################
10358 12:23:13.559106
10359 12:23:13.809795 04e80000 ################################################################
10360 12:23:13.809977
10361 12:23:14.070283 04f00000 ################################################################
10362 12:23:14.070425
10363 12:23:14.336774 04f80000 ################################################################
10364 12:23:14.336935
10365 12:23:14.600664 05000000 ################################################################
10366 12:23:14.600822
10367 12:23:14.880646 05080000 ################################################################
10368 12:23:14.880790
10369 12:23:15.130609 05100000 ################################################################
10370 12:23:15.130780
10371 12:23:15.390995 05180000 ################################################################
10372 12:23:15.391158
10373 12:23:15.675857 05200000 ################################################################
10374 12:23:15.675995
10375 12:23:15.934440 05280000 ################################################################
10376 12:23:15.934583
10377 12:23:16.180539 05300000 ################################################################
10378 12:23:16.180707
10379 12:23:16.432355 05380000 ################################################################
10380 12:23:16.432494
10381 12:23:16.698313 05400000 ################################################################
10382 12:23:16.698448
10383 12:23:16.964607 05480000 ################################################################
10384 12:23:16.964753
10385 12:23:17.230024 05500000 ################################################################
10386 12:23:17.230168
10387 12:23:17.501238 05580000 ################################################################
10388 12:23:17.501375
10389 12:23:17.753214 05600000 ################################################################
10390 12:23:17.753382
10391 12:23:18.030981 05680000 ################################################################
10392 12:23:18.031131
10393 12:23:18.326153 05700000 ################################################################
10394 12:23:18.326334
10395 12:23:18.590017 05780000 ################################################################
10396 12:23:18.590162
10397 12:23:18.846150 05800000 ################################################################
10398 12:23:18.846328
10399 12:23:19.105620 05880000 ################################################################
10400 12:23:19.105769
10401 12:23:19.361697 05900000 ################################################################
10402 12:23:19.361840
10403 12:23:19.624824 05980000 ################################################################
10404 12:23:19.624958
10405 12:23:19.874107 05a00000 ################################################################
10406 12:23:19.874245
10407 12:23:20.132564 05a80000 ################################################################
10408 12:23:20.132703
10409 12:23:20.394237 05b00000 ################################################################
10410 12:23:20.394377
10411 12:23:20.642980 05b80000 ################################################################
10412 12:23:20.643115
10413 12:23:20.893888 05c00000 ################################################################
10414 12:23:20.894027
10415 12:23:21.144204 05c80000 ################################################################
10416 12:23:21.144351
10417 12:23:21.409044 05d00000 ################################################################
10418 12:23:21.409191
10419 12:23:21.662127 05d80000 ################################################################
10420 12:23:21.662275
10421 12:23:21.913437 05e00000 ################################################################
10422 12:23:21.913578
10423 12:23:22.180803 05e80000 ################################################################
10424 12:23:22.180940
10425 12:23:22.442710 05f00000 ################################################################
10426 12:23:22.442852
10427 12:23:22.723184 05f80000 ################################################################
10428 12:23:22.723321
10429 12:23:23.002062 06000000 ################################################################
10430 12:23:23.002194
10431 12:23:23.285572 06080000 ################################################################
10432 12:23:23.285705
10433 12:23:23.560573 06100000 ################################################################
10434 12:23:23.560726
10435 12:23:23.822645 06180000 ################################################################
10436 12:23:23.822795
10437 12:23:24.095494 06200000 ################################################################
10438 12:23:24.095761
10439 12:23:24.345769 06280000 ################################################################
10440 12:23:24.346034
10441 12:23:24.599188 06300000 ################################################################
10442 12:23:24.599339
10443 12:23:24.865216 06380000 ################################################################
10444 12:23:24.865361
10445 12:23:25.133553 06400000 ################################################################
10446 12:23:25.133704
10447 12:23:25.401630 06480000 ################################################################
10448 12:23:25.401776
10449 12:23:25.664199 06500000 ################################################################
10450 12:23:25.664373
10451 12:23:25.934314 06580000 ################################################################
10452 12:23:25.934465
10453 12:23:26.200470 06600000 ################################################################
10454 12:23:26.200616
10455 12:23:26.476203 06680000 ################################################################
10456 12:23:26.476353
10457 12:23:26.768365 06700000 ################################################################
10458 12:23:26.768516
10459 12:23:27.031989 06780000 ################################################################
10460 12:23:27.032137
10461 12:23:27.218115 06800000 ########################################### done.
10462 12:23:27.218289
10463 12:23:27.221538 The bootfile was 109397254 bytes long.
10464 12:23:27.221621
10465 12:23:27.225024 Sending tftp read request... done.
10466 12:23:27.225106
10467 12:23:27.228558 Waiting for the transfer...
10468 12:23:27.228641
10469 12:23:27.228707 00000000 # done.
10470 12:23:27.228769
10471 12:23:27.238853 Command line loaded dynamically from TFTP file: 11299254/tftp-deploy-u8xrdn7k/kernel/cmdline
10472 12:23:27.238937
10473 12:23:27.251581 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10474 12:23:27.251707
10475 12:23:27.251773 Loading FIT.
10476 12:23:27.251834
10477 12:23:27.254972 Image ramdisk-1 has 98307568 bytes.
10478 12:23:27.255054
10479 12:23:27.258057 Image fdt-1 has 47278 bytes.
10480 12:23:27.258138
10481 12:23:27.261266 Image kernel-1 has 11040376 bytes.
10482 12:23:27.261347
10483 12:23:27.268457 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10484 12:23:27.268539
10485 12:23:27.288209 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10486 12:23:27.288299
10487 12:23:27.291381 Choosing best match conf-1 for compat google,spherion-rev2.
10488 12:23:27.296023
10489 12:23:27.300875 Connected to device vid:did:rid of 1ae0:0028:00
10490 12:23:27.308887
10491 12:23:27.312423 tpm_get_response: command 0x17b, return code 0x0
10492 12:23:27.312505
10493 12:23:27.315533 ec_init: CrosEC protocol v3 supported (256, 248)
10494 12:23:27.319573
10495 12:23:27.322904 tpm_cleanup: add release locality here.
10496 12:23:27.322986
10497 12:23:27.323051 Shutting down all USB controllers.
10498 12:23:27.326139
10499 12:23:27.326293 Removing current net device
10500 12:23:27.326381
10501 12:23:27.333003 Exiting depthcharge with code 4 at timestamp: 90582068
10502 12:23:27.333088
10503 12:23:27.336328 LZMA decompressing kernel-1 to 0x821a6718
10504 12:23:27.336413
10505 12:23:27.339159 LZMA decompressing kernel-1 to 0x40000000
10506 12:23:28.726787
10507 12:23:28.726949 jumping to kernel
10508 12:23:28.727450 end: 2.2.4 bootloader-commands (duration 00:01:03) [common]
10509 12:23:28.727565 start: 2.2.5 auto-login-action (timeout 00:03:23) [common]
10510 12:23:28.727705 Setting prompt string to ['Linux version [0-9]']
10511 12:23:28.727791 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10512 12:23:28.727874 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10513 12:23:28.808528
10514 12:23:28.812057 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10515 12:23:28.815766 start: 2.2.5.1 login-action (timeout 00:03:22) [common]
10516 12:23:28.815874 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10517 12:23:28.815958 Setting prompt string to []
10518 12:23:28.816064 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10519 12:23:28.816150 Using line separator: #'\n'#
10520 12:23:28.816223 No login prompt set.
10521 12:23:28.816307 Parsing kernel messages
10522 12:23:28.816416 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10523 12:23:28.816602 [login-action] Waiting for messages, (timeout 00:03:22)
10524 12:23:28.834741 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j14831-arm64-gcc-10-defconfig-arm64-chromebook-g8jrt) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 16 12:04:53 UTC 2023
10525 12:23:28.838033 [ 0.000000] random: crng init done
10526 12:23:28.845158 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10527 12:23:28.848328 [ 0.000000] efi: UEFI not found.
10528 12:23:28.854739 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10529 12:23:28.861839 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10530 12:23:28.871433 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10531 12:23:28.881397 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10532 12:23:28.888248 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10533 12:23:28.894731 [ 0.000000] printk: bootconsole [mtk8250] enabled
10534 12:23:28.898049 [ 0.000000] NUMA: No NUMA configuration found
10535 12:23:28.908274 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10536 12:23:28.911247 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10537 12:23:28.914497 [ 0.000000] Zone ranges:
10538 12:23:28.921281 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10539 12:23:28.924766 [ 0.000000] DMA32 empty
10540 12:23:28.931380 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10541 12:23:28.934442 [ 0.000000] Movable zone start for each node
10542 12:23:28.937620 [ 0.000000] Early memory node ranges
10543 12:23:28.944412 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10544 12:23:28.951297 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10545 12:23:28.957921 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10546 12:23:28.961356 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10547 12:23:28.967444 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10548 12:23:28.974479 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10549 12:23:29.033088 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10550 12:23:29.039521 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10551 12:23:29.046135 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10552 12:23:29.049505 [ 0.000000] psci: probing for conduit method from DT.
10553 12:23:29.056136 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10554 12:23:29.059575 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10555 12:23:29.066326 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10556 12:23:29.069700 [ 0.000000] psci: SMC Calling Convention v1.2
10557 12:23:29.076155 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10558 12:23:29.079437 [ 0.000000] Detected VIPT I-cache on CPU0
10559 12:23:29.085902 [ 0.000000] CPU features: detected: GIC system register CPU interface
10560 12:23:29.093014 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10561 12:23:29.099731 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10562 12:23:29.105987 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10563 12:23:29.112931 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10564 12:23:29.119499 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10565 12:23:29.126050 [ 0.000000] alternatives: applying boot alternatives
10566 12:23:29.132276 [ 0.000000] Fallback order for Node 0: 0
10567 12:23:29.139768 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10568 12:23:29.142464 [ 0.000000] Policy zone: Normal
10569 12:23:29.155778 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10570 12:23:29.165954 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10571 12:23:29.177197 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10572 12:23:29.187200 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10573 12:23:29.194037 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10574 12:23:29.197303 <6>[ 0.000000] software IO TLB: area num 8.
10575 12:23:29.253889 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10576 12:23:29.403356 <6>[ 0.000000] Memory: 7873556K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 479212K reserved, 32768K cma-reserved)
10577 12:23:29.409878 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10578 12:23:29.416120 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10579 12:23:29.419259 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10580 12:23:29.426177 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10581 12:23:29.432764 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10582 12:23:29.435990 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10583 12:23:29.446313 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10584 12:23:29.452663 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10585 12:23:29.456222 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10586 12:23:29.463636 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10587 12:23:29.467517 <6>[ 0.000000] GICv3: 608 SPIs implemented
10588 12:23:29.473511 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10589 12:23:29.477125 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10590 12:23:29.480248 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10591 12:23:29.490079 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10592 12:23:29.500135 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10593 12:23:29.513880 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10594 12:23:29.520445 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10595 12:23:29.529557 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10596 12:23:29.543182 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10597 12:23:29.549638 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10598 12:23:29.555819 <6>[ 0.009182] Console: colour dummy device 80x25
10599 12:23:29.565738 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10600 12:23:29.568977 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10601 12:23:29.575707 <6>[ 0.029221] LSM: Security Framework initializing
10602 12:23:29.582500 <6>[ 0.034161] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10603 12:23:29.592549 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10604 12:23:29.599556 <6>[ 0.051453] cblist_init_generic: Setting adjustable number of callback queues.
10605 12:23:29.605776 <6>[ 0.058898] cblist_init_generic: Setting shift to 3 and lim to 1.
10606 12:23:29.615798 <6>[ 0.065237] cblist_init_generic: Setting adjustable number of callback queues.
10607 12:23:29.619105 <6>[ 0.072663] cblist_init_generic: Setting shift to 3 and lim to 1.
10608 12:23:29.626001 <6>[ 0.079076] rcu: Hierarchical SRCU implementation.
10609 12:23:29.632613 <6>[ 0.084120] rcu: Max phase no-delay instances is 1000.
10610 12:23:29.639035 <6>[ 0.091147] EFI services will not be available.
10611 12:23:29.641977 <6>[ 0.096147] smp: Bringing up secondary CPUs ...
10612 12:23:29.649878 <6>[ 0.101199] Detected VIPT I-cache on CPU1
10613 12:23:29.656419 <6>[ 0.101268] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10614 12:23:29.663146 <6>[ 0.101299] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10615 12:23:29.666815 <6>[ 0.101633] Detected VIPT I-cache on CPU2
10616 12:23:29.673567 <6>[ 0.101682] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10617 12:23:29.679747 <6>[ 0.101697] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10618 12:23:29.686454 <6>[ 0.101956] Detected VIPT I-cache on CPU3
10619 12:23:29.693156 <6>[ 0.102004] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10620 12:23:29.700341 <6>[ 0.102018] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10621 12:23:29.703422 <6>[ 0.102321] CPU features: detected: Spectre-v4
10622 12:23:29.710183 <6>[ 0.102327] CPU features: detected: Spectre-BHB
10623 12:23:29.713439 <6>[ 0.102332] Detected PIPT I-cache on CPU4
10624 12:23:29.719794 <6>[ 0.102391] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10625 12:23:29.726645 <6>[ 0.102408] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10626 12:23:29.733244 <6>[ 0.102700] Detected PIPT I-cache on CPU5
10627 12:23:29.740011 <6>[ 0.102762] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10628 12:23:29.746168 <6>[ 0.102779] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10629 12:23:29.749423 <6>[ 0.103064] Detected PIPT I-cache on CPU6
10630 12:23:29.756476 <6>[ 0.103127] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10631 12:23:29.762987 <6>[ 0.103144] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10632 12:23:29.769491 <6>[ 0.103442] Detected PIPT I-cache on CPU7
10633 12:23:29.776377 <6>[ 0.103507] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10634 12:23:29.782760 <6>[ 0.103524] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10635 12:23:29.786424 <6>[ 0.103571] smp: Brought up 1 node, 8 CPUs
10636 12:23:29.793341 <6>[ 0.244808] SMP: Total of 8 processors activated.
10637 12:23:29.796445 <6>[ 0.249729] CPU features: detected: 32-bit EL0 Support
10638 12:23:29.806590 <6>[ 0.255125] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10639 12:23:29.812663 <6>[ 0.263925] CPU features: detected: Common not Private translations
10640 12:23:29.816379 <6>[ 0.270401] CPU features: detected: CRC32 instructions
10641 12:23:29.822717 <6>[ 0.275753] CPU features: detected: RCpc load-acquire (LDAPR)
10642 12:23:29.829761 <6>[ 0.281750] CPU features: detected: LSE atomic instructions
10643 12:23:29.836246 <6>[ 0.287568] CPU features: detected: Privileged Access Never
10644 12:23:29.839504 <6>[ 0.293383] CPU features: detected: RAS Extension Support
10645 12:23:29.846300 <6>[ 0.299027] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10646 12:23:29.852697 <6>[ 0.306245] CPU: All CPU(s) started at EL2
10647 12:23:29.859733 <6>[ 0.310588] alternatives: applying system-wide alternatives
10648 12:23:29.867571 <6>[ 0.321289] devtmpfs: initialized
10649 12:23:29.880061 <6>[ 0.330282] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10650 12:23:29.890056 <6>[ 0.340243] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10651 12:23:29.896727 <6>[ 0.348317] pinctrl core: initialized pinctrl subsystem
10652 12:23:29.900241 <6>[ 0.354994] DMI not present or invalid.
10653 12:23:29.906969 <6>[ 0.359405] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10654 12:23:29.916673 <6>[ 0.366255] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10655 12:23:29.923864 <6>[ 0.373836] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10656 12:23:29.933360 <6>[ 0.382049] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10657 12:23:29.936688 <6>[ 0.390290] audit: initializing netlink subsys (disabled)
10658 12:23:29.946555 <5>[ 0.395982] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10659 12:23:29.953485 <6>[ 0.396694] thermal_sys: Registered thermal governor 'step_wise'
10660 12:23:29.959686 <6>[ 0.403950] thermal_sys: Registered thermal governor 'power_allocator'
10661 12:23:29.963263 <6>[ 0.410205] cpuidle: using governor menu
10662 12:23:29.966782 <6>[ 0.421168] NET: Registered PF_QIPCRTR protocol family
10663 12:23:29.976684 <6>[ 0.426645] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10664 12:23:29.979752 <6>[ 0.433750] ASID allocator initialised with 32768 entries
10665 12:23:29.986929 <6>[ 0.440321] Serial: AMBA PL011 UART driver
10666 12:23:29.995911 <4>[ 0.449163] Trying to register duplicate clock ID: 134
10667 12:23:30.051981 <6>[ 0.508757] KASLR enabled
10668 12:23:30.066402 <6>[ 0.516470] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10669 12:23:30.073300 <6>[ 0.523481] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10670 12:23:30.079413 <6>[ 0.529970] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10671 12:23:30.086455 <6>[ 0.536975] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10672 12:23:30.092819 <6>[ 0.543462] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10673 12:23:30.099965 <6>[ 0.550464] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10674 12:23:30.106094 <6>[ 0.556953] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10675 12:23:30.113127 <6>[ 0.563958] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10676 12:23:30.116250 <6>[ 0.571470] ACPI: Interpreter disabled.
10677 12:23:30.124425 <6>[ 0.577905] iommu: Default domain type: Translated
10678 12:23:30.131098 <6>[ 0.583018] iommu: DMA domain TLB invalidation policy: strict mode
10679 12:23:30.134764 <5>[ 0.589671] SCSI subsystem initialized
10680 12:23:30.140960 <6>[ 0.593835] usbcore: registered new interface driver usbfs
10681 12:23:30.147956 <6>[ 0.599566] usbcore: registered new interface driver hub
10682 12:23:30.150816 <6>[ 0.605118] usbcore: registered new device driver usb
10683 12:23:30.157754 <6>[ 0.611217] pps_core: LinuxPPS API ver. 1 registered
10684 12:23:30.167646 <6>[ 0.616411] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10685 12:23:30.171135 <6>[ 0.625758] PTP clock support registered
10686 12:23:30.173996 <6>[ 0.630002] EDAC MC: Ver: 3.0.0
10687 12:23:30.181826 <6>[ 0.635159] FPGA manager framework
10688 12:23:30.188370 <6>[ 0.638838] Advanced Linux Sound Architecture Driver Initialized.
10689 12:23:30.191444 <6>[ 0.645615] vgaarb: loaded
10690 12:23:30.198673 <6>[ 0.648790] clocksource: Switched to clocksource arch_sys_counter
10691 12:23:30.201326 <5>[ 0.655224] VFS: Disk quotas dquot_6.6.0
10692 12:23:30.208162 <6>[ 0.659409] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10693 12:23:30.211737 <6>[ 0.666598] pnp: PnP ACPI: disabled
10694 12:23:30.219712 <6>[ 0.673279] NET: Registered PF_INET protocol family
10695 12:23:30.229819 <6>[ 0.678865] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10696 12:23:30.241271 <6>[ 0.691163] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10697 12:23:30.250900 <6>[ 0.699978] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10698 12:23:30.257815 <6>[ 0.707947] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10699 12:23:30.264511 <6>[ 0.716645] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10700 12:23:30.276531 <6>[ 0.726389] TCP: Hash tables configured (established 65536 bind 65536)
10701 12:23:30.283121 <6>[ 0.733245] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10702 12:23:30.289201 <6>[ 0.740443] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10703 12:23:30.296176 <6>[ 0.748146] NET: Registered PF_UNIX/PF_LOCAL protocol family
10704 12:23:30.303060 <6>[ 0.754324] RPC: Registered named UNIX socket transport module.
10705 12:23:30.305891 <6>[ 0.760479] RPC: Registered udp transport module.
10706 12:23:30.312495 <6>[ 0.765411] RPC: Registered tcp transport module.
10707 12:23:30.319506 <6>[ 0.770344] RPC: Registered tcp NFSv4.1 backchannel transport module.
10708 12:23:30.322900 <6>[ 0.777014] PCI: CLS 0 bytes, default 64
10709 12:23:30.326305 <6>[ 0.781423] Unpacking initramfs...
10710 12:23:30.350910 <6>[ 0.800891] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10711 12:23:30.360563 <6>[ 0.809547] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10712 12:23:30.363871 <6>[ 0.818405] kvm [1]: IPA Size Limit: 40 bits
10713 12:23:30.370965 <6>[ 0.822933] kvm [1]: GICv3: no GICV resource entry
10714 12:23:30.374188 <6>[ 0.827953] kvm [1]: disabling GICv2 emulation
10715 12:23:30.380533 <6>[ 0.832640] kvm [1]: GIC system register CPU interface enabled
10716 12:23:30.384162 <6>[ 0.838807] kvm [1]: vgic interrupt IRQ18
10717 12:23:30.390438 <6>[ 0.843159] kvm [1]: VHE mode initialized successfully
10718 12:23:30.397306 <5>[ 0.849683] Initialise system trusted keyrings
10719 12:23:30.403409 <6>[ 0.854495] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10720 12:23:30.410867 <6>[ 0.864539] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10721 12:23:30.417969 <5>[ 0.870953] NFS: Registering the id_resolver key type
10722 12:23:30.421197 <5>[ 0.876256] Key type id_resolver registered
10723 12:23:30.427603 <5>[ 0.880672] Key type id_legacy registered
10724 12:23:30.434364 <6>[ 0.884953] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10725 12:23:30.441108 <6>[ 0.891872] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10726 12:23:30.447245 <6>[ 0.899591] 9p: Installing v9fs 9p2000 file system support
10727 12:23:30.483556 <5>[ 0.937145] Key type asymmetric registered
10728 12:23:30.487304 <5>[ 0.941478] Asymmetric key parser 'x509' registered
10729 12:23:30.497383 <6>[ 0.946639] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10730 12:23:30.500380 <6>[ 0.954251] io scheduler mq-deadline registered
10731 12:23:30.503643 <6>[ 0.959043] io scheduler kyber registered
10732 12:23:30.522597 <6>[ 0.976101] EINJ: ACPI disabled.
10733 12:23:30.555133 <4>[ 1.001745] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10734 12:23:30.564829 <4>[ 1.012361] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10735 12:23:30.579550 <6>[ 1.033193] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10736 12:23:30.587598 <6>[ 1.041192] printk: console [ttyS0] disabled
10737 12:23:30.615532 <6>[ 1.065834] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10738 12:23:30.622294 <6>[ 1.075309] printk: console [ttyS0] enabled
10739 12:23:30.625722 <6>[ 1.075309] printk: console [ttyS0] enabled
10740 12:23:30.632426 <6>[ 1.084204] printk: bootconsole [mtk8250] disabled
10741 12:23:30.635462 <6>[ 1.084204] printk: bootconsole [mtk8250] disabled
10742 12:23:30.642036 <6>[ 1.095445] SuperH (H)SCI(F) driver initialized
10743 12:23:30.645700 <6>[ 1.100747] msm_serial: driver initialized
10744 12:23:30.659766 <6>[ 1.109775] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10745 12:23:30.669574 <6>[ 1.118321] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10746 12:23:30.676228 <6>[ 1.126863] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10747 12:23:30.685964 <6>[ 1.135492] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10748 12:23:30.692869 <6>[ 1.144199] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10749 12:23:30.702783 <6>[ 1.152920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10750 12:23:30.712634 <6>[ 1.161461] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10751 12:23:30.719490 <6>[ 1.170266] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10752 12:23:30.729861 <6>[ 1.178809] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10753 12:23:30.740701 <6>[ 1.194388] loop: module loaded
10754 12:23:30.747505 <6>[ 1.200368] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10755 12:23:30.770537 <4>[ 1.223893] mtk-pmic-keys: Failed to locate of_node [id: -1]
10756 12:23:30.777223 <6>[ 1.230866] megasas: 07.719.03.00-rc1
10757 12:23:30.787003 <6>[ 1.240717] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10758 12:23:30.794451 <6>[ 1.248203] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10759 12:23:30.811818 <6>[ 1.265101] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10760 12:23:30.868621 <6>[ 1.315364] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10761 12:23:34.313431 <6>[ 4.767204] Freeing initrd memory: 95996K
10762 12:23:34.323561 <6>[ 4.777430] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10763 12:23:34.334771 <6>[ 4.788396] tun: Universal TUN/TAP device driver, 1.6
10764 12:23:34.337659 <6>[ 4.794471] thunder_xcv, ver 1.0
10765 12:23:34.340979 <6>[ 4.797976] thunder_bgx, ver 1.0
10766 12:23:34.344686 <6>[ 4.801470] nicpf, ver 1.0
10767 12:23:34.354997 <6>[ 4.805510] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10768 12:23:34.358458 <6>[ 4.812985] hns3: Copyright (c) 2017 Huawei Corporation.
10769 12:23:34.361626 <6>[ 4.818573] hclge is initializing
10770 12:23:34.368128 <6>[ 4.822154] e1000: Intel(R) PRO/1000 Network Driver
10771 12:23:34.374735 <6>[ 4.827283] e1000: Copyright (c) 1999-2006 Intel Corporation.
10772 12:23:34.378698 <6>[ 4.833295] e1000e: Intel(R) PRO/1000 Network Driver
10773 12:23:34.384886 <6>[ 4.838510] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10774 12:23:34.391116 <6>[ 4.844698] igb: Intel(R) Gigabit Ethernet Network Driver
10775 12:23:34.398169 <6>[ 4.850347] igb: Copyright (c) 2007-2014 Intel Corporation.
10776 12:23:34.404493 <6>[ 4.856182] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10777 12:23:34.411341 <6>[ 4.862700] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10778 12:23:34.414445 <6>[ 4.869162] sky2: driver version 1.30
10779 12:23:34.421427 <6>[ 4.874168] VFIO - User Level meta-driver version: 0.3
10780 12:23:34.428974 <6>[ 4.882452] usbcore: registered new interface driver usb-storage
10781 12:23:34.435008 <6>[ 4.888902] usbcore: registered new device driver onboard-usb-hub
10782 12:23:34.444415 <6>[ 4.898050] mt6397-rtc mt6359-rtc: registered as rtc0
10783 12:23:34.454032 <6>[ 4.903540] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-16T12:22:28 UTC (1692188548)
10784 12:23:34.457119 <6>[ 4.913148] i2c_dev: i2c /dev entries driver
10785 12:23:34.474288 <6>[ 4.924994] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10786 12:23:34.495259 <6>[ 4.948997] cpu cpu0: EM: created perf domain
10787 12:23:34.498772 <6>[ 4.954040] cpu cpu4: EM: created perf domain
10788 12:23:34.505470 <6>[ 4.959654] sdhci: Secure Digital Host Controller Interface driver
10789 12:23:34.512311 <6>[ 4.966088] sdhci: Copyright(c) Pierre Ossman
10790 12:23:34.518912 <6>[ 4.971043] Synopsys Designware Multimedia Card Interface Driver
10791 12:23:34.525698 <6>[ 4.977681] sdhci-pltfm: SDHCI platform and OF driver helper
10792 12:23:34.529071 <6>[ 4.977719] mmc0: CQHCI version 5.10
10793 12:23:34.535665 <6>[ 4.987918] ledtrig-cpu: registered to indicate activity on CPUs
10794 12:23:34.542720 <6>[ 4.994952] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10795 12:23:34.549044 <6>[ 5.002013] usbcore: registered new interface driver usbhid
10796 12:23:34.552183 <6>[ 5.007835] usbhid: USB HID core driver
10797 12:23:34.558991 <6>[ 5.012041] spi_master spi0: will run message pump with realtime priority
10798 12:23:34.602415 <6>[ 5.049956] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10799 12:23:34.622187 <6>[ 5.065904] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10800 12:23:34.629528 <6>[ 5.080493] cros-ec-spi spi0.0: Chrome EC device registered
10801 12:23:34.632613 <6>[ 5.086579] mmc0: Command Queue Engine enabled
10802 12:23:34.639003 <6>[ 5.091325] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10803 12:23:34.645576 <6>[ 5.098964] mmcblk0: mmc0:0001 DA4128 116 GiB
10804 12:23:34.657763 <6>[ 5.111489] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10805 12:23:34.667382 <6>[ 5.115320] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10806 12:23:34.674208 <6>[ 5.118856] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10807 12:23:34.677644 <6>[ 5.128042] NET: Registered PF_PACKET protocol family
10808 12:23:34.684062 <6>[ 5.132704] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10809 12:23:34.687517 <6>[ 5.137330] 9pnet: Installing 9P2000 support
10810 12:23:34.694191 <6>[ 5.143157] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10811 12:23:34.700636 <5>[ 5.147047] Key type dns_resolver registered
10812 12:23:34.704092 <6>[ 5.158306] registered taskstats version 1
10813 12:23:34.707013 <5>[ 5.162685] Loading compiled-in X.509 certificates
10814 12:23:34.736791 <4>[ 5.184097] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10815 12:23:34.746933 <4>[ 5.194806] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10816 12:23:34.753458 <3>[ 5.205361] debugfs: File 'uA_load' in directory '/' already present!
10817 12:23:34.760106 <3>[ 5.212080] debugfs: File 'min_uV' in directory '/' already present!
10818 12:23:34.766899 <3>[ 5.218743] debugfs: File 'max_uV' in directory '/' already present!
10819 12:23:34.773351 <3>[ 5.225437] debugfs: File 'constraint_flags' in directory '/' already present!
10820 12:23:34.784385 <3>[ 5.234970] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10821 12:23:34.795202 <6>[ 5.248975] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10822 12:23:34.802014 <6>[ 5.255749] xhci-mtk 11200000.usb: xHCI Host Controller
10823 12:23:34.808645 <6>[ 5.261242] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10824 12:23:34.818496 <6>[ 5.269083] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10825 12:23:34.824853 <6>[ 5.278506] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10826 12:23:34.831989 <6>[ 5.284576] xhci-mtk 11200000.usb: xHCI Host Controller
10827 12:23:34.838196 <6>[ 5.290053] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10828 12:23:34.845008 <6>[ 5.297700] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10829 12:23:34.851343 <6>[ 5.305373] hub 1-0:1.0: USB hub found
10830 12:23:34.854668 <6>[ 5.309387] hub 1-0:1.0: 1 port detected
10831 12:23:34.864513 <6>[ 5.313655] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10832 12:23:34.868043 <6>[ 5.322207] hub 2-0:1.0: USB hub found
10833 12:23:34.871056 <6>[ 5.326215] hub 2-0:1.0: 1 port detected
10834 12:23:34.880408 <6>[ 5.334050] mtk-msdc 11f70000.mmc: Got CD GPIO
10835 12:23:34.891548 <6>[ 5.341722] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10836 12:23:34.897882 <6>[ 5.349746] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10837 12:23:34.907602 <4>[ 5.357654] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10838 12:23:34.917992 <6>[ 5.367185] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10839 12:23:34.924236 <6>[ 5.375262] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10840 12:23:34.930973 <6>[ 5.383284] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10841 12:23:34.940867 <6>[ 5.391206] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10842 12:23:34.947335 <6>[ 5.399022] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10843 12:23:34.957320 <6>[ 5.406840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10844 12:23:34.967481 <6>[ 5.417348] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10845 12:23:34.973871 <6>[ 5.425710] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10846 12:23:34.984251 <6>[ 5.434058] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10847 12:23:34.990857 <6>[ 5.442396] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10848 12:23:35.000674 <6>[ 5.450735] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10849 12:23:35.007567 <6>[ 5.459073] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10850 12:23:35.017404 <6>[ 5.467411] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10851 12:23:35.023943 <6>[ 5.475755] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10852 12:23:35.033683 <6>[ 5.484094] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10853 12:23:35.040315 <6>[ 5.492432] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10854 12:23:35.050517 <6>[ 5.500769] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10855 12:23:35.056943 <6>[ 5.509107] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10856 12:23:35.067153 <6>[ 5.517445] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10857 12:23:35.073347 <6>[ 5.525784] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10858 12:23:35.083543 <6>[ 5.534121] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10859 12:23:35.089998 <6>[ 5.542843] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10860 12:23:35.096675 <6>[ 5.549988] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10861 12:23:35.103237 <6>[ 5.556768] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10862 12:23:35.109963 <6>[ 5.563532] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10863 12:23:35.117060 <6>[ 5.570474] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10864 12:23:35.126543 <6>[ 5.577251] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10865 12:23:35.136500 <6>[ 5.586383] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10866 12:23:35.146331 <6>[ 5.595504] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10867 12:23:35.156521 <6>[ 5.604798] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10868 12:23:35.166153 <6>[ 5.614266] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10869 12:23:35.172694 <6>[ 5.623734] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10870 12:23:35.182867 <6>[ 5.632854] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10871 12:23:35.192526 <6>[ 5.642321] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10872 12:23:35.202734 <6>[ 5.651441] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10873 12:23:35.212683 <6>[ 5.660734] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10874 12:23:35.222041 <6>[ 5.670894] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10875 12:23:35.232350 <6>[ 5.682798] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10876 12:23:35.281814 <6>[ 5.732900] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10877 12:23:35.436547 <6>[ 5.890485] hub 1-1:1.0: USB hub found
10878 12:23:35.439626 <6>[ 5.894956] hub 1-1:1.0: 4 ports detected
10879 12:23:35.562427 <6>[ 6.013147] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10880 12:23:35.588345 <6>[ 6.042214] hub 2-1:1.0: USB hub found
10881 12:23:35.591539 <6>[ 6.046657] hub 2-1:1.0: 3 ports detected
10882 12:23:35.762177 <6>[ 6.213082] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10883 12:23:35.894632 <6>[ 6.348960] hub 1-1.4:1.0: USB hub found
10884 12:23:35.897903 <6>[ 6.353615] hub 1-1.4:1.0: 2 ports detected
10885 12:23:35.974181 <6>[ 6.425217] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10886 12:23:36.194235 <6>[ 6.645113] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10887 12:23:36.386687 <6>[ 6.837094] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10888 12:23:47.507195 <6>[ 17.966093] ALSA device list:
10889 12:23:47.514171 <6>[ 17.969382] No soundcards found.
10890 12:23:47.522197 <6>[ 17.977325] Freeing unused kernel memory: 8384K
10891 12:23:47.525538 <6>[ 17.982332] Run /init as init process
10892 12:23:47.570980 <6>[ 18.026476] NET: Registered PF_INET6 protocol family
10893 12:23:47.577818 <6>[ 18.032861] Segment Routing with IPv6
10894 12:23:47.580751 <6>[ 18.036800] In-situ OAM (IOAM) with IPv6
10895 12:23:47.615002 <30>[ 18.050774] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10896 12:23:47.618549 <30>[ 18.074630] systemd[1]: Detected architecture arm64.
10897 12:23:47.618653
10898 12:23:47.624948 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10899 12:23:47.625036
10900 12:23:47.637355 <30>[ 18.093169] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10901 12:23:47.759007 <30>[ 18.211426] systemd[1]: Queued start job for default target Graphical Interface.
10902 12:23:47.802518 <30>[ 18.257771] systemd[1]: Created slice system-getty.slice.
10903 12:23:47.809170 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10904 12:23:47.825946 <30>[ 18.281587] systemd[1]: Created slice system-modprobe.slice.
10905 12:23:47.832581 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10906 12:23:47.854145 <30>[ 18.309701] systemd[1]: Created slice system-serial\x2dgetty.slice.
10907 12:23:47.864352 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10908 12:23:47.878425 <30>[ 18.333801] systemd[1]: Created slice User and Session Slice.
10909 12:23:47.884843 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10910 12:23:47.905342 <30>[ 18.357678] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10911 12:23:47.915525 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10912 12:23:47.933806 <30>[ 18.385714] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10913 12:23:47.940087 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10914 12:23:47.965093 <30>[ 18.413539] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10915 12:23:47.971220 <30>[ 18.425826] systemd[1]: Reached target Local Encrypted Volumes.
10916 12:23:47.978082 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10917 12:23:47.993650 <30>[ 18.449168] systemd[1]: Reached target Paths.
10918 12:23:47.997104 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10919 12:23:48.017504 <30>[ 18.473156] systemd[1]: Reached target Remote File Systems.
10920 12:23:48.024471 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10921 12:23:48.042145 <30>[ 18.497440] systemd[1]: Reached target Slices.
10922 12:23:48.048436 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10923 12:23:48.061676 <30>[ 18.517103] systemd[1]: Reached target Swap.
10924 12:23:48.065061 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10925 12:23:48.085332 <30>[ 18.537568] systemd[1]: Listening on initctl Compatibility Named Pipe.
10926 12:23:48.092081 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10927 12:23:48.098846 <30>[ 18.552668] systemd[1]: Listening on Journal Audit Socket.
10928 12:23:48.105175 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10929 12:23:48.118131 <30>[ 18.573520] systemd[1]: Listening on Journal Socket (/dev/log).
10930 12:23:48.124579 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10931 12:23:48.143107 <30>[ 18.598309] systemd[1]: Listening on Journal Socket.
10932 12:23:48.149588 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10933 12:23:48.162017 <30>[ 18.617635] systemd[1]: Listening on udev Control Socket.
10934 12:23:48.168841 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10935 12:23:48.186874 <30>[ 18.642105] systemd[1]: Listening on udev Kernel Socket.
10936 12:23:48.193293 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10937 12:23:48.241758 <30>[ 18.697325] systemd[1]: Mounting Huge Pages File System...
10938 12:23:48.248219 Mounting [0;1;39mHuge Pages File System[0m...
10939 12:23:48.265346 <30>[ 18.721103] systemd[1]: Mounting POSIX Message Queue File System...
10940 12:23:48.272579 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10941 12:23:48.309747 <30>[ 18.765150] systemd[1]: Mounting Kernel Debug File System...
10942 12:23:48.316160 Mounting [0;1;39mKernel Debug File System[0m...
10943 12:23:48.333030 <30>[ 18.785372] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10944 12:23:48.346262 <30>[ 18.798343] systemd[1]: Starting Create list of static device nodes for the current kernel...
10945 12:23:48.352601 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10946 12:23:48.373524 <30>[ 18.829381] systemd[1]: Starting Load Kernel Module configfs...
10947 12:23:48.380153 Starting [0;1;39mLoad Kernel Module configfs[0m...
10948 12:23:48.397447 <30>[ 18.853166] systemd[1]: Starting Load Kernel Module drm...
10949 12:23:48.404497 Starting [0;1;39mLoad Kernel Module drm[0m...
10950 12:23:48.420988 <30>[ 18.873155] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10951 12:23:48.435192 <30>[ 18.890533] systemd[1]: Starting Journal Service...
10952 12:23:48.438414 Starting [0;1;39mJournal Service[0m...
10953 12:23:48.456286 <30>[ 18.911797] systemd[1]: Starting Load Kernel Modules...
10954 12:23:48.463035 Starting [0;1;39mLoad Kernel Modules[0m...
10955 12:23:48.485815 <30>[ 18.938004] systemd[1]: Starting Remount Root and Kernel File Systems...
10956 12:23:48.492207 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10957 12:23:48.508862 <30>[ 18.964424] systemd[1]: Starting Coldplug All udev Devices...
10958 12:23:48.515423 Starting [0;1;39mColdplug All udev Devices[0m...
10959 12:23:48.532909 <30>[ 18.988359] systemd[1]: Started Journal Service.
10960 12:23:48.539095 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10961 12:23:48.555575 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10962 12:23:48.570692 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10963 12:23:48.586396 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10964 12:23:48.606189 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10965 12:23:48.623829 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10966 12:23:48.640798 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10967 12:23:48.659133 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10968 12:23:48.714412 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10969 12:23:48.729519 See 'systemctl status systemd-remount-fs.service' for details.
10970 12:23:48.750480 Mounting [0;1;39mKernel Configuration File System[0m...
10971 12:23:48.768887 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10972 12:23:48.781290 <46>[ 19.233763] systemd-journald[176]: Received client request to flush runtime journal.
10973 12:23:48.795086 Starting [0;1;39mLoad/Save Random Seed[0m...
10974 12:23:48.818135 Starting [0;1;39mApply Kernel Variables[0m...
10975 12:23:48.842506 Starting [0;1;39mCreate System Users[0m...
10976 12:23:48.867041 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10977 12:23:48.882552 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10978 12:23:48.906661 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10979 12:23:48.919372 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10980 12:23:48.935468 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10981 12:23:48.951269 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10982 12:23:48.997888 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10983 12:23:49.021744 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10984 12:23:49.034048 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10985 12:23:49.049339 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10986 12:23:49.082353 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10987 12:23:49.113232 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10988 12:23:49.133179 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10989 12:23:49.149801 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10990 12:23:49.196299 Starting [0;1;39mNetwork Time Synchronization[0m...
10991 12:23:49.216221 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10992 12:23:49.264831 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10993 12:23:49.286073 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<6>[ 19.738356] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10994 12:23:49.289123 e Synchronization[0m.
10995 12:23:49.302460 <6>[ 19.754391] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10996 12:23:49.308608 <6>[ 19.762320] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10997 12:23:49.318985 <6>[ 19.771424] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10998 12:23:49.325808 <6>[ 19.777506] remoteproc remoteproc0: scp is available
10999 12:23:49.328764 <6>[ 19.785427] remoteproc remoteproc0: powering up scp
11000 12:23:49.338772 <6>[ 19.790565] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11001 12:23:49.345590 <6>[ 19.790585] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11002 12:23:49.348805 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11003 12:23:49.359020 <3>[ 19.811305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11004 12:23:49.365335 <3>[ 19.819503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11005 12:23:49.375895 <3>[ 19.827964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11006 12:23:49.382134 <6>[ 19.833212] usbcore: registered new interface driver r8152
11007 12:23:49.392191 [[0;32m OK [0m] Created slice [0;1;39msyste<3>[ 19.845652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11008 12:23:49.395428 m-systemd\x2dbacklight.slice[0m.
11009 12:23:49.405609 <3>[ 19.857830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11010 12:23:49.412199 <3>[ 19.866241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11011 12:23:49.423097 <3>[ 19.875049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11012 12:23:49.429627 <3>[ 19.883371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11013 12:23:49.435938 <6>[ 19.884479] mc: Linux media interface: v0.10
11014 12:23:49.442932 <3>[ 19.885726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11015 12:23:49.449645 <4>[ 19.886490] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11016 12:23:49.459232 <4>[ 19.887226] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11017 12:23:49.465881 <3>[ 19.890314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11018 12:23:49.475706 <3>[ 19.890341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11019 12:23:49.482307 [[0;32m OK [<3>[ 19.890350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11020 12:23:49.491996 <6>[ 19.900726] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11021 12:23:49.502046 0m] Reached targ<3>[ 19.907796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11022 12:23:49.512201 et [0;1;39mSyst<6>[ 19.930569] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11023 12:23:49.518895 em Time Set[0m.<6>[ 19.930577] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11024 12:23:49.518982
11025 12:23:49.528597 <3>[ 19.935004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11026 12:23:49.532370 <6>[ 19.944441] remoteproc remoteproc0: remote processor scp is now up
11027 12:23:49.542978 <6>[ 19.946249] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11028 12:23:49.549570 <3>[ 19.952129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11029 12:23:49.556195 <3>[ 19.952140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11030 12:23:49.565752 <4>[ 19.961656] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11031 12:23:49.572362 <4>[ 19.961656] Fallback method does not support PEC.
11032 12:23:49.579162 <3>[ 19.971523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11033 12:23:49.585679 <6>[ 19.972447] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11034 12:23:49.591994 <6>[ 19.982646] videodev: Linux video capture interface: v2.00
11035 12:23:49.599349 <6>[ 19.988350] pci_bus 0000:00: root bus resource [bus 00-ff]
11036 12:23:49.605508 <3>[ 19.988983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11037 12:23:49.615602 <3>[ 20.000655] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11038 12:23:49.622337 <6>[ 20.001965] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11039 12:23:49.632747 <6>[ 20.010444] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11040 12:23:49.639454 <6>[ 20.010614] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11041 12:23:49.649635 <6>[ 20.018010] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11042 12:23:49.656694 <6>[ 20.018067] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11043 12:23:49.666290 <6>[ 20.018084] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11044 12:23:49.669660 <6>[ 20.018184] pci 0000:00:00.0: supports D1 D2
11045 12:23:49.676313 <6>[ 20.018189] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11046 12:23:49.683081 <6>[ 20.028903] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11047 12:23:49.692947 <6>[ 20.033313] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11048 12:23:49.699637 <6>[ 20.040852] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11049 12:23:49.709555 <3>[ 20.094975] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11050 12:23:49.716062 <3>[ 20.096078] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11051 12:23:49.722851 <6>[ 20.101964] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11052 12:23:49.732619 <6>[ 20.184438] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11053 12:23:49.739812 [[0;32m OK [<6>[ 20.192124] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11054 12:23:49.746138 0m] Reached targ<6>[ 20.194738] Bluetooth: Core ver 2.22
11055 12:23:49.749857 <6>[ 20.201726] pci 0000:01:00.0: supports D1 D2
11056 12:23:49.755971 <6>[ 20.210704] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11057 12:23:49.762923 <6>[ 20.210821] NET: Registered PF_BLUETOOTH protocol family
11058 12:23:49.772723 et [0;1;39mSyst<4>[ 20.218310] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11059 12:23:49.779332 em Time Synchron<6>[ 20.221934] usbcore: registered new interface driver cdc_ether
11060 12:23:49.786366 <6>[ 20.223155] Bluetooth: HCI device and connection manager initialized
11061 12:23:49.796344 <4>[ 20.233592] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11062 12:23:49.799469 <6>[ 20.241062] Bluetooth: HCI socket layer initialized
11063 12:23:49.806054 <6>[ 20.253456] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11064 12:23:49.813092 <6>[ 20.254956] usbcore: registered new interface driver r8153_ecm
11065 12:23:49.819885 <6>[ 20.255723] Bluetooth: L2CAP socket layer initialized
11066 12:23:49.826671 <6>[ 20.260983] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11067 12:23:49.833470 <6>[ 20.261214] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11068 12:23:49.847003 <6>[ 20.262372] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11069 12:23:49.847090 ized[0m.
11070 12:23:49.853617 <6>[ 20.262528] usbcore: registered new interface driver uvcvideo
11071 12:23:49.857245 <6>[ 20.267736] Bluetooth: SCO socket layer initialized
11072 12:23:49.867281 <6>[ 20.273818] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11073 12:23:49.873572 <3>[ 20.276983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11074 12:23:49.883475 <3>[ 20.297129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11075 12:23:49.890452 <6>[ 20.306663] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11076 12:23:49.900139 <6>[ 20.306679] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11077 12:23:49.906721 <6>[ 20.306694] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11078 12:23:49.914215 <6>[ 20.306707] pci 0000:00:00.0: PCI bridge to [bus 01]
11079 12:23:49.921026 <6>[ 20.306714] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11080 12:23:49.928335 <6>[ 20.307294] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11081 12:23:49.935159 <6>[ 20.310720] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11082 12:23:49.941934 <6>[ 20.326665] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11083 12:23:49.948345 <6>[ 20.328225] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11084 12:23:49.955195 <6>[ 20.336413] usbcore: registered new interface driver btusb
11085 12:23:49.965073 <4>[ 20.337268] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11086 12:23:49.972163 <3>[ 20.337289] Bluetooth: hci0: Failed to load firmware file (-2)
11087 12:23:49.975708 <3>[ 20.337293] Bluetooth: hci0: Failed to set up firmware (-2)
11088 12:23:49.985362 <4>[ 20.337298] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11089 12:23:49.995701 <6>[ 20.338034] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11090 12:23:50.002102 <6>[ 20.344691] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11091 12:23:50.008590 <3>[ 20.382299] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11092 12:23:50.019386 <3>[ 20.383448] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11093 12:23:50.026041 <3>[ 20.388169] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11094 12:23:50.036344 <5>[ 20.410573] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11095 12:23:50.042486 <3>[ 20.435245] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11096 12:23:50.049603 <5>[ 20.448633] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11097 12:23:50.060335 <3>[ 20.479705] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11098 12:23:50.066760 <4>[ 20.488185] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11099 12:23:50.073618 <6>[ 20.529409] r8152 2-1.3:1.0 eth0: v1.12.13
11100 12:23:50.077259 <6>[ 20.533988] cfg80211: failed to load regulatory.db
11101 12:23:50.084202 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11102 12:23:50.110659 [[0;32m OK [0m] Finished [0;1;39mLoad/Save <6>[ 20.563548] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11103 12:23:50.117575 <6>[ 20.568930] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11104 12:23:50.125003 Screen …s of l<6>[ 20.577643] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11105 12:23:50.127677 eds:white:kbd_backlight[0m.
11106 12:23:50.149816 <6>[ 20.605454] mt7921e 0000:01:00.0: ASIC revision: 79610010
11107 12:23:50.259114 <4>[ 20.708400] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11108 12:23:50.277688 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11109 12:23:50.293649 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11110 12:23:50.312842 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11111 12:23:50.328822 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11112 12:23:50.341613 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11113 12:23:50.361369 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11114 12:23:50.377910 <4>[ 20.827236] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11115 12:23:50.384525 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11116 12:23:50.397541 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11117 12:23:50.417465 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11118 12:23:50.450560 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11119 12:23:50.498819 <4>[ 20.948128] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11120 12:23:50.502296 Starting [0;1;39mUser Login Management[0m...
11121 12:23:50.520983 Starting [0;1;39mPermit User Sessions[0m...
11122 12:23:50.538995 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11123 12:23:50.559484 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11124 12:23:50.582569 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11125 12:23:50.598629 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11126 12:23:50.618537 <4>[ 21.067694] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11127 12:23:50.635327 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11128 12:23:50.655346 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11129 12:23:50.671212 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11130 12:23:50.691542 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11131 12:23:50.705838 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11132 12:23:50.739044 <4>[ 21.187836] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11133 12:23:50.770718 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11134 12:23:50.806709 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11135 12:23:50.858561 <4>[ 21.307744] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11136 12:23:50.875979
11137 12:23:50.876110
11138 12:23:50.879221 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11139 12:23:50.879321
11140 12:23:50.882557 debian-bullseye-arm64 login: root (automatic login)
11141 12:23:50.882642
11142 12:23:50.882707
11143 12:23:50.912681 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Wed Aug 16 12:04:53 UTC 2023 aarch64
11144 12:23:50.912775
11145 12:23:50.919050 The programs included with the Debian GNU/Linux system are free software;
11146 12:23:50.925674 the exact distribution terms for each program are described in the
11147 12:23:50.929284 individual files in /usr/share/doc/*/copyright.
11148 12:23:50.929367
11149 12:23:50.935951 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11150 12:23:50.939316 permitted by applicable law.
11151 12:23:50.939693 Matched prompt #10: / #
11153 12:23:50.939929 Setting prompt string to ['/ #']
11154 12:23:50.940020 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11156 12:23:50.940211 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11157 12:23:50.940297 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11158 12:23:50.940368 Setting prompt string to ['/ #']
11159 12:23:50.940428 Forcing a shell prompt, looking for ['/ #']
11161 12:23:50.990643 / #
11162 12:23:50.990766 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11163 12:23:50.990887 Waiting using forced prompt support (timeout 00:02:30)
11164 12:23:50.991015 <4>[ 21.427928] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11165 12:23:50.995871
11166 12:23:50.996145 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11167 12:23:50.996243 start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11168 12:23:50.996338 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11169 12:23:50.996459 end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11170 12:23:50.996550 end: 2 depthcharge-action (duration 00:02:00) [common]
11171 12:23:50.996637 start: 3 lava-test-retry (timeout 00:05:00) [common]
11172 12:23:50.996753 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11173 12:23:50.996828 Using namespace: common
11175 12:23:51.097229 / # #
11176 12:23:51.097403 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11177 12:23:51.098484 #<4>[ 21.547723] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11178 12:23:51.139759
11179 12:23:51.140101 Using /lava-11299254
11181 12:23:51.240495 / # export SHELL=/bin/sh
11182 12:23:51.240702 export SHELL=/bin/sh<4>[ 21.667792] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11183 12:23:51.246184
11185 12:23:51.346712 / # . /lava-11299254/environment
11186 12:23:51.346930 . /lava-11299254/environment<4>[ 21.787797] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11187 12:23:51.351756
11189 12:23:51.496209 / # /lava-11299254/bin/lava-test-runner /lava-11299254/0
11190 12:23:51.496359 Test shell timeout: 10s (minimum of the action and connection timeout)
11191 12:23:51.496719 <3>[ 21.905170] mt7921e 0000:01:00.0: hardware init failed
11192 12:23:51.501166 /lava-11299254/bin/lava-test-runner /lava-11299254/0
11193 12:23:51.543699 + export TESTRUN_ID=0_sleep
11194 12:23:51.543802 + cd /lava-11299254/0/tests/0_sleep
11195 12:23:51.543909 + cat uuid
11196 12:23:51.543972 + UUID=11299254_1.5.2.3.1
11197 12:23:51.544032 + set +x
11198 12:23:51.544268 <LAVA_SIGNAL_STARTRUN 0_sleep 11299254_1.5.2.3.1>
11199 12:23:51.544335 + ./config/lava/sleep/sleep.sh mem freeze
11200 12:23:51.544395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11201 12:23:51.544686 Received signal: <STARTRUN> 0_sleep 11299254_1.5.2.3.1
11202 12:23:51.544790 Starting test lava.0_sleep (11299254_1.5.2.3.1)
11203 12:23:51.544878 Skipping test definition patterns.
11204 12:23:51.544976 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11206 12:23:51.548483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11207 12:23:51.548729 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11209 12:23:51.551393 rtcwake: assuming RTC uses UTC ...
11210 12:23:51.558423 rtcwake: wakeup from "mem" using rtc0 at Wed<6>[ 22.016394] PM: suspend entry (deep)
11211 12:23:51.564544 Aug 16 12:22:51<6>[ 22.020774] Filesystems sync: 0.000 seconds
11212 12:23:51.564631 2023
11213 12:23:51.572285 <6>[ 22.028363] Freezing user space processes
11214 12:23:51.579145 <6>[ 22.034252] Freezing user space processes completed (elapsed 0.001 seconds)
11215 12:23:51.585830 <6>[ 22.041484] OOM killer disabled.
11216 12:23:51.588741 <6>[ 22.044966] Freezing remaining freezable tasks
11217 12:23:51.599023 <6>[ 22.050831] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11218 12:23:51.605431 <6>[ 22.058500] printk: Suspending console(s) (use no_console_suspend to debug)
11219 12:23:54.935297 <3>[ 25.165160] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11220 12:23:54.944974 <3>[ 25.165193] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11221 12:23:54.954783 <3>[ 25.165240] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11222 12:23:54.961498 <3>[ 25.165280] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11223 12:23:54.967802 <3>[ 25.165564] PM: Some devices failed to suspend, or early wake event detected
11224 12:23:54.977765 <4>[ 25.181781] typec port0-partner: PM: parent port0 should not be sleeping
11225 12:23:54.981223 <6>[ 25.437932] OOM killer enabled.
11226 12:23:54.984744 <6>[ 25.441345] Restarting tasks ... done.
11227 12:23:54.991294 <5>[ 25.447429] random: crng reseeded on system resumption
11228 12:23:54.994829 <6>[ 25.453919] PM: suspend exit
11229 12:23:54.997812 rtcwake: write error
11230 12:23:55.005318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11231 12:23:55.005609 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11233 12:23:55.008975 rtcwake: assuming RTC uses UTC ...
11234 12:23:55.015330 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 16 12:22:55 2023
11235 12:23:55.028029 <6>[ 25.484500] PM: suspend entry (deep)
11236 12:23:55.031526 <6>[ 25.488399] Filesystems sync: 0.000 seconds
11237 12:23:55.034772 <6>[ 25.493451] Freezing user space processes
11238 12:23:55.046243 <6>[ 25.499383] Freezing user space processes completed (elapsed 0.001 seconds)
11239 12:23:55.049817 <6>[ 25.506615] OOM killer disabled.
11240 12:23:55.053146 <6>[ 25.510097] Freezing remaining freezable tasks
11241 12:23:55.063058 <6>[ 25.516184] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11242 12:23:55.069555 <6>[ 25.523865] printk: Suspending console(s) (use no_console_suspend to debug)
11243 12:23:58.518335 <3>[ 28.749118] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11244 12:23:58.528360 <3>[ 28.749152] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11245 12:23:58.538442 <3>[ 28.749209] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11246 12:23:58.545073 <3>[ 28.749256] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11247 12:23:58.552045 <3>[ 28.749536] PM: Some devices failed to suspend, or early wake event detected
11248 12:23:58.554726 <6>[ 29.014844] OOM killer enabled.
11249 12:23:58.566180 <6>[ 29.018264] Restarting tasks ... done.
11250 12:23:58.569782 <5>[ 29.027017] random: crng reseeded on system resumption
11251 12:23:58.573364 <6>[ 29.033643] PM: suspend exit
11252 12:23:58.576844 rtcwake: write error
11253 12:23:58.584544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11254 12:23:58.584837 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11256 12:23:58.587656 rtcwake: assuming RTC uses UTC ...
11257 12:23:58.594259 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 16 12:22:58 2023
11258 12:23:58.606955 <6>[ 29.063776] PM: suspend entry (deep)
11259 12:23:58.610138 <6>[ 29.067671] Filesystems sync: 0.000 seconds
11260 12:23:58.613840 <6>[ 29.072660] Freezing user space processes
11261 12:23:58.625309 <6>[ 29.078701] Freezing user space processes completed (elapsed 0.001 seconds)
11262 12:23:58.628586 <6>[ 29.085930] OOM killer disabled.
11263 12:23:58.631869 <6>[ 29.089413] Freezing remaining freezable tasks
11264 12:23:58.641913 <6>[ 29.095499] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11265 12:23:58.648519 <6>[ 29.103184] printk: Suspending console(s) (use no_console_suspend to debug)
11266 12:24:02.110335 <3>[ 32.333173] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11267 12:24:02.120374 <3>[ 32.333220] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11268 12:24:02.130194 <3>[ 32.333273] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11269 12:24:02.136859 <3>[ 32.333322] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11270 12:24:02.143841 <3>[ 32.333628] PM: Some devices failed to suspend, or early wake event detected
11271 12:24:02.146684 <6>[ 32.607125] OOM killer enabled.
11272 12:24:02.155756 <6>[ 32.610537] Restarting tasks ... done.
11273 12:24:02.162375 <5>[ 32.618171] random: crng reseeded on system resumption
11274 12:24:02.165319 <6>[ 32.624724] PM: suspend exit
11275 12:24:02.169432 rtcwake: write error
11276 12:24:02.175572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11277 12:24:02.175896 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11279 12:24:02.178948 rtcwake: assuming RTC uses UTC ...
11280 12:24:02.185411 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 16 12:23:02 2023
11281 12:24:02.197206 <6>[ 32.654602] PM: suspend entry (deep)
11282 12:24:02.200589 <6>[ 32.658501] Filesystems sync: 0.000 seconds
11283 12:24:02.204276 <6>[ 32.663520] Freezing user space processes
11284 12:24:02.215170 <6>[ 32.668903] Freezing user space processes completed (elapsed 0.001 seconds)
11285 12:24:02.218230 <6>[ 32.676137] OOM killer disabled.
11286 12:24:02.221689 <6>[ 32.679618] Freezing remaining freezable tasks
11287 12:24:02.231827 <6>[ 32.685574] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11288 12:24:02.238561 <6>[ 32.693227] printk: Suspending console(s) (use no_console_suspend to debug)
11289 12:24:05.685985 <3>[ 35.917095] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11290 12:24:05.695823 <3>[ 35.917124] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11291 12:24:05.705400 <3>[ 35.917165] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11292 12:24:05.712561 <3>[ 35.917207] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11293 12:24:05.718947 <3>[ 35.917513] PM: Some devices failed to suspend, or early wake event detected
11294 12:24:05.722422 <6>[ 36.182919] OOM killer enabled.
11295 12:24:05.732029 <6>[ 36.186333] Restarting tasks ... done.
11296 12:24:05.735416 <5>[ 36.193710] random: crng reseeded on system resumption
11297 12:24:05.739534 <6>[ 36.200527] PM: suspend exit
11298 12:24:05.743093 rtcwake: write error
11299 12:24:05.751146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11300 12:24:05.751410 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11302 12:24:05.753925 rtcwake: assuming RTC uses UTC ...
11303 12:24:05.760488 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 16 12:23:06 2023
11304 12:24:05.773473 <6>[ 36.230981] PM: suspend entry (deep)
11305 12:24:05.777153 <6>[ 36.234888] Filesystems sync: 0.000 seconds
11306 12:24:05.780310 <6>[ 36.239909] Freezing user space processes
11307 12:24:05.791500 <6>[ 36.245880] Freezing user space processes completed (elapsed 0.001 seconds)
11308 12:24:05.795164 <6>[ 36.253109] OOM killer disabled.
11309 12:24:05.798172 <6>[ 36.256586] Freezing remaining freezable tasks
11310 12:24:05.808720 <6>[ 36.262636] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11311 12:24:05.815443 <6>[ 36.270314] printk: Suspending console(s) (use no_console_suspend to debug)
11312 12:24:09.269159 <3>[ 39.501092] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11313 12:24:09.278923 <3>[ 39.501122] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11314 12:24:09.288914 <3>[ 39.501165] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11315 12:24:09.295894 <3>[ 39.501205] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11316 12:24:09.302335 <3>[ 39.501510] PM: Some devices failed to suspend, or early wake event detected
11317 12:24:09.308769 <6>[ 39.767019] OOM killer enabled.
11318 12:24:09.315739 <6>[ 39.770431] Restarting tasks ... done.
11319 12:24:09.319317 <5>[ 39.777835] random: crng reseeded on system resumption
11320 12:24:09.322857 <6>[ 39.784143] PM: suspend exit
11321 12:24:09.326336 rtcwake: write error
11322 12:24:09.334286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11323 12:24:09.334546 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11325 12:24:09.337556 rtcwake: assuming RTC uses UTC ...
11326 12:24:09.344288 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 16 12:23:09 2023
11327 12:24:09.356510 <6>[ 39.814584] PM: suspend entry (deep)
11328 12:24:09.359715 <6>[ 39.818472] Filesystems sync: 0.000 seconds
11329 12:24:09.363125 <6>[ 39.823489] Freezing user space processes
11330 12:24:09.374634 <6>[ 39.829380] Freezing user space processes completed (elapsed 0.001 seconds)
11331 12:24:09.377918 <6>[ 39.836600] OOM killer disabled.
11332 12:24:09.381555 <6>[ 39.840081] Freezing remaining freezable tasks
11333 12:24:09.391540 <6>[ 39.846137] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11334 12:24:09.398345 <6>[ 39.853805] printk: Suspending console(s) (use no_console_suspend to debug)
11335 12:24:12.852441 <3>[ 43.085127] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11336 12:24:12.865841 <3>[ 43.085156] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11337 12:24:12.872307 <3>[ 43.085199] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11338 12:24:12.879209 <3>[ 43.085239] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11339 12:24:12.889054 <3>[ 43.085541] PM: Some devices failed to suspend, or early wake event detected
11340 12:24:12.892494 <6>[ 43.351017] OOM killer enabled.
11341 12:24:12.904208 <6>[ 43.354429] Restarting tasks ... done.
11342 12:24:12.907737 <5>[ 43.366690] random: crng reseeded on system resumption
11343 12:24:12.911779 <6>[ 43.373415] PM: suspend exit
11344 12:24:12.914917 rtcwake: write error
11345 12:24:12.923014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11346 12:24:12.923297 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11348 12:24:12.926293 rtcwake: assuming RTC uses UTC ...
11349 12:24:12.933138 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 16 12:23:13 2023
11350 12:24:12.945470 <6>[ 43.404033] PM: suspend entry (deep)
11351 12:24:12.948989 <6>[ 43.407929] Filesystems sync: 0.000 seconds
11352 12:24:12.952417 <6>[ 43.413010] Freezing user space processes
11353 12:24:12.963998 <6>[ 43.418971] Freezing user space processes completed (elapsed 0.001 seconds)
11354 12:24:12.967523 <6>[ 43.426207] OOM killer disabled.
11355 12:24:12.970460 <6>[ 43.429687] Freezing remaining freezable tasks
11356 12:24:12.980798 <6>[ 43.435742] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11357 12:24:12.987544 <6>[ 43.443415] printk: Suspending console(s) (use no_console_suspend to debug)
11358 12:24:16.436191 <3>[ 46.669095] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11359 12:24:16.446021 <3>[ 46.669125] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11360 12:24:16.455963 <3>[ 46.669167] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11361 12:24:16.462920 <3>[ 46.669208] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11362 12:24:16.469390 <3>[ 46.669507] PM: Some devices failed to suspend, or early wake event detected
11363 12:24:16.476303 <6>[ 46.934895] OOM killer enabled.
11364 12:24:16.479647 <6>[ 46.938307] Restarting tasks ... done.
11365 12:24:16.486445 <5>[ 46.944345] random: crng reseeded on system resumption
11366 12:24:16.489864 <6>[ 46.950621] PM: suspend exit
11367 12:24:16.492756 rtcwake: write error
11368 12:24:16.500045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11369 12:24:16.500307 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11371 12:24:16.503041 rtcwake: assuming RTC uses UTC ...
11372 12:24:16.509359 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 16 12:23:16 2023
11373 12:24:16.522317 <6>[ 46.981079] PM: suspend entry (deep)
11374 12:24:16.525912 <6>[ 46.984987] Filesystems sync: 0.000 seconds
11375 12:24:16.529058 <6>[ 46.990002] Freezing user space processes
11376 12:24:16.540702 <6>[ 46.995993] Freezing user space processes completed (elapsed 0.001 seconds)
11377 12:24:16.544179 <6>[ 47.003225] OOM killer disabled.
11378 12:24:16.547145 <6>[ 47.006707] Freezing remaining freezable tasks
11379 12:24:16.557363 <6>[ 47.012798] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11380 12:24:16.564042 <6>[ 47.020459] printk: Suspending console(s) (use no_console_suspend to debug)
11381 12:24:20.020677 <6>[ 48.205180] vpu: disabling
11382 12:24:20.024222 <6>[ 48.205327] vproc2: disabling
11383 12:24:20.027327 <6>[ 48.205381] vproc1: disabling
11384 12:24:20.030729 <6>[ 48.205436] vaud18: disabling
11385 12:24:20.034128 <6>[ 48.205683] vsram_others: disabling
11386 12:24:20.037604 <6>[ 48.205882] va09: disabling
11387 12:24:20.040598 <6>[ 48.205959] vsram_md: disabling
11388 12:24:20.044053 <6>[ 48.206087] Vgpu: disabling
11389 12:24:20.050928 <3>[ 50.253089] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11390 12:24:20.060853 <3>[ 50.253120] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11391 12:24:20.070891 <3>[ 50.253162] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11392 12:24:20.077324 <3>[ 50.253203] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11393 12:24:20.084036 <3>[ 50.253447] PM: Some devices failed to suspend, or early wake event detected
11394 12:24:20.087564 <6>[ 50.549105] OOM killer enabled.
11395 12:24:20.094899 <6>[ 50.552504] Restarting tasks ... done.
11396 12:24:20.098332 <5>[ 50.558158] random: crng reseeded on system resumption
11397 12:24:20.102921 <6>[ 50.565139] PM: suspend exit
11398 12:24:20.105629 rtcwake: write error
11399 12:24:20.113236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11400 12:24:20.113501 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11402 12:24:20.116702 rtcwake: assuming RTC uses UTC ...
11403 12:24:20.123512 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 16 12:23:20 2023
11404 12:24:20.135749 <6>[ 50.594941] PM: suspend entry (deep)
11405 12:24:20.139226 <6>[ 50.598835] Filesystems sync: 0.000 seconds
11406 12:24:20.142618 <6>[ 50.603866] Freezing user space processes
11407 12:24:20.154152 <6>[ 50.609782] Freezing user space processes completed (elapsed 0.001 seconds)
11408 12:24:20.157082 <6>[ 50.617006] OOM killer disabled.
11409 12:24:20.160496 <6>[ 50.620484] Freezing remaining freezable tasks
11410 12:24:20.170749 <6>[ 50.626511] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11411 12:24:20.177558 <6>[ 50.634180] printk: Suspending console(s) (use no_console_suspend to debug)
11412 12:24:23.607933 <3>[ 53.837134] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11413 12:24:23.617660 <3>[ 53.837171] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11414 12:24:23.627899 <3>[ 53.837217] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11415 12:24:23.634145 <3>[ 53.837262] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11416 12:24:23.640871 <3>[ 53.837468] PM: Some devices failed to suspend, or early wake event detected
11417 12:24:23.647664 <6>[ 54.107212] OOM killer enabled.
11418 12:24:23.650602 <6>[ 54.110623] Restarting tasks ... done.
11419 12:24:23.657596 <5>[ 54.116707] random: crng reseeded on system resumption
11420 12:24:23.661137 <6>[ 54.123187] PM: suspend exit
11421 12:24:23.663986 rtcwake: write error
11422 12:24:23.671642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11423 12:24:23.671922 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11425 12:24:23.674456 rtcwake: assuming RTC uses UTC ...
11426 12:24:23.681504 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 16 12:23:24 2023
11427 12:24:23.693873 <6>[ 54.153452] PM: suspend entry (deep)
11428 12:24:23.697290 <6>[ 54.157345] Filesystems sync: 0.000 seconds
11429 12:24:23.700285 <6>[ 54.162398] Freezing user space processes
11430 12:24:23.712597 <6>[ 54.168322] Freezing user space processes completed (elapsed 0.001 seconds)
11431 12:24:23.715404 <6>[ 54.175559] OOM killer disabled.
11432 12:24:23.718812 <6>[ 54.179039] Freezing remaining freezable tasks
11433 12:24:23.728956 <6>[ 54.185020] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11434 12:24:23.735257 <6>[ 54.192689] printk: Suspending console(s) (use no_console_suspend to debug)
11435 12:24:27.191255 <3>[ 57.421165] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11436 12:24:27.200845 <3>[ 57.421204] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11437 12:24:27.211213 <3>[ 57.421254] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11438 12:24:27.218048 <3>[ 57.421294] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11439 12:24:27.224461 <3>[ 57.421558] PM: Some devices failed to suspend, or early wake event detected
11440 12:24:27.231432 <6>[ 57.691081] OOM killer enabled.
11441 12:24:27.234181 <6>[ 57.694492] Restarting tasks ... done.
11442 12:24:27.241166 <5>[ 57.700266] random: crng reseeded on system resumption
11443 12:24:27.244585 <6>[ 57.706475] PM: suspend exit
11444 12:24:27.247975 rtcwake: write error
11445 12:24:27.254584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11446 12:24:27.254872 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11448 12:24:27.258074 rtcwake: assuming RTC uses UTC ...
11449 12:24:27.264283 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:27 2023
11450 12:24:27.278454 <6>[ 57.738381] PM: suspend entry (s2idle)
11451 12:24:27.281533 <6>[ 57.742450] Filesystems sync: 0.000 seconds
11452 12:24:27.285032 <6>[ 57.747480] Freezing user space processes
11453 12:24:27.296562 <6>[ 57.752956] Freezing user space processes completed (elapsed 0.001 seconds)
11454 12:24:27.299480 <6>[ 57.760174] OOM killer disabled.
11455 12:24:27.302749 <6>[ 57.763654] Freezing remaining freezable tasks
11456 12:24:27.313286 <6>[ 57.769581] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11457 12:24:27.319829 <6>[ 57.777232] printk: Suspending console(s) (use no_console_suspend to debug)
11458 12:24:30.779094 <3>[ 61.005087] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11459 12:24:30.788865 <3>[ 61.005116] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11460 12:24:30.798725 <3>[ 61.005159] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11461 12:24:30.805658 <3>[ 61.005201] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11462 12:24:30.812091 <3>[ 61.005514] PM: Some devices failed to suspend, or early wake event detected
11463 12:24:30.818701 <6>[ 61.279137] OOM killer enabled.
11464 12:24:30.821799 <6>[ 61.282549] Restarting tasks ... done.
11465 12:24:30.828921 <5>[ 61.288480] random: crng reseeded on system resumption
11466 12:24:30.832190 <6>[ 61.295839] PM: suspend exit
11467 12:24:30.835796 rtcwake: write error
11468 12:24:30.842952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11469 12:24:30.843211 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11471 12:24:30.846360 rtcwake: assuming RTC uses UTC ...
11472 12:24:30.852755 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:31 2023
11473 12:24:30.865727 <6>[ 61.326027] PM: suspend entry (s2idle)
11474 12:24:30.869006 <6>[ 61.330109] Filesystems sync: 0.000 seconds
11475 12:24:30.872737 <6>[ 61.335161] Freezing user space processes
11476 12:24:30.883739 <6>[ 61.341017] Freezing user space processes completed (elapsed 0.001 seconds)
11477 12:24:30.887335 <6>[ 61.348242] OOM killer disabled.
11478 12:24:30.890912 <6>[ 61.351723] Freezing remaining freezable tasks
11479 12:24:30.900523 <6>[ 61.357739] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11480 12:24:30.907548 <6>[ 61.365411] printk: Suspending console(s) (use no_console_suspend to debug)
11481 12:24:34.358493 <3>[ 64.589094] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11482 12:24:34.368702 <3>[ 64.589123] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11483 12:24:34.378902 <3>[ 64.589167] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11484 12:24:34.385078 <3>[ 64.589207] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11485 12:24:34.391963 <3>[ 64.589508] PM: Some devices failed to suspend, or early wake event detected
11486 12:24:34.395246 <6>[ 64.859122] OOM killer enabled.
11487 12:24:34.404120 <6>[ 64.862532] Restarting tasks ... done.
11488 12:24:34.407018 <5>[ 64.868653] random: crng reseeded on system resumption
11489 12:24:34.411814 <6>[ 64.875993] PM: suspend exit
11490 12:24:34.415231 rtcwake: write error
11491 12:24:34.423153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11492 12:24:34.423436 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11494 12:24:34.426142 rtcwake: assuming RTC uses UTC ...
11495 12:24:34.432686 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:34 2023
11496 12:24:34.445444 <6>[ 64.906298] PM: suspend entry (s2idle)
11497 12:24:34.448936 <6>[ 64.910374] Filesystems sync: 0.000 seconds
11498 12:24:34.452407 <6>[ 64.915421] Freezing user space processes
11499 12:24:34.463736 <6>[ 64.920928] Freezing user space processes completed (elapsed 0.001 seconds)
11500 12:24:34.466593 <6>[ 64.928149] OOM killer disabled.
11501 12:24:34.469793 <6>[ 64.931628] Freezing remaining freezable tasks
11502 12:24:34.480279 <6>[ 64.937558] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11503 12:24:34.486951 <6>[ 64.945215] printk: Suspending console(s) (use no_console_suspend to debug)
11504 12:24:37.946594 <3>[ 68.173102] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11505 12:24:37.956588 <3>[ 68.173131] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11506 12:24:37.966550 <3>[ 68.173174] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11507 12:24:37.972979 <3>[ 68.173215] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11508 12:24:37.979908 <3>[ 68.173460] PM: Some devices failed to suspend, or early wake event detected
11509 12:24:37.982777 <6>[ 68.447178] OOM killer enabled.
11510 12:24:37.991475 <6>[ 68.450596] Restarting tasks ... done.
11511 12:24:37.994434 <5>[ 68.456533] random: crng reseeded on system resumption
11512 12:24:37.998518 <6>[ 68.463007] PM: suspend exit
11513 12:24:38.001856 rtcwake: write error
11514 12:24:38.009666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11515 12:24:38.009923 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11517 12:24:38.013157 rtcwake: assuming RTC uses UTC ...
11518 12:24:38.019498 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:38 2023
11519 12:24:38.032549 <6>[ 68.493519] PM: suspend entry (s2idle)
11520 12:24:38.035329 <6>[ 68.497588] Filesystems sync: 0.000 seconds
11521 12:24:38.042391 <6>[ 68.502601] Freezing user space processes
11522 12:24:38.048841 <6>[ 68.508487] Freezing user space processes completed (elapsed 0.001 seconds)
11523 12:24:38.052193 <6>[ 68.515725] OOM killer disabled.
11524 12:24:38.059063 <6>[ 68.519207] Freezing remaining freezable tasks
11525 12:24:38.065631 <6>[ 68.524817] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11526 12:24:38.072062 <6>[ 68.532467] printk: Suspending console(s) (use no_console_suspend to debug)
11527 12:24:41.521572 <3>[ 71.757123] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11528 12:24:41.531586 <3>[ 71.757156] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11529 12:24:41.541593 <3>[ 71.757204] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11530 12:24:41.548343 <3>[ 71.757258] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11531 12:24:41.554671 <3>[ 71.757556] PM: Some devices failed to suspend, or early wake event detected
11532 12:24:41.561801 <6>[ 72.022980] OOM killer enabled.
11533 12:24:41.564641 <6>[ 72.026392] Restarting tasks ... done.
11534 12:24:41.571203 <5>[ 72.032327] random: crng reseeded on system resumption
11535 12:24:41.574681 <6>[ 72.039287] PM: suspend exit
11536 12:24:41.578138 rtcwake: write error
11537 12:24:41.585485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11538 12:24:41.585771 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11540 12:24:41.588768 rtcwake: assuming RTC uses UTC ...
11541 12:24:41.595489 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:41 2023
11542 12:24:41.607742 <6>[ 72.069410] PM: suspend entry (s2idle)
11543 12:24:41.611202 <6>[ 72.073483] Filesystems sync: 0.000 seconds
11544 12:24:41.614378 <6>[ 72.078523] Freezing user space processes
11545 12:24:41.626159 <6>[ 72.084405] Freezing user space processes completed (elapsed 0.001 seconds)
11546 12:24:41.629581 <6>[ 72.091642] OOM killer disabled.
11547 12:24:41.633289 <6>[ 72.095124] Freezing remaining freezable tasks
11548 12:24:41.642611 <6>[ 72.100822] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11549 12:24:41.649370 <6>[ 72.108474] printk: Suspending console(s) (use no_console_suspend to debug)
11550 12:24:45.113734 <3>[ 75.341104] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11551 12:24:45.123742 <3>[ 75.341134] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11552 12:24:45.133571 <3>[ 75.341177] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11553 12:24:45.140330 <3>[ 75.341217] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11554 12:24:45.146559 <3>[ 75.341459] PM: Some devices failed to suspend, or early wake event detected
11555 12:24:45.150011 <6>[ 75.615141] OOM killer enabled.
11556 12:24:45.158649 <6>[ 75.618553] Restarting tasks ... done.
11557 12:24:45.162053 <5>[ 75.624689] random: crng reseeded on system resumption
11558 12:24:45.166358 <6>[ 75.631752] PM: suspend exit
11559 12:24:45.169828 rtcwake: write error
11560 12:24:45.177368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11561 12:24:45.177627 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11563 12:24:45.180751 rtcwake: assuming RTC uses UTC ...
11564 12:24:45.187897 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:45 2023
11565 12:24:45.200046 <6>[ 75.662072] PM: suspend entry (s2idle)
11566 12:24:45.203508 <6>[ 75.666144] Filesystems sync: 0.000 seconds
11567 12:24:45.210410 <6>[ 75.671164] Freezing user space processes
11568 12:24:45.216697 <6>[ 75.677075] Freezing user space processes completed (elapsed 0.001 seconds)
11569 12:24:45.220032 <6>[ 75.684302] OOM killer disabled.
11570 12:24:45.226583 <6>[ 75.687785] Freezing remaining freezable tasks
11571 12:24:45.233643 <6>[ 75.693885] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11572 12:24:45.243267 <6>[ 75.701552] printk: Suspending console(s) (use no_console_suspend to debug)
11573 12:24:48.693099 <3>[ 78.925091] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11574 12:24:48.703083 <3>[ 78.925121] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11575 12:24:48.712909 <3>[ 78.925164] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11576 12:24:48.719524 <3>[ 78.925204] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11577 12:24:48.725820 <3>[ 78.925492] PM: Some devices failed to suspend, or early wake event detected
11578 12:24:48.729207 <6>[ 79.194973] OOM killer enabled.
11579 12:24:48.739184 <6>[ 79.198389] Restarting tasks ... done.
11580 12:24:48.742116 <5>[ 79.205474] random: crng reseeded on system resumption
11581 12:24:48.747172 <6>[ 79.212745] PM: suspend exit
11582 12:24:48.750000 rtcwake: write error
11583 12:24:48.758044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11584 12:24:48.758296 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11586 12:24:48.761357 rtcwake: assuming RTC uses UTC ...
11587 12:24:48.768391 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:49 2023
11588 12:24:48.780455 <6>[ 79.242998] PM: suspend entry (s2idle)
11589 12:24:48.784202 <6>[ 79.247067] Filesystems sync: 0.000 seconds
11590 12:24:48.787132 <6>[ 79.252093] Freezing user space processes
11591 12:24:48.799093 <6>[ 79.258008] Freezing user space processes completed (elapsed 0.001 seconds)
11592 12:24:48.802428 <6>[ 79.265249] OOM killer disabled.
11593 12:24:48.805774 <6>[ 79.268725] Freezing remaining freezable tasks
11594 12:24:48.815989 <6>[ 79.274770] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11595 12:24:48.822311 <6>[ 79.282442] printk: Suspending console(s) (use no_console_suspend to debug)
11596 12:24:52.280591 <3>[ 82.509180] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11597 12:24:52.290729 <3>[ 82.509219] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11598 12:24:52.300492 <3>[ 82.509271] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11599 12:24:52.307246 <3>[ 82.509316] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11600 12:24:52.313851 <3>[ 82.509637] PM: Some devices failed to suspend, or early wake event detected
11601 12:24:52.317095 <6>[ 82.783103] OOM killer enabled.
11602 12:24:52.326047 <6>[ 82.786521] Restarting tasks ... done.
11603 12:24:52.328939 <5>[ 82.792640] random: crng reseeded on system resumption
11604 12:24:52.333855 <6>[ 82.799914] PM: suspend exit
11605 12:24:52.336938 rtcwake: write error
11606 12:24:52.345336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11607 12:24:52.345589 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11609 12:24:52.348268 rtcwake: assuming RTC uses UTC ...
11610 12:24:52.355244 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:52 2023
11611 12:24:52.367678 <6>[ 82.830450] PM: suspend entry (s2idle)
11612 12:24:52.371246 <6>[ 82.834531] Filesystems sync: 0.000 seconds
11613 12:24:52.374179 <6>[ 82.839539] Freezing user space processes
11614 12:24:52.385605 <6>[ 82.844883] Freezing user space processes completed (elapsed 0.001 seconds)
11615 12:24:52.389313 <6>[ 82.852102] OOM killer disabled.
11616 12:24:52.391852 <6>[ 82.855581] Freezing remaining freezable tasks
11617 12:24:52.402203 <6>[ 82.861451] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11618 12:24:52.408852 <6>[ 82.869107] printk: Suspending console(s) (use no_console_suspend to debug)
11619 12:24:55.860546 <3>[ 86.093110] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11620 12:24:55.870030 <3>[ 86.093139] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11621 12:24:55.880386 <3>[ 86.093182] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11622 12:24:55.886632 <3>[ 86.093226] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11623 12:24:55.893439 <3>[ 86.093485] PM: Some devices failed to suspend, or early wake event detected
11624 12:24:55.900135 <6>[ 86.363134] OOM killer enabled.
11625 12:24:55.903015 <6>[ 86.366557] Restarting tasks ... done.
11626 12:24:55.909699 <5>[ 86.372797] random: crng reseeded on system resumption
11627 12:24:55.913009 <6>[ 86.379206] PM: suspend exit
11628 12:24:55.916299 rtcwake: write error
11629 12:24:55.923516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11630 12:24:55.923800 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11632 12:24:55.926877 rtcwake: assuming RTC uses UTC ...
11633 12:24:55.933267 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:56 2023
11634 12:24:55.946405 <6>[ 86.409187] PM: suspend entry (s2idle)
11635 12:24:55.949329 <6>[ 86.413256] Filesystems sync: 0.000 seconds
11636 12:24:55.955682 <6>[ 86.418278] Freezing user space processes
11637 12:24:55.962475 <6>[ 86.424168] Freezing user space processes completed (elapsed 0.001 seconds)
11638 12:24:55.965918 <6>[ 86.431400] OOM killer disabled.
11639 12:24:55.972439 <6>[ 86.434883] Freezing remaining freezable tasks
11640 12:24:55.979160 <6>[ 86.440978] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11641 12:24:55.989080 <6>[ 86.448646] printk: Suspending console(s) (use no_console_suspend to debug)
11642 12:24:59.448413 <3>[ 89.677135] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11643 12:24:59.457929 <3>[ 89.677165] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11644 12:24:59.468273 <3>[ 89.677206] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11645 12:24:59.474402 <3>[ 89.677247] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11646 12:24:59.481515 <3>[ 89.677550] PM: Some devices failed to suspend, or early wake event detected
11647 12:24:59.484584 <6>[ 89.951115] OOM killer enabled.
11648 12:24:59.492760 <6>[ 89.954532] Restarting tasks ... done.
11649 12:24:59.496060 <5>[ 89.960443] random: crng reseeded on system resumption
11650 12:24:59.500561 <6>[ 89.967670] PM: suspend exit
11651 12:24:59.504337 rtcwake: write error
11652 12:24:59.512018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11653 12:24:59.512410 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11655 12:24:59.515214 rtcwake: assuming RTC uses UTC ...
11656 12:24:59.521963 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 16 12:23:59 2023
11657 12:24:59.534227 <6>[ 89.997747] PM: suspend entry (s2idle)
11658 12:24:59.537847 <6>[ 90.001816] Filesystems sync: 0.000 seconds
11659 12:24:59.541274 <6>[ 90.006838] Freezing user space processes
11660 12:24:59.552831 <6>[ 90.012747] Freezing user space processes completed (elapsed 0.001 seconds)
11661 12:24:59.556257 <6>[ 90.019975] OOM killer disabled.
11662 12:24:59.558948 <6>[ 90.023457] Freezing remaining freezable tasks
11663 12:24:59.569465 <6>[ 90.029349] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11664 12:24:59.575751 <6>[ 90.037005] printk: Suspending console(s) (use no_console_suspend to debug)
11665 12:25:03.023125 <3>[ 93.261091] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11666 12:25:03.033252 <3>[ 93.261121] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11667 12:25:03.043173 <3>[ 93.261164] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11668 12:25:03.050065 <3>[ 93.261204] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11669 12:25:03.056704 <3>[ 93.261444] PM: Some devices failed to suspend, or early wake event detected
11670 12:25:03.063057 <6>[ 93.527070] OOM killer enabled.
11671 12:25:03.066612 <6>[ 93.530486] Restarting tasks ... done.
11672 12:25:03.074082 <5>[ 93.537776] random: crng reseeded on system resumption
11673 12:25:03.076912 <6>[ 93.544280] PM: suspend exit
11674 12:25:03.080272 rtcwake: write error
11675 12:25:03.087926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11676 12:25:03.088279 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11678 12:25:03.091277 + set +x
11679 12:25:03.094330 <LAVA_SIGNAL_ENDRUN 0_sleep 11299254_1.5.2.3.1>
11680 12:25:03.094506 <LAVA_TEST_RUNNER EXIT>
11681 12:25:03.094839 Received signal: <ENDRUN> 0_sleep 11299254_1.5.2.3.1
11682 12:25:03.095000 Ending use of test pattern.
11683 12:25:03.095132 Ending test lava.0_sleep (11299254_1.5.2.3.1), duration 71.55
11685 12:25:03.095588 ok: lava_test_shell seems to have completed
11686 12:25:03.096005 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11687 12:25:03.096200 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11688 12:25:03.096380 end: 3 lava-test-retry (duration 00:01:12) [common]
11689 12:25:03.096561 start: 4 finalize (timeout 00:06:15) [common]
11690 12:25:03.096751 start: 4.1 power-off (timeout 00:00:30) [common]
11691 12:25:03.097064 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11692 12:25:03.189645 >> Command sent successfully.
11693 12:25:03.199825 Returned 0 in 0 seconds
11694 12:25:03.300612 end: 4.1 power-off (duration 00:00:00) [common]
11696 12:25:03.301835 start: 4.2 read-feedback (timeout 00:06:15) [common]
11697 12:25:03.302700 Listened to connection for namespace 'common' for up to 1s
11698 12:25:03.303363 Listened to connection for namespace 'common' for up to 1s
11699 12:25:04.303484 Finalising connection for namespace 'common'
11700 12:25:04.303915 Disconnecting from shell: Finalise
11701 12:25:04.304129 / #
11702 12:25:04.404696 end: 4.2 read-feedback (duration 00:00:01) [common]
11703 12:25:04.405013 end: 4 finalize (duration 00:00:01) [common]
11704 12:25:04.405262 Cleaning after the job
11705 12:25:04.405478 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/ramdisk
11706 12:25:04.428114 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/kernel
11707 12:25:04.457254 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/dtb
11708 12:25:04.457492 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299254/tftp-deploy-u8xrdn7k/modules
11709 12:25:04.464637 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11299254
11710 12:25:04.633898 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11299254
11711 12:25:04.634078 Job finished correctly