Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 64
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 31
- Errors: 1
1 12:19:27.078741 lava-dispatcher, installed at version: 2023.06
2 12:19:27.078972 start: 0 validate
3 12:19:27.079111 Start time: 2023-08-16 12:19:27.079103+00:00 (UTC)
4 12:19:27.079262 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:19:27.079418 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:19:27.347088 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:19:27.347273 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:20:04.603430 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:20:04.603612 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:20:04.859249 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:20:04.859467 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-1-g0a940c1b3dc0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:20:09.117917 validate duration: 42.04
14 12:20:09.118343 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:20:09.118510 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:20:09.118666 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:20:09.118857 Not decompressing ramdisk as can be used compressed.
18 12:20:09.119001 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 12:20:09.119126 saving as /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/ramdisk/rootfs.cpio.gz
20 12:20:09.119246 total size: 26246609 (25 MB)
21 12:20:09.368576 progress 0 % (0 MB)
22 12:20:09.375852 progress 5 % (1 MB)
23 12:20:09.382839 progress 10 % (2 MB)
24 12:20:09.389741 progress 15 % (3 MB)
25 12:20:09.397010 progress 20 % (5 MB)
26 12:20:09.404452 progress 25 % (6 MB)
27 12:20:09.411983 progress 30 % (7 MB)
28 12:20:09.419445 progress 35 % (8 MB)
29 12:20:09.426790 progress 40 % (10 MB)
30 12:20:09.434814 progress 45 % (11 MB)
31 12:20:09.442511 progress 50 % (12 MB)
32 12:20:09.449909 progress 55 % (13 MB)
33 12:20:09.457389 progress 60 % (15 MB)
34 12:20:09.464718 progress 65 % (16 MB)
35 12:20:09.472066 progress 70 % (17 MB)
36 12:20:09.479490 progress 75 % (18 MB)
37 12:20:09.486790 progress 80 % (20 MB)
38 12:20:09.494157 progress 85 % (21 MB)
39 12:20:09.501254 progress 90 % (22 MB)
40 12:20:09.508376 progress 95 % (23 MB)
41 12:20:09.515634 progress 100 % (25 MB)
42 12:20:09.515910 25 MB downloaded in 0.40 s (63.10 MB/s)
43 12:20:09.516132 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:20:09.516549 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:20:09.516680 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:20:09.516806 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:20:09.516957 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:20:09.517034 saving as /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/kernel/Image
50 12:20:09.517098 total size: 49220096 (46 MB)
51 12:20:09.517185 No compression specified
52 12:20:09.518338 progress 0 % (0 MB)
53 12:20:09.531925 progress 5 % (2 MB)
54 12:20:09.545625 progress 10 % (4 MB)
55 12:20:09.559541 progress 15 % (7 MB)
56 12:20:09.573266 progress 20 % (9 MB)
57 12:20:09.587140 progress 25 % (11 MB)
58 12:20:09.600843 progress 30 % (14 MB)
59 12:20:09.614231 progress 35 % (16 MB)
60 12:20:09.627757 progress 40 % (18 MB)
61 12:20:09.641600 progress 45 % (21 MB)
62 12:20:09.655631 progress 50 % (23 MB)
63 12:20:09.669548 progress 55 % (25 MB)
64 12:20:09.683463 progress 60 % (28 MB)
65 12:20:09.697372 progress 65 % (30 MB)
66 12:20:09.711134 progress 70 % (32 MB)
67 12:20:09.724801 progress 75 % (35 MB)
68 12:20:09.738183 progress 80 % (37 MB)
69 12:20:09.751872 progress 85 % (39 MB)
70 12:20:09.765733 progress 90 % (42 MB)
71 12:20:09.779904 progress 95 % (44 MB)
72 12:20:09.793643 progress 100 % (46 MB)
73 12:20:09.793839 46 MB downloaded in 0.28 s (169.62 MB/s)
74 12:20:09.794062 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:20:09.794447 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:20:09.794568 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:20:09.794695 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:20:09.794870 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:20:09.794973 saving as /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/dtb/mt8192-asurada-spherion-r0.dtb
81 12:20:09.795066 total size: 47278 (0 MB)
82 12:20:09.795163 No compression specified
83 12:20:09.796824 progress 69 % (0 MB)
84 12:20:09.797144 progress 100 % (0 MB)
85 12:20:09.797338 0 MB downloaded in 0.00 s (19.87 MB/s)
86 12:20:09.797515 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:20:09.797894 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:20:09.798015 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:20:09.798133 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:20:09.798285 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-1-g0a940c1b3dc0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:20:09.798386 saving as /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/modules/modules.tar
93 12:20:09.798480 total size: 8615968 (8 MB)
94 12:20:09.798576 Using unxz to decompress xz
95 12:20:09.802293 progress 0 % (0 MB)
96 12:20:09.824430 progress 5 % (0 MB)
97 12:20:09.847404 progress 10 % (0 MB)
98 12:20:09.874807 progress 15 % (1 MB)
99 12:20:09.902556 progress 20 % (1 MB)
100 12:20:09.929093 progress 25 % (2 MB)
101 12:20:09.955714 progress 30 % (2 MB)
102 12:20:09.984117 progress 35 % (2 MB)
103 12:20:10.011351 progress 40 % (3 MB)
104 12:20:10.037769 progress 45 % (3 MB)
105 12:20:10.064353 progress 50 % (4 MB)
106 12:20:10.089986 progress 55 % (4 MB)
107 12:20:10.115443 progress 60 % (4 MB)
108 12:20:10.138599 progress 65 % (5 MB)
109 12:20:10.167807 progress 70 % (5 MB)
110 12:20:10.192554 progress 75 % (6 MB)
111 12:20:10.219904 progress 80 % (6 MB)
112 12:20:10.250332 progress 85 % (7 MB)
113 12:20:10.277266 progress 90 % (7 MB)
114 12:20:10.301776 progress 95 % (7 MB)
115 12:20:10.325287 progress 100 % (8 MB)
116 12:20:10.331771 8 MB downloaded in 0.53 s (15.41 MB/s)
117 12:20:10.332036 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:20:10.332448 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:20:10.332578 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:20:10.332705 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:20:10.332838 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:20:10.332967 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:20:10.333233 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6
125 12:20:10.333414 makedir: /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin
126 12:20:10.333554 makedir: /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/tests
127 12:20:10.333685 makedir: /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/results
128 12:20:10.333841 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-add-keys
129 12:20:10.334025 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-add-sources
130 12:20:10.334192 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-background-process-start
131 12:20:10.334367 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-background-process-stop
132 12:20:10.334533 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-common-functions
133 12:20:10.334692 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-echo-ipv4
134 12:20:10.334876 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-install-packages
135 12:20:10.335038 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-installed-packages
136 12:20:10.335227 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-os-build
137 12:20:10.335405 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-probe-channel
138 12:20:10.335568 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-probe-ip
139 12:20:10.335729 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-target-ip
140 12:20:10.335889 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-target-mac
141 12:20:10.336019 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-target-storage
142 12:20:10.336150 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-test-case
143 12:20:10.336313 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-test-event
144 12:20:10.336480 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-test-feedback
145 12:20:10.336640 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-test-raise
146 12:20:10.336802 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-test-reference
147 12:20:10.336953 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-test-runner
148 12:20:10.337080 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-test-set
149 12:20:10.337215 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-test-shell
150 12:20:10.337355 Updating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-install-packages (oe)
151 12:20:10.337553 Updating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/bin/lava-installed-packages (oe)
152 12:20:10.337717 Creating /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/environment
153 12:20:10.337866 LAVA metadata
154 12:20:10.337975 - LAVA_JOB_ID=11299277
155 12:20:10.338073 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:20:10.338216 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:20:10.338312 skipped lava-vland-overlay
158 12:20:10.338434 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:20:10.338549 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:20:10.338648 skipped lava-multinode-overlay
161 12:20:10.338756 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:20:10.338881 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:20:10.338994 Loading test definitions
164 12:20:10.339146 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:20:10.339258 Using /lava-11299277 at stage 0
166 12:20:10.339699 uuid=11299277_1.5.2.3.1 testdef=None
167 12:20:10.339821 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:20:10.339931 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:20:10.340668 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:20:10.341007 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:20:10.341979 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:20:10.342377 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:20:10.343341 runner path: /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11299277_1.5.2.3.1
176 12:20:10.343548 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:20:10.343920 Creating lava-test-runner.conf files
179 12:20:10.344023 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11299277/lava-overlay-kkvkp3o6/lava-11299277/0 for stage 0
180 12:20:10.344148 - 0_v4l2-compliance-mtk-vcodec-enc
181 12:20:10.344293 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:20:10.344426 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:20:10.353061 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:20:10.353194 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:20:10.353322 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:20:10.353452 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:20:10.353577 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:20:11.091949 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:20:11.092331 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:20:11.092458 extracting modules file /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11299277/extract-overlay-ramdisk-41wuu_7a/ramdisk
191 12:20:11.315796 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:20:11.315983 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:20:11.316086 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299277/compress-overlay-iaffc4uo/overlay-1.5.2.4.tar.gz to ramdisk
194 12:20:11.316169 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299277/compress-overlay-iaffc4uo/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11299277/extract-overlay-ramdisk-41wuu_7a/ramdisk
195 12:20:11.323118 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:20:11.323241 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:20:11.323342 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:20:11.323434 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:20:11.323513 Building ramdisk /var/lib/lava/dispatcher/tmp/11299277/extract-overlay-ramdisk-41wuu_7a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11299277/extract-overlay-ramdisk-41wuu_7a/ramdisk
200 12:20:11.898477 >> 228241 blocks
201 12:20:15.937546 rename /var/lib/lava/dispatcher/tmp/11299277/extract-overlay-ramdisk-41wuu_7a/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/ramdisk/ramdisk.cpio.gz
202 12:20:15.938108 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:20:15.938295 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 12:20:15.938470 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 12:20:15.938636 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/kernel/Image'
206 12:20:29.298608 Returned 0 in 13 seconds
207 12:20:29.399231 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/kernel/image.itb
208 12:20:29.961920 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:20:29.962316 output: Created: Wed Aug 16 13:20:29 2023
210 12:20:29.962426 output: Image 0 (kernel-1)
211 12:20:29.962525 output: Description:
212 12:20:29.962632 output: Created: Wed Aug 16 13:20:29 2023
213 12:20:29.962738 output: Type: Kernel Image
214 12:20:29.962849 output: Compression: lzma compressed
215 12:20:29.962959 output: Data Size: 11040376 Bytes = 10781.62 KiB = 10.53 MiB
216 12:20:29.963066 output: Architecture: AArch64
217 12:20:29.963168 output: OS: Linux
218 12:20:29.963274 output: Load Address: 0x00000000
219 12:20:29.963370 output: Entry Point: 0x00000000
220 12:20:29.963462 output: Hash algo: crc32
221 12:20:29.963566 output: Hash value: 79630449
222 12:20:29.963661 output: Image 1 (fdt-1)
223 12:20:29.963749 output: Description: mt8192-asurada-spherion-r0
224 12:20:29.963835 output: Created: Wed Aug 16 13:20:29 2023
225 12:20:29.963924 output: Type: Flat Device Tree
226 12:20:29.964009 output: Compression: uncompressed
227 12:20:29.964105 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:20:29.964202 output: Architecture: AArch64
229 12:20:29.964298 output: Hash algo: crc32
230 12:20:29.964395 output: Hash value: cc4352de
231 12:20:29.964488 output: Image 2 (ramdisk-1)
232 12:20:29.964583 output: Description: unavailable
233 12:20:29.964675 output: Created: Wed Aug 16 13:20:29 2023
234 12:20:29.964776 output: Type: RAMDisk Image
235 12:20:29.964868 output: Compression: Unknown Compression
236 12:20:29.964959 output: Data Size: 39341352 Bytes = 38419.29 KiB = 37.52 MiB
237 12:20:29.965049 output: Architecture: AArch64
238 12:20:29.965141 output: OS: Linux
239 12:20:29.965244 output: Load Address: unavailable
240 12:20:29.965340 output: Entry Point: unavailable
241 12:20:29.965431 output: Hash algo: crc32
242 12:20:29.965519 output: Hash value: e3430e8f
243 12:20:29.965605 output: Default Configuration: 'conf-1'
244 12:20:29.965696 output: Configuration 0 (conf-1)
245 12:20:29.965783 output: Description: mt8192-asurada-spherion-r0
246 12:20:29.965871 output: Kernel: kernel-1
247 12:20:29.965961 output: Init Ramdisk: ramdisk-1
248 12:20:29.966049 output: FDT: fdt-1
249 12:20:29.966139 output: Loadables: kernel-1
250 12:20:29.966225 output:
251 12:20:29.966465 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:20:29.966596 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:20:29.966734 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 12:20:29.966865 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 12:20:29.966974 No LXC device requested
256 12:20:29.967094 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:20:29.967223 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 12:20:29.967356 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:20:29.967463 Checking files for TFTP limit of 4294967296 bytes.
260 12:20:29.968120 end: 1 tftp-deploy (duration 00:00:21) [common]
261 12:20:29.968255 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:20:29.968382 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:20:29.968550 substitutions:
264 12:20:29.968647 - {DTB}: 11299277/tftp-deploy-4sizsku6/dtb/mt8192-asurada-spherion-r0.dtb
265 12:20:29.968749 - {INITRD}: 11299277/tftp-deploy-4sizsku6/ramdisk/ramdisk.cpio.gz
266 12:20:29.968849 - {KERNEL}: 11299277/tftp-deploy-4sizsku6/kernel/Image
267 12:20:29.968943 - {LAVA_MAC}: None
268 12:20:29.969038 - {PRESEED_CONFIG}: None
269 12:20:29.969132 - {PRESEED_LOCAL}: None
270 12:20:29.969221 - {RAMDISK}: 11299277/tftp-deploy-4sizsku6/ramdisk/ramdisk.cpio.gz
271 12:20:29.969314 - {ROOT_PART}: None
272 12:20:29.969406 - {ROOT}: None
273 12:20:29.969496 - {SERVER_IP}: 192.168.201.1
274 12:20:29.969587 - {TEE}: None
275 12:20:29.969674 Parsed boot commands:
276 12:20:29.969745 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:20:29.969940 Parsed boot commands: tftpboot 192.168.201.1 11299277/tftp-deploy-4sizsku6/kernel/image.itb 11299277/tftp-deploy-4sizsku6/kernel/cmdline
278 12:20:29.970068 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:20:29.970198 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:20:29.970328 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:20:29.970459 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:20:29.970566 Not connected, no need to disconnect.
283 12:20:29.970679 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:20:29.970801 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:20:29.970905 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 12:20:29.974518 Setting prompt string to ['lava-test: # ']
287 12:20:29.974904 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:20:29.975045 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:20:29.975184 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:20:29.975320 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:20:29.975664 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 12:20:35.111447 >> Command sent successfully.
293 12:20:35.114381 Returned 0 in 5 seconds
294 12:20:35.214781 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:20:35.215283 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:20:35.215457 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:20:35.215592 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:20:35.215697 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:20:35.215816 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:20:35.216210 [Enter `^Ec?' for help]
302 12:20:35.390616
303 12:20:35.390785
304 12:20:35.390884 F0: 102B 0000
305 12:20:35.390955
306 12:20:35.391023 F3: 1001 0000 [0200]
307 12:20:35.391085
308 12:20:35.394017 F3: 1001 0000
309 12:20:35.394104
310 12:20:35.394174 F7: 102D 0000
311 12:20:35.394239
312 12:20:35.394300 F1: 0000 0000
313 12:20:35.394360
314 12:20:35.397895 V0: 0000 0000 [0001]
315 12:20:35.397982
316 12:20:35.398049 00: 0007 8000
317 12:20:35.398119
318 12:20:35.401561 01: 0000 0000
319 12:20:35.401648
320 12:20:35.401716 BP: 0C00 0209 [0000]
321 12:20:35.401780
322 12:20:35.405475 G0: 1182 0000
323 12:20:35.405561
324 12:20:35.405632 EC: 0000 0021 [4000]
325 12:20:35.405696
326 12:20:35.408898 S7: 0000 0000 [0000]
327 12:20:35.408984
328 12:20:35.409051 CC: 0000 0000 [0001]
329 12:20:35.409114
330 12:20:35.411853 T0: 0000 0040 [010F]
331 12:20:35.411969
332 12:20:35.412070 Jump to BL
333 12:20:35.412161
334 12:20:35.437531
335 12:20:35.437621
336 12:20:35.437689
337 12:20:35.444666 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:20:35.448205 ARM64: Exception handlers installed.
339 12:20:35.452058 ARM64: Testing exception
340 12:20:35.455823 ARM64: Done test exception
341 12:20:35.462605 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:20:35.469939 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:20:35.477405 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:20:35.487754 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:20:35.494807 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:20:35.504777 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:20:35.515233 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:20:35.522067 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:20:35.540390 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:20:35.543623 WDT: Last reset was cold boot
351 12:20:35.546914 SPI1(PAD0) initialized at 2873684 Hz
352 12:20:35.550124 SPI5(PAD0) initialized at 992727 Hz
353 12:20:35.553356 VBOOT: Loading verstage.
354 12:20:35.560151 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:20:35.563250 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:20:35.566643 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:20:35.570000 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:20:35.577337 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:20:35.584305 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:20:35.595043 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:20:35.595163
362 12:20:35.595233
363 12:20:35.605122 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:20:35.608560 ARM64: Exception handlers installed.
365 12:20:35.611382 ARM64: Testing exception
366 12:20:35.611495 ARM64: Done test exception
367 12:20:35.618390 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:20:35.621710 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:20:35.635704 Probing TPM: . done!
370 12:20:35.635793 TPM ready after 0 ms
371 12:20:35.642568 Connected to device vid:did:rid of 1ae0:0028:00
372 12:20:35.650494 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:20:35.708620 Initialized TPM device CR50 revision 0
374 12:20:35.719061 tlcl_send_startup: Startup return code is 0
375 12:20:35.719162 TPM: setup succeeded
376 12:20:35.730558 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:20:35.739223 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:20:35.749195 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:20:35.758581 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:20:35.762393 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:20:35.768393 in-header: 03 07 00 00 08 00 00 00
382 12:20:35.772159 in-data: aa e4 47 04 13 02 00 00
383 12:20:35.775903 Chrome EC: UHEPI supported
384 12:20:35.782832 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:20:35.786740 in-header: 03 ad 00 00 08 00 00 00
386 12:20:35.790212 in-data: 00 20 20 08 00 00 00 00
387 12:20:35.790299 Phase 1
388 12:20:35.793973 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:20:35.801270 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:20:35.804872 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:20:35.808793 Recovery requested (1009000e)
392 12:20:35.817937 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:20:35.823208 tlcl_extend: response is 0
394 12:20:35.832897 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:20:35.838330 tlcl_extend: response is 0
396 12:20:35.845181 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:20:35.865968 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:20:35.872909 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:20:35.872998
400 12:20:35.873066
401 12:20:35.882846 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:20:35.885844 ARM64: Exception handlers installed.
403 12:20:35.885946 ARM64: Testing exception
404 12:20:35.889335 ARM64: Done test exception
405 12:20:35.910700 pmic_efuse_setting: Set efuses in 11 msecs
406 12:20:35.914214 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:20:35.920596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:20:35.924308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:20:35.931374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:20:35.934217 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:20:35.937571 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:20:35.944973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:20:35.948688 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:20:35.953039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:20:35.956815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:20:35.964224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:20:35.968045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:20:35.971653 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:20:35.978090 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:20:35.981173 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:20:35.987943 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:20:35.994955 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:20:35.998871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:20:36.006258 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:20:36.010030 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:20:36.016738 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:20:36.023487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:20:36.027183 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:20:36.033804 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:20:36.040692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:20:36.043650 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:20:36.050455 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:20:36.053858 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:20:36.060942 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:20:36.063773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:20:36.070835 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:20:36.074056 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:20:36.080534 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:20:36.084110 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:20:36.091012 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:20:36.093920 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:20:36.100865 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:20:36.104351 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:20:36.111131 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:20:36.114259 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:20:36.117692 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:20:36.124357 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:20:36.127778 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:20:36.131177 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:20:36.138031 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:20:36.141740 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:20:36.145596 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:20:36.148936 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:20:36.152296 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:20:36.158666 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:20:36.162029 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:20:36.165497 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:20:36.172115 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:20:36.181975 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:20:36.185680 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:20:36.195447 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:20:36.202613 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:20:36.208787 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:20:36.212156 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:20:36.215531 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:20:36.223482 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1c
467 12:20:36.230319 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:20:36.233347 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:20:36.236738 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:20:36.248107 [RTC]rtc_get_frequency_meter,154: input=15, output=773
471 12:20:36.258248 [RTC]rtc_get_frequency_meter,154: input=23, output=958
472 12:20:36.266815 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 12:20:36.276465 [RTC]rtc_get_frequency_meter,154: input=17, output=817
474 12:20:36.286315 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 12:20:36.289459 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 12:20:36.296350 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 12:20:36.299679 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 12:20:36.302816 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 12:20:36.306229 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 12:20:36.309592 ADC[4]: Raw value=902139 ID=7
481 12:20:36.312987 ADC[3]: Raw value=213179 ID=1
482 12:20:36.313068 RAM Code: 0x71
483 12:20:36.319841 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 12:20:36.323145 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 12:20:36.333091 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 12:20:36.339416 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 12:20:36.342643 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 12:20:36.346403 in-header: 03 07 00 00 08 00 00 00
489 12:20:36.349385 in-data: aa e4 47 04 13 02 00 00
490 12:20:36.352697 Chrome EC: UHEPI supported
491 12:20:36.359452 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 12:20:36.362779 in-header: 03 ed 00 00 08 00 00 00
493 12:20:36.366115 in-data: 80 20 60 08 00 00 00 00
494 12:20:36.369481 MRC: failed to locate region type 0.
495 12:20:36.376239 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 12:20:36.379674 DRAM-K: Running full calibration
497 12:20:36.386731 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 12:20:36.386871 header.status = 0x0
499 12:20:36.389827 header.version = 0x6 (expected: 0x6)
500 12:20:36.392857 header.size = 0xd00 (expected: 0xd00)
501 12:20:36.396200 header.flags = 0x0
502 12:20:36.403256 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 12:20:36.418926 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
504 12:20:36.425918 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 12:20:36.429063 dram_init: ddr_geometry: 2
506 12:20:36.432069 [EMI] MDL number = 2
507 12:20:36.432175 [EMI] Get MDL freq = 0
508 12:20:36.435901 dram_init: ddr_type: 0
509 12:20:36.436031 is_discrete_lpddr4: 1
510 12:20:36.439122 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 12:20:36.439194
512 12:20:36.439263
513 12:20:36.442373 [Bian_co] ETT version 0.0.0.1
514 12:20:36.448982 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 12:20:36.449074
516 12:20:36.452379 dramc_set_vcore_voltage set vcore to 650000
517 12:20:36.452523 Read voltage for 800, 4
518 12:20:36.455687 Vio18 = 0
519 12:20:36.455817 Vcore = 650000
520 12:20:36.455934 Vdram = 0
521 12:20:36.458950 Vddq = 0
522 12:20:36.459085 Vmddr = 0
523 12:20:36.462276 dram_init: config_dvfs: 1
524 12:20:36.465864 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 12:20:36.472352 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 12:20:36.475821 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 12:20:36.479074 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 12:20:36.482395 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 12:20:36.485696 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 12:20:36.489574 MEM_TYPE=3, freq_sel=18
531 12:20:36.493045 sv_algorithm_assistance_LP4_1600
532 12:20:36.497152 ============ PULL DRAM RESETB DOWN ============
533 12:20:36.500644 ========== PULL DRAM RESETB DOWN end =========
534 12:20:36.504170 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 12:20:36.508245 ===================================
536 12:20:36.511955 LPDDR4 DRAM CONFIGURATION
537 12:20:36.515387 ===================================
538 12:20:36.515487 EX_ROW_EN[0] = 0x0
539 12:20:36.519199 EX_ROW_EN[1] = 0x0
540 12:20:36.519295 LP4Y_EN = 0x0
541 12:20:36.523018 WORK_FSP = 0x0
542 12:20:36.523114 WL = 0x2
543 12:20:36.526713 RL = 0x2
544 12:20:36.526807 BL = 0x2
545 12:20:36.526900 RPST = 0x0
546 12:20:36.530666 RD_PRE = 0x0
547 12:20:36.530761 WR_PRE = 0x1
548 12:20:36.534342 WR_PST = 0x0
549 12:20:36.534437 DBI_WR = 0x0
550 12:20:36.537586 DBI_RD = 0x0
551 12:20:36.537679 OTF = 0x1
552 12:20:36.540986 ===================================
553 12:20:36.544867 ===================================
554 12:20:36.548641 ANA top config
555 12:20:36.548767 ===================================
556 12:20:36.552151 DLL_ASYNC_EN = 0
557 12:20:36.555509 ALL_SLAVE_EN = 1
558 12:20:36.558669 NEW_RANK_MODE = 1
559 12:20:36.558761 DLL_IDLE_MODE = 1
560 12:20:36.562021 LP45_APHY_COMB_EN = 1
561 12:20:36.565284 TX_ODT_DIS = 1
562 12:20:36.568767 NEW_8X_MODE = 1
563 12:20:36.571847 ===================================
564 12:20:36.575286 ===================================
565 12:20:36.578657 data_rate = 1600
566 12:20:36.578749 CKR = 1
567 12:20:36.581911 DQ_P2S_RATIO = 8
568 12:20:36.585291 ===================================
569 12:20:36.589033 CA_P2S_RATIO = 8
570 12:20:36.591896 DQ_CA_OPEN = 0
571 12:20:36.595743 DQ_SEMI_OPEN = 0
572 12:20:36.598806 CA_SEMI_OPEN = 0
573 12:20:36.598898 CA_FULL_RATE = 0
574 12:20:36.602393 DQ_CKDIV4_EN = 1
575 12:20:36.606047 CA_CKDIV4_EN = 1
576 12:20:36.609583 CA_PREDIV_EN = 0
577 12:20:36.613202 PH8_DLY = 0
578 12:20:36.613295 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 12:20:36.616938 DQ_AAMCK_DIV = 4
580 12:20:36.620881 CA_AAMCK_DIV = 4
581 12:20:36.620965 CA_ADMCK_DIV = 4
582 12:20:36.624667 DQ_TRACK_CA_EN = 0
583 12:20:36.628448 CA_PICK = 800
584 12:20:36.632072 CA_MCKIO = 800
585 12:20:36.632161 MCKIO_SEMI = 0
586 12:20:36.635243 PLL_FREQ = 3068
587 12:20:36.638651 DQ_UI_PI_RATIO = 32
588 12:20:36.642232 CA_UI_PI_RATIO = 0
589 12:20:36.645621 ===================================
590 12:20:36.648507 ===================================
591 12:20:36.651911 memory_type:LPDDR4
592 12:20:36.652042 GP_NUM : 10
593 12:20:36.655234 SRAM_EN : 1
594 12:20:36.658786 MD32_EN : 0
595 12:20:36.662285 ===================================
596 12:20:36.662379 [ANA_INIT] >>>>>>>>>>>>>>
597 12:20:36.666119 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 12:20:36.670112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:20:36.674139 ===================================
600 12:20:36.674238 data_rate = 1600,PCW = 0X7600
601 12:20:36.678063 ===================================
602 12:20:36.681768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 12:20:36.689572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 12:20:36.693343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 12:20:36.697388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 12:20:36.700472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 12:20:36.703605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 12:20:36.707182 [ANA_INIT] flow start
609 12:20:36.707274 [ANA_INIT] PLL >>>>>>>>
610 12:20:36.710573 [ANA_INIT] PLL <<<<<<<<
611 12:20:36.713835 [ANA_INIT] MIDPI >>>>>>>>
612 12:20:36.717206 [ANA_INIT] MIDPI <<<<<<<<
613 12:20:36.717294 [ANA_INIT] DLL >>>>>>>>
614 12:20:36.720533 [ANA_INIT] flow end
615 12:20:36.724036 ============ LP4 DIFF to SE enter ============
616 12:20:36.727413 ============ LP4 DIFF to SE exit ============
617 12:20:36.730652 [ANA_INIT] <<<<<<<<<<<<<
618 12:20:36.733966 [Flow] Enable top DCM control >>>>>
619 12:20:36.737349 [Flow] Enable top DCM control <<<<<
620 12:20:36.740600 Enable DLL master slave shuffle
621 12:20:36.743975 ==============================================================
622 12:20:36.747324 Gating Mode config
623 12:20:36.753996 ==============================================================
624 12:20:36.754092 Config description:
625 12:20:36.764094 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 12:20:36.770873 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 12:20:36.777292 SELPH_MODE 0: By rank 1: By Phase
628 12:20:36.780657 ==============================================================
629 12:20:36.783924 GAT_TRACK_EN = 1
630 12:20:36.787565 RX_GATING_MODE = 2
631 12:20:36.790807 RX_GATING_TRACK_MODE = 2
632 12:20:36.794139 SELPH_MODE = 1
633 12:20:36.797609 PICG_EARLY_EN = 1
634 12:20:36.800709 VALID_LAT_VALUE = 1
635 12:20:36.804221 ==============================================================
636 12:20:36.807271 Enter into Gating configuration >>>>
637 12:20:36.810736 Exit from Gating configuration <<<<
638 12:20:36.814065 Enter into DVFS_PRE_config >>>>>
639 12:20:36.827556 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 12:20:36.827706 Exit from DVFS_PRE_config <<<<<
641 12:20:36.830890 Enter into PICG configuration >>>>
642 12:20:36.834375 Exit from PICG configuration <<<<
643 12:20:36.837655 [RX_INPUT] configuration >>>>>
644 12:20:36.841077 [RX_INPUT] configuration <<<<<
645 12:20:36.847382 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 12:20:36.851041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 12:20:36.857738 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 12:20:36.864521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 12:20:36.871045 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 12:20:36.877609 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 12:20:36.881060 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 12:20:36.884501 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 12:20:36.887894 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 12:20:36.891175 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 12:20:36.895067 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 12:20:36.901812 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 12:20:36.905355 ===================================
658 12:20:36.905445 LPDDR4 DRAM CONFIGURATION
659 12:20:36.908579 ===================================
660 12:20:36.911771 EX_ROW_EN[0] = 0x0
661 12:20:36.915203 EX_ROW_EN[1] = 0x0
662 12:20:36.915290 LP4Y_EN = 0x0
663 12:20:36.918798 WORK_FSP = 0x0
664 12:20:36.918920 WL = 0x2
665 12:20:36.921816 RL = 0x2
666 12:20:36.921927 BL = 0x2
667 12:20:36.925446 RPST = 0x0
668 12:20:36.925534 RD_PRE = 0x0
669 12:20:36.928695 WR_PRE = 0x1
670 12:20:36.928836 WR_PST = 0x0
671 12:20:36.931937 DBI_WR = 0x0
672 12:20:36.932049 DBI_RD = 0x0
673 12:20:36.935645 OTF = 0x1
674 12:20:36.938831 ===================================
675 12:20:36.942216 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 12:20:36.945425 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 12:20:36.952082 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 12:20:36.952199 ===================================
679 12:20:36.955410 LPDDR4 DRAM CONFIGURATION
680 12:20:36.959040 ===================================
681 12:20:36.962382 EX_ROW_EN[0] = 0x10
682 12:20:36.962468 EX_ROW_EN[1] = 0x0
683 12:20:36.965365 LP4Y_EN = 0x0
684 12:20:36.965442 WORK_FSP = 0x0
685 12:20:36.968972 WL = 0x2
686 12:20:36.969047 RL = 0x2
687 12:20:36.972244 BL = 0x2
688 12:20:36.972347 RPST = 0x0
689 12:20:36.975519 RD_PRE = 0x0
690 12:20:36.979104 WR_PRE = 0x1
691 12:20:36.979211 WR_PST = 0x0
692 12:20:36.982290 DBI_WR = 0x0
693 12:20:36.982370 DBI_RD = 0x0
694 12:20:36.985644 OTF = 0x1
695 12:20:36.988885 ===================================
696 12:20:36.992287 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 12:20:36.997559 nWR fixed to 40
698 12:20:37.000950 [ModeRegInit_LP4] CH0 RK0
699 12:20:37.001041 [ModeRegInit_LP4] CH0 RK1
700 12:20:37.004322 [ModeRegInit_LP4] CH1 RK0
701 12:20:37.007487 [ModeRegInit_LP4] CH1 RK1
702 12:20:37.007572 match AC timing 13
703 12:20:37.014132 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 12:20:37.017277 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 12:20:37.020733 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 12:20:37.027551 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 12:20:37.030719 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 12:20:37.030853 [EMI DOE] emi_dcm 0
709 12:20:37.037292 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 12:20:37.037423 ==
711 12:20:37.040789 Dram Type= 6, Freq= 0, CH_0, rank 0
712 12:20:37.044023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 12:20:37.044148 ==
714 12:20:37.050972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 12:20:37.057410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 12:20:37.065413 [CA 0] Center 37 (7~68) winsize 62
717 12:20:37.069305 [CA 1] Center 38 (7~69) winsize 63
718 12:20:37.072845 [CA 2] Center 35 (5~66) winsize 62
719 12:20:37.076431 [CA 3] Center 35 (5~66) winsize 62
720 12:20:37.080032 [CA 4] Center 34 (4~65) winsize 62
721 12:20:37.083759 [CA 5] Center 33 (3~64) winsize 62
722 12:20:37.083847
723 12:20:37.087506 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 12:20:37.087594
725 12:20:37.090849 [CATrainingPosCal] consider 1 rank data
726 12:20:37.090935 u2DelayCellTimex100 = 270/100 ps
727 12:20:37.094454 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
728 12:20:37.098580 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 12:20:37.105424 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 12:20:37.105536 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 12:20:37.109533 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 12:20:37.112907 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 12:20:37.112989
734 12:20:37.120367 CA PerBit enable=1, Macro0, CA PI delay=33
735 12:20:37.120484
736 12:20:37.120590 [CBTSetCACLKResult] CA Dly = 33
737 12:20:37.123875 CS Dly: 5 (0~36)
738 12:20:37.123958 ==
739 12:20:37.127826 Dram Type= 6, Freq= 0, CH_0, rank 1
740 12:20:37.131676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 12:20:37.131762 ==
742 12:20:37.135211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 12:20:37.141785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 12:20:37.152236 [CA 0] Center 38 (7~69) winsize 63
745 12:20:37.155663 [CA 1] Center 38 (8~69) winsize 62
746 12:20:37.159287 [CA 2] Center 36 (6~67) winsize 62
747 12:20:37.163035 [CA 3] Center 35 (5~66) winsize 62
748 12:20:37.167005 [CA 4] Center 35 (4~66) winsize 63
749 12:20:37.167138 [CA 5] Center 34 (4~65) winsize 62
750 12:20:37.167258
751 12:20:37.170821 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 12:20:37.174691
753 12:20:37.174773 [CATrainingPosCal] consider 2 rank data
754 12:20:37.178180 u2DelayCellTimex100 = 270/100 ps
755 12:20:37.182194 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
756 12:20:37.185629 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 12:20:37.189347 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 12:20:37.193249 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 12:20:37.196521 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 12:20:37.200687 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 12:20:37.200801
762 12:20:37.204565 CA PerBit enable=1, Macro0, CA PI delay=34
763 12:20:37.204677
764 12:20:37.208144 [CBTSetCACLKResult] CA Dly = 34
765 12:20:37.208259 CS Dly: 6 (0~38)
766 12:20:37.208365
767 12:20:37.212238 ----->DramcWriteLeveling(PI) begin...
768 12:20:37.212326 ==
769 12:20:37.215981 Dram Type= 6, Freq= 0, CH_0, rank 0
770 12:20:37.219020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 12:20:37.222689 ==
772 12:20:37.222779 Write leveling (Byte 0): 30 => 30
773 12:20:37.226482 Write leveling (Byte 1): 29 => 29
774 12:20:37.229917 DramcWriteLeveling(PI) end<-----
775 12:20:37.230004
776 12:20:37.230074 ==
777 12:20:37.233861 Dram Type= 6, Freq= 0, CH_0, rank 0
778 12:20:37.237868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 12:20:37.237956 ==
780 12:20:37.241450 [Gating] SW mode calibration
781 12:20:37.248536 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 12:20:37.252613 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 12:20:37.256302 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 12:20:37.263717 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
785 12:20:37.267441 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 12:20:37.271137 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:20:37.274501 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:20:37.278149 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:20:37.282235 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:20:37.289795 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:20:37.293552 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:20:37.296962 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:20:37.300852 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:20:37.304966 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:20:37.308585 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:20:37.315789 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:20:37.319865 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:20:37.323169 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:20:37.326748 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:20:37.330539 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
801 12:20:37.337811 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 12:20:37.341356 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:20:37.345045 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:20:37.348826 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:20:37.352728 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:20:37.359775 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:20:37.363634 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:20:37.367767 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:20:37.371419 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
810 12:20:37.374711 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
811 12:20:37.381354 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:20:37.384527 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:20:37.388043 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 12:20:37.394692 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:20:37.398119 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:20:37.401332 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
817 12:20:37.408244 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
818 12:20:37.411564 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
819 12:20:37.414902 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:20:37.421245 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:20:37.424929 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:20:37.428048 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:20:37.431457 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:20:37.438263 0 11 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
825 12:20:37.441846 0 11 8 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
826 12:20:37.444779 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
827 12:20:37.451397 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:20:37.454818 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:20:37.458185 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 12:20:37.464972 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:20:37.468320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:20:37.471572 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
833 12:20:37.478285 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 12:20:37.481609 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:20:37.484891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:20:37.491683 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:20:37.494940 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:20:37.498708 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:20:37.501942 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:20:37.508575 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:20:37.511913 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:20:37.515251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:20:37.521810 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:20:37.525144 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:20:37.528454 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:20:37.535216 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:20:37.538236 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:20:37.541498 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 12:20:37.548170 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:20:37.548250 Total UI for P1: 0, mck2ui 16
851 12:20:37.555350 best dqsien dly found for B0: ( 0, 14, 4)
852 12:20:37.555462 Total UI for P1: 0, mck2ui 16
853 12:20:37.561602 best dqsien dly found for B1: ( 0, 14, 6)
854 12:20:37.565478 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
855 12:20:37.568636 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
856 12:20:37.568739
857 12:20:37.571957 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
858 12:20:37.575618 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
859 12:20:37.578467 [Gating] SW calibration Done
860 12:20:37.578551 ==
861 12:20:37.581856 Dram Type= 6, Freq= 0, CH_0, rank 0
862 12:20:37.585566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 12:20:37.585677 ==
864 12:20:37.585773 RX Vref Scan: 0
865 12:20:37.588837
866 12:20:37.588922 RX Vref 0 -> 0, step: 1
867 12:20:37.588989
868 12:20:37.592029 RX Delay -130 -> 252, step: 16
869 12:20:37.595644 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
870 12:20:37.599048 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 12:20:37.605371 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
872 12:20:37.608584 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
873 12:20:37.612374 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
874 12:20:37.615561 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 12:20:37.618888 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 12:20:37.625799 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 12:20:37.629011 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 12:20:37.632261 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
879 12:20:37.635801 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
880 12:20:37.638938 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 12:20:37.645549 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
882 12:20:37.648998 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 12:20:37.652554 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 12:20:37.655858 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
885 12:20:37.655970 ==
886 12:20:37.659083 Dram Type= 6, Freq= 0, CH_0, rank 0
887 12:20:37.665551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 12:20:37.665662 ==
889 12:20:37.665771 DQS Delay:
890 12:20:37.665875 DQS0 = 0, DQS1 = 0
891 12:20:37.668695 DQM Delay:
892 12:20:37.668814 DQM0 = 93, DQM1 = 82
893 12:20:37.672080 DQ Delay:
894 12:20:37.675487 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
895 12:20:37.678698 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
896 12:20:37.682297 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
897 12:20:37.685453 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
898 12:20:37.685584
899 12:20:37.685716
900 12:20:37.685833 ==
901 12:20:37.688720 Dram Type= 6, Freq= 0, CH_0, rank 0
902 12:20:37.692478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 12:20:37.692566 ==
904 12:20:37.692635
905 12:20:37.692700
906 12:20:37.695645 TX Vref Scan disable
907 12:20:37.695731 == TX Byte 0 ==
908 12:20:37.702375 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
909 12:20:37.705402 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
910 12:20:37.705489 == TX Byte 1 ==
911 12:20:37.712512 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
912 12:20:37.715836 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
913 12:20:37.715923 ==
914 12:20:37.719038 Dram Type= 6, Freq= 0, CH_0, rank 0
915 12:20:37.722483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 12:20:37.722572 ==
917 12:20:37.736269 TX Vref=22, minBit 11, minWin=26, winSum=437
918 12:20:37.739574 TX Vref=24, minBit 5, minWin=27, winSum=441
919 12:20:37.742707 TX Vref=26, minBit 6, minWin=27, winSum=447
920 12:20:37.746219 TX Vref=28, minBit 5, minWin=27, winSum=449
921 12:20:37.749469 TX Vref=30, minBit 6, minWin=27, winSum=451
922 12:20:37.756121 TX Vref=32, minBit 12, minWin=27, winSum=449
923 12:20:37.759672 [TxChooseVref] Worse bit 6, Min win 27, Win sum 451, Final Vref 30
924 12:20:37.759801
925 12:20:37.762971 Final TX Range 1 Vref 30
926 12:20:37.763096
927 12:20:37.763209 ==
928 12:20:37.766252 Dram Type= 6, Freq= 0, CH_0, rank 0
929 12:20:37.769544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 12:20:37.769669 ==
931 12:20:37.769787
932 12:20:37.772902
933 12:20:37.773030 TX Vref Scan disable
934 12:20:37.776104 == TX Byte 0 ==
935 12:20:37.779417 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 12:20:37.782705 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 12:20:37.786261 == TX Byte 1 ==
938 12:20:37.789378 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
939 12:20:37.792730 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
940 12:20:37.796058
941 12:20:37.796141 [DATLAT]
942 12:20:37.796208 Freq=800, CH0 RK0
943 12:20:37.796271
944 12:20:37.799299 DATLAT Default: 0xa
945 12:20:37.799382 0, 0xFFFF, sum = 0
946 12:20:37.802977 1, 0xFFFF, sum = 0
947 12:20:37.803062 2, 0xFFFF, sum = 0
948 12:20:37.806092 3, 0xFFFF, sum = 0
949 12:20:37.806179 4, 0xFFFF, sum = 0
950 12:20:37.809590 5, 0xFFFF, sum = 0
951 12:20:37.809719 6, 0xFFFF, sum = 0
952 12:20:37.813067 7, 0xFFFF, sum = 0
953 12:20:37.816379 8, 0xFFFF, sum = 0
954 12:20:37.816501 9, 0x0, sum = 1
955 12:20:37.816612 10, 0x0, sum = 2
956 12:20:37.819643 11, 0x0, sum = 3
957 12:20:37.819767 12, 0x0, sum = 4
958 12:20:37.822928 best_step = 10
959 12:20:37.823050
960 12:20:37.823160 ==
961 12:20:37.826257 Dram Type= 6, Freq= 0, CH_0, rank 0
962 12:20:37.830042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 12:20:37.830163 ==
964 12:20:37.833413 RX Vref Scan: 1
965 12:20:37.833534
966 12:20:37.833644 Set Vref Range= 32 -> 127
967 12:20:37.833756
968 12:20:37.836651 RX Vref 32 -> 127, step: 1
969 12:20:37.836803
970 12:20:37.839906 RX Delay -79 -> 252, step: 8
971 12:20:37.840023
972 12:20:37.843296 Set Vref, RX VrefLevel [Byte0]: 32
973 12:20:37.846458 [Byte1]: 32
974 12:20:37.846584
975 12:20:37.849607 Set Vref, RX VrefLevel [Byte0]: 33
976 12:20:37.853226 [Byte1]: 33
977 12:20:37.856541
978 12:20:37.856667 Set Vref, RX VrefLevel [Byte0]: 34
979 12:20:37.859470 [Byte1]: 34
980 12:20:37.863680
981 12:20:37.863799 Set Vref, RX VrefLevel [Byte0]: 35
982 12:20:37.867273 [Byte1]: 35
983 12:20:37.871416
984 12:20:37.871539 Set Vref, RX VrefLevel [Byte0]: 36
985 12:20:37.874934 [Byte1]: 36
986 12:20:37.879099
987 12:20:37.879221 Set Vref, RX VrefLevel [Byte0]: 37
988 12:20:37.882249 [Byte1]: 37
989 12:20:37.886386
990 12:20:37.886507 Set Vref, RX VrefLevel [Byte0]: 38
991 12:20:37.889681 [Byte1]: 38
992 12:20:37.894128
993 12:20:37.894250 Set Vref, RX VrefLevel [Byte0]: 39
994 12:20:37.897454 [Byte1]: 39
995 12:20:37.901693
996 12:20:37.901818 Set Vref, RX VrefLevel [Byte0]: 40
997 12:20:37.904918 [Byte1]: 40
998 12:20:37.909271
999 12:20:37.909404 Set Vref, RX VrefLevel [Byte0]: 41
1000 12:20:37.912900 [Byte1]: 41
1001 12:20:37.916825
1002 12:20:37.916949 Set Vref, RX VrefLevel [Byte0]: 42
1003 12:20:37.920087 [Byte1]: 42
1004 12:20:37.924232
1005 12:20:37.924353 Set Vref, RX VrefLevel [Byte0]: 43
1006 12:20:37.927971 [Byte1]: 43
1007 12:20:37.932038
1008 12:20:37.932161 Set Vref, RX VrefLevel [Byte0]: 44
1009 12:20:37.935374 [Byte1]: 44
1010 12:20:37.939551
1011 12:20:37.939674 Set Vref, RX VrefLevel [Byte0]: 45
1012 12:20:37.942774 [Byte1]: 45
1013 12:20:37.946969
1014 12:20:37.947091 Set Vref, RX VrefLevel [Byte0]: 46
1015 12:20:37.950494 [Byte1]: 46
1016 12:20:37.954513
1017 12:20:37.954635 Set Vref, RX VrefLevel [Byte0]: 47
1018 12:20:37.957545 [Byte1]: 47
1019 12:20:37.961925
1020 12:20:37.962047 Set Vref, RX VrefLevel [Byte0]: 48
1021 12:20:37.965096 [Byte1]: 48
1022 12:20:37.969384
1023 12:20:37.969503 Set Vref, RX VrefLevel [Byte0]: 49
1024 12:20:37.972714 [Byte1]: 49
1025 12:20:37.976875
1026 12:20:37.976990 Set Vref, RX VrefLevel [Byte0]: 50
1027 12:20:37.980451 [Byte1]: 50
1028 12:20:37.984508
1029 12:20:37.984626 Set Vref, RX VrefLevel [Byte0]: 51
1030 12:20:37.987725 [Byte1]: 51
1031 12:20:37.991946
1032 12:20:37.992023 Set Vref, RX VrefLevel [Byte0]: 52
1033 12:20:37.995543 [Byte1]: 52
1034 12:20:37.999572
1035 12:20:37.999650 Set Vref, RX VrefLevel [Byte0]: 53
1036 12:20:38.002895 [Byte1]: 53
1037 12:20:38.007291
1038 12:20:38.007380 Set Vref, RX VrefLevel [Byte0]: 54
1039 12:20:38.010555 [Byte1]: 54
1040 12:20:38.015115
1041 12:20:38.015214 Set Vref, RX VrefLevel [Byte0]: 55
1042 12:20:38.018329 [Byte1]: 55
1043 12:20:38.022517
1044 12:20:38.022600 Set Vref, RX VrefLevel [Byte0]: 56
1045 12:20:38.025836 [Byte1]: 56
1046 12:20:38.029986
1047 12:20:38.030068 Set Vref, RX VrefLevel [Byte0]: 57
1048 12:20:38.033145 [Byte1]: 57
1049 12:20:38.037367
1050 12:20:38.037450 Set Vref, RX VrefLevel [Byte0]: 58
1051 12:20:38.040716 [Byte1]: 58
1052 12:20:38.045294
1053 12:20:38.045408 Set Vref, RX VrefLevel [Byte0]: 59
1054 12:20:38.048255 [Byte1]: 59
1055 12:20:38.052384
1056 12:20:38.052468 Set Vref, RX VrefLevel [Byte0]: 60
1057 12:20:38.055639 [Byte1]: 60
1058 12:20:38.060095
1059 12:20:38.060178 Set Vref, RX VrefLevel [Byte0]: 61
1060 12:20:38.063343 [Byte1]: 61
1061 12:20:38.067582
1062 12:20:38.067708 Set Vref, RX VrefLevel [Byte0]: 62
1063 12:20:38.071054 [Byte1]: 62
1064 12:20:38.075184
1065 12:20:38.075287 Set Vref, RX VrefLevel [Byte0]: 63
1066 12:20:38.078616 [Byte1]: 63
1067 12:20:38.082695
1068 12:20:38.082778 Set Vref, RX VrefLevel [Byte0]: 64
1069 12:20:38.086086 [Byte1]: 64
1070 12:20:38.090489
1071 12:20:38.090572 Set Vref, RX VrefLevel [Byte0]: 65
1072 12:20:38.093746 [Byte1]: 65
1073 12:20:38.097687
1074 12:20:38.097771 Set Vref, RX VrefLevel [Byte0]: 66
1075 12:20:38.101331 [Byte1]: 66
1076 12:20:38.105196
1077 12:20:38.105279 Set Vref, RX VrefLevel [Byte0]: 67
1078 12:20:38.108755 [Byte1]: 67
1079 12:20:38.112917
1080 12:20:38.113029 Set Vref, RX VrefLevel [Byte0]: 68
1081 12:20:38.116309 [Byte1]: 68
1082 12:20:38.120641
1083 12:20:38.120726 Set Vref, RX VrefLevel [Byte0]: 69
1084 12:20:38.123901 [Byte1]: 69
1085 12:20:38.128000
1086 12:20:38.128083 Set Vref, RX VrefLevel [Byte0]: 70
1087 12:20:38.131490 [Byte1]: 70
1088 12:20:38.135929
1089 12:20:38.136012 Set Vref, RX VrefLevel [Byte0]: 71
1090 12:20:38.139166 [Byte1]: 71
1091 12:20:38.142949
1092 12:20:38.143032 Set Vref, RX VrefLevel [Byte0]: 72
1093 12:20:38.146537 [Byte1]: 72
1094 12:20:38.150848
1095 12:20:38.150974 Set Vref, RX VrefLevel [Byte0]: 73
1096 12:20:38.154055 [Byte1]: 73
1097 12:20:38.158125
1098 12:20:38.158246 Set Vref, RX VrefLevel [Byte0]: 74
1099 12:20:38.161644 [Byte1]: 74
1100 12:20:38.165902
1101 12:20:38.166037 Set Vref, RX VrefLevel [Byte0]: 75
1102 12:20:38.168908 [Byte1]: 75
1103 12:20:38.173261
1104 12:20:38.173384 Final RX Vref Byte 0 = 60 to rank0
1105 12:20:38.176497 Final RX Vref Byte 1 = 56 to rank0
1106 12:20:38.180072 Final RX Vref Byte 0 = 60 to rank1
1107 12:20:38.183055 Final RX Vref Byte 1 = 56 to rank1==
1108 12:20:38.186699 Dram Type= 6, Freq= 0, CH_0, rank 0
1109 12:20:38.193446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1110 12:20:38.193552 ==
1111 12:20:38.193645 DQS Delay:
1112 12:20:38.193734 DQS0 = 0, DQS1 = 0
1113 12:20:38.196937 DQM Delay:
1114 12:20:38.197018 DQM0 = 93, DQM1 = 82
1115 12:20:38.200176 DQ Delay:
1116 12:20:38.203205 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1117 12:20:38.203287 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1118 12:20:38.206656 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
1119 12:20:38.213504 DQ12 =84, DQ13 =84, DQ14 =96, DQ15 =88
1120 12:20:38.213586
1121 12:20:38.213651
1122 12:20:38.220124 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1123 12:20:38.223628 CH0 RK0: MR19=606, MR18=3D38
1124 12:20:38.230495 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1125 12:20:38.230577
1126 12:20:38.233231 ----->DramcWriteLeveling(PI) begin...
1127 12:20:38.233314 ==
1128 12:20:38.236827 Dram Type= 6, Freq= 0, CH_0, rank 1
1129 12:20:38.239972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 12:20:38.240054 ==
1131 12:20:38.243589 Write leveling (Byte 0): 31 => 31
1132 12:20:38.246959 Write leveling (Byte 1): 28 => 28
1133 12:20:38.250152 DramcWriteLeveling(PI) end<-----
1134 12:20:38.250233
1135 12:20:38.250298 ==
1136 12:20:38.253710 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 12:20:38.256744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 12:20:38.256860 ==
1139 12:20:38.259939 [Gating] SW mode calibration
1140 12:20:38.266900 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1141 12:20:38.273425 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1142 12:20:38.276878 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1143 12:20:38.280136 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1144 12:20:38.286691 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1145 12:20:38.290310 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 12:20:38.293660 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 12:20:38.300256 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 12:20:38.303847 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 12:20:38.306886 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 12:20:38.310282 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 12:20:38.317268 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 12:20:38.361161 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 12:20:38.361517 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:20:38.361595 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:20:38.361663 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:20:38.361724 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:20:38.362072 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:20:38.362393 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:20:38.362463 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1160 12:20:38.362526 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1161 12:20:38.362586 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:20:38.405039 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:20:38.405394 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:20:38.405466 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:20:38.405529 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:20:38.405590 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:20:38.405955 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:20:38.406220 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1169 12:20:38.406324 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 12:20:38.406412 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 12:20:38.406475 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 12:20:38.440951 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 12:20:38.441228 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 12:20:38.441299 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 12:20:38.441362 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
1176 12:20:38.441816 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1177 12:20:38.442313 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:20:38.442683 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:20:38.442848 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:20:38.445398 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:20:38.448540 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:20:38.451981 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:20:38.455399 0 11 4 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
1184 12:20:38.462298 0 11 8 | B1->B0 | 3737 4545 | 0 1 | (1 1) (0 0)
1185 12:20:38.465350 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 12:20:38.468644 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 12:20:38.475407 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 12:20:38.478794 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 12:20:38.482174 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 12:20:38.488902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 12:20:38.492423 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1192 12:20:38.496105 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 12:20:38.500031 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 12:20:38.503842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 12:20:38.510849 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 12:20:38.514547 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 12:20:38.517405 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 12:20:38.521597 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:20:38.528575 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:20:38.531589 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:20:38.535085 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:20:38.542063 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:20:38.545104 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:20:38.548224 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:20:38.554791 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:20:38.558451 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:20:38.561590 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1208 12:20:38.568303 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 12:20:38.568386 Total UI for P1: 0, mck2ui 16
1210 12:20:38.574975 best dqsien dly found for B0: ( 0, 14, 4)
1211 12:20:38.575058 Total UI for P1: 0, mck2ui 16
1212 12:20:38.578449 best dqsien dly found for B1: ( 0, 14, 4)
1213 12:20:38.584703 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1214 12:20:38.588401 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1215 12:20:38.588484
1216 12:20:38.591574 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1217 12:20:38.594829 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1218 12:20:38.598617 [Gating] SW calibration Done
1219 12:20:38.598700 ==
1220 12:20:38.601571 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 12:20:38.605072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 12:20:38.605155 ==
1223 12:20:38.605221 RX Vref Scan: 0
1224 12:20:38.608280
1225 12:20:38.608362 RX Vref 0 -> 0, step: 1
1226 12:20:38.608458
1227 12:20:38.611610 RX Delay -130 -> 252, step: 16
1228 12:20:38.615146 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1229 12:20:38.618253 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1230 12:20:38.625226 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1231 12:20:38.628412 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1232 12:20:38.631500 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1233 12:20:38.635136 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1234 12:20:38.638201 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1235 12:20:38.645352 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1236 12:20:38.648324 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1237 12:20:38.651941 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1238 12:20:38.655132 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1239 12:20:38.658493 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1240 12:20:38.664872 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1241 12:20:38.668513 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1242 12:20:38.671727 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1243 12:20:38.675418 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1244 12:20:38.675537 ==
1245 12:20:38.678494 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 12:20:38.681946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1247 12:20:38.685142 ==
1248 12:20:38.685260 DQS Delay:
1249 12:20:38.685372 DQS0 = 0, DQS1 = 0
1250 12:20:38.688624 DQM Delay:
1251 12:20:38.688742 DQM0 = 90, DQM1 = 82
1252 12:20:38.692199 DQ Delay:
1253 12:20:38.692310 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =77
1254 12:20:38.695284 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
1255 12:20:38.698476 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1256 12:20:38.702463 DQ12 =93, DQ13 =85, DQ14 =93, DQ15 =93
1257 12:20:38.702546
1258 12:20:38.705250
1259 12:20:38.705332 ==
1260 12:20:38.708624 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 12:20:38.712216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 12:20:38.712301 ==
1263 12:20:38.712368
1264 12:20:38.712481
1265 12:20:38.715117 TX Vref Scan disable
1266 12:20:38.715200 == TX Byte 0 ==
1267 12:20:38.721768 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1268 12:20:38.725403 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1269 12:20:38.725485 == TX Byte 1 ==
1270 12:20:38.732137 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1271 12:20:38.735447 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1272 12:20:38.735534 ==
1273 12:20:38.738649 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 12:20:38.741680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 12:20:38.741763 ==
1276 12:20:38.755661 TX Vref=22, minBit 3, minWin=27, winSum=446
1277 12:20:38.759183 TX Vref=24, minBit 3, minWin=27, winSum=448
1278 12:20:38.762448 TX Vref=26, minBit 8, minWin=27, winSum=449
1279 12:20:38.765863 TX Vref=28, minBit 8, minWin=27, winSum=454
1280 12:20:38.769208 TX Vref=30, minBit 8, minWin=27, winSum=457
1281 12:20:38.772825 TX Vref=32, minBit 8, minWin=27, winSum=457
1282 12:20:38.779046 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
1283 12:20:38.779130
1284 12:20:38.782755 Final TX Range 1 Vref 30
1285 12:20:38.782839
1286 12:20:38.782904 ==
1287 12:20:38.786152 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 12:20:38.789095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 12:20:38.789178 ==
1290 12:20:38.789244
1291 12:20:38.789305
1292 12:20:38.792483 TX Vref Scan disable
1293 12:20:38.796062 == TX Byte 0 ==
1294 12:20:38.799147 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1295 12:20:38.802861 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1296 12:20:38.805836 == TX Byte 1 ==
1297 12:20:38.809430 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1298 12:20:38.812470 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1299 12:20:38.812551
1300 12:20:38.815835 [DATLAT]
1301 12:20:38.815916 Freq=800, CH0 RK1
1302 12:20:38.815980
1303 12:20:38.819357 DATLAT Default: 0xa
1304 12:20:38.819438 0, 0xFFFF, sum = 0
1305 12:20:38.822455 1, 0xFFFF, sum = 0
1306 12:20:38.822537 2, 0xFFFF, sum = 0
1307 12:20:38.826146 3, 0xFFFF, sum = 0
1308 12:20:38.826227 4, 0xFFFF, sum = 0
1309 12:20:38.829266 5, 0xFFFF, sum = 0
1310 12:20:38.829347 6, 0xFFFF, sum = 0
1311 12:20:38.832669 7, 0xFFFF, sum = 0
1312 12:20:38.832758 8, 0xFFFF, sum = 0
1313 12:20:38.835765 9, 0x0, sum = 1
1314 12:20:38.835846 10, 0x0, sum = 2
1315 12:20:38.839428 11, 0x0, sum = 3
1316 12:20:38.839511 12, 0x0, sum = 4
1317 12:20:38.842536 best_step = 10
1318 12:20:38.842617
1319 12:20:38.842679 ==
1320 12:20:38.845998 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 12:20:38.849433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 12:20:38.849514 ==
1323 12:20:38.852679 RX Vref Scan: 0
1324 12:20:38.852798
1325 12:20:38.852862 RX Vref 0 -> 0, step: 1
1326 12:20:38.852927
1327 12:20:38.856341 RX Delay -95 -> 252, step: 8
1328 12:20:38.862523 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1329 12:20:38.866012 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1330 12:20:38.869249 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1331 12:20:38.872977 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1332 12:20:38.876143 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1333 12:20:38.879317 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1334 12:20:38.886006 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1335 12:20:38.889450 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1336 12:20:38.892975 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1337 12:20:38.896293 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1338 12:20:38.899437 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1339 12:20:38.906116 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1340 12:20:38.909884 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1341 12:20:38.913186 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1342 12:20:38.916206 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1343 12:20:38.919651 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1344 12:20:38.922922 ==
1345 12:20:38.926437 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 12:20:38.929646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 12:20:38.929730 ==
1348 12:20:38.929795 DQS Delay:
1349 12:20:38.933157 DQS0 = 0, DQS1 = 0
1350 12:20:38.933239 DQM Delay:
1351 12:20:38.936576 DQM0 = 90, DQM1 = 82
1352 12:20:38.936658 DQ Delay:
1353 12:20:38.939585 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1354 12:20:38.943238 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1355 12:20:38.946485 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =80
1356 12:20:38.950020 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1357 12:20:38.950102
1358 12:20:38.950167
1359 12:20:38.956210 [DQSOSCAuto] RK1, (LSB)MR18= 0x441e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1360 12:20:38.959781 CH0 RK1: MR19=606, MR18=441E
1361 12:20:38.966507 CH0_RK1: MR19=0x606, MR18=0x441E, DQSOSC=392, MR23=63, INC=96, DEC=64
1362 12:20:38.969986 [RxdqsGatingPostProcess] freq 800
1363 12:20:38.972931 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1364 12:20:38.976306 Pre-setting of DQS Precalculation
1365 12:20:38.983208 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1366 12:20:38.983290 ==
1367 12:20:38.986613 Dram Type= 6, Freq= 0, CH_1, rank 0
1368 12:20:38.989656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 12:20:38.989739 ==
1370 12:20:38.996309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1371 12:20:39.002966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1372 12:20:39.010903 [CA 0] Center 36 (6~67) winsize 62
1373 12:20:39.014416 [CA 1] Center 36 (6~67) winsize 62
1374 12:20:39.017671 [CA 2] Center 35 (5~65) winsize 61
1375 12:20:39.020885 [CA 3] Center 34 (3~65) winsize 63
1376 12:20:39.024136 [CA 4] Center 34 (4~65) winsize 62
1377 12:20:39.027525 [CA 5] Center 34 (3~65) winsize 63
1378 12:20:39.027609
1379 12:20:39.031171 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1380 12:20:39.031254
1381 12:20:39.034326 [CATrainingPosCal] consider 1 rank data
1382 12:20:39.037821 u2DelayCellTimex100 = 270/100 ps
1383 12:20:39.041402 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1384 12:20:39.044114 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1385 12:20:39.051092 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1386 12:20:39.054324 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1387 12:20:39.057746 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1388 12:20:39.061177 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1389 12:20:39.061261
1390 12:20:39.064246 CA PerBit enable=1, Macro0, CA PI delay=34
1391 12:20:39.064329
1392 12:20:39.067455 [CBTSetCACLKResult] CA Dly = 34
1393 12:20:39.067565 CS Dly: 5 (0~36)
1394 12:20:39.067664 ==
1395 12:20:39.071003 Dram Type= 6, Freq= 0, CH_1, rank 1
1396 12:20:39.077844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 12:20:39.077934 ==
1398 12:20:39.081054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1399 12:20:39.087804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1400 12:20:39.097465 [CA 0] Center 36 (6~67) winsize 62
1401 12:20:39.100187 [CA 1] Center 37 (6~68) winsize 63
1402 12:20:39.103682 [CA 2] Center 35 (5~66) winsize 62
1403 12:20:39.107260 [CA 3] Center 34 (4~65) winsize 62
1404 12:20:39.110160 [CA 4] Center 34 (4~65) winsize 62
1405 12:20:39.113878 [CA 5] Center 34 (4~65) winsize 62
1406 12:20:39.113962
1407 12:20:39.117162 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1408 12:20:39.117262
1409 12:20:39.120458 [CATrainingPosCal] consider 2 rank data
1410 12:20:39.123598 u2DelayCellTimex100 = 270/100 ps
1411 12:20:39.127012 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1412 12:20:39.130263 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 12:20:39.136888 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1414 12:20:39.140466 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1415 12:20:39.143886 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 12:20:39.147048 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1417 12:20:39.147131
1418 12:20:39.150890 CA PerBit enable=1, Macro0, CA PI delay=34
1419 12:20:39.150973
1420 12:20:39.153827 [CBTSetCACLKResult] CA Dly = 34
1421 12:20:39.153910 CS Dly: 6 (0~38)
1422 12:20:39.153976
1423 12:20:39.157274 ----->DramcWriteLeveling(PI) begin...
1424 12:20:39.157358 ==
1425 12:20:39.160814 Dram Type= 6, Freq= 0, CH_1, rank 0
1426 12:20:39.164805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 12:20:39.168076 ==
1428 12:20:39.168160 Write leveling (Byte 0): 25 => 25
1429 12:20:39.171767 Write leveling (Byte 1): 30 => 30
1430 12:20:39.175468 DramcWriteLeveling(PI) end<-----
1431 12:20:39.175552
1432 12:20:39.175617 ==
1433 12:20:39.179039 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 12:20:39.182617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 12:20:39.182709 ==
1436 12:20:39.186733 [Gating] SW mode calibration
1437 12:20:39.194219 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1438 12:20:39.197801 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1439 12:20:39.204276 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1440 12:20:39.207741 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1441 12:20:39.211275 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 12:20:39.214396 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 12:20:39.220969 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 12:20:39.224720 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 12:20:39.227912 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 12:20:39.234702 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 12:20:39.238046 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 12:20:39.241304 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 12:20:39.248442 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 12:20:39.251243 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:20:39.254509 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:20:39.261341 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:20:39.264656 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:20:39.268041 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:20:39.274531 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1456 12:20:39.278289 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1457 12:20:39.281318 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1458 12:20:39.284636 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:20:39.291675 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:20:39.294780 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:20:39.298125 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:20:39.304656 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:20:39.308358 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:20:39.311654 0 9 4 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
1465 12:20:39.318225 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1466 12:20:39.321330 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 12:20:39.324898 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 12:20:39.331736 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 12:20:39.334776 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 12:20:39.338115 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 12:20:39.344953 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1472 12:20:39.348469 0 10 4 | B1->B0 | 2d2d 2c2c | 1 0 | (1 0) (1 0)
1473 12:20:39.351589 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:20:39.358348 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:20:39.362058 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:20:39.364809 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:20:39.368440 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:20:39.375190 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:20:39.378117 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1480 12:20:39.381771 0 11 4 | B1->B0 | 2f2f 3838 | 0 0 | (0 0) (0 0)
1481 12:20:39.388332 0 11 8 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1482 12:20:39.391895 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 12:20:39.395027 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 12:20:39.401751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 12:20:39.405368 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 12:20:39.408457 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 12:20:39.414989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 12:20:39.418345 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1489 12:20:39.421877 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1490 12:20:39.428461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 12:20:39.431854 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 12:20:39.435333 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 12:20:39.438451 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 12:20:39.445373 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 12:20:39.448482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 12:20:39.452049 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 12:20:39.458491 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 12:20:39.462151 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:20:39.465345 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:20:39.472023 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:20:39.475495 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:20:39.478765 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:20:39.485431 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1504 12:20:39.488651 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1505 12:20:39.492338 Total UI for P1: 0, mck2ui 16
1506 12:20:39.495283 best dqsien dly found for B0: ( 0, 14, 0)
1507 12:20:39.498926 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 12:20:39.501985 Total UI for P1: 0, mck2ui 16
1509 12:20:39.505810 best dqsien dly found for B1: ( 0, 14, 4)
1510 12:20:39.508840 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1511 12:20:39.512358 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1512 12:20:39.512441
1513 12:20:39.515471 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1514 12:20:39.518927 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1515 12:20:39.522258 [Gating] SW calibration Done
1516 12:20:39.522366 ==
1517 12:20:39.525582 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 12:20:39.532392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1519 12:20:39.532475 ==
1520 12:20:39.532541 RX Vref Scan: 0
1521 12:20:39.532604
1522 12:20:39.535587 RX Vref 0 -> 0, step: 1
1523 12:20:39.535674
1524 12:20:39.538710 RX Delay -130 -> 252, step: 16
1525 12:20:39.542280 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1526 12:20:39.545552 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1527 12:20:39.548836 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1528 12:20:39.552330 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1529 12:20:39.559072 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1530 12:20:39.562687 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1531 12:20:39.565575 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1532 12:20:39.569130 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1533 12:20:39.572397 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1534 12:20:39.578995 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1535 12:20:39.582367 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1536 12:20:39.585855 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1537 12:20:39.589417 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1538 12:20:39.592615 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1539 12:20:39.599402 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1540 12:20:39.602864 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1541 12:20:39.602985 ==
1542 12:20:39.606019 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 12:20:39.609551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 12:20:39.609672 ==
1545 12:20:39.609782 DQS Delay:
1546 12:20:39.612865 DQS0 = 0, DQS1 = 0
1547 12:20:39.612950 DQM Delay:
1548 12:20:39.615923 DQM0 = 88, DQM1 = 80
1549 12:20:39.615999 DQ Delay:
1550 12:20:39.619575 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1551 12:20:39.622680 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1552 12:20:39.626260 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1553 12:20:39.629143 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1554 12:20:39.629228
1555 12:20:39.629312
1556 12:20:39.629391 ==
1557 12:20:39.632810 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 12:20:39.636122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 12:20:39.639459 ==
1560 12:20:39.639544
1561 12:20:39.639627
1562 12:20:39.639707 TX Vref Scan disable
1563 12:20:39.642747 == TX Byte 0 ==
1564 12:20:39.646038 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1565 12:20:39.649400 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1566 12:20:39.652823 == TX Byte 1 ==
1567 12:20:39.655847 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1568 12:20:39.659494 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1569 12:20:39.662762 ==
1570 12:20:39.662845 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 12:20:39.669653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 12:20:39.669761 ==
1573 12:20:39.682066 TX Vref=22, minBit 10, minWin=27, winSum=451
1574 12:20:39.685544 TX Vref=24, minBit 15, minWin=27, winSum=453
1575 12:20:39.688748 TX Vref=26, minBit 15, minWin=27, winSum=455
1576 12:20:39.691910 TX Vref=28, minBit 8, minWin=28, winSum=459
1577 12:20:39.695403 TX Vref=30, minBit 15, minWin=27, winSum=458
1578 12:20:39.701771 TX Vref=32, minBit 9, minWin=27, winSum=455
1579 12:20:39.705244 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
1580 12:20:39.705322
1581 12:20:39.708500 Final TX Range 1 Vref 28
1582 12:20:39.708585
1583 12:20:39.708652 ==
1584 12:20:39.711912 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:20:39.715220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:20:39.718824 ==
1587 12:20:39.718908
1588 12:20:39.718973
1589 12:20:39.719033 TX Vref Scan disable
1590 12:20:39.722320 == TX Byte 0 ==
1591 12:20:39.725759 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1592 12:20:39.729200 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1593 12:20:39.732155 == TX Byte 1 ==
1594 12:20:39.735748 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1595 12:20:39.738834 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1596 12:20:39.742395
1597 12:20:39.742478 [DATLAT]
1598 12:20:39.742543 Freq=800, CH1 RK0
1599 12:20:39.742605
1600 12:20:39.745867 DATLAT Default: 0xa
1601 12:20:39.746014 0, 0xFFFF, sum = 0
1602 12:20:39.749710 1, 0xFFFF, sum = 0
1603 12:20:39.749795 2, 0xFFFF, sum = 0
1604 12:20:39.752697 3, 0xFFFF, sum = 0
1605 12:20:39.752805 4, 0xFFFF, sum = 0
1606 12:20:39.755990 5, 0xFFFF, sum = 0
1607 12:20:39.756075 6, 0xFFFF, sum = 0
1608 12:20:39.759583 7, 0xFFFF, sum = 0
1609 12:20:39.759668 8, 0xFFFF, sum = 0
1610 12:20:39.762795 9, 0x0, sum = 1
1611 12:20:39.762880 10, 0x0, sum = 2
1612 12:20:39.766566 11, 0x0, sum = 3
1613 12:20:39.766650 12, 0x0, sum = 4
1614 12:20:39.769632 best_step = 10
1615 12:20:39.769715
1616 12:20:39.769782 ==
1617 12:20:39.773189 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 12:20:39.776458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 12:20:39.776542 ==
1620 12:20:39.776608 RX Vref Scan: 1
1621 12:20:39.779577
1622 12:20:39.779660 Set Vref Range= 32 -> 127
1623 12:20:39.779727
1624 12:20:39.782836 RX Vref 32 -> 127, step: 1
1625 12:20:39.782962
1626 12:20:39.786481 RX Delay -95 -> 252, step: 8
1627 12:20:39.786561
1628 12:20:39.789551 Set Vref, RX VrefLevel [Byte0]: 32
1629 12:20:39.793240 [Byte1]: 32
1630 12:20:39.793348
1631 12:20:39.796342 Set Vref, RX VrefLevel [Byte0]: 33
1632 12:20:39.799605 [Byte1]: 33
1633 12:20:39.799688
1634 12:20:39.803205 Set Vref, RX VrefLevel [Byte0]: 34
1635 12:20:39.806294 [Byte1]: 34
1636 12:20:39.810035
1637 12:20:39.810120 Set Vref, RX VrefLevel [Byte0]: 35
1638 12:20:39.813598 [Byte1]: 35
1639 12:20:39.817745
1640 12:20:39.817829 Set Vref, RX VrefLevel [Byte0]: 36
1641 12:20:39.821266 [Byte1]: 36
1642 12:20:39.825324
1643 12:20:39.825407 Set Vref, RX VrefLevel [Byte0]: 37
1644 12:20:39.831741 [Byte1]: 37
1645 12:20:39.831825
1646 12:20:39.835202 Set Vref, RX VrefLevel [Byte0]: 38
1647 12:20:39.838357 [Byte1]: 38
1648 12:20:39.838440
1649 12:20:39.842086 Set Vref, RX VrefLevel [Byte0]: 39
1650 12:20:39.845594 [Byte1]: 39
1651 12:20:39.845678
1652 12:20:39.848323 Set Vref, RX VrefLevel [Byte0]: 40
1653 12:20:39.851930 [Byte1]: 40
1654 12:20:39.855556
1655 12:20:39.855639 Set Vref, RX VrefLevel [Byte0]: 41
1656 12:20:39.858889 [Byte1]: 41
1657 12:20:39.863336
1658 12:20:39.863420 Set Vref, RX VrefLevel [Byte0]: 42
1659 12:20:39.866477 [Byte1]: 42
1660 12:20:39.870976
1661 12:20:39.871063 Set Vref, RX VrefLevel [Byte0]: 43
1662 12:20:39.874478 [Byte1]: 43
1663 12:20:39.878308
1664 12:20:39.878391 Set Vref, RX VrefLevel [Byte0]: 44
1665 12:20:39.882095 [Byte1]: 44
1666 12:20:39.885944
1667 12:20:39.886029 Set Vref, RX VrefLevel [Byte0]: 45
1668 12:20:39.889363 [Byte1]: 45
1669 12:20:39.893896
1670 12:20:39.893979 Set Vref, RX VrefLevel [Byte0]: 46
1671 12:20:39.896917 [Byte1]: 46
1672 12:20:39.901308
1673 12:20:39.901408 Set Vref, RX VrefLevel [Byte0]: 47
1674 12:20:39.904537 [Byte1]: 47
1675 12:20:39.909087
1676 12:20:39.909172 Set Vref, RX VrefLevel [Byte0]: 48
1677 12:20:39.912205 [Byte1]: 48
1678 12:20:39.916345
1679 12:20:39.916430 Set Vref, RX VrefLevel [Byte0]: 49
1680 12:20:39.919820 [Byte1]: 49
1681 12:20:39.924019
1682 12:20:39.924141 Set Vref, RX VrefLevel [Byte0]: 50
1683 12:20:39.930439 [Byte1]: 50
1684 12:20:39.930521
1685 12:20:39.933911 Set Vref, RX VrefLevel [Byte0]: 51
1686 12:20:39.937290 [Byte1]: 51
1687 12:20:39.937376
1688 12:20:39.940739 Set Vref, RX VrefLevel [Byte0]: 52
1689 12:20:39.943892 [Byte1]: 52
1690 12:20:39.943977
1691 12:20:39.947574 Set Vref, RX VrefLevel [Byte0]: 53
1692 12:20:39.950516 [Byte1]: 53
1693 12:20:39.954891
1694 12:20:39.954975 Set Vref, RX VrefLevel [Byte0]: 54
1695 12:20:39.957699 [Byte1]: 54
1696 12:20:39.962007
1697 12:20:39.962159 Set Vref, RX VrefLevel [Byte0]: 55
1698 12:20:39.965454 [Byte1]: 55
1699 12:20:39.969627
1700 12:20:39.969749 Set Vref, RX VrefLevel [Byte0]: 56
1701 12:20:39.973043 [Byte1]: 56
1702 12:20:39.977427
1703 12:20:39.977551 Set Vref, RX VrefLevel [Byte0]: 57
1704 12:20:39.980459 [Byte1]: 57
1705 12:20:39.985057
1706 12:20:39.985176 Set Vref, RX VrefLevel [Byte0]: 58
1707 12:20:39.988043 [Byte1]: 58
1708 12:20:39.992614
1709 12:20:39.992729 Set Vref, RX VrefLevel [Byte0]: 59
1710 12:20:39.995918 [Byte1]: 59
1711 12:20:40.000031
1712 12:20:40.000146 Set Vref, RX VrefLevel [Byte0]: 60
1713 12:20:40.003450 [Byte1]: 60
1714 12:20:40.007578
1715 12:20:40.007696 Set Vref, RX VrefLevel [Byte0]: 61
1716 12:20:40.010977 [Byte1]: 61
1717 12:20:40.015428
1718 12:20:40.015548 Set Vref, RX VrefLevel [Byte0]: 62
1719 12:20:40.018617 [Byte1]: 62
1720 12:20:40.022607
1721 12:20:40.022712 Set Vref, RX VrefLevel [Byte0]: 63
1722 12:20:40.026247 [Byte1]: 63
1723 12:20:40.030508
1724 12:20:40.030590 Set Vref, RX VrefLevel [Byte0]: 64
1725 12:20:40.033976 [Byte1]: 64
1726 12:20:40.038543
1727 12:20:40.038625 Set Vref, RX VrefLevel [Byte0]: 65
1728 12:20:40.041264 [Byte1]: 65
1729 12:20:40.045655
1730 12:20:40.045737 Set Vref, RX VrefLevel [Byte0]: 66
1731 12:20:40.049085 [Byte1]: 66
1732 12:20:40.053315
1733 12:20:40.053397 Set Vref, RX VrefLevel [Byte0]: 67
1734 12:20:40.056381 [Byte1]: 67
1735 12:20:40.060703
1736 12:20:40.060805 Set Vref, RX VrefLevel [Byte0]: 68
1737 12:20:40.064264 [Byte1]: 68
1738 12:20:40.068451
1739 12:20:40.068532 Set Vref, RX VrefLevel [Byte0]: 69
1740 12:20:40.071864 [Byte1]: 69
1741 12:20:40.075895
1742 12:20:40.075976 Set Vref, RX VrefLevel [Byte0]: 70
1743 12:20:40.079260 [Byte1]: 70
1744 12:20:40.083728
1745 12:20:40.083829 Set Vref, RX VrefLevel [Byte0]: 71
1746 12:20:40.086794 [Byte1]: 71
1747 12:20:40.091043
1748 12:20:40.091125 Set Vref, RX VrefLevel [Byte0]: 72
1749 12:20:40.094659 [Byte1]: 72
1750 12:20:40.098914
1751 12:20:40.098995 Set Vref, RX VrefLevel [Byte0]: 73
1752 12:20:40.101994 [Byte1]: 73
1753 12:20:40.106478
1754 12:20:40.106560 Set Vref, RX VrefLevel [Byte0]: 74
1755 12:20:40.109710 [Byte1]: 74
1756 12:20:40.114085
1757 12:20:40.114167 Set Vref, RX VrefLevel [Byte0]: 75
1758 12:20:40.117262 [Byte1]: 75
1759 12:20:40.121495
1760 12:20:40.121576 Set Vref, RX VrefLevel [Byte0]: 76
1761 12:20:40.125016 [Byte1]: 76
1762 12:20:40.129025
1763 12:20:40.129110 Set Vref, RX VrefLevel [Byte0]: 77
1764 12:20:40.132563 [Byte1]: 77
1765 12:20:40.136636
1766 12:20:40.136721 Final RX Vref Byte 0 = 51 to rank0
1767 12:20:40.140074 Final RX Vref Byte 1 = 61 to rank0
1768 12:20:40.143252 Final RX Vref Byte 0 = 51 to rank1
1769 12:20:40.146735 Final RX Vref Byte 1 = 61 to rank1==
1770 12:20:40.150131 Dram Type= 6, Freq= 0, CH_1, rank 0
1771 12:20:40.156971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1772 12:20:40.157074 ==
1773 12:20:40.157167 DQS Delay:
1774 12:20:40.157256 DQS0 = 0, DQS1 = 0
1775 12:20:40.160079 DQM Delay:
1776 12:20:40.160189 DQM0 = 91, DQM1 = 81
1777 12:20:40.163432 DQ Delay:
1778 12:20:40.166831 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1779 12:20:40.166916 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1780 12:20:40.170370 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1781 12:20:40.176772 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =84
1782 12:20:40.176870
1783 12:20:40.176936
1784 12:20:40.183826 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1785 12:20:40.186971 CH1 RK0: MR19=606, MR18=2D4A
1786 12:20:40.193732 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1787 12:20:40.193816
1788 12:20:40.197203 ----->DramcWriteLeveling(PI) begin...
1789 12:20:40.197288 ==
1790 12:20:40.200383 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 12:20:40.203852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 12:20:40.203936 ==
1793 12:20:40.207220 Write leveling (Byte 0): 28 => 28
1794 12:20:40.210595 Write leveling (Byte 1): 29 => 29
1795 12:20:40.213702 DramcWriteLeveling(PI) end<-----
1796 12:20:40.213787
1797 12:20:40.213853 ==
1798 12:20:40.217432 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 12:20:40.220514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 12:20:40.220598 ==
1801 12:20:40.223567 [Gating] SW mode calibration
1802 12:20:40.230466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1803 12:20:40.237175 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1804 12:20:40.240433 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1805 12:20:40.243957 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1806 12:20:40.250601 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:20:40.254035 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:20:40.257119 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:20:40.260649 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:20:40.267222 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:20:40.270780 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:20:40.274115 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:20:40.280855 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:20:40.284170 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:20:40.287320 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:20:40.293797 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:20:40.297139 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:20:40.300440 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:20:40.307329 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:20:40.310378 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1821 12:20:40.313925 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1822 12:20:40.320582 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:20:40.323973 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:20:40.327159 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:20:40.334048 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:20:40.337605 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:20:40.340613 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:20:40.347077 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:20:40.350510 0 9 4 | B1->B0 | 2424 2323 | 1 1 | (1 1) (1 1)
1830 12:20:40.354177 0 9 8 | B1->B0 | 3030 3232 | 0 1 | (0 0) (1 1)
1831 12:20:40.357272 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 12:20:40.364057 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 12:20:40.367620 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:20:40.370903 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 12:20:40.377645 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 12:20:40.380666 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 12:20:40.384321 0 10 4 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
1838 12:20:40.390917 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:20:40.394416 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:20:40.397514 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:20:40.404396 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:20:40.407534 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:20:40.411082 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:20:40.417528 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:20:40.420959 0 11 4 | B1->B0 | 3333 3636 | 0 0 | (1 1) (0 0)
1846 12:20:40.424476 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1847 12:20:40.427608 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 12:20:40.434291 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 12:20:40.437517 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:20:40.441169 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 12:20:40.447947 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 12:20:40.451215 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 12:20:40.454298 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1854 12:20:40.461293 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1855 12:20:40.464440 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:20:40.467734 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:20:40.474570 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:20:40.477919 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:20:40.481069 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:20:40.488065 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:20:40.491138 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:20:40.494651 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:20:40.501381 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:20:40.504419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:20:40.507933 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:20:40.511314 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:20:40.518015 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:20:40.521115 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:20:40.524592 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1870 12:20:40.531237 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1871 12:20:40.534842 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 12:20:40.538030 Total UI for P1: 0, mck2ui 16
1873 12:20:40.541288 best dqsien dly found for B0: ( 0, 14, 6)
1874 12:20:40.544958 Total UI for P1: 0, mck2ui 16
1875 12:20:40.547993 best dqsien dly found for B1: ( 0, 14, 6)
1876 12:20:40.551587 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1877 12:20:40.554728 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1878 12:20:40.554814
1879 12:20:40.558083 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1880 12:20:40.561163 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1881 12:20:40.564541 [Gating] SW calibration Done
1882 12:20:40.564643 ==
1883 12:20:40.568227 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 12:20:40.571467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 12:20:40.571553 ==
1886 12:20:40.574573 RX Vref Scan: 0
1887 12:20:40.574658
1888 12:20:40.577917 RX Vref 0 -> 0, step: 1
1889 12:20:40.578001
1890 12:20:40.578067 RX Delay -130 -> 252, step: 16
1891 12:20:40.584842 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1892 12:20:40.587946 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1893 12:20:40.591261 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1894 12:20:40.594691 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1895 12:20:40.598078 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1896 12:20:40.604540 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1897 12:20:40.608220 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1898 12:20:40.611316 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1899 12:20:40.614881 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1900 12:20:40.618162 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1901 12:20:40.624845 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1902 12:20:40.628329 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1903 12:20:40.631513 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1904 12:20:40.635132 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1905 12:20:40.638316 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1906 12:20:40.644736 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1907 12:20:40.644845 ==
1908 12:20:40.648304 Dram Type= 6, Freq= 0, CH_1, rank 1
1909 12:20:40.651436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1910 12:20:40.651534 ==
1911 12:20:40.651600 DQS Delay:
1912 12:20:40.655030 DQS0 = 0, DQS1 = 0
1913 12:20:40.655137 DQM Delay:
1914 12:20:40.658314 DQM0 = 89, DQM1 = 81
1915 12:20:40.658432 DQ Delay:
1916 12:20:40.661627 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1917 12:20:40.665104 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1918 12:20:40.668094 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1919 12:20:40.671439 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1920 12:20:40.671524
1921 12:20:40.671591
1922 12:20:40.671658 ==
1923 12:20:40.674789 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 12:20:40.678330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 12:20:40.678417 ==
1926 12:20:40.681416
1927 12:20:40.681530
1928 12:20:40.681605 TX Vref Scan disable
1929 12:20:40.684853 == TX Byte 0 ==
1930 12:20:40.688506 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1931 12:20:40.691561 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1932 12:20:40.694793 == TX Byte 1 ==
1933 12:20:40.698182 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1934 12:20:40.701518 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1935 12:20:40.701606 ==
1936 12:20:40.704927 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 12:20:40.711602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 12:20:40.711691 ==
1939 12:20:40.723260 TX Vref=22, minBit 13, minWin=27, winSum=452
1940 12:20:40.726828 TX Vref=24, minBit 13, minWin=27, winSum=453
1941 12:20:40.730046 TX Vref=26, minBit 13, minWin=27, winSum=457
1942 12:20:40.733458 TX Vref=28, minBit 8, minWin=28, winSum=457
1943 12:20:40.736577 TX Vref=30, minBit 13, minWin=27, winSum=458
1944 12:20:40.743337 TX Vref=32, minBit 15, minWin=27, winSum=459
1945 12:20:40.746577 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 28
1946 12:20:40.746664
1947 12:20:40.749927 Final TX Range 1 Vref 28
1948 12:20:40.750017
1949 12:20:40.750086 ==
1950 12:20:40.753041 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 12:20:40.756767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 12:20:40.759812 ==
1953 12:20:40.759898
1954 12:20:40.759965
1955 12:20:40.760028 TX Vref Scan disable
1956 12:20:40.763428 == TX Byte 0 ==
1957 12:20:40.766724 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1958 12:20:40.770214 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1959 12:20:40.773662 == TX Byte 1 ==
1960 12:20:40.776713 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1961 12:20:40.780124 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1962 12:20:40.783248
1963 12:20:40.783383 [DATLAT]
1964 12:20:40.783502 Freq=800, CH1 RK1
1965 12:20:40.783620
1966 12:20:40.786946 DATLAT Default: 0xa
1967 12:20:40.787071 0, 0xFFFF, sum = 0
1968 12:20:40.790008 1, 0xFFFF, sum = 0
1969 12:20:40.790134 2, 0xFFFF, sum = 0
1970 12:20:40.793647 3, 0xFFFF, sum = 0
1971 12:20:40.793757 4, 0xFFFF, sum = 0
1972 12:20:40.797055 5, 0xFFFF, sum = 0
1973 12:20:40.797143 6, 0xFFFF, sum = 0
1974 12:20:40.800183 7, 0xFFFF, sum = 0
1975 12:20:40.803210 8, 0xFFFF, sum = 0
1976 12:20:40.803324 9, 0x0, sum = 1
1977 12:20:40.803441 10, 0x0, sum = 2
1978 12:20:40.806929 11, 0x0, sum = 3
1979 12:20:40.807046 12, 0x0, sum = 4
1980 12:20:40.810488 best_step = 10
1981 12:20:40.810597
1982 12:20:40.810692 ==
1983 12:20:40.813393 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 12:20:40.817049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 12:20:40.817160 ==
1986 12:20:40.819996 RX Vref Scan: 0
1987 12:20:40.820108
1988 12:20:40.820212 RX Vref 0 -> 0, step: 1
1989 12:20:40.820306
1990 12:20:40.823612 RX Delay -95 -> 252, step: 8
1991 12:20:40.829988 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1992 12:20:40.833619 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1993 12:20:40.836595 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1994 12:20:40.840187 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1995 12:20:40.843758 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1996 12:20:40.850016 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
1997 12:20:40.853510 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1998 12:20:40.857128 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
1999 12:20:40.860382 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2000 12:20:40.863545 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2001 12:20:40.866691 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2002 12:20:40.873820 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2003 12:20:40.876736 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2004 12:20:40.880301 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2005 12:20:40.883793 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2006 12:20:40.890220 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2007 12:20:40.890304 ==
2008 12:20:40.893588 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 12:20:40.897391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 12:20:40.897516 ==
2011 12:20:40.897624 DQS Delay:
2012 12:20:40.900201 DQS0 = 0, DQS1 = 0
2013 12:20:40.900326 DQM Delay:
2014 12:20:40.903654 DQM0 = 91, DQM1 = 83
2015 12:20:40.903777 DQ Delay:
2016 12:20:40.907170 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2017 12:20:40.910175 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2018 12:20:40.913830 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2019 12:20:40.916657 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2020 12:20:40.916770
2021 12:20:40.916867
2022 12:20:40.923392 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
2023 12:20:40.926903 CH1 RK1: MR19=606, MR18=3A10
2024 12:20:40.933935 CH1_RK1: MR19=0x606, MR18=0x3A10, DQSOSC=395, MR23=63, INC=94, DEC=63
2025 12:20:40.937167 [RxdqsGatingPostProcess] freq 800
2026 12:20:40.943717 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2027 12:20:40.943851 Pre-setting of DQS Precalculation
2028 12:20:40.950500 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2029 12:20:40.957325 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2030 12:20:40.963527 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2031 12:20:40.963654
2032 12:20:40.963772
2033 12:20:40.967131 [Calibration Summary] 1600 Mbps
2034 12:20:40.970276 CH 0, Rank 0
2035 12:20:40.970377 SW Impedance : PASS
2036 12:20:40.973854 DUTY Scan : NO K
2037 12:20:40.973954 ZQ Calibration : PASS
2038 12:20:40.977014 Jitter Meter : NO K
2039 12:20:40.980332 CBT Training : PASS
2040 12:20:40.980415 Write leveling : PASS
2041 12:20:40.984225 RX DQS gating : PASS
2042 12:20:40.987564 RX DQ/DQS(RDDQC) : PASS
2043 12:20:40.987647 TX DQ/DQS : PASS
2044 12:20:40.990573 RX DATLAT : PASS
2045 12:20:40.993919 RX DQ/DQS(Engine): PASS
2046 12:20:40.994058 TX OE : NO K
2047 12:20:40.997229 All Pass.
2048 12:20:40.997314
2049 12:20:40.997380 CH 0, Rank 1
2050 12:20:41.001021 SW Impedance : PASS
2051 12:20:41.001104 DUTY Scan : NO K
2052 12:20:41.003876 ZQ Calibration : PASS
2053 12:20:41.007382 Jitter Meter : NO K
2054 12:20:41.007470 CBT Training : PASS
2055 12:20:41.010665 Write leveling : PASS
2056 12:20:41.010742 RX DQS gating : PASS
2057 12:20:41.013871 RX DQ/DQS(RDDQC) : PASS
2058 12:20:41.017223 TX DQ/DQS : PASS
2059 12:20:41.017301 RX DATLAT : PASS
2060 12:20:41.020411 RX DQ/DQS(Engine): PASS
2061 12:20:41.023864 TX OE : NO K
2062 12:20:41.023943 All Pass.
2063 12:20:41.024042
2064 12:20:41.024146 CH 1, Rank 0
2065 12:20:41.027416 SW Impedance : PASS
2066 12:20:41.030450 DUTY Scan : NO K
2067 12:20:41.030528 ZQ Calibration : PASS
2068 12:20:41.033755 Jitter Meter : NO K
2069 12:20:41.037329 CBT Training : PASS
2070 12:20:41.037410 Write leveling : PASS
2071 12:20:41.040591 RX DQS gating : PASS
2072 12:20:41.044140 RX DQ/DQS(RDDQC) : PASS
2073 12:20:41.044215 TX DQ/DQS : PASS
2074 12:20:41.047263 RX DATLAT : PASS
2075 12:20:41.050528 RX DQ/DQS(Engine): PASS
2076 12:20:41.050605 TX OE : NO K
2077 12:20:41.050704 All Pass.
2078 12:20:41.053732
2079 12:20:41.053815 CH 1, Rank 1
2080 12:20:41.057147 SW Impedance : PASS
2081 12:20:41.057230 DUTY Scan : NO K
2082 12:20:41.060537 ZQ Calibration : PASS
2083 12:20:41.060651 Jitter Meter : NO K
2084 12:20:41.063909 CBT Training : PASS
2085 12:20:41.067104 Write leveling : PASS
2086 12:20:41.067186 RX DQS gating : PASS
2087 12:20:41.070297 RX DQ/DQS(RDDQC) : PASS
2088 12:20:41.073909 TX DQ/DQS : PASS
2089 12:20:41.073986 RX DATLAT : PASS
2090 12:20:41.077513 RX DQ/DQS(Engine): PASS
2091 12:20:41.080424 TX OE : NO K
2092 12:20:41.080498 All Pass.
2093 12:20:41.080560
2094 12:20:41.080619 DramC Write-DBI off
2095 12:20:41.083973 PER_BANK_REFRESH: Hybrid Mode
2096 12:20:41.087350 TX_TRACKING: ON
2097 12:20:41.090721 [GetDramInforAfterCalByMRR] Vendor 6.
2098 12:20:41.093777 [GetDramInforAfterCalByMRR] Revision 606.
2099 12:20:41.097275 [GetDramInforAfterCalByMRR] Revision 2 0.
2100 12:20:41.097400 MR0 0x3b3b
2101 12:20:41.100378 MR8 0x5151
2102 12:20:41.104249 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2103 12:20:41.104354
2104 12:20:41.104448 MR0 0x3b3b
2105 12:20:41.104538 MR8 0x5151
2106 12:20:41.110720 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 12:20:41.110804
2108 12:20:41.116887 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2109 12:20:41.120413 [FAST_K] Save calibration result to emmc
2110 12:20:41.123836 [FAST_K] Save calibration result to emmc
2111 12:20:41.126993 dram_init: config_dvfs: 1
2112 12:20:41.130658 dramc_set_vcore_voltage set vcore to 662500
2113 12:20:41.133984 Read voltage for 1200, 2
2114 12:20:41.134068 Vio18 = 0
2115 12:20:41.137079 Vcore = 662500
2116 12:20:41.137195 Vdram = 0
2117 12:20:41.137275 Vddq = 0
2118 12:20:41.137350 Vmddr = 0
2119 12:20:41.143719 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2120 12:20:41.150525 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2121 12:20:41.150655 MEM_TYPE=3, freq_sel=15
2122 12:20:41.153637 sv_algorithm_assistance_LP4_1600
2123 12:20:41.157310 ============ PULL DRAM RESETB DOWN ============
2124 12:20:41.163765 ========== PULL DRAM RESETB DOWN end =========
2125 12:20:41.167457 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2126 12:20:41.170629 ===================================
2127 12:20:41.173835 LPDDR4 DRAM CONFIGURATION
2128 12:20:41.177546 ===================================
2129 12:20:41.177672 EX_ROW_EN[0] = 0x0
2130 12:20:41.180654 EX_ROW_EN[1] = 0x0
2131 12:20:41.180811 LP4Y_EN = 0x0
2132 12:20:41.184160 WORK_FSP = 0x0
2133 12:20:41.184284 WL = 0x4
2134 12:20:41.187277 RL = 0x4
2135 12:20:41.187406 BL = 0x2
2136 12:20:41.190736 RPST = 0x0
2137 12:20:41.190862 RD_PRE = 0x0
2138 12:20:41.194131 WR_PRE = 0x1
2139 12:20:41.194251 WR_PST = 0x0
2140 12:20:41.197346 DBI_WR = 0x0
2141 12:20:41.197446 DBI_RD = 0x0
2142 12:20:41.200888 OTF = 0x1
2143 12:20:41.204243 ===================================
2144 12:20:41.207226 ===================================
2145 12:20:41.207309 ANA top config
2146 12:20:41.210934 ===================================
2147 12:20:41.214256 DLL_ASYNC_EN = 0
2148 12:20:41.217289 ALL_SLAVE_EN = 0
2149 12:20:41.220722 NEW_RANK_MODE = 1
2150 12:20:41.220831 DLL_IDLE_MODE = 1
2151 12:20:41.223965 LP45_APHY_COMB_EN = 1
2152 12:20:41.227388 TX_ODT_DIS = 1
2153 12:20:41.231024 NEW_8X_MODE = 1
2154 12:20:41.234284 ===================================
2155 12:20:41.237426 ===================================
2156 12:20:41.240912 data_rate = 2400
2157 12:20:41.240996 CKR = 1
2158 12:20:41.244022 DQ_P2S_RATIO = 8
2159 12:20:41.247662 ===================================
2160 12:20:41.250854 CA_P2S_RATIO = 8
2161 12:20:41.254375 DQ_CA_OPEN = 0
2162 12:20:41.257552 DQ_SEMI_OPEN = 0
2163 12:20:41.260943 CA_SEMI_OPEN = 0
2164 12:20:41.261026 CA_FULL_RATE = 0
2165 12:20:41.264127 DQ_CKDIV4_EN = 0
2166 12:20:41.267746 CA_CKDIV4_EN = 0
2167 12:20:41.270910 CA_PREDIV_EN = 0
2168 12:20:41.274032 PH8_DLY = 17
2169 12:20:41.277705 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2170 12:20:41.277789 DQ_AAMCK_DIV = 4
2171 12:20:41.280925 CA_AAMCK_DIV = 4
2172 12:20:41.284434 CA_ADMCK_DIV = 4
2173 12:20:41.287723 DQ_TRACK_CA_EN = 0
2174 12:20:41.290789 CA_PICK = 1200
2175 12:20:41.294373 CA_MCKIO = 1200
2176 12:20:41.294473 MCKIO_SEMI = 0
2177 12:20:41.297498 PLL_FREQ = 2366
2178 12:20:41.301067 DQ_UI_PI_RATIO = 32
2179 12:20:41.304120 CA_UI_PI_RATIO = 0
2180 12:20:41.307953 ===================================
2181 12:20:41.311007 ===================================
2182 12:20:41.314169 memory_type:LPDDR4
2183 12:20:41.314253 GP_NUM : 10
2184 12:20:41.317497 SRAM_EN : 1
2185 12:20:41.320961 MD32_EN : 0
2186 12:20:41.324195 ===================================
2187 12:20:41.324280 [ANA_INIT] >>>>>>>>>>>>>>
2188 12:20:41.327713 <<<<<< [CONFIGURE PHASE]: ANA_TX
2189 12:20:41.331118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2190 12:20:41.334423 ===================================
2191 12:20:41.337561 data_rate = 2400,PCW = 0X5b00
2192 12:20:41.340918 ===================================
2193 12:20:41.344326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2194 12:20:41.351222 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 12:20:41.354395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 12:20:41.361557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2197 12:20:41.364688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2198 12:20:41.367860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2199 12:20:41.367979 [ANA_INIT] flow start
2200 12:20:41.371445 [ANA_INIT] PLL >>>>>>>>
2201 12:20:41.374810 [ANA_INIT] PLL <<<<<<<<
2202 12:20:41.374927 [ANA_INIT] MIDPI >>>>>>>>
2203 12:20:41.377896 [ANA_INIT] MIDPI <<<<<<<<
2204 12:20:41.381417 [ANA_INIT] DLL >>>>>>>>
2205 12:20:41.381538 [ANA_INIT] DLL <<<<<<<<
2206 12:20:41.384581 [ANA_INIT] flow end
2207 12:20:41.387881 ============ LP4 DIFF to SE enter ============
2208 12:20:41.391438 ============ LP4 DIFF to SE exit ============
2209 12:20:41.394603 [ANA_INIT] <<<<<<<<<<<<<
2210 12:20:41.398131 [Flow] Enable top DCM control >>>>>
2211 12:20:41.401316 [Flow] Enable top DCM control <<<<<
2212 12:20:41.404615 Enable DLL master slave shuffle
2213 12:20:41.411275 ==============================================================
2214 12:20:41.411360 Gating Mode config
2215 12:20:41.418134 ==============================================================
2216 12:20:41.418236 Config description:
2217 12:20:41.428301 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2218 12:20:41.435005 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2219 12:20:41.441718 SELPH_MODE 0: By rank 1: By Phase
2220 12:20:41.445195 ==============================================================
2221 12:20:41.448509 GAT_TRACK_EN = 1
2222 12:20:41.451655 RX_GATING_MODE = 2
2223 12:20:41.455120 RX_GATING_TRACK_MODE = 2
2224 12:20:41.458274 SELPH_MODE = 1
2225 12:20:41.461757 PICG_EARLY_EN = 1
2226 12:20:41.465078 VALID_LAT_VALUE = 1
2227 12:20:41.468280 ==============================================================
2228 12:20:41.471888 Enter into Gating configuration >>>>
2229 12:20:41.475042 Exit from Gating configuration <<<<
2230 12:20:41.478285 Enter into DVFS_PRE_config >>>>>
2231 12:20:41.491790 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2232 12:20:41.491879 Exit from DVFS_PRE_config <<<<<
2233 12:20:41.495029 Enter into PICG configuration >>>>
2234 12:20:41.498332 Exit from PICG configuration <<<<
2235 12:20:41.501621 [RX_INPUT] configuration >>>>>
2236 12:20:41.505149 [RX_INPUT] configuration <<<<<
2237 12:20:41.511596 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2238 12:20:41.515211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2239 12:20:41.522037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 12:20:41.528273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 12:20:41.535293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 12:20:41.541841 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 12:20:41.545024 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2244 12:20:41.548600 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2245 12:20:41.552041 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2246 12:20:41.558379 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2247 12:20:41.561981 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2248 12:20:41.565150 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2249 12:20:41.568443 ===================================
2250 12:20:41.572071 LPDDR4 DRAM CONFIGURATION
2251 12:20:41.575298 ===================================
2252 12:20:41.575384 EX_ROW_EN[0] = 0x0
2253 12:20:41.578418 EX_ROW_EN[1] = 0x0
2254 12:20:41.578531 LP4Y_EN = 0x0
2255 12:20:41.582036 WORK_FSP = 0x0
2256 12:20:41.585270 WL = 0x4
2257 12:20:41.585352 RL = 0x4
2258 12:20:41.588536 BL = 0x2
2259 12:20:41.588631 RPST = 0x0
2260 12:20:41.591998 RD_PRE = 0x0
2261 12:20:41.592080 WR_PRE = 0x1
2262 12:20:41.595279 WR_PST = 0x0
2263 12:20:41.595360 DBI_WR = 0x0
2264 12:20:41.598838 DBI_RD = 0x0
2265 12:20:41.598937 OTF = 0x1
2266 12:20:41.601805 ===================================
2267 12:20:41.605436 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2268 12:20:41.611809 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2269 12:20:41.615658 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 12:20:41.618864 ===================================
2271 12:20:41.621890 LPDDR4 DRAM CONFIGURATION
2272 12:20:41.625438 ===================================
2273 12:20:41.625521 EX_ROW_EN[0] = 0x10
2274 12:20:41.628590 EX_ROW_EN[1] = 0x0
2275 12:20:41.628689 LP4Y_EN = 0x0
2276 12:20:41.632250 WORK_FSP = 0x0
2277 12:20:41.632332 WL = 0x4
2278 12:20:41.635345 RL = 0x4
2279 12:20:41.635429 BL = 0x2
2280 12:20:41.639004 RPST = 0x0
2281 12:20:41.639093 RD_PRE = 0x0
2282 12:20:41.641970 WR_PRE = 0x1
2283 12:20:41.642053 WR_PST = 0x0
2284 12:20:41.645683 DBI_WR = 0x0
2285 12:20:41.645781 DBI_RD = 0x0
2286 12:20:41.648867 OTF = 0x1
2287 12:20:41.651913 ===================================
2288 12:20:41.658774 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2289 12:20:41.658858 ==
2290 12:20:41.662379 Dram Type= 6, Freq= 0, CH_0, rank 0
2291 12:20:41.665604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2292 12:20:41.665708 ==
2293 12:20:41.668633 [Duty_Offset_Calibration]
2294 12:20:41.668742 B0:2 B1:0 CA:1
2295 12:20:41.668893
2296 12:20:41.672239 [DutyScan_Calibration_Flow] k_type=0
2297 12:20:41.681773
2298 12:20:41.681857 ==CLK 0==
2299 12:20:41.685052 Final CLK duty delay cell = -4
2300 12:20:41.688597 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2301 12:20:41.691817 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2302 12:20:41.695117 [-4] AVG Duty = 4953%(X100)
2303 12:20:41.695198
2304 12:20:41.698733 CH0 CLK Duty spec in!! Max-Min= 156%
2305 12:20:41.701814 [DutyScan_Calibration_Flow] ====Done====
2306 12:20:41.701894
2307 12:20:41.705108 [DutyScan_Calibration_Flow] k_type=1
2308 12:20:41.720833
2309 12:20:41.720915 ==DQS 0 ==
2310 12:20:41.724056 Final DQS duty delay cell = 0
2311 12:20:41.727311 [0] MAX Duty = 5187%(X100), DQS PI = 30
2312 12:20:41.730829 [0] MIN Duty = 4938%(X100), DQS PI = 2
2313 12:20:41.730906 [0] AVG Duty = 5062%(X100)
2314 12:20:41.733957
2315 12:20:41.734038 ==DQS 1 ==
2316 12:20:41.737241 Final DQS duty delay cell = -4
2317 12:20:41.740645 [-4] MAX Duty = 5124%(X100), DQS PI = 48
2318 12:20:41.743871 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2319 12:20:41.747334 [-4] AVG Duty = 5031%(X100)
2320 12:20:41.747415
2321 12:20:41.751038 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2322 12:20:41.751119
2323 12:20:41.753885 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2324 12:20:41.757580 [DutyScan_Calibration_Flow] ====Done====
2325 12:20:41.757668
2326 12:20:41.760579 [DutyScan_Calibration_Flow] k_type=3
2327 12:20:41.776666
2328 12:20:41.776814 ==DQM 0 ==
2329 12:20:41.780243 Final DQM duty delay cell = 0
2330 12:20:41.783292 [0] MAX Duty = 5062%(X100), DQS PI = 24
2331 12:20:41.786762 [0] MIN Duty = 4844%(X100), DQS PI = 2
2332 12:20:41.786842 [0] AVG Duty = 4953%(X100)
2333 12:20:41.786906
2334 12:20:41.790362 ==DQM 1 ==
2335 12:20:41.793808 Final DQM duty delay cell = -4
2336 12:20:41.796725 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2337 12:20:41.800403 [-4] MIN Duty = 4813%(X100), DQS PI = 10
2338 12:20:41.804632 [-4] AVG Duty = 4906%(X100)
2339 12:20:41.804745
2340 12:20:41.807113 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2341 12:20:41.807221
2342 12:20:41.810182 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2343 12:20:41.813747 [DutyScan_Calibration_Flow] ====Done====
2344 12:20:41.813821
2345 12:20:41.816525 [DutyScan_Calibration_Flow] k_type=2
2346 12:20:41.832570
2347 12:20:41.832674 ==DQ 0 ==
2348 12:20:41.836276 Final DQ duty delay cell = -4
2349 12:20:41.839449 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2350 12:20:41.843009 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2351 12:20:41.843118 [-4] AVG Duty = 4969%(X100)
2352 12:20:41.846084
2353 12:20:41.846168 ==DQ 1 ==
2354 12:20:41.849671 Final DQ duty delay cell = 0
2355 12:20:41.852730 [0] MAX Duty = 4969%(X100), DQS PI = 8
2356 12:20:41.856477 [0] MIN Duty = 4907%(X100), DQS PI = 0
2357 12:20:41.856604 [0] AVG Duty = 4938%(X100)
2358 12:20:41.856697
2359 12:20:41.860124 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2360 12:20:41.860238
2361 12:20:41.863195 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2362 12:20:41.869730 [DutyScan_Calibration_Flow] ====Done====
2363 12:20:41.869815 ==
2364 12:20:41.872746 Dram Type= 6, Freq= 0, CH_1, rank 0
2365 12:20:41.876139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 12:20:41.876222 ==
2367 12:20:41.879745 [Duty_Offset_Calibration]
2368 12:20:41.879828 B0:0 B1:-1 CA:2
2369 12:20:41.879894
2370 12:20:41.882718 [DutyScan_Calibration_Flow] k_type=0
2371 12:20:41.892763
2372 12:20:41.892860 ==CLK 0==
2373 12:20:41.896331 Final CLK duty delay cell = 0
2374 12:20:41.899648 [0] MAX Duty = 5156%(X100), DQS PI = 14
2375 12:20:41.902916 [0] MIN Duty = 4938%(X100), DQS PI = 44
2376 12:20:41.902999 [0] AVG Duty = 5047%(X100)
2377 12:20:41.906258
2378 12:20:41.906357 CH1 CLK Duty spec in!! Max-Min= 218%
2379 12:20:41.912651 [DutyScan_Calibration_Flow] ====Done====
2380 12:20:41.912810
2381 12:20:41.916261 [DutyScan_Calibration_Flow] k_type=1
2382 12:20:41.932136
2383 12:20:41.932275 ==DQS 0 ==
2384 12:20:41.935421 Final DQS duty delay cell = 0
2385 12:20:41.938997 [0] MAX Duty = 5093%(X100), DQS PI = 22
2386 12:20:41.942270 [0] MIN Duty = 4969%(X100), DQS PI = 0
2387 12:20:41.945383 [0] AVG Duty = 5031%(X100)
2388 12:20:41.945522
2389 12:20:41.945634 ==DQS 1 ==
2390 12:20:41.948570 Final DQS duty delay cell = 0
2391 12:20:41.952287 [0] MAX Duty = 5187%(X100), DQS PI = 62
2392 12:20:41.955460 [0] MIN Duty = 4844%(X100), DQS PI = 36
2393 12:20:41.959102 [0] AVG Duty = 5015%(X100)
2394 12:20:41.959184
2395 12:20:41.961975 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2396 12:20:41.962058
2397 12:20:41.965170 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2398 12:20:41.968568 [DutyScan_Calibration_Flow] ====Done====
2399 12:20:41.968650
2400 12:20:41.972251 [DutyScan_Calibration_Flow] k_type=3
2401 12:20:41.988642
2402 12:20:41.988742 ==DQM 0 ==
2403 12:20:41.992265 Final DQM duty delay cell = 4
2404 12:20:41.995510 [4] MAX Duty = 5093%(X100), DQS PI = 20
2405 12:20:41.999069 [4] MIN Duty = 4938%(X100), DQS PI = 30
2406 12:20:41.999152 [4] AVG Duty = 5015%(X100)
2407 12:20:42.002167
2408 12:20:42.002249 ==DQM 1 ==
2409 12:20:42.005811 Final DQM duty delay cell = -4
2410 12:20:42.009096 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2411 12:20:42.012458 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2412 12:20:42.015551 [-4] AVG Duty = 4875%(X100)
2413 12:20:42.015634
2414 12:20:42.019074 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2415 12:20:42.019158
2416 12:20:42.022554 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2417 12:20:42.026125 [DutyScan_Calibration_Flow] ====Done====
2418 12:20:42.026207
2419 12:20:42.028973 [DutyScan_Calibration_Flow] k_type=2
2420 12:20:42.045928
2421 12:20:42.046012 ==DQ 0 ==
2422 12:20:42.049116 Final DQ duty delay cell = 0
2423 12:20:42.052222 [0] MAX Duty = 5062%(X100), DQS PI = 20
2424 12:20:42.055490 [0] MIN Duty = 4938%(X100), DQS PI = 30
2425 12:20:42.055573 [0] AVG Duty = 5000%(X100)
2426 12:20:42.059107
2427 12:20:42.059189 ==DQ 1 ==
2428 12:20:42.062283 Final DQ duty delay cell = 0
2429 12:20:42.065743 [0] MAX Duty = 5062%(X100), DQS PI = 4
2430 12:20:42.068922 [0] MIN Duty = 4813%(X100), DQS PI = 36
2431 12:20:42.069005 [0] AVG Duty = 4937%(X100)
2432 12:20:42.069071
2433 12:20:42.072282 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2434 12:20:42.072410
2435 12:20:42.078859 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2436 12:20:42.082513 [DutyScan_Calibration_Flow] ====Done====
2437 12:20:42.085563 nWR fixed to 30
2438 12:20:42.085647 [ModeRegInit_LP4] CH0 RK0
2439 12:20:42.088922 [ModeRegInit_LP4] CH0 RK1
2440 12:20:42.092382 [ModeRegInit_LP4] CH1 RK0
2441 12:20:42.092477 [ModeRegInit_LP4] CH1 RK1
2442 12:20:42.095754 match AC timing 7
2443 12:20:42.098815 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2444 12:20:42.102478 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2445 12:20:42.108776 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2446 12:20:42.112400 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2447 12:20:42.119016 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2448 12:20:42.119098 ==
2449 12:20:42.122266 Dram Type= 6, Freq= 0, CH_0, rank 0
2450 12:20:42.125596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2451 12:20:42.125717 ==
2452 12:20:42.132481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2453 12:20:42.135518 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2454 12:20:42.145409 [CA 0] Center 38 (7~69) winsize 63
2455 12:20:42.149076 [CA 1] Center 38 (8~69) winsize 62
2456 12:20:42.152479 [CA 2] Center 35 (5~66) winsize 62
2457 12:20:42.155753 [CA 3] Center 35 (4~66) winsize 63
2458 12:20:42.158863 [CA 4] Center 34 (4~65) winsize 62
2459 12:20:42.162172 [CA 5] Center 33 (3~63) winsize 61
2460 12:20:42.162255
2461 12:20:42.165421 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2462 12:20:42.165503
2463 12:20:42.168656 [CATrainingPosCal] consider 1 rank data
2464 12:20:42.172198 u2DelayCellTimex100 = 270/100 ps
2465 12:20:42.175729 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2466 12:20:42.179194 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2467 12:20:42.185861 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2468 12:20:42.188932 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2469 12:20:42.192475 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2470 12:20:42.195565 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2471 12:20:42.195671
2472 12:20:42.198979 CA PerBit enable=1, Macro0, CA PI delay=33
2473 12:20:42.199078
2474 12:20:42.202218 [CBTSetCACLKResult] CA Dly = 33
2475 12:20:42.202317 CS Dly: 6 (0~37)
2476 12:20:42.202415 ==
2477 12:20:42.205874 Dram Type= 6, Freq= 0, CH_0, rank 1
2478 12:20:42.212514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2479 12:20:42.212597 ==
2480 12:20:42.215836 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2481 12:20:42.222448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2482 12:20:42.231339 [CA 0] Center 39 (8~70) winsize 63
2483 12:20:42.234504 [CA 1] Center 38 (8~69) winsize 62
2484 12:20:42.237946 [CA 2] Center 35 (5~66) winsize 62
2485 12:20:42.241288 [CA 3] Center 35 (5~66) winsize 62
2486 12:20:42.245046 [CA 4] Center 34 (4~65) winsize 62
2487 12:20:42.248012 [CA 5] Center 34 (4~64) winsize 61
2488 12:20:42.248093
2489 12:20:42.251141 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2490 12:20:42.251223
2491 12:20:42.254375 [CATrainingPosCal] consider 2 rank data
2492 12:20:42.258004 u2DelayCellTimex100 = 270/100 ps
2493 12:20:42.261209 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2494 12:20:42.264729 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2495 12:20:42.271404 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2496 12:20:42.274597 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 12:20:42.278199 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2498 12:20:42.281259 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2499 12:20:42.281358
2500 12:20:42.284561 CA PerBit enable=1, Macro0, CA PI delay=33
2501 12:20:42.284657
2502 12:20:42.288127 [CBTSetCACLKResult] CA Dly = 33
2503 12:20:42.288225 CS Dly: 7 (0~39)
2504 12:20:42.288305
2505 12:20:42.291281 ----->DramcWriteLeveling(PI) begin...
2506 12:20:42.291365 ==
2507 12:20:42.294891 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 12:20:42.301222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 12:20:42.301331 ==
2510 12:20:42.304863 Write leveling (Byte 0): 33 => 33
2511 12:20:42.308241 Write leveling (Byte 1): 30 => 30
2512 12:20:42.308323 DramcWriteLeveling(PI) end<-----
2513 12:20:42.308388
2514 12:20:42.311866 ==
2515 12:20:42.314843 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 12:20:42.318268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 12:20:42.318352 ==
2518 12:20:42.321728 [Gating] SW mode calibration
2519 12:20:42.328377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2520 12:20:42.331512 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2521 12:20:42.338467 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2522 12:20:42.341593 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2523 12:20:42.344946 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 12:20:42.351803 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 12:20:42.355030 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 12:20:42.358703 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 12:20:42.365193 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2528 12:20:42.368344 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2529 12:20:42.371659 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2530 12:20:42.375249 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2531 12:20:42.381547 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 12:20:42.384963 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 12:20:42.388393 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 12:20:42.395098 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 12:20:42.398226 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2536 12:20:42.401550 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2537 12:20:42.408374 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2538 12:20:42.411946 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 12:20:42.415102 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 12:20:42.421583 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 12:20:42.425039 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 12:20:42.428415 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 12:20:42.435338 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 12:20:42.438650 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2545 12:20:42.441819 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2546 12:20:42.448599 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 12:20:42.452132 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:20:42.454966 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:20:42.458730 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:20:42.465442 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:20:42.468614 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:20:42.471863 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:20:42.478480 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:20:42.482095 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:20:42.485298 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:20:42.491712 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:20:42.494962 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:20:42.498536 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:20:42.505215 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:20:42.508372 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2561 12:20:42.511994 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2562 12:20:42.515191 Total UI for P1: 0, mck2ui 16
2563 12:20:42.518923 best dqsien dly found for B0: ( 1, 3, 28)
2564 12:20:42.525324 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 12:20:42.528738 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 12:20:42.531988 Total UI for P1: 0, mck2ui 16
2567 12:20:42.535533 best dqsien dly found for B1: ( 1, 4, 0)
2568 12:20:42.538904 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2569 12:20:42.542060 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2570 12:20:42.542143
2571 12:20:42.545381 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2572 12:20:42.548837 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2573 12:20:42.552003 [Gating] SW calibration Done
2574 12:20:42.552086 ==
2575 12:20:42.555613 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 12:20:42.558878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 12:20:42.558963 ==
2578 12:20:42.562267 RX Vref Scan: 0
2579 12:20:42.562364
2580 12:20:42.562445 RX Vref 0 -> 0, step: 1
2581 12:20:42.562507
2582 12:20:42.565640 RX Delay -40 -> 252, step: 8
2583 12:20:42.568826 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2584 12:20:42.575528 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2585 12:20:42.579194 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2586 12:20:42.582506 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2587 12:20:42.585676 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2588 12:20:42.588893 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2589 12:20:42.595723 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2590 12:20:42.598912 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2591 12:20:42.602187 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2592 12:20:42.605785 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2593 12:20:42.608814 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2594 12:20:42.612264 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2595 12:20:42.619287 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2596 12:20:42.622720 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2597 12:20:42.625866 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2598 12:20:42.629125 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2599 12:20:42.629208 ==
2600 12:20:42.632541 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 12:20:42.639622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 12:20:42.639720 ==
2603 12:20:42.639786 DQS Delay:
2604 12:20:42.642435 DQS0 = 0, DQS1 = 0
2605 12:20:42.642518 DQM Delay:
2606 12:20:42.642584 DQM0 = 122, DQM1 = 110
2607 12:20:42.646093 DQ Delay:
2608 12:20:42.649152 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2609 12:20:42.652590 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2610 12:20:42.655985 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2611 12:20:42.659378 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2612 12:20:42.659474
2613 12:20:42.659557
2614 12:20:42.659632 ==
2615 12:20:42.662893 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 12:20:42.666138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 12:20:42.666221 ==
2618 12:20:42.669291
2619 12:20:42.669373
2620 12:20:42.669438 TX Vref Scan disable
2621 12:20:42.672413 == TX Byte 0 ==
2622 12:20:42.676067 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2623 12:20:42.679246 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2624 12:20:42.682481 == TX Byte 1 ==
2625 12:20:42.686077 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2626 12:20:42.689294 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2627 12:20:42.689376 ==
2628 12:20:42.692908 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 12:20:42.699489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 12:20:42.699572 ==
2631 12:20:42.710368 TX Vref=22, minBit 6, minWin=24, winSum=407
2632 12:20:42.713342 TX Vref=24, minBit 3, minWin=24, winSum=407
2633 12:20:42.717007 TX Vref=26, minBit 0, minWin=25, winSum=412
2634 12:20:42.720132 TX Vref=28, minBit 4, minWin=25, winSum=422
2635 12:20:42.723333 TX Vref=30, minBit 5, minWin=25, winSum=419
2636 12:20:42.726578 TX Vref=32, minBit 1, minWin=25, winSum=416
2637 12:20:42.733353 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
2638 12:20:42.733464
2639 12:20:42.736675 Final TX Range 1 Vref 28
2640 12:20:42.736817
2641 12:20:42.736885 ==
2642 12:20:42.740000 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 12:20:42.743288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 12:20:42.743394 ==
2645 12:20:42.743486
2646 12:20:42.743623
2647 12:20:42.746609 TX Vref Scan disable
2648 12:20:42.750171 == TX Byte 0 ==
2649 12:20:42.753326 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2650 12:20:42.756609 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2651 12:20:42.760036 == TX Byte 1 ==
2652 12:20:42.763374 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2653 12:20:42.766847 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2654 12:20:42.767000
2655 12:20:42.770259 [DATLAT]
2656 12:20:42.770411 Freq=1200, CH0 RK0
2657 12:20:42.770523
2658 12:20:42.773751 DATLAT Default: 0xd
2659 12:20:42.773902 0, 0xFFFF, sum = 0
2660 12:20:42.776983 1, 0xFFFF, sum = 0
2661 12:20:42.777116 2, 0xFFFF, sum = 0
2662 12:20:42.780471 3, 0xFFFF, sum = 0
2663 12:20:42.780626 4, 0xFFFF, sum = 0
2664 12:20:42.783827 5, 0xFFFF, sum = 0
2665 12:20:42.783947 6, 0xFFFF, sum = 0
2666 12:20:42.786909 7, 0xFFFF, sum = 0
2667 12:20:42.787015 8, 0xFFFF, sum = 0
2668 12:20:42.790495 9, 0xFFFF, sum = 0
2669 12:20:42.790580 10, 0xFFFF, sum = 0
2670 12:20:42.793701 11, 0xFFFF, sum = 0
2671 12:20:42.793786 12, 0x0, sum = 1
2672 12:20:42.797191 13, 0x0, sum = 2
2673 12:20:42.797276 14, 0x0, sum = 3
2674 12:20:42.800355 15, 0x0, sum = 4
2675 12:20:42.800467 best_step = 13
2676 12:20:42.800568
2677 12:20:42.800661 ==
2678 12:20:42.803660 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 12:20:42.810047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 12:20:42.810173 ==
2681 12:20:42.810282 RX Vref Scan: 1
2682 12:20:42.810381
2683 12:20:42.813288 Set Vref Range= 32 -> 127
2684 12:20:42.813385
2685 12:20:42.816770 RX Vref 32 -> 127, step: 1
2686 12:20:42.816883
2687 12:20:42.820381 RX Delay -13 -> 252, step: 4
2688 12:20:42.820480
2689 12:20:42.823568 Set Vref, RX VrefLevel [Byte0]: 32
2690 12:20:42.826930 [Byte1]: 32
2691 12:20:42.827004
2692 12:20:42.830122 Set Vref, RX VrefLevel [Byte0]: 33
2693 12:20:42.833935 [Byte1]: 33
2694 12:20:42.834017
2695 12:20:42.836857 Set Vref, RX VrefLevel [Byte0]: 34
2696 12:20:42.840450 [Byte1]: 34
2697 12:20:42.844292
2698 12:20:42.844375 Set Vref, RX VrefLevel [Byte0]: 35
2699 12:20:42.847276 [Byte1]: 35
2700 12:20:42.852181
2701 12:20:42.852263 Set Vref, RX VrefLevel [Byte0]: 36
2702 12:20:42.855385 [Byte1]: 36
2703 12:20:42.859759
2704 12:20:42.859842 Set Vref, RX VrefLevel [Byte0]: 37
2705 12:20:42.863072 [Byte1]: 37
2706 12:20:42.868030
2707 12:20:42.868133 Set Vref, RX VrefLevel [Byte0]: 38
2708 12:20:42.870831 [Byte1]: 38
2709 12:20:42.875741
2710 12:20:42.875856 Set Vref, RX VrefLevel [Byte0]: 39
2711 12:20:42.878948 [Byte1]: 39
2712 12:20:42.883454
2713 12:20:42.883538 Set Vref, RX VrefLevel [Byte0]: 40
2714 12:20:42.886698 [Byte1]: 40
2715 12:20:42.891202
2716 12:20:42.891286 Set Vref, RX VrefLevel [Byte0]: 41
2717 12:20:42.894801 [Byte1]: 41
2718 12:20:42.899245
2719 12:20:42.899327 Set Vref, RX VrefLevel [Byte0]: 42
2720 12:20:42.902509 [Byte1]: 42
2721 12:20:42.907212
2722 12:20:42.907291 Set Vref, RX VrefLevel [Byte0]: 43
2723 12:20:42.910477 [Byte1]: 43
2724 12:20:42.915062
2725 12:20:42.915146 Set Vref, RX VrefLevel [Byte0]: 44
2726 12:20:42.918261 [Byte1]: 44
2727 12:20:42.922909
2728 12:20:42.922998 Set Vref, RX VrefLevel [Byte0]: 45
2729 12:20:42.926221 [Byte1]: 45
2730 12:20:42.930752
2731 12:20:42.930838 Set Vref, RX VrefLevel [Byte0]: 46
2732 12:20:42.934264 [Byte1]: 46
2733 12:20:42.938839
2734 12:20:42.938921 Set Vref, RX VrefLevel [Byte0]: 47
2735 12:20:42.941975 [Byte1]: 47
2736 12:20:42.946557
2737 12:20:42.946639 Set Vref, RX VrefLevel [Byte0]: 48
2738 12:20:42.950188 [Byte1]: 48
2739 12:20:42.954360
2740 12:20:42.954442 Set Vref, RX VrefLevel [Byte0]: 49
2741 12:20:42.957921 [Byte1]: 49
2742 12:20:42.962370
2743 12:20:42.962452 Set Vref, RX VrefLevel [Byte0]: 50
2744 12:20:42.965773 [Byte1]: 50
2745 12:20:42.970324
2746 12:20:42.970445 Set Vref, RX VrefLevel [Byte0]: 51
2747 12:20:42.973757 [Byte1]: 51
2748 12:20:42.977982
2749 12:20:42.978095 Set Vref, RX VrefLevel [Byte0]: 52
2750 12:20:42.981342 [Byte1]: 52
2751 12:20:42.985948
2752 12:20:42.986030 Set Vref, RX VrefLevel [Byte0]: 53
2753 12:20:42.989378 [Byte1]: 53
2754 12:20:42.993936
2755 12:20:42.994019 Set Vref, RX VrefLevel [Byte0]: 54
2756 12:20:42.997447 [Byte1]: 54
2757 12:20:43.002241
2758 12:20:43.002326 Set Vref, RX VrefLevel [Byte0]: 55
2759 12:20:43.005268 [Byte1]: 55
2760 12:20:43.009646
2761 12:20:43.009729 Set Vref, RX VrefLevel [Byte0]: 56
2762 12:20:43.013035 [Byte1]: 56
2763 12:20:43.017533
2764 12:20:43.017609 Set Vref, RX VrefLevel [Byte0]: 57
2765 12:20:43.021122 [Byte1]: 57
2766 12:20:43.025417
2767 12:20:43.025500 Set Vref, RX VrefLevel [Byte0]: 58
2768 12:20:43.028985 [Byte1]: 58
2769 12:20:43.033557
2770 12:20:43.033654 Set Vref, RX VrefLevel [Byte0]: 59
2771 12:20:43.036883 [Byte1]: 59
2772 12:20:43.041167
2773 12:20:43.041250 Set Vref, RX VrefLevel [Byte0]: 60
2774 12:20:43.044507 [Byte1]: 60
2775 12:20:43.049021
2776 12:20:43.049099 Set Vref, RX VrefLevel [Byte0]: 61
2777 12:20:43.052652 [Byte1]: 61
2778 12:20:43.057225
2779 12:20:43.057301 Set Vref, RX VrefLevel [Byte0]: 62
2780 12:20:43.060349 [Byte1]: 62
2781 12:20:43.064766
2782 12:20:43.064863 Set Vref, RX VrefLevel [Byte0]: 63
2783 12:20:43.068487 [Byte1]: 63
2784 12:20:43.073100
2785 12:20:43.073183 Set Vref, RX VrefLevel [Byte0]: 64
2786 12:20:43.076024 [Byte1]: 64
2787 12:20:43.080872
2788 12:20:43.080955 Set Vref, RX VrefLevel [Byte0]: 65
2789 12:20:43.084041 [Byte1]: 65
2790 12:20:43.088541
2791 12:20:43.088625 Set Vref, RX VrefLevel [Byte0]: 66
2792 12:20:43.091915 [Byte1]: 66
2793 12:20:43.096459
2794 12:20:43.096542 Set Vref, RX VrefLevel [Byte0]: 67
2795 12:20:43.099787 [Byte1]: 67
2796 12:20:43.104246
2797 12:20:43.104330 Set Vref, RX VrefLevel [Byte0]: 68
2798 12:20:43.107832 [Byte1]: 68
2799 12:20:43.112426
2800 12:20:43.112548 Set Vref, RX VrefLevel [Byte0]: 69
2801 12:20:43.115445 [Byte1]: 69
2802 12:20:43.120321
2803 12:20:43.120442 Set Vref, RX VrefLevel [Byte0]: 70
2804 12:20:43.123439 [Byte1]: 70
2805 12:20:43.127952
2806 12:20:43.128072 Final RX Vref Byte 0 = 58 to rank0
2807 12:20:43.131488 Final RX Vref Byte 1 = 50 to rank0
2808 12:20:43.134646 Final RX Vref Byte 0 = 58 to rank1
2809 12:20:43.138114 Final RX Vref Byte 1 = 50 to rank1==
2810 12:20:43.141248 Dram Type= 6, Freq= 0, CH_0, rank 0
2811 12:20:43.148136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2812 12:20:43.148259 ==
2813 12:20:43.148372 DQS Delay:
2814 12:20:43.148484 DQS0 = 0, DQS1 = 0
2815 12:20:43.151489 DQM Delay:
2816 12:20:43.151608 DQM0 = 123, DQM1 = 109
2817 12:20:43.154644 DQ Delay:
2818 12:20:43.157991 DQ0 =122, DQ1 =124, DQ2 =118, DQ3 =120
2819 12:20:43.161524 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2820 12:20:43.164725 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2821 12:20:43.168306 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2822 12:20:43.168434
2823 12:20:43.168540
2824 12:20:43.174797 [DQSOSCAuto] RK0, (LSB)MR18= 0xb07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
2825 12:20:43.178029 CH0 RK0: MR19=404, MR18=B07
2826 12:20:43.185061 CH0_RK0: MR19=0x404, MR18=0xB07, DQSOSC=405, MR23=63, INC=39, DEC=26
2827 12:20:43.185144
2828 12:20:43.188346 ----->DramcWriteLeveling(PI) begin...
2829 12:20:43.188471 ==
2830 12:20:43.191391 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 12:20:43.194909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 12:20:43.194993 ==
2833 12:20:43.197979 Write leveling (Byte 0): 34 => 34
2834 12:20:43.201661 Write leveling (Byte 1): 30 => 30
2835 12:20:43.205155 DramcWriteLeveling(PI) end<-----
2836 12:20:43.205238
2837 12:20:43.205305 ==
2838 12:20:43.208533 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 12:20:43.211559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 12:20:43.215206 ==
2841 12:20:43.215290 [Gating] SW mode calibration
2842 12:20:43.221718 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2843 12:20:43.228529 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2844 12:20:43.231726 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2845 12:20:43.238246 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 12:20:43.241774 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 12:20:43.244988 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 12:20:43.251711 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 12:20:43.255402 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 12:20:43.258246 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 12:20:43.261827 0 15 28 | B1->B0 | 3333 3232 | 0 0 | (0 0) (1 0)
2852 12:20:43.268566 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2853 12:20:43.271829 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 12:20:43.275267 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 12:20:43.281989 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 12:20:43.285181 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 12:20:43.288675 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 12:20:43.295232 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
2859 12:20:43.298565 1 0 28 | B1->B0 | 3939 4343 | 0 1 | (1 1) (0 0)
2860 12:20:43.302155 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 12:20:43.308661 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 12:20:43.311953 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 12:20:43.315139 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 12:20:43.321726 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 12:20:43.325170 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 12:20:43.328887 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 12:20:43.335088 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2868 12:20:43.338514 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:20:43.342089 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:20:43.345354 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:20:43.352033 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:20:43.355250 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:20:43.358708 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:20:43.365469 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:20:43.368510 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:20:43.372492 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:20:43.378934 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:20:43.382030 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:20:43.385249 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:20:43.392038 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:20:43.395600 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:20:43.398761 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:20:43.405580 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2884 12:20:43.408600 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 12:20:43.411911 Total UI for P1: 0, mck2ui 16
2886 12:20:43.415638 best dqsien dly found for B0: ( 1, 3, 28)
2887 12:20:43.418782 Total UI for P1: 0, mck2ui 16
2888 12:20:43.422305 best dqsien dly found for B1: ( 1, 3, 30)
2889 12:20:43.425466 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2890 12:20:43.429027 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2891 12:20:43.429110
2892 12:20:43.432351 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2893 12:20:43.435724 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2894 12:20:43.438955 [Gating] SW calibration Done
2895 12:20:43.439074 ==
2896 12:20:43.442319 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 12:20:43.445801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 12:20:43.445924 ==
2899 12:20:43.448895 RX Vref Scan: 0
2900 12:20:43.448975
2901 12:20:43.449040 RX Vref 0 -> 0, step: 1
2902 12:20:43.452036
2903 12:20:43.452133 RX Delay -40 -> 252, step: 8
2904 12:20:43.458771 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2905 12:20:43.462425 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2906 12:20:43.465903 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2907 12:20:43.468999 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2908 12:20:43.472467 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2909 12:20:43.475788 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2910 12:20:43.482434 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2911 12:20:43.485553 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2912 12:20:43.489137 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2913 12:20:43.492429 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2914 12:20:43.495494 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2915 12:20:43.502320 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2916 12:20:43.505955 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2917 12:20:43.509124 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2918 12:20:43.512609 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2919 12:20:43.515774 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2920 12:20:43.519291 ==
2921 12:20:43.522434 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 12:20:43.525706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 12:20:43.525790 ==
2924 12:20:43.525857 DQS Delay:
2925 12:20:43.529236 DQS0 = 0, DQS1 = 0
2926 12:20:43.529319 DQM Delay:
2927 12:20:43.532550 DQM0 = 120, DQM1 = 108
2928 12:20:43.532633 DQ Delay:
2929 12:20:43.535687 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2930 12:20:43.539375 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2931 12:20:43.542698 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2932 12:20:43.546025 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2933 12:20:43.546108
2934 12:20:43.546192
2935 12:20:43.546317 ==
2936 12:20:43.549401 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 12:20:43.555626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 12:20:43.555709 ==
2939 12:20:43.555775
2940 12:20:43.555836
2941 12:20:43.555896 TX Vref Scan disable
2942 12:20:43.558915 == TX Byte 0 ==
2943 12:20:43.562445 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2944 12:20:43.565754 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2945 12:20:43.569082 == TX Byte 1 ==
2946 12:20:43.572345 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2947 12:20:43.576000 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2948 12:20:43.579109 ==
2949 12:20:43.582308 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 12:20:43.585552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 12:20:43.585636 ==
2952 12:20:43.597197 TX Vref=22, minBit 0, minWin=24, winSum=407
2953 12:20:43.600626 TX Vref=24, minBit 1, minWin=24, winSum=409
2954 12:20:43.603821 TX Vref=26, minBit 3, minWin=24, winSum=412
2955 12:20:43.607353 TX Vref=28, minBit 1, minWin=25, winSum=416
2956 12:20:43.610947 TX Vref=30, minBit 1, minWin=25, winSum=418
2957 12:20:43.613861 TX Vref=32, minBit 1, minWin=25, winSum=419
2958 12:20:43.620619 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 32
2959 12:20:43.620720
2960 12:20:43.623936 Final TX Range 1 Vref 32
2961 12:20:43.624009
2962 12:20:43.624086 ==
2963 12:20:43.627114 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 12:20:43.630574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 12:20:43.630659 ==
2966 12:20:43.630744
2967 12:20:43.630824
2968 12:20:43.633886 TX Vref Scan disable
2969 12:20:43.637427 == TX Byte 0 ==
2970 12:20:43.640495 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2971 12:20:43.643752 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2972 12:20:43.647334 == TX Byte 1 ==
2973 12:20:43.650776 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2974 12:20:43.653856 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2975 12:20:43.653940
2976 12:20:43.657573 [DATLAT]
2977 12:20:43.657658 Freq=1200, CH0 RK1
2978 12:20:43.657742
2979 12:20:43.660745 DATLAT Default: 0xd
2980 12:20:43.660873 0, 0xFFFF, sum = 0
2981 12:20:43.663971 1, 0xFFFF, sum = 0
2982 12:20:43.664057 2, 0xFFFF, sum = 0
2983 12:20:43.667442 3, 0xFFFF, sum = 0
2984 12:20:43.667528 4, 0xFFFF, sum = 0
2985 12:20:43.670799 5, 0xFFFF, sum = 0
2986 12:20:43.670886 6, 0xFFFF, sum = 0
2987 12:20:43.674103 7, 0xFFFF, sum = 0
2988 12:20:43.674189 8, 0xFFFF, sum = 0
2989 12:20:43.677207 9, 0xFFFF, sum = 0
2990 12:20:43.680878 10, 0xFFFF, sum = 0
2991 12:20:43.680964 11, 0xFFFF, sum = 0
2992 12:20:43.683963 12, 0x0, sum = 1
2993 12:20:43.684048 13, 0x0, sum = 2
2994 12:20:43.684134 14, 0x0, sum = 3
2995 12:20:43.687573 15, 0x0, sum = 4
2996 12:20:43.687659 best_step = 13
2997 12:20:43.687743
2998 12:20:43.687823 ==
2999 12:20:43.690771 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 12:20:43.697334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 12:20:43.697434 ==
3002 12:20:43.697520 RX Vref Scan: 0
3003 12:20:43.697601
3004 12:20:43.700856 RX Vref 0 -> 0, step: 1
3005 12:20:43.700954
3006 12:20:43.704030 RX Delay -21 -> 252, step: 4
3007 12:20:43.707530 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3008 12:20:43.710704 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3009 12:20:43.717378 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3010 12:20:43.720946 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3011 12:20:43.724131 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3012 12:20:43.727312 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3013 12:20:43.730993 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3014 12:20:43.734274 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3015 12:20:43.740872 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3016 12:20:43.744271 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3017 12:20:43.747898 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3018 12:20:43.751069 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3019 12:20:43.754391 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3020 12:20:43.761038 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3021 12:20:43.764496 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3022 12:20:43.767831 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3023 12:20:43.767929 ==
3024 12:20:43.771076 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 12:20:43.774206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 12:20:43.774314 ==
3027 12:20:43.777900 DQS Delay:
3028 12:20:43.777975 DQS0 = 0, DQS1 = 0
3029 12:20:43.781072 DQM Delay:
3030 12:20:43.781177 DQM0 = 120, DQM1 = 107
3031 12:20:43.784695 DQ Delay:
3032 12:20:43.787868 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =116
3033 12:20:43.791139 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3034 12:20:43.794655 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3035 12:20:43.798116 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3036 12:20:43.798197
3037 12:20:43.798262
3038 12:20:43.804431 [DQSOSCAuto] RK1, (LSB)MR18= 0xff7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 404 ps
3039 12:20:43.807668 CH0 RK1: MR19=403, MR18=FF7
3040 12:20:43.814344 CH0_RK1: MR19=0x403, MR18=0xFF7, DQSOSC=404, MR23=63, INC=40, DEC=26
3041 12:20:43.817852 [RxdqsGatingPostProcess] freq 1200
3042 12:20:43.821064 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3043 12:20:43.824442 best DQS0 dly(2T, 0.5T) = (0, 11)
3044 12:20:43.827720 best DQS1 dly(2T, 0.5T) = (0, 12)
3045 12:20:43.831353 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3046 12:20:43.834514 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3047 12:20:43.837684 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 12:20:43.840980 best DQS1 dly(2T, 0.5T) = (0, 11)
3049 12:20:43.844739 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 12:20:43.847719 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3051 12:20:43.850956 Pre-setting of DQS Precalculation
3052 12:20:43.854345 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3053 12:20:43.854466 ==
3054 12:20:43.857890 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 12:20:43.864371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 12:20:43.864492 ==
3057 12:20:43.867814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3058 12:20:43.874168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3059 12:20:43.882848 [CA 0] Center 37 (7~68) winsize 62
3060 12:20:43.886337 [CA 1] Center 37 (7~68) winsize 62
3061 12:20:43.890023 [CA 2] Center 35 (5~65) winsize 61
3062 12:20:43.893132 [CA 3] Center 34 (4~65) winsize 62
3063 12:20:43.896637 [CA 4] Center 34 (4~64) winsize 61
3064 12:20:43.899763 [CA 5] Center 33 (3~64) winsize 62
3065 12:20:43.899885
3066 12:20:43.903291 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3067 12:20:43.903395
3068 12:20:43.906505 [CATrainingPosCal] consider 1 rank data
3069 12:20:43.910053 u2DelayCellTimex100 = 270/100 ps
3070 12:20:43.913330 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3071 12:20:43.916369 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3072 12:20:43.919879 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3073 12:20:43.926604 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3074 12:20:43.929919 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3075 12:20:43.933552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3076 12:20:43.933633
3077 12:20:43.936731 CA PerBit enable=1, Macro0, CA PI delay=33
3078 12:20:43.936838
3079 12:20:43.940210 [CBTSetCACLKResult] CA Dly = 33
3080 12:20:43.940292 CS Dly: 5 (0~36)
3081 12:20:43.940357 ==
3082 12:20:43.943306 Dram Type= 6, Freq= 0, CH_1, rank 1
3083 12:20:43.949989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 12:20:43.950071 ==
3085 12:20:43.953823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3086 12:20:43.960224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3087 12:20:43.968651 [CA 0] Center 38 (8~68) winsize 61
3088 12:20:43.972101 [CA 1] Center 38 (8~68) winsize 61
3089 12:20:43.975211 [CA 2] Center 35 (5~66) winsize 62
3090 12:20:43.978616 [CA 3] Center 34 (4~65) winsize 62
3091 12:20:43.982279 [CA 4] Center 35 (5~65) winsize 61
3092 12:20:43.985412 [CA 5] Center 33 (3~64) winsize 62
3093 12:20:43.985510
3094 12:20:43.989044 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3095 12:20:43.989127
3096 12:20:43.992364 [CATrainingPosCal] consider 2 rank data
3097 12:20:43.995505 u2DelayCellTimex100 = 270/100 ps
3098 12:20:43.999094 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3099 12:20:44.002127 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3100 12:20:44.005579 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3101 12:20:44.012137 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3102 12:20:44.015577 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3103 12:20:44.018668 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3104 12:20:44.018751
3105 12:20:44.022265 CA PerBit enable=1, Macro0, CA PI delay=33
3106 12:20:44.022348
3107 12:20:44.025770 [CBTSetCACLKResult] CA Dly = 33
3108 12:20:44.025852 CS Dly: 6 (0~38)
3109 12:20:44.025917
3110 12:20:44.028884 ----->DramcWriteLeveling(PI) begin...
3111 12:20:44.032292 ==
3112 12:20:44.032374 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 12:20:44.038704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 12:20:44.038787 ==
3115 12:20:44.042348 Write leveling (Byte 0): 25 => 25
3116 12:20:44.045417 Write leveling (Byte 1): 28 => 28
3117 12:20:44.048633 DramcWriteLeveling(PI) end<-----
3118 12:20:44.048748
3119 12:20:44.048845 ==
3120 12:20:44.052241 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 12:20:44.055462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 12:20:44.055537 ==
3123 12:20:44.058785 [Gating] SW mode calibration
3124 12:20:44.065527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3125 12:20:44.069031 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3126 12:20:44.075630 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 12:20:44.079421 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 12:20:44.082231 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 12:20:44.088960 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 12:20:44.092146 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 12:20:44.095511 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3132 12:20:44.102092 0 15 24 | B1->B0 | 2e2e 2b2b | 0 1 | (0 1) (1 0)
3133 12:20:44.105758 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3134 12:20:44.109129 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 12:20:44.115819 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 12:20:44.119111 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 12:20:44.122141 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 12:20:44.125723 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 12:20:44.132135 1 0 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
3140 12:20:44.135691 1 0 24 | B1->B0 | 3c3c 4242 | 0 0 | (1 1) (0 0)
3141 12:20:44.139197 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 12:20:44.145538 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 12:20:44.149074 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 12:20:44.152253 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 12:20:44.159325 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 12:20:44.162164 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 12:20:44.165697 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 12:20:44.172602 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3149 12:20:44.175866 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3150 12:20:44.179001 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:20:44.185798 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:20:44.189111 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:20:44.192210 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:20:44.198950 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:20:44.202414 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:20:44.205734 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:20:44.212411 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:20:44.215867 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:20:44.218979 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:20:44.222645 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:20:44.229019 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:20:44.232597 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:20:44.235789 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3164 12:20:44.242581 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3165 12:20:44.245799 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 12:20:44.248935 Total UI for P1: 0, mck2ui 16
3167 12:20:44.252444 best dqsien dly found for B0: ( 1, 3, 22)
3168 12:20:44.255702 Total UI for P1: 0, mck2ui 16
3169 12:20:44.259304 best dqsien dly found for B1: ( 1, 3, 22)
3170 12:20:44.262679 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3171 12:20:44.265939 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3172 12:20:44.266021
3173 12:20:44.269329 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3174 12:20:44.272757 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3175 12:20:44.276106 [Gating] SW calibration Done
3176 12:20:44.276226 ==
3177 12:20:44.279389 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 12:20:44.282616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 12:20:44.285994 ==
3180 12:20:44.286115 RX Vref Scan: 0
3181 12:20:44.286226
3182 12:20:44.289251 RX Vref 0 -> 0, step: 1
3183 12:20:44.289373
3184 12:20:44.289484 RX Delay -40 -> 252, step: 8
3185 12:20:44.295915 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3186 12:20:44.299527 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3187 12:20:44.302672 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3188 12:20:44.306365 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3189 12:20:44.309527 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3190 12:20:44.316404 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3191 12:20:44.319228 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3192 12:20:44.322880 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3193 12:20:44.325985 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3194 12:20:44.329520 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3195 12:20:44.336107 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3196 12:20:44.339260 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3197 12:20:44.342840 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3198 12:20:44.346209 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3199 12:20:44.349343 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3200 12:20:44.356215 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3201 12:20:44.356333 ==
3202 12:20:44.359821 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 12:20:44.362989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 12:20:44.363107 ==
3205 12:20:44.363220 DQS Delay:
3206 12:20:44.366198 DQS0 = 0, DQS1 = 0
3207 12:20:44.366314 DQM Delay:
3208 12:20:44.369788 DQM0 = 121, DQM1 = 112
3209 12:20:44.369900 DQ Delay:
3210 12:20:44.373117 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3211 12:20:44.376329 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3212 12:20:44.380031 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3213 12:20:44.383132 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3214 12:20:44.383254
3215 12:20:44.383362
3216 12:20:44.383469 ==
3217 12:20:44.386391 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 12:20:44.393140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 12:20:44.393260 ==
3220 12:20:44.393371
3221 12:20:44.393479
3222 12:20:44.393583 TX Vref Scan disable
3223 12:20:44.396340 == TX Byte 0 ==
3224 12:20:44.399982 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3225 12:20:44.406476 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3226 12:20:44.406603 == TX Byte 1 ==
3227 12:20:44.410125 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3228 12:20:44.413210 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3229 12:20:44.416555 ==
3230 12:20:44.420023 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 12:20:44.423578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 12:20:44.423697 ==
3233 12:20:44.434467 TX Vref=22, minBit 10, minWin=24, winSum=405
3234 12:20:44.437514 TX Vref=24, minBit 10, minWin=24, winSum=410
3235 12:20:44.441273 TX Vref=26, minBit 2, minWin=25, winSum=417
3236 12:20:44.444468 TX Vref=28, minBit 10, minWin=25, winSum=423
3237 12:20:44.448074 TX Vref=30, minBit 1, minWin=26, winSum=427
3238 12:20:44.451506 TX Vref=32, minBit 9, minWin=25, winSum=423
3239 12:20:44.457637 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3240 12:20:44.457757
3241 12:20:44.461284 Final TX Range 1 Vref 30
3242 12:20:44.461403
3243 12:20:44.461514 ==
3244 12:20:44.464478 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 12:20:44.467636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 12:20:44.467757 ==
3247 12:20:44.467869
3248 12:20:44.471290
3249 12:20:44.471413 TX Vref Scan disable
3250 12:20:44.474461 == TX Byte 0 ==
3251 12:20:44.477945 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3252 12:20:44.481490 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3253 12:20:44.484651 == TX Byte 1 ==
3254 12:20:44.488075 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3255 12:20:44.491411 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3256 12:20:44.491534
3257 12:20:44.494716 [DATLAT]
3258 12:20:44.494824 Freq=1200, CH1 RK0
3259 12:20:44.494918
3260 12:20:44.498129 DATLAT Default: 0xd
3261 12:20:44.498226 0, 0xFFFF, sum = 0
3262 12:20:44.501202 1, 0xFFFF, sum = 0
3263 12:20:44.501300 2, 0xFFFF, sum = 0
3264 12:20:44.504791 3, 0xFFFF, sum = 0
3265 12:20:44.504888 4, 0xFFFF, sum = 0
3266 12:20:44.508084 5, 0xFFFF, sum = 0
3267 12:20:44.508246 6, 0xFFFF, sum = 0
3268 12:20:44.511393 7, 0xFFFF, sum = 0
3269 12:20:44.511524 8, 0xFFFF, sum = 0
3270 12:20:44.514559 9, 0xFFFF, sum = 0
3271 12:20:44.514681 10, 0xFFFF, sum = 0
3272 12:20:44.518272 11, 0xFFFF, sum = 0
3273 12:20:44.518424 12, 0x0, sum = 1
3274 12:20:44.521386 13, 0x0, sum = 2
3275 12:20:44.521518 14, 0x0, sum = 3
3276 12:20:44.525003 15, 0x0, sum = 4
3277 12:20:44.525136 best_step = 13
3278 12:20:44.525249
3279 12:20:44.525366 ==
3280 12:20:44.528074 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 12:20:44.535009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 12:20:44.535145 ==
3283 12:20:44.535260 RX Vref Scan: 1
3284 12:20:44.535382
3285 12:20:44.538258 Set Vref Range= 32 -> 127
3286 12:20:44.538389
3287 12:20:44.541382 RX Vref 32 -> 127, step: 1
3288 12:20:44.541503
3289 12:20:44.544835 RX Delay -13 -> 252, step: 4
3290 12:20:44.544956
3291 12:20:44.545075 Set Vref, RX VrefLevel [Byte0]: 32
3292 12:20:44.548041 [Byte1]: 32
3293 12:20:44.552686
3294 12:20:44.552854 Set Vref, RX VrefLevel [Byte0]: 33
3295 12:20:44.556328 [Byte1]: 33
3296 12:20:44.560894
3297 12:20:44.561025 Set Vref, RX VrefLevel [Byte0]: 34
3298 12:20:44.564054 [Byte1]: 34
3299 12:20:44.568646
3300 12:20:44.568809 Set Vref, RX VrefLevel [Byte0]: 35
3301 12:20:44.571832 [Byte1]: 35
3302 12:20:44.576355
3303 12:20:44.576475 Set Vref, RX VrefLevel [Byte0]: 36
3304 12:20:44.579589 [Byte1]: 36
3305 12:20:44.584112
3306 12:20:44.584237 Set Vref, RX VrefLevel [Byte0]: 37
3307 12:20:44.587713 [Byte1]: 37
3308 12:20:44.592144
3309 12:20:44.592265 Set Vref, RX VrefLevel [Byte0]: 38
3310 12:20:44.595571 [Byte1]: 38
3311 12:20:44.600481
3312 12:20:44.600601 Set Vref, RX VrefLevel [Byte0]: 39
3313 12:20:44.603749 [Byte1]: 39
3314 12:20:44.608021
3315 12:20:44.608154 Set Vref, RX VrefLevel [Byte0]: 40
3316 12:20:44.611462 [Byte1]: 40
3317 12:20:44.615776
3318 12:20:44.615909 Set Vref, RX VrefLevel [Byte0]: 41
3319 12:20:44.619120 [Byte1]: 41
3320 12:20:44.623638
3321 12:20:44.623773 Set Vref, RX VrefLevel [Byte0]: 42
3322 12:20:44.626886 [Byte1]: 42
3323 12:20:44.631741
3324 12:20:44.631861 Set Vref, RX VrefLevel [Byte0]: 43
3325 12:20:44.634899 [Byte1]: 43
3326 12:20:44.639380
3327 12:20:44.639508 Set Vref, RX VrefLevel [Byte0]: 44
3328 12:20:44.642958 [Byte1]: 44
3329 12:20:44.647365
3330 12:20:44.647484 Set Vref, RX VrefLevel [Byte0]: 45
3331 12:20:44.650685 [Byte1]: 45
3332 12:20:44.655212
3333 12:20:44.655293 Set Vref, RX VrefLevel [Byte0]: 46
3334 12:20:44.658567 [Byte1]: 46
3335 12:20:44.663764
3336 12:20:44.663844 Set Vref, RX VrefLevel [Byte0]: 47
3337 12:20:44.666663 [Byte1]: 47
3338 12:20:44.671122
3339 12:20:44.671203 Set Vref, RX VrefLevel [Byte0]: 48
3340 12:20:44.674268 [Byte1]: 48
3341 12:20:44.678782
3342 12:20:44.678862 Set Vref, RX VrefLevel [Byte0]: 49
3343 12:20:44.682351 [Byte1]: 49
3344 12:20:44.687076
3345 12:20:44.687159 Set Vref, RX VrefLevel [Byte0]: 50
3346 12:20:44.690263 [Byte1]: 50
3347 12:20:44.694831
3348 12:20:44.694914 Set Vref, RX VrefLevel [Byte0]: 51
3349 12:20:44.697880 [Byte1]: 51
3350 12:20:44.702398
3351 12:20:44.702481 Set Vref, RX VrefLevel [Byte0]: 52
3352 12:20:44.706090 [Byte1]: 52
3353 12:20:44.710553
3354 12:20:44.710636 Set Vref, RX VrefLevel [Byte0]: 53
3355 12:20:44.713992 [Byte1]: 53
3356 12:20:44.718617
3357 12:20:44.718700 Set Vref, RX VrefLevel [Byte0]: 54
3358 12:20:44.721812 [Byte1]: 54
3359 12:20:44.726561
3360 12:20:44.726647 Set Vref, RX VrefLevel [Byte0]: 55
3361 12:20:44.729703 [Byte1]: 55
3362 12:20:44.734069
3363 12:20:44.734173 Set Vref, RX VrefLevel [Byte0]: 56
3364 12:20:44.737576 [Byte1]: 56
3365 12:20:44.742102
3366 12:20:44.742185 Set Vref, RX VrefLevel [Byte0]: 57
3367 12:20:44.745216 [Byte1]: 57
3368 12:20:44.750024
3369 12:20:44.753064 Set Vref, RX VrefLevel [Byte0]: 58
3370 12:20:44.753148 [Byte1]: 58
3371 12:20:44.758006
3372 12:20:44.758089 Set Vref, RX VrefLevel [Byte0]: 59
3373 12:20:44.761165 [Byte1]: 59
3374 12:20:44.765963
3375 12:20:44.766046 Set Vref, RX VrefLevel [Byte0]: 60
3376 12:20:44.768985 [Byte1]: 60
3377 12:20:44.773464
3378 12:20:44.773546 Set Vref, RX VrefLevel [Byte0]: 61
3379 12:20:44.777128 [Byte1]: 61
3380 12:20:44.781574
3381 12:20:44.781655 Set Vref, RX VrefLevel [Byte0]: 62
3382 12:20:44.784754 [Byte1]: 62
3383 12:20:44.789548
3384 12:20:44.789629 Set Vref, RX VrefLevel [Byte0]: 63
3385 12:20:44.792760 [Byte1]: 63
3386 12:20:44.797361
3387 12:20:44.797444 Set Vref, RX VrefLevel [Byte0]: 64
3388 12:20:44.800495 [Byte1]: 64
3389 12:20:44.805295
3390 12:20:44.805376 Set Vref, RX VrefLevel [Byte0]: 65
3391 12:20:44.808372 [Byte1]: 65
3392 12:20:44.813118
3393 12:20:44.813229 Set Vref, RX VrefLevel [Byte0]: 66
3394 12:20:44.816377 [Byte1]: 66
3395 12:20:44.820986
3396 12:20:44.821087 Set Vref, RX VrefLevel [Byte0]: 67
3397 12:20:44.824403 [Byte1]: 67
3398 12:20:44.829001
3399 12:20:44.829084 Final RX Vref Byte 0 = 51 to rank0
3400 12:20:44.832328 Final RX Vref Byte 1 = 57 to rank0
3401 12:20:44.835562 Final RX Vref Byte 0 = 51 to rank1
3402 12:20:44.838859 Final RX Vref Byte 1 = 57 to rank1==
3403 12:20:44.842378 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 12:20:44.848724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 12:20:44.848852 ==
3406 12:20:44.848919 DQS Delay:
3407 12:20:44.848980 DQS0 = 0, DQS1 = 0
3408 12:20:44.851930 DQM Delay:
3409 12:20:44.852009 DQM0 = 119, DQM1 = 113
3410 12:20:44.855324 DQ Delay:
3411 12:20:44.858613 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3412 12:20:44.862238 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3413 12:20:44.865299 DQ8 =102, DQ9 =100, DQ10 =116, DQ11 =108
3414 12:20:44.868733 DQ12 =124, DQ13 =118, DQ14 =120, DQ15 =120
3415 12:20:44.868846
3416 12:20:44.868908
3417 12:20:44.875492 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3418 12:20:44.878825 CH1 RK0: MR19=404, MR18=518
3419 12:20:44.885446 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3420 12:20:44.885546
3421 12:20:44.889116 ----->DramcWriteLeveling(PI) begin...
3422 12:20:44.889202 ==
3423 12:20:44.892242 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 12:20:44.895684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 12:20:44.895780 ==
3426 12:20:44.898924 Write leveling (Byte 0): 25 => 25
3427 12:20:44.902423 Write leveling (Byte 1): 30 => 30
3428 12:20:44.905971 DramcWriteLeveling(PI) end<-----
3429 12:20:44.906056
3430 12:20:44.906140 ==
3431 12:20:44.908965 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 12:20:44.912517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 12:20:44.915654 ==
3434 12:20:44.915737 [Gating] SW mode calibration
3435 12:20:44.922358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 12:20:44.929673 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 12:20:44.932299 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 12:20:44.939204 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 12:20:44.942602 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 12:20:44.945788 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 12:20:44.952442 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 12:20:44.955819 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 12:20:44.959252 0 15 24 | B1->B0 | 2a2a 3434 | 0 1 | (0 1) (1 0)
3444 12:20:44.965988 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (1 0)
3445 12:20:44.969339 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 12:20:44.972779 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 12:20:44.975858 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 12:20:44.982941 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 12:20:44.985751 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 12:20:44.989342 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 12:20:44.995945 1 0 24 | B1->B0 | 3c3c 2c2c | 0 0 | (0 0) (0 0)
3452 12:20:44.999071 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3453 12:20:45.003056 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 12:20:45.009483 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 12:20:45.012971 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 12:20:45.015942 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 12:20:45.022760 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 12:20:45.026269 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 12:20:45.029496 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3460 12:20:45.035990 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3461 12:20:45.039212 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:20:45.042817 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:20:45.049343 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:20:45.052676 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:20:45.055864 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:20:45.062473 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:20:45.066050 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:20:45.069229 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:20:45.072698 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:20:45.079337 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 12:20:45.082439 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:20:45.086062 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:20:45.092679 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:20:45.095977 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:20:45.099258 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 12:20:45.106283 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3477 12:20:45.109305 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 12:20:45.112999 Total UI for P1: 0, mck2ui 16
3479 12:20:45.116138 best dqsien dly found for B0: ( 1, 3, 26)
3480 12:20:45.119442 Total UI for P1: 0, mck2ui 16
3481 12:20:45.122798 best dqsien dly found for B1: ( 1, 3, 26)
3482 12:20:45.125952 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3483 12:20:45.129261 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3484 12:20:45.129366
3485 12:20:45.132494 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 12:20:45.136106 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3487 12:20:45.139255 [Gating] SW calibration Done
3488 12:20:45.139353 ==
3489 12:20:45.142934 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 12:20:45.145730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 12:20:45.149108 ==
3492 12:20:45.149188 RX Vref Scan: 0
3493 12:20:45.149256
3494 12:20:45.152459 RX Vref 0 -> 0, step: 1
3495 12:20:45.152553
3496 12:20:45.155651 RX Delay -40 -> 252, step: 8
3497 12:20:45.159055 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3498 12:20:45.162711 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3499 12:20:45.165711 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3500 12:20:45.168839 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3501 12:20:45.175635 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3502 12:20:45.179071 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3503 12:20:45.182317 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3504 12:20:45.185797 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3505 12:20:45.189011 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3506 12:20:45.192557 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3507 12:20:45.198854 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3508 12:20:45.202490 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3509 12:20:45.205671 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3510 12:20:45.208707 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3511 12:20:45.215630 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3512 12:20:45.218620 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3513 12:20:45.218704 ==
3514 12:20:45.222009 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 12:20:45.225473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 12:20:45.225574 ==
3517 12:20:45.228742 DQS Delay:
3518 12:20:45.228882 DQS0 = 0, DQS1 = 0
3519 12:20:45.228981 DQM Delay:
3520 12:20:45.232090 DQM0 = 120, DQM1 = 112
3521 12:20:45.232191 DQ Delay:
3522 12:20:45.235243 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3523 12:20:45.238829 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3524 12:20:45.241962 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3525 12:20:45.248529 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3526 12:20:45.248613
3527 12:20:45.248680
3528 12:20:45.248793 ==
3529 12:20:45.251805 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 12:20:45.255201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 12:20:45.255285 ==
3532 12:20:45.255350
3533 12:20:45.255410
3534 12:20:45.258569 TX Vref Scan disable
3535 12:20:45.258698 == TX Byte 0 ==
3536 12:20:45.265318 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3537 12:20:45.268696 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3538 12:20:45.268853 == TX Byte 1 ==
3539 12:20:45.274953 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3540 12:20:45.278077 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3541 12:20:45.278177 ==
3542 12:20:45.281604 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 12:20:45.285056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 12:20:45.285140 ==
3545 12:20:45.298170 TX Vref=22, minBit 3, minWin=25, winSum=416
3546 12:20:45.301330 TX Vref=24, minBit 1, minWin=26, winSum=421
3547 12:20:45.304891 TX Vref=26, minBit 3, minWin=26, winSum=428
3548 12:20:45.308092 TX Vref=28, minBit 1, minWin=26, winSum=432
3549 12:20:45.311669 TX Vref=30, minBit 10, minWin=26, winSum=434
3550 12:20:45.317825 TX Vref=32, minBit 1, minWin=26, winSum=430
3551 12:20:45.321420 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 30
3552 12:20:45.321503
3553 12:20:45.324483 Final TX Range 1 Vref 30
3554 12:20:45.324567
3555 12:20:45.324681 ==
3556 12:20:45.327869 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 12:20:45.331358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 12:20:45.334579 ==
3559 12:20:45.334658
3560 12:20:45.334747
3561 12:20:45.334828 TX Vref Scan disable
3562 12:20:45.337903 == TX Byte 0 ==
3563 12:20:45.341169 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3564 12:20:45.347805 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3565 12:20:45.347882 == TX Byte 1 ==
3566 12:20:45.350890 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3567 12:20:45.357868 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3568 12:20:45.357972
3569 12:20:45.358056 [DATLAT]
3570 12:20:45.358154 Freq=1200, CH1 RK1
3571 12:20:45.358260
3572 12:20:45.360954 DATLAT Default: 0xd
3573 12:20:45.361061 0, 0xFFFF, sum = 0
3574 12:20:45.364270 1, 0xFFFF, sum = 0
3575 12:20:45.367647 2, 0xFFFF, sum = 0
3576 12:20:45.367728 3, 0xFFFF, sum = 0
3577 12:20:45.371312 4, 0xFFFF, sum = 0
3578 12:20:45.371434 5, 0xFFFF, sum = 0
3579 12:20:45.374444 6, 0xFFFF, sum = 0
3580 12:20:45.374529 7, 0xFFFF, sum = 0
3581 12:20:45.377776 8, 0xFFFF, sum = 0
3582 12:20:45.377857 9, 0xFFFF, sum = 0
3583 12:20:45.380972 10, 0xFFFF, sum = 0
3584 12:20:45.381047 11, 0xFFFF, sum = 0
3585 12:20:45.384681 12, 0x0, sum = 1
3586 12:20:45.384801 13, 0x0, sum = 2
3587 12:20:45.387837 14, 0x0, sum = 3
3588 12:20:45.387911 15, 0x0, sum = 4
3589 12:20:45.387975 best_step = 13
3590 12:20:45.390944
3591 12:20:45.391052 ==
3592 12:20:45.394595 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 12:20:45.397650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 12:20:45.397751 ==
3595 12:20:45.397843 RX Vref Scan: 0
3596 12:20:45.397931
3597 12:20:45.400847 RX Vref 0 -> 0, step: 1
3598 12:20:45.400947
3599 12:20:45.404519 RX Delay -13 -> 252, step: 4
3600 12:20:45.407755 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3601 12:20:45.414472 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3602 12:20:45.417679 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3603 12:20:45.421286 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3604 12:20:45.424434 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3605 12:20:45.427577 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3606 12:20:45.434417 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3607 12:20:45.438026 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3608 12:20:45.441052 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3609 12:20:45.444562 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3610 12:20:45.447690 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3611 12:20:45.454552 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3612 12:20:45.457825 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3613 12:20:45.461191 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3614 12:20:45.464131 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3615 12:20:45.467933 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3616 12:20:45.471035 ==
3617 12:20:45.471225 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 12:20:45.477524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 12:20:45.477603 ==
3620 12:20:45.477671 DQS Delay:
3621 12:20:45.480870 DQS0 = 0, DQS1 = 0
3622 12:20:45.480950 DQM Delay:
3623 12:20:45.484245 DQM0 = 119, DQM1 = 113
3624 12:20:45.484346 DQ Delay:
3625 12:20:45.488001 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3626 12:20:45.490889 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3627 12:20:45.494444 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3628 12:20:45.497662 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3629 12:20:45.497781
3630 12:20:45.497893
3631 12:20:45.507642 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3632 12:20:45.507744 CH1 RK1: MR19=403, MR18=8ED
3633 12:20:45.514625 CH1_RK1: MR19=0x403, MR18=0x8ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3634 12:20:45.518270 [RxdqsGatingPostProcess] freq 1200
3635 12:20:45.524091 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 12:20:45.527746 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 12:20:45.530865 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 12:20:45.534148 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 12:20:45.537460 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 12:20:45.540680 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 12:20:45.540804 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 12:20:45.544203 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 12:20:45.547816 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 12:20:45.550763 Pre-setting of DQS Precalculation
3645 12:20:45.557631 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 12:20:45.564082 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 12:20:45.570806 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 12:20:45.570914
3649 12:20:45.571006
3650 12:20:45.574077 [Calibration Summary] 2400 Mbps
3651 12:20:45.577999 CH 0, Rank 0
3652 12:20:45.578084 SW Impedance : PASS
3653 12:20:45.580915 DUTY Scan : NO K
3654 12:20:45.580994 ZQ Calibration : PASS
3655 12:20:45.584097 Jitter Meter : NO K
3656 12:20:45.587462 CBT Training : PASS
3657 12:20:45.587560 Write leveling : PASS
3658 12:20:45.590470 RX DQS gating : PASS
3659 12:20:45.594101 RX DQ/DQS(RDDQC) : PASS
3660 12:20:45.594200 TX DQ/DQS : PASS
3661 12:20:45.597620 RX DATLAT : PASS
3662 12:20:45.601081 RX DQ/DQS(Engine): PASS
3663 12:20:45.601177 TX OE : NO K
3664 12:20:45.603981 All Pass.
3665 12:20:45.604077
3666 12:20:45.604168 CH 0, Rank 1
3667 12:20:45.607168 SW Impedance : PASS
3668 12:20:45.607267 DUTY Scan : NO K
3669 12:20:45.610821 ZQ Calibration : PASS
3670 12:20:45.613995 Jitter Meter : NO K
3671 12:20:45.614090 CBT Training : PASS
3672 12:20:45.617773 Write leveling : PASS
3673 12:20:45.620833 RX DQS gating : PASS
3674 12:20:45.620916 RX DQ/DQS(RDDQC) : PASS
3675 12:20:45.623989 TX DQ/DQS : PASS
3676 12:20:45.624091 RX DATLAT : PASS
3677 12:20:45.627134 RX DQ/DQS(Engine): PASS
3678 12:20:45.630422 TX OE : NO K
3679 12:20:45.630523 All Pass.
3680 12:20:45.630614
3681 12:20:45.630702 CH 1, Rank 0
3682 12:20:45.633961 SW Impedance : PASS
3683 12:20:45.637114 DUTY Scan : NO K
3684 12:20:45.637216 ZQ Calibration : PASS
3685 12:20:45.640669 Jitter Meter : NO K
3686 12:20:45.643744 CBT Training : PASS
3687 12:20:45.643838 Write leveling : PASS
3688 12:20:45.647012 RX DQS gating : PASS
3689 12:20:45.650428 RX DQ/DQS(RDDQC) : PASS
3690 12:20:45.650527 TX DQ/DQS : PASS
3691 12:20:45.654035 RX DATLAT : PASS
3692 12:20:45.657237 RX DQ/DQS(Engine): PASS
3693 12:20:45.657332 TX OE : NO K
3694 12:20:45.660229 All Pass.
3695 12:20:45.660322
3696 12:20:45.660415 CH 1, Rank 1
3697 12:20:45.663894 SW Impedance : PASS
3698 12:20:45.663987 DUTY Scan : NO K
3699 12:20:45.667070 ZQ Calibration : PASS
3700 12:20:45.670544 Jitter Meter : NO K
3701 12:20:45.670672 CBT Training : PASS
3702 12:20:45.674069 Write leveling : PASS
3703 12:20:45.674153 RX DQS gating : PASS
3704 12:20:45.677454 RX DQ/DQS(RDDQC) : PASS
3705 12:20:45.680784 TX DQ/DQS : PASS
3706 12:20:45.680867 RX DATLAT : PASS
3707 12:20:45.683987 RX DQ/DQS(Engine): PASS
3708 12:20:45.687415 TX OE : NO K
3709 12:20:45.687497 All Pass.
3710 12:20:45.687563
3711 12:20:45.690495 DramC Write-DBI off
3712 12:20:45.690607 PER_BANK_REFRESH: Hybrid Mode
3713 12:20:45.693953 TX_TRACKING: ON
3714 12:20:45.700697 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 12:20:45.707149 [FAST_K] Save calibration result to emmc
3716 12:20:45.710342 dramc_set_vcore_voltage set vcore to 650000
3717 12:20:45.710419 Read voltage for 600, 5
3718 12:20:45.713916 Vio18 = 0
3719 12:20:45.713999 Vcore = 650000
3720 12:20:45.714066 Vdram = 0
3721 12:20:45.717115 Vddq = 0
3722 12:20:45.717198 Vmddr = 0
3723 12:20:45.720617 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 12:20:45.727042 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 12:20:45.730517 MEM_TYPE=3, freq_sel=19
3726 12:20:45.734258 sv_algorithm_assistance_LP4_1600
3727 12:20:45.737198 ============ PULL DRAM RESETB DOWN ============
3728 12:20:45.740375 ========== PULL DRAM RESETB DOWN end =========
3729 12:20:45.743794 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 12:20:45.747291 ===================================
3731 12:20:45.750408 LPDDR4 DRAM CONFIGURATION
3732 12:20:45.754038 ===================================
3733 12:20:45.757140 EX_ROW_EN[0] = 0x0
3734 12:20:45.757223 EX_ROW_EN[1] = 0x0
3735 12:20:45.760690 LP4Y_EN = 0x0
3736 12:20:45.760805 WORK_FSP = 0x0
3737 12:20:45.763861 WL = 0x2
3738 12:20:45.763942 RL = 0x2
3739 12:20:45.766975 BL = 0x2
3740 12:20:45.767057 RPST = 0x0
3741 12:20:45.770163 RD_PRE = 0x0
3742 12:20:45.773696 WR_PRE = 0x1
3743 12:20:45.773777 WR_PST = 0x0
3744 12:20:45.777256 DBI_WR = 0x0
3745 12:20:45.777338 DBI_RD = 0x0
3746 12:20:45.780267 OTF = 0x1
3747 12:20:45.783591 ===================================
3748 12:20:45.787075 ===================================
3749 12:20:45.787158 ANA top config
3750 12:20:45.790732 ===================================
3751 12:20:45.793596 DLL_ASYNC_EN = 0
3752 12:20:45.793684 ALL_SLAVE_EN = 1
3753 12:20:45.797038 NEW_RANK_MODE = 1
3754 12:20:45.800484 DLL_IDLE_MODE = 1
3755 12:20:45.804001 LP45_APHY_COMB_EN = 1
3756 12:20:45.807005 TX_ODT_DIS = 1
3757 12:20:45.807157 NEW_8X_MODE = 1
3758 12:20:45.810277 ===================================
3759 12:20:45.813807 ===================================
3760 12:20:45.816854 data_rate = 1200
3761 12:20:45.820511 CKR = 1
3762 12:20:45.823668 DQ_P2S_RATIO = 8
3763 12:20:45.826882 ===================================
3764 12:20:45.830410 CA_P2S_RATIO = 8
3765 12:20:45.833824 DQ_CA_OPEN = 0
3766 12:20:45.833908 DQ_SEMI_OPEN = 0
3767 12:20:45.837184 CA_SEMI_OPEN = 0
3768 12:20:45.840061 CA_FULL_RATE = 0
3769 12:20:45.843610 DQ_CKDIV4_EN = 1
3770 12:20:45.846798 CA_CKDIV4_EN = 1
3771 12:20:45.850246 CA_PREDIV_EN = 0
3772 12:20:45.850329 PH8_DLY = 0
3773 12:20:45.853388 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 12:20:45.856632 DQ_AAMCK_DIV = 4
3775 12:20:45.860275 CA_AAMCK_DIV = 4
3776 12:20:45.863467 CA_ADMCK_DIV = 4
3777 12:20:45.866546 DQ_TRACK_CA_EN = 0
3778 12:20:45.866629 CA_PICK = 600
3779 12:20:45.870347 CA_MCKIO = 600
3780 12:20:45.873546 MCKIO_SEMI = 0
3781 12:20:45.876634 PLL_FREQ = 2288
3782 12:20:45.880037 DQ_UI_PI_RATIO = 32
3783 12:20:45.883114 CA_UI_PI_RATIO = 0
3784 12:20:45.886478 ===================================
3785 12:20:45.890073 ===================================
3786 12:20:45.890157 memory_type:LPDDR4
3787 12:20:45.893261 GP_NUM : 10
3788 12:20:45.896379 SRAM_EN : 1
3789 12:20:45.896465 MD32_EN : 0
3790 12:20:45.899953 ===================================
3791 12:20:45.903380 [ANA_INIT] >>>>>>>>>>>>>>
3792 12:20:45.906309 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 12:20:45.909720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 12:20:45.913129 ===================================
3795 12:20:45.916630 data_rate = 1200,PCW = 0X5800
3796 12:20:45.919842 ===================================
3797 12:20:45.923277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 12:20:45.926374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 12:20:45.933001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 12:20:45.936210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 12:20:45.939937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 12:20:45.943131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 12:20:45.946205 [ANA_INIT] flow start
3804 12:20:45.949467 [ANA_INIT] PLL >>>>>>>>
3805 12:20:45.949543 [ANA_INIT] PLL <<<<<<<<
3806 12:20:45.952961 [ANA_INIT] MIDPI >>>>>>>>
3807 12:20:45.956480 [ANA_INIT] MIDPI <<<<<<<<
3808 12:20:45.959710 [ANA_INIT] DLL >>>>>>>>
3809 12:20:45.959807 [ANA_INIT] flow end
3810 12:20:45.963036 ============ LP4 DIFF to SE enter ============
3811 12:20:45.969347 ============ LP4 DIFF to SE exit ============
3812 12:20:45.969427 [ANA_INIT] <<<<<<<<<<<<<
3813 12:20:45.973089 [Flow] Enable top DCM control >>>>>
3814 12:20:45.976132 [Flow] Enable top DCM control <<<<<
3815 12:20:45.979757 Enable DLL master slave shuffle
3816 12:20:45.986185 ==============================================================
3817 12:20:45.986266 Gating Mode config
3818 12:20:45.992729 ==============================================================
3819 12:20:45.996335 Config description:
3820 12:20:46.006418 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 12:20:46.009513 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 12:20:46.016487 SELPH_MODE 0: By rank 1: By Phase
3823 12:20:46.023107 ==============================================================
3824 12:20:46.023190 GAT_TRACK_EN = 1
3825 12:20:46.026545 RX_GATING_MODE = 2
3826 12:20:46.029564 RX_GATING_TRACK_MODE = 2
3827 12:20:46.033024 SELPH_MODE = 1
3828 12:20:46.036346 PICG_EARLY_EN = 1
3829 12:20:46.039292 VALID_LAT_VALUE = 1
3830 12:20:46.046452 ==============================================================
3831 12:20:46.049571 Enter into Gating configuration >>>>
3832 12:20:46.052812 Exit from Gating configuration <<<<
3833 12:20:46.056250 Enter into DVFS_PRE_config >>>>>
3834 12:20:46.065968 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 12:20:46.069662 Exit from DVFS_PRE_config <<<<<
3836 12:20:46.072796 Enter into PICG configuration >>>>
3837 12:20:46.076392 Exit from PICG configuration <<<<
3838 12:20:46.079518 [RX_INPUT] configuration >>>>>
3839 12:20:46.079606 [RX_INPUT] configuration <<<<<
3840 12:20:46.086419 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 12:20:46.093019 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 12:20:46.095946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 12:20:46.102893 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 12:20:46.109760 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 12:20:46.116333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 12:20:46.119527 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 12:20:46.122836 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 12:20:46.129336 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 12:20:46.132470 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 12:20:46.135911 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 12:20:46.142501 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 12:20:46.146266 ===================================
3853 12:20:46.146352 LPDDR4 DRAM CONFIGURATION
3854 12:20:46.149334 ===================================
3855 12:20:46.152560 EX_ROW_EN[0] = 0x0
3856 12:20:46.152642 EX_ROW_EN[1] = 0x0
3857 12:20:46.156156 LP4Y_EN = 0x0
3858 12:20:46.156234 WORK_FSP = 0x0
3859 12:20:46.159342 WL = 0x2
3860 12:20:46.162781 RL = 0x2
3861 12:20:46.162857 BL = 0x2
3862 12:20:46.165878 RPST = 0x0
3863 12:20:46.165986 RD_PRE = 0x0
3864 12:20:46.169188 WR_PRE = 0x1
3865 12:20:46.169261 WR_PST = 0x0
3866 12:20:46.172670 DBI_WR = 0x0
3867 12:20:46.172832 DBI_RD = 0x0
3868 12:20:46.175857 OTF = 0x1
3869 12:20:46.179075 ===================================
3870 12:20:46.182560 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 12:20:46.186113 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 12:20:46.189490 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 12:20:46.192420 ===================================
3874 12:20:46.195955 LPDDR4 DRAM CONFIGURATION
3875 12:20:46.199302 ===================================
3876 12:20:46.202430 EX_ROW_EN[0] = 0x10
3877 12:20:46.202564 EX_ROW_EN[1] = 0x0
3878 12:20:46.205753 LP4Y_EN = 0x0
3879 12:20:46.205884 WORK_FSP = 0x0
3880 12:20:46.209223 WL = 0x2
3881 12:20:46.209347 RL = 0x2
3882 12:20:46.212381 BL = 0x2
3883 12:20:46.212505 RPST = 0x0
3884 12:20:46.215637 RD_PRE = 0x0
3885 12:20:46.215763 WR_PRE = 0x1
3886 12:20:46.219358 WR_PST = 0x0
3887 12:20:46.222297 DBI_WR = 0x0
3888 12:20:46.222421 DBI_RD = 0x0
3889 12:20:46.225638 OTF = 0x1
3890 12:20:46.229028 ===================================
3891 12:20:46.232414 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 12:20:46.237820 nWR fixed to 30
3893 12:20:46.240865 [ModeRegInit_LP4] CH0 RK0
3894 12:20:46.240972 [ModeRegInit_LP4] CH0 RK1
3895 12:20:46.244175 [ModeRegInit_LP4] CH1 RK0
3896 12:20:46.247811 [ModeRegInit_LP4] CH1 RK1
3897 12:20:46.247904 match AC timing 17
3898 12:20:46.254244 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 12:20:46.257436 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 12:20:46.260718 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 12:20:46.267798 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 12:20:46.271108 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 12:20:46.271189 ==
3904 12:20:46.274348 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 12:20:46.277553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 12:20:46.277633 ==
3907 12:20:46.284281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 12:20:46.290665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3909 12:20:46.294327 [CA 0] Center 36 (5~67) winsize 63
3910 12:20:46.297451 [CA 1] Center 36 (6~67) winsize 62
3911 12:20:46.300847 [CA 2] Center 34 (4~65) winsize 62
3912 12:20:46.304275 [CA 3] Center 34 (3~65) winsize 63
3913 12:20:46.307271 [CA 4] Center 33 (3~64) winsize 62
3914 12:20:46.310795 [CA 5] Center 33 (2~64) winsize 63
3915 12:20:46.310922
3916 12:20:46.313890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3917 12:20:46.314019
3918 12:20:46.317669 [CATrainingPosCal] consider 1 rank data
3919 12:20:46.320684 u2DelayCellTimex100 = 270/100 ps
3920 12:20:46.323815 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3921 12:20:46.327284 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3922 12:20:46.330740 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3923 12:20:46.334091 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3924 12:20:46.337600 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3925 12:20:46.340678 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3926 12:20:46.343876
3927 12:20:46.347565 CA PerBit enable=1, Macro0, CA PI delay=33
3928 12:20:46.347648
3929 12:20:46.350635 [CBTSetCACLKResult] CA Dly = 33
3930 12:20:46.350728 CS Dly: 5 (0~36)
3931 12:20:46.350813 ==
3932 12:20:46.353897 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 12:20:46.357326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 12:20:46.357407 ==
3935 12:20:46.364053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 12:20:46.370358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3937 12:20:46.373824 [CA 0] Center 36 (6~67) winsize 62
3938 12:20:46.377044 [CA 1] Center 36 (6~67) winsize 62
3939 12:20:46.380405 [CA 2] Center 35 (4~66) winsize 63
3940 12:20:46.383612 [CA 3] Center 35 (4~66) winsize 63
3941 12:20:46.387186 [CA 4] Center 34 (3~65) winsize 63
3942 12:20:46.390350 [CA 5] Center 34 (3~65) winsize 63
3943 12:20:46.390431
3944 12:20:46.393887 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3945 12:20:46.393962
3946 12:20:46.396909 [CATrainingPosCal] consider 2 rank data
3947 12:20:46.400653 u2DelayCellTimex100 = 270/100 ps
3948 12:20:46.403563 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3949 12:20:46.406992 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3950 12:20:46.410677 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 12:20:46.413632 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 12:20:46.417256 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 12:20:46.423930 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 12:20:46.424013
3955 12:20:46.427055 CA PerBit enable=1, Macro0, CA PI delay=33
3956 12:20:46.427137
3957 12:20:46.430578 [CBTSetCACLKResult] CA Dly = 33
3958 12:20:46.430661 CS Dly: 5 (0~37)
3959 12:20:46.430730
3960 12:20:46.433812 ----->DramcWriteLeveling(PI) begin...
3961 12:20:46.433958 ==
3962 12:20:46.436881 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 12:20:46.444141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 12:20:46.444273 ==
3965 12:20:46.447112 Write leveling (Byte 0): 34 => 34
3966 12:20:46.447194 Write leveling (Byte 1): 30 => 30
3967 12:20:46.450411 DramcWriteLeveling(PI) end<-----
3968 12:20:46.450493
3969 12:20:46.450559 ==
3970 12:20:46.453689 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 12:20:46.460336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 12:20:46.460419 ==
3973 12:20:46.463867 [Gating] SW mode calibration
3974 12:20:46.470230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 12:20:46.473548 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 12:20:46.480221 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 12:20:46.483614 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 12:20:46.487128 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 12:20:46.493751 0 9 12 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 0)
3980 12:20:46.497090 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3981 12:20:46.500386 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 12:20:46.503590 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 12:20:46.510188 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 12:20:46.513762 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 12:20:46.516951 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 12:20:46.523741 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 12:20:46.526922 0 10 12 | B1->B0 | 2424 3838 | 0 0 | (0 0) (1 1)
3988 12:20:46.530191 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3989 12:20:46.536769 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 12:20:46.540275 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 12:20:46.543826 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 12:20:46.550318 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 12:20:46.553480 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 12:20:46.557080 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 12:20:46.563837 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3996 12:20:46.567229 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:20:46.570113 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:20:46.577222 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:20:46.580220 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:20:46.583498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:20:46.590121 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:20:46.593378 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:20:46.597032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:20:46.603500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:20:46.606587 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:20:46.610141 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:20:46.613849 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:20:46.620172 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:20:46.623523 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:20:46.626617 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:20:46.633460 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4012 12:20:46.636840 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 12:20:46.639979 Total UI for P1: 0, mck2ui 16
4014 12:20:46.643047 best dqsien dly found for B0: ( 0, 13, 12)
4015 12:20:46.646572 Total UI for P1: 0, mck2ui 16
4016 12:20:46.649714 best dqsien dly found for B1: ( 0, 13, 14)
4017 12:20:46.653223 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4018 12:20:46.656729 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4019 12:20:46.656851
4020 12:20:46.659849 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4021 12:20:46.663074 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4022 12:20:46.666517 [Gating] SW calibration Done
4023 12:20:46.666600 ==
4024 12:20:46.670217 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 12:20:46.676579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 12:20:46.676670 ==
4027 12:20:46.676799 RX Vref Scan: 0
4028 12:20:46.676900
4029 12:20:46.679794 RX Vref 0 -> 0, step: 1
4030 12:20:46.679876
4031 12:20:46.683315 RX Delay -230 -> 252, step: 16
4032 12:20:46.686372 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4033 12:20:46.689754 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4034 12:20:46.693310 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 12:20:46.699650 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4036 12:20:46.703288 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4037 12:20:46.706415 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4038 12:20:46.709718 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4039 12:20:46.713223 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4040 12:20:46.719638 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4041 12:20:46.723219 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4042 12:20:46.726568 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4043 12:20:46.729715 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4044 12:20:46.736579 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4045 12:20:46.739782 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4046 12:20:46.743299 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4047 12:20:46.746727 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4048 12:20:46.746806 ==
4049 12:20:46.749923 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 12:20:46.756628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 12:20:46.756719 ==
4052 12:20:46.756842 DQS Delay:
4053 12:20:46.759787 DQS0 = 0, DQS1 = 0
4054 12:20:46.759866 DQM Delay:
4055 12:20:46.759969 DQM0 = 49, DQM1 = 38
4056 12:20:46.763321 DQ Delay:
4057 12:20:46.766347 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4058 12:20:46.770119 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4059 12:20:46.773624 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4060 12:20:46.776550 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4061 12:20:46.776663
4062 12:20:46.776795
4063 12:20:46.776875 ==
4064 12:20:46.779697 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 12:20:46.783164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 12:20:46.783245 ==
4067 12:20:46.783325
4068 12:20:46.783401
4069 12:20:46.786573 TX Vref Scan disable
4070 12:20:46.786667 == TX Byte 0 ==
4071 12:20:46.793284 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4072 12:20:46.796477 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4073 12:20:46.796554 == TX Byte 1 ==
4074 12:20:46.803126 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4075 12:20:46.806458 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4076 12:20:46.806539 ==
4077 12:20:46.809852 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 12:20:46.813116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 12:20:46.813193 ==
4080 12:20:46.813282
4081 12:20:46.816436
4082 12:20:46.816535 TX Vref Scan disable
4083 12:20:46.819933 == TX Byte 0 ==
4084 12:20:46.823208 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4085 12:20:46.830030 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4086 12:20:46.830114 == TX Byte 1 ==
4087 12:20:46.833226 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4088 12:20:46.839951 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4089 12:20:46.840037
4090 12:20:46.840103 [DATLAT]
4091 12:20:46.840183 Freq=600, CH0 RK0
4092 12:20:46.840259
4093 12:20:46.843176 DATLAT Default: 0x9
4094 12:20:46.843259 0, 0xFFFF, sum = 0
4095 12:20:46.846380 1, 0xFFFF, sum = 0
4096 12:20:46.846465 2, 0xFFFF, sum = 0
4097 12:20:46.849887 3, 0xFFFF, sum = 0
4098 12:20:46.852988 4, 0xFFFF, sum = 0
4099 12:20:46.853072 5, 0xFFFF, sum = 0
4100 12:20:46.856553 6, 0xFFFF, sum = 0
4101 12:20:46.856638 7, 0xFFFF, sum = 0
4102 12:20:46.859681 8, 0x0, sum = 1
4103 12:20:46.859766 9, 0x0, sum = 2
4104 12:20:46.859834 10, 0x0, sum = 3
4105 12:20:46.862836 11, 0x0, sum = 4
4106 12:20:46.862920 best_step = 9
4107 12:20:46.862987
4108 12:20:46.863048 ==
4109 12:20:46.866401 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 12:20:46.872929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 12:20:46.873013 ==
4112 12:20:46.873080 RX Vref Scan: 1
4113 12:20:46.873142
4114 12:20:46.876510 RX Vref 0 -> 0, step: 1
4115 12:20:46.876608
4116 12:20:46.879580 RX Delay -179 -> 252, step: 8
4117 12:20:46.879692
4118 12:20:46.882704 Set Vref, RX VrefLevel [Byte0]: 58
4119 12:20:46.886178 [Byte1]: 50
4120 12:20:46.886262
4121 12:20:46.889685 Final RX Vref Byte 0 = 58 to rank0
4122 12:20:46.893291 Final RX Vref Byte 1 = 50 to rank0
4123 12:20:46.896259 Final RX Vref Byte 0 = 58 to rank1
4124 12:20:46.899659 Final RX Vref Byte 1 = 50 to rank1==
4125 12:20:46.903057 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 12:20:46.906224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 12:20:46.906414 ==
4128 12:20:46.909791 DQS Delay:
4129 12:20:46.909874 DQS0 = 0, DQS1 = 0
4130 12:20:46.909942 DQM Delay:
4131 12:20:46.913039 DQM0 = 48, DQM1 = 39
4132 12:20:46.913124 DQ Delay:
4133 12:20:46.916252 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4134 12:20:46.919923 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4135 12:20:46.923011 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =32
4136 12:20:46.926451 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4137 12:20:46.926534
4138 12:20:46.926599
4139 12:20:46.936076 [DQSOSCAuto] RK0, (LSB)MR18= 0x5852, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4140 12:20:46.939628 CH0 RK0: MR19=808, MR18=5852
4141 12:20:46.942842 CH0_RK0: MR19=0x808, MR18=0x5852, DQSOSC=393, MR23=63, INC=169, DEC=113
4142 12:20:46.942925
4143 12:20:46.946047 ----->DramcWriteLeveling(PI) begin...
4144 12:20:46.949822 ==
4145 12:20:46.952681 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 12:20:46.956081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 12:20:46.956194 ==
4148 12:20:46.959616 Write leveling (Byte 0): 34 => 34
4149 12:20:46.962654 Write leveling (Byte 1): 33 => 33
4150 12:20:46.966219 DramcWriteLeveling(PI) end<-----
4151 12:20:46.966330
4152 12:20:46.966395 ==
4153 12:20:46.969901 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 12:20:46.972716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 12:20:46.972853 ==
4156 12:20:46.976225 [Gating] SW mode calibration
4157 12:20:46.982620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 12:20:46.989557 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 12:20:46.992834 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 12:20:46.996099 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 12:20:46.999379 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 12:20:47.006399 0 9 12 | B1->B0 | 3333 3030 | 1 1 | (1 0) (1 1)
4163 12:20:47.009643 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4164 12:20:47.012627 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 12:20:47.019376 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 12:20:47.023051 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 12:20:47.026157 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 12:20:47.032719 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 12:20:47.036422 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 12:20:47.039572 0 10 12 | B1->B0 | 2424 2c2c | 0 1 | (0 0) (0 0)
4171 12:20:47.046347 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4172 12:20:47.049434 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 12:20:47.053047 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 12:20:47.059481 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 12:20:47.062554 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 12:20:47.066218 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 12:20:47.072639 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 12:20:47.076180 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 12:20:47.079396 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4180 12:20:47.085861 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:20:47.089123 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:20:47.092781 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:20:47.099433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:20:47.102910 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:20:47.105824 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:20:47.109205 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:20:47.116273 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:20:47.119493 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:20:47.122409 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:20:47.129253 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:20:47.132746 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:20:47.136111 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:20:47.142937 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4194 12:20:47.146090 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4195 12:20:47.149600 Total UI for P1: 0, mck2ui 16
4196 12:20:47.152916 best dqsien dly found for B1: ( 0, 13, 10)
4197 12:20:47.156021 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4198 12:20:47.159692 Total UI for P1: 0, mck2ui 16
4199 12:20:47.162954 best dqsien dly found for B0: ( 0, 13, 10)
4200 12:20:47.166233 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4201 12:20:47.169597 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4202 12:20:47.169680
4203 12:20:47.172729 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4204 12:20:47.179375 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4205 12:20:47.179485 [Gating] SW calibration Done
4206 12:20:47.182789 ==
4207 12:20:47.182891 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 12:20:47.189130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 12:20:47.189239 ==
4210 12:20:47.189333 RX Vref Scan: 0
4211 12:20:47.189424
4212 12:20:47.192971 RX Vref 0 -> 0, step: 1
4213 12:20:47.193054
4214 12:20:47.196189 RX Delay -230 -> 252, step: 16
4215 12:20:47.199260 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4216 12:20:47.202772 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4217 12:20:47.209588 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4218 12:20:47.212760 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4219 12:20:47.216309 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4220 12:20:47.219195 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4221 12:20:47.222643 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4222 12:20:47.229479 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4223 12:20:47.232799 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4224 12:20:47.236154 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4225 12:20:47.239292 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4226 12:20:47.245922 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4227 12:20:47.249462 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4228 12:20:47.252703 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4229 12:20:47.255852 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4230 12:20:47.262626 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4231 12:20:47.262710 ==
4232 12:20:47.266139 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 12:20:47.269518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 12:20:47.269603 ==
4235 12:20:47.269670 DQS Delay:
4236 12:20:47.272660 DQS0 = 0, DQS1 = 0
4237 12:20:47.272743 DQM Delay:
4238 12:20:47.275868 DQM0 = 52, DQM1 = 43
4239 12:20:47.275950 DQ Delay:
4240 12:20:47.279033 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4241 12:20:47.282507 DQ4 =49, DQ5 =49, DQ6 =65, DQ7 =57
4242 12:20:47.285920 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4243 12:20:47.289030 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4244 12:20:47.289112
4245 12:20:47.289178
4246 12:20:47.289238 ==
4247 12:20:47.292555 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 12:20:47.295758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 12:20:47.295841 ==
4250 12:20:47.295906
4251 12:20:47.295967
4252 12:20:47.298952 TX Vref Scan disable
4253 12:20:47.302545 == TX Byte 0 ==
4254 12:20:47.306127 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4255 12:20:47.309031 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4256 12:20:47.312488 == TX Byte 1 ==
4257 12:20:47.315864 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4258 12:20:47.318814 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4259 12:20:47.318897 ==
4260 12:20:47.322604 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 12:20:47.329043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 12:20:47.329127 ==
4263 12:20:47.329192
4264 12:20:47.329270
4265 12:20:47.329343 TX Vref Scan disable
4266 12:20:47.333141 == TX Byte 0 ==
4267 12:20:47.336428 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4268 12:20:47.343333 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4269 12:20:47.343489 == TX Byte 1 ==
4270 12:20:47.346371 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4271 12:20:47.353189 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4272 12:20:47.353272
4273 12:20:47.353337 [DATLAT]
4274 12:20:47.353398 Freq=600, CH0 RK1
4275 12:20:47.353458
4276 12:20:47.356359 DATLAT Default: 0x9
4277 12:20:47.356442 0, 0xFFFF, sum = 0
4278 12:20:47.360206 1, 0xFFFF, sum = 0
4279 12:20:47.360289 2, 0xFFFF, sum = 0
4280 12:20:47.363360 3, 0xFFFF, sum = 0
4281 12:20:47.363444 4, 0xFFFF, sum = 0
4282 12:20:47.366492 5, 0xFFFF, sum = 0
4283 12:20:47.369738 6, 0xFFFF, sum = 0
4284 12:20:47.369822 7, 0xFFFF, sum = 0
4285 12:20:47.369889 8, 0x0, sum = 1
4286 12:20:47.373057 9, 0x0, sum = 2
4287 12:20:47.373160 10, 0x0, sum = 3
4288 12:20:47.376629 11, 0x0, sum = 4
4289 12:20:47.376712 best_step = 9
4290 12:20:47.376813
4291 12:20:47.376875 ==
4292 12:20:47.379714 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 12:20:47.386507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 12:20:47.386589 ==
4295 12:20:47.386653 RX Vref Scan: 0
4296 12:20:47.386713
4297 12:20:47.389968 RX Vref 0 -> 0, step: 1
4298 12:20:47.390074
4299 12:20:47.393010 RX Delay -179 -> 252, step: 8
4300 12:20:47.396512 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4301 12:20:47.403132 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4302 12:20:47.406227 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4303 12:20:47.409895 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4304 12:20:47.413057 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4305 12:20:47.416474 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4306 12:20:47.423088 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4307 12:20:47.426188 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4308 12:20:47.429942 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4309 12:20:47.432898 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4310 12:20:47.436359 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4311 12:20:47.442830 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4312 12:20:47.446431 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4313 12:20:47.449465 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4314 12:20:47.452993 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4315 12:20:47.459308 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4316 12:20:47.459409 ==
4317 12:20:47.462796 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 12:20:47.466018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 12:20:47.466113 ==
4320 12:20:47.466178 DQS Delay:
4321 12:20:47.469613 DQS0 = 0, DQS1 = 0
4322 12:20:47.469693 DQM Delay:
4323 12:20:47.472719 DQM0 = 48, DQM1 = 40
4324 12:20:47.472835 DQ Delay:
4325 12:20:47.476275 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4326 12:20:47.479755 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4327 12:20:47.482938 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4328 12:20:47.486522 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4329 12:20:47.486602
4330 12:20:47.486665
4331 12:20:47.492868 [DQSOSCAuto] RK1, (LSB)MR18= 0x6230, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4332 12:20:47.496510 CH0 RK1: MR19=808, MR18=6230
4333 12:20:47.502662 CH0_RK1: MR19=0x808, MR18=0x6230, DQSOSC=391, MR23=63, INC=171, DEC=114
4334 12:20:47.506220 [RxdqsGatingPostProcess] freq 600
4335 12:20:47.513031 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4336 12:20:47.513114 Pre-setting of DQS Precalculation
4337 12:20:47.519435 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4338 12:20:47.519517 ==
4339 12:20:47.522665 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 12:20:47.525747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 12:20:47.525830 ==
4342 12:20:47.532876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4343 12:20:47.539167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4344 12:20:47.542972 [CA 0] Center 35 (5~66) winsize 62
4345 12:20:47.545956 [CA 1] Center 35 (5~66) winsize 62
4346 12:20:47.549401 [CA 2] Center 34 (4~65) winsize 62
4347 12:20:47.552742 [CA 3] Center 33 (3~64) winsize 62
4348 12:20:47.555775 [CA 4] Center 33 (3~64) winsize 62
4349 12:20:47.559387 [CA 5] Center 33 (3~64) winsize 62
4350 12:20:47.559469
4351 12:20:47.562514 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4352 12:20:47.562596
4353 12:20:47.566140 [CATrainingPosCal] consider 1 rank data
4354 12:20:47.569223 u2DelayCellTimex100 = 270/100 ps
4355 12:20:47.572855 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4356 12:20:47.575890 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4357 12:20:47.579001 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 12:20:47.582385 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4359 12:20:47.585630 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4360 12:20:47.589313 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4361 12:20:47.592576
4362 12:20:47.595838 CA PerBit enable=1, Macro0, CA PI delay=33
4363 12:20:47.595963
4364 12:20:47.599073 [CBTSetCACLKResult] CA Dly = 33
4365 12:20:47.599192 CS Dly: 5 (0~36)
4366 12:20:47.599302 ==
4367 12:20:47.602591 Dram Type= 6, Freq= 0, CH_1, rank 1
4368 12:20:47.605840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 12:20:47.605938 ==
4370 12:20:47.612251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 12:20:47.619099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4372 12:20:47.622208 [CA 0] Center 36 (6~66) winsize 61
4373 12:20:47.625730 [CA 1] Center 36 (5~67) winsize 63
4374 12:20:47.629057 [CA 2] Center 34 (4~65) winsize 62
4375 12:20:47.632219 [CA 3] Center 34 (4~65) winsize 62
4376 12:20:47.635481 [CA 4] Center 34 (4~65) winsize 62
4377 12:20:47.639240 [CA 5] Center 34 (3~65) winsize 63
4378 12:20:47.639367
4379 12:20:47.642178 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4380 12:20:47.642299
4381 12:20:47.645753 [CATrainingPosCal] consider 2 rank data
4382 12:20:47.649081 u2DelayCellTimex100 = 270/100 ps
4383 12:20:47.652413 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4384 12:20:47.655445 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 12:20:47.659061 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 12:20:47.662379 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4387 12:20:47.665745 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4388 12:20:47.672168 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 12:20:47.672250
4390 12:20:47.675289 CA PerBit enable=1, Macro0, CA PI delay=33
4391 12:20:47.675371
4392 12:20:47.678824 [CBTSetCACLKResult] CA Dly = 33
4393 12:20:47.678906 CS Dly: 5 (0~37)
4394 12:20:47.678971
4395 12:20:47.681971 ----->DramcWriteLeveling(PI) begin...
4396 12:20:47.682054 ==
4397 12:20:47.685497 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 12:20:47.692145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 12:20:47.692228 ==
4400 12:20:47.695390 Write leveling (Byte 0): 28 => 28
4401 12:20:47.695474 Write leveling (Byte 1): 31 => 31
4402 12:20:47.699054 DramcWriteLeveling(PI) end<-----
4403 12:20:47.699136
4404 12:20:47.699201 ==
4405 12:20:47.701929 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 12:20:47.708593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 12:20:47.708701 ==
4408 12:20:47.712082 [Gating] SW mode calibration
4409 12:20:47.718764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4410 12:20:47.721978 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4411 12:20:47.728613 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 12:20:47.731995 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 12:20:47.735075 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 12:20:47.742005 0 9 12 | B1->B0 | 2e2e 2d2d | 0 0 | (0 0) (0 0)
4415 12:20:47.745308 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 12:20:47.748375 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 12:20:47.752178 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 12:20:47.758383 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 12:20:47.761827 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 12:20:47.765115 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 12:20:47.771895 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4422 12:20:47.775079 0 10 12 | B1->B0 | 3838 3c3c | 1 0 | (1 1) (1 1)
4423 12:20:47.778643 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 12:20:47.785140 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 12:20:47.788277 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 12:20:47.791729 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 12:20:47.798572 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 12:20:47.801660 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 12:20:47.805142 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 12:20:47.811721 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4431 12:20:47.815116 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:20:47.818453 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:20:47.825202 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:20:47.828405 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:20:47.831571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:20:47.838088 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:20:47.841743 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:20:47.844990 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:20:47.851782 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:20:47.854868 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:20:47.858371 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:20:47.865300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:20:47.868381 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:20:47.871564 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:20:47.875164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:20:47.881714 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4447 12:20:47.884722 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 12:20:47.888419 Total UI for P1: 0, mck2ui 16
4449 12:20:47.891479 best dqsien dly found for B0: ( 0, 13, 12)
4450 12:20:47.895030 Total UI for P1: 0, mck2ui 16
4451 12:20:47.898346 best dqsien dly found for B1: ( 0, 13, 12)
4452 12:20:47.901664 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4453 12:20:47.904727 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4454 12:20:47.904833
4455 12:20:47.908351 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4456 12:20:47.914941 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4457 12:20:47.915028 [Gating] SW calibration Done
4458 12:20:47.915128 ==
4459 12:20:47.918186 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 12:20:47.924664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 12:20:47.924757 ==
4462 12:20:47.924842 RX Vref Scan: 0
4463 12:20:47.924905
4464 12:20:47.928191 RX Vref 0 -> 0, step: 1
4465 12:20:47.928273
4466 12:20:47.931397 RX Delay -230 -> 252, step: 16
4467 12:20:47.934930 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4468 12:20:47.938126 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4469 12:20:47.941587 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4470 12:20:47.948070 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4471 12:20:47.951551 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4472 12:20:47.954618 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4473 12:20:47.958148 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4474 12:20:47.961316 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4475 12:20:47.968046 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4476 12:20:47.971401 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4477 12:20:47.974616 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4478 12:20:47.978196 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4479 12:20:47.984874 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4480 12:20:47.987942 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4481 12:20:47.991523 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4482 12:20:47.994702 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4483 12:20:47.997912 ==
4484 12:20:47.997999 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 12:20:48.004441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 12:20:48.004555 ==
4487 12:20:48.004625 DQS Delay:
4488 12:20:48.007948 DQS0 = 0, DQS1 = 0
4489 12:20:48.008033 DQM Delay:
4490 12:20:48.011086 DQM0 = 50, DQM1 = 38
4491 12:20:48.011170 DQ Delay:
4492 12:20:48.014725 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4493 12:20:48.017663 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4494 12:20:48.020809 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4495 12:20:48.024173 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4496 12:20:48.024276
4497 12:20:48.024344
4498 12:20:48.024408 ==
4499 12:20:48.027722 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 12:20:48.030821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 12:20:48.030910 ==
4502 12:20:48.031002
4503 12:20:48.031067
4504 12:20:48.034393 TX Vref Scan disable
4505 12:20:48.037606 == TX Byte 0 ==
4506 12:20:48.041181 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4507 12:20:48.044280 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4508 12:20:48.047687 == TX Byte 1 ==
4509 12:20:48.051183 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4510 12:20:48.054260 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4511 12:20:48.054389 ==
4512 12:20:48.057367 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 12:20:48.060630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 12:20:48.064371 ==
4515 12:20:48.064471
4516 12:20:48.064557
4517 12:20:48.064658 TX Vref Scan disable
4518 12:20:48.068416 == TX Byte 0 ==
4519 12:20:48.071781 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4520 12:20:48.077979 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4521 12:20:48.078066 == TX Byte 1 ==
4522 12:20:48.081334 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4523 12:20:48.087957 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4524 12:20:48.088043
4525 12:20:48.088129 [DATLAT]
4526 12:20:48.088210 Freq=600, CH1 RK0
4527 12:20:48.088289
4528 12:20:48.091415 DATLAT Default: 0x9
4529 12:20:48.091500 0, 0xFFFF, sum = 0
4530 12:20:48.094727 1, 0xFFFF, sum = 0
4531 12:20:48.094813 2, 0xFFFF, sum = 0
4532 12:20:48.098124 3, 0xFFFF, sum = 0
4533 12:20:48.101223 4, 0xFFFF, sum = 0
4534 12:20:48.101311 5, 0xFFFF, sum = 0
4535 12:20:48.104708 6, 0xFFFF, sum = 0
4536 12:20:48.104831 7, 0xFFFF, sum = 0
4537 12:20:48.107831 8, 0x0, sum = 1
4538 12:20:48.107944 9, 0x0, sum = 2
4539 12:20:48.108029 10, 0x0, sum = 3
4540 12:20:48.111573 11, 0x0, sum = 4
4541 12:20:48.111671 best_step = 9
4542 12:20:48.111756
4543 12:20:48.111835 ==
4544 12:20:48.114713 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 12:20:48.121388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 12:20:48.121480 ==
4547 12:20:48.121584 RX Vref Scan: 1
4548 12:20:48.121684
4549 12:20:48.124653 RX Vref 0 -> 0, step: 1
4550 12:20:48.124761
4551 12:20:48.128238 RX Delay -179 -> 252, step: 8
4552 12:20:48.128315
4553 12:20:48.131434 Set Vref, RX VrefLevel [Byte0]: 51
4554 12:20:48.134522 [Byte1]: 57
4555 12:20:48.134628
4556 12:20:48.138103 Final RX Vref Byte 0 = 51 to rank0
4557 12:20:48.141364 Final RX Vref Byte 1 = 57 to rank0
4558 12:20:48.144550 Final RX Vref Byte 0 = 51 to rank1
4559 12:20:48.147639 Final RX Vref Byte 1 = 57 to rank1==
4560 12:20:48.151203 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 12:20:48.154240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 12:20:48.154323 ==
4563 12:20:48.157680 DQS Delay:
4564 12:20:48.157763 DQS0 = 0, DQS1 = 0
4565 12:20:48.161166 DQM Delay:
4566 12:20:48.161291 DQM0 = 47, DQM1 = 40
4567 12:20:48.161398 DQ Delay:
4568 12:20:48.164327 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4569 12:20:48.167895 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =44
4570 12:20:48.171089 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4571 12:20:48.174580 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4572 12:20:48.174698
4573 12:20:48.174809
4574 12:20:48.184435 [DQSOSCAuto] RK0, (LSB)MR18= 0x496f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4575 12:20:48.187614 CH1 RK0: MR19=808, MR18=496F
4576 12:20:48.191039 CH1_RK0: MR19=0x808, MR18=0x496F, DQSOSC=389, MR23=63, INC=173, DEC=115
4577 12:20:48.194249
4578 12:20:48.197832 ----->DramcWriteLeveling(PI) begin...
4579 12:20:48.197917 ==
4580 12:20:48.200936 Dram Type= 6, Freq= 0, CH_1, rank 1
4581 12:20:48.204659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 12:20:48.204777 ==
4583 12:20:48.207687 Write leveling (Byte 0): 29 => 29
4584 12:20:48.210824 Write leveling (Byte 1): 30 => 30
4585 12:20:48.214428 DramcWriteLeveling(PI) end<-----
4586 12:20:48.214517
4587 12:20:48.214583 ==
4588 12:20:48.217602 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 12:20:48.220908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 12:20:48.220983 ==
4591 12:20:48.224163 [Gating] SW mode calibration
4592 12:20:48.230856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4593 12:20:48.237656 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4594 12:20:48.240737 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 12:20:48.244220 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 12:20:48.250601 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4597 12:20:48.254141 0 9 12 | B1->B0 | 2d2d 3333 | 0 1 | (1 0) (1 0)
4598 12:20:48.257402 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 12:20:48.264007 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 12:20:48.267347 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 12:20:48.270429 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 12:20:48.277214 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 12:20:48.280901 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 12:20:48.283914 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4605 12:20:48.287108 0 10 12 | B1->B0 | 3d3d 2929 | 0 0 | (0 0) (0 0)
4606 12:20:48.294131 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 12:20:48.297326 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 12:20:48.300630 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 12:20:48.307179 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 12:20:48.310355 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 12:20:48.313866 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 12:20:48.320156 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 12:20:48.323695 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:20:48.327219 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 12:20:48.333537 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:20:48.337195 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:20:48.340296 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:20:48.347045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:20:48.350239 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:20:48.353353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:20:48.360389 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:20:48.363610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:20:48.366725 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:20:48.373539 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:20:48.376712 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:20:48.380235 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:20:48.386991 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:20:48.390166 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:20:48.393413 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4630 12:20:48.400168 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 12:20:48.400293 Total UI for P1: 0, mck2ui 16
4632 12:20:48.407012 best dqsien dly found for B0: ( 0, 13, 12)
4633 12:20:48.407145 Total UI for P1: 0, mck2ui 16
4634 12:20:48.409948 best dqsien dly found for B1: ( 0, 13, 12)
4635 12:20:48.417073 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4636 12:20:48.419725 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4637 12:20:48.419868
4638 12:20:48.423367 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4639 12:20:48.426689 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4640 12:20:48.429828 [Gating] SW calibration Done
4641 12:20:48.429961 ==
4642 12:20:48.433385 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 12:20:48.436472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 12:20:48.436603 ==
4645 12:20:48.440114 RX Vref Scan: 0
4646 12:20:48.440243
4647 12:20:48.440357 RX Vref 0 -> 0, step: 1
4648 12:20:48.440470
4649 12:20:48.443237 RX Delay -230 -> 252, step: 16
4650 12:20:48.446320 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4651 12:20:48.453177 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4652 12:20:48.456411 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4653 12:20:48.459942 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4654 12:20:48.463369 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4655 12:20:48.466543 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4656 12:20:48.473263 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4657 12:20:48.476448 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4658 12:20:48.479683 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4659 12:20:48.482809 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4660 12:20:48.489565 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4661 12:20:48.492874 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4662 12:20:48.496401 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4663 12:20:48.499754 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4664 12:20:48.506348 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4665 12:20:48.509571 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4666 12:20:48.509701 ==
4667 12:20:48.512979 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 12:20:48.516022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 12:20:48.516146 ==
4670 12:20:48.519703 DQS Delay:
4671 12:20:48.519835 DQS0 = 0, DQS1 = 0
4672 12:20:48.519950 DQM Delay:
4673 12:20:48.522740 DQM0 = 53, DQM1 = 46
4674 12:20:48.522869 DQ Delay:
4675 12:20:48.526255 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4676 12:20:48.529461 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4677 12:20:48.532863 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4678 12:20:48.536488 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4679 12:20:48.536590
4680 12:20:48.536683
4681 12:20:48.536793 ==
4682 12:20:48.539494 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 12:20:48.546107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 12:20:48.546190 ==
4685 12:20:48.546258
4686 12:20:48.546327
4687 12:20:48.546388 TX Vref Scan disable
4688 12:20:48.549768 == TX Byte 0 ==
4689 12:20:48.552955 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4690 12:20:48.559755 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4691 12:20:48.559883 == TX Byte 1 ==
4692 12:20:48.563265 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4693 12:20:48.566413 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4694 12:20:48.569612 ==
4695 12:20:48.573159 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 12:20:48.576334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 12:20:48.576461 ==
4698 12:20:48.576582
4699 12:20:48.576694
4700 12:20:48.579542 TX Vref Scan disable
4701 12:20:48.579661 == TX Byte 0 ==
4702 12:20:48.586360 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 12:20:48.589279 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 12:20:48.592729 == TX Byte 1 ==
4705 12:20:48.596144 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4706 12:20:48.599426 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4707 12:20:48.599546
4708 12:20:48.599670 [DATLAT]
4709 12:20:48.602562 Freq=600, CH1 RK1
4710 12:20:48.602676
4711 12:20:48.602785 DATLAT Default: 0x9
4712 12:20:48.606220 0, 0xFFFF, sum = 0
4713 12:20:48.606366 1, 0xFFFF, sum = 0
4714 12:20:48.609282 2, 0xFFFF, sum = 0
4715 12:20:48.612454 3, 0xFFFF, sum = 0
4716 12:20:48.612584 4, 0xFFFF, sum = 0
4717 12:20:48.616060 5, 0xFFFF, sum = 0
4718 12:20:48.616186 6, 0xFFFF, sum = 0
4719 12:20:48.619168 7, 0xFFFF, sum = 0
4720 12:20:48.619292 8, 0x0, sum = 1
4721 12:20:48.619410 9, 0x0, sum = 2
4722 12:20:48.622767 10, 0x0, sum = 3
4723 12:20:48.622897 11, 0x0, sum = 4
4724 12:20:48.626532 best_step = 9
4725 12:20:48.626651
4726 12:20:48.626768 ==
4727 12:20:48.629101 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 12:20:48.632583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 12:20:48.632718 ==
4730 12:20:48.636073 RX Vref Scan: 0
4731 12:20:48.636191
4732 12:20:48.636310 RX Vref 0 -> 0, step: 1
4733 12:20:48.636421
4734 12:20:48.639279 RX Delay -179 -> 252, step: 8
4735 12:20:48.646805 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4736 12:20:48.649771 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4737 12:20:48.653377 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4738 12:20:48.656598 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4739 12:20:48.663477 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4740 12:20:48.666451 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4741 12:20:48.669920 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4742 12:20:48.673476 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4743 12:20:48.676496 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4744 12:20:48.679653 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4745 12:20:48.686469 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4746 12:20:48.690001 iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304
4747 12:20:48.693285 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4748 12:20:48.696614 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4749 12:20:48.703310 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4750 12:20:48.706622 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4751 12:20:48.706750 ==
4752 12:20:48.710292 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 12:20:48.713635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 12:20:48.713772 ==
4755 12:20:48.716607 DQS Delay:
4756 12:20:48.716728 DQS0 = 0, DQS1 = 0
4757 12:20:48.716898 DQM Delay:
4758 12:20:48.719749 DQM0 = 48, DQM1 = 42
4759 12:20:48.719890 DQ Delay:
4760 12:20:48.723266 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4761 12:20:48.726556 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4762 12:20:48.730010 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =36
4763 12:20:48.733289 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4764 12:20:48.733418
4765 12:20:48.733531
4766 12:20:48.743178 [DQSOSCAuto] RK1, (LSB)MR18= 0x551b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4767 12:20:48.743299 CH1 RK1: MR19=808, MR18=551B
4768 12:20:48.749677 CH1_RK1: MR19=0x808, MR18=0x551B, DQSOSC=393, MR23=63, INC=169, DEC=113
4769 12:20:48.753156 [RxdqsGatingPostProcess] freq 600
4770 12:20:48.759877 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4771 12:20:48.763012 Pre-setting of DQS Precalculation
4772 12:20:48.766677 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4773 12:20:48.772906 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4774 12:20:48.779898 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4775 12:20:48.783683
4776 12:20:48.783764
4777 12:20:48.783830 [Calibration Summary] 1200 Mbps
4778 12:20:48.786734 CH 0, Rank 0
4779 12:20:48.786816 SW Impedance : PASS
4780 12:20:48.789904 DUTY Scan : NO K
4781 12:20:48.793435 ZQ Calibration : PASS
4782 12:20:48.793516 Jitter Meter : NO K
4783 12:20:48.796669 CBT Training : PASS
4784 12:20:48.799840 Write leveling : PASS
4785 12:20:48.799923 RX DQS gating : PASS
4786 12:20:48.803241 RX DQ/DQS(RDDQC) : PASS
4787 12:20:48.806805 TX DQ/DQS : PASS
4788 12:20:48.806927 RX DATLAT : PASS
4789 12:20:48.810056 RX DQ/DQS(Engine): PASS
4790 12:20:48.813118 TX OE : NO K
4791 12:20:48.813241 All Pass.
4792 12:20:48.813354
4793 12:20:48.813467 CH 0, Rank 1
4794 12:20:48.816718 SW Impedance : PASS
4795 12:20:48.819869 DUTY Scan : NO K
4796 12:20:48.819986 ZQ Calibration : PASS
4797 12:20:48.823384 Jitter Meter : NO K
4798 12:20:48.823504 CBT Training : PASS
4799 12:20:48.826515 Write leveling : PASS
4800 12:20:48.830123 RX DQS gating : PASS
4801 12:20:48.830242 RX DQ/DQS(RDDQC) : PASS
4802 12:20:48.833247 TX DQ/DQS : PASS
4803 12:20:48.836682 RX DATLAT : PASS
4804 12:20:48.836818 RX DQ/DQS(Engine): PASS
4805 12:20:48.839918 TX OE : NO K
4806 12:20:48.840037 All Pass.
4807 12:20:48.840142
4808 12:20:48.843402 CH 1, Rank 0
4809 12:20:48.843524 SW Impedance : PASS
4810 12:20:48.846749 DUTY Scan : NO K
4811 12:20:48.849899 ZQ Calibration : PASS
4812 12:20:48.849982 Jitter Meter : NO K
4813 12:20:48.853903 CBT Training : PASS
4814 12:20:48.856631 Write leveling : PASS
4815 12:20:48.856716 RX DQS gating : PASS
4816 12:20:48.859883 RX DQ/DQS(RDDQC) : PASS
4817 12:20:48.863099 TX DQ/DQS : PASS
4818 12:20:48.863182 RX DATLAT : PASS
4819 12:20:48.866742 RX DQ/DQS(Engine): PASS
4820 12:20:48.866825 TX OE : NO K
4821 12:20:48.870021 All Pass.
4822 12:20:48.870121
4823 12:20:48.870220 CH 1, Rank 1
4824 12:20:48.873066 SW Impedance : PASS
4825 12:20:48.873151 DUTY Scan : NO K
4826 12:20:48.876591 ZQ Calibration : PASS
4827 12:20:48.879725 Jitter Meter : NO K
4828 12:20:48.879825 CBT Training : PASS
4829 12:20:48.883274 Write leveling : PASS
4830 12:20:48.886435 RX DQS gating : PASS
4831 12:20:48.886518 RX DQ/DQS(RDDQC) : PASS
4832 12:20:48.890251 TX DQ/DQS : PASS
4833 12:20:48.893263 RX DATLAT : PASS
4834 12:20:48.893376 RX DQ/DQS(Engine): PASS
4835 12:20:48.896464 TX OE : NO K
4836 12:20:48.896547 All Pass.
4837 12:20:48.896614
4838 12:20:48.900097 DramC Write-DBI off
4839 12:20:48.903238 PER_BANK_REFRESH: Hybrid Mode
4840 12:20:48.903327 TX_TRACKING: ON
4841 12:20:48.913003 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4842 12:20:48.916523 [FAST_K] Save calibration result to emmc
4843 12:20:48.919699 dramc_set_vcore_voltage set vcore to 662500
4844 12:20:48.923125 Read voltage for 933, 3
4845 12:20:48.923208 Vio18 = 0
4846 12:20:48.923274 Vcore = 662500
4847 12:20:48.926407 Vdram = 0
4848 12:20:48.926490 Vddq = 0
4849 12:20:48.926595 Vmddr = 0
4850 12:20:48.933068 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4851 12:20:48.936233 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4852 12:20:48.939813 MEM_TYPE=3, freq_sel=17
4853 12:20:48.943127 sv_algorithm_assistance_LP4_1600
4854 12:20:48.946168 ============ PULL DRAM RESETB DOWN ============
4855 12:20:48.949928 ========== PULL DRAM RESETB DOWN end =========
4856 12:20:48.956224 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4857 12:20:48.959467 ===================================
4858 12:20:48.959568 LPDDR4 DRAM CONFIGURATION
4859 12:20:48.962845 ===================================
4860 12:20:48.966071 EX_ROW_EN[0] = 0x0
4861 12:20:48.969315 EX_ROW_EN[1] = 0x0
4862 12:20:48.969415 LP4Y_EN = 0x0
4863 12:20:48.972548 WORK_FSP = 0x0
4864 12:20:48.972647 WL = 0x3
4865 12:20:48.975911 RL = 0x3
4866 12:20:48.976036 BL = 0x2
4867 12:20:48.979458 RPST = 0x0
4868 12:20:48.979558 RD_PRE = 0x0
4869 12:20:48.982550 WR_PRE = 0x1
4870 12:20:48.982650 WR_PST = 0x0
4871 12:20:48.985997 DBI_WR = 0x0
4872 12:20:48.986097 DBI_RD = 0x0
4873 12:20:48.989237 OTF = 0x1
4874 12:20:48.992703 ===================================
4875 12:20:48.995941 ===================================
4876 12:20:48.996041 ANA top config
4877 12:20:48.999489 ===================================
4878 12:20:49.002798 DLL_ASYNC_EN = 0
4879 12:20:49.005953 ALL_SLAVE_EN = 1
4880 12:20:49.009180 NEW_RANK_MODE = 1
4881 12:20:49.009265 DLL_IDLE_MODE = 1
4882 12:20:49.012590 LP45_APHY_COMB_EN = 1
4883 12:20:49.016090 TX_ODT_DIS = 1
4884 12:20:49.019465 NEW_8X_MODE = 1
4885 12:20:49.022388 ===================================
4886 12:20:49.025963 ===================================
4887 12:20:49.029117 data_rate = 1866
4888 12:20:49.029218 CKR = 1
4889 12:20:49.032647 DQ_P2S_RATIO = 8
4890 12:20:49.035949 ===================================
4891 12:20:49.039588 CA_P2S_RATIO = 8
4892 12:20:49.042842 DQ_CA_OPEN = 0
4893 12:20:49.046038 DQ_SEMI_OPEN = 0
4894 12:20:49.046124 CA_SEMI_OPEN = 0
4895 12:20:49.049412 CA_FULL_RATE = 0
4896 12:20:49.052523 DQ_CKDIV4_EN = 1
4897 12:20:49.056553 CA_CKDIV4_EN = 1
4898 12:20:49.059403 CA_PREDIV_EN = 0
4899 12:20:49.062812 PH8_DLY = 0
4900 12:20:49.062944 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4901 12:20:49.066169 DQ_AAMCK_DIV = 4
4902 12:20:49.069582 CA_AAMCK_DIV = 4
4903 12:20:49.072777 CA_ADMCK_DIV = 4
4904 12:20:49.076036 DQ_TRACK_CA_EN = 0
4905 12:20:49.079324 CA_PICK = 933
4906 12:20:49.082520 CA_MCKIO = 933
4907 12:20:49.082652 MCKIO_SEMI = 0
4908 12:20:49.085977 PLL_FREQ = 3732
4909 12:20:49.089474 DQ_UI_PI_RATIO = 32
4910 12:20:49.092628 CA_UI_PI_RATIO = 0
4911 12:20:49.096146 ===================================
4912 12:20:49.099239 ===================================
4913 12:20:49.102938 memory_type:LPDDR4
4914 12:20:49.103027 GP_NUM : 10
4915 12:20:49.105970 SRAM_EN : 1
4916 12:20:49.106054 MD32_EN : 0
4917 12:20:49.109145 ===================================
4918 12:20:49.112653 [ANA_INIT] >>>>>>>>>>>>>>
4919 12:20:49.116170 <<<<<< [CONFIGURE PHASE]: ANA_TX
4920 12:20:49.119359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4921 12:20:49.122538 ===================================
4922 12:20:49.125750 data_rate = 1866,PCW = 0X8f00
4923 12:20:49.129181 ===================================
4924 12:20:49.132404 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4925 12:20:49.139245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 12:20:49.142402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 12:20:49.149232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4928 12:20:49.152361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4929 12:20:49.155510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4930 12:20:49.155609 [ANA_INIT] flow start
4931 12:20:49.159078 [ANA_INIT] PLL >>>>>>>>
4932 12:20:49.162132 [ANA_INIT] PLL <<<<<<<<
4933 12:20:49.162232 [ANA_INIT] MIDPI >>>>>>>>
4934 12:20:49.165561 [ANA_INIT] MIDPI <<<<<<<<
4935 12:20:49.168928 [ANA_INIT] DLL >>>>>>>>
4936 12:20:49.169043 [ANA_INIT] flow end
4937 12:20:49.175714 ============ LP4 DIFF to SE enter ============
4938 12:20:49.179200 ============ LP4 DIFF to SE exit ============
4939 12:20:49.182725 [ANA_INIT] <<<<<<<<<<<<<
4940 12:20:49.185668 [Flow] Enable top DCM control >>>>>
4941 12:20:49.189194 [Flow] Enable top DCM control <<<<<
4942 12:20:49.189303 Enable DLL master slave shuffle
4943 12:20:49.195706 ==============================================================
4944 12:20:49.199128 Gating Mode config
4945 12:20:49.202308 ==============================================================
4946 12:20:49.205504 Config description:
4947 12:20:49.215339 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4948 12:20:49.222464 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4949 12:20:49.225631 SELPH_MODE 0: By rank 1: By Phase
4950 12:20:49.232393 ==============================================================
4951 12:20:49.235557 GAT_TRACK_EN = 1
4952 12:20:49.238975 RX_GATING_MODE = 2
4953 12:20:49.242272 RX_GATING_TRACK_MODE = 2
4954 12:20:49.242347 SELPH_MODE = 1
4955 12:20:49.245479 PICG_EARLY_EN = 1
4956 12:20:49.249100 VALID_LAT_VALUE = 1
4957 12:20:49.255922 ==============================================================
4958 12:20:49.258736 Enter into Gating configuration >>>>
4959 12:20:49.262491 Exit from Gating configuration <<<<
4960 12:20:49.265779 Enter into DVFS_PRE_config >>>>>
4961 12:20:49.275449 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4962 12:20:49.278833 Exit from DVFS_PRE_config <<<<<
4963 12:20:49.282444 Enter into PICG configuration >>>>
4964 12:20:49.285264 Exit from PICG configuration <<<<
4965 12:20:49.288608 [RX_INPUT] configuration >>>>>
4966 12:20:49.291958 [RX_INPUT] configuration <<<<<
4967 12:20:49.295405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4968 12:20:49.302052 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4969 12:20:49.308392 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 12:20:49.315186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 12:20:49.321843 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 12:20:49.325272 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 12:20:49.331816 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4974 12:20:49.335007 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4975 12:20:49.338645 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4976 12:20:49.341786 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4977 12:20:49.345440 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4978 12:20:49.351574 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4979 12:20:49.355135 ===================================
4980 12:20:49.358231 LPDDR4 DRAM CONFIGURATION
4981 12:20:49.361811 ===================================
4982 12:20:49.361948 EX_ROW_EN[0] = 0x0
4983 12:20:49.364891 EX_ROW_EN[1] = 0x0
4984 12:20:49.364975 LP4Y_EN = 0x0
4985 12:20:49.368521 WORK_FSP = 0x0
4986 12:20:49.368605 WL = 0x3
4987 12:20:49.371673 RL = 0x3
4988 12:20:49.371756 BL = 0x2
4989 12:20:49.375298 RPST = 0x0
4990 12:20:49.375382 RD_PRE = 0x0
4991 12:20:49.378440 WR_PRE = 0x1
4992 12:20:49.378524 WR_PST = 0x0
4993 12:20:49.381651 DBI_WR = 0x0
4994 12:20:49.381735 DBI_RD = 0x0
4995 12:20:49.385038 OTF = 0x1
4996 12:20:49.388588 ===================================
4997 12:20:49.391794 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4998 12:20:49.394923 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4999 12:20:49.401653 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 12:20:49.405003 ===================================
5001 12:20:49.405130 LPDDR4 DRAM CONFIGURATION
5002 12:20:49.408594 ===================================
5003 12:20:49.411829 EX_ROW_EN[0] = 0x10
5004 12:20:49.415094 EX_ROW_EN[1] = 0x0
5005 12:20:49.415240 LP4Y_EN = 0x0
5006 12:20:49.418706 WORK_FSP = 0x0
5007 12:20:49.418837 WL = 0x3
5008 12:20:49.421857 RL = 0x3
5009 12:20:49.421983 BL = 0x2
5010 12:20:49.424950 RPST = 0x0
5011 12:20:49.425074 RD_PRE = 0x0
5012 12:20:49.428327 WR_PRE = 0x1
5013 12:20:49.428461 WR_PST = 0x0
5014 12:20:49.431770 DBI_WR = 0x0
5015 12:20:49.431891 DBI_RD = 0x0
5016 12:20:49.434926 OTF = 0x1
5017 12:20:49.438510 ===================================
5018 12:20:49.445213 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5019 12:20:49.448282 nWR fixed to 30
5020 12:20:49.448412 [ModeRegInit_LP4] CH0 RK0
5021 12:20:49.451448 [ModeRegInit_LP4] CH0 RK1
5022 12:20:49.455049 [ModeRegInit_LP4] CH1 RK0
5023 12:20:49.458209 [ModeRegInit_LP4] CH1 RK1
5024 12:20:49.458332 match AC timing 9
5025 12:20:49.461852 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5026 12:20:49.468167 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5027 12:20:49.471347 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5028 12:20:49.478105 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5029 12:20:49.481729 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5030 12:20:49.481837 ==
5031 12:20:49.484839 Dram Type= 6, Freq= 0, CH_0, rank 0
5032 12:20:49.488355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5033 12:20:49.488426 ==
5034 12:20:49.494772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5035 12:20:49.501498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5036 12:20:49.504708 [CA 0] Center 38 (7~69) winsize 63
5037 12:20:49.507863 [CA 1] Center 38 (8~69) winsize 62
5038 12:20:49.511518 [CA 2] Center 35 (5~66) winsize 62
5039 12:20:49.514670 [CA 3] Center 34 (4~65) winsize 62
5040 12:20:49.517928 [CA 4] Center 34 (4~64) winsize 61
5041 12:20:49.521446 [CA 5] Center 33 (3~64) winsize 62
5042 12:20:49.521530
5043 12:20:49.524616 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5044 12:20:49.524713
5045 12:20:49.528120 [CATrainingPosCal] consider 1 rank data
5046 12:20:49.531247 u2DelayCellTimex100 = 270/100 ps
5047 12:20:49.534352 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5048 12:20:49.537950 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5049 12:20:49.541219 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5050 12:20:49.544343 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5051 12:20:49.547897 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5052 12:20:49.551152 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5053 12:20:49.551249
5054 12:20:49.557629 CA PerBit enable=1, Macro0, CA PI delay=33
5055 12:20:49.557713
5056 12:20:49.557780 [CBTSetCACLKResult] CA Dly = 33
5057 12:20:49.561185 CS Dly: 7 (0~38)
5058 12:20:49.561267 ==
5059 12:20:49.564337 Dram Type= 6, Freq= 0, CH_0, rank 1
5060 12:20:49.568035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 12:20:49.568120 ==
5062 12:20:49.574671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 12:20:49.581391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5064 12:20:49.584475 [CA 0] Center 38 (7~69) winsize 63
5065 12:20:49.587731 [CA 1] Center 38 (8~69) winsize 62
5066 12:20:49.591370 [CA 2] Center 36 (6~66) winsize 61
5067 12:20:49.594440 [CA 3] Center 35 (5~66) winsize 62
5068 12:20:49.597540 [CA 4] Center 34 (4~65) winsize 62
5069 12:20:49.601339 [CA 5] Center 34 (4~64) winsize 61
5070 12:20:49.601458
5071 12:20:49.604722 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5072 12:20:49.604876
5073 12:20:49.607724 [CATrainingPosCal] consider 2 rank data
5074 12:20:49.610989 u2DelayCellTimex100 = 270/100 ps
5075 12:20:49.614652 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5076 12:20:49.617582 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5077 12:20:49.621411 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5078 12:20:49.624238 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5079 12:20:49.627836 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5080 12:20:49.630938 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5081 12:20:49.631022
5082 12:20:49.637520 CA PerBit enable=1, Macro0, CA PI delay=34
5083 12:20:49.637602
5084 12:20:49.637667 [CBTSetCACLKResult] CA Dly = 34
5085 12:20:49.640937 CS Dly: 7 (0~39)
5086 12:20:49.641019
5087 12:20:49.644090 ----->DramcWriteLeveling(PI) begin...
5088 12:20:49.644198 ==
5089 12:20:49.647617 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 12:20:49.650939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 12:20:49.651022 ==
5092 12:20:49.654447 Write leveling (Byte 0): 32 => 32
5093 12:20:49.657630 Write leveling (Byte 1): 29 => 29
5094 12:20:49.660718 DramcWriteLeveling(PI) end<-----
5095 12:20:49.660821
5096 12:20:49.660887 ==
5097 12:20:49.664417 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 12:20:49.667631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 12:20:49.671107 ==
5100 12:20:49.671191 [Gating] SW mode calibration
5101 12:20:49.680929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5102 12:20:49.684139 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5103 12:20:49.687766 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5104 12:20:49.694382 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 12:20:49.697515 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 12:20:49.700720 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 12:20:49.707289 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 12:20:49.710749 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 12:20:49.714035 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5110 12:20:49.720788 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
5111 12:20:49.724292 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5112 12:20:49.727370 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 12:20:49.734024 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 12:20:49.737291 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 12:20:49.740532 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 12:20:49.747535 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 12:20:49.750671 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5118 12:20:49.754205 0 15 28 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
5119 12:20:49.760744 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5120 12:20:49.763734 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 12:20:49.767377 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 12:20:49.774137 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 12:20:49.777376 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 12:20:49.780483 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 12:20:49.783925 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5126 12:20:49.790564 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5127 12:20:49.794250 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5128 12:20:49.797412 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:20:49.804030 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:20:49.807135 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:20:49.810463 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:20:49.817330 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:20:49.820760 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:20:49.823887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:20:49.830834 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:20:49.834021 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:20:49.837432 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:20:49.844078 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:20:49.847403 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:20:49.850477 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5141 12:20:49.857351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5142 12:20:49.860585 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5143 12:20:49.864167 Total UI for P1: 0, mck2ui 16
5144 12:20:49.867422 best dqsien dly found for B0: ( 1, 2, 22)
5145 12:20:49.870580 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 12:20:49.874077 Total UI for P1: 0, mck2ui 16
5147 12:20:49.877529 best dqsien dly found for B1: ( 1, 2, 28)
5148 12:20:49.880532 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5149 12:20:49.883800 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5150 12:20:49.883886
5151 12:20:49.887396 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5152 12:20:49.893746 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5153 12:20:49.893831 [Gating] SW calibration Done
5154 12:20:49.893899 ==
5155 12:20:49.897335 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 12:20:49.904343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 12:20:49.904429 ==
5158 12:20:49.904495 RX Vref Scan: 0
5159 12:20:49.904559
5160 12:20:49.907211 RX Vref 0 -> 0, step: 1
5161 12:20:49.907296
5162 12:20:49.910213 RX Delay -80 -> 252, step: 8
5163 12:20:49.913862 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5164 12:20:49.917147 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5165 12:20:49.920468 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5166 12:20:49.923874 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5167 12:20:49.930543 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5168 12:20:49.934147 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5169 12:20:49.936974 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5170 12:20:49.940709 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5171 12:20:49.943653 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5172 12:20:49.950455 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5173 12:20:49.953750 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5174 12:20:49.957121 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5175 12:20:49.960159 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5176 12:20:49.963873 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5177 12:20:49.966950 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5178 12:20:49.973854 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5179 12:20:49.973938 ==
5180 12:20:49.976874 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 12:20:49.980512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 12:20:49.980597 ==
5183 12:20:49.980665 DQS Delay:
5184 12:20:49.983711 DQS0 = 0, DQS1 = 0
5185 12:20:49.983793 DQM Delay:
5186 12:20:49.986847 DQM0 = 106, DQM1 = 90
5187 12:20:49.986929 DQ Delay:
5188 12:20:49.990116 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5189 12:20:49.993691 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5190 12:20:49.996724 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =87
5191 12:20:50.000143 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5192 12:20:50.000225
5193 12:20:50.000290
5194 12:20:50.000351 ==
5195 12:20:50.003719 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 12:20:50.006748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 12:20:50.010383 ==
5198 12:20:50.010508
5199 12:20:50.010648
5200 12:20:50.010760 TX Vref Scan disable
5201 12:20:50.013629 == TX Byte 0 ==
5202 12:20:50.016676 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5203 12:20:50.020101 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5204 12:20:50.023431 == TX Byte 1 ==
5205 12:20:50.026933 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5206 12:20:50.030068 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5207 12:20:50.033270 ==
5208 12:20:50.033353 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 12:20:50.040408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 12:20:50.040518 ==
5211 12:20:50.040613
5212 12:20:50.040702
5213 12:20:50.043613 TX Vref Scan disable
5214 12:20:50.043696 == TX Byte 0 ==
5215 12:20:50.049949 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5216 12:20:50.053443 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5217 12:20:50.053526 == TX Byte 1 ==
5218 12:20:50.059953 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5219 12:20:50.063617 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5220 12:20:50.063701
5221 12:20:50.063767 [DATLAT]
5222 12:20:50.066780 Freq=933, CH0 RK0
5223 12:20:50.066864
5224 12:20:50.066931 DATLAT Default: 0xd
5225 12:20:50.070549 0, 0xFFFF, sum = 0
5226 12:20:50.070638 1, 0xFFFF, sum = 0
5227 12:20:50.073561 2, 0xFFFF, sum = 0
5228 12:20:50.073642 3, 0xFFFF, sum = 0
5229 12:20:50.076693 4, 0xFFFF, sum = 0
5230 12:20:50.076788 5, 0xFFFF, sum = 0
5231 12:20:50.079862 6, 0xFFFF, sum = 0
5232 12:20:50.079947 7, 0xFFFF, sum = 0
5233 12:20:50.083669 8, 0xFFFF, sum = 0
5234 12:20:50.083754 9, 0xFFFF, sum = 0
5235 12:20:50.086669 10, 0x0, sum = 1
5236 12:20:50.086754 11, 0x0, sum = 2
5237 12:20:50.090222 12, 0x0, sum = 3
5238 12:20:50.090307 13, 0x0, sum = 4
5239 12:20:50.093562 best_step = 11
5240 12:20:50.093646
5241 12:20:50.093712 ==
5242 12:20:50.096765 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 12:20:50.100239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 12:20:50.100322 ==
5245 12:20:50.103511 RX Vref Scan: 1
5246 12:20:50.103594
5247 12:20:50.103678 RX Vref 0 -> 0, step: 1
5248 12:20:50.103756
5249 12:20:50.106539 RX Delay -61 -> 252, step: 4
5250 12:20:50.106625
5251 12:20:50.109765 Set Vref, RX VrefLevel [Byte0]: 58
5252 12:20:50.113399 [Byte1]: 50
5253 12:20:50.117028
5254 12:20:50.117111 Final RX Vref Byte 0 = 58 to rank0
5255 12:20:50.120411 Final RX Vref Byte 1 = 50 to rank0
5256 12:20:50.123770 Final RX Vref Byte 0 = 58 to rank1
5257 12:20:50.127006 Final RX Vref Byte 1 = 50 to rank1==
5258 12:20:50.130183 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:20:50.136992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:20:50.137077 ==
5261 12:20:50.137173 DQS Delay:
5262 12:20:50.137274 DQS0 = 0, DQS1 = 0
5263 12:20:50.140092 DQM Delay:
5264 12:20:50.140175 DQM0 = 107, DQM1 = 91
5265 12:20:50.143653 DQ Delay:
5266 12:20:50.146923 DQ0 =108, DQ1 =106, DQ2 =102, DQ3 =106
5267 12:20:50.150264 DQ4 =108, DQ5 =100, DQ6 =116, DQ7 =114
5268 12:20:50.153830 DQ8 =84, DQ9 =76, DQ10 =92, DQ11 =90
5269 12:20:50.157039 DQ12 =94, DQ13 =94, DQ14 =104, DQ15 =98
5270 12:20:50.157165
5271 12:20:50.157342
5272 12:20:50.163592 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5273 12:20:50.167003 CH0 RK0: MR19=505, MR18=221E
5274 12:20:50.173766 CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42
5275 12:20:50.173851
5276 12:20:50.176862 ----->DramcWriteLeveling(PI) begin...
5277 12:20:50.176948 ==
5278 12:20:50.180335 Dram Type= 6, Freq= 0, CH_0, rank 1
5279 12:20:50.183543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 12:20:50.183671 ==
5281 12:20:50.186625 Write leveling (Byte 0): 30 => 30
5282 12:20:50.190205 Write leveling (Byte 1): 29 => 29
5283 12:20:50.193408 DramcWriteLeveling(PI) end<-----
5284 12:20:50.193525
5285 12:20:50.193639 ==
5286 12:20:50.196663 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 12:20:50.200361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 12:20:50.203568 ==
5289 12:20:50.203692 [Gating] SW mode calibration
5290 12:20:50.213442 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5291 12:20:50.217217 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5292 12:20:50.220316 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 12:20:50.226704 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 12:20:50.230348 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 12:20:50.233395 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 12:20:50.240055 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 12:20:50.243330 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 12:20:50.246890 0 14 24 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
5299 12:20:50.253380 0 14 28 | B1->B0 | 2f2f 2828 | 0 0 | (1 0) (0 0)
5300 12:20:50.257051 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 12:20:50.260449 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 12:20:50.266767 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 12:20:50.270011 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 12:20:50.273435 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 12:20:50.280081 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 12:20:50.283275 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5307 12:20:50.286382 0 15 28 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
5308 12:20:50.293065 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 12:20:50.296650 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 12:20:50.299747 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 12:20:50.306437 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 12:20:50.309904 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 12:20:50.313443 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 12:20:50.316560 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5315 12:20:50.323522 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5316 12:20:50.326722 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5317 12:20:50.330016 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:20:50.336767 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:20:50.339715 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:20:50.342792 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:20:50.350113 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:20:50.352969 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:20:50.356553 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:20:50.362989 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:20:50.366327 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:20:50.369716 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:20:50.376087 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:20:50.379390 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:20:50.383037 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:20:50.389312 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5331 12:20:50.392911 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5332 12:20:50.396367 Total UI for P1: 0, mck2ui 16
5333 12:20:50.399396 best dqsien dly found for B1: ( 1, 2, 24)
5334 12:20:50.402980 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5335 12:20:50.409277 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 12:20:50.409362 Total UI for P1: 0, mck2ui 16
5337 12:20:50.416069 best dqsien dly found for B0: ( 1, 2, 30)
5338 12:20:50.419561 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5339 12:20:50.422664 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5340 12:20:50.422747
5341 12:20:50.426024 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5342 12:20:50.429747 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5343 12:20:50.432737 [Gating] SW calibration Done
5344 12:20:50.432830 ==
5345 12:20:50.436200 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 12:20:50.439433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 12:20:50.439517 ==
5348 12:20:50.442616 RX Vref Scan: 0
5349 12:20:50.442700
5350 12:20:50.442766 RX Vref 0 -> 0, step: 1
5351 12:20:50.442828
5352 12:20:50.446094 RX Delay -80 -> 252, step: 8
5353 12:20:50.449718 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5354 12:20:50.452867 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5355 12:20:50.459336 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5356 12:20:50.462716 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5357 12:20:50.466395 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5358 12:20:50.469208 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5359 12:20:50.472602 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5360 12:20:50.479219 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5361 12:20:50.482556 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5362 12:20:50.485606 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5363 12:20:50.489075 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5364 12:20:50.492592 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5365 12:20:50.495825 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5366 12:20:50.502683 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5367 12:20:50.505795 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5368 12:20:50.508915 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5369 12:20:50.509001 ==
5370 12:20:50.512591 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 12:20:50.515649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 12:20:50.515735 ==
5373 12:20:50.519300 DQS Delay:
5374 12:20:50.519386 DQS0 = 0, DQS1 = 0
5375 12:20:50.519454 DQM Delay:
5376 12:20:50.522507 DQM0 = 104, DQM1 = 91
5377 12:20:50.522597 DQ Delay:
5378 12:20:50.525767 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5379 12:20:50.529059 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5380 12:20:50.532624 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5381 12:20:50.535715 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5382 12:20:50.535800
5383 12:20:50.535868
5384 12:20:50.539029 ==
5385 12:20:50.539116 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 12:20:50.545937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 12:20:50.546023 ==
5388 12:20:50.546091
5389 12:20:50.546153
5390 12:20:50.549104 TX Vref Scan disable
5391 12:20:50.549189 == TX Byte 0 ==
5392 12:20:50.552611 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5393 12:20:50.559263 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5394 12:20:50.559349 == TX Byte 1 ==
5395 12:20:50.562320 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5396 12:20:50.569323 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5397 12:20:50.569410 ==
5398 12:20:50.572594 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 12:20:50.576077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 12:20:50.576162 ==
5401 12:20:50.576229
5402 12:20:50.576307
5403 12:20:50.579255 TX Vref Scan disable
5404 12:20:50.582190 == TX Byte 0 ==
5405 12:20:50.585542 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5406 12:20:50.589018 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5407 12:20:50.592431 == TX Byte 1 ==
5408 12:20:50.596011 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5409 12:20:50.599280 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5410 12:20:50.599407
5411 12:20:50.599517 [DATLAT]
5412 12:20:50.602511 Freq=933, CH0 RK1
5413 12:20:50.602635
5414 12:20:50.602750 DATLAT Default: 0xb
5415 12:20:50.605676 0, 0xFFFF, sum = 0
5416 12:20:50.609258 1, 0xFFFF, sum = 0
5417 12:20:50.609345 2, 0xFFFF, sum = 0
5418 12:20:50.612569 3, 0xFFFF, sum = 0
5419 12:20:50.612655 4, 0xFFFF, sum = 0
5420 12:20:50.615792 5, 0xFFFF, sum = 0
5421 12:20:50.615879 6, 0xFFFF, sum = 0
5422 12:20:50.619367 7, 0xFFFF, sum = 0
5423 12:20:50.619455 8, 0xFFFF, sum = 0
5424 12:20:50.622434 9, 0xFFFF, sum = 0
5425 12:20:50.622552 10, 0x0, sum = 1
5426 12:20:50.625782 11, 0x0, sum = 2
5427 12:20:50.625926 12, 0x0, sum = 3
5428 12:20:50.628922 13, 0x0, sum = 4
5429 12:20:50.629005 best_step = 11
5430 12:20:50.629070
5431 12:20:50.629131 ==
5432 12:20:50.632583 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 12:20:50.635804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 12:20:50.635886 ==
5435 12:20:50.638853 RX Vref Scan: 0
5436 12:20:50.639006
5437 12:20:50.642285 RX Vref 0 -> 0, step: 1
5438 12:20:50.642367
5439 12:20:50.642432 RX Delay -53 -> 252, step: 4
5440 12:20:50.650181 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5441 12:20:50.653421 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5442 12:20:50.656749 iDelay=199, Bit 2, Center 104 (19 ~ 190) 172
5443 12:20:50.659784 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5444 12:20:50.663462 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5445 12:20:50.670003 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5446 12:20:50.673190 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5447 12:20:50.676681 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5448 12:20:50.680012 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5449 12:20:50.683423 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5450 12:20:50.689979 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5451 12:20:50.693210 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5452 12:20:50.696405 iDelay=199, Bit 12, Center 100 (15 ~ 186) 172
5453 12:20:50.699998 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5454 12:20:50.703100 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5455 12:20:50.706656 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5456 12:20:50.709807 ==
5457 12:20:50.713458 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 12:20:50.716611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 12:20:50.716689 ==
5460 12:20:50.716764 DQS Delay:
5461 12:20:50.719718 DQS0 = 0, DQS1 = 0
5462 12:20:50.719792 DQM Delay:
5463 12:20:50.723413 DQM0 = 104, DQM1 = 92
5464 12:20:50.723497 DQ Delay:
5465 12:20:50.726602 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =98
5466 12:20:50.729783 DQ4 =104, DQ5 =100, DQ6 =110, DQ7 =110
5467 12:20:50.732922 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =90
5468 12:20:50.736179 DQ12 =100, DQ13 =94, DQ14 =100, DQ15 =98
5469 12:20:50.736263
5470 12:20:50.736329
5471 12:20:50.746399 [DQSOSCAuto] RK1, (LSB)MR18= 0x290b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5472 12:20:50.746485 CH0 RK1: MR19=505, MR18=290B
5473 12:20:50.752915 CH0_RK1: MR19=0x505, MR18=0x290B, DQSOSC=408, MR23=63, INC=65, DEC=43
5474 12:20:50.756175 [RxdqsGatingPostProcess] freq 933
5475 12:20:50.762998 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5476 12:20:50.766573 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 12:20:50.769671 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 12:20:50.773231 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 12:20:50.776405 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 12:20:50.776529 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 12:20:50.779579 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 12:20:50.783062 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 12:20:50.786430 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 12:20:50.789489 Pre-setting of DQS Precalculation
5485 12:20:50.796268 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5486 12:20:50.796397 ==
5487 12:20:50.799893 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 12:20:50.802803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 12:20:50.802929 ==
5490 12:20:50.809471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5491 12:20:50.816041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5492 12:20:50.819592 [CA 0] Center 37 (7~68) winsize 62
5493 12:20:50.822851 [CA 1] Center 37 (7~68) winsize 62
5494 12:20:50.825981 [CA 2] Center 36 (6~66) winsize 61
5495 12:20:50.829716 [CA 3] Center 34 (4~65) winsize 62
5496 12:20:50.832849 [CA 4] Center 35 (5~65) winsize 61
5497 12:20:50.832976 [CA 5] Center 34 (4~65) winsize 62
5498 12:20:50.835969
5499 12:20:50.839610 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5500 12:20:50.839728
5501 12:20:50.842791 [CATrainingPosCal] consider 1 rank data
5502 12:20:50.846043 u2DelayCellTimex100 = 270/100 ps
5503 12:20:50.849251 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5504 12:20:50.852658 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5505 12:20:50.856137 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5506 12:20:50.859316 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5507 12:20:50.862928 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5508 12:20:50.866002 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5509 12:20:50.866124
5510 12:20:50.869699 CA PerBit enable=1, Macro0, CA PI delay=34
5511 12:20:50.872845
5512 12:20:50.872970 [CBTSetCACLKResult] CA Dly = 34
5513 12:20:50.875822 CS Dly: 6 (0~37)
5514 12:20:50.875946 ==
5515 12:20:50.879410 Dram Type= 6, Freq= 0, CH_1, rank 1
5516 12:20:50.882628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 12:20:50.882747 ==
5518 12:20:50.889178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 12:20:50.895643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5520 12:20:50.899093 [CA 0] Center 38 (8~68) winsize 61
5521 12:20:50.902551 [CA 1] Center 38 (8~69) winsize 62
5522 12:20:50.905718 [CA 2] Center 36 (5~67) winsize 63
5523 12:20:50.909164 [CA 3] Center 35 (5~65) winsize 61
5524 12:20:50.912483 [CA 4] Center 35 (5~66) winsize 62
5525 12:20:50.915872 [CA 5] Center 35 (5~65) winsize 61
5526 12:20:50.915985
5527 12:20:50.919351 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5528 12:20:50.919460
5529 12:20:50.922523 [CATrainingPosCal] consider 2 rank data
5530 12:20:50.925935 u2DelayCellTimex100 = 270/100 ps
5531 12:20:50.929202 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5532 12:20:50.932389 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5533 12:20:50.936054 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5534 12:20:50.939157 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5535 12:20:50.942311 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5536 12:20:50.945590 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5537 12:20:50.945689
5538 12:20:50.952439 CA PerBit enable=1, Macro0, CA PI delay=35
5539 12:20:50.952544
5540 12:20:50.952635 [CBTSetCACLKResult] CA Dly = 35
5541 12:20:50.955914 CS Dly: 7 (0~39)
5542 12:20:50.956012
5543 12:20:50.958988 ----->DramcWriteLeveling(PI) begin...
5544 12:20:50.959062 ==
5545 12:20:50.962499 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 12:20:50.965621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 12:20:50.965713 ==
5548 12:20:50.968957 Write leveling (Byte 0): 26 => 26
5549 12:20:50.972268 Write leveling (Byte 1): 28 => 28
5550 12:20:50.975992 DramcWriteLeveling(PI) end<-----
5551 12:20:50.976070
5552 12:20:50.976161 ==
5553 12:20:50.979016 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 12:20:50.982217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 12:20:50.985850 ==
5556 12:20:50.985963 [Gating] SW mode calibration
5557 12:20:50.996116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5558 12:20:50.999486 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5559 12:20:51.002102 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 12:20:51.008669 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 12:20:51.012134 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 12:20:51.015468 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 12:20:51.022198 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 12:20:51.025427 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 12:20:51.028732 0 14 24 | B1->B0 | 3232 3131 | 0 0 | (1 0) (0 0)
5566 12:20:51.035480 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5567 12:20:51.039027 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 12:20:51.042165 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 12:20:51.049055 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 12:20:51.052424 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 12:20:51.055314 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 12:20:51.062410 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 12:20:51.065574 0 15 24 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (1 1)
5574 12:20:51.068744 0 15 28 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
5575 12:20:51.072188 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 12:20:51.078566 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 12:20:51.082100 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 12:20:51.085302 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 12:20:51.092449 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 12:20:51.095692 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 12:20:51.098830 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5582 12:20:51.105764 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5583 12:20:51.108901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:20:51.112201 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:20:51.118765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:20:51.122176 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:20:51.125749 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:20:51.132396 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:20:51.135682 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:20:51.138813 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:20:51.145624 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:20:51.148829 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:20:51.152411 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:20:51.158762 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:20:51.162243 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:20:51.165436 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5597 12:20:51.168929 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5598 12:20:51.175444 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5599 12:20:51.178656 Total UI for P1: 0, mck2ui 16
5600 12:20:51.182288 best dqsien dly found for B0: ( 1, 2, 22)
5601 12:20:51.185421 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 12:20:51.189021 Total UI for P1: 0, mck2ui 16
5603 12:20:51.192160 best dqsien dly found for B1: ( 1, 2, 26)
5604 12:20:51.195609 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5605 12:20:51.198862 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5606 12:20:51.198948
5607 12:20:51.201921 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5608 12:20:51.205613 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5609 12:20:51.208633 [Gating] SW calibration Done
5610 12:20:51.208724 ==
5611 12:20:51.212210 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 12:20:51.219006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 12:20:51.219095 ==
5614 12:20:51.219162 RX Vref Scan: 0
5615 12:20:51.219233
5616 12:20:51.222266 RX Vref 0 -> 0, step: 1
5617 12:20:51.222357
5618 12:20:51.225406 RX Delay -80 -> 252, step: 8
5619 12:20:51.228763 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5620 12:20:51.231851 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5621 12:20:51.235435 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5622 12:20:51.238869 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5623 12:20:51.242083 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5624 12:20:51.248483 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5625 12:20:51.252089 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5626 12:20:51.255321 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5627 12:20:51.258442 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5628 12:20:51.261990 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5629 12:20:51.265053 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5630 12:20:51.272175 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5631 12:20:51.275296 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5632 12:20:51.278503 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5633 12:20:51.282409 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5634 12:20:51.285192 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5635 12:20:51.285312 ==
5636 12:20:51.288449 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 12:20:51.295119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 12:20:51.295246 ==
5639 12:20:51.295342 DQS Delay:
5640 12:20:51.298795 DQS0 = 0, DQS1 = 0
5641 12:20:51.298906 DQM Delay:
5642 12:20:51.301919 DQM0 = 102, DQM1 = 95
5643 12:20:51.302018 DQ Delay:
5644 12:20:51.305149 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5645 12:20:51.308726 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5646 12:20:51.311807 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5647 12:20:51.315484 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5648 12:20:51.315592
5649 12:20:51.315685
5650 12:20:51.315774 ==
5651 12:20:51.318571 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 12:20:51.321729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 12:20:51.321840 ==
5654 12:20:51.321946
5655 12:20:51.322036
5656 12:20:51.324964 TX Vref Scan disable
5657 12:20:51.328372 == TX Byte 0 ==
5658 12:20:51.331756 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 12:20:51.335111 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 12:20:51.338277 == TX Byte 1 ==
5661 12:20:51.341788 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5662 12:20:51.345017 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5663 12:20:51.345144 ==
5664 12:20:51.348393 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 12:20:51.354619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 12:20:51.354698 ==
5667 12:20:51.354815
5668 12:20:51.354875
5669 12:20:51.354965 TX Vref Scan disable
5670 12:20:51.358923 == TX Byte 0 ==
5671 12:20:51.362018 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5672 12:20:51.365773 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5673 12:20:51.369087 == TX Byte 1 ==
5674 12:20:51.372112 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5675 12:20:51.375466 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5676 12:20:51.379041
5677 12:20:51.379152 [DATLAT]
5678 12:20:51.379248 Freq=933, CH1 RK0
5679 12:20:51.379343
5680 12:20:51.382134 DATLAT Default: 0xd
5681 12:20:51.382236 0, 0xFFFF, sum = 0
5682 12:20:51.385324 1, 0xFFFF, sum = 0
5683 12:20:51.385399 2, 0xFFFF, sum = 0
5684 12:20:51.388993 3, 0xFFFF, sum = 0
5685 12:20:51.389066 4, 0xFFFF, sum = 0
5686 12:20:51.391887 5, 0xFFFF, sum = 0
5687 12:20:51.395558 6, 0xFFFF, sum = 0
5688 12:20:51.395631 7, 0xFFFF, sum = 0
5689 12:20:51.398746 8, 0xFFFF, sum = 0
5690 12:20:51.398829 9, 0xFFFF, sum = 0
5691 12:20:51.401904 10, 0x0, sum = 1
5692 12:20:51.401987 11, 0x0, sum = 2
5693 12:20:51.402054 12, 0x0, sum = 3
5694 12:20:51.405122 13, 0x0, sum = 4
5695 12:20:51.405206 best_step = 11
5696 12:20:51.405271
5697 12:20:51.408708 ==
5698 12:20:51.408826 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 12:20:51.415217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 12:20:51.415333 ==
5701 12:20:51.415429 RX Vref Scan: 1
5702 12:20:51.415520
5703 12:20:51.418625 RX Vref 0 -> 0, step: 1
5704 12:20:51.418723
5705 12:20:51.422229 RX Delay -53 -> 252, step: 4
5706 12:20:51.422329
5707 12:20:51.425047 Set Vref, RX VrefLevel [Byte0]: 51
5708 12:20:51.428308 [Byte1]: 57
5709 12:20:51.428393
5710 12:20:51.431784 Final RX Vref Byte 0 = 51 to rank0
5711 12:20:51.435191 Final RX Vref Byte 1 = 57 to rank0
5712 12:20:51.438505 Final RX Vref Byte 0 = 51 to rank1
5713 12:20:51.441967 Final RX Vref Byte 1 = 57 to rank1==
5714 12:20:51.445385 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 12:20:51.448526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 12:20:51.448636 ==
5717 12:20:51.451935 DQS Delay:
5718 12:20:51.452033 DQS0 = 0, DQS1 = 0
5719 12:20:51.454977 DQM Delay:
5720 12:20:51.455060 DQM0 = 104, DQM1 = 97
5721 12:20:51.455127 DQ Delay:
5722 12:20:51.458554 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5723 12:20:51.465349 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5724 12:20:51.468404 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =92
5725 12:20:51.472033 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =102
5726 12:20:51.472115
5727 12:20:51.472188
5728 12:20:51.478601 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e36, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5729 12:20:51.481844 CH1 RK0: MR19=505, MR18=1E36
5730 12:20:51.488536 CH1_RK0: MR19=0x505, MR18=0x1E36, DQSOSC=404, MR23=63, INC=66, DEC=44
5731 12:20:51.488615
5732 12:20:51.491622 ----->DramcWriteLeveling(PI) begin...
5733 12:20:51.491700 ==
5734 12:20:51.494817 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 12:20:51.498075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:20:51.498161 ==
5737 12:20:51.501662 Write leveling (Byte 0): 24 => 24
5738 12:20:51.504938 Write leveling (Byte 1): 31 => 31
5739 12:20:51.508267 DramcWriteLeveling(PI) end<-----
5740 12:20:51.508349
5741 12:20:51.508413 ==
5742 12:20:51.511705 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 12:20:51.514763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 12:20:51.514877 ==
5745 12:20:51.518096 [Gating] SW mode calibration
5746 12:20:51.524810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5747 12:20:51.531518 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5748 12:20:51.534666 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 12:20:51.541393 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 12:20:51.544714 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 12:20:51.547932 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 12:20:51.554808 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 12:20:51.558270 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 12:20:51.561359 0 14 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
5755 12:20:51.564926 0 14 28 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
5756 12:20:51.571306 0 15 0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5757 12:20:51.574799 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 12:20:51.578038 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 12:20:51.585024 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 12:20:51.588103 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 12:20:51.591169 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 12:20:51.597885 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5763 12:20:51.601458 0 15 28 | B1->B0 | 4545 3e3e | 0 1 | (0 0) (0 0)
5764 12:20:51.604708 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5765 12:20:51.611128 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 12:20:51.614334 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 12:20:51.617964 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 12:20:51.624202 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 12:20:51.627723 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 12:20:51.630823 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5771 12:20:51.637575 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5772 12:20:51.640987 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:20:51.644043 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:20:51.650748 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:20:51.654123 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:20:51.657258 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:20:51.664147 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:20:51.667267 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:20:51.670497 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:20:51.677175 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:20:51.680497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:20:51.683874 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:20:51.690286 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:20:51.693810 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:20:51.696888 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:20:51.703907 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5787 12:20:51.706978 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5788 12:20:51.710185 Total UI for P1: 0, mck2ui 16
5789 12:20:51.713882 best dqsien dly found for B1: ( 1, 2, 24)
5790 12:20:51.717037 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 12:20:51.720226 Total UI for P1: 0, mck2ui 16
5792 12:20:51.723384 best dqsien dly found for B0: ( 1, 2, 26)
5793 12:20:51.726540 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5794 12:20:51.730056 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5795 12:20:51.730159
5796 12:20:51.736710 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5797 12:20:51.739847 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5798 12:20:51.743497 [Gating] SW calibration Done
5799 12:20:51.743600 ==
5800 12:20:51.746588 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 12:20:51.749824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 12:20:51.749928 ==
5803 12:20:51.750030 RX Vref Scan: 0
5804 12:20:51.750122
5805 12:20:51.753263 RX Vref 0 -> 0, step: 1
5806 12:20:51.753364
5807 12:20:51.756396 RX Delay -80 -> 252, step: 8
5808 12:20:51.759802 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5809 12:20:51.763210 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5810 12:20:51.769720 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5811 12:20:51.773157 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5812 12:20:51.776506 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5813 12:20:51.779636 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5814 12:20:51.783534 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5815 12:20:51.786629 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5816 12:20:51.793163 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5817 12:20:51.796576 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5818 12:20:51.799799 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5819 12:20:51.803179 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5820 12:20:51.806219 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5821 12:20:51.812904 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5822 12:20:51.816192 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5823 12:20:51.819273 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5824 12:20:51.819352 ==
5825 12:20:51.822547 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 12:20:51.826228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 12:20:51.826305 ==
5828 12:20:51.829476 DQS Delay:
5829 12:20:51.829560 DQS0 = 0, DQS1 = 0
5830 12:20:51.829626 DQM Delay:
5831 12:20:51.832593 DQM0 = 102, DQM1 = 95
5832 12:20:51.832675 DQ Delay:
5833 12:20:51.836246 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5834 12:20:51.839129 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =99
5835 12:20:51.842748 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5836 12:20:51.845926 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5837 12:20:51.849222
5838 12:20:51.849304
5839 12:20:51.849370 ==
5840 12:20:51.852577 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 12:20:51.855724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 12:20:51.855803 ==
5843 12:20:51.855868
5844 12:20:51.855927
5845 12:20:51.859373 TX Vref Scan disable
5846 12:20:51.859457 == TX Byte 0 ==
5847 12:20:51.865740 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5848 12:20:51.869071 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5849 12:20:51.869178 == TX Byte 1 ==
5850 12:20:51.875542 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5851 12:20:51.878921 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5852 12:20:51.879020 ==
5853 12:20:51.882350 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 12:20:51.885568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 12:20:51.885646 ==
5856 12:20:51.885710
5857 12:20:51.885770
5858 12:20:51.889056 TX Vref Scan disable
5859 12:20:51.892143 == TX Byte 0 ==
5860 12:20:51.895554 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5861 12:20:51.898762 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5862 12:20:51.902425 == TX Byte 1 ==
5863 12:20:51.905524 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5864 12:20:51.908877 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5865 12:20:51.909010
5866 12:20:51.912338 [DATLAT]
5867 12:20:51.912476 Freq=933, CH1 RK1
5868 12:20:51.912609
5869 12:20:51.915691 DATLAT Default: 0xb
5870 12:20:51.915810 0, 0xFFFF, sum = 0
5871 12:20:51.918605 1, 0xFFFF, sum = 0
5872 12:20:51.918729 2, 0xFFFF, sum = 0
5873 12:20:51.922120 3, 0xFFFF, sum = 0
5874 12:20:51.922259 4, 0xFFFF, sum = 0
5875 12:20:51.925352 5, 0xFFFF, sum = 0
5876 12:20:51.925461 6, 0xFFFF, sum = 0
5877 12:20:51.929038 7, 0xFFFF, sum = 0
5878 12:20:51.929123 8, 0xFFFF, sum = 0
5879 12:20:51.932153 9, 0xFFFF, sum = 0
5880 12:20:51.932238 10, 0x0, sum = 1
5881 12:20:51.935365 11, 0x0, sum = 2
5882 12:20:51.935466 12, 0x0, sum = 3
5883 12:20:51.938948 13, 0x0, sum = 4
5884 12:20:51.939063 best_step = 11
5885 12:20:51.939162
5886 12:20:51.939254 ==
5887 12:20:51.942101 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 12:20:51.948743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 12:20:51.948847 ==
5890 12:20:51.948917 RX Vref Scan: 0
5891 12:20:51.948983
5892 12:20:51.952553 RX Vref 0 -> 0, step: 1
5893 12:20:51.952653
5894 12:20:51.955432 RX Delay -53 -> 252, step: 4
5895 12:20:51.958850 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5896 12:20:51.961870 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5897 12:20:51.969121 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5898 12:20:51.972114 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5899 12:20:51.975374 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5900 12:20:51.978656 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5901 12:20:51.981894 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5902 12:20:51.988987 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5903 12:20:51.992299 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5904 12:20:51.995454 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5905 12:20:51.998586 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5906 12:20:52.001968 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5907 12:20:52.005444 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5908 12:20:52.012215 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5909 12:20:52.015169 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5910 12:20:52.018783 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5911 12:20:52.018903 ==
5912 12:20:52.022059 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 12:20:52.025297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 12:20:52.025418 ==
5915 12:20:52.028635 DQS Delay:
5916 12:20:52.028742 DQS0 = 0, DQS1 = 0
5917 12:20:52.032197 DQM Delay:
5918 12:20:52.032309 DQM0 = 104, DQM1 = 97
5919 12:20:52.032400 DQ Delay:
5920 12:20:52.035192 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5921 12:20:52.042062 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =104
5922 12:20:52.045103 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5923 12:20:52.048770 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5924 12:20:52.048885
5925 12:20:52.048950
5926 12:20:52.055491 [DQSOSCAuto] RK1, (LSB)MR18= 0x23ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5927 12:20:52.058527 CH1 RK1: MR19=504, MR18=23FF
5928 12:20:52.065077 CH1_RK1: MR19=0x504, MR18=0x23FF, DQSOSC=410, MR23=63, INC=64, DEC=42
5929 12:20:52.068290 [RxdqsGatingPostProcess] freq 933
5930 12:20:52.071808 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5931 12:20:52.075056 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 12:20:52.078549 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 12:20:52.081595 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 12:20:52.085263 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 12:20:52.088577 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 12:20:52.091462 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 12:20:52.095034 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 12:20:52.098287 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 12:20:52.101723 Pre-setting of DQS Precalculation
5940 12:20:52.104843 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5941 12:20:52.115074 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5942 12:20:52.121451 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5943 12:20:52.121542
5944 12:20:52.121609
5945 12:20:52.124764 [Calibration Summary] 1866 Mbps
5946 12:20:52.124852 CH 0, Rank 0
5947 12:20:52.128386 SW Impedance : PASS
5948 12:20:52.128471 DUTY Scan : NO K
5949 12:20:52.131573 ZQ Calibration : PASS
5950 12:20:52.134756 Jitter Meter : NO K
5951 12:20:52.134842 CBT Training : PASS
5952 12:20:52.138326 Write leveling : PASS
5953 12:20:52.141324 RX DQS gating : PASS
5954 12:20:52.141412 RX DQ/DQS(RDDQC) : PASS
5955 12:20:52.144528 TX DQ/DQS : PASS
5956 12:20:52.148144 RX DATLAT : PASS
5957 12:20:52.148222 RX DQ/DQS(Engine): PASS
5958 12:20:52.151288 TX OE : NO K
5959 12:20:52.151375 All Pass.
5960 12:20:52.151440
5961 12:20:52.154504 CH 0, Rank 1
5962 12:20:52.154586 SW Impedance : PASS
5963 12:20:52.158153 DUTY Scan : NO K
5964 12:20:52.161217 ZQ Calibration : PASS
5965 12:20:52.161293 Jitter Meter : NO K
5966 12:20:52.164843 CBT Training : PASS
5967 12:20:52.164917 Write leveling : PASS
5968 12:20:52.167923 RX DQS gating : PASS
5969 12:20:52.171138 RX DQ/DQS(RDDQC) : PASS
5970 12:20:52.171214 TX DQ/DQS : PASS
5971 12:20:52.174679 RX DATLAT : PASS
5972 12:20:52.177967 RX DQ/DQS(Engine): PASS
5973 12:20:52.178048 TX OE : NO K
5974 12:20:52.181097 All Pass.
5975 12:20:52.181182
5976 12:20:52.181249 CH 1, Rank 0
5977 12:20:52.184626 SW Impedance : PASS
5978 12:20:52.184705 DUTY Scan : NO K
5979 12:20:52.187933 ZQ Calibration : PASS
5980 12:20:52.191724 Jitter Meter : NO K
5981 12:20:52.191805 CBT Training : PASS
5982 12:20:52.194624 Write leveling : PASS
5983 12:20:52.197981 RX DQS gating : PASS
5984 12:20:52.198099 RX DQ/DQS(RDDQC) : PASS
5985 12:20:52.201477 TX DQ/DQS : PASS
5986 12:20:52.204595 RX DATLAT : PASS
5987 12:20:52.204679 RX DQ/DQS(Engine): PASS
5988 12:20:52.208030 TX OE : NO K
5989 12:20:52.208116 All Pass.
5990 12:20:52.208187
5991 12:20:52.211357 CH 1, Rank 1
5992 12:20:52.211443 SW Impedance : PASS
5993 12:20:52.214734 DUTY Scan : NO K
5994 12:20:52.214821 ZQ Calibration : PASS
5995 12:20:52.217958 Jitter Meter : NO K
5996 12:20:52.221743 CBT Training : PASS
5997 12:20:52.221851 Write leveling : PASS
5998 12:20:52.224595 RX DQS gating : PASS
5999 12:20:52.227815 RX DQ/DQS(RDDQC) : PASS
6000 12:20:52.227899 TX DQ/DQS : PASS
6001 12:20:52.231138 RX DATLAT : PASS
6002 12:20:52.234361 RX DQ/DQS(Engine): PASS
6003 12:20:52.234470 TX OE : NO K
6004 12:20:52.237990 All Pass.
6005 12:20:52.238101
6006 12:20:52.238197 DramC Write-DBI off
6007 12:20:52.240987 PER_BANK_REFRESH: Hybrid Mode
6008 12:20:52.241062 TX_TRACKING: ON
6009 12:20:52.251376 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6010 12:20:52.254555 [FAST_K] Save calibration result to emmc
6011 12:20:52.257661 dramc_set_vcore_voltage set vcore to 650000
6012 12:20:52.261206 Read voltage for 400, 6
6013 12:20:52.261281 Vio18 = 0
6014 12:20:52.264335 Vcore = 650000
6015 12:20:52.264439 Vdram = 0
6016 12:20:52.264531 Vddq = 0
6017 12:20:52.267920 Vmddr = 0
6018 12:20:52.270893 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6019 12:20:52.277568 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6020 12:20:52.277648 MEM_TYPE=3, freq_sel=20
6021 12:20:52.280783 sv_algorithm_assistance_LP4_800
6022 12:20:52.284320 ============ PULL DRAM RESETB DOWN ============
6023 12:20:52.291010 ========== PULL DRAM RESETB DOWN end =========
6024 12:20:52.294217 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6025 12:20:52.298111 ===================================
6026 12:20:52.300834 LPDDR4 DRAM CONFIGURATION
6027 12:20:52.304285 ===================================
6028 12:20:52.304395 EX_ROW_EN[0] = 0x0
6029 12:20:52.307728 EX_ROW_EN[1] = 0x0
6030 12:20:52.307821 LP4Y_EN = 0x0
6031 12:20:52.310992 WORK_FSP = 0x0
6032 12:20:52.314405 WL = 0x2
6033 12:20:52.314513 RL = 0x2
6034 12:20:52.317748 BL = 0x2
6035 12:20:52.317859 RPST = 0x0
6036 12:20:52.320777 RD_PRE = 0x0
6037 12:20:52.320882 WR_PRE = 0x1
6038 12:20:52.324458 WR_PST = 0x0
6039 12:20:52.324563 DBI_WR = 0x0
6040 12:20:52.327714 DBI_RD = 0x0
6041 12:20:52.327823 OTF = 0x1
6042 12:20:52.331228 ===================================
6043 12:20:52.334468 ===================================
6044 12:20:52.337659 ANA top config
6045 12:20:52.341083 ===================================
6046 12:20:52.341196 DLL_ASYNC_EN = 0
6047 12:20:52.344294 ALL_SLAVE_EN = 1
6048 12:20:52.347457 NEW_RANK_MODE = 1
6049 12:20:52.350742 DLL_IDLE_MODE = 1
6050 12:20:52.350845 LP45_APHY_COMB_EN = 1
6051 12:20:52.354385 TX_ODT_DIS = 1
6052 12:20:52.357658 NEW_8X_MODE = 1
6053 12:20:52.360791 ===================================
6054 12:20:52.364206 ===================================
6055 12:20:52.367363 data_rate = 800
6056 12:20:52.370886 CKR = 1
6057 12:20:52.374036 DQ_P2S_RATIO = 4
6058 12:20:52.377654 ===================================
6059 12:20:52.377739 CA_P2S_RATIO = 4
6060 12:20:52.381185 DQ_CA_OPEN = 0
6061 12:20:52.384390 DQ_SEMI_OPEN = 1
6062 12:20:52.387444 CA_SEMI_OPEN = 1
6063 12:20:52.391021 CA_FULL_RATE = 0
6064 12:20:52.391122 DQ_CKDIV4_EN = 0
6065 12:20:52.394041 CA_CKDIV4_EN = 1
6066 12:20:52.397471 CA_PREDIV_EN = 0
6067 12:20:52.401071 PH8_DLY = 0
6068 12:20:52.404511 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6069 12:20:52.407786 DQ_AAMCK_DIV = 0
6070 12:20:52.407889 CA_AAMCK_DIV = 0
6071 12:20:52.410869 CA_ADMCK_DIV = 4
6072 12:20:52.414172 DQ_TRACK_CA_EN = 0
6073 12:20:52.417396 CA_PICK = 800
6074 12:20:52.420702 CA_MCKIO = 400
6075 12:20:52.424039 MCKIO_SEMI = 400
6076 12:20:52.427460 PLL_FREQ = 3016
6077 12:20:52.430830 DQ_UI_PI_RATIO = 32
6078 12:20:52.430950 CA_UI_PI_RATIO = 32
6079 12:20:52.433791 ===================================
6080 12:20:52.437264 ===================================
6081 12:20:52.440454 memory_type:LPDDR4
6082 12:20:52.443585 GP_NUM : 10
6083 12:20:52.443688 SRAM_EN : 1
6084 12:20:52.447228 MD32_EN : 0
6085 12:20:52.450320 ===================================
6086 12:20:52.453874 [ANA_INIT] >>>>>>>>>>>>>>
6087 12:20:52.457092 <<<<<< [CONFIGURE PHASE]: ANA_TX
6088 12:20:52.460580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6089 12:20:52.463723 ===================================
6090 12:20:52.463871 data_rate = 800,PCW = 0X7400
6091 12:20:52.466901 ===================================
6092 12:20:52.470523 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6093 12:20:52.476882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 12:20:52.490325 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 12:20:52.493419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6096 12:20:52.497043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6097 12:20:52.500014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6098 12:20:52.503695 [ANA_INIT] flow start
6099 12:20:52.503802 [ANA_INIT] PLL >>>>>>>>
6100 12:20:52.506844 [ANA_INIT] PLL <<<<<<<<
6101 12:20:52.510359 [ANA_INIT] MIDPI >>>>>>>>
6102 12:20:52.510474 [ANA_INIT] MIDPI <<<<<<<<
6103 12:20:52.513435 [ANA_INIT] DLL >>>>>>>>
6104 12:20:52.516866 [ANA_INIT] flow end
6105 12:20:52.520056 ============ LP4 DIFF to SE enter ============
6106 12:20:52.523379 ============ LP4 DIFF to SE exit ============
6107 12:20:52.526878 [ANA_INIT] <<<<<<<<<<<<<
6108 12:20:52.530323 [Flow] Enable top DCM control >>>>>
6109 12:20:52.533533 [Flow] Enable top DCM control <<<<<
6110 12:20:52.536629 Enable DLL master slave shuffle
6111 12:20:52.539956 ==============================================================
6112 12:20:52.543174 Gating Mode config
6113 12:20:52.549934 ==============================================================
6114 12:20:52.550025 Config description:
6115 12:20:52.560146 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6116 12:20:52.566726 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6117 12:20:52.569989 SELPH_MODE 0: By rank 1: By Phase
6118 12:20:52.576305 ==============================================================
6119 12:20:52.579527 GAT_TRACK_EN = 0
6120 12:20:52.583305 RX_GATING_MODE = 2
6121 12:20:52.586445 RX_GATING_TRACK_MODE = 2
6122 12:20:52.589647 SELPH_MODE = 1
6123 12:20:52.593125 PICG_EARLY_EN = 1
6124 12:20:52.596212 VALID_LAT_VALUE = 1
6125 12:20:52.599882 ==============================================================
6126 12:20:52.602892 Enter into Gating configuration >>>>
6127 12:20:52.606452 Exit from Gating configuration <<<<
6128 12:20:52.609658 Enter into DVFS_PRE_config >>>>>
6129 12:20:52.623132 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6130 12:20:52.623252 Exit from DVFS_PRE_config <<<<<
6131 12:20:52.626590 Enter into PICG configuration >>>>
6132 12:20:52.630141 Exit from PICG configuration <<<<
6133 12:20:52.633273 [RX_INPUT] configuration >>>>>
6134 12:20:52.636480 [RX_INPUT] configuration <<<<<
6135 12:20:52.643157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6136 12:20:52.646614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6137 12:20:52.652736 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6138 12:20:52.659458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6139 12:20:52.666278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 12:20:52.673016 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 12:20:52.676245 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6142 12:20:52.679550 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6143 12:20:52.683087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6144 12:20:52.689535 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6145 12:20:52.692723 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6146 12:20:52.696291 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6147 12:20:52.699509 ===================================
6148 12:20:52.702706 LPDDR4 DRAM CONFIGURATION
6149 12:20:52.706218 ===================================
6150 12:20:52.706347 EX_ROW_EN[0] = 0x0
6151 12:20:52.709681 EX_ROW_EN[1] = 0x0
6152 12:20:52.712860 LP4Y_EN = 0x0
6153 12:20:52.712985 WORK_FSP = 0x0
6154 12:20:52.716408 WL = 0x2
6155 12:20:52.716536 RL = 0x2
6156 12:20:52.719551 BL = 0x2
6157 12:20:52.719678 RPST = 0x0
6158 12:20:52.723054 RD_PRE = 0x0
6159 12:20:52.723179 WR_PRE = 0x1
6160 12:20:52.726163 WR_PST = 0x0
6161 12:20:52.726289 DBI_WR = 0x0
6162 12:20:52.729311 DBI_RD = 0x0
6163 12:20:52.729438 OTF = 0x1
6164 12:20:52.732723 ===================================
6165 12:20:52.735916 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6166 12:20:52.742663 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6167 12:20:52.746025 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 12:20:52.749676 ===================================
6169 12:20:52.752823 LPDDR4 DRAM CONFIGURATION
6170 12:20:52.755991 ===================================
6171 12:20:52.756077 EX_ROW_EN[0] = 0x10
6172 12:20:52.759613 EX_ROW_EN[1] = 0x0
6173 12:20:52.759729 LP4Y_EN = 0x0
6174 12:20:52.762735 WORK_FSP = 0x0
6175 12:20:52.762852 WL = 0x2
6176 12:20:52.766290 RL = 0x2
6177 12:20:52.769467 BL = 0x2
6178 12:20:52.769618 RPST = 0x0
6179 12:20:52.772636 RD_PRE = 0x0
6180 12:20:52.772737 WR_PRE = 0x1
6181 12:20:52.775884 WR_PST = 0x0
6182 12:20:52.775982 DBI_WR = 0x0
6183 12:20:52.779587 DBI_RD = 0x0
6184 12:20:52.779660 OTF = 0x1
6185 12:20:52.782784 ===================================
6186 12:20:52.789449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6187 12:20:52.793006 nWR fixed to 30
6188 12:20:52.796710 [ModeRegInit_LP4] CH0 RK0
6189 12:20:52.796858 [ModeRegInit_LP4] CH0 RK1
6190 12:20:52.799741 [ModeRegInit_LP4] CH1 RK0
6191 12:20:52.803165 [ModeRegInit_LP4] CH1 RK1
6192 12:20:52.803259 match AC timing 19
6193 12:20:52.809935 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6194 12:20:52.812920 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6195 12:20:52.816574 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6196 12:20:52.823451 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6197 12:20:52.826341 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6198 12:20:52.826461 ==
6199 12:20:52.829411 Dram Type= 6, Freq= 0, CH_0, rank 0
6200 12:20:52.833033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6201 12:20:52.833117 ==
6202 12:20:52.839573 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6203 12:20:52.846427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6204 12:20:52.849590 [CA 0] Center 36 (8~64) winsize 57
6205 12:20:52.852821 [CA 1] Center 36 (8~64) winsize 57
6206 12:20:52.856030 [CA 2] Center 36 (8~64) winsize 57
6207 12:20:52.856179 [CA 3] Center 36 (8~64) winsize 57
6208 12:20:52.859717 [CA 4] Center 36 (8~64) winsize 57
6209 12:20:52.863005 [CA 5] Center 36 (8~64) winsize 57
6210 12:20:52.863088
6211 12:20:52.869351 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6212 12:20:52.869434
6213 12:20:52.872955 [CATrainingPosCal] consider 1 rank data
6214 12:20:52.876108 u2DelayCellTimex100 = 270/100 ps
6215 12:20:52.879719 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 12:20:52.882736 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 12:20:52.885892 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 12:20:52.889585 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 12:20:52.892702 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 12:20:52.896026 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 12:20:52.896103
6222 12:20:52.899531 CA PerBit enable=1, Macro0, CA PI delay=36
6223 12:20:52.899608
6224 12:20:52.902718 [CBTSetCACLKResult] CA Dly = 36
6225 12:20:52.906349 CS Dly: 1 (0~32)
6226 12:20:52.906425 ==
6227 12:20:52.909365 Dram Type= 6, Freq= 0, CH_0, rank 1
6228 12:20:52.912563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 12:20:52.912676 ==
6230 12:20:52.919227 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 12:20:52.922874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6232 12:20:52.926169 [CA 0] Center 36 (8~64) winsize 57
6233 12:20:52.929159 [CA 1] Center 36 (8~64) winsize 57
6234 12:20:52.932590 [CA 2] Center 36 (8~64) winsize 57
6235 12:20:52.936022 [CA 3] Center 36 (8~64) winsize 57
6236 12:20:52.939319 [CA 4] Center 36 (8~64) winsize 57
6237 12:20:52.942926 [CA 5] Center 36 (8~64) winsize 57
6238 12:20:52.943027
6239 12:20:52.946278 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6240 12:20:52.946385
6241 12:20:52.949588 [CATrainingPosCal] consider 2 rank data
6242 12:20:52.952562 u2DelayCellTimex100 = 270/100 ps
6243 12:20:52.956360 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:20:52.959366 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:20:52.962732 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:20:52.969389 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:20:52.972600 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:20:52.976085 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:20:52.976165
6250 12:20:52.979269 CA PerBit enable=1, Macro0, CA PI delay=36
6251 12:20:52.979389
6252 12:20:52.982595 [CBTSetCACLKResult] CA Dly = 36
6253 12:20:52.982685 CS Dly: 1 (0~32)
6254 12:20:52.982755
6255 12:20:52.985778 ----->DramcWriteLeveling(PI) begin...
6256 12:20:52.985866 ==
6257 12:20:52.989377 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 12:20:52.995828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 12:20:52.995915 ==
6260 12:20:52.998918 Write leveling (Byte 0): 40 => 8
6261 12:20:53.002549 Write leveling (Byte 1): 32 => 0
6262 12:20:53.002634 DramcWriteLeveling(PI) end<-----
6263 12:20:53.002703
6264 12:20:53.005621 ==
6265 12:20:53.009196 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 12:20:53.012212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 12:20:53.012298 ==
6268 12:20:53.015801 [Gating] SW mode calibration
6269 12:20:53.022444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6270 12:20:53.025968 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6271 12:20:53.032601 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 12:20:53.035802 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 12:20:53.038880 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 12:20:53.045472 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 12:20:53.048783 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 12:20:53.052204 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 12:20:53.058708 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 12:20:53.062174 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 12:20:53.065405 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 12:20:53.068701 Total UI for P1: 0, mck2ui 16
6281 12:20:53.072503 best dqsien dly found for B0: ( 0, 14, 24)
6282 12:20:53.075514 Total UI for P1: 0, mck2ui 16
6283 12:20:53.078919 best dqsien dly found for B1: ( 0, 14, 24)
6284 12:20:53.082253 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6285 12:20:53.085382 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6286 12:20:53.085508
6287 12:20:53.092228 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 12:20:53.095311 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 12:20:53.095435 [Gating] SW calibration Done
6290 12:20:53.099002 ==
6291 12:20:53.101938 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 12:20:53.105229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 12:20:53.105323 ==
6294 12:20:53.105386 RX Vref Scan: 0
6295 12:20:53.105446
6296 12:20:53.108759 RX Vref 0 -> 0, step: 1
6297 12:20:53.108857
6298 12:20:53.111938 RX Delay -410 -> 252, step: 16
6299 12:20:53.115163 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6300 12:20:53.121988 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6301 12:20:53.124969 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6302 12:20:53.128687 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6303 12:20:53.131866 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6304 12:20:53.138531 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6305 12:20:53.141561 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6306 12:20:53.145095 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6307 12:20:53.148676 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6308 12:20:53.151863 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6309 12:20:53.158615 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6310 12:20:53.161974 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6311 12:20:53.165167 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6312 12:20:53.168498 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6313 12:20:53.175326 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6314 12:20:53.178571 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6315 12:20:53.178653 ==
6316 12:20:53.182245 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 12:20:53.185016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 12:20:53.185100 ==
6319 12:20:53.188217 DQS Delay:
6320 12:20:53.188298 DQS0 = 27, DQS1 = 43
6321 12:20:53.191976 DQM Delay:
6322 12:20:53.192057 DQM0 = 14, DQM1 = 13
6323 12:20:53.192122 DQ Delay:
6324 12:20:53.194985 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6325 12:20:53.198596 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6326 12:20:53.201692 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6327 12:20:53.204856 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6328 12:20:53.204938
6329 12:20:53.205003
6330 12:20:53.205063 ==
6331 12:20:53.208375 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 12:20:53.215049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 12:20:53.215140 ==
6334 12:20:53.215208
6335 12:20:53.215270
6336 12:20:53.215330 TX Vref Scan disable
6337 12:20:53.218445 == TX Byte 0 ==
6338 12:20:53.221976 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 12:20:53.225170 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 12:20:53.228537 == TX Byte 1 ==
6341 12:20:53.231720 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6342 12:20:53.235363 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6343 12:20:53.235449 ==
6344 12:20:53.238527 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 12:20:53.244742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 12:20:53.244838 ==
6347 12:20:53.244927
6348 12:20:53.245009
6349 12:20:53.248365 TX Vref Scan disable
6350 12:20:53.248452 == TX Byte 0 ==
6351 12:20:53.251776 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 12:20:53.255123 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 12:20:53.258548 == TX Byte 1 ==
6354 12:20:53.261688 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6355 12:20:53.265137 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6356 12:20:53.268322
6357 12:20:53.268407 [DATLAT]
6358 12:20:53.268495 Freq=400, CH0 RK0
6359 12:20:53.268578
6360 12:20:53.271282 DATLAT Default: 0xf
6361 12:20:53.271368 0, 0xFFFF, sum = 0
6362 12:20:53.274952 1, 0xFFFF, sum = 0
6363 12:20:53.275039 2, 0xFFFF, sum = 0
6364 12:20:53.278257 3, 0xFFFF, sum = 0
6365 12:20:53.281230 4, 0xFFFF, sum = 0
6366 12:20:53.281318 5, 0xFFFF, sum = 0
6367 12:20:53.284691 6, 0xFFFF, sum = 0
6368 12:20:53.284843 7, 0xFFFF, sum = 0
6369 12:20:53.288157 8, 0xFFFF, sum = 0
6370 12:20:53.288259 9, 0xFFFF, sum = 0
6371 12:20:53.291541 10, 0xFFFF, sum = 0
6372 12:20:53.291627 11, 0xFFFF, sum = 0
6373 12:20:53.294664 12, 0xFFFF, sum = 0
6374 12:20:53.294749 13, 0x0, sum = 1
6375 12:20:53.298157 14, 0x0, sum = 2
6376 12:20:53.298241 15, 0x0, sum = 3
6377 12:20:53.301329 16, 0x0, sum = 4
6378 12:20:53.301445 best_step = 14
6379 12:20:53.301545
6380 12:20:53.301639 ==
6381 12:20:53.305032 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 12:20:53.308477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 12:20:53.308578 ==
6384 12:20:53.311394 RX Vref Scan: 1
6385 12:20:53.311516
6386 12:20:53.314763 RX Vref 0 -> 0, step: 1
6387 12:20:53.314883
6388 12:20:53.314996 RX Delay -327 -> 252, step: 8
6389 12:20:53.318047
6390 12:20:53.318162 Set Vref, RX VrefLevel [Byte0]: 58
6391 12:20:53.321626 [Byte1]: 50
6392 12:20:53.327088
6393 12:20:53.327210 Final RX Vref Byte 0 = 58 to rank0
6394 12:20:53.330368 Final RX Vref Byte 1 = 50 to rank0
6395 12:20:53.333573 Final RX Vref Byte 0 = 58 to rank1
6396 12:20:53.337223 Final RX Vref Byte 1 = 50 to rank1==
6397 12:20:53.340484 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 12:20:53.346766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 12:20:53.346849 ==
6400 12:20:53.346915 DQS Delay:
6401 12:20:53.350194 DQS0 = 28, DQS1 = 48
6402 12:20:53.350277 DQM Delay:
6403 12:20:53.350343 DQM0 = 12, DQM1 = 15
6404 12:20:53.353338 DQ Delay:
6405 12:20:53.356931 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6406 12:20:53.357014 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6407 12:20:53.360133 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6408 12:20:53.363833 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6409 12:20:53.363917
6410 12:20:53.367091
6411 12:20:53.373756 [DQSOSCAuto] RK0, (LSB)MR18= 0xada4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6412 12:20:53.376718 CH0 RK0: MR19=C0C, MR18=ADA4
6413 12:20:53.383707 CH0_RK0: MR19=0xC0C, MR18=0xADA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6414 12:20:53.383794 ==
6415 12:20:53.386923 Dram Type= 6, Freq= 0, CH_0, rank 1
6416 12:20:53.390505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 12:20:53.390607 ==
6418 12:20:53.393515 [Gating] SW mode calibration
6419 12:20:53.400296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6420 12:20:53.406616 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6421 12:20:53.410141 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 12:20:53.413562 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 12:20:53.419894 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 12:20:53.423303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 12:20:53.426512 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 12:20:53.429679 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 12:20:53.436349 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 12:20:53.439759 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 12:20:53.443212 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 12:20:53.446436 Total UI for P1: 0, mck2ui 16
6431 12:20:53.449650 best dqsien dly found for B0: ( 0, 14, 24)
6432 12:20:53.453033 Total UI for P1: 0, mck2ui 16
6433 12:20:53.456653 best dqsien dly found for B1: ( 0, 14, 24)
6434 12:20:53.459799 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6435 12:20:53.466592 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6436 12:20:53.466672
6437 12:20:53.469725 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 12:20:53.472959 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 12:20:53.476383 [Gating] SW calibration Done
6440 12:20:53.476455 ==
6441 12:20:53.479872 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 12:20:53.482894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 12:20:53.482978 ==
6444 12:20:53.483045 RX Vref Scan: 0
6445 12:20:53.486380
6446 12:20:53.486463 RX Vref 0 -> 0, step: 1
6447 12:20:53.486530
6448 12:20:53.489679 RX Delay -410 -> 252, step: 16
6449 12:20:53.493076 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6450 12:20:53.499717 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6451 12:20:53.503165 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6452 12:20:53.506434 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6453 12:20:53.509759 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6454 12:20:53.516090 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6455 12:20:53.520080 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6456 12:20:53.522693 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6457 12:20:53.526465 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6458 12:20:53.532980 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6459 12:20:53.536087 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6460 12:20:53.539676 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6461 12:20:53.543039 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6462 12:20:53.549495 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6463 12:20:53.552657 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6464 12:20:53.556242 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6465 12:20:53.556328 ==
6466 12:20:53.559431 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 12:20:53.566121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 12:20:53.566259 ==
6469 12:20:53.566385 DQS Delay:
6470 12:20:53.569366 DQS0 = 27, DQS1 = 43
6471 12:20:53.569500 DQM Delay:
6472 12:20:53.569618 DQM0 = 9, DQM1 = 15
6473 12:20:53.572654 DQ Delay:
6474 12:20:53.576106 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6475 12:20:53.576233 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6476 12:20:53.579265 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6477 12:20:53.582813 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6478 12:20:53.582941
6479 12:20:53.583067
6480 12:20:53.585886 ==
6481 12:20:53.586012 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 12:20:53.592667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 12:20:53.592810 ==
6484 12:20:53.592929
6485 12:20:53.593048
6486 12:20:53.596087 TX Vref Scan disable
6487 12:20:53.596221 == TX Byte 0 ==
6488 12:20:53.599623 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6489 12:20:53.602786 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6490 12:20:53.606193 == TX Byte 1 ==
6491 12:20:53.609420 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6492 12:20:53.612742 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6493 12:20:53.615913 ==
6494 12:20:53.616037 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 12:20:53.622818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 12:20:53.622966 ==
6497 12:20:53.623082
6498 12:20:53.623218
6499 12:20:53.626222 TX Vref Scan disable
6500 12:20:53.626348 == TX Byte 0 ==
6501 12:20:53.629158 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6502 12:20:53.635894 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6503 12:20:53.636022 == TX Byte 1 ==
6504 12:20:53.639367 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6505 12:20:53.642597 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6506 12:20:53.645752
6507 12:20:53.645892 [DATLAT]
6508 12:20:53.646010 Freq=400, CH0 RK1
6509 12:20:53.646133
6510 12:20:53.649398 DATLAT Default: 0xe
6511 12:20:53.649533 0, 0xFFFF, sum = 0
6512 12:20:53.652474 1, 0xFFFF, sum = 0
6513 12:20:53.652600 2, 0xFFFF, sum = 0
6514 12:20:53.656050 3, 0xFFFF, sum = 0
6515 12:20:53.656202 4, 0xFFFF, sum = 0
6516 12:20:53.659275 5, 0xFFFF, sum = 0
6517 12:20:53.659401 6, 0xFFFF, sum = 0
6518 12:20:53.662734 7, 0xFFFF, sum = 0
6519 12:20:53.665813 8, 0xFFFF, sum = 0
6520 12:20:53.665936 9, 0xFFFF, sum = 0
6521 12:20:53.669275 10, 0xFFFF, sum = 0
6522 12:20:53.669401 11, 0xFFFF, sum = 0
6523 12:20:53.672369 12, 0xFFFF, sum = 0
6524 12:20:53.672491 13, 0x0, sum = 1
6525 12:20:53.675982 14, 0x0, sum = 2
6526 12:20:53.676106 15, 0x0, sum = 3
6527 12:20:53.679355 16, 0x0, sum = 4
6528 12:20:53.679462 best_step = 14
6529 12:20:53.679564
6530 12:20:53.679654 ==
6531 12:20:53.682563 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 12:20:53.685844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 12:20:53.685957 ==
6534 12:20:53.688988 RX Vref Scan: 0
6535 12:20:53.689072
6536 12:20:53.692501 RX Vref 0 -> 0, step: 1
6537 12:20:53.692590
6538 12:20:53.692657 RX Delay -327 -> 252, step: 8
6539 12:20:53.700996 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6540 12:20:53.704611 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6541 12:20:53.707849 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6542 12:20:53.711075 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6543 12:20:53.717927 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6544 12:20:53.721307 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6545 12:20:53.724206 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6546 12:20:53.727766 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6547 12:20:53.734219 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6548 12:20:53.737859 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6549 12:20:53.740921 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6550 12:20:53.744549 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6551 12:20:53.750755 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6552 12:20:53.754342 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6553 12:20:53.757667 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6554 12:20:53.764190 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6555 12:20:53.764272 ==
6556 12:20:53.767683 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 12:20:53.770714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 12:20:53.770796 ==
6559 12:20:53.770861 DQS Delay:
6560 12:20:53.773970 DQS0 = 28, DQS1 = 44
6561 12:20:53.774052 DQM Delay:
6562 12:20:53.777570 DQM0 = 9, DQM1 = 14
6563 12:20:53.777672 DQ Delay:
6564 12:20:53.780567 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6565 12:20:53.784092 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6566 12:20:53.787342 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6567 12:20:53.790441 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6568 12:20:53.790523
6569 12:20:53.790589
6570 12:20:53.797245 [DQSOSCAuto] RK1, (LSB)MR18= 0xb76b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6571 12:20:53.800809 CH0 RK1: MR19=C0C, MR18=B76B
6572 12:20:53.807478 CH0_RK1: MR19=0xC0C, MR18=0xB76B, DQSOSC=387, MR23=63, INC=394, DEC=262
6573 12:20:53.810437 [RxdqsGatingPostProcess] freq 400
6574 12:20:53.817612 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6575 12:20:53.817696 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 12:20:53.820614 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 12:20:53.824124 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 12:20:53.827381 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 12:20:53.830525 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 12:20:53.833973 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 12:20:53.837035 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 12:20:53.840396 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 12:20:53.843981 Pre-setting of DQS Precalculation
6584 12:20:53.850375 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6585 12:20:53.850499 ==
6586 12:20:53.853882 Dram Type= 6, Freq= 0, CH_1, rank 0
6587 12:20:53.857024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 12:20:53.857146 ==
6589 12:20:53.863663 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6590 12:20:53.866838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6591 12:20:53.870492 [CA 0] Center 36 (8~64) winsize 57
6592 12:20:53.873965 [CA 1] Center 36 (8~64) winsize 57
6593 12:20:53.877062 [CA 2] Center 36 (8~64) winsize 57
6594 12:20:53.880158 [CA 3] Center 36 (8~64) winsize 57
6595 12:20:53.883659 [CA 4] Center 36 (8~64) winsize 57
6596 12:20:53.886842 [CA 5] Center 36 (8~64) winsize 57
6597 12:20:53.886964
6598 12:20:53.890506 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6599 12:20:53.890628
6600 12:20:53.893599 [CATrainingPosCal] consider 1 rank data
6601 12:20:53.896817 u2DelayCellTimex100 = 270/100 ps
6602 12:20:53.900450 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 12:20:53.903636 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 12:20:53.906834 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 12:20:53.910418 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 12:20:53.917076 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 12:20:53.920287 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 12:20:53.920411
6609 12:20:53.923534 CA PerBit enable=1, Macro0, CA PI delay=36
6610 12:20:53.923653
6611 12:20:53.926701 [CBTSetCACLKResult] CA Dly = 36
6612 12:20:53.926820 CS Dly: 1 (0~32)
6613 12:20:53.926933 ==
6614 12:20:53.930118 Dram Type= 6, Freq= 0, CH_1, rank 1
6615 12:20:53.936891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 12:20:53.937013 ==
6617 12:20:53.940394 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 12:20:53.946699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6619 12:20:53.950077 [CA 0] Center 36 (8~64) winsize 57
6620 12:20:53.953557 [CA 1] Center 36 (8~64) winsize 57
6621 12:20:53.956704 [CA 2] Center 36 (8~64) winsize 57
6622 12:20:53.959983 [CA 3] Center 36 (8~64) winsize 57
6623 12:20:53.963401 [CA 4] Center 36 (8~64) winsize 57
6624 12:20:53.966618 [CA 5] Center 36 (8~64) winsize 57
6625 12:20:53.966738
6626 12:20:53.969826 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6627 12:20:53.969946
6628 12:20:53.973433 [CATrainingPosCal] consider 2 rank data
6629 12:20:53.976901 u2DelayCellTimex100 = 270/100 ps
6630 12:20:53.979848 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:20:53.983573 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:20:53.986665 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:20:53.990244 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:20:53.993519 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:20:53.996621 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:20:53.996759
6637 12:20:54.000376 CA PerBit enable=1, Macro0, CA PI delay=36
6638 12:20:54.003455
6639 12:20:54.003553 [CBTSetCACLKResult] CA Dly = 36
6640 12:20:54.007028 CS Dly: 1 (0~32)
6641 12:20:54.007109
6642 12:20:54.010203 ----->DramcWriteLeveling(PI) begin...
6643 12:20:54.010287 ==
6644 12:20:54.013674 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 12:20:54.016727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 12:20:54.016839 ==
6647 12:20:54.020343 Write leveling (Byte 0): 40 => 8
6648 12:20:54.023800 Write leveling (Byte 1): 32 => 0
6649 12:20:54.026944 DramcWriteLeveling(PI) end<-----
6650 12:20:54.027026
6651 12:20:54.027091 ==
6652 12:20:54.030071 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 12:20:54.033267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 12:20:54.033349 ==
6655 12:20:54.036897 [Gating] SW mode calibration
6656 12:20:54.043346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6657 12:20:54.049941 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6658 12:20:54.053578 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 12:20:54.059808 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 12:20:54.063490 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 12:20:54.066469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 12:20:54.073280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 12:20:54.076420 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 12:20:54.079753 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 12:20:54.086488 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 12:20:54.089978 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 12:20:54.093131 Total UI for P1: 0, mck2ui 16
6668 12:20:54.096402 best dqsien dly found for B0: ( 0, 14, 24)
6669 12:20:54.100117 Total UI for P1: 0, mck2ui 16
6670 12:20:54.103034 best dqsien dly found for B1: ( 0, 14, 24)
6671 12:20:54.106541 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6672 12:20:54.109734 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6673 12:20:54.109815
6674 12:20:54.113222 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 12:20:54.116434 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 12:20:54.119909 [Gating] SW calibration Done
6677 12:20:54.119991 ==
6678 12:20:54.123031 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 12:20:54.126662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 12:20:54.126744 ==
6681 12:20:54.130018 RX Vref Scan: 0
6682 12:20:54.130100
6683 12:20:54.133089 RX Vref 0 -> 0, step: 1
6684 12:20:54.133170
6685 12:20:54.133235 RX Delay -410 -> 252, step: 16
6686 12:20:54.139850 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6687 12:20:54.143203 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6688 12:20:54.146313 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6689 12:20:54.150044 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6690 12:20:54.156360 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6691 12:20:54.159526 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6692 12:20:54.163172 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6693 12:20:54.166325 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6694 12:20:54.172978 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6695 12:20:54.176251 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6696 12:20:54.179416 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6697 12:20:54.182786 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6698 12:20:54.189551 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6699 12:20:54.192749 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6700 12:20:54.196445 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6701 12:20:54.203162 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6702 12:20:54.203272 ==
6703 12:20:54.206351 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 12:20:54.209591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 12:20:54.209717 ==
6706 12:20:54.209860 DQS Delay:
6707 12:20:54.212851 DQS0 = 27, DQS1 = 43
6708 12:20:54.212982 DQM Delay:
6709 12:20:54.216077 DQM0 = 6, DQM1 = 16
6710 12:20:54.216201 DQ Delay:
6711 12:20:54.219466 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6712 12:20:54.223178 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6713 12:20:54.226519 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6714 12:20:54.229890 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6715 12:20:54.229973
6716 12:20:54.230038
6717 12:20:54.230097 ==
6718 12:20:54.232767 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 12:20:54.236430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 12:20:54.236539 ==
6721 12:20:54.236633
6722 12:20:54.236722
6723 12:20:54.239613 TX Vref Scan disable
6724 12:20:54.239695 == TX Byte 0 ==
6725 12:20:54.246322 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 12:20:54.249518 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 12:20:54.249646 == TX Byte 1 ==
6728 12:20:54.256142 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6729 12:20:54.259329 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6730 12:20:54.259449 ==
6731 12:20:54.262846 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 12:20:54.266066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 12:20:54.266191 ==
6734 12:20:54.266304
6735 12:20:54.266415
6736 12:20:54.269646 TX Vref Scan disable
6737 12:20:54.269765 == TX Byte 0 ==
6738 12:20:54.276058 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 12:20:54.279416 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 12:20:54.279538 == TX Byte 1 ==
6741 12:20:54.285774 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6742 12:20:54.289448 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6743 12:20:54.289531
6744 12:20:54.289613 [DATLAT]
6745 12:20:54.292424 Freq=400, CH1 RK0
6746 12:20:54.292507
6747 12:20:54.292573 DATLAT Default: 0xf
6748 12:20:54.296085 0, 0xFFFF, sum = 0
6749 12:20:54.296170 1, 0xFFFF, sum = 0
6750 12:20:54.299302 2, 0xFFFF, sum = 0
6751 12:20:54.299387 3, 0xFFFF, sum = 0
6752 12:20:54.302851 4, 0xFFFF, sum = 0
6753 12:20:54.302937 5, 0xFFFF, sum = 0
6754 12:20:54.306018 6, 0xFFFF, sum = 0
6755 12:20:54.309551 7, 0xFFFF, sum = 0
6756 12:20:54.309635 8, 0xFFFF, sum = 0
6757 12:20:54.312577 9, 0xFFFF, sum = 0
6758 12:20:54.312679 10, 0xFFFF, sum = 0
6759 12:20:54.316048 11, 0xFFFF, sum = 0
6760 12:20:54.316123 12, 0xFFFF, sum = 0
6761 12:20:54.319446 13, 0x0, sum = 1
6762 12:20:54.319547 14, 0x0, sum = 2
6763 12:20:54.322636 15, 0x0, sum = 3
6764 12:20:54.322736 16, 0x0, sum = 4
6765 12:20:54.322829 best_step = 14
6766 12:20:54.322920
6767 12:20:54.326326 ==
6768 12:20:54.329327 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 12:20:54.332697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 12:20:54.332837 ==
6771 12:20:54.332929 RX Vref Scan: 1
6772 12:20:54.333017
6773 12:20:54.336138 RX Vref 0 -> 0, step: 1
6774 12:20:54.336220
6775 12:20:54.339060 RX Delay -327 -> 252, step: 8
6776 12:20:54.339168
6777 12:20:54.342753 Set Vref, RX VrefLevel [Byte0]: 51
6778 12:20:54.345776 [Byte1]: 57
6779 12:20:54.349384
6780 12:20:54.349469 Final RX Vref Byte 0 = 51 to rank0
6781 12:20:54.352961 Final RX Vref Byte 1 = 57 to rank0
6782 12:20:54.356154 Final RX Vref Byte 0 = 51 to rank1
6783 12:20:54.359474 Final RX Vref Byte 1 = 57 to rank1==
6784 12:20:54.362676 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 12:20:54.369530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 12:20:54.369639 ==
6787 12:20:54.369733 DQS Delay:
6788 12:20:54.372606 DQS0 = 32, DQS1 = 44
6789 12:20:54.372730 DQM Delay:
6790 12:20:54.372848 DQM0 = 12, DQM1 = 15
6791 12:20:54.375990 DQ Delay:
6792 12:20:54.379511 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6793 12:20:54.379619 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6794 12:20:54.382677 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6795 12:20:54.386129 DQ12 =28, DQ13 =24, DQ14 =20, DQ15 =20
6796 12:20:54.386259
6797 12:20:54.389816
6798 12:20:54.396403 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6799 12:20:54.399574 CH1 RK0: MR19=C0C, MR18=99D3
6800 12:20:54.406289 CH1_RK0: MR19=0xC0C, MR18=0x99D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6801 12:20:54.406373 ==
6802 12:20:54.409506 Dram Type= 6, Freq= 0, CH_1, rank 1
6803 12:20:54.412977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 12:20:54.413105 ==
6805 12:20:54.416087 [Gating] SW mode calibration
6806 12:20:54.422613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6807 12:20:54.429494 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6808 12:20:54.432622 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 12:20:54.435826 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 12:20:54.439361 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 12:20:54.445695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 12:20:54.449282 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 12:20:54.452403 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 12:20:54.459154 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 12:20:54.462525 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 12:20:54.465981 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 12:20:54.469379 Total UI for P1: 0, mck2ui 16
6818 12:20:54.472593 best dqsien dly found for B0: ( 0, 14, 24)
6819 12:20:54.475603 Total UI for P1: 0, mck2ui 16
6820 12:20:54.479206 best dqsien dly found for B1: ( 0, 14, 24)
6821 12:20:54.482421 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6822 12:20:54.485853 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6823 12:20:54.489021
6824 12:20:54.492594 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 12:20:54.495779 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 12:20:54.499446 [Gating] SW calibration Done
6827 12:20:54.499529 ==
6828 12:20:54.502545 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 12:20:54.505723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 12:20:54.505805 ==
6831 12:20:54.505871 RX Vref Scan: 0
6832 12:20:54.505930
6833 12:20:54.509404 RX Vref 0 -> 0, step: 1
6834 12:20:54.509486
6835 12:20:54.512663 RX Delay -410 -> 252, step: 16
6836 12:20:54.515798 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6837 12:20:54.522439 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6838 12:20:54.525953 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6839 12:20:54.529057 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6840 12:20:54.532643 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6841 12:20:54.539092 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6842 12:20:54.542206 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6843 12:20:54.545817 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6844 12:20:54.548935 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6845 12:20:54.555684 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6846 12:20:54.558784 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6847 12:20:54.561993 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6848 12:20:54.565523 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6849 12:20:54.572396 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6850 12:20:54.575142 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6851 12:20:54.579101 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6852 12:20:54.579216 ==
6853 12:20:54.581940 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 12:20:54.588698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 12:20:54.588831 ==
6856 12:20:54.588913 DQS Delay:
6857 12:20:54.591957 DQS0 = 35, DQS1 = 43
6858 12:20:54.592039 DQM Delay:
6859 12:20:54.592105 DQM0 = 16, DQM1 = 18
6860 12:20:54.595267 DQ Delay:
6861 12:20:54.598515 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6862 12:20:54.601945 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6863 12:20:54.602028 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6864 12:20:54.608644 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6865 12:20:54.608726
6866 12:20:54.608829
6867 12:20:54.608891 ==
6868 12:20:54.611649 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 12:20:54.615343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 12:20:54.615426 ==
6871 12:20:54.615491
6872 12:20:54.615550
6873 12:20:54.618604 TX Vref Scan disable
6874 12:20:54.618686 == TX Byte 0 ==
6875 12:20:54.621717 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6876 12:20:54.628515 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6877 12:20:54.628598 == TX Byte 1 ==
6878 12:20:54.631733 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6879 12:20:54.638098 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6880 12:20:54.638189 ==
6881 12:20:54.641481 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 12:20:54.644927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 12:20:54.645009 ==
6884 12:20:54.645074
6885 12:20:54.645133
6886 12:20:54.648146 TX Vref Scan disable
6887 12:20:54.648227 == TX Byte 0 ==
6888 12:20:54.654808 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6889 12:20:54.658384 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6890 12:20:54.658466 == TX Byte 1 ==
6891 12:20:54.664700 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6892 12:20:54.667818 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6893 12:20:54.667900
6894 12:20:54.667964 [DATLAT]
6895 12:20:54.671479 Freq=400, CH1 RK1
6896 12:20:54.671562
6897 12:20:54.671627 DATLAT Default: 0xe
6898 12:20:54.674513 0, 0xFFFF, sum = 0
6899 12:20:54.674596 1, 0xFFFF, sum = 0
6900 12:20:54.677857 2, 0xFFFF, sum = 0
6901 12:20:54.677940 3, 0xFFFF, sum = 0
6902 12:20:54.681425 4, 0xFFFF, sum = 0
6903 12:20:54.681508 5, 0xFFFF, sum = 0
6904 12:20:54.684435 6, 0xFFFF, sum = 0
6905 12:20:54.684518 7, 0xFFFF, sum = 0
6906 12:20:54.688046 8, 0xFFFF, sum = 0
6907 12:20:54.688130 9, 0xFFFF, sum = 0
6908 12:20:54.691539 10, 0xFFFF, sum = 0
6909 12:20:54.691623 11, 0xFFFF, sum = 0
6910 12:20:54.694425 12, 0xFFFF, sum = 0
6911 12:20:54.694508 13, 0x0, sum = 1
6912 12:20:54.697840 14, 0x0, sum = 2
6913 12:20:54.697943 15, 0x0, sum = 3
6914 12:20:54.701192 16, 0x0, sum = 4
6915 12:20:54.701276 best_step = 14
6916 12:20:54.701341
6917 12:20:54.701400 ==
6918 12:20:54.704614 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 12:20:54.711434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 12:20:54.711517 ==
6921 12:20:54.711583 RX Vref Scan: 0
6922 12:20:54.711644
6923 12:20:54.714590 RX Vref 0 -> 0, step: 1
6924 12:20:54.714672
6925 12:20:54.717721 RX Delay -327 -> 252, step: 8
6926 12:20:54.724665 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6927 12:20:54.728036 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6928 12:20:54.731154 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6929 12:20:54.734504 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6930 12:20:54.741179 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6931 12:20:54.744589 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6932 12:20:54.748010 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6933 12:20:54.751502 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6934 12:20:54.757926 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6935 12:20:54.761086 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6936 12:20:54.764412 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6937 12:20:54.767835 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6938 12:20:54.774553 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
6939 12:20:54.777702 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6940 12:20:54.780886 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6941 12:20:54.784544 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6942 12:20:54.787723 ==
6943 12:20:54.787832 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 12:20:54.794395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 12:20:54.794482 ==
6946 12:20:54.794548 DQS Delay:
6947 12:20:54.798204 DQS0 = 28, DQS1 = 40
6948 12:20:54.798290 DQM Delay:
6949 12:20:54.800810 DQM0 = 9, DQM1 = 15
6950 12:20:54.800901 DQ Delay:
6951 12:20:54.804104 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6952 12:20:54.807703 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =4
6953 12:20:54.810880 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6954 12:20:54.814219 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6955 12:20:54.814302
6956 12:20:54.814367
6957 12:20:54.820711 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf57, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6958 12:20:54.824366 CH1 RK1: MR19=C0C, MR18=AF57
6959 12:20:54.830636 CH1_RK1: MR19=0xC0C, MR18=0xAF57, DQSOSC=388, MR23=63, INC=392, DEC=261
6960 12:20:54.834292 [RxdqsGatingPostProcess] freq 400
6961 12:20:54.837198 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6962 12:20:54.840734 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 12:20:54.843873 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 12:20:54.847559 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 12:20:54.850864 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 12:20:54.853992 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 12:20:54.857460 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 12:20:54.860467 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 12:20:54.863705 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 12:20:54.867352 Pre-setting of DQS Precalculation
6971 12:20:54.870573 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6972 12:20:54.880606 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6973 12:20:54.887103 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6974 12:20:54.887187
6975 12:20:54.887253
6976 12:20:54.890742 [Calibration Summary] 800 Mbps
6977 12:20:54.890826 CH 0, Rank 0
6978 12:20:54.893809 SW Impedance : PASS
6979 12:20:54.893893 DUTY Scan : NO K
6980 12:20:54.897099 ZQ Calibration : PASS
6981 12:20:54.900615 Jitter Meter : NO K
6982 12:20:54.900698 CBT Training : PASS
6983 12:20:54.903876 Write leveling : PASS
6984 12:20:54.907188 RX DQS gating : PASS
6985 12:20:54.907271 RX DQ/DQS(RDDQC) : PASS
6986 12:20:54.910349 TX DQ/DQS : PASS
6987 12:20:54.913732 RX DATLAT : PASS
6988 12:20:54.913846 RX DQ/DQS(Engine): PASS
6989 12:20:54.917178 TX OE : NO K
6990 12:20:54.917263 All Pass.
6991 12:20:54.917332
6992 12:20:54.917396 CH 0, Rank 1
6993 12:20:54.920492 SW Impedance : PASS
6994 12:20:54.923894 DUTY Scan : NO K
6995 12:20:54.924024 ZQ Calibration : PASS
6996 12:20:54.927109 Jitter Meter : NO K
6997 12:20:54.930668 CBT Training : PASS
6998 12:20:54.930783 Write leveling : NO K
6999 12:20:54.933768 RX DQS gating : PASS
7000 12:20:54.937082 RX DQ/DQS(RDDQC) : PASS
7001 12:20:54.937204 TX DQ/DQS : PASS
7002 12:20:54.940316 RX DATLAT : PASS
7003 12:20:54.943811 RX DQ/DQS(Engine): PASS
7004 12:20:54.943932 TX OE : NO K
7005 12:20:54.946930 All Pass.
7006 12:20:54.947049
7007 12:20:54.947162 CH 1, Rank 0
7008 12:20:54.950524 SW Impedance : PASS
7009 12:20:54.950638 DUTY Scan : NO K
7010 12:20:54.953795 ZQ Calibration : PASS
7011 12:20:54.956787 Jitter Meter : NO K
7012 12:20:54.956907 CBT Training : PASS
7013 12:20:54.960540 Write leveling : PASS
7014 12:20:54.960657 RX DQS gating : PASS
7015 12:20:54.963656 RX DQ/DQS(RDDQC) : PASS
7016 12:20:54.966794 TX DQ/DQS : PASS
7017 12:20:54.966916 RX DATLAT : PASS
7018 12:20:54.970317 RX DQ/DQS(Engine): PASS
7019 12:20:54.973962 TX OE : NO K
7020 12:20:54.974083 All Pass.
7021 12:20:54.974196
7022 12:20:54.974304 CH 1, Rank 1
7023 12:20:54.977159 SW Impedance : PASS
7024 12:20:54.980206 DUTY Scan : NO K
7025 12:20:54.980324 ZQ Calibration : PASS
7026 12:20:54.983458 Jitter Meter : NO K
7027 12:20:54.986918 CBT Training : PASS
7028 12:20:54.987038 Write leveling : NO K
7029 12:20:54.990563 RX DQS gating : PASS
7030 12:20:54.993500 RX DQ/DQS(RDDQC) : PASS
7031 12:20:54.993622 TX DQ/DQS : PASS
7032 12:20:54.996864 RX DATLAT : PASS
7033 12:20:55.000332 RX DQ/DQS(Engine): PASS
7034 12:20:55.000452 TX OE : NO K
7035 12:20:55.000565 All Pass.
7036 12:20:55.003693
7037 12:20:55.003812 DramC Write-DBI off
7038 12:20:55.007120 PER_BANK_REFRESH: Hybrid Mode
7039 12:20:55.007239 TX_TRACKING: ON
7040 12:20:55.017095 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7041 12:20:55.020441 [FAST_K] Save calibration result to emmc
7042 12:20:55.023481 dramc_set_vcore_voltage set vcore to 725000
7043 12:20:55.027070 Read voltage for 1600, 0
7044 12:20:55.027192 Vio18 = 0
7045 12:20:55.030233 Vcore = 725000
7046 12:20:55.030357 Vdram = 0
7047 12:20:55.030466 Vddq = 0
7048 12:20:55.030577 Vmddr = 0
7049 12:20:55.037161 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7050 12:20:55.043401 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7051 12:20:55.043523 MEM_TYPE=3, freq_sel=13
7052 12:20:55.046818 sv_algorithm_assistance_LP4_3733
7053 12:20:55.049962 ============ PULL DRAM RESETB DOWN ============
7054 12:20:55.056986 ========== PULL DRAM RESETB DOWN end =========
7055 12:20:55.060047 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7056 12:20:55.063532 ===================================
7057 12:20:55.066732 LPDDR4 DRAM CONFIGURATION
7058 12:20:55.070234 ===================================
7059 12:20:55.070357 EX_ROW_EN[0] = 0x0
7060 12:20:55.073415 EX_ROW_EN[1] = 0x0
7061 12:20:55.073532 LP4Y_EN = 0x0
7062 12:20:55.076963 WORK_FSP = 0x1
7063 12:20:55.077084 WL = 0x5
7064 12:20:55.080034 RL = 0x5
7065 12:20:55.083741 BL = 0x2
7066 12:20:55.083862 RPST = 0x0
7067 12:20:55.086793 RD_PRE = 0x0
7068 12:20:55.086913 WR_PRE = 0x1
7069 12:20:55.089930 WR_PST = 0x1
7070 12:20:55.090050 DBI_WR = 0x0
7071 12:20:55.093298 DBI_RD = 0x0
7072 12:20:55.093417 OTF = 0x1
7073 12:20:55.096833 ===================================
7074 12:20:55.100093 ===================================
7075 12:20:55.103669 ANA top config
7076 12:20:55.103755 ===================================
7077 12:20:55.106841 DLL_ASYNC_EN = 0
7078 12:20:55.109929 ALL_SLAVE_EN = 0
7079 12:20:55.113226 NEW_RANK_MODE = 1
7080 12:20:55.116653 DLL_IDLE_MODE = 1
7081 12:20:55.116786 LP45_APHY_COMB_EN = 1
7082 12:20:55.119799 TX_ODT_DIS = 0
7083 12:20:55.123393 NEW_8X_MODE = 1
7084 12:20:55.126634 ===================================
7085 12:20:55.130044 ===================================
7086 12:20:55.133459 data_rate = 3200
7087 12:20:55.136940 CKR = 1
7088 12:20:55.137051 DQ_P2S_RATIO = 8
7089 12:20:55.139805 ===================================
7090 12:20:55.143345 CA_P2S_RATIO = 8
7091 12:20:55.146561 DQ_CA_OPEN = 0
7092 12:20:55.150111 DQ_SEMI_OPEN = 0
7093 12:20:55.153262 CA_SEMI_OPEN = 0
7094 12:20:55.156971 CA_FULL_RATE = 0
7095 12:20:55.157056 DQ_CKDIV4_EN = 0
7096 12:20:55.160020 CA_CKDIV4_EN = 0
7097 12:20:55.163423 CA_PREDIV_EN = 0
7098 12:20:55.166643 PH8_DLY = 12
7099 12:20:55.170330 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7100 12:20:55.173382 DQ_AAMCK_DIV = 4
7101 12:20:55.173468 CA_AAMCK_DIV = 4
7102 12:20:55.176976 CA_ADMCK_DIV = 4
7103 12:20:55.179944 DQ_TRACK_CA_EN = 0
7104 12:20:55.183219 CA_PICK = 1600
7105 12:20:55.186808 CA_MCKIO = 1600
7106 12:20:55.190000 MCKIO_SEMI = 0
7107 12:20:55.193167 PLL_FREQ = 3068
7108 12:20:55.193253 DQ_UI_PI_RATIO = 32
7109 12:20:55.196512 CA_UI_PI_RATIO = 0
7110 12:20:55.200087 ===================================
7111 12:20:55.203383 ===================================
7112 12:20:55.206504 memory_type:LPDDR4
7113 12:20:55.210067 GP_NUM : 10
7114 12:20:55.210153 SRAM_EN : 1
7115 12:20:55.213116 MD32_EN : 0
7116 12:20:55.216355 ===================================
7117 12:20:55.219924 [ANA_INIT] >>>>>>>>>>>>>>
7118 12:20:55.220010 <<<<<< [CONFIGURE PHASE]: ANA_TX
7119 12:20:55.223117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7120 12:20:55.226358 ===================================
7121 12:20:55.229804 data_rate = 3200,PCW = 0X7600
7122 12:20:55.233053 ===================================
7123 12:20:55.236430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7124 12:20:55.242887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 12:20:55.249862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 12:20:55.252954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7127 12:20:55.256117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7128 12:20:55.259645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7129 12:20:55.262704 [ANA_INIT] flow start
7130 12:20:55.262789 [ANA_INIT] PLL >>>>>>>>
7131 12:20:55.266248 [ANA_INIT] PLL <<<<<<<<
7132 12:20:55.269723 [ANA_INIT] MIDPI >>>>>>>>
7133 12:20:55.272857 [ANA_INIT] MIDPI <<<<<<<<
7134 12:20:55.272943 [ANA_INIT] DLL >>>>>>>>
7135 12:20:55.275949 [ANA_INIT] DLL <<<<<<<<
7136 12:20:55.276034 [ANA_INIT] flow end
7137 12:20:55.282561 ============ LP4 DIFF to SE enter ============
7138 12:20:55.286171 ============ LP4 DIFF to SE exit ============
7139 12:20:55.289367 [ANA_INIT] <<<<<<<<<<<<<
7140 12:20:55.292593 [Flow] Enable top DCM control >>>>>
7141 12:20:55.295824 [Flow] Enable top DCM control <<<<<
7142 12:20:55.299304 Enable DLL master slave shuffle
7143 12:20:55.302663 ==============================================================
7144 12:20:55.305912 Gating Mode config
7145 12:20:55.309608 ==============================================================
7146 12:20:55.312702 Config description:
7147 12:20:55.322264 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7148 12:20:55.328998 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7149 12:20:55.332479 SELPH_MODE 0: By rank 1: By Phase
7150 12:20:55.338870 ==============================================================
7151 12:20:55.342837 GAT_TRACK_EN = 1
7152 12:20:55.345930 RX_GATING_MODE = 2
7153 12:20:55.348905 RX_GATING_TRACK_MODE = 2
7154 12:20:55.352343 SELPH_MODE = 1
7155 12:20:55.355543 PICG_EARLY_EN = 1
7156 12:20:55.355627 VALID_LAT_VALUE = 1
7157 12:20:55.362085 ==============================================================
7158 12:20:55.365748 Enter into Gating configuration >>>>
7159 12:20:55.368766 Exit from Gating configuration <<<<
7160 12:20:55.372170 Enter into DVFS_PRE_config >>>>>
7161 12:20:55.382339 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7162 12:20:55.385562 Exit from DVFS_PRE_config <<<<<
7163 12:20:55.388621 Enter into PICG configuration >>>>
7164 12:20:55.391819 Exit from PICG configuration <<<<
7165 12:20:55.395368 [RX_INPUT] configuration >>>>>
7166 12:20:55.398576 [RX_INPUT] configuration <<<<<
7167 12:20:55.405163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7168 12:20:55.408352 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7169 12:20:55.415449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7170 12:20:55.421611 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7171 12:20:55.428438 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 12:20:55.435077 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 12:20:55.438482 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7174 12:20:55.441765 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7175 12:20:55.444865 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7176 12:20:55.451343 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7177 12:20:55.454911 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7178 12:20:55.458349 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 12:20:55.461844 ===================================
7180 12:20:55.464944 LPDDR4 DRAM CONFIGURATION
7181 12:20:55.468049 ===================================
7182 12:20:55.468132 EX_ROW_EN[0] = 0x0
7183 12:20:55.471693 EX_ROW_EN[1] = 0x0
7184 12:20:55.475012 LP4Y_EN = 0x0
7185 12:20:55.475095 WORK_FSP = 0x1
7186 12:20:55.478402 WL = 0x5
7187 12:20:55.478486 RL = 0x5
7188 12:20:55.481569 BL = 0x2
7189 12:20:55.481652 RPST = 0x0
7190 12:20:55.485215 RD_PRE = 0x0
7191 12:20:55.485299 WR_PRE = 0x1
7192 12:20:55.488367 WR_PST = 0x1
7193 12:20:55.488451 DBI_WR = 0x0
7194 12:20:55.491463 DBI_RD = 0x0
7195 12:20:55.491547 OTF = 0x1
7196 12:20:55.494614 ===================================
7197 12:20:55.498175 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7198 12:20:55.504894 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7199 12:20:55.508003 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 12:20:55.511395 ===================================
7201 12:20:55.514527 LPDDR4 DRAM CONFIGURATION
7202 12:20:55.518145 ===================================
7203 12:20:55.518256 EX_ROW_EN[0] = 0x10
7204 12:20:55.521182 EX_ROW_EN[1] = 0x0
7205 12:20:55.521256 LP4Y_EN = 0x0
7206 12:20:55.524872 WORK_FSP = 0x1
7207 12:20:55.524971 WL = 0x5
7208 12:20:55.528016 RL = 0x5
7209 12:20:55.528089 BL = 0x2
7210 12:20:55.531451 RPST = 0x0
7211 12:20:55.534762 RD_PRE = 0x0
7212 12:20:55.534861 WR_PRE = 0x1
7213 12:20:55.538210 WR_PST = 0x1
7214 12:20:55.538309 DBI_WR = 0x0
7215 12:20:55.541180 DBI_RD = 0x0
7216 12:20:55.541252 OTF = 0x1
7217 12:20:55.544502 ===================================
7218 12:20:55.551592 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7219 12:20:55.551667 ==
7220 12:20:55.554669 Dram Type= 6, Freq= 0, CH_0, rank 0
7221 12:20:55.557833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7222 12:20:55.557906 ==
7223 12:20:55.561158 [Duty_Offset_Calibration]
7224 12:20:55.561308 B0:2 B1:0 CA:1
7225 12:20:55.564589
7226 12:20:55.567729 [DutyScan_Calibration_Flow] k_type=0
7227 12:20:55.575214
7228 12:20:55.575311 ==CLK 0==
7229 12:20:55.578503 Final CLK duty delay cell = -4
7230 12:20:55.581923 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7231 12:20:55.585033 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7232 12:20:55.589033 [-4] AVG Duty = 4937%(X100)
7233 12:20:55.589134
7234 12:20:55.591938 CH0 CLK Duty spec in!! Max-Min= 187%
7235 12:20:55.595103 [DutyScan_Calibration_Flow] ====Done====
7236 12:20:55.595205
7237 12:20:55.598684 [DutyScan_Calibration_Flow] k_type=1
7238 12:20:55.615011
7239 12:20:55.615117 ==DQS 0 ==
7240 12:20:55.618041 Final DQS duty delay cell = 0
7241 12:20:55.621209 [0] MAX Duty = 5249%(X100), DQS PI = 32
7242 12:20:55.624722 [0] MIN Duty = 4969%(X100), DQS PI = 2
7243 12:20:55.624848 [0] AVG Duty = 5109%(X100)
7244 12:20:55.627870
7245 12:20:55.627975 ==DQS 1 ==
7246 12:20:55.631550 Final DQS duty delay cell = -4
7247 12:20:55.634619 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7248 12:20:55.637907 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7249 12:20:55.641126 [-4] AVG Duty = 5000%(X100)
7250 12:20:55.641235
7251 12:20:55.644641 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7252 12:20:55.644778
7253 12:20:55.647977 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7254 12:20:55.651474 [DutyScan_Calibration_Flow] ====Done====
7255 12:20:55.651582
7256 12:20:55.654725 [DutyScan_Calibration_Flow] k_type=3
7257 12:20:55.671419
7258 12:20:55.671539 ==DQM 0 ==
7259 12:20:55.674803 Final DQM duty delay cell = 0
7260 12:20:55.678089 [0] MAX Duty = 5093%(X100), DQS PI = 24
7261 12:20:55.681469 [0] MIN Duty = 4844%(X100), DQS PI = 2
7262 12:20:55.681553 [0] AVG Duty = 4968%(X100)
7263 12:20:55.684725
7264 12:20:55.684811 ==DQM 1 ==
7265 12:20:55.687697 Final DQM duty delay cell = -4
7266 12:20:55.691331 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7267 12:20:55.694626 [-4] MIN Duty = 4751%(X100), DQS PI = 8
7268 12:20:55.698425 [-4] AVG Duty = 4891%(X100)
7269 12:20:55.698537
7270 12:20:55.701489 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7271 12:20:55.701574
7272 12:20:55.704691 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7273 12:20:55.707824 [DutyScan_Calibration_Flow] ====Done====
7274 12:20:55.707934
7275 12:20:55.710986 [DutyScan_Calibration_Flow] k_type=2
7276 12:20:55.728649
7277 12:20:55.728770 ==DQ 0 ==
7278 12:20:55.731923 Final DQ duty delay cell = 0
7279 12:20:55.735619 [0] MAX Duty = 5124%(X100), DQS PI = 32
7280 12:20:55.738766 [0] MIN Duty = 5000%(X100), DQS PI = 16
7281 12:20:55.738855 [0] AVG Duty = 5062%(X100)
7282 12:20:55.741997
7283 12:20:55.742081 ==DQ 1 ==
7284 12:20:55.745305 Final DQ duty delay cell = 0
7285 12:20:55.748359 [0] MAX Duty = 4969%(X100), DQS PI = 50
7286 12:20:55.751723 [0] MIN Duty = 4875%(X100), DQS PI = 8
7287 12:20:55.751809 [0] AVG Duty = 4922%(X100)
7288 12:20:55.751878
7289 12:20:55.758570 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7290 12:20:55.758655
7291 12:20:55.761871 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7292 12:20:55.765170 [DutyScan_Calibration_Flow] ====Done====
7293 12:20:55.765254 ==
7294 12:20:55.768439 Dram Type= 6, Freq= 0, CH_1, rank 0
7295 12:20:55.771908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7296 12:20:55.771990 ==
7297 12:20:55.775251 [Duty_Offset_Calibration]
7298 12:20:55.775331 B0:0 B1:-1 CA:2
7299 12:20:55.775396
7300 12:20:55.778800 [DutyScan_Calibration_Flow] k_type=0
7301 12:20:55.788966
7302 12:20:55.789046 ==CLK 0==
7303 12:20:55.792285 Final CLK duty delay cell = 0
7304 12:20:55.795484 [0] MAX Duty = 5156%(X100), DQS PI = 10
7305 12:20:55.798798 [0] MIN Duty = 4906%(X100), DQS PI = 46
7306 12:20:55.798902 [0] AVG Duty = 5031%(X100)
7307 12:20:55.802135
7308 12:20:55.805335 CH1 CLK Duty spec in!! Max-Min= 250%
7309 12:20:55.808860 [DutyScan_Calibration_Flow] ====Done====
7310 12:20:55.808974
7311 12:20:55.812198 [DutyScan_Calibration_Flow] k_type=1
7312 12:20:55.828531
7313 12:20:55.828646 ==DQS 0 ==
7314 12:20:55.831711 Final DQS duty delay cell = 0
7315 12:20:55.835507 [0] MAX Duty = 5124%(X100), DQS PI = 24
7316 12:20:55.838839 [0] MIN Duty = 4969%(X100), DQS PI = 0
7317 12:20:55.841910 [0] AVG Duty = 5046%(X100)
7318 12:20:55.841996
7319 12:20:55.842063 ==DQS 1 ==
7320 12:20:55.845163 Final DQS duty delay cell = 0
7321 12:20:55.848693 [0] MAX Duty = 5187%(X100), DQS PI = 62
7322 12:20:55.852267 [0] MIN Duty = 4844%(X100), DQS PI = 32
7323 12:20:55.852352 [0] AVG Duty = 5015%(X100)
7324 12:20:55.855451
7325 12:20:55.858457 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7326 12:20:55.858539
7327 12:20:55.861940 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7328 12:20:55.865601 [DutyScan_Calibration_Flow] ====Done====
7329 12:20:55.865675
7330 12:20:55.868666 [DutyScan_Calibration_Flow] k_type=3
7331 12:20:55.886374
7332 12:20:55.886460 ==DQM 0 ==
7333 12:20:55.889786 Final DQM duty delay cell = 4
7334 12:20:55.893033 [4] MAX Duty = 5125%(X100), DQS PI = 8
7335 12:20:55.896231 [4] MIN Duty = 4969%(X100), DQS PI = 44
7336 12:20:55.899508 [4] AVG Duty = 5047%(X100)
7337 12:20:55.899592
7338 12:20:55.899658 ==DQM 1 ==
7339 12:20:55.902823 Final DQM duty delay cell = 0
7340 12:20:55.906349 [0] MAX Duty = 5281%(X100), DQS PI = 58
7341 12:20:55.909506 [0] MIN Duty = 4876%(X100), DQS PI = 34
7342 12:20:55.909591 [0] AVG Duty = 5078%(X100)
7343 12:20:55.913149
7344 12:20:55.916439 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7345 12:20:55.916550
7346 12:20:55.919527 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7347 12:20:55.923053 [DutyScan_Calibration_Flow] ====Done====
7348 12:20:55.923137
7349 12:20:55.926006 [DutyScan_Calibration_Flow] k_type=2
7350 12:20:55.943459
7351 12:20:55.943569 ==DQ 0 ==
7352 12:20:55.947072 Final DQ duty delay cell = 0
7353 12:20:55.949891 [0] MAX Duty = 5093%(X100), DQS PI = 18
7354 12:20:55.953326 [0] MIN Duty = 4969%(X100), DQS PI = 46
7355 12:20:55.956404 [0] AVG Duty = 5031%(X100)
7356 12:20:55.956504
7357 12:20:55.956596 ==DQ 1 ==
7358 12:20:55.959609 Final DQ duty delay cell = 0
7359 12:20:55.963004 [0] MAX Duty = 5062%(X100), DQS PI = 0
7360 12:20:55.966410 [0] MIN Duty = 4813%(X100), DQS PI = 34
7361 12:20:55.966498 [0] AVG Duty = 4937%(X100)
7362 12:20:55.969717
7363 12:20:55.972849 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7364 12:20:55.972933
7365 12:20:55.976118 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7366 12:20:55.979419 [DutyScan_Calibration_Flow] ====Done====
7367 12:20:55.982906 nWR fixed to 30
7368 12:20:55.983018 [ModeRegInit_LP4] CH0 RK0
7369 12:20:55.986129 [ModeRegInit_LP4] CH0 RK1
7370 12:20:55.989335 [ModeRegInit_LP4] CH1 RK0
7371 12:20:55.992589 [ModeRegInit_LP4] CH1 RK1
7372 12:20:55.992674 match AC timing 5
7373 12:20:55.999375 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7374 12:20:56.002832 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7375 12:20:56.005965 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7376 12:20:56.012609 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7377 12:20:56.016401 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7378 12:20:56.016485 [MiockJmeterHQA]
7379 12:20:56.016555
7380 12:20:56.019483 [DramcMiockJmeter] u1RxGatingPI = 0
7381 12:20:56.022755 0 : 4255, 4029
7382 12:20:56.022841 4 : 4363, 4137
7383 12:20:56.026413 8 : 4252, 4026
7384 12:20:56.026499 12 : 4252, 4027
7385 12:20:56.026567 16 : 4252, 4027
7386 12:20:56.029409 20 : 4253, 4027
7387 12:20:56.029495 24 : 4255, 4029
7388 12:20:56.032945 28 : 4252, 4027
7389 12:20:56.033030 32 : 4252, 4027
7390 12:20:56.036182 36 : 4366, 4139
7391 12:20:56.036268 40 : 4252, 4027
7392 12:20:56.036337 44 : 4255, 4029
7393 12:20:56.039273 48 : 4253, 4027
7394 12:20:56.039358 52 : 4362, 4137
7395 12:20:56.042838 56 : 4250, 4027
7396 12:20:56.042923 60 : 4361, 4137
7397 12:20:56.045830 64 : 4252, 4027
7398 12:20:56.045918 68 : 4250, 4027
7399 12:20:56.049167 72 : 4250, 4027
7400 12:20:56.049280 76 : 4253, 4029
7401 12:20:56.049379 80 : 4250, 4027
7402 12:20:56.053155 84 : 4250, 4027
7403 12:20:56.053241 88 : 4363, 3844
7404 12:20:56.055765 92 : 4250, 0
7405 12:20:56.055850 96 : 4250, 0
7406 12:20:56.055917 100 : 4360, 0
7407 12:20:56.059429 104 : 4252, 0
7408 12:20:56.059515 108 : 4249, 0
7409 12:20:56.062626 112 : 4250, 0
7410 12:20:56.062712 116 : 4253, 0
7411 12:20:56.062779 120 : 4361, 0
7412 12:20:56.065817 124 : 4250, 0
7413 12:20:56.065903 128 : 4250, 0
7414 12:20:56.069663 132 : 4250, 0
7415 12:20:56.069752 136 : 4360, 0
7416 12:20:56.069820 140 : 4361, 0
7417 12:20:56.072970 144 : 4250, 0
7418 12:20:56.073058 148 : 4250, 0
7419 12:20:56.073127 152 : 4250, 0
7420 12:20:56.075884 156 : 4250, 0
7421 12:20:56.075969 160 : 4250, 0
7422 12:20:56.079114 164 : 4250, 0
7423 12:20:56.079227 168 : 4253, 0
7424 12:20:56.079325 172 : 4361, 0
7425 12:20:56.082788 176 : 4250, 0
7426 12:20:56.082890 180 : 4250, 0
7427 12:20:56.085991 184 : 4361, 0
7428 12:20:56.086077 188 : 4360, 0
7429 12:20:56.086151 192 : 4363, 0
7430 12:20:56.089265 196 : 4250, 0
7431 12:20:56.089341 200 : 4361, 1
7432 12:20:56.092685 204 : 4250, 2093
7433 12:20:56.092814 208 : 4361, 4137
7434 12:20:56.096174 212 : 4361, 4137
7435 12:20:56.096278 216 : 4250, 4027
7436 12:20:56.096373 220 : 4363, 4140
7437 12:20:56.099146 224 : 4361, 4137
7438 12:20:56.099233 228 : 4253, 4029
7439 12:20:56.102367 232 : 4250, 4026
7440 12:20:56.102453 236 : 4253, 4029
7441 12:20:56.105703 240 : 4250, 4027
7442 12:20:56.105790 244 : 4250, 4027
7443 12:20:56.109272 248 : 4250, 4027
7444 12:20:56.109405 252 : 4250, 4026
7445 12:20:56.112304 256 : 4250, 4027
7446 12:20:56.112434 260 : 4361, 4137
7447 12:20:56.115657 264 : 4361, 4137
7448 12:20:56.115787 268 : 4250, 4026
7449 12:20:56.119273 272 : 4361, 4137
7450 12:20:56.119386 276 : 4361, 4137
7451 12:20:56.119490 280 : 4250, 4027
7452 12:20:56.122297 284 : 4250, 4026
7453 12:20:56.122415 288 : 4252, 4029
7454 12:20:56.125858 292 : 4250, 4027
7455 12:20:56.125977 296 : 4250, 4026
7456 12:20:56.128977 300 : 4250, 4026
7457 12:20:56.129068 304 : 4250, 4026
7458 12:20:56.132340 308 : 4250, 4027
7459 12:20:56.132426 312 : 4361, 4077
7460 12:20:56.136047 316 : 4360, 2068
7461 12:20:56.136136
7462 12:20:56.136202 MIOCK jitter meter ch=0
7463 12:20:56.136265
7464 12:20:56.139375 1T = (316-92) = 224 dly cells
7465 12:20:56.145792 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7466 12:20:56.145876 ==
7467 12:20:56.149054 Dram Type= 6, Freq= 0, CH_0, rank 0
7468 12:20:56.152475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7469 12:20:56.152556 ==
7470 12:20:56.158788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7471 12:20:56.162407 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7472 12:20:56.165555 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7473 12:20:56.172213 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7474 12:20:56.181797 [CA 0] Center 42 (12~72) winsize 61
7475 12:20:56.185429 [CA 1] Center 42 (12~72) winsize 61
7476 12:20:56.188684 [CA 2] Center 37 (7~67) winsize 61
7477 12:20:56.191725 [CA 3] Center 37 (7~67) winsize 61
7478 12:20:56.195132 [CA 4] Center 35 (5~66) winsize 62
7479 12:20:56.198696 [CA 5] Center 35 (5~65) winsize 61
7480 12:20:56.198782
7481 12:20:56.201746 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7482 12:20:56.201860
7483 12:20:56.205030 [CATrainingPosCal] consider 1 rank data
7484 12:20:56.208541 u2DelayCellTimex100 = 290/100 ps
7485 12:20:56.211622 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7486 12:20:56.218566 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7487 12:20:56.221817 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7488 12:20:56.225083 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7489 12:20:56.228308 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7490 12:20:56.231834 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7491 12:20:56.231920
7492 12:20:56.235086 CA PerBit enable=1, Macro0, CA PI delay=35
7493 12:20:56.235208
7494 12:20:56.238617 [CBTSetCACLKResult] CA Dly = 35
7495 12:20:56.242034 CS Dly: 9 (0~40)
7496 12:20:56.245351 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7497 12:20:56.248147 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7498 12:20:56.248272 ==
7499 12:20:56.251835 Dram Type= 6, Freq= 0, CH_0, rank 1
7500 12:20:56.255064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 12:20:56.258128 ==
7502 12:20:56.261363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 12:20:56.265057 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 12:20:56.271610 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 12:20:56.274725 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 12:20:56.285140 [CA 0] Center 43 (13~73) winsize 61
7507 12:20:56.288289 [CA 1] Center 43 (13~73) winsize 61
7508 12:20:56.292050 [CA 2] Center 37 (8~67) winsize 60
7509 12:20:56.295303 [CA 3] Center 37 (8~67) winsize 60
7510 12:20:56.298586 [CA 4] Center 36 (6~66) winsize 61
7511 12:20:56.302078 [CA 5] Center 36 (6~66) winsize 61
7512 12:20:56.302189
7513 12:20:56.305266 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 12:20:56.305376
7515 12:20:56.308821 [CATrainingPosCal] consider 2 rank data
7516 12:20:56.312099 u2DelayCellTimex100 = 290/100 ps
7517 12:20:56.315139 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7518 12:20:56.321645 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7519 12:20:56.325254 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7520 12:20:56.328600 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7521 12:20:56.332085 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7522 12:20:56.335518 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7523 12:20:56.335631
7524 12:20:56.338781 CA PerBit enable=1, Macro0, CA PI delay=35
7525 12:20:56.338890
7526 12:20:56.341994 [CBTSetCACLKResult] CA Dly = 35
7527 12:20:56.345519 CS Dly: 10 (0~43)
7528 12:20:56.348335 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 12:20:56.351610 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 12:20:56.351733
7531 12:20:56.355443 ----->DramcWriteLeveling(PI) begin...
7532 12:20:56.355567 ==
7533 12:20:56.358494 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 12:20:56.361768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 12:20:56.365272 ==
7536 12:20:56.365392 Write leveling (Byte 0): 35 => 35
7537 12:20:56.368383 Write leveling (Byte 1): 31 => 31
7538 12:20:56.371707 DramcWriteLeveling(PI) end<-----
7539 12:20:56.371830
7540 12:20:56.371940 ==
7541 12:20:56.375095 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 12:20:56.381706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 12:20:56.381833 ==
7544 12:20:56.381951 [Gating] SW mode calibration
7545 12:20:56.391647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7546 12:20:56.394925 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7547 12:20:56.398304 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 12:20:56.404768 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 12:20:56.408527 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7550 12:20:56.411676 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7551 12:20:56.418381 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7552 12:20:56.422060 1 4 20 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7553 12:20:56.424943 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 12:20:56.431613 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 12:20:56.435096 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 12:20:56.438344 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 12:20:56.444979 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
7558 12:20:56.448362 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7559 12:20:56.451959 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7560 12:20:56.458785 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7561 12:20:56.461865 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 12:20:56.465447 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 12:20:56.471789 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 12:20:56.474900 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 12:20:56.478129 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7566 12:20:56.484835 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7567 12:20:56.488232 1 6 16 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
7568 12:20:56.491395 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7569 12:20:56.498257 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 12:20:56.501810 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 12:20:56.505111 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 12:20:56.508194 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 12:20:56.514817 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7574 12:20:56.518294 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 12:20:56.524489 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7576 12:20:56.528025 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7577 12:20:56.531184 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 12:20:56.534711 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:20:56.541284 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:20:56.544584 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:20:56.547816 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:20:56.554689 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:20:56.557988 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:20:56.561193 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:20:56.567644 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 12:20:56.571173 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 12:20:56.574401 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 12:20:56.580866 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 12:20:56.584094 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 12:20:56.587697 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 12:20:56.594184 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7592 12:20:56.597677 Total UI for P1: 0, mck2ui 16
7593 12:20:56.600708 best dqsien dly found for B0: ( 1, 9, 10)
7594 12:20:56.603981 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 12:20:56.607623 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 12:20:56.610715 Total UI for P1: 0, mck2ui 16
7597 12:20:56.614488 best dqsien dly found for B1: ( 1, 9, 20)
7598 12:20:56.617693 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7599 12:20:56.620983 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7600 12:20:56.621067
7601 12:20:56.627398 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7602 12:20:56.630995 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7603 12:20:56.634110 [Gating] SW calibration Done
7604 12:20:56.634194 ==
7605 12:20:56.637443 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 12:20:56.640734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 12:20:56.640850 ==
7608 12:20:56.640946 RX Vref Scan: 0
7609 12:20:56.641037
7610 12:20:56.644403 RX Vref 0 -> 0, step: 1
7611 12:20:56.644487
7612 12:20:56.647383 RX Delay 0 -> 252, step: 8
7613 12:20:56.650778 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7614 12:20:56.653993 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7615 12:20:56.657539 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7616 12:20:56.663868 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7617 12:20:56.667500 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7618 12:20:56.670672 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7619 12:20:56.674239 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7620 12:20:56.678054 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7621 12:20:56.683911 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7622 12:20:56.687472 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7623 12:20:56.690626 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7624 12:20:56.694168 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7625 12:20:56.697556 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7626 12:20:56.704024 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7627 12:20:56.707128 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7628 12:20:56.710322 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7629 12:20:56.710433 ==
7630 12:20:56.714057 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 12:20:56.717138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 12:20:56.717248 ==
7633 12:20:56.720797 DQS Delay:
7634 12:20:56.720882 DQS0 = 0, DQS1 = 0
7635 12:20:56.723904 DQM Delay:
7636 12:20:56.723984 DQM0 = 138, DQM1 = 125
7637 12:20:56.724048 DQ Delay:
7638 12:20:56.730819 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7639 12:20:56.733791 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7640 12:20:56.737250 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
7641 12:20:56.740398 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7642 12:20:56.740485
7643 12:20:56.740590
7644 12:20:56.740691 ==
7645 12:20:56.743560 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 12:20:56.747057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 12:20:56.747144 ==
7648 12:20:56.747231
7649 12:20:56.747312
7650 12:20:56.750127 TX Vref Scan disable
7651 12:20:56.753500 == TX Byte 0 ==
7652 12:20:56.756932 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7653 12:20:56.760340 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7654 12:20:56.763688 == TX Byte 1 ==
7655 12:20:56.767025 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7656 12:20:56.770454 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7657 12:20:56.770541 ==
7658 12:20:56.773431 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 12:20:56.777097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 12:20:56.780266 ==
7661 12:20:56.792605
7662 12:20:56.796169 TX Vref early break, caculate TX vref
7663 12:20:56.799606 TX Vref=16, minBit 0, minWin=23, winSum=375
7664 12:20:56.802522 TX Vref=18, minBit 1, minWin=23, winSum=386
7665 12:20:56.805682 TX Vref=20, minBit 4, minWin=24, winSum=397
7666 12:20:56.809413 TX Vref=22, minBit 12, minWin=24, winSum=404
7667 12:20:56.812701 TX Vref=24, minBit 6, minWin=25, winSum=415
7668 12:20:56.819236 TX Vref=26, minBit 4, minWin=25, winSum=424
7669 12:20:56.822274 TX Vref=28, minBit 7, minWin=25, winSum=426
7670 12:20:56.826000 TX Vref=30, minBit 0, minWin=26, winSum=424
7671 12:20:56.829124 TX Vref=32, minBit 0, minWin=25, winSum=411
7672 12:20:56.832628 TX Vref=34, minBit 2, minWin=24, winSum=404
7673 12:20:56.836008 TX Vref=36, minBit 0, minWin=24, winSum=394
7674 12:20:56.842510 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
7675 12:20:56.842597
7676 12:20:56.845864 Final TX Range 0 Vref 30
7677 12:20:56.845950
7678 12:20:56.846017 ==
7679 12:20:56.849120 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 12:20:56.852458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 12:20:56.852544 ==
7682 12:20:56.852611
7683 12:20:56.852673
7684 12:20:56.855873 TX Vref Scan disable
7685 12:20:56.862643 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7686 12:20:56.862730 == TX Byte 0 ==
7687 12:20:56.865934 u2DelayCellOfst[0]=13 cells (4 PI)
7688 12:20:56.869444 u2DelayCellOfst[1]=16 cells (5 PI)
7689 12:20:56.872714 u2DelayCellOfst[2]=10 cells (3 PI)
7690 12:20:56.876185 u2DelayCellOfst[3]=13 cells (4 PI)
7691 12:20:56.879257 u2DelayCellOfst[4]=6 cells (2 PI)
7692 12:20:56.882494 u2DelayCellOfst[5]=0 cells (0 PI)
7693 12:20:56.885984 u2DelayCellOfst[6]=16 cells (5 PI)
7694 12:20:56.889481 u2DelayCellOfst[7]=16 cells (5 PI)
7695 12:20:56.892863 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7696 12:20:56.895843 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7697 12:20:56.898992 == TX Byte 1 ==
7698 12:20:56.902486 u2DelayCellOfst[8]=0 cells (0 PI)
7699 12:20:56.902573 u2DelayCellOfst[9]=0 cells (0 PI)
7700 12:20:56.905693 u2DelayCellOfst[10]=6 cells (2 PI)
7701 12:20:56.909411 u2DelayCellOfst[11]=3 cells (1 PI)
7702 12:20:56.912431 u2DelayCellOfst[12]=13 cells (4 PI)
7703 12:20:56.915596 u2DelayCellOfst[13]=10 cells (3 PI)
7704 12:20:56.919291 u2DelayCellOfst[14]=16 cells (5 PI)
7705 12:20:56.922441 u2DelayCellOfst[15]=13 cells (4 PI)
7706 12:20:56.925845 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7707 12:20:56.932481 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7708 12:20:56.932593 DramC Write-DBI on
7709 12:20:56.932700 ==
7710 12:20:56.935696 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 12:20:56.942044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 12:20:56.942179 ==
7713 12:20:56.942299
7714 12:20:56.942413
7715 12:20:56.942525 TX Vref Scan disable
7716 12:20:56.946465 == TX Byte 0 ==
7717 12:20:56.949399 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7718 12:20:56.952645 == TX Byte 1 ==
7719 12:20:56.956402 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7720 12:20:56.959498 DramC Write-DBI off
7721 12:20:56.959582
7722 12:20:56.959649 [DATLAT]
7723 12:20:56.959711 Freq=1600, CH0 RK0
7724 12:20:56.959772
7725 12:20:56.962919 DATLAT Default: 0xf
7726 12:20:56.963021 0, 0xFFFF, sum = 0
7727 12:20:56.966058 1, 0xFFFF, sum = 0
7728 12:20:56.969371 2, 0xFFFF, sum = 0
7729 12:20:56.969457 3, 0xFFFF, sum = 0
7730 12:20:56.972821 4, 0xFFFF, sum = 0
7731 12:20:56.972907 5, 0xFFFF, sum = 0
7732 12:20:56.976005 6, 0xFFFF, sum = 0
7733 12:20:56.976098 7, 0xFFFF, sum = 0
7734 12:20:56.979720 8, 0xFFFF, sum = 0
7735 12:20:56.979806 9, 0xFFFF, sum = 0
7736 12:20:56.982701 10, 0xFFFF, sum = 0
7737 12:20:56.982788 11, 0xFFFF, sum = 0
7738 12:20:56.986208 12, 0xFFFF, sum = 0
7739 12:20:56.986294 13, 0xFFFF, sum = 0
7740 12:20:56.989505 14, 0x0, sum = 1
7741 12:20:56.989594 15, 0x0, sum = 2
7742 12:20:56.992972 16, 0x0, sum = 3
7743 12:20:56.993058 17, 0x0, sum = 4
7744 12:20:56.996240 best_step = 15
7745 12:20:56.996325
7746 12:20:56.996392 ==
7747 12:20:56.999430 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 12:20:57.003091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 12:20:57.003177 ==
7750 12:20:57.003244 RX Vref Scan: 1
7751 12:20:57.003307
7752 12:20:57.006387 Set Vref Range= 24 -> 127
7753 12:20:57.006472
7754 12:20:57.009590 RX Vref 24 -> 127, step: 1
7755 12:20:57.009675
7756 12:20:57.012687 RX Delay 19 -> 252, step: 4
7757 12:20:57.012797
7758 12:20:57.015927 Set Vref, RX VrefLevel [Byte0]: 24
7759 12:20:57.019459 [Byte1]: 24
7760 12:20:57.019544
7761 12:20:57.022601 Set Vref, RX VrefLevel [Byte0]: 25
7762 12:20:57.026143 [Byte1]: 25
7763 12:20:57.026228
7764 12:20:57.029546 Set Vref, RX VrefLevel [Byte0]: 26
7765 12:20:57.032621 [Byte1]: 26
7766 12:20:57.036412
7767 12:20:57.036498 Set Vref, RX VrefLevel [Byte0]: 27
7768 12:20:57.039811 [Byte1]: 27
7769 12:20:57.044131
7770 12:20:57.044206 Set Vref, RX VrefLevel [Byte0]: 28
7771 12:20:57.047342 [Byte1]: 28
7772 12:20:57.051561
7773 12:20:57.051645 Set Vref, RX VrefLevel [Byte0]: 29
7774 12:20:57.054736 [Byte1]: 29
7775 12:20:57.059351
7776 12:20:57.059430 Set Vref, RX VrefLevel [Byte0]: 30
7777 12:20:57.062553 [Byte1]: 30
7778 12:20:57.066756
7779 12:20:57.066833 Set Vref, RX VrefLevel [Byte0]: 31
7780 12:20:57.069968 [Byte1]: 31
7781 12:20:57.074656
7782 12:20:57.074751 Set Vref, RX VrefLevel [Byte0]: 32
7783 12:20:57.077876 [Byte1]: 32
7784 12:20:57.082269
7785 12:20:57.082352 Set Vref, RX VrefLevel [Byte0]: 33
7786 12:20:57.084946 [Byte1]: 33
7787 12:20:57.089622
7788 12:20:57.089704 Set Vref, RX VrefLevel [Byte0]: 34
7789 12:20:57.092681 [Byte1]: 34
7790 12:20:57.097288
7791 12:20:57.097372 Set Vref, RX VrefLevel [Byte0]: 35
7792 12:20:57.100338 [Byte1]: 35
7793 12:20:57.104405
7794 12:20:57.104513 Set Vref, RX VrefLevel [Byte0]: 36
7795 12:20:57.107946 [Byte1]: 36
7796 12:20:57.112068
7797 12:20:57.112202 Set Vref, RX VrefLevel [Byte0]: 37
7798 12:20:57.115197 [Byte1]: 37
7799 12:20:57.119628
7800 12:20:57.119714 Set Vref, RX VrefLevel [Byte0]: 38
7801 12:20:57.122788 [Byte1]: 38
7802 12:20:57.127315
7803 12:20:57.127420 Set Vref, RX VrefLevel [Byte0]: 39
7804 12:20:57.130594 [Byte1]: 39
7805 12:20:57.135021
7806 12:20:57.135102 Set Vref, RX VrefLevel [Byte0]: 40
7807 12:20:57.138357 [Byte1]: 40
7808 12:20:57.142310
7809 12:20:57.142409 Set Vref, RX VrefLevel [Byte0]: 41
7810 12:20:57.145503 [Byte1]: 41
7811 12:20:57.150031
7812 12:20:57.150138 Set Vref, RX VrefLevel [Byte0]: 42
7813 12:20:57.153222 [Byte1]: 42
7814 12:20:57.157533
7815 12:20:57.157614 Set Vref, RX VrefLevel [Byte0]: 43
7816 12:20:57.161073 [Byte1]: 43
7817 12:20:57.165059
7818 12:20:57.165142 Set Vref, RX VrefLevel [Byte0]: 44
7819 12:20:57.168566 [Byte1]: 44
7820 12:20:57.172594
7821 12:20:57.172676 Set Vref, RX VrefLevel [Byte0]: 45
7822 12:20:57.176175 [Byte1]: 45
7823 12:20:57.180875
7824 12:20:57.180956 Set Vref, RX VrefLevel [Byte0]: 46
7825 12:20:57.183530 [Byte1]: 46
7826 12:20:57.188094
7827 12:20:57.188175 Set Vref, RX VrefLevel [Byte0]: 47
7828 12:20:57.191021 [Byte1]: 47
7829 12:20:57.195712
7830 12:20:57.195830 Set Vref, RX VrefLevel [Byte0]: 48
7831 12:20:57.198808 [Byte1]: 48
7832 12:20:57.202801
7833 12:20:57.202904 Set Vref, RX VrefLevel [Byte0]: 49
7834 12:20:57.206451 [Byte1]: 49
7835 12:20:57.210905
7836 12:20:57.210987 Set Vref, RX VrefLevel [Byte0]: 50
7837 12:20:57.213832 [Byte1]: 50
7838 12:20:57.218486
7839 12:20:57.218568 Set Vref, RX VrefLevel [Byte0]: 51
7840 12:20:57.221504 [Byte1]: 51
7841 12:20:57.226104
7842 12:20:57.226185 Set Vref, RX VrefLevel [Byte0]: 52
7843 12:20:57.229248 [Byte1]: 52
7844 12:20:57.233358
7845 12:20:57.233456 Set Vref, RX VrefLevel [Byte0]: 53
7846 12:20:57.236503 [Byte1]: 53
7847 12:20:57.241047
7848 12:20:57.241144 Set Vref, RX VrefLevel [Byte0]: 54
7849 12:20:57.244089 [Byte1]: 54
7850 12:20:57.248650
7851 12:20:57.248789 Set Vref, RX VrefLevel [Byte0]: 55
7852 12:20:57.251695 [Byte1]: 55
7853 12:20:57.256182
7854 12:20:57.256254 Set Vref, RX VrefLevel [Byte0]: 56
7855 12:20:57.259336 [Byte1]: 56
7856 12:20:57.263835
7857 12:20:57.263924 Set Vref, RX VrefLevel [Byte0]: 57
7858 12:20:57.266747 [Byte1]: 57
7859 12:20:57.271224
7860 12:20:57.271296 Set Vref, RX VrefLevel [Byte0]: 58
7861 12:20:57.274417 [Byte1]: 58
7862 12:20:57.278832
7863 12:20:57.278913 Set Vref, RX VrefLevel [Byte0]: 59
7864 12:20:57.282180 [Byte1]: 59
7865 12:20:57.286514
7866 12:20:57.286640 Set Vref, RX VrefLevel [Byte0]: 60
7867 12:20:57.290037 [Byte1]: 60
7868 12:20:57.293767
7869 12:20:57.293849 Set Vref, RX VrefLevel [Byte0]: 61
7870 12:20:57.297228 [Byte1]: 61
7871 12:20:57.301438
7872 12:20:57.301545 Set Vref, RX VrefLevel [Byte0]: 62
7873 12:20:57.304737 [Byte1]: 62
7874 12:20:57.308831
7875 12:20:57.308913 Set Vref, RX VrefLevel [Byte0]: 63
7876 12:20:57.312448 [Byte1]: 63
7877 12:20:57.316402
7878 12:20:57.316508 Set Vref, RX VrefLevel [Byte0]: 64
7879 12:20:57.319912 [Byte1]: 64
7880 12:20:57.324438
7881 12:20:57.324520 Set Vref, RX VrefLevel [Byte0]: 65
7882 12:20:57.327637 [Byte1]: 65
7883 12:20:57.331695
7884 12:20:57.331776 Set Vref, RX VrefLevel [Byte0]: 66
7885 12:20:57.335206 [Byte1]: 66
7886 12:20:57.339184
7887 12:20:57.339265 Set Vref, RX VrefLevel [Byte0]: 67
7888 12:20:57.342825 [Byte1]: 67
7889 12:20:57.347165
7890 12:20:57.347246 Set Vref, RX VrefLevel [Byte0]: 68
7891 12:20:57.350257 [Byte1]: 68
7892 12:20:57.354413
7893 12:20:57.354494 Set Vref, RX VrefLevel [Byte0]: 69
7894 12:20:57.357911 [Byte1]: 69
7895 12:20:57.362223
7896 12:20:57.362304 Set Vref, RX VrefLevel [Byte0]: 70
7897 12:20:57.365451 [Byte1]: 70
7898 12:20:57.369623
7899 12:20:57.369704 Set Vref, RX VrefLevel [Byte0]: 71
7900 12:20:57.373231 [Byte1]: 71
7901 12:20:57.377238
7902 12:20:57.377319 Set Vref, RX VrefLevel [Byte0]: 72
7903 12:20:57.380282 [Byte1]: 72
7904 12:20:57.384940
7905 12:20:57.385022 Set Vref, RX VrefLevel [Byte0]: 73
7906 12:20:57.387960 [Byte1]: 73
7907 12:20:57.392106
7908 12:20:57.392187 Set Vref, RX VrefLevel [Byte0]: 74
7909 12:20:57.395601 [Byte1]: 74
7910 12:20:57.399903
7911 12:20:57.399987 Set Vref, RX VrefLevel [Byte0]: 75
7912 12:20:57.403048 [Byte1]: 75
7913 12:20:57.407481
7914 12:20:57.407562 Set Vref, RX VrefLevel [Byte0]: 76
7915 12:20:57.410636 [Byte1]: 76
7916 12:20:57.415334
7917 12:20:57.415432 Set Vref, RX VrefLevel [Byte0]: 77
7918 12:20:57.418381 [Byte1]: 77
7919 12:20:57.422685
7920 12:20:57.422792 Set Vref, RX VrefLevel [Byte0]: 78
7921 12:20:57.425962 [Byte1]: 78
7922 12:20:57.430102
7923 12:20:57.430183 Final RX Vref Byte 0 = 62 to rank0
7924 12:20:57.433656 Final RX Vref Byte 1 = 62 to rank0
7925 12:20:57.436785 Final RX Vref Byte 0 = 62 to rank1
7926 12:20:57.439942 Final RX Vref Byte 1 = 62 to rank1==
7927 12:20:57.443419 Dram Type= 6, Freq= 0, CH_0, rank 0
7928 12:20:57.449975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7929 12:20:57.450057 ==
7930 12:20:57.450122 DQS Delay:
7931 12:20:57.450182 DQS0 = 0, DQS1 = 0
7932 12:20:57.453518 DQM Delay:
7933 12:20:57.453600 DQM0 = 136, DQM1 = 124
7934 12:20:57.456647 DQ Delay:
7935 12:20:57.460219 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7936 12:20:57.463443 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =144
7937 12:20:57.466790 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7938 12:20:57.470026 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7939 12:20:57.470109
7940 12:20:57.470173
7941 12:20:57.470232
7942 12:20:57.473571 [DramC_TX_OE_Calibration] TA2
7943 12:20:57.476677 Original DQ_B0 (3 6) =30, OEN = 27
7944 12:20:57.480323 Original DQ_B1 (3 6) =30, OEN = 27
7945 12:20:57.483376 24, 0x0, End_B0=24 End_B1=24
7946 12:20:57.483493 25, 0x0, End_B0=25 End_B1=25
7947 12:20:57.486692 26, 0x0, End_B0=26 End_B1=26
7948 12:20:57.489983 27, 0x0, End_B0=27 End_B1=27
7949 12:20:57.493195 28, 0x0, End_B0=28 End_B1=28
7950 12:20:57.493279 29, 0x0, End_B0=29 End_B1=29
7951 12:20:57.496758 30, 0x0, End_B0=30 End_B1=30
7952 12:20:57.499966 31, 0x4141, End_B0=30 End_B1=30
7953 12:20:57.503520 Byte0 end_step=30 best_step=27
7954 12:20:57.506732 Byte1 end_step=30 best_step=27
7955 12:20:57.509919 Byte0 TX OE(2T, 0.5T) = (3, 3)
7956 12:20:57.510002 Byte1 TX OE(2T, 0.5T) = (3, 3)
7957 12:20:57.513282
7958 12:20:57.513395
7959 12:20:57.520159 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7960 12:20:57.523191 CH0 RK0: MR19=303, MR18=1D1B
7961 12:20:57.530042 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7962 12:20:57.530127
7963 12:20:57.533194 ----->DramcWriteLeveling(PI) begin...
7964 12:20:57.533279 ==
7965 12:20:57.536341 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 12:20:57.540114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 12:20:57.540202 ==
7968 12:20:57.543319 Write leveling (Byte 0): 39 => 39
7969 12:20:57.546498 Write leveling (Byte 1): 31 => 31
7970 12:20:57.549968 DramcWriteLeveling(PI) end<-----
7971 12:20:57.550079
7972 12:20:57.550145 ==
7973 12:20:57.553465 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 12:20:57.556457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 12:20:57.556541 ==
7976 12:20:57.559770 [Gating] SW mode calibration
7977 12:20:57.566294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7978 12:20:57.572871 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7979 12:20:57.576412 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 12:20:57.579788 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 12:20:57.586185 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 12:20:57.589778 1 4 12 | B1->B0 | 2a2a 3232 | 1 0 | (1 1) (0 0)
7983 12:20:57.593020 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 12:20:57.599850 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 12:20:57.602946 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 12:20:57.606144 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 12:20:57.613070 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 12:20:57.616588 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7989 12:20:57.619606 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7990 12:20:57.626359 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 1)
7991 12:20:57.629405 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7992 12:20:57.632620 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 12:20:57.639361 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 12:20:57.642985 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 12:20:57.646158 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 12:20:57.652812 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 12:20:57.656082 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7998 12:20:57.659609 1 6 12 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
7999 12:20:57.665978 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 12:20:57.669544 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 12:20:57.672968 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 12:20:57.675950 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 12:20:57.682844 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 12:20:57.686353 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 12:20:57.689394 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 12:20:57.696197 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8007 12:20:57.699342 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8008 12:20:57.702524 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:20:57.709661 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:20:57.712830 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:20:57.715762 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:20:57.722482 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:20:57.726035 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 12:20:57.729286 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 12:20:57.736086 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 12:20:57.739216 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 12:20:57.742354 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 12:20:57.748923 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 12:20:57.752142 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 12:20:57.755788 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 12:20:57.762431 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8022 12:20:57.765723 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8023 12:20:57.768920 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8024 12:20:57.775662 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 12:20:57.775768 Total UI for P1: 0, mck2ui 16
8026 12:20:57.782148 best dqsien dly found for B0: ( 1, 9, 12)
8027 12:20:57.782232 Total UI for P1: 0, mck2ui 16
8028 12:20:57.785652 best dqsien dly found for B1: ( 1, 9, 14)
8029 12:20:57.792288 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8030 12:20:57.795867 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8031 12:20:57.795955
8032 12:20:57.799066 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8033 12:20:57.802451 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8034 12:20:57.805885 [Gating] SW calibration Done
8035 12:20:57.805965 ==
8036 12:20:57.809002 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 12:20:57.812489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 12:20:57.812571 ==
8039 12:20:57.815574 RX Vref Scan: 0
8040 12:20:57.815659
8041 12:20:57.815726 RX Vref 0 -> 0, step: 1
8042 12:20:57.815788
8043 12:20:57.819281 RX Delay 0 -> 252, step: 8
8044 12:20:57.822499 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8045 12:20:57.825991 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8046 12:20:57.832162 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8047 12:20:57.835685 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8048 12:20:57.839215 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8049 12:20:57.842031 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8050 12:20:57.845621 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8051 12:20:57.852092 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8052 12:20:57.855477 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8053 12:20:57.858576 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8054 12:20:57.862084 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8055 12:20:57.868721 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8056 12:20:57.872083 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8057 12:20:57.875108 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8058 12:20:57.878351 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8059 12:20:57.881797 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8060 12:20:57.885292 ==
8061 12:20:57.885416 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 12:20:57.891949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 12:20:57.892076 ==
8064 12:20:57.892189 DQS Delay:
8065 12:20:57.895139 DQS0 = 0, DQS1 = 0
8066 12:20:57.895234 DQM Delay:
8067 12:20:57.898321 DQM0 = 136, DQM1 = 125
8068 12:20:57.898409 DQ Delay:
8069 12:20:57.901588 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8070 12:20:57.905279 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8071 12:20:57.908465 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8072 12:20:57.911645 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8073 12:20:57.911731
8074 12:20:57.911806
8075 12:20:57.911870 ==
8076 12:20:57.915202 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 12:20:57.921677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 12:20:57.921762 ==
8079 12:20:57.921829
8080 12:20:57.921890
8081 12:20:57.921950 TX Vref Scan disable
8082 12:20:57.925281 == TX Byte 0 ==
8083 12:20:57.928626 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8084 12:20:57.934794 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8085 12:20:57.934880 == TX Byte 1 ==
8086 12:20:57.938426 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8087 12:20:57.944783 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8088 12:20:57.944869 ==
8089 12:20:57.948124 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 12:20:57.951605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 12:20:57.951691 ==
8092 12:20:57.966130
8093 12:20:57.969309 TX Vref early break, caculate TX vref
8094 12:20:57.972739 TX Vref=16, minBit 8, minWin=23, winSum=388
8095 12:20:57.976057 TX Vref=18, minBit 0, minWin=24, winSum=402
8096 12:20:57.979646 TX Vref=20, minBit 8, minWin=24, winSum=405
8097 12:20:57.982650 TX Vref=22, minBit 0, minWin=25, winSum=412
8098 12:20:57.986203 TX Vref=24, minBit 0, minWin=25, winSum=423
8099 12:20:57.992938 TX Vref=26, minBit 0, minWin=26, winSum=429
8100 12:20:57.995907 TX Vref=28, minBit 2, minWin=26, winSum=433
8101 12:20:57.999584 TX Vref=30, minBit 0, minWin=26, winSum=428
8102 12:20:58.002743 TX Vref=32, minBit 0, minWin=26, winSum=421
8103 12:20:58.006206 TX Vref=34, minBit 2, minWin=25, winSum=414
8104 12:20:58.009445 TX Vref=36, minBit 2, minWin=24, winSum=403
8105 12:20:58.015701 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 28
8106 12:20:58.015786
8107 12:20:58.019257 Final TX Range 0 Vref 28
8108 12:20:58.019341
8109 12:20:58.019407 ==
8110 12:20:58.022469 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 12:20:58.025627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 12:20:58.025711 ==
8113 12:20:58.025776
8114 12:20:58.029173
8115 12:20:58.029256 TX Vref Scan disable
8116 12:20:58.035460 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8117 12:20:58.035544 == TX Byte 0 ==
8118 12:20:58.039251 u2DelayCellOfst[0]=13 cells (4 PI)
8119 12:20:58.042193 u2DelayCellOfst[1]=16 cells (5 PI)
8120 12:20:58.045651 u2DelayCellOfst[2]=13 cells (4 PI)
8121 12:20:58.049170 u2DelayCellOfst[3]=13 cells (4 PI)
8122 12:20:58.052304 u2DelayCellOfst[4]=10 cells (3 PI)
8123 12:20:58.055593 u2DelayCellOfst[5]=0 cells (0 PI)
8124 12:20:58.058989 u2DelayCellOfst[6]=16 cells (5 PI)
8125 12:20:58.062414 u2DelayCellOfst[7]=20 cells (6 PI)
8126 12:20:58.065460 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8127 12:20:58.068929 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8128 12:20:58.072057 == TX Byte 1 ==
8129 12:20:58.075349 u2DelayCellOfst[8]=3 cells (1 PI)
8130 12:20:58.078920 u2DelayCellOfst[9]=0 cells (0 PI)
8131 12:20:58.081958 u2DelayCellOfst[10]=10 cells (3 PI)
8132 12:20:58.085471 u2DelayCellOfst[11]=3 cells (1 PI)
8133 12:20:58.085554 u2DelayCellOfst[12]=13 cells (4 PI)
8134 12:20:58.088631 u2DelayCellOfst[13]=13 cells (4 PI)
8135 12:20:58.092075 u2DelayCellOfst[14]=13 cells (4 PI)
8136 12:20:58.095716 u2DelayCellOfst[15]=10 cells (3 PI)
8137 12:20:58.102068 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8138 12:20:58.105631 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8139 12:20:58.105714 DramC Write-DBI on
8140 12:20:58.105780 ==
8141 12:20:58.109092 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 12:20:58.115636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 12:20:58.115719 ==
8144 12:20:58.115784
8145 12:20:58.115845
8146 12:20:58.115904 TX Vref Scan disable
8147 12:20:58.119723 == TX Byte 0 ==
8148 12:20:58.122913 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8149 12:20:58.126541 == TX Byte 1 ==
8150 12:20:58.129662 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8151 12:20:58.132790 DramC Write-DBI off
8152 12:20:58.132873
8153 12:20:58.132938 [DATLAT]
8154 12:20:58.132998 Freq=1600, CH0 RK1
8155 12:20:58.133058
8156 12:20:58.136185 DATLAT Default: 0xf
8157 12:20:58.139571 0, 0xFFFF, sum = 0
8158 12:20:58.139656 1, 0xFFFF, sum = 0
8159 12:20:58.143084 2, 0xFFFF, sum = 0
8160 12:20:58.143175 3, 0xFFFF, sum = 0
8161 12:20:58.146163 4, 0xFFFF, sum = 0
8162 12:20:58.146248 5, 0xFFFF, sum = 0
8163 12:20:58.149570 6, 0xFFFF, sum = 0
8164 12:20:58.149660 7, 0xFFFF, sum = 0
8165 12:20:58.152838 8, 0xFFFF, sum = 0
8166 12:20:58.152937 9, 0xFFFF, sum = 0
8167 12:20:58.155912 10, 0xFFFF, sum = 0
8168 12:20:58.156031 11, 0xFFFF, sum = 0
8169 12:20:58.159333 12, 0xFFFF, sum = 0
8170 12:20:58.159422 13, 0xFFFF, sum = 0
8171 12:20:58.162528 14, 0x0, sum = 1
8172 12:20:58.162640 15, 0x0, sum = 2
8173 12:20:58.165844 16, 0x0, sum = 3
8174 12:20:58.165928 17, 0x0, sum = 4
8175 12:20:58.169477 best_step = 15
8176 12:20:58.169585
8177 12:20:58.169679 ==
8178 12:20:58.172538 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 12:20:58.175747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 12:20:58.175831 ==
8181 12:20:58.179286 RX Vref Scan: 0
8182 12:20:58.179418
8183 12:20:58.179534 RX Vref 0 -> 0, step: 1
8184 12:20:58.179677
8185 12:20:58.182455 RX Delay 11 -> 252, step: 4
8186 12:20:58.189093 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8187 12:20:58.192729 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8188 12:20:58.195754 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8189 12:20:58.199172 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8190 12:20:58.202337 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8191 12:20:58.205588 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8192 12:20:58.212290 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8193 12:20:58.215698 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8194 12:20:58.219035 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8195 12:20:58.222736 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8196 12:20:58.225928 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8197 12:20:58.232567 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8198 12:20:58.235858 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8199 12:20:58.239475 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8200 12:20:58.242736 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8201 12:20:58.249499 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8202 12:20:58.249583 ==
8203 12:20:58.252406 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 12:20:58.255785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 12:20:58.255869 ==
8206 12:20:58.255936 DQS Delay:
8207 12:20:58.258991 DQS0 = 0, DQS1 = 0
8208 12:20:58.259074 DQM Delay:
8209 12:20:58.262302 DQM0 = 133, DQM1 = 123
8210 12:20:58.262389 DQ Delay:
8211 12:20:58.265748 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8212 12:20:58.268981 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8213 12:20:58.272490 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8214 12:20:58.275579 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8215 12:20:58.275663
8216 12:20:58.275734
8217 12:20:58.275798
8218 12:20:58.279193 [DramC_TX_OE_Calibration] TA2
8219 12:20:58.282413 Original DQ_B0 (3 6) =30, OEN = 27
8220 12:20:58.285915 Original DQ_B1 (3 6) =30, OEN = 27
8221 12:20:58.288954 24, 0x0, End_B0=24 End_B1=24
8222 12:20:58.292539 25, 0x0, End_B0=25 End_B1=25
8223 12:20:58.292616 26, 0x0, End_B0=26 End_B1=26
8224 12:20:58.295682 27, 0x0, End_B0=27 End_B1=27
8225 12:20:58.299192 28, 0x0, End_B0=28 End_B1=28
8226 12:20:58.302217 29, 0x0, End_B0=29 End_B1=29
8227 12:20:58.305910 30, 0x0, End_B0=30 End_B1=30
8228 12:20:58.305996 31, 0x4141, End_B0=30 End_B1=30
8229 12:20:58.309105 Byte0 end_step=30 best_step=27
8230 12:20:58.312331 Byte1 end_step=30 best_step=27
8231 12:20:58.315819 Byte0 TX OE(2T, 0.5T) = (3, 3)
8232 12:20:58.319055 Byte1 TX OE(2T, 0.5T) = (3, 3)
8233 12:20:58.319176
8234 12:20:58.319301
8235 12:20:58.325508 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8236 12:20:58.329041 CH0 RK1: MR19=303, MR18=220F
8237 12:20:58.335526 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8238 12:20:58.338740 [RxdqsGatingPostProcess] freq 1600
8239 12:20:58.345528 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8240 12:20:58.345611 best DQS0 dly(2T, 0.5T) = (1, 1)
8241 12:20:58.349022 best DQS1 dly(2T, 0.5T) = (1, 1)
8242 12:20:58.352140 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8243 12:20:58.355321 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8244 12:20:58.358948 best DQS0 dly(2T, 0.5T) = (1, 1)
8245 12:20:58.362238 best DQS1 dly(2T, 0.5T) = (1, 1)
8246 12:20:58.365347 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8247 12:20:58.368691 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8248 12:20:58.372125 Pre-setting of DQS Precalculation
8249 12:20:58.375355 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8250 12:20:58.375439 ==
8251 12:20:58.378756 Dram Type= 6, Freq= 0, CH_1, rank 0
8252 12:20:58.385331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 12:20:58.385416 ==
8254 12:20:58.388727 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8255 12:20:58.395141 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8256 12:20:58.398566 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8257 12:20:58.405023 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8258 12:20:58.412620 [CA 0] Center 42 (12~72) winsize 61
8259 12:20:58.416364 [CA 1] Center 42 (12~72) winsize 61
8260 12:20:58.419455 [CA 2] Center 38 (9~68) winsize 60
8261 12:20:58.422700 [CA 3] Center 37 (8~67) winsize 60
8262 12:20:58.426004 [CA 4] Center 37 (8~67) winsize 60
8263 12:20:58.429641 [CA 5] Center 37 (7~67) winsize 61
8264 12:20:58.429725
8265 12:20:58.432713 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8266 12:20:58.432834
8267 12:20:58.435769 [CATrainingPosCal] consider 1 rank data
8268 12:20:58.439409 u2DelayCellTimex100 = 290/100 ps
8269 12:20:58.442539 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8270 12:20:58.449380 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8271 12:20:58.452548 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8272 12:20:58.455821 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8273 12:20:58.459358 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8274 12:20:58.462470 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8275 12:20:58.462592
8276 12:20:58.466028 CA PerBit enable=1, Macro0, CA PI delay=37
8277 12:20:58.466145
8278 12:20:58.469292 [CBTSetCACLKResult] CA Dly = 37
8279 12:20:58.472391 CS Dly: 8 (0~39)
8280 12:20:58.475717 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8281 12:20:58.479276 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8282 12:20:58.479375 ==
8283 12:20:58.482626 Dram Type= 6, Freq= 0, CH_1, rank 1
8284 12:20:58.485845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 12:20:58.485932 ==
8286 12:20:58.492566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 12:20:58.495829 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 12:20:58.502525 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 12:20:58.505660 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 12:20:58.516082 [CA 0] Center 42 (13~72) winsize 60
8291 12:20:58.519398 [CA 1] Center 42 (12~72) winsize 61
8292 12:20:58.522694 [CA 2] Center 38 (9~68) winsize 60
8293 12:20:58.525637 [CA 3] Center 37 (8~67) winsize 60
8294 12:20:58.529225 [CA 4] Center 38 (9~67) winsize 59
8295 12:20:58.532345 [CA 5] Center 37 (7~67) winsize 61
8296 12:20:58.532466
8297 12:20:58.536090 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8298 12:20:58.536206
8299 12:20:58.539090 [CATrainingPosCal] consider 2 rank data
8300 12:20:58.542530 u2DelayCellTimex100 = 290/100 ps
8301 12:20:58.545701 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8302 12:20:58.552354 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8303 12:20:58.555917 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8304 12:20:58.559512 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8305 12:20:58.562649 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8306 12:20:58.565677 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8307 12:20:58.565759
8308 12:20:58.569153 CA PerBit enable=1, Macro0, CA PI delay=37
8309 12:20:58.569227
8310 12:20:58.572478 [CBTSetCACLKResult] CA Dly = 37
8311 12:20:58.572551 CS Dly: 9 (0~42)
8312 12:20:58.579259 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 12:20:58.582441 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 12:20:58.582570
8315 12:20:58.585977 ----->DramcWriteLeveling(PI) begin...
8316 12:20:58.586100 ==
8317 12:20:58.589028 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 12:20:58.592374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 12:20:58.592493 ==
8320 12:20:58.595705 Write leveling (Byte 0): 22 => 22
8321 12:20:58.599157 Write leveling (Byte 1): 26 => 26
8322 12:20:58.602518 DramcWriteLeveling(PI) end<-----
8323 12:20:58.602642
8324 12:20:58.602756 ==
8325 12:20:58.605668 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 12:20:58.612334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 12:20:58.612443 ==
8328 12:20:58.612539 [Gating] SW mode calibration
8329 12:20:58.622317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8330 12:20:58.625517 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8331 12:20:58.629260 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 12:20:58.635474 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 12:20:58.638847 1 4 8 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (0 0)
8334 12:20:58.642171 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 12:20:58.648691 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 12:20:58.652342 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 12:20:58.655699 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 12:20:58.662227 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 12:20:58.665436 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 12:20:58.668976 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8341 12:20:58.675491 1 5 8 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
8342 12:20:58.678991 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 12:20:58.681974 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 12:20:58.689276 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 12:20:58.691924 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 12:20:58.695555 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 12:20:58.701838 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 12:20:58.705149 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8349 12:20:58.708798 1 6 8 | B1->B0 | 3333 3b3b | 0 0 | (0 0) (0 0)
8350 12:20:58.715197 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 12:20:58.718628 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 12:20:58.722042 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 12:20:58.728749 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 12:20:58.732306 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 12:20:58.735355 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 12:20:58.741996 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 12:20:58.745250 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8358 12:20:58.748494 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8359 12:20:58.752173 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:20:58.758484 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:20:58.761950 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:20:58.765392 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:20:58.772014 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 12:20:58.775295 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 12:20:58.778438 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 12:20:58.785072 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 12:20:58.788276 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 12:20:58.792021 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 12:20:58.798516 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 12:20:58.801754 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 12:20:58.805001 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 12:20:58.811456 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8373 12:20:58.815294 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8374 12:20:58.818257 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8375 12:20:58.821832 Total UI for P1: 0, mck2ui 16
8376 12:20:58.824705 best dqsien dly found for B0: ( 1, 9, 6)
8377 12:20:58.831664 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 12:20:58.831749 Total UI for P1: 0, mck2ui 16
8379 12:20:58.838455 best dqsien dly found for B1: ( 1, 9, 10)
8380 12:20:58.841596 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8381 12:20:58.845133 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8382 12:20:58.845215
8383 12:20:58.848181 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8384 12:20:58.851426 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8385 12:20:58.854685 [Gating] SW calibration Done
8386 12:20:58.854769 ==
8387 12:20:58.858434 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 12:20:58.861647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 12:20:58.861729 ==
8390 12:20:58.865019 RX Vref Scan: 0
8391 12:20:58.865102
8392 12:20:58.865169 RX Vref 0 -> 0, step: 1
8393 12:20:58.865231
8394 12:20:58.868090 RX Delay 0 -> 252, step: 8
8395 12:20:58.871674 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
8396 12:20:58.874792 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8397 12:20:58.881948 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8398 12:20:58.884747 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8399 12:20:58.888314 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8400 12:20:58.891717 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8401 12:20:58.894802 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8402 12:20:58.901518 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8403 12:20:58.904741 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8404 12:20:58.908378 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8405 12:20:58.911590 iDelay=200, Bit 10, Center 135 (88 ~ 183) 96
8406 12:20:58.915040 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8407 12:20:58.921528 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8408 12:20:58.924930 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8409 12:20:58.928591 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8410 12:20:58.931435 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8411 12:20:58.931516 ==
8412 12:20:58.934993 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 12:20:58.941689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 12:20:58.941777 ==
8415 12:20:58.941851 DQS Delay:
8416 12:20:58.941943 DQS0 = 0, DQS1 = 0
8417 12:20:58.944573 DQM Delay:
8418 12:20:58.944693 DQM0 = 136, DQM1 = 131
8419 12:20:58.948167 DQ Delay:
8420 12:20:58.951234 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =139
8421 12:20:58.955051 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8422 12:20:58.958192 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8423 12:20:58.961453 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8424 12:20:58.961538
8425 12:20:58.961606
8426 12:20:58.961669 ==
8427 12:20:58.964607 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 12:20:58.967826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 12:20:58.967937 ==
8430 12:20:58.971438
8431 12:20:58.971523
8432 12:20:58.971591 TX Vref Scan disable
8433 12:20:58.974585 == TX Byte 0 ==
8434 12:20:58.978069 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8435 12:20:58.981178 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8436 12:20:58.984688 == TX Byte 1 ==
8437 12:20:58.988302 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8438 12:20:58.991536 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8439 12:20:58.991621 ==
8440 12:20:58.994862 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 12:20:59.001533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 12:20:59.001620 ==
8443 12:20:59.012633
8444 12:20:59.016262 TX Vref early break, caculate TX vref
8445 12:20:59.019757 TX Vref=16, minBit 12, minWin=22, winSum=373
8446 12:20:59.023007 TX Vref=18, minBit 10, minWin=23, winSum=385
8447 12:20:59.026199 TX Vref=20, minBit 1, minWin=24, winSum=400
8448 12:20:59.029765 TX Vref=22, minBit 14, minWin=24, winSum=402
8449 12:20:59.032835 TX Vref=24, minBit 1, minWin=25, winSum=419
8450 12:20:59.039503 TX Vref=26, minBit 1, minWin=25, winSum=420
8451 12:20:59.042954 TX Vref=28, minBit 1, minWin=25, winSum=428
8452 12:20:59.046194 TX Vref=30, minBit 13, minWin=25, winSum=424
8453 12:20:59.049648 TX Vref=32, minBit 8, minWin=25, winSum=415
8454 12:20:59.053084 TX Vref=34, minBit 0, minWin=25, winSum=404
8455 12:20:59.059828 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 28
8456 12:20:59.059955
8457 12:20:59.062942 Final TX Range 0 Vref 28
8458 12:20:59.063065
8459 12:20:59.063182 ==
8460 12:20:59.066123 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 12:20:59.069294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 12:20:59.069418 ==
8463 12:20:59.069532
8464 12:20:59.069649
8465 12:20:59.072925 TX Vref Scan disable
8466 12:20:59.079345 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8467 12:20:59.079477 == TX Byte 0 ==
8468 12:20:59.082812 u2DelayCellOfst[0]=16 cells (5 PI)
8469 12:20:59.086080 u2DelayCellOfst[1]=6 cells (2 PI)
8470 12:20:59.089505 u2DelayCellOfst[2]=0 cells (0 PI)
8471 12:20:59.093145 u2DelayCellOfst[3]=3 cells (1 PI)
8472 12:20:59.096427 u2DelayCellOfst[4]=6 cells (2 PI)
8473 12:20:59.099520 u2DelayCellOfst[5]=20 cells (6 PI)
8474 12:20:59.102985 u2DelayCellOfst[6]=16 cells (5 PI)
8475 12:20:59.103111 u2DelayCellOfst[7]=6 cells (2 PI)
8476 12:20:59.109432 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8477 12:20:59.112846 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8478 12:20:59.112973 == TX Byte 1 ==
8479 12:20:59.116575 u2DelayCellOfst[8]=0 cells (0 PI)
8480 12:20:59.119616 u2DelayCellOfst[9]=3 cells (1 PI)
8481 12:20:59.122963 u2DelayCellOfst[10]=10 cells (3 PI)
8482 12:20:59.126131 u2DelayCellOfst[11]=3 cells (1 PI)
8483 12:20:59.129828 u2DelayCellOfst[12]=13 cells (4 PI)
8484 12:20:59.132926 u2DelayCellOfst[13]=16 cells (5 PI)
8485 12:20:59.136404 u2DelayCellOfst[14]=16 cells (5 PI)
8486 12:20:59.139699 u2DelayCellOfst[15]=13 cells (4 PI)
8487 12:20:59.142692 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8488 12:20:59.146193 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8489 12:20:59.149670 DramC Write-DBI on
8490 12:20:59.149790 ==
8491 12:20:59.153027 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 12:20:59.155882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 12:20:59.156007 ==
8494 12:20:59.156123
8495 12:20:59.159619
8496 12:20:59.159735 TX Vref Scan disable
8497 12:20:59.162731 == TX Byte 0 ==
8498 12:20:59.165928 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8499 12:20:59.169349 == TX Byte 1 ==
8500 12:20:59.172765 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8501 12:20:59.172900 DramC Write-DBI off
8502 12:20:59.173014
8503 12:20:59.175886 [DATLAT]
8504 12:20:59.176001 Freq=1600, CH1 RK0
8505 12:20:59.176116
8506 12:20:59.179538 DATLAT Default: 0xf
8507 12:20:59.179667 0, 0xFFFF, sum = 0
8508 12:20:59.182568 1, 0xFFFF, sum = 0
8509 12:20:59.182694 2, 0xFFFF, sum = 0
8510 12:20:59.185686 3, 0xFFFF, sum = 0
8511 12:20:59.185808 4, 0xFFFF, sum = 0
8512 12:20:59.189396 5, 0xFFFF, sum = 0
8513 12:20:59.192430 6, 0xFFFF, sum = 0
8514 12:20:59.192550 7, 0xFFFF, sum = 0
8515 12:20:59.195708 8, 0xFFFF, sum = 0
8516 12:20:59.195832 9, 0xFFFF, sum = 0
8517 12:20:59.199117 10, 0xFFFF, sum = 0
8518 12:20:59.199239 11, 0xFFFF, sum = 0
8519 12:20:59.202341 12, 0xFFFF, sum = 0
8520 12:20:59.202464 13, 0xFFFF, sum = 0
8521 12:20:59.205706 14, 0x0, sum = 1
8522 12:20:59.205830 15, 0x0, sum = 2
8523 12:20:59.208998 16, 0x0, sum = 3
8524 12:20:59.209123 17, 0x0, sum = 4
8525 12:20:59.212228 best_step = 15
8526 12:20:59.212345
8527 12:20:59.212457 ==
8528 12:20:59.215784 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 12:20:59.219245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 12:20:59.219375 ==
8531 12:20:59.219486 RX Vref Scan: 1
8532 12:20:59.219599
8533 12:20:59.222444 Set Vref Range= 24 -> 127
8534 12:20:59.222563
8535 12:20:59.225736 RX Vref 24 -> 127, step: 1
8536 12:20:59.225857
8537 12:20:59.229328 RX Delay 19 -> 252, step: 4
8538 12:20:59.229453
8539 12:20:59.232295 Set Vref, RX VrefLevel [Byte0]: 24
8540 12:20:59.235626 [Byte1]: 24
8541 12:20:59.235744
8542 12:20:59.239039 Set Vref, RX VrefLevel [Byte0]: 25
8543 12:20:59.242375 [Byte1]: 25
8544 12:20:59.242501
8545 12:20:59.245771 Set Vref, RX VrefLevel [Byte0]: 26
8546 12:20:59.248724 [Byte1]: 26
8547 12:20:59.252380
8548 12:20:59.255856 Set Vref, RX VrefLevel [Byte0]: 27
8549 12:20:59.258927 [Byte1]: 27
8550 12:20:59.259045
8551 12:20:59.262521 Set Vref, RX VrefLevel [Byte0]: 28
8552 12:20:59.265676 [Byte1]: 28
8553 12:20:59.265797
8554 12:20:59.269183 Set Vref, RX VrefLevel [Byte0]: 29
8555 12:20:59.272295 [Byte1]: 29
8556 12:20:59.272416
8557 12:20:59.275486 Set Vref, RX VrefLevel [Byte0]: 30
8558 12:20:59.279071 [Byte1]: 30
8559 12:20:59.282957
8560 12:20:59.283063 Set Vref, RX VrefLevel [Byte0]: 31
8561 12:20:59.286492 [Byte1]: 31
8562 12:20:59.290452
8563 12:20:59.290535 Set Vref, RX VrefLevel [Byte0]: 32
8564 12:20:59.294027 [Byte1]: 32
8565 12:20:59.298060
8566 12:20:59.298144 Set Vref, RX VrefLevel [Byte0]: 33
8567 12:20:59.301600 [Byte1]: 33
8568 12:20:59.305652
8569 12:20:59.305735 Set Vref, RX VrefLevel [Byte0]: 34
8570 12:20:59.309415 [Byte1]: 34
8571 12:20:59.313273
8572 12:20:59.313369 Set Vref, RX VrefLevel [Byte0]: 35
8573 12:20:59.316597 [Byte1]: 35
8574 12:20:59.320860
8575 12:20:59.320936 Set Vref, RX VrefLevel [Byte0]: 36
8576 12:20:59.324187 [Byte1]: 36
8577 12:20:59.328141
8578 12:20:59.328226 Set Vref, RX VrefLevel [Byte0]: 37
8579 12:20:59.331925 [Byte1]: 37
8580 12:20:59.336000
8581 12:20:59.336084 Set Vref, RX VrefLevel [Byte0]: 38
8582 12:20:59.339106 [Byte1]: 38
8583 12:20:59.343492
8584 12:20:59.343575 Set Vref, RX VrefLevel [Byte0]: 39
8585 12:20:59.346865 [Byte1]: 39
8586 12:20:59.350899
8587 12:20:59.350982 Set Vref, RX VrefLevel [Byte0]: 40
8588 12:20:59.354474 [Byte1]: 40
8589 12:20:59.358726
8590 12:20:59.358809 Set Vref, RX VrefLevel [Byte0]: 41
8591 12:20:59.361779 [Byte1]: 41
8592 12:20:59.366331
8593 12:20:59.366414 Set Vref, RX VrefLevel [Byte0]: 42
8594 12:20:59.369539 [Byte1]: 42
8595 12:20:59.373983
8596 12:20:59.374067 Set Vref, RX VrefLevel [Byte0]: 43
8597 12:20:59.377135 [Byte1]: 43
8598 12:20:59.381565
8599 12:20:59.381649 Set Vref, RX VrefLevel [Byte0]: 44
8600 12:20:59.384799 [Byte1]: 44
8601 12:20:59.388858
8602 12:20:59.388941 Set Vref, RX VrefLevel [Byte0]: 45
8603 12:20:59.392312 [Byte1]: 45
8604 12:20:59.396538
8605 12:20:59.396625 Set Vref, RX VrefLevel [Byte0]: 46
8606 12:20:59.399689 [Byte1]: 46
8607 12:20:59.404189
8608 12:20:59.404272 Set Vref, RX VrefLevel [Byte0]: 47
8609 12:20:59.407317 [Byte1]: 47
8610 12:20:59.411749
8611 12:20:59.411833 Set Vref, RX VrefLevel [Byte0]: 48
8612 12:20:59.415166 [Byte1]: 48
8613 12:20:59.419472
8614 12:20:59.419555 Set Vref, RX VrefLevel [Byte0]: 49
8615 12:20:59.422360 [Byte1]: 49
8616 12:20:59.426879
8617 12:20:59.426989 Set Vref, RX VrefLevel [Byte0]: 50
8618 12:20:59.430151 [Byte1]: 50
8619 12:20:59.434297
8620 12:20:59.434426 Set Vref, RX VrefLevel [Byte0]: 51
8621 12:20:59.437799 [Byte1]: 51
8622 12:20:59.441996
8623 12:20:59.442095 Set Vref, RX VrefLevel [Byte0]: 52
8624 12:20:59.444971 [Byte1]: 52
8625 12:20:59.449752
8626 12:20:59.449853 Set Vref, RX VrefLevel [Byte0]: 53
8627 12:20:59.452903 [Byte1]: 53
8628 12:20:59.456957
8629 12:20:59.457087 Set Vref, RX VrefLevel [Byte0]: 54
8630 12:20:59.460284 [Byte1]: 54
8631 12:20:59.464931
8632 12:20:59.465013 Set Vref, RX VrefLevel [Byte0]: 55
8633 12:20:59.467997 [Byte1]: 55
8634 12:20:59.472376
8635 12:20:59.472497 Set Vref, RX VrefLevel [Byte0]: 56
8636 12:20:59.475599 [Byte1]: 56
8637 12:20:59.479743
8638 12:20:59.479824 Set Vref, RX VrefLevel [Byte0]: 57
8639 12:20:59.483040 [Byte1]: 57
8640 12:20:59.487361
8641 12:20:59.487442 Set Vref, RX VrefLevel [Byte0]: 58
8642 12:20:59.490601 [Byte1]: 58
8643 12:20:59.495055
8644 12:20:59.495136 Set Vref, RX VrefLevel [Byte0]: 59
8645 12:20:59.498512 [Byte1]: 59
8646 12:20:59.502512
8647 12:20:59.502625 Set Vref, RX VrefLevel [Byte0]: 60
8648 12:20:59.505723 [Byte1]: 60
8649 12:20:59.509987
8650 12:20:59.510061 Set Vref, RX VrefLevel [Byte0]: 61
8651 12:20:59.513484 [Byte1]: 61
8652 12:20:59.517797
8653 12:20:59.517878 Set Vref, RX VrefLevel [Byte0]: 62
8654 12:20:59.521132 [Byte1]: 62
8655 12:20:59.525380
8656 12:20:59.525527 Set Vref, RX VrefLevel [Byte0]: 63
8657 12:20:59.528483 [Byte1]: 63
8658 12:20:59.532616
8659 12:20:59.532698 Set Vref, RX VrefLevel [Byte0]: 64
8660 12:20:59.536111 [Byte1]: 64
8661 12:20:59.540524
8662 12:20:59.540607 Set Vref, RX VrefLevel [Byte0]: 65
8663 12:20:59.543911 [Byte1]: 65
8664 12:20:59.548059
8665 12:20:59.548142 Set Vref, RX VrefLevel [Byte0]: 66
8666 12:20:59.551550 [Byte1]: 66
8667 12:20:59.555456
8668 12:20:59.555541 Set Vref, RX VrefLevel [Byte0]: 67
8669 12:20:59.558714 [Byte1]: 67
8670 12:20:59.563240
8671 12:20:59.563323 Set Vref, RX VrefLevel [Byte0]: 68
8672 12:20:59.566439 [Byte1]: 68
8673 12:20:59.570731
8674 12:20:59.570814 Set Vref, RX VrefLevel [Byte0]: 69
8675 12:20:59.573828 [Byte1]: 69
8676 12:20:59.578441
8677 12:20:59.578524 Set Vref, RX VrefLevel [Byte0]: 70
8678 12:20:59.581653 [Byte1]: 70
8679 12:20:59.586152
8680 12:20:59.586235 Set Vref, RX VrefLevel [Byte0]: 71
8681 12:20:59.589158 [Byte1]: 71
8682 12:20:59.593459
8683 12:20:59.593542 Set Vref, RX VrefLevel [Byte0]: 72
8684 12:20:59.596890 [Byte1]: 72
8685 12:20:59.600942
8686 12:20:59.601025 Set Vref, RX VrefLevel [Byte0]: 73
8687 12:20:59.604353 [Byte1]: 73
8688 12:20:59.608428
8689 12:20:59.608511 Set Vref, RX VrefLevel [Byte0]: 74
8690 12:20:59.611681 [Byte1]: 74
8691 12:20:59.616237
8692 12:20:59.616321 Set Vref, RX VrefLevel [Byte0]: 75
8693 12:20:59.619473 [Byte1]: 75
8694 12:20:59.623820
8695 12:20:59.623902 Final RX Vref Byte 0 = 59 to rank0
8696 12:20:59.627067 Final RX Vref Byte 1 = 64 to rank0
8697 12:20:59.630396 Final RX Vref Byte 0 = 59 to rank1
8698 12:20:59.633849 Final RX Vref Byte 1 = 64 to rank1==
8699 12:20:59.637132 Dram Type= 6, Freq= 0, CH_1, rank 0
8700 12:20:59.643800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8701 12:20:59.643885 ==
8702 12:20:59.643950 DQS Delay:
8703 12:20:59.644010 DQS0 = 0, DQS1 = 0
8704 12:20:59.647125 DQM Delay:
8705 12:20:59.647206 DQM0 = 134, DQM1 = 129
8706 12:20:59.650272 DQ Delay:
8707 12:20:59.653759 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8708 12:20:59.657023 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8709 12:20:59.660563 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8710 12:20:59.663799 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8711 12:20:59.663881
8712 12:20:59.663945
8713 12:20:59.664004
8714 12:20:59.667101 [DramC_TX_OE_Calibration] TA2
8715 12:20:59.670632 Original DQ_B0 (3 6) =30, OEN = 27
8716 12:20:59.673811 Original DQ_B1 (3 6) =30, OEN = 27
8717 12:20:59.676829 24, 0x0, End_B0=24 End_B1=24
8718 12:20:59.676912 25, 0x0, End_B0=25 End_B1=25
8719 12:20:59.680366 26, 0x0, End_B0=26 End_B1=26
8720 12:20:59.683500 27, 0x0, End_B0=27 End_B1=27
8721 12:20:59.686984 28, 0x0, End_B0=28 End_B1=28
8722 12:20:59.687067 29, 0x0, End_B0=29 End_B1=29
8723 12:20:59.690073 30, 0x0, End_B0=30 End_B1=30
8724 12:20:59.693734 31, 0x4141, End_B0=30 End_B1=30
8725 12:20:59.696918 Byte0 end_step=30 best_step=27
8726 12:20:59.699972 Byte1 end_step=30 best_step=27
8727 12:20:59.703449 Byte0 TX OE(2T, 0.5T) = (3, 3)
8728 12:20:59.703531 Byte1 TX OE(2T, 0.5T) = (3, 3)
8729 12:20:59.706529
8730 12:20:59.706607
8731 12:20:59.713197 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8732 12:20:59.716683 CH1 RK0: MR19=303, MR18=1A28
8733 12:20:59.723418 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8734 12:20:59.723501
8735 12:20:59.726672 ----->DramcWriteLeveling(PI) begin...
8736 12:20:59.726755 ==
8737 12:20:59.730479 Dram Type= 6, Freq= 0, CH_1, rank 1
8738 12:20:59.733343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 12:20:59.733425 ==
8740 12:20:59.736658 Write leveling (Byte 0): 25 => 25
8741 12:20:59.740171 Write leveling (Byte 1): 28 => 28
8742 12:20:59.743299 DramcWriteLeveling(PI) end<-----
8743 12:20:59.743383
8744 12:20:59.743448 ==
8745 12:20:59.746649 Dram Type= 6, Freq= 0, CH_1, rank 1
8746 12:20:59.750303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 12:20:59.750387 ==
8748 12:20:59.753474 [Gating] SW mode calibration
8749 12:20:59.760065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8750 12:20:59.766781 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8751 12:20:59.769927 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 12:20:59.773609 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 12:20:59.780222 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8754 12:20:59.783331 1 4 12 | B1->B0 | 3434 2c2b | 1 1 | (1 1) (0 0)
8755 12:20:59.786901 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 12:20:59.793615 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 12:20:59.796780 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 12:20:59.800307 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 12:20:59.807025 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 12:20:59.810389 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 12:20:59.813820 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)
8762 12:20:59.817025 1 5 12 | B1->B0 | 2323 3131 | 0 1 | (1 0) (0 1)
8763 12:20:59.823780 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 12:20:59.827272 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 12:20:59.830374 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 12:20:59.836999 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 12:20:59.840584 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 12:20:59.843912 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 12:20:59.850213 1 6 8 | B1->B0 | 4444 2424 | 0 0 | (0 0) (0 0)
8770 12:20:59.853570 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8771 12:20:59.856725 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 12:20:59.863426 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 12:20:59.866872 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 12:20:59.869977 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 12:20:59.876606 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 12:20:59.879806 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 12:20:59.883250 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8778 12:20:59.889914 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8779 12:20:59.892995 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 12:20:59.896590 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 12:20:59.903240 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 12:20:59.906396 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 12:20:59.910035 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:20:59.916584 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:20:59.919742 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:20:59.922894 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:20:59.929481 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:20:59.932931 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:20:59.936410 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 12:20:59.943080 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 12:20:59.946440 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 12:20:59.949557 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:20:59.956299 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8794 12:20:59.959740 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8795 12:20:59.962950 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 12:20:59.966070 Total UI for P1: 0, mck2ui 16
8797 12:20:59.969386 best dqsien dly found for B0: ( 1, 9, 10)
8798 12:20:59.972913 Total UI for P1: 0, mck2ui 16
8799 12:20:59.975999 best dqsien dly found for B1: ( 1, 9, 10)
8800 12:20:59.979620 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8801 12:20:59.982725 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8802 12:20:59.982827
8803 12:20:59.986284 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8804 12:20:59.992929 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8805 12:20:59.993012 [Gating] SW calibration Done
8806 12:20:59.993078 ==
8807 12:20:59.996096 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 12:21:00.002861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 12:21:00.002946 ==
8810 12:21:00.003012 RX Vref Scan: 0
8811 12:21:00.003075
8812 12:21:00.005987 RX Vref 0 -> 0, step: 1
8813 12:21:00.006102
8814 12:21:00.009472 RX Delay 0 -> 252, step: 8
8815 12:21:00.012678 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8816 12:21:00.016137 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8817 12:21:00.019324 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8818 12:21:00.026175 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8819 12:21:00.029273 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8820 12:21:00.032502 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8821 12:21:00.036065 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8822 12:21:00.039473 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8823 12:21:00.042463 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8824 12:21:00.049262 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8825 12:21:00.052906 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8826 12:21:00.055851 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8827 12:21:00.059285 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8828 12:21:00.065970 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8829 12:21:00.069124 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8830 12:21:00.072429 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8831 12:21:00.072603 ==
8832 12:21:00.075978 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 12:21:00.079138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 12:21:00.079259 ==
8835 12:21:00.082429 DQS Delay:
8836 12:21:00.082527 DQS0 = 0, DQS1 = 0
8837 12:21:00.085633 DQM Delay:
8838 12:21:00.085756 DQM0 = 136, DQM1 = 132
8839 12:21:00.085864 DQ Delay:
8840 12:21:00.089135 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8841 12:21:00.095684 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8842 12:21:00.099336 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8843 12:21:00.102408 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8844 12:21:00.102486
8845 12:21:00.102565
8846 12:21:00.102625 ==
8847 12:21:00.106048 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 12:21:00.109319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 12:21:00.109402 ==
8850 12:21:00.109469
8851 12:21:00.109531
8852 12:21:00.112461 TX Vref Scan disable
8853 12:21:00.115633 == TX Byte 0 ==
8854 12:21:00.119445 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8855 12:21:00.122604 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8856 12:21:00.125645 == TX Byte 1 ==
8857 12:21:00.129020 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8858 12:21:00.132232 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8859 12:21:00.132316 ==
8860 12:21:00.135744 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 12:21:00.139361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 12:21:00.142213 ==
8863 12:21:00.153009
8864 12:21:00.156515 TX Vref early break, caculate TX vref
8865 12:21:00.159795 TX Vref=16, minBit 11, minWin=22, winSum=381
8866 12:21:00.163399 TX Vref=18, minBit 10, minWin=23, winSum=391
8867 12:21:00.166311 TX Vref=20, minBit 9, minWin=23, winSum=394
8868 12:21:00.169886 TX Vref=22, minBit 9, minWin=23, winSum=407
8869 12:21:00.173084 TX Vref=24, minBit 9, minWin=24, winSum=416
8870 12:21:00.179946 TX Vref=26, minBit 12, minWin=24, winSum=420
8871 12:21:00.183107 TX Vref=28, minBit 10, minWin=24, winSum=418
8872 12:21:00.186290 TX Vref=30, minBit 10, minWin=24, winSum=414
8873 12:21:00.189960 TX Vref=32, minBit 9, minWin=24, winSum=406
8874 12:21:00.193208 TX Vref=34, minBit 0, minWin=24, winSum=398
8875 12:21:00.199621 [TxChooseVref] Worse bit 12, Min win 24, Win sum 420, Final Vref 26
8876 12:21:00.199727
8877 12:21:00.203100 Final TX Range 0 Vref 26
8878 12:21:00.203221
8879 12:21:00.203334 ==
8880 12:21:00.206240 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 12:21:00.209855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 12:21:00.209974 ==
8883 12:21:00.210089
8884 12:21:00.210202
8885 12:21:00.213014 TX Vref Scan disable
8886 12:21:00.219786 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8887 12:21:00.219910 == TX Byte 0 ==
8888 12:21:00.222964 u2DelayCellOfst[0]=16 cells (5 PI)
8889 12:21:00.226483 u2DelayCellOfst[1]=13 cells (4 PI)
8890 12:21:00.230002 u2DelayCellOfst[2]=0 cells (0 PI)
8891 12:21:00.233268 u2DelayCellOfst[3]=6 cells (2 PI)
8892 12:21:00.236348 u2DelayCellOfst[4]=10 cells (3 PI)
8893 12:21:00.239756 u2DelayCellOfst[5]=20 cells (6 PI)
8894 12:21:00.242791 u2DelayCellOfst[6]=16 cells (5 PI)
8895 12:21:00.246145 u2DelayCellOfst[7]=6 cells (2 PI)
8896 12:21:00.249864 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8897 12:21:00.252844 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8898 12:21:00.256169 == TX Byte 1 ==
8899 12:21:00.256294 u2DelayCellOfst[8]=0 cells (0 PI)
8900 12:21:00.259609 u2DelayCellOfst[9]=3 cells (1 PI)
8901 12:21:00.263102 u2DelayCellOfst[10]=6 cells (2 PI)
8902 12:21:00.266332 u2DelayCellOfst[11]=3 cells (1 PI)
8903 12:21:00.269640 u2DelayCellOfst[12]=10 cells (3 PI)
8904 12:21:00.272782 u2DelayCellOfst[13]=13 cells (4 PI)
8905 12:21:00.275905 u2DelayCellOfst[14]=16 cells (5 PI)
8906 12:21:00.279488 u2DelayCellOfst[15]=16 cells (5 PI)
8907 12:21:00.282594 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8908 12:21:00.289382 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8909 12:21:00.289508 DramC Write-DBI on
8910 12:21:00.289627 ==
8911 12:21:00.292537 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 12:21:00.299165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 12:21:00.299289 ==
8914 12:21:00.299405
8915 12:21:00.299521
8916 12:21:00.299628 TX Vref Scan disable
8917 12:21:00.303029 == TX Byte 0 ==
8918 12:21:00.306557 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8919 12:21:00.309343 == TX Byte 1 ==
8920 12:21:00.312943 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8921 12:21:00.316137 DramC Write-DBI off
8922 12:21:00.316257
8923 12:21:00.316371 [DATLAT]
8924 12:21:00.316482 Freq=1600, CH1 RK1
8925 12:21:00.316594
8926 12:21:00.319659 DATLAT Default: 0xf
8927 12:21:00.319775 0, 0xFFFF, sum = 0
8928 12:21:00.322763 1, 0xFFFF, sum = 0
8929 12:21:00.326070 2, 0xFFFF, sum = 0
8930 12:21:00.326194 3, 0xFFFF, sum = 0
8931 12:21:00.329710 4, 0xFFFF, sum = 0
8932 12:21:00.329839 5, 0xFFFF, sum = 0
8933 12:21:00.332962 6, 0xFFFF, sum = 0
8934 12:21:00.333088 7, 0xFFFF, sum = 0
8935 12:21:00.336002 8, 0xFFFF, sum = 0
8936 12:21:00.336128 9, 0xFFFF, sum = 0
8937 12:21:00.339543 10, 0xFFFF, sum = 0
8938 12:21:00.339670 11, 0xFFFF, sum = 0
8939 12:21:00.342762 12, 0xFFFF, sum = 0
8940 12:21:00.342888 13, 0xFFFF, sum = 0
8941 12:21:00.345799 14, 0x0, sum = 1
8942 12:21:00.345921 15, 0x0, sum = 2
8943 12:21:00.349317 16, 0x0, sum = 3
8944 12:21:00.349441 17, 0x0, sum = 4
8945 12:21:00.352619 best_step = 15
8946 12:21:00.352741
8947 12:21:00.352855 ==
8948 12:21:00.356223 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 12:21:00.359482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 12:21:00.359605 ==
8951 12:21:00.362848 RX Vref Scan: 0
8952 12:21:00.362969
8953 12:21:00.363083 RX Vref 0 -> 0, step: 1
8954 12:21:00.363192
8955 12:21:00.365886 RX Delay 19 -> 252, step: 4
8956 12:21:00.369459 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8957 12:21:00.375974 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8958 12:21:00.379072 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8959 12:21:00.382679 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8960 12:21:00.386110 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8961 12:21:00.389165 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8962 12:21:00.392275 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8963 12:21:00.399071 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8964 12:21:00.402585 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8965 12:21:00.405558 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8966 12:21:00.409309 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8967 12:21:00.412437 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8968 12:21:00.419064 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8969 12:21:00.422645 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8970 12:21:00.425765 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8971 12:21:00.429015 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8972 12:21:00.429093 ==
8973 12:21:00.432338 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 12:21:00.439578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 12:21:00.439693 ==
8976 12:21:00.439789 DQS Delay:
8977 12:21:00.442566 DQS0 = 0, DQS1 = 0
8978 12:21:00.442636 DQM Delay:
8979 12:21:00.442703 DQM0 = 133, DQM1 = 129
8980 12:21:00.446056 DQ Delay:
8981 12:21:00.449024 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8982 12:21:00.452453 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
8983 12:21:00.456272 DQ8 =112, DQ9 =118, DQ10 =128, DQ11 =124
8984 12:21:00.459466 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =142
8985 12:21:00.459574
8986 12:21:00.459666
8987 12:21:00.459763
8988 12:21:00.462544 [DramC_TX_OE_Calibration] TA2
8989 12:21:00.465592 Original DQ_B0 (3 6) =30, OEN = 27
8990 12:21:00.469187 Original DQ_B1 (3 6) =30, OEN = 27
8991 12:21:00.472326 24, 0x0, End_B0=24 End_B1=24
8992 12:21:00.472431 25, 0x0, End_B0=25 End_B1=25
8993 12:21:00.475822 26, 0x0, End_B0=26 End_B1=26
8994 12:21:00.479289 27, 0x0, End_B0=27 End_B1=27
8995 12:21:00.482190 28, 0x0, End_B0=28 End_B1=28
8996 12:21:00.486090 29, 0x0, End_B0=29 End_B1=29
8997 12:21:00.486198 30, 0x0, End_B0=30 End_B1=30
8998 12:21:00.488914 31, 0x4141, End_B0=30 End_B1=30
8999 12:21:00.492408 Byte0 end_step=30 best_step=27
9000 12:21:00.495595 Byte1 end_step=30 best_step=27
9001 12:21:00.499322 Byte0 TX OE(2T, 0.5T) = (3, 3)
9002 12:21:00.502408 Byte1 TX OE(2T, 0.5T) = (3, 3)
9003 12:21:00.502534
9004 12:21:00.502648
9005 12:21:00.509070 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9006 12:21:00.512172 CH1 RK1: MR19=303, MR18=1E09
9007 12:21:00.519105 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9008 12:21:00.522229 [RxdqsGatingPostProcess] freq 1600
9009 12:21:00.525504 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9010 12:21:00.529044 best DQS0 dly(2T, 0.5T) = (1, 1)
9011 12:21:00.532456 best DQS1 dly(2T, 0.5T) = (1, 1)
9012 12:21:00.535404 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9013 12:21:00.539034 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9014 12:21:00.542367 best DQS0 dly(2T, 0.5T) = (1, 1)
9015 12:21:00.545520 best DQS1 dly(2T, 0.5T) = (1, 1)
9016 12:21:00.548625 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9017 12:21:00.552138 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9018 12:21:00.555211 Pre-setting of DQS Precalculation
9019 12:21:00.558583 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9020 12:21:00.565395 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9021 12:21:00.571897 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9022 12:21:00.575077
9023 12:21:00.575180
9024 12:21:00.575273 [Calibration Summary] 3200 Mbps
9025 12:21:00.578726 CH 0, Rank 0
9026 12:21:00.578821 SW Impedance : PASS
9027 12:21:00.582161 DUTY Scan : NO K
9028 12:21:00.585279 ZQ Calibration : PASS
9029 12:21:00.585363 Jitter Meter : NO K
9030 12:21:00.588941 CBT Training : PASS
9031 12:21:00.592291 Write leveling : PASS
9032 12:21:00.592374 RX DQS gating : PASS
9033 12:21:00.595126 RX DQ/DQS(RDDQC) : PASS
9034 12:21:00.598793 TX DQ/DQS : PASS
9035 12:21:00.598878 RX DATLAT : PASS
9036 12:21:00.602083 RX DQ/DQS(Engine): PASS
9037 12:21:00.605223 TX OE : PASS
9038 12:21:00.605307 All Pass.
9039 12:21:00.605373
9040 12:21:00.605435 CH 0, Rank 1
9041 12:21:00.608413 SW Impedance : PASS
9042 12:21:00.611933 DUTY Scan : NO K
9043 12:21:00.612017 ZQ Calibration : PASS
9044 12:21:00.615138 Jitter Meter : NO K
9045 12:21:00.618481 CBT Training : PASS
9046 12:21:00.618559 Write leveling : PASS
9047 12:21:00.621609 RX DQS gating : PASS
9048 12:21:00.621697 RX DQ/DQS(RDDQC) : PASS
9049 12:21:00.625307 TX DQ/DQS : PASS
9050 12:21:00.628437 RX DATLAT : PASS
9051 12:21:00.628515 RX DQ/DQS(Engine): PASS
9052 12:21:00.632124 TX OE : PASS
9053 12:21:00.632211 All Pass.
9054 12:21:00.632297
9055 12:21:00.635264 CH 1, Rank 0
9056 12:21:00.635340 SW Impedance : PASS
9057 12:21:00.638418 DUTY Scan : NO K
9058 12:21:00.641884 ZQ Calibration : PASS
9059 12:21:00.642017 Jitter Meter : NO K
9060 12:21:00.645190 CBT Training : PASS
9061 12:21:00.648706 Write leveling : PASS
9062 12:21:00.648838 RX DQS gating : PASS
9063 12:21:00.651862 RX DQ/DQS(RDDQC) : PASS
9064 12:21:00.655190 TX DQ/DQS : PASS
9065 12:21:00.655275 RX DATLAT : PASS
9066 12:21:00.658553 RX DQ/DQS(Engine): PASS
9067 12:21:00.658636 TX OE : PASS
9068 12:21:00.661831 All Pass.
9069 12:21:00.661922
9070 12:21:00.662035 CH 1, Rank 1
9071 12:21:00.664993 SW Impedance : PASS
9072 12:21:00.665092 DUTY Scan : NO K
9073 12:21:00.668519 ZQ Calibration : PASS
9074 12:21:00.671850 Jitter Meter : NO K
9075 12:21:00.671934 CBT Training : PASS
9076 12:21:00.675564 Write leveling : PASS
9077 12:21:00.678653 RX DQS gating : PASS
9078 12:21:00.678769 RX DQ/DQS(RDDQC) : PASS
9079 12:21:00.681703 TX DQ/DQS : PASS
9080 12:21:00.685097 RX DATLAT : PASS
9081 12:21:00.685181 RX DQ/DQS(Engine): PASS
9082 12:21:00.688447 TX OE : PASS
9083 12:21:00.688531 All Pass.
9084 12:21:00.688596
9085 12:21:00.691605 DramC Write-DBI on
9086 12:21:00.695186 PER_BANK_REFRESH: Hybrid Mode
9087 12:21:00.695269 TX_TRACKING: ON
9088 12:21:00.704923 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9089 12:21:00.711654 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9090 12:21:00.718407 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9091 12:21:00.721817 [FAST_K] Save calibration result to emmc
9092 12:21:00.725144 sync common calibartion params.
9093 12:21:00.728561 sync cbt_mode0:1, 1:1
9094 12:21:00.731818 dram_init: ddr_geometry: 2
9095 12:21:00.731902 dram_init: ddr_geometry: 2
9096 12:21:00.734957 dram_init: ddr_geometry: 2
9097 12:21:00.738763 0:dram_rank_size:100000000
9098 12:21:00.738849 1:dram_rank_size:100000000
9099 12:21:00.745203 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9100 12:21:00.748525 DFS_SHUFFLE_HW_MODE: ON
9101 12:21:00.751674 dramc_set_vcore_voltage set vcore to 725000
9102 12:21:00.755533 Read voltage for 1600, 0
9103 12:21:00.755616 Vio18 = 0
9104 12:21:00.755681 Vcore = 725000
9105 12:21:00.758824 Vdram = 0
9106 12:21:00.758907 Vddq = 0
9107 12:21:00.758973 Vmddr = 0
9108 12:21:00.761847 switch to 3200 Mbps bootup
9109 12:21:00.761930 [DramcRunTimeConfig]
9110 12:21:00.765185 PHYPLL
9111 12:21:00.765268 DPM_CONTROL_AFTERK: ON
9112 12:21:00.768710 PER_BANK_REFRESH: ON
9113 12:21:00.771529 REFRESH_OVERHEAD_REDUCTION: ON
9114 12:21:00.771616 CMD_PICG_NEW_MODE: OFF
9115 12:21:00.774917 XRTWTW_NEW_MODE: ON
9116 12:21:00.775008 XRTRTR_NEW_MODE: ON
9117 12:21:00.778489 TX_TRACKING: ON
9118 12:21:00.778589 RDSEL_TRACKING: OFF
9119 12:21:00.781813 DQS Precalculation for DVFS: ON
9120 12:21:00.785057 RX_TRACKING: OFF
9121 12:21:00.785140 HW_GATING DBG: ON
9122 12:21:00.788145 ZQCS_ENABLE_LP4: ON
9123 12:21:00.788228 RX_PICG_NEW_MODE: ON
9124 12:21:00.791509 TX_PICG_NEW_MODE: ON
9125 12:21:00.791592 ENABLE_RX_DCM_DPHY: ON
9126 12:21:00.795219 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9127 12:21:00.798405 DUMMY_READ_FOR_TRACKING: OFF
9128 12:21:00.801911 !!! SPM_CONTROL_AFTERK: OFF
9129 12:21:00.804934 !!! SPM could not control APHY
9130 12:21:00.805018 IMPEDANCE_TRACKING: ON
9131 12:21:00.808096 TEMP_SENSOR: ON
9132 12:21:00.808179 HW_SAVE_FOR_SR: OFF
9133 12:21:00.811766 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9134 12:21:00.814887 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9135 12:21:00.818697 Read ODT Tracking: ON
9136 12:21:00.821452 Refresh Rate DeBounce: ON
9137 12:21:00.821536 DFS_NO_QUEUE_FLUSH: ON
9138 12:21:00.824953 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9139 12:21:00.828571 ENABLE_DFS_RUNTIME_MRW: OFF
9140 12:21:00.831581 DDR_RESERVE_NEW_MODE: ON
9141 12:21:00.831664 MR_CBT_SWITCH_FREQ: ON
9142 12:21:00.834634 =========================
9143 12:21:00.853799 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9144 12:21:00.857009 dram_init: ddr_geometry: 2
9145 12:21:00.875403 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9146 12:21:00.879093 dram_init: dram init end (result: 0)
9147 12:21:00.885557 DRAM-K: Full calibration passed in 24494 msecs
9148 12:21:00.888503 MRC: failed to locate region type 0.
9149 12:21:00.888589 DRAM rank0 size:0x100000000,
9150 12:21:00.892335 DRAM rank1 size=0x100000000
9151 12:21:00.901783 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9152 12:21:00.908688 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9153 12:21:00.915017 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9154 12:21:00.921909 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9155 12:21:00.924993 DRAM rank0 size:0x100000000,
9156 12:21:00.928490 DRAM rank1 size=0x100000000
9157 12:21:00.928573 CBMEM:
9158 12:21:00.931870 IMD: root @ 0xfffff000 254 entries.
9159 12:21:00.935034 IMD: root @ 0xffffec00 62 entries.
9160 12:21:00.938697 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9161 12:21:00.941847 WARNING: RO_VPD is uninitialized or empty.
9162 12:21:00.948516 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9163 12:21:00.955278 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9164 12:21:00.967983 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9165 12:21:00.979583 BS: romstage times (exec / console): total (unknown) / 23999 ms
9166 12:21:00.979692
9167 12:21:00.979786
9168 12:21:00.989804 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9169 12:21:00.992728 ARM64: Exception handlers installed.
9170 12:21:00.996313 ARM64: Testing exception
9171 12:21:00.999587 ARM64: Done test exception
9172 12:21:00.999671 Enumerating buses...
9173 12:21:01.002580 Show all devs... Before device enumeration.
9174 12:21:01.006175 Root Device: enabled 1
9175 12:21:01.009379 CPU_CLUSTER: 0: enabled 1
9176 12:21:01.009462 CPU: 00: enabled 1
9177 12:21:01.012771 Compare with tree...
9178 12:21:01.012853 Root Device: enabled 1
9179 12:21:01.015945 CPU_CLUSTER: 0: enabled 1
9180 12:21:01.019448 CPU: 00: enabled 1
9181 12:21:01.019531 Root Device scanning...
9182 12:21:01.022499 scan_static_bus for Root Device
9183 12:21:01.026097 CPU_CLUSTER: 0 enabled
9184 12:21:01.029595 scan_static_bus for Root Device done
9185 12:21:01.032911 scan_bus: bus Root Device finished in 8 msecs
9186 12:21:01.033009 done
9187 12:21:01.039065 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9188 12:21:01.042699 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9189 12:21:01.049304 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9190 12:21:01.052653 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9191 12:21:01.055822 Allocating resources...
9192 12:21:01.058978 Reading resources...
9193 12:21:01.062334 Root Device read_resources bus 0 link: 0
9194 12:21:01.062418 DRAM rank0 size:0x100000000,
9195 12:21:01.065676 DRAM rank1 size=0x100000000
9196 12:21:01.069315 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9197 12:21:01.072415 CPU: 00 missing read_resources
9198 12:21:01.078948 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9199 12:21:01.082363 Root Device read_resources bus 0 link: 0 done
9200 12:21:01.082446 Done reading resources.
9201 12:21:01.088644 Show resources in subtree (Root Device)...After reading.
9202 12:21:01.092327 Root Device child on link 0 CPU_CLUSTER: 0
9203 12:21:01.095628 CPU_CLUSTER: 0 child on link 0 CPU: 00
9204 12:21:01.105517 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9205 12:21:01.105602 CPU: 00
9206 12:21:01.108640 Root Device assign_resources, bus 0 link: 0
9207 12:21:01.112240 CPU_CLUSTER: 0 missing set_resources
9208 12:21:01.118930 Root Device assign_resources, bus 0 link: 0 done
9209 12:21:01.119014 Done setting resources.
9210 12:21:01.125603 Show resources in subtree (Root Device)...After assigning values.
9211 12:21:01.128719 Root Device child on link 0 CPU_CLUSTER: 0
9212 12:21:01.131931 CPU_CLUSTER: 0 child on link 0 CPU: 00
9213 12:21:01.142203 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9214 12:21:01.142288 CPU: 00
9215 12:21:01.145178 Done allocating resources.
9216 12:21:01.148413 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9217 12:21:01.151997 Enabling resources...
9218 12:21:01.152106 done.
9219 12:21:01.158618 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9220 12:21:01.158701 Initializing devices...
9221 12:21:01.161728 Root Device init
9222 12:21:01.161811 init hardware done!
9223 12:21:01.165199 0x00000018: ctrlr->caps
9224 12:21:01.168395 52.000 MHz: ctrlr->f_max
9225 12:21:01.168481 0.400 MHz: ctrlr->f_min
9226 12:21:01.171660 0x40ff8080: ctrlr->voltages
9227 12:21:01.175352 sclk: 390625
9228 12:21:01.175435 Bus Width = 1
9229 12:21:01.175500 sclk: 390625
9230 12:21:01.178527 Bus Width = 1
9231 12:21:01.178627 Early init status = 3
9232 12:21:01.185067 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9233 12:21:01.188177 in-header: 03 fc 00 00 01 00 00 00
9234 12:21:01.191747 in-data: 00
9235 12:21:01.194789 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9236 12:21:01.199979 in-header: 03 fd 00 00 00 00 00 00
9237 12:21:01.203195 in-data:
9238 12:21:01.206748 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9239 12:21:01.211174 in-header: 03 fc 00 00 01 00 00 00
9240 12:21:01.214333 in-data: 00
9241 12:21:01.217411 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9242 12:21:01.223267 in-header: 03 fd 00 00 00 00 00 00
9243 12:21:01.226269 in-data:
9244 12:21:01.229840 [SSUSB] Setting up USB HOST controller...
9245 12:21:01.232921 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9246 12:21:01.236206 [SSUSB] phy power-on done.
9247 12:21:01.239867 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9248 12:21:01.246542 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9249 12:21:01.249679 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9250 12:21:01.256401 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9251 12:21:01.262803 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9252 12:21:01.269877 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9253 12:21:01.276417 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9254 12:21:01.283178 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9255 12:21:01.286449 SPM: binary array size = 0x9dc
9256 12:21:01.289701 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9257 12:21:01.296423 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9258 12:21:01.302790 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9259 12:21:01.306394 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9260 12:21:01.309773 configure_display: Starting display init
9261 12:21:01.346290 anx7625_power_on_init: Init interface.
9262 12:21:01.349822 anx7625_disable_pd_protocol: Disabled PD feature.
9263 12:21:01.353067 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9264 12:21:01.380646 anx7625_start_dp_work: Secure OCM version=00
9265 12:21:01.384274 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9266 12:21:01.398797 sp_tx_get_edid_block: EDID Block = 1
9267 12:21:01.501418 Extracted contents:
9268 12:21:01.504702 header: 00 ff ff ff ff ff ff 00
9269 12:21:01.508042 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9270 12:21:01.511334 version: 01 04
9271 12:21:01.515043 basic params: 95 1f 11 78 0a
9272 12:21:01.518124 chroma info: 76 90 94 55 54 90 27 21 50 54
9273 12:21:01.521501 established: 00 00 00
9274 12:21:01.527911 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9275 12:21:01.531499 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9276 12:21:01.538263 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9277 12:21:01.544629 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9278 12:21:01.551029 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9279 12:21:01.554456 extensions: 00
9280 12:21:01.554540 checksum: fb
9281 12:21:01.554605
9282 12:21:01.557876 Manufacturer: IVO Model 57d Serial Number 0
9283 12:21:01.561167 Made week 0 of 2020
9284 12:21:01.561250 EDID version: 1.4
9285 12:21:01.564340 Digital display
9286 12:21:01.568074 6 bits per primary color channel
9287 12:21:01.568159 DisplayPort interface
9288 12:21:01.571185 Maximum image size: 31 cm x 17 cm
9289 12:21:01.574419 Gamma: 220%
9290 12:21:01.574502 Check DPMS levels
9291 12:21:01.577962 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9292 12:21:01.581093 First detailed timing is preferred timing
9293 12:21:01.584687 Established timings supported:
9294 12:21:01.588000 Standard timings supported:
9295 12:21:01.588107 Detailed timings
9296 12:21:01.594744 Hex of detail: 383680a07038204018303c0035ae10000019
9297 12:21:01.597596 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9298 12:21:01.604600 0780 0798 07c8 0820 hborder 0
9299 12:21:01.607641 0438 043b 0447 0458 vborder 0
9300 12:21:01.611029 -hsync -vsync
9301 12:21:01.611127 Did detailed timing
9302 12:21:01.614388 Hex of detail: 000000000000000000000000000000000000
9303 12:21:01.617534 Manufacturer-specified data, tag 0
9304 12:21:01.624143 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9305 12:21:01.627629 ASCII string: InfoVision
9306 12:21:01.630792 Hex of detail: 000000fe00523134304e574635205248200a
9307 12:21:01.634008 ASCII string: R140NWF5 RH
9308 12:21:01.634089 Checksum
9309 12:21:01.637527 Checksum: 0xfb (valid)
9310 12:21:01.640602 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9311 12:21:01.644160 DSI data_rate: 832800000 bps
9312 12:21:01.650831 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9313 12:21:01.653845 anx7625_parse_edid: pixelclock(138800).
9314 12:21:01.657089 hactive(1920), hsync(48), hfp(24), hbp(88)
9315 12:21:01.660660 vactive(1080), vsync(12), vfp(3), vbp(17)
9316 12:21:01.663702 anx7625_dsi_config: config dsi.
9317 12:21:01.670359 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9318 12:21:01.683339 anx7625_dsi_config: success to config DSI
9319 12:21:01.686905 anx7625_dp_start: MIPI phy setup OK.
9320 12:21:01.690433 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9321 12:21:01.693564 mtk_ddp_mode_set invalid vrefresh 60
9322 12:21:01.696676 main_disp_path_setup
9323 12:21:01.696779 ovl_layer_smi_id_en
9324 12:21:01.700355 ovl_layer_smi_id_en
9325 12:21:01.700436 ccorr_config
9326 12:21:01.700500 aal_config
9327 12:21:01.703329 gamma_config
9328 12:21:01.703410 postmask_config
9329 12:21:01.706744 dither_config
9330 12:21:01.710065 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9331 12:21:01.716555 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9332 12:21:01.720207 Root Device init finished in 555 msecs
9333 12:21:01.723438 CPU_CLUSTER: 0 init
9334 12:21:01.730178 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9335 12:21:01.733232 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9336 12:21:01.736500 APU_MBOX 0x190000b0 = 0x10001
9337 12:21:01.739972 APU_MBOX 0x190001b0 = 0x10001
9338 12:21:01.743117 APU_MBOX 0x190005b0 = 0x10001
9339 12:21:01.746728 APU_MBOX 0x190006b0 = 0x10001
9340 12:21:01.749866 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9341 12:21:01.762356 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9342 12:21:01.774946 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9343 12:21:01.781704 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9344 12:21:01.793390 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9345 12:21:01.802410 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9346 12:21:01.806027 CPU_CLUSTER: 0 init finished in 81 msecs
9347 12:21:01.809057 Devices initialized
9348 12:21:01.812296 Show all devs... After init.
9349 12:21:01.812421 Root Device: enabled 1
9350 12:21:01.816055 CPU_CLUSTER: 0: enabled 1
9351 12:21:01.819365 CPU: 00: enabled 1
9352 12:21:01.822357 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9353 12:21:01.825780 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9354 12:21:01.829046 ELOG: NV offset 0x57f000 size 0x1000
9355 12:21:01.835923 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9356 12:21:01.842143 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9357 12:21:01.845748 ELOG: Event(17) added with size 13 at 2023-08-16 12:20:55 UTC
9358 12:21:01.848882 out: cmd=0x121: 03 db 21 01 00 00 00 00
9359 12:21:01.852669 in-header: 03 3b 00 00 2c 00 00 00
9360 12:21:01.865764 in-data: 24 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9361 12:21:01.872487 ELOG: Event(A1) added with size 10 at 2023-08-16 12:20:55 UTC
9362 12:21:01.878965 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9363 12:21:01.885761 ELOG: Event(A0) added with size 9 at 2023-08-16 12:20:55 UTC
9364 12:21:01.889373 elog_add_boot_reason: Logged dev mode boot
9365 12:21:01.892378 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9366 12:21:01.896046 Finalize devices...
9367 12:21:01.896155 Devices finalized
9368 12:21:01.902392 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9369 12:21:01.905657 Writing coreboot table at 0xffe64000
9370 12:21:01.909216 0. 000000000010a000-0000000000113fff: RAMSTAGE
9371 12:21:01.912363 1. 0000000040000000-00000000400fffff: RAM
9372 12:21:01.915845 2. 0000000040100000-000000004032afff: RAMSTAGE
9373 12:21:01.922649 3. 000000004032b000-00000000545fffff: RAM
9374 12:21:01.925991 4. 0000000054600000-000000005465ffff: BL31
9375 12:21:01.928955 5. 0000000054660000-00000000ffe63fff: RAM
9376 12:21:01.932436 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9377 12:21:01.939322 7. 0000000100000000-000000023fffffff: RAM
9378 12:21:01.939405 Passing 5 GPIOs to payload:
9379 12:21:01.945579 NAME | PORT | POLARITY | VALUE
9380 12:21:01.949156 EC in RW | 0x000000aa | low | undefined
9381 12:21:01.955583 EC interrupt | 0x00000005 | low | undefined
9382 12:21:01.959129 TPM interrupt | 0x000000ab | high | undefined
9383 12:21:01.962322 SD card detect | 0x00000011 | high | undefined
9384 12:21:01.969140 speaker enable | 0x00000093 | high | undefined
9385 12:21:01.972472 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9386 12:21:01.975817 in-header: 03 f9 00 00 02 00 00 00
9387 12:21:01.975915 in-data: 02 00
9388 12:21:01.979077 ADC[4]: Raw value=901770 ID=7
9389 12:21:01.982181 ADC[3]: Raw value=212810 ID=1
9390 12:21:01.982280 RAM Code: 0x71
9391 12:21:01.985587 ADC[6]: Raw value=74502 ID=0
9392 12:21:01.989273 ADC[5]: Raw value=212072 ID=1
9393 12:21:01.989356 SKU Code: 0x1
9394 12:21:01.995953 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5b98
9395 12:21:01.999090 coreboot table: 964 bytes.
9396 12:21:02.002307 IMD ROOT 0. 0xfffff000 0x00001000
9397 12:21:02.005770 IMD SMALL 1. 0xffffe000 0x00001000
9398 12:21:02.008925 RO MCACHE 2. 0xffffc000 0x00001104
9399 12:21:02.012500 CONSOLE 3. 0xfff7c000 0x00080000
9400 12:21:02.015683 FMAP 4. 0xfff7b000 0x00000452
9401 12:21:02.018912 TIME STAMP 5. 0xfff7a000 0x00000910
9402 12:21:02.022285 VBOOT WORK 6. 0xfff66000 0x00014000
9403 12:21:02.025502 RAMOOPS 7. 0xffe66000 0x00100000
9404 12:21:02.028876 COREBOOT 8. 0xffe64000 0x00002000
9405 12:21:02.028981 IMD small region:
9406 12:21:02.032116 IMD ROOT 0. 0xffffec00 0x00000400
9407 12:21:02.035711 VPD 1. 0xffffeba0 0x0000004c
9408 12:21:02.038827 MMC STATUS 2. 0xffffeb80 0x00000004
9409 12:21:02.045714 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9410 12:21:02.045798 Probing TPM: done!
9411 12:21:02.052607 Connected to device vid:did:rid of 1ae0:0028:00
9412 12:21:02.059154 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9413 12:21:02.062308 Initialized TPM device CR50 revision 0
9414 12:21:02.066406 Checking cr50 for pending updates
9415 12:21:02.072268 Reading cr50 TPM mode
9416 12:21:02.080673 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9417 12:21:02.087457 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9418 12:21:02.127381 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9419 12:21:02.130581 Checking segment from ROM address 0x40100000
9420 12:21:02.133898 Checking segment from ROM address 0x4010001c
9421 12:21:02.140883 Loading segment from ROM address 0x40100000
9422 12:21:02.140967 code (compression=0)
9423 12:21:02.150908 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9424 12:21:02.157366 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9425 12:21:02.157451 it's not compressed!
9426 12:21:02.163894 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9427 12:21:02.167162 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9428 12:21:02.187818 Loading segment from ROM address 0x4010001c
9429 12:21:02.187902 Entry Point 0x80000000
9430 12:21:02.191002 Loaded segments
9431 12:21:02.194553 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9432 12:21:02.200984 Jumping to boot code at 0x80000000(0xffe64000)
9433 12:21:02.208029 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9434 12:21:02.214214 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9435 12:21:02.222454 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9436 12:21:02.225577 Checking segment from ROM address 0x40100000
9437 12:21:02.229203 Checking segment from ROM address 0x4010001c
9438 12:21:02.235728 Loading segment from ROM address 0x40100000
9439 12:21:02.235813 code (compression=1)
9440 12:21:02.242137 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9441 12:21:02.252356 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9442 12:21:02.252489 using LZMA
9443 12:21:02.260881 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9444 12:21:02.267343 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9445 12:21:02.270883 Loading segment from ROM address 0x4010001c
9446 12:21:02.271019 Entry Point 0x54601000
9447 12:21:02.274061 Loaded segments
9448 12:21:02.277146 NOTICE: MT8192 bl31_setup
9449 12:21:02.283995 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9450 12:21:02.287231 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9451 12:21:02.290812 WARNING: region 0:
9452 12:21:02.293907 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 12:21:02.294031 WARNING: region 1:
9454 12:21:02.300780 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9455 12:21:02.303996 WARNING: region 2:
9456 12:21:02.307467 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9457 12:21:02.310804 WARNING: region 3:
9458 12:21:02.314359 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9459 12:21:02.317731 WARNING: region 4:
9460 12:21:02.323987 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9461 12:21:02.324119 WARNING: region 5:
9462 12:21:02.327293 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 12:21:02.330799 WARNING: region 6:
9464 12:21:02.333911 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 12:21:02.337551 WARNING: region 7:
9466 12:21:02.340979 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 12:21:02.347269 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9468 12:21:02.350838 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9469 12:21:02.354248 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9470 12:21:02.360689 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9471 12:21:02.364128 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9472 12:21:02.367181 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9473 12:21:02.374089 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9474 12:21:02.377736 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9475 12:21:02.383930 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9476 12:21:02.387516 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9477 12:21:02.390920 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9478 12:21:02.397551 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9479 12:21:02.401114 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9480 12:21:02.404419 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9481 12:21:02.411121 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9482 12:21:02.414337 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9483 12:21:02.417561 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9484 12:21:02.424429 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9485 12:21:02.427618 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9486 12:21:02.431244 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9487 12:21:02.438032 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9488 12:21:02.441214 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9489 12:21:02.447910 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9490 12:21:02.451217 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9491 12:21:02.454662 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9492 12:21:02.461148 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9493 12:21:02.464485 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9494 12:21:02.471313 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9495 12:21:02.474828 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9496 12:21:02.477921 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9497 12:21:02.484895 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9498 12:21:02.488031 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9499 12:21:02.491355 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9500 12:21:02.498140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9501 12:21:02.501442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9502 12:21:02.504954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9503 12:21:02.508111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9504 12:21:02.514567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9505 12:21:02.518227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9506 12:21:02.521402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9507 12:21:02.524890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9508 12:21:02.531180 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9509 12:21:02.534775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9510 12:21:02.537979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9511 12:21:02.541130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9512 12:21:02.548190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9513 12:21:02.551317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9514 12:21:02.554872 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9515 12:21:02.561510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9516 12:21:02.564739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9517 12:21:02.568160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9518 12:21:02.574963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9519 12:21:02.578058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9520 12:21:02.584714 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9521 12:21:02.588568 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9522 12:21:02.591512 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9523 12:21:02.598370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9524 12:21:02.601785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9525 12:21:02.608096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9526 12:21:02.611720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9527 12:21:02.618720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9528 12:21:02.621813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9529 12:21:02.625133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9530 12:21:02.631629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9531 12:21:02.635296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9532 12:21:02.641725 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9533 12:21:02.644929 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9534 12:21:02.651689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9535 12:21:02.655210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9536 12:21:02.658628 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9537 12:21:02.665176 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9538 12:21:02.668547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9539 12:21:02.675084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9540 12:21:02.678617 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9541 12:21:02.685094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9542 12:21:02.688612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9543 12:21:02.691855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9544 12:21:02.698513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9545 12:21:02.702157 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9546 12:21:02.708604 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9547 12:21:02.711800 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9548 12:21:02.718674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9549 12:21:02.721797 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9550 12:21:02.725039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9551 12:21:02.732134 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9552 12:21:02.735207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9553 12:21:02.741919 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9554 12:21:02.745198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9555 12:21:02.751918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9556 12:21:02.755351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9557 12:21:02.758305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9558 12:21:02.765034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9559 12:21:02.768589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9560 12:21:02.775350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9561 12:21:02.778551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9562 12:21:02.785526 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9563 12:21:02.788968 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9564 12:21:02.792065 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9565 12:21:02.795280 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9566 12:21:02.802283 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9567 12:21:02.805546 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9568 12:21:02.808553 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9569 12:21:02.815286 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9570 12:21:02.818852 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9571 12:21:02.825366 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9572 12:21:02.828533 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9573 12:21:02.832143 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9574 12:21:02.838583 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9575 12:21:02.842184 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9576 12:21:02.845318 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9577 12:21:02.852144 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9578 12:21:02.855367 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9579 12:21:02.862013 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9580 12:21:02.865884 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9581 12:21:02.868708 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9582 12:21:02.875725 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9583 12:21:02.878683 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9584 12:21:02.882136 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9585 12:21:02.888744 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9586 12:21:02.892203 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9587 12:21:02.895826 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9588 12:21:02.898802 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9589 12:21:02.902461 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9590 12:21:02.908730 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9591 12:21:02.912354 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9592 12:21:02.918987 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9593 12:21:02.922105 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9594 12:21:02.925310 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9595 12:21:02.932001 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9596 12:21:02.935647 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9597 12:21:02.939065 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9598 12:21:02.945672 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9599 12:21:02.948883 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9600 12:21:02.955312 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9601 12:21:02.959023 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9602 12:21:02.965760 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9603 12:21:02.968893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9604 12:21:02.972039 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9605 12:21:02.979114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9606 12:21:02.982022 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9607 12:21:02.985486 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9608 12:21:02.992180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9609 12:21:02.995611 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9610 12:21:03.002291 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9611 12:21:03.005463 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9612 12:21:03.008779 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9613 12:21:03.015789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9614 12:21:03.019289 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9615 12:21:03.022366 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9616 12:21:03.028957 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9617 12:21:03.032551 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9618 12:21:03.038947 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9619 12:21:03.042578 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9620 12:21:03.045691 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9621 12:21:03.052447 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9622 12:21:03.055611 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9623 12:21:03.059236 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9624 12:21:03.065867 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9625 12:21:03.069077 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9626 12:21:03.075824 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9627 12:21:03.078976 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9628 12:21:03.082534 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9629 12:21:03.088888 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9630 12:21:03.092357 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9631 12:21:03.099161 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9632 12:21:03.102159 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9633 12:21:03.105622 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9634 12:21:03.112576 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9635 12:21:03.115592 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9636 12:21:03.122225 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9637 12:21:03.125949 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9638 12:21:03.128967 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9639 12:21:03.135788 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9640 12:21:03.138928 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9641 12:21:03.142541 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9642 12:21:03.148975 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9643 12:21:03.151980 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9644 12:21:03.158659 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9645 12:21:03.162321 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9646 12:21:03.165513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9647 12:21:03.172126 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9648 12:21:03.175206 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9649 12:21:03.181978 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9650 12:21:03.185489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9651 12:21:03.188657 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9652 12:21:03.195530 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9653 12:21:03.198484 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9654 12:21:03.205416 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9655 12:21:03.208745 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9656 12:21:03.211986 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9657 12:21:03.218879 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9658 12:21:03.222018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9659 12:21:03.228561 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9660 12:21:03.231814 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9661 12:21:03.235367 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9662 12:21:03.241618 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9663 12:21:03.245273 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9664 12:21:03.251842 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9665 12:21:03.255308 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9666 12:21:03.261656 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9667 12:21:03.265304 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9668 12:21:03.268513 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9669 12:21:03.275162 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9670 12:21:03.278431 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9671 12:21:03.285027 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9672 12:21:03.288283 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9673 12:21:03.291989 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9674 12:21:03.298476 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9675 12:21:03.301854 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9676 12:21:03.308445 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9677 12:21:03.311750 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9678 12:21:03.315358 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9679 12:21:03.321855 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9680 12:21:03.325081 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9681 12:21:03.331711 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9682 12:21:03.335148 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9683 12:21:03.341894 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9684 12:21:03.345056 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9685 12:21:03.348215 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9686 12:21:03.354980 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9687 12:21:03.358194 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9688 12:21:03.365066 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9689 12:21:03.368354 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9690 12:21:03.371547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9691 12:21:03.378141 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9692 12:21:03.381348 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9693 12:21:03.388055 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9694 12:21:03.391774 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9695 12:21:03.398389 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9696 12:21:03.401584 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9697 12:21:03.404731 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9698 12:21:03.408416 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9699 12:21:03.411645 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9700 12:21:03.417875 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9701 12:21:03.421462 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9702 12:21:03.424684 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9703 12:21:03.431518 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9704 12:21:03.434978 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9705 12:21:03.438354 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9706 12:21:03.444640 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9707 12:21:03.448368 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9708 12:21:03.454810 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9709 12:21:03.458456 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9710 12:21:03.461319 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9711 12:21:03.468124 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9712 12:21:03.471298 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9713 12:21:03.474681 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9714 12:21:03.481487 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9715 12:21:03.484467 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9716 12:21:03.488146 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9717 12:21:03.494830 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9718 12:21:03.497963 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9719 12:21:03.504332 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9720 12:21:03.507998 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9721 12:21:03.511383 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9722 12:21:03.518149 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9723 12:21:03.521535 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9724 12:21:03.524353 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9725 12:21:03.531028 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9726 12:21:03.534499 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9727 12:21:03.537877 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9728 12:21:03.544505 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9729 12:21:03.547611 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9730 12:21:03.551263 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9731 12:21:03.557612 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9732 12:21:03.560842 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9733 12:21:03.567520 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9734 12:21:03.571034 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9735 12:21:03.574360 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9736 12:21:03.581031 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9737 12:21:03.584249 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9738 12:21:03.587358 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9739 12:21:03.590873 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9740 12:21:03.594128 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9741 12:21:03.600940 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9742 12:21:03.604052 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9743 12:21:03.607725 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9744 12:21:03.611158 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9745 12:21:03.617632 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9746 12:21:03.620946 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9747 12:21:03.624290 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9748 12:21:03.630877 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9749 12:21:03.634579 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9750 12:21:03.637624 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9751 12:21:03.644130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9752 12:21:03.647504 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9753 12:21:03.654106 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9754 12:21:03.657672 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9755 12:21:03.660767 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9756 12:21:03.667540 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9757 12:21:03.670691 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9758 12:21:03.677455 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9759 12:21:03.680572 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9760 12:21:03.684071 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9761 12:21:03.690932 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9762 12:21:03.694084 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9763 12:21:03.700681 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9764 12:21:03.703885 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9765 12:21:03.707581 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9766 12:21:03.714017 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9767 12:21:03.717209 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9768 12:21:03.723818 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9769 12:21:03.727755 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9770 12:21:03.733796 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9771 12:21:03.737367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9772 12:21:03.740402 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9773 12:21:03.747015 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9774 12:21:03.750385 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9775 12:21:03.757074 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9776 12:21:03.761013 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9777 12:21:03.763894 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9778 12:21:03.770345 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9779 12:21:03.774187 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9780 12:21:03.777488 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9781 12:21:03.784155 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9782 12:21:03.787411 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9783 12:21:03.794177 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9784 12:21:03.797238 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9785 12:21:03.804161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9786 12:21:03.807262 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9787 12:21:03.810832 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9788 12:21:03.817409 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9789 12:21:03.820511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9790 12:21:03.827262 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9791 12:21:03.830495 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9792 12:21:03.833820 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9793 12:21:03.840927 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9794 12:21:03.844150 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9795 12:21:03.850754 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9796 12:21:03.854175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9797 12:21:03.857177 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9798 12:21:03.863929 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9799 12:21:03.867504 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9800 12:21:03.873787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9801 12:21:03.877175 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9802 12:21:03.880679 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9803 12:21:03.887243 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9804 12:21:03.890779 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9805 12:21:03.897048 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9806 12:21:03.900537 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9807 12:21:03.904093 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9808 12:21:03.910766 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9809 12:21:03.913839 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9810 12:21:03.920504 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9811 12:21:03.923822 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9812 12:21:03.927589 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9813 12:21:03.933819 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9814 12:21:03.937512 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9815 12:21:03.943645 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9816 12:21:03.947137 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9817 12:21:03.950353 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9818 12:21:03.957334 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9819 12:21:03.960498 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9820 12:21:03.966951 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9821 12:21:03.970467 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9822 12:21:03.977230 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9823 12:21:03.980284 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9824 12:21:03.983738 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9825 12:21:03.990097 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9826 12:21:03.993751 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9827 12:21:04.000528 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9828 12:21:04.003465 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9829 12:21:04.010044 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9830 12:21:04.013249 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9831 12:21:04.016772 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9832 12:21:04.023567 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9833 12:21:04.026723 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9834 12:21:04.033391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9835 12:21:04.036515 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9836 12:21:04.043267 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9837 12:21:04.046721 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9838 12:21:04.050055 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9839 12:21:04.056837 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9840 12:21:04.060094 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9841 12:21:04.066952 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9842 12:21:04.070146 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9843 12:21:04.076667 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9844 12:21:04.080207 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9845 12:21:04.083281 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9846 12:21:04.090280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9847 12:21:04.093504 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9848 12:21:04.100132 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9849 12:21:04.103288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9850 12:21:04.109969 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9851 12:21:04.113196 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9852 12:21:04.116723 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9853 12:21:04.123469 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9854 12:21:04.126491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9855 12:21:04.133240 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9856 12:21:04.136896 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9857 12:21:04.143774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9858 12:21:04.146882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9859 12:21:04.153272 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9860 12:21:04.156714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9861 12:21:04.160323 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9862 12:21:04.166567 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9863 12:21:04.170086 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9864 12:21:04.176527 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9865 12:21:04.180208 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9866 12:21:04.186286 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9867 12:21:04.190003 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9868 12:21:04.193114 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9869 12:21:04.200027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9870 12:21:04.203141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9871 12:21:04.206611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9872 12:21:04.213403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9873 12:21:04.216731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9874 12:21:04.223459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9875 12:21:04.226546 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9876 12:21:04.233269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9877 12:21:04.236908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9878 12:21:04.243177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9879 12:21:04.246506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9880 12:21:04.253058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9881 12:21:04.256508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9882 12:21:04.262924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9883 12:21:04.266522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9884 12:21:04.272864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9885 12:21:04.276953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9886 12:21:04.282730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9887 12:21:04.286250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9888 12:21:04.292980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9889 12:21:04.296132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9890 12:21:04.303040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9891 12:21:04.306252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9892 12:21:04.312914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9893 12:21:04.316543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9894 12:21:04.322741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9895 12:21:04.326355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9896 12:21:04.332601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9897 12:21:04.336220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9898 12:21:04.342890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9899 12:21:04.346399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9900 12:21:04.352913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9901 12:21:04.355881 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9902 12:21:04.359292 INFO: [APUAPC] vio 0
9903 12:21:04.362771 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9904 12:21:04.366024 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9905 12:21:04.369539 INFO: [APUAPC] D0_APC_0: 0x400510
9906 12:21:04.372630 INFO: [APUAPC] D0_APC_1: 0x0
9907 12:21:04.375714 INFO: [APUAPC] D0_APC_2: 0x1540
9908 12:21:04.379374 INFO: [APUAPC] D0_APC_3: 0x0
9909 12:21:04.382621 INFO: [APUAPC] D1_APC_0: 0xffffffff
9910 12:21:04.385940 INFO: [APUAPC] D1_APC_1: 0xffffffff
9911 12:21:04.389013 INFO: [APUAPC] D1_APC_2: 0x3fffff
9912 12:21:04.392422 INFO: [APUAPC] D1_APC_3: 0x0
9913 12:21:04.395597 INFO: [APUAPC] D2_APC_0: 0xffffffff
9914 12:21:04.398854 INFO: [APUAPC] D2_APC_1: 0xffffffff
9915 12:21:04.402330 INFO: [APUAPC] D2_APC_2: 0x3fffff
9916 12:21:04.405523 INFO: [APUAPC] D2_APC_3: 0x0
9917 12:21:04.409070 INFO: [APUAPC] D3_APC_0: 0xffffffff
9918 12:21:04.412218 INFO: [APUAPC] D3_APC_1: 0xffffffff
9919 12:21:04.416071 INFO: [APUAPC] D3_APC_2: 0x3fffff
9920 12:21:04.419031 INFO: [APUAPC] D3_APC_3: 0x0
9921 12:21:04.422243 INFO: [APUAPC] D4_APC_0: 0xffffffff
9922 12:21:04.425672 INFO: [APUAPC] D4_APC_1: 0xffffffff
9923 12:21:04.428777 INFO: [APUAPC] D4_APC_2: 0x3fffff
9924 12:21:04.432444 INFO: [APUAPC] D4_APC_3: 0x0
9925 12:21:04.435556 INFO: [APUAPC] D5_APC_0: 0xffffffff
9926 12:21:04.438738 INFO: [APUAPC] D5_APC_1: 0xffffffff
9927 12:21:04.442356 INFO: [APUAPC] D5_APC_2: 0x3fffff
9928 12:21:04.445555 INFO: [APUAPC] D5_APC_3: 0x0
9929 12:21:04.448732 INFO: [APUAPC] D6_APC_0: 0xffffffff
9930 12:21:04.452035 INFO: [APUAPC] D6_APC_1: 0xffffffff
9931 12:21:04.455610 INFO: [APUAPC] D6_APC_2: 0x3fffff
9932 12:21:04.458847 INFO: [APUAPC] D6_APC_3: 0x0
9933 12:21:04.462539 INFO: [APUAPC] D7_APC_0: 0xffffffff
9934 12:21:04.465345 INFO: [APUAPC] D7_APC_1: 0xffffffff
9935 12:21:04.468822 INFO: [APUAPC] D7_APC_2: 0x3fffff
9936 12:21:04.472015 INFO: [APUAPC] D7_APC_3: 0x0
9937 12:21:04.475471 INFO: [APUAPC] D8_APC_0: 0xffffffff
9938 12:21:04.478685 INFO: [APUAPC] D8_APC_1: 0xffffffff
9939 12:21:04.481992 INFO: [APUAPC] D8_APC_2: 0x3fffff
9940 12:21:04.482075 INFO: [APUAPC] D8_APC_3: 0x0
9941 12:21:04.488584 INFO: [APUAPC] D9_APC_0: 0xffffffff
9942 12:21:04.492140 INFO: [APUAPC] D9_APC_1: 0xffffffff
9943 12:21:04.495477 INFO: [APUAPC] D9_APC_2: 0x3fffff
9944 12:21:04.495559 INFO: [APUAPC] D9_APC_3: 0x0
9945 12:21:04.498984 INFO: [APUAPC] D10_APC_0: 0xffffffff
9946 12:21:04.505608 INFO: [APUAPC] D10_APC_1: 0xffffffff
9947 12:21:04.508989 INFO: [APUAPC] D10_APC_2: 0x3fffff
9948 12:21:04.509074 INFO: [APUAPC] D10_APC_3: 0x0
9949 12:21:04.512255 INFO: [APUAPC] D11_APC_0: 0xffffffff
9950 12:21:04.518793 INFO: [APUAPC] D11_APC_1: 0xffffffff
9951 12:21:04.521950 INFO: [APUAPC] D11_APC_2: 0x3fffff
9952 12:21:04.522077 INFO: [APUAPC] D11_APC_3: 0x0
9953 12:21:04.525658 INFO: [APUAPC] D12_APC_0: 0xffffffff
9954 12:21:04.531908 INFO: [APUAPC] D12_APC_1: 0xffffffff
9955 12:21:04.535597 INFO: [APUAPC] D12_APC_2: 0x3fffff
9956 12:21:04.535725 INFO: [APUAPC] D12_APC_3: 0x0
9957 12:21:04.538720 INFO: [APUAPC] D13_APC_0: 0xffffffff
9958 12:21:04.545164 INFO: [APUAPC] D13_APC_1: 0xffffffff
9959 12:21:04.548920 INFO: [APUAPC] D13_APC_2: 0x3fffff
9960 12:21:04.549004 INFO: [APUAPC] D13_APC_3: 0x0
9961 12:21:04.555190 INFO: [APUAPC] D14_APC_0: 0xffffffff
9962 12:21:04.558810 INFO: [APUAPC] D14_APC_1: 0xffffffff
9963 12:21:04.562183 INFO: [APUAPC] D14_APC_2: 0x3fffff
9964 12:21:04.562269 INFO: [APUAPC] D14_APC_3: 0x0
9965 12:21:04.568633 INFO: [APUAPC] D15_APC_0: 0xffffffff
9966 12:21:04.572084 INFO: [APUAPC] D15_APC_1: 0xffffffff
9967 12:21:04.575290 INFO: [APUAPC] D15_APC_2: 0x3fffff
9968 12:21:04.575374 INFO: [APUAPC] D15_APC_3: 0x0
9969 12:21:04.578483 INFO: [APUAPC] APC_CON: 0x4
9970 12:21:04.582024 INFO: [NOCDAPC] D0_APC_0: 0x0
9971 12:21:04.585409 INFO: [NOCDAPC] D0_APC_1: 0x0
9972 12:21:04.588670 INFO: [NOCDAPC] D1_APC_0: 0x0
9973 12:21:04.591926 INFO: [NOCDAPC] D1_APC_1: 0xfff
9974 12:21:04.595415 INFO: [NOCDAPC] D2_APC_0: 0x0
9975 12:21:04.598680 INFO: [NOCDAPC] D2_APC_1: 0xfff
9976 12:21:04.602176 INFO: [NOCDAPC] D3_APC_0: 0x0
9977 12:21:04.602260 INFO: [NOCDAPC] D3_APC_1: 0xfff
9978 12:21:04.605555 INFO: [NOCDAPC] D4_APC_0: 0x0
9979 12:21:04.608763 INFO: [NOCDAPC] D4_APC_1: 0xfff
9980 12:21:04.612188 INFO: [NOCDAPC] D5_APC_0: 0x0
9981 12:21:04.615404 INFO: [NOCDAPC] D5_APC_1: 0xfff
9982 12:21:04.618702 INFO: [NOCDAPC] D6_APC_0: 0x0
9983 12:21:04.622133 INFO: [NOCDAPC] D6_APC_1: 0xfff
9984 12:21:04.625098 INFO: [NOCDAPC] D7_APC_0: 0x0
9985 12:21:04.628730 INFO: [NOCDAPC] D7_APC_1: 0xfff
9986 12:21:04.631880 INFO: [NOCDAPC] D8_APC_0: 0x0
9987 12:21:04.635152 INFO: [NOCDAPC] D8_APC_1: 0xfff
9988 12:21:04.635258 INFO: [NOCDAPC] D9_APC_0: 0x0
9989 12:21:04.638722 INFO: [NOCDAPC] D9_APC_1: 0xfff
9990 12:21:04.642039 INFO: [NOCDAPC] D10_APC_0: 0x0
9991 12:21:04.645556 INFO: [NOCDAPC] D10_APC_1: 0xfff
9992 12:21:04.648832 INFO: [NOCDAPC] D11_APC_0: 0x0
9993 12:21:04.651978 INFO: [NOCDAPC] D11_APC_1: 0xfff
9994 12:21:04.655129 INFO: [NOCDAPC] D12_APC_0: 0x0
9995 12:21:04.658783 INFO: [NOCDAPC] D12_APC_1: 0xfff
9996 12:21:04.662004 INFO: [NOCDAPC] D13_APC_0: 0x0
9997 12:21:04.665253 INFO: [NOCDAPC] D13_APC_1: 0xfff
9998 12:21:04.668315 INFO: [NOCDAPC] D14_APC_0: 0x0
9999 12:21:04.671763 INFO: [NOCDAPC] D14_APC_1: 0xfff
10000 12:21:04.675169 INFO: [NOCDAPC] D15_APC_0: 0x0
10001 12:21:04.678407 INFO: [NOCDAPC] D15_APC_1: 0xfff
10002 12:21:04.678505 INFO: [NOCDAPC] APC_CON: 0x4
10003 12:21:04.681690 INFO: [APUAPC] set_apusys_apc done
10004 12:21:04.685371 INFO: [DEVAPC] devapc_init done
10005 12:21:04.691751 INFO: GICv3 without legacy support detected.
10006 12:21:04.695340 INFO: ARM GICv3 driver initialized in EL3
10007 12:21:04.698658 INFO: Maximum SPI INTID supported: 639
10008 12:21:04.701635 INFO: BL31: Initializing runtime services
10009 12:21:04.708209 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10010 12:21:04.711778 INFO: SPM: enable CPC mode
10011 12:21:04.714791 INFO: mcdi ready for mcusys-off-idle and system suspend
10012 12:21:04.721662 INFO: BL31: Preparing for EL3 exit to normal world
10013 12:21:04.725043 INFO: Entry point address = 0x80000000
10014 12:21:04.725127 INFO: SPSR = 0x8
10015 12:21:04.731763
10016 12:21:04.731847
10017 12:21:04.731913
10018 12:21:04.735173 Starting depthcharge on Spherion...
10019 12:21:04.735271
10020 12:21:04.735338 Wipe memory regions:
10021 12:21:04.735401
10022 12:21:04.736027 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10023 12:21:04.736127 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10024 12:21:04.736207 Setting prompt string to ['asurada:']
10025 12:21:04.736283 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10026 12:21:04.738347 [0x00000040000000, 0x00000054600000)
10027 12:21:04.860895
10028 12:21:04.861024 [0x00000054660000, 0x00000080000000)
10029 12:21:05.121474
10030 12:21:05.121633 [0x000000821a7280, 0x000000ffe64000)
10031 12:21:05.866610
10032 12:21:05.866765 [0x00000100000000, 0x00000240000000)
10033 12:21:07.756701
10034 12:21:07.759793 Initializing XHCI USB controller at 0x11200000.
10035 12:21:08.797570
10036 12:21:08.800993 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10037 12:21:08.801136
10038 12:21:08.801262
10039 12:21:08.801326
10040 12:21:08.801606 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 12:21:08.901957 asurada: tftpboot 192.168.201.1 11299277/tftp-deploy-4sizsku6/kernel/image.itb 11299277/tftp-deploy-4sizsku6/kernel/cmdline
10043 12:21:08.902110 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10044 12:21:08.902234 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10045 12:21:08.906696 tftpboot 192.168.201.1 11299277/tftp-deploy-4sizsku6/kernel/image.ittp-deploy-4sizsku6/kernel/cmdline
10046 12:21:08.906782
10047 12:21:08.906847 Waiting for link
10048 12:21:09.066805
10049 12:21:09.066957 R8152: Initializing
10050 12:21:09.067028
10051 12:21:09.070435 Version 9 (ocp_data = 6010)
10052 12:21:09.070506
10053 12:21:09.073594 R8152: Done initializing
10054 12:21:09.073677
10055 12:21:09.073742 Adding net device
10056 12:21:11.019327
10057 12:21:11.019485 done.
10058 12:21:11.019556
10059 12:21:11.019619 MAC: 00:e0:4c:72:2d:d6
10060 12:21:11.019684
10061 12:21:11.022374 Sending DHCP discover... done.
10062 12:21:11.022478
10063 12:21:11.025901 Waiting for reply... done.
10064 12:21:11.026005
10065 12:21:11.029097 Sending DHCP request... done.
10066 12:21:11.029179
10067 12:21:11.029244 Waiting for reply... done.
10068 12:21:11.029306
10069 12:21:11.032300 My ip is 192.168.201.21
10070 12:21:11.032404
10071 12:21:11.035924 The DHCP server ip is 192.168.201.1
10072 12:21:11.035995
10073 12:21:11.039378 TFTP server IP predefined by user: 192.168.201.1
10074 12:21:11.039474
10075 12:21:11.045655 Bootfile predefined by user: 11299277/tftp-deploy-4sizsku6/kernel/image.itb
10076 12:21:11.045753
10077 12:21:11.049074 Sending tftp read request... done.
10078 12:21:11.049149
10079 12:21:11.052264 Waiting for the transfer...
10080 12:21:11.052366
10081 12:21:11.321238 00000000 ################################################################
10082 12:21:11.321389
10083 12:21:11.587519 00080000 ################################################################
10084 12:21:11.587667
10085 12:21:11.861105 00100000 ################################################################
10086 12:21:11.861257
10087 12:21:12.126061 00180000 ################################################################
10088 12:21:12.126211
10089 12:21:12.396646 00200000 ################################################################
10090 12:21:12.396832
10091 12:21:12.663353 00280000 ################################################################
10092 12:21:12.663524
10093 12:21:12.932717 00300000 ################################################################
10094 12:21:12.932941
10095 12:21:13.221841 00380000 ################################################################
10096 12:21:13.222022
10097 12:21:13.517686 00400000 ################################################################
10098 12:21:13.517868
10099 12:21:13.792286 00480000 ################################################################
10100 12:21:13.792446
10101 12:21:14.085874 00500000 ################################################################
10102 12:21:14.086014
10103 12:21:14.356233 00580000 ################################################################
10104 12:21:14.356409
10105 12:21:14.633149 00600000 ################################################################
10106 12:21:14.633309
10107 12:21:14.906726 00680000 ################################################################
10108 12:21:14.906877
10109 12:21:15.170602 00700000 ################################################################
10110 12:21:15.170769
10111 12:21:15.459859 00780000 ################################################################
10112 12:21:15.460011
10113 12:21:15.749572 00800000 ################################################################
10114 12:21:15.749779
10115 12:21:16.030403 00880000 ################################################################
10116 12:21:16.030618
10117 12:21:16.301739 00900000 ################################################################
10118 12:21:16.301891
10119 12:21:16.580606 00980000 ################################################################
10120 12:21:16.580847
10121 12:21:16.848322 00a00000 ################################################################
10122 12:21:16.848516
10123 12:21:17.115238 00a80000 ################################################################
10124 12:21:17.115374
10125 12:21:17.372900 00b00000 ################################################################
10126 12:21:17.373092
10127 12:21:17.632958 00b80000 ################################################################
10128 12:21:17.633111
10129 12:21:17.905589 00c00000 ################################################################
10130 12:21:17.905727
10131 12:21:18.193773 00c80000 ################################################################
10132 12:21:18.193966
10133 12:21:18.465509 00d00000 ################################################################
10134 12:21:18.465643
10135 12:21:18.749289 00d80000 ################################################################
10136 12:21:18.749468
10137 12:21:19.014142 00e00000 ################################################################
10138 12:21:19.014276
10139 12:21:19.295359 00e80000 ################################################################
10140 12:21:19.295492
10141 12:21:19.564597 00f00000 ################################################################
10142 12:21:19.564741
10143 12:21:19.844651 00f80000 ################################################################
10144 12:21:19.844848
10145 12:21:20.125539 01000000 ################################################################
10146 12:21:20.125683
10147 12:21:20.398314 01080000 ################################################################
10148 12:21:20.398449
10149 12:21:20.656299 01100000 ################################################################
10150 12:21:20.656432
10151 12:21:20.929621 01180000 ################################################################
10152 12:21:20.929756
10153 12:21:21.212999 01200000 ################################################################
10154 12:21:21.213139
10155 12:21:21.488243 01280000 ################################################################
10156 12:21:21.488448
10157 12:21:21.767387 01300000 ################################################################
10158 12:21:21.767638
10159 12:21:22.043069 01380000 ################################################################
10160 12:21:22.043220
10161 12:21:22.322867 01400000 ################################################################
10162 12:21:22.323006
10163 12:21:22.608087 01480000 ################################################################
10164 12:21:22.608285
10165 12:21:22.878228 01500000 ################################################################
10166 12:21:22.878438
10167 12:21:23.129468 01580000 ################################################################
10168 12:21:23.129659
10169 12:21:23.396789 01600000 ################################################################
10170 12:21:23.396948
10171 12:21:23.680649 01680000 ################################################################
10172 12:21:23.680852
10173 12:21:23.963305 01700000 ################################################################
10174 12:21:23.963514
10175 12:21:24.258459 01780000 ################################################################
10176 12:21:24.258656
10177 12:21:24.538758 01800000 ################################################################
10178 12:21:24.538964
10179 12:21:24.834653 01880000 ################################################################
10180 12:21:24.834800
10181 12:21:25.124639 01900000 ################################################################
10182 12:21:25.124812
10183 12:21:25.415280 01980000 ################################################################
10184 12:21:25.415419
10185 12:21:25.707194 01a00000 ################################################################
10186 12:21:25.707332
10187 12:21:25.999060 01a80000 ################################################################
10188 12:21:25.999195
10189 12:21:26.290035 01b00000 ################################################################
10190 12:21:26.290239
10191 12:21:26.583134 01b80000 ################################################################
10192 12:21:26.583330
10193 12:21:26.872313 01c00000 ################################################################
10194 12:21:26.872456
10195 12:21:27.167718 01c80000 ################################################################
10196 12:21:27.167919
10197 12:21:27.456844 01d00000 ################################################################
10198 12:21:27.456986
10199 12:21:27.744448 01d80000 ################################################################
10200 12:21:27.744593
10201 12:21:28.022345 01e00000 ################################################################
10202 12:21:28.022490
10203 12:21:28.304389 01e80000 ################################################################
10204 12:21:28.304587
10205 12:21:28.592943 01f00000 ################################################################
10206 12:21:28.593075
10207 12:21:28.886240 01f80000 ################################################################
10208 12:21:28.886441
10209 12:21:29.175778 02000000 ################################################################
10210 12:21:29.175959
10211 12:21:29.444536 02080000 ################################################################
10212 12:21:29.444671
10213 12:21:29.724851 02100000 ################################################################
10214 12:21:29.724992
10215 12:21:29.994910 02180000 ################################################################
10216 12:21:29.995048
10217 12:21:30.251618 02200000 ################################################################
10218 12:21:30.251779
10219 12:21:30.525779 02280000 ################################################################
10220 12:21:30.525969
10221 12:21:30.808824 02300000 ################################################################
10222 12:21:30.809023
10223 12:21:31.085569 02380000 ################################################################
10224 12:21:31.085708
10225 12:21:31.359791 02400000 ################################################################
10226 12:21:31.359929
10227 12:21:31.641761 02480000 ################################################################
10228 12:21:31.641898
10229 12:21:31.910000 02500000 ################################################################
10230 12:21:31.910212
10231 12:21:32.173596 02580000 ################################################################
10232 12:21:32.173733
10233 12:21:32.452813 02600000 ################################################################
10234 12:21:32.452955
10235 12:21:32.741044 02680000 ################################################################
10236 12:21:32.741251
10237 12:21:33.030497 02700000 ################################################################
10238 12:21:33.030637
10239 12:21:33.316041 02780000 ################################################################
10240 12:21:33.316230
10241 12:21:33.595922 02800000 ################################################################
10242 12:21:33.596062
10243 12:21:33.882978 02880000 ################################################################
10244 12:21:33.883145
10245 12:21:34.174506 02900000 ################################################################
10246 12:21:34.174649
10247 12:21:34.466995 02980000 ################################################################
10248 12:21:34.467130
10249 12:21:34.750904 02a00000 ################################################################
10250 12:21:34.751043
10251 12:21:35.037999 02a80000 ################################################################
10252 12:21:35.038138
10253 12:21:35.313558 02b00000 ################################################################
10254 12:21:35.313757
10255 12:21:35.602367 02b80000 ################################################################
10256 12:21:35.602571
10257 12:21:35.896423 02c00000 ################################################################
10258 12:21:35.896563
10259 12:21:36.193738 02c80000 ################################################################
10260 12:21:36.193902
10261 12:21:36.482313 02d00000 ################################################################
10262 12:21:36.482448
10263 12:21:36.773198 02d80000 ################################################################
10264 12:21:36.773378
10265 12:21:37.056090 02e00000 ################################################################
10266 12:21:37.056232
10267 12:21:37.348705 02e80000 ################################################################
10268 12:21:37.348930
10269 12:21:37.626060 02f00000 ################################################################
10270 12:21:37.626206
10271 12:21:37.914290 02f80000 ################################################################
10272 12:21:37.914426
10273 12:21:37.967902 03000000 ############# done.
10274 12:21:37.968033
10275 12:21:37.971551 The bootfile was 50431038 bytes long.
10276 12:21:37.971676
10277 12:21:37.974739 Sending tftp read request... done.
10278 12:21:37.974854
10279 12:21:37.978197 Waiting for the transfer...
10280 12:21:37.978316
10281 12:21:37.978433 00000000 # done.
10282 12:21:37.978550
10283 12:21:37.984527 Command line loaded dynamically from TFTP file: 11299277/tftp-deploy-4sizsku6/kernel/cmdline
10284 12:21:37.988094
10285 12:21:38.001188 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10286 12:21:38.001318
10287 12:21:38.001432 Loading FIT.
10288 12:21:38.001540
10289 12:21:38.004702 Image ramdisk-1 has 39341352 bytes.
10290 12:21:38.004829
10291 12:21:38.007840 Image fdt-1 has 47278 bytes.
10292 12:21:38.007965
10293 12:21:38.011295 Image kernel-1 has 11040376 bytes.
10294 12:21:38.011418
10295 12:21:38.017882 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10296 12:21:38.018007
10297 12:21:38.037753 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10298 12:21:38.037885
10299 12:21:38.041280 Choosing best match conf-1 for compat google,spherion-rev2.
10300 12:21:38.045731
10301 12:21:38.050610 Connected to device vid:did:rid of 1ae0:0028:00
10302 12:21:38.058381
10303 12:21:38.062250 tpm_get_response: command 0x17b, return code 0x0
10304 12:21:38.062375
10305 12:21:38.065297 ec_init: CrosEC protocol v3 supported (256, 248)
10306 12:21:38.068668
10307 12:21:38.071944 tpm_cleanup: add release locality here.
10308 12:21:38.072065
10309 12:21:38.075092 Shutting down all USB controllers.
10310 12:21:38.075211
10311 12:21:38.078751 Removing current net device
10312 12:21:38.078874
10313 12:21:38.082000 Exiting depthcharge with code 4 at timestamp: 62643239
10314 12:21:38.082123
10315 12:21:38.085654 LZMA decompressing kernel-1 to 0x821a6718
10316 12:21:38.085778
10317 12:21:38.091494 LZMA decompressing kernel-1 to 0x40000000
10318 12:21:39.477919
10319 12:21:39.478073 jumping to kernel
10320 12:21:39.478516 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10321 12:21:39.478617 start: 2.2.5 auto-login-action (timeout 00:03:50) [common]
10322 12:21:39.478694 Setting prompt string to ['Linux version [0-9]']
10323 12:21:39.478762 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10324 12:21:39.478829 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10325 12:21:39.559557
10326 12:21:39.562820 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10327 12:21:39.566395 start: 2.2.5.1 login-action (timeout 00:03:50) [common]
10328 12:21:39.566497 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10329 12:21:39.566571 Setting prompt string to []
10330 12:21:39.566651 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10331 12:21:39.566728 Using line separator: #'\n'#
10332 12:21:39.566789 No login prompt set.
10333 12:21:39.566852 Parsing kernel messages
10334 12:21:39.566910 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10335 12:21:39.567012 [login-action] Waiting for messages, (timeout 00:03:50)
10336 12:21:39.586403 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j14831-arm64-gcc-10-defconfig-arm64-chromebook-g8jrt) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 16 12:04:53 UTC 2023
10337 12:21:39.589532 [ 0.000000] random: crng init done
10338 12:21:39.595898 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10339 12:21:39.595983 [ 0.000000] efi: UEFI not found.
10340 12:21:39.605924 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10341 12:21:39.612848 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10342 12:21:39.622538 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10343 12:21:39.632713 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10344 12:21:39.639053 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10345 12:21:39.642420 [ 0.000000] printk: bootconsole [mtk8250] enabled
10346 12:21:39.651366 [ 0.000000] NUMA: No NUMA configuration found
10347 12:21:39.657777 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10348 12:21:39.664545 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10349 12:21:39.664628 [ 0.000000] Zone ranges:
10350 12:21:39.671065 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10351 12:21:39.674381 [ 0.000000] DMA32 empty
10352 12:21:39.681265 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10353 12:21:39.684593 [ 0.000000] Movable zone start for each node
10354 12:21:39.688005 [ 0.000000] Early memory node ranges
10355 12:21:39.694627 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10356 12:21:39.701368 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10357 12:21:39.707703 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10358 12:21:39.714609 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10359 12:21:39.720945 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10360 12:21:39.727632 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10361 12:21:39.783531 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10362 12:21:39.790162 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10363 12:21:39.797072 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10364 12:21:39.800394 [ 0.000000] psci: probing for conduit method from DT.
10365 12:21:39.806580 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10366 12:21:39.809860 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10367 12:21:39.816529 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10368 12:21:39.819739 [ 0.000000] psci: SMC Calling Convention v1.2
10369 12:21:39.826360 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10370 12:21:39.829956 [ 0.000000] Detected VIPT I-cache on CPU0
10371 12:21:39.836503 [ 0.000000] CPU features: detected: GIC system register CPU interface
10372 12:21:39.843108 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10373 12:21:39.849856 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10374 12:21:39.856605 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10375 12:21:39.863363 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10376 12:21:39.870058 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10377 12:21:39.876456 [ 0.000000] alternatives: applying boot alternatives
10378 12:21:39.882963 [ 0.000000] Fallback order for Node 0: 0
10379 12:21:39.889744 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10380 12:21:39.889828 [ 0.000000] Policy zone: Normal
10381 12:21:39.906262 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10382 12:21:39.916140 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10383 12:21:39.927001 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10384 12:21:39.936837 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10385 12:21:39.943518 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10386 12:21:39.946975 <6>[ 0.000000] software IO TLB: area num 8.
10387 12:21:40.003278 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10388 12:21:40.152702 <6>[ 0.000000] Memory: 7931140K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 421628K reserved, 32768K cma-reserved)
10389 12:21:40.159383 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10390 12:21:40.166240 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10391 12:21:40.169193 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10392 12:21:40.176013 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10393 12:21:40.182718 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10394 12:21:40.185814 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10395 12:21:40.195612 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10396 12:21:40.202671 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10397 12:21:40.208897 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10398 12:21:40.215508 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10399 12:21:40.219237 <6>[ 0.000000] GICv3: 608 SPIs implemented
10400 12:21:40.222296 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10401 12:21:40.228887 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10402 12:21:40.232129 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10403 12:21:40.238840 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10404 12:21:40.252431 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10405 12:21:40.262251 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10406 12:21:40.272052 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10407 12:21:40.279070 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10408 12:21:40.292747 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10409 12:21:40.299135 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10410 12:21:40.306257 <6>[ 0.009237] Console: colour dummy device 80x25
10411 12:21:40.315483 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10412 12:21:40.322165 <6>[ 0.024405] pid_max: default: 32768 minimum: 301
10413 12:21:40.325576 <6>[ 0.029277] LSM: Security Framework initializing
10414 12:21:40.332069 <6>[ 0.034215] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10415 12:21:40.342251 <6>[ 0.042029] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10416 12:21:40.348780 <6>[ 0.051518] cblist_init_generic: Setting adjustable number of callback queues.
10417 12:21:40.355737 <6>[ 0.058964] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 12:21:40.365295 <6>[ 0.065301] cblist_init_generic: Setting adjustable number of callback queues.
10419 12:21:40.372042 <6>[ 0.072773] cblist_init_generic: Setting shift to 3 and lim to 1.
10420 12:21:40.375541 <6>[ 0.079211] rcu: Hierarchical SRCU implementation.
10421 12:21:40.381731 <6>[ 0.084255] rcu: Max phase no-delay instances is 1000.
10422 12:21:40.388665 <6>[ 0.091284] EFI services will not be available.
10423 12:21:40.392467 <6>[ 0.096259] smp: Bringing up secondary CPUs ...
10424 12:21:40.400057 <6>[ 0.101342] Detected VIPT I-cache on CPU1
10425 12:21:40.406797 <6>[ 0.101414] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10426 12:21:40.413267 <6>[ 0.101445] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10427 12:21:40.416848 <6>[ 0.101777] Detected VIPT I-cache on CPU2
10428 12:21:40.423593 <6>[ 0.101824] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10429 12:21:40.430160 <6>[ 0.101839] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10430 12:21:40.436828 <6>[ 0.102097] Detected VIPT I-cache on CPU3
10431 12:21:40.443125 <6>[ 0.102144] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10432 12:21:40.450168 <6>[ 0.102157] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10433 12:21:40.453267 <6>[ 0.102460] CPU features: detected: Spectre-v4
10434 12:21:40.459926 <6>[ 0.102466] CPU features: detected: Spectre-BHB
10435 12:21:40.463240 <6>[ 0.102470] Detected PIPT I-cache on CPU4
10436 12:21:40.469742 <6>[ 0.102526] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10437 12:21:40.476640 <6>[ 0.102544] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10438 12:21:40.483365 <6>[ 0.102835] Detected PIPT I-cache on CPU5
10439 12:21:40.489566 <6>[ 0.102897] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10440 12:21:40.496198 <6>[ 0.102914] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10441 12:21:40.499798 <6>[ 0.103198] Detected PIPT I-cache on CPU6
10442 12:21:40.506307 <6>[ 0.103262] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10443 12:21:40.513016 <6>[ 0.103278] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10444 12:21:40.519617 <6>[ 0.103578] Detected PIPT I-cache on CPU7
10445 12:21:40.526618 <6>[ 0.103642] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10446 12:21:40.533054 <6>[ 0.103659] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10447 12:21:40.536266 <6>[ 0.103708] smp: Brought up 1 node, 8 CPUs
10448 12:21:40.542611 <6>[ 0.244929] SMP: Total of 8 processors activated.
10449 12:21:40.546018 <6>[ 0.249880] CPU features: detected: 32-bit EL0 Support
10450 12:21:40.556516 <6>[ 0.255276] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10451 12:21:40.562636 <6>[ 0.264077] CPU features: detected: Common not Private translations
10452 12:21:40.566097 <6>[ 0.270553] CPU features: detected: CRC32 instructions
10453 12:21:40.572701 <6>[ 0.275904] CPU features: detected: RCpc load-acquire (LDAPR)
10454 12:21:40.579316 <6>[ 0.281864] CPU features: detected: LSE atomic instructions
10455 12:21:40.585882 <6>[ 0.287646] CPU features: detected: Privileged Access Never
10456 12:21:40.589344 <6>[ 0.293462] CPU features: detected: RAS Extension Support
10457 12:21:40.599229 <6>[ 0.299071] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10458 12:21:40.602509 <6>[ 0.306290] CPU: All CPU(s) started at EL2
10459 12:21:40.609073 <6>[ 0.310607] alternatives: applying system-wide alternatives
10460 12:21:40.617827 <6>[ 0.321323] devtmpfs: initialized
10461 12:21:40.629884 <6>[ 0.330190] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10462 12:21:40.640010 <6>[ 0.340153] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10463 12:21:40.646596 <6>[ 0.348168] pinctrl core: initialized pinctrl subsystem
10464 12:21:40.649859 <6>[ 0.354852] DMI not present or invalid.
10465 12:21:40.656511 <6>[ 0.359263] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10466 12:21:40.666337 <6>[ 0.366120] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10467 12:21:40.673124 <6>[ 0.373707] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10468 12:21:40.682885 <6>[ 0.381922] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10469 12:21:40.686544 <6>[ 0.390165] audit: initializing netlink subsys (disabled)
10470 12:21:40.696338 <5>[ 0.395856] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10471 12:21:40.703020 <6>[ 0.396541] thermal_sys: Registered thermal governor 'step_wise'
10472 12:21:40.709544 <6>[ 0.403822] thermal_sys: Registered thermal governor 'power_allocator'
10473 12:21:40.712967 <6>[ 0.410080] cpuidle: using governor menu
10474 12:21:40.716082 <6>[ 0.421042] NET: Registered PF_QIPCRTR protocol family
10475 12:21:40.726513 <6>[ 0.426520] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10476 12:21:40.729610 <6>[ 0.433625] ASID allocator initialised with 32768 entries
10477 12:21:40.736688 <6>[ 0.440207] Serial: AMBA PL011 UART driver
10478 12:21:40.745385 <4>[ 0.449076] Trying to register duplicate clock ID: 134
10479 12:21:40.801724 <6>[ 0.508602] KASLR enabled
10480 12:21:40.816325 <6>[ 0.516391] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10481 12:21:40.822840 <6>[ 0.523407] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10482 12:21:40.829999 <6>[ 0.529894] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10483 12:21:40.835994 <6>[ 0.536900] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10484 12:21:40.842869 <6>[ 0.543386] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10485 12:21:40.849328 <6>[ 0.550390] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10486 12:21:40.856077 <6>[ 0.556879] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10487 12:21:40.862585 <6>[ 0.563884] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10488 12:21:40.865731 <6>[ 0.571375] ACPI: Interpreter disabled.
10489 12:21:40.874122 <6>[ 0.577797] iommu: Default domain type: Translated
10490 12:21:40.880756 <6>[ 0.582911] iommu: DMA domain TLB invalidation policy: strict mode
10491 12:21:40.884278 <5>[ 0.589564] SCSI subsystem initialized
10492 12:21:40.890737 <6>[ 0.593738] usbcore: registered new interface driver usbfs
10493 12:21:40.897459 <6>[ 0.599470] usbcore: registered new interface driver hub
10494 12:21:40.900655 <6>[ 0.605022] usbcore: registered new device driver usb
10495 12:21:40.907718 <6>[ 0.611121] pps_core: LinuxPPS API ver. 1 registered
10496 12:21:40.917621 <6>[ 0.616314] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10497 12:21:40.921237 <6>[ 0.625663] PTP clock support registered
10498 12:21:40.923919 <6>[ 0.629907] EDAC MC: Ver: 3.0.0
10499 12:21:40.931486 <6>[ 0.635053] FPGA manager framework
10500 12:21:40.937974 <6>[ 0.638733] Advanced Linux Sound Architecture Driver Initialized.
10501 12:21:40.941189 <6>[ 0.645512] vgaarb: loaded
10502 12:21:40.948084 <6>[ 0.648704] clocksource: Switched to clocksource arch_sys_counter
10503 12:21:40.951282 <5>[ 0.655138] VFS: Disk quotas dquot_6.6.0
10504 12:21:40.958092 <6>[ 0.659322] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10505 12:21:40.961281 <6>[ 0.666510] pnp: PnP ACPI: disabled
10506 12:21:40.969585 <6>[ 0.673202] NET: Registered PF_INET protocol family
10507 12:21:40.979347 <6>[ 0.678789] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10508 12:21:40.990906 <6>[ 0.691092] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10509 12:21:41.000721 <6>[ 0.699909] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10510 12:21:41.007249 <6>[ 0.707878] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10511 12:21:41.014145 <6>[ 0.716577] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10512 12:21:41.025835 <6>[ 0.726326] TCP: Hash tables configured (established 65536 bind 65536)
10513 12:21:41.032551 <6>[ 0.733185] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10514 12:21:41.039113 <6>[ 0.740387] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10515 12:21:41.046084 <6>[ 0.748063] NET: Registered PF_UNIX/PF_LOCAL protocol family
10516 12:21:41.052715 <6>[ 0.754245] RPC: Registered named UNIX socket transport module.
10517 12:21:41.055654 <6>[ 0.760399] RPC: Registered udp transport module.
10518 12:21:41.062222 <6>[ 0.765334] RPC: Registered tcp transport module.
10519 12:21:41.069429 <6>[ 0.770266] RPC: Registered tcp NFSv4.1 backchannel transport module.
10520 12:21:41.072107 <6>[ 0.776937] PCI: CLS 0 bytes, default 64
10521 12:21:41.075776 <6>[ 0.781341] Unpacking initramfs...
10522 12:21:41.100584 <6>[ 0.800813] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10523 12:21:41.110712 <6>[ 0.809465] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10524 12:21:41.113696 <6>[ 0.818324] kvm [1]: IPA Size Limit: 40 bits
10525 12:21:41.120609 <6>[ 0.822851] kvm [1]: GICv3: no GICV resource entry
10526 12:21:41.124360 <6>[ 0.827871] kvm [1]: disabling GICv2 emulation
10527 12:21:41.130564 <6>[ 0.832557] kvm [1]: GIC system register CPU interface enabled
10528 12:21:41.133979 <6>[ 0.838718] kvm [1]: vgic interrupt IRQ18
10529 12:21:41.140411 <6>[ 0.843077] kvm [1]: VHE mode initialized successfully
10530 12:21:41.143868 <5>[ 0.849459] Initialise system trusted keyrings
10531 12:21:41.150716 <6>[ 0.854296] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10532 12:21:41.160448 <6>[ 0.864271] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10533 12:21:41.167295 <5>[ 0.870648] NFS: Registering the id_resolver key type
10534 12:21:41.170479 <5>[ 0.875950] Key type id_resolver registered
10535 12:21:41.177052 <5>[ 0.880368] Key type id_legacy registered
10536 12:21:41.184160 <6>[ 0.884647] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10537 12:21:41.190464 <6>[ 0.891567] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10538 12:21:41.197102 <6>[ 0.899276] 9p: Installing v9fs 9p2000 file system support
10539 12:21:41.233080 <5>[ 0.936621] Key type asymmetric registered
10540 12:21:41.236325 <5>[ 0.940953] Asymmetric key parser 'x509' registered
10541 12:21:41.246192 <6>[ 0.946107] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10542 12:21:41.249385 <6>[ 0.953718] io scheduler mq-deadline registered
10543 12:21:41.253003 <6>[ 0.958496] io scheduler kyber registered
10544 12:21:41.272383 <6>[ 0.975691] EINJ: ACPI disabled.
10545 12:21:41.304657 <4>[ 1.001709] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 12:21:41.314538 <4>[ 1.012370] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10547 12:21:41.329337 <6>[ 1.033109] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10548 12:21:41.337329 <6>[ 1.041070] printk: console [ttyS0] disabled
10549 12:21:41.365585 <6>[ 1.065723] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10550 12:21:41.372261 <6>[ 1.075201] printk: console [ttyS0] enabled
10551 12:21:41.375505 <6>[ 1.075201] printk: console [ttyS0] enabled
10552 12:21:41.381970 <6>[ 1.084096] printk: bootconsole [mtk8250] disabled
10553 12:21:41.385896 <6>[ 1.084096] printk: bootconsole [mtk8250] disabled
10554 12:21:41.391747 <6>[ 1.095442] SuperH (H)SCI(F) driver initialized
10555 12:21:41.394930 <6>[ 1.100738] msm_serial: driver initialized
10556 12:21:41.409357 <6>[ 1.109680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10557 12:21:41.419436 <6>[ 1.118223] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10558 12:21:41.425900 <6>[ 1.126765] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10559 12:21:41.436288 <6>[ 1.135393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10560 12:21:41.442668 <6>[ 1.144103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10561 12:21:41.452843 <6>[ 1.152818] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10562 12:21:41.462715 <6>[ 1.161360] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10563 12:21:41.469405 <6>[ 1.170161] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10564 12:21:41.479180 <6>[ 1.178705] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10565 12:21:41.490579 <6>[ 1.194451] loop: module loaded
10566 12:21:41.497268 <6>[ 1.200416] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10567 12:21:41.519956 <4>[ 1.223880] mtk-pmic-keys: Failed to locate of_node [id: -1]
10568 12:21:41.527268 <6>[ 1.230893] megasas: 07.719.03.00-rc1
10569 12:21:41.536824 <6>[ 1.240656] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10570 12:21:41.544510 <6>[ 1.248084] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10571 12:21:41.561526 <6>[ 1.264799] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10572 12:21:41.617770 <6>[ 1.315037] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10573 12:21:42.674840 <6>[ 2.378535] Freeing initrd memory: 38412K
10574 12:21:42.685272 <6>[ 2.389109] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10575 12:21:42.696311 <6>[ 2.400253] tun: Universal TUN/TAP device driver, 1.6
10576 12:21:42.699919 <6>[ 2.406349] thunder_xcv, ver 1.0
10577 12:21:42.703473 <6>[ 2.409854] thunder_bgx, ver 1.0
10578 12:21:42.706266 <6>[ 2.413350] nicpf, ver 1.0
10579 12:21:42.717404 <6>[ 2.417410] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10580 12:21:42.720379 <6>[ 2.424887] hns3: Copyright (c) 2017 Huawei Corporation.
10581 12:21:42.727187 <6>[ 2.430474] hclge is initializing
10582 12:21:42.729951 <6>[ 2.434053] e1000: Intel(R) PRO/1000 Network Driver
10583 12:21:42.737000 <6>[ 2.439183] e1000: Copyright (c) 1999-2006 Intel Corporation.
10584 12:21:42.740074 <6>[ 2.445196] e1000e: Intel(R) PRO/1000 Network Driver
10585 12:21:42.746684 <6>[ 2.450412] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10586 12:21:42.753314 <6>[ 2.456601] igb: Intel(R) Gigabit Ethernet Network Driver
10587 12:21:42.760291 <6>[ 2.462251] igb: Copyright (c) 2007-2014 Intel Corporation.
10588 12:21:42.766398 <6>[ 2.468086] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10589 12:21:42.773203 <6>[ 2.474604] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10590 12:21:42.776712 <6>[ 2.481070] sky2: driver version 1.30
10591 12:21:42.783208 <6>[ 2.486097] VFIO - User Level meta-driver version: 0.3
10592 12:21:42.790809 <6>[ 2.494416] usbcore: registered new interface driver usb-storage
10593 12:21:42.796984 <6>[ 2.500867] usbcore: registered new device driver onboard-usb-hub
10594 12:21:42.806481 <6>[ 2.510052] mt6397-rtc mt6359-rtc: registered as rtc0
10595 12:21:42.816010 <6>[ 2.515546] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-16T12:21:36 UTC (1692188496)
10596 12:21:42.819519 <6>[ 2.525177] i2c_dev: i2c /dev entries driver
10597 12:21:42.836369 <6>[ 2.536953] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10598 12:21:42.857354 <6>[ 2.560958] cpu cpu0: EM: created perf domain
10599 12:21:42.860618 <6>[ 2.565960] cpu cpu4: EM: created perf domain
10600 12:21:42.867811 <6>[ 2.571573] sdhci: Secure Digital Host Controller Interface driver
10601 12:21:42.874275 <6>[ 2.578005] sdhci: Copyright(c) Pierre Ossman
10602 12:21:42.881207 <6>[ 2.582957] Synopsys Designware Multimedia Card Interface Driver
10603 12:21:42.887740 <6>[ 2.589598] sdhci-pltfm: SDHCI platform and OF driver helper
10604 12:21:42.891155 <6>[ 2.589722] mmc0: CQHCI version 5.10
10605 12:21:42.897572 <6>[ 2.599897] ledtrig-cpu: registered to indicate activity on CPUs
10606 12:21:42.904224 <6>[ 2.606939] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10607 12:21:42.911072 <6>[ 2.614009] usbcore: registered new interface driver usbhid
10608 12:21:42.914149 <6>[ 2.619832] usbhid: USB HID core driver
10609 12:21:42.921068 <6>[ 2.624042] spi_master spi0: will run message pump with realtime priority
10610 12:21:42.964114 <6>[ 2.661363] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10611 12:21:42.979365 <6>[ 2.676371] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10612 12:21:42.987621 <6>[ 2.691360] cros-ec-spi spi0.0: Chrome EC device registered
10613 12:21:42.994764 <6>[ 2.697461] mmc0: Command Queue Engine enabled
10614 12:21:43.001269 <6>[ 2.702224] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10615 12:21:43.004299 <6>[ 2.709551] mmcblk0: mmc0:0001 DA4128 116 GiB
10616 12:21:43.015410 <6>[ 2.719092] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10617 12:21:43.021936 <6>[ 2.725976] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10618 12:21:43.028672 <6>[ 2.732126] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10619 12:21:43.038423 <6>[ 2.736438] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10620 12:21:43.045431 <6>[ 2.738044] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10621 12:21:43.048598 <6>[ 2.748125] NET: Registered PF_PACKET protocol family
10622 12:21:43.055089 <6>[ 2.758604] 9pnet: Installing 9P2000 support
10623 12:21:43.058506 <5>[ 2.763167] Key type dns_resolver registered
10624 12:21:43.065128 <6>[ 2.768130] registered taskstats version 1
10625 12:21:43.068508 <5>[ 2.772516] Loading compiled-in X.509 certificates
10626 12:21:43.098179 <4>[ 2.795309] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10627 12:21:43.107816 <4>[ 2.806065] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10628 12:21:43.114876 <3>[ 2.816656] debugfs: File 'uA_load' in directory '/' already present!
10629 12:21:43.121244 <3>[ 2.823378] debugfs: File 'min_uV' in directory '/' already present!
10630 12:21:43.128006 <3>[ 2.830010] debugfs: File 'max_uV' in directory '/' already present!
10631 12:21:43.134877 <3>[ 2.836635] debugfs: File 'constraint_flags' in directory '/' already present!
10632 12:21:43.147431 <3>[ 2.847621] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10633 12:21:43.157823 <6>[ 2.861613] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10634 12:21:43.164674 <6>[ 2.868483] xhci-mtk 11200000.usb: xHCI Host Controller
10635 12:21:43.171431 <6>[ 2.874006] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10636 12:21:43.181171 <6>[ 2.881844] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10637 12:21:43.187801 <6>[ 2.891273] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10638 12:21:43.194778 <6>[ 2.897351] xhci-mtk 11200000.usb: xHCI Host Controller
10639 12:21:43.201541 <6>[ 2.902828] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10640 12:21:43.207860 <6>[ 2.910477] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10641 12:21:43.214395 <6>[ 2.918092] hub 1-0:1.0: USB hub found
10642 12:21:43.217877 <6>[ 2.922105] hub 1-0:1.0: 1 port detected
10643 12:21:43.224444 <6>[ 2.926376] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10644 12:21:43.230907 <6>[ 2.934885] hub 2-0:1.0: USB hub found
10645 12:21:43.234486 <6>[ 2.938891] hub 2-0:1.0: 1 port detected
10646 12:21:43.241536 <6>[ 2.945180] mtk-msdc 11f70000.mmc: Got CD GPIO
10647 12:21:43.252437 <6>[ 2.953052] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10648 12:21:43.259179 <6>[ 2.961074] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10649 12:21:43.269137 <4>[ 2.968979] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10650 12:21:43.279188 <6>[ 2.978499] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10651 12:21:43.285501 <6>[ 2.986579] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10652 12:21:43.292215 <6>[ 2.994720] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10653 12:21:43.302522 <6>[ 3.002650] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10654 12:21:43.308963 <6>[ 3.010504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10655 12:21:43.318732 <6>[ 3.018331] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10656 12:21:43.328465 <6>[ 3.028820] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10657 12:21:43.335517 <6>[ 3.037175] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10658 12:21:43.345338 <6>[ 3.045540] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10659 12:21:43.351752 <6>[ 3.053880] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10660 12:21:43.361723 <6>[ 3.062232] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10661 12:21:43.371673 <6>[ 3.070572] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10662 12:21:43.378711 <6>[ 3.078922] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10663 12:21:43.388103 <6>[ 3.087261] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10664 12:21:43.394561 <6>[ 3.095615] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10665 12:21:43.404644 <6>[ 3.103954] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10666 12:21:43.411033 <6>[ 3.112303] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10667 12:21:43.421273 <6>[ 3.120641] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10668 12:21:43.428669 <6>[ 3.128979] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10669 12:21:43.438064 <6>[ 3.137318] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10670 12:21:43.444555 <6>[ 3.145655] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10671 12:21:43.451139 <6>[ 3.154444] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10672 12:21:43.457505 <6>[ 3.161398] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10673 12:21:43.464199 <6>[ 3.168159] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10674 12:21:43.474192 <6>[ 3.174911] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10675 12:21:43.480801 <6>[ 3.181850] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10676 12:21:43.487362 <6>[ 3.188706] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10677 12:21:43.497727 <6>[ 3.197839] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10678 12:21:43.507383 <6>[ 3.206958] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10679 12:21:43.517398 <6>[ 3.216252] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10680 12:21:43.527203 <6>[ 3.225747] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10681 12:21:43.533760 <6>[ 3.235224] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10682 12:21:43.543864 <6>[ 3.244348] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10683 12:21:43.553733 <6>[ 3.253814] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10684 12:21:43.563571 <6>[ 3.262934] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10685 12:21:43.573673 <6>[ 3.272229] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10686 12:21:43.583488 <6>[ 3.282388] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10687 12:21:43.593660 <6>[ 3.294412] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10688 12:21:43.624494 <6>[ 3.325238] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10689 12:21:43.652412 <6>[ 3.356402] hub 2-1:1.0: USB hub found
10690 12:21:43.655578 <6>[ 3.360887] hub 2-1:1.0: 3 ports detected
10691 12:21:43.776390 <6>[ 3.476903] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10692 12:21:43.931194 <6>[ 3.635315] hub 1-1:1.0: USB hub found
10693 12:21:43.934491 <6>[ 3.639834] hub 1-1:1.0: 4 ports detected
10694 12:21:44.008328 <6>[ 3.709239] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10695 12:21:44.256593 <6>[ 3.957074] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10696 12:21:44.388710 <6>[ 4.092805] hub 1-1.4:1.0: USB hub found
10697 12:21:44.392218 <6>[ 4.097466] hub 1-1.4:1.0: 2 ports detected
10698 12:21:44.688092 <6>[ 4.388990] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10699 12:21:44.880487 <6>[ 4.580997] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10700 12:21:55.889110 <6>[ 15.597929] ALSA device list:
10701 12:21:55.895911 <6>[ 15.601221] No soundcards found.
10702 12:21:55.903594 <6>[ 15.609110] Freeing unused kernel memory: 8384K
10703 12:21:55.906960 <6>[ 15.614063] Run /init as init process
10704 12:21:55.952867 <6>[ 15.658265] NET: Registered PF_INET6 protocol family
10705 12:21:55.959599 <6>[ 15.664632] Segment Routing with IPv6
10706 12:21:55.962831 <6>[ 15.668592] In-situ OAM (IOAM) with IPv6
10707 12:21:55.993503 <30>[ 15.682305] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10708 12:21:56.000654 <30>[ 15.706170] systemd[1]: Detected architecture arm64.
10709 12:21:56.000740
10710 12:21:56.007383 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10711 12:21:56.007467
10712 12:21:56.019496 <30>[ 15.725048] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10713 12:21:56.158057 <30>[ 15.860210] systemd[1]: Queued start job for default target Graphical Interface.
10714 12:21:56.208206 <30>[ 15.913657] systemd[1]: Created slice system-getty.slice.
10715 12:21:56.214957 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10716 12:21:56.236221 <30>[ 15.941635] systemd[1]: Created slice system-modprobe.slice.
10717 12:21:56.243140 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10718 12:21:56.260233 <30>[ 15.965737] systemd[1]: Created slice system-serial\x2dgetty.slice.
10719 12:21:56.270345 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10720 12:21:56.284849 <30>[ 15.990090] systemd[1]: Created slice User and Session Slice.
10721 12:21:56.291306 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10722 12:21:56.311244 <30>[ 16.013253] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10723 12:21:56.320852 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10724 12:21:56.339947 <30>[ 16.041738] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10725 12:21:56.346302 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10726 12:21:56.371035 <30>[ 16.069528] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10727 12:21:56.377300 <30>[ 16.081809] systemd[1]: Reached target Local Encrypted Volumes.
10728 12:21:56.384024 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10729 12:21:56.400180 <30>[ 16.105578] systemd[1]: Reached target Paths.
10730 12:21:56.403515 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10731 12:21:56.419546 <30>[ 16.124982] systemd[1]: Reached target Remote File Systems.
10732 12:21:56.426092 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10733 12:21:56.444173 <30>[ 16.149367] systemd[1]: Reached target Slices.
10734 12:21:56.450370 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10735 12:21:56.463358 <30>[ 16.169004] systemd[1]: Reached target Swap.
10736 12:21:56.467011 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10737 12:21:56.487288 <30>[ 16.189488] systemd[1]: Listening on initctl Compatibility Named Pipe.
10738 12:21:56.494376 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10739 12:21:56.500447 <30>[ 16.204667] systemd[1]: Listening on Journal Audit Socket.
10740 12:21:56.507406 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10741 12:21:56.520130 <30>[ 16.225474] systemd[1]: Listening on Journal Socket (/dev/log).
10742 12:21:56.526874 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10743 12:21:56.544679 <30>[ 16.250222] systemd[1]: Listening on Journal Socket.
10744 12:21:56.551440 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10745 12:21:56.564096 <30>[ 16.269707] systemd[1]: Listening on Network Service Netlink Socket.
10746 12:21:56.574495 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10747 12:21:56.588122 <30>[ 16.293565] systemd[1]: Listening on udev Control Socket.
10748 12:21:56.594792 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10749 12:21:56.612704 <30>[ 16.318081] systemd[1]: Listening on udev Kernel Socket.
10750 12:21:56.619155 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10751 12:21:56.659512 <30>[ 16.365164] systemd[1]: Mounting Huge Pages File System...
10752 12:21:56.666337 Mounting [0;1;39mHuge Pages File System[0m...
10753 12:21:56.680792 <30>[ 16.386539] systemd[1]: Mounting POSIX Message Queue File System...
10754 12:21:56.687766 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10755 12:21:56.705390 <30>[ 16.410979] systemd[1]: Mounting Kernel Debug File System...
10756 12:21:56.712250 Mounting [0;1;39mKernel Debug File System[0m...
10757 12:21:56.730901 <30>[ 16.433191] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10758 12:21:56.743159 <30>[ 16.445107] systemd[1]: Starting Create list of static device nodes for the current kernel...
10759 12:21:56.749504 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10760 12:21:56.771571 <30>[ 16.476993] systemd[1]: Starting Load Kernel Module configfs...
10761 12:21:56.778169 Starting [0;1;39mLoad Kernel Module configfs[0m...
10762 12:21:56.796248 <30>[ 16.501424] systemd[1]: Starting Load Kernel Module drm...
10763 12:21:56.802555 Starting [0;1;39mLoad Kernel Module drm[0m...
10764 12:21:56.819013 <30>[ 16.521342] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10765 12:21:56.833564 <30>[ 16.539168] systemd[1]: Starting Journal Service...
10766 12:21:56.837094 Starting [0;1;39mJournal Service[0m...
10767 12:21:56.861163 <30>[ 16.566541] systemd[1]: Starting Load Kernel Modules...
10768 12:21:56.867683 Starting [0;1;39mLoad Kernel Modules[0m...
10769 12:21:56.892093 <30>[ 16.593873] systemd[1]: Starting Remount Root and Kernel File Systems...
10770 12:21:56.898111 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10771 12:21:56.913760 <30>[ 16.619399] systemd[1]: Starting Coldplug All udev Devices...
10772 12:21:56.920529 Starting [0;1;39mColdplug All udev Devices[0m...
10773 12:21:56.938249 <30>[ 16.643914] systemd[1]: Started Journal Service.
10774 12:21:56.944988 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10775 12:21:56.961759 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10776 12:21:56.980473 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10777 12:21:56.996404 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10778 12:21:57.017162 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10779 12:21:57.039193 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10780 12:21:57.062757 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10781 12:21:57.085315 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10782 12:21:57.105602 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10783 12:21:57.123794 See 'systemctl status systemd-remount-fs.service' for details.
10784 12:21:57.168715 Mounting [0;1;39mKernel Configuration File System[0m...
10785 12:21:57.186135 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10786 12:21:57.203244 <46>[ 16.905624] systemd-journald[188]: Received client request to flush runtime journal.
10787 12:21:57.212623 Starting [0;1;39mLoad/Save Random Seed[0m...
10788 12:21:57.236649 Starting [0;1;39mApply Kernel Variables[0m...
10789 12:21:57.261271 Starting [0;1;39mCreate System Users[0m...
10790 12:21:57.284854 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10791 12:21:57.304424 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10792 12:21:57.328589 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10793 12:21:57.341123 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10794 12:21:57.357233 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10795 12:21:57.372008 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10796 12:21:57.419708 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10797 12:21:57.441614 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10798 12:21:57.455700 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10799 12:21:57.471534 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10800 12:21:57.507741 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10801 12:21:57.532408 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10802 12:21:57.553330 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10803 12:21:57.573465 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10804 12:21:57.593453 Starting [0;1;39mNetwork Service[0m...
10805 12:21:57.613809 Starting [0;1;39mNetwork Time Synchronization[0m...
10806 12:21:57.634697 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10807 12:21:57.670110 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10808 12:21:57.704785 Starting [0;1;39mNetwork Name Resolution[0m...
10809 12:21:57.721495 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10810 12:21:57.736022 <6>[ 17.438181] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10811 12:21:57.756902 <6>[ 17.459050] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10812 12:21:57.760046 <6>[ 17.462760] remoteproc remoteproc0: scp is available
10813 12:21:57.770164 <6>[ 17.467173] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10814 12:21:57.776596 <6>[ 17.472376] remoteproc remoteproc0: powering up scp
10815 12:21:57.783344 <6>[ 17.482748] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10816 12:21:57.793085 <6>[ 17.486438] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10817 12:21:57.799699 <6>[ 17.503284] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10818 12:21:57.807207 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10819 12:21:57.821566 <3>[ 17.523449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 12:21:57.827753 <3>[ 17.531772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 12:21:57.837716 <3>[ 17.539906] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10822 12:21:57.847753 [[0;32m OK [0m] Started [0;<3>[ 17.550027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10823 12:21:57.857753 1;39mNetwork Nam<3>[ 17.559240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 12:21:57.867606 e Resolution[0m<3>[ 17.568575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10825 12:21:57.874380 <3>[ 17.578046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10826 12:21:57.874463 .
10827 12:21:57.884340 <3>[ 17.586129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10828 12:21:57.895948 [[0;32m OK [<3>[ 17.598715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 12:21:57.906246 <4>[ 17.600158] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10830 12:21:57.912280 <3>[ 17.613405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 12:21:57.922477 0m] Found device<4>[ 17.618838] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10832 12:21:57.928927 [0;1;39m/dev/t<6>[ 17.622010] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10833 12:21:57.932363 tyS0[0m.
10834 12:21:57.938939 <3>[ 17.623166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10835 12:21:57.948769 <3>[ 17.623175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 12:21:57.956199 <3>[ 17.624968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 12:21:57.959295 <6>[ 17.625261] mc: Linux media interface: v0.10
10838 12:21:57.965629 <6>[ 17.628482] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10839 12:21:57.971889 <6>[ 17.628493] pci_bus 0000:00: root bus resource [bus 00-ff]
10840 12:21:57.979232 <6>[ 17.628500] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10841 12:21:57.989492 <6>[ 17.628504] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10842 12:21:57.996244 <6>[ 17.628548] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10843 12:21:58.002615 <6>[ 17.628565] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10844 12:21:58.009450 <6>[ 17.628649] pci 0000:00:00.0: supports D1 D2
10845 12:21:58.016012 <6>[ 17.628653] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10846 12:21:58.022485 <6>[ 17.634516] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10847 12:21:58.029553 <6>[ 17.634524] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10848 12:21:58.039590 <6>[ 17.637439] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10849 12:21:58.049613 <3>[ 17.640922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10850 12:21:58.057601 <3>[ 17.640935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 12:21:58.063996 <3>[ 17.640945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10852 12:21:58.073887 <3>[ 17.640950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 12:21:58.080401 <3>[ 17.642425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 12:21:58.090736 <6>[ 17.644778] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10855 12:21:58.100123 <6>[ 17.649254] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10856 12:21:58.106688 <6>[ 17.649964] remoteproc remoteproc0: remote processor scp is now up
10857 12:21:58.113644 <4>[ 17.654198] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10858 12:21:58.120349 <4>[ 17.654198] Fallback method does not support PEC.
10859 12:21:58.127334 <6>[ 17.659911] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10860 12:21:58.130924 <6>[ 17.675715] videodev: Linux video capture interface: v2.00
10861 12:21:58.137385 <6>[ 17.677811] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10862 12:21:58.144217 <6>[ 17.681667] usbcore: registered new interface driver r8152
10863 12:21:58.154720 <3>[ 17.695503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 12:21:58.161450 <6>[ 17.700661] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10865 12:21:58.168033 <6>[ 17.700681] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10866 12:21:58.178569 <6>[ 17.741318] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10867 12:21:58.182076 <6>[ 17.741591] pci 0000:01:00.0: supports D1 D2
10868 12:21:58.191919 <3>[ 17.746732] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 12:21:58.198888 <3>[ 17.747542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10870 12:21:58.209147 <3>[ 17.767332] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 12:21:58.215997 <6>[ 17.768609] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10872 12:21:58.222393 <6>[ 17.776217] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10873 12:21:58.229062 <6>[ 17.785471] usbcore: registered new interface driver cdc_ether
10874 12:21:58.232310 <6>[ 17.788598] Bluetooth: Core ver 2.22
10875 12:21:58.239055 <6>[ 17.789286] NET: Registered PF_BLUETOOTH protocol family
10876 12:21:58.246497 <6>[ 17.789320] Bluetooth: HCI device and connection manager initialized
10877 12:21:58.249864 <6>[ 17.789437] Bluetooth: HCI socket layer initialized
10878 12:21:58.256792 <6>[ 17.789454] Bluetooth: L2CAP socket layer initialized
10879 12:21:58.259983 <6>[ 17.789499] Bluetooth: SCO socket layer initialized
10880 12:21:58.269483 <6>[ 17.791414] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10881 12:21:58.277140 <6>[ 17.793992] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10882 12:21:58.280128 <6>[ 17.810240] usbcore: registered new interface driver r8153_ecm
10883 12:21:58.290562 <6>[ 17.816128] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10884 12:21:58.297590 <6>[ 17.816658] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10885 12:21:58.304085 <4>[ 17.819564] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10886 12:21:58.314675 <4>[ 17.819575] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10887 12:21:58.321654 <6>[ 17.819944] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10888 12:21:58.334601 <6>[ 17.821193] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10889 12:21:58.342028 <6>[ 17.821958] usbcore: registered new interface driver uvcvideo
10890 12:21:58.345384 <6>[ 17.831381] usbcore: registered new interface driver btusb
10891 12:21:58.355387 <4>[ 17.832316] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10892 12:21:58.361831 <3>[ 17.832329] Bluetooth: hci0: Failed to load firmware file (-2)
10893 12:21:58.368598 <3>[ 17.832333] Bluetooth: hci0: Failed to set up firmware (-2)
10894 12:21:58.378218 <4>[ 17.832338] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10895 12:21:58.388077 <6>[ 17.835928] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10896 12:21:58.394841 <3>[ 17.843717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:21:58.404532 <6>[ 17.849378] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10898 12:21:58.411077 <6>[ 17.849865] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10899 12:21:58.417999 <3>[ 17.855139] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10900 12:21:58.427617 <3>[ 17.861705] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 12:21:58.434364 <6>[ 17.863723] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10902 12:21:58.444096 <3>[ 17.883325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 12:21:58.450678 <6>[ 17.888094] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10904 12:21:58.457381 <6>[ 17.912946] r8152 2-1.3:1.0 eth0: v1.12.13
10905 12:21:58.464032 <3>[ 17.914695] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 12:21:58.470719 <6>[ 17.918957] pci 0000:00:00.0: PCI bridge to [bus 01]
10907 12:21:58.477178 <6>[ 17.937327] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10908 12:21:58.484119 <6>[ 17.939190] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10909 12:21:58.493956 <3>[ 17.956619] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 12:21:58.500810 <6>[ 17.960641] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10911 12:21:58.506897 [[0;32m OK [<6>[ 18.211067] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10912 12:21:58.513664 0m] Created slic<6>[ 18.219001] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10913 12:21:58.520346 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10914 12:21:58.533512 <5>[ 18.235722] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10915 12:21:58.540181 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10916 12:21:58.555494 <5>[ 18.258110] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10917 12:21:58.565874 [[0;32m OK [<4>[ 18.266891] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10918 12:21:58.572334 0m] Reached targ<6>[ 18.276046] cfg80211: failed to load regulatory.db
10919 12:21:58.575357 et [0;1;39mHost and Network Name Lookups[0m.
10920 12:21:58.591895 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10921 12:21:58.612226 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10922 12:21:58.622452 <6>[ 18.324628] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10923 12:21:58.628999 <6>[ 18.332154] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10924 12:21:58.643648 <6>[ 18.348900] mt7921e 0000:01:00.0: ASIC revision: 79610010
10925 12:21:58.671618 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10926 12:21:58.697810 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10927 12:21:58.749715 <4>[ 18.448838] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10928 12:21:58.838689 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10929 12:21:58.851707 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10930 12:21:58.870757 <4>[ 18.569925] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10931 12:21:58.877280 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10932 12:21:58.895346 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10933 12:21:58.911504 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10934 12:21:58.931429 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10935 12:21:58.943829 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10936 12:21:58.959553 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10937 12:21:58.979865 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10938 12:21:58.994909 <4>[ 18.694021] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10939 12:21:59.037163 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10940 12:21:59.070340 Starting [0;1;39mUser Login Management[0m...
10941 12:21:59.088290 Starting [0;1;39mPermit User Sessions[0m...
10942 12:21:59.109665 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10943 12:21:59.124730 <4>[ 18.822766] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10944 12:21:59.139276 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10945 12:21:59.160229 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10946 12:21:59.176466 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10947 12:21:59.195665 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10948 12:21:59.213438 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10949 12:21:59.221761 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10950 12:21:59.237610 <4>[ 18.936969] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10951 12:21:59.245905 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10952 12:21:59.264215 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10953 12:21:59.320519 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10954 12:21:59.363164 [[0;32m OK [<4>[ 19.062705] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10955 12:21:59.370166 0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10956 12:21:59.413617
10957 12:21:59.413701
10958 12:21:59.417276 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10959 12:21:59.417361
10960 12:21:59.420276 debian-bullseye-arm64 login: root (automatic login)
10961 12:21:59.420361
10962 12:21:59.420447
10963 12:21:59.446659 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Wed Aug 16 12:04:53 UTC 2023 aarch64
10964 12:21:59.446746
10965 12:21:59.453245 The programs included with the Debian GNU/Linux system are free software;
10966 12:21:59.459836 the exact distribution terms for each program are described in the
10967 12:21:59.463500 individual files in /usr/share/doc/*/copyright.
10968 12:21:59.463586
10969 12:21:59.470349 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10970 12:21:59.473021 permitted by applicable law.
10971 12:21:59.473363 Matched prompt #10: / #
10973 12:21:59.473590 Setting prompt string to ['/ #']
10974 12:21:59.473703 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10976 12:21:59.473926 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10977 12:21:59.474027 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
10978 12:21:59.474133 Setting prompt string to ['/ #']
10979 12:21:59.474230 Forcing a shell prompt, looking for ['/ #']
10981 12:21:59.524494 / #
10982 12:21:59.524644 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10983 12:21:59.524805 Waiting using forced prompt support (timeout 00:02:30)
10984 12:21:59.524964 <4>[ 19.189588] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 12:21:59.529769
10986 12:21:59.530093 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10987 12:21:59.530245 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
10988 12:21:59.530405 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10989 12:21:59.530549 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
10990 12:21:59.530689 end: 2 depthcharge-action (duration 00:01:30) [common]
10991 12:21:59.530835 start: 3 lava-test-retry (timeout 00:08:10) [common]
10992 12:21:59.530985 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
10993 12:21:59.531111 Using namespace: common
10995 12:21:59.631514 / # #
10996 12:21:59.631623 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10997 12:21:59.631726 #<4>[ 19.313550] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10998 12:21:59.637062
10999 12:21:59.637324 Using /lava-11299277
11001 12:21:59.737649 / # export SHELL=/bin/sh
11002 12:21:59.737807 export SHELL=/bin/sh<4>[ 19.433286] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11003 12:21:59.742741
11005 12:21:59.843249 / # . /lava-11299277/environment
11006 12:21:59.854620 . /lava-11299277/environment<4>[ 19.553818] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11007 12:21:59.854712
11009 12:21:59.958895 / # /lava-11299277/bin/lava-test-runner /lava-11299277/0
11010 12:21:59.959014 Test shell timeout: 10s (minimum of the action and connection timeout)
11011 12:21:59.959353 <6>[ 19.579875] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11012 12:21:59.959434 <6>[ 19.585551] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11013 12:22:00.004869 /lava-11299277/bin/lava-test-runner /lava-11299277/0<3>[ 19.671366] mt7921e 0000:01:00.0: hardware init failed
11014 12:22:00.004957
11015 12:22:00.005043 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11016 12:22:00.005127 + cd /lava-11299277/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11017 12:22:00.005207 + cat uuid
11018 12:22:00.005286 + UUID=11299277_1.5.2.3.1
11019 12:22:00.005363 + set +x
11020 12:22:00.009783 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11299277_1.5.2.3.1>
11021 12:22:00.010060 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11299277_1.5.2.3.1
11022 12:22:00.010163 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11299277_1.5.2.3.1)
11023 12:22:00.010271 Skipping test definition patterns.
11024 12:22:00.013413 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11025 12:22:00.019775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11026 12:22:00.020034 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11028 12:22:00.026541 device: /dev/vide<4>[ 19.731088] use of bytesused == 0 is deprecated and will be removed in the future,
11029 12:22:00.030198 o2
11030 12:22:00.033449 <4>[ 19.739175] use the actual size instead.
11031 12:22:00.039634 <4>[ 19.745582] ------------[ cut here ]------------
11032 12:22:00.046363 <4>[ 19.750492] get_vaddr_frames() cannot follow VM_IO mapping
11033 12:22:00.056333 <4>[ 19.750626] WARNING: CPU: 1 PID: 316 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11034 12:22:00.105929 <4>[ 19.768735] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 mtk_vcodec_enc mtk_vcodec_common btusb mtk_vpu btintel r8153_ecm uvcvideo v4l2_mem2mem btmtk videobuf2_vmalloc videobuf2_dma_contig btrtl btbcm videobuf2_memops bluetooth cdc_ether videobuf2_v4l2 cros_ec_rpmsg videobuf2_common usbnet ecdh_generic videodev r8152 crct10dif_ce mc elants_i2c ecc hid_google_hammer sbs_battery elan_i2c rfkill cros_ec_typec cros_ec_chardev hid_vivaldi_common pcie_mediatek_gen3 mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11035 12:22:00.116172 <4>[ 19.818148] CPU: 1 PID: 316 Comm: v4l2-compliance Not tainted 6.1.45-cip3 #1
11036 12:22:00.119299 <4>[ 19.825447] Hardware name: Google Spherion (rev0 - 3) (DT)
11037 12:22:00.126025 <4>[ 19.831182] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11038 12:22:00.132702 <4>[ 19.838393] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11039 12:22:00.139200 <4>[ 19.844485] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11040 12:22:00.142761 <4>[ 19.850576] sp : ffff8000091c3850
11041 12:22:00.149344 <4>[ 19.854140] x29: ffff8000091c3850 x28: ffffbaedbf4c5000 x27: ffffbaedbf4c1238
11042 12:22:00.159168 <4>[ 19.861528] x26: 0000000000000000 x25: ffffbaee1762bfe0 x24: ffff73cd4f061298
11043 12:22:00.165904 <4>[ 19.868915] x23: ffff73cd49a95000 x22: ffff73cd40d48410 x21: 0000000000000000
11044 12:22:00.172228 <4>[ 19.876303] x20: 00000000fffffff2 x19: ffff73cd4aa83a00 x18: fffffffffffe9778
11045 12:22:00.178974 <4>[ 19.883690] x17: 0000000000000000 x16: ffffbaee1548bb90 x15: 0000000000000038
11046 12:22:00.188922 <4>[ 19.891078] x14: ffffbaee17f134a8 x13: 000000000000064e x12: 000000000000021a
11047 12:22:00.195380 <4>[ 19.898465] x11: fffffffffffe9778 x10: fffffffffffe9740 x9 : 00000000fffff21a
11048 12:22:00.202437 <4>[ 19.905852] x8 : ffffbaee17f134a8 x7 : ffffbaee17f6b4a8 x6 : 0000000000001938
11049 12:22:00.208466 <4>[ 19.913240] x5 : ffff73ce7ef2aa18 x4 : 00000000fffff21a x3 : ffffb8e0676d7000
11050 12:22:00.218703 <4>[ 19.920626] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff73cd4c90d880
11051 12:22:00.218786 <4>[ 19.928014] Call trace:
11052 12:22:00.225372 <4>[ 19.930711] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11053 12:22:00.232165 <4>[ 19.936456] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11054 12:22:00.238408 <4>[ 19.942459] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11055 12:22:00.245224 <4>[ 19.948812] __prepare_userptr+0x280/0x410 [videobuf2_common]
11056 12:22:00.248380 <4>[ 19.954816] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11057 12:22:00.255003 <4>[ 19.960473] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11058 12:22:00.261725 <4>[ 19.966652] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11059 12:22:00.268199 <4>[ 19.972153] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11060 12:22:00.274841 <4>[ 19.977929] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11061 12:22:00.278448 <4>[ 19.984194] v4l_prepare_buf+0x48/0x60 [videodev]
11062 12:22:00.284883 <4>[ 19.989224] __video_do_ioctl+0x184/0x3d0 [videodev]
11063 12:22:00.288336 <4>[ 19.994471] video_usercopy+0x358/0x680 [videodev]
11064 12:22:00.295154 <4>[ 19.999544] video_ioctl2+0x18/0x30 [videodev]
11065 12:22:00.298146 <4>[ 20.004271] v4l2_ioctl+0x40/0x60 [videodev]
11066 12:22:00.301454 <4>[ 20.008823] __arm64_sys_ioctl+0xa8/0xf0
11067 12:22:00.305446 <4>[ 20.013019] invoke_syscall+0x48/0x114
11068 12:22:00.311335 <4>[ 20.017024] el0_svc_common.constprop.0+0x44/0xec
11069 12:22:00.314809 <4>[ 20.021980] do_el0_svc+0x2c/0xd0
11070 12:22:00.317951 <4>[ 20.025547] el0_svc+0x2c/0x84
11071 12:22:00.321223 <4>[ 20.028856] el0t_64_sync_handler+0xb8/0xc0
11072 12:22:00.324866 <4>[ 20.033291] el0t_64_sync+0x18c/0x190
11073 12:22:00.331087 <4>[ 20.037205] ---[ end trace 0000000000000000 ]---
11074 12:22:00.343372 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11075 12:22:00.353440 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11076 12:22:00.360504
11077 12:22:00.375159 Compliance test for mtk-vcodec-enc device /dev/video2:
11078 12:22:00.382233
11079 12:22:00.398077 Driver Info:
11080 12:22:00.409907 Driver name : mtk-vcodec-enc
11081 12:22:00.427871 Card type : MT8192 video encoder
11082 12:22:00.439355 Bus info : platform:17020000.vcodec
11083 12:22:00.446727 Driver version : 6.1.45
11084 12:22:00.457743 Capabilities : 0x84204000
11085 12:22:00.473316 Video Memory-to-Memory Multiplanar
11086 12:22:00.483183 Streaming
11087 12:22:00.496605 Extended Pix Format
11088 12:22:00.509816 Device Capabilities
11089 12:22:00.521060 Device Caps : 0x04204000
11090 12:22:00.533173 Video Memory-to-Memory Multiplanar
11091 12:22:00.546154 Streaming
11092 12:22:00.561122 Extended Pix Format
11093 12:22:00.571479 Detected Stateful Encoder
11094 12:22:00.587382
11095 12:22:00.598408 Required ioctls:
11096 12:22:00.614130 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11097 12:22:00.614214 test VIDIOC_QUERYCAP: OK
11098 12:22:00.614465 Received signal: <TESTSET> START Required-ioctls
11099 12:22:00.614542 Starting test_set Required-ioctls
11100 12:22:00.637985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11101 12:22:00.638255 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11103 12:22:00.641184 test invalid ioctls: OK
11104 12:22:00.662442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11105 12:22:00.662527
11106 12:22:00.662762 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11108 12:22:00.672635 Allow for multiple opens:
11109 12:22:00.680532 <LAVA_SIGNAL_TESTSET STOP>
11110 12:22:00.680772 Received signal: <TESTSET> STOP
11111 12:22:00.680845 Closing test_set Required-ioctls
11112 12:22:00.689589 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11113 12:22:00.689841 Received signal: <TESTSET> START Allow-for-multiple-opens
11114 12:22:00.689910 Starting test_set Allow-for-multiple-opens
11115 12:22:00.693165 test second /dev/video2 open: OK
11116 12:22:00.713774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11117 12:22:00.714028 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11119 12:22:00.717275 test VIDIOC_QUERYCAP: OK
11120 12:22:00.740065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11121 12:22:00.740318 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11123 12:22:00.743120 test VIDIOC_G/S_PRIORITY: OK
11124 12:22:00.766095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11125 12:22:00.766346 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11127 12:22:00.769636 test for unlimited opens: OK
11128 12:22:00.790359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11129 12:22:00.790442
11130 12:22:00.790673 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11132 12:22:00.801191 Debug ioctls:
11133 12:22:00.809253 <LAVA_SIGNAL_TESTSET STOP>
11134 12:22:00.809503 Received signal: <TESTSET> STOP
11135 12:22:00.809572 Closing test_set Allow-for-multiple-opens
11136 12:22:00.818862 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11137 12:22:00.819112 Received signal: <TESTSET> START Debug-ioctls
11138 12:22:00.819181 Starting test_set Debug-ioctls
11139 12:22:00.821846 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11140 12:22:00.843232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11141 12:22:00.843484 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11143 12:22:00.849842 test VIDIOC_LOG_STATUS: OK (Not Supported)
11144 12:22:00.868242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11145 12:22:00.868326
11146 12:22:00.868559 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11148 12:22:00.881013 Input ioctls:
11149 12:22:00.890088 <LAVA_SIGNAL_TESTSET STOP>
11150 12:22:00.890340 Received signal: <TESTSET> STOP
11151 12:22:00.890406 Closing test_set Debug-ioctls
11152 12:22:00.899533 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11153 12:22:00.899783 Received signal: <TESTSET> START Input-ioctls
11154 12:22:00.899853 Starting test_set Input-ioctls
11155 12:22:00.903072 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11156 12:22:00.928674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11157 12:22:00.928933 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11159 12:22:00.931968 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11160 12:22:00.950208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11161 12:22:00.950457 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11163 12:22:00.956598 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11164 12:22:00.973717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11165 12:22:00.973967 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11167 12:22:00.980144 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11168 12:22:01.000456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11169 12:22:01.000706 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11171 12:22:01.003792 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11172 12:22:01.024473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11173 12:22:01.024723 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11175 12:22:01.027832 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11176 12:22:01.049981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11177 12:22:01.050232 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11179 12:22:01.053128 Inputs: 0 Audio Inputs: 0 Tuners: 0
11180 12:22:01.060846
11181 12:22:01.075559 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11182 12:22:01.097658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11183 12:22:01.097964 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11185 12:22:01.104302 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11186 12:22:01.125692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11187 12:22:01.125955 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11189 12:22:01.129204 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11190 12:22:01.149813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11191 12:22:01.150064 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11193 12:22:01.156142 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11194 12:22:01.175978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11195 12:22:01.176229 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11197 12:22:01.182343 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11198 12:22:01.200460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11199 12:22:01.200547
11200 12:22:01.200776 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11202 12:22:01.219809 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11203 12:22:01.241743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11204 12:22:01.241999 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11206 12:22:01.248216 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11207 12:22:01.271072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11208 12:22:01.271376 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11210 12:22:01.274403 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11211 12:22:01.293618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11212 12:22:01.293920 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11214 12:22:01.296778 test VIDIOC_G/S_EDID: OK (Not Supported)
11215 12:22:01.317693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11216 12:22:01.317775
11217 12:22:01.318009 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11219 12:22:01.328798 Control ioctls:
11220 12:22:01.336856 <LAVA_SIGNAL_TESTSET STOP>
11221 12:22:01.337105 Received signal: <TESTSET> STOP
11222 12:22:01.337174 Closing test_set Input-ioctls
11223 12:22:01.347396 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11224 12:22:01.347645 Received signal: <TESTSET> START Control-ioctls
11225 12:22:01.347714 Starting test_set Control-ioctls
11226 12:22:01.350603 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11227 12:22:01.375280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11228 12:22:01.375363 test VIDIOC_QUERYCTRL: OK
11229 12:22:01.375596 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11231 12:22:01.396372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11232 12:22:01.396623 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11234 12:22:01.399904 test VIDIOC_G/S_CTRL: OK
11235 12:22:01.422386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11236 12:22:01.422650 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11238 12:22:01.425540 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11239 12:22:01.452344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11240 12:22:01.452594 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11242 12:22:01.461773 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11243 12:22:01.464718 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11244 12:22:01.488701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11245 12:22:01.489003 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11247 12:22:01.492563 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11248 12:22:01.510483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11249 12:22:01.510783 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11251 12:22:01.513695 Standard Controls: 16 Private Controls: 0
11252 12:22:01.521225
11253 12:22:01.531003 Format ioctls:
11254 12:22:01.538150 <LAVA_SIGNAL_TESTSET STOP>
11255 12:22:01.538425 Received signal: <TESTSET> STOP
11256 12:22:01.538522 Closing test_set Control-ioctls
11257 12:22:01.547940 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11258 12:22:01.548190 Received signal: <TESTSET> START Format-ioctls
11259 12:22:01.548258 Starting test_set Format-ioctls
11260 12:22:01.551477 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11261 12:22:01.579837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11262 12:22:01.580088 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11264 12:22:01.582697 test VIDIOC_G/S_PARM: OK
11265 12:22:01.600325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11266 12:22:01.600575 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11268 12:22:01.603627 test VIDIOC_G_FBUF: OK (Not Supported)
11269 12:22:01.629488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11270 12:22:01.629739 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11272 12:22:01.632282 test VIDIOC_G_FMT: OK
11273 12:22:01.653788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11274 12:22:01.654092 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11276 12:22:01.657035 test VIDIOC_TRY_FMT: OK
11277 12:22:01.680852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11278 12:22:01.681155 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11280 12:22:01.690529 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11281 12:22:01.694390 test VIDIOC_S_FMT: FAIL
11282 12:22:01.721474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11283 12:22:01.721787 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11285 12:22:01.725144 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11286 12:22:01.759530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11287 12:22:01.759836 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11289 12:22:01.762739 test Cropping: OK
11290 12:22:01.792771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11291 12:22:01.793072 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11293 12:22:01.796553 test Composing: OK (Not Supported)
11294 12:22:01.821174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11295 12:22:01.821479 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11297 12:22:01.824543 test Scaling: OK (Not Supported)
11298 12:22:01.846354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11299 12:22:01.846479
11300 12:22:01.846768 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11302 12:22:01.855938 Codec ioctls:
11303 12:22:01.867316 <LAVA_SIGNAL_TESTSET STOP>
11304 12:22:01.867618 Received signal: <TESTSET> STOP
11305 12:22:01.867732 Closing test_set Format-ioctls
11306 12:22:01.877537 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11307 12:22:01.877840 Received signal: <TESTSET> START Codec-ioctls
11308 12:22:01.877957 Starting test_set Codec-ioctls
11309 12:22:01.880682 test VIDIOC_(TRY_)ENCODER_CMD: OK
11310 12:22:01.902995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11311 12:22:01.903303 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11313 12:22:01.909669 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11314 12:22:01.927964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11315 12:22:01.928259 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11317 12:22:01.934401 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11318 12:22:01.953703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11319 12:22:01.953828
11320 12:22:01.954117 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11322 12:22:01.964704 Buffer ioctls:
11323 12:22:01.971590 <LAVA_SIGNAL_TESTSET STOP>
11324 12:22:01.971886 Received signal: <TESTSET> STOP
11325 12:22:01.972003 Closing test_set Codec-ioctls
11326 12:22:01.981090 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11327 12:22:01.981393 Received signal: <TESTSET> START Buffer-ioctls
11328 12:22:01.981509 Starting test_set Buffer-ioctls
11329 12:22:01.984305 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11330 12:22:02.010383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11331 12:22:02.010509 test VIDIOC_EXPBUF: OK
11332 12:22:02.010799 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11334 12:22:02.036736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11335 12:22:02.037064 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11337 12:22:02.040073 test Requests: OK (Not Supported)
11338 12:22:02.059981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11339 12:22:02.060087
11340 12:22:02.060350 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11342 12:22:02.069500 Test input 0:
11343 12:22:02.084569
11344 12:22:02.094526 Streaming ioctls:
11345 12:22:02.102179 <LAVA_SIGNAL_TESTSET STOP>
11346 12:22:02.102430 Received signal: <TESTSET> STOP
11347 12:22:02.102497 Closing test_set Buffer-ioctls
11348 12:22:02.111376 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11349 12:22:02.111628 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11350 12:22:02.111699 Starting test_set Streaming-ioctls_Test-input-0
11351 12:22:02.114765 test read/write: OK (Not Supported)
11352 12:22:02.139229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11353 12:22:02.139544 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11355 12:22:02.145775 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11356 12:22:02.156480 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11357 12:22:02.161837 test blocking wait: FAIL
11358 12:22:02.189519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11359 12:22:02.189770 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11361 12:22:02.200025 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11362 12:22:02.203087 test MMAP (select): FAIL
11363 12:22:02.230848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11364 12:22:02.231101 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11366 12:22:02.237229 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11367 12:22:02.242127 test MMAP (epoll): FAIL
11368 12:22:02.270359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11369 12:22:02.270671 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11371 12:22:02.279909 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11372 12:22:02.291688 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11373 12:22:02.296678 test USERPTR (select): FAIL
11374 12:22:02.324100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11375 12:22:02.324380 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11377 12:22:02.330568 test DMABUF: Cannot test, specify --expbuf-device
11378 12:22:02.334357
11379 12:22:02.351749 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11380 12:22:02.356332 <LAVA_TEST_RUNNER EXIT>
11381 12:22:02.356587 ok: lava_test_shell seems to have completed
11382 12:22:02.356665 Marking unfinished test run as failed
11384 12:22:02.357580 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11385 12:22:02.357700 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11386 12:22:02.357789 end: 3 lava-test-retry (duration 00:00:03) [common]
11387 12:22:02.357876 start: 4 finalize (timeout 00:08:07) [common]
11388 12:22:02.357971 start: 4.1 power-off (timeout 00:00:30) [common]
11389 12:22:02.358122 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11390 12:22:02.433366 >> Command sent successfully.
11391 12:22:02.435882 Returned 0 in 0 seconds
11392 12:22:02.536252 end: 4.1 power-off (duration 00:00:00) [common]
11394 12:22:02.536560 start: 4.2 read-feedback (timeout 00:08:07) [common]
11395 12:22:02.536831 Listened to connection for namespace 'common' for up to 1s
11396 12:22:03.536872 Finalising connection for namespace 'common'
11397 12:22:03.537057 Disconnecting from shell: Finalise
11398 12:22:03.537138 / #
11399 12:22:03.637465 end: 4.2 read-feedback (duration 00:00:01) [common]
11400 12:22:03.637611 end: 4 finalize (duration 00:00:01) [common]
11401 12:22:03.637721 Cleaning after the job
11402 12:22:03.637823 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/ramdisk
11403 12:22:03.642092 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/kernel
11404 12:22:03.648434 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/dtb
11405 12:22:03.648596 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299277/tftp-deploy-4sizsku6/modules
11406 12:22:03.654043 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11299277
11407 12:22:03.709008 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11299277
11408 12:22:03.709189 Job finished correctly