Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 20
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 27
- Errors: 1
1 10:00:50.868660 lava-dispatcher, installed at version: 2023.06
2 10:00:50.868895 start: 0 validate
3 10:00:50.869046 Start time: 2023-08-23 10:00:50.869038+00:00 (UTC)
4 10:00:50.869188 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:50.869335 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 10:00:51.160410 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:51.161216 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:00:51.429459 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:00:51.429653 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:01:28.059497 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:01:28.060243 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:01:28.596364 validate duration: 37.73
14 10:01:28.597662 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:01:28.598217 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:01:28.598719 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:01:28.599402 Not decompressing ramdisk as can be used compressed.
18 10:01:28.599999 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 10:01:28.600400 saving as /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/ramdisk/rootfs.cpio.gz
20 10:01:28.600838 total size: 8181372 (7 MB)
21 10:01:32.086144 progress 0 % (0 MB)
22 10:01:32.098924 progress 5 % (0 MB)
23 10:01:32.110597 progress 10 % (0 MB)
24 10:01:32.119554 progress 15 % (1 MB)
25 10:01:32.125036 progress 20 % (1 MB)
26 10:01:32.129840 progress 25 % (1 MB)
27 10:01:32.133827 progress 30 % (2 MB)
28 10:01:32.137570 progress 35 % (2 MB)
29 10:01:32.140717 progress 40 % (3 MB)
30 10:01:32.143986 progress 45 % (3 MB)
31 10:01:32.146619 progress 50 % (3 MB)
32 10:01:32.149406 progress 55 % (4 MB)
33 10:01:32.151752 progress 60 % (4 MB)
34 10:01:32.154239 progress 65 % (5 MB)
35 10:01:32.156356 progress 70 % (5 MB)
36 10:01:32.158636 progress 75 % (5 MB)
37 10:01:32.160756 progress 80 % (6 MB)
38 10:01:32.162991 progress 85 % (6 MB)
39 10:01:32.165128 progress 90 % (7 MB)
40 10:01:32.167443 progress 95 % (7 MB)
41 10:01:32.169599 progress 100 % (7 MB)
42 10:01:32.169863 7 MB downloaded in 3.57 s (2.19 MB/s)
43 10:01:32.170056 end: 1.1.1 http-download (duration 00:00:04) [common]
45 10:01:32.170301 end: 1.1 download-retry (duration 00:00:04) [common]
46 10:01:32.170386 start: 1.2 download-retry (timeout 00:09:56) [common]
47 10:01:32.170467 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 10:01:32.170611 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:01:32.170681 saving as /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/kernel/Image
50 10:01:32.170739 total size: 49220096 (46 MB)
51 10:01:32.170798 No compression specified
52 10:01:32.171990 progress 0 % (0 MB)
53 10:01:32.184907 progress 5 % (2 MB)
54 10:01:32.197765 progress 10 % (4 MB)
55 10:01:32.210611 progress 15 % (7 MB)
56 10:01:32.223320 progress 20 % (9 MB)
57 10:01:32.235927 progress 25 % (11 MB)
58 10:01:32.248778 progress 30 % (14 MB)
59 10:01:32.261499 progress 35 % (16 MB)
60 10:01:32.274459 progress 40 % (18 MB)
61 10:01:32.287331 progress 45 % (21 MB)
62 10:01:32.300260 progress 50 % (23 MB)
63 10:01:32.312883 progress 55 % (25 MB)
64 10:01:32.325640 progress 60 % (28 MB)
65 10:01:32.338228 progress 65 % (30 MB)
66 10:01:32.350931 progress 70 % (32 MB)
67 10:01:32.363854 progress 75 % (35 MB)
68 10:01:32.376682 progress 80 % (37 MB)
69 10:01:32.389356 progress 85 % (39 MB)
70 10:01:32.402195 progress 90 % (42 MB)
71 10:01:32.415014 progress 95 % (44 MB)
72 10:01:32.427533 progress 100 % (46 MB)
73 10:01:32.427729 46 MB downloaded in 0.26 s (182.66 MB/s)
74 10:01:32.427886 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:01:32.428119 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:01:32.428207 start: 1.3 download-retry (timeout 00:09:56) [common]
78 10:01:32.428291 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 10:01:32.428490 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:01:32.428562 saving as /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/dtb/mt8192-asurada-spherion-r0.dtb
81 10:01:32.428623 total size: 47278 (0 MB)
82 10:01:32.428682 No compression specified
83 10:01:32.429788 progress 69 % (0 MB)
84 10:01:32.430062 progress 100 % (0 MB)
85 10:01:32.430215 0 MB downloaded in 0.00 s (28.35 MB/s)
86 10:01:32.430334 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:01:32.430560 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:01:32.430643 start: 1.4 download-retry (timeout 00:09:56) [common]
90 10:01:32.430723 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 10:01:32.430840 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:01:32.430907 saving as /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/modules/modules.tar
93 10:01:32.430966 total size: 8617228 (8 MB)
94 10:01:32.431025 Using unxz to decompress xz
95 10:01:32.435074 progress 0 % (0 MB)
96 10:01:32.457245 progress 5 % (0 MB)
97 10:01:32.479977 progress 10 % (0 MB)
98 10:01:32.506961 progress 15 % (1 MB)
99 10:01:32.534297 progress 20 % (1 MB)
100 10:01:32.560143 progress 25 % (2 MB)
101 10:01:32.587126 progress 30 % (2 MB)
102 10:01:32.614231 progress 35 % (2 MB)
103 10:01:32.639430 progress 40 % (3 MB)
104 10:01:32.664278 progress 45 % (3 MB)
105 10:01:32.690655 progress 50 % (4 MB)
106 10:01:32.716459 progress 55 % (4 MB)
107 10:01:32.742505 progress 60 % (4 MB)
108 10:01:32.766487 progress 65 % (5 MB)
109 10:01:32.794238 progress 70 % (5 MB)
110 10:01:32.818519 progress 75 % (6 MB)
111 10:01:32.845574 progress 80 % (6 MB)
112 10:01:32.875683 progress 85 % (7 MB)
113 10:01:32.902390 progress 90 % (7 MB)
114 10:01:32.926642 progress 95 % (7 MB)
115 10:01:32.949920 progress 100 % (8 MB)
116 10:01:32.956992 8 MB downloaded in 0.53 s (15.62 MB/s)
117 10:01:32.957254 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:01:32.957578 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:01:32.957674 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 10:01:32.957772 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 10:01:32.957880 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:01:32.957981 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 10:01:32.958212 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0
125 10:01:32.958356 makedir: /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin
126 10:01:32.958476 makedir: /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/tests
127 10:01:32.958619 makedir: /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/results
128 10:01:32.958737 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-add-keys
129 10:01:32.958887 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-add-sources
130 10:01:32.959024 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-background-process-start
131 10:01:32.959155 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-background-process-stop
132 10:01:32.959284 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-common-functions
133 10:01:32.959409 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-echo-ipv4
134 10:01:32.959534 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-install-packages
135 10:01:32.959709 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-installed-packages
136 10:01:32.959894 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-os-build
137 10:01:32.960028 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-probe-channel
138 10:01:32.960155 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-probe-ip
139 10:01:32.960281 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-target-ip
140 10:01:32.960418 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-target-mac
141 10:01:32.960600 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-target-storage
142 10:01:32.960805 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-test-case
143 10:01:32.961000 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-test-event
144 10:01:32.961188 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-test-feedback
145 10:01:32.961387 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-test-raise
146 10:01:32.961620 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-test-reference
147 10:01:32.961803 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-test-runner
148 10:01:32.961999 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-test-set
149 10:01:32.962214 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-test-shell
150 10:01:32.962403 Updating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-install-packages (oe)
151 10:01:32.962631 Updating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/bin/lava-installed-packages (oe)
152 10:01:32.962827 Creating /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/environment
153 10:01:32.962984 LAVA metadata
154 10:01:32.963114 - LAVA_JOB_ID=11336429
155 10:01:32.963222 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:01:32.963392 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 10:01:32.963511 skipped lava-vland-overlay
158 10:01:32.963675 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:01:32.963816 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 10:01:32.963936 skipped lava-multinode-overlay
161 10:01:32.964052 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:01:32.964193 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 10:01:32.964325 Loading test definitions
164 10:01:32.964468 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 10:01:32.964593 Using /lava-11336429 at stage 0
166 10:01:32.965119 uuid=11336429_1.5.2.3.1 testdef=None
167 10:01:32.965250 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:01:32.965385 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 10:01:32.966247 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:01:32.966634 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 10:01:32.967725 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:01:32.968087 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 10:01:32.969065 runner path: /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/0/tests/0_dmesg test_uuid 11336429_1.5.2.3.1
176 10:01:32.969283 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:01:32.969647 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:56) [common]
179 10:01:32.969768 Using /lava-11336429 at stage 1
180 10:01:32.970242 uuid=11336429_1.5.2.3.5 testdef=None
181 10:01:32.970380 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 10:01:32.970512 start: 1.5.2.3.6 test-overlay (timeout 00:09:56) [common]
183 10:01:32.971273 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 10:01:32.971657 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:56) [common]
186 10:01:32.973294 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 10:01:32.973684 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:56) [common]
189 10:01:32.974673 runner path: /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/1/tests/1_bootrr test_uuid 11336429_1.5.2.3.5
190 10:01:32.974900 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 10:01:32.975233 Creating lava-test-runner.conf files
193 10:01:32.975362 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/0 for stage 0
194 10:01:32.975497 - 0_dmesg
195 10:01:32.975657 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11336429/lava-overlay-nwp539v0/lava-11336429/1 for stage 1
196 10:01:32.975808 - 1_bootrr
197 10:01:32.975950 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 10:01:32.976087 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
199 10:01:32.988453 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 10:01:32.988637 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
201 10:01:32.988777 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 10:01:32.988917 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 10:01:32.989060 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
204 10:01:33.256880 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 10:01:33.257266 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
206 10:01:33.257387 extracting modules file /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11336429/extract-overlay-ramdisk-oi1zhequ/ramdisk
207 10:01:33.503307 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 10:01:33.503482 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
209 10:01:33.503650 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11336429/compress-overlay-0y7pu62l/overlay-1.5.2.4.tar.gz to ramdisk
210 10:01:33.503748 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11336429/compress-overlay-0y7pu62l/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11336429/extract-overlay-ramdisk-oi1zhequ/ramdisk
211 10:01:33.512272 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 10:01:33.512421 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
213 10:01:33.512529 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 10:01:33.512636 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
215 10:01:33.512727 Building ramdisk /var/lib/lava/dispatcher/tmp/11336429/extract-overlay-ramdisk-oi1zhequ/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11336429/extract-overlay-ramdisk-oi1zhequ/ramdisk
216 10:01:33.982057 >> 145125 blocks
217 10:01:36.340762 rename /var/lib/lava/dispatcher/tmp/11336429/extract-overlay-ramdisk-oi1zhequ/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/ramdisk/ramdisk.cpio.gz
218 10:01:36.341199 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 10:01:36.341322 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
220 10:01:36.341427 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
221 10:01:36.341544 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/kernel/Image'
222 10:01:50.166744 Returned 0 in 13 seconds
223 10:01:50.267392 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/kernel/image.itb
224 10:01:50.671791 output: FIT description: Kernel Image image with one or more FDT blobs
225 10:01:50.672157 output: Created: Wed Aug 23 11:01:50 2023
226 10:01:50.672259 output: Image 0 (kernel-1)
227 10:01:50.672350 output: Description:
228 10:01:50.672435 output: Created: Wed Aug 23 11:01:50 2023
229 10:01:50.672515 output: Type: Kernel Image
230 10:01:50.672597 output: Compression: lzma compressed
231 10:01:50.672691 output: Data Size: 11037260 Bytes = 10778.57 KiB = 10.53 MiB
232 10:01:50.672791 output: Architecture: AArch64
233 10:01:50.672892 output: OS: Linux
234 10:01:50.672989 output: Load Address: 0x00000000
235 10:01:50.673081 output: Entry Point: 0x00000000
236 10:01:50.673172 output: Hash algo: crc32
237 10:01:50.673263 output: Hash value: 17b65cb3
238 10:01:50.673353 output: Image 1 (fdt-1)
239 10:01:50.673444 output: Description: mt8192-asurada-spherion-r0
240 10:01:50.673535 output: Created: Wed Aug 23 11:01:50 2023
241 10:01:50.673626 output: Type: Flat Device Tree
242 10:01:50.673716 output: Compression: uncompressed
243 10:01:50.673806 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 10:01:50.673896 output: Architecture: AArch64
245 10:01:50.673986 output: Hash algo: crc32
246 10:01:50.674076 output: Hash value: cc4352de
247 10:01:50.674166 output: Image 2 (ramdisk-1)
248 10:01:50.674256 output: Description: unavailable
249 10:01:50.674345 output: Created: Wed Aug 23 11:01:50 2023
250 10:01:50.674435 output: Type: RAMDisk Image
251 10:01:50.674524 output: Compression: Unknown Compression
252 10:01:50.674613 output: Data Size: 21375458 Bytes = 20874.47 KiB = 20.39 MiB
253 10:01:50.674703 output: Architecture: AArch64
254 10:01:50.674793 output: OS: Linux
255 10:01:50.674882 output: Load Address: unavailable
256 10:01:50.674971 output: Entry Point: unavailable
257 10:01:50.675060 output: Hash algo: crc32
258 10:01:50.675149 output: Hash value: 8a836dd6
259 10:01:50.675238 output: Default Configuration: 'conf-1'
260 10:01:50.675327 output: Configuration 0 (conf-1)
261 10:01:50.675415 output: Description: mt8192-asurada-spherion-r0
262 10:01:50.675505 output: Kernel: kernel-1
263 10:01:50.675601 output: Init Ramdisk: ramdisk-1
264 10:01:50.675727 output: FDT: fdt-1
265 10:01:50.675817 output: Loadables: kernel-1
266 10:01:50.675906 output:
267 10:01:50.676160 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 10:01:50.676303 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 10:01:50.676452 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
270 10:01:50.676591 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
271 10:01:50.676705 No LXC device requested
272 10:01:50.676829 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 10:01:50.676957 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
274 10:01:50.677075 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 10:01:50.677184 Checking files for TFTP limit of 4294967296 bytes.
276 10:01:50.677857 end: 1 tftp-deploy (duration 00:00:22) [common]
277 10:01:50.677991 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 10:01:50.678121 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 10:01:50.678290 substitutions:
280 10:01:50.678385 - {DTB}: 11336429/tftp-deploy-fwpr3tbr/dtb/mt8192-asurada-spherion-r0.dtb
281 10:01:50.678486 - {INITRD}: 11336429/tftp-deploy-fwpr3tbr/ramdisk/ramdisk.cpio.gz
282 10:01:50.678583 - {KERNEL}: 11336429/tftp-deploy-fwpr3tbr/kernel/Image
283 10:01:50.678678 - {LAVA_MAC}: None
284 10:01:50.678773 - {PRESEED_CONFIG}: None
285 10:01:50.678866 - {PRESEED_LOCAL}: None
286 10:01:50.678959 - {RAMDISK}: 11336429/tftp-deploy-fwpr3tbr/ramdisk/ramdisk.cpio.gz
287 10:01:50.679052 - {ROOT_PART}: None
288 10:01:50.679144 - {ROOT}: None
289 10:01:50.679237 - {SERVER_IP}: 192.168.201.1
290 10:01:50.679328 - {TEE}: None
291 10:01:50.679420 Parsed boot commands:
292 10:01:50.679510 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 10:01:50.679794 Parsed boot commands: tftpboot 192.168.201.1 11336429/tftp-deploy-fwpr3tbr/kernel/image.itb 11336429/tftp-deploy-fwpr3tbr/kernel/cmdline
294 10:01:50.679920 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 10:01:50.680049 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 10:01:50.680182 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 10:01:50.680313 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 10:01:50.680395 Not connected, no need to disconnect.
299 10:01:50.680493 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 10:01:50.680593 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 10:01:50.680673 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
302 10:01:50.684748 Setting prompt string to ['lava-test: # ']
303 10:01:50.685187 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 10:01:50.685320 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 10:01:50.685456 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 10:01:50.685710 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 10:01:50.685964 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 10:01:55.820486 >> Command sent successfully.
309 10:01:55.824531 Returned 0 in 5 seconds
310 10:01:55.924931 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 10:01:55.925312 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 10:01:55.925430 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 10:01:55.925560 Setting prompt string to 'Starting depthcharge on Spherion...'
315 10:01:55.925662 Changing prompt to 'Starting depthcharge on Spherion...'
316 10:01:55.925748 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 10:01:55.926116 [Enter `^Ec?' for help]
318 10:01:56.097647
319 10:01:56.097795
320 10:01:56.097889 F0: 102B 0000
321 10:01:56.097972
322 10:01:56.098052 F3: 1001 0000 [0200]
323 10:01:56.098130
324 10:01:56.100842 F3: 1001 0000
325 10:01:56.100925
326 10:01:56.101032 F7: 102D 0000
327 10:01:56.101094
328 10:01:56.101151 F1: 0000 0000
329 10:01:56.101207
330 10:01:56.104090 V0: 0000 0000 [0001]
331 10:01:56.104171
332 10:01:56.104236 00: 0007 8000
333 10:01:56.104300
334 10:01:56.107457 01: 0000 0000
335 10:01:56.107540
336 10:01:56.107631 BP: 0C00 0209 [0000]
337 10:01:56.107705
338 10:01:56.111283 G0: 1182 0000
339 10:01:56.111390
340 10:01:56.111482 EC: 0000 0021 [4000]
341 10:01:56.111570
342 10:01:56.114583 S7: 0000 0000 [0000]
343 10:01:56.114664
344 10:01:56.114730 CC: 0000 0000 [0001]
345 10:01:56.114791
346 10:01:56.118160 T0: 0000 0040 [010F]
347 10:01:56.118242
348 10:01:56.118307 Jump to BL
349 10:01:56.118367
350 10:01:56.144291
351 10:01:56.144402
352 10:01:56.144468
353 10:01:56.151243 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 10:01:56.155013 ARM64: Exception handlers installed.
355 10:01:56.158153 ARM64: Testing exception
356 10:01:56.161991 ARM64: Done test exception
357 10:01:56.168868 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 10:01:56.178721 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 10:01:56.185866 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 10:01:56.195745 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 10:01:56.202797 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 10:01:56.208805 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 10:01:56.221332 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 10:01:56.227630 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 10:01:56.246667 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 10:01:56.250273 WDT: Last reset was cold boot
367 10:01:56.253259 SPI1(PAD0) initialized at 2873684 Hz
368 10:01:56.256632 SPI5(PAD0) initialized at 992727 Hz
369 10:01:56.260007 VBOOT: Loading verstage.
370 10:01:56.266604 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 10:01:56.271145 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 10:01:56.274573 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 10:01:56.277361 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 10:01:56.284528 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 10:01:56.290904 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 10:01:56.302344 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 10:01:56.302431
378 10:01:56.302496
379 10:01:56.312779 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 10:01:56.315909 ARM64: Exception handlers installed.
381 10:01:56.315994 ARM64: Testing exception
382 10:01:56.319081 ARM64: Done test exception
383 10:01:56.322481 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 10:01:56.329212 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 10:01:56.342563 Probing TPM: . done!
386 10:01:56.342646 TPM ready after 0 ms
387 10:01:56.350291 Connected to device vid:did:rid of 1ae0:0028:00
388 10:01:56.357381 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 10:01:56.416495 Initialized TPM device CR50 revision 0
390 10:01:56.427853 tlcl_send_startup: Startup return code is 0
391 10:01:56.427966 TPM: setup succeeded
392 10:01:56.438931 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 10:01:56.448252 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 10:01:56.462564 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 10:01:56.469895 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 10:01:56.473165 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 10:01:56.477283 in-header: 03 07 00 00 08 00 00 00
398 10:01:56.481065 in-data: aa e4 47 04 13 02 00 00
399 10:01:56.481208 Chrome EC: UHEPI supported
400 10:01:56.488362 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 10:01:56.491569 in-header: 03 95 00 00 08 00 00 00
402 10:01:56.495347 in-data: 18 20 20 08 00 00 00 00
403 10:01:56.495530 Phase 1
404 10:01:56.499089 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 10:01:56.506873 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 10:01:56.510576 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 10:01:56.514209 Recovery requested (1009000e)
408 10:01:56.523738 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 10:01:56.529474 tlcl_extend: response is 0
410 10:01:56.538800 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 10:01:56.544247 tlcl_extend: response is 0
412 10:01:56.551886 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 10:01:56.571285 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 10:01:56.578353 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 10:01:56.578769
416 10:01:56.579075
417 10:01:56.587976 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 10:01:56.591981 ARM64: Exception handlers installed.
419 10:01:56.594809 ARM64: Testing exception
420 10:01:56.595343 ARM64: Done test exception
421 10:01:56.616774 pmic_efuse_setting: Set efuses in 11 msecs
422 10:01:56.620588 pmwrap_interface_init: Select PMIF_VLD_RDY
423 10:01:56.626938 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 10:01:56.630670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 10:01:56.637869 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 10:01:56.642191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 10:01:56.645827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 10:01:56.649127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 10:01:56.656876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 10:01:56.660270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 10:01:56.663825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 10:01:56.667896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 10:01:56.674915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 10:01:56.678922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 10:01:56.682964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 10:01:56.689895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 10:01:56.693815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 10:01:56.701013 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 10:01:56.704694 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 10:01:56.712260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 10:01:56.716176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 10:01:56.723926 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 10:01:56.726986 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 10:01:56.734781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 10:01:56.738438 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 10:01:56.745542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 10:01:56.749749 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 10:01:56.756857 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 10:01:56.760505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 10:01:56.767995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 10:01:56.771701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 10:01:56.775112 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 10:01:56.782200 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 10:01:56.786401 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 10:01:56.789671 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 10:01:56.797314 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 10:01:56.800757 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 10:01:56.804405 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 10:01:56.812047 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 10:01:56.815738 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 10:01:56.820121 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 10:01:56.823029 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 10:01:56.830957 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 10:01:56.834534 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 10:01:56.837914 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 10:01:56.841511 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 10:01:56.845533 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 10:01:56.853132 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 10:01:56.856712 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 10:01:56.859837 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 10:01:56.863700 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 10:01:56.867659 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 10:01:56.870608 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 10:01:56.881965 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 10:01:56.889698 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 10:01:56.893483 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 10:01:56.900832 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 10:01:56.911513 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 10:01:56.915654 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 10:01:56.919353 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 10:01:56.922554 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 10:01:56.930824 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xe
483 10:01:56.934017 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 10:01:56.942253 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 10:01:56.945687 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 10:01:56.954886 [RTC]rtc_get_frequency_meter,154: input=15, output=759
487 10:01:56.963952 [RTC]rtc_get_frequency_meter,154: input=23, output=943
488 10:01:56.973295 [RTC]rtc_get_frequency_meter,154: input=19, output=850
489 10:01:56.983473 [RTC]rtc_get_frequency_meter,154: input=17, output=805
490 10:01:56.993342 [RTC]rtc_get_frequency_meter,154: input=16, output=780
491 10:01:57.002434 [RTC]rtc_get_frequency_meter,154: input=16, output=782
492 10:01:57.012055 [RTC]rtc_get_frequency_meter,154: input=17, output=803
493 10:01:57.015856 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 10:01:57.018869 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 10:01:57.023510 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 10:01:57.030435 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
497 10:01:57.034422 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 10:01:57.038145 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 10:01:57.042074 ADC[4]: Raw value=906573 ID=7
500 10:01:57.042500 ADC[3]: Raw value=213441 ID=1
501 10:01:57.045283 RAM Code: 0x71
502 10:01:57.049392 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 10:01:57.052537 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 10:01:57.063955 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 10:01:57.067828 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 10:01:57.071501 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 10:01:57.075676 in-header: 03 07 00 00 08 00 00 00
508 10:01:57.079443 in-data: aa e4 47 04 13 02 00 00
509 10:01:57.083249 Chrome EC: UHEPI supported
510 10:01:57.090705 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 10:01:57.094899 in-header: 03 95 00 00 08 00 00 00
512 10:01:57.095470 in-data: 18 20 20 08 00 00 00 00
513 10:01:57.098618 MRC: failed to locate region type 0.
514 10:01:57.106279 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 10:01:57.109627 DRAM-K: Running full calibration
516 10:01:57.113443 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 10:01:57.117123 header.status = 0x0
518 10:01:57.121286 header.version = 0x6 (expected: 0x6)
519 10:01:57.124823 header.size = 0xd00 (expected: 0xd00)
520 10:01:57.125329 header.flags = 0x0
521 10:01:57.131488 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 10:01:57.150430 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
523 10:01:57.157416 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 10:01:57.157901 dram_init: ddr_geometry: 2
525 10:01:57.161520 [EMI] MDL number = 2
526 10:01:57.161963 [EMI] Get MDL freq = 0
527 10:01:57.165316 dram_init: ddr_type: 0
528 10:01:57.168530 is_discrete_lpddr4: 1
529 10:01:57.169039 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 10:01:57.169394
531 10:01:57.172554
532 10:01:57.173069 [Bian_co] ETT version 0.0.0.1
533 10:01:57.176409 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 10:01:57.180184
535 10:01:57.183743 dramc_set_vcore_voltage set vcore to 650000
536 10:01:57.184322 Read voltage for 800, 4
537 10:01:57.184683 Vio18 = 0
538 10:01:57.187500 Vcore = 650000
539 10:01:57.188037 Vdram = 0
540 10:01:57.188394 Vddq = 0
541 10:01:57.188714 Vmddr = 0
542 10:01:57.191366 dram_init: config_dvfs: 1
543 10:01:57.195352 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 10:01:57.202029 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 10:01:57.206283 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 10:01:57.210196 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 10:01:57.213125 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 10:01:57.216408 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 10:01:57.220590 MEM_TYPE=3, freq_sel=18
550 10:01:57.224171 sv_algorithm_assistance_LP4_1600
551 10:01:57.228272 ============ PULL DRAM RESETB DOWN ============
552 10:01:57.231098 ========== PULL DRAM RESETB DOWN end =========
553 10:01:57.234992 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 10:01:57.238675 ===================================
555 10:01:57.242183 LPDDR4 DRAM CONFIGURATION
556 10:01:57.246154 ===================================
557 10:01:57.246581 EX_ROW_EN[0] = 0x0
558 10:01:57.249640 EX_ROW_EN[1] = 0x0
559 10:01:57.250064 LP4Y_EN = 0x0
560 10:01:57.253766 WORK_FSP = 0x0
561 10:01:57.254298 WL = 0x2
562 10:01:57.254639 RL = 0x2
563 10:01:57.257123 BL = 0x2
564 10:01:57.257658 RPST = 0x0
565 10:01:57.260289 RD_PRE = 0x0
566 10:01:57.260749 WR_PRE = 0x1
567 10:01:57.263429 WR_PST = 0x0
568 10:01:57.266736 DBI_WR = 0x0
569 10:01:57.267160 DBI_RD = 0x0
570 10:01:57.269903 OTF = 0x1
571 10:01:57.273302 ===================================
572 10:01:57.277237 ===================================
573 10:01:57.277660 ANA top config
574 10:01:57.280724 ===================================
575 10:01:57.284073 DLL_ASYNC_EN = 0
576 10:01:57.284609 ALL_SLAVE_EN = 1
577 10:01:57.287207 NEW_RANK_MODE = 1
578 10:01:57.290075 DLL_IDLE_MODE = 1
579 10:01:57.293792 LP45_APHY_COMB_EN = 1
580 10:01:57.297645 TX_ODT_DIS = 1
581 10:01:57.298182 NEW_8X_MODE = 1
582 10:01:57.300341 ===================================
583 10:01:57.304127 ===================================
584 10:01:57.307274 data_rate = 1600
585 10:01:57.310593 CKR = 1
586 10:01:57.313777 DQ_P2S_RATIO = 8
587 10:01:57.317912 ===================================
588 10:01:57.321096 CA_P2S_RATIO = 8
589 10:01:57.321627 DQ_CA_OPEN = 0
590 10:01:57.324111 DQ_SEMI_OPEN = 0
591 10:01:57.327750 CA_SEMI_OPEN = 0
592 10:01:57.330747 CA_FULL_RATE = 0
593 10:01:57.334180 DQ_CKDIV4_EN = 1
594 10:01:57.334706 CA_CKDIV4_EN = 1
595 10:01:57.338097 CA_PREDIV_EN = 0
596 10:01:57.340887 PH8_DLY = 0
597 10:01:57.344088 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 10:01:57.347868 DQ_AAMCK_DIV = 4
599 10:01:57.351244 CA_AAMCK_DIV = 4
600 10:01:57.351712 CA_ADMCK_DIV = 4
601 10:01:57.354656 DQ_TRACK_CA_EN = 0
602 10:01:57.357897 CA_PICK = 800
603 10:01:57.360874 CA_MCKIO = 800
604 10:01:57.364683 MCKIO_SEMI = 0
605 10:01:57.368268 PLL_FREQ = 3068
606 10:01:57.368804 DQ_UI_PI_RATIO = 32
607 10:01:57.372061 CA_UI_PI_RATIO = 0
608 10:01:57.375897 ===================================
609 10:01:57.380110 ===================================
610 10:01:57.380645 memory_type:LPDDR4
611 10:01:57.383261 GP_NUM : 10
612 10:01:57.387371 SRAM_EN : 1
613 10:01:57.387960 MD32_EN : 0
614 10:01:57.391186 ===================================
615 10:01:57.394387 [ANA_INIT] >>>>>>>>>>>>>>
616 10:01:57.394813 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 10:01:57.398757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 10:01:57.402018 ===================================
619 10:01:57.405110 data_rate = 1600,PCW = 0X7600
620 10:01:57.408330 ===================================
621 10:01:57.412326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 10:01:57.418864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 10:01:57.422319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 10:01:57.429369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 10:01:57.431980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 10:01:57.435294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 10:01:57.435763 [ANA_INIT] flow start
628 10:01:57.438573 [ANA_INIT] PLL >>>>>>>>
629 10:01:57.442612 [ANA_INIT] PLL <<<<<<<<
630 10:01:57.443104 [ANA_INIT] MIDPI >>>>>>>>
631 10:01:57.445998 [ANA_INIT] MIDPI <<<<<<<<
632 10:01:57.449272 [ANA_INIT] DLL >>>>>>>>
633 10:01:57.449790 [ANA_INIT] flow end
634 10:01:57.455716 ============ LP4 DIFF to SE enter ============
635 10:01:57.459476 ============ LP4 DIFF to SE exit ============
636 10:01:57.460022 [ANA_INIT] <<<<<<<<<<<<<
637 10:01:57.462303 [Flow] Enable top DCM control >>>>>
638 10:01:57.465535 [Flow] Enable top DCM control <<<<<
639 10:01:57.469541 Enable DLL master slave shuffle
640 10:01:57.475807 ==============================================================
641 10:01:57.476247 Gating Mode config
642 10:01:57.482118 ==============================================================
643 10:01:57.485793 Config description:
644 10:01:57.496245 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 10:01:57.502529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 10:01:57.505898 SELPH_MODE 0: By rank 1: By Phase
647 10:01:57.512592 ==============================================================
648 10:01:57.516082 GAT_TRACK_EN = 1
649 10:01:57.516501 RX_GATING_MODE = 2
650 10:01:57.519368 RX_GATING_TRACK_MODE = 2
651 10:01:57.522870 SELPH_MODE = 1
652 10:01:57.526029 PICG_EARLY_EN = 1
653 10:01:57.529791 VALID_LAT_VALUE = 1
654 10:01:57.536397 ==============================================================
655 10:01:57.539705 Enter into Gating configuration >>>>
656 10:01:57.543265 Exit from Gating configuration <<<<
657 10:01:57.546344 Enter into DVFS_PRE_config >>>>>
658 10:01:57.556405 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 10:01:57.559470 Exit from DVFS_PRE_config <<<<<
660 10:01:57.562609 Enter into PICG configuration >>>>
661 10:01:57.566562 Exit from PICG configuration <<<<
662 10:01:57.570018 [RX_INPUT] configuration >>>>>
663 10:01:57.570503 [RX_INPUT] configuration <<<<<
664 10:01:57.576526 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 10:01:57.579778 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 10:01:57.586546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 10:01:57.592897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 10:01:57.599722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 10:01:57.606797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 10:01:57.609955 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 10:01:57.613292 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 10:01:57.616307 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 10:01:57.623121 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 10:01:57.626512 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 10:01:57.629881 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 10:01:57.633346 ===================================
677 10:01:57.637052 LPDDR4 DRAM CONFIGURATION
678 10:01:57.639878 ===================================
679 10:01:57.643504 EX_ROW_EN[0] = 0x0
680 10:01:57.644105 EX_ROW_EN[1] = 0x0
681 10:01:57.646626 LP4Y_EN = 0x0
682 10:01:57.647042 WORK_FSP = 0x0
683 10:01:57.649979 WL = 0x2
684 10:01:57.650398 RL = 0x2
685 10:01:57.653197 BL = 0x2
686 10:01:57.653614 RPST = 0x0
687 10:01:57.656567 RD_PRE = 0x0
688 10:01:57.656983 WR_PRE = 0x1
689 10:01:57.659870 WR_PST = 0x0
690 10:01:57.660288 DBI_WR = 0x0
691 10:01:57.663141 DBI_RD = 0x0
692 10:01:57.663559 OTF = 0x1
693 10:01:57.666508 ===================================
694 10:01:57.670407 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 10:01:57.676979 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 10:01:57.680256 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 10:01:57.683318 ===================================
698 10:01:57.687233 LPDDR4 DRAM CONFIGURATION
699 10:01:57.690006 ===================================
700 10:01:57.690387 EX_ROW_EN[0] = 0x10
701 10:01:57.693308 EX_ROW_EN[1] = 0x0
702 10:01:57.697239 LP4Y_EN = 0x0
703 10:01:57.697753 WORK_FSP = 0x0
704 10:01:57.699944 WL = 0x2
705 10:01:57.700358 RL = 0x2
706 10:01:57.703741 BL = 0x2
707 10:01:57.704138 RPST = 0x0
708 10:01:57.706710 RD_PRE = 0x0
709 10:01:57.707223 WR_PRE = 0x1
710 10:01:57.710112 WR_PST = 0x0
711 10:01:57.710532 DBI_WR = 0x0
712 10:01:57.713421 DBI_RD = 0x0
713 10:01:57.713932 OTF = 0x1
714 10:01:57.717237 ===================================
715 10:01:57.723799 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 10:01:57.727571 nWR fixed to 40
717 10:01:57.730931 [ModeRegInit_LP4] CH0 RK0
718 10:01:57.731350 [ModeRegInit_LP4] CH0 RK1
719 10:01:57.734074 [ModeRegInit_LP4] CH1 RK0
720 10:01:57.737603 [ModeRegInit_LP4] CH1 RK1
721 10:01:57.738126 match AC timing 13
722 10:01:57.744183 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 10:01:57.747631 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 10:01:57.750946 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 10:01:57.757640 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 10:01:57.761010 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 10:01:57.761491 [EMI DOE] emi_dcm 0
728 10:01:57.767299 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 10:01:57.767714 ==
730 10:01:57.770597 Dram Type= 6, Freq= 0, CH_0, rank 0
731 10:01:57.774558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 10:01:57.774942 ==
733 10:01:57.781327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 10:01:57.784564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 10:01:57.795415 [CA 0] Center 36 (6~67) winsize 62
736 10:01:57.798138 [CA 1] Center 36 (6~67) winsize 62
737 10:01:57.802188 [CA 2] Center 34 (4~65) winsize 62
738 10:01:57.804811 [CA 3] Center 34 (4~64) winsize 61
739 10:01:57.808117 [CA 4] Center 33 (2~64) winsize 63
740 10:01:57.811932 [CA 5] Center 32 (2~62) winsize 61
741 10:01:57.812451
742 10:01:57.815204 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 10:01:57.815656
744 10:01:57.818394 [CATrainingPosCal] consider 1 rank data
745 10:01:57.822207 u2DelayCellTimex100 = 270/100 ps
746 10:01:57.825058 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
747 10:01:57.828255 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
748 10:01:57.832201 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
749 10:01:57.838891 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
750 10:01:57.842096 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
751 10:01:57.845301 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
752 10:01:57.845768
753 10:01:57.848623 CA PerBit enable=1, Macro0, CA PI delay=32
754 10:01:57.849113
755 10:01:57.851897 [CBTSetCACLKResult] CA Dly = 32
756 10:01:57.852366 CS Dly: 4 (0~35)
757 10:01:57.852693 ==
758 10:01:57.855349 Dram Type= 6, Freq= 0, CH_0, rank 1
759 10:01:57.862126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 10:01:57.862624 ==
761 10:01:57.865115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 10:01:57.871736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 10:01:57.881496 [CA 0] Center 36 (6~67) winsize 62
764 10:01:57.884305 [CA 1] Center 36 (6~67) winsize 62
765 10:01:57.887621 [CA 2] Center 33 (3~64) winsize 62
766 10:01:57.891195 [CA 3] Center 33 (3~64) winsize 62
767 10:01:57.894495 [CA 4] Center 32 (2~63) winsize 62
768 10:01:57.898058 [CA 5] Center 32 (2~63) winsize 62
769 10:01:57.898571
770 10:01:57.901304 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 10:01:57.901813
772 10:01:57.904357 [CATrainingPosCal] consider 2 rank data
773 10:01:57.908002 u2DelayCellTimex100 = 270/100 ps
774 10:01:57.911358 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
775 10:01:57.914460 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
776 10:01:57.921191 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
777 10:01:57.924874 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
778 10:01:57.928333 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
779 10:01:57.931331 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
780 10:01:57.931862
781 10:01:57.934884 CA PerBit enable=1, Macro0, CA PI delay=32
782 10:01:57.935365
783 10:01:57.938220 [CBTSetCACLKResult] CA Dly = 32
784 10:01:57.938674 CS Dly: 5 (0~37)
785 10:01:57.938983
786 10:01:57.941511 ----->DramcWriteLeveling(PI) begin...
787 10:01:57.944873 ==
788 10:01:57.945254 Dram Type= 6, Freq= 0, CH_0, rank 0
789 10:01:57.948758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 10:01:57.952922 ==
791 10:01:57.953405 Write leveling (Byte 0): 31 => 31
792 10:01:57.956914 Write leveling (Byte 1): 30 => 30
793 10:01:57.960532 DramcWriteLeveling(PI) end<-----
794 10:01:57.961062
795 10:01:57.961382 ==
796 10:01:57.963679 Dram Type= 6, Freq= 0, CH_0, rank 0
797 10:01:57.967006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 10:01:57.967389 ==
799 10:01:57.970184 [Gating] SW mode calibration
800 10:01:57.977089 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 10:01:57.984474 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 10:01:57.987658 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 10:01:57.990630 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 10:01:57.997684 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 10:01:58.000892 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:01:58.004294 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:01:58.007384 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:01:58.014103 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:01:58.017314 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:01:58.021155 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:01:58.027503 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:01:58.031291 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 10:01:58.034191 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 10:01:58.041436 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 10:01:58.044432 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 10:01:58.047823 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 10:01:58.054548 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 10:01:58.057313 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
819 10:01:58.060574 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 10:01:58.067733 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
821 10:01:58.071228 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 10:01:58.074232 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:01:58.078028 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:01:58.084470 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:01:58.087987 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:01:58.091144 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:01:58.097792 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 10:01:58.101502 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
829 10:01:58.104653 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
830 10:01:58.110828 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 10:01:58.114447 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 10:01:58.117517 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 10:01:58.124866 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 10:01:58.127534 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 10:01:58.130927 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
836 10:01:58.138461 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
837 10:01:58.141463 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 10:01:58.144672 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 10:01:58.148013 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 10:01:58.154845 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 10:01:58.158073 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 10:01:58.161971 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 10:01:58.168511 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 10:01:58.171968 0 11 8 | B1->B0 | 2e2e 4040 | 0 0 | (0 0) (0 0)
845 10:01:58.175143 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
846 10:01:58.181685 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 10:01:58.184829 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 10:01:58.188218 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 10:01:58.194693 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 10:01:58.197966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 10:01:58.202203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 10:01:58.208371 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 10:01:58.211765 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 10:01:58.215062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 10:01:58.218169 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 10:01:58.225223 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 10:01:58.228492 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 10:01:58.231741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 10:01:58.238501 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 10:01:58.241792 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 10:01:58.245391 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 10:01:58.251839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 10:01:58.255288 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 10:01:58.258503 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 10:01:58.265508 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 10:01:58.268570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 10:01:58.272127 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 10:01:58.278556 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 10:01:58.279259 Total UI for P1: 0, mck2ui 16
870 10:01:58.281799 best dqsien dly found for B0: ( 0, 14, 4)
871 10:01:58.288299 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 10:01:58.291979 Total UI for P1: 0, mck2ui 16
873 10:01:58.295402 best dqsien dly found for B1: ( 0, 14, 8)
874 10:01:58.298811 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
875 10:01:58.302084 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 10:01:58.302689
877 10:01:58.305878 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
878 10:01:58.309278 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 10:01:58.312432 [Gating] SW calibration Done
880 10:01:58.312848 ==
881 10:01:58.315767 Dram Type= 6, Freq= 0, CH_0, rank 0
882 10:01:58.318936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 10:01:58.319368 ==
884 10:01:58.322394 RX Vref Scan: 0
885 10:01:58.322808
886 10:01:58.323137 RX Vref 0 -> 0, step: 1
887 10:01:58.323446
888 10:01:58.325937 RX Delay -130 -> 252, step: 16
889 10:01:58.329133 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
890 10:01:58.335550 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
891 10:01:58.339079 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 10:01:58.342558 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 10:01:58.346361 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
894 10:01:58.349548 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
895 10:01:58.352785 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
896 10:01:58.358992 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
897 10:01:58.362645 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
898 10:01:58.366476 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
899 10:01:58.368929 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
900 10:01:58.373000 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
901 10:01:58.379621 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
902 10:01:58.382967 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
903 10:01:58.385933 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
904 10:01:58.389338 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
905 10:01:58.389761 ==
906 10:01:58.392696 Dram Type= 6, Freq= 0, CH_0, rank 0
907 10:01:58.399640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 10:01:58.400097 ==
909 10:01:58.400412 DQS Delay:
910 10:01:58.403087 DQS0 = 0, DQS1 = 0
911 10:01:58.403474 DQM Delay:
912 10:01:58.403831 DQM0 = 89, DQM1 = 81
913 10:01:58.406029 DQ Delay:
914 10:01:58.409539 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
915 10:01:58.413279 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
916 10:01:58.416033 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
917 10:01:58.419204 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
918 10:01:58.419584
919 10:01:58.419937
920 10:01:58.420392 ==
921 10:01:58.423399 Dram Type= 6, Freq= 0, CH_0, rank 0
922 10:01:58.426219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 10:01:58.426749 ==
924 10:01:58.427056
925 10:01:58.427378
926 10:01:58.429944 TX Vref Scan disable
927 10:01:58.430319 == TX Byte 0 ==
928 10:01:58.436330 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
929 10:01:58.439913 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
930 10:01:58.440299 == TX Byte 1 ==
931 10:01:58.448466 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
932 10:01:58.449407 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
933 10:01:58.449797 ==
934 10:01:58.453264 Dram Type= 6, Freq= 0, CH_0, rank 0
935 10:01:58.456428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 10:01:58.456819 ==
937 10:01:58.469644 TX Vref=22, minBit 8, minWin=27, winSum=447
938 10:01:58.473356 TX Vref=24, minBit 9, minWin=27, winSum=451
939 10:01:58.476522 TX Vref=26, minBit 0, minWin=28, winSum=456
940 10:01:58.479828 TX Vref=28, minBit 8, minWin=28, winSum=458
941 10:01:58.483130 TX Vref=30, minBit 8, minWin=28, winSum=459
942 10:01:58.487049 TX Vref=32, minBit 5, minWin=28, winSum=456
943 10:01:58.493623 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
944 10:01:58.494006
945 10:01:58.496827 Final TX Range 1 Vref 30
946 10:01:58.497206
947 10:01:58.497651 ==
948 10:01:58.500106 Dram Type= 6, Freq= 0, CH_0, rank 0
949 10:01:58.503293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 10:01:58.503859 ==
951 10:01:58.504249
952 10:01:58.506836
953 10:01:58.507282 TX Vref Scan disable
954 10:01:58.509817 == TX Byte 0 ==
955 10:01:58.513366 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
956 10:01:58.516534 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
957 10:01:58.520299 == TX Byte 1 ==
958 10:01:58.523328 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
959 10:01:58.526602 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
960 10:01:58.526991
961 10:01:58.530288 [DATLAT]
962 10:01:58.530674 Freq=800, CH0 RK0
963 10:01:58.530984
964 10:01:58.533498 DATLAT Default: 0xa
965 10:01:58.533887 0, 0xFFFF, sum = 0
966 10:01:58.536698 1, 0xFFFF, sum = 0
967 10:01:58.537147 2, 0xFFFF, sum = 0
968 10:01:58.540236 3, 0xFFFF, sum = 0
969 10:01:58.540640 4, 0xFFFF, sum = 0
970 10:01:58.543285 5, 0xFFFF, sum = 0
971 10:01:58.543751 6, 0xFFFF, sum = 0
972 10:01:58.547085 7, 0xFFFF, sum = 0
973 10:01:58.547469 8, 0xFFFF, sum = 0
974 10:01:58.550424 9, 0x0, sum = 1
975 10:01:58.550804 10, 0x0, sum = 2
976 10:01:58.553578 11, 0x0, sum = 3
977 10:01:58.554078 12, 0x0, sum = 4
978 10:01:58.556547 best_step = 10
979 10:01:58.556934
980 10:01:58.557242 ==
981 10:01:58.559774 Dram Type= 6, Freq= 0, CH_0, rank 0
982 10:01:58.564073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 10:01:58.564606 ==
984 10:01:58.567211 RX Vref Scan: 1
985 10:01:58.567790
986 10:01:58.568136 Set Vref Range= 32 -> 127
987 10:01:58.568452
988 10:01:58.570104 RX Vref 32 -> 127, step: 1
989 10:01:58.570526
990 10:01:58.573167 RX Delay -95 -> 252, step: 8
991 10:01:58.573588
992 10:01:58.577110 Set Vref, RX VrefLevel [Byte0]: 32
993 10:01:58.580214 [Byte1]: 32
994 10:01:58.580642
995 10:01:58.583260 Set Vref, RX VrefLevel [Byte0]: 33
996 10:01:58.587177 [Byte1]: 33
997 10:01:58.590242
998 10:01:58.590785 Set Vref, RX VrefLevel [Byte0]: 34
999 10:01:58.593604 [Byte1]: 34
1000 10:01:58.598260
1001 10:01:58.598682 Set Vref, RX VrefLevel [Byte0]: 35
1002 10:01:58.600903 [Byte1]: 35
1003 10:01:58.605676
1004 10:01:58.606097 Set Vref, RX VrefLevel [Byte0]: 36
1005 10:01:58.609049 [Byte1]: 36
1006 10:01:58.613607
1007 10:01:58.614028 Set Vref, RX VrefLevel [Byte0]: 37
1008 10:01:58.616744 [Byte1]: 37
1009 10:01:58.621329
1010 10:01:58.621752 Set Vref, RX VrefLevel [Byte0]: 38
1011 10:01:58.624613 [Byte1]: 38
1012 10:01:58.628894
1013 10:01:58.629317 Set Vref, RX VrefLevel [Byte0]: 39
1014 10:01:58.632225 [Byte1]: 39
1015 10:01:58.636123
1016 10:01:58.636543 Set Vref, RX VrefLevel [Byte0]: 40
1017 10:01:58.639390 [Byte1]: 40
1018 10:01:58.644019
1019 10:01:58.644443 Set Vref, RX VrefLevel [Byte0]: 41
1020 10:01:58.647384 [Byte1]: 41
1021 10:01:58.651268
1022 10:01:58.651813 Set Vref, RX VrefLevel [Byte0]: 42
1023 10:01:58.654029 [Byte1]: 42
1024 10:01:58.658838
1025 10:01:58.659270 Set Vref, RX VrefLevel [Byte0]: 43
1026 10:01:58.662141 [Byte1]: 43
1027 10:01:58.666282
1028 10:01:58.666724 Set Vref, RX VrefLevel [Byte0]: 44
1029 10:01:58.669714 [Byte1]: 44
1030 10:01:58.673847
1031 10:01:58.674278 Set Vref, RX VrefLevel [Byte0]: 45
1032 10:01:58.677382 [Byte1]: 45
1033 10:01:58.681184
1034 10:01:58.681620 Set Vref, RX VrefLevel [Byte0]: 46
1035 10:01:58.684982 [Byte1]: 46
1036 10:01:58.688847
1037 10:01:58.689325 Set Vref, RX VrefLevel [Byte0]: 47
1038 10:01:58.692096 [Byte1]: 47
1039 10:01:58.696421
1040 10:01:58.696803 Set Vref, RX VrefLevel [Byte0]: 48
1041 10:01:58.699994 [Byte1]: 48
1042 10:01:58.704221
1043 10:01:58.704637 Set Vref, RX VrefLevel [Byte0]: 49
1044 10:01:58.707468 [Byte1]: 49
1045 10:01:58.711906
1046 10:01:58.712324 Set Vref, RX VrefLevel [Byte0]: 50
1047 10:01:58.715304 [Byte1]: 50
1048 10:01:58.719482
1049 10:01:58.720060 Set Vref, RX VrefLevel [Byte0]: 51
1050 10:01:58.722595 [Byte1]: 51
1051 10:01:58.727100
1052 10:01:58.727682 Set Vref, RX VrefLevel [Byte0]: 52
1053 10:01:58.730301 [Byte1]: 52
1054 10:01:58.734843
1055 10:01:58.735261 Set Vref, RX VrefLevel [Byte0]: 53
1056 10:01:58.738165 [Byte1]: 53
1057 10:01:58.742177
1058 10:01:58.742597 Set Vref, RX VrefLevel [Byte0]: 54
1059 10:01:58.745582 [Byte1]: 54
1060 10:01:58.750178
1061 10:01:58.750718 Set Vref, RX VrefLevel [Byte0]: 55
1062 10:01:58.753383 [Byte1]: 55
1063 10:01:58.757312
1064 10:01:58.757827 Set Vref, RX VrefLevel [Byte0]: 56
1065 10:01:58.760980 [Byte1]: 56
1066 10:01:58.764987
1067 10:01:58.765463 Set Vref, RX VrefLevel [Byte0]: 57
1068 10:01:58.768809 [Byte1]: 57
1069 10:01:58.772592
1070 10:01:58.773049 Set Vref, RX VrefLevel [Byte0]: 58
1071 10:01:58.776069 [Byte1]: 58
1072 10:01:58.780004
1073 10:01:58.780417 Set Vref, RX VrefLevel [Byte0]: 59
1074 10:01:58.783828 [Byte1]: 59
1075 10:01:58.787913
1076 10:01:58.788510 Set Vref, RX VrefLevel [Byte0]: 60
1077 10:01:58.791090 [Byte1]: 60
1078 10:01:58.795704
1079 10:01:58.796143 Set Vref, RX VrefLevel [Byte0]: 61
1080 10:01:58.801650 [Byte1]: 61
1081 10:01:58.802034
1082 10:01:58.805025 Set Vref, RX VrefLevel [Byte0]: 62
1083 10:01:58.808737 [Byte1]: 62
1084 10:01:58.809123
1085 10:01:58.811951 Set Vref, RX VrefLevel [Byte0]: 63
1086 10:01:58.815239 [Byte1]: 63
1087 10:01:58.815654
1088 10:01:58.818379 Set Vref, RX VrefLevel [Byte0]: 64
1089 10:01:58.821545 [Byte1]: 64
1090 10:01:58.826070
1091 10:01:58.826448 Set Vref, RX VrefLevel [Byte0]: 65
1092 10:01:58.829310 [Byte1]: 65
1093 10:01:58.833237
1094 10:01:58.833755 Set Vref, RX VrefLevel [Byte0]: 66
1095 10:01:58.836952 [Byte1]: 66
1096 10:01:58.841056
1097 10:01:58.841563 Set Vref, RX VrefLevel [Byte0]: 67
1098 10:01:58.844034 [Byte1]: 67
1099 10:01:58.848846
1100 10:01:58.849349 Set Vref, RX VrefLevel [Byte0]: 68
1101 10:01:58.851779 [Byte1]: 68
1102 10:01:58.856196
1103 10:01:58.856612 Set Vref, RX VrefLevel [Byte0]: 69
1104 10:01:58.859439 [Byte1]: 69
1105 10:01:58.864096
1106 10:01:58.864660 Set Vref, RX VrefLevel [Byte0]: 70
1107 10:01:58.867220 [Byte1]: 70
1108 10:01:58.871522
1109 10:01:58.871969 Set Vref, RX VrefLevel [Byte0]: 71
1110 10:01:58.874865 [Byte1]: 71
1111 10:01:58.878709
1112 10:01:58.879122 Set Vref, RX VrefLevel [Byte0]: 72
1113 10:01:58.882504 [Byte1]: 72
1114 10:01:58.886816
1115 10:01:58.887319 Set Vref, RX VrefLevel [Byte0]: 73
1116 10:01:58.889734 [Byte1]: 73
1117 10:01:58.893918
1118 10:01:58.894336 Set Vref, RX VrefLevel [Byte0]: 74
1119 10:01:58.897579 [Byte1]: 74
1120 10:01:58.901860
1121 10:01:58.902365 Set Vref, RX VrefLevel [Byte0]: 75
1122 10:01:58.905276 [Byte1]: 75
1123 10:01:58.909628
1124 10:01:58.910278 Final RX Vref Byte 0 = 55 to rank0
1125 10:01:58.912856 Final RX Vref Byte 1 = 55 to rank0
1126 10:01:58.916161 Final RX Vref Byte 0 = 55 to rank1
1127 10:01:58.919959 Final RX Vref Byte 1 = 55 to rank1==
1128 10:01:58.922523 Dram Type= 6, Freq= 0, CH_0, rank 0
1129 10:01:58.929633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 10:01:58.930197 ==
1131 10:01:58.930692 DQS Delay:
1132 10:01:58.931148 DQS0 = 0, DQS1 = 0
1133 10:01:58.932750 DQM Delay:
1134 10:01:58.933264 DQM0 = 92, DQM1 = 86
1135 10:01:58.935996 DQ Delay:
1136 10:01:58.939222 DQ0 =96, DQ1 =96, DQ2 =88, DQ3 =88
1137 10:01:58.942959 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1138 10:01:58.943380 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
1139 10:01:58.949344 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1140 10:01:58.949907
1141 10:01:58.950266
1142 10:01:58.955972 [DQSOSCAuto] RK0, (LSB)MR18= 0x5047, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1143 10:01:58.959328 CH0 RK0: MR19=606, MR18=5047
1144 10:01:58.965949 CH0_RK0: MR19=0x606, MR18=0x5047, DQSOSC=389, MR23=63, INC=97, DEC=65
1145 10:01:58.966332
1146 10:01:58.969256 ----->DramcWriteLeveling(PI) begin...
1147 10:01:58.969645 ==
1148 10:01:58.972981 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 10:01:58.976381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 10:01:58.976768 ==
1151 10:01:58.979274 Write leveling (Byte 0): 32 => 32
1152 10:01:58.983197 Write leveling (Byte 1): 30 => 30
1153 10:01:58.986051 DramcWriteLeveling(PI) end<-----
1154 10:01:58.986782
1155 10:01:58.987141 ==
1156 10:01:58.989555 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 10:01:58.992930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 10:01:58.993349 ==
1159 10:01:58.996370 [Gating] SW mode calibration
1160 10:01:59.002636 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1161 10:01:59.009354 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1162 10:01:59.013047 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 10:01:59.016292 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1164 10:01:59.063507 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1165 10:01:59.064039 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:01:59.064703 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:01:59.065058 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:01:59.065371 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:01:59.065666 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:01:59.066071 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:01:59.066550 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:01:59.066988 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:01:59.067295 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:01:59.107427 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:01:59.108071 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:01:59.108415 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:01:59.108728 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:01:59.109030 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 10:01:59.109641 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 10:01:59.110031 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1181 10:01:59.110349 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 10:01:59.110641 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 10:01:59.110924 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 10:01:59.129422 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 10:01:59.129956 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 10:01:59.130303 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:01:59.130615 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:01:59.130914 0 9 8 | B1->B0 | 2f2f 2a2a | 0 1 | (0 0) (1 1)
1189 10:01:59.133061 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 10:01:59.136310 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 10:01:59.139966 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 10:01:59.146366 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 10:01:59.149420 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 10:01:59.153450 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 10:01:59.156208 0 10 4 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
1196 10:01:59.163377 0 10 8 | B1->B0 | 2929 2525 | 0 0 | (1 0) (0 0)
1197 10:01:59.166293 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 10:01:59.169813 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 10:01:59.176323 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 10:01:59.179572 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 10:01:59.182934 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 10:01:59.190753 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 10:01:59.193907 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1204 10:01:59.197596 0 11 8 | B1->B0 | 3f3f 3535 | 0 0 | (0 0) (0 0)
1205 10:01:59.201669 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 10:01:59.205507 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 10:01:59.211689 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 10:01:59.215324 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 10:01:59.219191 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 10:01:59.222538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 10:01:59.228972 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 10:01:59.232253 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1213 10:01:59.236131 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:01:59.242499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:01:59.245856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:01:59.249144 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:01:59.255466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:01:59.259415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 10:01:59.262625 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 10:01:59.268957 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 10:01:59.272469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 10:01:59.276131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 10:01:59.282611 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 10:01:59.286165 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 10:01:59.289070 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 10:01:59.292297 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 10:01:59.299371 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 10:01:59.302477 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1229 10:01:59.305803 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 10:01:59.309105 Total UI for P1: 0, mck2ui 16
1231 10:01:59.312416 best dqsien dly found for B0: ( 0, 14, 8)
1232 10:01:59.315538 Total UI for P1: 0, mck2ui 16
1233 10:01:59.319254 best dqsien dly found for B1: ( 0, 14, 8)
1234 10:01:59.322183 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1235 10:01:59.326055 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1236 10:01:59.326474
1237 10:01:59.332852 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1238 10:01:59.335879 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1239 10:01:59.336301 [Gating] SW calibration Done
1240 10:01:59.339217 ==
1241 10:01:59.342472 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 10:01:59.345831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1243 10:01:59.346248 ==
1244 10:01:59.346578 RX Vref Scan: 0
1245 10:01:59.346882
1246 10:01:59.348949 RX Vref 0 -> 0, step: 1
1247 10:01:59.349364
1248 10:01:59.352586 RX Delay -130 -> 252, step: 16
1249 10:01:59.355638 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1250 10:01:59.359530 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1251 10:01:59.363083 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1252 10:01:59.369524 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1253 10:01:59.372743 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1254 10:01:59.375662 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1255 10:01:59.378896 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1256 10:01:59.382564 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1257 10:01:59.389232 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1258 10:01:59.392365 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1259 10:01:59.395726 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1260 10:01:59.398955 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1261 10:01:59.405724 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1262 10:01:59.408756 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1263 10:01:59.412138 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1264 10:01:59.416013 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1265 10:01:59.416536 ==
1266 10:01:59.418983 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 10:01:59.422759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 10:01:59.425806 ==
1269 10:01:59.426257 DQS Delay:
1270 10:01:59.426597 DQS0 = 0, DQS1 = 0
1271 10:01:59.429274 DQM Delay:
1272 10:01:59.429752 DQM0 = 91, DQM1 = 80
1273 10:01:59.432498 DQ Delay:
1274 10:01:59.432917 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1275 10:01:59.435718 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1276 10:01:59.439200 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1277 10:01:59.442480 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1278 10:01:59.442898
1279 10:01:59.445670
1280 10:01:59.446098 ==
1281 10:01:59.449481 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 10:01:59.452706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 10:01:59.453140 ==
1284 10:01:59.453592
1285 10:01:59.453915
1286 10:01:59.455852 TX Vref Scan disable
1287 10:01:59.456284 == TX Byte 0 ==
1288 10:01:59.462672 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1289 10:01:59.466293 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1290 10:01:59.466811 == TX Byte 1 ==
1291 10:01:59.472573 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1292 10:01:59.475711 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1293 10:01:59.476132 ==
1294 10:01:59.479083 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 10:01:59.482583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 10:01:59.483107 ==
1297 10:01:59.496292 TX Vref=22, minBit 8, minWin=27, winSum=445
1298 10:01:59.499459 TX Vref=24, minBit 10, minWin=27, winSum=445
1299 10:01:59.503263 TX Vref=26, minBit 1, minWin=28, winSum=453
1300 10:01:59.506471 TX Vref=28, minBit 4, minWin=28, winSum=457
1301 10:01:59.509536 TX Vref=30, minBit 7, minWin=28, winSum=459
1302 10:01:59.516404 TX Vref=32, minBit 2, minWin=28, winSum=452
1303 10:01:59.519632 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 30
1304 10:01:59.520058
1305 10:01:59.522826 Final TX Range 1 Vref 30
1306 10:01:59.523243
1307 10:01:59.523649 ==
1308 10:01:59.526285 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 10:01:59.529125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 10:01:59.529542 ==
1311 10:01:59.529871
1312 10:01:59.532811
1313 10:01:59.533219 TX Vref Scan disable
1314 10:01:59.535843 == TX Byte 0 ==
1315 10:01:59.539329 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1316 10:01:59.542909 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1317 10:01:59.545944 == TX Byte 1 ==
1318 10:01:59.549222 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1319 10:01:59.553226 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1320 10:01:59.556402
1321 10:01:59.556808 [DATLAT]
1322 10:01:59.557131 Freq=800, CH0 RK1
1323 10:01:59.557431
1324 10:01:59.559634 DATLAT Default: 0xa
1325 10:01:59.560054 0, 0xFFFF, sum = 0
1326 10:01:59.562854 1, 0xFFFF, sum = 0
1327 10:01:59.563258 2, 0xFFFF, sum = 0
1328 10:01:59.565857 3, 0xFFFF, sum = 0
1329 10:01:59.566240 4, 0xFFFF, sum = 0
1330 10:01:59.569443 5, 0xFFFF, sum = 0
1331 10:01:59.569823 6, 0xFFFF, sum = 0
1332 10:01:59.572925 7, 0xFFFF, sum = 0
1333 10:01:59.573309 8, 0xFFFF, sum = 0
1334 10:01:59.576270 9, 0x0, sum = 1
1335 10:01:59.576652 10, 0x0, sum = 2
1336 10:01:59.579410 11, 0x0, sum = 3
1337 10:01:59.579889 12, 0x0, sum = 4
1338 10:01:59.582767 best_step = 10
1339 10:01:59.583144
1340 10:01:59.583444 ==
1341 10:01:59.586261 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 10:01:59.589383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 10:01:59.589765 ==
1344 10:01:59.593223 RX Vref Scan: 0
1345 10:01:59.593595
1346 10:01:59.593891 RX Vref 0 -> 0, step: 1
1347 10:01:59.594169
1348 10:01:59.596401 RX Delay -95 -> 252, step: 8
1349 10:01:59.603564 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1350 10:01:59.606368 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1351 10:01:59.609738 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1352 10:01:59.613111 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1353 10:01:59.616189 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1354 10:01:59.623099 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1355 10:01:59.626307 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1356 10:01:59.629363 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1357 10:01:59.633214 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1358 10:01:59.636075 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1359 10:01:59.639590 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1360 10:01:59.646314 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1361 10:01:59.649359 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1362 10:01:59.652837 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1363 10:01:59.655959 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1364 10:01:59.662897 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1365 10:01:59.663293 ==
1366 10:01:59.666065 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 10:01:59.669448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 10:01:59.669829 ==
1369 10:01:59.670143 DQS Delay:
1370 10:01:59.672684 DQS0 = 0, DQS1 = 0
1371 10:01:59.673063 DQM Delay:
1372 10:01:59.676383 DQM0 = 94, DQM1 = 84
1373 10:01:59.676764 DQ Delay:
1374 10:01:59.679892 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =92
1375 10:01:59.683120 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1376 10:01:59.686356 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1377 10:01:59.689561 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1378 10:01:59.690042
1379 10:01:59.690462
1380 10:01:59.696485 [DQSOSCAuto] RK1, (LSB)MR18= 0x4515, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1381 10:01:59.699690 CH0 RK1: MR19=606, MR18=4515
1382 10:01:59.706564 CH0_RK1: MR19=0x606, MR18=0x4515, DQSOSC=392, MR23=63, INC=96, DEC=64
1383 10:01:59.709652 [RxdqsGatingPostProcess] freq 800
1384 10:01:59.716698 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1385 10:01:59.717092 Pre-setting of DQS Precalculation
1386 10:01:59.723005 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1387 10:01:59.723390 ==
1388 10:01:59.726383 Dram Type= 6, Freq= 0, CH_1, rank 0
1389 10:01:59.729623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 10:01:59.730005 ==
1391 10:01:59.736522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 10:01:59.743024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 10:01:59.750928 [CA 0] Center 36 (6~67) winsize 62
1394 10:01:59.754359 [CA 1] Center 36 (6~67) winsize 62
1395 10:01:59.757478 [CA 2] Center 34 (4~65) winsize 62
1396 10:01:59.761118 [CA 3] Center 34 (4~65) winsize 62
1397 10:01:59.764501 [CA 4] Center 35 (5~65) winsize 61
1398 10:01:59.767462 [CA 5] Center 34 (4~65) winsize 62
1399 10:01:59.767656
1400 10:01:59.770731 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1401 10:01:59.770949
1402 10:01:59.774129 [CATrainingPosCal] consider 1 rank data
1403 10:01:59.778123 u2DelayCellTimex100 = 270/100 ps
1404 10:01:59.780718 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1405 10:01:59.784311 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1406 10:01:59.790873 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 10:01:59.794763 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1408 10:01:59.798164 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1409 10:01:59.801502 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 10:01:59.801786
1411 10:01:59.804778 CA PerBit enable=1, Macro0, CA PI delay=34
1412 10:01:59.805101
1413 10:01:59.807883 [CBTSetCACLKResult] CA Dly = 34
1414 10:01:59.808211 CS Dly: 6 (0~37)
1415 10:01:59.808409 ==
1416 10:01:59.811068 Dram Type= 6, Freq= 0, CH_1, rank 1
1417 10:01:59.818324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 10:01:59.818839 ==
1419 10:01:59.821336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 10:01:59.827878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 10:01:59.837523 [CA 0] Center 36 (6~67) winsize 62
1422 10:01:59.840742 [CA 1] Center 37 (6~68) winsize 63
1423 10:01:59.843898 [CA 2] Center 35 (5~66) winsize 62
1424 10:01:59.847372 [CA 3] Center 34 (4~65) winsize 62
1425 10:01:59.851153 [CA 4] Center 35 (5~66) winsize 62
1426 10:01:59.854666 [CA 5] Center 34 (4~65) winsize 62
1427 10:01:59.855083
1428 10:01:59.858218 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1429 10:01:59.858636
1430 10:01:59.861354 [CATrainingPosCal] consider 2 rank data
1431 10:01:59.865220 u2DelayCellTimex100 = 270/100 ps
1432 10:01:59.869481 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 10:01:59.872897 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 10:01:59.876725 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1435 10:01:59.880377 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 10:01:59.883720 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1437 10:01:59.887709 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 10:01:59.888226
1439 10:01:59.891500 CA PerBit enable=1, Macro0, CA PI delay=34
1440 10:01:59.892068
1441 10:01:59.894292 [CBTSetCACLKResult] CA Dly = 34
1442 10:01:59.894703 CS Dly: 6 (0~38)
1443 10:01:59.895026
1444 10:01:59.897763 ----->DramcWriteLeveling(PI) begin...
1445 10:01:59.898179 ==
1446 10:01:59.901191 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 10:01:59.908137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 10:01:59.908660 ==
1449 10:01:59.911296 Write leveling (Byte 0): 26 => 26
1450 10:01:59.911745 Write leveling (Byte 1): 26 => 26
1451 10:01:59.914496 DramcWriteLeveling(PI) end<-----
1452 10:01:59.914905
1453 10:01:59.917815 ==
1454 10:01:59.918325 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 10:01:59.924231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 10:01:59.924644 ==
1457 10:01:59.927662 [Gating] SW mode calibration
1458 10:01:59.935099 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1459 10:01:59.938239 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1460 10:01:59.944602 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1461 10:01:59.948040 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1462 10:01:59.951812 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:01:59.954808 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:01:59.961602 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:01:59.964882 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:01:59.968080 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:01:59.974753 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:01:59.978095 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:01:59.981546 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:01:59.988179 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:01:59.991208 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:01:59.995170 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:02:00.001450 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:02:00.004909 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 10:02:00.008180 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 10:02:00.015143 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1477 10:02:00.018459 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1478 10:02:00.021506 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 10:02:00.028388 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 10:02:00.031330 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:02:00.035203 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 10:02:00.038395 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 10:02:00.044933 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 10:02:00.048155 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:02:00.051442 0 9 4 | B1->B0 | 2323 2626 | 1 1 | (1 1) (1 1)
1486 10:02:00.058470 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1487 10:02:00.061808 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 10:02:00.064939 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 10:02:00.071459 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 10:02:00.074485 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 10:02:00.077873 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 10:02:00.084467 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1493 10:02:00.087770 0 10 4 | B1->B0 | 3232 2d2d | 0 1 | (0 1) (1 0)
1494 10:02:00.091133 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1495 10:02:00.097832 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 10:02:00.101079 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 10:02:00.104973 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 10:02:00.111317 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 10:02:00.115006 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 10:02:00.117774 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 10:02:00.121471 0 11 4 | B1->B0 | 2828 3535 | 0 1 | (0 0) (0 0)
1502 10:02:00.127993 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1503 10:02:00.131155 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 10:02:00.134330 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 10:02:00.141367 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 10:02:00.144574 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 10:02:00.147914 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 10:02:00.154461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1509 10:02:00.157810 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 10:02:00.161102 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:02:00.168157 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:02:00.171399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:02:00.174561 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:02:00.181123 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:02:00.184915 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:02:00.187848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:02:00.194577 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 10:02:00.198361 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 10:02:00.201601 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 10:02:00.204582 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 10:02:00.211520 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 10:02:00.214903 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 10:02:00.217949 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 10:02:00.224830 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1525 10:02:00.228019 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1526 10:02:00.231289 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 10:02:00.234750 Total UI for P1: 0, mck2ui 16
1528 10:02:00.238364 best dqsien dly found for B0: ( 0, 14, 4)
1529 10:02:00.241418 Total UI for P1: 0, mck2ui 16
1530 10:02:00.244596 best dqsien dly found for B1: ( 0, 14, 2)
1531 10:02:00.248286 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1532 10:02:00.251485 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1533 10:02:00.251602
1534 10:02:00.254754 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1535 10:02:00.261333 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1536 10:02:00.261405 [Gating] SW calibration Done
1537 10:02:00.261466 ==
1538 10:02:00.265102 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 10:02:00.271778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1540 10:02:00.271858 ==
1541 10:02:00.271921 RX Vref Scan: 0
1542 10:02:00.271979
1543 10:02:00.275126 RX Vref 0 -> 0, step: 1
1544 10:02:00.275205
1545 10:02:00.278170 RX Delay -130 -> 252, step: 16
1546 10:02:00.281468 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1547 10:02:00.285285 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1548 10:02:00.288574 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1549 10:02:00.294901 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1550 10:02:00.298765 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1551 10:02:00.301849 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1552 10:02:00.305019 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1553 10:02:00.308256 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1554 10:02:00.312188 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1555 10:02:00.318655 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1556 10:02:00.321952 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1557 10:02:00.325624 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1558 10:02:00.328757 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1559 10:02:00.331638 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1560 10:02:00.338850 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1561 10:02:00.341733 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1562 10:02:00.341813 ==
1563 10:02:00.345209 Dram Type= 6, Freq= 0, CH_1, rank 0
1564 10:02:00.348784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1565 10:02:00.348863 ==
1566 10:02:00.351724 DQS Delay:
1567 10:02:00.351802 DQS0 = 0, DQS1 = 0
1568 10:02:00.351864 DQM Delay:
1569 10:02:00.355262 DQM0 = 96, DQM1 = 93
1570 10:02:00.355340 DQ Delay:
1571 10:02:00.358912 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1572 10:02:00.362034 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1573 10:02:00.365477 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1574 10:02:00.368632 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1575 10:02:00.368711
1576 10:02:00.368773
1577 10:02:00.371798 ==
1578 10:02:00.371877 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 10:02:00.378764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 10:02:00.378853 ==
1581 10:02:00.378918
1582 10:02:00.378981
1583 10:02:00.382154 TX Vref Scan disable
1584 10:02:00.382233 == TX Byte 0 ==
1585 10:02:00.385451 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1586 10:02:00.392146 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1587 10:02:00.392225 == TX Byte 1 ==
1588 10:02:00.395423 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1589 10:02:00.401773 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1590 10:02:00.401853 ==
1591 10:02:00.405013 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 10:02:00.408743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 10:02:00.408822 ==
1594 10:02:00.421921 TX Vref=22, minBit 1, minWin=26, winSum=433
1595 10:02:00.425093 TX Vref=24, minBit 0, minWin=27, winSum=441
1596 10:02:00.428001 TX Vref=26, minBit 1, minWin=26, winSum=441
1597 10:02:00.431644 TX Vref=28, minBit 0, minWin=27, winSum=445
1598 10:02:00.435508 TX Vref=30, minBit 1, minWin=27, winSum=443
1599 10:02:00.439274 TX Vref=32, minBit 7, minWin=26, winSum=440
1600 10:02:00.445798 [TxChooseVref] Worse bit 0, Min win 27, Win sum 445, Final Vref 28
1601 10:02:00.445878
1602 10:02:00.448906 Final TX Range 1 Vref 28
1603 10:02:00.448986
1604 10:02:00.449057 ==
1605 10:02:00.452469 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 10:02:00.455498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 10:02:00.455626 ==
1608 10:02:00.455704
1609 10:02:00.455762
1610 10:02:00.458768 TX Vref Scan disable
1611 10:02:00.462595 == TX Byte 0 ==
1612 10:02:00.465756 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1613 10:02:00.469250 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1614 10:02:00.472121 == TX Byte 1 ==
1615 10:02:00.475790 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1616 10:02:00.479204 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1617 10:02:00.479283
1618 10:02:00.482400 [DATLAT]
1619 10:02:00.482479 Freq=800, CH1 RK0
1620 10:02:00.482542
1621 10:02:00.486059 DATLAT Default: 0xa
1622 10:02:00.486138 0, 0xFFFF, sum = 0
1623 10:02:00.489087 1, 0xFFFF, sum = 0
1624 10:02:00.489167 2, 0xFFFF, sum = 0
1625 10:02:00.492245 3, 0xFFFF, sum = 0
1626 10:02:00.492326 4, 0xFFFF, sum = 0
1627 10:02:00.496105 5, 0xFFFF, sum = 0
1628 10:02:00.496196 6, 0xFFFF, sum = 0
1629 10:02:00.499205 7, 0xFFFF, sum = 0
1630 10:02:00.499285 8, 0xFFFF, sum = 0
1631 10:02:00.502275 9, 0x0, sum = 1
1632 10:02:00.502356 10, 0x0, sum = 2
1633 10:02:00.506004 11, 0x0, sum = 3
1634 10:02:00.506084 12, 0x0, sum = 4
1635 10:02:00.506148 best_step = 10
1636 10:02:00.509298
1637 10:02:00.509377 ==
1638 10:02:00.512569 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 10:02:00.515560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 10:02:00.515678 ==
1641 10:02:00.515750 RX Vref Scan: 1
1642 10:02:00.515817
1643 10:02:00.519533 Set Vref Range= 32 -> 127
1644 10:02:00.519650
1645 10:02:00.522818 RX Vref 32 -> 127, step: 1
1646 10:02:00.522898
1647 10:02:00.525998 RX Delay -63 -> 252, step: 8
1648 10:02:00.526077
1649 10:02:00.529225 Set Vref, RX VrefLevel [Byte0]: 32
1650 10:02:00.532357 [Byte1]: 32
1651 10:02:00.532436
1652 10:02:00.536089 Set Vref, RX VrefLevel [Byte0]: 33
1653 10:02:00.539496 [Byte1]: 33
1654 10:02:00.539607
1655 10:02:00.542523 Set Vref, RX VrefLevel [Byte0]: 34
1656 10:02:00.546316 [Byte1]: 34
1657 10:02:00.546395
1658 10:02:00.549455 Set Vref, RX VrefLevel [Byte0]: 35
1659 10:02:00.552618 [Byte1]: 35
1660 10:02:00.556400
1661 10:02:00.556480 Set Vref, RX VrefLevel [Byte0]: 36
1662 10:02:00.559919 [Byte1]: 36
1663 10:02:00.564063
1664 10:02:00.564142 Set Vref, RX VrefLevel [Byte0]: 37
1665 10:02:00.567042 [Byte1]: 37
1666 10:02:00.571566
1667 10:02:00.571686 Set Vref, RX VrefLevel [Byte0]: 38
1668 10:02:00.574849 [Byte1]: 38
1669 10:02:00.579176
1670 10:02:00.579255 Set Vref, RX VrefLevel [Byte0]: 39
1671 10:02:00.582488 [Byte1]: 39
1672 10:02:00.586729
1673 10:02:00.586808 Set Vref, RX VrefLevel [Byte0]: 40
1674 10:02:00.590135 [Byte1]: 40
1675 10:02:00.594090
1676 10:02:00.594169 Set Vref, RX VrefLevel [Byte0]: 41
1677 10:02:00.597295 [Byte1]: 41
1678 10:02:00.601272
1679 10:02:00.601350 Set Vref, RX VrefLevel [Byte0]: 42
1680 10:02:00.604903 [Byte1]: 42
1681 10:02:00.609065
1682 10:02:00.609144 Set Vref, RX VrefLevel [Byte0]: 43
1683 10:02:00.612240 [Byte1]: 43
1684 10:02:00.616769
1685 10:02:00.616848 Set Vref, RX VrefLevel [Byte0]: 44
1686 10:02:00.620035 [Byte1]: 44
1687 10:02:00.623750
1688 10:02:00.623828 Set Vref, RX VrefLevel [Byte0]: 45
1689 10:02:00.627581 [Byte1]: 45
1690 10:02:00.631507
1691 10:02:00.631650 Set Vref, RX VrefLevel [Byte0]: 46
1692 10:02:00.634856 [Byte1]: 46
1693 10:02:00.639086
1694 10:02:00.639164 Set Vref, RX VrefLevel [Byte0]: 47
1695 10:02:00.642396 [Byte1]: 47
1696 10:02:00.646264
1697 10:02:00.646343 Set Vref, RX VrefLevel [Byte0]: 48
1698 10:02:00.650074 [Byte1]: 48
1699 10:02:00.653998
1700 10:02:00.654080 Set Vref, RX VrefLevel [Byte0]: 49
1701 10:02:00.657146 [Byte1]: 49
1702 10:02:00.661753
1703 10:02:00.661862 Set Vref, RX VrefLevel [Byte0]: 50
1704 10:02:00.664764 [Byte1]: 50
1705 10:02:00.668925
1706 10:02:00.669004 Set Vref, RX VrefLevel [Byte0]: 51
1707 10:02:00.672395 [Byte1]: 51
1708 10:02:00.676605
1709 10:02:00.676684 Set Vref, RX VrefLevel [Byte0]: 52
1710 10:02:00.679901 [Byte1]: 52
1711 10:02:00.684248
1712 10:02:00.684328 Set Vref, RX VrefLevel [Byte0]: 53
1713 10:02:00.687513 [Byte1]: 53
1714 10:02:00.691419
1715 10:02:00.691499 Set Vref, RX VrefLevel [Byte0]: 54
1716 10:02:00.694650 [Byte1]: 54
1717 10:02:00.699040
1718 10:02:00.699120 Set Vref, RX VrefLevel [Byte0]: 55
1719 10:02:00.702163 [Byte1]: 55
1720 10:02:00.706300
1721 10:02:00.706381 Set Vref, RX VrefLevel [Byte0]: 56
1722 10:02:00.709815 [Byte1]: 56
1723 10:02:00.713921
1724 10:02:00.714001 Set Vref, RX VrefLevel [Byte0]: 57
1725 10:02:00.717139 [Byte1]: 57
1726 10:02:00.721683
1727 10:02:00.721763 Set Vref, RX VrefLevel [Byte0]: 58
1728 10:02:00.724758 [Byte1]: 58
1729 10:02:00.728891
1730 10:02:00.728974 Set Vref, RX VrefLevel [Byte0]: 59
1731 10:02:00.732121 [Byte1]: 59
1732 10:02:00.736630
1733 10:02:00.736711 Set Vref, RX VrefLevel [Byte0]: 60
1734 10:02:00.739872 [Byte1]: 60
1735 10:02:00.744070
1736 10:02:00.744150 Set Vref, RX VrefLevel [Byte0]: 61
1737 10:02:00.747263 [Byte1]: 61
1738 10:02:00.751160
1739 10:02:00.751240 Set Vref, RX VrefLevel [Byte0]: 62
1740 10:02:00.754507 [Byte1]: 62
1741 10:02:00.758994
1742 10:02:00.759075 Set Vref, RX VrefLevel [Byte0]: 63
1743 10:02:00.762139 [Byte1]: 63
1744 10:02:00.766442
1745 10:02:00.766522 Set Vref, RX VrefLevel [Byte0]: 64
1746 10:02:00.769777 [Byte1]: 64
1747 10:02:00.773787
1748 10:02:00.773883 Set Vref, RX VrefLevel [Byte0]: 65
1749 10:02:00.777081 [Byte1]: 65
1750 10:02:00.781732
1751 10:02:00.781840 Set Vref, RX VrefLevel [Byte0]: 66
1752 10:02:00.784922 [Byte1]: 66
1753 10:02:00.788730
1754 10:02:00.788810 Set Vref, RX VrefLevel [Byte0]: 67
1755 10:02:00.792098 [Byte1]: 67
1756 10:02:00.796146
1757 10:02:00.796226 Set Vref, RX VrefLevel [Byte0]: 68
1758 10:02:00.800029 [Byte1]: 68
1759 10:02:00.803834
1760 10:02:00.803914 Set Vref, RX VrefLevel [Byte0]: 69
1761 10:02:00.807054 [Byte1]: 69
1762 10:02:00.811410
1763 10:02:00.811490 Set Vref, RX VrefLevel [Byte0]: 70
1764 10:02:00.814454 [Byte1]: 70
1765 10:02:00.818894
1766 10:02:00.818974 Set Vref, RX VrefLevel [Byte0]: 71
1767 10:02:00.822024 [Byte1]: 71
1768 10:02:00.826283
1769 10:02:00.826363 Set Vref, RX VrefLevel [Byte0]: 72
1770 10:02:00.829752 [Byte1]: 72
1771 10:02:00.833645
1772 10:02:00.833759 Final RX Vref Byte 0 = 61 to rank0
1773 10:02:00.837008 Final RX Vref Byte 1 = 56 to rank0
1774 10:02:00.840670 Final RX Vref Byte 0 = 61 to rank1
1775 10:02:00.843748 Final RX Vref Byte 1 = 56 to rank1==
1776 10:02:00.847441 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 10:02:00.854190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 10:02:00.854272 ==
1779 10:02:00.854336 DQS Delay:
1780 10:02:00.854395 DQS0 = 0, DQS1 = 0
1781 10:02:00.857369 DQM Delay:
1782 10:02:00.857470 DQM0 = 95, DQM1 = 90
1783 10:02:00.860535 DQ Delay:
1784 10:02:00.863782 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1785 10:02:00.867496 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1786 10:02:00.867576 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1787 10:02:00.873925 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =96
1788 10:02:00.874032
1789 10:02:00.874098
1790 10:02:00.880917 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1791 10:02:00.884216 CH1 RK0: MR19=606, MR18=2C48
1792 10:02:00.890566 CH1_RK0: MR19=0x606, MR18=0x2C48, DQSOSC=391, MR23=63, INC=96, DEC=64
1793 10:02:00.890671
1794 10:02:00.894033 ----->DramcWriteLeveling(PI) begin...
1795 10:02:00.894114 ==
1796 10:02:00.897188 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 10:02:00.901019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 10:02:00.901101 ==
1799 10:02:00.904197 Write leveling (Byte 0): 25 => 25
1800 10:02:00.907422 Write leveling (Byte 1): 26 => 26
1801 10:02:00.910599 DramcWriteLeveling(PI) end<-----
1802 10:02:00.910680
1803 10:02:00.910743 ==
1804 10:02:00.914459 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 10:02:00.917374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 10:02:00.917480 ==
1807 10:02:00.921230 [Gating] SW mode calibration
1808 10:02:00.927523 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 10:02:00.934132 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 10:02:00.937844 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1811 10:02:00.940912 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1812 10:02:00.947443 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 10:02:00.950918 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 10:02:00.954516 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 10:02:00.960931 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:02:00.964733 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:02:00.968046 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:02:00.971336 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:02:00.977708 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 10:02:00.981007 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:02:00.984687 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:02:00.991328 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:02:00.994614 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:02:00.998035 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:02:01.004245 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:02:01.007880 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1827 10:02:01.011096 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1828 10:02:01.017774 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:02:01.020969 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:02:01.024623 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:02:01.031221 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:02:01.034475 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 10:02:01.037715 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 10:02:01.044770 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 10:02:01.047872 0 9 4 | B1->B0 | 2c2c 2323 | 0 1 | (0 0) (1 1)
1836 10:02:01.051547 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1837 10:02:01.054724 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 10:02:01.061078 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 10:02:01.064612 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 10:02:01.068128 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 10:02:01.075097 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 10:02:01.078209 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1843 10:02:01.081496 0 10 4 | B1->B0 | 2a2a 2e2e | 1 1 | (1 0) (1 0)
1844 10:02:01.088449 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 10:02:01.091577 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 10:02:01.094947 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 10:02:01.101420 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 10:02:01.105268 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 10:02:01.108285 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 10:02:01.111830 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1851 10:02:01.118192 0 11 4 | B1->B0 | 3a3a 2d2d | 0 0 | (1 1) (0 0)
1852 10:02:01.121907 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1853 10:02:01.125174 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 10:02:01.131378 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 10:02:01.134882 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 10:02:01.138468 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 10:02:01.144915 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 10:02:01.148583 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1859 10:02:01.151753 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1860 10:02:01.158127 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 10:02:01.161982 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 10:02:01.165123 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 10:02:01.171629 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 10:02:01.174855 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 10:02:01.178596 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:02:01.185050 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:02:01.188180 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 10:02:01.191664 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:02:01.198445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 10:02:01.201645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 10:02:01.204907 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 10:02:01.211483 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 10:02:01.214730 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:02:01.218531 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 10:02:01.221477 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1876 10:02:01.227983 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 10:02:01.231900 Total UI for P1: 0, mck2ui 16
1878 10:02:01.235085 best dqsien dly found for B0: ( 0, 14, 4)
1879 10:02:01.238053 Total UI for P1: 0, mck2ui 16
1880 10:02:01.241596 best dqsien dly found for B1: ( 0, 14, 4)
1881 10:02:01.245023 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1882 10:02:01.248080 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1883 10:02:01.248161
1884 10:02:01.251402 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1885 10:02:01.255161 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1886 10:02:01.258464 [Gating] SW calibration Done
1887 10:02:01.258544 ==
1888 10:02:01.261716 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 10:02:01.264911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 10:02:01.264992 ==
1891 10:02:01.268118 RX Vref Scan: 0
1892 10:02:01.268198
1893 10:02:01.268262 RX Vref 0 -> 0, step: 1
1894 10:02:01.268321
1895 10:02:01.271845 RX Delay -130 -> 252, step: 16
1896 10:02:01.275050 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1897 10:02:01.281556 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1898 10:02:01.284739 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1899 10:02:01.288414 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1900 10:02:01.291574 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1901 10:02:01.294820 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1902 10:02:01.301772 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1903 10:02:01.304858 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1904 10:02:01.308432 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1905 10:02:01.311855 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1906 10:02:01.315026 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1907 10:02:01.321695 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1908 10:02:01.325396 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1909 10:02:01.328503 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1910 10:02:01.332251 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1911 10:02:01.335232 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1912 10:02:01.335337 ==
1913 10:02:01.338877 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 10:02:01.345399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 10:02:01.345479 ==
1916 10:02:01.345541 DQS Delay:
1917 10:02:01.348497 DQS0 = 0, DQS1 = 0
1918 10:02:01.348578 DQM Delay:
1919 10:02:01.348648 DQM0 = 94, DQM1 = 92
1920 10:02:01.352415 DQ Delay:
1921 10:02:01.355381 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1922 10:02:01.358470 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1923 10:02:01.362323 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1924 10:02:01.365537 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1925 10:02:01.365617
1926 10:02:01.365680
1927 10:02:01.365739 ==
1928 10:02:01.368623 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 10:02:01.371714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 10:02:01.371794 ==
1931 10:02:01.371857
1932 10:02:01.371915
1933 10:02:01.375701 TX Vref Scan disable
1934 10:02:01.378893 == TX Byte 0 ==
1935 10:02:01.382175 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1936 10:02:01.385553 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1937 10:02:01.388590 == TX Byte 1 ==
1938 10:02:01.391759 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1939 10:02:01.395732 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1940 10:02:01.395811 ==
1941 10:02:01.398864 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 10:02:01.402086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 10:02:01.405446 ==
1944 10:02:01.416255 TX Vref=22, minBit 0, minWin=27, winSum=439
1945 10:02:01.420084 TX Vref=24, minBit 1, minWin=26, winSum=440
1946 10:02:01.423130 TX Vref=26, minBit 0, minWin=27, winSum=445
1947 10:02:01.426924 TX Vref=28, minBit 0, minWin=27, winSum=445
1948 10:02:01.429793 TX Vref=30, minBit 0, minWin=27, winSum=446
1949 10:02:01.433249 TX Vref=32, minBit 0, minWin=27, winSum=446
1950 10:02:01.439794 [TxChooseVref] Worse bit 0, Min win 27, Win sum 446, Final Vref 30
1951 10:02:01.439878
1952 10:02:01.443451 Final TX Range 1 Vref 30
1953 10:02:01.443531
1954 10:02:01.443618 ==
1955 10:02:01.446840 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 10:02:01.450313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 10:02:01.450394 ==
1958 10:02:01.450458
1959 10:02:01.450516
1960 10:02:01.453458 TX Vref Scan disable
1961 10:02:01.456559 == TX Byte 0 ==
1962 10:02:01.460137 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1963 10:02:01.463478 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1964 10:02:01.466810 == TX Byte 1 ==
1965 10:02:01.470332 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1966 10:02:01.473625 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1967 10:02:01.473731
1968 10:02:01.476603 [DATLAT]
1969 10:02:01.476690 Freq=800, CH1 RK1
1970 10:02:01.476769
1971 10:02:01.479882 DATLAT Default: 0xa
1972 10:02:01.479981 0, 0xFFFF, sum = 0
1973 10:02:01.482974 1, 0xFFFF, sum = 0
1974 10:02:01.483161 2, 0xFFFF, sum = 0
1975 10:02:01.486473 3, 0xFFFF, sum = 0
1976 10:02:01.486575 4, 0xFFFF, sum = 0
1977 10:02:01.489926 5, 0xFFFF, sum = 0
1978 10:02:01.490027 6, 0xFFFF, sum = 0
1979 10:02:01.493259 7, 0xFFFF, sum = 0
1980 10:02:01.493411 8, 0xFFFF, sum = 0
1981 10:02:01.496463 9, 0x0, sum = 1
1982 10:02:01.496538 10, 0x0, sum = 2
1983 10:02:01.499822 11, 0x0, sum = 3
1984 10:02:01.499893 12, 0x0, sum = 4
1985 10:02:01.503077 best_step = 10
1986 10:02:01.503162
1987 10:02:01.503251 ==
1988 10:02:01.506407 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 10:02:01.509706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 10:02:01.509786 ==
1991 10:02:01.513032 RX Vref Scan: 0
1992 10:02:01.513112
1993 10:02:01.513175 RX Vref 0 -> 0, step: 1
1994 10:02:01.513234
1995 10:02:01.517001 RX Delay -79 -> 252, step: 8
1996 10:02:01.523475 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1997 10:02:01.526601 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1998 10:02:01.529962 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1999 10:02:01.533660 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2000 10:02:01.536884 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2001 10:02:01.540075 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2002 10:02:01.546843 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2003 10:02:01.550449 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2004 10:02:01.553397 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2005 10:02:01.556618 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2006 10:02:01.560053 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2007 10:02:01.563520 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2008 10:02:01.570243 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2009 10:02:01.573901 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2010 10:02:01.576759 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2011 10:02:01.579993 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2012 10:02:01.580100 ==
2013 10:02:01.583735 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 10:02:01.589972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 10:02:01.590070 ==
2016 10:02:01.590134 DQS Delay:
2017 10:02:01.590225 DQS0 = 0, DQS1 = 0
2018 10:02:01.593350 DQM Delay:
2019 10:02:01.593431 DQM0 = 97, DQM1 = 91
2020 10:02:01.596622 DQ Delay:
2021 10:02:01.600346 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2022 10:02:01.603569 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2023 10:02:01.607014 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2024 10:02:01.610171 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2025 10:02:01.610293
2026 10:02:01.610404
2027 10:02:01.616926 [DQSOSCAuto] RK1, (LSB)MR18= 0x460f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2028 10:02:01.620306 CH1 RK1: MR19=606, MR18=460F
2029 10:02:01.626849 CH1_RK1: MR19=0x606, MR18=0x460F, DQSOSC=392, MR23=63, INC=96, DEC=64
2030 10:02:01.630172 [RxdqsGatingPostProcess] freq 800
2031 10:02:01.633990 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2032 10:02:01.637258 Pre-setting of DQS Precalculation
2033 10:02:01.643691 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2034 10:02:01.650450 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2035 10:02:01.657046 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2036 10:02:01.657129
2037 10:02:01.657193
2038 10:02:01.660975 [Calibration Summary] 1600 Mbps
2039 10:02:01.661057 CH 0, Rank 0
2040 10:02:01.663890 SW Impedance : PASS
2041 10:02:01.667399 DUTY Scan : NO K
2042 10:02:01.667510 ZQ Calibration : PASS
2043 10:02:01.670635 Jitter Meter : NO K
2044 10:02:01.670715 CBT Training : PASS
2045 10:02:01.674036 Write leveling : PASS
2046 10:02:01.677596 RX DQS gating : PASS
2047 10:02:01.677677 RX DQ/DQS(RDDQC) : PASS
2048 10:02:01.680684 TX DQ/DQS : PASS
2049 10:02:01.684212 RX DATLAT : PASS
2050 10:02:01.684293 RX DQ/DQS(Engine): PASS
2051 10:02:01.687540 TX OE : NO K
2052 10:02:01.687647 All Pass.
2053 10:02:01.687712
2054 10:02:01.690596 CH 0, Rank 1
2055 10:02:01.690676 SW Impedance : PASS
2056 10:02:01.693993 DUTY Scan : NO K
2057 10:02:01.697264 ZQ Calibration : PASS
2058 10:02:01.697338 Jitter Meter : NO K
2059 10:02:01.700547 CBT Training : PASS
2060 10:02:01.704182 Write leveling : PASS
2061 10:02:01.704264 RX DQS gating : PASS
2062 10:02:01.707324 RX DQ/DQS(RDDQC) : PASS
2063 10:02:01.707404 TX DQ/DQS : PASS
2064 10:02:01.710505 RX DATLAT : PASS
2065 10:02:01.714385 RX DQ/DQS(Engine): PASS
2066 10:02:01.714501 TX OE : NO K
2067 10:02:01.717598 All Pass.
2068 10:02:01.717682
2069 10:02:01.717749 CH 1, Rank 0
2070 10:02:01.720849 SW Impedance : PASS
2071 10:02:01.720931 DUTY Scan : NO K
2072 10:02:01.724165 ZQ Calibration : PASS
2073 10:02:01.727382 Jitter Meter : NO K
2074 10:02:01.727465 CBT Training : PASS
2075 10:02:01.730747 Write leveling : PASS
2076 10:02:01.734532 RX DQS gating : PASS
2077 10:02:01.734615 RX DQ/DQS(RDDQC) : PASS
2078 10:02:01.737582 TX DQ/DQS : PASS
2079 10:02:01.740839 RX DATLAT : PASS
2080 10:02:01.740919 RX DQ/DQS(Engine): PASS
2081 10:02:01.744099 TX OE : NO K
2082 10:02:01.744180 All Pass.
2083 10:02:01.744255
2084 10:02:01.747299 CH 1, Rank 1
2085 10:02:01.747379 SW Impedance : PASS
2086 10:02:01.750610 DUTY Scan : NO K
2087 10:02:01.750690 ZQ Calibration : PASS
2088 10:02:01.754441 Jitter Meter : NO K
2089 10:02:01.757689 CBT Training : PASS
2090 10:02:01.757770 Write leveling : PASS
2091 10:02:01.760995 RX DQS gating : PASS
2092 10:02:01.764776 RX DQ/DQS(RDDQC) : PASS
2093 10:02:01.764857 TX DQ/DQS : PASS
2094 10:02:01.768049 RX DATLAT : PASS
2095 10:02:01.771319 RX DQ/DQS(Engine): PASS
2096 10:02:01.771400 TX OE : NO K
2097 10:02:01.771464 All Pass.
2098 10:02:01.774366
2099 10:02:01.774434 DramC Write-DBI off
2100 10:02:01.777661 PER_BANK_REFRESH: Hybrid Mode
2101 10:02:01.777729 TX_TRACKING: ON
2102 10:02:01.781466 [GetDramInforAfterCalByMRR] Vendor 6.
2103 10:02:01.784630 [GetDramInforAfterCalByMRR] Revision 606.
2104 10:02:01.791311 [GetDramInforAfterCalByMRR] Revision 2 0.
2105 10:02:01.791392 MR0 0x3b3b
2106 10:02:01.791466 MR8 0x5151
2107 10:02:01.794527 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 10:02:01.794638
2109 10:02:01.797912 MR0 0x3b3b
2110 10:02:01.798054 MR8 0x5151
2111 10:02:01.801317 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 10:02:01.801424
2113 10:02:01.811117 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2114 10:02:01.814627 [FAST_K] Save calibration result to emmc
2115 10:02:01.817877 [FAST_K] Save calibration result to emmc
2116 10:02:01.821392 dram_init: config_dvfs: 1
2117 10:02:01.824479 dramc_set_vcore_voltage set vcore to 662500
2118 10:02:01.824621 Read voltage for 1200, 2
2119 10:02:01.828176 Vio18 = 0
2120 10:02:01.828274 Vcore = 662500
2121 10:02:01.828338 Vdram = 0
2122 10:02:01.831274 Vddq = 0
2123 10:02:01.831373 Vmddr = 0
2124 10:02:01.834511 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2125 10:02:01.841685 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2126 10:02:01.844794 MEM_TYPE=3, freq_sel=15
2127 10:02:01.847851 sv_algorithm_assistance_LP4_1600
2128 10:02:01.851153 ============ PULL DRAM RESETB DOWN ============
2129 10:02:01.854457 ========== PULL DRAM RESETB DOWN end =========
2130 10:02:01.861584 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2131 10:02:01.864843 ===================================
2132 10:02:01.864923 LPDDR4 DRAM CONFIGURATION
2133 10:02:01.867963 ===================================
2134 10:02:01.871243 EX_ROW_EN[0] = 0x0
2135 10:02:01.871322 EX_ROW_EN[1] = 0x0
2136 10:02:01.874573 LP4Y_EN = 0x0
2137 10:02:01.874651 WORK_FSP = 0x0
2138 10:02:01.877835 WL = 0x4
2139 10:02:01.877913 RL = 0x4
2140 10:02:01.881569 BL = 0x2
2141 10:02:01.881652 RPST = 0x0
2142 10:02:01.884857 RD_PRE = 0x0
2143 10:02:01.888064 WR_PRE = 0x1
2144 10:02:01.888143 WR_PST = 0x0
2145 10:02:01.891169 DBI_WR = 0x0
2146 10:02:01.891256 DBI_RD = 0x0
2147 10:02:01.894450 OTF = 0x1
2148 10:02:01.898181 ===================================
2149 10:02:01.901235 ===================================
2150 10:02:01.901316 ANA top config
2151 10:02:01.904767 ===================================
2152 10:02:01.907759 DLL_ASYNC_EN = 0
2153 10:02:01.907840 ALL_SLAVE_EN = 0
2154 10:02:01.911553 NEW_RANK_MODE = 1
2155 10:02:01.914750 DLL_IDLE_MODE = 1
2156 10:02:01.917859 LP45_APHY_COMB_EN = 1
2157 10:02:01.921583 TX_ODT_DIS = 1
2158 10:02:01.921665 NEW_8X_MODE = 1
2159 10:02:01.924761 ===================================
2160 10:02:01.928475 ===================================
2161 10:02:01.931175 data_rate = 2400
2162 10:02:01.934523 CKR = 1
2163 10:02:01.937995 DQ_P2S_RATIO = 8
2164 10:02:01.941208 ===================================
2165 10:02:01.944812 CA_P2S_RATIO = 8
2166 10:02:01.944895 DQ_CA_OPEN = 0
2167 10:02:01.948214 DQ_SEMI_OPEN = 0
2168 10:02:01.951470 CA_SEMI_OPEN = 0
2169 10:02:01.954629 CA_FULL_RATE = 0
2170 10:02:01.957859 DQ_CKDIV4_EN = 0
2171 10:02:01.961782 CA_CKDIV4_EN = 0
2172 10:02:01.961864 CA_PREDIV_EN = 0
2173 10:02:01.964977 PH8_DLY = 17
2174 10:02:01.968153 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2175 10:02:01.971393 DQ_AAMCK_DIV = 4
2176 10:02:01.974883 CA_AAMCK_DIV = 4
2177 10:02:01.978087 CA_ADMCK_DIV = 4
2178 10:02:01.978195 DQ_TRACK_CA_EN = 0
2179 10:02:01.981425 CA_PICK = 1200
2180 10:02:01.985131 CA_MCKIO = 1200
2181 10:02:01.988368 MCKIO_SEMI = 0
2182 10:02:01.991492 PLL_FREQ = 2366
2183 10:02:01.994721 DQ_UI_PI_RATIO = 32
2184 10:02:01.998064 CA_UI_PI_RATIO = 0
2185 10:02:02.001414 ===================================
2186 10:02:02.004665 ===================================
2187 10:02:02.004738 memory_type:LPDDR4
2188 10:02:02.008254 GP_NUM : 10
2189 10:02:02.011914 SRAM_EN : 1
2190 10:02:02.012004 MD32_EN : 0
2191 10:02:02.015291 ===================================
2192 10:02:02.018242 [ANA_INIT] >>>>>>>>>>>>>>
2193 10:02:02.021941 <<<<<< [CONFIGURE PHASE]: ANA_TX
2194 10:02:02.025102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2195 10:02:02.028269 ===================================
2196 10:02:02.031464 data_rate = 2400,PCW = 0X5b00
2197 10:02:02.031545 ===================================
2198 10:02:02.038720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2199 10:02:02.041979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 10:02:02.048623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 10:02:02.051989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2202 10:02:02.055083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2203 10:02:02.058623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2204 10:02:02.062154 [ANA_INIT] flow start
2205 10:02:02.062277 [ANA_INIT] PLL >>>>>>>>
2206 10:02:02.064939 [ANA_INIT] PLL <<<<<<<<
2207 10:02:02.068185 [ANA_INIT] MIDPI >>>>>>>>
2208 10:02:02.071833 [ANA_INIT] MIDPI <<<<<<<<
2209 10:02:02.071916 [ANA_INIT] DLL >>>>>>>>
2210 10:02:02.075192 [ANA_INIT] DLL <<<<<<<<
2211 10:02:02.078433 [ANA_INIT] flow end
2212 10:02:02.081747 ============ LP4 DIFF to SE enter ============
2213 10:02:02.085180 ============ LP4 DIFF to SE exit ============
2214 10:02:02.088310 [ANA_INIT] <<<<<<<<<<<<<
2215 10:02:02.092169 [Flow] Enable top DCM control >>>>>
2216 10:02:02.095511 [Flow] Enable top DCM control <<<<<
2217 10:02:02.095585 Enable DLL master slave shuffle
2218 10:02:02.102046 ==============================================================
2219 10:02:02.105435 Gating Mode config
2220 10:02:02.108830 ==============================================================
2221 10:02:02.112127 Config description:
2222 10:02:02.122434 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2223 10:02:02.128972 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2224 10:02:02.131981 SELPH_MODE 0: By rank 1: By Phase
2225 10:02:02.139166 ==============================================================
2226 10:02:02.142515 GAT_TRACK_EN = 1
2227 10:02:02.145772 RX_GATING_MODE = 2
2228 10:02:02.149023 RX_GATING_TRACK_MODE = 2
2229 10:02:02.149120 SELPH_MODE = 1
2230 10:02:02.152464 PICG_EARLY_EN = 1
2231 10:02:02.155756 VALID_LAT_VALUE = 1
2232 10:02:02.162405 ==============================================================
2233 10:02:02.165744 Enter into Gating configuration >>>>
2234 10:02:02.169070 Exit from Gating configuration <<<<
2235 10:02:02.172140 Enter into DVFS_PRE_config >>>>>
2236 10:02:02.182775 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2237 10:02:02.185683 Exit from DVFS_PRE_config <<<<<
2238 10:02:02.189091 Enter into PICG configuration >>>>
2239 10:02:02.192850 Exit from PICG configuration <<<<
2240 10:02:02.195729 [RX_INPUT] configuration >>>>>
2241 10:02:02.199243 [RX_INPUT] configuration <<<<<
2242 10:02:02.202364 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2243 10:02:02.209145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2244 10:02:02.215937 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 10:02:02.219276 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 10:02:02.225758 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 10:02:02.232815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 10:02:02.235780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2249 10:02:02.239533 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2250 10:02:02.245945 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2251 10:02:02.249022 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2252 10:02:02.252895 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2253 10:02:02.259466 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2254 10:02:02.262739 ===================================
2255 10:02:02.262842 LPDDR4 DRAM CONFIGURATION
2256 10:02:02.266042 ===================================
2257 10:02:02.269275 EX_ROW_EN[0] = 0x0
2258 10:02:02.269349 EX_ROW_EN[1] = 0x0
2259 10:02:02.272584 LP4Y_EN = 0x0
2260 10:02:02.275690 WORK_FSP = 0x0
2261 10:02:02.275798 WL = 0x4
2262 10:02:02.279095 RL = 0x4
2263 10:02:02.279195 BL = 0x2
2264 10:02:02.282361 RPST = 0x0
2265 10:02:02.282464 RD_PRE = 0x0
2266 10:02:02.286218 WR_PRE = 0x1
2267 10:02:02.286302 WR_PST = 0x0
2268 10:02:02.289653 DBI_WR = 0x0
2269 10:02:02.289725 DBI_RD = 0x0
2270 10:02:02.292940 OTF = 0x1
2271 10:02:02.295993 ===================================
2272 10:02:02.299018 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2273 10:02:02.302616 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2274 10:02:02.306102 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 10:02:02.309299 ===================================
2276 10:02:02.312504 LPDDR4 DRAM CONFIGURATION
2277 10:02:02.315812 ===================================
2278 10:02:02.319431 EX_ROW_EN[0] = 0x10
2279 10:02:02.319512 EX_ROW_EN[1] = 0x0
2280 10:02:02.322969 LP4Y_EN = 0x0
2281 10:02:02.323050 WORK_FSP = 0x0
2282 10:02:02.326267 WL = 0x4
2283 10:02:02.326347 RL = 0x4
2284 10:02:02.329350 BL = 0x2
2285 10:02:02.329430 RPST = 0x0
2286 10:02:02.333033 RD_PRE = 0x0
2287 10:02:02.333113 WR_PRE = 0x1
2288 10:02:02.336311 WR_PST = 0x0
2289 10:02:02.336392 DBI_WR = 0x0
2290 10:02:02.339522 DBI_RD = 0x0
2291 10:02:02.339609 OTF = 0x1
2292 10:02:02.343124 ===================================
2293 10:02:02.349855 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2294 10:02:02.349937 ==
2295 10:02:02.353129 Dram Type= 6, Freq= 0, CH_0, rank 0
2296 10:02:02.359903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2297 10:02:02.359985 ==
2298 10:02:02.360068 [Duty_Offset_Calibration]
2299 10:02:02.363153 B0:2 B1:1 CA:1
2300 10:02:02.363233
2301 10:02:02.366298 [DutyScan_Calibration_Flow] k_type=0
2302 10:02:02.374818
2303 10:02:02.374899 ==CLK 0==
2304 10:02:02.378171 Final CLK duty delay cell = 0
2305 10:02:02.381715 [0] MAX Duty = 5187%(X100), DQS PI = 24
2306 10:02:02.384909 [0] MIN Duty = 4875%(X100), DQS PI = 0
2307 10:02:02.384990 [0] AVG Duty = 5031%(X100)
2308 10:02:02.385054
2309 10:02:02.388436 CH0 CLK Duty spec in!! Max-Min= 312%
2310 10:02:02.395076 [DutyScan_Calibration_Flow] ====Done====
2311 10:02:02.395181
2312 10:02:02.398348 [DutyScan_Calibration_Flow] k_type=1
2313 10:02:02.413949
2314 10:02:02.414035 ==DQS 0 ==
2315 10:02:02.417261 Final DQS duty delay cell = -4
2316 10:02:02.420159 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2317 10:02:02.423642 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2318 10:02:02.426983 [-4] AVG Duty = 4937%(X100)
2319 10:02:02.427063
2320 10:02:02.427164 ==DQS 1 ==
2321 10:02:02.430183 Final DQS duty delay cell = 0
2322 10:02:02.433580 [0] MAX Duty = 5156%(X100), DQS PI = 0
2323 10:02:02.437016 [0] MIN Duty = 5031%(X100), DQS PI = 32
2324 10:02:02.440519 [0] AVG Duty = 5093%(X100)
2325 10:02:02.440624
2326 10:02:02.443456 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2327 10:02:02.443570
2328 10:02:02.447061 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2329 10:02:02.450240 [DutyScan_Calibration_Flow] ====Done====
2330 10:02:02.450358
2331 10:02:02.453393 [DutyScan_Calibration_Flow] k_type=3
2332 10:02:02.470112
2333 10:02:02.470194 ==DQM 0 ==
2334 10:02:02.473428 Final DQM duty delay cell = 0
2335 10:02:02.476695 [0] MAX Duty = 5156%(X100), DQS PI = 30
2336 10:02:02.479985 [0] MIN Duty = 4907%(X100), DQS PI = 58
2337 10:02:02.480080 [0] AVG Duty = 5031%(X100)
2338 10:02:02.483107
2339 10:02:02.483185 ==DQM 1 ==
2340 10:02:02.486350 Final DQM duty delay cell = -4
2341 10:02:02.490084 [-4] MAX Duty = 5000%(X100), DQS PI = 60
2342 10:02:02.493087 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2343 10:02:02.496480 [-4] AVG Duty = 4937%(X100)
2344 10:02:02.496560
2345 10:02:02.499780 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2346 10:02:02.499860
2347 10:02:02.503095 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2348 10:02:02.506387 [DutyScan_Calibration_Flow] ====Done====
2349 10:02:02.506466
2350 10:02:02.509660 [DutyScan_Calibration_Flow] k_type=2
2351 10:02:02.526506
2352 10:02:02.526587 ==DQ 0 ==
2353 10:02:02.530428 Final DQ duty delay cell = 0
2354 10:02:02.533548 [0] MAX Duty = 5062%(X100), DQS PI = 28
2355 10:02:02.537026 [0] MIN Duty = 4906%(X100), DQS PI = 0
2356 10:02:02.537106 [0] AVG Duty = 4984%(X100)
2357 10:02:02.537168
2358 10:02:02.539882 ==DQ 1 ==
2359 10:02:02.543475 Final DQ duty delay cell = 0
2360 10:02:02.547109 [0] MAX Duty = 5093%(X100), DQS PI = 10
2361 10:02:02.550108 [0] MIN Duty = 4938%(X100), DQS PI = 36
2362 10:02:02.550188 [0] AVG Duty = 5015%(X100)
2363 10:02:02.550252
2364 10:02:02.553768 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2365 10:02:02.553848
2366 10:02:02.556820 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2367 10:02:02.563206 [DutyScan_Calibration_Flow] ====Done====
2368 10:02:02.563285 ==
2369 10:02:02.566854 Dram Type= 6, Freq= 0, CH_1, rank 0
2370 10:02:02.570181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 10:02:02.570284 ==
2372 10:02:02.573719 [Duty_Offset_Calibration]
2373 10:02:02.573800 B0:1 B1:0 CA:0
2374 10:02:02.573863
2375 10:02:02.576834 [DutyScan_Calibration_Flow] k_type=0
2376 10:02:02.586049
2377 10:02:02.586146 ==CLK 0==
2378 10:02:02.589129 Final CLK duty delay cell = -4
2379 10:02:02.592313 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2380 10:02:02.596165 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2381 10:02:02.599487 [-4] AVG Duty = 4969%(X100)
2382 10:02:02.599619
2383 10:02:02.602785 CH1 CLK Duty spec in!! Max-Min= 124%
2384 10:02:02.606108 [DutyScan_Calibration_Flow] ====Done====
2385 10:02:02.606188
2386 10:02:02.609387 [DutyScan_Calibration_Flow] k_type=1
2387 10:02:02.625413
2388 10:02:02.625493 ==DQS 0 ==
2389 10:02:02.628767 Final DQS duty delay cell = 0
2390 10:02:02.632139 [0] MAX Duty = 5094%(X100), DQS PI = 24
2391 10:02:02.635422 [0] MIN Duty = 4875%(X100), DQS PI = 0
2392 10:02:02.635535 [0] AVG Duty = 4984%(X100)
2393 10:02:02.639427
2394 10:02:02.639507 ==DQS 1 ==
2395 10:02:02.642743 Final DQS duty delay cell = 0
2396 10:02:02.645965 [0] MAX Duty = 5218%(X100), DQS PI = 18
2397 10:02:02.649321 [0] MIN Duty = 4969%(X100), DQS PI = 10
2398 10:02:02.649426 [0] AVG Duty = 5093%(X100)
2399 10:02:02.649505
2400 10:02:02.652486 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2401 10:02:02.656103
2402 10:02:02.659154 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2403 10:02:02.662498 [DutyScan_Calibration_Flow] ====Done====
2404 10:02:02.662619
2405 10:02:02.665817 [DutyScan_Calibration_Flow] k_type=3
2406 10:02:02.682517
2407 10:02:02.682651 ==DQM 0 ==
2408 10:02:02.685675 Final DQM duty delay cell = 0
2409 10:02:02.688825 [0] MAX Duty = 5156%(X100), DQS PI = 6
2410 10:02:02.691858 [0] MIN Duty = 5031%(X100), DQS PI = 0
2411 10:02:02.695467 [0] AVG Duty = 5093%(X100)
2412 10:02:02.695570
2413 10:02:02.695666 ==DQM 1 ==
2414 10:02:02.698677 Final DQM duty delay cell = 0
2415 10:02:02.702000 [0] MAX Duty = 5031%(X100), DQS PI = 16
2416 10:02:02.705319 [0] MIN Duty = 4907%(X100), DQS PI = 34
2417 10:02:02.708447 [0] AVG Duty = 4969%(X100)
2418 10:02:02.708521
2419 10:02:02.712072 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2420 10:02:02.712174
2421 10:02:02.715386 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2422 10:02:02.718502 [DutyScan_Calibration_Flow] ====Done====
2423 10:02:02.718628
2424 10:02:02.721759 [DutyScan_Calibration_Flow] k_type=2
2425 10:02:02.737725
2426 10:02:02.737836 ==DQ 0 ==
2427 10:02:02.740951 Final DQ duty delay cell = -4
2428 10:02:02.744859 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2429 10:02:02.748009 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2430 10:02:02.748114 [-4] AVG Duty = 5000%(X100)
2431 10:02:02.751231
2432 10:02:02.751333 ==DQ 1 ==
2433 10:02:02.754295 Final DQ duty delay cell = 0
2434 10:02:02.757828 [0] MAX Duty = 5125%(X100), DQS PI = 20
2435 10:02:02.760965 [0] MIN Duty = 4969%(X100), DQS PI = 12
2436 10:02:02.761072 [0] AVG Duty = 5047%(X100)
2437 10:02:02.764093
2438 10:02:02.767748 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2439 10:02:02.767847
2440 10:02:02.771421 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2441 10:02:02.774657 [DutyScan_Calibration_Flow] ====Done====
2442 10:02:02.777918 nWR fixed to 30
2443 10:02:02.778021 [ModeRegInit_LP4] CH0 RK0
2444 10:02:02.781102 [ModeRegInit_LP4] CH0 RK1
2445 10:02:02.784481 [ModeRegInit_LP4] CH1 RK0
2446 10:02:02.787862 [ModeRegInit_LP4] CH1 RK1
2447 10:02:02.787971 match AC timing 7
2448 10:02:02.791097 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2449 10:02:02.797758 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2450 10:02:02.801432 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2451 10:02:02.804696 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2452 10:02:02.811377 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2453 10:02:02.811480 ==
2454 10:02:02.814560 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 10:02:02.817580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 10:02:02.817685 ==
2457 10:02:02.824215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2458 10:02:02.830731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2459 10:02:02.838040 [CA 0] Center 39 (8~70) winsize 63
2460 10:02:02.841449 [CA 1] Center 39 (8~70) winsize 63
2461 10:02:02.844873 [CA 2] Center 35 (5~66) winsize 62
2462 10:02:02.848357 [CA 3] Center 34 (4~65) winsize 62
2463 10:02:02.851710 [CA 4] Center 33 (3~64) winsize 62
2464 10:02:02.854410 [CA 5] Center 32 (3~62) winsize 60
2465 10:02:02.854514
2466 10:02:02.858388 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2467 10:02:02.858491
2468 10:02:02.861552 [CATrainingPosCal] consider 1 rank data
2469 10:02:02.864682 u2DelayCellTimex100 = 270/100 ps
2470 10:02:02.868233 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2471 10:02:02.871333 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2472 10:02:02.878073 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2473 10:02:02.881563 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2474 10:02:02.884825 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2475 10:02:02.888142 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2476 10:02:02.888249
2477 10:02:02.891477 CA PerBit enable=1, Macro0, CA PI delay=32
2478 10:02:02.891563
2479 10:02:02.894849 [CBTSetCACLKResult] CA Dly = 32
2480 10:02:02.894930 CS Dly: 6 (0~37)
2481 10:02:02.894995 ==
2482 10:02:02.898159 Dram Type= 6, Freq= 0, CH_0, rank 1
2483 10:02:02.904789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 10:02:02.904899 ==
2485 10:02:02.908197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 10:02:02.915191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2487 10:02:02.923688 [CA 0] Center 38 (8~69) winsize 62
2488 10:02:02.927299 [CA 1] Center 38 (8~69) winsize 62
2489 10:02:02.930694 [CA 2] Center 35 (4~66) winsize 63
2490 10:02:02.933985 [CA 3] Center 34 (4~65) winsize 62
2491 10:02:02.937266 [CA 4] Center 33 (3~63) winsize 61
2492 10:02:02.940426 [CA 5] Center 32 (3~62) winsize 60
2493 10:02:02.940535
2494 10:02:02.943576 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 10:02:02.943717
2496 10:02:02.947331 [CATrainingPosCal] consider 2 rank data
2497 10:02:02.950345 u2DelayCellTimex100 = 270/100 ps
2498 10:02:02.953962 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2499 10:02:02.957128 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2500 10:02:02.963923 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2501 10:02:02.967361 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2502 10:02:02.970341 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2503 10:02:02.973458 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2504 10:02:02.973536
2505 10:02:02.977225 CA PerBit enable=1, Macro0, CA PI delay=32
2506 10:02:02.977307
2507 10:02:02.980513 [CBTSetCACLKResult] CA Dly = 32
2508 10:02:02.980650 CS Dly: 6 (0~38)
2509 10:02:02.980764
2510 10:02:02.983560 ----->DramcWriteLeveling(PI) begin...
2511 10:02:02.987331 ==
2512 10:02:02.987442 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 10:02:02.993855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 10:02:02.993971 ==
2515 10:02:02.997244 Write leveling (Byte 0): 34 => 34
2516 10:02:03.000561 Write leveling (Byte 1): 28 => 28
2517 10:02:03.003947 DramcWriteLeveling(PI) end<-----
2518 10:02:03.004032
2519 10:02:03.004098 ==
2520 10:02:03.007246 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 10:02:03.010507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 10:02:03.010589 ==
2523 10:02:03.013808 [Gating] SW mode calibration
2524 10:02:03.020803 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2525 10:02:03.024134 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2526 10:02:03.030382 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
2527 10:02:03.034179 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2528 10:02:03.037473 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 10:02:03.043565 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 10:02:03.046992 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 10:02:03.050954 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 10:02:03.057228 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2533 10:02:03.060566 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
2534 10:02:03.063725 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2535 10:02:03.070452 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 10:02:03.073940 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 10:02:03.077205 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 10:02:03.084153 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 10:02:03.087231 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 10:02:03.090573 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2541 10:02:03.094253 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2542 10:02:03.100881 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
2543 10:02:03.103756 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 10:02:03.107540 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 10:02:03.114164 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 10:02:03.117462 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 10:02:03.120593 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 10:02:03.127627 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 10:02:03.130710 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 10:02:03.133763 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 10:02:03.140838 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 10:02:03.144084 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 10:02:03.147160 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 10:02:03.154282 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 10:02:03.157410 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:02:03.160683 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:02:03.167102 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 10:02:03.170975 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 10:02:03.174273 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 10:02:03.177544 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:02:03.183940 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 10:02:03.187549 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 10:02:03.191161 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 10:02:03.197394 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 10:02:03.201145 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 10:02:03.204269 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2567 10:02:03.207773 Total UI for P1: 0, mck2ui 16
2568 10:02:03.210848 best dqsien dly found for B0: ( 1, 3, 28)
2569 10:02:03.217739 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 10:02:03.217849 Total UI for P1: 0, mck2ui 16
2571 10:02:03.224431 best dqsien dly found for B1: ( 1, 4, 0)
2572 10:02:03.227936 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2573 10:02:03.231050 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2574 10:02:03.231148
2575 10:02:03.234195 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2576 10:02:03.237820 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2577 10:02:03.241012 [Gating] SW calibration Done
2578 10:02:03.241083 ==
2579 10:02:03.244384 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 10:02:03.247451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 10:02:03.247557 ==
2582 10:02:03.251200 RX Vref Scan: 0
2583 10:02:03.251305
2584 10:02:03.251396 RX Vref 0 -> 0, step: 1
2585 10:02:03.251483
2586 10:02:03.254389 RX Delay -40 -> 252, step: 8
2587 10:02:03.257620 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2588 10:02:03.260918 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2589 10:02:03.268085 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2590 10:02:03.271330 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2591 10:02:03.274502 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2592 10:02:03.277827 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2593 10:02:03.281074 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2594 10:02:03.287852 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2595 10:02:03.291090 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2596 10:02:03.294924 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2597 10:02:03.298071 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2598 10:02:03.301499 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2599 10:02:03.307908 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2600 10:02:03.311617 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2601 10:02:03.314671 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2602 10:02:03.317821 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2603 10:02:03.317902 ==
2604 10:02:03.321122 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 10:02:03.324712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 10:02:03.328420 ==
2607 10:02:03.328526 DQS Delay:
2608 10:02:03.328618 DQS0 = 0, DQS1 = 0
2609 10:02:03.331133 DQM Delay:
2610 10:02:03.331239 DQM0 = 121, DQM1 = 113
2611 10:02:03.334471 DQ Delay:
2612 10:02:03.338137 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2613 10:02:03.341360 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2614 10:02:03.344376 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2615 10:02:03.348086 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2616 10:02:03.348186
2617 10:02:03.348275
2618 10:02:03.348360 ==
2619 10:02:03.351483 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 10:02:03.355169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 10:02:03.355242 ==
2622 10:02:03.355302
2623 10:02:03.355408
2624 10:02:03.358317 TX Vref Scan disable
2625 10:02:03.361400 == TX Byte 0 ==
2626 10:02:03.364738 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2627 10:02:03.368558 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2628 10:02:03.371823 == TX Byte 1 ==
2629 10:02:03.375124 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2630 10:02:03.378381 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2631 10:02:03.378461 ==
2632 10:02:03.381822 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 10:02:03.385018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 10:02:03.388603 ==
2635 10:02:03.399142 TX Vref=22, minBit 5, minWin=24, winSum=404
2636 10:02:03.402601 TX Vref=24, minBit 0, minWin=25, winSum=412
2637 10:02:03.405813 TX Vref=26, minBit 4, minWin=24, winSum=417
2638 10:02:03.408627 TX Vref=28, minBit 0, minWin=26, winSum=424
2639 10:02:03.412529 TX Vref=30, minBit 10, minWin=25, winSum=420
2640 10:02:03.415711 TX Vref=32, minBit 0, minWin=26, winSum=426
2641 10:02:03.422504 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 32
2642 10:02:03.422605
2643 10:02:03.425750 Final TX Range 1 Vref 32
2644 10:02:03.425865
2645 10:02:03.425927 ==
2646 10:02:03.429019 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 10:02:03.432402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 10:02:03.432487 ==
2649 10:02:03.432576
2650 10:02:03.432664
2651 10:02:03.435673 TX Vref Scan disable
2652 10:02:03.438929 == TX Byte 0 ==
2653 10:02:03.442083 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2654 10:02:03.445531 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2655 10:02:03.448678 == TX Byte 1 ==
2656 10:02:03.452506 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2657 10:02:03.455649 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2658 10:02:03.455730
2659 10:02:03.458907 [DATLAT]
2660 10:02:03.458987 Freq=1200, CH0 RK0
2661 10:02:03.459052
2662 10:02:03.462218 DATLAT Default: 0xd
2663 10:02:03.462298 0, 0xFFFF, sum = 0
2664 10:02:03.465271 1, 0xFFFF, sum = 0
2665 10:02:03.465353 2, 0xFFFF, sum = 0
2666 10:02:03.468960 3, 0xFFFF, sum = 0
2667 10:02:03.469041 4, 0xFFFF, sum = 0
2668 10:02:03.472451 5, 0xFFFF, sum = 0
2669 10:02:03.472562 6, 0xFFFF, sum = 0
2670 10:02:03.475817 7, 0xFFFF, sum = 0
2671 10:02:03.475899 8, 0xFFFF, sum = 0
2672 10:02:03.479076 9, 0xFFFF, sum = 0
2673 10:02:03.482076 10, 0xFFFF, sum = 0
2674 10:02:03.482185 11, 0xFFFF, sum = 0
2675 10:02:03.485358 12, 0x0, sum = 1
2676 10:02:03.485440 13, 0x0, sum = 2
2677 10:02:03.485505 14, 0x0, sum = 3
2678 10:02:03.488955 15, 0x0, sum = 4
2679 10:02:03.489039 best_step = 13
2680 10:02:03.489103
2681 10:02:03.489226 ==
2682 10:02:03.492202 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 10:02:03.498840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 10:02:03.498921 ==
2685 10:02:03.498985 RX Vref Scan: 1
2686 10:02:03.499045
2687 10:02:03.502741 Set Vref Range= 32 -> 127
2688 10:02:03.502821
2689 10:02:03.505943 RX Vref 32 -> 127, step: 1
2690 10:02:03.506022
2691 10:02:03.509324 RX Delay -13 -> 252, step: 4
2692 10:02:03.509405
2693 10:02:03.512617 Set Vref, RX VrefLevel [Byte0]: 32
2694 10:02:03.515937 [Byte1]: 32
2695 10:02:03.516018
2696 10:02:03.519139 Set Vref, RX VrefLevel [Byte0]: 33
2697 10:02:03.522418 [Byte1]: 33
2698 10:02:03.522498
2699 10:02:03.525555 Set Vref, RX VrefLevel [Byte0]: 34
2700 10:02:03.529263 [Byte1]: 34
2701 10:02:03.532721
2702 10:02:03.532801 Set Vref, RX VrefLevel [Byte0]: 35
2703 10:02:03.536211 [Byte1]: 35
2704 10:02:03.540689
2705 10:02:03.540769 Set Vref, RX VrefLevel [Byte0]: 36
2706 10:02:03.544110 [Byte1]: 36
2707 10:02:03.548886
2708 10:02:03.548966 Set Vref, RX VrefLevel [Byte0]: 37
2709 10:02:03.552100 [Byte1]: 37
2710 10:02:03.556711
2711 10:02:03.556785 Set Vref, RX VrefLevel [Byte0]: 38
2712 10:02:03.559819 [Byte1]: 38
2713 10:02:03.564162
2714 10:02:03.564241 Set Vref, RX VrefLevel [Byte0]: 39
2715 10:02:03.567662 [Byte1]: 39
2716 10:02:03.572193
2717 10:02:03.572276 Set Vref, RX VrefLevel [Byte0]: 40
2718 10:02:03.575555 [Byte1]: 40
2719 10:02:03.580103
2720 10:02:03.580176 Set Vref, RX VrefLevel [Byte0]: 41
2721 10:02:03.583381 [Byte1]: 41
2722 10:02:03.587872
2723 10:02:03.588012 Set Vref, RX VrefLevel [Byte0]: 42
2724 10:02:03.591679 [Byte1]: 42
2725 10:02:03.595857
2726 10:02:03.595930 Set Vref, RX VrefLevel [Byte0]: 43
2727 10:02:03.599098 [Byte1]: 43
2728 10:02:03.603768
2729 10:02:03.603853 Set Vref, RX VrefLevel [Byte0]: 44
2730 10:02:03.607357 [Byte1]: 44
2731 10:02:03.611882
2732 10:02:03.611986 Set Vref, RX VrefLevel [Byte0]: 45
2733 10:02:03.615209 [Byte1]: 45
2734 10:02:03.620070
2735 10:02:03.620144 Set Vref, RX VrefLevel [Byte0]: 46
2736 10:02:03.622681 [Byte1]: 46
2737 10:02:03.627443
2738 10:02:03.627523 Set Vref, RX VrefLevel [Byte0]: 47
2739 10:02:03.630601 [Byte1]: 47
2740 10:02:03.635338
2741 10:02:03.635420 Set Vref, RX VrefLevel [Byte0]: 48
2742 10:02:03.638616 [Byte1]: 48
2743 10:02:03.643108
2744 10:02:03.643184 Set Vref, RX VrefLevel [Byte0]: 49
2745 10:02:03.646443 [Byte1]: 49
2746 10:02:03.650974
2747 10:02:03.651048 Set Vref, RX VrefLevel [Byte0]: 50
2748 10:02:03.654856 [Byte1]: 50
2749 10:02:03.659402
2750 10:02:03.659477 Set Vref, RX VrefLevel [Byte0]: 51
2751 10:02:03.662743 [Byte1]: 51
2752 10:02:03.667094
2753 10:02:03.667174 Set Vref, RX VrefLevel [Byte0]: 52
2754 10:02:03.670471 [Byte1]: 52
2755 10:02:03.675129
2756 10:02:03.675210 Set Vref, RX VrefLevel [Byte0]: 53
2757 10:02:03.678457 [Byte1]: 53
2758 10:02:03.683025
2759 10:02:03.683106 Set Vref, RX VrefLevel [Byte0]: 54
2760 10:02:03.686399 [Byte1]: 54
2761 10:02:03.690854
2762 10:02:03.690935 Set Vref, RX VrefLevel [Byte0]: 55
2763 10:02:03.694001 [Byte1]: 55
2764 10:02:03.698606
2765 10:02:03.698685 Set Vref, RX VrefLevel [Byte0]: 56
2766 10:02:03.701715 [Byte1]: 56
2767 10:02:03.706373
2768 10:02:03.706452 Set Vref, RX VrefLevel [Byte0]: 57
2769 10:02:03.709726 [Byte1]: 57
2770 10:02:03.714708
2771 10:02:03.714787 Set Vref, RX VrefLevel [Byte0]: 58
2772 10:02:03.717596 [Byte1]: 58
2773 10:02:03.722211
2774 10:02:03.722290 Set Vref, RX VrefLevel [Byte0]: 59
2775 10:02:03.725601 [Byte1]: 59
2776 10:02:03.730405
2777 10:02:03.730484 Set Vref, RX VrefLevel [Byte0]: 60
2778 10:02:03.733655 [Byte1]: 60
2779 10:02:03.738036
2780 10:02:03.738115 Set Vref, RX VrefLevel [Byte0]: 61
2781 10:02:03.741130 [Byte1]: 61
2782 10:02:03.745833
2783 10:02:03.745911 Set Vref, RX VrefLevel [Byte0]: 62
2784 10:02:03.748887 [Byte1]: 62
2785 10:02:03.754094
2786 10:02:03.754195 Set Vref, RX VrefLevel [Byte0]: 63
2787 10:02:03.757469 [Byte1]: 63
2788 10:02:03.762026
2789 10:02:03.762137 Set Vref, RX VrefLevel [Byte0]: 64
2790 10:02:03.765283 [Byte1]: 64
2791 10:02:03.769718
2792 10:02:03.769826 Set Vref, RX VrefLevel [Byte0]: 65
2793 10:02:03.772845 [Byte1]: 65
2794 10:02:03.777267
2795 10:02:03.780666 Set Vref, RX VrefLevel [Byte0]: 66
2796 10:02:03.780745 [Byte1]: 66
2797 10:02:03.785250
2798 10:02:03.785330 Set Vref, RX VrefLevel [Byte0]: 67
2799 10:02:03.788408 [Byte1]: 67
2800 10:02:03.793281
2801 10:02:03.793362 Set Vref, RX VrefLevel [Byte0]: 68
2802 10:02:03.796403 [Byte1]: 68
2803 10:02:03.800879
2804 10:02:03.800959 Final RX Vref Byte 0 = 55 to rank0
2805 10:02:03.804938 Final RX Vref Byte 1 = 49 to rank0
2806 10:02:03.808024 Final RX Vref Byte 0 = 55 to rank1
2807 10:02:03.811293 Final RX Vref Byte 1 = 49 to rank1==
2808 10:02:03.814556 Dram Type= 6, Freq= 0, CH_0, rank 0
2809 10:02:03.821257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2810 10:02:03.821338 ==
2811 10:02:03.821418 DQS Delay:
2812 10:02:03.821567 DQS0 = 0, DQS1 = 0
2813 10:02:03.824527 DQM Delay:
2814 10:02:03.824663 DQM0 = 120, DQM1 = 112
2815 10:02:03.827609 DQ Delay:
2816 10:02:03.831453 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =120
2817 10:02:03.834202 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2818 10:02:03.837611 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2819 10:02:03.841400 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2820 10:02:03.841480
2821 10:02:03.841543
2822 10:02:03.847872 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2823 10:02:03.850905 CH0 RK0: MR19=404, MR18=1610
2824 10:02:03.857808 CH0_RK0: MR19=0x404, MR18=0x1610, DQSOSC=401, MR23=63, INC=40, DEC=27
2825 10:02:03.857889
2826 10:02:03.861008 ----->DramcWriteLeveling(PI) begin...
2827 10:02:03.861090 ==
2828 10:02:03.864100 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 10:02:03.868213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 10:02:03.871423 ==
2831 10:02:03.871503 Write leveling (Byte 0): 32 => 32
2832 10:02:03.874794 Write leveling (Byte 1): 28 => 28
2833 10:02:03.877827 DramcWriteLeveling(PI) end<-----
2834 10:02:03.877907
2835 10:02:03.877969 ==
2836 10:02:03.881113 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 10:02:03.887789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 10:02:03.887870 ==
2839 10:02:03.887933 [Gating] SW mode calibration
2840 10:02:03.897624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2841 10:02:03.900896 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2842 10:02:03.904858 0 15 0 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (0 0)
2843 10:02:03.911137 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 10:02:03.914272 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 10:02:03.918119 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 10:02:03.924644 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 10:02:03.927897 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 10:02:03.931068 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 10:02:03.938063 0 15 28 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
2850 10:02:03.941445 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 10:02:03.944494 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 10:02:03.951446 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 10:02:03.954360 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 10:02:03.957576 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 10:02:03.964392 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 10:02:03.967982 1 0 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
2857 10:02:03.971023 1 0 28 | B1->B0 | 3f3f 4241 | 0 1 | (0 0) (0 0)
2858 10:02:03.977830 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2859 10:02:03.981691 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 10:02:03.984515 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 10:02:03.990977 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 10:02:03.994788 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 10:02:03.997979 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 10:02:04.001068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2865 10:02:04.008110 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2866 10:02:04.011286 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 10:02:04.014434 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 10:02:04.021508 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 10:02:04.024661 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 10:02:04.028111 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 10:02:04.034591 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 10:02:04.037817 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 10:02:04.040919 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 10:02:04.047773 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 10:02:04.051396 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 10:02:04.054551 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 10:02:04.061341 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 10:02:04.064475 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 10:02:04.068198 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 10:02:04.074459 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 10:02:04.078068 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2882 10:02:04.081111 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2883 10:02:04.087914 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 10:02:04.087995 Total UI for P1: 0, mck2ui 16
2885 10:02:04.091472 best dqsien dly found for B0: ( 1, 3, 30)
2886 10:02:04.094729 Total UI for P1: 0, mck2ui 16
2887 10:02:04.097898 best dqsien dly found for B1: ( 1, 3, 30)
2888 10:02:04.101713 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2889 10:02:04.104852 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2890 10:02:04.108502
2891 10:02:04.111616 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2892 10:02:04.115223 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2893 10:02:04.118525 [Gating] SW calibration Done
2894 10:02:04.118605 ==
2895 10:02:04.121783 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 10:02:04.124993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 10:02:04.125073 ==
2898 10:02:04.125168 RX Vref Scan: 0
2899 10:02:04.125227
2900 10:02:04.128133 RX Vref 0 -> 0, step: 1
2901 10:02:04.128213
2902 10:02:04.131983 RX Delay -40 -> 252, step: 8
2903 10:02:04.135139 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2904 10:02:04.138343 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2905 10:02:04.141561 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2906 10:02:04.148682 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2907 10:02:04.151941 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2908 10:02:04.154970 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2909 10:02:04.158514 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2910 10:02:04.162060 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2911 10:02:04.168575 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2912 10:02:04.171746 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2913 10:02:04.175285 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2914 10:02:04.178330 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2915 10:02:04.182024 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2916 10:02:04.188778 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2917 10:02:04.192009 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2918 10:02:04.194928 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2919 10:02:04.195026 ==
2920 10:02:04.198486 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 10:02:04.201904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 10:02:04.202009 ==
2923 10:02:04.204955 DQS Delay:
2924 10:02:04.205035 DQS0 = 0, DQS1 = 0
2925 10:02:04.208172 DQM Delay:
2926 10:02:04.208252 DQM0 = 122, DQM1 = 112
2927 10:02:04.208315 DQ Delay:
2928 10:02:04.211918 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2929 10:02:04.218857 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2930 10:02:04.221817 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2931 10:02:04.224890 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2932 10:02:04.224977
2933 10:02:04.225039
2934 10:02:04.225097 ==
2935 10:02:04.228790 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 10:02:04.232103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 10:02:04.232199 ==
2938 10:02:04.232285
2939 10:02:04.232375
2940 10:02:04.235268 TX Vref Scan disable
2941 10:02:04.238555 == TX Byte 0 ==
2942 10:02:04.241778 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2943 10:02:04.245062 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2944 10:02:04.249056 == TX Byte 1 ==
2945 10:02:04.252114 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2946 10:02:04.255401 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2947 10:02:04.255502 ==
2948 10:02:04.258804 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 10:02:04.261693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 10:02:04.261765 ==
2951 10:02:04.275379 TX Vref=22, minBit 5, minWin=25, winSum=412
2952 10:02:04.278657 TX Vref=24, minBit 1, minWin=25, winSum=421
2953 10:02:04.282256 TX Vref=26, minBit 13, minWin=25, winSum=422
2954 10:02:04.285271 TX Vref=28, minBit 3, minWin=25, winSum=423
2955 10:02:04.288782 TX Vref=30, minBit 1, minWin=26, winSum=427
2956 10:02:04.295626 TX Vref=32, minBit 0, minWin=26, winSum=421
2957 10:02:04.298890 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
2958 10:02:04.298970
2959 10:02:04.301877 Final TX Range 1 Vref 30
2960 10:02:04.301957
2961 10:02:04.302027 ==
2962 10:02:04.305506 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 10:02:04.308474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 10:02:04.308555 ==
2965 10:02:04.308618
2966 10:02:04.312099
2967 10:02:04.312178 TX Vref Scan disable
2968 10:02:04.315713 == TX Byte 0 ==
2969 10:02:04.318895 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2970 10:02:04.322310 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2971 10:02:04.325283 == TX Byte 1 ==
2972 10:02:04.328858 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2973 10:02:04.332113 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2974 10:02:04.332187
2975 10:02:04.335263 [DATLAT]
2976 10:02:04.335334 Freq=1200, CH0 RK1
2977 10:02:04.335394
2978 10:02:04.339099 DATLAT Default: 0xd
2979 10:02:04.339196 0, 0xFFFF, sum = 0
2980 10:02:04.342374 1, 0xFFFF, sum = 0
2981 10:02:04.342480 2, 0xFFFF, sum = 0
2982 10:02:04.345573 3, 0xFFFF, sum = 0
2983 10:02:04.345670 4, 0xFFFF, sum = 0
2984 10:02:04.348905 5, 0xFFFF, sum = 0
2985 10:02:04.349008 6, 0xFFFF, sum = 0
2986 10:02:04.352010 7, 0xFFFF, sum = 0
2987 10:02:04.352096 8, 0xFFFF, sum = 0
2988 10:02:04.355761 9, 0xFFFF, sum = 0
2989 10:02:04.359180 10, 0xFFFF, sum = 0
2990 10:02:04.359254 11, 0xFFFF, sum = 0
2991 10:02:04.362501 12, 0x0, sum = 1
2992 10:02:04.362606 13, 0x0, sum = 2
2993 10:02:04.362698 14, 0x0, sum = 3
2994 10:02:04.365829 15, 0x0, sum = 4
2995 10:02:04.365899 best_step = 13
2996 10:02:04.365959
2997 10:02:04.366040 ==
2998 10:02:04.369076 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 10:02:04.375849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 10:02:04.375955 ==
3001 10:02:04.376044 RX Vref Scan: 0
3002 10:02:04.376130
3003 10:02:04.378938 RX Vref 0 -> 0, step: 1
3004 10:02:04.379034
3005 10:02:04.382613 RX Delay -13 -> 252, step: 4
3006 10:02:04.385470 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3007 10:02:04.388799 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3008 10:02:04.395545 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3009 10:02:04.398975 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3010 10:02:04.402693 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3011 10:02:04.405805 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3012 10:02:04.409043 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3013 10:02:04.412545 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3014 10:02:04.419038 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3015 10:02:04.422631 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3016 10:02:04.426338 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3017 10:02:04.429925 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3018 10:02:04.432396 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3019 10:02:04.439345 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3020 10:02:04.442566 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3021 10:02:04.445769 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3022 10:02:04.445851 ==
3023 10:02:04.448973 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 10:02:04.452856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 10:02:04.452967 ==
3026 10:02:04.456119 DQS Delay:
3027 10:02:04.456245 DQS0 = 0, DQS1 = 0
3028 10:02:04.459298 DQM Delay:
3029 10:02:04.459414 DQM0 = 121, DQM1 = 110
3030 10:02:04.459510 DQ Delay:
3031 10:02:04.462433 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3032 10:02:04.468955 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3033 10:02:04.472815 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =100
3034 10:02:04.475966 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3035 10:02:04.476074
3036 10:02:04.476180
3037 10:02:04.482360 [DQSOSCAuto] RK1, (LSB)MR18= 0xef0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3038 10:02:04.486405 CH0 RK1: MR19=403, MR18=EF0
3039 10:02:04.492631 CH0_RK1: MR19=0x403, MR18=0xEF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3040 10:02:04.496342 [RxdqsGatingPostProcess] freq 1200
3041 10:02:04.499605 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3042 10:02:04.502792 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 10:02:04.505840 best DQS1 dly(2T, 0.5T) = (0, 12)
3044 10:02:04.509530 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 10:02:04.512732 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3046 10:02:04.516558 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 10:02:04.519553 best DQS1 dly(2T, 0.5T) = (0, 11)
3048 10:02:04.522678 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 10:02:04.526249 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3050 10:02:04.529437 Pre-setting of DQS Precalculation
3051 10:02:04.532855 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3052 10:02:04.532955 ==
3053 10:02:04.536073 Dram Type= 6, Freq= 0, CH_1, rank 0
3054 10:02:04.542679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 10:02:04.542785 ==
3056 10:02:04.546487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3057 10:02:04.553127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3058 10:02:04.561584 [CA 0] Center 37 (7~68) winsize 62
3059 10:02:04.564876 [CA 1] Center 37 (7~68) winsize 62
3060 10:02:04.568125 [CA 2] Center 35 (5~65) winsize 61
3061 10:02:04.571375 [CA 3] Center 34 (4~64) winsize 61
3062 10:02:04.574720 [CA 4] Center 34 (4~64) winsize 61
3063 10:02:04.578323 [CA 5] Center 33 (3~63) winsize 61
3064 10:02:04.578405
3065 10:02:04.581508 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3066 10:02:04.581590
3067 10:02:04.584767 [CATrainingPosCal] consider 1 rank data
3068 10:02:04.587920 u2DelayCellTimex100 = 270/100 ps
3069 10:02:04.591613 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3070 10:02:04.594868 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3071 10:02:04.598025 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3072 10:02:04.604820 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3073 10:02:04.608027 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3074 10:02:04.611293 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3075 10:02:04.611365
3076 10:02:04.614462 CA PerBit enable=1, Macro0, CA PI delay=33
3077 10:02:04.614572
3078 10:02:04.618176 [CBTSetCACLKResult] CA Dly = 33
3079 10:02:04.618247 CS Dly: 8 (0~39)
3080 10:02:04.618307 ==
3081 10:02:04.621181 Dram Type= 6, Freq= 0, CH_1, rank 1
3082 10:02:04.627841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 10:02:04.627923 ==
3084 10:02:04.631354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3085 10:02:04.637868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3086 10:02:04.646906 [CA 0] Center 38 (8~68) winsize 61
3087 10:02:04.650509 [CA 1] Center 37 (7~68) winsize 62
3088 10:02:04.653751 [CA 2] Center 35 (5~65) winsize 61
3089 10:02:04.657082 [CA 3] Center 34 (4~65) winsize 62
3090 10:02:04.660701 [CA 4] Center 34 (4~65) winsize 62
3091 10:02:04.663916 [CA 5] Center 34 (4~64) winsize 61
3092 10:02:04.663996
3093 10:02:04.667104 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3094 10:02:04.667184
3095 10:02:04.670460 [CATrainingPosCal] consider 2 rank data
3096 10:02:04.673717 u2DelayCellTimex100 = 270/100 ps
3097 10:02:04.677622 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3098 10:02:04.680695 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3099 10:02:04.683852 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3100 10:02:04.690728 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3101 10:02:04.694012 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3102 10:02:04.697291 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3103 10:02:04.697370
3104 10:02:04.700400 CA PerBit enable=1, Macro0, CA PI delay=33
3105 10:02:04.700479
3106 10:02:04.704244 [CBTSetCACLKResult] CA Dly = 33
3107 10:02:04.704324 CS Dly: 8 (0~40)
3108 10:02:04.704387
3109 10:02:04.707335 ----->DramcWriteLeveling(PI) begin...
3110 10:02:04.707442 ==
3111 10:02:04.710789 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 10:02:04.717198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 10:02:04.717279 ==
3114 10:02:04.720401 Write leveling (Byte 0): 27 => 27
3115 10:02:04.724120 Write leveling (Byte 1): 27 => 27
3116 10:02:04.724200 DramcWriteLeveling(PI) end<-----
3117 10:02:04.724273
3118 10:02:04.727227 ==
3119 10:02:04.730898 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 10:02:04.734208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 10:02:04.734281 ==
3122 10:02:04.737339 [Gating] SW mode calibration
3123 10:02:04.744236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3124 10:02:04.747112 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3125 10:02:04.754400 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 10:02:04.757693 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 10:02:04.760623 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 10:02:04.767437 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 10:02:04.770767 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 10:02:04.774020 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 10:02:04.780959 0 15 24 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 0)
3132 10:02:04.784323 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3133 10:02:04.787534 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 10:02:04.791237 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 10:02:04.797606 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 10:02:04.800813 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 10:02:04.804000 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 10:02:04.811010 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 10:02:04.814256 1 0 24 | B1->B0 | 3535 4545 | 0 0 | (1 1) (0 0)
3140 10:02:04.817469 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 10:02:04.823993 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 10:02:04.827909 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 10:02:04.831125 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 10:02:04.837294 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 10:02:04.841125 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 10:02:04.844235 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 10:02:04.850662 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 10:02:04.854487 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3149 10:02:04.857450 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 10:02:04.864223 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 10:02:04.867576 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 10:02:04.870733 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 10:02:04.877616 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 10:02:04.880575 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 10:02:04.884031 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 10:02:04.887507 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 10:02:04.894281 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 10:02:04.897959 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 10:02:04.901108 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 10:02:04.907717 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 10:02:04.910993 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 10:02:04.914145 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 10:02:04.921279 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3164 10:02:04.924402 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3165 10:02:04.927530 Total UI for P1: 0, mck2ui 16
3166 10:02:04.930974 best dqsien dly found for B0: ( 1, 3, 24)
3167 10:02:04.934280 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 10:02:04.937925 Total UI for P1: 0, mck2ui 16
3169 10:02:04.941104 best dqsien dly found for B1: ( 1, 3, 26)
3170 10:02:04.944396 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3171 10:02:04.947609 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3172 10:02:04.947703
3173 10:02:04.950779 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3174 10:02:04.957594 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3175 10:02:04.957674 [Gating] SW calibration Done
3176 10:02:04.957737 ==
3177 10:02:04.960857 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 10:02:04.967826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 10:02:04.967906 ==
3180 10:02:04.967969 RX Vref Scan: 0
3181 10:02:04.968028
3182 10:02:04.970785 RX Vref 0 -> 0, step: 1
3183 10:02:04.970865
3184 10:02:04.974592 RX Delay -40 -> 252, step: 8
3185 10:02:04.977882 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3186 10:02:04.981113 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3187 10:02:04.984289 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3188 10:02:04.991219 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3189 10:02:04.994297 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3190 10:02:04.997886 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3191 10:02:05.001148 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3192 10:02:05.004395 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3193 10:02:05.007869 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3194 10:02:05.014482 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3195 10:02:05.017730 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3196 10:02:05.020962 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3197 10:02:05.024783 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3198 10:02:05.031358 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3199 10:02:05.034451 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3200 10:02:05.038119 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3201 10:02:05.038199 ==
3202 10:02:05.041027 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 10:02:05.044837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 10:02:05.044916 ==
3205 10:02:05.047947 DQS Delay:
3206 10:02:05.048026 DQS0 = 0, DQS1 = 0
3207 10:02:05.048088 DQM Delay:
3208 10:02:05.051039 DQM0 = 120, DQM1 = 116
3209 10:02:05.051145 DQ Delay:
3210 10:02:05.054349 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3211 10:02:05.058276 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3212 10:02:05.064442 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3213 10:02:05.067740 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3214 10:02:05.067820
3215 10:02:05.067882
3216 10:02:05.067940 ==
3217 10:02:05.071497 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 10:02:05.074781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 10:02:05.074878 ==
3220 10:02:05.074942
3221 10:02:05.075001
3222 10:02:05.077877 TX Vref Scan disable
3223 10:02:05.077956 == TX Byte 0 ==
3224 10:02:05.084807 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3225 10:02:05.087981 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3226 10:02:05.088061 == TX Byte 1 ==
3227 10:02:05.094908 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3228 10:02:05.098194 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3229 10:02:05.098297 ==
3230 10:02:05.101486 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 10:02:05.104514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 10:02:05.104593 ==
3233 10:02:05.116967 TX Vref=22, minBit 9, minWin=24, winSum=412
3234 10:02:05.120672 TX Vref=24, minBit 9, minWin=25, winSum=421
3235 10:02:05.123619 TX Vref=26, minBit 1, minWin=25, winSum=425
3236 10:02:05.126906 TX Vref=28, minBit 9, minWin=25, winSum=427
3237 10:02:05.130198 TX Vref=30, minBit 1, minWin=26, winSum=428
3238 10:02:05.134063 TX Vref=32, minBit 9, minWin=26, winSum=427
3239 10:02:05.140607 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3240 10:02:05.140687
3241 10:02:05.143792 Final TX Range 1 Vref 30
3242 10:02:05.143872
3243 10:02:05.143934 ==
3244 10:02:05.147231 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 10:02:05.150989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 10:02:05.151069 ==
3247 10:02:05.151131
3248 10:02:05.151189
3249 10:02:05.154003 TX Vref Scan disable
3250 10:02:05.157204 == TX Byte 0 ==
3251 10:02:05.161071 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3252 10:02:05.164239 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3253 10:02:05.167502 == TX Byte 1 ==
3254 10:02:05.170748 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3255 10:02:05.173920 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3256 10:02:05.174002
3257 10:02:05.177787 [DATLAT]
3258 10:02:05.177866 Freq=1200, CH1 RK0
3259 10:02:05.177929
3260 10:02:05.180984 DATLAT Default: 0xd
3261 10:02:05.181063 0, 0xFFFF, sum = 0
3262 10:02:05.184276 1, 0xFFFF, sum = 0
3263 10:02:05.184357 2, 0xFFFF, sum = 0
3264 10:02:05.187459 3, 0xFFFF, sum = 0
3265 10:02:05.187540 4, 0xFFFF, sum = 0
3266 10:02:05.190759 5, 0xFFFF, sum = 0
3267 10:02:05.190840 6, 0xFFFF, sum = 0
3268 10:02:05.194479 7, 0xFFFF, sum = 0
3269 10:02:05.194560 8, 0xFFFF, sum = 0
3270 10:02:05.197998 9, 0xFFFF, sum = 0
3271 10:02:05.198079 10, 0xFFFF, sum = 0
3272 10:02:05.200816 11, 0xFFFF, sum = 0
3273 10:02:05.200896 12, 0x0, sum = 1
3274 10:02:05.204312 13, 0x0, sum = 2
3275 10:02:05.204393 14, 0x0, sum = 3
3276 10:02:05.207681 15, 0x0, sum = 4
3277 10:02:05.207761 best_step = 13
3278 10:02:05.207824
3279 10:02:05.207882 ==
3280 10:02:05.211151 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 10:02:05.217494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 10:02:05.217574 ==
3283 10:02:05.217638 RX Vref Scan: 1
3284 10:02:05.217697
3285 10:02:05.221407 Set Vref Range= 32 -> 127
3286 10:02:05.221487
3287 10:02:05.224475 RX Vref 32 -> 127, step: 1
3288 10:02:05.224555
3289 10:02:05.224619 RX Delay -5 -> 252, step: 4
3290 10:02:05.224678
3291 10:02:05.227884 Set Vref, RX VrefLevel [Byte0]: 32
3292 10:02:05.230800 [Byte1]: 32
3293 10:02:05.235262
3294 10:02:05.235341 Set Vref, RX VrefLevel [Byte0]: 33
3295 10:02:05.238675 [Byte1]: 33
3296 10:02:05.243296
3297 10:02:05.243376 Set Vref, RX VrefLevel [Byte0]: 34
3298 10:02:05.246601 [Byte1]: 34
3299 10:02:05.251036
3300 10:02:05.251115 Set Vref, RX VrefLevel [Byte0]: 35
3301 10:02:05.253943 [Byte1]: 35
3302 10:02:05.258726
3303 10:02:05.258805 Set Vref, RX VrefLevel [Byte0]: 36
3304 10:02:05.262233 [Byte1]: 36
3305 10:02:05.266658
3306 10:02:05.266738 Set Vref, RX VrefLevel [Byte0]: 37
3307 10:02:05.269804 [Byte1]: 37
3308 10:02:05.274134
3309 10:02:05.274213 Set Vref, RX VrefLevel [Byte0]: 38
3310 10:02:05.278003 [Byte1]: 38
3311 10:02:05.282523
3312 10:02:05.282602 Set Vref, RX VrefLevel [Byte0]: 39
3313 10:02:05.285727 [Byte1]: 39
3314 10:02:05.290091
3315 10:02:05.290169 Set Vref, RX VrefLevel [Byte0]: 40
3316 10:02:05.293311 [Byte1]: 40
3317 10:02:05.297840
3318 10:02:05.297918 Set Vref, RX VrefLevel [Byte0]: 41
3319 10:02:05.301188 [Byte1]: 41
3320 10:02:05.305952
3321 10:02:05.306031 Set Vref, RX VrefLevel [Byte0]: 42
3322 10:02:05.309152 [Byte1]: 42
3323 10:02:05.313429
3324 10:02:05.313507 Set Vref, RX VrefLevel [Byte0]: 43
3325 10:02:05.317191 [Byte1]: 43
3326 10:02:05.321453
3327 10:02:05.321559 Set Vref, RX VrefLevel [Byte0]: 44
3328 10:02:05.324964 [Byte1]: 44
3329 10:02:05.329406
3330 10:02:05.329491 Set Vref, RX VrefLevel [Byte0]: 45
3331 10:02:05.332673 [Byte1]: 45
3332 10:02:05.337493
3333 10:02:05.337571 Set Vref, RX VrefLevel [Byte0]: 46
3334 10:02:05.340627 [Byte1]: 46
3335 10:02:05.345311
3336 10:02:05.345389 Set Vref, RX VrefLevel [Byte0]: 47
3337 10:02:05.348530 [Byte1]: 47
3338 10:02:05.352884
3339 10:02:05.352962 Set Vref, RX VrefLevel [Byte0]: 48
3340 10:02:05.356074 [Byte1]: 48
3341 10:02:05.361112
3342 10:02:05.361190 Set Vref, RX VrefLevel [Byte0]: 49
3343 10:02:05.364202 [Byte1]: 49
3344 10:02:05.368562
3345 10:02:05.368640 Set Vref, RX VrefLevel [Byte0]: 50
3346 10:02:05.372062 [Byte1]: 50
3347 10:02:05.376480
3348 10:02:05.376558 Set Vref, RX VrefLevel [Byte0]: 51
3349 10:02:05.379630 [Byte1]: 51
3350 10:02:05.384181
3351 10:02:05.384259 Set Vref, RX VrefLevel [Byte0]: 52
3352 10:02:05.387514 [Byte1]: 52
3353 10:02:05.392619
3354 10:02:05.392697 Set Vref, RX VrefLevel [Byte0]: 53
3355 10:02:05.395757 [Byte1]: 53
3356 10:02:05.400407
3357 10:02:05.400485 Set Vref, RX VrefLevel [Byte0]: 54
3358 10:02:05.403725 [Byte1]: 54
3359 10:02:05.408118
3360 10:02:05.408195 Set Vref, RX VrefLevel [Byte0]: 55
3361 10:02:05.411264 [Byte1]: 55
3362 10:02:05.415720
3363 10:02:05.415823 Set Vref, RX VrefLevel [Byte0]: 56
3364 10:02:05.418842 [Byte1]: 56
3365 10:02:05.423399
3366 10:02:05.423478 Set Vref, RX VrefLevel [Byte0]: 57
3367 10:02:05.427240 [Byte1]: 57
3368 10:02:05.431495
3369 10:02:05.431573 Set Vref, RX VrefLevel [Byte0]: 58
3370 10:02:05.434592 [Byte1]: 58
3371 10:02:05.439196
3372 10:02:05.439275 Set Vref, RX VrefLevel [Byte0]: 59
3373 10:02:05.442935 [Byte1]: 59
3374 10:02:05.447469
3375 10:02:05.447648 Set Vref, RX VrefLevel [Byte0]: 60
3376 10:02:05.450803 [Byte1]: 60
3377 10:02:05.455173
3378 10:02:05.455251 Set Vref, RX VrefLevel [Byte0]: 61
3379 10:02:05.458278 [Byte1]: 61
3380 10:02:05.462634
3381 10:02:05.462712 Set Vref, RX VrefLevel [Byte0]: 62
3382 10:02:05.466469 [Byte1]: 62
3383 10:02:05.470848
3384 10:02:05.470927 Set Vref, RX VrefLevel [Byte0]: 63
3385 10:02:05.474000 [Byte1]: 63
3386 10:02:05.478841
3387 10:02:05.478919 Set Vref, RX VrefLevel [Byte0]: 64
3388 10:02:05.481860 [Byte1]: 64
3389 10:02:05.486160
3390 10:02:05.486239 Set Vref, RX VrefLevel [Byte0]: 65
3391 10:02:05.490171 [Byte1]: 65
3392 10:02:05.494174
3393 10:02:05.494254 Set Vref, RX VrefLevel [Byte0]: 66
3394 10:02:05.497501 [Byte1]: 66
3395 10:02:05.502010
3396 10:02:05.502090 Set Vref, RX VrefLevel [Byte0]: 67
3397 10:02:05.505141 [Byte1]: 67
3398 10:02:05.510217
3399 10:02:05.510296 Set Vref, RX VrefLevel [Byte0]: 68
3400 10:02:05.513189 [Byte1]: 68
3401 10:02:05.517620
3402 10:02:05.517699 Set Vref, RX VrefLevel [Byte0]: 69
3403 10:02:05.521277 [Byte1]: 69
3404 10:02:05.525769
3405 10:02:05.525848 Final RX Vref Byte 0 = 53 to rank0
3406 10:02:05.529009 Final RX Vref Byte 1 = 51 to rank0
3407 10:02:05.532297 Final RX Vref Byte 0 = 53 to rank1
3408 10:02:05.535464 Final RX Vref Byte 1 = 51 to rank1==
3409 10:02:05.538777 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 10:02:05.545592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 10:02:05.545673 ==
3412 10:02:05.545737 DQS Delay:
3413 10:02:05.545796 DQS0 = 0, DQS1 = 0
3414 10:02:05.549228 DQM Delay:
3415 10:02:05.549307 DQM0 = 119, DQM1 = 117
3416 10:02:05.552050 DQ Delay:
3417 10:02:05.555485 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3418 10:02:05.558770 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3419 10:02:05.562214 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3420 10:02:05.565285 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3421 10:02:05.565365
3422 10:02:05.565429
3423 10:02:05.572461 [DQSOSCAuto] RK0, (LSB)MR18= 0x315, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3424 10:02:05.575372 CH1 RK0: MR19=404, MR18=315
3425 10:02:05.582130 CH1_RK0: MR19=0x404, MR18=0x315, DQSOSC=401, MR23=63, INC=40, DEC=27
3426 10:02:05.582212
3427 10:02:05.585431 ----->DramcWriteLeveling(PI) begin...
3428 10:02:05.585513 ==
3429 10:02:05.588712 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 10:02:05.592189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 10:02:05.595918 ==
3432 10:02:05.595998 Write leveling (Byte 0): 26 => 26
3433 10:02:05.599101 Write leveling (Byte 1): 27 => 27
3434 10:02:05.602289 DramcWriteLeveling(PI) end<-----
3435 10:02:05.602369
3436 10:02:05.602432 ==
3437 10:02:05.605385 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 10:02:05.609224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 10:02:05.612433 ==
3440 10:02:05.612512 [Gating] SW mode calibration
3441 10:02:05.622406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3442 10:02:05.625587 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3443 10:02:05.628838 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 10:02:05.635948 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 10:02:05.639282 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 10:02:05.642595 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 10:02:05.649173 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 10:02:05.652518 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3449 10:02:05.656085 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (1 0) (0 0)
3450 10:02:05.662687 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 10:02:05.665636 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 10:02:05.669089 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 10:02:05.675728 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 10:02:05.678983 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 10:02:05.682798 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 10:02:05.685945 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3457 10:02:05.692261 1 0 24 | B1->B0 | 4343 2a2a | 0 0 | (0 0) (0 0)
3458 10:02:05.695761 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 10:02:05.699402 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 10:02:05.706091 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 10:02:05.709284 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 10:02:05.712478 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 10:02:05.718936 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 10:02:05.722688 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 10:02:05.725811 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3466 10:02:05.732688 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3467 10:02:05.735970 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 10:02:05.739276 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 10:02:05.745761 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 10:02:05.748899 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 10:02:05.752877 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 10:02:05.759449 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 10:02:05.762718 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 10:02:05.766043 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 10:02:05.772523 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 10:02:05.776043 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 10:02:05.778990 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 10:02:05.782695 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 10:02:05.789501 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 10:02:05.792708 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3481 10:02:05.795619 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 10:02:05.802505 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3483 10:02:05.805877 Total UI for P1: 0, mck2ui 16
3484 10:02:05.809066 best dqsien dly found for B1: ( 1, 3, 22)
3485 10:02:05.812766 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 10:02:05.815804 Total UI for P1: 0, mck2ui 16
3487 10:02:05.818847 best dqsien dly found for B0: ( 1, 3, 26)
3488 10:02:05.822793 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3489 10:02:05.826012 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3490 10:02:05.826108
3491 10:02:05.829036 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3492 10:02:05.832772 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3493 10:02:05.835905 [Gating] SW calibration Done
3494 10:02:05.836005 ==
3495 10:02:05.839006 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 10:02:05.842277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 10:02:05.845594 ==
3498 10:02:05.845690 RX Vref Scan: 0
3499 10:02:05.845777
3500 10:02:05.848820 RX Vref 0 -> 0, step: 1
3501 10:02:05.848925
3502 10:02:05.852709 RX Delay -40 -> 252, step: 8
3503 10:02:05.855995 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3504 10:02:05.859322 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3505 10:02:05.862697 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3506 10:02:05.865863 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3507 10:02:05.872413 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3508 10:02:05.875644 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3509 10:02:05.878738 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3510 10:02:05.881975 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3511 10:02:05.885757 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3512 10:02:05.892246 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3513 10:02:05.895441 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3514 10:02:05.899010 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3515 10:02:05.902495 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3516 10:02:05.905676 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3517 10:02:05.912666 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3518 10:02:05.915753 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3519 10:02:05.915822 ==
3520 10:02:05.919431 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 10:02:05.922645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 10:02:05.922720 ==
3523 10:02:05.922782 DQS Delay:
3524 10:02:05.925979 DQS0 = 0, DQS1 = 0
3525 10:02:05.926095 DQM Delay:
3526 10:02:05.929126 DQM0 = 120, DQM1 = 118
3527 10:02:05.929218 DQ Delay:
3528 10:02:05.932677 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =115
3529 10:02:05.935679 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3530 10:02:05.939198 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3531 10:02:05.945603 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3532 10:02:05.945744
3533 10:02:05.945832
3534 10:02:05.945920 ==
3535 10:02:05.948933 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 10:02:05.952696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 10:02:05.952768 ==
3538 10:02:05.952828
3539 10:02:05.952885
3540 10:02:05.955990 TX Vref Scan disable
3541 10:02:05.956084 == TX Byte 0 ==
3542 10:02:05.962335 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3543 10:02:05.965553 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3544 10:02:05.965646 == TX Byte 1 ==
3545 10:02:05.971957 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3546 10:02:05.975876 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3547 10:02:05.975972 ==
3548 10:02:05.978972 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 10:02:05.982178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 10:02:05.982276 ==
3551 10:02:05.994487 TX Vref=22, minBit 10, minWin=24, winSum=418
3552 10:02:05.997672 TX Vref=24, minBit 1, minWin=26, winSum=423
3553 10:02:06.001054 TX Vref=26, minBit 10, minWin=25, winSum=427
3554 10:02:06.004413 TX Vref=28, minBit 9, minWin=26, winSum=431
3555 10:02:06.007515 TX Vref=30, minBit 9, minWin=26, winSum=434
3556 10:02:06.014452 TX Vref=32, minBit 10, minWin=25, winSum=431
3557 10:02:06.017537 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3558 10:02:06.017637
3559 10:02:06.020989 Final TX Range 1 Vref 30
3560 10:02:06.021084
3561 10:02:06.021158 ==
3562 10:02:06.024148 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 10:02:06.027623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 10:02:06.031047 ==
3565 10:02:06.031144
3566 10:02:06.031239
3567 10:02:06.031326 TX Vref Scan disable
3568 10:02:06.034374 == TX Byte 0 ==
3569 10:02:06.037774 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3570 10:02:06.044532 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3571 10:02:06.044637 == TX Byte 1 ==
3572 10:02:06.048291 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3573 10:02:06.051748 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3574 10:02:06.054635
3575 10:02:06.054733 [DATLAT]
3576 10:02:06.054822 Freq=1200, CH1 RK1
3577 10:02:06.054884
3578 10:02:06.058133 DATLAT Default: 0xd
3579 10:02:06.058232 0, 0xFFFF, sum = 0
3580 10:02:06.061591 1, 0xFFFF, sum = 0
3581 10:02:06.061692 2, 0xFFFF, sum = 0
3582 10:02:06.064736 3, 0xFFFF, sum = 0
3583 10:02:06.064836 4, 0xFFFF, sum = 0
3584 10:02:06.067911 5, 0xFFFF, sum = 0
3585 10:02:06.071079 6, 0xFFFF, sum = 0
3586 10:02:06.071178 7, 0xFFFF, sum = 0
3587 10:02:06.074404 8, 0xFFFF, sum = 0
3588 10:02:06.074504 9, 0xFFFF, sum = 0
3589 10:02:06.077707 10, 0xFFFF, sum = 0
3590 10:02:06.077805 11, 0xFFFF, sum = 0
3591 10:02:06.080953 12, 0x0, sum = 1
3592 10:02:06.081066 13, 0x0, sum = 2
3593 10:02:06.084108 14, 0x0, sum = 3
3594 10:02:06.084214 15, 0x0, sum = 4
3595 10:02:06.088009 best_step = 13
3596 10:02:06.088108
3597 10:02:06.088196 ==
3598 10:02:06.091199 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 10:02:06.094327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 10:02:06.094425 ==
3601 10:02:06.094513 RX Vref Scan: 0
3602 10:02:06.094601
3603 10:02:06.097660 RX Vref 0 -> 0, step: 1
3604 10:02:06.097726
3605 10:02:06.100779 RX Delay -5 -> 252, step: 4
3606 10:02:06.104718 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3607 10:02:06.110706 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3608 10:02:06.114389 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3609 10:02:06.117833 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3610 10:02:06.121030 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3611 10:02:06.124205 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3612 10:02:06.130531 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3613 10:02:06.134422 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3614 10:02:06.137675 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3615 10:02:06.140602 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3616 10:02:06.144058 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3617 10:02:06.150819 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3618 10:02:06.154349 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3619 10:02:06.157777 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3620 10:02:06.160686 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3621 10:02:06.164241 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3622 10:02:06.167864 ==
3623 10:02:06.170695 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 10:02:06.174237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 10:02:06.174383 ==
3626 10:02:06.174522 DQS Delay:
3627 10:02:06.177315 DQS0 = 0, DQS1 = 0
3628 10:02:06.177385 DQM Delay:
3629 10:02:06.181051 DQM0 = 120, DQM1 = 118
3630 10:02:06.181139 DQ Delay:
3631 10:02:06.184315 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3632 10:02:06.187579 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3633 10:02:06.190849 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3634 10:02:06.194028 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3635 10:02:06.194123
3636 10:02:06.194212
3637 10:02:06.204053 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3638 10:02:06.204157 CH1 RK1: MR19=403, MR18=13F1
3639 10:02:06.210771 CH1_RK1: MR19=0x403, MR18=0x13F1, DQSOSC=402, MR23=63, INC=40, DEC=27
3640 10:02:06.214671 [RxdqsGatingPostProcess] freq 1200
3641 10:02:06.221089 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3642 10:02:06.224208 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 10:02:06.227491 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 10:02:06.230714 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 10:02:06.234183 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 10:02:06.237485 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 10:02:06.240832 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 10:02:06.240935 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 10:02:06.244056 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 10:02:06.247272 Pre-setting of DQS Precalculation
3651 10:02:06.254016 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3652 10:02:06.260917 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3653 10:02:06.267618 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3654 10:02:06.267695
3655 10:02:06.267760
3656 10:02:06.271191 [Calibration Summary] 2400 Mbps
3657 10:02:06.274292 CH 0, Rank 0
3658 10:02:06.274392 SW Impedance : PASS
3659 10:02:06.277827 DUTY Scan : NO K
3660 10:02:06.280649 ZQ Calibration : PASS
3661 10:02:06.280718 Jitter Meter : NO K
3662 10:02:06.284166 CBT Training : PASS
3663 10:02:06.284237 Write leveling : PASS
3664 10:02:06.287360 RX DQS gating : PASS
3665 10:02:06.290482 RX DQ/DQS(RDDQC) : PASS
3666 10:02:06.290581 TX DQ/DQS : PASS
3667 10:02:06.294398 RX DATLAT : PASS
3668 10:02:06.297551 RX DQ/DQS(Engine): PASS
3669 10:02:06.297653 TX OE : NO K
3670 10:02:06.300749 All Pass.
3671 10:02:06.300825
3672 10:02:06.300885 CH 0, Rank 1
3673 10:02:06.304037 SW Impedance : PASS
3674 10:02:06.304134 DUTY Scan : NO K
3675 10:02:06.307263 ZQ Calibration : PASS
3676 10:02:06.310548 Jitter Meter : NO K
3677 10:02:06.310624 CBT Training : PASS
3678 10:02:06.313831 Write leveling : PASS
3679 10:02:06.317128 RX DQS gating : PASS
3680 10:02:06.317198 RX DQ/DQS(RDDQC) : PASS
3681 10:02:06.320264 TX DQ/DQS : PASS
3682 10:02:06.324116 RX DATLAT : PASS
3683 10:02:06.324189 RX DQ/DQS(Engine): PASS
3684 10:02:06.327354 TX OE : NO K
3685 10:02:06.327424 All Pass.
3686 10:02:06.327490
3687 10:02:06.330824 CH 1, Rank 0
3688 10:02:06.330897 SW Impedance : PASS
3689 10:02:06.333982 DUTY Scan : NO K
3690 10:02:06.334078 ZQ Calibration : PASS
3691 10:02:06.337358 Jitter Meter : NO K
3692 10:02:06.340505 CBT Training : PASS
3693 10:02:06.340605 Write leveling : PASS
3694 10:02:06.343691 RX DQS gating : PASS
3695 10:02:06.346896 RX DQ/DQS(RDDQC) : PASS
3696 10:02:06.346964 TX DQ/DQS : PASS
3697 10:02:06.350159 RX DATLAT : PASS
3698 10:02:06.353719 RX DQ/DQS(Engine): PASS
3699 10:02:06.353817 TX OE : NO K
3700 10:02:06.356945 All Pass.
3701 10:02:06.357041
3702 10:02:06.357129 CH 1, Rank 1
3703 10:02:06.360755 SW Impedance : PASS
3704 10:02:06.360855 DUTY Scan : NO K
3705 10:02:06.363860 ZQ Calibration : PASS
3706 10:02:06.366869 Jitter Meter : NO K
3707 10:02:06.366942 CBT Training : PASS
3708 10:02:06.370481 Write leveling : PASS
3709 10:02:06.373563 RX DQS gating : PASS
3710 10:02:06.373661 RX DQ/DQS(RDDQC) : PASS
3711 10:02:06.377227 TX DQ/DQS : PASS
3712 10:02:06.377325 RX DATLAT : PASS
3713 10:02:06.380241 RX DQ/DQS(Engine): PASS
3714 10:02:06.383989 TX OE : NO K
3715 10:02:06.384078 All Pass.
3716 10:02:06.384166
3717 10:02:06.386970 DramC Write-DBI off
3718 10:02:06.390408 PER_BANK_REFRESH: Hybrid Mode
3719 10:02:06.390527 TX_TRACKING: ON
3720 10:02:06.400191 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3721 10:02:06.403831 [FAST_K] Save calibration result to emmc
3722 10:02:06.406997 dramc_set_vcore_voltage set vcore to 650000
3723 10:02:06.407093 Read voltage for 600, 5
3724 10:02:06.410180 Vio18 = 0
3725 10:02:06.410271 Vcore = 650000
3726 10:02:06.410361 Vdram = 0
3727 10:02:06.413424 Vddq = 0
3728 10:02:06.413517 Vmddr = 0
3729 10:02:06.419907 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3730 10:02:06.423714 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3731 10:02:06.426819 MEM_TYPE=3, freq_sel=19
3732 10:02:06.430004 sv_algorithm_assistance_LP4_1600
3733 10:02:06.433257 ============ PULL DRAM RESETB DOWN ============
3734 10:02:06.436576 ========== PULL DRAM RESETB DOWN end =========
3735 10:02:06.443715 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3736 10:02:06.446758 ===================================
3737 10:02:06.446855 LPDDR4 DRAM CONFIGURATION
3738 10:02:06.450089 ===================================
3739 10:02:06.453371 EX_ROW_EN[0] = 0x0
3740 10:02:06.456533 EX_ROW_EN[1] = 0x0
3741 10:02:06.456638 LP4Y_EN = 0x0
3742 10:02:06.459801 WORK_FSP = 0x0
3743 10:02:06.459888 WL = 0x2
3744 10:02:06.463415 RL = 0x2
3745 10:02:06.463517 BL = 0x2
3746 10:02:06.466543 RPST = 0x0
3747 10:02:06.466639 RD_PRE = 0x0
3748 10:02:06.470321 WR_PRE = 0x1
3749 10:02:06.470421 WR_PST = 0x0
3750 10:02:06.473434 DBI_WR = 0x0
3751 10:02:06.473559 DBI_RD = 0x0
3752 10:02:06.476549 OTF = 0x1
3753 10:02:06.479968 ===================================
3754 10:02:06.483543 ===================================
3755 10:02:06.483680 ANA top config
3756 10:02:06.486740 ===================================
3757 10:02:06.489619 DLL_ASYNC_EN = 0
3758 10:02:06.492947 ALL_SLAVE_EN = 1
3759 10:02:06.493060 NEW_RANK_MODE = 1
3760 10:02:06.496507 DLL_IDLE_MODE = 1
3761 10:02:06.499588 LP45_APHY_COMB_EN = 1
3762 10:02:06.503135 TX_ODT_DIS = 1
3763 10:02:06.506721 NEW_8X_MODE = 1
3764 10:02:06.509938 ===================================
3765 10:02:06.513117 ===================================
3766 10:02:06.513205 data_rate = 1200
3767 10:02:06.516572 CKR = 1
3768 10:02:06.519744 DQ_P2S_RATIO = 8
3769 10:02:06.522966 ===================================
3770 10:02:06.526266 CA_P2S_RATIO = 8
3771 10:02:06.529536 DQ_CA_OPEN = 0
3772 10:02:06.533133 DQ_SEMI_OPEN = 0
3773 10:02:06.533207 CA_SEMI_OPEN = 0
3774 10:02:06.536442 CA_FULL_RATE = 0
3775 10:02:06.539521 DQ_CKDIV4_EN = 1
3776 10:02:06.542924 CA_CKDIV4_EN = 1
3777 10:02:06.546229 CA_PREDIV_EN = 0
3778 10:02:06.549552 PH8_DLY = 0
3779 10:02:06.549650 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3780 10:02:06.552526 DQ_AAMCK_DIV = 4
3781 10:02:06.555802 CA_AAMCK_DIV = 4
3782 10:02:06.559750 CA_ADMCK_DIV = 4
3783 10:02:06.563027 DQ_TRACK_CA_EN = 0
3784 10:02:06.566233 CA_PICK = 600
3785 10:02:06.569400 CA_MCKIO = 600
3786 10:02:06.569500 MCKIO_SEMI = 0
3787 10:02:06.572829 PLL_FREQ = 2288
3788 10:02:06.575960 DQ_UI_PI_RATIO = 32
3789 10:02:06.579628 CA_UI_PI_RATIO = 0
3790 10:02:06.582756 ===================================
3791 10:02:06.586085 ===================================
3792 10:02:06.589198 memory_type:LPDDR4
3793 10:02:06.589323 GP_NUM : 10
3794 10:02:06.593073 SRAM_EN : 1
3795 10:02:06.593179 MD32_EN : 0
3796 10:02:06.595960 ===================================
3797 10:02:06.599143 [ANA_INIT] >>>>>>>>>>>>>>
3798 10:02:06.602954 <<<<<< [CONFIGURE PHASE]: ANA_TX
3799 10:02:06.606009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3800 10:02:06.609196 ===================================
3801 10:02:06.612787 data_rate = 1200,PCW = 0X5800
3802 10:02:06.616455 ===================================
3803 10:02:06.619097 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3804 10:02:06.625977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 10:02:06.629066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 10:02:06.636090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3807 10:02:06.639431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3808 10:02:06.642598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3809 10:02:06.642698 [ANA_INIT] flow start
3810 10:02:06.645973 [ANA_INIT] PLL >>>>>>>>
3811 10:02:06.649207 [ANA_INIT] PLL <<<<<<<<
3812 10:02:06.649306 [ANA_INIT] MIDPI >>>>>>>>
3813 10:02:06.653029 [ANA_INIT] MIDPI <<<<<<<<
3814 10:02:06.655685 [ANA_INIT] DLL >>>>>>>>
3815 10:02:06.655767 [ANA_INIT] flow end
3816 10:02:06.662482 ============ LP4 DIFF to SE enter ============
3817 10:02:06.665774 ============ LP4 DIFF to SE exit ============
3818 10:02:06.669580 [ANA_INIT] <<<<<<<<<<<<<
3819 10:02:06.669678 [Flow] Enable top DCM control >>>>>
3820 10:02:06.672863 [Flow] Enable top DCM control <<<<<
3821 10:02:06.675962 Enable DLL master slave shuffle
3822 10:02:06.682335 ==============================================================
3823 10:02:06.685621 Gating Mode config
3824 10:02:06.689383 ==============================================================
3825 10:02:06.692604 Config description:
3826 10:02:06.702289 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3827 10:02:06.709023 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3828 10:02:06.712100 SELPH_MODE 0: By rank 1: By Phase
3829 10:02:06.718858 ==============================================================
3830 10:02:06.722468 GAT_TRACK_EN = 1
3831 10:02:06.725699 RX_GATING_MODE = 2
3832 10:02:06.728837 RX_GATING_TRACK_MODE = 2
3833 10:02:06.728931 SELPH_MODE = 1
3834 10:02:06.732031 PICG_EARLY_EN = 1
3835 10:02:06.735800 VALID_LAT_VALUE = 1
3836 10:02:06.742133 ==============================================================
3837 10:02:06.745462 Enter into Gating configuration >>>>
3838 10:02:06.748760 Exit from Gating configuration <<<<
3839 10:02:06.752069 Enter into DVFS_PRE_config >>>>>
3840 10:02:06.762186 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3841 10:02:06.765419 Exit from DVFS_PRE_config <<<<<
3842 10:02:06.768711 Enter into PICG configuration >>>>
3843 10:02:06.772571 Exit from PICG configuration <<<<
3844 10:02:06.775851 [RX_INPUT] configuration >>>>>
3845 10:02:06.779159 [RX_INPUT] configuration <<<<<
3846 10:02:06.782449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3847 10:02:06.788919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3848 10:02:06.795621 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 10:02:06.802135 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 10:02:06.805388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 10:02:06.811997 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 10:02:06.815674 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3853 10:02:06.822376 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3854 10:02:06.825517 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3855 10:02:06.828911 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3856 10:02:06.831953 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3857 10:02:06.838975 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3858 10:02:06.841996 ===================================
3859 10:02:06.845668 LPDDR4 DRAM CONFIGURATION
3860 10:02:06.845764 ===================================
3861 10:02:06.849012 EX_ROW_EN[0] = 0x0
3862 10:02:06.852429 EX_ROW_EN[1] = 0x0
3863 10:02:06.852497 LP4Y_EN = 0x0
3864 10:02:06.855540 WORK_FSP = 0x0
3865 10:02:06.855666 WL = 0x2
3866 10:02:06.858699 RL = 0x2
3867 10:02:06.858796 BL = 0x2
3868 10:02:06.862006 RPST = 0x0
3869 10:02:06.862099 RD_PRE = 0x0
3870 10:02:06.865373 WR_PRE = 0x1
3871 10:02:06.865466 WR_PST = 0x0
3872 10:02:06.868508 DBI_WR = 0x0
3873 10:02:06.868576 DBI_RD = 0x0
3874 10:02:06.871766 OTF = 0x1
3875 10:02:06.875575 ===================================
3876 10:02:06.878660 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3877 10:02:06.881942 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3878 10:02:06.888535 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 10:02:06.892432 ===================================
3880 10:02:06.892500 LPDDR4 DRAM CONFIGURATION
3881 10:02:06.895698 ===================================
3882 10:02:06.898693 EX_ROW_EN[0] = 0x10
3883 10:02:06.898766 EX_ROW_EN[1] = 0x0
3884 10:02:06.902218 LP4Y_EN = 0x0
3885 10:02:06.905640 WORK_FSP = 0x0
3886 10:02:06.905737 WL = 0x2
3887 10:02:06.908622 RL = 0x2
3888 10:02:06.908688 BL = 0x2
3889 10:02:06.912181 RPST = 0x0
3890 10:02:06.912247 RD_PRE = 0x0
3891 10:02:06.915364 WR_PRE = 0x1
3892 10:02:06.915434 WR_PST = 0x0
3893 10:02:06.919092 DBI_WR = 0x0
3894 10:02:06.919178 DBI_RD = 0x0
3895 10:02:06.922115 OTF = 0x1
3896 10:02:06.925710 ===================================
3897 10:02:06.932186 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3898 10:02:06.935228 nWR fixed to 30
3899 10:02:06.935339 [ModeRegInit_LP4] CH0 RK0
3900 10:02:06.938834 [ModeRegInit_LP4] CH0 RK1
3901 10:02:06.941901 [ModeRegInit_LP4] CH1 RK0
3902 10:02:06.942002 [ModeRegInit_LP4] CH1 RK1
3903 10:02:06.945720 match AC timing 17
3904 10:02:06.948759 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3905 10:02:06.952219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3906 10:02:06.958620 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3907 10:02:06.962484 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3908 10:02:06.968993 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3909 10:02:06.969089 ==
3910 10:02:06.972211 Dram Type= 6, Freq= 0, CH_0, rank 0
3911 10:02:06.975417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3912 10:02:06.975511 ==
3913 10:02:06.982060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3914 10:02:06.985330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3915 10:02:06.989448 [CA 0] Center 35 (4~66) winsize 63
3916 10:02:06.992874 [CA 1] Center 35 (5~66) winsize 62
3917 10:02:06.996706 [CA 2] Center 33 (3~64) winsize 62
3918 10:02:06.999852 [CA 3] Center 33 (2~64) winsize 63
3919 10:02:07.003137 [CA 4] Center 33 (2~64) winsize 63
3920 10:02:07.006441 [CA 5] Center 32 (2~63) winsize 62
3921 10:02:07.006536
3922 10:02:07.009431 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3923 10:02:07.009525
3924 10:02:07.012930 [CATrainingPosCal] consider 1 rank data
3925 10:02:07.016075 u2DelayCellTimex100 = 270/100 ps
3926 10:02:07.019507 CA0 delay=35 (4~66),Diff = 3 PI (28 cell)
3927 10:02:07.025882 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3928 10:02:07.029672 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3929 10:02:07.032865 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3930 10:02:07.036013 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3931 10:02:07.039537 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3932 10:02:07.039690
3933 10:02:07.042488 CA PerBit enable=1, Macro0, CA PI delay=32
3934 10:02:07.042585
3935 10:02:07.046037 [CBTSetCACLKResult] CA Dly = 32
3936 10:02:07.046142 CS Dly: 4 (0~35)
3937 10:02:07.049590 ==
3938 10:02:07.052832 Dram Type= 6, Freq= 0, CH_0, rank 1
3939 10:02:07.055997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3940 10:02:07.056077 ==
3941 10:02:07.059083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3942 10:02:07.065930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3943 10:02:07.069804 [CA 0] Center 35 (5~66) winsize 62
3944 10:02:07.073213 [CA 1] Center 35 (5~66) winsize 62
3945 10:02:07.076453 [CA 2] Center 34 (3~65) winsize 63
3946 10:02:07.079577 [CA 3] Center 33 (2~64) winsize 63
3947 10:02:07.083406 [CA 4] Center 32 (2~63) winsize 62
3948 10:02:07.086538 [CA 5] Center 32 (2~63) winsize 62
3949 10:02:07.086612
3950 10:02:07.089744 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3951 10:02:07.089842
3952 10:02:07.093016 [CATrainingPosCal] consider 2 rank data
3953 10:02:07.096826 u2DelayCellTimex100 = 270/100 ps
3954 10:02:07.100212 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3955 10:02:07.103330 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3956 10:02:07.109887 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3957 10:02:07.113069 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3958 10:02:07.116817 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3959 10:02:07.120252 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3960 10:02:07.120339
3961 10:02:07.123110 CA PerBit enable=1, Macro0, CA PI delay=32
3962 10:02:07.123214
3963 10:02:07.126363 [CBTSetCACLKResult] CA Dly = 32
3964 10:02:07.126469 CS Dly: 4 (0~36)
3965 10:02:07.126558
3966 10:02:07.129994 ----->DramcWriteLeveling(PI) begin...
3967 10:02:07.132961 ==
3968 10:02:07.133034 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 10:02:07.139462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 10:02:07.139562 ==
3971 10:02:07.143255 Write leveling (Byte 0): 36 => 36
3972 10:02:07.146463 Write leveling (Byte 1): 31 => 31
3973 10:02:07.149819 DramcWriteLeveling(PI) end<-----
3974 10:02:07.149917
3975 10:02:07.150015 ==
3976 10:02:07.152806 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 10:02:07.156344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 10:02:07.156444 ==
3979 10:02:07.159792 [Gating] SW mode calibration
3980 10:02:07.166706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3981 10:02:07.169723 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3982 10:02:07.176659 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 10:02:07.179488 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 10:02:07.183448 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 10:02:07.189674 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
3986 10:02:07.192891 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3987 10:02:07.196047 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 10:02:07.202736 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 10:02:07.206524 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 10:02:07.209740 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 10:02:07.216435 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 10:02:07.219587 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 10:02:07.222770 0 10 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
3994 10:02:07.229643 0 10 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
3995 10:02:07.232847 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 10:02:07.235882 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 10:02:07.242560 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 10:02:07.246120 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 10:02:07.249267 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 10:02:07.256331 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 10:02:07.259545 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4002 10:02:07.262643 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 10:02:07.269125 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 10:02:07.272442 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 10:02:07.275563 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 10:02:07.282389 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 10:02:07.285575 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 10:02:07.288831 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 10:02:07.295902 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 10:02:07.298862 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 10:02:07.302027 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 10:02:07.309120 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 10:02:07.312439 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 10:02:07.315689 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 10:02:07.319066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 10:02:07.325956 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 10:02:07.329149 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4018 10:02:07.332154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4019 10:02:07.335375 Total UI for P1: 0, mck2ui 16
4020 10:02:07.338817 best dqsien dly found for B0: ( 0, 13, 12)
4021 10:02:07.345725 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 10:02:07.348808 Total UI for P1: 0, mck2ui 16
4023 10:02:07.351870 best dqsien dly found for B1: ( 0, 13, 16)
4024 10:02:07.355706 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4025 10:02:07.358650 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4026 10:02:07.358722
4027 10:02:07.362223 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4028 10:02:07.365496 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4029 10:02:07.368622 [Gating] SW calibration Done
4030 10:02:07.368719 ==
4031 10:02:07.372337 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 10:02:07.375550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 10:02:07.375691 ==
4034 10:02:07.378592 RX Vref Scan: 0
4035 10:02:07.378686
4036 10:02:07.382101 RX Vref 0 -> 0, step: 1
4037 10:02:07.382207
4038 10:02:07.382297 RX Delay -230 -> 252, step: 16
4039 10:02:07.388672 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4040 10:02:07.391713 iDelay=218, Bit 1, Center 65 (-86 ~ 217) 304
4041 10:02:07.395510 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4042 10:02:07.398764 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4043 10:02:07.401993 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4044 10:02:07.408959 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4045 10:02:07.412274 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4046 10:02:07.415513 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4047 10:02:07.418754 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4048 10:02:07.421934 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4049 10:02:07.428672 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4050 10:02:07.431890 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4051 10:02:07.434936 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4052 10:02:07.438590 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4053 10:02:07.445109 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4054 10:02:07.448208 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4055 10:02:07.448314 ==
4056 10:02:07.451490 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 10:02:07.455112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 10:02:07.455185 ==
4059 10:02:07.458429 DQS Delay:
4060 10:02:07.458527 DQS0 = 0, DQS1 = 0
4061 10:02:07.458617 DQM Delay:
4062 10:02:07.461595 DQM0 = 58, DQM1 = 51
4063 10:02:07.461708 DQ Delay:
4064 10:02:07.465353 DQ0 =57, DQ1 =65, DQ2 =57, DQ3 =57
4065 10:02:07.468386 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4066 10:02:07.471951 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =41
4067 10:02:07.474892 DQ12 =57, DQ13 =57, DQ14 =65, DQ15 =65
4068 10:02:07.475004
4069 10:02:07.475097
4070 10:02:07.475186 ==
4071 10:02:07.478018 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 10:02:07.484929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 10:02:07.485046 ==
4074 10:02:07.485178
4075 10:02:07.485365
4076 10:02:07.485548 TX Vref Scan disable
4077 10:02:07.488461 == TX Byte 0 ==
4078 10:02:07.492062 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4079 10:02:07.495307 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4080 10:02:07.498485 == TX Byte 1 ==
4081 10:02:07.502054 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4082 10:02:07.508318 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4083 10:02:07.508399 ==
4084 10:02:07.511893 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 10:02:07.515067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 10:02:07.515148 ==
4087 10:02:07.515211
4088 10:02:07.515270
4089 10:02:07.518314 TX Vref Scan disable
4090 10:02:07.521542 == TX Byte 0 ==
4091 10:02:07.525297 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4092 10:02:07.528568 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4093 10:02:07.531517 == TX Byte 1 ==
4094 10:02:07.535131 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4095 10:02:07.538408 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4096 10:02:07.538501
4097 10:02:07.538563 [DATLAT]
4098 10:02:07.541519 Freq=600, CH0 RK0
4099 10:02:07.541629
4100 10:02:07.541692 DATLAT Default: 0x9
4101 10:02:07.544652 0, 0xFFFF, sum = 0
4102 10:02:07.547887 1, 0xFFFF, sum = 0
4103 10:02:07.547968 2, 0xFFFF, sum = 0
4104 10:02:07.551743 3, 0xFFFF, sum = 0
4105 10:02:07.551838 4, 0xFFFF, sum = 0
4106 10:02:07.555074 5, 0xFFFF, sum = 0
4107 10:02:07.555155 6, 0xFFFF, sum = 0
4108 10:02:07.558228 7, 0xFFFF, sum = 0
4109 10:02:07.558309 8, 0x0, sum = 1
4110 10:02:07.561216 9, 0x0, sum = 2
4111 10:02:07.561298 10, 0x0, sum = 3
4112 10:02:07.564478 11, 0x0, sum = 4
4113 10:02:07.564560 best_step = 9
4114 10:02:07.564638
4115 10:02:07.564710 ==
4116 10:02:07.568447 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 10:02:07.571794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 10:02:07.571874 ==
4119 10:02:07.574632 RX Vref Scan: 1
4120 10:02:07.574712
4121 10:02:07.574812 RX Vref 0 -> 0, step: 1
4122 10:02:07.574871
4123 10:02:07.577947 RX Delay -163 -> 252, step: 8
4124 10:02:07.578027
4125 10:02:07.581450 Set Vref, RX VrefLevel [Byte0]: 55
4126 10:02:07.585010 [Byte1]: 49
4127 10:02:07.588636
4128 10:02:07.588717 Final RX Vref Byte 0 = 55 to rank0
4129 10:02:07.591932 Final RX Vref Byte 1 = 49 to rank0
4130 10:02:07.595312 Final RX Vref Byte 0 = 55 to rank1
4131 10:02:07.598972 Final RX Vref Byte 1 = 49 to rank1==
4132 10:02:07.601827 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 10:02:07.608455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 10:02:07.608540 ==
4135 10:02:07.608602 DQS Delay:
4136 10:02:07.612078 DQS0 = 0, DQS1 = 0
4137 10:02:07.612153 DQM Delay:
4138 10:02:07.612215 DQM0 = 51, DQM1 = 45
4139 10:02:07.615095 DQ Delay:
4140 10:02:07.618940 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4141 10:02:07.622036 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4142 10:02:07.625384 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4143 10:02:07.628724 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4144 10:02:07.628821
4145 10:02:07.628918
4146 10:02:07.635127 [DQSOSCAuto] RK0, (LSB)MR18= 0x7165, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4147 10:02:07.638914 CH0 RK0: MR19=808, MR18=7165
4148 10:02:07.645231 CH0_RK0: MR19=0x808, MR18=0x7165, DQSOSC=388, MR23=63, INC=174, DEC=116
4149 10:02:07.645311
4150 10:02:07.648406 ----->DramcWriteLeveling(PI) begin...
4151 10:02:07.648480 ==
4152 10:02:07.652230 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 10:02:07.655588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 10:02:07.655726 ==
4155 10:02:07.658834 Write leveling (Byte 0): 34 => 34
4156 10:02:07.662109 Write leveling (Byte 1): 31 => 31
4157 10:02:07.665211 DramcWriteLeveling(PI) end<-----
4158 10:02:07.665307
4159 10:02:07.665403 ==
4160 10:02:07.668977 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 10:02:07.672261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 10:02:07.672358 ==
4163 10:02:07.675515 [Gating] SW mode calibration
4164 10:02:07.682470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4165 10:02:07.688707 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4166 10:02:07.691972 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 10:02:07.695558 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 10:02:07.701903 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 10:02:07.705665 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
4170 10:02:07.708628 0 9 16 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
4171 10:02:07.715326 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 10:02:07.718963 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 10:02:07.722047 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 10:02:07.728813 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 10:02:07.731890 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 10:02:07.735134 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 10:02:07.742131 0 10 12 | B1->B0 | 2525 2f2e | 0 1 | (0 0) (0 0)
4178 10:02:07.745177 0 10 16 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
4179 10:02:07.748395 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 10:02:07.755403 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 10:02:07.758460 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 10:02:07.761766 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 10:02:07.768906 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 10:02:07.772029 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 10:02:07.774941 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4186 10:02:07.781934 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4187 10:02:07.785109 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 10:02:07.788376 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 10:02:07.791754 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 10:02:07.798639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 10:02:07.801625 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 10:02:07.805207 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 10:02:07.811861 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 10:02:07.814820 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 10:02:07.818486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 10:02:07.825439 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 10:02:07.828556 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 10:02:07.831451 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 10:02:07.838240 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 10:02:07.841491 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 10:02:07.844658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4202 10:02:07.851342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 10:02:07.854985 Total UI for P1: 0, mck2ui 16
4204 10:02:07.858196 best dqsien dly found for B0: ( 0, 13, 12)
4205 10:02:07.858279 Total UI for P1: 0, mck2ui 16
4206 10:02:07.864712 best dqsien dly found for B1: ( 0, 13, 14)
4207 10:02:07.868053 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4208 10:02:07.871380 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4209 10:02:07.871487
4210 10:02:07.874542 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4211 10:02:07.877722 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4212 10:02:07.881291 [Gating] SW calibration Done
4213 10:02:07.881373 ==
4214 10:02:07.884968 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 10:02:07.888149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 10:02:07.888231 ==
4217 10:02:07.891373 RX Vref Scan: 0
4218 10:02:07.891454
4219 10:02:07.894547 RX Vref 0 -> 0, step: 1
4220 10:02:07.894656
4221 10:02:07.894724 RX Delay -230 -> 252, step: 16
4222 10:02:07.901060 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4223 10:02:07.904381 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4224 10:02:07.908131 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4225 10:02:07.911042 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4226 10:02:07.914774 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4227 10:02:07.921226 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4228 10:02:07.925044 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4229 10:02:07.928372 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4230 10:02:07.931759 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4231 10:02:07.934868 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4232 10:02:07.941204 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4233 10:02:07.945004 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4234 10:02:07.947979 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4235 10:02:07.951175 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4236 10:02:07.958011 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4237 10:02:07.961734 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4238 10:02:07.961817 ==
4239 10:02:07.964853 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 10:02:07.968053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 10:02:07.968136 ==
4242 10:02:07.971373 DQS Delay:
4243 10:02:07.971455 DQS0 = 0, DQS1 = 0
4244 10:02:07.971553 DQM Delay:
4245 10:02:07.974566 DQM0 = 53, DQM1 = 42
4246 10:02:07.974649 DQ Delay:
4247 10:02:07.978401 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4248 10:02:07.981710 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4249 10:02:07.984851 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4250 10:02:07.987885 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4251 10:02:07.987967
4252 10:02:07.988051
4253 10:02:07.988130 ==
4254 10:02:07.991474 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 10:02:07.998148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 10:02:07.998232 ==
4257 10:02:07.998317
4258 10:02:07.998397
4259 10:02:07.998506 TX Vref Scan disable
4260 10:02:08.002019 == TX Byte 0 ==
4261 10:02:08.005135 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4262 10:02:08.008430 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4263 10:02:08.011732 == TX Byte 1 ==
4264 10:02:08.014959 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4265 10:02:08.021497 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4266 10:02:08.021580 ==
4267 10:02:08.025211 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 10:02:08.028341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 10:02:08.028424 ==
4270 10:02:08.028509
4271 10:02:08.028590
4272 10:02:08.031532 TX Vref Scan disable
4273 10:02:08.034702 == TX Byte 0 ==
4274 10:02:08.038316 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4275 10:02:08.041744 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4276 10:02:08.044795 == TX Byte 1 ==
4277 10:02:08.047986 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4278 10:02:08.051586 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4279 10:02:08.051707
4280 10:02:08.051771 [DATLAT]
4281 10:02:08.055033 Freq=600, CH0 RK1
4282 10:02:08.055102
4283 10:02:08.055159 DATLAT Default: 0x9
4284 10:02:08.058086 0, 0xFFFF, sum = 0
4285 10:02:08.061399 1, 0xFFFF, sum = 0
4286 10:02:08.061481 2, 0xFFFF, sum = 0
4287 10:02:08.065066 3, 0xFFFF, sum = 0
4288 10:02:08.065147 4, 0xFFFF, sum = 0
4289 10:02:08.067969 5, 0xFFFF, sum = 0
4290 10:02:08.068063 6, 0xFFFF, sum = 0
4291 10:02:08.071187 7, 0xFFFF, sum = 0
4292 10:02:08.071259 8, 0x0, sum = 1
4293 10:02:08.075049 9, 0x0, sum = 2
4294 10:02:08.075130 10, 0x0, sum = 3
4295 10:02:08.075194 11, 0x0, sum = 4
4296 10:02:08.078287 best_step = 9
4297 10:02:08.078366
4298 10:02:08.078430 ==
4299 10:02:08.081569 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 10:02:08.084771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 10:02:08.084851 ==
4302 10:02:08.088048 RX Vref Scan: 0
4303 10:02:08.088127
4304 10:02:08.088190 RX Vref 0 -> 0, step: 1
4305 10:02:08.091263
4306 10:02:08.091343 RX Delay -179 -> 252, step: 8
4307 10:02:08.098688 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4308 10:02:08.102039 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4309 10:02:08.105901 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4310 10:02:08.109178 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4311 10:02:08.112398 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4312 10:02:08.118792 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4313 10:02:08.122714 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4314 10:02:08.125755 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4315 10:02:08.128980 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4316 10:02:08.131970 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4317 10:02:08.139064 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4318 10:02:08.142280 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4319 10:02:08.145497 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4320 10:02:08.149076 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4321 10:02:08.155363 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4322 10:02:08.158964 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4323 10:02:08.159043 ==
4324 10:02:08.162072 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 10:02:08.165754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 10:02:08.165834 ==
4327 10:02:08.165897 DQS Delay:
4328 10:02:08.168761 DQS0 = 0, DQS1 = 0
4329 10:02:08.168840 DQM Delay:
4330 10:02:08.171839 DQM0 = 53, DQM1 = 46
4331 10:02:08.171922 DQ Delay:
4332 10:02:08.175314 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4333 10:02:08.178367 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4334 10:02:08.182162 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4335 10:02:08.185401 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4336 10:02:08.185505
4337 10:02:08.185595
4338 10:02:08.195485 [DQSOSCAuto] RK1, (LSB)MR18= 0x692a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 390 ps
4339 10:02:08.195567 CH0 RK1: MR19=808, MR18=692A
4340 10:02:08.201567 CH0_RK1: MR19=0x808, MR18=0x692A, DQSOSC=390, MR23=63, INC=172, DEC=114
4341 10:02:08.204840 [RxdqsGatingPostProcess] freq 600
4342 10:02:08.212088 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4343 10:02:08.215477 Pre-setting of DQS Precalculation
4344 10:02:08.218713 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4345 10:02:08.218794 ==
4346 10:02:08.222048 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 10:02:08.225381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 10:02:08.228412 ==
4349 10:02:08.231633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 10:02:08.238051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4351 10:02:08.241961 [CA 0] Center 35 (5~66) winsize 62
4352 10:02:08.244848 [CA 1] Center 35 (5~66) winsize 62
4353 10:02:08.248527 [CA 2] Center 34 (4~65) winsize 62
4354 10:02:08.251775 [CA 3] Center 34 (3~65) winsize 63
4355 10:02:08.255045 [CA 4] Center 34 (4~65) winsize 62
4356 10:02:08.257994 [CA 5] Center 33 (3~64) winsize 62
4357 10:02:08.258073
4358 10:02:08.261690 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4359 10:02:08.261770
4360 10:02:08.265077 [CATrainingPosCal] consider 1 rank data
4361 10:02:08.267917 u2DelayCellTimex100 = 270/100 ps
4362 10:02:08.271729 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4363 10:02:08.274687 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4364 10:02:08.278379 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 10:02:08.285010 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4366 10:02:08.287849 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4367 10:02:08.291678 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 10:02:08.291892
4369 10:02:08.294879 CA PerBit enable=1, Macro0, CA PI delay=33
4370 10:02:08.295034
4371 10:02:08.297698 [CBTSetCACLKResult] CA Dly = 33
4372 10:02:08.297831 CS Dly: 6 (0~37)
4373 10:02:08.297901 ==
4374 10:02:08.301736 Dram Type= 6, Freq= 0, CH_1, rank 1
4375 10:02:08.308167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 10:02:08.308344 ==
4377 10:02:08.311297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 10:02:08.318069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4379 10:02:08.321385 [CA 0] Center 36 (5~67) winsize 63
4380 10:02:08.324660 [CA 1] Center 36 (6~67) winsize 62
4381 10:02:08.327794 [CA 2] Center 35 (4~66) winsize 63
4382 10:02:08.331578 [CA 3] Center 35 (4~66) winsize 63
4383 10:02:08.334814 [CA 4] Center 35 (4~66) winsize 63
4384 10:02:08.338065 [CA 5] Center 34 (4~65) winsize 62
4385 10:02:08.338258
4386 10:02:08.341471 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4387 10:02:08.341558
4388 10:02:08.344793 [CATrainingPosCal] consider 2 rank data
4389 10:02:08.347848 u2DelayCellTimex100 = 270/100 ps
4390 10:02:08.351087 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4391 10:02:08.354615 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4392 10:02:08.360991 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 10:02:08.364578 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4394 10:02:08.367873 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4395 10:02:08.370924 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4396 10:02:08.371010
4397 10:02:08.374362 CA PerBit enable=1, Macro0, CA PI delay=34
4398 10:02:08.374445
4399 10:02:08.378018 [CBTSetCACLKResult] CA Dly = 34
4400 10:02:08.378102 CS Dly: 6 (0~38)
4401 10:02:08.378188
4402 10:02:08.381168 ----->DramcWriteLeveling(PI) begin...
4403 10:02:08.384356 ==
4404 10:02:08.387937 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 10:02:08.390867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 10:02:08.391018 ==
4407 10:02:08.394474 Write leveling (Byte 0): 29 => 29
4408 10:02:08.397546 Write leveling (Byte 1): 31 => 31
4409 10:02:08.401354 DramcWriteLeveling(PI) end<-----
4410 10:02:08.401493
4411 10:02:08.401612 ==
4412 10:02:08.404631 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 10:02:08.407777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 10:02:08.407917 ==
4415 10:02:08.411079 [Gating] SW mode calibration
4416 10:02:08.417312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 10:02:08.424077 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4418 10:02:08.427397 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 10:02:08.430656 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 10:02:08.434469 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4421 10:02:08.440870 0 9 12 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
4422 10:02:08.444097 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4423 10:02:08.447329 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 10:02:08.454393 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 10:02:08.457615 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 10:02:08.460701 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 10:02:08.467330 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 10:02:08.471120 0 10 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
4429 10:02:08.474220 0 10 12 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
4430 10:02:08.481299 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 10:02:08.484016 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 10:02:08.487456 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 10:02:08.494485 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 10:02:08.497347 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 10:02:08.501003 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 10:02:08.507767 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 10:02:08.511012 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4438 10:02:08.514328 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 10:02:08.520710 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 10:02:08.524494 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 10:02:08.527614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 10:02:08.530860 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 10:02:08.537675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 10:02:08.540965 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 10:02:08.544252 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 10:02:08.550688 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 10:02:08.554062 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 10:02:08.557337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 10:02:08.563948 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 10:02:08.567717 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 10:02:08.570766 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 10:02:08.577335 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4453 10:02:08.581159 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4454 10:02:08.584476 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 10:02:08.587475 Total UI for P1: 0, mck2ui 16
4456 10:02:08.590631 best dqsien dly found for B0: ( 0, 13, 12)
4457 10:02:08.594289 Total UI for P1: 0, mck2ui 16
4458 10:02:08.597251 best dqsien dly found for B1: ( 0, 13, 10)
4459 10:02:08.600374 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4460 10:02:08.603985 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4461 10:02:08.604065
4462 10:02:08.610859 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4463 10:02:08.614069 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4464 10:02:08.617404 [Gating] SW calibration Done
4465 10:02:08.617510 ==
4466 10:02:08.620582 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 10:02:08.623683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 10:02:08.623770 ==
4469 10:02:08.623855 RX Vref Scan: 0
4470 10:02:08.623920
4471 10:02:08.627345 RX Vref 0 -> 0, step: 1
4472 10:02:08.627463
4473 10:02:08.630470 RX Delay -230 -> 252, step: 16
4474 10:02:08.633643 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4475 10:02:08.640405 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4476 10:02:08.643649 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4477 10:02:08.646804 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4478 10:02:08.650098 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4479 10:02:08.653823 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4480 10:02:08.660412 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4481 10:02:08.663759 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4482 10:02:08.666922 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4483 10:02:08.670174 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4484 10:02:08.676446 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4485 10:02:08.680139 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4486 10:02:08.683513 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4487 10:02:08.686689 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4488 10:02:08.689908 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4489 10:02:08.696959 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4490 10:02:08.697065 ==
4491 10:02:08.700098 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 10:02:08.703581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 10:02:08.703665 ==
4494 10:02:08.703730 DQS Delay:
4495 10:02:08.706759 DQS0 = 0, DQS1 = 0
4496 10:02:08.706835 DQM Delay:
4497 10:02:08.710390 DQM0 = 47, DQM1 = 46
4498 10:02:08.710495 DQ Delay:
4499 10:02:08.713358 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4500 10:02:08.717110 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4501 10:02:08.719930 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4502 10:02:08.723441 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4503 10:02:08.723551
4504 10:02:08.723652
4505 10:02:08.723750 ==
4506 10:02:08.726499 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 10:02:08.730265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 10:02:08.733514 ==
4509 10:02:08.733623
4510 10:02:08.733713
4511 10:02:08.733809 TX Vref Scan disable
4512 10:02:08.736735 == TX Byte 0 ==
4513 10:02:08.740353 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4514 10:02:08.743288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4515 10:02:08.746570 == TX Byte 1 ==
4516 10:02:08.750270 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4517 10:02:08.753470 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4518 10:02:08.756644 ==
4519 10:02:08.759990 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 10:02:08.763108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 10:02:08.763184 ==
4522 10:02:08.763282
4523 10:02:08.763370
4524 10:02:08.766434 TX Vref Scan disable
4525 10:02:08.766533 == TX Byte 0 ==
4526 10:02:08.773141 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4527 10:02:08.776399 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4528 10:02:08.776482 == TX Byte 1 ==
4529 10:02:08.783414 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4530 10:02:08.786331 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4531 10:02:08.786414
4532 10:02:08.786478 [DATLAT]
4533 10:02:08.789408 Freq=600, CH1 RK0
4534 10:02:08.789513
4535 10:02:08.789616 DATLAT Default: 0x9
4536 10:02:08.793270 0, 0xFFFF, sum = 0
4537 10:02:08.793373 1, 0xFFFF, sum = 0
4538 10:02:08.796292 2, 0xFFFF, sum = 0
4539 10:02:08.796376 3, 0xFFFF, sum = 0
4540 10:02:08.799537 4, 0xFFFF, sum = 0
4541 10:02:08.802860 5, 0xFFFF, sum = 0
4542 10:02:08.802960 6, 0xFFFF, sum = 0
4543 10:02:08.806486 7, 0xFFFF, sum = 0
4544 10:02:08.806584 8, 0x0, sum = 1
4545 10:02:08.806678 9, 0x0, sum = 2
4546 10:02:08.809541 10, 0x0, sum = 3
4547 10:02:08.809646 11, 0x0, sum = 4
4548 10:02:08.812732 best_step = 9
4549 10:02:08.812812
4550 10:02:08.812900 ==
4551 10:02:08.816407 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 10:02:08.819599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 10:02:08.819696 ==
4554 10:02:08.822829 RX Vref Scan: 1
4555 10:02:08.822910
4556 10:02:08.822974 RX Vref 0 -> 0, step: 1
4557 10:02:08.823034
4558 10:02:08.826423 RX Delay -163 -> 252, step: 8
4559 10:02:08.826503
4560 10:02:08.829545 Set Vref, RX VrefLevel [Byte0]: 53
4561 10:02:08.832732 [Byte1]: 51
4562 10:02:08.836681
4563 10:02:08.836761 Final RX Vref Byte 0 = 53 to rank0
4564 10:02:08.839981 Final RX Vref Byte 1 = 51 to rank0
4565 10:02:08.843702 Final RX Vref Byte 0 = 53 to rank1
4566 10:02:08.846826 Final RX Vref Byte 1 = 51 to rank1==
4567 10:02:08.849936 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 10:02:08.856754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 10:02:08.856857 ==
4570 10:02:08.856948 DQS Delay:
4571 10:02:08.857038 DQS0 = 0, DQS1 = 0
4572 10:02:08.860118 DQM Delay:
4573 10:02:08.860215 DQM0 = 49, DQM1 = 45
4574 10:02:08.863443 DQ Delay:
4575 10:02:08.866697 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4576 10:02:08.866771 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4577 10:02:08.869985 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4578 10:02:08.873307 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4579 10:02:08.877147
4580 10:02:08.877249
4581 10:02:08.883745 [DQSOSCAuto] RK0, (LSB)MR18= 0x496e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4582 10:02:08.886904 CH1 RK0: MR19=808, MR18=496E
4583 10:02:08.893804 CH1_RK0: MR19=0x808, MR18=0x496E, DQSOSC=389, MR23=63, INC=173, DEC=115
4584 10:02:08.893908
4585 10:02:08.896871 ----->DramcWriteLeveling(PI) begin...
4586 10:02:08.896971 ==
4587 10:02:08.899809 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 10:02:08.903360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 10:02:08.903458 ==
4590 10:02:08.906629 Write leveling (Byte 0): 31 => 31
4591 10:02:08.910532 Write leveling (Byte 1): 31 => 31
4592 10:02:08.913487 DramcWriteLeveling(PI) end<-----
4593 10:02:08.913581
4594 10:02:08.913675 ==
4595 10:02:08.916639 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 10:02:08.920375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 10:02:08.920485 ==
4598 10:02:08.923618 [Gating] SW mode calibration
4599 10:02:08.929983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4600 10:02:08.937002 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4601 10:02:08.940085 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 10:02:08.943375 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 10:02:08.950067 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4604 10:02:08.953347 0 9 12 | B1->B0 | 2d2d 2c2c | 0 0 | (1 0) (1 0)
4605 10:02:08.956714 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 10:02:08.963838 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 10:02:08.966983 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 10:02:08.970044 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 10:02:08.976619 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 10:02:08.979896 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 10:02:08.983154 0 10 8 | B1->B0 | 2626 2525 | 1 1 | (0 0) (0 0)
4612 10:02:08.989700 0 10 12 | B1->B0 | 3d3d 3939 | 0 0 | (0 0) (0 0)
4613 10:02:08.992934 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 10:02:08.996560 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 10:02:09.003085 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 10:02:09.006804 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 10:02:09.009817 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 10:02:09.016668 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 10:02:09.019750 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4620 10:02:09.023177 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 10:02:09.029748 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 10:02:09.032841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 10:02:09.036607 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 10:02:09.039934 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 10:02:09.046442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 10:02:09.049635 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 10:02:09.052903 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 10:02:09.060070 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 10:02:09.063210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 10:02:09.066343 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 10:02:09.072902 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 10:02:09.076429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 10:02:09.079813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 10:02:09.086270 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 10:02:09.089531 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 10:02:09.093244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 10:02:09.096451 Total UI for P1: 0, mck2ui 16
4638 10:02:09.099467 best dqsien dly found for B0: ( 0, 13, 10)
4639 10:02:09.102674 Total UI for P1: 0, mck2ui 16
4640 10:02:09.106407 best dqsien dly found for B1: ( 0, 13, 10)
4641 10:02:09.109613 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4642 10:02:09.112700 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4643 10:02:09.115908
4644 10:02:09.119622 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4645 10:02:09.122829 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4646 10:02:09.126001 [Gating] SW calibration Done
4647 10:02:09.126160 ==
4648 10:02:09.129482 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 10:02:09.132978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 10:02:09.133144 ==
4651 10:02:09.133252 RX Vref Scan: 0
4652 10:02:09.133340
4653 10:02:09.135973 RX Vref 0 -> 0, step: 1
4654 10:02:09.136093
4655 10:02:09.139730 RX Delay -230 -> 252, step: 16
4656 10:02:09.143011 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4657 10:02:09.146244 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4658 10:02:09.152692 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4659 10:02:09.155926 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4660 10:02:09.159878 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4661 10:02:09.163061 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4662 10:02:09.166316 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4663 10:02:09.172931 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4664 10:02:09.176211 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4665 10:02:09.179384 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4666 10:02:09.183202 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4667 10:02:09.189420 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4668 10:02:09.193050 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4669 10:02:09.195989 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4670 10:02:09.199588 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4671 10:02:09.206138 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4672 10:02:09.206227 ==
4673 10:02:09.209446 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 10:02:09.212669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 10:02:09.212742 ==
4676 10:02:09.212811 DQS Delay:
4677 10:02:09.215946 DQS0 = 0, DQS1 = 0
4678 10:02:09.216018 DQM Delay:
4679 10:02:09.219660 DQM0 = 50, DQM1 = 48
4680 10:02:09.219744 DQ Delay:
4681 10:02:09.223012 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4682 10:02:09.226144 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4683 10:02:09.229659 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4684 10:02:09.232830 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4685 10:02:09.232900
4686 10:02:09.232966
4687 10:02:09.233028 ==
4688 10:02:09.235834 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 10:02:09.239216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 10:02:09.239337 ==
4691 10:02:09.239419
4692 10:02:09.239479
4693 10:02:09.242699 TX Vref Scan disable
4694 10:02:09.246256 == TX Byte 0 ==
4695 10:02:09.249232 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4696 10:02:09.253102 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4697 10:02:09.256382 == TX Byte 1 ==
4698 10:02:09.259657 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4699 10:02:09.262909 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4700 10:02:09.262983 ==
4701 10:02:09.266317 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 10:02:09.272726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 10:02:09.272800 ==
4704 10:02:09.272867
4705 10:02:09.272925
4706 10:02:09.272984 TX Vref Scan disable
4707 10:02:09.277263 == TX Byte 0 ==
4708 10:02:09.280399 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4709 10:02:09.286788 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4710 10:02:09.286868 == TX Byte 1 ==
4711 10:02:09.290061 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4712 10:02:09.297008 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4713 10:02:09.297081
4714 10:02:09.297152 [DATLAT]
4715 10:02:09.297212 Freq=600, CH1 RK1
4716 10:02:09.297271
4717 10:02:09.300262 DATLAT Default: 0x9
4718 10:02:09.300331 0, 0xFFFF, sum = 0
4719 10:02:09.303243 1, 0xFFFF, sum = 0
4720 10:02:09.303316 2, 0xFFFF, sum = 0
4721 10:02:09.306890 3, 0xFFFF, sum = 0
4722 10:02:09.310039 4, 0xFFFF, sum = 0
4723 10:02:09.310115 5, 0xFFFF, sum = 0
4724 10:02:09.313743 6, 0xFFFF, sum = 0
4725 10:02:09.313820 7, 0xFFFF, sum = 0
4726 10:02:09.316611 8, 0x0, sum = 1
4727 10:02:09.316682 9, 0x0, sum = 2
4728 10:02:09.316748 10, 0x0, sum = 3
4729 10:02:09.320090 11, 0x0, sum = 4
4730 10:02:09.320157 best_step = 9
4731 10:02:09.320222
4732 10:02:09.320282 ==
4733 10:02:09.323309 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 10:02:09.329844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 10:02:09.329923 ==
4736 10:02:09.329988 RX Vref Scan: 0
4737 10:02:09.330048
4738 10:02:09.333579 RX Vref 0 -> 0, step: 1
4739 10:02:09.333654
4740 10:02:09.336543 RX Delay -163 -> 252, step: 8
4741 10:02:09.339759 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4742 10:02:09.346716 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4743 10:02:09.349809 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4744 10:02:09.353228 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4745 10:02:09.356815 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4746 10:02:09.359888 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4747 10:02:09.363072 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4748 10:02:09.370228 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4749 10:02:09.373416 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4750 10:02:09.376582 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4751 10:02:09.379903 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4752 10:02:09.386498 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4753 10:02:09.389836 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4754 10:02:09.393152 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4755 10:02:09.396339 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4756 10:02:09.403493 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4757 10:02:09.403629 ==
4758 10:02:09.406711 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 10:02:09.409782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 10:02:09.409863 ==
4761 10:02:09.409928 DQS Delay:
4762 10:02:09.413176 DQS0 = 0, DQS1 = 0
4763 10:02:09.413255 DQM Delay:
4764 10:02:09.416453 DQM0 = 49, DQM1 = 45
4765 10:02:09.416535 DQ Delay:
4766 10:02:09.419730 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4767 10:02:09.423429 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4768 10:02:09.426551 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4769 10:02:09.429527 DQ12 =52, DQ13 =48, DQ14 =52, DQ15 =56
4770 10:02:09.429607
4771 10:02:09.429671
4772 10:02:09.436676 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4773 10:02:09.439762 CH1 RK1: MR19=808, MR18=6C23
4774 10:02:09.446433 CH1_RK1: MR19=0x808, MR18=0x6C23, DQSOSC=389, MR23=63, INC=173, DEC=115
4775 10:02:09.449648 [RxdqsGatingPostProcess] freq 600
4776 10:02:09.456098 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4777 10:02:09.456179 Pre-setting of DQS Precalculation
4778 10:02:09.462947 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4779 10:02:09.469556 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4780 10:02:09.476560 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4781 10:02:09.476642
4782 10:02:09.476705
4783 10:02:09.479750 [Calibration Summary] 1200 Mbps
4784 10:02:09.483066 CH 0, Rank 0
4785 10:02:09.483160 SW Impedance : PASS
4786 10:02:09.486200 DUTY Scan : NO K
4787 10:02:09.489245 ZQ Calibration : PASS
4788 10:02:09.489326 Jitter Meter : NO K
4789 10:02:09.492854 CBT Training : PASS
4790 10:02:09.492934 Write leveling : PASS
4791 10:02:09.496101 RX DQS gating : PASS
4792 10:02:09.499344 RX DQ/DQS(RDDQC) : PASS
4793 10:02:09.499425 TX DQ/DQS : PASS
4794 10:02:09.502665 RX DATLAT : PASS
4795 10:02:09.505964 RX DQ/DQS(Engine): PASS
4796 10:02:09.506074 TX OE : NO K
4797 10:02:09.509298 All Pass.
4798 10:02:09.509415
4799 10:02:09.509507 CH 0, Rank 1
4800 10:02:09.513083 SW Impedance : PASS
4801 10:02:09.513190 DUTY Scan : NO K
4802 10:02:09.516156 ZQ Calibration : PASS
4803 10:02:09.519452 Jitter Meter : NO K
4804 10:02:09.519558 CBT Training : PASS
4805 10:02:09.522535 Write leveling : PASS
4806 10:02:09.525795 RX DQS gating : PASS
4807 10:02:09.525901 RX DQ/DQS(RDDQC) : PASS
4808 10:02:09.528942 TX DQ/DQS : PASS
4809 10:02:09.532801 RX DATLAT : PASS
4810 10:02:09.532891 RX DQ/DQS(Engine): PASS
4811 10:02:09.535922 TX OE : NO K
4812 10:02:09.536014 All Pass.
4813 10:02:09.536076
4814 10:02:09.539053 CH 1, Rank 0
4815 10:02:09.539168 SW Impedance : PASS
4816 10:02:09.542798 DUTY Scan : NO K
4817 10:02:09.545696 ZQ Calibration : PASS
4818 10:02:09.545800 Jitter Meter : NO K
4819 10:02:09.548913 CBT Training : PASS
4820 10:02:09.549010 Write leveling : PASS
4821 10:02:09.552353 RX DQS gating : PASS
4822 10:02:09.555871 RX DQ/DQS(RDDQC) : PASS
4823 10:02:09.555943 TX DQ/DQS : PASS
4824 10:02:09.559182 RX DATLAT : PASS
4825 10:02:09.562292 RX DQ/DQS(Engine): PASS
4826 10:02:09.562364 TX OE : NO K
4827 10:02:09.565889 All Pass.
4828 10:02:09.565986
4829 10:02:09.566049 CH 1, Rank 1
4830 10:02:09.568975 SW Impedance : PASS
4831 10:02:09.569088 DUTY Scan : NO K
4832 10:02:09.572059 ZQ Calibration : PASS
4833 10:02:09.575747 Jitter Meter : NO K
4834 10:02:09.575853 CBT Training : PASS
4835 10:02:09.578852 Write leveling : PASS
4836 10:02:09.582069 RX DQS gating : PASS
4837 10:02:09.582150 RX DQ/DQS(RDDQC) : PASS
4838 10:02:09.585834 TX DQ/DQS : PASS
4839 10:02:09.589011 RX DATLAT : PASS
4840 10:02:09.589122 RX DQ/DQS(Engine): PASS
4841 10:02:09.592335 TX OE : NO K
4842 10:02:09.592418 All Pass.
4843 10:02:09.592484
4844 10:02:09.595481 DramC Write-DBI off
4845 10:02:09.599172 PER_BANK_REFRESH: Hybrid Mode
4846 10:02:09.599256 TX_TRACKING: ON
4847 10:02:09.609215 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4848 10:02:09.612358 [FAST_K] Save calibration result to emmc
4849 10:02:09.615487 dramc_set_vcore_voltage set vcore to 662500
4850 10:02:09.618611 Read voltage for 933, 3
4851 10:02:09.618713 Vio18 = 0
4852 10:02:09.618807 Vcore = 662500
4853 10:02:09.622471 Vdram = 0
4854 10:02:09.622604 Vddq = 0
4855 10:02:09.622695 Vmddr = 0
4856 10:02:09.628905 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4857 10:02:09.632176 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4858 10:02:09.635390 MEM_TYPE=3, freq_sel=17
4859 10:02:09.638427 sv_algorithm_assistance_LP4_1600
4860 10:02:09.642297 ============ PULL DRAM RESETB DOWN ============
4861 10:02:09.645484 ========== PULL DRAM RESETB DOWN end =========
4862 10:02:09.651984 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4863 10:02:09.655723 ===================================
4864 10:02:09.655826 LPDDR4 DRAM CONFIGURATION
4865 10:02:09.658725 ===================================
4866 10:02:09.662197 EX_ROW_EN[0] = 0x0
4867 10:02:09.665461 EX_ROW_EN[1] = 0x0
4868 10:02:09.665553 LP4Y_EN = 0x0
4869 10:02:09.668739 WORK_FSP = 0x0
4870 10:02:09.668833 WL = 0x3
4871 10:02:09.672172 RL = 0x3
4872 10:02:09.672290 BL = 0x2
4873 10:02:09.675477 RPST = 0x0
4874 10:02:09.675587 RD_PRE = 0x0
4875 10:02:09.678691 WR_PRE = 0x1
4876 10:02:09.678798 WR_PST = 0x0
4877 10:02:09.682137 DBI_WR = 0x0
4878 10:02:09.682248 DBI_RD = 0x0
4879 10:02:09.685491 OTF = 0x1
4880 10:02:09.688822 ===================================
4881 10:02:09.692049 ===================================
4882 10:02:09.692161 ANA top config
4883 10:02:09.695353 ===================================
4884 10:02:09.698689 DLL_ASYNC_EN = 0
4885 10:02:09.701976 ALL_SLAVE_EN = 1
4886 10:02:09.702057 NEW_RANK_MODE = 1
4887 10:02:09.705253 DLL_IDLE_MODE = 1
4888 10:02:09.708844 LP45_APHY_COMB_EN = 1
4889 10:02:09.711944 TX_ODT_DIS = 1
4890 10:02:09.715050 NEW_8X_MODE = 1
4891 10:02:09.718375 ===================================
4892 10:02:09.721658 ===================================
4893 10:02:09.721763 data_rate = 1866
4894 10:02:09.725013 CKR = 1
4895 10:02:09.728322 DQ_P2S_RATIO = 8
4896 10:02:09.731622 ===================================
4897 10:02:09.734961 CA_P2S_RATIO = 8
4898 10:02:09.738234 DQ_CA_OPEN = 0
4899 10:02:09.741860 DQ_SEMI_OPEN = 0
4900 10:02:09.741965 CA_SEMI_OPEN = 0
4901 10:02:09.745133 CA_FULL_RATE = 0
4902 10:02:09.748277 DQ_CKDIV4_EN = 1
4903 10:02:09.751557 CA_CKDIV4_EN = 1
4904 10:02:09.754795 CA_PREDIV_EN = 0
4905 10:02:09.758632 PH8_DLY = 0
4906 10:02:09.758712 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4907 10:02:09.761436 DQ_AAMCK_DIV = 4
4908 10:02:09.765051 CA_AAMCK_DIV = 4
4909 10:02:09.768315 CA_ADMCK_DIV = 4
4910 10:02:09.771405 DQ_TRACK_CA_EN = 0
4911 10:02:09.774565 CA_PICK = 933
4912 10:02:09.778550 CA_MCKIO = 933
4913 10:02:09.778645 MCKIO_SEMI = 0
4914 10:02:09.781709 PLL_FREQ = 3732
4915 10:02:09.784661 DQ_UI_PI_RATIO = 32
4916 10:02:09.788180 CA_UI_PI_RATIO = 0
4917 10:02:09.791783 ===================================
4918 10:02:09.794705 ===================================
4919 10:02:09.798025 memory_type:LPDDR4
4920 10:02:09.798128 GP_NUM : 10
4921 10:02:09.801389 SRAM_EN : 1
4922 10:02:09.801494 MD32_EN : 0
4923 10:02:09.805000 ===================================
4924 10:02:09.808271 [ANA_INIT] >>>>>>>>>>>>>>
4925 10:02:09.811653 <<<<<< [CONFIGURE PHASE]: ANA_TX
4926 10:02:09.814673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4927 10:02:09.817806 ===================================
4928 10:02:09.821716 data_rate = 1866,PCW = 0X8f00
4929 10:02:09.824821 ===================================
4930 10:02:09.828185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4931 10:02:09.834967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 10:02:09.838182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 10:02:09.844668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4934 10:02:09.848419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4935 10:02:09.851695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4936 10:02:09.851785 [ANA_INIT] flow start
4937 10:02:09.854944 [ANA_INIT] PLL >>>>>>>>
4938 10:02:09.858187 [ANA_INIT] PLL <<<<<<<<
4939 10:02:09.858289 [ANA_INIT] MIDPI >>>>>>>>
4940 10:02:09.861418 [ANA_INIT] MIDPI <<<<<<<<
4941 10:02:09.864623 [ANA_INIT] DLL >>>>>>>>
4942 10:02:09.864699 [ANA_INIT] flow end
4943 10:02:09.870978 ============ LP4 DIFF to SE enter ============
4944 10:02:09.874881 ============ LP4 DIFF to SE exit ============
4945 10:02:09.878036 [ANA_INIT] <<<<<<<<<<<<<
4946 10:02:09.881047 [Flow] Enable top DCM control >>>>>
4947 10:02:09.881159 [Flow] Enable top DCM control <<<<<
4948 10:02:09.884812 Enable DLL master slave shuffle
4949 10:02:09.891117 ==============================================================
4950 10:02:09.894825 Gating Mode config
4951 10:02:09.898082 ==============================================================
4952 10:02:09.901366 Config description:
4953 10:02:09.911362 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4954 10:02:09.917904 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4955 10:02:09.920927 SELPH_MODE 0: By rank 1: By Phase
4956 10:02:09.927711 ==============================================================
4957 10:02:09.930992 GAT_TRACK_EN = 1
4958 10:02:09.934601 RX_GATING_MODE = 2
4959 10:02:09.937696 RX_GATING_TRACK_MODE = 2
4960 10:02:09.937795 SELPH_MODE = 1
4961 10:02:09.940941 PICG_EARLY_EN = 1
4962 10:02:09.944180 VALID_LAT_VALUE = 1
4963 10:02:09.951259 ==============================================================
4964 10:02:09.954517 Enter into Gating configuration >>>>
4965 10:02:09.957668 Exit from Gating configuration <<<<
4966 10:02:09.960925 Enter into DVFS_PRE_config >>>>>
4967 10:02:09.970824 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4968 10:02:09.974030 Exit from DVFS_PRE_config <<<<<
4969 10:02:09.977792 Enter into PICG configuration >>>>
4970 10:02:09.980981 Exit from PICG configuration <<<<
4971 10:02:09.984161 [RX_INPUT] configuration >>>>>
4972 10:02:09.987343 [RX_INPUT] configuration <<<<<
4973 10:02:09.991075 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4974 10:02:09.997843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4975 10:02:10.004159 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 10:02:10.010626 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 10:02:10.013977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 10:02:10.020726 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 10:02:10.024290 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4980 10:02:10.030482 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4981 10:02:10.034359 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4982 10:02:10.037342 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4983 10:02:10.040798 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4984 10:02:10.047359 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 10:02:10.050637 ===================================
4986 10:02:10.053712 LPDDR4 DRAM CONFIGURATION
4987 10:02:10.057020 ===================================
4988 10:02:10.057124 EX_ROW_EN[0] = 0x0
4989 10:02:10.060881 EX_ROW_EN[1] = 0x0
4990 10:02:10.060963 LP4Y_EN = 0x0
4991 10:02:10.064066 WORK_FSP = 0x0
4992 10:02:10.064137 WL = 0x3
4993 10:02:10.067404 RL = 0x3
4994 10:02:10.067475 BL = 0x2
4995 10:02:10.070790 RPST = 0x0
4996 10:02:10.070861 RD_PRE = 0x0
4997 10:02:10.074048 WR_PRE = 0x1
4998 10:02:10.074118 WR_PST = 0x0
4999 10:02:10.077111 DBI_WR = 0x0
5000 10:02:10.077182 DBI_RD = 0x0
5001 10:02:10.080886 OTF = 0x1
5002 10:02:10.084098 ===================================
5003 10:02:10.087031 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5004 10:02:10.091009 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5005 10:02:10.097622 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 10:02:10.100798 ===================================
5007 10:02:10.100900 LPDDR4 DRAM CONFIGURATION
5008 10:02:10.103798 ===================================
5009 10:02:10.107542 EX_ROW_EN[0] = 0x10
5010 10:02:10.110769 EX_ROW_EN[1] = 0x0
5011 10:02:10.110874 LP4Y_EN = 0x0
5012 10:02:10.113946 WORK_FSP = 0x0
5013 10:02:10.114051 WL = 0x3
5014 10:02:10.117216 RL = 0x3
5015 10:02:10.117312 BL = 0x2
5016 10:02:10.120349 RPST = 0x0
5017 10:02:10.120452 RD_PRE = 0x0
5018 10:02:10.124166 WR_PRE = 0x1
5019 10:02:10.124243 WR_PST = 0x0
5020 10:02:10.127398 DBI_WR = 0x0
5021 10:02:10.127466 DBI_RD = 0x0
5022 10:02:10.130702 OTF = 0x1
5023 10:02:10.133883 ===================================
5024 10:02:10.140549 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5025 10:02:10.144081 nWR fixed to 30
5026 10:02:10.144190 [ModeRegInit_LP4] CH0 RK0
5027 10:02:10.146964 [ModeRegInit_LP4] CH0 RK1
5028 10:02:10.150333 [ModeRegInit_LP4] CH1 RK0
5029 10:02:10.153823 [ModeRegInit_LP4] CH1 RK1
5030 10:02:10.153937 match AC timing 9
5031 10:02:10.157359 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5032 10:02:10.163688 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5033 10:02:10.166817 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5034 10:02:10.173811 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5035 10:02:10.177006 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5036 10:02:10.177089 ==
5037 10:02:10.180382 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 10:02:10.183569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 10:02:10.183662 ==
5040 10:02:10.190451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 10:02:10.196665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5042 10:02:10.199946 [CA 0] Center 37 (6~68) winsize 63
5043 10:02:10.203803 [CA 1] Center 37 (7~68) winsize 62
5044 10:02:10.207006 [CA 2] Center 34 (4~65) winsize 62
5045 10:02:10.210098 [CA 3] Center 34 (3~65) winsize 63
5046 10:02:10.213819 [CA 4] Center 33 (3~64) winsize 62
5047 10:02:10.217031 [CA 5] Center 32 (2~62) winsize 61
5048 10:02:10.217111
5049 10:02:10.220358 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5050 10:02:10.220438
5051 10:02:10.223576 [CATrainingPosCal] consider 1 rank data
5052 10:02:10.226689 u2DelayCellTimex100 = 270/100 ps
5053 10:02:10.230570 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5054 10:02:10.233712 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5055 10:02:10.236940 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5056 10:02:10.240203 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5057 10:02:10.243440 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5058 10:02:10.246624 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5059 10:02:10.246725
5060 10:02:10.250402 CA PerBit enable=1, Macro0, CA PI delay=32
5061 10:02:10.250501
5062 10:02:10.253977 [CBTSetCACLKResult] CA Dly = 32
5063 10:02:10.256792 CS Dly: 5 (0~36)
5064 10:02:10.256891 ==
5065 10:02:10.260412 Dram Type= 6, Freq= 0, CH_0, rank 1
5066 10:02:10.263554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 10:02:10.263678 ==
5068 10:02:10.270386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 10:02:10.276711 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5070 10:02:10.280296 [CA 0] Center 37 (7~68) winsize 62
5071 10:02:10.283571 [CA 1] Center 37 (7~68) winsize 62
5072 10:02:10.286695 [CA 2] Center 34 (4~65) winsize 62
5073 10:02:10.290021 [CA 3] Center 34 (4~65) winsize 62
5074 10:02:10.293353 [CA 4] Center 33 (3~63) winsize 61
5075 10:02:10.297193 [CA 5] Center 32 (2~62) winsize 61
5076 10:02:10.297273
5077 10:02:10.300320 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5078 10:02:10.300401
5079 10:02:10.303537 [CATrainingPosCal] consider 2 rank data
5080 10:02:10.306711 u2DelayCellTimex100 = 270/100 ps
5081 10:02:10.310463 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5082 10:02:10.313730 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5083 10:02:10.316643 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5084 10:02:10.320440 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5085 10:02:10.323585 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5086 10:02:10.327031 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5087 10:02:10.327117
5088 10:02:10.333287 CA PerBit enable=1, Macro0, CA PI delay=32
5089 10:02:10.333370
5090 10:02:10.333454 [CBTSetCACLKResult] CA Dly = 32
5091 10:02:10.337131 CS Dly: 5 (0~37)
5092 10:02:10.337213
5093 10:02:10.340390 ----->DramcWriteLeveling(PI) begin...
5094 10:02:10.340474 ==
5095 10:02:10.343769 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 10:02:10.347011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 10:02:10.347094 ==
5098 10:02:10.350401 Write leveling (Byte 0): 32 => 32
5099 10:02:10.353519 Write leveling (Byte 1): 30 => 30
5100 10:02:10.356919 DramcWriteLeveling(PI) end<-----
5101 10:02:10.357008
5102 10:02:10.357090 ==
5103 10:02:10.360062 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 10:02:10.363201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 10:02:10.366727 ==
5106 10:02:10.366810 [Gating] SW mode calibration
5107 10:02:10.373689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 10:02:10.379902 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5109 10:02:10.383417 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5110 10:02:10.389978 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 10:02:10.393684 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 10:02:10.396807 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 10:02:10.403444 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 10:02:10.407121 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 10:02:10.410372 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5116 10:02:10.413976 0 14 28 | B1->B0 | 3333 2525 | 1 0 | (1 1) (1 0)
5117 10:02:10.420524 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
5118 10:02:10.423479 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 10:02:10.427137 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 10:02:10.433333 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 10:02:10.436676 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 10:02:10.440484 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 10:02:10.446484 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5124 10:02:10.449788 0 15 28 | B1->B0 | 2323 3e3d | 0 1 | (0 0) (0 0)
5125 10:02:10.453621 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5126 10:02:10.459968 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 10:02:10.463203 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 10:02:10.466535 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 10:02:10.473348 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 10:02:10.476931 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 10:02:10.480023 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 10:02:10.486535 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5133 10:02:10.489553 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5134 10:02:10.493358 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 10:02:10.499553 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 10:02:10.503271 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 10:02:10.506423 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 10:02:10.513393 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 10:02:10.516628 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 10:02:10.519753 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 10:02:10.526427 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 10:02:10.529987 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 10:02:10.533138 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 10:02:10.540082 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 10:02:10.543227 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 10:02:10.546452 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 10:02:10.552849 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 10:02:10.556038 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5149 10:02:10.559681 Total UI for P1: 0, mck2ui 16
5150 10:02:10.562866 best dqsien dly found for B0: ( 1, 2, 24)
5151 10:02:10.566167 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5152 10:02:10.569935 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 10:02:10.573160 Total UI for P1: 0, mck2ui 16
5154 10:02:10.576446 best dqsien dly found for B1: ( 1, 2, 30)
5155 10:02:10.579717 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5156 10:02:10.583332 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5157 10:02:10.586437
5158 10:02:10.589491 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5159 10:02:10.593244 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5160 10:02:10.596439 [Gating] SW calibration Done
5161 10:02:10.596514 ==
5162 10:02:10.599698 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 10:02:10.602779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 10:02:10.602881 ==
5165 10:02:10.602976 RX Vref Scan: 0
5166 10:02:10.603051
5167 10:02:10.606572 RX Vref 0 -> 0, step: 1
5168 10:02:10.606677
5169 10:02:10.609702 RX Delay -80 -> 252, step: 8
5170 10:02:10.612855 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5171 10:02:10.616635 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5172 10:02:10.622906 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5173 10:02:10.626033 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5174 10:02:10.629328 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5175 10:02:10.632628 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5176 10:02:10.636389 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5177 10:02:10.639512 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5178 10:02:10.645979 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5179 10:02:10.649812 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5180 10:02:10.652990 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5181 10:02:10.656279 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5182 10:02:10.659551 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5183 10:02:10.662734 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5184 10:02:10.669728 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5185 10:02:10.672990 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5186 10:02:10.673067 ==
5187 10:02:10.676305 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 10:02:10.679491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 10:02:10.679589 ==
5190 10:02:10.679689 DQS Delay:
5191 10:02:10.682815 DQS0 = 0, DQS1 = 0
5192 10:02:10.682911 DQM Delay:
5193 10:02:10.686119 DQM0 = 103, DQM1 = 95
5194 10:02:10.686222 DQ Delay:
5195 10:02:10.689280 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5196 10:02:10.692705 DQ4 =103, DQ5 =91, DQ6 =115, DQ7 =115
5197 10:02:10.695822 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5198 10:02:10.698969 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5199 10:02:10.699102
5200 10:02:10.699228
5201 10:02:10.702810 ==
5202 10:02:10.702912 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 10:02:10.709066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 10:02:10.709147 ==
5205 10:02:10.709220
5206 10:02:10.709281
5207 10:02:10.712120 TX Vref Scan disable
5208 10:02:10.712218 == TX Byte 0 ==
5209 10:02:10.715891 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5210 10:02:10.722361 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5211 10:02:10.722447 == TX Byte 1 ==
5212 10:02:10.725382 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5213 10:02:10.732189 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5214 10:02:10.732290 ==
5215 10:02:10.735367 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 10:02:10.739260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 10:02:10.739358 ==
5218 10:02:10.739447
5219 10:02:10.739537
5220 10:02:10.742548 TX Vref Scan disable
5221 10:02:10.745672 == TX Byte 0 ==
5222 10:02:10.748889 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5223 10:02:10.752328 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5224 10:02:10.755851 == TX Byte 1 ==
5225 10:02:10.759138 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5226 10:02:10.762390 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5227 10:02:10.762502
5228 10:02:10.762594 [DATLAT]
5229 10:02:10.765555 Freq=933, CH0 RK0
5230 10:02:10.765650
5231 10:02:10.768811 DATLAT Default: 0xd
5232 10:02:10.768886 0, 0xFFFF, sum = 0
5233 10:02:10.772477 1, 0xFFFF, sum = 0
5234 10:02:10.772568 2, 0xFFFF, sum = 0
5235 10:02:10.775493 3, 0xFFFF, sum = 0
5236 10:02:10.775615 4, 0xFFFF, sum = 0
5237 10:02:10.778706 5, 0xFFFF, sum = 0
5238 10:02:10.778814 6, 0xFFFF, sum = 0
5239 10:02:10.782050 7, 0xFFFF, sum = 0
5240 10:02:10.782125 8, 0xFFFF, sum = 0
5241 10:02:10.785383 9, 0xFFFF, sum = 0
5242 10:02:10.785499 10, 0x0, sum = 1
5243 10:02:10.788800 11, 0x0, sum = 2
5244 10:02:10.788916 12, 0x0, sum = 3
5245 10:02:10.791939 13, 0x0, sum = 4
5246 10:02:10.792040 best_step = 11
5247 10:02:10.792129
5248 10:02:10.792226 ==
5249 10:02:10.795731 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 10:02:10.798704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 10:02:10.798810 ==
5252 10:02:10.802318 RX Vref Scan: 1
5253 10:02:10.802421
5254 10:02:10.805325 RX Vref 0 -> 0, step: 1
5255 10:02:10.805427
5256 10:02:10.805525 RX Delay -45 -> 252, step: 4
5257 10:02:10.805614
5258 10:02:10.808886 Set Vref, RX VrefLevel [Byte0]: 55
5259 10:02:10.812080 [Byte1]: 49
5260 10:02:10.817072
5261 10:02:10.817149 Final RX Vref Byte 0 = 55 to rank0
5262 10:02:10.820130 Final RX Vref Byte 1 = 49 to rank0
5263 10:02:10.823377 Final RX Vref Byte 0 = 55 to rank1
5264 10:02:10.826555 Final RX Vref Byte 1 = 49 to rank1==
5265 10:02:10.830287 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 10:02:10.836585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 10:02:10.836690 ==
5268 10:02:10.836788 DQS Delay:
5269 10:02:10.836878 DQS0 = 0, DQS1 = 0
5270 10:02:10.840183 DQM Delay:
5271 10:02:10.840291 DQM0 = 104, DQM1 = 95
5272 10:02:10.843281 DQ Delay:
5273 10:02:10.847033 DQ0 =104, DQ1 =104, DQ2 =104, DQ3 =104
5274 10:02:10.850243 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5275 10:02:10.853569 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =90
5276 10:02:10.856676 DQ12 =100, DQ13 =98, DQ14 =108, DQ15 =102
5277 10:02:10.856781
5278 10:02:10.856873
5279 10:02:10.863226 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5280 10:02:10.866552 CH0 RK0: MR19=505, MR18=322A
5281 10:02:10.873693 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5282 10:02:10.873796
5283 10:02:10.876882 ----->DramcWriteLeveling(PI) begin...
5284 10:02:10.876998 ==
5285 10:02:10.880009 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 10:02:10.883274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 10:02:10.883375 ==
5288 10:02:10.886586 Write leveling (Byte 0): 33 => 33
5289 10:02:10.889919 Write leveling (Byte 1): 30 => 30
5290 10:02:10.893266 DramcWriteLeveling(PI) end<-----
5291 10:02:10.893371
5292 10:02:10.893463 ==
5293 10:02:10.896607 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 10:02:10.903128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 10:02:10.903233 ==
5296 10:02:10.903328 [Gating] SW mode calibration
5297 10:02:10.913166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5298 10:02:10.916276 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5299 10:02:10.920015 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5300 10:02:10.926150 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 10:02:10.929956 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 10:02:10.933200 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 10:02:10.939946 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 10:02:10.943137 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 10:02:10.946284 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 10:02:10.952980 0 14 28 | B1->B0 | 2929 2c2c | 0 0 | (0 0) (0 1)
5307 10:02:10.956263 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 0)
5308 10:02:10.959720 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 10:02:10.966568 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 10:02:10.969602 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 10:02:10.973365 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 10:02:10.979691 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 10:02:10.982926 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5314 10:02:10.986666 0 15 28 | B1->B0 | 3838 3737 | 0 0 | (0 0) (0 0)
5315 10:02:10.993266 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5316 10:02:10.996560 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 10:02:10.999685 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 10:02:11.002965 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 10:02:11.009560 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 10:02:11.013235 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 10:02:11.016406 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 10:02:11.023269 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5323 10:02:11.026140 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5324 10:02:11.029627 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 10:02:11.036374 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 10:02:11.039513 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 10:02:11.042793 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 10:02:11.049676 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 10:02:11.052797 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 10:02:11.056386 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 10:02:11.062811 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 10:02:11.066435 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 10:02:11.069772 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 10:02:11.076192 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 10:02:11.079561 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 10:02:11.082496 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 10:02:11.089455 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 10:02:11.092712 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5339 10:02:11.096006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5340 10:02:11.099143 Total UI for P1: 0, mck2ui 16
5341 10:02:11.102373 best dqsien dly found for B1: ( 1, 2, 28)
5342 10:02:11.109167 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 10:02:11.109275 Total UI for P1: 0, mck2ui 16
5344 10:02:11.116005 best dqsien dly found for B0: ( 1, 2, 30)
5345 10:02:11.119245 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5346 10:02:11.122767 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5347 10:02:11.122840
5348 10:02:11.126070 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5349 10:02:11.129216 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5350 10:02:11.132406 [Gating] SW calibration Done
5351 10:02:11.132486 ==
5352 10:02:11.135518 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 10:02:11.139232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 10:02:11.139313 ==
5355 10:02:11.142519 RX Vref Scan: 0
5356 10:02:11.142599
5357 10:02:11.142662 RX Vref 0 -> 0, step: 1
5358 10:02:11.142721
5359 10:02:11.145424 RX Delay -80 -> 252, step: 8
5360 10:02:11.149090 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5361 10:02:11.155844 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5362 10:02:11.159159 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5363 10:02:11.162161 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5364 10:02:11.165657 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5365 10:02:11.168533 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5366 10:02:11.175480 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5367 10:02:11.178619 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5368 10:02:11.181869 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5369 10:02:11.185604 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5370 10:02:11.188603 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5371 10:02:11.192215 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5372 10:02:11.195452 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5373 10:02:11.202014 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5374 10:02:11.205175 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5375 10:02:11.209092 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5376 10:02:11.209172 ==
5377 10:02:11.212305 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 10:02:11.215548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 10:02:11.215667 ==
5380 10:02:11.218748 DQS Delay:
5381 10:02:11.218830 DQS0 = 0, DQS1 = 0
5382 10:02:11.222380 DQM Delay:
5383 10:02:11.222465 DQM0 = 106, DQM1 = 94
5384 10:02:11.222551 DQ Delay:
5385 10:02:11.225471 DQ0 =107, DQ1 =111, DQ2 =103, DQ3 =99
5386 10:02:11.228590 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5387 10:02:11.231954 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5388 10:02:11.238810 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5389 10:02:11.238893
5390 10:02:11.238977
5391 10:02:11.239057 ==
5392 10:02:11.242041 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 10:02:11.245373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 10:02:11.245461 ==
5395 10:02:11.245545
5396 10:02:11.245633
5397 10:02:11.248464 TX Vref Scan disable
5398 10:02:11.248547 == TX Byte 0 ==
5399 10:02:11.255414 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5400 10:02:11.258509 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5401 10:02:11.258593 == TX Byte 1 ==
5402 10:02:11.265548 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5403 10:02:11.268878 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5404 10:02:11.268960 ==
5405 10:02:11.271873 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 10:02:11.274911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 10:02:11.274994 ==
5408 10:02:11.275078
5409 10:02:11.275157
5410 10:02:11.278539 TX Vref Scan disable
5411 10:02:11.282153 == TX Byte 0 ==
5412 10:02:11.285429 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5413 10:02:11.288735 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5414 10:02:11.291806 == TX Byte 1 ==
5415 10:02:11.294953 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5416 10:02:11.298424 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5417 10:02:11.298507
5418 10:02:11.301895 [DATLAT]
5419 10:02:11.301976 Freq=933, CH0 RK1
5420 10:02:11.302061
5421 10:02:11.305131 DATLAT Default: 0xb
5422 10:02:11.305214 0, 0xFFFF, sum = 0
5423 10:02:11.308380 1, 0xFFFF, sum = 0
5424 10:02:11.308464 2, 0xFFFF, sum = 0
5425 10:02:11.312217 3, 0xFFFF, sum = 0
5426 10:02:11.312301 4, 0xFFFF, sum = 0
5427 10:02:11.315456 5, 0xFFFF, sum = 0
5428 10:02:11.315540 6, 0xFFFF, sum = 0
5429 10:02:11.318639 7, 0xFFFF, sum = 0
5430 10:02:11.318740 8, 0xFFFF, sum = 0
5431 10:02:11.322019 9, 0xFFFF, sum = 0
5432 10:02:11.322135 10, 0x0, sum = 1
5433 10:02:11.325161 11, 0x0, sum = 2
5434 10:02:11.325277 12, 0x0, sum = 3
5435 10:02:11.328161 13, 0x0, sum = 4
5436 10:02:11.328266 best_step = 11
5437 10:02:11.328339
5438 10:02:11.328413 ==
5439 10:02:11.331979 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 10:02:11.338471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 10:02:11.338553 ==
5442 10:02:11.338633 RX Vref Scan: 0
5443 10:02:11.338706
5444 10:02:11.341513 RX Vref 0 -> 0, step: 1
5445 10:02:11.341593
5446 10:02:11.345383 RX Delay -45 -> 252, step: 4
5447 10:02:11.348540 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5448 10:02:11.351641 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5449 10:02:11.358675 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5450 10:02:11.361844 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5451 10:02:11.364982 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5452 10:02:11.368465 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5453 10:02:11.371633 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5454 10:02:11.378604 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5455 10:02:11.381768 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5456 10:02:11.385434 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5457 10:02:11.388594 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5458 10:02:11.391726 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5459 10:02:11.394937 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5460 10:02:11.401498 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5461 10:02:11.405087 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5462 10:02:11.408019 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5463 10:02:11.408102 ==
5464 10:02:11.411613 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 10:02:11.415338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 10:02:11.415418 ==
5467 10:02:11.418755 DQS Delay:
5468 10:02:11.418834 DQS0 = 0, DQS1 = 0
5469 10:02:11.422039 DQM Delay:
5470 10:02:11.422119 DQM0 = 105, DQM1 = 94
5471 10:02:11.422182 DQ Delay:
5472 10:02:11.428404 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5473 10:02:11.431491 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5474 10:02:11.435123 DQ8 =84, DQ9 =86, DQ10 =94, DQ11 =90
5475 10:02:11.438346 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5476 10:02:11.438426
5477 10:02:11.438489
5478 10:02:11.444659 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5479 10:02:11.448339 CH0 RK1: MR19=505, MR18=2A02
5480 10:02:11.454680 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5481 10:02:11.458428 [RxdqsGatingPostProcess] freq 933
5482 10:02:11.461682 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5483 10:02:11.465063 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 10:02:11.468401 best DQS1 dly(2T, 0.5T) = (0, 10)
5485 10:02:11.471754 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 10:02:11.474813 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5487 10:02:11.478367 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 10:02:11.482031 best DQS1 dly(2T, 0.5T) = (0, 10)
5489 10:02:11.485113 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 10:02:11.488313 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5491 10:02:11.491347 Pre-setting of DQS Precalculation
5492 10:02:11.494696 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5493 10:02:11.494809 ==
5494 10:02:11.498204 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 10:02:11.504725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 10:02:11.504822 ==
5497 10:02:11.507899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 10:02:11.514665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5499 10:02:11.517733 [CA 0] Center 36 (6~67) winsize 62
5500 10:02:11.521408 [CA 1] Center 37 (6~68) winsize 63
5501 10:02:11.524612 [CA 2] Center 34 (4~65) winsize 62
5502 10:02:11.527752 [CA 3] Center 34 (4~65) winsize 62
5503 10:02:11.531010 [CA 4] Center 34 (4~65) winsize 62
5504 10:02:11.534207 [CA 5] Center 33 (3~64) winsize 62
5505 10:02:11.534290
5506 10:02:11.537767 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5507 10:02:11.537852
5508 10:02:11.540961 [CATrainingPosCal] consider 1 rank data
5509 10:02:11.544324 u2DelayCellTimex100 = 270/100 ps
5510 10:02:11.547585 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5511 10:02:11.554466 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5512 10:02:11.557804 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5513 10:02:11.561072 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5514 10:02:11.564191 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5515 10:02:11.567447 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5516 10:02:11.567564
5517 10:02:11.570846 CA PerBit enable=1, Macro0, CA PI delay=33
5518 10:02:11.571000
5519 10:02:11.574132 [CBTSetCACLKResult] CA Dly = 33
5520 10:02:11.577216 CS Dly: 6 (0~37)
5521 10:02:11.577296 ==
5522 10:02:11.580762 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 10:02:11.584336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 10:02:11.584416 ==
5525 10:02:11.590627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 10:02:11.594119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5527 10:02:11.598044 [CA 0] Center 36 (6~67) winsize 62
5528 10:02:11.601671 [CA 1] Center 37 (6~68) winsize 63
5529 10:02:11.604825 [CA 2] Center 35 (4~66) winsize 63
5530 10:02:11.607833 [CA 3] Center 34 (4~65) winsize 62
5531 10:02:11.611053 [CA 4] Center 34 (4~65) winsize 62
5532 10:02:11.614914 [CA 5] Center 34 (4~64) winsize 61
5533 10:02:11.614996
5534 10:02:11.618065 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5535 10:02:11.618147
5536 10:02:11.621198 [CATrainingPosCal] consider 2 rank data
5537 10:02:11.624369 u2DelayCellTimex100 = 270/100 ps
5538 10:02:11.627915 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5539 10:02:11.631210 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5540 10:02:11.637605 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5541 10:02:11.641388 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5542 10:02:11.644574 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5543 10:02:11.647800 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5544 10:02:11.647881
5545 10:02:11.650949 CA PerBit enable=1, Macro0, CA PI delay=34
5546 10:02:11.651031
5547 10:02:11.654573 [CBTSetCACLKResult] CA Dly = 34
5548 10:02:11.654654 CS Dly: 7 (0~40)
5549 10:02:11.657818
5550 10:02:11.660813 ----->DramcWriteLeveling(PI) begin...
5551 10:02:11.660897 ==
5552 10:02:11.664664 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 10:02:11.667645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 10:02:11.667727 ==
5555 10:02:11.670837 Write leveling (Byte 0): 30 => 30
5556 10:02:11.674106 Write leveling (Byte 1): 26 => 26
5557 10:02:11.677961 DramcWriteLeveling(PI) end<-----
5558 10:02:11.678042
5559 10:02:11.678115 ==
5560 10:02:11.681124 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 10:02:11.684408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 10:02:11.684490 ==
5563 10:02:11.687587 [Gating] SW mode calibration
5564 10:02:11.694702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5565 10:02:11.700997 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5566 10:02:11.704626 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 10:02:11.707800 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 10:02:11.714283 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 10:02:11.717531 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 10:02:11.720836 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 10:02:11.724274 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5572 10:02:11.730875 0 14 24 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
5573 10:02:11.734588 0 14 28 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
5574 10:02:11.737373 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 10:02:11.744152 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 10:02:11.747851 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 10:02:11.751129 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 10:02:11.757481 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 10:02:11.761276 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 10:02:11.764463 0 15 24 | B1->B0 | 2626 3333 | 0 1 | (0 0) (0 0)
5581 10:02:11.770900 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 10:02:11.773993 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 10:02:11.777373 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 10:02:11.783937 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 10:02:11.787724 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 10:02:11.790866 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 10:02:11.797461 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 10:02:11.800783 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5589 10:02:11.803923 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 10:02:11.810896 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 10:02:11.813989 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 10:02:11.817284 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 10:02:11.820620 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 10:02:11.827397 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 10:02:11.831046 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 10:02:11.833972 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 10:02:11.840546 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 10:02:11.844421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 10:02:11.847448 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 10:02:11.854034 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 10:02:11.857211 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 10:02:11.860626 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 10:02:11.867114 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5604 10:02:11.870543 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5605 10:02:11.874123 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 10:02:11.877297 Total UI for P1: 0, mck2ui 16
5607 10:02:11.880662 best dqsien dly found for B0: ( 1, 2, 22)
5608 10:02:11.883961 Total UI for P1: 0, mck2ui 16
5609 10:02:11.887176 best dqsien dly found for B1: ( 1, 2, 24)
5610 10:02:11.890418 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5611 10:02:11.893700 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5612 10:02:11.896934
5613 10:02:11.900105 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5614 10:02:11.903369 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5615 10:02:11.906535 [Gating] SW calibration Done
5616 10:02:11.906641 ==
5617 10:02:11.909946 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 10:02:11.913694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 10:02:11.913778 ==
5620 10:02:11.913861 RX Vref Scan: 0
5621 10:02:11.916948
5622 10:02:11.917030 RX Vref 0 -> 0, step: 1
5623 10:02:11.917114
5624 10:02:11.920204 RX Delay -80 -> 252, step: 8
5625 10:02:11.923411 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5626 10:02:11.926742 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5627 10:02:11.933074 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5628 10:02:11.936940 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5629 10:02:11.940166 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5630 10:02:11.943470 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5631 10:02:11.946492 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5632 10:02:11.949824 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5633 10:02:11.956502 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5634 10:02:11.959960 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5635 10:02:11.963027 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5636 10:02:11.966632 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5637 10:02:11.969530 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5638 10:02:11.976098 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5639 10:02:11.979833 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5640 10:02:11.983064 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5641 10:02:11.983147 ==
5642 10:02:11.986062 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 10:02:11.989550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 10:02:11.989633 ==
5645 10:02:11.992798 DQS Delay:
5646 10:02:11.992881 DQS0 = 0, DQS1 = 0
5647 10:02:11.996322 DQM Delay:
5648 10:02:11.996404 DQM0 = 102, DQM1 = 98
5649 10:02:11.996489 DQ Delay:
5650 10:02:11.999797 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5651 10:02:12.003010 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5652 10:02:12.006220 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5653 10:02:12.012605 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5654 10:02:12.012687
5655 10:02:12.012772
5656 10:02:12.012851 ==
5657 10:02:12.015835 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 10:02:12.019623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 10:02:12.019721 ==
5660 10:02:12.019805
5661 10:02:12.019884
5662 10:02:12.022920 TX Vref Scan disable
5663 10:02:12.023026 == TX Byte 0 ==
5664 10:02:12.029365 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5665 10:02:12.032490 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5666 10:02:12.032574 == TX Byte 1 ==
5667 10:02:12.039640 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5668 10:02:12.042912 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5669 10:02:12.042995 ==
5670 10:02:12.046246 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 10:02:12.049467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 10:02:12.049551 ==
5673 10:02:12.049635
5674 10:02:12.049714
5675 10:02:12.052563 TX Vref Scan disable
5676 10:02:12.055685 == TX Byte 0 ==
5677 10:02:12.059481 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5678 10:02:12.062671 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5679 10:02:12.066168 == TX Byte 1 ==
5680 10:02:12.069429 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5681 10:02:12.072506 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5682 10:02:12.072589
5683 10:02:12.075766 [DATLAT]
5684 10:02:12.075848 Freq=933, CH1 RK0
5685 10:02:12.075933
5686 10:02:12.079719 DATLAT Default: 0xd
5687 10:02:12.079812 0, 0xFFFF, sum = 0
5688 10:02:12.082896 1, 0xFFFF, sum = 0
5689 10:02:12.082980 2, 0xFFFF, sum = 0
5690 10:02:12.085972 3, 0xFFFF, sum = 0
5691 10:02:12.086056 4, 0xFFFF, sum = 0
5692 10:02:12.089292 5, 0xFFFF, sum = 0
5693 10:02:12.089376 6, 0xFFFF, sum = 0
5694 10:02:12.092368 7, 0xFFFF, sum = 0
5695 10:02:12.092452 8, 0xFFFF, sum = 0
5696 10:02:12.096017 9, 0xFFFF, sum = 0
5697 10:02:12.096101 10, 0x0, sum = 1
5698 10:02:12.099021 11, 0x0, sum = 2
5699 10:02:12.099105 12, 0x0, sum = 3
5700 10:02:12.102387 13, 0x0, sum = 4
5701 10:02:12.102471 best_step = 11
5702 10:02:12.102556
5703 10:02:12.102635 ==
5704 10:02:12.105875 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 10:02:12.112548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 10:02:12.112745 ==
5707 10:02:12.112840 RX Vref Scan: 1
5708 10:02:12.112943
5709 10:02:12.115814 RX Vref 0 -> 0, step: 1
5710 10:02:12.115916
5711 10:02:12.119091 RX Delay -45 -> 252, step: 4
5712 10:02:12.119189
5713 10:02:12.122173 Set Vref, RX VrefLevel [Byte0]: 53
5714 10:02:12.125894 [Byte1]: 51
5715 10:02:12.126004
5716 10:02:12.129350 Final RX Vref Byte 0 = 53 to rank0
5717 10:02:12.132486 Final RX Vref Byte 1 = 51 to rank0
5718 10:02:12.135697 Final RX Vref Byte 0 = 53 to rank1
5719 10:02:12.138708 Final RX Vref Byte 1 = 51 to rank1==
5720 10:02:12.142584 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 10:02:12.145741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 10:02:12.145820 ==
5723 10:02:12.149052 DQS Delay:
5724 10:02:12.149134 DQS0 = 0, DQS1 = 0
5725 10:02:12.149217 DQM Delay:
5726 10:02:12.152183 DQM0 = 103, DQM1 = 99
5727 10:02:12.152268 DQ Delay:
5728 10:02:12.155400 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5729 10:02:12.158696 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5730 10:02:12.162574 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5731 10:02:12.165695 DQ12 =106, DQ13 =106, DQ14 =108, DQ15 =108
5732 10:02:12.165777
5733 10:02:12.168828
5734 10:02:12.175279 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5735 10:02:12.178932 CH1 RK0: MR19=505, MR18=1C33
5736 10:02:12.185650 CH1_RK0: MR19=0x505, MR18=0x1C33, DQSOSC=405, MR23=63, INC=66, DEC=44
5737 10:02:12.185734
5738 10:02:12.188739 ----->DramcWriteLeveling(PI) begin...
5739 10:02:12.188823 ==
5740 10:02:12.191983 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 10:02:12.195175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 10:02:12.195277 ==
5743 10:02:12.199013 Write leveling (Byte 0): 25 => 25
5744 10:02:12.202233 Write leveling (Byte 1): 29 => 29
5745 10:02:12.205420 DramcWriteLeveling(PI) end<-----
5746 10:02:12.205523
5747 10:02:12.205615 ==
5748 10:02:12.208621 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 10:02:12.211802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 10:02:12.211902 ==
5751 10:02:12.215575 [Gating] SW mode calibration
5752 10:02:12.221538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5753 10:02:12.228479 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5754 10:02:12.232068 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 10:02:12.235171 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 10:02:12.242015 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 10:02:12.245170 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 10:02:12.248423 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 10:02:12.255215 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 10:02:12.258373 0 14 24 | B1->B0 | 2e2e 3131 | 1 1 | (1 1) (1 1)
5761 10:02:12.261705 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
5762 10:02:12.268842 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 10:02:12.271835 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 10:02:12.274973 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 10:02:12.281348 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 10:02:12.285075 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 10:02:12.288383 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 10:02:12.294734 0 15 24 | B1->B0 | 3c3c 2929 | 0 1 | (0 0) (0 0)
5769 10:02:12.297907 0 15 28 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
5770 10:02:12.301814 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 10:02:12.308370 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 10:02:12.311466 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 10:02:12.314544 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 10:02:12.321562 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 10:02:12.324689 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 10:02:12.328141 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5777 10:02:12.334934 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5778 10:02:12.338001 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 10:02:12.341370 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 10:02:12.345033 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 10:02:12.351604 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 10:02:12.354926 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 10:02:12.358410 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 10:02:12.365151 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 10:02:12.368474 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 10:02:12.371686 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 10:02:12.378170 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 10:02:12.381361 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 10:02:12.384587 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 10:02:12.391447 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 10:02:12.394644 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 10:02:12.397762 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5793 10:02:12.404751 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 10:02:12.404857 Total UI for P1: 0, mck2ui 16
5795 10:02:12.411073 best dqsien dly found for B0: ( 1, 2, 24)
5796 10:02:12.411157 Total UI for P1: 0, mck2ui 16
5797 10:02:12.417565 best dqsien dly found for B1: ( 1, 2, 24)
5798 10:02:12.420883 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5799 10:02:12.424123 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5800 10:02:12.424206
5801 10:02:12.427468 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5802 10:02:12.430694 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5803 10:02:12.434450 [Gating] SW calibration Done
5804 10:02:12.434532 ==
5805 10:02:12.437541 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 10:02:12.440914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 10:02:12.441029 ==
5808 10:02:12.444138 RX Vref Scan: 0
5809 10:02:12.444221
5810 10:02:12.444305 RX Vref 0 -> 0, step: 1
5811 10:02:12.444401
5812 10:02:12.447384 RX Delay -80 -> 252, step: 8
5813 10:02:12.453968 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5814 10:02:12.457833 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5815 10:02:12.460914 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5816 10:02:12.463856 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5817 10:02:12.467476 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5818 10:02:12.471091 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5819 10:02:12.477306 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5820 10:02:12.480794 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5821 10:02:12.484209 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5822 10:02:12.487272 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5823 10:02:12.490302 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5824 10:02:12.494225 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5825 10:02:12.500704 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5826 10:02:12.503774 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5827 10:02:12.507376 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5828 10:02:12.510639 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5829 10:02:12.510721 ==
5830 10:02:12.513746 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 10:02:12.520384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 10:02:12.520467 ==
5833 10:02:12.520553 DQS Delay:
5834 10:02:12.524005 DQS0 = 0, DQS1 = 0
5835 10:02:12.524087 DQM Delay:
5836 10:02:12.527159 DQM0 = 104, DQM1 = 98
5837 10:02:12.527244 DQ Delay:
5838 10:02:12.530481 DQ0 =107, DQ1 =103, DQ2 =87, DQ3 =103
5839 10:02:12.533698 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5840 10:02:12.536948 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5841 10:02:12.540203 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5842 10:02:12.540279
5843 10:02:12.540359
5844 10:02:12.540465 ==
5845 10:02:12.543746 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 10:02:12.547352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 10:02:12.547447 ==
5848 10:02:12.550311
5849 10:02:12.550425
5850 10:02:12.550524 TX Vref Scan disable
5851 10:02:12.553549 == TX Byte 0 ==
5852 10:02:12.557393 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5853 10:02:12.560546 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5854 10:02:12.563755 == TX Byte 1 ==
5855 10:02:12.566877 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5856 10:02:12.570707 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5857 10:02:12.570791 ==
5858 10:02:12.573751 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 10:02:12.580094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 10:02:12.580178 ==
5861 10:02:12.580263
5862 10:02:12.580343
5863 10:02:12.580420 TX Vref Scan disable
5864 10:02:12.584490 == TX Byte 0 ==
5865 10:02:12.588157 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5866 10:02:12.591441 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5867 10:02:12.594794 == TX Byte 1 ==
5868 10:02:12.597636 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5869 10:02:12.604522 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5870 10:02:12.604605
5871 10:02:12.604689 [DATLAT]
5872 10:02:12.604769 Freq=933, CH1 RK1
5873 10:02:12.604848
5874 10:02:12.607486 DATLAT Default: 0xb
5875 10:02:12.607610 0, 0xFFFF, sum = 0
5876 10:02:12.611112 1, 0xFFFF, sum = 0
5877 10:02:12.611196 2, 0xFFFF, sum = 0
5878 10:02:12.614208 3, 0xFFFF, sum = 0
5879 10:02:12.617428 4, 0xFFFF, sum = 0
5880 10:02:12.617544 5, 0xFFFF, sum = 0
5881 10:02:12.620735 6, 0xFFFF, sum = 0
5882 10:02:12.620819 7, 0xFFFF, sum = 0
5883 10:02:12.624647 8, 0xFFFF, sum = 0
5884 10:02:12.624755 9, 0xFFFF, sum = 0
5885 10:02:12.627918 10, 0x0, sum = 1
5886 10:02:12.628002 11, 0x0, sum = 2
5887 10:02:12.631080 12, 0x0, sum = 3
5888 10:02:12.631156 13, 0x0, sum = 4
5889 10:02:12.631253 best_step = 11
5890 10:02:12.631348
5891 10:02:12.634276 ==
5892 10:02:12.637599 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 10:02:12.640853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 10:02:12.640992 ==
5895 10:02:12.641147 RX Vref Scan: 0
5896 10:02:12.641268
5897 10:02:12.644011 RX Vref 0 -> 0, step: 1
5898 10:02:12.644091
5899 10:02:12.647215 RX Delay -45 -> 252, step: 4
5900 10:02:12.651152 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5901 10:02:12.657767 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5902 10:02:12.660944 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5903 10:02:12.664155 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5904 10:02:12.667381 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5905 10:02:12.670560 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5906 10:02:12.677411 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5907 10:02:12.680599 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5908 10:02:12.684218 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5909 10:02:12.687495 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5910 10:02:12.690689 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5911 10:02:12.694384 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5912 10:02:12.700629 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5913 10:02:12.704244 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5914 10:02:12.707212 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5915 10:02:12.710972 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5916 10:02:12.711104 ==
5917 10:02:12.714195 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 10:02:12.721100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 10:02:12.721201 ==
5920 10:02:12.721295 DQS Delay:
5921 10:02:12.721433 DQS0 = 0, DQS1 = 0
5922 10:02:12.724249 DQM Delay:
5923 10:02:12.724323 DQM0 = 104, DQM1 = 100
5924 10:02:12.727632 DQ Delay:
5925 10:02:12.731329 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5926 10:02:12.734425 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5927 10:02:12.737723 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5928 10:02:12.740961 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5929 10:02:12.741071
5930 10:02:12.741158
5931 10:02:12.747364 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5932 10:02:12.750656 CH1 RK1: MR19=504, MR18=2CFF
5933 10:02:12.757819 CH1_RK1: MR19=0x504, MR18=0x2CFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5934 10:02:12.760833 [RxdqsGatingPostProcess] freq 933
5935 10:02:12.767416 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5936 10:02:12.770639 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 10:02:12.770737 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 10:02:12.773871 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 10:02:12.777011 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 10:02:12.780775 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 10:02:12.784011 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 10:02:12.787342 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 10:02:12.790399 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 10:02:12.793585 Pre-setting of DQS Precalculation
5945 10:02:12.800620 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5946 10:02:12.806969 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5947 10:02:12.813847 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5948 10:02:12.813970
5949 10:02:12.814059
5950 10:02:12.816996 [Calibration Summary] 1866 Mbps
5951 10:02:12.817097 CH 0, Rank 0
5952 10:02:12.820215 SW Impedance : PASS
5953 10:02:12.823413 DUTY Scan : NO K
5954 10:02:12.823506 ZQ Calibration : PASS
5955 10:02:12.827113 Jitter Meter : NO K
5956 10:02:12.830656 CBT Training : PASS
5957 10:02:12.830725 Write leveling : PASS
5958 10:02:12.833774 RX DQS gating : PASS
5959 10:02:12.836776 RX DQ/DQS(RDDQC) : PASS
5960 10:02:12.836845 TX DQ/DQS : PASS
5961 10:02:12.840216 RX DATLAT : PASS
5962 10:02:12.843565 RX DQ/DQS(Engine): PASS
5963 10:02:12.843668 TX OE : NO K
5964 10:02:12.843731 All Pass.
5965 10:02:12.843790
5966 10:02:12.846710 CH 0, Rank 1
5967 10:02:12.849916 SW Impedance : PASS
5968 10:02:12.850044 DUTY Scan : NO K
5969 10:02:12.853745 ZQ Calibration : PASS
5970 10:02:12.853850 Jitter Meter : NO K
5971 10:02:12.856968 CBT Training : PASS
5972 10:02:12.860206 Write leveling : PASS
5973 10:02:12.860288 RX DQS gating : PASS
5974 10:02:12.863545 RX DQ/DQS(RDDQC) : PASS
5975 10:02:12.866716 TX DQ/DQS : PASS
5976 10:02:12.866796 RX DATLAT : PASS
5977 10:02:12.870374 RX DQ/DQS(Engine): PASS
5978 10:02:12.873241 TX OE : NO K
5979 10:02:12.873321 All Pass.
5980 10:02:12.873384
5981 10:02:12.873443 CH 1, Rank 0
5982 10:02:12.876915 SW Impedance : PASS
5983 10:02:12.880046 DUTY Scan : NO K
5984 10:02:12.880152 ZQ Calibration : PASS
5985 10:02:12.883321 Jitter Meter : NO K
5986 10:02:12.886444 CBT Training : PASS
5987 10:02:12.886524 Write leveling : PASS
5988 10:02:12.889752 RX DQS gating : PASS
5989 10:02:12.893687 RX DQ/DQS(RDDQC) : PASS
5990 10:02:12.893790 TX DQ/DQS : PASS
5991 10:02:12.896861 RX DATLAT : PASS
5992 10:02:12.899865 RX DQ/DQS(Engine): PASS
5993 10:02:12.899940 TX OE : NO K
5994 10:02:12.900002 All Pass.
5995 10:02:12.903011
5996 10:02:12.903107 CH 1, Rank 1
5997 10:02:12.906338 SW Impedance : PASS
5998 10:02:12.906436 DUTY Scan : NO K
5999 10:02:12.910027 ZQ Calibration : PASS
6000 10:02:12.910108 Jitter Meter : NO K
6001 10:02:12.913044 CBT Training : PASS
6002 10:02:12.916229 Write leveling : PASS
6003 10:02:12.916309 RX DQS gating : PASS
6004 10:02:12.920052 RX DQ/DQS(RDDQC) : PASS
6005 10:02:12.922916 TX DQ/DQS : PASS
6006 10:02:12.922996 RX DATLAT : PASS
6007 10:02:12.926660 RX DQ/DQS(Engine): PASS
6008 10:02:12.929833 TX OE : NO K
6009 10:02:12.929913 All Pass.
6010 10:02:12.929976
6011 10:02:12.932892 DramC Write-DBI off
6012 10:02:12.932972 PER_BANK_REFRESH: Hybrid Mode
6013 10:02:12.936068 TX_TRACKING: ON
6014 10:02:12.943058 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6015 10:02:12.949784 [FAST_K] Save calibration result to emmc
6016 10:02:12.953211 dramc_set_vcore_voltage set vcore to 650000
6017 10:02:12.953317 Read voltage for 400, 6
6018 10:02:12.956122 Vio18 = 0
6019 10:02:12.956202 Vcore = 650000
6020 10:02:12.956266 Vdram = 0
6021 10:02:12.959345 Vddq = 0
6022 10:02:12.959450 Vmddr = 0
6023 10:02:12.963186 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6024 10:02:12.969627 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6025 10:02:12.972955 MEM_TYPE=3, freq_sel=20
6026 10:02:12.976247 sv_algorithm_assistance_LP4_800
6027 10:02:12.979742 ============ PULL DRAM RESETB DOWN ============
6028 10:02:12.982565 ========== PULL DRAM RESETB DOWN end =========
6029 10:02:12.989805 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6030 10:02:12.989991 ===================================
6031 10:02:12.992491 LPDDR4 DRAM CONFIGURATION
6032 10:02:12.996372 ===================================
6033 10:02:12.999731 EX_ROW_EN[0] = 0x0
6034 10:02:12.999813 EX_ROW_EN[1] = 0x0
6035 10:02:13.002822 LP4Y_EN = 0x0
6036 10:02:13.002905 WORK_FSP = 0x0
6037 10:02:13.005856 WL = 0x2
6038 10:02:13.005963 RL = 0x2
6039 10:02:13.009172 BL = 0x2
6040 10:02:13.009254 RPST = 0x0
6041 10:02:13.012856 RD_PRE = 0x0
6042 10:02:13.016129 WR_PRE = 0x1
6043 10:02:13.016211 WR_PST = 0x0
6044 10:02:13.019350 DBI_WR = 0x0
6045 10:02:13.019432 DBI_RD = 0x0
6046 10:02:13.022585 OTF = 0x1
6047 10:02:13.025746 ===================================
6048 10:02:13.029419 ===================================
6049 10:02:13.029503 ANA top config
6050 10:02:13.032504 ===================================
6051 10:02:13.035778 DLL_ASYNC_EN = 0
6052 10:02:13.039412 ALL_SLAVE_EN = 1
6053 10:02:13.039495 NEW_RANK_MODE = 1
6054 10:02:13.042677 DLL_IDLE_MODE = 1
6055 10:02:13.045943 LP45_APHY_COMB_EN = 1
6056 10:02:13.049070 TX_ODT_DIS = 1
6057 10:02:13.049177 NEW_8X_MODE = 1
6058 10:02:13.052338 ===================================
6059 10:02:13.056037 ===================================
6060 10:02:13.059079 data_rate = 800
6061 10:02:13.062212 CKR = 1
6062 10:02:13.065873 DQ_P2S_RATIO = 4
6063 10:02:13.068945 ===================================
6064 10:02:13.072773 CA_P2S_RATIO = 4
6065 10:02:13.076087 DQ_CA_OPEN = 0
6066 10:02:13.076174 DQ_SEMI_OPEN = 1
6067 10:02:13.079345 CA_SEMI_OPEN = 1
6068 10:02:13.082582 CA_FULL_RATE = 0
6069 10:02:13.085790 DQ_CKDIV4_EN = 0
6070 10:02:13.089343 CA_CKDIV4_EN = 1
6071 10:02:13.092623 CA_PREDIV_EN = 0
6072 10:02:13.092706 PH8_DLY = 0
6073 10:02:13.095729 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6074 10:02:13.099192 DQ_AAMCK_DIV = 0
6075 10:02:13.102202 CA_AAMCK_DIV = 0
6076 10:02:13.105475 CA_ADMCK_DIV = 4
6077 10:02:13.109172 DQ_TRACK_CA_EN = 0
6078 10:02:13.109255 CA_PICK = 800
6079 10:02:13.112222 CA_MCKIO = 400
6080 10:02:13.115427 MCKIO_SEMI = 400
6081 10:02:13.119151 PLL_FREQ = 3016
6082 10:02:13.122345 DQ_UI_PI_RATIO = 32
6083 10:02:13.125680 CA_UI_PI_RATIO = 32
6084 10:02:13.128877 ===================================
6085 10:02:13.132095 ===================================
6086 10:02:13.135873 memory_type:LPDDR4
6087 10:02:13.135956 GP_NUM : 10
6088 10:02:13.138897 SRAM_EN : 1
6089 10:02:13.138980 MD32_EN : 0
6090 10:02:13.142110 ===================================
6091 10:02:13.145837 [ANA_INIT] >>>>>>>>>>>>>>
6092 10:02:13.148944 <<<<<< [CONFIGURE PHASE]: ANA_TX
6093 10:02:13.152066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6094 10:02:13.155315 ===================================
6095 10:02:13.158623 data_rate = 800,PCW = 0X7400
6096 10:02:13.162526 ===================================
6097 10:02:13.165602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6098 10:02:13.168764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 10:02:13.182498 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 10:02:13.185702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6101 10:02:13.188900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6102 10:02:13.192126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6103 10:02:13.195334 [ANA_INIT] flow start
6104 10:02:13.198948 [ANA_INIT] PLL >>>>>>>>
6105 10:02:13.199027 [ANA_INIT] PLL <<<<<<<<
6106 10:02:13.201947 [ANA_INIT] MIDPI >>>>>>>>
6107 10:02:13.205405 [ANA_INIT] MIDPI <<<<<<<<
6108 10:02:13.205487 [ANA_INIT] DLL >>>>>>>>
6109 10:02:13.208801 [ANA_INIT] flow end
6110 10:02:13.212315 ============ LP4 DIFF to SE enter ============
6111 10:02:13.215428 ============ LP4 DIFF to SE exit ============
6112 10:02:13.218595 [ANA_INIT] <<<<<<<<<<<<<
6113 10:02:13.222174 [Flow] Enable top DCM control >>>>>
6114 10:02:13.225092 [Flow] Enable top DCM control <<<<<
6115 10:02:13.228959 Enable DLL master slave shuffle
6116 10:02:13.235304 ==============================================================
6117 10:02:13.235447 Gating Mode config
6118 10:02:13.241838 ==============================================================
6119 10:02:13.244715 Config description:
6120 10:02:13.251714 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6121 10:02:13.258183 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6122 10:02:13.265003 SELPH_MODE 0: By rank 1: By Phase
6123 10:02:13.271764 ==============================================================
6124 10:02:13.274840 GAT_TRACK_EN = 0
6125 10:02:13.274939 RX_GATING_MODE = 2
6126 10:02:13.278013 RX_GATING_TRACK_MODE = 2
6127 10:02:13.281099 SELPH_MODE = 1
6128 10:02:13.284943 PICG_EARLY_EN = 1
6129 10:02:13.288160 VALID_LAT_VALUE = 1
6130 10:02:13.294834 ==============================================================
6131 10:02:13.298057 Enter into Gating configuration >>>>
6132 10:02:13.301230 Exit from Gating configuration <<<<
6133 10:02:13.304250 Enter into DVFS_PRE_config >>>>>
6134 10:02:13.314234 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6135 10:02:13.317779 Exit from DVFS_PRE_config <<<<<
6136 10:02:13.320810 Enter into PICG configuration >>>>
6137 10:02:13.324125 Exit from PICG configuration <<<<
6138 10:02:13.327802 [RX_INPUT] configuration >>>>>
6139 10:02:13.330901 [RX_INPUT] configuration <<<<<
6140 10:02:13.334331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6141 10:02:13.341158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6142 10:02:13.347515 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 10:02:13.350668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 10:02:13.357655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 10:02:13.363961 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 10:02:13.367820 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6147 10:02:13.374081 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6148 10:02:13.377715 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6149 10:02:13.381015 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6150 10:02:13.384213 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6151 10:02:13.390461 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6152 10:02:13.393766 ===================================
6153 10:02:13.393843 LPDDR4 DRAM CONFIGURATION
6154 10:02:13.397747 ===================================
6155 10:02:13.401012 EX_ROW_EN[0] = 0x0
6156 10:02:13.404236 EX_ROW_EN[1] = 0x0
6157 10:02:13.404306 LP4Y_EN = 0x0
6158 10:02:13.407448 WORK_FSP = 0x0
6159 10:02:13.407547 WL = 0x2
6160 10:02:13.410848 RL = 0x2
6161 10:02:13.410943 BL = 0x2
6162 10:02:13.413889 RPST = 0x0
6163 10:02:13.413998 RD_PRE = 0x0
6164 10:02:13.417101 WR_PRE = 0x1
6165 10:02:13.417202 WR_PST = 0x0
6166 10:02:13.420705 DBI_WR = 0x0
6167 10:02:13.420821 DBI_RD = 0x0
6168 10:02:13.424261 OTF = 0x1
6169 10:02:13.427394 ===================================
6170 10:02:13.430438 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6171 10:02:13.434349 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6172 10:02:13.440677 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 10:02:13.444242 ===================================
6174 10:02:13.444325 LPDDR4 DRAM CONFIGURATION
6175 10:02:13.447138 ===================================
6176 10:02:13.450451 EX_ROW_EN[0] = 0x10
6177 10:02:13.450565 EX_ROW_EN[1] = 0x0
6178 10:02:13.454219 LP4Y_EN = 0x0
6179 10:02:13.457303 WORK_FSP = 0x0
6180 10:02:13.457385 WL = 0x2
6181 10:02:13.460300 RL = 0x2
6182 10:02:13.460383 BL = 0x2
6183 10:02:13.463575 RPST = 0x0
6184 10:02:13.463696 RD_PRE = 0x0
6185 10:02:13.467483 WR_PRE = 0x1
6186 10:02:13.467616 WR_PST = 0x0
6187 10:02:13.470615 DBI_WR = 0x0
6188 10:02:13.470695 DBI_RD = 0x0
6189 10:02:13.473788 OTF = 0x1
6190 10:02:13.476930 ===================================
6191 10:02:13.483758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6192 10:02:13.486997 nWR fixed to 30
6193 10:02:13.487104 [ModeRegInit_LP4] CH0 RK0
6194 10:02:13.490154 [ModeRegInit_LP4] CH0 RK1
6195 10:02:13.493844 [ModeRegInit_LP4] CH1 RK0
6196 10:02:13.493924 [ModeRegInit_LP4] CH1 RK1
6197 10:02:13.497101 match AC timing 19
6198 10:02:13.500404 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6199 10:02:13.506770 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6200 10:02:13.509988 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6201 10:02:13.513669 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6202 10:02:13.520083 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6203 10:02:13.520164 ==
6204 10:02:13.523332 Dram Type= 6, Freq= 0, CH_0, rank 0
6205 10:02:13.526902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6206 10:02:13.527009 ==
6207 10:02:13.533854 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6208 10:02:13.536876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6209 10:02:13.539976 [CA 0] Center 36 (8~64) winsize 57
6210 10:02:13.543883 [CA 1] Center 36 (8~64) winsize 57
6211 10:02:13.546937 [CA 2] Center 36 (8~64) winsize 57
6212 10:02:13.550059 [CA 3] Center 36 (8~64) winsize 57
6213 10:02:13.553544 [CA 4] Center 36 (8~64) winsize 57
6214 10:02:13.556966 [CA 5] Center 36 (8~64) winsize 57
6215 10:02:13.557046
6216 10:02:13.560186 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6217 10:02:13.560266
6218 10:02:13.563491 [CATrainingPosCal] consider 1 rank data
6219 10:02:13.566928 u2DelayCellTimex100 = 270/100 ps
6220 10:02:13.570211 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 10:02:13.573469 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 10:02:13.579876 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 10:02:13.583508 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 10:02:13.586619 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 10:02:13.589804 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 10:02:13.589884
6227 10:02:13.593159 CA PerBit enable=1, Macro0, CA PI delay=36
6228 10:02:13.593239
6229 10:02:13.596382 [CBTSetCACLKResult] CA Dly = 36
6230 10:02:13.596503 CS Dly: 1 (0~32)
6231 10:02:13.600016 ==
6232 10:02:13.600096 Dram Type= 6, Freq= 0, CH_0, rank 1
6233 10:02:13.606441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 10:02:13.606522 ==
6235 10:02:13.609714 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 10:02:13.616182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6237 10:02:13.619998 [CA 0] Center 36 (8~64) winsize 57
6238 10:02:13.623245 [CA 1] Center 36 (8~64) winsize 57
6239 10:02:13.626556 [CA 2] Center 36 (8~64) winsize 57
6240 10:02:13.629603 [CA 3] Center 36 (8~64) winsize 57
6241 10:02:13.633242 [CA 4] Center 36 (8~64) winsize 57
6242 10:02:13.636498 [CA 5] Center 36 (8~64) winsize 57
6243 10:02:13.636598
6244 10:02:13.639752 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6245 10:02:13.639828
6246 10:02:13.642921 [CATrainingPosCal] consider 2 rank data
6247 10:02:13.646079 u2DelayCellTimex100 = 270/100 ps
6248 10:02:13.649619 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 10:02:13.653153 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 10:02:13.656397 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 10:02:13.659627 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 10:02:13.662750 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 10:02:13.669648 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 10:02:13.669750
6255 10:02:13.672732 CA PerBit enable=1, Macro0, CA PI delay=36
6256 10:02:13.672809
6257 10:02:13.676317 [CBTSetCACLKResult] CA Dly = 36
6258 10:02:13.676400 CS Dly: 1 (0~32)
6259 10:02:13.676493
6260 10:02:13.679383 ----->DramcWriteLeveling(PI) begin...
6261 10:02:13.679464 ==
6262 10:02:13.683036 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 10:02:13.686145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 10:02:13.689247 ==
6265 10:02:13.689326 Write leveling (Byte 0): 40 => 8
6266 10:02:13.693081 Write leveling (Byte 1): 40 => 8
6267 10:02:13.696310 DramcWriteLeveling(PI) end<-----
6268 10:02:13.696415
6269 10:02:13.696518 ==
6270 10:02:13.699458 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 10:02:13.706324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 10:02:13.706405 ==
6273 10:02:13.706469 [Gating] SW mode calibration
6274 10:02:13.716135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6275 10:02:13.719377 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6276 10:02:13.723101 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 10:02:13.729366 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 10:02:13.732776 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 10:02:13.736246 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 10:02:13.742662 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 10:02:13.745800 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 10:02:13.748995 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 10:02:13.756039 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 10:02:13.759209 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 10:02:13.762644 Total UI for P1: 0, mck2ui 16
6286 10:02:13.765966 best dqsien dly found for B0: ( 0, 14, 24)
6287 10:02:13.769554 Total UI for P1: 0, mck2ui 16
6288 10:02:13.772473 best dqsien dly found for B1: ( 0, 14, 24)
6289 10:02:13.776055 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6290 10:02:13.779187 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6291 10:02:13.779284
6292 10:02:13.782751 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 10:02:13.785840 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 10:02:13.788949 [Gating] SW calibration Done
6295 10:02:13.789043 ==
6296 10:02:13.792533 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 10:02:13.799115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 10:02:13.799196 ==
6299 10:02:13.799259 RX Vref Scan: 0
6300 10:02:13.799318
6301 10:02:13.802183 RX Vref 0 -> 0, step: 1
6302 10:02:13.802286
6303 10:02:13.805954 RX Delay -410 -> 252, step: 16
6304 10:02:13.809038 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6305 10:02:13.812040 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6306 10:02:13.818705 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6307 10:02:13.822450 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6308 10:02:13.825610 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6309 10:02:13.828711 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6310 10:02:13.835328 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6311 10:02:13.838577 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6312 10:02:13.842363 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6313 10:02:13.845679 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6314 10:02:13.852083 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6315 10:02:13.855211 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6316 10:02:13.858995 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6317 10:02:13.862252 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6318 10:02:13.868541 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6319 10:02:13.872089 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6320 10:02:13.872194 ==
6321 10:02:13.875332 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 10:02:13.878739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 10:02:13.878811 ==
6324 10:02:13.882214 DQS Delay:
6325 10:02:13.882309 DQS0 = 27, DQS1 = 35
6326 10:02:13.882395 DQM Delay:
6327 10:02:13.885810 DQM0 = 9, DQM1 = 11
6328 10:02:13.885906 DQ Delay:
6329 10:02:13.888683 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6330 10:02:13.892093 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6331 10:02:13.895158 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6332 10:02:13.898719 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6333 10:02:13.898794
6334 10:02:13.898862
6335 10:02:13.898925 ==
6336 10:02:13.902294 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 10:02:13.905247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 10:02:13.905320 ==
6339 10:02:13.908755
6340 10:02:13.908863
6341 10:02:13.908925 TX Vref Scan disable
6342 10:02:13.911874 == TX Byte 0 ==
6343 10:02:13.915771 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 10:02:13.918851 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 10:02:13.921977 == TX Byte 1 ==
6346 10:02:13.925287 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 10:02:13.928614 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 10:02:13.928698 ==
6349 10:02:13.931763 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 10:02:13.935472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 10:02:13.938721 ==
6352 10:02:13.938797
6353 10:02:13.938862
6354 10:02:13.938921 TX Vref Scan disable
6355 10:02:13.941863 == TX Byte 0 ==
6356 10:02:13.945640 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 10:02:13.948771 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 10:02:13.952047 == TX Byte 1 ==
6359 10:02:13.955288 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 10:02:13.958553 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 10:02:13.958632
6362 10:02:13.958695 [DATLAT]
6363 10:02:13.961692 Freq=400, CH0 RK0
6364 10:02:13.961771
6365 10:02:13.964988 DATLAT Default: 0xf
6366 10:02:13.965106 0, 0xFFFF, sum = 0
6367 10:02:13.968888 1, 0xFFFF, sum = 0
6368 10:02:13.968982 2, 0xFFFF, sum = 0
6369 10:02:13.972118 3, 0xFFFF, sum = 0
6370 10:02:13.972192 4, 0xFFFF, sum = 0
6371 10:02:13.975292 5, 0xFFFF, sum = 0
6372 10:02:13.975363 6, 0xFFFF, sum = 0
6373 10:02:13.978607 7, 0xFFFF, sum = 0
6374 10:02:13.978684 8, 0xFFFF, sum = 0
6375 10:02:13.981640 9, 0xFFFF, sum = 0
6376 10:02:13.981726 10, 0xFFFF, sum = 0
6377 10:02:13.985529 11, 0xFFFF, sum = 0
6378 10:02:13.985602 12, 0xFFFF, sum = 0
6379 10:02:13.988507 13, 0x0, sum = 1
6380 10:02:13.988576 14, 0x0, sum = 2
6381 10:02:13.991573 15, 0x0, sum = 3
6382 10:02:13.991676 16, 0x0, sum = 4
6383 10:02:13.995037 best_step = 14
6384 10:02:13.995150
6385 10:02:13.995246 ==
6386 10:02:13.998778 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 10:02:14.001611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 10:02:14.001713 ==
6389 10:02:14.004775 RX Vref Scan: 1
6390 10:02:14.004858
6391 10:02:14.004921 RX Vref 0 -> 0, step: 1
6392 10:02:14.004980
6393 10:02:14.008297 RX Delay -311 -> 252, step: 8
6394 10:02:14.008369
6395 10:02:14.011902 Set Vref, RX VrefLevel [Byte0]: 55
6396 10:02:14.014847 [Byte1]: 49
6397 10:02:14.019487
6398 10:02:14.019587 Final RX Vref Byte 0 = 55 to rank0
6399 10:02:14.022629 Final RX Vref Byte 1 = 49 to rank0
6400 10:02:14.025737 Final RX Vref Byte 0 = 55 to rank1
6401 10:02:14.029365 Final RX Vref Byte 1 = 49 to rank1==
6402 10:02:14.032551 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 10:02:14.039326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 10:02:14.039408 ==
6405 10:02:14.039472 DQS Delay:
6406 10:02:14.042589 DQS0 = 24, DQS1 = 36
6407 10:02:14.042662 DQM Delay:
6408 10:02:14.042743 DQM0 = 7, DQM1 = 12
6409 10:02:14.045765 DQ Delay:
6410 10:02:14.049467 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6411 10:02:14.049566 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6412 10:02:14.052782 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6413 10:02:14.055971 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6414 10:02:14.056042
6415 10:02:14.056118
6416 10:02:14.065658 [DQSOSCAuto] RK0, (LSB)MR18= 0xcfbd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6417 10:02:14.069679 CH0 RK0: MR19=C0C, MR18=CFBD
6418 10:02:14.076279 CH0_RK0: MR19=0xC0C, MR18=0xCFBD, DQSOSC=384, MR23=63, INC=400, DEC=267
6419 10:02:14.076362 ==
6420 10:02:14.079454 Dram Type= 6, Freq= 0, CH_0, rank 1
6421 10:02:14.082654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 10:02:14.082738 ==
6423 10:02:14.085726 [Gating] SW mode calibration
6424 10:02:14.092368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6425 10:02:14.095459 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6426 10:02:14.102200 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 10:02:14.105762 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 10:02:14.109424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 10:02:14.115451 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 10:02:14.119151 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 10:02:14.122346 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 10:02:14.128857 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 10:02:14.132044 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 10:02:14.135681 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 10:02:14.138658 Total UI for P1: 0, mck2ui 16
6436 10:02:14.142230 best dqsien dly found for B0: ( 0, 14, 24)
6437 10:02:14.145486 Total UI for P1: 0, mck2ui 16
6438 10:02:14.148718 best dqsien dly found for B1: ( 0, 14, 24)
6439 10:02:14.151856 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6440 10:02:14.155823 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6441 10:02:14.158461
6442 10:02:14.161722 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 10:02:14.165706 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 10:02:14.168831 [Gating] SW calibration Done
6445 10:02:14.168914 ==
6446 10:02:14.172122 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 10:02:14.175489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 10:02:14.175572 ==
6449 10:02:14.175664 RX Vref Scan: 0
6450 10:02:14.178756
6451 10:02:14.178838 RX Vref 0 -> 0, step: 1
6452 10:02:14.178924
6453 10:02:14.181927 RX Delay -410 -> 252, step: 16
6454 10:02:14.184948 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6455 10:02:14.191915 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6456 10:02:14.195446 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6457 10:02:14.198606 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6458 10:02:14.201826 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6459 10:02:14.208738 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6460 10:02:14.211802 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6461 10:02:14.215000 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6462 10:02:14.218222 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6463 10:02:14.225263 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6464 10:02:14.228309 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6465 10:02:14.231885 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6466 10:02:14.235162 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6467 10:02:14.241546 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6468 10:02:14.245071 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6469 10:02:14.248276 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6470 10:02:14.248359 ==
6471 10:02:14.252048 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 10:02:14.255028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 10:02:14.258176 ==
6474 10:02:14.258252 DQS Delay:
6475 10:02:14.258366 DQS0 = 19, DQS1 = 35
6476 10:02:14.262029 DQM Delay:
6477 10:02:14.262098 DQM0 = 5, DQM1 = 12
6478 10:02:14.265358 DQ Delay:
6479 10:02:14.265436 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6480 10:02:14.268473 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6481 10:02:14.271703 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6482 10:02:14.275045 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6483 10:02:14.275115
6484 10:02:14.275174
6485 10:02:14.275230 ==
6486 10:02:14.278325 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 10:02:14.285446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 10:02:14.285518 ==
6489 10:02:14.285586
6490 10:02:14.285647
6491 10:02:14.285704 TX Vref Scan disable
6492 10:02:14.288654 == TX Byte 0 ==
6493 10:02:14.291841 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6494 10:02:14.294958 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6495 10:02:14.298145 == TX Byte 1 ==
6496 10:02:14.301497 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6497 10:02:14.305212 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6498 10:02:14.305282 ==
6499 10:02:14.308317 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 10:02:14.315190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 10:02:14.315278 ==
6502 10:02:14.315347
6503 10:02:14.315407
6504 10:02:14.315469 TX Vref Scan disable
6505 10:02:14.318613 == TX Byte 0 ==
6506 10:02:14.321735 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6507 10:02:14.325032 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6508 10:02:14.328169 == TX Byte 1 ==
6509 10:02:14.331780 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6510 10:02:14.335338 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6511 10:02:14.335421
6512 10:02:14.338464 [DATLAT]
6513 10:02:14.338545 Freq=400, CH0 RK1
6514 10:02:14.338630
6515 10:02:14.341602 DATLAT Default: 0xe
6516 10:02:14.341685 0, 0xFFFF, sum = 0
6517 10:02:14.345431 1, 0xFFFF, sum = 0
6518 10:02:14.345515 2, 0xFFFF, sum = 0
6519 10:02:14.348639 3, 0xFFFF, sum = 0
6520 10:02:14.348722 4, 0xFFFF, sum = 0
6521 10:02:14.351858 5, 0xFFFF, sum = 0
6522 10:02:14.351943 6, 0xFFFF, sum = 0
6523 10:02:14.355377 7, 0xFFFF, sum = 0
6524 10:02:14.355485 8, 0xFFFF, sum = 0
6525 10:02:14.358559 9, 0xFFFF, sum = 0
6526 10:02:14.358643 10, 0xFFFF, sum = 0
6527 10:02:14.361644 11, 0xFFFF, sum = 0
6528 10:02:14.365180 12, 0xFFFF, sum = 0
6529 10:02:14.365263 13, 0x0, sum = 1
6530 10:02:14.365349 14, 0x0, sum = 2
6531 10:02:14.368185 15, 0x0, sum = 3
6532 10:02:14.368269 16, 0x0, sum = 4
6533 10:02:14.371421 best_step = 14
6534 10:02:14.371503
6535 10:02:14.371621 ==
6536 10:02:14.375394 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 10:02:14.378762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 10:02:14.378846 ==
6539 10:02:14.381951 RX Vref Scan: 0
6540 10:02:14.382034
6541 10:02:14.382118 RX Vref 0 -> 0, step: 1
6542 10:02:14.382198
6543 10:02:14.385218 RX Delay -311 -> 252, step: 8
6544 10:02:14.392762 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6545 10:02:14.396619 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6546 10:02:14.399772 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6547 10:02:14.403003 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6548 10:02:14.409430 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6549 10:02:14.412961 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6550 10:02:14.416183 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6551 10:02:14.419478 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6552 10:02:14.425980 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6553 10:02:14.429378 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6554 10:02:14.433206 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6555 10:02:14.436202 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6556 10:02:14.442583 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6557 10:02:14.446236 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6558 10:02:14.449243 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6559 10:02:14.456169 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6560 10:02:14.456253 ==
6561 10:02:14.459249 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 10:02:14.462874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 10:02:14.462958 ==
6564 10:02:14.463042 DQS Delay:
6565 10:02:14.466002 DQS0 = 24, DQS1 = 32
6566 10:02:14.466085 DQM Delay:
6567 10:02:14.469691 DQM0 = 9, DQM1 = 10
6568 10:02:14.469774 DQ Delay:
6569 10:02:14.472647 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6570 10:02:14.476358 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6571 10:02:14.479504 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6572 10:02:14.482689 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6573 10:02:14.482771
6574 10:02:14.482855
6575 10:02:14.489264 [DQSOSCAuto] RK1, (LSB)MR18= 0xc262, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps
6576 10:02:14.492441 CH0 RK1: MR19=C0C, MR18=C262
6577 10:02:14.499614 CH0_RK1: MR19=0xC0C, MR18=0xC262, DQSOSC=385, MR23=63, INC=398, DEC=265
6578 10:02:14.502815 [RxdqsGatingPostProcess] freq 400
6579 10:02:14.506058 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6580 10:02:14.509261 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 10:02:14.512463 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 10:02:14.516311 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 10:02:14.519256 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 10:02:14.522374 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 10:02:14.526119 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 10:02:14.529132 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 10:02:14.532770 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 10:02:14.536074 Pre-setting of DQS Precalculation
6589 10:02:14.539246 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6590 10:02:14.542583 ==
6591 10:02:14.545734 Dram Type= 6, Freq= 0, CH_1, rank 0
6592 10:02:14.549374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 10:02:14.549457 ==
6594 10:02:14.552335 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6595 10:02:14.559206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6596 10:02:14.562476 [CA 0] Center 36 (8~64) winsize 57
6597 10:02:14.565700 [CA 1] Center 36 (8~64) winsize 57
6598 10:02:14.568801 [CA 2] Center 36 (8~64) winsize 57
6599 10:02:14.572356 [CA 3] Center 36 (8~64) winsize 57
6600 10:02:14.575804 [CA 4] Center 36 (8~64) winsize 57
6601 10:02:14.578751 [CA 5] Center 36 (8~64) winsize 57
6602 10:02:14.578832
6603 10:02:14.582454 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6604 10:02:14.582564
6605 10:02:14.585402 [CATrainingPosCal] consider 1 rank data
6606 10:02:14.589411 u2DelayCellTimex100 = 270/100 ps
6607 10:02:14.592666 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 10:02:14.595825 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 10:02:14.599186 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 10:02:14.602336 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 10:02:14.605633 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 10:02:14.612764 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 10:02:14.612846
6614 10:02:14.616065 CA PerBit enable=1, Macro0, CA PI delay=36
6615 10:02:14.616147
6616 10:02:14.619270 [CBTSetCACLKResult] CA Dly = 36
6617 10:02:14.619353 CS Dly: 1 (0~32)
6618 10:02:14.619438 ==
6619 10:02:14.622340 Dram Type= 6, Freq= 0, CH_1, rank 1
6620 10:02:14.625405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 10:02:14.629015 ==
6622 10:02:14.632163 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 10:02:14.638936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6624 10:02:14.642194 [CA 0] Center 36 (8~64) winsize 57
6625 10:02:14.645381 [CA 1] Center 36 (8~64) winsize 57
6626 10:02:14.648607 [CA 2] Center 36 (8~64) winsize 57
6627 10:02:14.651832 [CA 3] Center 36 (8~64) winsize 57
6628 10:02:14.655168 [CA 4] Center 36 (8~64) winsize 57
6629 10:02:14.658849 [CA 5] Center 36 (8~64) winsize 57
6630 10:02:14.658975
6631 10:02:14.661935 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6632 10:02:14.662043
6633 10:02:14.665615 [CATrainingPosCal] consider 2 rank data
6634 10:02:14.668516 u2DelayCellTimex100 = 270/100 ps
6635 10:02:14.672143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 10:02:14.675375 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 10:02:14.678580 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 10:02:14.682216 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 10:02:14.685149 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 10:02:14.688806 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 10:02:14.688886
6642 10:02:14.691774 CA PerBit enable=1, Macro0, CA PI delay=36
6643 10:02:14.695444
6644 10:02:14.695523 [CBTSetCACLKResult] CA Dly = 36
6645 10:02:14.698830 CS Dly: 1 (0~32)
6646 10:02:14.698911
6647 10:02:14.702014 ----->DramcWriteLeveling(PI) begin...
6648 10:02:14.702096 ==
6649 10:02:14.705517 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 10:02:14.708655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 10:02:14.708738 ==
6652 10:02:14.711948 Write leveling (Byte 0): 40 => 8
6653 10:02:14.715091 Write leveling (Byte 1): 40 => 8
6654 10:02:14.718459 DramcWriteLeveling(PI) end<-----
6655 10:02:14.718541
6656 10:02:14.718625 ==
6657 10:02:14.721689 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 10:02:14.724973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 10:02:14.725057 ==
6660 10:02:14.728825 [Gating] SW mode calibration
6661 10:02:14.734985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6662 10:02:14.741855 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6663 10:02:14.744908 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 10:02:14.751398 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 10:02:14.755367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 10:02:14.758758 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 10:02:14.764629 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 10:02:14.768531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 10:02:14.771676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 10:02:14.778417 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 10:02:14.782019 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 10:02:14.785218 Total UI for P1: 0, mck2ui 16
6673 10:02:14.788387 best dqsien dly found for B0: ( 0, 14, 24)
6674 10:02:14.791582 Total UI for P1: 0, mck2ui 16
6675 10:02:14.794891 best dqsien dly found for B1: ( 0, 14, 24)
6676 10:02:14.798536 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6677 10:02:14.801611 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6678 10:02:14.801694
6679 10:02:14.805114 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 10:02:14.808217 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 10:02:14.811723 [Gating] SW calibration Done
6682 10:02:14.811805 ==
6683 10:02:14.814612 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 10:02:14.818420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 10:02:14.818502 ==
6686 10:02:14.821702 RX Vref Scan: 0
6687 10:02:14.821785
6688 10:02:14.824730 RX Vref 0 -> 0, step: 1
6689 10:02:14.824813
6690 10:02:14.824898 RX Delay -410 -> 252, step: 16
6691 10:02:14.831398 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6692 10:02:14.835112 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6693 10:02:14.838157 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6694 10:02:14.842001 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6695 10:02:14.848268 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6696 10:02:14.851970 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6697 10:02:14.855161 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6698 10:02:14.858439 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6699 10:02:14.865407 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6700 10:02:14.868780 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6701 10:02:14.871958 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6702 10:02:14.875042 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6703 10:02:14.882147 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6704 10:02:14.885258 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6705 10:02:14.888463 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6706 10:02:14.892076 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6707 10:02:14.892175 ==
6708 10:02:14.895295 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 10:02:14.901660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 10:02:14.901756 ==
6711 10:02:14.901839 DQS Delay:
6712 10:02:14.904957 DQS0 = 35, DQS1 = 35
6713 10:02:14.905040 DQM Delay:
6714 10:02:14.905125 DQM0 = 20, DQM1 = 18
6715 10:02:14.908297 DQ Delay:
6716 10:02:14.911548 DQ0 =32, DQ1 =8, DQ2 =0, DQ3 =16
6717 10:02:14.915441 DQ4 =24, DQ5 =32, DQ6 =32, DQ7 =16
6718 10:02:14.915548 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6719 10:02:14.922066 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6720 10:02:14.922148
6721 10:02:14.922232
6722 10:02:14.922312 ==
6723 10:02:14.925556 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 10:02:14.928506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 10:02:14.928590 ==
6726 10:02:14.928674
6727 10:02:14.928784
6728 10:02:14.932112 TX Vref Scan disable
6729 10:02:14.932194 == TX Byte 0 ==
6730 10:02:14.935437 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 10:02:14.941714 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 10:02:14.941797 == TX Byte 1 ==
6733 10:02:14.945366 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 10:02:14.951895 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 10:02:14.951979 ==
6736 10:02:14.955274 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 10:02:14.958511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 10:02:14.958612 ==
6739 10:02:14.958702
6740 10:02:14.958780
6741 10:02:14.961846 TX Vref Scan disable
6742 10:02:14.961951 == TX Byte 0 ==
6743 10:02:14.964944 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 10:02:14.971962 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 10:02:14.972037 == TX Byte 1 ==
6746 10:02:14.975240 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 10:02:14.981914 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 10:02:14.982013
6749 10:02:14.982094 [DATLAT]
6750 10:02:14.982185 Freq=400, CH1 RK0
6751 10:02:14.985057
6752 10:02:14.985153 DATLAT Default: 0xf
6753 10:02:14.988167 0, 0xFFFF, sum = 0
6754 10:02:14.988272 1, 0xFFFF, sum = 0
6755 10:02:14.991849 2, 0xFFFF, sum = 0
6756 10:02:14.991933 3, 0xFFFF, sum = 0
6757 10:02:14.994817 4, 0xFFFF, sum = 0
6758 10:02:14.994913 5, 0xFFFF, sum = 0
6759 10:02:14.998529 6, 0xFFFF, sum = 0
6760 10:02:14.998637 7, 0xFFFF, sum = 0
6761 10:02:15.001632 8, 0xFFFF, sum = 0
6762 10:02:15.001737 9, 0xFFFF, sum = 0
6763 10:02:15.004770 10, 0xFFFF, sum = 0
6764 10:02:15.004845 11, 0xFFFF, sum = 0
6765 10:02:15.007931 12, 0xFFFF, sum = 0
6766 10:02:15.008015 13, 0x0, sum = 1
6767 10:02:15.011864 14, 0x0, sum = 2
6768 10:02:15.011948 15, 0x0, sum = 3
6769 10:02:15.015137 16, 0x0, sum = 4
6770 10:02:15.015221 best_step = 14
6771 10:02:15.015319
6772 10:02:15.015416 ==
6773 10:02:15.018446 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 10:02:15.024800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 10:02:15.024883 ==
6776 10:02:15.024966 RX Vref Scan: 1
6777 10:02:15.025046
6778 10:02:15.028086 RX Vref 0 -> 0, step: 1
6779 10:02:15.028168
6780 10:02:15.031213 RX Delay -311 -> 252, step: 8
6781 10:02:15.031296
6782 10:02:15.034871 Set Vref, RX VrefLevel [Byte0]: 53
6783 10:02:15.037876 [Byte1]: 51
6784 10:02:15.037959
6785 10:02:15.041269 Final RX Vref Byte 0 = 53 to rank0
6786 10:02:15.044826 Final RX Vref Byte 1 = 51 to rank0
6787 10:02:15.047873 Final RX Vref Byte 0 = 53 to rank1
6788 10:02:15.051452 Final RX Vref Byte 1 = 51 to rank1==
6789 10:02:15.054623 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 10:02:15.057620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 10:02:15.061189 ==
6792 10:02:15.061272 DQS Delay:
6793 10:02:15.061365 DQS0 = 32, DQS1 = 32
6794 10:02:15.064418 DQM Delay:
6795 10:02:15.064500 DQM0 = 14, DQM1 = 11
6796 10:02:15.068193 DQ Delay:
6797 10:02:15.068281 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6798 10:02:15.071342 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6799 10:02:15.074560 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6800 10:02:15.077717 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6801 10:02:15.077813
6802 10:02:15.077906
6803 10:02:15.087709 [DQSOSCAuto] RK0, (LSB)MR18= 0x97d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6804 10:02:15.090852 CH1 RK0: MR19=C0C, MR18=97D0
6805 10:02:15.097891 CH1_RK0: MR19=0xC0C, MR18=0x97D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6806 10:02:15.098003 ==
6807 10:02:15.100904 Dram Type= 6, Freq= 0, CH_1, rank 1
6808 10:02:15.104295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 10:02:15.104399 ==
6810 10:02:15.107377 [Gating] SW mode calibration
6811 10:02:15.114332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6812 10:02:15.117583 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6813 10:02:15.124144 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 10:02:15.127331 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 10:02:15.131216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 10:02:15.137760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 10:02:15.141056 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 10:02:15.144331 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 10:02:15.151025 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 10:02:15.153888 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 10:02:15.157328 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 10:02:15.160796 Total UI for P1: 0, mck2ui 16
6823 10:02:15.164242 best dqsien dly found for B0: ( 0, 14, 24)
6824 10:02:15.167067 Total UI for P1: 0, mck2ui 16
6825 10:02:15.170795 best dqsien dly found for B1: ( 0, 14, 24)
6826 10:02:15.174231 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6827 10:02:15.177187 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6828 10:02:15.177281
6829 10:02:15.184202 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 10:02:15.187368 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 10:02:15.190495 [Gating] SW calibration Done
6832 10:02:15.190599 ==
6833 10:02:15.194299 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 10:02:15.197459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 10:02:15.197554 ==
6836 10:02:15.197645 RX Vref Scan: 0
6837 10:02:15.197720
6838 10:02:15.200627 RX Vref 0 -> 0, step: 1
6839 10:02:15.200698
6840 10:02:15.203896 RX Delay -410 -> 252, step: 16
6841 10:02:15.207080 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6842 10:02:15.213832 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6843 10:02:15.217350 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6844 10:02:15.220576 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6845 10:02:15.224205 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6846 10:02:15.227578 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6847 10:02:15.234089 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6848 10:02:15.237541 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6849 10:02:15.240710 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6850 10:02:15.244018 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6851 10:02:15.250732 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6852 10:02:15.254048 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6853 10:02:15.257190 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6854 10:02:15.263565 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6855 10:02:15.267127 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6856 10:02:15.270337 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6857 10:02:15.270417 ==
6858 10:02:15.273514 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 10:02:15.276717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 10:02:15.280287 ==
6861 10:02:15.280367 DQS Delay:
6862 10:02:15.280430 DQS0 = 35, DQS1 = 35
6863 10:02:15.283726 DQM Delay:
6864 10:02:15.283806 DQM0 = 17, DQM1 = 13
6865 10:02:15.287016 DQ Delay:
6866 10:02:15.287096 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6867 10:02:15.290440 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6868 10:02:15.293807 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6869 10:02:15.297040 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6870 10:02:15.297120
6871 10:02:15.297222
6872 10:02:15.300455 ==
6873 10:02:15.300569 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 10:02:15.307039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 10:02:15.307145 ==
6876 10:02:15.307236
6877 10:02:15.307359
6878 10:02:15.310339 TX Vref Scan disable
6879 10:02:15.310419 == TX Byte 0 ==
6880 10:02:15.313587 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6881 10:02:15.319991 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6882 10:02:15.320100 == TX Byte 1 ==
6883 10:02:15.323745 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6884 10:02:15.326814 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6885 10:02:15.330084 ==
6886 10:02:15.333654 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 10:02:15.336739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 10:02:15.336841 ==
6889 10:02:15.336934
6890 10:02:15.337019
6891 10:02:15.340058 TX Vref Scan disable
6892 10:02:15.340153 == TX Byte 0 ==
6893 10:02:15.343843 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6894 10:02:15.350356 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6895 10:02:15.350453 == TX Byte 1 ==
6896 10:02:15.353587 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6897 10:02:15.356816 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6898 10:02:15.360000
6899 10:02:15.360072 [DATLAT]
6900 10:02:15.360132 Freq=400, CH1 RK1
6901 10:02:15.360190
6902 10:02:15.363743 DATLAT Default: 0xe
6903 10:02:15.363811 0, 0xFFFF, sum = 0
6904 10:02:15.366924 1, 0xFFFF, sum = 0
6905 10:02:15.367026 2, 0xFFFF, sum = 0
6906 10:02:15.370259 3, 0xFFFF, sum = 0
6907 10:02:15.370363 4, 0xFFFF, sum = 0
6908 10:02:15.373354 5, 0xFFFF, sum = 0
6909 10:02:15.376499 6, 0xFFFF, sum = 0
6910 10:02:15.376569 7, 0xFFFF, sum = 0
6911 10:02:15.380375 8, 0xFFFF, sum = 0
6912 10:02:15.380449 9, 0xFFFF, sum = 0
6913 10:02:15.383542 10, 0xFFFF, sum = 0
6914 10:02:15.383678 11, 0xFFFF, sum = 0
6915 10:02:15.386322 12, 0xFFFF, sum = 0
6916 10:02:15.386418 13, 0x0, sum = 1
6917 10:02:15.390064 14, 0x0, sum = 2
6918 10:02:15.390161 15, 0x0, sum = 3
6919 10:02:15.393182 16, 0x0, sum = 4
6920 10:02:15.393279 best_step = 14
6921 10:02:15.393364
6922 10:02:15.393455 ==
6923 10:02:15.396726 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 10:02:15.399965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 10:02:15.400037 ==
6926 10:02:15.403507 RX Vref Scan: 0
6927 10:02:15.403628
6928 10:02:15.406580 RX Vref 0 -> 0, step: 1
6929 10:02:15.406675
6930 10:02:15.406767 RX Delay -311 -> 252, step: 8
6931 10:02:15.415528 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6932 10:02:15.418833 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6933 10:02:15.421960 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6934 10:02:15.425183 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6935 10:02:15.431775 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6936 10:02:15.435533 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6937 10:02:15.438520 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6938 10:02:15.442071 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6939 10:02:15.448408 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6940 10:02:15.451738 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6941 10:02:15.455550 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6942 10:02:15.458904 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6943 10:02:15.465354 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6944 10:02:15.468415 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6945 10:02:15.471762 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6946 10:02:15.475007 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6947 10:02:15.478664 ==
6948 10:02:15.481837 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 10:02:15.485025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 10:02:15.485109 ==
6951 10:02:15.485190 DQS Delay:
6952 10:02:15.488334 DQS0 = 28, DQS1 = 36
6953 10:02:15.488432 DQM Delay:
6954 10:02:15.492242 DQM0 = 11, DQM1 = 15
6955 10:02:15.492325 DQ Delay:
6956 10:02:15.495511 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6957 10:02:15.498676 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6958 10:02:15.501689 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6959 10:02:15.505191 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6960 10:02:15.505287
6961 10:02:15.505372
6962 10:02:15.511654 [DQSOSCAuto] RK1, (LSB)MR18= 0xcd5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6963 10:02:15.515387 CH1 RK1: MR19=C0C, MR18=CD5C
6964 10:02:15.521604 CH1_RK1: MR19=0xC0C, MR18=0xCD5C, DQSOSC=384, MR23=63, INC=400, DEC=267
6965 10:02:15.525235 [RxdqsGatingPostProcess] freq 400
6966 10:02:15.528267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6967 10:02:15.531751 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 10:02:15.535303 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 10:02:15.538609 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 10:02:15.541852 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 10:02:15.544868 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 10:02:15.548839 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 10:02:15.551745 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 10:02:15.555366 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 10:02:15.558246 Pre-setting of DQS Precalculation
6976 10:02:15.562086 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6977 10:02:15.571805 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6978 10:02:15.578361 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6979 10:02:15.578445
6980 10:02:15.578528
6981 10:02:15.582221 [Calibration Summary] 800 Mbps
6982 10:02:15.582304 CH 0, Rank 0
6983 10:02:15.585471 SW Impedance : PASS
6984 10:02:15.585555 DUTY Scan : NO K
6985 10:02:15.588638 ZQ Calibration : PASS
6986 10:02:15.591767 Jitter Meter : NO K
6987 10:02:15.591849 CBT Training : PASS
6988 10:02:15.594957 Write leveling : PASS
6989 10:02:15.598187 RX DQS gating : PASS
6990 10:02:15.598384 RX DQ/DQS(RDDQC) : PASS
6991 10:02:15.601962 TX DQ/DQS : PASS
6992 10:02:15.605276 RX DATLAT : PASS
6993 10:02:15.605371 RX DQ/DQS(Engine): PASS
6994 10:02:15.608336 TX OE : NO K
6995 10:02:15.608477 All Pass.
6996 10:02:15.608567
6997 10:02:15.608654 CH 0, Rank 1
6998 10:02:15.611429 SW Impedance : PASS
6999 10:02:15.615056 DUTY Scan : NO K
7000 10:02:15.615191 ZQ Calibration : PASS
7001 10:02:15.618493 Jitter Meter : NO K
7002 10:02:15.621604 CBT Training : PASS
7003 10:02:15.621684 Write leveling : NO K
7004 10:02:15.625118 RX DQS gating : PASS
7005 10:02:15.628365 RX DQ/DQS(RDDQC) : PASS
7006 10:02:15.628445 TX DQ/DQS : PASS
7007 10:02:15.631497 RX DATLAT : PASS
7008 10:02:15.635369 RX DQ/DQS(Engine): PASS
7009 10:02:15.635472 TX OE : NO K
7010 10:02:15.638401 All Pass.
7011 10:02:15.638474
7012 10:02:15.638543 CH 1, Rank 0
7013 10:02:15.642024 SW Impedance : PASS
7014 10:02:15.642110 DUTY Scan : NO K
7015 10:02:15.644909 ZQ Calibration : PASS
7016 10:02:15.644979 Jitter Meter : NO K
7017 10:02:15.648478 CBT Training : PASS
7018 10:02:15.651507 Write leveling : PASS
7019 10:02:15.651654 RX DQS gating : PASS
7020 10:02:15.655323 RX DQ/DQS(RDDQC) : PASS
7021 10:02:15.658491 TX DQ/DQS : PASS
7022 10:02:15.658565 RX DATLAT : PASS
7023 10:02:15.661537 RX DQ/DQS(Engine): PASS
7024 10:02:15.665230 TX OE : NO K
7025 10:02:15.665304 All Pass.
7026 10:02:15.665364
7027 10:02:15.665428 CH 1, Rank 1
7028 10:02:15.668384 SW Impedance : PASS
7029 10:02:15.671631 DUTY Scan : NO K
7030 10:02:15.671743 ZQ Calibration : PASS
7031 10:02:15.674696 Jitter Meter : NO K
7032 10:02:15.677953 CBT Training : PASS
7033 10:02:15.678025 Write leveling : NO K
7034 10:02:15.681743 RX DQS gating : PASS
7035 10:02:15.684899 RX DQ/DQS(RDDQC) : PASS
7036 10:02:15.685013 TX DQ/DQS : PASS
7037 10:02:15.688152 RX DATLAT : PASS
7038 10:02:15.691356 RX DQ/DQS(Engine): PASS
7039 10:02:15.691431 TX OE : NO K
7040 10:02:15.694902 All Pass.
7041 10:02:15.695008
7042 10:02:15.695070 DramC Write-DBI off
7043 10:02:15.698339 PER_BANK_REFRESH: Hybrid Mode
7044 10:02:15.698413 TX_TRACKING: ON
7045 10:02:15.707921 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7046 10:02:15.711099 [FAST_K] Save calibration result to emmc
7047 10:02:15.714427 dramc_set_vcore_voltage set vcore to 725000
7048 10:02:15.718189 Read voltage for 1600, 0
7049 10:02:15.718264 Vio18 = 0
7050 10:02:15.721372 Vcore = 725000
7051 10:02:15.721444 Vdram = 0
7052 10:02:15.721513 Vddq = 0
7053 10:02:15.724565 Vmddr = 0
7054 10:02:15.728147 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7055 10:02:15.734520 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7056 10:02:15.734600 MEM_TYPE=3, freq_sel=13
7057 10:02:15.737866 sv_algorithm_assistance_LP4_3733
7058 10:02:15.741142 ============ PULL DRAM RESETB DOWN ============
7059 10:02:15.747845 ========== PULL DRAM RESETB DOWN end =========
7060 10:02:15.750855 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7061 10:02:15.754570 ===================================
7062 10:02:15.757884 LPDDR4 DRAM CONFIGURATION
7063 10:02:15.760927 ===================================
7064 10:02:15.761009 EX_ROW_EN[0] = 0x0
7065 10:02:15.764458 EX_ROW_EN[1] = 0x0
7066 10:02:15.767782 LP4Y_EN = 0x0
7067 10:02:15.767864 WORK_FSP = 0x1
7068 10:02:15.770720 WL = 0x5
7069 10:02:15.770803 RL = 0x5
7070 10:02:15.774406 BL = 0x2
7071 10:02:15.774514 RPST = 0x0
7072 10:02:15.777625 RD_PRE = 0x0
7073 10:02:15.777732 WR_PRE = 0x1
7074 10:02:15.781327 WR_PST = 0x1
7075 10:02:15.781431 DBI_WR = 0x0
7076 10:02:15.784588 DBI_RD = 0x0
7077 10:02:15.784660 OTF = 0x1
7078 10:02:15.787716 ===================================
7079 10:02:15.790888 ===================================
7080 10:02:15.794253 ANA top config
7081 10:02:15.797933 ===================================
7082 10:02:15.798031 DLL_ASYNC_EN = 0
7083 10:02:15.801099 ALL_SLAVE_EN = 0
7084 10:02:15.804326 NEW_RANK_MODE = 1
7085 10:02:15.807542 DLL_IDLE_MODE = 1
7086 10:02:15.807640 LP45_APHY_COMB_EN = 1
7087 10:02:15.810765 TX_ODT_DIS = 0
7088 10:02:15.814659 NEW_8X_MODE = 1
7089 10:02:15.817966 ===================================
7090 10:02:15.821073 ===================================
7091 10:02:15.824307 data_rate = 3200
7092 10:02:15.827508 CKR = 1
7093 10:02:15.830693 DQ_P2S_RATIO = 8
7094 10:02:15.834006 ===================================
7095 10:02:15.834115 CA_P2S_RATIO = 8
7096 10:02:15.837761 DQ_CA_OPEN = 0
7097 10:02:15.840820 DQ_SEMI_OPEN = 0
7098 10:02:15.844031 CA_SEMI_OPEN = 0
7099 10:02:15.847324 CA_FULL_RATE = 0
7100 10:02:15.850609 DQ_CKDIV4_EN = 0
7101 10:02:15.850687 CA_CKDIV4_EN = 0
7102 10:02:15.853824 CA_PREDIV_EN = 0
7103 10:02:15.857591 PH8_DLY = 12
7104 10:02:15.860579 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7105 10:02:15.864239 DQ_AAMCK_DIV = 4
7106 10:02:15.867430 CA_AAMCK_DIV = 4
7107 10:02:15.867507 CA_ADMCK_DIV = 4
7108 10:02:15.870687 DQ_TRACK_CA_EN = 0
7109 10:02:15.873888 CA_PICK = 1600
7110 10:02:15.877458 CA_MCKIO = 1600
7111 10:02:15.880650 MCKIO_SEMI = 0
7112 10:02:15.883980 PLL_FREQ = 3068
7113 10:02:15.887463 DQ_UI_PI_RATIO = 32
7114 10:02:15.887548 CA_UI_PI_RATIO = 0
7115 10:02:15.890396 ===================================
7116 10:02:15.893757 ===================================
7117 10:02:15.897023 memory_type:LPDDR4
7118 10:02:15.900225 GP_NUM : 10
7119 10:02:15.900310 SRAM_EN : 1
7120 10:02:15.904048 MD32_EN : 0
7121 10:02:15.907111 ===================================
7122 10:02:15.910273 [ANA_INIT] >>>>>>>>>>>>>>
7123 10:02:15.914087 <<<<<< [CONFIGURE PHASE]: ANA_TX
7124 10:02:15.917508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7125 10:02:15.920783 ===================================
7126 10:02:15.920868 data_rate = 3200,PCW = 0X7600
7127 10:02:15.924074 ===================================
7128 10:02:15.927228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7129 10:02:15.933759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 10:02:15.940434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 10:02:15.943700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7132 10:02:15.946909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7133 10:02:15.950787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7134 10:02:15.953833 [ANA_INIT] flow start
7135 10:02:15.957026 [ANA_INIT] PLL >>>>>>>>
7136 10:02:15.957110 [ANA_INIT] PLL <<<<<<<<
7137 10:02:15.960337 [ANA_INIT] MIDPI >>>>>>>>
7138 10:02:15.963695 [ANA_INIT] MIDPI <<<<<<<<
7139 10:02:15.963780 [ANA_INIT] DLL >>>>>>>>
7140 10:02:15.966711 [ANA_INIT] DLL <<<<<<<<
7141 10:02:15.970661 [ANA_INIT] flow end
7142 10:02:15.973415 ============ LP4 DIFF to SE enter ============
7143 10:02:15.977186 ============ LP4 DIFF to SE exit ============
7144 10:02:15.980400 [ANA_INIT] <<<<<<<<<<<<<
7145 10:02:15.983530 [Flow] Enable top DCM control >>>>>
7146 10:02:15.987270 [Flow] Enable top DCM control <<<<<
7147 10:02:15.990355 Enable DLL master slave shuffle
7148 10:02:15.993957 ==============================================================
7149 10:02:15.996872 Gating Mode config
7150 10:02:16.000411 ==============================================================
7151 10:02:16.003547 Config description:
7152 10:02:16.013677 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7153 10:02:16.020093 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7154 10:02:16.023431 SELPH_MODE 0: By rank 1: By Phase
7155 10:02:16.030481 ==============================================================
7156 10:02:16.033746 GAT_TRACK_EN = 1
7157 10:02:16.037073 RX_GATING_MODE = 2
7158 10:02:16.040396 RX_GATING_TRACK_MODE = 2
7159 10:02:16.043786 SELPH_MODE = 1
7160 10:02:16.047049 PICG_EARLY_EN = 1
7161 10:02:16.047123 VALID_LAT_VALUE = 1
7162 10:02:16.053505 ==============================================================
7163 10:02:16.056690 Enter into Gating configuration >>>>
7164 10:02:16.059923 Exit from Gating configuration <<<<
7165 10:02:16.063245 Enter into DVFS_PRE_config >>>>>
7166 10:02:16.073787 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7167 10:02:16.077157 Exit from DVFS_PRE_config <<<<<
7168 10:02:16.079992 Enter into PICG configuration >>>>
7169 10:02:16.083426 Exit from PICG configuration <<<<
7170 10:02:16.086897 [RX_INPUT] configuration >>>>>
7171 10:02:16.090480 [RX_INPUT] configuration <<<<<
7172 10:02:16.093497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7173 10:02:16.099941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7174 10:02:16.106886 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 10:02:16.113315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 10:02:16.120364 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 10:02:16.123326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 10:02:16.130470 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7179 10:02:16.133479 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7180 10:02:16.136642 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7181 10:02:16.140484 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7182 10:02:16.146989 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7183 10:02:16.150296 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7184 10:02:16.153329 ===================================
7185 10:02:16.156530 LPDDR4 DRAM CONFIGURATION
7186 10:02:16.160335 ===================================
7187 10:02:16.160416 EX_ROW_EN[0] = 0x0
7188 10:02:16.163451 EX_ROW_EN[1] = 0x0
7189 10:02:16.163557 LP4Y_EN = 0x0
7190 10:02:16.166727 WORK_FSP = 0x1
7191 10:02:16.166808 WL = 0x5
7192 10:02:16.170044 RL = 0x5
7193 10:02:16.170125 BL = 0x2
7194 10:02:16.173150 RPST = 0x0
7195 10:02:16.173230 RD_PRE = 0x0
7196 10:02:16.176822 WR_PRE = 0x1
7197 10:02:16.176902 WR_PST = 0x1
7198 10:02:16.179758 DBI_WR = 0x0
7199 10:02:16.183522 DBI_RD = 0x0
7200 10:02:16.183632 OTF = 0x1
7201 10:02:16.186603 ===================================
7202 10:02:16.189660 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7203 10:02:16.193176 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7204 10:02:16.200033 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 10:02:16.203439 ===================================
7206 10:02:16.206515 LPDDR4 DRAM CONFIGURATION
7207 10:02:16.209709 ===================================
7208 10:02:16.209792 EX_ROW_EN[0] = 0x10
7209 10:02:16.213435 EX_ROW_EN[1] = 0x0
7210 10:02:16.213517 LP4Y_EN = 0x0
7211 10:02:16.216708 WORK_FSP = 0x1
7212 10:02:16.216791 WL = 0x5
7213 10:02:16.219817 RL = 0x5
7214 10:02:16.219899 BL = 0x2
7215 10:02:16.222930 RPST = 0x0
7216 10:02:16.223012 RD_PRE = 0x0
7217 10:02:16.226523 WR_PRE = 0x1
7218 10:02:16.226605 WR_PST = 0x1
7219 10:02:16.230080 DBI_WR = 0x0
7220 10:02:16.230193 DBI_RD = 0x0
7221 10:02:16.233176 OTF = 0x1
7222 10:02:16.236511 ===================================
7223 10:02:16.242889 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7224 10:02:16.242972 ==
7225 10:02:16.246163 Dram Type= 6, Freq= 0, CH_0, rank 0
7226 10:02:16.250024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7227 10:02:16.250107 ==
7228 10:02:16.253172 [Duty_Offset_Calibration]
7229 10:02:16.253254 B0:2 B1:1 CA:1
7230 10:02:16.253353
7231 10:02:16.256410 [DutyScan_Calibration_Flow] k_type=0
7232 10:02:16.267203
7233 10:02:16.267309 ==CLK 0==
7234 10:02:16.270513 Final CLK duty delay cell = 0
7235 10:02:16.273791 [0] MAX Duty = 5156%(X100), DQS PI = 22
7236 10:02:16.277683 [0] MIN Duty = 4907%(X100), DQS PI = 0
7237 10:02:16.277766 [0] AVG Duty = 5031%(X100)
7238 10:02:16.280896
7239 10:02:16.284072 CH0 CLK Duty spec in!! Max-Min= 249%
7240 10:02:16.287742 [DutyScan_Calibration_Flow] ====Done====
7241 10:02:16.287822
7242 10:02:16.290622 [DutyScan_Calibration_Flow] k_type=1
7243 10:02:16.306708
7244 10:02:16.306792 ==DQS 0 ==
7245 10:02:16.309659 Final DQS duty delay cell = -4
7246 10:02:16.312954 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7247 10:02:16.316400 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7248 10:02:16.319565 [-4] AVG Duty = 4891%(X100)
7249 10:02:16.319711
7250 10:02:16.319799 ==DQS 1 ==
7251 10:02:16.323341 Final DQS duty delay cell = 0
7252 10:02:16.326612 [0] MAX Duty = 5187%(X100), DQS PI = 4
7253 10:02:16.329838 [0] MIN Duty = 5031%(X100), DQS PI = 52
7254 10:02:16.333235 [0] AVG Duty = 5109%(X100)
7255 10:02:16.333318
7256 10:02:16.336391 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7257 10:02:16.336473
7258 10:02:16.339721 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7259 10:02:16.343280 [DutyScan_Calibration_Flow] ====Done====
7260 10:02:16.343362
7261 10:02:16.346263 [DutyScan_Calibration_Flow] k_type=3
7262 10:02:16.363184
7263 10:02:16.363267 ==DQM 0 ==
7264 10:02:16.366324 Final DQM duty delay cell = 0
7265 10:02:16.369473 [0] MAX Duty = 5218%(X100), DQS PI = 34
7266 10:02:16.372695 [0] MIN Duty = 4907%(X100), DQS PI = 54
7267 10:02:16.376614 [0] AVG Duty = 5062%(X100)
7268 10:02:16.376695
7269 10:02:16.376758 ==DQM 1 ==
7270 10:02:16.379869 Final DQM duty delay cell = -4
7271 10:02:16.383198 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7272 10:02:16.386367 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7273 10:02:16.389659 [-4] AVG Duty = 4922%(X100)
7274 10:02:16.389739
7275 10:02:16.392798 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7276 10:02:16.392878
7277 10:02:16.396419 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7278 10:02:16.399369 [DutyScan_Calibration_Flow] ====Done====
7279 10:02:16.399475
7280 10:02:16.402641 [DutyScan_Calibration_Flow] k_type=2
7281 10:02:16.420822
7282 10:02:16.420903 ==DQ 0 ==
7283 10:02:16.423689 Final DQ duty delay cell = 0
7284 10:02:16.427474 [0] MAX Duty = 5062%(X100), DQS PI = 24
7285 10:02:16.430923 [0] MIN Duty = 4907%(X100), DQS PI = 0
7286 10:02:16.431002 [0] AVG Duty = 4984%(X100)
7287 10:02:16.433866
7288 10:02:16.433944 ==DQ 1 ==
7289 10:02:16.437177 Final DQ duty delay cell = 0
7290 10:02:16.440834 [0] MAX Duty = 5125%(X100), DQS PI = 6
7291 10:02:16.444016 [0] MIN Duty = 4938%(X100), DQS PI = 34
7292 10:02:16.444091 [0] AVG Duty = 5031%(X100)
7293 10:02:16.444152
7294 10:02:16.447285 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7295 10:02:16.450628
7296 10:02:16.450709 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7297 10:02:16.457506 [DutyScan_Calibration_Flow] ====Done====
7298 10:02:16.457587 ==
7299 10:02:16.460440 Dram Type= 6, Freq= 0, CH_1, rank 0
7300 10:02:16.463807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7301 10:02:16.463889 ==
7302 10:02:16.467400 [Duty_Offset_Calibration]
7303 10:02:16.467506 B0:1 B1:0 CA:0
7304 10:02:16.467639
7305 10:02:16.470589 [DutyScan_Calibration_Flow] k_type=0
7306 10:02:16.479805
7307 10:02:16.479884 ==CLK 0==
7308 10:02:16.483551 Final CLK duty delay cell = -4
7309 10:02:16.486863 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7310 10:02:16.489903 [-4] MIN Duty = 4875%(X100), DQS PI = 50
7311 10:02:16.493145 [-4] AVG Duty = 4937%(X100)
7312 10:02:16.493225
7313 10:02:16.496409 CH1 CLK Duty spec in!! Max-Min= 125%
7314 10:02:16.499779 [DutyScan_Calibration_Flow] ====Done====
7315 10:02:16.499859
7316 10:02:16.503086 [DutyScan_Calibration_Flow] k_type=1
7317 10:02:16.520406
7318 10:02:16.520488 ==DQS 0 ==
7319 10:02:16.523710 Final DQS duty delay cell = 0
7320 10:02:16.526952 [0] MAX Duty = 5094%(X100), DQS PI = 14
7321 10:02:16.530115 [0] MIN Duty = 4875%(X100), DQS PI = 0
7322 10:02:16.530199 [0] AVG Duty = 4984%(X100)
7323 10:02:16.533162
7324 10:02:16.533241 ==DQS 1 ==
7325 10:02:16.536690 Final DQS duty delay cell = 0
7326 10:02:16.539573 [0] MAX Duty = 5249%(X100), DQS PI = 18
7327 10:02:16.543467 [0] MIN Duty = 4938%(X100), DQS PI = 8
7328 10:02:16.543573 [0] AVG Duty = 5093%(X100)
7329 10:02:16.546565
7330 10:02:16.549874 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7331 10:02:16.549953
7332 10:02:16.552971 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7333 10:02:16.556836 [DutyScan_Calibration_Flow] ====Done====
7334 10:02:16.556914
7335 10:02:16.559436 [DutyScan_Calibration_Flow] k_type=3
7336 10:02:16.576495
7337 10:02:16.576570 ==DQM 0 ==
7338 10:02:16.580239 Final DQM duty delay cell = 0
7339 10:02:16.583430 [0] MAX Duty = 5218%(X100), DQS PI = 18
7340 10:02:16.586750 [0] MIN Duty = 4969%(X100), DQS PI = 48
7341 10:02:16.590026 [0] AVG Duty = 5093%(X100)
7342 10:02:16.590103
7343 10:02:16.590163 ==DQM 1 ==
7344 10:02:16.593117 Final DQM duty delay cell = 0
7345 10:02:16.596967 [0] MAX Duty = 5093%(X100), DQS PI = 16
7346 10:02:16.600139 [0] MIN Duty = 4907%(X100), DQS PI = 52
7347 10:02:16.603439 [0] AVG Duty = 5000%(X100)
7348 10:02:16.603518
7349 10:02:16.606672 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7350 10:02:16.606749
7351 10:02:16.609796 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7352 10:02:16.613658 [DutyScan_Calibration_Flow] ====Done====
7353 10:02:16.613738
7354 10:02:16.616728 [DutyScan_Calibration_Flow] k_type=2
7355 10:02:16.632927
7356 10:02:16.633011 ==DQ 0 ==
7357 10:02:16.636174 Final DQ duty delay cell = -4
7358 10:02:16.639999 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7359 10:02:16.643291 [-4] MIN Duty = 4875%(X100), DQS PI = 48
7360 10:02:16.646487 [-4] AVG Duty = 4968%(X100)
7361 10:02:16.646568
7362 10:02:16.646632 ==DQ 1 ==
7363 10:02:16.649390 Final DQ duty delay cell = 0
7364 10:02:16.653161 [0] MAX Duty = 5093%(X100), DQS PI = 16
7365 10:02:16.656191 [0] MIN Duty = 4938%(X100), DQS PI = 8
7366 10:02:16.656273 [0] AVG Duty = 5015%(X100)
7367 10:02:16.656336
7368 10:02:16.662973 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7369 10:02:16.663054
7370 10:02:16.666639 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7371 10:02:16.669879 [DutyScan_Calibration_Flow] ====Done====
7372 10:02:16.673055 nWR fixed to 30
7373 10:02:16.673129 [ModeRegInit_LP4] CH0 RK0
7374 10:02:16.676110 [ModeRegInit_LP4] CH0 RK1
7375 10:02:16.679850 [ModeRegInit_LP4] CH1 RK0
7376 10:02:16.682985 [ModeRegInit_LP4] CH1 RK1
7377 10:02:16.683055 match AC timing 5
7378 10:02:16.686491 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7379 10:02:16.692822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7380 10:02:16.695932 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7381 10:02:16.702647 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7382 10:02:16.706533 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7383 10:02:16.706616 [MiockJmeterHQA]
7384 10:02:16.706678
7385 10:02:16.709778 [DramcMiockJmeter] u1RxGatingPI = 0
7386 10:02:16.712940 0 : 4255, 4027
7387 10:02:16.713008 4 : 4252, 4027
7388 10:02:16.713067 8 : 4252, 4027
7389 10:02:16.716154 12 : 4252, 4027
7390 10:02:16.716218 16 : 4253, 4027
7391 10:02:16.719471 20 : 4252, 4027
7392 10:02:16.719534 24 : 4255, 4029
7393 10:02:16.723068 28 : 4252, 4027
7394 10:02:16.723132 32 : 4253, 4026
7395 10:02:16.726072 36 : 4365, 4140
7396 10:02:16.726135 40 : 4253, 4026
7397 10:02:16.726191 44 : 4255, 4030
7398 10:02:16.729642 48 : 4252, 4027
7399 10:02:16.729706 52 : 4363, 4137
7400 10:02:16.733238 56 : 4250, 4027
7401 10:02:16.733318 60 : 4360, 4137
7402 10:02:16.736605 64 : 4255, 4029
7403 10:02:16.736671 68 : 4250, 4027
7404 10:02:16.736729 72 : 4252, 4027
7405 10:02:16.739866 76 : 4253, 4029
7406 10:02:16.739929 80 : 4360, 4137
7407 10:02:16.743111 84 : 4250, 4026
7408 10:02:16.743179 88 : 4361, 266
7409 10:02:16.746332 92 : 4250, 0
7410 10:02:16.746403 96 : 4361, 0
7411 10:02:16.746460 100 : 4252, 0
7412 10:02:16.749709 104 : 4253, 0
7413 10:02:16.749775 108 : 4361, 0
7414 10:02:16.749838 112 : 4360, 0
7415 10:02:16.752807 116 : 4250, 0
7416 10:02:16.752896 120 : 4250, 0
7417 10:02:16.756019 124 : 4360, 0
7418 10:02:16.756092 128 : 4360, 0
7419 10:02:16.756158 132 : 4250, 0
7420 10:02:16.759435 136 : 4250, 0
7421 10:02:16.759515 140 : 4250, 0
7422 10:02:16.763307 144 : 4252, 0
7423 10:02:16.763374 148 : 4250, 0
7424 10:02:16.763431 152 : 4250, 0
7425 10:02:16.766396 156 : 4252, 0
7426 10:02:16.766460 160 : 4361, 0
7427 10:02:16.769482 164 : 4361, 0
7428 10:02:16.769547 168 : 4250, 0
7429 10:02:16.769604 172 : 4250, 0
7430 10:02:16.773068 176 : 4360, 0
7431 10:02:16.773142 180 : 4361, 0
7432 10:02:16.773199 184 : 4250, 0
7433 10:02:16.776529 188 : 4250, 0
7434 10:02:16.776606 192 : 4250, 0
7435 10:02:16.779478 196 : 4252, 0
7436 10:02:16.779543 200 : 4250, 0
7437 10:02:16.779625 204 : 4250, 991
7438 10:02:16.783200 208 : 4250, 3915
7439 10:02:16.783264 212 : 4250, 4026
7440 10:02:16.786263 216 : 4250, 4027
7441 10:02:16.786334 220 : 4361, 4138
7442 10:02:16.789348 224 : 4360, 4137
7443 10:02:16.789440 228 : 4250, 4027
7444 10:02:16.792932 232 : 4363, 4140
7445 10:02:16.792999 236 : 4250, 4026
7446 10:02:16.796404 240 : 4250, 4027
7447 10:02:16.796475 244 : 4250, 4026
7448 10:02:16.799321 248 : 4253, 4029
7449 10:02:16.799386 252 : 4250, 4027
7450 10:02:16.802604 256 : 4250, 4027
7451 10:02:16.802676 260 : 4250, 4026
7452 10:02:16.802736 264 : 4253, 4029
7453 10:02:16.806384 268 : 4250, 4027
7454 10:02:16.806466 272 : 4361, 4138
7455 10:02:16.809740 276 : 4360, 4137
7456 10:02:16.809822 280 : 4250, 4027
7457 10:02:16.812982 284 : 4364, 4140
7458 10:02:16.813064 288 : 4250, 4026
7459 10:02:16.816344 292 : 4250, 4027
7460 10:02:16.816426 296 : 4250, 4026
7461 10:02:16.819632 300 : 4253, 4029
7462 10:02:16.819714 304 : 4250, 4027
7463 10:02:16.822784 308 : 4250, 3997
7464 10:02:16.822865 312 : 4250, 2219
7465 10:02:16.822930 316 : 4253, 10
7466 10:02:16.825964
7467 10:02:16.826044 MIOCK jitter meter ch=0
7468 10:02:16.826131
7469 10:02:16.829818 1T = (316-88) = 228 dly cells
7470 10:02:16.836256 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7471 10:02:16.836338 ==
7472 10:02:16.839372 Dram Type= 6, Freq= 0, CH_0, rank 0
7473 10:02:16.842928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7474 10:02:16.843009 ==
7475 10:02:16.849835 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7476 10:02:16.852478 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7477 10:02:16.856271 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7478 10:02:16.862602 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7479 10:02:16.871599 [CA 0] Center 43 (13~74) winsize 62
7480 10:02:16.875399 [CA 1] Center 43 (12~74) winsize 63
7481 10:02:16.878601 [CA 2] Center 38 (9~68) winsize 60
7482 10:02:16.881675 [CA 3] Center 38 (8~68) winsize 61
7483 10:02:16.885030 [CA 4] Center 36 (7~66) winsize 60
7484 10:02:16.888497 [CA 5] Center 36 (7~65) winsize 59
7485 10:02:16.888603
7486 10:02:16.891976 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7487 10:02:16.892057
7488 10:02:16.894981 [CATrainingPosCal] consider 1 rank data
7489 10:02:16.898601 u2DelayCellTimex100 = 285/100 ps
7490 10:02:16.901821 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7491 10:02:16.908384 CA1 delay=43 (12~74),Diff = 7 PI (23 cell)
7492 10:02:16.911747 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7493 10:02:16.915310 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7494 10:02:16.918574 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7495 10:02:16.921875 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7496 10:02:16.921956
7497 10:02:16.925032 CA PerBit enable=1, Macro0, CA PI delay=36
7498 10:02:16.925113
7499 10:02:16.928321 [CBTSetCACLKResult] CA Dly = 36
7500 10:02:16.931467 CS Dly: 9 (0~40)
7501 10:02:16.934655 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7502 10:02:16.938324 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7503 10:02:16.938405 ==
7504 10:02:16.941374 Dram Type= 6, Freq= 0, CH_0, rank 1
7505 10:02:16.944618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 10:02:16.944700 ==
7507 10:02:16.951240 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 10:02:16.954965 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 10:02:16.961428 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 10:02:16.964591 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 10:02:16.974823 [CA 0] Center 42 (12~73) winsize 62
7512 10:02:16.978648 [CA 1] Center 42 (12~73) winsize 62
7513 10:02:16.981935 [CA 2] Center 38 (8~68) winsize 61
7514 10:02:16.985047 [CA 3] Center 38 (8~68) winsize 61
7515 10:02:16.988159 [CA 4] Center 35 (5~65) winsize 61
7516 10:02:16.991997 [CA 5] Center 35 (5~65) winsize 61
7517 10:02:16.992078
7518 10:02:16.995143 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7519 10:02:16.995224
7520 10:02:16.998014 [CATrainingPosCal] consider 2 rank data
7521 10:02:17.001477 u2DelayCellTimex100 = 285/100 ps
7522 10:02:17.005123 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7523 10:02:17.011283 CA1 delay=42 (12~73),Diff = 6 PI (20 cell)
7524 10:02:17.015095 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7525 10:02:17.018169 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7526 10:02:17.021738 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7527 10:02:17.024797 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7528 10:02:17.024878
7529 10:02:17.027963 CA PerBit enable=1, Macro0, CA PI delay=36
7530 10:02:17.028071
7531 10:02:17.031274 [CBTSetCACLKResult] CA Dly = 36
7532 10:02:17.034559 CS Dly: 10 (0~42)
7533 10:02:17.037846 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 10:02:17.041687 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 10:02:17.041759
7536 10:02:17.045193 ----->DramcWriteLeveling(PI) begin...
7537 10:02:17.045265 ==
7538 10:02:17.048019 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 10:02:17.051338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 10:02:17.054597 ==
7541 10:02:17.054674 Write leveling (Byte 0): 36 => 36
7542 10:02:17.058140 Write leveling (Byte 1): 28 => 28
7543 10:02:17.061571 DramcWriteLeveling(PI) end<-----
7544 10:02:17.061638
7545 10:02:17.061696 ==
7546 10:02:17.064673 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 10:02:17.071048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 10:02:17.071120 ==
7549 10:02:17.074401 [Gating] SW mode calibration
7550 10:02:17.081524 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7551 10:02:17.084795 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7552 10:02:17.091208 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 10:02:17.094988 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 10:02:17.098276 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7555 10:02:17.101711 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7556 10:02:17.107839 1 4 16 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
7557 10:02:17.111472 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7558 10:02:17.114509 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 10:02:17.121639 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 10:02:17.124650 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7561 10:02:17.127768 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 10:02:17.134483 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7563 10:02:17.138089 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7564 10:02:17.141002 1 5 16 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
7565 10:02:17.148075 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7566 10:02:17.151123 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7567 10:02:17.154253 1 5 28 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7568 10:02:17.161429 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7569 10:02:17.164586 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 10:02:17.167561 1 6 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7571 10:02:17.174449 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7572 10:02:17.177634 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7573 10:02:17.180767 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 10:02:17.187980 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 10:02:17.191454 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 10:02:17.194600 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 10:02:17.201078 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 10:02:17.204347 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 10:02:17.207620 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7580 10:02:17.214445 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7581 10:02:17.217676 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 10:02:17.220826 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 10:02:17.224365 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 10:02:17.231180 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 10:02:17.234199 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 10:02:17.237779 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 10:02:17.244579 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 10:02:17.247772 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 10:02:17.251066 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 10:02:17.257733 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 10:02:17.261403 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 10:02:17.264527 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 10:02:17.270913 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 10:02:17.274688 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 10:02:17.277552 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7596 10:02:17.284367 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 10:02:17.284448 Total UI for P1: 0, mck2ui 16
7598 10:02:17.290779 best dqsien dly found for B0: ( 1, 9, 10)
7599 10:02:17.294089 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 10:02:17.297356 Total UI for P1: 0, mck2ui 16
7601 10:02:17.301063 best dqsien dly found for B1: ( 1, 9, 16)
7602 10:02:17.304379 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7603 10:02:17.307712 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7604 10:02:17.307793
7605 10:02:17.310930 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7606 10:02:17.314223 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7607 10:02:17.317325 [Gating] SW calibration Done
7608 10:02:17.317402 ==
7609 10:02:17.321195 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 10:02:17.324462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 10:02:17.327823 ==
7612 10:02:17.327894 RX Vref Scan: 0
7613 10:02:17.327953
7614 10:02:17.330731 RX Vref 0 -> 0, step: 1
7615 10:02:17.330801
7616 10:02:17.330858 RX Delay 0 -> 252, step: 8
7617 10:02:17.337551 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7618 10:02:17.340675 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7619 10:02:17.344343 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7620 10:02:17.347467 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7621 10:02:17.350743 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7622 10:02:17.357886 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7623 10:02:17.360928 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7624 10:02:17.364135 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7625 10:02:17.367095 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7626 10:02:17.370688 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7627 10:02:17.377657 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7628 10:02:17.380816 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7629 10:02:17.384079 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7630 10:02:17.387081 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7631 10:02:17.390495 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7632 10:02:17.397341 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7633 10:02:17.397415 ==
7634 10:02:17.400678 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 10:02:17.404062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 10:02:17.404135 ==
7637 10:02:17.404195 DQS Delay:
7638 10:02:17.407219 DQS0 = 0, DQS1 = 0
7639 10:02:17.407290 DQM Delay:
7640 10:02:17.411036 DQM0 = 137, DQM1 = 130
7641 10:02:17.411102 DQ Delay:
7642 10:02:17.413754 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7643 10:02:17.417713 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7644 10:02:17.420706 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7645 10:02:17.424542 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7646 10:02:17.424606
7647 10:02:17.424663
7648 10:02:17.427913 ==
7649 10:02:17.430951 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 10:02:17.434222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 10:02:17.434293 ==
7652 10:02:17.434359
7653 10:02:17.434415
7654 10:02:17.437267 TX Vref Scan disable
7655 10:02:17.437335 == TX Byte 0 ==
7656 10:02:17.440458 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7657 10:02:17.447518 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7658 10:02:17.447605 == TX Byte 1 ==
7659 10:02:17.453789 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7660 10:02:17.457047 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7661 10:02:17.457127 ==
7662 10:02:17.460367 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 10:02:17.463578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 10:02:17.463680 ==
7665 10:02:17.477706
7666 10:02:17.481395 TX Vref early break, caculate TX vref
7667 10:02:17.484453 TX Vref=16, minBit 0, minWin=23, winSum=380
7668 10:02:17.487989 TX Vref=18, minBit 0, minWin=23, winSum=387
7669 10:02:17.490967 TX Vref=20, minBit 4, minWin=23, winSum=401
7670 10:02:17.494376 TX Vref=22, minBit 3, minWin=24, winSum=409
7671 10:02:17.498116 TX Vref=24, minBit 4, minWin=24, winSum=411
7672 10:02:17.504494 TX Vref=26, minBit 0, minWin=25, winSum=423
7673 10:02:17.507852 TX Vref=28, minBit 4, minWin=25, winSum=423
7674 10:02:17.510829 TX Vref=30, minBit 1, minWin=24, winSum=411
7675 10:02:17.514576 TX Vref=32, minBit 6, minWin=23, winSum=401
7676 10:02:17.517781 TX Vref=34, minBit 1, minWin=22, winSum=390
7677 10:02:17.524137 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
7678 10:02:17.524206
7679 10:02:17.528066 Final TX Range 0 Vref 26
7680 10:02:17.528137
7681 10:02:17.528195 ==
7682 10:02:17.531361 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 10:02:17.534607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 10:02:17.534678 ==
7685 10:02:17.534736
7686 10:02:17.534791
7687 10:02:17.537778 TX Vref Scan disable
7688 10:02:17.544408 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7689 10:02:17.544473 == TX Byte 0 ==
7690 10:02:17.547594 u2DelayCellOfst[0]=10 cells (3 PI)
7691 10:02:17.550787 u2DelayCellOfst[1]=17 cells (5 PI)
7692 10:02:17.554548 u2DelayCellOfst[2]=10 cells (3 PI)
7693 10:02:17.557786 u2DelayCellOfst[3]=10 cells (3 PI)
7694 10:02:17.560805 u2DelayCellOfst[4]=6 cells (2 PI)
7695 10:02:17.564044 u2DelayCellOfst[5]=0 cells (0 PI)
7696 10:02:17.567405 u2DelayCellOfst[6]=17 cells (5 PI)
7697 10:02:17.567470 u2DelayCellOfst[7]=17 cells (5 PI)
7698 10:02:17.574577 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7699 10:02:17.577759 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7700 10:02:17.577825 == TX Byte 1 ==
7701 10:02:17.581018 u2DelayCellOfst[8]=3 cells (1 PI)
7702 10:02:17.584236 u2DelayCellOfst[9]=0 cells (0 PI)
7703 10:02:17.587337 u2DelayCellOfst[10]=6 cells (2 PI)
7704 10:02:17.590844 u2DelayCellOfst[11]=6 cells (2 PI)
7705 10:02:17.593893 u2DelayCellOfst[12]=10 cells (3 PI)
7706 10:02:17.597799 u2DelayCellOfst[13]=13 cells (4 PI)
7707 10:02:17.601009 u2DelayCellOfst[14]=13 cells (4 PI)
7708 10:02:17.604065 u2DelayCellOfst[15]=10 cells (3 PI)
7709 10:02:17.607559 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7710 10:02:17.614113 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7711 10:02:17.614220 DramC Write-DBI on
7712 10:02:17.614315 ==
7713 10:02:17.617598 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 10:02:17.620729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 10:02:17.623663 ==
7716 10:02:17.623741
7717 10:02:17.623804
7718 10:02:17.623862 TX Vref Scan disable
7719 10:02:17.627469 == TX Byte 0 ==
7720 10:02:17.630700 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7721 10:02:17.634106 == TX Byte 1 ==
7722 10:02:17.637922 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7723 10:02:17.638007 DramC Write-DBI off
7724 10:02:17.638073
7725 10:02:17.640567 [DATLAT]
7726 10:02:17.640648 Freq=1600, CH0 RK0
7727 10:02:17.640712
7728 10:02:17.643978 DATLAT Default: 0xf
7729 10:02:17.644058 0, 0xFFFF, sum = 0
7730 10:02:17.647691 1, 0xFFFF, sum = 0
7731 10:02:17.647773 2, 0xFFFF, sum = 0
7732 10:02:17.650693 3, 0xFFFF, sum = 0
7733 10:02:17.650775 4, 0xFFFF, sum = 0
7734 10:02:17.653831 5, 0xFFFF, sum = 0
7735 10:02:17.657741 6, 0xFFFF, sum = 0
7736 10:02:17.657823 7, 0xFFFF, sum = 0
7737 10:02:17.660909 8, 0xFFFF, sum = 0
7738 10:02:17.660992 9, 0xFFFF, sum = 0
7739 10:02:17.664155 10, 0xFFFF, sum = 0
7740 10:02:17.664237 11, 0xFFFF, sum = 0
7741 10:02:17.667211 12, 0xFFFF, sum = 0
7742 10:02:17.667319 13, 0xFFFF, sum = 0
7743 10:02:17.671093 14, 0x0, sum = 1
7744 10:02:17.671176 15, 0x0, sum = 2
7745 10:02:17.674428 16, 0x0, sum = 3
7746 10:02:17.674510 17, 0x0, sum = 4
7747 10:02:17.674613 best_step = 15
7748 10:02:17.677493
7749 10:02:17.677573 ==
7750 10:02:17.680672 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 10:02:17.684041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 10:02:17.684123 ==
7753 10:02:17.684186 RX Vref Scan: 1
7754 10:02:17.684246
7755 10:02:17.687856 Set Vref Range= 24 -> 127
7756 10:02:17.687937
7757 10:02:17.690615 RX Vref 24 -> 127, step: 1
7758 10:02:17.690696
7759 10:02:17.694321 RX Delay 19 -> 252, step: 4
7760 10:02:17.694401
7761 10:02:17.697806 Set Vref, RX VrefLevel [Byte0]: 24
7762 10:02:17.700991 [Byte1]: 24
7763 10:02:17.701072
7764 10:02:17.704164 Set Vref, RX VrefLevel [Byte0]: 25
7765 10:02:17.707447 [Byte1]: 25
7766 10:02:17.707553
7767 10:02:17.710627 Set Vref, RX VrefLevel [Byte0]: 26
7768 10:02:17.713677 [Byte1]: 26
7769 10:02:17.717690
7770 10:02:17.717770 Set Vref, RX VrefLevel [Byte0]: 27
7771 10:02:17.720734 [Byte1]: 27
7772 10:02:17.725011
7773 10:02:17.725091 Set Vref, RX VrefLevel [Byte0]: 28
7774 10:02:17.728453 [Byte1]: 28
7775 10:02:17.732833
7776 10:02:17.732917 Set Vref, RX VrefLevel [Byte0]: 29
7777 10:02:17.736002 [Byte1]: 29
7778 10:02:17.740742
7779 10:02:17.740822 Set Vref, RX VrefLevel [Byte0]: 30
7780 10:02:17.743756 [Byte1]: 30
7781 10:02:17.747686
7782 10:02:17.747767 Set Vref, RX VrefLevel [Byte0]: 31
7783 10:02:17.750962 [Byte1]: 31
7784 10:02:17.755182
7785 10:02:17.755262 Set Vref, RX VrefLevel [Byte0]: 32
7786 10:02:17.758801 [Byte1]: 32
7787 10:02:17.763204
7788 10:02:17.763284 Set Vref, RX VrefLevel [Byte0]: 33
7789 10:02:17.766439 [Byte1]: 33
7790 10:02:17.770832
7791 10:02:17.770912 Set Vref, RX VrefLevel [Byte0]: 34
7792 10:02:17.773919 [Byte1]: 34
7793 10:02:17.778324
7794 10:02:17.778404 Set Vref, RX VrefLevel [Byte0]: 35
7795 10:02:17.781717 [Byte1]: 35
7796 10:02:17.785620
7797 10:02:17.785700 Set Vref, RX VrefLevel [Byte0]: 36
7798 10:02:17.788892 [Byte1]: 36
7799 10:02:17.793391
7800 10:02:17.793471 Set Vref, RX VrefLevel [Byte0]: 37
7801 10:02:17.796685 [Byte1]: 37
7802 10:02:17.800651
7803 10:02:17.800731 Set Vref, RX VrefLevel [Byte0]: 38
7804 10:02:17.804175 [Byte1]: 38
7805 10:02:17.808575
7806 10:02:17.808656 Set Vref, RX VrefLevel [Byte0]: 39
7807 10:02:17.811830 [Byte1]: 39
7808 10:02:17.815802
7809 10:02:17.815882 Set Vref, RX VrefLevel [Byte0]: 40
7810 10:02:17.819631 [Byte1]: 40
7811 10:02:17.823302
7812 10:02:17.823382 Set Vref, RX VrefLevel [Byte0]: 41
7813 10:02:17.827073 [Byte1]: 41
7814 10:02:17.831111
7815 10:02:17.831192 Set Vref, RX VrefLevel [Byte0]: 42
7816 10:02:17.834289 [Byte1]: 42
7817 10:02:17.838517
7818 10:02:17.838597 Set Vref, RX VrefLevel [Byte0]: 43
7819 10:02:17.842110 [Byte1]: 43
7820 10:02:17.846335
7821 10:02:17.846415 Set Vref, RX VrefLevel [Byte0]: 44
7822 10:02:17.849382 [Byte1]: 44
7823 10:02:17.853917
7824 10:02:17.853997 Set Vref, RX VrefLevel [Byte0]: 45
7825 10:02:17.857106 [Byte1]: 45
7826 10:02:17.861448
7827 10:02:17.861529 Set Vref, RX VrefLevel [Byte0]: 46
7828 10:02:17.864593 [Byte1]: 46
7829 10:02:17.868947
7830 10:02:17.869027 Set Vref, RX VrefLevel [Byte0]: 47
7831 10:02:17.872219 [Byte1]: 47
7832 10:02:17.876678
7833 10:02:17.876758 Set Vref, RX VrefLevel [Byte0]: 48
7834 10:02:17.879762 [Byte1]: 48
7835 10:02:17.884245
7836 10:02:17.884326 Set Vref, RX VrefLevel [Byte0]: 49
7837 10:02:17.887501 [Byte1]: 49
7838 10:02:17.891953
7839 10:02:17.892035 Set Vref, RX VrefLevel [Byte0]: 50
7840 10:02:17.895143 [Byte1]: 50
7841 10:02:17.899730
7842 10:02:17.899810 Set Vref, RX VrefLevel [Byte0]: 51
7843 10:02:17.902463 [Byte1]: 51
7844 10:02:17.906977
7845 10:02:17.907057 Set Vref, RX VrefLevel [Byte0]: 52
7846 10:02:17.910064 [Byte1]: 52
7847 10:02:17.914273
7848 10:02:17.914352 Set Vref, RX VrefLevel [Byte0]: 53
7849 10:02:17.918046 [Byte1]: 53
7850 10:02:17.921946
7851 10:02:17.922027 Set Vref, RX VrefLevel [Byte0]: 54
7852 10:02:17.925145 [Byte1]: 54
7853 10:02:17.929639
7854 10:02:17.929719 Set Vref, RX VrefLevel [Byte0]: 55
7855 10:02:17.932858 [Byte1]: 55
7856 10:02:17.937187
7857 10:02:17.937267 Set Vref, RX VrefLevel [Byte0]: 56
7858 10:02:17.940297 [Byte1]: 56
7859 10:02:17.944843
7860 10:02:17.944923 Set Vref, RX VrefLevel [Byte0]: 57
7861 10:02:17.948114 [Byte1]: 57
7862 10:02:17.952112
7863 10:02:17.952192 Set Vref, RX VrefLevel [Byte0]: 58
7864 10:02:17.955790 [Byte1]: 58
7865 10:02:17.959860
7866 10:02:17.959940 Set Vref, RX VrefLevel [Byte0]: 59
7867 10:02:17.963292 [Byte1]: 59
7868 10:02:17.967569
7869 10:02:17.967687 Set Vref, RX VrefLevel [Byte0]: 60
7870 10:02:17.970716 [Byte1]: 60
7871 10:02:17.975083
7872 10:02:17.975163 Set Vref, RX VrefLevel [Byte0]: 61
7873 10:02:17.978160 [Byte1]: 61
7874 10:02:17.982537
7875 10:02:17.982617 Set Vref, RX VrefLevel [Byte0]: 62
7876 10:02:17.985833 [Byte1]: 62
7877 10:02:17.990201
7878 10:02:17.990290 Set Vref, RX VrefLevel [Byte0]: 63
7879 10:02:17.993428 [Byte1]: 63
7880 10:02:17.997887
7881 10:02:17.997982 Set Vref, RX VrefLevel [Byte0]: 64
7882 10:02:18.001205 [Byte1]: 64
7883 10:02:18.005698
7884 10:02:18.005778 Set Vref, RX VrefLevel [Byte0]: 65
7885 10:02:18.008969 [Byte1]: 65
7886 10:02:18.012831
7887 10:02:18.012911 Set Vref, RX VrefLevel [Byte0]: 66
7888 10:02:18.016004 [Byte1]: 66
7889 10:02:18.020332
7890 10:02:18.020411 Set Vref, RX VrefLevel [Byte0]: 67
7891 10:02:18.023796 [Byte1]: 67
7892 10:02:18.028358
7893 10:02:18.028436 Set Vref, RX VrefLevel [Byte0]: 68
7894 10:02:18.031632 [Byte1]: 68
7895 10:02:18.035466
7896 10:02:18.035539 Set Vref, RX VrefLevel [Byte0]: 69
7897 10:02:18.038743 [Byte1]: 69
7898 10:02:18.043391
7899 10:02:18.043473 Set Vref, RX VrefLevel [Byte0]: 70
7900 10:02:18.046614 [Byte1]: 70
7901 10:02:18.050466
7902 10:02:18.050552 Set Vref, RX VrefLevel [Byte0]: 71
7903 10:02:18.054204 [Byte1]: 71
7904 10:02:18.058210
7905 10:02:18.058292 Set Vref, RX VrefLevel [Byte0]: 72
7906 10:02:18.061746 [Byte1]: 72
7907 10:02:18.065989
7908 10:02:18.066071 Set Vref, RX VrefLevel [Byte0]: 73
7909 10:02:18.069471 [Byte1]: 73
7910 10:02:18.073269
7911 10:02:18.073350 Set Vref, RX VrefLevel [Byte0]: 74
7912 10:02:18.076672 [Byte1]: 74
7913 10:02:18.081098
7914 10:02:18.081179 Final RX Vref Byte 0 = 55 to rank0
7915 10:02:18.084346 Final RX Vref Byte 1 = 64 to rank0
7916 10:02:18.087522 Final RX Vref Byte 0 = 55 to rank1
7917 10:02:18.091305 Final RX Vref Byte 1 = 64 to rank1==
7918 10:02:18.094433 Dram Type= 6, Freq= 0, CH_0, rank 0
7919 10:02:18.101267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7920 10:02:18.101351 ==
7921 10:02:18.101435 DQS Delay:
7922 10:02:18.101532 DQS0 = 0, DQS1 = 0
7923 10:02:18.104436 DQM Delay:
7924 10:02:18.104534 DQM0 = 133, DQM1 = 128
7925 10:02:18.107768 DQ Delay:
7926 10:02:18.110982 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7927 10:02:18.114202 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7928 10:02:18.117446 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
7929 10:02:18.120726 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7930 10:02:18.120808
7931 10:02:18.120892
7932 10:02:18.120971
7933 10:02:18.124564 [DramC_TX_OE_Calibration] TA2
7934 10:02:18.127789 Original DQ_B0 (3 6) =30, OEN = 27
7935 10:02:18.131154 Original DQ_B1 (3 6) =30, OEN = 27
7936 10:02:18.134483 24, 0x0, End_B0=24 End_B1=24
7937 10:02:18.134567 25, 0x0, End_B0=25 End_B1=25
7938 10:02:18.137765 26, 0x0, End_B0=26 End_B1=26
7939 10:02:18.140963 27, 0x0, End_B0=27 End_B1=27
7940 10:02:18.144191 28, 0x0, End_B0=28 End_B1=28
7941 10:02:18.144275 29, 0x0, End_B0=29 End_B1=29
7942 10:02:18.147378 30, 0x0, End_B0=30 End_B1=30
7943 10:02:18.151286 31, 0x4141, End_B0=30 End_B1=30
7944 10:02:18.154531 Byte0 end_step=30 best_step=27
7945 10:02:18.157618 Byte1 end_step=30 best_step=27
7946 10:02:18.160838 Byte0 TX OE(2T, 0.5T) = (3, 3)
7947 10:02:18.160921 Byte1 TX OE(2T, 0.5T) = (3, 3)
7948 10:02:18.163975
7949 10:02:18.164057
7950 10:02:18.170859 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
7951 10:02:18.174336 CH0 RK0: MR19=303, MR18=2824
7952 10:02:18.181013 CH0_RK0: MR19=0x303, MR18=0x2824, DQSOSC=389, MR23=63, INC=24, DEC=16
7953 10:02:18.181126
7954 10:02:18.184085 ----->DramcWriteLeveling(PI) begin...
7955 10:02:18.184169 ==
7956 10:02:18.187303 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 10:02:18.190997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 10:02:18.191103 ==
7959 10:02:18.194252 Write leveling (Byte 0): 35 => 35
7960 10:02:18.197354 Write leveling (Byte 1): 28 => 28
7961 10:02:18.200503 DramcWriteLeveling(PI) end<-----
7962 10:02:18.200609
7963 10:02:18.200709 ==
7964 10:02:18.204210 Dram Type= 6, Freq= 0, CH_0, rank 1
7965 10:02:18.207541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 10:02:18.207677 ==
7967 10:02:18.210980 [Gating] SW mode calibration
7968 10:02:18.217801 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7969 10:02:18.224106 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7970 10:02:18.227428 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7971 10:02:18.230656 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7972 10:02:18.237394 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 10:02:18.240399 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
7974 10:02:18.243611 1 4 16 | B1->B0 | 2f2f 3535 | 0 0 | (0 0) (0 0)
7975 10:02:18.250233 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7976 10:02:18.254044 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 10:02:18.257385 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7978 10:02:18.263867 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7979 10:02:18.267073 1 5 4 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7980 10:02:18.270287 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7981 10:02:18.277127 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
7982 10:02:18.280176 1 5 16 | B1->B0 | 2d2d 2626 | 0 0 | (0 1) (1 0)
7983 10:02:18.283628 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7984 10:02:18.290081 1 5 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7985 10:02:18.293735 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7986 10:02:18.296811 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7987 10:02:18.303818 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7988 10:02:18.306902 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7989 10:02:18.310154 1 6 12 | B1->B0 | 2626 3b3b | 0 1 | (0 0) (0 0)
7990 10:02:18.316995 1 6 16 | B1->B0 | 3f3f 4645 | 0 1 | (0 0) (0 0)
7991 10:02:18.320181 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 10:02:18.323290 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 10:02:18.330116 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 10:02:18.333183 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 10:02:18.337092 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 10:02:18.343510 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 10:02:18.346478 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7998 10:02:18.350268 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7999 10:02:18.356677 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 10:02:18.360007 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 10:02:18.363321 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 10:02:18.366732 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 10:02:18.373063 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 10:02:18.376358 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 10:02:18.379582 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 10:02:18.386981 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 10:02:18.389944 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 10:02:18.393444 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 10:02:18.399978 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 10:02:18.403144 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 10:02:18.406667 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 10:02:18.412902 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 10:02:18.416000 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8014 10:02:18.419614 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 10:02:18.425977 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 10:02:18.429846 Total UI for P1: 0, mck2ui 16
8017 10:02:18.432852 best dqsien dly found for B0: ( 1, 9, 14)
8018 10:02:18.432949 Total UI for P1: 0, mck2ui 16
8019 10:02:18.439336 best dqsien dly found for B1: ( 1, 9, 14)
8020 10:02:18.443053 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8021 10:02:18.446340 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8022 10:02:18.446412
8023 10:02:18.449578 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8024 10:02:18.452671 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8025 10:02:18.456076 [Gating] SW calibration Done
8026 10:02:18.456175 ==
8027 10:02:18.459340 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 10:02:18.462644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 10:02:18.462725 ==
8030 10:02:18.465857 RX Vref Scan: 0
8031 10:02:18.465936
8032 10:02:18.466000 RX Vref 0 -> 0, step: 1
8033 10:02:18.469585
8034 10:02:18.469664 RX Delay 0 -> 252, step: 8
8035 10:02:18.472867 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8036 10:02:18.479342 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8037 10:02:18.482353 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8038 10:02:18.485683 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8039 10:02:18.488950 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8040 10:02:18.492326 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8041 10:02:18.499314 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8042 10:02:18.502317 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8043 10:02:18.505860 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8044 10:02:18.508807 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8045 10:02:18.512398 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8046 10:02:18.519084 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8047 10:02:18.522169 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8048 10:02:18.525763 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8049 10:02:18.528822 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8050 10:02:18.535378 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8051 10:02:18.535459 ==
8052 10:02:18.539192 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 10:02:18.542168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 10:02:18.542249 ==
8055 10:02:18.542311 DQS Delay:
8056 10:02:18.545421 DQS0 = 0, DQS1 = 0
8057 10:02:18.545524 DQM Delay:
8058 10:02:18.548893 DQM0 = 136, DQM1 = 130
8059 10:02:18.548972 DQ Delay:
8060 10:02:18.552424 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8061 10:02:18.555408 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8062 10:02:18.559170 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8063 10:02:18.562218 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8064 10:02:18.562298
8065 10:02:18.562360
8066 10:02:18.565634 ==
8067 10:02:18.568927 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 10:02:18.572222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 10:02:18.572303 ==
8070 10:02:18.572366
8071 10:02:18.572424
8072 10:02:18.575339 TX Vref Scan disable
8073 10:02:18.575418 == TX Byte 0 ==
8074 10:02:18.578596 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8075 10:02:18.584942 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8076 10:02:18.585022 == TX Byte 1 ==
8077 10:02:18.592186 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8078 10:02:18.595324 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8079 10:02:18.595403 ==
8080 10:02:18.598599 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 10:02:18.601854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 10:02:18.601934 ==
8083 10:02:18.616067
8084 10:02:18.619535 TX Vref early break, caculate TX vref
8085 10:02:18.622444 TX Vref=16, minBit 1, minWin=22, winSum=387
8086 10:02:18.625676 TX Vref=18, minBit 1, minWin=24, winSum=403
8087 10:02:18.629254 TX Vref=20, minBit 1, minWin=24, winSum=408
8088 10:02:18.632718 TX Vref=22, minBit 1, minWin=24, winSum=415
8089 10:02:18.635816 TX Vref=24, minBit 1, minWin=24, winSum=419
8090 10:02:18.642420 TX Vref=26, minBit 3, minWin=25, winSum=426
8091 10:02:18.645592 TX Vref=28, minBit 0, minWin=25, winSum=419
8092 10:02:18.648903 TX Vref=30, minBit 0, minWin=25, winSum=418
8093 10:02:18.652794 TX Vref=32, minBit 7, minWin=24, winSum=410
8094 10:02:18.656085 TX Vref=34, minBit 1, minWin=24, winSum=402
8095 10:02:18.662360 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 26
8096 10:02:18.662466
8097 10:02:18.665828 Final TX Range 0 Vref 26
8098 10:02:18.665930
8099 10:02:18.666019 ==
8100 10:02:18.669552 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 10:02:18.672555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 10:02:18.672629 ==
8103 10:02:18.672690
8104 10:02:18.672753
8105 10:02:18.676038 TX Vref Scan disable
8106 10:02:18.682237 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8107 10:02:18.682339 == TX Byte 0 ==
8108 10:02:18.686008 u2DelayCellOfst[0]=13 cells (4 PI)
8109 10:02:18.689342 u2DelayCellOfst[1]=13 cells (4 PI)
8110 10:02:18.692493 u2DelayCellOfst[2]=10 cells (3 PI)
8111 10:02:18.695707 u2DelayCellOfst[3]=6 cells (2 PI)
8112 10:02:18.699076 u2DelayCellOfst[4]=10 cells (3 PI)
8113 10:02:18.702301 u2DelayCellOfst[5]=0 cells (0 PI)
8114 10:02:18.705459 u2DelayCellOfst[6]=13 cells (4 PI)
8115 10:02:18.705531 u2DelayCellOfst[7]=17 cells (5 PI)
8116 10:02:18.712389 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8117 10:02:18.716033 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8118 10:02:18.716108 == TX Byte 1 ==
8119 10:02:18.719255 u2DelayCellOfst[8]=3 cells (1 PI)
8120 10:02:18.722609 u2DelayCellOfst[9]=0 cells (0 PI)
8121 10:02:18.725654 u2DelayCellOfst[10]=6 cells (2 PI)
8122 10:02:18.729155 u2DelayCellOfst[11]=6 cells (2 PI)
8123 10:02:18.732200 u2DelayCellOfst[12]=10 cells (3 PI)
8124 10:02:18.735981 u2DelayCellOfst[13]=10 cells (3 PI)
8125 10:02:18.739028 u2DelayCellOfst[14]=17 cells (5 PI)
8126 10:02:18.742423 u2DelayCellOfst[15]=10 cells (3 PI)
8127 10:02:18.745246 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8128 10:02:18.752216 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8129 10:02:18.752316 DramC Write-DBI on
8130 10:02:18.752407 ==
8131 10:02:18.755490 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 10:02:18.758664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 10:02:18.758763 ==
8134 10:02:18.761943
8135 10:02:18.762041
8136 10:02:18.762131 TX Vref Scan disable
8137 10:02:18.765691 == TX Byte 0 ==
8138 10:02:18.768864 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8139 10:02:18.771827 == TX Byte 1 ==
8140 10:02:18.775468 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8141 10:02:18.778578 DramC Write-DBI off
8142 10:02:18.778653
8143 10:02:18.778714 [DATLAT]
8144 10:02:18.778771 Freq=1600, CH0 RK1
8145 10:02:18.778830
8146 10:02:18.782256 DATLAT Default: 0xf
8147 10:02:18.782354 0, 0xFFFF, sum = 0
8148 10:02:18.785391 1, 0xFFFF, sum = 0
8149 10:02:18.788919 2, 0xFFFF, sum = 0
8150 10:02:18.789001 3, 0xFFFF, sum = 0
8151 10:02:18.791816 4, 0xFFFF, sum = 0
8152 10:02:18.791898 5, 0xFFFF, sum = 0
8153 10:02:18.795110 6, 0xFFFF, sum = 0
8154 10:02:18.795190 7, 0xFFFF, sum = 0
8155 10:02:18.798508 8, 0xFFFF, sum = 0
8156 10:02:18.798590 9, 0xFFFF, sum = 0
8157 10:02:18.801754 10, 0xFFFF, sum = 0
8158 10:02:18.801835 11, 0xFFFF, sum = 0
8159 10:02:18.805573 12, 0xFFFF, sum = 0
8160 10:02:18.805654 13, 0xFFFF, sum = 0
8161 10:02:18.808627 14, 0x0, sum = 1
8162 10:02:18.808710 15, 0x0, sum = 2
8163 10:02:18.811960 16, 0x0, sum = 3
8164 10:02:18.812087 17, 0x0, sum = 4
8165 10:02:18.814959 best_step = 15
8166 10:02:18.815039
8167 10:02:18.815102 ==
8168 10:02:18.818859 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 10:02:18.821966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 10:02:18.822047 ==
8171 10:02:18.822110 RX Vref Scan: 0
8172 10:02:18.825142
8173 10:02:18.825221 RX Vref 0 -> 0, step: 1
8174 10:02:18.825284
8175 10:02:18.828411 RX Delay 19 -> 252, step: 4
8176 10:02:18.832100 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8177 10:02:18.838780 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8178 10:02:18.841850 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8179 10:02:18.845099 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8180 10:02:18.848607 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8181 10:02:18.851691 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8182 10:02:18.858790 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8183 10:02:18.862002 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8184 10:02:18.865175 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8185 10:02:18.868355 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8186 10:02:18.871706 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8187 10:02:18.878643 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8188 10:02:18.881765 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8189 10:02:18.885439 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8190 10:02:18.888644 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8191 10:02:18.891858 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8192 10:02:18.891932 ==
8193 10:02:18.894848 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 10:02:18.901519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 10:02:18.901622 ==
8196 10:02:18.901711 DQS Delay:
8197 10:02:18.905284 DQS0 = 0, DQS1 = 0
8198 10:02:18.905359 DQM Delay:
8199 10:02:18.908548 DQM0 = 134, DQM1 = 127
8200 10:02:18.908626 DQ Delay:
8201 10:02:18.911784 DQ0 =132, DQ1 =138, DQ2 =130, DQ3 =132
8202 10:02:18.914909 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8203 10:02:18.918703 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8204 10:02:18.921898 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8205 10:02:18.921979
8206 10:02:18.922043
8207 10:02:18.922127
8208 10:02:18.925108 [DramC_TX_OE_Calibration] TA2
8209 10:02:18.928729 Original DQ_B0 (3 6) =30, OEN = 27
8210 10:02:18.932072 Original DQ_B1 (3 6) =30, OEN = 27
8211 10:02:18.935328 24, 0x0, End_B0=24 End_B1=24
8212 10:02:18.935401 25, 0x0, End_B0=25 End_B1=25
8213 10:02:18.938582 26, 0x0, End_B0=26 End_B1=26
8214 10:02:18.941740 27, 0x0, End_B0=27 End_B1=27
8215 10:02:18.945362 28, 0x0, End_B0=28 End_B1=28
8216 10:02:18.948267 29, 0x0, End_B0=29 End_B1=29
8217 10:02:18.948347 30, 0x0, End_B0=30 End_B1=30
8218 10:02:18.952158 31, 0x4141, End_B0=30 End_B1=30
8219 10:02:18.955412 Byte0 end_step=30 best_step=27
8220 10:02:18.958674 Byte1 end_step=30 best_step=27
8221 10:02:18.961807 Byte0 TX OE(2T, 0.5T) = (3, 3)
8222 10:02:18.964947 Byte1 TX OE(2T, 0.5T) = (3, 3)
8223 10:02:18.965044
8224 10:02:18.965130
8225 10:02:18.971532 [DQSOSCAuto] RK1, (LSB)MR18= 0x240c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
8226 10:02:18.975088 CH0 RK1: MR19=303, MR18=240C
8227 10:02:18.981535 CH0_RK1: MR19=0x303, MR18=0x240C, DQSOSC=391, MR23=63, INC=24, DEC=16
8228 10:02:18.985238 [RxdqsGatingPostProcess] freq 1600
8229 10:02:18.988403 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8230 10:02:18.991489 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 10:02:18.994945 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 10:02:18.998098 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 10:02:19.001770 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 10:02:19.004811 best DQS0 dly(2T, 0.5T) = (1, 1)
8235 10:02:19.008068 best DQS1 dly(2T, 0.5T) = (1, 1)
8236 10:02:19.011599 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8237 10:02:19.014936 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8238 10:02:19.018123 Pre-setting of DQS Precalculation
8239 10:02:19.021753 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8240 10:02:19.021826 ==
8241 10:02:19.024972 Dram Type= 6, Freq= 0, CH_1, rank 0
8242 10:02:19.028203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 10:02:19.031236 ==
8244 10:02:19.035081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8245 10:02:19.038387 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8246 10:02:19.044788 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8247 10:02:19.047762 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8248 10:02:19.058508 [CA 0] Center 42 (13~72) winsize 60
8249 10:02:19.061835 [CA 1] Center 42 (12~72) winsize 61
8250 10:02:19.065006 [CA 2] Center 38 (9~68) winsize 60
8251 10:02:19.068327 [CA 3] Center 38 (10~67) winsize 58
8252 10:02:19.072021 [CA 4] Center 39 (10~68) winsize 59
8253 10:02:19.074994 [CA 5] Center 37 (8~67) winsize 60
8254 10:02:19.075086
8255 10:02:19.078770 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8256 10:02:19.078863
8257 10:02:19.081769 [CATrainingPosCal] consider 1 rank data
8258 10:02:19.085346 u2DelayCellTimex100 = 285/100 ps
8259 10:02:19.088677 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8260 10:02:19.095553 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8261 10:02:19.098693 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8262 10:02:19.101826 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8263 10:02:19.105191 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8264 10:02:19.108495 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8265 10:02:19.108570
8266 10:02:19.111461 CA PerBit enable=1, Macro0, CA PI delay=37
8267 10:02:19.111554
8268 10:02:19.115098 [CBTSetCACLKResult] CA Dly = 37
8269 10:02:19.118329 CS Dly: 10 (0~41)
8270 10:02:19.121479 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8271 10:02:19.125070 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8272 10:02:19.125165 ==
8273 10:02:19.128310 Dram Type= 6, Freq= 0, CH_1, rank 1
8274 10:02:19.131679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 10:02:19.134733 ==
8276 10:02:19.138423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8277 10:02:19.141746 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8278 10:02:19.148168 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8279 10:02:19.154960 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8280 10:02:19.161776 [CA 0] Center 42 (12~72) winsize 61
8281 10:02:19.165044 [CA 1] Center 41 (12~71) winsize 60
8282 10:02:19.168375 [CA 2] Center 38 (9~68) winsize 60
8283 10:02:19.171681 [CA 3] Center 38 (9~67) winsize 59
8284 10:02:19.174912 [CA 4] Center 38 (8~68) winsize 61
8285 10:02:19.178180 [CA 5] Center 37 (8~67) winsize 60
8286 10:02:19.178260
8287 10:02:19.182110 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8288 10:02:19.182191
8289 10:02:19.185251 [CATrainingPosCal] consider 2 rank data
8290 10:02:19.188315 u2DelayCellTimex100 = 285/100 ps
8291 10:02:19.191978 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8292 10:02:19.198747 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8293 10:02:19.201877 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8294 10:02:19.204942 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8295 10:02:19.208363 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8296 10:02:19.211533 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8297 10:02:19.211671
8298 10:02:19.215306 CA PerBit enable=1, Macro0, CA PI delay=37
8299 10:02:19.215387
8300 10:02:19.218425 [CBTSetCACLKResult] CA Dly = 37
8301 10:02:19.221966 CS Dly: 11 (0~44)
8302 10:02:19.225111 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8303 10:02:19.228727 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8304 10:02:19.228809
8305 10:02:19.232000 ----->DramcWriteLeveling(PI) begin...
8306 10:02:19.232082 ==
8307 10:02:19.235143 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 10:02:19.239012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 10:02:19.242129 ==
8310 10:02:19.242231 Write leveling (Byte 0): 27 => 27
8311 10:02:19.245435 Write leveling (Byte 1): 28 => 28
8312 10:02:19.248722 DramcWriteLeveling(PI) end<-----
8313 10:02:19.248801
8314 10:02:19.248864 ==
8315 10:02:19.252118 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 10:02:19.258403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 10:02:19.258508 ==
8318 10:02:19.258599 [Gating] SW mode calibration
8319 10:02:19.268637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8320 10:02:19.271899 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8321 10:02:19.278308 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 10:02:19.281589 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 10:02:19.285312 1 4 8 | B1->B0 | 2322 2e2e | 1 0 | (0 0) (1 1)
8324 10:02:19.288443 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
8325 10:02:19.294739 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 10:02:19.298419 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 10:02:19.301540 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 10:02:19.308484 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 10:02:19.311546 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 10:02:19.315325 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 10:02:19.321433 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8332 10:02:19.325063 1 5 12 | B1->B0 | 2626 2424 | 0 0 | (1 0) (1 0)
8333 10:02:19.328259 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 10:02:19.335031 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 10:02:19.338044 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 10:02:19.341886 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 10:02:19.348289 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 10:02:19.351448 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 10:02:19.354754 1 6 8 | B1->B0 | 2727 3f3f | 0 1 | (0 0) (0 0)
8340 10:02:19.361702 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 10:02:19.364935 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 10:02:19.368208 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 10:02:19.375135 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 10:02:19.378285 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 10:02:19.381460 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 10:02:19.388437 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 10:02:19.391603 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8348 10:02:19.394634 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8349 10:02:19.401735 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8350 10:02:19.404968 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 10:02:19.408074 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 10:02:19.411768 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 10:02:19.418261 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 10:02:19.421380 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 10:02:19.425043 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 10:02:19.431287 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 10:02:19.434681 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 10:02:19.437749 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 10:02:19.444723 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 10:02:19.448083 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 10:02:19.451157 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 10:02:19.458399 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 10:02:19.461497 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8364 10:02:19.464523 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8365 10:02:19.471108 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 10:02:19.471202 Total UI for P1: 0, mck2ui 16
8367 10:02:19.477601 best dqsien dly found for B0: ( 1, 9, 12)
8368 10:02:19.477698 Total UI for P1: 0, mck2ui 16
8369 10:02:19.484506 best dqsien dly found for B1: ( 1, 9, 10)
8370 10:02:19.487707 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8371 10:02:19.490914 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8372 10:02:19.491004
8373 10:02:19.494713 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8374 10:02:19.497884 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8375 10:02:19.501116 [Gating] SW calibration Done
8376 10:02:19.501209 ==
8377 10:02:19.504423 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 10:02:19.507489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 10:02:19.507585 ==
8380 10:02:19.510792 RX Vref Scan: 0
8381 10:02:19.510889
8382 10:02:19.510981 RX Vref 0 -> 0, step: 1
8383 10:02:19.511066
8384 10:02:19.514635 RX Delay 0 -> 252, step: 8
8385 10:02:19.517820 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8386 10:02:19.524402 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8387 10:02:19.527553 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8388 10:02:19.530958 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8389 10:02:19.534198 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8390 10:02:19.537772 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8391 10:02:19.544701 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8392 10:02:19.547632 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8393 10:02:19.551440 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8394 10:02:19.554505 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8395 10:02:19.557569 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8396 10:02:19.560871 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8397 10:02:19.567571 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8398 10:02:19.570741 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8399 10:02:19.574752 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8400 10:02:19.578063 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8401 10:02:19.578143 ==
8402 10:02:19.581405 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 10:02:19.587740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 10:02:19.587821 ==
8405 10:02:19.587884 DQS Delay:
8406 10:02:19.590995 DQS0 = 0, DQS1 = 0
8407 10:02:19.591075 DQM Delay:
8408 10:02:19.594193 DQM0 = 136, DQM1 = 133
8409 10:02:19.594273 DQ Delay:
8410 10:02:19.597860 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8411 10:02:19.601132 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8412 10:02:19.604307 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8413 10:02:19.607554 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8414 10:02:19.607676
8415 10:02:19.607741
8416 10:02:19.607799 ==
8417 10:02:19.610836 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 10:02:19.617800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 10:02:19.617880 ==
8420 10:02:19.617943
8421 10:02:19.618002
8422 10:02:19.618058 TX Vref Scan disable
8423 10:02:19.620869 == TX Byte 0 ==
8424 10:02:19.624082 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8425 10:02:19.627421 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8426 10:02:19.630674 == TX Byte 1 ==
8427 10:02:19.633942 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8428 10:02:19.637962 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8429 10:02:19.641176 ==
8430 10:02:19.644348 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 10:02:19.647531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 10:02:19.647648 ==
8433 10:02:19.659363
8434 10:02:19.662320 TX Vref early break, caculate TX vref
8435 10:02:19.665926 TX Vref=16, minBit 1, minWin=22, winSum=376
8436 10:02:19.669433 TX Vref=18, minBit 2, minWin=23, winSum=385
8437 10:02:19.672458 TX Vref=20, minBit 0, minWin=24, winSum=398
8438 10:02:19.675946 TX Vref=22, minBit 0, minWin=24, winSum=405
8439 10:02:19.678963 TX Vref=24, minBit 0, minWin=25, winSum=413
8440 10:02:19.685961 TX Vref=26, minBit 0, minWin=25, winSum=421
8441 10:02:19.689137 TX Vref=28, minBit 1, minWin=25, winSum=425
8442 10:02:19.692287 TX Vref=30, minBit 2, minWin=24, winSum=418
8443 10:02:19.696073 TX Vref=32, minBit 0, minWin=24, winSum=414
8444 10:02:19.699270 TX Vref=34, minBit 10, minWin=23, winSum=398
8445 10:02:19.705714 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28
8446 10:02:19.705813
8447 10:02:19.708890 Final TX Range 0 Vref 28
8448 10:02:19.708987
8449 10:02:19.709078 ==
8450 10:02:19.712187 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 10:02:19.715915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 10:02:19.715982 ==
8453 10:02:19.716040
8454 10:02:19.716094
8455 10:02:19.719151 TX Vref Scan disable
8456 10:02:19.725491 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8457 10:02:19.725585 == TX Byte 0 ==
8458 10:02:19.728688 u2DelayCellOfst[0]=17 cells (5 PI)
8459 10:02:19.732399 u2DelayCellOfst[1]=10 cells (3 PI)
8460 10:02:19.735705 u2DelayCellOfst[2]=0 cells (0 PI)
8461 10:02:19.738934 u2DelayCellOfst[3]=6 cells (2 PI)
8462 10:02:19.742080 u2DelayCellOfst[4]=6 cells (2 PI)
8463 10:02:19.745453 u2DelayCellOfst[5]=17 cells (5 PI)
8464 10:02:19.748806 u2DelayCellOfst[6]=17 cells (5 PI)
8465 10:02:19.748871 u2DelayCellOfst[7]=3 cells (1 PI)
8466 10:02:19.755371 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8467 10:02:19.758625 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8468 10:02:19.758726 == TX Byte 1 ==
8469 10:02:19.761849 u2DelayCellOfst[8]=0 cells (0 PI)
8470 10:02:19.765448 u2DelayCellOfst[9]=3 cells (1 PI)
8471 10:02:19.768738 u2DelayCellOfst[10]=13 cells (4 PI)
8472 10:02:19.771919 u2DelayCellOfst[11]=6 cells (2 PI)
8473 10:02:19.775430 u2DelayCellOfst[12]=17 cells (5 PI)
8474 10:02:19.778932 u2DelayCellOfst[13]=17 cells (5 PI)
8475 10:02:19.781970 u2DelayCellOfst[14]=17 cells (5 PI)
8476 10:02:19.785503 u2DelayCellOfst[15]=17 cells (5 PI)
8477 10:02:19.788525 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8478 10:02:19.795374 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8479 10:02:19.795475 DramC Write-DBI on
8480 10:02:19.795567 ==
8481 10:02:19.798493 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 10:02:19.801613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 10:02:19.805365 ==
8484 10:02:19.805450
8485 10:02:19.805513
8486 10:02:19.805571 TX Vref Scan disable
8487 10:02:19.808514 == TX Byte 0 ==
8488 10:02:19.811670 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8489 10:02:19.815437 == TX Byte 1 ==
8490 10:02:19.818490 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8491 10:02:19.818570 DramC Write-DBI off
8492 10:02:19.821741
8493 10:02:19.821820 [DATLAT]
8494 10:02:19.821883 Freq=1600, CH1 RK0
8495 10:02:19.821948
8496 10:02:19.824938 DATLAT Default: 0xf
8497 10:02:19.825018 0, 0xFFFF, sum = 0
8498 10:02:19.828802 1, 0xFFFF, sum = 0
8499 10:02:19.828883 2, 0xFFFF, sum = 0
8500 10:02:19.832014 3, 0xFFFF, sum = 0
8501 10:02:19.832095 4, 0xFFFF, sum = 0
8502 10:02:19.835343 5, 0xFFFF, sum = 0
8503 10:02:19.838380 6, 0xFFFF, sum = 0
8504 10:02:19.838461 7, 0xFFFF, sum = 0
8505 10:02:19.841646 8, 0xFFFF, sum = 0
8506 10:02:19.841728 9, 0xFFFF, sum = 0
8507 10:02:19.844999 10, 0xFFFF, sum = 0
8508 10:02:19.845080 11, 0xFFFF, sum = 0
8509 10:02:19.848875 12, 0xFFFF, sum = 0
8510 10:02:19.848956 13, 0xFFFF, sum = 0
8511 10:02:19.851549 14, 0x0, sum = 1
8512 10:02:19.851671 15, 0x0, sum = 2
8513 10:02:19.855393 16, 0x0, sum = 3
8514 10:02:19.855474 17, 0x0, sum = 4
8515 10:02:19.858684 best_step = 15
8516 10:02:19.858764
8517 10:02:19.858827 ==
8518 10:02:19.862002 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 10:02:19.865332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 10:02:19.865413 ==
8521 10:02:19.865476 RX Vref Scan: 1
8522 10:02:19.868529
8523 10:02:19.868625 Set Vref Range= 24 -> 127
8524 10:02:19.868704
8525 10:02:19.871833 RX Vref 24 -> 127, step: 1
8526 10:02:19.871914
8527 10:02:19.874884 RX Delay 27 -> 252, step: 4
8528 10:02:19.874964
8529 10:02:19.878538 Set Vref, RX VrefLevel [Byte0]: 24
8530 10:02:19.881918 [Byte1]: 24
8531 10:02:19.881998
8532 10:02:19.884897 Set Vref, RX VrefLevel [Byte0]: 25
8533 10:02:19.888305 [Byte1]: 25
8534 10:02:19.888385
8535 10:02:19.891578 Set Vref, RX VrefLevel [Byte0]: 26
8536 10:02:19.895019 [Byte1]: 26
8537 10:02:19.898577
8538 10:02:19.898657 Set Vref, RX VrefLevel [Byte0]: 27
8539 10:02:19.902224 [Byte1]: 27
8540 10:02:19.906429
8541 10:02:19.906508 Set Vref, RX VrefLevel [Byte0]: 28
8542 10:02:19.909479 [Byte1]: 28
8543 10:02:19.913432
8544 10:02:19.913511 Set Vref, RX VrefLevel [Byte0]: 29
8545 10:02:19.917097 [Byte1]: 29
8546 10:02:19.920939
8547 10:02:19.921019 Set Vref, RX VrefLevel [Byte0]: 30
8548 10:02:19.924755 [Byte1]: 30
8549 10:02:19.928635
8550 10:02:19.928714 Set Vref, RX VrefLevel [Byte0]: 31
8551 10:02:19.931880 [Byte1]: 31
8552 10:02:19.936368
8553 10:02:19.936447 Set Vref, RX VrefLevel [Byte0]: 32
8554 10:02:19.939575 [Byte1]: 32
8555 10:02:19.943970
8556 10:02:19.944053 Set Vref, RX VrefLevel [Byte0]: 33
8557 10:02:19.947192 [Byte1]: 33
8558 10:02:19.951082
8559 10:02:19.951161 Set Vref, RX VrefLevel [Byte0]: 34
8560 10:02:19.954926 [Byte1]: 34
8561 10:02:19.959010
8562 10:02:19.959089 Set Vref, RX VrefLevel [Byte0]: 35
8563 10:02:19.962298 [Byte1]: 35
8564 10:02:19.966691
8565 10:02:19.966771 Set Vref, RX VrefLevel [Byte0]: 36
8566 10:02:19.969943 [Byte1]: 36
8567 10:02:19.973980
8568 10:02:19.974059 Set Vref, RX VrefLevel [Byte0]: 37
8569 10:02:19.977164 [Byte1]: 37
8570 10:02:19.981540
8571 10:02:19.981619 Set Vref, RX VrefLevel [Byte0]: 38
8572 10:02:19.984723 [Byte1]: 38
8573 10:02:19.989010
8574 10:02:19.989089 Set Vref, RX VrefLevel [Byte0]: 39
8575 10:02:19.992231 [Byte1]: 39
8576 10:02:19.996307
8577 10:02:19.996388 Set Vref, RX VrefLevel [Byte0]: 40
8578 10:02:19.999760 [Byte1]: 40
8579 10:02:20.004246
8580 10:02:20.004344 Set Vref, RX VrefLevel [Byte0]: 41
8581 10:02:20.007191 [Byte1]: 41
8582 10:02:20.012008
8583 10:02:20.012088 Set Vref, RX VrefLevel [Byte0]: 42
8584 10:02:20.014963 [Byte1]: 42
8585 10:02:20.018986
8586 10:02:20.019059 Set Vref, RX VrefLevel [Byte0]: 43
8587 10:02:20.022354 [Byte1]: 43
8588 10:02:20.026988
8589 10:02:20.027075 Set Vref, RX VrefLevel [Byte0]: 44
8590 10:02:20.029777 [Byte1]: 44
8591 10:02:20.034381
8592 10:02:20.034456 Set Vref, RX VrefLevel [Byte0]: 45
8593 10:02:20.037487 [Byte1]: 45
8594 10:02:20.042016
8595 10:02:20.042114 Set Vref, RX VrefLevel [Byte0]: 46
8596 10:02:20.045405 [Byte1]: 46
8597 10:02:20.049106
8598 10:02:20.049178 Set Vref, RX VrefLevel [Byte0]: 47
8599 10:02:20.052953 [Byte1]: 47
8600 10:02:20.056816
8601 10:02:20.056911 Set Vref, RX VrefLevel [Byte0]: 48
8602 10:02:20.060111 [Byte1]: 48
8603 10:02:20.064538
8604 10:02:20.064610 Set Vref, RX VrefLevel [Byte0]: 49
8605 10:02:20.067891 [Byte1]: 49
8606 10:02:20.071743
8607 10:02:20.071813 Set Vref, RX VrefLevel [Byte0]: 50
8608 10:02:20.075020 [Byte1]: 50
8609 10:02:20.079599
8610 10:02:20.079702 Set Vref, RX VrefLevel [Byte0]: 51
8611 10:02:20.082894 [Byte1]: 51
8612 10:02:20.087391
8613 10:02:20.087488 Set Vref, RX VrefLevel [Byte0]: 52
8614 10:02:20.090419 [Byte1]: 52
8615 10:02:20.094426
8616 10:02:20.094521 Set Vref, RX VrefLevel [Byte0]: 53
8617 10:02:20.097726 [Byte1]: 53
8618 10:02:20.102168
8619 10:02:20.102267 Set Vref, RX VrefLevel [Byte0]: 54
8620 10:02:20.105357 [Byte1]: 54
8621 10:02:20.109838
8622 10:02:20.109938 Set Vref, RX VrefLevel [Byte0]: 55
8623 10:02:20.112937 [Byte1]: 55
8624 10:02:20.117153
8625 10:02:20.117250 Set Vref, RX VrefLevel [Byte0]: 56
8626 10:02:20.120115 [Byte1]: 56
8627 10:02:20.124663
8628 10:02:20.124761 Set Vref, RX VrefLevel [Byte0]: 57
8629 10:02:20.131211 [Byte1]: 57
8630 10:02:20.131310
8631 10:02:20.134343 Set Vref, RX VrefLevel [Byte0]: 58
8632 10:02:20.137639 [Byte1]: 58
8633 10:02:20.137738
8634 10:02:20.141056 Set Vref, RX VrefLevel [Byte0]: 59
8635 10:02:20.144112 [Byte1]: 59
8636 10:02:20.144199
8637 10:02:20.147508 Set Vref, RX VrefLevel [Byte0]: 60
8638 10:02:20.151300 [Byte1]: 60
8639 10:02:20.155002
8640 10:02:20.155098 Set Vref, RX VrefLevel [Byte0]: 61
8641 10:02:20.158306 [Byte1]: 61
8642 10:02:20.162124
8643 10:02:20.162222 Set Vref, RX VrefLevel [Byte0]: 62
8644 10:02:20.165500 [Byte1]: 62
8645 10:02:20.170132
8646 10:02:20.170233 Set Vref, RX VrefLevel [Byte0]: 63
8647 10:02:20.173297 [Byte1]: 63
8648 10:02:20.177197
8649 10:02:20.177267 Set Vref, RX VrefLevel [Byte0]: 64
8650 10:02:20.180429 [Byte1]: 64
8651 10:02:20.184950
8652 10:02:20.185020 Set Vref, RX VrefLevel [Byte0]: 65
8653 10:02:20.188091 [Byte1]: 65
8654 10:02:20.192433
8655 10:02:20.192531 Set Vref, RX VrefLevel [Byte0]: 66
8656 10:02:20.195491 [Byte1]: 66
8657 10:02:20.200098
8658 10:02:20.200168 Set Vref, RX VrefLevel [Byte0]: 67
8659 10:02:20.203336 [Byte1]: 67
8660 10:02:20.207705
8661 10:02:20.207777 Set Vref, RX VrefLevel [Byte0]: 68
8662 10:02:20.210980 [Byte1]: 68
8663 10:02:20.214780
8664 10:02:20.214875 Set Vref, RX VrefLevel [Byte0]: 69
8665 10:02:20.218272 [Byte1]: 69
8666 10:02:20.222721
8667 10:02:20.222819 Set Vref, RX VrefLevel [Byte0]: 70
8668 10:02:20.225786 [Byte1]: 70
8669 10:02:20.229942
8670 10:02:20.230037 Set Vref, RX VrefLevel [Byte0]: 71
8671 10:02:20.233102 [Byte1]: 71
8672 10:02:20.237528
8673 10:02:20.237605 Set Vref, RX VrefLevel [Byte0]: 72
8674 10:02:20.241012 [Byte1]: 72
8675 10:02:20.245484
8676 10:02:20.245555 Set Vref, RX VrefLevel [Byte0]: 73
8677 10:02:20.248691 [Byte1]: 73
8678 10:02:20.252438
8679 10:02:20.252521 Set Vref, RX VrefLevel [Byte0]: 74
8680 10:02:20.256075 [Byte1]: 74
8681 10:02:20.260564
8682 10:02:20.260644 Set Vref, RX VrefLevel [Byte0]: 75
8683 10:02:20.263359 [Byte1]: 75
8684 10:02:20.267582
8685 10:02:20.267699 Set Vref, RX VrefLevel [Byte0]: 76
8686 10:02:20.270859 [Byte1]: 76
8687 10:02:20.275319
8688 10:02:20.275418 Set Vref, RX VrefLevel [Byte0]: 77
8689 10:02:20.278576 [Byte1]: 77
8690 10:02:20.283065
8691 10:02:20.283160 Set Vref, RX VrefLevel [Byte0]: 78
8692 10:02:20.285812 [Byte1]: 78
8693 10:02:20.290360
8694 10:02:20.290455 Final RX Vref Byte 0 = 58 to rank0
8695 10:02:20.293491 Final RX Vref Byte 1 = 56 to rank0
8696 10:02:20.297205 Final RX Vref Byte 0 = 58 to rank1
8697 10:02:20.300344 Final RX Vref Byte 1 = 56 to rank1==
8698 10:02:20.303680 Dram Type= 6, Freq= 0, CH_1, rank 0
8699 10:02:20.310180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8700 10:02:20.310281 ==
8701 10:02:20.310370 DQS Delay:
8702 10:02:20.313355 DQS0 = 0, DQS1 = 0
8703 10:02:20.313448 DQM Delay:
8704 10:02:20.313533 DQM0 = 133, DQM1 = 131
8705 10:02:20.316600 DQ Delay:
8706 10:02:20.319952 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8707 10:02:20.323714 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8708 10:02:20.326657 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8709 10:02:20.330332 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8710 10:02:20.330407
8711 10:02:20.330471
8712 10:02:20.330528
8713 10:02:20.333408 [DramC_TX_OE_Calibration] TA2
8714 10:02:20.336541 Original DQ_B0 (3 6) =30, OEN = 27
8715 10:02:20.339812 Original DQ_B1 (3 6) =30, OEN = 27
8716 10:02:20.343627 24, 0x0, End_B0=24 End_B1=24
8717 10:02:20.343725 25, 0x0, End_B0=25 End_B1=25
8718 10:02:20.346802 26, 0x0, End_B0=26 End_B1=26
8719 10:02:20.349754 27, 0x0, End_B0=27 End_B1=27
8720 10:02:20.353499 28, 0x0, End_B0=28 End_B1=28
8721 10:02:20.356582 29, 0x0, End_B0=29 End_B1=29
8722 10:02:20.356660 30, 0x0, End_B0=30 End_B1=30
8723 10:02:20.359765 31, 0x4141, End_B0=30 End_B1=30
8724 10:02:20.363431 Byte0 end_step=30 best_step=27
8725 10:02:20.366604 Byte1 end_step=30 best_step=27
8726 10:02:20.370141 Byte0 TX OE(2T, 0.5T) = (3, 3)
8727 10:02:20.373066 Byte1 TX OE(2T, 0.5T) = (3, 3)
8728 10:02:20.373137
8729 10:02:20.373199
8730 10:02:20.379829 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8731 10:02:20.383047 CH1 RK0: MR19=303, MR18=1725
8732 10:02:20.390149 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8733 10:02:20.390224
8734 10:02:20.393472 ----->DramcWriteLeveling(PI) begin...
8735 10:02:20.393569 ==
8736 10:02:20.396639 Dram Type= 6, Freq= 0, CH_1, rank 1
8737 10:02:20.399782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 10:02:20.399864 ==
8739 10:02:20.403406 Write leveling (Byte 0): 26 => 26
8740 10:02:20.406675 Write leveling (Byte 1): 29 => 29
8741 10:02:20.409881 DramcWriteLeveling(PI) end<-----
8742 10:02:20.409961
8743 10:02:20.410023 ==
8744 10:02:20.412970 Dram Type= 6, Freq= 0, CH_1, rank 1
8745 10:02:20.416251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 10:02:20.416332 ==
8747 10:02:20.420106 [Gating] SW mode calibration
8748 10:02:20.426633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8749 10:02:20.433418 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8750 10:02:20.436907 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 10:02:20.439870 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 10:02:20.446704 1 4 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
8753 10:02:20.450003 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8754 10:02:20.453020 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 10:02:20.459947 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 10:02:20.463075 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 10:02:20.466828 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 10:02:20.473268 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 10:02:20.476707 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8760 10:02:20.479798 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
8761 10:02:20.486075 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 0)
8762 10:02:20.489460 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 10:02:20.493141 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 10:02:20.499622 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 10:02:20.502723 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 10:02:20.505851 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 10:02:20.512929 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8768 10:02:20.516180 1 6 8 | B1->B0 | 3c3c 2424 | 1 0 | (0 0) (0 0)
8769 10:02:20.519359 1 6 12 | B1->B0 | 4646 3b3b | 0 1 | (0 0) (0 0)
8770 10:02:20.525973 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 10:02:20.529223 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 10:02:20.532757 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 10:02:20.539139 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 10:02:20.542388 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 10:02:20.545831 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 10:02:20.553013 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8777 10:02:20.556074 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8778 10:02:20.559214 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8779 10:02:20.562387 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 10:02:20.569337 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 10:02:20.572337 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 10:02:20.576142 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 10:02:20.582609 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 10:02:20.585947 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 10:02:20.588987 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 10:02:20.595976 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 10:02:20.599118 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 10:02:20.602560 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 10:02:20.608850 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 10:02:20.612005 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 10:02:20.615947 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8792 10:02:20.622405 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8793 10:02:20.625067 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8794 10:02:20.628447 Total UI for P1: 0, mck2ui 16
8795 10:02:20.632324 best dqsien dly found for B1: ( 1, 9, 6)
8796 10:02:20.635447 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8797 10:02:20.641827 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 10:02:20.641902 Total UI for P1: 0, mck2ui 16
8799 10:02:20.648657 best dqsien dly found for B0: ( 1, 9, 14)
8800 10:02:20.656207 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8801 10:02:20.656313 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8802 10:02:20.656408
8803 10:02:20.658778 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8804 10:02:20.661666 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8805 10:02:20.665167 [Gating] SW calibration Done
8806 10:02:20.665250 ==
8807 10:02:20.668716 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 10:02:20.671691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 10:02:20.671774 ==
8810 10:02:20.675520 RX Vref Scan: 0
8811 10:02:20.675660
8812 10:02:20.675730 RX Vref 0 -> 0, step: 1
8813 10:02:20.675790
8814 10:02:20.678638 RX Delay 0 -> 252, step: 8
8815 10:02:20.681812 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8816 10:02:20.688127 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8817 10:02:20.691414 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8818 10:02:20.694647 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8819 10:02:20.697927 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8820 10:02:20.705032 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8821 10:02:20.708276 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8822 10:02:20.711304 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8823 10:02:20.714811 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8824 10:02:20.718225 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8825 10:02:20.724973 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8826 10:02:20.728186 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8827 10:02:20.731360 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8828 10:02:20.734618 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8829 10:02:20.737941 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8830 10:02:20.744445 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8831 10:02:20.744519 ==
8832 10:02:20.748227 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 10:02:20.751513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 10:02:20.751651 ==
8835 10:02:20.751720 DQS Delay:
8836 10:02:20.754710 DQS0 = 0, DQS1 = 0
8837 10:02:20.754782 DQM Delay:
8838 10:02:20.758360 DQM0 = 136, DQM1 = 133
8839 10:02:20.758460 DQ Delay:
8840 10:02:20.761614 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8841 10:02:20.764888 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8842 10:02:20.767839 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8843 10:02:20.771382 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8844 10:02:20.771489
8845 10:02:20.771587
8846 10:02:20.774793 ==
8847 10:02:20.774899 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 10:02:20.781337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 10:02:20.781448 ==
8850 10:02:20.781590
8851 10:02:20.781702
8852 10:02:20.784878 TX Vref Scan disable
8853 10:02:20.784961 == TX Byte 0 ==
8854 10:02:20.788060 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8855 10:02:20.794925 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8856 10:02:20.795008 == TX Byte 1 ==
8857 10:02:20.798077 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8858 10:02:20.804752 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8859 10:02:20.804835 ==
8860 10:02:20.807978 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 10:02:20.811319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 10:02:20.811402 ==
8863 10:02:20.824334
8864 10:02:20.827347 TX Vref early break, caculate TX vref
8865 10:02:20.830574 TX Vref=16, minBit 0, minWin=23, winSum=385
8866 10:02:20.833842 TX Vref=18, minBit 0, minWin=23, winSum=390
8867 10:02:20.837295 TX Vref=20, minBit 1, minWin=24, winSum=403
8868 10:02:20.841041 TX Vref=22, minBit 0, minWin=25, winSum=408
8869 10:02:20.844006 TX Vref=24, minBit 0, minWin=25, winSum=418
8870 10:02:20.850634 TX Vref=26, minBit 0, minWin=25, winSum=421
8871 10:02:20.853984 TX Vref=28, minBit 0, minWin=25, winSum=425
8872 10:02:20.857137 TX Vref=30, minBit 0, minWin=25, winSum=422
8873 10:02:20.860819 TX Vref=32, minBit 0, minWin=24, winSum=411
8874 10:02:20.863968 TX Vref=34, minBit 0, minWin=24, winSum=402
8875 10:02:20.870416 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8876 10:02:20.870499
8877 10:02:20.873490 Final TX Range 0 Vref 28
8878 10:02:20.873573
8879 10:02:20.873657 ==
8880 10:02:20.877116 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 10:02:20.880290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 10:02:20.880373 ==
8883 10:02:20.880457
8884 10:02:20.880536
8885 10:02:20.883984 TX Vref Scan disable
8886 10:02:20.890359 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8887 10:02:20.890441 == TX Byte 0 ==
8888 10:02:20.894004 u2DelayCellOfst[0]=17 cells (5 PI)
8889 10:02:20.897103 u2DelayCellOfst[1]=13 cells (4 PI)
8890 10:02:20.900111 u2DelayCellOfst[2]=0 cells (0 PI)
8891 10:02:20.903933 u2DelayCellOfst[3]=6 cells (2 PI)
8892 10:02:20.907085 u2DelayCellOfst[4]=6 cells (2 PI)
8893 10:02:20.910335 u2DelayCellOfst[5]=17 cells (5 PI)
8894 10:02:20.913559 u2DelayCellOfst[6]=17 cells (5 PI)
8895 10:02:20.913629 u2DelayCellOfst[7]=6 cells (2 PI)
8896 10:02:20.920128 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8897 10:02:20.923955 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8898 10:02:20.924031 == TX Byte 1 ==
8899 10:02:20.927299 u2DelayCellOfst[8]=0 cells (0 PI)
8900 10:02:20.930524 u2DelayCellOfst[9]=3 cells (1 PI)
8901 10:02:20.933730 u2DelayCellOfst[10]=10 cells (3 PI)
8902 10:02:20.936914 u2DelayCellOfst[11]=6 cells (2 PI)
8903 10:02:20.940061 u2DelayCellOfst[12]=13 cells (4 PI)
8904 10:02:20.943407 u2DelayCellOfst[13]=13 cells (4 PI)
8905 10:02:20.946603 u2DelayCellOfst[14]=17 cells (5 PI)
8906 10:02:20.950235 u2DelayCellOfst[15]=17 cells (5 PI)
8907 10:02:20.953813 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8908 10:02:20.960371 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8909 10:02:20.960454 DramC Write-DBI on
8910 10:02:20.960517 ==
8911 10:02:20.963249 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 10:02:20.966844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 10:02:20.966915 ==
8914 10:02:20.970074
8915 10:02:20.970213
8916 10:02:20.970271 TX Vref Scan disable
8917 10:02:20.973357 == TX Byte 0 ==
8918 10:02:20.976512 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8919 10:02:20.979950 == TX Byte 1 ==
8920 10:02:20.983710 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8921 10:02:20.983782 DramC Write-DBI off
8922 10:02:20.986640
8923 10:02:20.986708 [DATLAT]
8924 10:02:20.986766 Freq=1600, CH1 RK1
8925 10:02:20.986823
8926 10:02:20.990307 DATLAT Default: 0xf
8927 10:02:20.990404 0, 0xFFFF, sum = 0
8928 10:02:20.993399 1, 0xFFFF, sum = 0
8929 10:02:20.993472 2, 0xFFFF, sum = 0
8930 10:02:20.996800 3, 0xFFFF, sum = 0
8931 10:02:20.996870 4, 0xFFFF, sum = 0
8932 10:02:21.000492 5, 0xFFFF, sum = 0
8933 10:02:21.000563 6, 0xFFFF, sum = 0
8934 10:02:21.003779 7, 0xFFFF, sum = 0
8935 10:02:21.003852 8, 0xFFFF, sum = 0
8936 10:02:21.006755 9, 0xFFFF, sum = 0
8937 10:02:21.010517 10, 0xFFFF, sum = 0
8938 10:02:21.010603 11, 0xFFFF, sum = 0
8939 10:02:21.013759 12, 0xFFFF, sum = 0
8940 10:02:21.013843 13, 0xFFFF, sum = 0
8941 10:02:21.017041 14, 0x0, sum = 1
8942 10:02:21.017125 15, 0x0, sum = 2
8943 10:02:21.020330 16, 0x0, sum = 3
8944 10:02:21.020414 17, 0x0, sum = 4
8945 10:02:21.020498 best_step = 15
8946 10:02:21.020595
8947 10:02:21.023558 ==
8948 10:02:21.026870 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 10:02:21.030104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 10:02:21.030186 ==
8951 10:02:21.030270 RX Vref Scan: 0
8952 10:02:21.030351
8953 10:02:21.033401 RX Vref 0 -> 0, step: 1
8954 10:02:21.033484
8955 10:02:21.036665 RX Delay 19 -> 252, step: 4
8956 10:02:21.040547 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8957 10:02:21.043708 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8958 10:02:21.050456 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8959 10:02:21.053635 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8960 10:02:21.056750 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8961 10:02:21.060326 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8962 10:02:21.063495 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8963 10:02:21.069767 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8964 10:02:21.073566 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8965 10:02:21.076743 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8966 10:02:21.080371 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8967 10:02:21.083245 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8968 10:02:21.090333 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8969 10:02:21.093395 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8970 10:02:21.097358 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8971 10:02:21.100062 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8972 10:02:21.100134 ==
8973 10:02:21.103354 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 10:02:21.106630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 10:02:21.110151 ==
8976 10:02:21.110256 DQS Delay:
8977 10:02:21.110393 DQS0 = 0, DQS1 = 0
8978 10:02:21.113212 DQM Delay:
8979 10:02:21.113308 DQM0 = 134, DQM1 = 130
8980 10:02:21.116406 DQ Delay:
8981 10:02:21.120298 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8982 10:02:21.123447 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8983 10:02:21.126804 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8984 10:02:21.129991 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
8985 10:02:21.130086
8986 10:02:21.130175
8987 10:02:21.130259
8988 10:02:21.133462 [DramC_TX_OE_Calibration] TA2
8989 10:02:21.136598 Original DQ_B0 (3 6) =30, OEN = 27
8990 10:02:21.139671 Original DQ_B1 (3 6) =30, OEN = 27
8991 10:02:21.142957 24, 0x0, End_B0=24 End_B1=24
8992 10:02:21.143055 25, 0x0, End_B0=25 End_B1=25
8993 10:02:21.146939 26, 0x0, End_B0=26 End_B1=26
8994 10:02:21.149526 27, 0x0, End_B0=27 End_B1=27
8995 10:02:21.153429 28, 0x0, End_B0=28 End_B1=28
8996 10:02:21.156675 29, 0x0, End_B0=29 End_B1=29
8997 10:02:21.156745 30, 0x0, End_B0=30 End_B1=30
8998 10:02:21.159988 31, 0x4141, End_B0=30 End_B1=30
8999 10:02:21.163172 Byte0 end_step=30 best_step=27
9000 10:02:21.166343 Byte1 end_step=30 best_step=27
9001 10:02:21.169369 Byte0 TX OE(2T, 0.5T) = (3, 3)
9002 10:02:21.173150 Byte1 TX OE(2T, 0.5T) = (3, 3)
9003 10:02:21.173250
9004 10:02:21.173350
9005 10:02:21.179567 [DQSOSCAuto] RK1, (LSB)MR18= 0x2408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9006 10:02:21.182765 CH1 RK1: MR19=303, MR18=2408
9007 10:02:21.189924 CH1_RK1: MR19=0x303, MR18=0x2408, DQSOSC=391, MR23=63, INC=24, DEC=16
9008 10:02:21.192632 [RxdqsGatingPostProcess] freq 1600
9009 10:02:21.196279 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9010 10:02:21.199553 best DQS0 dly(2T, 0.5T) = (1, 1)
9011 10:02:21.203096 best DQS1 dly(2T, 0.5T) = (1, 1)
9012 10:02:21.206302 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9013 10:02:21.209313 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9014 10:02:21.213050 best DQS0 dly(2T, 0.5T) = (1, 1)
9015 10:02:21.216486 best DQS1 dly(2T, 0.5T) = (1, 1)
9016 10:02:21.219772 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9017 10:02:21.223044 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9018 10:02:21.226147 Pre-setting of DQS Precalculation
9019 10:02:21.229527 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9020 10:02:21.235838 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9021 10:02:21.242707 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9022 10:02:21.245937
9023 10:02:21.246038
9024 10:02:21.246170 [Calibration Summary] 3200 Mbps
9025 10:02:21.249093 CH 0, Rank 0
9026 10:02:21.249171 SW Impedance : PASS
9027 10:02:21.252887 DUTY Scan : NO K
9028 10:02:21.256207 ZQ Calibration : PASS
9029 10:02:21.256338 Jitter Meter : NO K
9030 10:02:21.258924 CBT Training : PASS
9031 10:02:21.262681 Write leveling : PASS
9032 10:02:21.262848 RX DQS gating : PASS
9033 10:02:21.265904 RX DQ/DQS(RDDQC) : PASS
9034 10:02:21.269112 TX DQ/DQS : PASS
9035 10:02:21.269210 RX DATLAT : PASS
9036 10:02:21.272149 RX DQ/DQS(Engine): PASS
9037 10:02:21.275701 TX OE : PASS
9038 10:02:21.275777 All Pass.
9039 10:02:21.275840
9040 10:02:21.275973 CH 0, Rank 1
9041 10:02:21.279392 SW Impedance : PASS
9042 10:02:21.282335 DUTY Scan : NO K
9043 10:02:21.282475 ZQ Calibration : PASS
9044 10:02:21.285584 Jitter Meter : NO K
9045 10:02:21.288772 CBT Training : PASS
9046 10:02:21.288878 Write leveling : PASS
9047 10:02:21.292035 RX DQS gating : PASS
9048 10:02:21.292186 RX DQ/DQS(RDDQC) : PASS
9049 10:02:21.295814 TX DQ/DQS : PASS
9050 10:02:21.299133 RX DATLAT : PASS
9051 10:02:21.299215 RX DQ/DQS(Engine): PASS
9052 10:02:21.302276 TX OE : PASS
9053 10:02:21.302358 All Pass.
9054 10:02:21.302424
9055 10:02:21.305885 CH 1, Rank 0
9056 10:02:21.305976 SW Impedance : PASS
9057 10:02:21.308778 DUTY Scan : NO K
9058 10:02:21.312879 ZQ Calibration : PASS
9059 10:02:21.312961 Jitter Meter : NO K
9060 10:02:21.315884 CBT Training : PASS
9061 10:02:21.319314 Write leveling : PASS
9062 10:02:21.319422 RX DQS gating : PASS
9063 10:02:21.322220 RX DQ/DQS(RDDQC) : PASS
9064 10:02:21.325638 TX DQ/DQS : PASS
9065 10:02:21.325721 RX DATLAT : PASS
9066 10:02:21.328897 RX DQ/DQS(Engine): PASS
9067 10:02:21.332016 TX OE : PASS
9068 10:02:21.332099 All Pass.
9069 10:02:21.332164
9070 10:02:21.332224 CH 1, Rank 1
9071 10:02:21.335832 SW Impedance : PASS
9072 10:02:21.338842 DUTY Scan : NO K
9073 10:02:21.338926 ZQ Calibration : PASS
9074 10:02:21.342189 Jitter Meter : NO K
9075 10:02:21.342280 CBT Training : PASS
9076 10:02:21.345666 Write leveling : PASS
9077 10:02:21.348991 RX DQS gating : PASS
9078 10:02:21.349068 RX DQ/DQS(RDDQC) : PASS
9079 10:02:21.352085 TX DQ/DQS : PASS
9080 10:02:21.355546 RX DATLAT : PASS
9081 10:02:21.355642 RX DQ/DQS(Engine): PASS
9082 10:02:21.358776 TX OE : PASS
9083 10:02:21.358859 All Pass.
9084 10:02:21.358924
9085 10:02:21.362359 DramC Write-DBI on
9086 10:02:21.365860 PER_BANK_REFRESH: Hybrid Mode
9087 10:02:21.365943 TX_TRACKING: ON
9088 10:02:21.375559 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9089 10:02:21.382415 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9090 10:02:21.389046 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9091 10:02:21.392024 [FAST_K] Save calibration result to emmc
9092 10:02:21.395674 sync common calibartion params.
9093 10:02:21.398973 sync cbt_mode0:1, 1:1
9094 10:02:21.402059 dram_init: ddr_geometry: 2
9095 10:02:21.402139 dram_init: ddr_geometry: 2
9096 10:02:21.405323 dram_init: ddr_geometry: 2
9097 10:02:21.408584 0:dram_rank_size:100000000
9098 10:02:21.412340 1:dram_rank_size:100000000
9099 10:02:21.415305 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9100 10:02:21.418696 DFS_SHUFFLE_HW_MODE: ON
9101 10:02:21.421907 dramc_set_vcore_voltage set vcore to 725000
9102 10:02:21.425706 Read voltage for 1600, 0
9103 10:02:21.425787 Vio18 = 0
9104 10:02:21.425850 Vcore = 725000
9105 10:02:21.429093 Vdram = 0
9106 10:02:21.429174 Vddq = 0
9107 10:02:21.429237 Vmddr = 0
9108 10:02:21.432358 switch to 3200 Mbps bootup
9109 10:02:21.435469 [DramcRunTimeConfig]
9110 10:02:21.435575 PHYPLL
9111 10:02:21.435709 DPM_CONTROL_AFTERK: ON
9112 10:02:21.438771 PER_BANK_REFRESH: ON
9113 10:02:21.442011 REFRESH_OVERHEAD_REDUCTION: ON
9114 10:02:21.442091 CMD_PICG_NEW_MODE: OFF
9115 10:02:21.445263 XRTWTW_NEW_MODE: ON
9116 10:02:21.445343 XRTRTR_NEW_MODE: ON
9117 10:02:21.448528 TX_TRACKING: ON
9118 10:02:21.448610 RDSEL_TRACKING: OFF
9119 10:02:21.452314 DQS Precalculation for DVFS: ON
9120 10:02:21.455578 RX_TRACKING: OFF
9121 10:02:21.455706 HW_GATING DBG: ON
9122 10:02:21.458779 ZQCS_ENABLE_LP4: ON
9123 10:02:21.458860 RX_PICG_NEW_MODE: ON
9124 10:02:21.461796 TX_PICG_NEW_MODE: ON
9125 10:02:21.465308 ENABLE_RX_DCM_DPHY: ON
9126 10:02:21.465415 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9127 10:02:21.468815 DUMMY_READ_FOR_TRACKING: OFF
9128 10:02:21.471725 !!! SPM_CONTROL_AFTERK: OFF
9129 10:02:21.475565 !!! SPM could not control APHY
9130 10:02:21.475703 IMPEDANCE_TRACKING: ON
9131 10:02:21.478644 TEMP_SENSOR: ON
9132 10:02:21.478715 HW_SAVE_FOR_SR: OFF
9133 10:02:21.481987 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9134 10:02:21.485406 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9135 10:02:21.488582 Read ODT Tracking: ON
9136 10:02:21.492058 Refresh Rate DeBounce: ON
9137 10:02:21.492134 DFS_NO_QUEUE_FLUSH: ON
9138 10:02:21.495366 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9139 10:02:21.498810 ENABLE_DFS_RUNTIME_MRW: OFF
9140 10:02:21.502345 DDR_RESERVE_NEW_MODE: ON
9141 10:02:21.502425 MR_CBT_SWITCH_FREQ: ON
9142 10:02:21.505446 =========================
9143 10:02:21.525181 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9144 10:02:21.527713 dram_init: ddr_geometry: 2
9145 10:02:21.545991 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9146 10:02:21.549823 dram_init: dram init end (result: 0)
9147 10:02:21.556228 DRAM-K: Full calibration passed in 24435 msecs
9148 10:02:21.559576 MRC: failed to locate region type 0.
9149 10:02:21.559681 DRAM rank0 size:0x100000000,
9150 10:02:21.562971 DRAM rank1 size=0x100000000
9151 10:02:21.572604 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9152 10:02:21.579516 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9153 10:02:21.586201 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9154 10:02:21.592554 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9155 10:02:21.595718 DRAM rank0 size:0x100000000,
9156 10:02:21.599240 DRAM rank1 size=0x100000000
9157 10:02:21.599320 CBMEM:
9158 10:02:21.602764 IMD: root @ 0xfffff000 254 entries.
9159 10:02:21.605881 IMD: root @ 0xffffec00 62 entries.
9160 10:02:21.609544 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9161 10:02:21.612758 WARNING: RO_VPD is uninitialized or empty.
9162 10:02:21.619498 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9163 10:02:21.626352 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9164 10:02:21.638846 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9165 10:02:21.650453 BS: romstage times (exec / console): total (unknown) / 23972 ms
9166 10:02:21.650535
9167 10:02:21.650598
9168 10:02:21.660083 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9169 10:02:21.663349 ARM64: Exception handlers installed.
9170 10:02:21.667349 ARM64: Testing exception
9171 10:02:21.667430 ARM64: Done test exception
9172 10:02:21.670685 Enumerating buses...
9173 10:02:21.673875 Show all devs... Before device enumeration.
9174 10:02:21.677030 Root Device: enabled 1
9175 10:02:21.680289 CPU_CLUSTER: 0: enabled 1
9176 10:02:21.680370 CPU: 00: enabled 1
9177 10:02:21.683450 Compare with tree...
9178 10:02:21.683530 Root Device: enabled 1
9179 10:02:21.686698 CPU_CLUSTER: 0: enabled 1
9180 10:02:21.689840 CPU: 00: enabled 1
9181 10:02:21.689979 Root Device scanning...
9182 10:02:21.693204 scan_static_bus for Root Device
9183 10:02:21.696549 CPU_CLUSTER: 0 enabled
9184 10:02:21.700407 scan_static_bus for Root Device done
9185 10:02:21.703044 scan_bus: bus Root Device finished in 8 msecs
9186 10:02:21.703137 done
9187 10:02:21.709628 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9188 10:02:21.712958 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9189 10:02:21.720058 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9190 10:02:21.723079 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9191 10:02:21.726670 Allocating resources...
9192 10:02:21.730090 Reading resources...
9193 10:02:21.733001 Root Device read_resources bus 0 link: 0
9194 10:02:21.733082 DRAM rank0 size:0x100000000,
9195 10:02:21.736725 DRAM rank1 size=0x100000000
9196 10:02:21.739527 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9197 10:02:21.743084 CPU: 00 missing read_resources
9198 10:02:21.749517 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9199 10:02:21.752871 Root Device read_resources bus 0 link: 0 done
9200 10:02:21.752952 Done reading resources.
9201 10:02:21.759359 Show resources in subtree (Root Device)...After reading.
9202 10:02:21.763115 Root Device child on link 0 CPU_CLUSTER: 0
9203 10:02:21.766332 CPU_CLUSTER: 0 child on link 0 CPU: 00
9204 10:02:21.776334 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9205 10:02:21.776417 CPU: 00
9206 10:02:21.779310 Root Device assign_resources, bus 0 link: 0
9207 10:02:21.783105 CPU_CLUSTER: 0 missing set_resources
9208 10:02:21.789722 Root Device assign_resources, bus 0 link: 0 done
9209 10:02:21.789803 Done setting resources.
9210 10:02:21.796124 Show resources in subtree (Root Device)...After assigning values.
9211 10:02:21.799138 Root Device child on link 0 CPU_CLUSTER: 0
9212 10:02:21.802706 CPU_CLUSTER: 0 child on link 0 CPU: 00
9213 10:02:21.812545 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9214 10:02:21.812627 CPU: 00
9215 10:02:21.815707 Done allocating resources.
9216 10:02:21.818932 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9217 10:02:21.822786 Enabling resources...
9218 10:02:21.822867 done.
9219 10:02:21.829382 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9220 10:02:21.829463 Initializing devices...
9221 10:02:21.832545 Root Device init
9222 10:02:21.832625 init hardware done!
9223 10:02:21.835959 0x00000018: ctrlr->caps
9224 10:02:21.839095 52.000 MHz: ctrlr->f_max
9225 10:02:21.839176 0.400 MHz: ctrlr->f_min
9226 10:02:21.842350 0x40ff8080: ctrlr->voltages
9227 10:02:21.842433 sclk: 390625
9228 10:02:21.845582 Bus Width = 1
9229 10:02:21.845662 sclk: 390625
9230 10:02:21.849387 Bus Width = 1
9231 10:02:21.849467 Early init status = 3
9232 10:02:21.855752 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9233 10:02:21.859215 in-header: 03 fc 00 00 01 00 00 00
9234 10:02:21.859295 in-data: 00
9235 10:02:21.865808 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9236 10:02:21.869226 in-header: 03 fd 00 00 00 00 00 00
9237 10:02:21.872609 in-data:
9238 10:02:21.875750 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9239 10:02:21.878799 in-header: 03 fc 00 00 01 00 00 00
9240 10:02:21.882082 in-data: 00
9241 10:02:21.885624 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9242 10:02:21.890058 in-header: 03 fd 00 00 00 00 00 00
9243 10:02:21.893568 in-data:
9244 10:02:21.896595 [SSUSB] Setting up USB HOST controller...
9245 10:02:21.899864 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9246 10:02:21.903733 [SSUSB] phy power-on done.
9247 10:02:21.906564 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9248 10:02:21.913330 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9249 10:02:21.916574 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9250 10:02:21.923685 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9251 10:02:21.930084 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9252 10:02:21.936634 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9253 10:02:21.943132 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9254 10:02:21.950303 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9255 10:02:21.953004 SPM: binary array size = 0x9dc
9256 10:02:21.956296 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9257 10:02:21.963308 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9258 10:02:21.969659 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9259 10:02:21.973210 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9260 10:02:21.979580 configure_display: Starting display init
9261 10:02:22.013586 anx7625_power_on_init: Init interface.
9262 10:02:22.016708 anx7625_disable_pd_protocol: Disabled PD feature.
9263 10:02:22.020143 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9264 10:02:22.048048 anx7625_start_dp_work: Secure OCM version=00
9265 10:02:22.051342 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9266 10:02:22.065665 sp_tx_get_edid_block: EDID Block = 1
9267 10:02:22.168857 Extracted contents:
9268 10:02:22.172081 header: 00 ff ff ff ff ff ff 00
9269 10:02:22.175240 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9270 10:02:22.178405 version: 01 04
9271 10:02:22.181649 basic params: 95 1f 11 78 0a
9272 10:02:22.184865 chroma info: 76 90 94 55 54 90 27 21 50 54
9273 10:02:22.188638 established: 00 00 00
9274 10:02:22.194921 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9275 10:02:22.198014 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9276 10:02:22.205001 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9277 10:02:22.211544 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9278 10:02:22.218092 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9279 10:02:22.221216 extensions: 00
9280 10:02:22.221295 checksum: fb
9281 10:02:22.221358
9282 10:02:22.225067 Manufacturer: IVO Model 57d Serial Number 0
9283 10:02:22.227806 Made week 0 of 2020
9284 10:02:22.227888 EDID version: 1.4
9285 10:02:22.231712 Digital display
9286 10:02:22.234745 6 bits per primary color channel
9287 10:02:22.234829 DisplayPort interface
9288 10:02:22.238526 Maximum image size: 31 cm x 17 cm
9289 10:02:22.241384 Gamma: 220%
9290 10:02:22.241466 Check DPMS levels
9291 10:02:22.244958 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9292 10:02:22.248083 First detailed timing is preferred timing
9293 10:02:22.251241 Established timings supported:
9294 10:02:22.254557 Standard timings supported:
9295 10:02:22.258407 Detailed timings
9296 10:02:22.261499 Hex of detail: 383680a07038204018303c0035ae10000019
9297 10:02:22.264975 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9298 10:02:22.271708 0780 0798 07c8 0820 hborder 0
9299 10:02:22.274729 0438 043b 0447 0458 vborder 0
9300 10:02:22.278238 -hsync -vsync
9301 10:02:22.278321 Did detailed timing
9302 10:02:22.281340 Hex of detail: 000000000000000000000000000000000000
9303 10:02:22.285076 Manufacturer-specified data, tag 0
9304 10:02:22.291436 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9305 10:02:22.291519 ASCII string: InfoVision
9306 10:02:22.298368 Hex of detail: 000000fe00523134304e574635205248200a
9307 10:02:22.301628 ASCII string: R140NWF5 RH
9308 10:02:22.301726 Checksum
9309 10:02:22.301823 Checksum: 0xfb (valid)
9310 10:02:22.308398 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9311 10:02:22.311722 DSI data_rate: 832800000 bps
9312 10:02:22.314941 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9313 10:02:22.318189 anx7625_parse_edid: pixelclock(138800).
9314 10:02:22.324777 hactive(1920), hsync(48), hfp(24), hbp(88)
9315 10:02:22.328066 vactive(1080), vsync(12), vfp(3), vbp(17)
9316 10:02:22.331344 anx7625_dsi_config: config dsi.
9317 10:02:22.337951 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9318 10:02:22.350461 anx7625_dsi_config: success to config DSI
9319 10:02:22.353929 anx7625_dp_start: MIPI phy setup OK.
9320 10:02:22.357499 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9321 10:02:22.360911 mtk_ddp_mode_set invalid vrefresh 60
9322 10:02:22.364343 main_disp_path_setup
9323 10:02:22.364439 ovl_layer_smi_id_en
9324 10:02:22.367545 ovl_layer_smi_id_en
9325 10:02:22.367651 ccorr_config
9326 10:02:22.367730 aal_config
9327 10:02:22.370789 gamma_config
9328 10:02:22.370868 postmask_config
9329 10:02:22.373933 dither_config
9330 10:02:22.376905 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9331 10:02:22.384117 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9332 10:02:22.386995 Root Device init finished in 551 msecs
9333 10:02:22.390686 CPU_CLUSTER: 0 init
9334 10:02:22.396938 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9335 10:02:22.400606 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9336 10:02:22.403559 APU_MBOX 0x190000b0 = 0x10001
9337 10:02:22.407249 APU_MBOX 0x190001b0 = 0x10001
9338 10:02:22.410650 APU_MBOX 0x190005b0 = 0x10001
9339 10:02:22.413823 APU_MBOX 0x190006b0 = 0x10001
9340 10:02:22.416921 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9341 10:02:22.429781 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9342 10:02:22.441956 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9343 10:02:22.448398 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9344 10:02:22.460344 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9345 10:02:22.469490 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9346 10:02:22.472722 CPU_CLUSTER: 0 init finished in 81 msecs
9347 10:02:22.475741 Devices initialized
9348 10:02:22.479548 Show all devs... After init.
9349 10:02:22.479652 Root Device: enabled 1
9350 10:02:22.482644 CPU_CLUSTER: 0: enabled 1
9351 10:02:22.485623 CPU: 00: enabled 1
9352 10:02:22.489419 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9353 10:02:22.492723 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9354 10:02:22.495898 ELOG: NV offset 0x57f000 size 0x1000
9355 10:02:22.502525 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9356 10:02:22.509314 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9357 10:02:22.512379 ELOG: Event(17) added with size 13 at 2023-08-23 10:01:17 UTC
9358 10:02:22.515929 out: cmd=0x121: 03 db 21 01 00 00 00 00
9359 10:02:22.519924 in-header: 03 f5 00 00 2c 00 00 00
9360 10:02:22.532923 in-data: 6a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9361 10:02:22.539586 ELOG: Event(A1) added with size 10 at 2023-08-23 10:01:17 UTC
9362 10:02:22.545968 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9363 10:02:22.553028 ELOG: Event(A0) added with size 9 at 2023-08-23 10:01:17 UTC
9364 10:02:22.556316 elog_add_boot_reason: Logged dev mode boot
9365 10:02:22.559498 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9366 10:02:22.562589 Finalize devices...
9367 10:02:22.562670 Devices finalized
9368 10:02:22.569831 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9369 10:02:22.573078 Writing coreboot table at 0xffe64000
9370 10:02:22.576171 0. 000000000010a000-0000000000113fff: RAMSTAGE
9371 10:02:22.579986 1. 0000000040000000-00000000400fffff: RAM
9372 10:02:22.582805 2. 0000000040100000-000000004032afff: RAMSTAGE
9373 10:02:22.589822 3. 000000004032b000-00000000545fffff: RAM
9374 10:02:22.592855 4. 0000000054600000-000000005465ffff: BL31
9375 10:02:22.596298 5. 0000000054660000-00000000ffe63fff: RAM
9376 10:02:22.599533 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9377 10:02:22.605992 7. 0000000100000000-000000023fffffff: RAM
9378 10:02:22.606097 Passing 5 GPIOs to payload:
9379 10:02:22.612828 NAME | PORT | POLARITY | VALUE
9380 10:02:22.615757 EC in RW | 0x000000aa | low | undefined
9381 10:02:22.622598 EC interrupt | 0x00000005 | low | undefined
9382 10:02:22.625636 TPM interrupt | 0x000000ab | high | undefined
9383 10:02:22.629306 SD card detect | 0x00000011 | high | undefined
9384 10:02:22.635738 speaker enable | 0x00000093 | high | undefined
9385 10:02:22.639123 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9386 10:02:22.642366 in-header: 03 f9 00 00 02 00 00 00
9387 10:02:22.642447 in-data: 02 00
9388 10:02:22.645674 ADC[4]: Raw value=904726 ID=7
9389 10:02:22.648854 ADC[3]: Raw value=213441 ID=1
9390 10:02:22.648934 RAM Code: 0x71
9391 10:02:22.652148 ADC[6]: Raw value=75701 ID=0
9392 10:02:22.655953 ADC[5]: Raw value=213072 ID=1
9393 10:02:22.656033 SKU Code: 0x1
9394 10:02:22.662328 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7
9395 10:02:22.665337 coreboot table: 964 bytes.
9396 10:02:22.669158 IMD ROOT 0. 0xfffff000 0x00001000
9397 10:02:22.672481 IMD SMALL 1. 0xffffe000 0x00001000
9398 10:02:22.675814 RO MCACHE 2. 0xffffc000 0x00001104
9399 10:02:22.678962 CONSOLE 3. 0xfff7c000 0x00080000
9400 10:02:22.682437 FMAP 4. 0xfff7b000 0x00000452
9401 10:02:22.685624 TIME STAMP 5. 0xfff7a000 0x00000910
9402 10:02:22.688706 VBOOT WORK 6. 0xfff66000 0x00014000
9403 10:02:22.692348 RAMOOPS 7. 0xffe66000 0x00100000
9404 10:02:22.695330 COREBOOT 8. 0xffe64000 0x00002000
9405 10:02:22.695410 IMD small region:
9406 10:02:22.698514 IMD ROOT 0. 0xffffec00 0x00000400
9407 10:02:22.701938 VPD 1. 0xffffeb80 0x0000006c
9408 10:02:22.705322 MMC STATUS 2. 0xffffeb60 0x00000004
9409 10:02:22.711740 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9410 10:02:22.715582 Probing TPM: done!
9411 10:02:22.718898 Connected to device vid:did:rid of 1ae0:0028:00
9412 10:02:22.728600 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9413 10:02:22.732217 Initialized TPM device CR50 revision 0
9414 10:02:22.736010 Checking cr50 for pending updates
9415 10:02:22.739340 Reading cr50 TPM mode
9416 10:02:22.747873 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9417 10:02:22.754316 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9418 10:02:22.794219 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9419 10:02:22.797750 Checking segment from ROM address 0x40100000
9420 10:02:22.800993 Checking segment from ROM address 0x4010001c
9421 10:02:22.807872 Loading segment from ROM address 0x40100000
9422 10:02:22.807954 code (compression=0)
9423 10:02:22.814812 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9424 10:02:22.824529 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9425 10:02:22.824610 it's not compressed!
9426 10:02:22.831528 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9427 10:02:22.834719 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9428 10:02:22.854827 Loading segment from ROM address 0x4010001c
9429 10:02:22.854909 Entry Point 0x80000000
9430 10:02:22.858262 Loaded segments
9431 10:02:22.862072 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9432 10:02:22.868380 Jumping to boot code at 0x80000000(0xffe64000)
9433 10:02:22.874629 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9434 10:02:22.881693 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9435 10:02:22.889608 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9436 10:02:22.892847 Checking segment from ROM address 0x40100000
9437 10:02:22.896064 Checking segment from ROM address 0x4010001c
9438 10:02:22.902906 Loading segment from ROM address 0x40100000
9439 10:02:22.902987 code (compression=1)
9440 10:02:22.909668 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9441 10:02:22.919198 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9442 10:02:22.919290 using LZMA
9443 10:02:22.927704 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9444 10:02:22.934343 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9445 10:02:22.937555 Loading segment from ROM address 0x4010001c
9446 10:02:22.937636 Entry Point 0x54601000
9447 10:02:22.940742 Loaded segments
9448 10:02:22.944427 NOTICE: MT8192 bl31_setup
9449 10:02:22.951484 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9450 10:02:22.954587 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9451 10:02:22.957718 WARNING: region 0:
9452 10:02:22.961326 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 10:02:22.961407 WARNING: region 1:
9454 10:02:22.968060 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9455 10:02:22.971585 WARNING: region 2:
9456 10:02:22.974479 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9457 10:02:22.978112 WARNING: region 3:
9458 10:02:22.981631 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9459 10:02:22.984748 WARNING: region 4:
9460 10:02:22.987995 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9461 10:02:22.991381 WARNING: region 5:
9462 10:02:22.994716 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 10:02:22.998682 WARNING: region 6:
9464 10:02:23.001901 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 10:02:23.001982 WARNING: region 7:
9466 10:02:23.008355 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 10:02:23.015021 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9468 10:02:23.018239 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9469 10:02:23.022032 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9470 10:02:23.025065 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9471 10:02:23.031502 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9472 10:02:23.035425 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9473 10:02:23.041965 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9474 10:02:23.045139 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9475 10:02:23.048366 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9476 10:02:23.055481 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9477 10:02:23.058843 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9478 10:02:23.061999 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9479 10:02:23.068499 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9480 10:02:23.072013 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9481 10:02:23.078556 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9482 10:02:23.081963 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9483 10:02:23.085558 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9484 10:02:23.092259 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9485 10:02:23.095290 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9486 10:02:23.098999 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9487 10:02:23.105466 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9488 10:02:23.108752 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9489 10:02:23.111995 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9490 10:02:23.118726 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9491 10:02:23.122481 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9492 10:02:23.129046 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9493 10:02:23.132012 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9494 10:02:23.135866 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9495 10:02:23.142548 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9496 10:02:23.145745 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9497 10:02:23.152307 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9498 10:02:23.155410 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9499 10:02:23.159386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9500 10:02:23.162472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9501 10:02:23.168902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9502 10:02:23.172166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9503 10:02:23.175839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9504 10:02:23.178969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9505 10:02:23.185606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9506 10:02:23.189317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9507 10:02:23.192766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9508 10:02:23.195784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9509 10:02:23.202202 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9510 10:02:23.205819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9511 10:02:23.209088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9512 10:02:23.212441 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9513 10:02:23.218917 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9514 10:02:23.222738 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9515 10:02:23.225737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9516 10:02:23.232777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9517 10:02:23.236024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9518 10:02:23.242427 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9519 10:02:23.246233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9520 10:02:23.249091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9521 10:02:23.256050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9522 10:02:23.259389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9523 10:02:23.266402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9524 10:02:23.269594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9525 10:02:23.275932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9526 10:02:23.279796 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9527 10:02:23.283129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9528 10:02:23.289360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9529 10:02:23.292904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9530 10:02:23.299424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9531 10:02:23.302501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9532 10:02:23.309500 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9533 10:02:23.312483 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9534 10:02:23.316054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9535 10:02:23.322849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9536 10:02:23.326021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9537 10:02:23.332652 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9538 10:02:23.336488 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9539 10:02:23.342991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9540 10:02:23.346083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9541 10:02:23.349670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9542 10:02:23.356347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9543 10:02:23.359966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9544 10:02:23.366430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9545 10:02:23.369626 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9546 10:02:23.376644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9547 10:02:23.379884 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9548 10:02:23.383099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9549 10:02:23.389657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9550 10:02:23.392886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9551 10:02:23.399643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9552 10:02:23.402939 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9553 10:02:23.409715 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9554 10:02:23.413394 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9555 10:02:23.416673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9556 10:02:23.422910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9557 10:02:23.426567 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9558 10:02:23.433316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9559 10:02:23.436489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9560 10:02:23.439853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9561 10:02:23.446389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9562 10:02:23.450329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9563 10:02:23.456544 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9564 10:02:23.460462 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9565 10:02:23.463393 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9566 10:02:23.467097 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9567 10:02:23.470215 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9568 10:02:23.477376 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9569 10:02:23.479968 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9570 10:02:23.486682 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9571 10:02:23.490061 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9572 10:02:23.496723 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9573 10:02:23.499825 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9574 10:02:23.503666 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9575 10:02:23.510457 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9576 10:02:23.513579 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9577 10:02:23.516750 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9578 10:02:23.523704 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9579 10:02:23.526890 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9580 10:02:23.533741 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9581 10:02:23.536799 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9582 10:02:23.539931 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9583 10:02:23.546981 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9584 10:02:23.550131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9585 10:02:23.554022 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9586 10:02:23.560253 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9587 10:02:23.563504 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9588 10:02:23.566827 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9589 10:02:23.570458 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9590 10:02:23.576948 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9591 10:02:23.580562 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9592 10:02:23.583787 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9593 10:02:23.590896 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9594 10:02:23.594155 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9595 10:02:23.597470 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9596 10:02:23.603949 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9597 10:02:23.607318 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9598 10:02:23.613953 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9599 10:02:23.617546 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9600 10:02:23.620710 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9601 10:02:23.627522 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9602 10:02:23.630825 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9603 10:02:23.633976 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9604 10:02:23.640550 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9605 10:02:23.644101 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9606 10:02:23.650772 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9607 10:02:23.654265 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9608 10:02:23.657317 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9609 10:02:23.664145 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9610 10:02:23.667321 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9611 10:02:23.670426 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9612 10:02:23.677462 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9613 10:02:23.680636 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9614 10:02:23.687728 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9615 10:02:23.690964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9616 10:02:23.694212 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9617 10:02:23.700643 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9618 10:02:23.703960 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9619 10:02:23.710989 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9620 10:02:23.714315 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9621 10:02:23.717466 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9622 10:02:23.724380 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9623 10:02:23.727775 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9624 10:02:23.734007 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9625 10:02:23.737279 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9626 10:02:23.741134 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9627 10:02:23.747745 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9628 10:02:23.750891 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9629 10:02:23.754028 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9630 10:02:23.760750 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9631 10:02:23.764251 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9632 10:02:23.770749 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9633 10:02:23.773974 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9634 10:02:23.777182 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9635 10:02:23.783765 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9636 10:02:23.787572 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9637 10:02:23.794008 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9638 10:02:23.797580 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9639 10:02:23.800840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9640 10:02:23.807222 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9641 10:02:23.810456 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9642 10:02:23.813796 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9643 10:02:23.820464 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9644 10:02:23.824261 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9645 10:02:23.830775 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9646 10:02:23.834351 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9647 10:02:23.837340 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9648 10:02:23.843804 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9649 10:02:23.847546 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9650 10:02:23.853782 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9651 10:02:23.857665 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9652 10:02:23.861044 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9653 10:02:23.867381 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9654 10:02:23.870360 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9655 10:02:23.877374 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9656 10:02:23.880469 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9657 10:02:23.884106 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9658 10:02:23.890649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9659 10:02:23.894026 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9660 10:02:23.900238 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9661 10:02:23.903781 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9662 10:02:23.906753 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9663 10:02:23.913539 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9664 10:02:23.916707 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9665 10:02:23.923228 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9666 10:02:23.927086 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9667 10:02:23.933633 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9668 10:02:23.936879 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9669 10:02:23.939993 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9670 10:02:23.946798 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9671 10:02:23.950290 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9672 10:02:23.956918 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9673 10:02:23.959828 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9674 10:02:23.963339 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9675 10:02:23.969527 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9676 10:02:23.972866 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9677 10:02:23.980010 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9678 10:02:23.983006 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9679 10:02:23.989579 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9680 10:02:23.993243 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9681 10:02:23.996561 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9682 10:02:24.002998 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9683 10:02:24.006201 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9684 10:02:24.013141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9685 10:02:24.016217 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9686 10:02:24.022787 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9687 10:02:24.026627 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9688 10:02:24.029971 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9689 10:02:24.036431 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9690 10:02:24.039753 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9691 10:02:24.046194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9692 10:02:24.049353 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9693 10:02:24.052747 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9694 10:02:24.059805 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9695 10:02:24.062943 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9696 10:02:24.066003 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9697 10:02:24.072923 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9698 10:02:24.075789 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9699 10:02:24.079310 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9700 10:02:24.082322 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9701 10:02:24.089087 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9702 10:02:24.092783 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9703 10:02:24.099107 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9704 10:02:24.102327 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9705 10:02:24.106065 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9706 10:02:24.112424 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9707 10:02:24.115711 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9708 10:02:24.118945 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9709 10:02:24.125878 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9710 10:02:24.129597 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9711 10:02:24.132755 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9712 10:02:24.139362 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9713 10:02:24.142579 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9714 10:02:24.149571 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9715 10:02:24.153012 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9716 10:02:24.156304 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9717 10:02:24.162765 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9718 10:02:24.165897 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9719 10:02:24.169025 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9720 10:02:24.175988 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9721 10:02:24.179182 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9722 10:02:24.182851 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9723 10:02:24.189345 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9724 10:02:24.192480 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9725 10:02:24.196071 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9726 10:02:24.202502 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9727 10:02:24.205784 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9728 10:02:24.212547 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9729 10:02:24.215589 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9730 10:02:24.218930 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9731 10:02:24.225819 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9732 10:02:24.229103 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9733 10:02:24.232131 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9734 10:02:24.239054 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9735 10:02:24.242186 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9736 10:02:24.245624 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9737 10:02:24.248851 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9738 10:02:24.255340 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9739 10:02:24.259452 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9740 10:02:24.262552 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9741 10:02:24.265682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9742 10:02:24.272208 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9743 10:02:24.275934 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9744 10:02:24.279063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9745 10:02:24.282395 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9746 10:02:24.288847 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9747 10:02:24.292530 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9748 10:02:24.295417 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9749 10:02:24.302375 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9750 10:02:24.305509 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9751 10:02:24.308698 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9752 10:02:24.315878 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9753 10:02:24.318701 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9754 10:02:24.325402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9755 10:02:24.328775 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9756 10:02:24.332139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9757 10:02:24.338679 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9758 10:02:24.342474 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9759 10:02:24.348695 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9760 10:02:24.351935 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9761 10:02:24.358537 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9762 10:02:24.362445 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9763 10:02:24.365536 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9764 10:02:24.372466 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9765 10:02:24.375683 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9766 10:02:24.382148 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9767 10:02:24.385427 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9768 10:02:24.388811 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9769 10:02:24.395276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9770 10:02:24.399013 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9771 10:02:24.405694 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9772 10:02:24.408782 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9773 10:02:24.411793 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9774 10:02:24.418973 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9775 10:02:24.422358 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9776 10:02:24.428554 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9777 10:02:24.432403 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9778 10:02:24.438577 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9779 10:02:24.442163 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9780 10:02:24.445040 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9781 10:02:24.452248 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9782 10:02:24.455124 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9783 10:02:24.458452 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9784 10:02:24.465421 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9785 10:02:24.468642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9786 10:02:24.475517 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9787 10:02:24.478802 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9788 10:02:24.481996 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9789 10:02:24.488932 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9790 10:02:24.492069 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9791 10:02:24.498621 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9792 10:02:24.502375 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9793 10:02:24.505544 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9794 10:02:24.512402 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9795 10:02:24.515509 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9796 10:02:24.521980 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9797 10:02:24.525125 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9798 10:02:24.528907 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9799 10:02:24.535253 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9800 10:02:24.538659 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9801 10:02:24.545379 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9802 10:02:24.548390 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9803 10:02:24.555154 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9804 10:02:24.558455 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9805 10:02:24.561614 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9806 10:02:24.568575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9807 10:02:24.571409 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9808 10:02:24.577992 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9809 10:02:24.581223 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9810 10:02:24.588389 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9811 10:02:24.591558 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9812 10:02:24.594672 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9813 10:02:24.601248 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9814 10:02:24.604487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9815 10:02:24.611430 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9816 10:02:24.614495 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9817 10:02:24.617717 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9818 10:02:24.624532 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9819 10:02:24.627807 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9820 10:02:24.634156 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9821 10:02:24.638170 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9822 10:02:24.641354 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9823 10:02:24.647707 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9824 10:02:24.651365 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9825 10:02:24.657751 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9826 10:02:24.661424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9827 10:02:24.667816 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9828 10:02:24.670962 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9829 10:02:24.674253 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9830 10:02:24.680911 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9831 10:02:24.684609 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9832 10:02:24.691341 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9833 10:02:24.694507 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9834 10:02:24.700781 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9835 10:02:24.704485 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9836 10:02:24.707707 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9837 10:02:24.714214 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9838 10:02:24.717294 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9839 10:02:24.724328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9840 10:02:24.727473 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9841 10:02:24.733887 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9842 10:02:24.737616 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9843 10:02:24.743928 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9844 10:02:24.747281 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9845 10:02:24.751023 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9846 10:02:24.757345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9847 10:02:24.760514 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9848 10:02:24.767513 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9849 10:02:24.770632 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9850 10:02:24.777280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9851 10:02:24.780437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9852 10:02:24.783986 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9853 10:02:24.790834 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9854 10:02:24.793996 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9855 10:02:24.800389 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9856 10:02:24.803797 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9857 10:02:24.810185 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9858 10:02:24.813981 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9859 10:02:24.820230 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9860 10:02:24.823993 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9861 10:02:24.827179 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9862 10:02:24.833652 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9863 10:02:24.836908 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9864 10:02:24.843340 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9865 10:02:24.847040 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9866 10:02:24.853510 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9867 10:02:24.856784 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9868 10:02:24.859822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9869 10:02:24.866921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9870 10:02:24.870203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9871 10:02:24.876746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9872 10:02:24.879710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9873 10:02:24.886942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9874 10:02:24.889929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9875 10:02:24.896624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9876 10:02:24.900229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9877 10:02:24.903300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9878 10:02:24.909814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9879 10:02:24.913356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9880 10:02:24.919762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9881 10:02:24.923466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9882 10:02:24.929771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9883 10:02:24.932954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9884 10:02:24.940130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9885 10:02:24.943311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9886 10:02:24.949728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9887 10:02:24.952895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9888 10:02:24.959839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9889 10:02:24.963009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9890 10:02:24.969529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9891 10:02:24.973313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9892 10:02:24.979745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9893 10:02:24.983599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9894 10:02:24.989694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9895 10:02:24.993324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9896 10:02:24.999973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9897 10:02:25.003018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9898 10:02:25.009728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9899 10:02:25.013120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9900 10:02:25.019701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9901 10:02:25.022727 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9902 10:02:25.026228 INFO: [APUAPC] vio 0
9903 10:02:25.029265 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9904 10:02:25.036323 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9905 10:02:25.039625 INFO: [APUAPC] D0_APC_0: 0x400510
9906 10:02:25.039718 INFO: [APUAPC] D0_APC_1: 0x0
9907 10:02:25.042918 INFO: [APUAPC] D0_APC_2: 0x1540
9908 10:02:25.046107 INFO: [APUAPC] D0_APC_3: 0x0
9909 10:02:25.049162 INFO: [APUAPC] D1_APC_0: 0xffffffff
9910 10:02:25.052774 INFO: [APUAPC] D1_APC_1: 0xffffffff
9911 10:02:25.055795 INFO: [APUAPC] D1_APC_2: 0x3fffff
9912 10:02:25.059010 INFO: [APUAPC] D1_APC_3: 0x0
9913 10:02:25.062893 INFO: [APUAPC] D2_APC_0: 0xffffffff
9914 10:02:25.065866 INFO: [APUAPC] D2_APC_1: 0xffffffff
9915 10:02:25.069588 INFO: [APUAPC] D2_APC_2: 0x3fffff
9916 10:02:25.072804 INFO: [APUAPC] D2_APC_3: 0x0
9917 10:02:25.076048 INFO: [APUAPC] D3_APC_0: 0xffffffff
9918 10:02:25.079416 INFO: [APUAPC] D3_APC_1: 0xffffffff
9919 10:02:25.082587 INFO: [APUAPC] D3_APC_2: 0x3fffff
9920 10:02:25.085694 INFO: [APUAPC] D3_APC_3: 0x0
9921 10:02:25.088942 INFO: [APUAPC] D4_APC_0: 0xffffffff
9922 10:02:25.092348 INFO: [APUAPC] D4_APC_1: 0xffffffff
9923 10:02:25.095509 INFO: [APUAPC] D4_APC_2: 0x3fffff
9924 10:02:25.099316 INFO: [APUAPC] D4_APC_3: 0x0
9925 10:02:25.102527 INFO: [APUAPC] D5_APC_0: 0xffffffff
9926 10:02:25.105598 INFO: [APUAPC] D5_APC_1: 0xffffffff
9927 10:02:25.109197 INFO: [APUAPC] D5_APC_2: 0x3fffff
9928 10:02:25.112725 INFO: [APUAPC] D5_APC_3: 0x0
9929 10:02:25.115829 INFO: [APUAPC] D6_APC_0: 0xffffffff
9930 10:02:25.118954 INFO: [APUAPC] D6_APC_1: 0xffffffff
9931 10:02:25.122647 INFO: [APUAPC] D6_APC_2: 0x3fffff
9932 10:02:25.125872 INFO: [APUAPC] D6_APC_3: 0x0
9933 10:02:25.129146 INFO: [APUAPC] D7_APC_0: 0xffffffff
9934 10:02:25.132274 INFO: [APUAPC] D7_APC_1: 0xffffffff
9935 10:02:25.135769 INFO: [APUAPC] D7_APC_2: 0x3fffff
9936 10:02:25.139283 INFO: [APUAPC] D7_APC_3: 0x0
9937 10:02:25.142379 INFO: [APUAPC] D8_APC_0: 0xffffffff
9938 10:02:25.145670 INFO: [APUAPC] D8_APC_1: 0xffffffff
9939 10:02:25.148952 INFO: [APUAPC] D8_APC_2: 0x3fffff
9940 10:02:25.152244 INFO: [APUAPC] D8_APC_3: 0x0
9941 10:02:25.155569 INFO: [APUAPC] D9_APC_0: 0xffffffff
9942 10:02:25.159134 INFO: [APUAPC] D9_APC_1: 0xffffffff
9943 10:02:25.162198 INFO: [APUAPC] D9_APC_2: 0x3fffff
9944 10:02:25.162277 INFO: [APUAPC] D9_APC_3: 0x0
9945 10:02:25.169264 INFO: [APUAPC] D10_APC_0: 0xffffffff
9946 10:02:25.172331 INFO: [APUAPC] D10_APC_1: 0xffffffff
9947 10:02:25.176004 INFO: [APUAPC] D10_APC_2: 0x3fffff
9948 10:02:25.176085 INFO: [APUAPC] D10_APC_3: 0x0
9949 10:02:25.182448 INFO: [APUAPC] D11_APC_0: 0xffffffff
9950 10:02:25.185642 INFO: [APUAPC] D11_APC_1: 0xffffffff
9951 10:02:25.188907 INFO: [APUAPC] D11_APC_2: 0x3fffff
9952 10:02:25.188988 INFO: [APUAPC] D11_APC_3: 0x0
9953 10:02:25.196011 INFO: [APUAPC] D12_APC_0: 0xffffffff
9954 10:02:25.199109 INFO: [APUAPC] D12_APC_1: 0xffffffff
9955 10:02:25.202381 INFO: [APUAPC] D12_APC_2: 0x3fffff
9956 10:02:25.202461 INFO: [APUAPC] D12_APC_3: 0x0
9957 10:02:25.208752 INFO: [APUAPC] D13_APC_0: 0xffffffff
9958 10:02:25.212582 INFO: [APUAPC] D13_APC_1: 0xffffffff
9959 10:02:25.215746 INFO: [APUAPC] D13_APC_2: 0x3fffff
9960 10:02:25.219229 INFO: [APUAPC] D13_APC_3: 0x0
9961 10:02:25.222701 INFO: [APUAPC] D14_APC_0: 0xffffffff
9962 10:02:25.225525 INFO: [APUAPC] D14_APC_1: 0xffffffff
9963 10:02:25.229219 INFO: [APUAPC] D14_APC_2: 0x3fffff
9964 10:02:25.232465 INFO: [APUAPC] D14_APC_3: 0x0
9965 10:02:25.235817 INFO: [APUAPC] D15_APC_0: 0xffffffff
9966 10:02:25.239042 INFO: [APUAPC] D15_APC_1: 0xffffffff
9967 10:02:25.242230 INFO: [APUAPC] D15_APC_2: 0x3fffff
9968 10:02:25.245360 INFO: [APUAPC] D15_APC_3: 0x0
9969 10:02:25.245440 INFO: [APUAPC] APC_CON: 0x4
9970 10:02:25.249009 INFO: [NOCDAPC] D0_APC_0: 0x0
9971 10:02:25.252428 INFO: [NOCDAPC] D0_APC_1: 0x0
9972 10:02:25.255665 INFO: [NOCDAPC] D1_APC_0: 0x0
9973 10:02:25.258965 INFO: [NOCDAPC] D1_APC_1: 0xfff
9974 10:02:25.262336 INFO: [NOCDAPC] D2_APC_0: 0x0
9975 10:02:25.265414 INFO: [NOCDAPC] D2_APC_1: 0xfff
9976 10:02:25.268660 INFO: [NOCDAPC] D3_APC_0: 0x0
9977 10:02:25.272284 INFO: [NOCDAPC] D3_APC_1: 0xfff
9978 10:02:25.272363 INFO: [NOCDAPC] D4_APC_0: 0x0
9979 10:02:25.275306 INFO: [NOCDAPC] D4_APC_1: 0xfff
9980 10:02:25.278758 INFO: [NOCDAPC] D5_APC_0: 0x0
9981 10:02:25.281842 INFO: [NOCDAPC] D5_APC_1: 0xfff
9982 10:02:25.285619 INFO: [NOCDAPC] D6_APC_0: 0x0
9983 10:02:25.288851 INFO: [NOCDAPC] D6_APC_1: 0xfff
9984 10:02:25.292021 INFO: [NOCDAPC] D7_APC_0: 0x0
9985 10:02:25.295318 INFO: [NOCDAPC] D7_APC_1: 0xfff
9986 10:02:25.298570 INFO: [NOCDAPC] D8_APC_0: 0x0
9987 10:02:25.301721 INFO: [NOCDAPC] D8_APC_1: 0xfff
9988 10:02:25.305423 INFO: [NOCDAPC] D9_APC_0: 0x0
9989 10:02:25.305502 INFO: [NOCDAPC] D9_APC_1: 0xfff
9990 10:02:25.308606 INFO: [NOCDAPC] D10_APC_0: 0x0
9991 10:02:25.311768 INFO: [NOCDAPC] D10_APC_1: 0xfff
9992 10:02:25.315680 INFO: [NOCDAPC] D11_APC_0: 0x0
9993 10:02:25.319000 INFO: [NOCDAPC] D11_APC_1: 0xfff
9994 10:02:25.322137 INFO: [NOCDAPC] D12_APC_0: 0x0
9995 10:02:25.325162 INFO: [NOCDAPC] D12_APC_1: 0xfff
9996 10:02:25.328949 INFO: [NOCDAPC] D13_APC_0: 0x0
9997 10:02:25.331988 INFO: [NOCDAPC] D13_APC_1: 0xfff
9998 10:02:25.335723 INFO: [NOCDAPC] D14_APC_0: 0x0
9999 10:02:25.338581 INFO: [NOCDAPC] D14_APC_1: 0xfff
10000 10:02:25.341749 INFO: [NOCDAPC] D15_APC_0: 0x0
10001 10:02:25.345646 INFO: [NOCDAPC] D15_APC_1: 0xfff
10002 10:02:25.348367 INFO: [NOCDAPC] APC_CON: 0x4
10003 10:02:25.351622 INFO: [APUAPC] set_apusys_apc done
10004 10:02:25.351702 INFO: [DEVAPC] devapc_init done
10005 10:02:25.358388 INFO: GICv3 without legacy support detected.
10006 10:02:25.361708 INFO: ARM GICv3 driver initialized in EL3
10007 10:02:25.365143 INFO: Maximum SPI INTID supported: 639
10008 10:02:25.368658 INFO: BL31: Initializing runtime services
10009 10:02:25.375738 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10010 10:02:25.378916 INFO: SPM: enable CPC mode
10011 10:02:25.382068 INFO: mcdi ready for mcusys-off-idle and system suspend
10012 10:02:25.388691 INFO: BL31: Preparing for EL3 exit to normal world
10013 10:02:25.391808 INFO: Entry point address = 0x80000000
10014 10:02:25.391888 INFO: SPSR = 0x8
10015 10:02:25.399326
10016 10:02:25.399405
10017 10:02:25.399468
10018 10:02:25.402662 Starting depthcharge on Spherion...
10019 10:02:25.402741
10020 10:02:25.402803 Wipe memory regions:
10021 10:02:25.402861
10022 10:02:25.403520 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10023 10:02:25.403647 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10024 10:02:25.403759 Setting prompt string to ['asurada:']
10025 10:02:25.403839 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10026 10:02:25.405792 [0x00000040000000, 0x00000054600000)
10027 10:02:25.528170
10028 10:02:25.528286 [0x00000054660000, 0x00000080000000)
10029 10:02:25.788667
10030 10:02:25.788798 [0x000000821a7280, 0x000000ffe64000)
10031 10:02:26.533796
10032 10:02:26.533935 [0x00000100000000, 0x00000240000000)
10033 10:02:28.423658
10034 10:02:28.426834 Initializing XHCI USB controller at 0x11200000.
10035 10:02:29.465665
10036 10:02:29.468906 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10037 10:02:29.468997
10038 10:02:29.469061
10039 10:02:29.469142
10040 10:02:29.469424 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 10:02:29.569760 asurada: tftpboot 192.168.201.1 11336429/tftp-deploy-fwpr3tbr/kernel/image.itb 11336429/tftp-deploy-fwpr3tbr/kernel/cmdline
10043 10:02:29.569899 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10044 10:02:29.569985 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10045 10:02:29.574000 tftpboot 192.168.201.1 11336429/tftp-deploy-fwpr3tbr/kernel/image.ittp-deploy-fwpr3tbr/kernel/cmdline
10046 10:02:29.574084
10047 10:02:29.574147 Waiting for link
10048 10:02:29.734393
10049 10:02:29.734517 R8152: Initializing
10050 10:02:29.734605
10051 10:02:29.737620 Version 9 (ocp_data = 6010)
10052 10:02:29.737702
10053 10:02:29.740830 R8152: Done initializing
10054 10:02:29.740910
10055 10:02:29.740975 Adding net device
10056 10:02:31.613678
10057 10:02:31.613837 done.
10058 10:02:31.613905
10059 10:02:31.613965 MAC: 00:e0:4c:78:7a:aa
10060 10:02:31.614023
10061 10:02:31.617298 Sending DHCP discover... done.
10062 10:02:31.617382
10063 10:02:31.620595 Waiting for reply... done.
10064 10:02:31.620677
10065 10:02:31.623780 Sending DHCP request... done.
10066 10:02:31.623861
10067 10:02:31.623925 Waiting for reply... done.
10068 10:02:31.623985
10069 10:02:31.627005 My ip is 192.168.201.12
10070 10:02:31.627086
10071 10:02:31.630218 The DHCP server ip is 192.168.201.1
10072 10:02:31.630300
10073 10:02:31.633817 TFTP server IP predefined by user: 192.168.201.1
10074 10:02:31.633899
10075 10:02:31.640118 Bootfile predefined by user: 11336429/tftp-deploy-fwpr3tbr/kernel/image.itb
10076 10:02:31.640206
10077 10:02:31.643984 Sending tftp read request... done.
10078 10:02:31.644065
10079 10:02:31.647215 Waiting for the transfer...
10080 10:02:31.647295
10081 10:02:31.898807 00000000 ################################################################
10082 10:02:31.898940
10083 10:02:32.146906 00080000 ################################################################
10084 10:02:32.147047
10085 10:02:32.398384 00100000 ################################################################
10086 10:02:32.398517
10087 10:02:32.648713 00180000 ################################################################
10088 10:02:32.648854
10089 10:02:32.899638 00200000 ################################################################
10090 10:02:32.899780
10091 10:02:33.153717 00280000 ################################################################
10092 10:02:33.153883
10093 10:02:33.401099 00300000 ################################################################
10094 10:02:33.401244
10095 10:02:33.651232 00380000 ################################################################
10096 10:02:33.651368
10097 10:02:33.912276 00400000 ################################################################
10098 10:02:33.912419
10099 10:02:34.196409 00480000 ################################################################
10100 10:02:34.196552
10101 10:02:34.453289 00500000 ################################################################
10102 10:02:34.453454
10103 10:02:34.712284 00580000 ################################################################
10104 10:02:34.712416
10105 10:02:34.962233 00600000 ################################################################
10106 10:02:34.962393
10107 10:02:35.209237 00680000 ################################################################
10108 10:02:35.209377
10109 10:02:35.456265 00700000 ################################################################
10110 10:02:35.456406
10111 10:02:35.709990 00780000 ################################################################
10112 10:02:35.710120
10113 10:02:35.963481 00800000 ################################################################
10114 10:02:35.963642
10115 10:02:36.212915 00880000 ################################################################
10116 10:02:36.213056
10117 10:02:36.465593 00900000 ################################################################
10118 10:02:36.465761
10119 10:02:36.712007 00980000 ################################################################
10120 10:02:36.712144
10121 10:02:36.967382 00a00000 ################################################################
10122 10:02:36.967514
10123 10:02:37.217462 00a80000 ################################################################
10124 10:02:37.217594
10125 10:02:37.468011 00b00000 ################################################################
10126 10:02:37.468143
10127 10:02:37.717291 00b80000 ################################################################
10128 10:02:37.717425
10129 10:02:37.970371 00c00000 ################################################################
10130 10:02:37.970523
10131 10:02:38.225527 00c80000 ################################################################
10132 10:02:38.225659
10133 10:02:38.473314 00d00000 ################################################################
10134 10:02:38.473444
10135 10:02:38.727161 00d80000 ################################################################
10136 10:02:38.727293
10137 10:02:38.978313 00e00000 ################################################################
10138 10:02:38.978444
10139 10:02:39.227587 00e80000 ################################################################
10140 10:02:39.227752
10141 10:02:39.478641 00f00000 ################################################################
10142 10:02:39.478784
10143 10:02:39.727888 00f80000 ################################################################
10144 10:02:39.728031
10145 10:02:39.977250 01000000 ################################################################
10146 10:02:39.977391
10147 10:02:40.226889 01080000 ################################################################
10148 10:02:40.227020
10149 10:02:40.476857 01100000 ################################################################
10150 10:02:40.476989
10151 10:02:40.726123 01180000 ################################################################
10152 10:02:40.726261
10153 10:02:40.975944 01200000 ################################################################
10154 10:02:40.976114
10155 10:02:41.229221 01280000 ################################################################
10156 10:02:41.229349
10157 10:02:41.479826 01300000 ################################################################
10158 10:02:41.479956
10159 10:02:41.738302 01380000 ################################################################
10160 10:02:41.738498
10161 10:02:42.004119 01400000 ################################################################
10162 10:02:42.004252
10163 10:02:42.280323 01480000 ################################################################
10164 10:02:42.280454
10165 10:02:42.555922 01500000 ################################################################
10166 10:02:42.556056
10167 10:02:42.814066 01580000 ################################################################
10168 10:02:42.814195
10169 10:02:43.064406 01600000 ################################################################
10170 10:02:43.064548
10171 10:02:43.328622 01680000 ################################################################
10172 10:02:43.328769
10173 10:02:43.594242 01700000 ################################################################
10174 10:02:43.594411
10175 10:02:43.846989 01780000 ################################################################
10176 10:02:43.847151
10177 10:02:44.098301 01800000 ################################################################
10178 10:02:44.098468
10179 10:02:44.348913 01880000 ################################################################
10180 10:02:44.349069
10181 10:02:44.598774 01900000 ################################################################
10182 10:02:44.598935
10183 10:02:44.868652 01980000 ################################################################
10184 10:02:44.868786
10185 10:02:45.151474 01a00000 ################################################################
10186 10:02:45.151665
10187 10:02:45.415533 01a80000 ################################################################
10188 10:02:45.415682
10189 10:02:45.667912 01b00000 ################################################################
10190 10:02:45.668065
10191 10:02:45.917570 01b80000 ################################################################
10192 10:02:45.917720
10193 10:02:46.167614 01c00000 ################################################################
10194 10:02:46.167771
10195 10:02:46.417650 01c80000 ################################################################
10196 10:02:46.417816
10197 10:02:46.666992 01d00000 ################################################################
10198 10:02:46.667134
10199 10:02:46.917429 01d80000 ################################################################
10200 10:02:46.917589
10201 10:02:47.167370 01e00000 ################################################################
10202 10:02:47.167506
10203 10:02:47.393611 01e80000 ########################################################### done.
10204 10:02:47.393740
10205 10:02:47.396783 The bootfile was 32462030 bytes long.
10206 10:02:47.396870
10207 10:02:47.400328 Sending tftp read request... done.
10208 10:02:47.400417
10209 10:02:47.403334 Waiting for the transfer...
10210 10:02:47.403458
10211 10:02:47.406870 00000000 # done.
10212 10:02:47.407047
10213 10:02:47.414018 Command line loaded dynamically from TFTP file: 11336429/tftp-deploy-fwpr3tbr/kernel/cmdline
10214 10:02:47.414204
10215 10:02:47.426939 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10216 10:02:47.427174
10217 10:02:47.430213 Loading FIT.
10218 10:02:47.430441
10219 10:02:47.430571 Image ramdisk-1 has 21375458 bytes.
10220 10:02:47.433520
10221 10:02:47.433768 Image fdt-1 has 47278 bytes.
10222 10:02:47.433917
10223 10:02:47.436889 Image kernel-1 has 11037260 bytes.
10224 10:02:47.437090
10225 10:02:47.447021 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10226 10:02:47.447421
10227 10:02:47.463349 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10228 10:02:47.463940
10229 10:02:47.470511 Choosing best match conf-1 for compat google,spherion-rev2.
10230 10:02:47.474108
10231 10:02:47.478780 Connected to device vid:did:rid of 1ae0:0028:00
10232 10:02:47.487060
10233 10:02:47.489880 tpm_get_response: command 0x17b, return code 0x0
10234 10:02:47.490394
10235 10:02:47.493237 ec_init: CrosEC protocol v3 supported (256, 248)
10236 10:02:47.497427
10237 10:02:47.500214 tpm_cleanup: add release locality here.
10238 10:02:47.500730
10239 10:02:47.501103 Shutting down all USB controllers.
10240 10:02:47.503649
10241 10:02:47.504115 Removing current net device
10242 10:02:47.504482
10243 10:02:47.510813 Exiting depthcharge with code 4 at timestamp: 51362257
10244 10:02:47.511273
10245 10:02:47.514111 LZMA decompressing kernel-1 to 0x821a6718
10246 10:02:47.514568
10247 10:02:47.517046 LZMA decompressing kernel-1 to 0x40000000
10248 10:02:48.903702
10249 10:02:48.904194 jumping to kernel
10250 10:02:48.905517 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10251 10:02:48.905986 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10252 10:02:48.906359 Setting prompt string to ['Linux version [0-9]']
10253 10:02:48.906703 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10254 10:02:48.907039 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10255 10:02:48.986317
10256 10:02:48.988986 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10257 10:02:48.993063 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10258 10:02:48.993533 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10259 10:02:48.993895 Setting prompt string to []
10260 10:02:48.994283 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10261 10:02:48.994657 Using line separator: #'\n'#
10262 10:02:48.994973 No login prompt set.
10263 10:02:48.995277 Parsing kernel messages
10264 10:02:48.995560 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10265 10:02:48.996092 [login-action] Waiting for messages, (timeout 00:04:02)
10266 10:02:49.012290 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j18697-arm64-gcc-10-defconfig-arm64-chromebook-vvl9c) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 23 09:52:58 UTC 2023
10267 10:02:49.015924 [ 0.000000] random: crng init done
10268 10:02:49.019425 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10269 10:02:49.022660 [ 0.000000] efi: UEFI not found.
10270 10:02:49.032861 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10271 10:02:49.039073 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10272 10:02:49.049143 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10273 10:02:49.058699 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10274 10:02:49.066586 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10275 10:02:49.069337 [ 0.000000] printk: bootconsole [mtk8250] enabled
10276 10:02:49.077475 [ 0.000000] NUMA: No NUMA configuration found
10277 10:02:49.084126 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10278 10:02:49.090995 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10279 10:02:49.091567 [ 0.000000] Zone ranges:
10280 10:02:49.097226 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10281 10:02:49.100716 [ 0.000000] DMA32 empty
10282 10:02:49.107776 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10283 10:02:49.111072 [ 0.000000] Movable zone start for each node
10284 10:02:49.114277 [ 0.000000] Early memory node ranges
10285 10:02:49.120473 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10286 10:02:49.127326 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10287 10:02:49.134145 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10288 10:02:49.140987 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10289 10:02:49.147425 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10290 10:02:49.153596 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10291 10:02:49.210177 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10292 10:02:49.216456 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10293 10:02:49.223316 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10294 10:02:49.226534 [ 0.000000] psci: probing for conduit method from DT.
10295 10:02:49.232958 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10296 10:02:49.236828 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10297 10:02:49.242894 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10298 10:02:49.246142 [ 0.000000] psci: SMC Calling Convention v1.2
10299 10:02:49.253251 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10300 10:02:49.256362 [ 0.000000] Detected VIPT I-cache on CPU0
10301 10:02:49.263216 [ 0.000000] CPU features: detected: GIC system register CPU interface
10302 10:02:49.269654 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10303 10:02:49.276392 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10304 10:02:49.283318 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10305 10:02:49.289878 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10306 10:02:49.299490 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10307 10:02:49.303450 [ 0.000000] alternatives: applying boot alternatives
10308 10:02:49.309382 [ 0.000000] Fallback order for Node 0: 0
10309 10:02:49.316072 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10310 10:02:49.319865 [ 0.000000] Policy zone: Normal
10311 10:02:49.333316 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10312 10:02:49.342529 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10313 10:02:49.354785 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10314 10:02:49.364577 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10315 10:02:49.371187 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10316 10:02:49.374762 <6>[ 0.000000] software IO TLB: area num 8.
10317 10:02:49.432215 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10318 10:02:49.582016 <6>[ 0.000000] Memory: 7948684K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 404084K reserved, 32768K cma-reserved)
10319 10:02:49.588075 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10320 10:02:49.594817 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10321 10:02:49.598118 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10322 10:02:49.604910 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10323 10:02:49.611245 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10324 10:02:49.614585 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10325 10:02:49.624407 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10326 10:02:49.631170 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10327 10:02:49.637869 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10328 10:02:49.644219 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10329 10:02:49.647527 <6>[ 0.000000] GICv3: 608 SPIs implemented
10330 10:02:49.651718 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10331 10:02:49.657539 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10332 10:02:49.660853 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10333 10:02:49.667738 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10334 10:02:49.680886 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10335 10:02:49.690469 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10336 10:02:49.700882 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10337 10:02:49.707905 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10338 10:02:49.721468 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10339 10:02:49.727915 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10340 10:02:49.734590 <6>[ 0.009182] Console: colour dummy device 80x25
10341 10:02:49.744358 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10342 10:02:49.751638 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10343 10:02:49.754700 <6>[ 0.029316] LSM: Security Framework initializing
10344 10:02:49.761010 <6>[ 0.034252] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10345 10:02:49.771110 <6>[ 0.042065] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10346 10:02:49.777377 <6>[ 0.051501] cblist_init_generic: Setting adjustable number of callback queues.
10347 10:02:49.784316 <6>[ 0.058945] cblist_init_generic: Setting shift to 3 and lim to 1.
10348 10:02:49.794454 <6>[ 0.065324] cblist_init_generic: Setting adjustable number of callback queues.
10349 10:02:49.800614 <6>[ 0.072795] cblist_init_generic: Setting shift to 3 and lim to 1.
10350 10:02:49.803857 <6>[ 0.079196] rcu: Hierarchical SRCU implementation.
10351 10:02:49.810432 <6>[ 0.084210] rcu: Max phase no-delay instances is 1000.
10352 10:02:49.817254 <6>[ 0.091234] EFI services will not be available.
10353 10:02:49.820322 <6>[ 0.096203] smp: Bringing up secondary CPUs ...
10354 10:02:49.829276 <6>[ 0.101259] Detected VIPT I-cache on CPU1
10355 10:02:49.835202 <6>[ 0.101329] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10356 10:02:49.842150 <6>[ 0.101363] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10357 10:02:49.845723 <6>[ 0.101698] Detected VIPT I-cache on CPU2
10358 10:02:49.852035 <6>[ 0.101750] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10359 10:02:49.858471 <6>[ 0.101767] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10360 10:02:49.865866 <6>[ 0.102032] Detected VIPT I-cache on CPU3
10361 10:02:49.872317 <6>[ 0.102078] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10362 10:02:49.878781 <6>[ 0.102092] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10363 10:02:49.882044 <6>[ 0.102399] CPU features: detected: Spectre-v4
10364 10:02:49.889111 <6>[ 0.102405] CPU features: detected: Spectre-BHB
10365 10:02:49.891698 <6>[ 0.102410] Detected PIPT I-cache on CPU4
10366 10:02:49.899168 <6>[ 0.102465] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10367 10:02:49.905789 <6>[ 0.102483] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10368 10:02:49.911575 <6>[ 0.102775] Detected PIPT I-cache on CPU5
10369 10:02:49.918662 <6>[ 0.102837] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10370 10:02:49.925267 <6>[ 0.102853] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10371 10:02:49.928560 <6>[ 0.103140] Detected PIPT I-cache on CPU6
10372 10:02:49.935533 <6>[ 0.103203] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10373 10:02:49.941408 <6>[ 0.103219] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10374 10:02:49.948512 <6>[ 0.103519] Detected PIPT I-cache on CPU7
10375 10:02:49.955149 <6>[ 0.103584] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10376 10:02:49.961822 <6>[ 0.103600] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10377 10:02:49.964884 <6>[ 0.103647] smp: Brought up 1 node, 8 CPUs
10378 10:02:49.972082 <6>[ 0.244923] SMP: Total of 8 processors activated.
10379 10:02:49.974521 <6>[ 0.249874] CPU features: detected: 32-bit EL0 Support
10380 10:02:49.985012 <6>[ 0.255238] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10381 10:02:49.991461 <6>[ 0.264093] CPU features: detected: Common not Private translations
10382 10:02:49.994977 <6>[ 0.270569] CPU features: detected: CRC32 instructions
10383 10:02:50.001169 <6>[ 0.275920] CPU features: detected: RCpc load-acquire (LDAPR)
10384 10:02:50.007661 <6>[ 0.281880] CPU features: detected: LSE atomic instructions
10385 10:02:50.014743 <6>[ 0.287662] CPU features: detected: Privileged Access Never
10386 10:02:50.017937 <6>[ 0.293478] CPU features: detected: RAS Extension Support
10387 10:02:50.027837 <6>[ 0.299087] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10388 10:02:50.031071 <6>[ 0.306306] CPU: All CPU(s) started at EL2
10389 10:02:50.037640 <6>[ 0.310623] alternatives: applying system-wide alternatives
10390 10:02:50.046116 <6>[ 0.321321] devtmpfs: initialized
10391 10:02:50.058855 <6>[ 0.330226] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10392 10:02:50.068928 <6>[ 0.340185] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10393 10:02:50.075415 <6>[ 0.348349] pinctrl core: initialized pinctrl subsystem
10394 10:02:50.078721 <6>[ 0.355016] DMI not present or invalid.
10395 10:02:50.085540 <6>[ 0.359422] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10396 10:02:50.095746 <6>[ 0.366274] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10397 10:02:50.102052 <6>[ 0.373854] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10398 10:02:50.112121 <6>[ 0.382076] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10399 10:02:50.115075 <6>[ 0.390319] audit: initializing netlink subsys (disabled)
10400 10:02:50.124906 <5>[ 0.396014] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10401 10:02:50.131766 <6>[ 0.396717] thermal_sys: Registered thermal governor 'step_wise'
10402 10:02:50.138505 <6>[ 0.403982] thermal_sys: Registered thermal governor 'power_allocator'
10403 10:02:50.141530 <6>[ 0.410239] cpuidle: using governor menu
10404 10:02:50.148231 <6>[ 0.421199] NET: Registered PF_QIPCRTR protocol family
10405 10:02:50.154905 <6>[ 0.426676] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10406 10:02:50.158083 <6>[ 0.433784] ASID allocator initialised with 32768 entries
10407 10:02:50.165226 <6>[ 0.440343] Serial: AMBA PL011 UART driver
10408 10:02:50.174469 <4>[ 0.449164] Trying to register duplicate clock ID: 134
10409 10:02:50.228663 <6>[ 0.506499] KASLR enabled
10410 10:02:50.242833 <6>[ 0.514196] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10411 10:02:50.249614 <6>[ 0.521211] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10412 10:02:50.256281 <6>[ 0.527700] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10413 10:02:50.263062 <6>[ 0.534703] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10414 10:02:50.269444 <6>[ 0.541188] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10415 10:02:50.275674 <6>[ 0.548191] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10416 10:02:50.282535 <6>[ 0.554678] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10417 10:02:50.289319 <6>[ 0.561682] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10418 10:02:50.292440 <6>[ 0.569186] ACPI: Interpreter disabled.
10419 10:02:50.300999 <6>[ 0.575575] iommu: Default domain type: Translated
10420 10:02:50.307007 <6>[ 0.580689] iommu: DMA domain TLB invalidation policy: strict mode
10421 10:02:50.310938 <5>[ 0.587341] SCSI subsystem initialized
10422 10:02:50.317120 <6>[ 0.591503] usbcore: registered new interface driver usbfs
10423 10:02:50.323935 <6>[ 0.597235] usbcore: registered new interface driver hub
10424 10:02:50.327685 <6>[ 0.602785] usbcore: registered new device driver usb
10425 10:02:50.333774 <6>[ 0.608874] pps_core: LinuxPPS API ver. 1 registered
10426 10:02:50.343831 <6>[ 0.614067] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10427 10:02:50.346934 <6>[ 0.623415] PTP clock support registered
10428 10:02:50.350810 <6>[ 0.627658] EDAC MC: Ver: 3.0.0
10429 10:02:50.358043 <6>[ 0.632811] FPGA manager framework
10430 10:02:50.361491 <6>[ 0.636491] Advanced Linux Sound Architecture Driver Initialized.
10431 10:02:50.364950 <6>[ 0.643258] vgaarb: loaded
10432 10:02:50.371654 <6>[ 0.646427] clocksource: Switched to clocksource arch_sys_counter
10433 10:02:50.378224 <5>[ 0.652866] VFS: Disk quotas dquot_6.6.0
10434 10:02:50.385455 <6>[ 0.657051] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10435 10:02:50.388203 <6>[ 0.664238] pnp: PnP ACPI: disabled
10436 10:02:50.396506 <6>[ 0.670902] NET: Registered PF_INET protocol family
10437 10:02:50.402897 <6>[ 0.676180] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10438 10:02:50.416952 <6>[ 0.688477] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10439 10:02:50.427563 <6>[ 0.697290] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10440 10:02:50.433654 <6>[ 0.705259] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10441 10:02:50.440038 <6>[ 0.713957] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10442 10:02:50.451947 <6>[ 0.723710] TCP: Hash tables configured (established 65536 bind 65536)
10443 10:02:50.459189 <6>[ 0.730566] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10444 10:02:50.465559 <6>[ 0.737767] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10445 10:02:50.472595 <6>[ 0.745467] NET: Registered PF_UNIX/PF_LOCAL protocol family
10446 10:02:50.478520 <6>[ 0.751640] RPC: Registered named UNIX socket transport module.
10447 10:02:50.482367 <6>[ 0.757794] RPC: Registered udp transport module.
10448 10:02:50.489206 <6>[ 0.762728] RPC: Registered tcp transport module.
10449 10:02:50.495499 <6>[ 0.767660] RPC: Registered tcp NFSv4.1 backchannel transport module.
10450 10:02:50.499016 <6>[ 0.774330] PCI: CLS 0 bytes, default 64
10451 10:02:50.502649 <6>[ 0.778726] Unpacking initramfs...
10452 10:02:50.523455 <6>[ 0.795051] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10453 10:02:50.533944 <6>[ 0.803713] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10454 10:02:50.536597 <6>[ 0.812600] kvm [1]: IPA Size Limit: 40 bits
10455 10:02:50.543489 <6>[ 0.817126] kvm [1]: GICv3: no GICV resource entry
10456 10:02:50.546633 <6>[ 0.822149] kvm [1]: disabling GICv2 emulation
10457 10:02:50.553670 <6>[ 0.826835] kvm [1]: GIC system register CPU interface enabled
10458 10:02:50.556953 <6>[ 0.832997] kvm [1]: vgic interrupt IRQ18
10459 10:02:50.563749 <6>[ 0.837350] kvm [1]: VHE mode initialized successfully
10460 10:02:50.570189 <5>[ 0.843776] Initialise system trusted keyrings
10461 10:02:50.576791 <6>[ 0.848570] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10462 10:02:50.583975 <6>[ 0.858568] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10463 10:02:50.590873 <5>[ 0.864966] NFS: Registering the id_resolver key type
10464 10:02:50.593544 <5>[ 0.870266] Key type id_resolver registered
10465 10:02:50.600755 <5>[ 0.874681] Key type id_legacy registered
10466 10:02:50.607434 <6>[ 0.878962] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10467 10:02:50.614170 <6>[ 0.885883] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10468 10:02:50.620005 <6>[ 0.893601] 9p: Installing v9fs 9p2000 file system support
10469 10:02:50.656500 <5>[ 0.931395] Key type asymmetric registered
10470 10:02:50.660055 <5>[ 0.935728] Asymmetric key parser 'x509' registered
10471 10:02:50.669580 <6>[ 0.940870] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10472 10:02:50.672754 <6>[ 0.948484] io scheduler mq-deadline registered
10473 10:02:50.676318 <6>[ 0.953244] io scheduler kyber registered
10474 10:02:50.695302 <6>[ 0.970246] EINJ: ACPI disabled.
10475 10:02:50.727675 <4>[ 0.995509] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10476 10:02:50.737020 <4>[ 1.006145] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10477 10:02:50.752654 <6>[ 1.027042] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10478 10:02:50.760245 <6>[ 1.035047] printk: console [ttyS0] disabled
10479 10:02:50.787984 <6>[ 1.059702] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10480 10:02:50.794577 <6>[ 1.069171] printk: console [ttyS0] enabled
10481 10:02:50.797635 <6>[ 1.069171] printk: console [ttyS0] enabled
10482 10:02:50.804933 <6>[ 1.078071] printk: bootconsole [mtk8250] disabled
10483 10:02:50.807554 <6>[ 1.078071] printk: bootconsole [mtk8250] disabled
10484 10:02:50.814519 <6>[ 1.089438] SuperH (H)SCI(F) driver initialized
10485 10:02:50.817760 <6>[ 1.094741] msm_serial: driver initialized
10486 10:02:50.832340 <6>[ 1.103779] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10487 10:02:50.842152 <6>[ 1.112327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10488 10:02:50.849126 <6>[ 1.120868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10489 10:02:50.858769 <6>[ 1.129496] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10490 10:02:50.865445 <6>[ 1.138203] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10491 10:02:50.875737 <6>[ 1.146917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10492 10:02:50.885775 <6>[ 1.155458] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10493 10:02:50.891845 <6>[ 1.164268] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10494 10:02:50.902244 <6>[ 1.172813] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10495 10:02:50.913791 <6>[ 1.188594] loop: module loaded
10496 10:02:50.920230 <6>[ 1.194620] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10497 10:02:50.943005 <4>[ 1.218109] mtk-pmic-keys: Failed to locate of_node [id: -1]
10498 10:02:50.950318 <6>[ 1.225180] megasas: 07.719.03.00-rc1
10499 10:02:50.960287 <6>[ 1.234975] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10500 10:02:50.967369 <6>[ 1.241836] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10501 10:02:50.983071 <6>[ 1.257906] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10502 10:02:51.039357 <6>[ 1.307430] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10503 10:02:51.425904 <6>[ 1.700837] Freeing initrd memory: 20868K
10504 10:02:51.441673 <6>[ 1.716573] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10505 10:02:51.453013 <6>[ 1.727666] tun: Universal TUN/TAP device driver, 1.6
10506 10:02:51.456163 <6>[ 1.733746] thunder_xcv, ver 1.0
10507 10:02:51.459278 <6>[ 1.737254] thunder_bgx, ver 1.0
10508 10:02:51.462667 <6>[ 1.740748] nicpf, ver 1.0
10509 10:02:51.473522 <6>[ 1.744786] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10510 10:02:51.476413 <6>[ 1.752262] hns3: Copyright (c) 2017 Huawei Corporation.
10511 10:02:51.479663 <6>[ 1.757849] hclge is initializing
10512 10:02:51.486613 <6>[ 1.761428] e1000: Intel(R) PRO/1000 Network Driver
10513 10:02:51.493408 <6>[ 1.766557] e1000: Copyright (c) 1999-2006 Intel Corporation.
10514 10:02:51.497153 <6>[ 1.772570] e1000e: Intel(R) PRO/1000 Network Driver
10515 10:02:51.503176 <6>[ 1.777785] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10516 10:02:51.510028 <6>[ 1.783970] igb: Intel(R) Gigabit Ethernet Network Driver
10517 10:02:51.516650 <6>[ 1.789619] igb: Copyright (c) 2007-2014 Intel Corporation.
10518 10:02:51.523295 <6>[ 1.795458] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10519 10:02:51.526276 <6>[ 1.801977] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10520 10:02:51.533516 <6>[ 1.808443] sky2: driver version 1.30
10521 10:02:51.540393 <6>[ 1.813449] VFIO - User Level meta-driver version: 0.3
10522 10:02:51.546862 <6>[ 1.821701] usbcore: registered new interface driver usb-storage
10523 10:02:51.553124 <6>[ 1.828155] usbcore: registered new device driver onboard-usb-hub
10524 10:02:51.561890 <6>[ 1.837248] mt6397-rtc mt6359-rtc: registered as rtc0
10525 10:02:51.572389 <6>[ 1.842710] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-23T10:01:46 UTC (1692784906)
10526 10:02:51.575508 <6>[ 1.852299] i2c_dev: i2c /dev entries driver
10527 10:02:51.591953 <6>[ 1.864063] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10528 10:02:51.612282 <6>[ 1.887059] cpu cpu0: EM: created perf domain
10529 10:02:51.615611 <6>[ 1.892084] cpu cpu4: EM: created perf domain
10530 10:02:51.622730 <6>[ 1.897749] sdhci: Secure Digital Host Controller Interface driver
10531 10:02:51.629921 <6>[ 1.904182] sdhci: Copyright(c) Pierre Ossman
10532 10:02:51.636256 <6>[ 1.909132] Synopsys Designware Multimedia Card Interface Driver
10533 10:02:51.642640 <6>[ 1.915778] sdhci-pltfm: SDHCI platform and OF driver helper
10534 10:02:51.646495 <6>[ 1.915898] mmc0: CQHCI version 5.10
10535 10:02:51.653008 <6>[ 1.925782] ledtrig-cpu: registered to indicate activity on CPUs
10536 10:02:51.659772 <6>[ 1.932907] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10537 10:02:51.666540 <6>[ 1.939960] usbcore: registered new interface driver usbhid
10538 10:02:51.669912 <6>[ 1.945782] usbhid: USB HID core driver
10539 10:02:51.676283 <6>[ 1.949945] spi_master spi0: will run message pump with realtime priority
10540 10:02:51.719332 <6>[ 1.987859] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10541 10:02:51.739068 <6>[ 2.003783] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10542 10:02:51.743083 <6>[ 2.017386] mmc0: Command Queue Engine enabled
10543 10:02:51.749120 <6>[ 2.022160] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10544 10:02:51.755933 <6>[ 2.029083] cros-ec-spi spi0.0: Chrome EC device registered
10545 10:02:51.759448 <6>[ 2.029401] mmcblk0: mmc0:0001 DA4128 116 GiB
10546 10:02:51.773082 <6>[ 2.048149] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10547 10:02:51.783312 <6>[ 2.052197] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10548 10:02:51.789841 <6>[ 2.055030] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10549 10:02:51.793668 <6>[ 2.064695] NET: Registered PF_PACKET protocol family
10550 10:02:51.800025 <6>[ 2.069322] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10551 10:02:51.803389 <6>[ 2.073982] 9pnet: Installing 9P2000 support
10552 10:02:51.810457 <6>[ 2.079828] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10553 10:02:51.813493 <5>[ 2.083654] Key type dns_resolver registered
10554 10:02:51.820368 <6>[ 2.095135] registered taskstats version 1
10555 10:02:51.823270 <5>[ 2.099514] Loading compiled-in X.509 certificates
10556 10:02:51.854340 <4>[ 2.122117] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 10:02:51.863976 <4>[ 2.132817] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 10:02:51.870294 <3>[ 2.143347] debugfs: File 'uA_load' in directory '/' already present!
10559 10:02:51.877181 <3>[ 2.150050] debugfs: File 'min_uV' in directory '/' already present!
10560 10:02:51.883700 <3>[ 2.156713] debugfs: File 'max_uV' in directory '/' already present!
10561 10:02:51.890919 <3>[ 2.163333] debugfs: File 'constraint_flags' in directory '/' already present!
10562 10:02:51.901509 <3>[ 2.172789] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10563 10:02:51.910587 <6>[ 2.185108] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10564 10:02:51.917322 <6>[ 2.191909] xhci-mtk 11200000.usb: xHCI Host Controller
10565 10:02:51.923380 <6>[ 2.197427] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10566 10:02:51.933570 <6>[ 2.205265] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10567 10:02:51.940225 <6>[ 2.214691] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10568 10:02:51.946859 <6>[ 2.220762] xhci-mtk 11200000.usb: xHCI Host Controller
10569 10:02:51.953816 <6>[ 2.226237] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10570 10:02:51.960514 <6>[ 2.233885] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10571 10:02:51.967209 <6>[ 2.241570] hub 1-0:1.0: USB hub found
10572 10:02:51.970814 <6>[ 2.245578] hub 1-0:1.0: 1 port detected
10573 10:02:51.977136 <6>[ 2.249846] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10574 10:02:51.983748 <6>[ 2.258373] hub 2-0:1.0: USB hub found
10575 10:02:51.987289 <6>[ 2.262379] hub 2-0:1.0: 1 port detected
10576 10:02:51.996540 <6>[ 2.270983] mtk-msdc 11f70000.mmc: Got CD GPIO
10577 10:02:52.006346 <6>[ 2.277291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10578 10:02:52.012783 <6>[ 2.285315] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10579 10:02:52.022868 <4>[ 2.293206] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10580 10:02:52.030144 <6>[ 2.302743] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10581 10:02:52.039573 <6>[ 2.310820] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10582 10:02:52.046156 <6>[ 2.318828] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10583 10:02:52.056041 <6>[ 2.326741] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10584 10:02:52.062819 <6>[ 2.334564] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10585 10:02:52.072462 <6>[ 2.342381] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10586 10:02:52.079725 <6>[ 2.352366] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10587 10:02:52.089268 <6>[ 2.360725] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10588 10:02:52.096317 <6>[ 2.369069] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10589 10:02:52.106028 <6>[ 2.377406] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10590 10:02:52.112833 <6>[ 2.385744] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10591 10:02:52.122787 <6>[ 2.394084] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10592 10:02:52.129416 <6>[ 2.402423] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10593 10:02:52.139237 <6>[ 2.410761] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10594 10:02:52.145370 <6>[ 2.419099] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10595 10:02:52.156036 <6>[ 2.427436] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10596 10:02:52.162685 <6>[ 2.435775] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10597 10:02:52.172390 <6>[ 2.444113] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10598 10:02:52.181988 <6>[ 2.452459] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10599 10:02:52.188829 <6>[ 2.460797] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10600 10:02:52.199099 <6>[ 2.469135] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10601 10:02:52.205543 <6>[ 2.477889] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10602 10:02:52.212506 <6>[ 2.485048] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10603 10:02:52.218925 <6>[ 2.491815] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10604 10:02:52.225151 <6>[ 2.498601] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10605 10:02:52.231952 <6>[ 2.505547] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10606 10:02:52.241803 <6>[ 2.512402] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10607 10:02:52.251797 <6>[ 2.521534] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10608 10:02:52.258135 <6>[ 2.530654] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10609 10:02:52.268129 <6>[ 2.539948] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10610 10:02:52.278326 <6>[ 2.549416] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10611 10:02:52.288121 <6>[ 2.558883] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10612 10:02:52.297762 <6>[ 2.568003] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10613 10:02:52.307771 <6>[ 2.577469] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10614 10:02:52.314238 <6>[ 2.586588] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10615 10:02:52.327828 <6>[ 2.595883] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10616 10:02:52.337787 <6>[ 2.606042] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10617 10:02:52.347177 <6>[ 2.617640] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10618 10:02:52.395173 <6>[ 2.666712] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10619 10:02:52.549580 <6>[ 2.824572] hub 1-1:1.0: USB hub found
10620 10:02:52.552998 <6>[ 2.829106] hub 1-1:1.0: 4 ports detected
10621 10:02:52.675445 <6>[ 2.947055] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10622 10:02:52.701323 <6>[ 2.976479] hub 2-1:1.0: USB hub found
10623 10:02:52.704821 <6>[ 2.980980] hub 2-1:1.0: 3 ports detected
10624 10:02:52.874575 <6>[ 3.146704] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10625 10:02:53.007642 <6>[ 3.282351] hub 1-1.4:1.0: USB hub found
10626 10:02:53.010752 <6>[ 3.287032] hub 1-1.4:1.0: 2 ports detected
10627 10:02:53.091262 <6>[ 3.362978] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10628 10:02:53.307020 <6>[ 3.578748] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10629 10:02:53.498955 <6>[ 3.770734] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10630 10:03:04.647849 <6>[ 14.927717] ALSA device list:
10631 10:03:04.654290 <6>[ 14.931011] No soundcards found.
10632 10:03:04.662468 <6>[ 14.938990] Freeing unused kernel memory: 8384K
10633 10:03:04.665546 <6>[ 14.943994] Run /init as init process
10634 10:03:04.700031 Starting syslogd: OK
10635 10:03:04.704911 Starting klogd: OK
10636 10:03:04.713404 Running sysctl: OK
10637 10:03:04.720346 Populating /dev using udev: <30>[ 14.998414] udevd[187]: starting version 3.2.9
10638 10:03:04.730506 <27>[ 15.006669] udevd[187]: specified user 'tss' unknown
10639 10:03:04.736557 <27>[ 15.012149] udevd[187]: specified group 'tss' unknown
10640 10:03:04.740109 <30>[ 15.018670] udevd[188]: starting eudev-3.2.9
10641 10:03:04.762264 <27>[ 15.038785] udevd[188]: specified user 'tss' unknown
10642 10:03:04.768980 <27>[ 15.044189] udevd[188]: specified group 'tss' unknown
10643 10:03:04.916929 <6>[ 15.190522] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10644 10:03:04.938740 <6>[ 15.211784] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10645 10:03:04.945158 <6>[ 15.219643] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10646 10:03:04.956566 <6>[ 15.229479] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10647 10:03:04.963041 <6>[ 15.230378] remoteproc remoteproc0: scp is available
10648 10:03:04.966280 <6>[ 15.243699] remoteproc remoteproc0: powering up scp
10649 10:03:04.976235 <6>[ 15.248850] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10650 10:03:04.983028 <6>[ 15.252087] usbcore: registered new interface driver r8152
10651 10:03:04.989558 <3>[ 15.253382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 10:03:04.996093 <3>[ 15.253392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 10:03:05.005696 <3>[ 15.253396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 10:03:05.012911 <6>[ 15.257319] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10655 10:03:05.019871 <3>[ 15.265208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 10:03:05.026809 <3>[ 15.301139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 10:03:05.036567 <3>[ 15.309848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 10:03:05.043668 <6>[ 15.310134] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10659 10:03:05.050306 <4>[ 15.311504] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10660 10:03:05.060265 <3>[ 15.318008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 10:03:05.063302 <6>[ 15.322611] mc: Linux media interface: v0.10
10662 10:03:05.069621 <4>[ 15.333417] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10663 10:03:05.079674 <3>[ 15.341030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 10:03:05.089535 <4>[ 15.351703] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10665 10:03:05.093340 <4>[ 15.351703] Fallback method does not support PEC.
10666 10:03:05.100368 <3>[ 15.353575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 10:03:05.106685 <6>[ 15.366508] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10668 10:03:05.117588 <3>[ 15.374956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 10:03:05.124125 <3>[ 15.378538] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10670 10:03:05.131171 <6>[ 15.384482] pci_bus 0000:00: root bus resource [bus 00-ff]
10671 10:03:05.137747 <3>[ 15.389880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 10:03:05.147096 <3>[ 15.389892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 10:03:05.153918 <6>[ 15.397427] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10674 10:03:05.163858 <6>[ 15.398523] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10675 10:03:05.167069 <6>[ 15.399516] videodev: Linux video capture interface: v2.00
10676 10:03:05.177462 <6>[ 15.399827] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10677 10:03:05.186967 <6>[ 15.399837] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10678 10:03:05.190658 <6>[ 15.399911] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10679 10:03:05.200677 <6>[ 15.399934] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10680 10:03:05.203891 <6>[ 15.400022] pci 0000:00:00.0: supports D1 D2
10681 10:03:05.210375 <6>[ 15.400024] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10682 10:03:05.220581 <6>[ 15.402390] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10683 10:03:05.226692 <6>[ 15.402768] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10684 10:03:05.233824 <6>[ 15.402809] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10685 10:03:05.240175 <6>[ 15.402833] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10686 10:03:05.246804 <6>[ 15.402858] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10687 10:03:05.253231 <6>[ 15.403005] pci 0000:01:00.0: supports D1 D2
10688 10:03:05.259769 <6>[ 15.403009] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10689 10:03:05.266884 <3>[ 15.406818] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10690 10:03:05.276423 <3>[ 15.407060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 10:03:05.283440 <3>[ 15.407072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 10:03:05.293436 <3>[ 15.407079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 10:03:05.299589 <3>[ 15.407090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 10:03:05.309687 <3>[ 15.407098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 10:03:05.316720 <3>[ 15.407157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 10:03:05.323362 <6>[ 15.410593] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10697 10:03:05.333175 <6>[ 15.410656] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10698 10:03:05.340307 <6>[ 15.410663] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10699 10:03:05.346450 <6>[ 15.410676] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10700 10:03:05.352905 <6>[ 15.410686] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10701 10:03:05.363100 <6>[ 15.410693] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10702 10:03:05.369254 <6>[ 15.410709] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10703 10:03:05.375916 <6>[ 15.410725] pci 0000:00:00.0: PCI bridge to [bus 01]
10704 10:03:05.383116 <6>[ 15.410736] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10705 10:03:05.389522 <6>[ 15.411079] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10706 10:03:05.396002 <6>[ 15.411687] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10707 10:03:05.402264 <6>[ 15.412011] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10708 10:03:05.408822 <6>[ 15.412687] remoteproc remoteproc0: remote processor scp is now up
10709 10:03:05.419238 <6>[ 15.418929] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10710 10:03:05.428849 <6>[ 15.419389] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10711 10:03:05.435941 <4>[ 15.434087] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10712 10:03:05.445452 <6>[ 15.468392] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10713 10:03:05.452754 <4>[ 15.473392] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10714 10:03:05.462375 <6>[ 15.474393] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10715 10:03:05.468678 <6>[ 15.481592] usbcore: registered new interface driver cdc_ether
10716 10:03:05.475636 <6>[ 15.486641] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10717 10:03:05.482209 <6>[ 15.494715] r8152 2-1.3:1.0 eth0: v1.12.13
10718 10:03:05.488715 <6>[ 15.501213] usbcore: registered new interface driver r8153_ecm
10719 10:03:05.495362 <6>[ 15.511393] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10720 10:03:05.501776 <5>[ 15.512094] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10721 10:03:05.505043 <6>[ 15.522888] Bluetooth: Core ver 2.22
10722 10:03:05.518404 <6>[ 15.531425] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10723 10:03:05.524933 <6>[ 15.534181] NET: Registered PF_BLUETOOTH protocol family
10724 10:03:05.531781 <5>[ 15.536374] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10725 10:03:05.538491 <4>[ 15.536445] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10726 10:03:05.544932 <6>[ 15.536454] cfg80211: failed to load regulatory.db
10727 10:03:05.551917 <6>[ 15.541192] usbcore: registered new interface driver uvcvideo
10728 10:03:05.558138 <6>[ 15.549741] Bluetooth: HCI device and connection manager initialized
10729 10:03:05.561608 <6>[ 15.549770] Bluetooth: HCI socket layer initialized
10730 10:03:05.568370 <6>[ 15.567746] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10731 10:03:05.574885 <6>[ 15.574009] Bluetooth: L2CAP socket layer initialized
10732 10:03:05.581447 <6>[ 15.655768] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10733 10:03:05.585026 <6>[ 15.657481] Bluetooth: SCO socket layer initialized
10734 10:03:05.591208 <6>[ 15.665561] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10735 10:03:05.598427 <6>[ 15.727153] usbcore: registered new interface driver btusb
10736 10:03:05.608117 <4>[ 15.728189] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10737 10:03:05.614522 <3>[ 15.728200] Bluetooth: hci0: Failed to load firmware file (-2)
10738 10:03:05.621236 <3>[ 15.728204] Bluetooth: hci0: Failed to set up firmware (-2)
10739 10:03:05.631183 <4>[ 15.728209] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10740 10:03:05.637498 <6>[ 15.754691] mt7921e 0000:01:00.0: ASIC revision: 79610010
10741 10:03:05.745154 <4>[ 16.015309] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10742 10:03:05.763442 done
10743 10:03:05.774901 Saving random seed: OK
10744 10:03:05.791980 Starting network: OK
10745 10:03:05.825841 Starting dropbear sshd: <6>[ 16.102682] NET: Registered PF_INET6 protocol family
10746 10:03:05.832063 <6>[ 16.109247] Segment Routing with IPv6
10747 10:03:05.835361 <6>[ 16.113214] In-situ OAM (IOAM) with IPv6
10748 10:03:05.840478 OK
10749 10:03:05.863824 /bin/sh: can't a<4>[ 16.134136] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10750 10:03:05.867050 ccess tty; job control turned off
10751 10:03:05.867631 Matched prompt #10: / #
10753 10:03:05.868072 Setting prompt string to ['/ #']
10754 10:03:05.868254 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10756 10:03:05.868656 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10757 10:03:05.868841 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
10758 10:03:05.868982 Setting prompt string to ['/ #']
10759 10:03:05.869107 Forcing a shell prompt, looking for ['/ #']
10761 10:03:05.919491 / #
10762 10:03:05.920244 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10763 10:03:05.920810 Waiting using forced prompt support (timeout 00:02:30)
10764 10:03:05.925813
10765 10:03:05.926753 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10766 10:03:05.927418 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
10767 10:03:05.928148 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10768 10:03:05.928805 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10769 10:03:05.929440 end: 2 depthcharge-action (duration 00:01:15) [common]
10770 10:03:05.930094 start: 3 lava-test-retry (timeout 00:01:00) [common]
10771 10:03:05.930733 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10772 10:03:05.931138 Using namespace: common
10774 10:03:06.032271 / # #
10775 10:03:06.032856 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10776 10:03:06.033370 <4>[ 16.253106] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 10:03:06.038706 #
10778 10:03:06.039422 Using /lava-11336429
10780 10:03:06.140473 / # export SHELL=/bin/sh
10781 10:03:06.141259 <4>[ 16.373348] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 10:03:06.146714 export SHELL=/bin/sh
10784 10:03:06.248383 / # . /lava-11336429/environment
10785 10:03:06.249047 . /lava-11336429/environment<4>[ 16.493654] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 10:03:06.255250
10788 10:03:06.356496 / # /lava-11336429/bin/lava-test-runner /lava-11336429/0
10789 10:03:06.357066 Test shell timeout: 10s (minimum of the action and connection timeout)
10790 10:03:06.358599 /lava-11336429/bin/lava-test-runner /lava-11336429/0<4>[ 16.613233] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 10:03:06.362801
10792 10:03:06.403993 + export 'TESTRUN_ID=0_dmesg'
10793 10:03:06.404504 +<8>[ 16.664982] <LAVA_SIGNAL_STARTRUN 0_dmesg 11336429_1.5.2.3.1>
10794 10:03:06.404845 cd /lava-11336429/0/tests/0_dmesg
10795 10:03:06.405154 + cat uuid
10796 10:03:06.405739 Received signal: <STARTRUN> 0_dmesg 11336429_1.5.2.3.1
10797 10:03:06.406071 Starting test lava.0_dmesg (11336429_1.5.2.3.1)
10798 10:03:06.406461 Skipping test definition patterns.
10799 10:03:06.406930 + UUID=11336429_1.5.2.3.1
10800 10:03:06.407256 + set +x
10801 10:03:06.407552 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10802 10:03:06.411912 <8>[ 16.685387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10803 10:03:06.412582 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10805 10:03:06.432134 <8>[ 16.705642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10806 10:03:06.432816 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10808 10:03:06.465072 <4>[ 16.735032] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 10:03:06.471763 <8>[ 16.737905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10810 10:03:06.472555 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10812 10:03:06.476728 + set +x
10813 10:03:06.480026 <8>[ 16.756747] <LAVA_SIGNAL_ENDRUN 0_dmesg 11336429_1.5.2.3.1>
10814 10:03:06.480694 Received signal: <ENDRUN> 0_dmesg 11336429_1.5.2.3.1
10815 10:03:06.481100 Ending use of test pattern.
10816 10:03:06.481416 Ending test lava.0_dmesg (11336429_1.5.2.3.1), duration 0.08
10818 10:03:06.487032 <LAVA_TEST_RUNNER EXIT>
10819 10:03:06.487731 ok: lava_test_shell seems to have completed
10820 10:03:06.488256 alert: pass
crit: pass
emerg: pass
10821 10:03:06.488656 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10822 10:03:06.489073 end: 3 lava-test-retry (duration 00:00:01) [common]
10823 10:03:06.489497 start: 4 lava-test-retry (timeout 00:01:00) [common]
10824 10:03:06.489901 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10825 10:03:06.490225 Using namespace: common
10827 10:03:06.591284 / # #
10828 10:03:06.591954 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10829 10:03:06.592549 Using /lava-11336429
10831 10:03:06.693972 export SHELL=/bin/sh
10832 10:03:06.694677 #<4>[ 16.865198] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10833 10:03:06.695042
10835 10:03:06.796285 / # export SHELL=/bin/sh. /lava-11336429/environment
10836 10:03:06.796502
10837 10:03:06.796603 / # <4>[ 16.985566] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10839 10:03:06.897353 . /lava-11336429/environment/lava-11336429/bin/lava-test-runner /lava-11336429/1
10840 10:03:06.897581 Test shell timeout: 10s (minimum of the action and connection timeout)
10841 10:03:06.897768
10842 10:03:06.897884 / # <4>[ 17.105159] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 10:03:06.903469 /lava-11336429/bin/lava-test-runner /lava-11336429/1
10844 10:03:06.944052 + export 'TESTRUN_ID=1_bootrr'
10845 10:03:06.944543 <8>[ 17.205457] <LAVA_SIGNAL_STARTRUN 1_bootrr 11336429_1.5.2.3.5>
10846 10:03:06.944904 + cd /lava-11336429/1/tests/1_bootrr
10847 10:03:06.945217 + cat uuid
10848 10:03:06.945544 + UUID=11336429_1.5.2.3.5
10849 10:03:06.945865 + set +x
10850 10:03:06.946431 Received signal: <STARTRUN> 1_bootrr 11336429_1.5.2.3.5
10851 10:03:06.946801 Starting test lava.1_bootrr (11336429_1.5.2.3.5)
10852 10:03:06.947201 Skipping test definition patterns.
10853 10:03:06.949510 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-1<3>[ 17.224524] mt7921e 0000:01:00.0: hardware init failed
10854 10:03:06.953139 1336429/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10855 10:03:06.962382 + cd /opt/bootrr/libexec/bootrr<8>[ 17.236105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10856 10:03:06.962852
10857 10:03:06.963473 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10859 10:03:06.965767 + sh helpers/bootrr-auto
10860 10:03:06.969033 /lava-11336429/1/../bin/lava-test-case
10861 10:03:06.972250 /lava-11336429/1/../bin/lava-test-case
10862 10:03:06.978826 <8>[ 17.254904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10863 10:03:06.979834 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10865 10:03:06.986622 /usr/bin/tpm2_getcap
10866 10:03:07.020332 /lava-11336429/1/../bin/lava-test-case
10867 10:03:07.026871 <8>[ 17.300120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10868 10:03:07.027666 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10870 10:03:07.044049 /lava-11336429/1/../bin/lava-test-case
10871 10:03:07.049961 <8>[ 17.323064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10872 10:03:07.050652 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10874 10:03:07.060140 /lava-11336429/1/../bin/lava-test-case
10875 10:03:07.066190 <8>[ 17.339919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10876 10:03:07.066898 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10878 10:03:07.077486 /lava-11336429/1/../bin/lava-test-case
10879 10:03:07.084429 <8>[ 17.357801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10880 10:03:07.085099 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10882 10:03:07.094650 /lava-11336429/1/../bin/lava-test-case
10883 10:03:07.101387 <8>[ 17.374587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10884 10:03:07.102160 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10886 10:03:07.111102 /lava-11336429/1/../bin/lava-test-case
10887 10:03:07.117633 <8>[ 17.392439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10888 10:03:07.118469 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10890 10:03:07.127721 /lava-11336429/1/../bin/lava-test-case
10891 10:03:07.134595 <8>[ 17.407987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10892 10:03:07.135258 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10894 10:03:07.153201 /lava-11336429/1/../bin/lava-tes<8>[ 17.425728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10895 10:03:07.153723 t-case
10896 10:03:07.154325 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10898 10:03:07.160547 /lava-11336429/1/../bin/lava-test-case
10899 10:03:07.167353 <8>[ 17.440576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10900 10:03:07.168167 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10902 10:03:07.179054 /lava-11336429/1/../bin/lava-test-case
10903 10:03:07.185336 <8>[ 17.459033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10904 10:03:07.186014 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10906 10:03:07.196313 /lava-11336429/1/../bin/lava-test-case
10907 10:03:07.202845 <8>[ 17.476596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10908 10:03:07.203541 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10910 10:03:07.214668 /lava-11336429/1/../bin/lava-test-case
10911 10:03:07.221382 <8>[ 17.495235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10912 10:03:07.222155 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10914 10:03:07.232565 /lava-11336429/1/../bin/lava-test-case
10915 10:03:07.239325 <8>[ 17.514067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10916 10:03:07.240050 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10918 10:03:07.249770 /lava-11336429/1/../bin/lava-test-case
10919 10:03:07.256314 <8>[ 17.530078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10920 10:03:07.257089 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10922 10:03:07.267372 /lava-11336429/1/../bin/lava-test-case
10923 10:03:07.273847 <8>[ 17.547530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10924 10:03:07.274567 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10926 10:03:07.290114 /lava-11336429/1/../bin/lava-tes<8>[ 17.562661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10927 10:03:07.290650 t-case
10928 10:03:07.291251 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10930 10:03:07.299783 /lava-11336429/1/../bin/lava-test-case
10931 10:03:07.306217 <8>[ 17.581379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10932 10:03:07.306995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10934 10:03:07.316250 /lava-11336429/1/../bin/lava-test-case
10935 10:03:07.323153 <8>[ 17.596508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10936 10:03:07.323826 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10938 10:03:07.333664 /lava-11336429/1/../bin/lava-test-case
10939 10:03:07.340270 <8>[ 17.614607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10940 10:03:07.340996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10942 10:03:07.349528 /lava-11336429/1/../bin/lava-test-case
10943 10:03:07.356018 <8>[ 17.630852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10944 10:03:07.356801 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10946 10:03:07.369522 /lava-11336429/1/../bin/lava-test-case
10947 10:03:07.375277 <8>[ 17.649844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10948 10:03:07.376024 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10950 10:03:07.391997 /lava-11336429/1/../bin/lava-tes<8>[ 17.665173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10951 10:03:07.392592 t-case
10952 10:03:07.393388 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10954 10:03:07.402564 /lava-11336429/1/../bin/lava-test-case
10955 10:03:07.408952 <8>[ 17.682401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10956 10:03:07.409633 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10958 10:03:07.420507 /lava-11336429/1/../bin/lava-test-case
10959 10:03:07.427044 <8>[ 17.700645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10960 10:03:07.427721 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10962 10:03:07.444818 /lava-11336429/1/../bin/lava-tes<8>[ 17.717324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10963 10:03:07.445241 t-case
10964 10:03:07.445828 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10966 10:03:07.454797 /lava-11336429/1/../bin/lava-test-case
10967 10:03:07.461347 <8>[ 17.735240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10968 10:03:07.462259 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10970 10:03:07.478816 /lava-11336429/1/../bin/lava-tes<8>[ 17.751248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10971 10:03:07.479415 t-case
10972 10:03:07.480302 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10974 10:03:07.488040 /lava-11336429/1/../bin/lava-test-case
10975 10:03:07.494750 <8>[ 17.770304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10976 10:03:07.495639 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10978 10:03:07.506909 /lava-11336429/1/../bin/lava-test-case
10979 10:03:07.513316 <8>[ 17.787280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10980 10:03:07.513989 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10982 10:03:07.525235 /lava-11336429/1/../bin/lava-test-case
10983 10:03:07.532021 <8>[ 17.804963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10984 10:03:07.532694 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10986 10:03:07.541900 /lava-11336429/1/../bin/lava-test-case
10987 10:03:07.549094 <8>[ 17.823437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10988 10:03:07.549789 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10990 10:03:07.565939 /lava-11336429/1/../bin/lava-tes<8>[ 17.838992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10991 10:03:07.566371 t-case
10992 10:03:07.567140 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10994 10:03:07.585523 /lava-11336429/1/../bin/lava-tes<8>[ 17.858381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10995 10:03:07.585959 t-case
10996 10:03:07.586660 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10998 10:03:07.596023 /lava-11336429/1/../bin/lava-test-case
10999 10:03:07.602549 <8>[ 17.876209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11000 10:03:07.603476 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11002 10:03:07.611353 /lava-11336429/1/../bin/lava-test-case
11003 10:03:07.617883 <8>[ 17.892551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11004 10:03:07.618556 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11006 10:03:07.631880 /lava-11336429/1/../bin/lava-test-case
11007 10:03:07.637905 <8>[ 17.911806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11008 10:03:07.638690 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11010 10:03:07.646995 /lava-11336429/1/../bin/lava-test-case
11011 10:03:07.653199 <8>[ 17.927318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11012 10:03:07.653995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11014 10:03:07.665642 /lava-11336429/1/../bin/lava-test-case
11015 10:03:07.671529 <8>[ 17.945822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11016 10:03:07.672231 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11018 10:03:07.680290 /lava-11336429/1/../bin/lava-test-case
11019 10:03:07.686842 <8>[ 17.961313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11020 10:03:07.687537 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11022 10:03:07.699343 /lava-11336429/1/../bin/lava-test-case
11023 10:03:07.706214 <8>[ 17.979674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11024 10:03:07.706953 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11026 10:03:07.714669 /lava-11336429/1/../bin/lava-test-case
11027 10:03:07.721150 <8>[ 17.994393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11028 10:03:07.722014 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11030 10:03:07.732604 /lava-11336429/1/../bin/lava-test-case
11031 10:03:07.739341 <8>[ 18.012473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11032 10:03:07.740066 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11034 10:03:07.756277 /lava-11336429/1/../bin/lava-tes<8>[ 18.029037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11035 10:03:07.756757 t-case
11036 10:03:07.757345 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11038 10:03:07.774838 /lava-11336429/1/../bin/lava-tes<8>[ 18.047490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11039 10:03:07.775398 t-case
11040 10:03:07.776046 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11042 10:03:07.783288 /lava-11336429/1/../bin/lava-test-case
11043 10:03:07.789542 <8>[ 18.063225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11044 10:03:07.790300 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11046 10:03:07.799779 /lava-11336429/1/../bin/lava-test-case
11047 10:03:07.806121 <8>[ 18.080088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11048 10:03:07.806961 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11050 10:03:07.815166 /lava-11336429/1/../bin/lava-test-case
11051 10:03:07.822109 <8>[ 18.095754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11052 10:03:07.822934 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11054 10:03:07.832919 /lava-11336429/1/../bin/lava-test-case
11055 10:03:07.839506 <8>[ 18.112910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11056 10:03:07.840233 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11058 10:03:07.857750 /lava-11336429/1/../bin/lava-tes<8>[ 18.130127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11059 10:03:07.858320 t-case
11060 10:03:07.858914 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11062 10:03:07.865694 /lava-11336429/1/../bin/lava-test-case
11063 10:03:07.872054 <8>[ 18.145670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11064 10:03:07.872731 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11066 10:03:07.890361 /lava-11336429/1/../bin/lava-tes<8>[ 18.163181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11067 10:03:07.890798 t-case
11068 10:03:07.891380 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11070 10:03:07.898980 /lava-11336429/1/../bin/lava-test-case
11071 10:03:07.905661 <8>[ 18.178466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11072 10:03:07.906487 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11074 10:03:07.924285 /lava-11336429/1/../bin/lava-tes<8>[ 18.196732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11075 10:03:07.924759 t-case
11076 10:03:07.925389 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11078 10:03:07.933096 /lava-11336429/1/../bin/lava-test-case
11079 10:03:07.940062 <8>[ 18.213786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11080 10:03:07.940788 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11082 10:03:07.951190 /lava-11336429/1/../bin/lava-test-case
11083 10:03:07.958161 <8>[ 18.231531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11084 10:03:07.958983 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11086 10:03:07.967781 /lava-11336429/1/../bin/lava-test-case
11087 10:03:07.974148 <8>[ 18.248721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11088 10:03:07.974982 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11090 10:03:07.986764 /lava-11336429/1/../bin/lava-test-case
11091 10:03:07.993588 <8>[ 18.266484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11092 10:03:07.994279 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11094 10:03:08.001130 /lava-11336429/1/../bin/lava-test-case
11095 10:03:08.011571 <8>[ 18.284882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11096 10:03:08.012307 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11098 10:03:08.021542 /lava-11336429/1/../bin/lava-test-case
11099 10:03:08.028356 <8>[ 18.302642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11100 10:03:08.029084 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11102 10:03:08.038845 /lava-11336429/1/../bin/lava-test-case
11103 10:03:08.045387 <8>[ 18.319375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11104 10:03:08.046247 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11106 10:03:08.053049 /lava-11336429/1/../bin/lava-test-case
11107 10:03:08.060012 <8>[ 18.333588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11108 10:03:08.060602 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11110 10:03:08.069627 /lava-11336429/1/../bin/lava-test-case
11111 10:03:08.076172 <8>[ 18.351354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11112 10:03:08.076425 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11114 10:03:08.092724 /lava-11336429/1/../bin/lava-tes<8>[ 18.366147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11115 10:03:08.092805 t-case
11116 10:03:08.093039 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11118 10:03:08.103843 /lava-11336429/1/../bin/lava-test-case
11119 10:03:08.110526 <8>[ 18.383824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11120 10:03:08.110814 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11122 10:03:08.119732 /lava-11336429/1/../bin/lava-test-case
11123 10:03:08.126280 <8>[ 18.399993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11124 10:03:08.126616 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11126 10:03:08.138566 /lava-11336429/1/../bin/lava-test-case
11127 10:03:08.145423 <8>[ 18.418770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11128 10:03:08.146020 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11130 10:03:08.154821 /lava-11336429/1/../bin/lava-test-case
11131 10:03:08.165509 <8>[ 18.438978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11132 10:03:08.166184 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11134 10:03:08.175768 /lava-11336429/1/../bin/lava-test-case
11135 10:03:08.182715 <8>[ 18.455995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11136 10:03:08.183413 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11138 10:03:08.193505 /lava-11336429/1/../bin/lava-test-case
11139 10:03:08.200237 <8>[ 18.474535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11140 10:03:08.200914 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11142 10:03:08.212040 /lava-11336429/1/../bin/lava-test-case
11143 10:03:08.218628 <8>[ 18.492277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11144 10:03:08.219301 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11146 10:03:08.229082 /lava-11336429/1/../bin/lava-test-case
11147 10:03:08.235479 <8>[ 18.509552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11148 10:03:08.236259 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11150 10:03:08.253413 /lava-11336429/1/../bin/lava-tes<8>[ 18.526229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11151 10:03:08.253865 t-case
11152 10:03:08.254662 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11154 10:03:08.263483 /lava-11336429/1/../bin/lava-test-case
11155 10:03:08.270426 <8>[ 18.543733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11156 10:03:08.271240 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11158 10:03:08.280381 /lava-11336429/1/../bin/lava-test-case
11159 10:03:08.287383 <8>[ 18.561465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11160 10:03:08.288223 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11162 10:03:08.297447 /lava-11336429/1/../bin/lava-test-case
11163 10:03:08.304640 <8>[ 18.578995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11164 10:03:08.305314 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11166 10:03:08.315848 /lava-11336429/1/../bin/lava-test-case
11167 10:03:08.322252 <8>[ 18.596310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11168 10:03:08.323235 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11170 10:03:08.333371 /lava-11336429/1/../bin/lava-test-case
11171 10:03:08.340110 <8>[ 18.613740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11172 10:03:08.340783 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11174 10:03:08.351367 /lava-11336429/1/../bin/lava-test-case
11175 10:03:08.357606 <8>[ 18.631621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11176 10:03:08.358284 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11178 10:03:08.368072 /lava-11336429/1/../bin/lava-test-case
11179 10:03:08.374516 <8>[ 18.648330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11180 10:03:08.375310 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11182 10:03:08.384753 /lava-11336429/1/../bin/lava-test-case
11183 10:03:08.391049 <8>[ 18.665773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11184 10:03:08.391753 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11186 10:03:08.401299 /lava-11336429/1/../bin/lava-test-case
11187 10:03:08.407668 <8>[ 18.681446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11188 10:03:08.408584 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11190 10:03:08.422471 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11192 10:03:08.425414 /lava-11336429/1/../bin/lava-tes<8>[ 18.698278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11193 10:03:08.425971 t-case
11194 10:03:08.432194 /lava-11336429/1/../bin/lava-test-case
11195 10:03:08.438796 <8>[ 18.714191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11196 10:03:08.439468 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11198 10:03:08.452359 /lava-11336429/1/../bin/lava-test-case
11199 10:03:08.458889 <8>[ 18.732207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11200 10:03:08.459728 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11202 10:03:08.467155 /lava-11336429/1/../bin/lava-test-case
11203 10:03:08.473895 <8>[ 18.748471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11204 10:03:08.474688 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11206 10:03:08.487171 /lava-11336429/1/../bin/lava-test-case
11207 10:03:08.493982 <8>[ 18.767587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11208 10:03:08.494785 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11210 10:03:08.509213 /lava-11336429/1/../bin/lava-tes<8>[ 18.782146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11211 10:03:08.509851 t-case
11212 10:03:08.510459 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11214 10:03:08.521829 /lava-11336429/1/../bin/lava-test-case
11215 10:03:08.528857 <8>[ 18.802093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11216 10:03:08.529650 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11218 10:03:08.536959 /lava-11336429/1/../bin/lava-test-case
11219 10:03:08.543849 <8>[ 18.816549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11220 10:03:08.544588 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11222 10:03:08.555056 /lava-11336429/1/../bin/lava-test-case
11223 10:03:08.562076 <8>[ 18.835667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11224 10:03:08.562797 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11226 10:03:08.576345 /lava-11336429/1/../bin/lava-tes<8>[ 18.849590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11227 10:03:08.576812 t-case
11228 10:03:08.577471 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11230 10:03:08.588641 /lava-11336429/1/../bin/lava-test-case
11231 10:03:08.595137 <8>[ 18.868153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11232 10:03:08.595804 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11234 10:03:08.614828 /lava-11336429/1/../bin/lava-tes<8>[ 18.888138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11235 10:03:08.615384 t-case
11236 10:03:08.616027 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11238 10:03:08.623336 /lava-11336429/1/../bin/lava-test-case
11239 10:03:08.629561 <8>[ 18.903490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11240 10:03:08.630232 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11242 10:03:08.649071 /lava-11336429/1/../bin/lava-tes<8>[ 18.921669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11243 10:03:08.649582 t-case
11244 10:03:08.650178 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11246 10:03:08.656219 /lava-11336429/1/../bin/lava-test-case
11247 10:03:08.662648 <8>[ 18.937503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11248 10:03:08.663443 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11250 10:03:08.678516 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11252 10:03:08.681210 /lava-11336429/1/../bin/lava-tes<8>[ 18.954371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11253 10:03:08.681677 t-case
11254 10:03:08.689339 /lava-11336429/1/../bin/lava-test-case
11255 10:03:08.696087 <8>[ 18.969411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11256 10:03:08.696784 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11258 10:03:09.709036 /lava-11336429/1/../bin/lava-test-case
11259 10:03:09.715977 <8>[ 19.989436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11260 10:03:09.716662 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11262 10:03:09.725853 /lava-11336429/1/../bin/lava-test-case
11263 10:03:09.732486 <8>[ 20.006574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11264 10:03:09.733151 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11266 10:03:10.746983 /lava-11336429/1/../bin/lava-test-case
11267 10:03:10.753712 <8>[ 21.028568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11268 10:03:10.754436 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11270 10:03:10.764414 /lava-11336429/1/../bin/lava-test-case
11271 10:03:10.770529 <8>[ 21.044899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11272 10:03:10.771234 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11274 10:03:11.784739 /lava-11336429/1/../bin/lava-test-case
11275 10:03:11.791145 <8>[ 22.066555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11276 10:03:11.791837 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11278 10:03:11.801811 /lava-11336429/1/../bin/lava-test-case
11279 10:03:11.808700 <8>[ 22.082744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11280 10:03:11.809510 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11282 10:03:12.822350 /lava-11336429/1/../bin/lava-test-case
11283 10:03:12.829226 <8>[ 23.105190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11284 10:03:12.829496 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11286 10:03:12.845665 /lava-11336429/1/../bin/lava-tes<8>[ 23.119559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11287 10:03:12.845770 t-case
11288 10:03:12.846038 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11290 10:03:13.859396 /lava-11336429/1/../bin/lava-test-case
11291 10:03:13.866073 <8>[ 24.142010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11292 10:03:13.866337 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11294 10:03:13.875360 /lava-11336429/1/../bin/lava-test-case
11295 10:03:13.881575 <8>[ 24.155989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11296 10:03:13.881834 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11298 10:03:14.897203 /lava-11336429/1/../bin/lava-test-case
11299 10:03:14.903814 <8>[ 25.178931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11300 10:03:14.904085 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11302 10:03:14.924141 /lava-11336429/1/../bin/lava-tes<8>[ 25.198380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11303 10:03:14.924239 t-case
11304 10:03:14.924476 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11306 10:03:15.937327 /lava-11336429/1/../bin/lava-test-case
11307 10:03:15.943528 <8>[ 26.219650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11308 10:03:15.943845 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11310 10:03:15.954876 /lava-11336429/1/../bin/lava-test-case
11311 10:03:15.961048 <8>[ 26.236025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11312 10:03:15.961313 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11314 10:03:15.971245 /lava-11336429/1/../bin/lava-test-case
11315 10:03:15.977982 <8>[ 26.252719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11316 10:03:15.978239 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11318 10:03:16.996052 /lava-11336429/1/../bin/lava-test-case
11319 10:03:17.002911 <8>[ 27.279222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11320 10:03:17.003178 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11322 10:03:17.013983 /lava-11336429/1/../bin/lava-test-case
11323 10:03:17.021054 <8>[ 27.295852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11324 10:03:17.021313 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11326 10:03:17.040932 /lava-11336429/1/../bin/lava-tes<8>[ 27.315010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11327 10:03:17.041034 t-case
11328 10:03:17.041272 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11330 10:03:17.050373 /lava-11336429/1/../bin/lava-test-case
11331 10:03:17.056570 <8>[ 27.331764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11332 10:03:17.056823 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11334 10:03:17.067653 /lava-11336429/1/../bin/lava-test-case
11335 10:03:17.078065 <8>[ 27.352846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11336 10:03:17.078338 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11338 10:03:17.088119 /lava-11336429/1/../bin/lava-test-case
11339 10:03:17.094699 <8>[ 27.370447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11340 10:03:17.094993 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11342 10:03:17.107113 /lava-11336429/1/../bin/lava-test-case
11343 10:03:17.113502 <8>[ 27.389105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11344 10:03:17.113761 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11346 10:03:17.123112 /lava-11336429/1/../bin/lava-test-case
11347 10:03:17.129213 <8>[ 27.404523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11348 10:03:17.129472 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11350 10:03:17.147820 /lava-11336429/1/../bin/lava-tes<8>[ 27.422489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11351 10:03:17.147921 t-case
11352 10:03:17.148160 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11354 10:03:17.159355 /lava-11336429/1/../bin/lava-test-case
11355 10:03:17.166405 <8>[ 27.441738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11356 10:03:17.166662 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11358 10:03:17.182123 /lava-11336429/1/../bin/lava-tes<8>[ 27.456345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11359 10:03:17.182216 t-case
11360 10:03:17.182452 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11362 10:03:17.193631 /lava-11336429/1/../bin/lava-test-case
11363 10:03:17.200451 <8>[ 27.475188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11364 10:03:17.200711 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11366 10:03:17.215608 /lava-11336429/1/../bin/lava-tes<8>[ 27.489895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11367 10:03:17.215741 t-case
11368 10:03:17.216039 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11370 10:03:17.226955 /lava-11336429/1/../bin/lava-test-case
11371 10:03:17.233561 <8>[ 27.508909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11372 10:03:17.233822 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11374 10:03:17.242618 /lava-11336429/1/../bin/lava-test-case
11375 10:03:17.249215 <8>[ 27.523680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11376 10:03:17.249477 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11378 10:03:17.263482 /lava-11336429/1/../bin/lava-test-case
11379 10:03:17.269827 <8>[ 27.545396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11380 10:03:17.270081 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11382 10:03:17.279163 /lava-11336429/1/../bin/lava-test-case
11383 10:03:17.285628 <8>[ 27.560210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11384 10:03:17.285882 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11386 10:03:17.306575 /lava-11336429/1/../bin/lava-tes<8>[ 27.580930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11387 10:03:17.306666 t-case
11388 10:03:17.306903 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11390 10:03:17.323180 /lava-11336429/1/../bin/lava-tes<8>[ 27.597885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11391 10:03:17.323268 t-case
11392 10:03:17.323507 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11394 10:03:17.335557 /lava-11336429/1/../bin/lava-test-case
11395 10:03:17.342623 <8>[ 27.617886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11396 10:03:17.342884 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11398 10:03:17.350729 /lava-11336429/1/../bin/lava-test-case
11399 10:03:17.357598 <8>[ 27.633753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11400 10:03:17.357854 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11402 10:03:18.372862 /lava-11336429/1/../bin/lava-test-case
11403 10:03:18.379217 <8>[ 28.655574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11404 10:03:18.379479 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11406 10:03:19.393965 /lava-11336429/1/../bin/lava-test-case
11407 10:03:19.400810 <8>[ 29.677202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11408 10:03:19.401081 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11410 10:03:19.410291 /lava-11336429/1/../bin/lava-test-case
11411 10:03:19.417243 <8>[ 29.692007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11412 10:03:19.417505 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11414 10:03:19.432590 /lava-11336429/1/../bin/lava-test-case
11415 10:03:19.439007 <8>[ 29.715460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11416 10:03:19.439269 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11418 10:03:19.448793 /lava-11336429/1/../bin/lava-test-case
11419 10:03:19.455198 <8>[ 29.730479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11420 10:03:19.455519 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11422 10:03:19.469039 /lava-11336429/1/../bin/lava-test-case
11423 10:03:19.475360 <8>[ 29.751128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11424 10:03:19.475651 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11426 10:03:19.490539 /lava-11336429/1/../bin/lava-tes<8>[ 29.765160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11427 10:03:19.490631 t-case
11428 10:03:19.490870 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11430 10:03:19.505473 /lava-11336429/1/../bin/lava-tes<8>[ 29.782986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11431 10:03:19.505745 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11433 10:03:19.508739 t-case
11434 10:03:19.523922 /lava-11336429/1/../bin/lava-tes<8>[ 29.798181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11435 10:03:19.524014 t-case
11436 10:03:19.524252 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11438 10:03:19.534593 /lava-11336429/1/../bin/lava-test-case
11439 10:03:19.541178 <8>[ 29.816739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11440 10:03:19.541435 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11442 10:03:19.555876 /lava-11336429/1/../bin/lava-tes<8>[ 29.830596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11443 10:03:19.555979 t-case
11444 10:03:19.556220 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11446 10:03:19.568936 /lava-11336429/1/../bin/lava-test-case
11447 10:03:19.575225 <8>[ 29.852451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11448 10:03:19.575484 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11450 10:03:19.584888 /lava-11336429/1/../bin/lava-test-case
11451 10:03:19.591225 <8>[ 29.867176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11452 10:03:19.591561 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11454 10:03:19.603428 /lava-11336429/1/../bin/lava-test-case
11455 10:03:19.610256 <8>[ 29.885448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11456 10:03:19.610515 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11458 10:03:19.618036 /lava-11336429/1/../bin/lava-test-case
11459 10:03:19.624797 <8>[ 29.899901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11460 10:03:19.625055 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11462 10:03:19.639480 /lava-11336429/1/../bin/lava-tes<8>[ 29.917288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11463 10:03:19.639761 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11465 10:03:19.642573 t-case
11466 10:03:19.650629 /lava-11336429/1/../bin/lava-test-case
11467 10:03:19.657507 <8>[ 29.934397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11468 10:03:19.657777 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11470 10:03:19.670382 /lava-11336429/1/../bin/lava-test-case
11471 10:03:19.677296 <8>[ 29.952561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11472 10:03:19.677558 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11474 10:03:19.684899 /lava-11336429/1/../bin/lava-test-case
11475 10:03:19.691450 <8>[ 29.967590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11476 10:03:19.691731 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11478 10:03:19.702354 /lava-11336429/1/../bin/lava-test-case
11479 10:03:19.708748 <8>[ 29.985435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11480 10:03:19.709001 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11482 10:03:19.719168 /lava-11336429/1/../bin/lava-test-case
11483 10:03:19.725406 <8>[ 30.000615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11484 10:03:19.725671 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11486 10:03:19.735958 /lava-11336429/1/../bin/lava-test-case
11487 10:03:19.742468 <8>[ 30.017869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11488 10:03:19.742736 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11490 10:03:20.754867 /lava-11336429/1/../bin/lava-test-case
11491 10:03:20.761406 <8>[ 31.037955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11492 10:03:20.761681 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11494 10:03:21.774377 /lava-11336429/1/../bin/lava-test-case
11495 10:03:21.781034 <8>[ 32.058337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11496 10:03:21.781314 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11497 10:03:21.781407 Bad test result: blocked
11498 10:03:21.792404 /lava-11336429/1/../bin/lava-test-case
11499 10:03:21.798854 <8>[ 32.073934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11500 10:03:21.799127 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11502 10:03:22.813554 /lava-11336429/1/../bin/lava-test-case
11503 10:03:22.820557 <8>[ 33.097173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11504 10:03:22.820853 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11506 10:03:22.830686 /lava-11336429/1/../bin/lava-test-case
11507 10:03:22.837666 <8>[ 33.113366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11508 10:03:22.837927 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11510 10:03:22.853755 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11512 10:03:22.856724 /lava-11336429/1/../bin/lava-tes<8>[ 33.131405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11513 10:03:22.856807 t-case
11514 10:03:22.871415 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11516 10:03:22.874174 /lava-11336429/1/../bin/lava-tes<8>[ 33.149402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11517 10:03:22.874256 t-case
11518 10:03:22.882565 /lava-11336429/1/../bin/lava-test-case
11519 10:03:22.888970 <8>[ 33.165097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11520 10:03:22.889227 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11522 10:03:22.901858 /lava-11336429/1/../bin/lava-test-case
11523 10:03:22.908481 <8>[ 33.184388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11524 10:03:22.908735 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11526 10:03:22.924366 /lava-11336429/1/../bin/lava-tes<8>[ 33.199303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11527 10:03:22.924461 t-case
11528 10:03:22.924723 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11530 10:03:23.936744 /lava-11336429/1/../bin/lava-test-case
11531 10:03:23.943434 <8>[ 34.219851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11532 10:03:23.943703 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11534 10:03:23.963058 /lava-11336429/1/../bin/lava-tes<8>[ 34.238361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11535 10:03:23.963141 t-case
11536 10:03:23.963375 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11538 10:03:24.975888 /lava-11336429/1/../bin/lava-test-case
11539 10:03:24.982344 <8>[ 35.258239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11540 10:03:24.982618 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11542 10:03:24.990236 /lava-11336429/1/../bin/lava-test-case
11543 10:03:24.996726 <8>[ 35.273163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11544 10:03:24.996980 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11546 10:03:26.011821 /lava-11336429/1/../bin/lava-test-case
11547 10:03:26.018511 <8>[ 36.296167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11548 10:03:26.018802 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11550 10:03:26.028606 /lava-11336429/1/../bin/lava-test-case
11551 10:03:26.034757 <8>[ 36.310617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11552 10:03:26.035032 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11554 10:03:27.051976 /lava-11336429/1/../bin/lava-test-case
11555 10:03:27.058657 <8>[ 37.336205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11556 10:03:27.058956 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11558 10:03:27.068238 /lava-11336429/1/../bin/lava-test-case
11559 10:03:27.075190 <8>[ 37.350489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11560 10:03:27.075471 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11562 10:03:27.092504 /lava-11336429/1/../bin/lava-tes<8>[ 37.371059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11563 10:03:27.092808 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11565 10:03:27.095507 t-case
11566 10:03:27.106289 /lava-11336429/1/../bin/lava-test-case
11567 10:03:27.113044 <8>[ 37.389470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11568 10:03:27.113333 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11570 10:03:27.132522 /lava-11336429/1/../bin/lava-tes<8>[ 37.407614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11571 10:03:27.132665 t-case
11572 10:03:27.132912 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11574 10:03:27.141843 /lava-11336429/1/../bin/lava-test-case
11575 10:03:27.148602 <8>[ 37.425149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11576 10:03:27.148885 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11578 10:03:27.168068 /lava-11336429/1/../bin/lava-tes<8>[ 37.443126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11579 10:03:27.168212 t-case
11580 10:03:27.168459 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11582 10:03:27.179786 /lava-11336429/1/../bin/lava-test-case
11583 10:03:27.186630 <8>[ 37.462712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11584 10:03:27.186909 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11586 10:03:27.195111 /lava-11336429/1/../bin/lava-test-case
11587 10:03:27.201189 <8>[ 37.477750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11588 10:03:27.201467 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11590 10:03:27.213187 /lava-11336429/1/../bin/lava-test-case
11591 10:03:27.219925 <8>[ 37.496351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11592 10:03:27.220276 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11594 10:03:27.223760 + set +x
11595 10:03:27.227153 Received signal: <ENDRUN> 1_bootrr 11336429_1.5.2.3.5
11596 10:03:27.227275 Ending use of test pattern.
11597 10:03:27.227347 Ending test lava.1_bootrr (11336429_1.5.2.3.5), duration 20.28
11599 10:03:27.230144 <8>[ 37.506366] <LAVA_SIGNAL_ENDRUN 1_bootrr 11336429_1.5.2.3.5>
11600 10:03:27.230402 ok: lava_test_shell seems to have completed
11601 10:03:27.231760 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11602 10:03:27.231929 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11603 10:03:27.232072 end: 4 lava-test-retry (duration 00:00:21) [common]
11604 10:03:27.232219 start: 5 finalize (timeout 00:08:01) [common]
11605 10:03:27.232317 start: 5.1 power-off (timeout 00:00:30) [common]
11606 10:03:27.232484 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11607 10:03:27.314119 >> Command sent successfully.
11608 10:03:27.316622 Returned 0 in 0 seconds
11609 10:03:27.417051 end: 5.1 power-off (duration 00:00:00) [common]
11611 10:03:27.417401 start: 5.2 read-feedback (timeout 00:08:01) [common]
11613 10:03:27.417969 Listened to connection for namespace 'common' for up to 1s
11614 10:03:28.418630 Finalising connection for namespace 'common'
11615 10:03:28.418813 Disconnecting from shell: Finalise
11616 10:03:28.418895 / #
11617 10:03:28.519244 end: 5.2 read-feedback (duration 00:00:01) [common]
11618 10:03:28.519426 end: 5 finalize (duration 00:00:01) [common]
11619 10:03:28.519542 Cleaning after the job
11620 10:03:28.519727 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/ramdisk
11621 10:03:28.522698 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/kernel
11622 10:03:28.531070 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/dtb
11623 10:03:28.531291 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336429/tftp-deploy-fwpr3tbr/modules
11624 10:03:28.538435 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11336429
11625 10:03:28.585353 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11336429
11626 10:03:28.585534 Job finished correctly