Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 27
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 38
- Errors: 1
1 10:00:02.439833 lava-dispatcher, installed at version: 2023.06
2 10:00:02.440042 start: 0 validate
3 10:00:02.440182 Start time: 2023-08-23 10:00:02.440174+00:00 (UTC)
4 10:00:02.440317 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:02.440465 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 10:00:02.709928 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:02.710866 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:00:09.484248 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:00:09.484775 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:00:09.748491 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:00:09.748721 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:00:10.267737 Using caching service: 'http://localhost/cache/?uri=%s'
13 10:00:10.268431 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 10:00:23.271529 validate duration: 20.83
16 10:00:23.271792 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:00:23.271893 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:00:23.271981 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:00:23.272113 Not decompressing ramdisk as can be used compressed.
20 10:00:23.272199 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 10:00:23.272262 saving as /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/ramdisk/initrd.cpio.gz
22 10:00:23.272323 total size: 4665412 (4 MB)
23 10:00:23.539565 progress 0 % (0 MB)
24 10:00:23.547757 progress 5 % (0 MB)
25 10:00:23.554258 progress 10 % (0 MB)
26 10:00:23.560724 progress 15 % (0 MB)
27 10:00:23.566567 progress 20 % (0 MB)
28 10:00:23.570820 progress 25 % (1 MB)
29 10:00:23.574273 progress 30 % (1 MB)
30 10:00:23.577206 progress 35 % (1 MB)
31 10:00:23.579915 progress 40 % (1 MB)
32 10:00:23.582546 progress 45 % (2 MB)
33 10:00:23.584822 progress 50 % (2 MB)
34 10:00:23.586848 progress 55 % (2 MB)
35 10:00:23.588837 progress 60 % (2 MB)
36 10:00:23.590753 progress 65 % (2 MB)
37 10:00:23.592457 progress 70 % (3 MB)
38 10:00:23.594171 progress 75 % (3 MB)
39 10:00:23.595812 progress 80 % (3 MB)
40 10:00:23.597572 progress 85 % (3 MB)
41 10:00:23.599086 progress 90 % (4 MB)
42 10:00:23.600644 progress 95 % (4 MB)
43 10:00:23.602050 progress 100 % (4 MB)
44 10:00:23.602219 4 MB downloaded in 0.33 s (13.49 MB/s)
45 10:00:23.602383 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:00:23.602649 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:00:23.602744 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:00:23.602837 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:00:23.602992 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 10:00:23.603071 saving as /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/kernel/Image
52 10:00:23.603140 total size: 49220096 (46 MB)
53 10:00:23.603208 No compression specified
54 10:00:23.869329 progress 0 % (0 MB)
55 10:00:23.882380 progress 5 % (2 MB)
56 10:00:23.895056 progress 10 % (4 MB)
57 10:00:23.907749 progress 15 % (7 MB)
58 10:00:23.920473 progress 20 % (9 MB)
59 10:00:23.933378 progress 25 % (11 MB)
60 10:00:23.946209 progress 30 % (14 MB)
61 10:00:23.959162 progress 35 % (16 MB)
62 10:00:23.971889 progress 40 % (18 MB)
63 10:00:23.984734 progress 45 % (21 MB)
64 10:00:23.997756 progress 50 % (23 MB)
65 10:00:24.010561 progress 55 % (25 MB)
66 10:00:24.023225 progress 60 % (28 MB)
67 10:00:24.035992 progress 65 % (30 MB)
68 10:00:24.048720 progress 70 % (32 MB)
69 10:00:24.061474 progress 75 % (35 MB)
70 10:00:24.074329 progress 80 % (37 MB)
71 10:00:24.086928 progress 85 % (39 MB)
72 10:00:24.099595 progress 90 % (42 MB)
73 10:00:24.112078 progress 95 % (44 MB)
74 10:00:24.124602 progress 100 % (46 MB)
75 10:00:24.124734 46 MB downloaded in 0.52 s (89.99 MB/s)
76 10:00:24.124888 end: 1.2.1 http-download (duration 00:00:01) [common]
78 10:00:24.125129 end: 1.2 download-retry (duration 00:00:01) [common]
79 10:00:24.125217 start: 1.3 download-retry (timeout 00:09:59) [common]
80 10:00:24.125307 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 10:00:24.125456 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 10:00:24.125530 saving as /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/dtb/mt8192-asurada-spherion-r0.dtb
83 10:00:24.125592 total size: 47278 (0 MB)
84 10:00:24.125652 No compression specified
85 10:00:24.387877 progress 69 % (0 MB)
86 10:00:24.388220 progress 100 % (0 MB)
87 10:00:24.388386 0 MB downloaded in 0.26 s (0.17 MB/s)
88 10:00:24.388532 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:00:24.388865 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:00:24.388975 start: 1.4 download-retry (timeout 00:09:59) [common]
92 10:00:24.389059 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 10:00:24.389200 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 10:00:24.389269 saving as /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/nfsrootfs/full.rootfs.tar
95 10:00:24.389330 total size: 125290964 (119 MB)
96 10:00:24.389392 Using unxz to decompress xz
97 10:00:24.658668 progress 0 % (0 MB)
98 10:00:24.993029 progress 5 % (6 MB)
99 10:00:25.339806 progress 10 % (11 MB)
100 10:00:25.678225 progress 15 % (17 MB)
101 10:00:25.874261 progress 20 % (23 MB)
102 10:00:26.048376 progress 25 % (29 MB)
103 10:00:26.396212 progress 30 % (35 MB)
104 10:00:26.749568 progress 35 % (41 MB)
105 10:00:27.133821 progress 40 % (47 MB)
106 10:00:27.520465 progress 45 % (53 MB)
107 10:00:27.919666 progress 50 % (59 MB)
108 10:00:28.288992 progress 55 % (65 MB)
109 10:00:28.666390 progress 60 % (71 MB)
110 10:00:29.008172 progress 65 % (77 MB)
111 10:00:29.370897 progress 70 % (83 MB)
112 10:00:29.750745 progress 75 % (89 MB)
113 10:00:30.175558 progress 80 % (95 MB)
114 10:00:30.602715 progress 85 % (101 MB)
115 10:00:30.860331 progress 90 % (107 MB)
116 10:00:31.210645 progress 95 % (113 MB)
117 10:00:31.595402 progress 100 % (119 MB)
118 10:00:31.601089 119 MB downloaded in 7.21 s (16.57 MB/s)
119 10:00:31.601355 end: 1.4.1 http-download (duration 00:00:07) [common]
121 10:00:31.601620 end: 1.4 download-retry (duration 00:00:07) [common]
122 10:00:31.601713 start: 1.5 download-retry (timeout 00:09:52) [common]
123 10:00:31.601801 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 10:00:31.601966 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 10:00:31.602040 saving as /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/modules/modules.tar
126 10:00:31.602102 total size: 8617228 (8 MB)
127 10:00:31.602167 Using unxz to decompress xz
128 10:00:31.606058 progress 0 % (0 MB)
129 10:00:31.627458 progress 5 % (0 MB)
130 10:00:31.650080 progress 10 % (0 MB)
131 10:00:31.677607 progress 15 % (1 MB)
132 10:00:31.704343 progress 20 % (1 MB)
133 10:00:31.731004 progress 25 % (2 MB)
134 10:00:31.758032 progress 30 % (2 MB)
135 10:00:31.784862 progress 35 % (2 MB)
136 10:00:31.810568 progress 40 % (3 MB)
137 10:00:31.835818 progress 45 % (3 MB)
138 10:00:31.863531 progress 50 % (4 MB)
139 10:00:31.890115 progress 55 % (4 MB)
140 10:00:31.915920 progress 60 % (4 MB)
141 10:00:31.939661 progress 65 % (5 MB)
142 10:00:31.968894 progress 70 % (5 MB)
143 10:00:31.994009 progress 75 % (6 MB)
144 10:00:32.021102 progress 80 % (6 MB)
145 10:00:32.052378 progress 85 % (7 MB)
146 10:00:32.080114 progress 90 % (7 MB)
147 10:00:32.105440 progress 95 % (7 MB)
148 10:00:32.129547 progress 100 % (8 MB)
149 10:00:32.136180 8 MB downloaded in 0.53 s (15.39 MB/s)
150 10:00:32.136495 end: 1.5.1 http-download (duration 00:00:01) [common]
152 10:00:32.136805 end: 1.5 download-retry (duration 00:00:01) [common]
153 10:00:32.136901 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 10:00:32.136996 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 10:00:34.317326 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11336442/extract-nfsrootfs-f56f79f8
156 10:00:34.317515 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 10:00:34.317619 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 10:00:34.317787 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg
159 10:00:34.317953 makedir: /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin
160 10:00:34.318056 makedir: /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/tests
161 10:00:34.318157 makedir: /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/results
162 10:00:34.318257 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-add-keys
163 10:00:34.318404 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-add-sources
164 10:00:34.318553 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-background-process-start
165 10:00:34.318696 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-background-process-stop
166 10:00:34.318826 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-common-functions
167 10:00:34.318951 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-echo-ipv4
168 10:00:34.319075 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-install-packages
169 10:00:34.319202 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-installed-packages
170 10:00:34.319325 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-os-build
171 10:00:34.319454 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-probe-channel
172 10:00:34.319578 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-probe-ip
173 10:00:34.319702 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-target-ip
174 10:00:34.319829 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-target-mac
175 10:00:34.319952 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-target-storage
176 10:00:34.320078 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-test-case
177 10:00:34.320232 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-test-event
178 10:00:34.320355 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-test-feedback
179 10:00:34.320485 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-test-raise
180 10:00:34.320610 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-test-reference
181 10:00:34.321037 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-test-runner
182 10:00:34.321168 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-test-set
183 10:00:34.321294 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-test-shell
184 10:00:34.321422 Updating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-install-packages (oe)
185 10:00:34.321576 Updating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/bin/lava-installed-packages (oe)
186 10:00:34.321699 Creating /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/environment
187 10:00:34.321795 LAVA metadata
188 10:00:34.321866 - LAVA_JOB_ID=11336442
189 10:00:34.321929 - LAVA_DISPATCHER_IP=192.168.201.1
190 10:00:34.322029 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 10:00:34.322096 skipped lava-vland-overlay
192 10:00:34.322170 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 10:00:34.322248 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 10:00:34.322323 skipped lava-multinode-overlay
195 10:00:34.322408 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 10:00:34.322484 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 10:00:34.322556 Loading test definitions
198 10:00:34.322640 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 10:00:34.322709 Using /lava-11336442 at stage 0
200 10:00:34.323029 uuid=11336442_1.6.2.3.1 testdef=None
201 10:00:34.323117 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 10:00:34.323201 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 10:00:34.323706 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 10:00:34.323924 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 10:00:34.324573 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 10:00:34.324824 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 10:00:34.325447 runner path: /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/0/tests/0_dmesg test_uuid 11336442_1.6.2.3.1
210 10:00:34.325604 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 10:00:34.325826 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 10:00:34.325897 Using /lava-11336442 at stage 1
214 10:00:34.326206 uuid=11336442_1.6.2.3.5 testdef=None
215 10:00:34.326293 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 10:00:34.326377 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 10:00:34.326875 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 10:00:34.327090 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 10:00:34.327726 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 10:00:34.327952 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 10:00:34.328578 runner path: /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/1/tests/1_bootrr test_uuid 11336442_1.6.2.3.5
224 10:00:34.328773 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 10:00:34.329037 Creating lava-test-runner.conf files
227 10:00:34.329100 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/0 for stage 0
228 10:00:34.329189 - 0_dmesg
229 10:00:34.329268 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11336442/lava-overlay-fmub6zvg/lava-11336442/1 for stage 1
230 10:00:34.329358 - 1_bootrr
231 10:00:34.329452 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 10:00:34.329537 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 10:00:34.337019 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 10:00:34.337121 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 10:00:34.337205 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 10:00:34.337288 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 10:00:34.337371 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 10:00:34.458926 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 10:00:34.459321 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 10:00:34.459449 extracting modules file /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11336442/extract-nfsrootfs-f56f79f8
241 10:00:34.683239 extracting modules file /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11336442/extract-overlay-ramdisk-ade9ybcq/ramdisk
242 10:00:34.911567 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 10:00:34.911741 start: 1.6.5 apply-overlay-tftp (timeout 00:09:48) [common]
244 10:00:34.911842 [common] Applying overlay to NFS
245 10:00:34.911917 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11336442/compress-overlay-ebrrf4jh/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11336442/extract-nfsrootfs-f56f79f8
246 10:00:34.920101 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 10:00:34.920218 start: 1.6.6 configure-preseed-file (timeout 00:09:48) [common]
248 10:00:34.920312 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 10:00:34.920399 start: 1.6.7 compress-ramdisk (timeout 00:09:48) [common]
250 10:00:34.920479 Building ramdisk /var/lib/lava/dispatcher/tmp/11336442/extract-overlay-ramdisk-ade9ybcq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11336442/extract-overlay-ramdisk-ade9ybcq/ramdisk
251 10:00:35.217679 >> 119213 blocks
252 10:00:37.116187 rename /var/lib/lava/dispatcher/tmp/11336442/extract-overlay-ramdisk-ade9ybcq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/ramdisk/ramdisk.cpio.gz
253 10:00:37.116766 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 10:00:37.116901 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
255 10:00:37.117005 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
256 10:00:37.117117 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/kernel/Image'
257 10:00:50.248386 Returned 0 in 13 seconds
258 10:00:50.349073 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/kernel/image.itb
259 10:00:50.688614 output: FIT description: Kernel Image image with one or more FDT blobs
260 10:00:50.689028 output: Created: Wed Aug 23 11:00:50 2023
261 10:00:50.689102 output: Image 0 (kernel-1)
262 10:00:50.689169 output: Description:
263 10:00:50.689231 output: Created: Wed Aug 23 11:00:50 2023
264 10:00:50.689293 output: Type: Kernel Image
265 10:00:50.689355 output: Compression: lzma compressed
266 10:00:50.689416 output: Data Size: 11037260 Bytes = 10778.57 KiB = 10.53 MiB
267 10:00:50.689484 output: Architecture: AArch64
268 10:00:50.689544 output: OS: Linux
269 10:00:50.689603 output: Load Address: 0x00000000
270 10:00:50.689656 output: Entry Point: 0x00000000
271 10:00:50.689710 output: Hash algo: crc32
272 10:00:50.689763 output: Hash value: 17b65cb3
273 10:00:50.689817 output: Image 1 (fdt-1)
274 10:00:50.689870 output: Description: mt8192-asurada-spherion-r0
275 10:00:50.689922 output: Created: Wed Aug 23 11:00:50 2023
276 10:00:50.689976 output: Type: Flat Device Tree
277 10:00:50.690028 output: Compression: uncompressed
278 10:00:50.690081 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 10:00:50.690134 output: Architecture: AArch64
280 10:00:50.690187 output: Hash algo: crc32
281 10:00:50.690239 output: Hash value: cc4352de
282 10:00:50.690291 output: Image 2 (ramdisk-1)
283 10:00:50.690344 output: Description: unavailable
284 10:00:50.690396 output: Created: Wed Aug 23 11:00:50 2023
285 10:00:50.690448 output: Type: RAMDisk Image
286 10:00:50.690501 output: Compression: Unknown Compression
287 10:00:50.690554 output: Data Size: 17767501 Bytes = 17351.08 KiB = 16.94 MiB
288 10:00:50.690607 output: Architecture: AArch64
289 10:00:50.690660 output: OS: Linux
290 10:00:50.690712 output: Load Address: unavailable
291 10:00:50.690764 output: Entry Point: unavailable
292 10:00:50.690817 output: Hash algo: crc32
293 10:00:50.690869 output: Hash value: a3885cd7
294 10:00:50.690921 output: Default Configuration: 'conf-1'
295 10:00:50.690973 output: Configuration 0 (conf-1)
296 10:00:50.691026 output: Description: mt8192-asurada-spherion-r0
297 10:00:50.691079 output: Kernel: kernel-1
298 10:00:50.691131 output: Init Ramdisk: ramdisk-1
299 10:00:50.691184 output: FDT: fdt-1
300 10:00:50.691236 output: Loadables: kernel-1
301 10:00:50.691289 output:
302 10:00:50.691498 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 10:00:50.691655 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 10:00:50.691772 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
305 10:00:50.691868 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 10:00:50.691950 No LXC device requested
307 10:00:50.692040 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 10:00:50.692131 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 10:00:50.692212 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 10:00:50.692281 Checking files for TFTP limit of 4294967296 bytes.
311 10:00:50.692828 end: 1 tftp-deploy (duration 00:00:27) [common]
312 10:00:50.692934 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 10:00:50.693025 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 10:00:50.693150 substitutions:
315 10:00:50.693217 - {DTB}: 11336442/tftp-deploy-pqke0388/dtb/mt8192-asurada-spherion-r0.dtb
316 10:00:50.693283 - {INITRD}: 11336442/tftp-deploy-pqke0388/ramdisk/ramdisk.cpio.gz
317 10:00:50.693342 - {KERNEL}: 11336442/tftp-deploy-pqke0388/kernel/Image
318 10:00:50.693400 - {LAVA_MAC}: None
319 10:00:50.693457 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11336442/extract-nfsrootfs-f56f79f8
320 10:00:50.693519 - {NFS_SERVER_IP}: 192.168.201.1
321 10:00:50.693574 - {PRESEED_CONFIG}: None
322 10:00:50.693629 - {PRESEED_LOCAL}: None
323 10:00:50.693683 - {RAMDISK}: 11336442/tftp-deploy-pqke0388/ramdisk/ramdisk.cpio.gz
324 10:00:50.693738 - {ROOT_PART}: None
325 10:00:50.693792 - {ROOT}: None
326 10:00:50.693846 - {SERVER_IP}: 192.168.201.1
327 10:00:50.693900 - {TEE}: None
328 10:00:50.693954 Parsed boot commands:
329 10:00:50.694009 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 10:00:50.694194 Parsed boot commands: tftpboot 192.168.201.1 11336442/tftp-deploy-pqke0388/kernel/image.itb 11336442/tftp-deploy-pqke0388/kernel/cmdline
331 10:00:50.694282 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 10:00:50.694365 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 10:00:50.694454 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 10:00:50.694540 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 10:00:50.694611 Not connected, no need to disconnect.
336 10:00:50.694683 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 10:00:50.694767 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 10:00:50.694832 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
339 10:00:50.698724 Setting prompt string to ['lava-test: # ']
340 10:00:50.699098 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 10:00:50.699209 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 10:00:50.699306 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 10:00:50.699398 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 10:00:50.699632 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
345 10:00:55.848291 >> Command sent successfully.
346 10:00:55.858922 Returned 0 in 5 seconds
347 10:00:55.960259 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 10:00:55.961804 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 10:00:55.962350 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 10:00:55.962825 Setting prompt string to 'Starting depthcharge on Spherion...'
352 10:00:55.963187 Changing prompt to 'Starting depthcharge on Spherion...'
353 10:00:55.963544 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 10:00:55.964820 [Enter `^Ec?' for help]
355 10:00:56.129522
356 10:00:56.130035
357 10:00:56.130376 F0: 102B 0000
358 10:00:56.130699
359 10:00:56.131005 F3: 1001 0000 [0200]
360 10:00:56.132807
361 10:00:56.133234 F3: 1001 0000
362 10:00:56.133574
363 10:00:56.133888 F7: 102D 0000
364 10:00:56.134192
365 10:00:56.135761 F1: 0000 0000
366 10:00:56.136185
367 10:00:56.136521 V0: 0000 0000 [0001]
368 10:00:56.136895
369 10:00:56.139365 00: 0007 8000
370 10:00:56.139843
371 10:00:56.140178 01: 0000 0000
372 10:00:56.140518
373 10:00:56.143047 BP: 0C00 0209 [0000]
374 10:00:56.143576
375 10:00:56.143923 G0: 1182 0000
376 10:00:56.144235
377 10:00:56.146405 EC: 0000 0021 [4000]
378 10:00:56.146936
379 10:00:56.147276 S7: 0000 0000 [0000]
380 10:00:56.147591
381 10:00:56.149485 CC: 0000 0000 [0001]
382 10:00:56.149910
383 10:00:56.150245 T0: 0000 0040 [010F]
384 10:00:56.150561
385 10:00:56.150862 Jump to BL
386 10:00:56.151154
387 10:00:56.176298
388 10:00:56.176872
389 10:00:56.177215
390 10:00:56.183925 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 10:00:56.187254 ARM64: Exception handlers installed.
392 10:00:56.191346 ARM64: Testing exception
393 10:00:56.194446 ARM64: Done test exception
394 10:00:56.201459 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 10:00:56.211461 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 10:00:56.218197 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 10:00:56.228704 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 10:00:56.235270 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 10:00:56.241711 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 10:00:56.253153 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 10:00:56.260526 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 10:00:56.279393 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 10:00:56.282778 WDT: Last reset was cold boot
404 10:00:56.286434 SPI1(PAD0) initialized at 2873684 Hz
405 10:00:56.289744 SPI5(PAD0) initialized at 992727 Hz
406 10:00:56.293012 VBOOT: Loading verstage.
407 10:00:56.299458 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 10:00:56.302888 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 10:00:56.306424 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 10:00:56.309439 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 10:00:56.317224 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 10:00:56.323209 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 10:00:56.334435 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 10:00:56.334960
415 10:00:56.335293
416 10:00:56.344143 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 10:00:56.347828 ARM64: Exception handlers installed.
418 10:00:56.351331 ARM64: Testing exception
419 10:00:56.351851 ARM64: Done test exception
420 10:00:56.358062 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 10:00:56.360572 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 10:00:56.374901 Probing TPM: . done!
423 10:00:56.375424 TPM ready after 0 ms
424 10:00:56.383497 Connected to device vid:did:rid of 1ae0:0028:00
425 10:00:56.390470 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 10:00:56.448816 Initialized TPM device CR50 revision 0
427 10:00:56.459223 tlcl_send_startup: Startup return code is 0
428 10:00:56.459735 TPM: setup succeeded
429 10:00:56.471647 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 10:00:56.479822 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 10:00:56.492661 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 10:00:56.502076 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 10:00:56.505254 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 10:00:56.510810 in-header: 03 07 00 00 08 00 00 00
435 10:00:56.514333 in-data: aa e4 47 04 13 02 00 00
436 10:00:56.517674 Chrome EC: UHEPI supported
437 10:00:56.525099 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 10:00:56.528288 in-header: 03 ad 00 00 08 00 00 00
439 10:00:56.532038 in-data: 00 20 20 08 00 00 00 00
440 10:00:56.532463 Phase 1
441 10:00:56.536191 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 10:00:56.543364 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 10:00:56.546768 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 10:00:56.550390 Recovery requested (1009000e)
445 10:00:56.559446 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 10:00:56.564392 tlcl_extend: response is 0
447 10:00:56.574630 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 10:00:56.579687 tlcl_extend: response is 0
449 10:00:56.586895 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 10:00:56.606793 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 10:00:56.613503 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 10:00:56.613939
453 10:00:56.614274
454 10:00:56.624844 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 10:00:56.627863 ARM64: Exception handlers installed.
456 10:00:56.628320 ARM64: Testing exception
457 10:00:56.631466 ARM64: Done test exception
458 10:00:56.651393 pmic_efuse_setting: Set efuses in 11 msecs
459 10:00:56.655297 pmwrap_interface_init: Select PMIF_VLD_RDY
460 10:00:56.662307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 10:00:56.665897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 10:00:56.672251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 10:00:56.676255 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 10:00:56.680589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 10:00:56.684071 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 10:00:56.691644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 10:00:56.695359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 10:00:56.699094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 10:00:56.702520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 10:00:56.709862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 10:00:56.713864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 10:00:56.717597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 10:00:56.725256 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 10:00:56.728611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 10:00:56.736244 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 10:00:56.739843 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 10:00:56.746666 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 10:00:56.750547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 10:00:56.758765 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 10:00:56.762536 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 10:00:56.770580 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 10:00:56.774023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 10:00:56.781699 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 10:00:56.785399 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 10:00:56.792840 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 10:00:56.796840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 10:00:56.799998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 10:00:56.807310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 10:00:56.810995 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 10:00:56.814539 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 10:00:56.822044 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 10:00:56.825667 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 10:00:56.829645 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 10:00:56.837231 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 10:00:56.840996 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 10:00:56.844838 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 10:00:56.852467 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 10:00:56.855913 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 10:00:56.859131 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 10:00:56.862934 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 10:00:56.867058 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 10:00:56.874412 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 10:00:56.877967 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 10:00:56.881760 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 10:00:56.885256 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 10:00:56.889432 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 10:00:56.893672 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 10:00:56.900149 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 10:00:56.904060 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 10:00:56.907548 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 10:00:56.915181 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 10:00:56.923147 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 10:00:56.926086 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 10:00:56.938043 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 10:00:56.944646 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 10:00:56.949197 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 10:00:56.952493 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 10:00:56.955466 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 10:00:56.964608 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x6
520 10:00:56.968618 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 10:00:56.976713 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 10:00:56.979808 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 10:00:56.988939 [RTC]rtc_get_frequency_meter,154: input=15, output=790
524 10:00:56.998584 [RTC]rtc_get_frequency_meter,154: input=23, output=978
525 10:00:57.008224 [RTC]rtc_get_frequency_meter,154: input=19, output=885
526 10:00:57.017926 [RTC]rtc_get_frequency_meter,154: input=17, output=837
527 10:00:57.027081 [RTC]rtc_get_frequency_meter,154: input=16, output=814
528 10:00:57.036642 [RTC]rtc_get_frequency_meter,154: input=15, output=790
529 10:00:57.046414 [RTC]rtc_get_frequency_meter,154: input=16, output=814
530 10:00:57.049912 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
531 10:00:57.053645 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
532 10:00:57.057717 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 10:00:57.064826 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 10:00:57.068591 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 10:00:57.072576 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 10:00:57.076089 ADC[4]: Raw value=902436 ID=7
537 10:00:57.076173 ADC[3]: Raw value=213336 ID=1
538 10:00:57.079993 RAM Code: 0x71
539 10:00:57.083481 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 10:00:57.087589 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 10:00:57.099333 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 10:00:57.102570 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 10:00:57.106076 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 10:00:57.109440 in-header: 03 07 00 00 08 00 00 00
545 10:00:57.113659 in-data: aa e4 47 04 13 02 00 00
546 10:00:57.117679 Chrome EC: UHEPI supported
547 10:00:57.124579 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 10:00:57.128488 in-header: 03 ed 00 00 08 00 00 00
549 10:00:57.132059 in-data: 80 20 60 08 00 00 00 00
550 10:00:57.132220 MRC: failed to locate region type 0.
551 10:00:57.139762 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 10:00:57.143350 DRAM-K: Running full calibration
553 10:00:57.151030 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 10:00:57.151354 header.status = 0x0
555 10:00:57.155310 header.version = 0x6 (expected: 0x6)
556 10:00:57.159099 header.size = 0xd00 (expected: 0xd00)
557 10:00:57.159538 header.flags = 0x0
558 10:00:57.166433 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 10:00:57.184551 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 10:00:57.191972 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 10:00:57.192422 dram_init: ddr_geometry: 2
562 10:00:57.196073 [EMI] MDL number = 2
563 10:00:57.196522 [EMI] Get MDL freq = 0
564 10:00:57.199638 dram_init: ddr_type: 0
565 10:00:57.203541 is_discrete_lpddr4: 1
566 10:00:57.203988 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 10:00:57.204443
568 10:00:57.204944
569 10:00:57.207215 [Bian_co] ETT version 0.0.0.1
570 10:00:57.210949 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 10:00:57.214413
572 10:00:57.218423 dramc_set_vcore_voltage set vcore to 650000
573 10:00:57.218848 Read voltage for 800, 4
574 10:00:57.219185 Vio18 = 0
575 10:00:57.222001 Vcore = 650000
576 10:00:57.222579 Vdram = 0
577 10:00:57.222937 Vddq = 0
578 10:00:57.226309 Vmddr = 0
579 10:00:57.226753 dram_init: config_dvfs: 1
580 10:00:57.232816 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 10:00:57.236655 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 10:00:57.239649 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
583 10:00:57.243310 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
584 10:00:57.246493 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
585 10:00:57.253274 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
586 10:00:57.253788 MEM_TYPE=3, freq_sel=18
587 10:00:57.256834 sv_algorithm_assistance_LP4_1600
588 10:00:57.259637 ============ PULL DRAM RESETB DOWN ============
589 10:00:57.266790 ========== PULL DRAM RESETB DOWN end =========
590 10:00:57.270026 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 10:00:57.273675 ===================================
592 10:00:57.276639 LPDDR4 DRAM CONFIGURATION
593 10:00:57.280157 ===================================
594 10:00:57.280716 EX_ROW_EN[0] = 0x0
595 10:00:57.283589 EX_ROW_EN[1] = 0x0
596 10:00:57.284020 LP4Y_EN = 0x0
597 10:00:57.287226 WORK_FSP = 0x0
598 10:00:57.287756 WL = 0x2
599 10:00:57.289983 RL = 0x2
600 10:00:57.290411 BL = 0x2
601 10:00:57.293591 RPST = 0x0
602 10:00:57.294016 RD_PRE = 0x0
603 10:00:57.296579 WR_PRE = 0x1
604 10:00:57.297052 WR_PST = 0x0
605 10:00:57.299889 DBI_WR = 0x0
606 10:00:57.300313 DBI_RD = 0x0
607 10:00:57.303482 OTF = 0x1
608 10:00:57.307141 ===================================
609 10:00:57.310551 ===================================
610 10:00:57.310979 ANA top config
611 10:00:57.313649 ===================================
612 10:00:57.316937 DLL_ASYNC_EN = 0
613 10:00:57.320600 ALL_SLAVE_EN = 1
614 10:00:57.323818 NEW_RANK_MODE = 1
615 10:00:57.324255 DLL_IDLE_MODE = 1
616 10:00:57.326818 LP45_APHY_COMB_EN = 1
617 10:00:57.330290 TX_ODT_DIS = 1
618 10:00:57.333915 NEW_8X_MODE = 1
619 10:00:57.337369 ===================================
620 10:00:57.340276 ===================================
621 10:00:57.343653 data_rate = 1600
622 10:00:57.344081 CKR = 1
623 10:00:57.347458 DQ_P2S_RATIO = 8
624 10:00:57.351097 ===================================
625 10:00:57.353983 CA_P2S_RATIO = 8
626 10:00:57.357576 DQ_CA_OPEN = 0
627 10:00:57.360946 DQ_SEMI_OPEN = 0
628 10:00:57.361377 CA_SEMI_OPEN = 0
629 10:00:57.364270 CA_FULL_RATE = 0
630 10:00:57.367281 DQ_CKDIV4_EN = 1
631 10:00:57.370817 CA_CKDIV4_EN = 1
632 10:00:57.373894 CA_PREDIV_EN = 0
633 10:00:57.377174 PH8_DLY = 0
634 10:00:57.377602 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 10:00:57.380617 DQ_AAMCK_DIV = 4
636 10:00:57.383954 CA_AAMCK_DIV = 4
637 10:00:57.387649 CA_ADMCK_DIV = 4
638 10:00:57.390637 DQ_TRACK_CA_EN = 0
639 10:00:57.394561 CA_PICK = 800
640 10:00:57.395084 CA_MCKIO = 800
641 10:00:57.398111 MCKIO_SEMI = 0
642 10:00:57.402093 PLL_FREQ = 3068
643 10:00:57.404840 DQ_UI_PI_RATIO = 32
644 10:00:57.408810 CA_UI_PI_RATIO = 0
645 10:00:57.409482 ===================================
646 10:00:57.412762 ===================================
647 10:00:57.416362 memory_type:LPDDR4
648 10:00:57.420153 GP_NUM : 10
649 10:00:57.420576 SRAM_EN : 1
650 10:00:57.424032 MD32_EN : 0
651 10:00:57.424576 ===================================
652 10:00:57.427666 [ANA_INIT] >>>>>>>>>>>>>>
653 10:00:57.431494 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 10:00:57.434866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 10:00:57.438553 ===================================
656 10:00:57.439107 data_rate = 1600,PCW = 0X7600
657 10:00:57.441648 ===================================
658 10:00:57.445303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 10:00:57.452243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 10:00:57.458930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 10:00:57.462389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 10:00:57.465283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 10:00:57.469219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 10:00:57.472763 [ANA_INIT] flow start
665 10:00:57.473289 [ANA_INIT] PLL >>>>>>>>
666 10:00:57.475411 [ANA_INIT] PLL <<<<<<<<
667 10:00:57.478868 [ANA_INIT] MIDPI >>>>>>>>
668 10:00:57.482198 [ANA_INIT] MIDPI <<<<<<<<
669 10:00:57.482723 [ANA_INIT] DLL >>>>>>>>
670 10:00:57.485617 [ANA_INIT] flow end
671 10:00:57.489068 ============ LP4 DIFF to SE enter ============
672 10:00:57.492835 ============ LP4 DIFF to SE exit ============
673 10:00:57.496029 [ANA_INIT] <<<<<<<<<<<<<
674 10:00:57.498922 [Flow] Enable top DCM control >>>>>
675 10:00:57.502652 [Flow] Enable top DCM control <<<<<
676 10:00:57.506112 Enable DLL master slave shuffle
677 10:00:57.509424 ==============================================================
678 10:00:57.512251 Gating Mode config
679 10:00:57.519247 ==============================================================
680 10:00:57.520021 Config description:
681 10:00:57.528835 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 10:00:57.535457 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 10:00:57.539020 SELPH_MODE 0: By rank 1: By Phase
684 10:00:57.545610 ==============================================================
685 10:00:57.549572 GAT_TRACK_EN = 1
686 10:00:57.552481 RX_GATING_MODE = 2
687 10:00:57.556177 RX_GATING_TRACK_MODE = 2
688 10:00:57.559040 SELPH_MODE = 1
689 10:00:57.562707 PICG_EARLY_EN = 1
690 10:00:57.565969 VALID_LAT_VALUE = 1
691 10:00:57.569210 ==============================================================
692 10:00:57.572356 Enter into Gating configuration >>>>
693 10:00:57.575906 Exit from Gating configuration <<<<
694 10:00:57.579202 Enter into DVFS_PRE_config >>>>>
695 10:00:57.589478 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 10:00:57.592932 Exit from DVFS_PRE_config <<<<<
697 10:00:57.596172 Enter into PICG configuration >>>>
698 10:00:57.599680 Exit from PICG configuration <<<<
699 10:00:57.603145 [RX_INPUT] configuration >>>>>
700 10:00:57.606129 [RX_INPUT] configuration <<<<<
701 10:00:57.609904 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 10:00:57.616494 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 10:00:57.623465 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 10:00:57.630024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 10:00:57.633508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 10:00:57.640464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 10:00:57.643466 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 10:00:57.650106 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 10:00:57.653641 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 10:00:57.657089 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 10:00:57.660572 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 10:00:57.667376 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 10:00:57.670595 ===================================
714 10:00:57.671162 LPDDR4 DRAM CONFIGURATION
715 10:00:57.673864 ===================================
716 10:00:57.677120 EX_ROW_EN[0] = 0x0
717 10:00:57.677551 EX_ROW_EN[1] = 0x0
718 10:00:57.680359 LP4Y_EN = 0x0
719 10:00:57.680835 WORK_FSP = 0x0
720 10:00:57.683774 WL = 0x2
721 10:00:57.687155 RL = 0x2
722 10:00:57.687585 BL = 0x2
723 10:00:57.690505 RPST = 0x0
724 10:00:57.690935 RD_PRE = 0x0
725 10:00:57.694070 WR_PRE = 0x1
726 10:00:57.694500 WR_PST = 0x0
727 10:00:57.697069 DBI_WR = 0x0
728 10:00:57.697500 DBI_RD = 0x0
729 10:00:57.700588 OTF = 0x1
730 10:00:57.703995 ===================================
731 10:00:57.707476 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 10:00:57.710819 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 10:00:57.714328 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 10:00:57.717786 ===================================
735 10:00:57.720982 LPDDR4 DRAM CONFIGURATION
736 10:00:57.723893 ===================================
737 10:00:57.727602 EX_ROW_EN[0] = 0x10
738 10:00:57.728032 EX_ROW_EN[1] = 0x0
739 10:00:57.731158 LP4Y_EN = 0x0
740 10:00:57.731683 WORK_FSP = 0x0
741 10:00:57.734519 WL = 0x2
742 10:00:57.735042 RL = 0x2
743 10:00:57.737784 BL = 0x2
744 10:00:57.738424 RPST = 0x0
745 10:00:57.740645 RD_PRE = 0x0
746 10:00:57.741226 WR_PRE = 0x1
747 10:00:57.744312 WR_PST = 0x0
748 10:00:57.744829 DBI_WR = 0x0
749 10:00:57.747742 DBI_RD = 0x0
750 10:00:57.748265 OTF = 0x1
751 10:00:57.750737 ===================================
752 10:00:57.758001 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 10:00:57.762030 nWR fixed to 40
754 10:00:57.765380 [ModeRegInit_LP4] CH0 RK0
755 10:00:57.765868 [ModeRegInit_LP4] CH0 RK1
756 10:00:57.769078 [ModeRegInit_LP4] CH1 RK0
757 10:00:57.772095 [ModeRegInit_LP4] CH1 RK1
758 10:00:57.772754 match AC timing 13
759 10:00:57.778630 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 10:00:57.782060 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 10:00:57.785461 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 10:00:57.792589 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 10:00:57.795612 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 10:00:57.796304 [EMI DOE] emi_dcm 0
765 10:00:57.802623 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 10:00:57.803058 ==
767 10:00:57.806102 Dram Type= 6, Freq= 0, CH_0, rank 0
768 10:00:57.808949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 10:00:57.809380 ==
770 10:00:57.816044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 10:00:57.818855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 10:00:57.829817 [CA 0] Center 37 (6~68) winsize 63
773 10:00:57.833276 [CA 1] Center 37 (6~68) winsize 63
774 10:00:57.836408 [CA 2] Center 35 (5~66) winsize 62
775 10:00:57.839796 [CA 3] Center 35 (5~65) winsize 61
776 10:00:57.842813 [CA 4] Center 34 (3~65) winsize 63
777 10:00:57.846409 [CA 5] Center 33 (3~64) winsize 62
778 10:00:57.846841
779 10:00:57.849411 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 10:00:57.849842
781 10:00:57.852753 [CATrainingPosCal] consider 1 rank data
782 10:00:57.856285 u2DelayCellTimex100 = 270/100 ps
783 10:00:57.859588 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
784 10:00:57.862954 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 10:00:57.866522 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
786 10:00:57.873447 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
787 10:00:57.876342 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
788 10:00:57.879953 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 10:00:57.880376
790 10:00:57.883485 CA PerBit enable=1, Macro0, CA PI delay=33
791 10:00:57.883981
792 10:00:57.886779 [CBTSetCACLKResult] CA Dly = 33
793 10:00:57.887423 CS Dly: 5 (0~36)
794 10:00:57.887783 ==
795 10:00:57.890187 Dram Type= 6, Freq= 0, CH_0, rank 1
796 10:00:57.896601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 10:00:57.897095 ==
798 10:00:57.900030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 10:00:57.906698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 10:00:57.916164 [CA 0] Center 37 (6~68) winsize 63
801 10:00:57.919565 [CA 1] Center 37 (7~68) winsize 62
802 10:00:57.922583 [CA 2] Center 35 (4~66) winsize 63
803 10:00:57.925952 [CA 3] Center 35 (4~66) winsize 63
804 10:00:57.929410 [CA 4] Center 33 (3~64) winsize 62
805 10:00:57.932987 [CA 5] Center 33 (3~64) winsize 62
806 10:00:57.933430
807 10:00:57.936320 [CmdBusTrainingLP45] Vref(ca) range 1: 32
808 10:00:57.936866
809 10:00:57.940079 [CATrainingPosCal] consider 2 rank data
810 10:00:57.942825 u2DelayCellTimex100 = 270/100 ps
811 10:00:57.946710 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
812 10:00:57.949520 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 10:00:57.953403 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
814 10:00:57.959715 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
815 10:00:57.962961 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 10:00:57.966292 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 10:00:57.966724
818 10:00:57.970446 CA PerBit enable=1, Macro0, CA PI delay=33
819 10:00:57.970982
820 10:00:57.973383 [CBTSetCACLKResult] CA Dly = 33
821 10:00:57.973958 CS Dly: 5 (0~37)
822 10:00:57.974328
823 10:00:57.976636 ----->DramcWriteLeveling(PI) begin...
824 10:00:57.977251 ==
825 10:00:57.980082 Dram Type= 6, Freq= 0, CH_0, rank 0
826 10:00:57.984218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 10:00:57.987617 ==
828 10:00:57.988156 Write leveling (Byte 0): 29 => 29
829 10:00:57.991419 Write leveling (Byte 1): 29 => 29
830 10:00:57.995285 DramcWriteLeveling(PI) end<-----
831 10:00:57.995951
832 10:00:57.996373 ==
833 10:00:57.998763 Dram Type= 6, Freq= 0, CH_0, rank 0
834 10:00:58.002008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 10:00:58.002582 ==
836 10:00:58.005598 [Gating] SW mode calibration
837 10:00:58.012335 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 10:00:58.019601 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 10:00:58.023028 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 10:00:58.026223 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 10:00:58.029883 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
842 10:00:58.036326 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 10:00:58.039695 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 10:00:58.043100 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 10:00:58.049384 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 10:00:58.053311 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 10:00:58.056340 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 10:00:58.063441 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 10:00:58.066575 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 10:00:58.069699 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 10:00:58.073337 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 10:00:58.080005 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 10:00:58.083177 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 10:00:58.086952 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 10:00:58.093271 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 10:00:58.096651 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
857 10:00:58.100121 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
858 10:00:58.106755 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 10:00:58.110618 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 10:00:58.113139 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 10:00:58.120320 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 10:00:58.123660 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 10:00:58.126779 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 10:00:58.133874 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 10:00:58.137064 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 10:00:58.140394 0 9 12 | B1->B0 | 2b2b 3130 | 0 1 | (0 0) (0 0)
867 10:00:58.143464 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 10:00:58.150519 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 10:00:58.153996 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 10:00:58.156934 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 10:00:58.163700 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 10:00:58.167140 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
873 10:00:58.170768 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
874 10:00:58.177041 0 10 12 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
875 10:00:58.180764 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 10:00:58.183655 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 10:00:58.190790 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 10:00:58.193894 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 10:00:58.197416 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 10:00:58.204352 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 10:00:58.207128 0 11 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
882 10:00:58.210494 0 11 12 | B1->B0 | 3838 4242 | 0 1 | (1 1) (0 0)
883 10:00:58.213810 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 10:00:58.220503 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 10:00:58.224347 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 10:00:58.227571 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 10:00:58.234050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 10:00:58.237870 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 10:00:58.240964 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
890 10:00:58.247665 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
891 10:00:58.250624 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 10:00:58.254548 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 10:00:58.261312 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 10:00:58.264586 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 10:00:58.267553 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 10:00:58.271280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 10:00:58.277462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 10:00:58.280983 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 10:00:58.284328 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 10:00:58.291229 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 10:00:58.294459 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 10:00:58.297564 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 10:00:58.304454 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 10:00:58.307988 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 10:00:58.310951 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
906 10:00:58.318104 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
907 10:00:58.318535 Total UI for P1: 0, mck2ui 16
908 10:00:58.321364 best dqsien dly found for B0: ( 0, 14, 8)
909 10:00:58.324781 Total UI for P1: 0, mck2ui 16
910 10:00:58.327695 best dqsien dly found for B1: ( 0, 14, 10)
911 10:00:58.331306 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
912 10:00:58.338210 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
913 10:00:58.338646
914 10:00:58.341317 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
915 10:00:58.344928 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
916 10:00:58.348377 [Gating] SW calibration Done
917 10:00:58.348844 ==
918 10:00:58.351149 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:00:58.354708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:00:58.355134 ==
921 10:00:58.355469 RX Vref Scan: 0
922 10:00:58.355782
923 10:00:58.358039 RX Vref 0 -> 0, step: 1
924 10:00:58.358465
925 10:00:58.361446 RX Delay -130 -> 252, step: 16
926 10:00:58.364824 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
927 10:00:58.368260 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 10:00:58.374716 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 10:00:58.378318 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
930 10:00:58.381788 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
931 10:00:58.384710 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
932 10:00:58.388067 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
933 10:00:58.391968 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
934 10:00:58.398491 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
935 10:00:58.402160 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
936 10:00:58.405061 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
937 10:00:58.408302 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
938 10:00:58.411643 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
939 10:00:58.418311 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
940 10:00:58.422147 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 10:00:58.424877 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
942 10:00:58.425112 ==
943 10:00:58.428183 Dram Type= 6, Freq= 0, CH_0, rank 0
944 10:00:58.431652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 10:00:58.431953 ==
946 10:00:58.435217 DQS Delay:
947 10:00:58.435443 DQS0 = 0, DQS1 = 0
948 10:00:58.438613 DQM Delay:
949 10:00:58.438842 DQM0 = 84, DQM1 = 76
950 10:00:58.439023 DQ Delay:
951 10:00:58.441617 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
952 10:00:58.445061 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
953 10:00:58.448019 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
954 10:00:58.451553 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
955 10:00:58.451635
956 10:00:58.451700
957 10:00:58.451760 ==
958 10:00:58.455159 Dram Type= 6, Freq= 0, CH_0, rank 0
959 10:00:58.461609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 10:00:58.461695 ==
961 10:00:58.461761
962 10:00:58.461822
963 10:00:58.461880 TX Vref Scan disable
964 10:00:58.465552 == TX Byte 0 ==
965 10:00:58.468782 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
966 10:00:58.472218 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
967 10:00:58.475505 == TX Byte 1 ==
968 10:00:58.479053 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
969 10:00:58.482381 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
970 10:00:58.486011 ==
971 10:00:58.486093 Dram Type= 6, Freq= 0, CH_0, rank 0
972 10:00:58.492440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 10:00:58.492523 ==
974 10:00:58.504898 TX Vref=22, minBit 0, minWin=27, winSum=438
975 10:00:58.508172 TX Vref=24, minBit 0, minWin=27, winSum=443
976 10:00:58.511191 TX Vref=26, minBit 3, minWin=27, winSum=445
977 10:00:58.514614 TX Vref=28, minBit 3, minWin=27, winSum=448
978 10:00:58.518140 TX Vref=30, minBit 12, minWin=27, winSum=451
979 10:00:58.521766 TX Vref=32, minBit 12, minWin=27, winSum=452
980 10:00:58.528380 [TxChooseVref] Worse bit 12, Min win 27, Win sum 452, Final Vref 32
981 10:00:58.528463
982 10:00:58.531394 Final TX Range 1 Vref 32
983 10:00:58.531503
984 10:00:58.531597 ==
985 10:00:58.535169 Dram Type= 6, Freq= 0, CH_0, rank 0
986 10:00:58.538271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 10:00:58.538354 ==
988 10:00:58.538419
989 10:00:58.538479
990 10:00:58.541386 TX Vref Scan disable
991 10:00:58.545024 == TX Byte 0 ==
992 10:00:58.548564 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
993 10:00:58.551424 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
994 10:00:58.555004 == TX Byte 1 ==
995 10:00:58.558062 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
996 10:00:58.561557 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
997 10:00:58.561646
998 10:00:58.565101 [DATLAT]
999 10:00:58.565183 Freq=800, CH0 RK0
1000 10:00:58.565248
1001 10:00:58.568392 DATLAT Default: 0xa
1002 10:00:58.568474 0, 0xFFFF, sum = 0
1003 10:00:58.571798 1, 0xFFFF, sum = 0
1004 10:00:58.571910 2, 0xFFFF, sum = 0
1005 10:00:58.575143 3, 0xFFFF, sum = 0
1006 10:00:58.575226 4, 0xFFFF, sum = 0
1007 10:00:58.578632 5, 0xFFFF, sum = 0
1008 10:00:58.578716 6, 0xFFFF, sum = 0
1009 10:00:58.581718 7, 0xFFFF, sum = 0
1010 10:00:58.581802 8, 0xFFFF, sum = 0
1011 10:00:58.585374 9, 0x0, sum = 1
1012 10:00:58.585458 10, 0x0, sum = 2
1013 10:00:58.588959 11, 0x0, sum = 3
1014 10:00:58.589042 12, 0x0, sum = 4
1015 10:00:58.591866 best_step = 10
1016 10:00:58.591947
1017 10:00:58.592012 ==
1018 10:00:58.595411 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 10:00:58.598875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 10:00:58.598975 ==
1021 10:00:58.601806 RX Vref Scan: 1
1022 10:00:58.601951
1023 10:00:58.602016 Set Vref Range= 32 -> 127
1024 10:00:58.602078
1025 10:00:58.605209 RX Vref 32 -> 127, step: 1
1026 10:00:58.605291
1027 10:00:58.608354 RX Delay -111 -> 252, step: 8
1028 10:00:58.608521
1029 10:00:58.611827 Set Vref, RX VrefLevel [Byte0]: 32
1030 10:00:58.615345 [Byte1]: 32
1031 10:00:58.615430
1032 10:00:58.618933 Set Vref, RX VrefLevel [Byte0]: 33
1033 10:00:58.622702 [Byte1]: 33
1034 10:00:58.622785
1035 10:00:58.626137 Set Vref, RX VrefLevel [Byte0]: 34
1036 10:00:58.629746 [Byte1]: 34
1037 10:00:58.633088
1038 10:00:58.633182 Set Vref, RX VrefLevel [Byte0]: 35
1039 10:00:58.636113 [Byte1]: 35
1040 10:00:58.640298
1041 10:00:58.640410 Set Vref, RX VrefLevel [Byte0]: 36
1042 10:00:58.644505 [Byte1]: 36
1043 10:00:58.648685
1044 10:00:58.648875 Set Vref, RX VrefLevel [Byte0]: 37
1045 10:00:58.651877 [Byte1]: 37
1046 10:00:58.656232
1047 10:00:58.656365 Set Vref, RX VrefLevel [Byte0]: 38
1048 10:00:58.659915 [Byte1]: 38
1049 10:00:58.663659
1050 10:00:58.663812 Set Vref, RX VrefLevel [Byte0]: 39
1051 10:00:58.667140 [Byte1]: 39
1052 10:00:58.671805
1053 10:00:58.672041 Set Vref, RX VrefLevel [Byte0]: 40
1054 10:00:58.675286 [Byte1]: 40
1055 10:00:58.679278
1056 10:00:58.679518 Set Vref, RX VrefLevel [Byte0]: 41
1057 10:00:58.682924 [Byte1]: 41
1058 10:00:58.686638
1059 10:00:58.686949 Set Vref, RX VrefLevel [Byte0]: 42
1060 10:00:58.690099 [Byte1]: 42
1061 10:00:58.694399
1062 10:00:58.694695 Set Vref, RX VrefLevel [Byte0]: 43
1063 10:00:58.697941 [Byte1]: 43
1064 10:00:58.702437
1065 10:00:58.702815 Set Vref, RX VrefLevel [Byte0]: 44
1066 10:00:58.708889 [Byte1]: 44
1067 10:00:58.709638
1068 10:00:58.709970 Set Vref, RX VrefLevel [Byte0]: 45
1069 10:00:58.712984 [Byte1]: 45
1070 10:00:58.717326
1071 10:00:58.717708 Set Vref, RX VrefLevel [Byte0]: 46
1072 10:00:58.721054 [Byte1]: 46
1073 10:00:58.725065
1074 10:00:58.725570 Set Vref, RX VrefLevel [Byte0]: 47
1075 10:00:58.728376 [Byte1]: 47
1076 10:00:58.732737
1077 10:00:58.733155 Set Vref, RX VrefLevel [Byte0]: 48
1078 10:00:58.736061 [Byte1]: 48
1079 10:00:58.740106
1080 10:00:58.740525 Set Vref, RX VrefLevel [Byte0]: 49
1081 10:00:58.743923 [Byte1]: 49
1082 10:00:58.748093
1083 10:00:58.748509 Set Vref, RX VrefLevel [Byte0]: 50
1084 10:00:58.751241 [Byte1]: 50
1085 10:00:58.755357
1086 10:00:58.755774 Set Vref, RX VrefLevel [Byte0]: 51
1087 10:00:58.759006 [Byte1]: 51
1088 10:00:58.762920
1089 10:00:58.763345 Set Vref, RX VrefLevel [Byte0]: 52
1090 10:00:58.766363 [Byte1]: 52
1091 10:00:58.770968
1092 10:00:58.771395 Set Vref, RX VrefLevel [Byte0]: 53
1093 10:00:58.773851 [Byte1]: 53
1094 10:00:58.778456
1095 10:00:58.779006 Set Vref, RX VrefLevel [Byte0]: 54
1096 10:00:58.781884 [Byte1]: 54
1097 10:00:58.785755
1098 10:00:58.786210 Set Vref, RX VrefLevel [Byte0]: 55
1099 10:00:58.789277 [Byte1]: 55
1100 10:00:58.793879
1101 10:00:58.794419 Set Vref, RX VrefLevel [Byte0]: 56
1102 10:00:58.797207 [Byte1]: 56
1103 10:00:58.801273
1104 10:00:58.801826 Set Vref, RX VrefLevel [Byte0]: 57
1105 10:00:58.805102 [Byte1]: 57
1106 10:00:58.809444
1107 10:00:58.809859 Set Vref, RX VrefLevel [Byte0]: 58
1108 10:00:58.812276 [Byte1]: 58
1109 10:00:58.816956
1110 10:00:58.817395 Set Vref, RX VrefLevel [Byte0]: 59
1111 10:00:58.819711 [Byte1]: 59
1112 10:00:58.824554
1113 10:00:58.825096 Set Vref, RX VrefLevel [Byte0]: 60
1114 10:00:58.827410 [Byte1]: 60
1115 10:00:58.831914
1116 10:00:58.832208 Set Vref, RX VrefLevel [Byte0]: 61
1117 10:00:58.835422 [Byte1]: 61
1118 10:00:58.839707
1119 10:00:58.840097 Set Vref, RX VrefLevel [Byte0]: 62
1120 10:00:58.843176 [Byte1]: 62
1121 10:00:58.846942
1122 10:00:58.847249 Set Vref, RX VrefLevel [Byte0]: 63
1123 10:00:58.850434 [Byte1]: 63
1124 10:00:58.855145
1125 10:00:58.855538 Set Vref, RX VrefLevel [Byte0]: 64
1126 10:00:58.858723 [Byte1]: 64
1127 10:00:58.862844
1128 10:00:58.863322 Set Vref, RX VrefLevel [Byte0]: 65
1129 10:00:58.866008 [Byte1]: 65
1130 10:00:58.870316
1131 10:00:58.870736 Set Vref, RX VrefLevel [Byte0]: 66
1132 10:00:58.874202 [Byte1]: 66
1133 10:00:58.877724
1134 10:00:58.878252 Set Vref, RX VrefLevel [Byte0]: 67
1135 10:00:58.881152 [Byte1]: 67
1136 10:00:58.885712
1137 10:00:58.886129 Set Vref, RX VrefLevel [Byte0]: 68
1138 10:00:58.888955 [Byte1]: 68
1139 10:00:58.893484
1140 10:00:58.893899 Set Vref, RX VrefLevel [Byte0]: 69
1141 10:00:58.896360 [Byte1]: 69
1142 10:00:58.901086
1143 10:00:58.901602 Set Vref, RX VrefLevel [Byte0]: 70
1144 10:00:58.904660 [Byte1]: 70
1145 10:00:58.908978
1146 10:00:58.909496 Set Vref, RX VrefLevel [Byte0]: 71
1147 10:00:58.912304 [Byte1]: 71
1148 10:00:58.916535
1149 10:00:58.917118 Set Vref, RX VrefLevel [Byte0]: 72
1150 10:00:58.919347 [Byte1]: 72
1151 10:00:58.923901
1152 10:00:58.924356 Set Vref, RX VrefLevel [Byte0]: 73
1153 10:00:58.927280 [Byte1]: 73
1154 10:00:58.931450
1155 10:00:58.931879 Final RX Vref Byte 0 = 61 to rank0
1156 10:00:58.934888 Final RX Vref Byte 1 = 54 to rank0
1157 10:00:58.938056 Final RX Vref Byte 0 = 61 to rank1
1158 10:00:58.941399 Final RX Vref Byte 1 = 54 to rank1==
1159 10:00:58.945025 Dram Type= 6, Freq= 0, CH_0, rank 0
1160 10:00:58.948243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 10:00:58.951288 ==
1162 10:00:58.951513 DQS Delay:
1163 10:00:58.951691 DQS0 = 0, DQS1 = 0
1164 10:00:58.954786 DQM Delay:
1165 10:00:58.955010 DQM0 = 87, DQM1 = 78
1166 10:00:58.958136 DQ Delay:
1167 10:00:58.958316 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1168 10:00:58.961117 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1169 10:00:58.964720 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1170 10:00:58.968167 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1171 10:00:58.968296
1172 10:00:58.968398
1173 10:00:58.978519 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1174 10:00:58.981743 CH0 RK0: MR19=606, MR18=2C13
1175 10:00:58.988089 CH0_RK0: MR19=0x606, MR18=0x2C13, DQSOSC=398, MR23=63, INC=93, DEC=62
1176 10:00:58.988333
1177 10:00:58.991652 ----->DramcWriteLeveling(PI) begin...
1178 10:00:58.992077 ==
1179 10:00:58.995198 Dram Type= 6, Freq= 0, CH_0, rank 1
1180 10:00:58.998611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 10:00:58.999034 ==
1182 10:00:59.001740 Write leveling (Byte 0): 30 => 30
1183 10:00:59.005600 Write leveling (Byte 1): 29 => 29
1184 10:00:59.008745 DramcWriteLeveling(PI) end<-----
1185 10:00:59.009165
1186 10:00:59.009495 ==
1187 10:00:59.012230 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 10:00:59.015142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 10:00:59.015440 ==
1190 10:00:59.018861 [Gating] SW mode calibration
1191 10:00:59.025663 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1192 10:00:59.028607 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1193 10:00:59.035071 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1194 10:00:59.039050 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1195 10:00:59.042131 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 10:00:59.048603 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 10:00:59.052403 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 10:00:59.055509 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 10:00:59.062502 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 10:00:59.106274 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 10:00:59.106623 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 10:00:59.106704 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 10:00:59.106812 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 10:00:59.106892 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 10:00:59.107159 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 10:00:59.107249 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 10:00:59.107311 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 10:00:59.107386 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 10:00:59.107633 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1210 10:00:59.150550 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1211 10:00:59.150690 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 10:00:59.150757 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 10:00:59.151006 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 10:00:59.151071 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 10:00:59.151142 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 10:00:59.151202 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 10:00:59.151691 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 10:00:59.152244 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 10:00:59.152533 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1220 10:00:59.185700 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1221 10:00:59.186436 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 10:00:59.186845 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 10:00:59.187586 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 10:00:59.187951 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 10:00:59.188269 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1226 10:00:59.188574 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1227 10:00:59.188931 0 10 8 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (0 0)
1228 10:00:59.189789 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 10:00:59.193339 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 10:00:59.196502 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 10:00:59.200187 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 10:00:59.206435 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 10:00:59.210215 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 10:00:59.213783 0 11 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1235 10:00:59.220588 0 11 8 | B1->B0 | 2727 3d3d | 0 0 | (0 0) (0 0)
1236 10:00:59.223729 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1237 10:00:59.227087 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 10:00:59.233987 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 10:00:59.237425 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 10:00:59.240893 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 10:00:59.244884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 10:00:59.248544 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1243 10:00:59.255010 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1244 10:00:59.258448 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 10:00:59.261821 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 10:00:59.268962 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 10:00:59.272180 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 10:00:59.275477 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 10:00:59.278928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 10:00:59.285919 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 10:00:59.289498 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 10:00:59.292240 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 10:00:59.299127 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 10:00:59.302594 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 10:00:59.305723 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 10:00:59.312420 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 10:00:59.315879 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 10:00:59.319259 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 10:00:59.325881 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1260 10:00:59.325971 Total UI for P1: 0, mck2ui 16
1261 10:00:59.329297 best dqsien dly found for B0: ( 0, 14, 6)
1262 10:00:59.335962 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 10:00:59.339692 Total UI for P1: 0, mck2ui 16
1264 10:00:59.342786 best dqsien dly found for B1: ( 0, 14, 10)
1265 10:00:59.346619 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1266 10:00:59.349290 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1267 10:00:59.349382
1268 10:00:59.353082 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1269 10:00:59.356361 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1270 10:00:59.360150 [Gating] SW calibration Done
1271 10:00:59.360314 ==
1272 10:00:59.362801 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 10:00:59.366165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 10:00:59.366263 ==
1275 10:00:59.369500 RX Vref Scan: 0
1276 10:00:59.369582
1277 10:00:59.369647 RX Vref 0 -> 0, step: 1
1278 10:00:59.369708
1279 10:00:59.373509 RX Delay -130 -> 252, step: 16
1280 10:00:59.377120 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1281 10:00:59.383671 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1282 10:00:59.387126 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1283 10:00:59.390174 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1284 10:00:59.393669 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1285 10:00:59.396778 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1286 10:00:59.403861 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1287 10:00:59.406737 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1288 10:00:59.409954 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1289 10:00:59.413880 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1290 10:00:59.417015 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1291 10:00:59.423373 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1292 10:00:59.426854 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1293 10:00:59.430457 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1294 10:00:59.433495 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1295 10:00:59.436962 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1296 10:00:59.437387 ==
1297 10:00:59.440346 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 10:00:59.447242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 10:00:59.447694 ==
1300 10:00:59.448155 DQS Delay:
1301 10:00:59.450322 DQS0 = 0, DQS1 = 0
1302 10:00:59.450754 DQM Delay:
1303 10:00:59.453499 DQM0 = 85, DQM1 = 77
1304 10:00:59.453929 DQ Delay:
1305 10:00:59.456751 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1306 10:00:59.460807 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1307 10:00:59.464081 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1308 10:00:59.466966 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1309 10:00:59.467433
1310 10:00:59.467875
1311 10:00:59.468293 ==
1312 10:00:59.470304 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 10:00:59.473529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 10:00:59.473974 ==
1315 10:00:59.474427
1316 10:00:59.474879
1317 10:00:59.477251 TX Vref Scan disable
1318 10:00:59.477684 == TX Byte 0 ==
1319 10:00:59.483812 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1320 10:00:59.487237 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1321 10:00:59.487678 == TX Byte 1 ==
1322 10:00:59.494208 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1323 10:00:59.497382 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1324 10:00:59.497811 ==
1325 10:00:59.500542 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 10:00:59.504231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 10:00:59.504659 ==
1328 10:00:59.517956 TX Vref=22, minBit 2, minWin=27, winSum=442
1329 10:00:59.520992 TX Vref=24, minBit 3, minWin=27, winSum=448
1330 10:00:59.524265 TX Vref=26, minBit 2, minWin=27, winSum=447
1331 10:00:59.527816 TX Vref=28, minBit 0, minWin=28, winSum=454
1332 10:00:59.531258 TX Vref=30, minBit 3, minWin=28, winSum=454
1333 10:00:59.534181 TX Vref=32, minBit 2, minWin=27, winSum=449
1334 10:00:59.541069 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
1335 10:00:59.541373
1336 10:00:59.544662 Final TX Range 1 Vref 28
1337 10:00:59.544995
1338 10:00:59.545233 ==
1339 10:00:59.547955 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 10:00:59.551367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 10:00:59.551669 ==
1342 10:00:59.551906
1343 10:00:59.552127
1344 10:00:59.554635 TX Vref Scan disable
1345 10:00:59.558157 == TX Byte 0 ==
1346 10:00:59.561230 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1347 10:00:59.564631 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1348 10:00:59.568338 == TX Byte 1 ==
1349 10:00:59.571400 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1350 10:00:59.574687 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1351 10:00:59.574986
1352 10:00:59.578099 [DATLAT]
1353 10:00:59.578394 Freq=800, CH0 RK1
1354 10:00:59.578631
1355 10:00:59.581407 DATLAT Default: 0xa
1356 10:00:59.581632 0, 0xFFFF, sum = 0
1357 10:00:59.584951 1, 0xFFFF, sum = 0
1358 10:00:59.585181 2, 0xFFFF, sum = 0
1359 10:00:59.588241 3, 0xFFFF, sum = 0
1360 10:00:59.588423 4, 0xFFFF, sum = 0
1361 10:00:59.591222 5, 0xFFFF, sum = 0
1362 10:00:59.591375 6, 0xFFFF, sum = 0
1363 10:00:59.594596 7, 0xFFFF, sum = 0
1364 10:00:59.594754 8, 0xFFFF, sum = 0
1365 10:00:59.598183 9, 0x0, sum = 1
1366 10:00:59.598315 10, 0x0, sum = 2
1367 10:00:59.601675 11, 0x0, sum = 3
1368 10:00:59.601790 12, 0x0, sum = 4
1369 10:00:59.604484 best_step = 10
1370 10:00:59.604596
1371 10:00:59.604693 ==
1372 10:00:59.608150 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 10:00:59.611267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 10:00:59.611358 ==
1375 10:00:59.611430 RX Vref Scan: 0
1376 10:00:59.614602
1377 10:00:59.614694 RX Vref 0 -> 0, step: 1
1378 10:00:59.614765
1379 10:00:59.617949 RX Delay -95 -> 252, step: 8
1380 10:00:59.621258 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1381 10:00:59.628403 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1382 10:00:59.631688 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1383 10:00:59.635235 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1384 10:00:59.638857 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1385 10:00:59.641835 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1386 10:00:59.645376 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1387 10:00:59.651915 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1388 10:00:59.655123 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1389 10:00:59.658698 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1390 10:00:59.661786 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1391 10:00:59.665349 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1392 10:00:59.672466 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1393 10:00:59.675500 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1394 10:00:59.679054 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1395 10:00:59.682338 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1396 10:00:59.682502 ==
1397 10:00:59.685454 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 10:00:59.692282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 10:00:59.692478 ==
1400 10:00:59.692633 DQS Delay:
1401 10:00:59.692770 DQS0 = 0, DQS1 = 0
1402 10:00:59.695557 DQM Delay:
1403 10:00:59.695671 DQM0 = 87, DQM1 = 77
1404 10:00:59.699186 DQ Delay:
1405 10:00:59.702685 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1406 10:00:59.702888 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1407 10:00:59.705703 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1408 10:00:59.709270 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1409 10:00:59.712528
1410 10:00:59.712759
1411 10:00:59.719199 [DQSOSCAuto] RK1, (LSB)MR18= 0x341d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1412 10:00:59.722369 CH0 RK1: MR19=606, MR18=341D
1413 10:00:59.729470 CH0_RK1: MR19=0x606, MR18=0x341D, DQSOSC=396, MR23=63, INC=94, DEC=62
1414 10:00:59.729707 [RxdqsGatingPostProcess] freq 800
1415 10:00:59.735872 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1416 10:00:59.739268 Pre-setting of DQS Precalculation
1417 10:00:59.742686 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1418 10:00:59.746356 ==
1419 10:00:59.749209 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 10:00:59.752805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 10:00:59.753128 ==
1422 10:00:59.756605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 10:00:59.762823 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 10:00:59.772656 [CA 0] Center 36 (6~66) winsize 61
1425 10:00:59.775768 [CA 1] Center 36 (6~66) winsize 61
1426 10:00:59.779412 [CA 2] Center 35 (5~65) winsize 61
1427 10:00:59.782979 [CA 3] Center 33 (3~64) winsize 62
1428 10:00:59.785547 [CA 4] Center 34 (4~65) winsize 62
1429 10:00:59.788951 [CA 5] Center 33 (3~64) winsize 62
1430 10:00:59.789186
1431 10:00:59.792182 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1432 10:00:59.792417
1433 10:00:59.796001 [CATrainingPosCal] consider 1 rank data
1434 10:00:59.799504 u2DelayCellTimex100 = 270/100 ps
1435 10:00:59.802882 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1436 10:00:59.805986 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1437 10:00:59.812501 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1438 10:00:59.816044 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1439 10:00:59.819510 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1440 10:00:59.822861 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1441 10:00:59.823271
1442 10:00:59.826370 CA PerBit enable=1, Macro0, CA PI delay=33
1443 10:00:59.826780
1444 10:00:59.829905 [CBTSetCACLKResult] CA Dly = 33
1445 10:00:59.830312 CS Dly: 4 (0~35)
1446 10:00:59.830636 ==
1447 10:00:59.832834 Dram Type= 6, Freq= 0, CH_1, rank 1
1448 10:00:59.839986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 10:00:59.840411 ==
1450 10:00:59.843635 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 10:00:59.849640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 10:00:59.859131 [CA 0] Center 36 (6~66) winsize 61
1453 10:00:59.862409 [CA 1] Center 36 (6~66) winsize 61
1454 10:00:59.865793 [CA 2] Center 33 (3~64) winsize 62
1455 10:00:59.868911 [CA 3] Center 33 (3~64) winsize 62
1456 10:00:59.872104 [CA 4] Center 34 (4~65) winsize 62
1457 10:00:59.875481 [CA 5] Center 33 (3~64) winsize 62
1458 10:00:59.875966
1459 10:00:59.878925 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1460 10:00:59.879413
1461 10:00:59.882289 [CATrainingPosCal] consider 2 rank data
1462 10:00:59.885960 u2DelayCellTimex100 = 270/100 ps
1463 10:00:59.889917 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1464 10:00:59.892658 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1465 10:00:59.896445 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1466 10:00:59.900017 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1467 10:00:59.903621 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1468 10:00:59.907105 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1469 10:00:59.907738
1470 10:00:59.910920 CA PerBit enable=1, Macro0, CA PI delay=33
1471 10:00:59.911429
1472 10:00:59.914323 [CBTSetCACLKResult] CA Dly = 33
1473 10:00:59.918213 CS Dly: 4 (0~36)
1474 10:00:59.918753
1475 10:00:59.922084 ----->DramcWriteLeveling(PI) begin...
1476 10:00:59.922797 ==
1477 10:00:59.925341 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 10:00:59.929201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 10:00:59.929682 ==
1480 10:00:59.932721 Write leveling (Byte 0): 29 => 29
1481 10:00:59.933238 Write leveling (Byte 1): 29 => 29
1482 10:00:59.936103 DramcWriteLeveling(PI) end<-----
1483 10:00:59.936549
1484 10:00:59.937005 ==
1485 10:00:59.939552 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 10:00:59.946614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 10:00:59.947198 ==
1488 10:00:59.947551 [Gating] SW mode calibration
1489 10:00:59.956828 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1490 10:00:59.959697 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1491 10:00:59.963563 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1492 10:00:59.969579 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1493 10:00:59.973414 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1494 10:00:59.976876 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 10:00:59.984034 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 10:00:59.987343 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 10:00:59.990571 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 10:00:59.996981 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 10:01:00.000546 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 10:01:00.003841 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 10:01:00.007359 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 10:01:00.013921 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1503 10:01:00.016939 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1504 10:01:00.020205 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 10:01:00.027204 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1506 10:01:00.030597 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 10:01:00.033836 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 10:01:00.040599 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1509 10:01:00.043674 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1510 10:01:00.047576 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 10:01:00.054598 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 10:01:00.057595 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 10:01:00.061380 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 10:01:00.063977 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 10:01:00.070857 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 10:01:00.074213 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 10:01:00.078131 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 10:01:00.084378 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1519 10:01:00.087929 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 10:01:00.091587 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 10:01:00.097760 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 10:01:00.100927 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 10:01:00.104435 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 10:01:00.111219 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 10:01:00.114848 0 10 8 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (0 1)
1526 10:01:00.118241 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 10:01:00.120978 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 10:01:00.127769 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 10:01:00.131449 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 10:01:00.134908 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 10:01:00.141473 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 10:01:00.145201 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 10:01:00.147776 0 11 8 | B1->B0 | 3535 3131 | 0 1 | (0 0) (0 0)
1534 10:01:00.155189 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 10:01:00.158590 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 10:01:00.161867 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 10:01:00.168379 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 10:01:00.171820 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 10:01:00.175343 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 10:01:00.178363 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 10:01:00.185466 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1542 10:01:00.188416 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1543 10:01:00.192155 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 10:01:00.199130 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 10:01:00.201894 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 10:01:00.205581 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 10:01:00.212245 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 10:01:00.215773 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 10:01:00.218626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 10:01:00.225426 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 10:01:00.229254 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 10:01:00.232181 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 10:01:00.235812 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 10:01:00.242391 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 10:01:00.245382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 10:01:00.249140 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1557 10:01:00.255927 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1558 10:01:00.259385 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 10:01:00.262899 Total UI for P1: 0, mck2ui 16
1560 10:01:00.265568 best dqsien dly found for B0: ( 0, 14, 6)
1561 10:01:00.269383 Total UI for P1: 0, mck2ui 16
1562 10:01:00.272445 best dqsien dly found for B1: ( 0, 14, 8)
1563 10:01:00.276265 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1564 10:01:00.279802 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1565 10:01:00.280358
1566 10:01:00.282298 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1567 10:01:00.286050 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1568 10:01:00.289413 [Gating] SW calibration Done
1569 10:01:00.289991 ==
1570 10:01:00.292642 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 10:01:00.296474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 10:01:00.297086 ==
1573 10:01:00.299871 RX Vref Scan: 0
1574 10:01:00.300426
1575 10:01:00.300842 RX Vref 0 -> 0, step: 1
1576 10:01:00.301188
1577 10:01:00.302567 RX Delay -130 -> 252, step: 16
1578 10:01:00.309605 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1579 10:01:00.312965 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1580 10:01:00.316496 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1581 10:01:00.319618 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1582 10:01:00.323128 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1583 10:01:00.326478 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1584 10:01:00.333192 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1585 10:01:00.336476 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1586 10:01:00.339974 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1587 10:01:00.343098 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1588 10:01:00.346677 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1589 10:01:00.353369 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1590 10:01:00.357345 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1591 10:01:00.360230 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1592 10:01:00.363389 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1593 10:01:00.367021 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1594 10:01:00.367578 ==
1595 10:01:00.370095 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 10:01:00.377092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 10:01:00.377619 ==
1598 10:01:00.377982 DQS Delay:
1599 10:01:00.379969 DQS0 = 0, DQS1 = 0
1600 10:01:00.380425 DQM Delay:
1601 10:01:00.380858 DQM0 = 82, DQM1 = 74
1602 10:01:00.383306 DQ Delay:
1603 10:01:00.387083 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1604 10:01:00.390527 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1605 10:01:00.394084 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1606 10:01:00.397325 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1607 10:01:00.397893
1608 10:01:00.398258
1609 10:01:00.398594 ==
1610 10:01:00.400716 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 10:01:00.403436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 10:01:00.403903 ==
1613 10:01:00.404264
1614 10:01:00.404621
1615 10:01:00.407379 TX Vref Scan disable
1616 10:01:00.407943 == TX Byte 0 ==
1617 10:01:00.413905 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1618 10:01:00.417333 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1619 10:01:00.417790 == TX Byte 1 ==
1620 10:01:00.423849 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1621 10:01:00.427352 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1622 10:01:00.427885 ==
1623 10:01:00.430772 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 10:01:00.433778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 10:01:00.434242 ==
1626 10:01:00.447331 TX Vref=22, minBit 0, minWin=27, winSum=439
1627 10:01:00.451238 TX Vref=24, minBit 11, minWin=26, winSum=438
1628 10:01:00.454323 TX Vref=26, minBit 0, minWin=27, winSum=443
1629 10:01:00.457708 TX Vref=28, minBit 4, minWin=27, winSum=448
1630 10:01:00.460655 TX Vref=30, minBit 4, minWin=27, winSum=450
1631 10:01:00.463955 TX Vref=32, minBit 0, minWin=28, winSum=451
1632 10:01:00.470789 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1633 10:01:00.471313
1634 10:01:00.473965 Final TX Range 1 Vref 32
1635 10:01:00.474387
1636 10:01:00.474718 ==
1637 10:01:00.477086 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 10:01:00.481196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 10:01:00.481608 ==
1640 10:01:00.481944
1641 10:01:00.482248
1642 10:01:00.484618 TX Vref Scan disable
1643 10:01:00.488036 == TX Byte 0 ==
1644 10:01:00.491827 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1645 10:01:00.494681 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1646 10:01:00.498129 == TX Byte 1 ==
1647 10:01:00.501359 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1648 10:01:00.504617 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1649 10:01:00.505161
1650 10:01:00.508215 [DATLAT]
1651 10:01:00.508747 Freq=800, CH1 RK0
1652 10:01:00.509089
1653 10:01:00.511335 DATLAT Default: 0xa
1654 10:01:00.511835 0, 0xFFFF, sum = 0
1655 10:01:00.514752 1, 0xFFFF, sum = 0
1656 10:01:00.515246 2, 0xFFFF, sum = 0
1657 10:01:00.518185 3, 0xFFFF, sum = 0
1658 10:01:00.518607 4, 0xFFFF, sum = 0
1659 10:01:00.521836 5, 0xFFFF, sum = 0
1660 10:01:00.522256 6, 0xFFFF, sum = 0
1661 10:01:00.524735 7, 0xFFFF, sum = 0
1662 10:01:00.525166 8, 0xFFFF, sum = 0
1663 10:01:00.528612 9, 0x0, sum = 1
1664 10:01:00.529080 10, 0x0, sum = 2
1665 10:01:00.531690 11, 0x0, sum = 3
1666 10:01:00.532125 12, 0x0, sum = 4
1667 10:01:00.532456 best_step = 10
1668 10:01:00.532821
1669 10:01:00.535035 ==
1670 10:01:00.538430 Dram Type= 6, Freq= 0, CH_1, rank 0
1671 10:01:00.541835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1672 10:01:00.542261 ==
1673 10:01:00.542651 RX Vref Scan: 1
1674 10:01:00.542986
1675 10:01:00.545233 Set Vref Range= 32 -> 127
1676 10:01:00.545664
1677 10:01:00.550001 RX Vref 32 -> 127, step: 1
1678 10:01:00.550670
1679 10:01:00.551756 RX Delay -111 -> 252, step: 8
1680 10:01:00.552179
1681 10:01:00.555443 Set Vref, RX VrefLevel [Byte0]: 32
1682 10:01:00.558988 [Byte1]: 32
1683 10:01:00.559568
1684 10:01:00.561849 Set Vref, RX VrefLevel [Byte0]: 33
1685 10:01:00.565447 [Byte1]: 33
1686 10:01:00.565876
1687 10:01:00.568242 Set Vref, RX VrefLevel [Byte0]: 34
1688 10:01:00.572020 [Byte1]: 34
1689 10:01:00.575248
1690 10:01:00.575798 Set Vref, RX VrefLevel [Byte0]: 35
1691 10:01:00.578654 [Byte1]: 35
1692 10:01:00.583003
1693 10:01:00.583575 Set Vref, RX VrefLevel [Byte0]: 36
1694 10:01:00.586112 [Byte1]: 36
1695 10:01:00.590623
1696 10:01:00.591115 Set Vref, RX VrefLevel [Byte0]: 37
1697 10:01:00.593989 [Byte1]: 37
1698 10:01:00.598094
1699 10:01:00.598578 Set Vref, RX VrefLevel [Byte0]: 38
1700 10:01:00.601674 [Byte1]: 38
1701 10:01:00.606498
1702 10:01:00.606904 Set Vref, RX VrefLevel [Byte0]: 39
1703 10:01:00.609154 [Byte1]: 39
1704 10:01:00.613357
1705 10:01:00.613768 Set Vref, RX VrefLevel [Byte0]: 40
1706 10:01:00.616729 [Byte1]: 40
1707 10:01:00.621561
1708 10:01:00.621973 Set Vref, RX VrefLevel [Byte0]: 41
1709 10:01:00.624496 [Byte1]: 41
1710 10:01:00.628586
1711 10:01:00.629012 Set Vref, RX VrefLevel [Byte0]: 42
1712 10:01:00.632080 [Byte1]: 42
1713 10:01:00.636495
1714 10:01:00.636954 Set Vref, RX VrefLevel [Byte0]: 43
1715 10:01:00.639696 [Byte1]: 43
1716 10:01:00.644114
1717 10:01:00.644526 Set Vref, RX VrefLevel [Byte0]: 44
1718 10:01:00.647198 [Byte1]: 44
1719 10:01:00.651623
1720 10:01:00.652038 Set Vref, RX VrefLevel [Byte0]: 45
1721 10:01:00.654996 [Byte1]: 45
1722 10:01:00.659509
1723 10:01:00.659923 Set Vref, RX VrefLevel [Byte0]: 46
1724 10:01:00.662977 [Byte1]: 46
1725 10:01:00.667313
1726 10:01:00.667769 Set Vref, RX VrefLevel [Byte0]: 47
1727 10:01:00.670392 [Byte1]: 47
1728 10:01:00.674983
1729 10:01:00.675400 Set Vref, RX VrefLevel [Byte0]: 48
1730 10:01:00.677786 [Byte1]: 48
1731 10:01:00.682262
1732 10:01:00.682678 Set Vref, RX VrefLevel [Byte0]: 49
1733 10:01:00.685787 [Byte1]: 49
1734 10:01:00.690116
1735 10:01:00.690530 Set Vref, RX VrefLevel [Byte0]: 50
1736 10:01:00.693602 [Byte1]: 50
1737 10:01:00.697969
1738 10:01:00.698381 Set Vref, RX VrefLevel [Byte0]: 51
1739 10:01:00.701198 [Byte1]: 51
1740 10:01:00.705284
1741 10:01:00.705802 Set Vref, RX VrefLevel [Byte0]: 52
1742 10:01:00.709220 [Byte1]: 52
1743 10:01:00.713271
1744 10:01:00.713720 Set Vref, RX VrefLevel [Byte0]: 53
1745 10:01:00.716875 [Byte1]: 53
1746 10:01:00.720725
1747 10:01:00.721304 Set Vref, RX VrefLevel [Byte0]: 54
1748 10:01:00.723709 [Byte1]: 54
1749 10:01:00.728447
1750 10:01:00.728956 Set Vref, RX VrefLevel [Byte0]: 55
1751 10:01:00.731957 [Byte1]: 55
1752 10:01:00.736024
1753 10:01:00.736453 Set Vref, RX VrefLevel [Byte0]: 56
1754 10:01:00.739070 [Byte1]: 56
1755 10:01:00.743472
1756 10:01:00.743901 Set Vref, RX VrefLevel [Byte0]: 57
1757 10:01:00.746964 [Byte1]: 57
1758 10:01:00.751086
1759 10:01:00.751514 Set Vref, RX VrefLevel [Byte0]: 58
1760 10:01:00.754550 [Byte1]: 58
1761 10:01:00.758682
1762 10:01:00.759141 Set Vref, RX VrefLevel [Byte0]: 59
1763 10:01:00.762135 [Byte1]: 59
1764 10:01:00.766580
1765 10:01:00.767001 Set Vref, RX VrefLevel [Byte0]: 60
1766 10:01:00.770015 [Byte1]: 60
1767 10:01:00.774464
1768 10:01:00.775053 Set Vref, RX VrefLevel [Byte0]: 61
1769 10:01:00.777169 [Byte1]: 61
1770 10:01:00.782057
1771 10:01:00.782560 Set Vref, RX VrefLevel [Byte0]: 62
1772 10:01:00.785451 [Byte1]: 62
1773 10:01:00.789368
1774 10:01:00.789918 Set Vref, RX VrefLevel [Byte0]: 63
1775 10:01:00.792657 [Byte1]: 63
1776 10:01:00.797219
1777 10:01:00.797657 Set Vref, RX VrefLevel [Byte0]: 64
1778 10:01:00.800093 [Byte1]: 64
1779 10:01:00.804521
1780 10:01:00.805037 Set Vref, RX VrefLevel [Byte0]: 65
1781 10:01:00.807985 [Byte1]: 65
1782 10:01:00.812501
1783 10:01:00.812989 Set Vref, RX VrefLevel [Byte0]: 66
1784 10:01:00.815561 [Byte1]: 66
1785 10:01:00.819987
1786 10:01:00.820409 Set Vref, RX VrefLevel [Byte0]: 67
1787 10:01:00.823452 [Byte1]: 67
1788 10:01:00.827480
1789 10:01:00.827907 Set Vref, RX VrefLevel [Byte0]: 68
1790 10:01:00.830990 [Byte1]: 68
1791 10:01:00.835589
1792 10:01:00.836003 Set Vref, RX VrefLevel [Byte0]: 69
1793 10:01:00.838768 [Byte1]: 69
1794 10:01:00.843433
1795 10:01:00.843846 Set Vref, RX VrefLevel [Byte0]: 70
1796 10:01:00.846276 [Byte1]: 70
1797 10:01:00.850897
1798 10:01:00.851329 Set Vref, RX VrefLevel [Byte0]: 71
1799 10:01:00.853916 [Byte1]: 71
1800 10:01:00.858307
1801 10:01:00.858718 Set Vref, RX VrefLevel [Byte0]: 72
1802 10:01:00.861672 [Byte1]: 72
1803 10:01:00.865985
1804 10:01:00.866400 Set Vref, RX VrefLevel [Byte0]: 73
1805 10:01:00.869229 [Byte1]: 73
1806 10:01:00.873062
1807 10:01:00.873145 Set Vref, RX VrefLevel [Byte0]: 74
1808 10:01:00.876353 [Byte1]: 74
1809 10:01:00.881087
1810 10:01:00.881167 Set Vref, RX VrefLevel [Byte0]: 75
1811 10:01:00.884143 [Byte1]: 75
1812 10:01:00.888333
1813 10:01:00.888413 Set Vref, RX VrefLevel [Byte0]: 76
1814 10:01:00.891823 [Byte1]: 76
1815 10:01:00.896026
1816 10:01:00.896106 Set Vref, RX VrefLevel [Byte0]: 77
1817 10:01:00.899480 [Byte1]: 77
1818 10:01:00.904090
1819 10:01:00.904170 Set Vref, RX VrefLevel [Byte0]: 78
1820 10:01:00.906941 [Byte1]: 78
1821 10:01:00.911294
1822 10:01:00.911374 Set Vref, RX VrefLevel [Byte0]: 79
1823 10:01:00.914724 [Byte1]: 79
1824 10:01:00.919140
1825 10:01:00.919221 Set Vref, RX VrefLevel [Byte0]: 80
1826 10:01:00.922459 [Byte1]: 80
1827 10:01:00.926882
1828 10:01:00.926968 Final RX Vref Byte 0 = 56 to rank0
1829 10:01:00.929942 Final RX Vref Byte 1 = 57 to rank0
1830 10:01:00.933351 Final RX Vref Byte 0 = 56 to rank1
1831 10:01:00.936980 Final RX Vref Byte 1 = 57 to rank1==
1832 10:01:00.940434 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 10:01:00.944069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 10:01:00.946927 ==
1835 10:01:00.947008 DQS Delay:
1836 10:01:00.947073 DQS0 = 0, DQS1 = 0
1837 10:01:00.950468 DQM Delay:
1838 10:01:00.950548 DQM0 = 83, DQM1 = 74
1839 10:01:00.954052 DQ Delay:
1840 10:01:00.954133 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1841 10:01:00.957417 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1842 10:01:00.960295 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1843 10:01:00.964002 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1844 10:01:00.964083
1845 10:01:00.964147
1846 10:01:00.973558 [DQSOSCAuto] RK0, (LSB)MR18= 0x28fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
1847 10:01:00.976641 CH1 RK0: MR19=605, MR18=28FC
1848 10:01:00.983394 CH1_RK0: MR19=0x605, MR18=0x28FC, DQSOSC=399, MR23=63, INC=92, DEC=61
1849 10:01:00.983517
1850 10:01:00.987160 ----->DramcWriteLeveling(PI) begin...
1851 10:01:00.987242 ==
1852 10:01:00.990773 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 10:01:00.993450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 10:01:00.993532 ==
1855 10:01:00.997200 Write leveling (Byte 0): 27 => 27
1856 10:01:01.000266 Write leveling (Byte 1): 29 => 29
1857 10:01:01.003793 DramcWriteLeveling(PI) end<-----
1858 10:01:01.003874
1859 10:01:01.003939 ==
1860 10:01:01.006886 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 10:01:01.010045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 10:01:01.010127 ==
1863 10:01:01.013354 [Gating] SW mode calibration
1864 10:01:01.020198 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 10:01:01.026974 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 10:01:01.030134 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1867 10:01:01.033534 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1868 10:01:01.040517 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 10:01:01.043426 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 10:01:01.046949 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 10:01:01.050651 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 10:01:01.056967 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 10:01:01.060484 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 10:01:01.063603 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 10:01:01.070826 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 10:01:01.074286 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 10:01:01.077152 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 10:01:01.084167 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1879 10:01:01.087856 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 10:01:01.090561 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 10:01:01.097454 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 10:01:01.100992 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1883 10:01:01.104427 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1884 10:01:01.107632 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1885 10:01:01.114479 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 10:01:01.117932 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 10:01:01.121004 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 10:01:01.127834 0 8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1889 10:01:01.130980 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 10:01:01.134708 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 10:01:01.141443 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1892 10:01:01.144527 0 9 8 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
1893 10:01:01.147899 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 10:01:01.154846 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 10:01:01.157762 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1896 10:01:01.161715 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 10:01:01.165051 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 10:01:01.171445 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1899 10:01:01.174841 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (1 1)
1900 10:01:01.178388 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 10:01:01.185386 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 10:01:01.188735 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 10:01:01.191836 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 10:01:01.198725 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 10:01:01.202088 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 10:01:01.205054 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 10:01:01.208375 0 11 4 | B1->B0 | 2e2e 3a3a | 1 0 | (0 0) (0 0)
1908 10:01:01.215292 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1909 10:01:01.218723 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 10:01:01.222001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 10:01:01.228969 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 10:01:01.232110 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 10:01:01.235711 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 10:01:01.242066 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1915 10:01:01.245504 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1916 10:01:01.248963 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1917 10:01:01.255538 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 10:01:01.258994 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 10:01:01.262691 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 10:01:01.265511 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 10:01:01.272402 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 10:01:01.276025 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 10:01:01.279539 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 10:01:01.285857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 10:01:01.289530 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 10:01:01.293155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 10:01:01.299606 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 10:01:01.302586 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 10:01:01.306012 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 10:01:01.313008 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1931 10:01:01.316375 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1932 10:01:01.319449 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 10:01:01.322713 Total UI for P1: 0, mck2ui 16
1934 10:01:01.326093 best dqsien dly found for B0: ( 0, 14, 2)
1935 10:01:01.329999 Total UI for P1: 0, mck2ui 16
1936 10:01:01.332939 best dqsien dly found for B1: ( 0, 14, 4)
1937 10:01:01.336707 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1938 10:01:01.339862 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1939 10:01:01.339943
1940 10:01:01.342875 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1941 10:01:01.346356 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1942 10:01:01.350083 [Gating] SW calibration Done
1943 10:01:01.350164 ==
1944 10:01:01.353318 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 10:01:01.356365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 10:01:01.356445 ==
1947 10:01:01.360212 RX Vref Scan: 0
1948 10:01:01.360292
1949 10:01:01.363106 RX Vref 0 -> 0, step: 1
1950 10:01:01.363186
1951 10:01:01.363250 RX Delay -130 -> 252, step: 16
1952 10:01:01.369816 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1953 10:01:01.373158 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1954 10:01:01.376765 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1955 10:01:01.379910 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1956 10:01:01.383224 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1957 10:01:01.390187 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1958 10:01:01.393599 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1959 10:01:01.397216 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1960 10:01:01.400222 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1961 10:01:01.403616 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1962 10:01:01.407318 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1963 10:01:01.413655 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1964 10:01:01.417224 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1965 10:01:01.420535 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1966 10:01:01.424007 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1967 10:01:01.427595 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1968 10:01:01.431044 ==
1969 10:01:01.433975 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 10:01:01.437590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 10:01:01.437672 ==
1972 10:01:01.437736 DQS Delay:
1973 10:01:01.440961 DQS0 = 0, DQS1 = 0
1974 10:01:01.441041 DQM Delay:
1975 10:01:01.444044 DQM0 = 80, DQM1 = 78
1976 10:01:01.444124 DQ Delay:
1977 10:01:01.447684 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1978 10:01:01.451182 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1979 10:01:01.454141 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1980 10:01:01.457372 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1981 10:01:01.457452
1982 10:01:01.457516
1983 10:01:01.457575 ==
1984 10:01:01.461125 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 10:01:01.464200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 10:01:01.464281 ==
1987 10:01:01.464344
1988 10:01:01.464403
1989 10:01:01.467767 TX Vref Scan disable
1990 10:01:01.467848 == TX Byte 0 ==
1991 10:01:01.474357 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1992 10:01:01.477630 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1993 10:01:01.477711 == TX Byte 1 ==
1994 10:01:01.484833 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1995 10:01:01.487648 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1996 10:01:01.487729 ==
1997 10:01:01.491121 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 10:01:01.494773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 10:01:01.494855 ==
2000 10:01:01.508153 TX Vref=22, minBit 0, minWin=27, winSum=443
2001 10:01:01.511631 TX Vref=24, minBit 1, minWin=27, winSum=445
2002 10:01:01.515361 TX Vref=26, minBit 11, minWin=27, winSum=447
2003 10:01:01.518851 TX Vref=28, minBit 0, minWin=28, winSum=454
2004 10:01:01.521875 TX Vref=30, minBit 0, minWin=28, winSum=451
2005 10:01:01.525039 TX Vref=32, minBit 0, minWin=28, winSum=454
2006 10:01:01.531740 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
2007 10:01:01.531823
2008 10:01:01.535259 Final TX Range 1 Vref 28
2009 10:01:01.535341
2010 10:01:01.535404 ==
2011 10:01:01.538299 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 10:01:01.541664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 10:01:01.541745 ==
2014 10:01:01.541808
2015 10:01:01.541870
2016 10:01:01.545060 TX Vref Scan disable
2017 10:01:01.548509 == TX Byte 0 ==
2018 10:01:01.552054 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 10:01:01.555490 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 10:01:01.558854 == TX Byte 1 ==
2021 10:01:01.561769 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2022 10:01:01.565523 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2023 10:01:01.565604
2024 10:01:01.568767 [DATLAT]
2025 10:01:01.568847 Freq=800, CH1 RK1
2026 10:01:01.568910
2027 10:01:01.571892 DATLAT Default: 0xa
2028 10:01:01.571974 0, 0xFFFF, sum = 0
2029 10:01:01.575238 1, 0xFFFF, sum = 0
2030 10:01:01.575319 2, 0xFFFF, sum = 0
2031 10:01:01.578983 3, 0xFFFF, sum = 0
2032 10:01:01.579064 4, 0xFFFF, sum = 0
2033 10:01:01.582044 5, 0xFFFF, sum = 0
2034 10:01:01.582126 6, 0xFFFF, sum = 0
2035 10:01:01.585401 7, 0xFFFF, sum = 0
2036 10:01:01.585483 8, 0xFFFF, sum = 0
2037 10:01:01.588986 9, 0x0, sum = 1
2038 10:01:01.589068 10, 0x0, sum = 2
2039 10:01:01.592169 11, 0x0, sum = 3
2040 10:01:01.592251 12, 0x0, sum = 4
2041 10:01:01.596110 best_step = 10
2042 10:01:01.596268
2043 10:01:01.596363 ==
2044 10:01:01.599291 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 10:01:01.602294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 10:01:01.602374 ==
2047 10:01:01.602438 RX Vref Scan: 0
2048 10:01:01.602498
2049 10:01:01.605748 RX Vref 0 -> 0, step: 1
2050 10:01:01.605828
2051 10:01:01.609252 RX Delay -95 -> 252, step: 8
2052 10:01:01.612597 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2053 10:01:01.619643 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2054 10:01:01.622601 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2055 10:01:01.625776 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2056 10:01:01.629319 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2057 10:01:01.633077 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2058 10:01:01.639555 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2059 10:01:01.643008 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2060 10:01:01.646222 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2061 10:01:01.649607 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2062 10:01:01.652610 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2063 10:01:01.656050 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2064 10:01:01.662889 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2065 10:01:01.666532 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2066 10:01:01.669432 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2067 10:01:01.672721 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2068 10:01:01.672802 ==
2069 10:01:01.676354 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 10:01:01.682933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 10:01:01.683014 ==
2072 10:01:01.683077 DQS Delay:
2073 10:01:01.683135 DQS0 = 0, DQS1 = 0
2074 10:01:01.686797 DQM Delay:
2075 10:01:01.686877 DQM0 = 80, DQM1 = 75
2076 10:01:01.689997 DQ Delay:
2077 10:01:01.692971 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2078 10:01:01.693051 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2079 10:01:01.696572 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2080 10:01:01.699842 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2081 10:01:01.703276
2082 10:01:01.703357
2083 10:01:01.710402 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2084 10:01:01.713455 CH1 RK1: MR19=606, MR18=1F2A
2085 10:01:01.720359 CH1_RK1: MR19=0x606, MR18=0x1F2A, DQSOSC=399, MR23=63, INC=92, DEC=61
2086 10:01:01.720469 [RxdqsGatingPostProcess] freq 800
2087 10:01:01.726778 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 10:01:01.730114 Pre-setting of DQS Precalculation
2089 10:01:01.733679 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 10:01:01.743992 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 10:01:01.750324 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 10:01:01.750406
2093 10:01:01.750471
2094 10:01:01.753715 [Calibration Summary] 1600 Mbps
2095 10:01:01.753796 CH 0, Rank 0
2096 10:01:01.757248 SW Impedance : PASS
2097 10:01:01.757329 DUTY Scan : NO K
2098 10:01:01.760210 ZQ Calibration : PASS
2099 10:01:01.763777 Jitter Meter : NO K
2100 10:01:01.763858 CBT Training : PASS
2101 10:01:01.767130 Write leveling : PASS
2102 10:01:01.770218 RX DQS gating : PASS
2103 10:01:01.770298 RX DQ/DQS(RDDQC) : PASS
2104 10:01:01.773727 TX DQ/DQS : PASS
2105 10:01:01.777245 RX DATLAT : PASS
2106 10:01:01.777329 RX DQ/DQS(Engine): PASS
2107 10:01:01.780414 TX OE : NO K
2108 10:01:01.780521 All Pass.
2109 10:01:01.780617
2110 10:01:01.780748 CH 0, Rank 1
2111 10:01:01.783949 SW Impedance : PASS
2112 10:01:01.787122 DUTY Scan : NO K
2113 10:01:01.787202 ZQ Calibration : PASS
2114 10:01:01.790763 Jitter Meter : NO K
2115 10:01:01.793928 CBT Training : PASS
2116 10:01:01.794009 Write leveling : PASS
2117 10:01:01.797525 RX DQS gating : PASS
2118 10:01:01.800815 RX DQ/DQS(RDDQC) : PASS
2119 10:01:01.800922 TX DQ/DQS : PASS
2120 10:01:01.803820 RX DATLAT : PASS
2121 10:01:01.807766 RX DQ/DQS(Engine): PASS
2122 10:01:01.807865 TX OE : NO K
2123 10:01:01.807955 All Pass.
2124 10:01:01.810908
2125 10:01:01.811004 CH 1, Rank 0
2126 10:01:01.814367 SW Impedance : PASS
2127 10:01:01.814463 DUTY Scan : NO K
2128 10:01:01.817608 ZQ Calibration : PASS
2129 10:01:01.817678 Jitter Meter : NO K
2130 10:01:01.820988 CBT Training : PASS
2131 10:01:01.823930 Write leveling : PASS
2132 10:01:01.824010 RX DQS gating : PASS
2133 10:01:01.827980 RX DQ/DQS(RDDQC) : PASS
2134 10:01:01.831029 TX DQ/DQS : PASS
2135 10:01:01.831111 RX DATLAT : PASS
2136 10:01:01.834499 RX DQ/DQS(Engine): PASS
2137 10:01:01.837615 TX OE : NO K
2138 10:01:01.837696 All Pass.
2139 10:01:01.837760
2140 10:01:01.837819 CH 1, Rank 1
2141 10:01:01.840971 SW Impedance : PASS
2142 10:01:01.844585 DUTY Scan : NO K
2143 10:01:01.844674 ZQ Calibration : PASS
2144 10:01:01.847859 Jitter Meter : NO K
2145 10:01:01.847940 CBT Training : PASS
2146 10:01:01.851243 Write leveling : PASS
2147 10:01:01.854850 RX DQS gating : PASS
2148 10:01:01.854931 RX DQ/DQS(RDDQC) : PASS
2149 10:01:01.857688 TX DQ/DQS : PASS
2150 10:01:01.861009 RX DATLAT : PASS
2151 10:01:01.861090 RX DQ/DQS(Engine): PASS
2152 10:01:01.864578 TX OE : NO K
2153 10:01:01.864659 All Pass.
2154 10:01:01.864731
2155 10:01:01.867939 DramC Write-DBI off
2156 10:01:01.871172 PER_BANK_REFRESH: Hybrid Mode
2157 10:01:01.871252 TX_TRACKING: ON
2158 10:01:01.874735 [GetDramInforAfterCalByMRR] Vendor 6.
2159 10:01:01.877669 [GetDramInforAfterCalByMRR] Revision 606.
2160 10:01:01.881357 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 10:01:01.884385 MR0 0x3b3b
2162 10:01:01.884467 MR8 0x5151
2163 10:01:01.887850 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 10:01:01.887931
2165 10:01:01.887994 MR0 0x3b3b
2166 10:01:01.891521 MR8 0x5151
2167 10:01:01.894391 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 10:01:01.894472
2169 10:01:01.904639 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 10:01:01.908371 [FAST_K] Save calibration result to emmc
2171 10:01:01.911394 [FAST_K] Save calibration result to emmc
2172 10:01:01.911493 dram_init: config_dvfs: 1
2173 10:01:01.917904 dramc_set_vcore_voltage set vcore to 662500
2174 10:01:01.917988 Read voltage for 1200, 2
2175 10:01:01.918051 Vio18 = 0
2176 10:01:01.921243 Vcore = 662500
2177 10:01:01.921315 Vdram = 0
2178 10:01:01.921392 Vddq = 0
2179 10:01:01.924567 Vmddr = 0
2180 10:01:01.928215 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 10:01:01.934626 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 10:01:01.934735 MEM_TYPE=3, freq_sel=15
2183 10:01:01.938331 sv_algorithm_assistance_LP4_1600
2184 10:01:01.945308 ============ PULL DRAM RESETB DOWN ============
2185 10:01:01.948416 ========== PULL DRAM RESETB DOWN end =========
2186 10:01:01.951787 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 10:01:01.955378 ===================================
2188 10:01:01.958253 LPDDR4 DRAM CONFIGURATION
2189 10:01:01.961550 ===================================
2190 10:01:01.961631 EX_ROW_EN[0] = 0x0
2191 10:01:01.965256 EX_ROW_EN[1] = 0x0
2192 10:01:01.968640 LP4Y_EN = 0x0
2193 10:01:01.968759 WORK_FSP = 0x0
2194 10:01:01.971966 WL = 0x4
2195 10:01:01.972047 RL = 0x4
2196 10:01:01.974905 BL = 0x2
2197 10:01:01.974985 RPST = 0x0
2198 10:01:01.978221 RD_PRE = 0x0
2199 10:01:01.978322 WR_PRE = 0x1
2200 10:01:01.981762 WR_PST = 0x0
2201 10:01:01.981936 DBI_WR = 0x0
2202 10:01:01.985417 DBI_RD = 0x0
2203 10:01:01.985501 OTF = 0x1
2204 10:01:01.988706 ===================================
2205 10:01:01.991737 ===================================
2206 10:01:01.995015 ANA top config
2207 10:01:01.998737 ===================================
2208 10:01:01.998819 DLL_ASYNC_EN = 0
2209 10:01:02.002238 ALL_SLAVE_EN = 0
2210 10:01:02.005172 NEW_RANK_MODE = 1
2211 10:01:02.008773 DLL_IDLE_MODE = 1
2212 10:01:02.008855 LP45_APHY_COMB_EN = 1
2213 10:01:02.012054 TX_ODT_DIS = 1
2214 10:01:02.015176 NEW_8X_MODE = 1
2215 10:01:02.018507 ===================================
2216 10:01:02.022169 ===================================
2217 10:01:02.025460 data_rate = 2400
2218 10:01:02.028532 CKR = 1
2219 10:01:02.028615 DQ_P2S_RATIO = 8
2220 10:01:02.032383 ===================================
2221 10:01:02.035227 CA_P2S_RATIO = 8
2222 10:01:02.038573 DQ_CA_OPEN = 0
2223 10:01:02.042210 DQ_SEMI_OPEN = 0
2224 10:01:02.045369 CA_SEMI_OPEN = 0
2225 10:01:02.049281 CA_FULL_RATE = 0
2226 10:01:02.049362 DQ_CKDIV4_EN = 0
2227 10:01:02.052169 CA_CKDIV4_EN = 0
2228 10:01:02.055612 CA_PREDIV_EN = 0
2229 10:01:02.059192 PH8_DLY = 17
2230 10:01:02.062634 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 10:01:02.062715 DQ_AAMCK_DIV = 4
2232 10:01:02.065985 CA_AAMCK_DIV = 4
2233 10:01:02.068904 CA_ADMCK_DIV = 4
2234 10:01:02.072294 DQ_TRACK_CA_EN = 0
2235 10:01:02.075764 CA_PICK = 1200
2236 10:01:02.079121 CA_MCKIO = 1200
2237 10:01:02.082922 MCKIO_SEMI = 0
2238 10:01:02.083003 PLL_FREQ = 2366
2239 10:01:02.085690 DQ_UI_PI_RATIO = 32
2240 10:01:02.089477 CA_UI_PI_RATIO = 0
2241 10:01:02.092639 ===================================
2242 10:01:02.095705 ===================================
2243 10:01:02.099113 memory_type:LPDDR4
2244 10:01:02.099227 GP_NUM : 10
2245 10:01:02.102601 SRAM_EN : 1
2246 10:01:02.106330 MD32_EN : 0
2247 10:01:02.109103 ===================================
2248 10:01:02.109185 [ANA_INIT] >>>>>>>>>>>>>>
2249 10:01:02.113251 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 10:01:02.116084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 10:01:02.119362 ===================================
2252 10:01:02.122948 data_rate = 2400,PCW = 0X5b00
2253 10:01:02.126067 ===================================
2254 10:01:02.129300 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 10:01:02.135786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 10:01:02.139394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 10:01:02.146011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 10:01:02.149623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 10:01:02.152936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 10:01:02.153018 [ANA_INIT] flow start
2261 10:01:02.156598 [ANA_INIT] PLL >>>>>>>>
2262 10:01:02.159732 [ANA_INIT] PLL <<<<<<<<
2263 10:01:02.159813 [ANA_INIT] MIDPI >>>>>>>>
2264 10:01:02.162927 [ANA_INIT] MIDPI <<<<<<<<
2265 10:01:02.165777 [ANA_INIT] DLL >>>>>>>>
2266 10:01:02.169168 [ANA_INIT] DLL <<<<<<<<
2267 10:01:02.169249 [ANA_INIT] flow end
2268 10:01:02.172918 ============ LP4 DIFF to SE enter ============
2269 10:01:02.179846 ============ LP4 DIFF to SE exit ============
2270 10:01:02.179928 [ANA_INIT] <<<<<<<<<<<<<
2271 10:01:02.182664 [Flow] Enable top DCM control >>>>>
2272 10:01:02.186163 [Flow] Enable top DCM control <<<<<
2273 10:01:02.189838 Enable DLL master slave shuffle
2274 10:01:02.196386 ==============================================================
2275 10:01:02.196469 Gating Mode config
2276 10:01:02.202948 ==============================================================
2277 10:01:02.203052 Config description:
2278 10:01:02.213188 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 10:01:02.220012 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 10:01:02.226789 SELPH_MODE 0: By rank 1: By Phase
2281 10:01:02.230378 ==============================================================
2282 10:01:02.233126 GAT_TRACK_EN = 1
2283 10:01:02.236413 RX_GATING_MODE = 2
2284 10:01:02.239920 RX_GATING_TRACK_MODE = 2
2285 10:01:02.243409 SELPH_MODE = 1
2286 10:01:02.246849 PICG_EARLY_EN = 1
2287 10:01:02.250032 VALID_LAT_VALUE = 1
2288 10:01:02.253271 ==============================================================
2289 10:01:02.256390 Enter into Gating configuration >>>>
2290 10:01:02.260011 Exit from Gating configuration <<<<
2291 10:01:02.263177 Enter into DVFS_PRE_config >>>>>
2292 10:01:02.276945 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 10:01:02.280328 Exit from DVFS_PRE_config <<<<<
2294 10:01:02.280409 Enter into PICG configuration >>>>
2295 10:01:02.283370 Exit from PICG configuration <<<<
2296 10:01:02.287181 [RX_INPUT] configuration >>>>>
2297 10:01:02.290242 [RX_INPUT] configuration <<<<<
2298 10:01:02.297099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 10:01:02.300373 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 10:01:02.306800 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 10:01:02.313789 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 10:01:02.320147 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 10:01:02.327095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 10:01:02.330702 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 10:01:02.333686 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 10:01:02.337468 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 10:01:02.340377 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 10:01:02.347082 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 10:01:02.350848 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 10:01:02.354085 ===================================
2311 10:01:02.357557 LPDDR4 DRAM CONFIGURATION
2312 10:01:02.360694 ===================================
2313 10:01:02.360790 EX_ROW_EN[0] = 0x0
2314 10:01:02.363986 EX_ROW_EN[1] = 0x0
2315 10:01:02.364068 LP4Y_EN = 0x0
2316 10:01:02.367422 WORK_FSP = 0x0
2317 10:01:02.367503 WL = 0x4
2318 10:01:02.370912 RL = 0x4
2319 10:01:02.370993 BL = 0x2
2320 10:01:02.374288 RPST = 0x0
2321 10:01:02.374370 RD_PRE = 0x0
2322 10:01:02.377700 WR_PRE = 0x1
2323 10:01:02.377819 WR_PST = 0x0
2324 10:01:02.381038 DBI_WR = 0x0
2325 10:01:02.381133 DBI_RD = 0x0
2326 10:01:02.384268 OTF = 0x1
2327 10:01:02.387744 ===================================
2328 10:01:02.390803 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 10:01:02.394473 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 10:01:02.401330 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 10:01:02.404033 ===================================
2332 10:01:02.404132 LPDDR4 DRAM CONFIGURATION
2333 10:01:02.407490 ===================================
2334 10:01:02.411015 EX_ROW_EN[0] = 0x10
2335 10:01:02.414549 EX_ROW_EN[1] = 0x0
2336 10:01:02.414631 LP4Y_EN = 0x0
2337 10:01:02.417580 WORK_FSP = 0x0
2338 10:01:02.417661 WL = 0x4
2339 10:01:02.420998 RL = 0x4
2340 10:01:02.421080 BL = 0x2
2341 10:01:02.424458 RPST = 0x0
2342 10:01:02.424540 RD_PRE = 0x0
2343 10:01:02.427854 WR_PRE = 0x1
2344 10:01:02.427943 WR_PST = 0x0
2345 10:01:02.430942 DBI_WR = 0x0
2346 10:01:02.431024 DBI_RD = 0x0
2347 10:01:02.434358 OTF = 0x1
2348 10:01:02.437776 ===================================
2349 10:01:02.444428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 10:01:02.444530 ==
2351 10:01:02.447863 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 10:01:02.451289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 10:01:02.451399 ==
2354 10:01:02.454878 [Duty_Offset_Calibration]
2355 10:01:02.454999 B0:3 B1:-1 CA:1
2356 10:01:02.455094
2357 10:01:02.457704 [DutyScan_Calibration_Flow] k_type=0
2358 10:01:02.466872
2359 10:01:02.467047 ==CLK 0==
2360 10:01:02.470232 Final CLK duty delay cell = -4
2361 10:01:02.474188 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2362 10:01:02.476996 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2363 10:01:02.481012 [-4] AVG Duty = 4953%(X100)
2364 10:01:02.481249
2365 10:01:02.484075 CH0 CLK Duty spec in!! Max-Min= 156%
2366 10:01:02.487526 [DutyScan_Calibration_Flow] ====Done====
2367 10:01:02.487911
2368 10:01:02.490921 [DutyScan_Calibration_Flow] k_type=1
2369 10:01:02.505131
2370 10:01:02.505213 ==DQS 0 ==
2371 10:01:02.508407 Final DQS duty delay cell = -4
2372 10:01:02.511635 [-4] MAX Duty = 5000%(X100), DQS PI = 46
2373 10:01:02.515359 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2374 10:01:02.518273 [-4] AVG Duty = 4937%(X100)
2375 10:01:02.518353
2376 10:01:02.518418 ==DQS 1 ==
2377 10:01:02.521619 Final DQS duty delay cell = -4
2378 10:01:02.525190 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2379 10:01:02.528790 [-4] MIN Duty = 5000%(X100), DQS PI = 58
2380 10:01:02.532090 [-4] AVG Duty = 5062%(X100)
2381 10:01:02.532173
2382 10:01:02.535743 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2383 10:01:02.535820
2384 10:01:02.538491 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2385 10:01:02.541884 [DutyScan_Calibration_Flow] ====Done====
2386 10:01:02.541957
2387 10:01:02.545278 [DutyScan_Calibration_Flow] k_type=3
2388 10:01:02.562270
2389 10:01:02.562346 ==DQM 0 ==
2390 10:01:02.565855 Final DQM duty delay cell = 0
2391 10:01:02.568675 [0] MAX Duty = 5000%(X100), DQS PI = 40
2392 10:01:02.572549 [0] MIN Duty = 4906%(X100), DQS PI = 2
2393 10:01:02.572624 [0] AVG Duty = 4953%(X100)
2394 10:01:02.575869
2395 10:01:02.575944 ==DQM 1 ==
2396 10:01:02.578968 Final DQM duty delay cell = 0
2397 10:01:02.582579 [0] MAX Duty = 5156%(X100), DQS PI = 62
2398 10:01:02.585375 [0] MIN Duty = 4969%(X100), DQS PI = 10
2399 10:01:02.585449 [0] AVG Duty = 5062%(X100)
2400 10:01:02.588809
2401 10:01:02.588876 CH0 DQM 0 Duty spec in!! Max-Min= 94%
2402 10:01:02.592394
2403 10:01:02.595908 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2404 10:01:02.599331 [DutyScan_Calibration_Flow] ====Done====
2405 10:01:02.599411
2406 10:01:02.602199 [DutyScan_Calibration_Flow] k_type=2
2407 10:01:02.618159
2408 10:01:02.618235 ==DQ 0 ==
2409 10:01:02.621432 Final DQ duty delay cell = -4
2410 10:01:02.624377 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2411 10:01:02.627667 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2412 10:01:02.631160 [-4] AVG Duty = 4968%(X100)
2413 10:01:02.631233
2414 10:01:02.631300 ==DQ 1 ==
2415 10:01:02.634697 Final DQ duty delay cell = 0
2416 10:01:02.638139 [0] MAX Duty = 5031%(X100), DQS PI = 18
2417 10:01:02.641453 [0] MIN Duty = 4907%(X100), DQS PI = 46
2418 10:01:02.641529 [0] AVG Duty = 4969%(X100)
2419 10:01:02.641593
2420 10:01:02.644915 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2421 10:01:02.648282
2422 10:01:02.651552 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2423 10:01:02.654968 [DutyScan_Calibration_Flow] ====Done====
2424 10:01:02.655037 ==
2425 10:01:02.658326 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 10:01:02.661586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 10:01:02.661655 ==
2428 10:01:02.664611 [Duty_Offset_Calibration]
2429 10:01:02.664721 B0:1 B1:1 CA:2
2430 10:01:02.664785
2431 10:01:02.668081 [DutyScan_Calibration_Flow] k_type=0
2432 10:01:02.678499
2433 10:01:02.678575 ==CLK 0==
2434 10:01:02.681688 Final CLK duty delay cell = 0
2435 10:01:02.685058 [0] MAX Duty = 5187%(X100), DQS PI = 24
2436 10:01:02.688495 [0] MIN Duty = 4969%(X100), DQS PI = 40
2437 10:01:02.688561 [0] AVG Duty = 5078%(X100)
2438 10:01:02.688627
2439 10:01:02.692044 CH1 CLK Duty spec in!! Max-Min= 218%
2440 10:01:02.698146 [DutyScan_Calibration_Flow] ====Done====
2441 10:01:02.698223
2442 10:01:02.701539 [DutyScan_Calibration_Flow] k_type=1
2443 10:01:02.717897
2444 10:01:02.717979 ==DQS 0 ==
2445 10:01:02.720928 Final DQS duty delay cell = 0
2446 10:01:02.724389 [0] MAX Duty = 5031%(X100), DQS PI = 18
2447 10:01:02.727438 [0] MIN Duty = 4844%(X100), DQS PI = 48
2448 10:01:02.727604 [0] AVG Duty = 4937%(X100)
2449 10:01:02.730976
2450 10:01:02.731060 ==DQS 1 ==
2451 10:01:02.734516 Final DQS duty delay cell = 0
2452 10:01:02.737959 [0] MAX Duty = 5062%(X100), DQS PI = 36
2453 10:01:02.740870 [0] MIN Duty = 4938%(X100), DQS PI = 0
2454 10:01:02.740955 [0] AVG Duty = 5000%(X100)
2455 10:01:02.741020
2456 10:01:02.744372 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2457 10:01:02.747830
2458 10:01:02.751251 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2459 10:01:02.754419 [DutyScan_Calibration_Flow] ====Done====
2460 10:01:02.754500
2461 10:01:02.757895 [DutyScan_Calibration_Flow] k_type=3
2462 10:01:02.774462
2463 10:01:02.774544 ==DQM 0 ==
2464 10:01:02.777250 Final DQM duty delay cell = 0
2465 10:01:02.780787 [0] MAX Duty = 5093%(X100), DQS PI = 16
2466 10:01:02.783916 [0] MIN Duty = 4907%(X100), DQS PI = 48
2467 10:01:02.783998 [0] AVG Duty = 5000%(X100)
2468 10:01:02.787550
2469 10:01:02.787632 ==DQM 1 ==
2470 10:01:02.791087 Final DQM duty delay cell = 0
2471 10:01:02.793968 [0] MAX Duty = 5156%(X100), DQS PI = 62
2472 10:01:02.797380 [0] MIN Duty = 4969%(X100), DQS PI = 4
2473 10:01:02.797462 [0] AVG Duty = 5062%(X100)
2474 10:01:02.797528
2475 10:01:02.800859 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2476 10:01:02.804378
2477 10:01:02.807746 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2478 10:01:02.811031 [DutyScan_Calibration_Flow] ====Done====
2479 10:01:02.811113
2480 10:01:02.814456 [DutyScan_Calibration_Flow] k_type=2
2481 10:01:02.829538
2482 10:01:02.829625 ==DQ 0 ==
2483 10:01:02.832887 Final DQ duty delay cell = 0
2484 10:01:02.836573 [0] MAX Duty = 5124%(X100), DQS PI = 18
2485 10:01:02.839901 [0] MIN Duty = 4938%(X100), DQS PI = 50
2486 10:01:02.839984 [0] AVG Duty = 5031%(X100)
2487 10:01:02.840049
2488 10:01:02.843401 ==DQ 1 ==
2489 10:01:02.846378 Final DQ duty delay cell = -4
2490 10:01:02.849937 [-4] MAX Duty = 5000%(X100), DQS PI = 58
2491 10:01:02.853497 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2492 10:01:02.853580 [-4] AVG Duty = 4953%(X100)
2493 10:01:02.853645
2494 10:01:02.856695 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2495 10:01:02.859894
2496 10:01:02.863365 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2497 10:01:02.866776 [DutyScan_Calibration_Flow] ====Done====
2498 10:01:02.869676 nWR fixed to 30
2499 10:01:02.869758 [ModeRegInit_LP4] CH0 RK0
2500 10:01:02.873085 [ModeRegInit_LP4] CH0 RK1
2501 10:01:02.876588 [ModeRegInit_LP4] CH1 RK0
2502 10:01:02.876693 [ModeRegInit_LP4] CH1 RK1
2503 10:01:02.879918 match AC timing 7
2504 10:01:02.883664 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 10:01:02.886746 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 10:01:02.893561 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 10:01:02.896785 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 10:01:02.903552 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 10:01:02.903634 ==
2510 10:01:02.907054 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 10:01:02.910445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 10:01:02.910528 ==
2513 10:01:02.917032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 10:01:02.920358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 10:01:02.930363 [CA 0] Center 40 (10~71) winsize 62
2516 10:01:02.933457 [CA 1] Center 39 (9~70) winsize 62
2517 10:01:02.936469 [CA 2] Center 36 (6~67) winsize 62
2518 10:01:02.939853 [CA 3] Center 35 (5~66) winsize 62
2519 10:01:02.943195 [CA 4] Center 35 (5~65) winsize 61
2520 10:01:02.946584 [CA 5] Center 34 (4~65) winsize 62
2521 10:01:02.946681
2522 10:01:02.950215 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2523 10:01:02.950299
2524 10:01:02.953640 [CATrainingPosCal] consider 1 rank data
2525 10:01:02.956547 u2DelayCellTimex100 = 270/100 ps
2526 10:01:02.959840 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2527 10:01:02.963822 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2528 10:01:02.970412 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2529 10:01:02.973760 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2530 10:01:02.976721 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2531 10:01:02.980284 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2532 10:01:02.980366
2533 10:01:02.983577 CA PerBit enable=1, Macro0, CA PI delay=34
2534 10:01:02.983659
2535 10:01:02.987064 [CBTSetCACLKResult] CA Dly = 34
2536 10:01:02.987146 CS Dly: 7 (0~38)
2537 10:01:02.987211 ==
2538 10:01:02.990511 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 10:01:02.996868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 10:01:02.996951 ==
2541 10:01:03.000420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 10:01:03.007067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2543 10:01:03.016190 [CA 0] Center 39 (9~70) winsize 62
2544 10:01:03.019141 [CA 1] Center 39 (9~70) winsize 62
2545 10:01:03.022687 [CA 2] Center 36 (6~67) winsize 62
2546 10:01:03.026098 [CA 3] Center 36 (5~67) winsize 63
2547 10:01:03.029352 [CA 4] Center 34 (4~65) winsize 62
2548 10:01:03.032604 [CA 5] Center 34 (4~64) winsize 61
2549 10:01:03.032749
2550 10:01:03.035985 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2551 10:01:03.036067
2552 10:01:03.039388 [CATrainingPosCal] consider 2 rank data
2553 10:01:03.042702 u2DelayCellTimex100 = 270/100 ps
2554 10:01:03.045948 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2555 10:01:03.049674 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2556 10:01:03.052641 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2557 10:01:03.059428 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2558 10:01:03.062883 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2559 10:01:03.066366 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2560 10:01:03.066447
2561 10:01:03.069747 CA PerBit enable=1, Macro0, CA PI delay=34
2562 10:01:03.069828
2563 10:01:03.073027 [CBTSetCACLKResult] CA Dly = 34
2564 10:01:03.073108 CS Dly: 8 (0~41)
2565 10:01:03.073173
2566 10:01:03.076450 ----->DramcWriteLeveling(PI) begin...
2567 10:01:03.076533 ==
2568 10:01:03.079936 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 10:01:03.086252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 10:01:03.086334 ==
2571 10:01:03.089747 Write leveling (Byte 0): 31 => 31
2572 10:01:03.089829 Write leveling (Byte 1): 29 => 29
2573 10:01:03.093505 DramcWriteLeveling(PI) end<-----
2574 10:01:03.093587
2575 10:01:03.093652 ==
2576 10:01:03.096457 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 10:01:03.103074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 10:01:03.103158 ==
2579 10:01:03.106493 [Gating] SW mode calibration
2580 10:01:03.113394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 10:01:03.116847 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 10:01:03.123640 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 10:01:03.126573 0 15 4 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
2584 10:01:03.130631 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 10:01:03.134114 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 10:01:03.140345 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 10:01:03.143759 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 10:01:03.147140 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 10:01:03.154028 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 10:01:03.157256 1 0 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2591 10:01:03.160277 1 0 4 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
2592 10:01:03.167413 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 10:01:03.170498 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 10:01:03.173676 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 10:01:03.180292 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 10:01:03.183653 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 10:01:03.187701 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 10:01:03.190450 1 1 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2599 10:01:03.197368 1 1 4 | B1->B0 | 3e3e 4444 | 0 0 | (1 1) (0 0)
2600 10:01:03.200872 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 10:01:03.203783 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 10:01:03.210813 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 10:01:03.214396 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 10:01:03.217298 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 10:01:03.224207 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 10:01:03.227391 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2607 10:01:03.231151 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2608 10:01:03.237311 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 10:01:03.240721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 10:01:03.244186 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 10:01:03.247967 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 10:01:03.254504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 10:01:03.258044 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 10:01:03.261516 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 10:01:03.267862 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 10:01:03.271149 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 10:01:03.274416 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 10:01:03.281672 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 10:01:03.285381 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 10:01:03.288123 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 10:01:03.294799 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 10:01:03.298511 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2623 10:01:03.301817 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2624 10:01:03.304686 Total UI for P1: 0, mck2ui 16
2625 10:01:03.308072 best dqsien dly found for B0: ( 1, 4, 0)
2626 10:01:03.311662 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 10:01:03.315076 Total UI for P1: 0, mck2ui 16
2628 10:01:03.318515 best dqsien dly found for B1: ( 1, 4, 2)
2629 10:01:03.321791 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2630 10:01:03.325058 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2631 10:01:03.325141
2632 10:01:03.331473 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2633 10:01:03.334866 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2634 10:01:03.334949 [Gating] SW calibration Done
2635 10:01:03.335013 ==
2636 10:01:03.338475 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 10:01:03.344859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 10:01:03.344942 ==
2639 10:01:03.345007 RX Vref Scan: 0
2640 10:01:03.345068
2641 10:01:03.348414 RX Vref 0 -> 0, step: 1
2642 10:01:03.348495
2643 10:01:03.352011 RX Delay -40 -> 252, step: 8
2644 10:01:03.355411 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2645 10:01:03.358725 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2646 10:01:03.361719 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2647 10:01:03.365348 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2648 10:01:03.372252 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2649 10:01:03.375826 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2650 10:01:03.378846 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2651 10:01:03.382443 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2652 10:01:03.385459 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2653 10:01:03.389334 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2654 10:01:03.395760 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2655 10:01:03.398692 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2656 10:01:03.402062 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2657 10:01:03.405980 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2658 10:01:03.412446 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2659 10:01:03.416312 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2660 10:01:03.416394 ==
2661 10:01:03.419124 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 10:01:03.422689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 10:01:03.422771 ==
2664 10:01:03.422836 DQS Delay:
2665 10:01:03.425551 DQS0 = 0, DQS1 = 0
2666 10:01:03.425632 DQM Delay:
2667 10:01:03.428844 DQM0 = 116, DQM1 = 107
2668 10:01:03.428929 DQ Delay:
2669 10:01:03.432418 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2670 10:01:03.435916 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2671 10:01:03.439349 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2672 10:01:03.442301 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2673 10:01:03.442383
2674 10:01:03.442447
2675 10:01:03.445589 ==
2676 10:01:03.445671 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 10:01:03.452867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 10:01:03.452949 ==
2679 10:01:03.453014
2680 10:01:03.453074
2681 10:01:03.456109 TX Vref Scan disable
2682 10:01:03.456191 == TX Byte 0 ==
2683 10:01:03.459137 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2684 10:01:03.466233 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2685 10:01:03.466315 == TX Byte 1 ==
2686 10:01:03.469451 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2687 10:01:03.476303 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2688 10:01:03.476385 ==
2689 10:01:03.479452 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 10:01:03.482980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 10:01:03.483063 ==
2692 10:01:03.494929 TX Vref=22, minBit 1, minWin=24, winSum=416
2693 10:01:03.497807 TX Vref=24, minBit 1, minWin=24, winSum=420
2694 10:01:03.501065 TX Vref=26, minBit 0, minWin=26, winSum=427
2695 10:01:03.504347 TX Vref=28, minBit 1, minWin=26, winSum=434
2696 10:01:03.507953 TX Vref=30, minBit 0, minWin=26, winSum=433
2697 10:01:03.511308 TX Vref=32, minBit 0, minWin=26, winSum=430
2698 10:01:03.517691 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 28
2699 10:01:03.517772
2700 10:01:03.521363 Final TX Range 1 Vref 28
2701 10:01:03.521443
2702 10:01:03.521529 ==
2703 10:01:03.524831 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 10:01:03.528373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 10:01:03.528453 ==
2706 10:01:03.528520
2707 10:01:03.528580
2708 10:01:03.531591 TX Vref Scan disable
2709 10:01:03.534609 == TX Byte 0 ==
2710 10:01:03.537977 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2711 10:01:03.541492 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2712 10:01:03.544560 == TX Byte 1 ==
2713 10:01:03.547915 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2714 10:01:03.551383 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2715 10:01:03.551472
2716 10:01:03.554751 [DATLAT]
2717 10:01:03.554832 Freq=1200, CH0 RK0
2718 10:01:03.554897
2719 10:01:03.558207 DATLAT Default: 0xd
2720 10:01:03.558288 0, 0xFFFF, sum = 0
2721 10:01:03.561191 1, 0xFFFF, sum = 0
2722 10:01:03.561273 2, 0xFFFF, sum = 0
2723 10:01:03.564705 3, 0xFFFF, sum = 0
2724 10:01:03.564802 4, 0xFFFF, sum = 0
2725 10:01:03.568346 5, 0xFFFF, sum = 0
2726 10:01:03.568430 6, 0xFFFF, sum = 0
2727 10:01:03.571516 7, 0xFFFF, sum = 0
2728 10:01:03.571599 8, 0xFFFF, sum = 0
2729 10:01:03.575234 9, 0xFFFF, sum = 0
2730 10:01:03.575318 10, 0xFFFF, sum = 0
2731 10:01:03.578592 11, 0xFFFF, sum = 0
2732 10:01:03.578676 12, 0x0, sum = 1
2733 10:01:03.581322 13, 0x0, sum = 2
2734 10:01:03.581405 14, 0x0, sum = 3
2735 10:01:03.584689 15, 0x0, sum = 4
2736 10:01:03.584772 best_step = 13
2737 10:01:03.584836
2738 10:01:03.584896 ==
2739 10:01:03.588478 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 10:01:03.594952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 10:01:03.595035 ==
2742 10:01:03.595100 RX Vref Scan: 1
2743 10:01:03.595160
2744 10:01:03.598530 Set Vref Range= 32 -> 127
2745 10:01:03.598612
2746 10:01:03.601617 RX Vref 32 -> 127, step: 1
2747 10:01:03.601699
2748 10:01:03.601764 RX Delay -21 -> 252, step: 4
2749 10:01:03.601825
2750 10:01:03.604995 Set Vref, RX VrefLevel [Byte0]: 32
2751 10:01:03.608461 [Byte1]: 32
2752 10:01:03.612542
2753 10:01:03.612623 Set Vref, RX VrefLevel [Byte0]: 33
2754 10:01:03.615910 [Byte1]: 33
2755 10:01:03.620432
2756 10:01:03.620513 Set Vref, RX VrefLevel [Byte0]: 34
2757 10:01:03.623974 [Byte1]: 34
2758 10:01:03.628546
2759 10:01:03.628628 Set Vref, RX VrefLevel [Byte0]: 35
2760 10:01:03.631682 [Byte1]: 35
2761 10:01:03.636591
2762 10:01:03.636697 Set Vref, RX VrefLevel [Byte0]: 36
2763 10:01:03.639510 [Byte1]: 36
2764 10:01:03.644109
2765 10:01:03.644190 Set Vref, RX VrefLevel [Byte0]: 37
2766 10:01:03.647553 [Byte1]: 37
2767 10:01:03.652354
2768 10:01:03.652435 Set Vref, RX VrefLevel [Byte0]: 38
2769 10:01:03.655936 [Byte1]: 38
2770 10:01:03.660466
2771 10:01:03.660548 Set Vref, RX VrefLevel [Byte0]: 39
2772 10:01:03.663304 [Byte1]: 39
2773 10:01:03.667889
2774 10:01:03.667970 Set Vref, RX VrefLevel [Byte0]: 40
2775 10:01:03.671481 [Byte1]: 40
2776 10:01:03.675990
2777 10:01:03.676071 Set Vref, RX VrefLevel [Byte0]: 41
2778 10:01:03.679319 [Byte1]: 41
2779 10:01:03.684038
2780 10:01:03.684119 Set Vref, RX VrefLevel [Byte0]: 42
2781 10:01:03.687513 [Byte1]: 42
2782 10:01:03.692046
2783 10:01:03.692130 Set Vref, RX VrefLevel [Byte0]: 43
2784 10:01:03.695165 [Byte1]: 43
2785 10:01:03.699670
2786 10:01:03.699754 Set Vref, RX VrefLevel [Byte0]: 44
2787 10:01:03.703065 [Byte1]: 44
2788 10:01:03.707966
2789 10:01:03.708047 Set Vref, RX VrefLevel [Byte0]: 45
2790 10:01:03.711237 [Byte1]: 45
2791 10:01:03.715595
2792 10:01:03.715676 Set Vref, RX VrefLevel [Byte0]: 46
2793 10:01:03.719089 [Byte1]: 46
2794 10:01:03.723574
2795 10:01:03.723682 Set Vref, RX VrefLevel [Byte0]: 47
2796 10:01:03.726798 [Byte1]: 47
2797 10:01:03.731320
2798 10:01:03.731402 Set Vref, RX VrefLevel [Byte0]: 48
2799 10:01:03.734872 [Byte1]: 48
2800 10:01:03.739352
2801 10:01:03.739433 Set Vref, RX VrefLevel [Byte0]: 49
2802 10:01:03.742944 [Byte1]: 49
2803 10:01:03.747345
2804 10:01:03.747426 Set Vref, RX VrefLevel [Byte0]: 50
2805 10:01:03.750871 [Byte1]: 50
2806 10:01:03.755494
2807 10:01:03.755576 Set Vref, RX VrefLevel [Byte0]: 51
2808 10:01:03.758646 [Byte1]: 51
2809 10:01:03.763068
2810 10:01:03.763158 Set Vref, RX VrefLevel [Byte0]: 52
2811 10:01:03.766387 [Byte1]: 52
2812 10:01:03.771084
2813 10:01:03.771166 Set Vref, RX VrefLevel [Byte0]: 53
2814 10:01:03.774410 [Byte1]: 53
2815 10:01:03.779213
2816 10:01:03.779294 Set Vref, RX VrefLevel [Byte0]: 54
2817 10:01:03.782163 [Byte1]: 54
2818 10:01:03.786896
2819 10:01:03.786978 Set Vref, RX VrefLevel [Byte0]: 55
2820 10:01:03.790503 [Byte1]: 55
2821 10:01:03.794999
2822 10:01:03.795096 Set Vref, RX VrefLevel [Byte0]: 56
2823 10:01:03.798418 [Byte1]: 56
2824 10:01:03.803032
2825 10:01:03.803113 Set Vref, RX VrefLevel [Byte0]: 57
2826 10:01:03.806522 [Byte1]: 57
2827 10:01:03.811142
2828 10:01:03.811223 Set Vref, RX VrefLevel [Byte0]: 58
2829 10:01:03.814017 [Byte1]: 58
2830 10:01:03.818990
2831 10:01:03.819071 Set Vref, RX VrefLevel [Byte0]: 59
2832 10:01:03.822193 [Byte1]: 59
2833 10:01:03.826522
2834 10:01:03.826603 Set Vref, RX VrefLevel [Byte0]: 60
2835 10:01:03.830240 [Byte1]: 60
2836 10:01:03.834453
2837 10:01:03.834535 Set Vref, RX VrefLevel [Byte0]: 61
2838 10:01:03.838135 [Byte1]: 61
2839 10:01:03.842630
2840 10:01:03.842711 Set Vref, RX VrefLevel [Byte0]: 62
2841 10:01:03.846086 [Byte1]: 62
2842 10:01:03.850326
2843 10:01:03.850408 Set Vref, RX VrefLevel [Byte0]: 63
2844 10:01:03.854217 [Byte1]: 63
2845 10:01:03.858241
2846 10:01:03.858322 Set Vref, RX VrefLevel [Byte0]: 64
2847 10:01:03.861803 [Byte1]: 64
2848 10:01:03.866489
2849 10:01:03.866570 Set Vref, RX VrefLevel [Byte0]: 65
2850 10:01:03.869504 [Byte1]: 65
2851 10:01:03.874095
2852 10:01:03.874176 Set Vref, RX VrefLevel [Byte0]: 66
2853 10:01:03.877546 [Byte1]: 66
2854 10:01:03.882061
2855 10:01:03.882143 Set Vref, RX VrefLevel [Byte0]: 67
2856 10:01:03.885525 [Byte1]: 67
2857 10:01:03.890110
2858 10:01:03.890191 Set Vref, RX VrefLevel [Byte0]: 68
2859 10:01:03.893636 [Byte1]: 68
2860 10:01:03.897885
2861 10:01:03.897967 Set Vref, RX VrefLevel [Byte0]: 69
2862 10:01:03.901502 [Byte1]: 69
2863 10:01:03.905942
2864 10:01:03.906023 Final RX Vref Byte 0 = 53 to rank0
2865 10:01:03.909201 Final RX Vref Byte 1 = 56 to rank0
2866 10:01:03.912510 Final RX Vref Byte 0 = 53 to rank1
2867 10:01:03.915858 Final RX Vref Byte 1 = 56 to rank1==
2868 10:01:03.919325 Dram Type= 6, Freq= 0, CH_0, rank 0
2869 10:01:03.922766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 10:01:03.926044 ==
2871 10:01:03.926172 DQS Delay:
2872 10:01:03.926237 DQS0 = 0, DQS1 = 0
2873 10:01:03.929326 DQM Delay:
2874 10:01:03.929408 DQM0 = 115, DQM1 = 106
2875 10:01:03.933173 DQ Delay:
2876 10:01:03.936735 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2877 10:01:03.939505 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2878 10:01:03.943254 DQ8 =92, DQ9 =94, DQ10 =108, DQ11 =96
2879 10:01:03.946055 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2880 10:01:03.946151
2881 10:01:03.946216
2882 10:01:03.952866 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbeb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
2883 10:01:03.956032 CH0 RK0: MR19=303, MR18=FBEB
2884 10:01:03.962835 CH0_RK0: MR19=0x303, MR18=0xFBEB, DQSOSC=412, MR23=63, INC=38, DEC=25
2885 10:01:03.962913
2886 10:01:03.966168 ----->DramcWriteLeveling(PI) begin...
2887 10:01:03.966243 ==
2888 10:01:03.969846 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 10:01:03.973250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 10:01:03.973326 ==
2891 10:01:03.976589 Write leveling (Byte 0): 32 => 32
2892 10:01:03.979658 Write leveling (Byte 1): 30 => 30
2893 10:01:03.982902 DramcWriteLeveling(PI) end<-----
2894 10:01:03.982975
2895 10:01:03.983038 ==
2896 10:01:03.986516 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 10:01:03.990029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 10:01:03.990101 ==
2899 10:01:03.993490 [Gating] SW mode calibration
2900 10:01:04.000146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2901 10:01:04.006674 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2902 10:01:04.010052 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 10:01:04.016703 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2904 10:01:04.020122 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 10:01:04.023366 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 10:01:04.026948 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 10:01:04.033851 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 10:01:04.037237 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2909 10:01:04.040270 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2910 10:01:04.047211 1 0 0 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
2911 10:01:04.050183 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 10:01:04.053474 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 10:01:04.060342 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 10:01:04.063577 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 10:01:04.067126 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 10:01:04.070270 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2917 10:01:04.077116 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2918 10:01:04.080739 1 1 0 | B1->B0 | 2726 3939 | 1 0 | (0 0) (0 0)
2919 10:01:04.084122 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2920 10:01:04.090681 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 10:01:04.094246 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 10:01:04.097245 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 10:01:04.104078 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 10:01:04.107764 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 10:01:04.110855 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2926 10:01:04.114448 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2927 10:01:04.121293 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 10:01:04.124591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 10:01:04.127817 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 10:01:04.134231 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 10:01:04.137768 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 10:01:04.141415 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 10:01:04.147854 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 10:01:04.151288 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 10:01:04.154771 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 10:01:04.161498 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 10:01:04.164642 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 10:01:04.168069 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 10:01:04.174561 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 10:01:04.178138 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 10:01:04.181160 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2942 10:01:04.184556 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2943 10:01:04.187958 Total UI for P1: 0, mck2ui 16
2944 10:01:04.191636 best dqsien dly found for B0: ( 1, 3, 28)
2945 10:01:04.198038 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 10:01:04.201468 Total UI for P1: 0, mck2ui 16
2947 10:01:04.205072 best dqsien dly found for B1: ( 1, 4, 0)
2948 10:01:04.207987 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2949 10:01:04.211414 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2950 10:01:04.211496
2951 10:01:04.214870 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2952 10:01:04.218317 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2953 10:01:04.221558 [Gating] SW calibration Done
2954 10:01:04.221641 ==
2955 10:01:04.225151 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 10:01:04.228266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 10:01:04.228343 ==
2958 10:01:04.232155 RX Vref Scan: 0
2959 10:01:04.232240
2960 10:01:04.232304 RX Vref 0 -> 0, step: 1
2961 10:01:04.232364
2962 10:01:04.235138 RX Delay -40 -> 252, step: 8
2963 10:01:04.238177 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2964 10:01:04.245271 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2965 10:01:04.248603 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2966 10:01:04.251858 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2967 10:01:04.255334 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2968 10:01:04.258717 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2969 10:01:04.262365 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2970 10:01:04.268904 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2971 10:01:04.271907 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2972 10:01:04.275509 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2973 10:01:04.278882 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2974 10:01:04.282321 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2975 10:01:04.288643 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2976 10:01:04.292129 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2977 10:01:04.295623 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2978 10:01:04.299091 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2979 10:01:04.299167 ==
2980 10:01:04.302542 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 10:01:04.305346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 10:01:04.308875 ==
2983 10:01:04.308950 DQS Delay:
2984 10:01:04.309012 DQS0 = 0, DQS1 = 0
2985 10:01:04.312523 DQM Delay:
2986 10:01:04.312622 DQM0 = 115, DQM1 = 107
2987 10:01:04.315346 DQ Delay:
2988 10:01:04.318688 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2989 10:01:04.322186 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2990 10:01:04.325670 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2991 10:01:04.328884 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =111
2992 10:01:04.328962
2993 10:01:04.329027
2994 10:01:04.329087 ==
2995 10:01:04.332265 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 10:01:04.335591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 10:01:04.335666 ==
2998 10:01:04.335736
2999 10:01:04.335796
3000 10:01:04.338796 TX Vref Scan disable
3001 10:01:04.342424 == TX Byte 0 ==
3002 10:01:04.345488 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3003 10:01:04.349414 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3004 10:01:04.352835 == TX Byte 1 ==
3005 10:01:04.355986 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3006 10:01:04.358924 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3007 10:01:04.359022 ==
3008 10:01:04.362304 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 10:01:04.365935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 10:01:04.366009 ==
3011 10:01:04.379235 TX Vref=22, minBit 3, minWin=25, winSum=423
3012 10:01:04.382247 TX Vref=24, minBit 3, minWin=25, winSum=430
3013 10:01:04.385759 TX Vref=26, minBit 1, minWin=26, winSum=432
3014 10:01:04.388971 TX Vref=28, minBit 0, minWin=27, winSum=437
3015 10:01:04.392874 TX Vref=30, minBit 12, minWin=26, winSum=435
3016 10:01:04.395694 TX Vref=32, minBit 12, minWin=26, winSum=437
3017 10:01:04.402794 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 28
3018 10:01:04.402871
3019 10:01:04.406093 Final TX Range 1 Vref 28
3020 10:01:04.406166
3021 10:01:04.406230 ==
3022 10:01:04.409186 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 10:01:04.412588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 10:01:04.412683 ==
3025 10:01:04.412763
3026 10:01:04.412822
3027 10:01:04.416314 TX Vref Scan disable
3028 10:01:04.419694 == TX Byte 0 ==
3029 10:01:04.422898 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3030 10:01:04.426347 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3031 10:01:04.429755 == TX Byte 1 ==
3032 10:01:04.432574 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3033 10:01:04.436555 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3034 10:01:04.436632
3035 10:01:04.439543 [DATLAT]
3036 10:01:04.439632 Freq=1200, CH0 RK1
3037 10:01:04.439694
3038 10:01:04.443213 DATLAT Default: 0xd
3039 10:01:04.443283 0, 0xFFFF, sum = 0
3040 10:01:04.446906 1, 0xFFFF, sum = 0
3041 10:01:04.446979 2, 0xFFFF, sum = 0
3042 10:01:04.449901 3, 0xFFFF, sum = 0
3043 10:01:04.449975 4, 0xFFFF, sum = 0
3044 10:01:04.453184 5, 0xFFFF, sum = 0
3045 10:01:04.453255 6, 0xFFFF, sum = 0
3046 10:01:04.456741 7, 0xFFFF, sum = 0
3047 10:01:04.456864 8, 0xFFFF, sum = 0
3048 10:01:04.460045 9, 0xFFFF, sum = 0
3049 10:01:04.460119 10, 0xFFFF, sum = 0
3050 10:01:04.462959 11, 0xFFFF, sum = 0
3051 10:01:04.463028 12, 0x0, sum = 1
3052 10:01:04.466286 13, 0x0, sum = 2
3053 10:01:04.466359 14, 0x0, sum = 3
3054 10:01:04.469985 15, 0x0, sum = 4
3055 10:01:04.470064 best_step = 13
3056 10:01:04.470150
3057 10:01:04.470211 ==
3058 10:01:04.473425 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 10:01:04.476342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 10:01:04.479766 ==
3061 10:01:04.479838 RX Vref Scan: 0
3062 10:01:04.479903
3063 10:01:04.483122 RX Vref 0 -> 0, step: 1
3064 10:01:04.483192
3065 10:01:04.486413 RX Delay -21 -> 252, step: 4
3066 10:01:04.489807 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3067 10:01:04.493776 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3068 10:01:04.496553 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3069 10:01:04.503156 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3070 10:01:04.506751 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3071 10:01:04.510269 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3072 10:01:04.513654 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3073 10:01:04.517255 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3074 10:01:04.520060 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3075 10:01:04.526868 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3076 10:01:04.530347 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3077 10:01:04.533918 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3078 10:01:04.536845 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3079 10:01:04.540698 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3080 10:01:04.547053 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3081 10:01:04.550233 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3082 10:01:04.550310 ==
3083 10:01:04.553796 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 10:01:04.557141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 10:01:04.557214 ==
3086 10:01:04.560163 DQS Delay:
3087 10:01:04.560230 DQS0 = 0, DQS1 = 0
3088 10:01:04.560293 DQM Delay:
3089 10:01:04.563540 DQM0 = 114, DQM1 = 106
3090 10:01:04.563607 DQ Delay:
3091 10:01:04.567016 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3092 10:01:04.570351 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3093 10:01:04.573610 DQ8 =94, DQ9 =94, DQ10 =106, DQ11 =96
3094 10:01:04.577166 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =114
3095 10:01:04.577266
3096 10:01:04.580696
3097 10:01:04.587041 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3098 10:01:04.590714 CH0 RK1: MR19=403, MR18=2F3
3099 10:01:04.597061 CH0_RK1: MR19=0x403, MR18=0x2F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3100 10:01:04.597141 [RxdqsGatingPostProcess] freq 1200
3101 10:01:04.603837 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3102 10:01:04.607608 best DQS0 dly(2T, 0.5T) = (0, 12)
3103 10:01:04.610397 best DQS1 dly(2T, 0.5T) = (0, 12)
3104 10:01:04.613805 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3105 10:01:04.617317 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3106 10:01:04.621033 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 10:01:04.624020 best DQS1 dly(2T, 0.5T) = (0, 12)
3108 10:01:04.627299 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 10:01:04.627373 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3110 10:01:04.630589 Pre-setting of DQS Precalculation
3111 10:01:04.637189 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3112 10:01:04.637272 ==
3113 10:01:04.640560 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 10:01:04.644577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 10:01:04.644721 ==
3116 10:01:04.650988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 10:01:04.657255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3118 10:01:04.664846 [CA 0] Center 38 (8~68) winsize 61
3119 10:01:04.668167 [CA 1] Center 38 (8~68) winsize 61
3120 10:01:04.671521 [CA 2] Center 35 (5~65) winsize 61
3121 10:01:04.674641 [CA 3] Center 34 (4~65) winsize 62
3122 10:01:04.678466 [CA 4] Center 34 (4~65) winsize 62
3123 10:01:04.681480 [CA 5] Center 33 (3~64) winsize 62
3124 10:01:04.681555
3125 10:01:04.684763 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3126 10:01:04.684837
3127 10:01:04.687831 [CATrainingPosCal] consider 1 rank data
3128 10:01:04.691398 u2DelayCellTimex100 = 270/100 ps
3129 10:01:04.694710 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3130 10:01:04.698183 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3131 10:01:04.704911 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3132 10:01:04.708319 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3133 10:01:04.711728 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3134 10:01:04.714977 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3135 10:01:04.715050
3136 10:01:04.718072 CA PerBit enable=1, Macro0, CA PI delay=33
3137 10:01:04.718146
3138 10:01:04.721471 [CBTSetCACLKResult] CA Dly = 33
3139 10:01:04.721542 CS Dly: 6 (0~37)
3140 10:01:04.721640 ==
3141 10:01:04.725087 Dram Type= 6, Freq= 0, CH_1, rank 1
3142 10:01:04.731974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 10:01:04.732075 ==
3144 10:01:04.735477 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 10:01:04.741820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3146 10:01:04.750318 [CA 0] Center 38 (8~68) winsize 61
3147 10:01:04.753752 [CA 1] Center 38 (8~68) winsize 61
3148 10:01:04.756591 [CA 2] Center 34 (4~65) winsize 62
3149 10:01:04.760435 [CA 3] Center 34 (4~65) winsize 62
3150 10:01:04.763465 [CA 4] Center 34 (4~65) winsize 62
3151 10:01:04.767046 [CA 5] Center 33 (3~64) winsize 62
3152 10:01:04.767121
3153 10:01:04.769960 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3154 10:01:04.770034
3155 10:01:04.773680 [CATrainingPosCal] consider 2 rank data
3156 10:01:04.777006 u2DelayCellTimex100 = 270/100 ps
3157 10:01:04.780199 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3158 10:01:04.783448 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 10:01:04.787256 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3160 10:01:04.793515 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3161 10:01:04.797179 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3162 10:01:04.800418 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3163 10:01:04.800495
3164 10:01:04.803890 CA PerBit enable=1, Macro0, CA PI delay=33
3165 10:01:04.803965
3166 10:01:04.807291 [CBTSetCACLKResult] CA Dly = 33
3167 10:01:04.807447 CS Dly: 7 (0~40)
3168 10:01:04.807564
3169 10:01:04.810613 ----->DramcWriteLeveling(PI) begin...
3170 10:01:04.810740 ==
3171 10:01:04.814059 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 10:01:04.820365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 10:01:04.820477 ==
3174 10:01:04.823756 Write leveling (Byte 0): 26 => 26
3175 10:01:04.823866 Write leveling (Byte 1): 28 => 28
3176 10:01:04.827284 DramcWriteLeveling(PI) end<-----
3177 10:01:04.827369
3178 10:01:04.830671 ==
3179 10:01:04.830748 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 10:01:04.837477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 10:01:04.837576 ==
3182 10:01:04.840973 [Gating] SW mode calibration
3183 10:01:04.847515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3184 10:01:04.850856 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3185 10:01:04.857738 0 15 0 | B1->B0 | 2b2b 2323 | 1 1 | (1 1) (1 1)
3186 10:01:04.861084 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 10:01:04.864415 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 10:01:04.867439 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 10:01:04.874005 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 10:01:04.877590 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 10:01:04.881029 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 10:01:04.887766 0 15 28 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
3193 10:01:04.891536 1 0 0 | B1->B0 | 2424 2727 | 0 0 | (1 0) (1 0)
3194 10:01:04.894173 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 10:01:04.901290 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 10:01:04.904356 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 10:01:04.907900 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3198 10:01:04.914699 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 10:01:04.918090 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 10:01:04.921115 1 0 28 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
3201 10:01:04.928343 1 1 0 | B1->B0 | 4242 3131 | 0 1 | (0 0) (0 0)
3202 10:01:04.931432 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 10:01:04.934617 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 10:01:04.937931 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 10:01:04.944807 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 10:01:04.948236 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 10:01:04.951710 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 10:01:04.958477 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 10:01:04.961880 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3210 10:01:04.964940 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 10:01:04.971688 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 10:01:04.975245 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 10:01:04.978812 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 10:01:04.981669 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 10:01:04.988704 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 10:01:04.992118 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 10:01:04.995387 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 10:01:05.002059 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 10:01:05.005693 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 10:01:05.008577 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 10:01:05.015740 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 10:01:05.019049 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 10:01:05.022057 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3224 10:01:05.029205 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 10:01:05.032683 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 10:01:05.035406 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 10:01:05.038943 Total UI for P1: 0, mck2ui 16
3228 10:01:05.042168 best dqsien dly found for B0: ( 1, 3, 28)
3229 10:01:05.045637 Total UI for P1: 0, mck2ui 16
3230 10:01:05.049001 best dqsien dly found for B1: ( 1, 3, 30)
3231 10:01:05.052503 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3232 10:01:05.056202 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3233 10:01:05.056282
3234 10:01:05.059388 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3235 10:01:05.062733 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3236 10:01:05.065706 [Gating] SW calibration Done
3237 10:01:05.065779 ==
3238 10:01:05.069627 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 10:01:05.075850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 10:01:05.075938 ==
3241 10:01:05.076011 RX Vref Scan: 0
3242 10:01:05.076073
3243 10:01:05.079379 RX Vref 0 -> 0, step: 1
3244 10:01:05.079462
3245 10:01:05.082324 RX Delay -40 -> 252, step: 8
3246 10:01:05.086142 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3247 10:01:05.089006 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3248 10:01:05.092577 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3249 10:01:05.096147 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3250 10:01:05.102880 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3251 10:01:05.105933 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3252 10:01:05.109290 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3253 10:01:05.112893 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3254 10:01:05.116215 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3255 10:01:05.119697 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3256 10:01:05.125998 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3257 10:01:05.129831 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3258 10:01:05.132820 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3259 10:01:05.136451 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3260 10:01:05.139863 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3261 10:01:05.146545 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3262 10:01:05.146646 ==
3263 10:01:05.149456 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 10:01:05.153287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 10:01:05.153388 ==
3266 10:01:05.153456 DQS Delay:
3267 10:01:05.156574 DQS0 = 0, DQS1 = 0
3268 10:01:05.156704 DQM Delay:
3269 10:01:05.159605 DQM0 = 115, DQM1 = 108
3270 10:01:05.159695 DQ Delay:
3271 10:01:05.162837 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3272 10:01:05.166329 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3273 10:01:05.169729 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3274 10:01:05.173220 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3275 10:01:05.173331
3276 10:01:05.173424
3277 10:01:05.173513 ==
3278 10:01:05.176674 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 10:01:05.183353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 10:01:05.183432 ==
3281 10:01:05.183498
3282 10:01:05.183568
3283 10:01:05.183627 TX Vref Scan disable
3284 10:01:05.186641 == TX Byte 0 ==
3285 10:01:05.190309 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3286 10:01:05.193208 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3287 10:01:05.196677 == TX Byte 1 ==
3288 10:01:05.200501 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3289 10:01:05.203697 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3290 10:01:05.206703 ==
3291 10:01:05.210093 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 10:01:05.213356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 10:01:05.213467 ==
3294 10:01:05.224713 TX Vref=22, minBit 3, minWin=24, winSum=409
3295 10:01:05.228023 TX Vref=24, minBit 1, minWin=25, winSum=414
3296 10:01:05.230986 TX Vref=26, minBit 8, minWin=25, winSum=417
3297 10:01:05.234611 TX Vref=28, minBit 0, minWin=26, winSum=424
3298 10:01:05.237732 TX Vref=30, minBit 0, minWin=26, winSum=425
3299 10:01:05.241515 TX Vref=32, minBit 9, minWin=25, winSum=424
3300 10:01:05.247703 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
3301 10:01:05.247781
3302 10:01:05.251116 Final TX Range 1 Vref 30
3303 10:01:05.251186
3304 10:01:05.251247 ==
3305 10:01:05.255027 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 10:01:05.258100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 10:01:05.258170 ==
3308 10:01:05.258243
3309 10:01:05.258301
3310 10:01:05.261344 TX Vref Scan disable
3311 10:01:05.264600 == TX Byte 0 ==
3312 10:01:05.267969 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3313 10:01:05.271258 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3314 10:01:05.274730 == TX Byte 1 ==
3315 10:01:05.278255 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3316 10:01:05.281574 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3317 10:01:05.281739
3318 10:01:05.285101 [DATLAT]
3319 10:01:05.285188 Freq=1200, CH1 RK0
3320 10:01:05.285250
3321 10:01:05.288122 DATLAT Default: 0xd
3322 10:01:05.288201 0, 0xFFFF, sum = 0
3323 10:01:05.291607 1, 0xFFFF, sum = 0
3324 10:01:05.291708 2, 0xFFFF, sum = 0
3325 10:01:05.294924 3, 0xFFFF, sum = 0
3326 10:01:05.294995 4, 0xFFFF, sum = 0
3327 10:01:05.298521 5, 0xFFFF, sum = 0
3328 10:01:05.298596 6, 0xFFFF, sum = 0
3329 10:01:05.301672 7, 0xFFFF, sum = 0
3330 10:01:05.301778 8, 0xFFFF, sum = 0
3331 10:01:05.305158 9, 0xFFFF, sum = 0
3332 10:01:05.305248 10, 0xFFFF, sum = 0
3333 10:01:05.308431 11, 0xFFFF, sum = 0
3334 10:01:05.308535 12, 0x0, sum = 1
3335 10:01:05.311957 13, 0x0, sum = 2
3336 10:01:05.312075 14, 0x0, sum = 3
3337 10:01:05.315445 15, 0x0, sum = 4
3338 10:01:05.315556 best_step = 13
3339 10:01:05.315648
3340 10:01:05.315740 ==
3341 10:01:05.318686 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 10:01:05.322121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 10:01:05.325534 ==
3344 10:01:05.325643 RX Vref Scan: 1
3345 10:01:05.325736
3346 10:01:05.328768 Set Vref Range= 32 -> 127
3347 10:01:05.328872
3348 10:01:05.328964 RX Vref 32 -> 127, step: 1
3349 10:01:05.332230
3350 10:01:05.332348 RX Delay -21 -> 252, step: 4
3351 10:01:05.332417
3352 10:01:05.335364 Set Vref, RX VrefLevel [Byte0]: 32
3353 10:01:05.338784 [Byte1]: 32
3354 10:01:05.342941
3355 10:01:05.343035 Set Vref, RX VrefLevel [Byte0]: 33
3356 10:01:05.346490 [Byte1]: 33
3357 10:01:05.350881
3358 10:01:05.350985 Set Vref, RX VrefLevel [Byte0]: 34
3359 10:01:05.354020 [Byte1]: 34
3360 10:01:05.358700
3361 10:01:05.358773 Set Vref, RX VrefLevel [Byte0]: 35
3362 10:01:05.362312 [Byte1]: 35
3363 10:01:05.366628
3364 10:01:05.366697 Set Vref, RX VrefLevel [Byte0]: 36
3365 10:01:05.369676 [Byte1]: 36
3366 10:01:05.374396
3367 10:01:05.374465 Set Vref, RX VrefLevel [Byte0]: 37
3368 10:01:05.378280 [Byte1]: 37
3369 10:01:05.382160
3370 10:01:05.382232 Set Vref, RX VrefLevel [Byte0]: 38
3371 10:01:05.385465 [Byte1]: 38
3372 10:01:05.390140
3373 10:01:05.390212 Set Vref, RX VrefLevel [Byte0]: 39
3374 10:01:05.393602 [Byte1]: 39
3375 10:01:05.398264
3376 10:01:05.398338 Set Vref, RX VrefLevel [Byte0]: 40
3377 10:01:05.401876 [Byte1]: 40
3378 10:01:05.405848
3379 10:01:05.405924 Set Vref, RX VrefLevel [Byte0]: 41
3380 10:01:05.409588 [Byte1]: 41
3381 10:01:05.414160
3382 10:01:05.414238 Set Vref, RX VrefLevel [Byte0]: 42
3383 10:01:05.417746 [Byte1]: 42
3384 10:01:05.422429
3385 10:01:05.422499 Set Vref, RX VrefLevel [Byte0]: 43
3386 10:01:05.425164 [Byte1]: 43
3387 10:01:05.429852
3388 10:01:05.429923 Set Vref, RX VrefLevel [Byte0]: 44
3389 10:01:05.433026 [Byte1]: 44
3390 10:01:05.437809
3391 10:01:05.437923 Set Vref, RX VrefLevel [Byte0]: 45
3392 10:01:05.441347 [Byte1]: 45
3393 10:01:05.445948
3394 10:01:05.446052 Set Vref, RX VrefLevel [Byte0]: 46
3395 10:01:05.448963 [Byte1]: 46
3396 10:01:05.453930
3397 10:01:05.454076 Set Vref, RX VrefLevel [Byte0]: 47
3398 10:01:05.456708 [Byte1]: 47
3399 10:01:05.461802
3400 10:01:05.461906 Set Vref, RX VrefLevel [Byte0]: 48
3401 10:01:05.464970 [Byte1]: 48
3402 10:01:05.469369
3403 10:01:05.469478 Set Vref, RX VrefLevel [Byte0]: 49
3404 10:01:05.472871 [Byte1]: 49
3405 10:01:05.477227
3406 10:01:05.477334 Set Vref, RX VrefLevel [Byte0]: 50
3407 10:01:05.480985 [Byte1]: 50
3408 10:01:05.485115
3409 10:01:05.485207 Set Vref, RX VrefLevel [Byte0]: 51
3410 10:01:05.488573 [Byte1]: 51
3411 10:01:05.493333
3412 10:01:05.493497 Set Vref, RX VrefLevel [Byte0]: 52
3413 10:01:05.496742 [Byte1]: 52
3414 10:01:05.501008
3415 10:01:05.501093 Set Vref, RX VrefLevel [Byte0]: 53
3416 10:01:05.504384 [Byte1]: 53
3417 10:01:05.509076
3418 10:01:05.509144 Set Vref, RX VrefLevel [Byte0]: 54
3419 10:01:05.512313 [Byte1]: 54
3420 10:01:05.517501
3421 10:01:05.517581 Set Vref, RX VrefLevel [Byte0]: 55
3422 10:01:05.520141 [Byte1]: 55
3423 10:01:05.524834
3424 10:01:05.524917 Set Vref, RX VrefLevel [Byte0]: 56
3425 10:01:05.528288 [Byte1]: 56
3426 10:01:05.532899
3427 10:01:05.532995 Set Vref, RX VrefLevel [Byte0]: 57
3428 10:01:05.535970 [Byte1]: 57
3429 10:01:05.540562
3430 10:01:05.540641 Set Vref, RX VrefLevel [Byte0]: 58
3431 10:01:05.543904 [Byte1]: 58
3432 10:01:05.548447
3433 10:01:05.548517 Set Vref, RX VrefLevel [Byte0]: 59
3434 10:01:05.551861 [Byte1]: 59
3435 10:01:05.556572
3436 10:01:05.556643 Set Vref, RX VrefLevel [Byte0]: 60
3437 10:01:05.559649 [Byte1]: 60
3438 10:01:05.564346
3439 10:01:05.564426 Set Vref, RX VrefLevel [Byte0]: 61
3440 10:01:05.568031 [Byte1]: 61
3441 10:01:05.572436
3442 10:01:05.572511 Set Vref, RX VrefLevel [Byte0]: 62
3443 10:01:05.575585 [Byte1]: 62
3444 10:01:05.580442
3445 10:01:05.580521 Set Vref, RX VrefLevel [Byte0]: 63
3446 10:01:05.583818 [Byte1]: 63
3447 10:01:05.588349
3448 10:01:05.588427 Set Vref, RX VrefLevel [Byte0]: 64
3449 10:01:05.591810 [Byte1]: 64
3450 10:01:05.596271
3451 10:01:05.596354 Set Vref, RX VrefLevel [Byte0]: 65
3452 10:01:05.599528 [Byte1]: 65
3453 10:01:05.604092
3454 10:01:05.604173 Set Vref, RX VrefLevel [Byte0]: 66
3455 10:01:05.607658 [Byte1]: 66
3456 10:01:05.612388
3457 10:01:05.612495 Set Vref, RX VrefLevel [Byte0]: 67
3458 10:01:05.615453 [Byte1]: 67
3459 10:01:05.620287
3460 10:01:05.620371 Set Vref, RX VrefLevel [Byte0]: 68
3461 10:01:05.623156 [Byte1]: 68
3462 10:01:05.627879
3463 10:01:05.627970 Set Vref, RX VrefLevel [Byte0]: 69
3464 10:01:05.631393 [Byte1]: 69
3465 10:01:05.636275
3466 10:01:05.636393 Set Vref, RX VrefLevel [Byte0]: 70
3467 10:01:05.638968 [Byte1]: 70
3468 10:01:05.643640
3469 10:01:05.643724 Set Vref, RX VrefLevel [Byte0]: 71
3470 10:01:05.647655 [Byte1]: 71
3471 10:01:05.652172
3472 10:01:05.652249 Final RX Vref Byte 0 = 57 to rank0
3473 10:01:05.654930 Final RX Vref Byte 1 = 52 to rank0
3474 10:01:05.658199 Final RX Vref Byte 0 = 57 to rank1
3475 10:01:05.661785 Final RX Vref Byte 1 = 52 to rank1==
3476 10:01:05.665274 Dram Type= 6, Freq= 0, CH_1, rank 0
3477 10:01:05.668735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 10:01:05.671662 ==
3479 10:01:05.671736 DQS Delay:
3480 10:01:05.671798 DQS0 = 0, DQS1 = 0
3481 10:01:05.675358 DQM Delay:
3482 10:01:05.675432 DQM0 = 116, DQM1 = 109
3483 10:01:05.678370 DQ Delay:
3484 10:01:05.681635 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3485 10:01:05.685038 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3486 10:01:05.688699 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3487 10:01:05.691798 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =114
3488 10:01:05.691867
3489 10:01:05.691928
3490 10:01:05.698568 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3491 10:01:05.702028 CH1 RK0: MR19=403, MR18=1E6
3492 10:01:05.708786 CH1_RK0: MR19=0x403, MR18=0x1E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3493 10:01:05.708894
3494 10:01:05.712401 ----->DramcWriteLeveling(PI) begin...
3495 10:01:05.712482 ==
3496 10:01:05.715631 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 10:01:05.718555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 10:01:05.718631 ==
3499 10:01:05.722010 Write leveling (Byte 0): 26 => 26
3500 10:01:05.725485 Write leveling (Byte 1): 30 => 30
3501 10:01:05.728655 DramcWriteLeveling(PI) end<-----
3502 10:01:05.728750
3503 10:01:05.728815 ==
3504 10:01:05.732599 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 10:01:05.735471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 10:01:05.735559 ==
3507 10:01:05.738976 [Gating] SW mode calibration
3508 10:01:05.745410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3509 10:01:05.752117 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3510 10:01:05.755497 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3511 10:01:05.759107 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 10:01:05.765690 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 10:01:05.769183 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 10:01:05.772120 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 10:01:05.779232 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3516 10:01:05.782430 0 15 24 | B1->B0 | 3232 2a2a | 1 0 | (1 1) (0 1)
3517 10:01:05.786014 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 1) (1 0)
3518 10:01:05.792903 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3519 10:01:05.796270 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3520 10:01:05.799573 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 10:01:05.805789 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 10:01:05.809086 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 10:01:05.812429 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 10:01:05.819257 1 0 24 | B1->B0 | 2626 4141 | 0 0 | (0 0) (0 0)
3525 10:01:05.822787 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3526 10:01:05.825708 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 10:01:05.832330 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 10:01:05.835795 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 10:01:05.839034 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 10:01:05.842381 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 10:01:05.849290 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3532 10:01:05.852526 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3533 10:01:05.855964 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3534 10:01:05.862832 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 10:01:05.865645 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 10:01:05.869358 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 10:01:05.875730 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 10:01:05.879292 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 10:01:05.882767 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 10:01:05.889410 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 10:01:05.892594 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 10:01:05.896171 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 10:01:05.902490 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 10:01:05.906071 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 10:01:05.909552 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 10:01:05.912839 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 10:01:05.919490 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3548 10:01:05.922808 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3549 10:01:05.926161 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3550 10:01:05.929602 Total UI for P1: 0, mck2ui 16
3551 10:01:05.933169 best dqsien dly found for B0: ( 1, 3, 22)
3552 10:01:05.939487 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 10:01:05.939612 Total UI for P1: 0, mck2ui 16
3554 10:01:05.946512 best dqsien dly found for B1: ( 1, 3, 28)
3555 10:01:05.949279 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3556 10:01:05.953127 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3557 10:01:05.953233
3558 10:01:05.956211 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3559 10:01:05.959279 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3560 10:01:05.962776 [Gating] SW calibration Done
3561 10:01:05.962879 ==
3562 10:01:05.966057 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 10:01:05.969616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 10:01:05.969714 ==
3565 10:01:05.972694 RX Vref Scan: 0
3566 10:01:05.972789
3567 10:01:05.972851 RX Vref 0 -> 0, step: 1
3568 10:01:05.972923
3569 10:01:05.976152 RX Delay -40 -> 252, step: 8
3570 10:01:05.979596 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3571 10:01:05.985986 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3572 10:01:05.989538 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3573 10:01:05.993122 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3574 10:01:05.996093 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3575 10:01:05.999867 iDelay=200, Bit 5, Center 123 (56 ~ 191) 136
3576 10:01:06.006459 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3577 10:01:06.009566 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3578 10:01:06.012914 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3579 10:01:06.016406 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3580 10:01:06.019966 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3581 10:01:06.023157 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3582 10:01:06.030143 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3583 10:01:06.033229 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3584 10:01:06.036348 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3585 10:01:06.039751 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3586 10:01:06.039831 ==
3587 10:01:06.043434 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 10:01:06.049714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 10:01:06.049805 ==
3590 10:01:06.049868 DQS Delay:
3591 10:01:06.053128 DQS0 = 0, DQS1 = 0
3592 10:01:06.053203 DQM Delay:
3593 10:01:06.053272 DQM0 = 114, DQM1 = 110
3594 10:01:06.056746 DQ Delay:
3595 10:01:06.060241 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3596 10:01:06.063019 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3597 10:01:06.066565 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =99
3598 10:01:06.069934 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3599 10:01:06.070033
3600 10:01:06.070131
3601 10:01:06.070220 ==
3602 10:01:06.073262 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 10:01:06.076190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 10:01:06.076296 ==
3605 10:01:06.080009
3606 10:01:06.080082
3607 10:01:06.080185 TX Vref Scan disable
3608 10:01:06.083164 == TX Byte 0 ==
3609 10:01:06.086933 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3610 10:01:06.089839 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3611 10:01:06.092940 == TX Byte 1 ==
3612 10:01:06.096579 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3613 10:01:06.099557 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3614 10:01:06.099664 ==
3615 10:01:06.103002 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 10:01:06.109534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 10:01:06.109608 ==
3618 10:01:06.120462 TX Vref=22, minBit 1, minWin=25, winSum=417
3619 10:01:06.123652 TX Vref=24, minBit 0, minWin=26, winSum=425
3620 10:01:06.127342 TX Vref=26, minBit 0, minWin=26, winSum=429
3621 10:01:06.131005 TX Vref=28, minBit 1, minWin=26, winSum=430
3622 10:01:06.134240 TX Vref=30, minBit 4, minWin=26, winSum=434
3623 10:01:06.137474 TX Vref=32, minBit 0, minWin=26, winSum=433
3624 10:01:06.144417 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 30
3625 10:01:06.144498
3626 10:01:06.147738 Final TX Range 1 Vref 30
3627 10:01:06.147846
3628 10:01:06.147911 ==
3629 10:01:06.151247 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 10:01:06.154121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 10:01:06.154227 ==
3632 10:01:06.154318
3633 10:01:06.154404
3634 10:01:06.157548 TX Vref Scan disable
3635 10:01:06.161148 == TX Byte 0 ==
3636 10:01:06.164111 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3637 10:01:06.167477 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3638 10:01:06.171116 == TX Byte 1 ==
3639 10:01:06.174591 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3640 10:01:06.177680 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3641 10:01:06.177795
3642 10:01:06.181045 [DATLAT]
3643 10:01:06.181132 Freq=1200, CH1 RK1
3644 10:01:06.181193
3645 10:01:06.184057 DATLAT Default: 0xd
3646 10:01:06.184136 0, 0xFFFF, sum = 0
3647 10:01:06.187705 1, 0xFFFF, sum = 0
3648 10:01:06.187777 2, 0xFFFF, sum = 0
3649 10:01:06.191252 3, 0xFFFF, sum = 0
3650 10:01:06.191350 4, 0xFFFF, sum = 0
3651 10:01:06.194362 5, 0xFFFF, sum = 0
3652 10:01:06.194472 6, 0xFFFF, sum = 0
3653 10:01:06.197689 7, 0xFFFF, sum = 0
3654 10:01:06.197793 8, 0xFFFF, sum = 0
3655 10:01:06.200900 9, 0xFFFF, sum = 0
3656 10:01:06.200981 10, 0xFFFF, sum = 0
3657 10:01:06.204209 11, 0xFFFF, sum = 0
3658 10:01:06.204285 12, 0x0, sum = 1
3659 10:01:06.207474 13, 0x0, sum = 2
3660 10:01:06.207549 14, 0x0, sum = 3
3661 10:01:06.210634 15, 0x0, sum = 4
3662 10:01:06.210718 best_step = 13
3663 10:01:06.210780
3664 10:01:06.210839 ==
3665 10:01:06.214313 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 10:01:06.220658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 10:01:06.220776 ==
3668 10:01:06.220841 RX Vref Scan: 0
3669 10:01:06.220902
3670 10:01:06.224175 RX Vref 0 -> 0, step: 1
3671 10:01:06.224254
3672 10:01:06.227857 RX Delay -21 -> 252, step: 4
3673 10:01:06.231194 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3674 10:01:06.234177 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3675 10:01:06.240744 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3676 10:01:06.244223 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3677 10:01:06.247584 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3678 10:01:06.250664 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3679 10:01:06.254031 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3680 10:01:06.257444 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3681 10:01:06.264671 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3682 10:01:06.267459 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3683 10:01:06.271009 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3684 10:01:06.274400 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3685 10:01:06.278090 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3686 10:01:06.284517 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3687 10:01:06.287904 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3688 10:01:06.290775 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3689 10:01:06.290846 ==
3690 10:01:06.294335 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 10:01:06.297715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 10:01:06.297795 ==
3693 10:01:06.300905 DQS Delay:
3694 10:01:06.300981 DQS0 = 0, DQS1 = 0
3695 10:01:06.304423 DQM Delay:
3696 10:01:06.304494 DQM0 = 113, DQM1 = 109
3697 10:01:06.307914 DQ Delay:
3698 10:01:06.311273 DQ0 =112, DQ1 =110, DQ2 =106, DQ3 =112
3699 10:01:06.314276 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3700 10:01:06.317607 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3701 10:01:06.321274 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3702 10:01:06.321342
3703 10:01:06.321405
3704 10:01:06.327513 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc03, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 411 ps
3705 10:01:06.331092 CH1 RK1: MR19=304, MR18=FC03
3706 10:01:06.337899 CH1_RK1: MR19=0x304, MR18=0xFC03, DQSOSC=408, MR23=63, INC=39, DEC=26
3707 10:01:06.341194 [RxdqsGatingPostProcess] freq 1200
3708 10:01:06.347566 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3709 10:01:06.347648 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 10:01:06.350917 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 10:01:06.354146 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 10:01:06.358003 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 10:01:06.361161 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 10:01:06.364409 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 10:01:06.367941 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 10:01:06.371180 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 10:01:06.374519 Pre-setting of DQS Precalculation
3718 10:01:06.377926 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3719 10:01:06.387886 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3720 10:01:06.394958 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3721 10:01:06.395033
3722 10:01:06.395098
3723 10:01:06.397986 [Calibration Summary] 2400 Mbps
3724 10:01:06.398077 CH 0, Rank 0
3725 10:01:06.401443 SW Impedance : PASS
3726 10:01:06.401515 DUTY Scan : NO K
3727 10:01:06.404800 ZQ Calibration : PASS
3728 10:01:06.407783 Jitter Meter : NO K
3729 10:01:06.407868 CBT Training : PASS
3730 10:01:06.411301 Write leveling : PASS
3731 10:01:06.414914 RX DQS gating : PASS
3732 10:01:06.414986 RX DQ/DQS(RDDQC) : PASS
3733 10:01:06.417792 TX DQ/DQS : PASS
3734 10:01:06.421313 RX DATLAT : PASS
3735 10:01:06.421383 RX DQ/DQS(Engine): PASS
3736 10:01:06.424621 TX OE : NO K
3737 10:01:06.424733 All Pass.
3738 10:01:06.424793
3739 10:01:06.424849 CH 0, Rank 1
3740 10:01:06.427753 SW Impedance : PASS
3741 10:01:06.431338 DUTY Scan : NO K
3742 10:01:06.431410 ZQ Calibration : PASS
3743 10:01:06.435013 Jitter Meter : NO K
3744 10:01:06.438261 CBT Training : PASS
3745 10:01:06.438350 Write leveling : PASS
3746 10:01:06.441412 RX DQS gating : PASS
3747 10:01:06.444432 RX DQ/DQS(RDDQC) : PASS
3748 10:01:06.444521 TX DQ/DQS : PASS
3749 10:01:06.448109 RX DATLAT : PASS
3750 10:01:06.451058 RX DQ/DQS(Engine): PASS
3751 10:01:06.451134 TX OE : NO K
3752 10:01:06.454666 All Pass.
3753 10:01:06.454740
3754 10:01:06.454801 CH 1, Rank 0
3755 10:01:06.457996 SW Impedance : PASS
3756 10:01:06.458066 DUTY Scan : NO K
3757 10:01:06.461400 ZQ Calibration : PASS
3758 10:01:06.464918 Jitter Meter : NO K
3759 10:01:06.464996 CBT Training : PASS
3760 10:01:06.468089 Write leveling : PASS
3761 10:01:06.468196 RX DQS gating : PASS
3762 10:01:06.471266 RX DQ/DQS(RDDQC) : PASS
3763 10:01:06.474870 TX DQ/DQS : PASS
3764 10:01:06.474950 RX DATLAT : PASS
3765 10:01:06.478131 RX DQ/DQS(Engine): PASS
3766 10:01:06.481494 TX OE : NO K
3767 10:01:06.481575 All Pass.
3768 10:01:06.481638
3769 10:01:06.481696 CH 1, Rank 1
3770 10:01:06.484563 SW Impedance : PASS
3771 10:01:06.488083 DUTY Scan : NO K
3772 10:01:06.488167 ZQ Calibration : PASS
3773 10:01:06.491863 Jitter Meter : NO K
3774 10:01:06.494659 CBT Training : PASS
3775 10:01:06.494731 Write leveling : PASS
3776 10:01:06.498114 RX DQS gating : PASS
3777 10:01:06.501772 RX DQ/DQS(RDDQC) : PASS
3778 10:01:06.501844 TX DQ/DQS : PASS
3779 10:01:06.504956 RX DATLAT : PASS
3780 10:01:06.505028 RX DQ/DQS(Engine): PASS
3781 10:01:06.508321 TX OE : NO K
3782 10:01:06.508394 All Pass.
3783 10:01:06.508458
3784 10:01:06.511258 DramC Write-DBI off
3785 10:01:06.514799 PER_BANK_REFRESH: Hybrid Mode
3786 10:01:06.514870 TX_TRACKING: ON
3787 10:01:06.524671 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3788 10:01:06.528267 [FAST_K] Save calibration result to emmc
3789 10:01:06.531717 dramc_set_vcore_voltage set vcore to 650000
3790 10:01:06.534582 Read voltage for 600, 5
3791 10:01:06.534688 Vio18 = 0
3792 10:01:06.538308 Vcore = 650000
3793 10:01:06.538377 Vdram = 0
3794 10:01:06.538437 Vddq = 0
3795 10:01:06.538498 Vmddr = 0
3796 10:01:06.544542 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3797 10:01:06.548006 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3798 10:01:06.551667 MEM_TYPE=3, freq_sel=19
3799 10:01:06.555002 sv_algorithm_assistance_LP4_1600
3800 10:01:06.558496 ============ PULL DRAM RESETB DOWN ============
3801 10:01:06.561272 ========== PULL DRAM RESETB DOWN end =========
3802 10:01:06.568506 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3803 10:01:06.571766 ===================================
3804 10:01:06.574761 LPDDR4 DRAM CONFIGURATION
3805 10:01:06.578040 ===================================
3806 10:01:06.578219 EX_ROW_EN[0] = 0x0
3807 10:01:06.581476 EX_ROW_EN[1] = 0x0
3808 10:01:06.581602 LP4Y_EN = 0x0
3809 10:01:06.584825 WORK_FSP = 0x0
3810 10:01:06.584905 WL = 0x2
3811 10:01:06.588370 RL = 0x2
3812 10:01:06.588450 BL = 0x2
3813 10:01:06.591717 RPST = 0x0
3814 10:01:06.591797 RD_PRE = 0x0
3815 10:01:06.594966 WR_PRE = 0x1
3816 10:01:06.595046 WR_PST = 0x0
3817 10:01:06.598439 DBI_WR = 0x0
3818 10:01:06.598519 DBI_RD = 0x0
3819 10:01:06.602049 OTF = 0x1
3820 10:01:06.604965 ===================================
3821 10:01:06.608396 ===================================
3822 10:01:06.608477 ANA top config
3823 10:01:06.612038 ===================================
3824 10:01:06.615380 DLL_ASYNC_EN = 0
3825 10:01:06.618919 ALL_SLAVE_EN = 1
3826 10:01:06.621665 NEW_RANK_MODE = 1
3827 10:01:06.621740 DLL_IDLE_MODE = 1
3828 10:01:06.625411 LP45_APHY_COMB_EN = 1
3829 10:01:06.628214 TX_ODT_DIS = 1
3830 10:01:06.631622 NEW_8X_MODE = 1
3831 10:01:06.635151 ===================================
3832 10:01:06.638757 ===================================
3833 10:01:06.641634 data_rate = 1200
3834 10:01:06.641715 CKR = 1
3835 10:01:06.645257 DQ_P2S_RATIO = 8
3836 10:01:06.648302 ===================================
3837 10:01:06.651707 CA_P2S_RATIO = 8
3838 10:01:06.655181 DQ_CA_OPEN = 0
3839 10:01:06.658657 DQ_SEMI_OPEN = 0
3840 10:01:06.658737 CA_SEMI_OPEN = 0
3841 10:01:06.661685 CA_FULL_RATE = 0
3842 10:01:06.665129 DQ_CKDIV4_EN = 1
3843 10:01:06.668602 CA_CKDIV4_EN = 1
3844 10:01:06.672293 CA_PREDIV_EN = 0
3845 10:01:06.675023 PH8_DLY = 0
3846 10:01:06.675103 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3847 10:01:06.678692 DQ_AAMCK_DIV = 4
3848 10:01:06.681849 CA_AAMCK_DIV = 4
3849 10:01:06.684895 CA_ADMCK_DIV = 4
3850 10:01:06.688639 DQ_TRACK_CA_EN = 0
3851 10:01:06.692021 CA_PICK = 600
3852 10:01:06.692101 CA_MCKIO = 600
3853 10:01:06.695496 MCKIO_SEMI = 0
3854 10:01:06.698690 PLL_FREQ = 2288
3855 10:01:06.701759 DQ_UI_PI_RATIO = 32
3856 10:01:06.705058 CA_UI_PI_RATIO = 0
3857 10:01:06.708692 ===================================
3858 10:01:06.711814 ===================================
3859 10:01:06.715184 memory_type:LPDDR4
3860 10:01:06.715258 GP_NUM : 10
3861 10:01:06.718641 SRAM_EN : 1
3862 10:01:06.718730 MD32_EN : 0
3863 10:01:06.721922 ===================================
3864 10:01:06.725144 [ANA_INIT] >>>>>>>>>>>>>>
3865 10:01:06.728427 <<<<<< [CONFIGURE PHASE]: ANA_TX
3866 10:01:06.731946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3867 10:01:06.735124 ===================================
3868 10:01:06.738372 data_rate = 1200,PCW = 0X5800
3869 10:01:06.742206 ===================================
3870 10:01:06.745111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3871 10:01:06.748592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 10:01:06.755630 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 10:01:06.758307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3874 10:01:06.765389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3875 10:01:06.768322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3876 10:01:06.768402 [ANA_INIT] flow start
3877 10:01:06.772467 [ANA_INIT] PLL >>>>>>>>
3878 10:01:06.775319 [ANA_INIT] PLL <<<<<<<<
3879 10:01:06.775399 [ANA_INIT] MIDPI >>>>>>>>
3880 10:01:06.778765 [ANA_INIT] MIDPI <<<<<<<<
3881 10:01:06.782234 [ANA_INIT] DLL >>>>>>>>
3882 10:01:06.782316 [ANA_INIT] flow end
3883 10:01:06.785594 ============ LP4 DIFF to SE enter ============
3884 10:01:06.792179 ============ LP4 DIFF to SE exit ============
3885 10:01:06.792256 [ANA_INIT] <<<<<<<<<<<<<
3886 10:01:06.795141 [Flow] Enable top DCM control >>>>>
3887 10:01:06.798768 [Flow] Enable top DCM control <<<<<
3888 10:01:06.802159 Enable DLL master slave shuffle
3889 10:01:06.808854 ==============================================================
3890 10:01:06.808957 Gating Mode config
3891 10:01:06.815388 ==============================================================
3892 10:01:06.818604 Config description:
3893 10:01:06.825705 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3894 10:01:06.831984 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3895 10:01:06.838985 SELPH_MODE 0: By rank 1: By Phase
3896 10:01:06.845610 ==============================================================
3897 10:01:06.845686 GAT_TRACK_EN = 1
3898 10:01:06.849379 RX_GATING_MODE = 2
3899 10:01:06.852516 RX_GATING_TRACK_MODE = 2
3900 10:01:06.855973 SELPH_MODE = 1
3901 10:01:06.858823 PICG_EARLY_EN = 1
3902 10:01:06.862050 VALID_LAT_VALUE = 1
3903 10:01:06.868427 ==============================================================
3904 10:01:06.871885 Enter into Gating configuration >>>>
3905 10:01:06.875379 Exit from Gating configuration <<<<
3906 10:01:06.878828 Enter into DVFS_PRE_config >>>>>
3907 10:01:06.888708 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3908 10:01:06.891851 Exit from DVFS_PRE_config <<<<<
3909 10:01:06.895367 Enter into PICG configuration >>>>
3910 10:01:06.898747 Exit from PICG configuration <<<<
3911 10:01:06.901528 [RX_INPUT] configuration >>>>>
3912 10:01:06.901615 [RX_INPUT] configuration <<<<<
3913 10:01:06.908405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3914 10:01:06.915322 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3915 10:01:06.918361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3916 10:01:06.925120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3917 10:01:06.931848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 10:01:06.938373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 10:01:06.941785 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3920 10:01:06.945417 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3921 10:01:06.951873 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3922 10:01:06.955505 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3923 10:01:06.958481 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3924 10:01:06.965105 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 10:01:06.968461 ===================================
3926 10:01:06.968558 LPDDR4 DRAM CONFIGURATION
3927 10:01:06.972166 ===================================
3928 10:01:06.974971 EX_ROW_EN[0] = 0x0
3929 10:01:06.975067 EX_ROW_EN[1] = 0x0
3930 10:01:06.978391 LP4Y_EN = 0x0
3931 10:01:06.978488 WORK_FSP = 0x0
3932 10:01:06.981881 WL = 0x2
3933 10:01:06.981981 RL = 0x2
3934 10:01:06.985270 BL = 0x2
3935 10:01:06.985345 RPST = 0x0
3936 10:01:06.988791 RD_PRE = 0x0
3937 10:01:06.991706 WR_PRE = 0x1
3938 10:01:06.991804 WR_PST = 0x0
3939 10:01:06.995035 DBI_WR = 0x0
3940 10:01:06.995129 DBI_RD = 0x0
3941 10:01:06.998408 OTF = 0x1
3942 10:01:07.001745 ===================================
3943 10:01:07.005294 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3944 10:01:07.008901 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3945 10:01:07.011823 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 10:01:07.015190 ===================================
3947 10:01:07.018618 LPDDR4 DRAM CONFIGURATION
3948 10:01:07.022035 ===================================
3949 10:01:07.025193 EX_ROW_EN[0] = 0x10
3950 10:01:07.025269 EX_ROW_EN[1] = 0x0
3951 10:01:07.028847 LP4Y_EN = 0x0
3952 10:01:07.028919 WORK_FSP = 0x0
3953 10:01:07.032246 WL = 0x2
3954 10:01:07.032316 RL = 0x2
3955 10:01:07.035370 BL = 0x2
3956 10:01:07.035497 RPST = 0x0
3957 10:01:07.038480 RD_PRE = 0x0
3958 10:01:07.038574 WR_PRE = 0x1
3959 10:01:07.042287 WR_PST = 0x0
3960 10:01:07.042384 DBI_WR = 0x0
3961 10:01:07.045537 DBI_RD = 0x0
3962 10:01:07.045605 OTF = 0x1
3963 10:01:07.048919 ===================================
3964 10:01:07.055336 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3965 10:01:07.059728 nWR fixed to 30
3966 10:01:07.063233 [ModeRegInit_LP4] CH0 RK0
3967 10:01:07.063332 [ModeRegInit_LP4] CH0 RK1
3968 10:01:07.066593 [ModeRegInit_LP4] CH1 RK0
3969 10:01:07.070257 [ModeRegInit_LP4] CH1 RK1
3970 10:01:07.070329 match AC timing 17
3971 10:01:07.076761 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3972 10:01:07.080253 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3973 10:01:07.083631 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3974 10:01:07.090789 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3975 10:01:07.093803 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3976 10:01:07.093873 ==
3977 10:01:07.096929 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 10:01:07.100477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 10:01:07.100573 ==
3980 10:01:07.107048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3981 10:01:07.114276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3982 10:01:07.117042 [CA 0] Center 36 (6~66) winsize 61
3983 10:01:07.120619 [CA 1] Center 35 (5~66) winsize 62
3984 10:01:07.123669 [CA 2] Center 34 (4~65) winsize 62
3985 10:01:07.127197 [CA 3] Center 34 (4~65) winsize 62
3986 10:01:07.130345 [CA 4] Center 34 (4~64) winsize 61
3987 10:01:07.130439 [CA 5] Center 33 (3~64) winsize 62
3988 10:01:07.133987
3989 10:01:07.136903 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3990 10:01:07.136980
3991 10:01:07.140426 [CATrainingPosCal] consider 1 rank data
3992 10:01:07.143571 u2DelayCellTimex100 = 270/100 ps
3993 10:01:07.147040 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3994 10:01:07.150517 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3995 10:01:07.153886 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 10:01:07.157047 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3997 10:01:07.160373 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3998 10:01:07.163713 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 10:01:07.163817
4000 10:01:07.170224 CA PerBit enable=1, Macro0, CA PI delay=33
4001 10:01:07.170296
4002 10:01:07.170367 [CBTSetCACLKResult] CA Dly = 33
4003 10:01:07.173618 CS Dly: 5 (0~36)
4004 10:01:07.173686 ==
4005 10:01:07.176586 Dram Type= 6, Freq= 0, CH_0, rank 1
4006 10:01:07.179994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 10:01:07.180090 ==
4008 10:01:07.186542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 10:01:07.193514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4010 10:01:07.197021 [CA 0] Center 36 (6~66) winsize 61
4011 10:01:07.200017 [CA 1] Center 36 (6~66) winsize 61
4012 10:01:07.203393 [CA 2] Center 34 (4~65) winsize 62
4013 10:01:07.206835 [CA 3] Center 34 (4~64) winsize 61
4014 10:01:07.209896 [CA 4] Center 33 (3~64) winsize 62
4015 10:01:07.213810 [CA 5] Center 33 (3~64) winsize 62
4016 10:01:07.213891
4017 10:01:07.216745 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4018 10:01:07.216825
4019 10:01:07.219999 [CATrainingPosCal] consider 2 rank data
4020 10:01:07.223471 u2DelayCellTimex100 = 270/100 ps
4021 10:01:07.226887 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 10:01:07.230309 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4023 10:01:07.233684 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4024 10:01:07.236802 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4025 10:01:07.240009 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4026 10:01:07.243008 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 10:01:07.243105
4028 10:01:07.249971 CA PerBit enable=1, Macro0, CA PI delay=33
4029 10:01:07.250069
4030 10:01:07.253382 [CBTSetCACLKResult] CA Dly = 33
4031 10:01:07.253457 CS Dly: 5 (0~36)
4032 10:01:07.253530
4033 10:01:07.256475 ----->DramcWriteLeveling(PI) begin...
4034 10:01:07.256590 ==
4035 10:01:07.260287 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 10:01:07.263464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 10:01:07.263542 ==
4038 10:01:07.266334 Write leveling (Byte 0): 33 => 33
4039 10:01:07.269491 Write leveling (Byte 1): 29 => 29
4040 10:01:07.273080 DramcWriteLeveling(PI) end<-----
4041 10:01:07.273149
4042 10:01:07.273209 ==
4043 10:01:07.276426 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 10:01:07.282983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 10:01:07.283072 ==
4046 10:01:07.283134 [Gating] SW mode calibration
4047 10:01:07.293642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4048 10:01:07.296400 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4049 10:01:07.300083 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 10:01:07.307072 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 10:01:07.309918 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 10:01:07.313308 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4053 10:01:07.319906 0 9 16 | B1->B0 | 3131 2828 | 1 0 | (1 0) (0 0)
4054 10:01:07.323477 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 10:01:07.326784 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 10:01:07.330504 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 10:01:07.337026 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 10:01:07.339919 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 10:01:07.343610 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 10:01:07.350082 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4061 10:01:07.354020 0 10 16 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (0 0)
4062 10:01:07.357021 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
4063 10:01:07.364050 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 10:01:07.367120 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 10:01:07.370599 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 10:01:07.376902 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 10:01:07.380461 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 10:01:07.383867 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 10:01:07.390269 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 10:01:07.393872 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4071 10:01:07.397283 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 10:01:07.403756 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 10:01:07.407500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 10:01:07.410425 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 10:01:07.413952 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 10:01:07.420892 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 10:01:07.423976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 10:01:07.427614 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 10:01:07.434110 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 10:01:07.437513 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 10:01:07.440395 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 10:01:07.447117 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 10:01:07.450925 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 10:01:07.454004 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 10:01:07.460514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4086 10:01:07.463784 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 10:01:07.467116 Total UI for P1: 0, mck2ui 16
4088 10:01:07.470630 best dqsien dly found for B0: ( 0, 13, 16)
4089 10:01:07.474097 Total UI for P1: 0, mck2ui 16
4090 10:01:07.477099 best dqsien dly found for B1: ( 0, 13, 16)
4091 10:01:07.480605 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4092 10:01:07.484300 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4093 10:01:07.484382
4094 10:01:07.487114 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4095 10:01:07.490623 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4096 10:01:07.494076 [Gating] SW calibration Done
4097 10:01:07.494178 ==
4098 10:01:07.497596 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 10:01:07.500886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 10:01:07.500969 ==
4101 10:01:07.504026 RX Vref Scan: 0
4102 10:01:07.504108
4103 10:01:07.507438 RX Vref 0 -> 0, step: 1
4104 10:01:07.507519
4105 10:01:07.507583 RX Delay -230 -> 252, step: 16
4106 10:01:07.514342 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4107 10:01:07.517326 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4108 10:01:07.520886 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4109 10:01:07.524237 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4110 10:01:07.530948 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4111 10:01:07.534467 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4112 10:01:07.537834 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4113 10:01:07.541352 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4114 10:01:07.544228 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4115 10:01:07.551067 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4116 10:01:07.554462 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4117 10:01:07.557460 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4118 10:01:07.560938 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4119 10:01:07.567843 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4120 10:01:07.570735 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4121 10:01:07.574243 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4122 10:01:07.574317 ==
4123 10:01:07.577714 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 10:01:07.580785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 10:01:07.580862 ==
4126 10:01:07.584576 DQS Delay:
4127 10:01:07.584651 DQS0 = 0, DQS1 = 0
4128 10:01:07.587467 DQM Delay:
4129 10:01:07.587539 DQM0 = 43, DQM1 = 35
4130 10:01:07.587599 DQ Delay:
4131 10:01:07.590744 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4132 10:01:07.594295 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4133 10:01:07.597713 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4134 10:01:07.601168 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4135 10:01:07.601242
4136 10:01:07.601307
4137 10:01:07.604371 ==
4138 10:01:07.604444 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 10:01:07.610791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 10:01:07.610870 ==
4141 10:01:07.610934
4142 10:01:07.610993
4143 10:01:07.614159 TX Vref Scan disable
4144 10:01:07.614227 == TX Byte 0 ==
4145 10:01:07.617796 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4146 10:01:07.624227 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4147 10:01:07.624301 == TX Byte 1 ==
4148 10:01:07.627609 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4149 10:01:07.634024 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4150 10:01:07.634099 ==
4151 10:01:07.637673 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 10:01:07.641177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 10:01:07.641255 ==
4154 10:01:07.641346
4155 10:01:07.641431
4156 10:01:07.643972 TX Vref Scan disable
4157 10:01:07.647741 == TX Byte 0 ==
4158 10:01:07.650925 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4159 10:01:07.654005 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4160 10:01:07.657898 == TX Byte 1 ==
4161 10:01:07.661361 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4162 10:01:07.664356 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4163 10:01:07.664422
4164 10:01:07.667655 [DATLAT]
4165 10:01:07.667726 Freq=600, CH0 RK0
4166 10:01:07.667790
4167 10:01:07.671395 DATLAT Default: 0x9
4168 10:01:07.671470 0, 0xFFFF, sum = 0
4169 10:01:07.674065 1, 0xFFFF, sum = 0
4170 10:01:07.674133 2, 0xFFFF, sum = 0
4171 10:01:07.677365 3, 0xFFFF, sum = 0
4172 10:01:07.677447 4, 0xFFFF, sum = 0
4173 10:01:07.680941 5, 0xFFFF, sum = 0
4174 10:01:07.681010 6, 0xFFFF, sum = 0
4175 10:01:07.684215 7, 0xFFFF, sum = 0
4176 10:01:07.684283 8, 0x0, sum = 1
4177 10:01:07.687660 9, 0x0, sum = 2
4178 10:01:07.687760 10, 0x0, sum = 3
4179 10:01:07.691050 11, 0x0, sum = 4
4180 10:01:07.691139 best_step = 9
4181 10:01:07.691215
4182 10:01:07.691272 ==
4183 10:01:07.694546 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 10:01:07.697624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 10:01:07.697708 ==
4186 10:01:07.701142 RX Vref Scan: 1
4187 10:01:07.701210
4188 10:01:07.704127 RX Vref 0 -> 0, step: 1
4189 10:01:07.704198
4190 10:01:07.704262 RX Delay -195 -> 252, step: 8
4191 10:01:07.704320
4192 10:01:07.707635 Set Vref, RX VrefLevel [Byte0]: 53
4193 10:01:07.710922 [Byte1]: 56
4194 10:01:07.715851
4195 10:01:07.715924 Final RX Vref Byte 0 = 53 to rank0
4196 10:01:07.719011 Final RX Vref Byte 1 = 56 to rank0
4197 10:01:07.722414 Final RX Vref Byte 0 = 53 to rank1
4198 10:01:07.725641 Final RX Vref Byte 1 = 56 to rank1==
4199 10:01:07.729318 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 10:01:07.735686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 10:01:07.735789 ==
4202 10:01:07.735887 DQS Delay:
4203 10:01:07.735982 DQS0 = 0, DQS1 = 0
4204 10:01:07.739206 DQM Delay:
4205 10:01:07.739289 DQM0 = 42, DQM1 = 33
4206 10:01:07.742697 DQ Delay:
4207 10:01:07.745503 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4208 10:01:07.745602 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4209 10:01:07.749063 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4210 10:01:07.752513 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4211 10:01:07.755710
4212 10:01:07.755789
4213 10:01:07.762214 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4214 10:01:07.765717 CH0 RK0: MR19=808, MR18=3F1F
4215 10:01:07.772396 CH0_RK0: MR19=0x808, MR18=0x3F1F, DQSOSC=397, MR23=63, INC=166, DEC=110
4216 10:01:07.772471
4217 10:01:07.775439 ----->DramcWriteLeveling(PI) begin...
4218 10:01:07.775511 ==
4219 10:01:07.778930 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 10:01:07.782430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 10:01:07.782509 ==
4222 10:01:07.785411 Write leveling (Byte 0): 34 => 34
4223 10:01:07.788754 Write leveling (Byte 1): 31 => 31
4224 10:01:07.792156 DramcWriteLeveling(PI) end<-----
4225 10:01:07.792229
4226 10:01:07.792290 ==
4227 10:01:07.795745 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 10:01:07.799428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 10:01:07.799515 ==
4230 10:01:07.802286 [Gating] SW mode calibration
4231 10:01:07.809092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4232 10:01:07.815745 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4233 10:01:07.818733 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 10:01:07.822514 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 10:01:07.829112 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 10:01:07.832441 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4237 10:01:07.836090 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4238 10:01:07.842287 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 10:01:07.845753 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 10:01:07.849313 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 10:01:07.856147 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 10:01:07.858972 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 10:01:07.862435 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 10:01:07.869415 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4245 10:01:07.872356 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4246 10:01:07.875586 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 10:01:07.879087 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 10:01:07.885724 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 10:01:07.889012 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 10:01:07.892526 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 10:01:07.899257 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 10:01:07.902604 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4253 10:01:07.905653 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4254 10:01:07.912636 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 10:01:07.915790 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 10:01:07.919179 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 10:01:07.925682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 10:01:07.929145 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 10:01:07.932561 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 10:01:07.939240 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 10:01:07.942383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 10:01:07.945692 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 10:01:07.952462 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 10:01:07.955983 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 10:01:07.959588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 10:01:07.962375 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 10:01:07.969339 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 10:01:07.972612 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4269 10:01:07.976104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4270 10:01:07.979067 Total UI for P1: 0, mck2ui 16
4271 10:01:07.982942 best dqsien dly found for B0: ( 0, 13, 12)
4272 10:01:07.989328 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 10:01:07.989410 Total UI for P1: 0, mck2ui 16
4274 10:01:07.995701 best dqsien dly found for B1: ( 0, 13, 16)
4275 10:01:07.999409 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4276 10:01:08.003019 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4277 10:01:08.003101
4278 10:01:08.006085 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4279 10:01:08.009432 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4280 10:01:08.012500 [Gating] SW calibration Done
4281 10:01:08.012582 ==
4282 10:01:08.015759 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 10:01:08.019550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 10:01:08.019664 ==
4285 10:01:08.022699 RX Vref Scan: 0
4286 10:01:08.022780
4287 10:01:08.022844 RX Vref 0 -> 0, step: 1
4288 10:01:08.022904
4289 10:01:08.026015 RX Delay -230 -> 252, step: 16
4290 10:01:08.032611 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4291 10:01:08.036119 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4292 10:01:08.039231 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4293 10:01:08.042612 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4294 10:01:08.046084 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4295 10:01:08.052400 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4296 10:01:08.055751 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4297 10:01:08.059243 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4298 10:01:08.062387 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4299 10:01:08.066305 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4300 10:01:08.072578 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 10:01:08.075654 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4302 10:01:08.079341 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4303 10:01:08.082722 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4304 10:01:08.089518 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4305 10:01:08.093081 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4306 10:01:08.093180 ==
4307 10:01:08.095929 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 10:01:08.099445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 10:01:08.099575 ==
4310 10:01:08.102968 DQS Delay:
4311 10:01:08.103066 DQS0 = 0, DQS1 = 0
4312 10:01:08.103162 DQM Delay:
4313 10:01:08.105834 DQM0 = 41, DQM1 = 34
4314 10:01:08.105932 DQ Delay:
4315 10:01:08.109452 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4316 10:01:08.112637 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4317 10:01:08.116124 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4318 10:01:08.119611 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4319 10:01:08.119711
4320 10:01:08.119806
4321 10:01:08.119882 ==
4322 10:01:08.123034 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 10:01:08.129215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 10:01:08.129314 ==
4325 10:01:08.129411
4326 10:01:08.129487
4327 10:01:08.129576 TX Vref Scan disable
4328 10:01:08.132995 == TX Byte 0 ==
4329 10:01:08.136314 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4330 10:01:08.139731 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4331 10:01:08.142968 == TX Byte 1 ==
4332 10:01:08.146258 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4333 10:01:08.149918 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4334 10:01:08.153385 ==
4335 10:01:08.153483 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 10:01:08.159837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 10:01:08.159936 ==
4338 10:01:08.160034
4339 10:01:08.160110
4340 10:01:08.163189 TX Vref Scan disable
4341 10:01:08.163291 == TX Byte 0 ==
4342 10:01:08.169843 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4343 10:01:08.173200 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4344 10:01:08.173298 == TX Byte 1 ==
4345 10:01:08.179762 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4346 10:01:08.183352 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4347 10:01:08.183434
4348 10:01:08.183499 [DATLAT]
4349 10:01:08.186854 Freq=600, CH0 RK1
4350 10:01:08.186935
4351 10:01:08.186998 DATLAT Default: 0x9
4352 10:01:08.190096 0, 0xFFFF, sum = 0
4353 10:01:08.190179 1, 0xFFFF, sum = 0
4354 10:01:08.193539 2, 0xFFFF, sum = 0
4355 10:01:08.193621 3, 0xFFFF, sum = 0
4356 10:01:08.197125 4, 0xFFFF, sum = 0
4357 10:01:08.197208 5, 0xFFFF, sum = 0
4358 10:01:08.199940 6, 0xFFFF, sum = 0
4359 10:01:08.200054 7, 0xFFFF, sum = 0
4360 10:01:08.203589 8, 0x0, sum = 1
4361 10:01:08.203672 9, 0x0, sum = 2
4362 10:01:08.207148 10, 0x0, sum = 3
4363 10:01:08.207233 11, 0x0, sum = 4
4364 10:01:08.209942 best_step = 9
4365 10:01:08.210023
4366 10:01:08.210085 ==
4367 10:01:08.213488 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 10:01:08.216714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 10:01:08.216796 ==
4370 10:01:08.216880 RX Vref Scan: 0
4371 10:01:08.220296
4372 10:01:08.220376 RX Vref 0 -> 0, step: 1
4373 10:01:08.220440
4374 10:01:08.223513 RX Delay -179 -> 252, step: 8
4375 10:01:08.229913 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4376 10:01:08.233232 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4377 10:01:08.236786 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4378 10:01:08.239984 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4379 10:01:08.247156 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4380 10:01:08.250428 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4381 10:01:08.253264 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4382 10:01:08.256846 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4383 10:01:08.260417 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4384 10:01:08.266663 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4385 10:01:08.270157 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4386 10:01:08.273590 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4387 10:01:08.276919 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4388 10:01:08.283308 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4389 10:01:08.287086 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4390 10:01:08.290103 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4391 10:01:08.290178 ==
4392 10:01:08.293074 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 10:01:08.296238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 10:01:08.299579 ==
4395 10:01:08.299663 DQS Delay:
4396 10:01:08.299730 DQS0 = 0, DQS1 = 0
4397 10:01:08.303255 DQM Delay:
4398 10:01:08.303358 DQM0 = 39, DQM1 = 31
4399 10:01:08.306659 DQ Delay:
4400 10:01:08.309604 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4401 10:01:08.309680 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4402 10:01:08.313278 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4403 10:01:08.316446 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =40
4404 10:01:08.316532
4405 10:01:08.319939
4406 10:01:08.326318 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4407 10:01:08.329689 CH0 RK1: MR19=808, MR18=4B2D
4408 10:01:08.336257 CH0_RK1: MR19=0x808, MR18=0x4B2D, DQSOSC=395, MR23=63, INC=168, DEC=112
4409 10:01:08.339870 [RxdqsGatingPostProcess] freq 600
4410 10:01:08.343113 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 10:01:08.346574 Pre-setting of DQS Precalculation
4412 10:01:08.353335 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 10:01:08.353446 ==
4414 10:01:08.356425 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 10:01:08.360004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 10:01:08.360077 ==
4417 10:01:08.363349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 10:01:08.369730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4419 10:01:08.373470 [CA 0] Center 35 (5~65) winsize 61
4420 10:01:08.376951 [CA 1] Center 35 (5~65) winsize 61
4421 10:01:08.380494 [CA 2] Center 34 (4~65) winsize 62
4422 10:01:08.383541 [CA 3] Center 33 (3~64) winsize 62
4423 10:01:08.387028 [CA 4] Center 34 (3~65) winsize 63
4424 10:01:08.390412 [CA 5] Center 33 (3~64) winsize 62
4425 10:01:08.390486
4426 10:01:08.393753 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4427 10:01:08.393853
4428 10:01:08.397196 [CATrainingPosCal] consider 1 rank data
4429 10:01:08.400698 u2DelayCellTimex100 = 270/100 ps
4430 10:01:08.403717 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4431 10:01:08.407025 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4432 10:01:08.413615 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 10:01:08.416853 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 10:01:08.420379 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4435 10:01:08.423978 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 10:01:08.424059
4437 10:01:08.427415 CA PerBit enable=1, Macro0, CA PI delay=33
4438 10:01:08.427496
4439 10:01:08.430424 [CBTSetCACLKResult] CA Dly = 33
4440 10:01:08.430505 CS Dly: 3 (0~34)
4441 10:01:08.430569 ==
4442 10:01:08.433817 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 10:01:08.440821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 10:01:08.440928 ==
4445 10:01:08.443947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 10:01:08.450501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4447 10:01:08.453814 [CA 0] Center 35 (5~66) winsize 62
4448 10:01:08.457353 [CA 1] Center 35 (5~66) winsize 62
4449 10:01:08.460381 [CA 2] Center 34 (3~65) winsize 63
4450 10:01:08.463968 [CA 3] Center 33 (3~64) winsize 62
4451 10:01:08.467490 [CA 4] Center 34 (3~65) winsize 63
4452 10:01:08.470292 [CA 5] Center 33 (3~64) winsize 62
4453 10:01:08.470365
4454 10:01:08.473844 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4455 10:01:08.473915
4456 10:01:08.477363 [CATrainingPosCal] consider 2 rank data
4457 10:01:08.480271 u2DelayCellTimex100 = 270/100 ps
4458 10:01:08.483801 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4459 10:01:08.487178 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4460 10:01:08.493616 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 10:01:08.497724 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 10:01:08.500542 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4463 10:01:08.503972 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 10:01:08.504047
4465 10:01:08.507136 CA PerBit enable=1, Macro0, CA PI delay=33
4466 10:01:08.507236
4467 10:01:08.510303 [CBTSetCACLKResult] CA Dly = 33
4468 10:01:08.510377 CS Dly: 4 (0~36)
4469 10:01:08.510457
4470 10:01:08.513563 ----->DramcWriteLeveling(PI) begin...
4471 10:01:08.516901 ==
4472 10:01:08.516974 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 10:01:08.523888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 10:01:08.523981 ==
4475 10:01:08.527048 Write leveling (Byte 0): 28 => 28
4476 10:01:08.530562 Write leveling (Byte 1): 32 => 32
4477 10:01:08.530666 DramcWriteLeveling(PI) end<-----
4478 10:01:08.533872
4479 10:01:08.533965 ==
4480 10:01:08.536994 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 10:01:08.540285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 10:01:08.540363 ==
4483 10:01:08.543953 [Gating] SW mode calibration
4484 10:01:08.550264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 10:01:08.553776 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 10:01:08.560334 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 10:01:08.563779 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4488 10:01:08.567202 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4489 10:01:08.573566 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4490 10:01:08.576993 0 9 16 | B1->B0 | 2f2f 2828 | 1 1 | (1 0) (1 0)
4491 10:01:08.580527 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 10:01:08.586955 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 10:01:08.590618 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 10:01:08.594058 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4495 10:01:08.600515 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 10:01:08.604025 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4497 10:01:08.607099 0 10 12 | B1->B0 | 2a2a 2c2c | 0 0 | (1 1) (0 0)
4498 10:01:08.613837 0 10 16 | B1->B0 | 4242 4242 | 0 0 | (1 1) (1 1)
4499 10:01:08.616888 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 10:01:08.620230 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 10:01:08.623786 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 10:01:08.630488 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 10:01:08.633890 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 10:01:08.637149 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 10:01:08.643735 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 10:01:08.647047 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4507 10:01:08.650363 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 10:01:08.657345 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 10:01:08.660321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 10:01:08.663876 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 10:01:08.670143 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 10:01:08.673953 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 10:01:08.677301 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 10:01:08.683609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 10:01:08.687130 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 10:01:08.690997 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 10:01:08.696936 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 10:01:08.700555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 10:01:08.704035 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 10:01:08.710415 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 10:01:08.713863 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 10:01:08.717305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 10:01:08.720260 Total UI for P1: 0, mck2ui 16
4524 10:01:08.723342 best dqsien dly found for B0: ( 0, 13, 14)
4525 10:01:08.727090 Total UI for P1: 0, mck2ui 16
4526 10:01:08.730345 best dqsien dly found for B1: ( 0, 13, 14)
4527 10:01:08.733345 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4528 10:01:08.736726 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4529 10:01:08.736824
4530 10:01:08.743300 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4531 10:01:08.746514 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4532 10:01:08.746612 [Gating] SW calibration Done
4533 10:01:08.750308 ==
4534 10:01:08.750380 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 10:01:08.756363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 10:01:08.756463 ==
4537 10:01:08.756566 RX Vref Scan: 0
4538 10:01:08.756678
4539 10:01:08.759777 RX Vref 0 -> 0, step: 1
4540 10:01:08.759873
4541 10:01:08.763070 RX Delay -230 -> 252, step: 16
4542 10:01:08.766654 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4543 10:01:08.770129 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4544 10:01:08.776786 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4545 10:01:08.780411 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4546 10:01:08.783743 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4547 10:01:08.786534 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4548 10:01:08.793092 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4549 10:01:08.796546 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4550 10:01:08.799635 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4551 10:01:08.802774 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4552 10:01:08.806368 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4553 10:01:08.812981 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4554 10:01:08.816515 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4555 10:01:08.819437 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4556 10:01:08.822901 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4557 10:01:08.829617 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4558 10:01:08.829695 ==
4559 10:01:08.833269 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 10:01:08.836100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 10:01:08.836174 ==
4562 10:01:08.836241 DQS Delay:
4563 10:01:08.839838 DQS0 = 0, DQS1 = 0
4564 10:01:08.839922 DQM Delay:
4565 10:01:08.843359 DQM0 = 44, DQM1 = 35
4566 10:01:08.843458 DQ Delay:
4567 10:01:08.846780 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4568 10:01:08.849685 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4569 10:01:08.853027 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4570 10:01:08.856533 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4571 10:01:08.856614
4572 10:01:08.856734
4573 10:01:08.856823 ==
4574 10:01:08.860120 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 10:01:08.863083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 10:01:08.863180 ==
4577 10:01:08.863251
4578 10:01:08.863310
4579 10:01:08.866377 TX Vref Scan disable
4580 10:01:08.869832 == TX Byte 0 ==
4581 10:01:08.873379 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4582 10:01:08.876384 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4583 10:01:08.879890 == TX Byte 1 ==
4584 10:01:08.883260 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4585 10:01:08.886599 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4586 10:01:08.886713 ==
4587 10:01:08.890082 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 10:01:08.896515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 10:01:08.896624 ==
4590 10:01:08.896743
4591 10:01:08.896818
4592 10:01:08.896879 TX Vref Scan disable
4593 10:01:08.900650 == TX Byte 0 ==
4594 10:01:08.904717 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4595 10:01:08.907584 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4596 10:01:08.910835 == TX Byte 1 ==
4597 10:01:08.914065 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4598 10:01:08.917359 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4599 10:01:08.920913
4600 10:01:08.920991 [DATLAT]
4601 10:01:08.921056 Freq=600, CH1 RK0
4602 10:01:08.921125
4603 10:01:08.924084 DATLAT Default: 0x9
4604 10:01:08.924184 0, 0xFFFF, sum = 0
4605 10:01:08.927858 1, 0xFFFF, sum = 0
4606 10:01:08.927959 2, 0xFFFF, sum = 0
4607 10:01:08.931286 3, 0xFFFF, sum = 0
4608 10:01:08.931384 4, 0xFFFF, sum = 0
4609 10:01:08.934680 5, 0xFFFF, sum = 0
4610 10:01:08.934791 6, 0xFFFF, sum = 0
4611 10:01:08.937882 7, 0xFFFF, sum = 0
4612 10:01:08.937995 8, 0x0, sum = 1
4613 10:01:08.941116 9, 0x0, sum = 2
4614 10:01:08.941202 10, 0x0, sum = 3
4615 10:01:08.944555 11, 0x0, sum = 4
4616 10:01:08.944639 best_step = 9
4617 10:01:08.944718
4618 10:01:08.944781 ==
4619 10:01:08.947448 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 10:01:08.954133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 10:01:08.954219 ==
4622 10:01:08.954286 RX Vref Scan: 1
4623 10:01:08.954348
4624 10:01:08.957475 RX Vref 0 -> 0, step: 1
4625 10:01:08.957548
4626 10:01:08.961255 RX Delay -195 -> 252, step: 8
4627 10:01:08.961325
4628 10:01:08.964078 Set Vref, RX VrefLevel [Byte0]: 57
4629 10:01:08.967480 [Byte1]: 52
4630 10:01:08.967583
4631 10:01:08.971107 Final RX Vref Byte 0 = 57 to rank0
4632 10:01:08.974279 Final RX Vref Byte 1 = 52 to rank0
4633 10:01:08.977705 Final RX Vref Byte 0 = 57 to rank1
4634 10:01:08.980981 Final RX Vref Byte 1 = 52 to rank1==
4635 10:01:08.984486 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 10:01:08.987537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 10:01:08.987649 ==
4638 10:01:08.990770 DQS Delay:
4639 10:01:08.990846 DQS0 = 0, DQS1 = 0
4640 10:01:08.990909 DQM Delay:
4641 10:01:08.994510 DQM0 = 40, DQM1 = 33
4642 10:01:08.994608 DQ Delay:
4643 10:01:08.997612 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4644 10:01:09.000986 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4645 10:01:09.004445 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4646 10:01:09.007983 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4647 10:01:09.008066
4648 10:01:09.008154
4649 10:01:09.017566 [DQSOSCAuto] RK0, (LSB)MR18= 0x480e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4650 10:01:09.017646 CH1 RK0: MR19=808, MR18=480E
4651 10:01:09.024264 CH1_RK0: MR19=0x808, MR18=0x480E, DQSOSC=396, MR23=63, INC=167, DEC=111
4652 10:01:09.024342
4653 10:01:09.027307 ----->DramcWriteLeveling(PI) begin...
4654 10:01:09.027389 ==
4655 10:01:09.031245 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 10:01:09.037770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 10:01:09.037872 ==
4658 10:01:09.041353 Write leveling (Byte 0): 32 => 32
4659 10:01:09.044373 Write leveling (Byte 1): 32 => 32
4660 10:01:09.044456 DramcWriteLeveling(PI) end<-----
4661 10:01:09.044547
4662 10:01:09.047901 ==
4663 10:01:09.051070 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 10:01:09.054067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 10:01:09.054167 ==
4666 10:01:09.057817 [Gating] SW mode calibration
4667 10:01:09.064599 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4668 10:01:09.067430 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4669 10:01:09.074353 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4670 10:01:09.077789 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4671 10:01:09.081238 0 9 8 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
4672 10:01:09.087706 0 9 12 | B1->B0 | 3232 2d2d | 1 1 | (1 1) (1 0)
4673 10:01:09.090668 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4674 10:01:09.094355 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 10:01:09.100930 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 10:01:09.104086 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 10:01:09.107659 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 10:01:09.114195 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 10:01:09.117662 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 10:01:09.121009 0 10 12 | B1->B0 | 3232 3d3d | 0 0 | (1 1) (0 0)
4681 10:01:09.127101 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 10:01:09.130513 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 10:01:09.133942 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 10:01:09.137367 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 10:01:09.144329 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 10:01:09.147283 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 10:01:09.150799 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4688 10:01:09.157813 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4689 10:01:09.161016 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 10:01:09.164254 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 10:01:09.171035 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 10:01:09.174100 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 10:01:09.177513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 10:01:09.184213 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 10:01:09.187819 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 10:01:09.190772 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 10:01:09.197765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 10:01:09.201267 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 10:01:09.204098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 10:01:09.211143 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 10:01:09.214211 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 10:01:09.217833 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 10:01:09.220658 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 10:01:09.227810 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4705 10:01:09.231255 Total UI for P1: 0, mck2ui 16
4706 10:01:09.234713 best dqsien dly found for B0: ( 0, 13, 10)
4707 10:01:09.237690 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 10:01:09.241405 Total UI for P1: 0, mck2ui 16
4709 10:01:09.244275 best dqsien dly found for B1: ( 0, 13, 14)
4710 10:01:09.247492 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4711 10:01:09.251178 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4712 10:01:09.251279
4713 10:01:09.254615 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4714 10:01:09.257459 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4715 10:01:09.260934 [Gating] SW calibration Done
4716 10:01:09.261010 ==
4717 10:01:09.264581 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 10:01:09.271241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 10:01:09.271318 ==
4720 10:01:09.271381 RX Vref Scan: 0
4721 10:01:09.271449
4722 10:01:09.274495 RX Vref 0 -> 0, step: 1
4723 10:01:09.274570
4724 10:01:09.277895 RX Delay -230 -> 252, step: 16
4725 10:01:09.280957 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4726 10:01:09.284555 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4727 10:01:09.288099 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4728 10:01:09.294562 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4729 10:01:09.298084 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4730 10:01:09.301052 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4731 10:01:09.304486 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4732 10:01:09.308457 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4733 10:01:09.314532 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4734 10:01:09.317875 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4735 10:01:09.320865 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4736 10:01:09.324408 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4737 10:01:09.330772 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4738 10:01:09.334142 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4739 10:01:09.337729 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4740 10:01:09.341056 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4741 10:01:09.341136 ==
4742 10:01:09.344467 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 10:01:09.350746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 10:01:09.350849 ==
4745 10:01:09.350945 DQS Delay:
4746 10:01:09.354837 DQS0 = 0, DQS1 = 0
4747 10:01:09.354940 DQM Delay:
4748 10:01:09.355032 DQM0 = 41, DQM1 = 38
4749 10:01:09.357783 DQ Delay:
4750 10:01:09.360705 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4751 10:01:09.364416 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4752 10:01:09.367934 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4753 10:01:09.370985 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4754 10:01:09.371060
4755 10:01:09.371127
4756 10:01:09.371187 ==
4757 10:01:09.374439 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 10:01:09.378035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 10:01:09.378111 ==
4760 10:01:09.378177
4761 10:01:09.378237
4762 10:01:09.380903 TX Vref Scan disable
4763 10:01:09.381073 == TX Byte 0 ==
4764 10:01:09.387900 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4765 10:01:09.391101 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4766 10:01:09.391217 == TX Byte 1 ==
4767 10:01:09.397714 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4768 10:01:09.401248 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4769 10:01:09.401332 ==
4770 10:01:09.404588 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 10:01:09.407610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 10:01:09.407690 ==
4773 10:01:09.407751
4774 10:01:09.407809
4775 10:01:09.411165 TX Vref Scan disable
4776 10:01:09.414657 == TX Byte 0 ==
4777 10:01:09.417691 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4778 10:01:09.421159 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4779 10:01:09.424588 == TX Byte 1 ==
4780 10:01:09.427881 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4781 10:01:09.431141 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4782 10:01:09.434282
4783 10:01:09.434355 [DATLAT]
4784 10:01:09.434417 Freq=600, CH1 RK1
4785 10:01:09.434485
4786 10:01:09.437959 DATLAT Default: 0x9
4787 10:01:09.438056 0, 0xFFFF, sum = 0
4788 10:01:09.441186 1, 0xFFFF, sum = 0
4789 10:01:09.441271 2, 0xFFFF, sum = 0
4790 10:01:09.444398 3, 0xFFFF, sum = 0
4791 10:01:09.444496 4, 0xFFFF, sum = 0
4792 10:01:09.447692 5, 0xFFFF, sum = 0
4793 10:01:09.447792 6, 0xFFFF, sum = 0
4794 10:01:09.451602 7, 0xFFFF, sum = 0
4795 10:01:09.451699 8, 0x0, sum = 1
4796 10:01:09.454868 9, 0x0, sum = 2
4797 10:01:09.454964 10, 0x0, sum = 3
4798 10:01:09.458223 11, 0x0, sum = 4
4799 10:01:09.458322 best_step = 9
4800 10:01:09.458410
4801 10:01:09.458495 ==
4802 10:01:09.461033 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 10:01:09.464463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 10:01:09.467926 ==
4805 10:01:09.468000 RX Vref Scan: 0
4806 10:01:09.468062
4807 10:01:09.471306 RX Vref 0 -> 0, step: 1
4808 10:01:09.471374
4809 10:01:09.474874 RX Delay -179 -> 252, step: 8
4810 10:01:09.477835 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4811 10:01:09.481232 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4812 10:01:09.487871 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4813 10:01:09.491523 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4814 10:01:09.494430 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4815 10:01:09.498076 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4816 10:01:09.504619 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4817 10:01:09.508304 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4818 10:01:09.511258 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4819 10:01:09.514816 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4820 10:01:09.517753 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4821 10:01:09.524781 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4822 10:01:09.527839 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4823 10:01:09.531276 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4824 10:01:09.534543 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4825 10:01:09.541297 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4826 10:01:09.541380 ==
4827 10:01:09.544589 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 10:01:09.548000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 10:01:09.548073 ==
4830 10:01:09.548135 DQS Delay:
4831 10:01:09.551632 DQS0 = 0, DQS1 = 0
4832 10:01:09.551730 DQM Delay:
4833 10:01:09.554983 DQM0 = 37, DQM1 = 32
4834 10:01:09.555079 DQ Delay:
4835 10:01:09.558085 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4836 10:01:09.561174 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4837 10:01:09.564463 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4838 10:01:09.567808 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4839 10:01:09.567915
4840 10:01:09.568006
4841 10:01:09.575148 [DQSOSCAuto] RK1, (LSB)MR18= 0x3846, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4842 10:01:09.577903 CH1 RK1: MR19=808, MR18=3846
4843 10:01:09.584407 CH1_RK1: MR19=0x808, MR18=0x3846, DQSOSC=396, MR23=63, INC=167, DEC=111
4844 10:01:09.587769 [RxdqsGatingPostProcess] freq 600
4845 10:01:09.594935 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 10:01:09.597778 Pre-setting of DQS Precalculation
4847 10:01:09.601327 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 10:01:09.608136 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 10:01:09.614682 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 10:01:09.614783
4851 10:01:09.614884
4852 10:01:09.617801 [Calibration Summary] 1200 Mbps
4853 10:01:09.621208 CH 0, Rank 0
4854 10:01:09.621305 SW Impedance : PASS
4855 10:01:09.624465 DUTY Scan : NO K
4856 10:01:09.627774 ZQ Calibration : PASS
4857 10:01:09.627850 Jitter Meter : NO K
4858 10:01:09.631143 CBT Training : PASS
4859 10:01:09.631246 Write leveling : PASS
4860 10:01:09.634663 RX DQS gating : PASS
4861 10:01:09.638331 RX DQ/DQS(RDDQC) : PASS
4862 10:01:09.638419 TX DQ/DQS : PASS
4863 10:01:09.641266 RX DATLAT : PASS
4864 10:01:09.644467 RX DQ/DQS(Engine): PASS
4865 10:01:09.644541 TX OE : NO K
4866 10:01:09.648018 All Pass.
4867 10:01:09.648117
4868 10:01:09.648205 CH 0, Rank 1
4869 10:01:09.651319 SW Impedance : PASS
4870 10:01:09.651394 DUTY Scan : NO K
4871 10:01:09.654377 ZQ Calibration : PASS
4872 10:01:09.657711 Jitter Meter : NO K
4873 10:01:09.657810 CBT Training : PASS
4874 10:01:09.661012 Write leveling : PASS
4875 10:01:09.664506 RX DQS gating : PASS
4876 10:01:09.664611 RX DQ/DQS(RDDQC) : PASS
4877 10:01:09.667980 TX DQ/DQS : PASS
4878 10:01:09.671360 RX DATLAT : PASS
4879 10:01:09.671458 RX DQ/DQS(Engine): PASS
4880 10:01:09.674485 TX OE : NO K
4881 10:01:09.674582 All Pass.
4882 10:01:09.674669
4883 10:01:09.677758 CH 1, Rank 0
4884 10:01:09.677862 SW Impedance : PASS
4885 10:01:09.681764 DUTY Scan : NO K
4886 10:01:09.681863 ZQ Calibration : PASS
4887 10:01:09.684800 Jitter Meter : NO K
4888 10:01:09.687907 CBT Training : PASS
4889 10:01:09.687983 Write leveling : PASS
4890 10:01:09.691485 RX DQS gating : PASS
4891 10:01:09.694297 RX DQ/DQS(RDDQC) : PASS
4892 10:01:09.694369 TX DQ/DQS : PASS
4893 10:01:09.697752 RX DATLAT : PASS
4894 10:01:09.701097 RX DQ/DQS(Engine): PASS
4895 10:01:09.701171 TX OE : NO K
4896 10:01:09.704676 All Pass.
4897 10:01:09.704749
4898 10:01:09.704810 CH 1, Rank 1
4899 10:01:09.708020 SW Impedance : PASS
4900 10:01:09.708102 DUTY Scan : NO K
4901 10:01:09.711198 ZQ Calibration : PASS
4902 10:01:09.714766 Jitter Meter : NO K
4903 10:01:09.714847 CBT Training : PASS
4904 10:01:09.717691 Write leveling : PASS
4905 10:01:09.717772 RX DQS gating : PASS
4906 10:01:09.721127 RX DQ/DQS(RDDQC) : PASS
4907 10:01:09.724446 TX DQ/DQS : PASS
4908 10:01:09.724527 RX DATLAT : PASS
4909 10:01:09.728086 RX DQ/DQS(Engine): PASS
4910 10:01:09.731206 TX OE : NO K
4911 10:01:09.731288 All Pass.
4912 10:01:09.731352
4913 10:01:09.734659 DramC Write-DBI off
4914 10:01:09.734741 PER_BANK_REFRESH: Hybrid Mode
4915 10:01:09.738105 TX_TRACKING: ON
4916 10:01:09.744999 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 10:01:09.751260 [FAST_K] Save calibration result to emmc
4918 10:01:09.754749 dramc_set_vcore_voltage set vcore to 662500
4919 10:01:09.754831 Read voltage for 933, 3
4920 10:01:09.758120 Vio18 = 0
4921 10:01:09.758202 Vcore = 662500
4922 10:01:09.758265 Vdram = 0
4923 10:01:09.761387 Vddq = 0
4924 10:01:09.761469 Vmddr = 0
4925 10:01:09.764835 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 10:01:09.771625 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 10:01:09.774575 MEM_TYPE=3, freq_sel=17
4928 10:01:09.774656 sv_algorithm_assistance_LP4_1600
4929 10:01:09.781342 ============ PULL DRAM RESETB DOWN ============
4930 10:01:09.784883 ========== PULL DRAM RESETB DOWN end =========
4931 10:01:09.787862 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 10:01:09.791635 ===================================
4933 10:01:09.795111 LPDDR4 DRAM CONFIGURATION
4934 10:01:09.798308 ===================================
4935 10:01:09.801513 EX_ROW_EN[0] = 0x0
4936 10:01:09.801594 EX_ROW_EN[1] = 0x0
4937 10:01:09.804847 LP4Y_EN = 0x0
4938 10:01:09.804928 WORK_FSP = 0x0
4939 10:01:09.808436 WL = 0x3
4940 10:01:09.808517 RL = 0x3
4941 10:01:09.811627 BL = 0x2
4942 10:01:09.811708 RPST = 0x0
4943 10:01:09.814791 RD_PRE = 0x0
4944 10:01:09.814904 WR_PRE = 0x1
4945 10:01:09.818287 WR_PST = 0x0
4946 10:01:09.818368 DBI_WR = 0x0
4947 10:01:09.821605 DBI_RD = 0x0
4948 10:01:09.821701 OTF = 0x1
4949 10:01:09.824532 ===================================
4950 10:01:09.828005 ===================================
4951 10:01:09.831637 ANA top config
4952 10:01:09.835148 ===================================
4953 10:01:09.838398 DLL_ASYNC_EN = 0
4954 10:01:09.838503 ALL_SLAVE_EN = 1
4955 10:01:09.841486 NEW_RANK_MODE = 1
4956 10:01:09.844851 DLL_IDLE_MODE = 1
4957 10:01:09.848598 LP45_APHY_COMB_EN = 1
4958 10:01:09.848724 TX_ODT_DIS = 1
4959 10:01:09.851328 NEW_8X_MODE = 1
4960 10:01:09.855113 ===================================
4961 10:01:09.858395 ===================================
4962 10:01:09.861836 data_rate = 1866
4963 10:01:09.865381 CKR = 1
4964 10:01:09.868287 DQ_P2S_RATIO = 8
4965 10:01:09.871581 ===================================
4966 10:01:09.871679 CA_P2S_RATIO = 8
4967 10:01:09.875395 DQ_CA_OPEN = 0
4968 10:01:09.878410 DQ_SEMI_OPEN = 0
4969 10:01:09.881650 CA_SEMI_OPEN = 0
4970 10:01:09.885432 CA_FULL_RATE = 0
4971 10:01:09.888469 DQ_CKDIV4_EN = 1
4972 10:01:09.888572 CA_CKDIV4_EN = 1
4973 10:01:09.891871 CA_PREDIV_EN = 0
4974 10:01:09.895439 PH8_DLY = 0
4975 10:01:09.898775 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 10:01:09.902055 DQ_AAMCK_DIV = 4
4977 10:01:09.905242 CA_AAMCK_DIV = 4
4978 10:01:09.905317 CA_ADMCK_DIV = 4
4979 10:01:09.908787 DQ_TRACK_CA_EN = 0
4980 10:01:09.912259 CA_PICK = 933
4981 10:01:09.915131 CA_MCKIO = 933
4982 10:01:09.918370 MCKIO_SEMI = 0
4983 10:01:09.921904 PLL_FREQ = 3732
4984 10:01:09.925424 DQ_UI_PI_RATIO = 32
4985 10:01:09.925525 CA_UI_PI_RATIO = 0
4986 10:01:09.928308 ===================================
4987 10:01:09.931766 ===================================
4988 10:01:09.935338 memory_type:LPDDR4
4989 10:01:09.938414 GP_NUM : 10
4990 10:01:09.938517 SRAM_EN : 1
4991 10:01:09.941936 MD32_EN : 0
4992 10:01:09.945678 ===================================
4993 10:01:09.948559 [ANA_INIT] >>>>>>>>>>>>>>
4994 10:01:09.948706 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 10:01:09.951806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 10:01:09.955341 ===================================
4997 10:01:09.958620 data_rate = 1866,PCW = 0X8f00
4998 10:01:09.962169 ===================================
4999 10:01:09.965627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 10:01:09.971827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 10:01:09.978638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 10:01:09.981992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 10:01:09.985272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 10:01:09.988642 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 10:01:09.991892 [ANA_INIT] flow start
5006 10:01:09.992005 [ANA_INIT] PLL >>>>>>>>
5007 10:01:09.995154 [ANA_INIT] PLL <<<<<<<<
5008 10:01:09.998618 [ANA_INIT] MIDPI >>>>>>>>
5009 10:01:09.998717 [ANA_INIT] MIDPI <<<<<<<<
5010 10:01:10.001936 [ANA_INIT] DLL >>>>>>>>
5011 10:01:10.005259 [ANA_INIT] flow end
5012 10:01:10.008684 ============ LP4 DIFF to SE enter ============
5013 10:01:10.011905 ============ LP4 DIFF to SE exit ============
5014 10:01:10.015332 [ANA_INIT] <<<<<<<<<<<<<
5015 10:01:10.019091 [Flow] Enable top DCM control >>>>>
5016 10:01:10.021888 [Flow] Enable top DCM control <<<<<
5017 10:01:10.024955 Enable DLL master slave shuffle
5018 10:01:10.028569 ==============================================================
5019 10:01:10.031713 Gating Mode config
5020 10:01:10.038572 ==============================================================
5021 10:01:10.038652 Config description:
5022 10:01:10.048474 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 10:01:10.055452 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 10:01:10.058390 SELPH_MODE 0: By rank 1: By Phase
5025 10:01:10.065296 ==============================================================
5026 10:01:10.068582 GAT_TRACK_EN = 1
5027 10:01:10.072042 RX_GATING_MODE = 2
5028 10:01:10.075395 RX_GATING_TRACK_MODE = 2
5029 10:01:10.078938 SELPH_MODE = 1
5030 10:01:10.081799 PICG_EARLY_EN = 1
5031 10:01:10.085382 VALID_LAT_VALUE = 1
5032 10:01:10.088876 ==============================================================
5033 10:01:10.091701 Enter into Gating configuration >>>>
5034 10:01:10.095249 Exit from Gating configuration <<<<
5035 10:01:10.098415 Enter into DVFS_PRE_config >>>>>
5036 10:01:10.108607 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 10:01:10.111878 Exit from DVFS_PRE_config <<<<<
5038 10:01:10.115190 Enter into PICG configuration >>>>
5039 10:01:10.118346 Exit from PICG configuration <<<<
5040 10:01:10.122061 [RX_INPUT] configuration >>>>>
5041 10:01:10.125001 [RX_INPUT] configuration <<<<<
5042 10:01:10.131877 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 10:01:10.135643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 10:01:10.142345 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 10:01:10.148630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 10:01:10.155681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 10:01:10.162029 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 10:01:10.165141 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 10:01:10.168647 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 10:01:10.172223 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 10:01:10.175466 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 10:01:10.182418 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 10:01:10.185348 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 10:01:10.188643 ===================================
5055 10:01:10.192087 LPDDR4 DRAM CONFIGURATION
5056 10:01:10.195261 ===================================
5057 10:01:10.195359 EX_ROW_EN[0] = 0x0
5058 10:01:10.198656 EX_ROW_EN[1] = 0x0
5059 10:01:10.198751 LP4Y_EN = 0x0
5060 10:01:10.202145 WORK_FSP = 0x0
5061 10:01:10.202238 WL = 0x3
5062 10:01:10.205778 RL = 0x3
5063 10:01:10.205880 BL = 0x2
5064 10:01:10.208847 RPST = 0x0
5065 10:01:10.208943 RD_PRE = 0x0
5066 10:01:10.212376 WR_PRE = 0x1
5067 10:01:10.212472 WR_PST = 0x0
5068 10:01:10.215599 DBI_WR = 0x0
5069 10:01:10.215695 DBI_RD = 0x0
5070 10:01:10.219191 OTF = 0x1
5071 10:01:10.222300 ===================================
5072 10:01:10.225648 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 10:01:10.229085 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 10:01:10.235695 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 10:01:10.239147 ===================================
5076 10:01:10.239246 LPDDR4 DRAM CONFIGURATION
5077 10:01:10.242341 ===================================
5078 10:01:10.245377 EX_ROW_EN[0] = 0x10
5079 10:01:10.248786 EX_ROW_EN[1] = 0x0
5080 10:01:10.248889 LP4Y_EN = 0x0
5081 10:01:10.252111 WORK_FSP = 0x0
5082 10:01:10.252206 WL = 0x3
5083 10:01:10.255891 RL = 0x3
5084 10:01:10.255991 BL = 0x2
5085 10:01:10.259110 RPST = 0x0
5086 10:01:10.259214 RD_PRE = 0x0
5087 10:01:10.262553 WR_PRE = 0x1
5088 10:01:10.262650 WR_PST = 0x0
5089 10:01:10.265590 DBI_WR = 0x0
5090 10:01:10.265660 DBI_RD = 0x0
5091 10:01:10.269032 OTF = 0x1
5092 10:01:10.272759 ===================================
5093 10:01:10.279029 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 10:01:10.282341 nWR fixed to 30
5095 10:01:10.282438 [ModeRegInit_LP4] CH0 RK0
5096 10:01:10.285911 [ModeRegInit_LP4] CH0 RK1
5097 10:01:10.289196 [ModeRegInit_LP4] CH1 RK0
5098 10:01:10.292229 [ModeRegInit_LP4] CH1 RK1
5099 10:01:10.292366 match AC timing 9
5100 10:01:10.295837 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 10:01:10.299341 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 10:01:10.305850 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 10:01:10.309301 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 10:01:10.316413 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 10:01:10.316516 ==
5106 10:01:10.319430 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 10:01:10.322539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 10:01:10.322635 ==
5109 10:01:10.329016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 10:01:10.332475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5111 10:01:10.336930 [CA 0] Center 38 (8~69) winsize 62
5112 10:01:10.339881 [CA 1] Center 38 (8~68) winsize 61
5113 10:01:10.343391 [CA 2] Center 35 (5~66) winsize 62
5114 10:01:10.346573 [CA 3] Center 35 (4~66) winsize 63
5115 10:01:10.349909 [CA 4] Center 34 (4~65) winsize 62
5116 10:01:10.353385 [CA 5] Center 34 (4~64) winsize 61
5117 10:01:10.353484
5118 10:01:10.356809 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5119 10:01:10.356899
5120 10:01:10.360315 [CATrainingPosCal] consider 1 rank data
5121 10:01:10.363348 u2DelayCellTimex100 = 270/100 ps
5122 10:01:10.366621 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5123 10:01:10.370237 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5124 10:01:10.373672 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5125 10:01:10.380217 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5126 10:01:10.383652 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5127 10:01:10.387006 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5128 10:01:10.387105
5129 10:01:10.390498 CA PerBit enable=1, Macro0, CA PI delay=34
5130 10:01:10.390595
5131 10:01:10.393544 [CBTSetCACLKResult] CA Dly = 34
5132 10:01:10.393623 CS Dly: 6 (0~37)
5133 10:01:10.393690 ==
5134 10:01:10.397288 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 10:01:10.403669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 10:01:10.403762 ==
5137 10:01:10.407010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 10:01:10.413863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5139 10:01:10.416728 [CA 0] Center 38 (8~69) winsize 62
5140 10:01:10.420312 [CA 1] Center 38 (7~69) winsize 63
5141 10:01:10.423867 [CA 2] Center 35 (5~66) winsize 62
5142 10:01:10.426730 [CA 3] Center 35 (4~66) winsize 63
5143 10:01:10.430207 [CA 4] Center 33 (3~64) winsize 62
5144 10:01:10.433964 [CA 5] Center 33 (3~64) winsize 62
5145 10:01:10.434066
5146 10:01:10.436713 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5147 10:01:10.436811
5148 10:01:10.440453 [CATrainingPosCal] consider 2 rank data
5149 10:01:10.443981 u2DelayCellTimex100 = 270/100 ps
5150 10:01:10.447282 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5151 10:01:10.450283 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5152 10:01:10.453472 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5153 10:01:10.460210 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5154 10:01:10.463686 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5155 10:01:10.466694 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5156 10:01:10.466797
5157 10:01:10.470253 CA PerBit enable=1, Macro0, CA PI delay=34
5158 10:01:10.470351
5159 10:01:10.473547 [CBTSetCACLKResult] CA Dly = 34
5160 10:01:10.473620 CS Dly: 7 (0~39)
5161 10:01:10.473683
5162 10:01:10.477359 ----->DramcWriteLeveling(PI) begin...
5163 10:01:10.477435 ==
5164 10:01:10.480440 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 10:01:10.487281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 10:01:10.487356 ==
5167 10:01:10.490306 Write leveling (Byte 0): 27 => 27
5168 10:01:10.490379 Write leveling (Byte 1): 26 => 26
5169 10:01:10.494091 DramcWriteLeveling(PI) end<-----
5170 10:01:10.494162
5171 10:01:10.497131 ==
5172 10:01:10.497230 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 10:01:10.503893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 10:01:10.503994 ==
5175 10:01:10.507177 [Gating] SW mode calibration
5176 10:01:10.513824 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 10:01:10.516944 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 10:01:10.524232 0 14 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
5179 10:01:10.527056 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5180 10:01:10.530485 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 10:01:10.536995 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 10:01:10.540896 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 10:01:10.544187 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 10:01:10.547226 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 10:01:10.553713 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
5186 10:01:10.557131 0 15 0 | B1->B0 | 3131 2828 | 0 0 | (0 1) (0 0)
5187 10:01:10.560918 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5188 10:01:10.567471 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 10:01:10.570455 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 10:01:10.573971 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 10:01:10.580775 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 10:01:10.583983 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 10:01:10.587652 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 10:01:10.594486 1 0 0 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
5195 10:01:10.597373 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5196 10:01:10.600965 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 10:01:10.607430 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 10:01:10.611058 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 10:01:10.614331 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 10:01:10.617700 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5201 10:01:10.624215 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5202 10:01:10.627719 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 10:01:10.631299 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5204 10:01:10.637665 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 10:01:10.641255 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 10:01:10.644274 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 10:01:10.650690 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 10:01:10.653926 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 10:01:10.657523 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 10:01:10.664171 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 10:01:10.667747 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 10:01:10.670839 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 10:01:10.677207 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 10:01:10.681326 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 10:01:10.684621 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 10:01:10.690762 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 10:01:10.694346 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5218 10:01:10.698031 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5219 10:01:10.701065 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5220 10:01:10.704507 Total UI for P1: 0, mck2ui 16
5221 10:01:10.708023 best dqsien dly found for B1: ( 1, 2, 30)
5222 10:01:10.714212 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 10:01:10.717657 Total UI for P1: 0, mck2ui 16
5224 10:01:10.721283 best dqsien dly found for B0: ( 1, 3, 0)
5225 10:01:10.724516 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5226 10:01:10.727647 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5227 10:01:10.727717
5228 10:01:10.730653 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5229 10:01:10.734588 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5230 10:01:10.737463 [Gating] SW calibration Done
5231 10:01:10.737580 ==
5232 10:01:10.740975 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 10:01:10.744565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 10:01:10.744643 ==
5235 10:01:10.748158 RX Vref Scan: 0
5236 10:01:10.748233
5237 10:01:10.748293 RX Vref 0 -> 0, step: 1
5238 10:01:10.748351
5239 10:01:10.751373 RX Delay -80 -> 252, step: 8
5240 10:01:10.754314 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5241 10:01:10.761244 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5242 10:01:10.764448 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5243 10:01:10.767647 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5244 10:01:10.771325 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5245 10:01:10.774614 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5246 10:01:10.777526 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5247 10:01:10.784676 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5248 10:01:10.787866 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5249 10:01:10.791316 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5250 10:01:10.794294 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5251 10:01:10.797762 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5252 10:01:10.801059 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5253 10:01:10.807600 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5254 10:01:10.811238 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5255 10:01:10.814662 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5256 10:01:10.814732 ==
5257 10:01:10.818304 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 10:01:10.821241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 10:01:10.821312 ==
5260 10:01:10.824502 DQS Delay:
5261 10:01:10.824569 DQS0 = 0, DQS1 = 0
5262 10:01:10.824629 DQM Delay:
5263 10:01:10.827977 DQM0 = 98, DQM1 = 87
5264 10:01:10.828046 DQ Delay:
5265 10:01:10.831348 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =91
5266 10:01:10.834776 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5267 10:01:10.837924 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5268 10:01:10.841430 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5269 10:01:10.841503
5270 10:01:10.841614
5271 10:01:10.845011 ==
5272 10:01:10.845085 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 10:01:10.851491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 10:01:10.851564 ==
5275 10:01:10.851625
5276 10:01:10.851689
5277 10:01:10.854211 TX Vref Scan disable
5278 10:01:10.854279 == TX Byte 0 ==
5279 10:01:10.857748 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5280 10:01:10.864777 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5281 10:01:10.864858 == TX Byte 1 ==
5282 10:01:10.868164 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5283 10:01:10.874425 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5284 10:01:10.874504 ==
5285 10:01:10.877831 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 10:01:10.881197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 10:01:10.881267 ==
5288 10:01:10.881328
5289 10:01:10.881385
5290 10:01:10.884699 TX Vref Scan disable
5291 10:01:10.887867 == TX Byte 0 ==
5292 10:01:10.891153 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5293 10:01:10.894585 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5294 10:01:10.898013 == TX Byte 1 ==
5295 10:01:10.901441 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5296 10:01:10.904598 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5297 10:01:10.904678
5298 10:01:10.904753 [DATLAT]
5299 10:01:10.908202 Freq=933, CH0 RK0
5300 10:01:10.908273
5301 10:01:10.908331 DATLAT Default: 0xd
5302 10:01:10.911332 0, 0xFFFF, sum = 0
5303 10:01:10.914942 1, 0xFFFF, sum = 0
5304 10:01:10.915012 2, 0xFFFF, sum = 0
5305 10:01:10.918268 3, 0xFFFF, sum = 0
5306 10:01:10.918337 4, 0xFFFF, sum = 0
5307 10:01:10.921199 5, 0xFFFF, sum = 0
5308 10:01:10.921268 6, 0xFFFF, sum = 0
5309 10:01:10.924644 7, 0xFFFF, sum = 0
5310 10:01:10.924755 8, 0xFFFF, sum = 0
5311 10:01:10.928056 9, 0xFFFF, sum = 0
5312 10:01:10.928130 10, 0x0, sum = 1
5313 10:01:10.931621 11, 0x0, sum = 2
5314 10:01:10.931694 12, 0x0, sum = 3
5315 10:01:10.934504 13, 0x0, sum = 4
5316 10:01:10.934579 best_step = 11
5317 10:01:10.934638
5318 10:01:10.934694 ==
5319 10:01:10.938113 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 10:01:10.941578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 10:01:10.941658 ==
5322 10:01:10.944824 RX Vref Scan: 1
5323 10:01:10.944899
5324 10:01:10.948076 RX Vref 0 -> 0, step: 1
5325 10:01:10.948151
5326 10:01:10.948250 RX Delay -61 -> 252, step: 4
5327 10:01:10.948307
5328 10:01:10.951204 Set Vref, RX VrefLevel [Byte0]: 53
5329 10:01:10.954336 [Byte1]: 56
5330 10:01:10.959049
5331 10:01:10.959123 Final RX Vref Byte 0 = 53 to rank0
5332 10:01:10.962418 Final RX Vref Byte 1 = 56 to rank0
5333 10:01:10.965874 Final RX Vref Byte 0 = 53 to rank1
5334 10:01:10.969201 Final RX Vref Byte 1 = 56 to rank1==
5335 10:01:10.972200 Dram Type= 6, Freq= 0, CH_0, rank 0
5336 10:01:10.979105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 10:01:10.979189 ==
5338 10:01:10.979252 DQS Delay:
5339 10:01:10.979311 DQS0 = 0, DQS1 = 0
5340 10:01:10.982650 DQM Delay:
5341 10:01:10.982720 DQM0 = 97, DQM1 = 89
5342 10:01:10.985457 DQ Delay:
5343 10:01:10.988900 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5344 10:01:10.992310 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =104
5345 10:01:10.995672 DQ8 =78, DQ9 =78, DQ10 =92, DQ11 =82
5346 10:01:10.999268 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5347 10:01:10.999347
5348 10:01:10.999408
5349 10:01:11.005673 [DQSOSCAuto] RK0, (LSB)MR18= 0x1602, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5350 10:01:11.009065 CH0 RK0: MR19=505, MR18=1602
5351 10:01:11.015801 CH0_RK0: MR19=0x505, MR18=0x1602, DQSOSC=414, MR23=63, INC=63, DEC=42
5352 10:01:11.015877
5353 10:01:11.019347 ----->DramcWriteLeveling(PI) begin...
5354 10:01:11.019425 ==
5355 10:01:11.022873 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 10:01:11.025737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 10:01:11.025808 ==
5358 10:01:11.029193 Write leveling (Byte 0): 30 => 30
5359 10:01:11.032562 Write leveling (Byte 1): 30 => 30
5360 10:01:11.035965 DramcWriteLeveling(PI) end<-----
5361 10:01:11.036046
5362 10:01:11.036105 ==
5363 10:01:11.039557 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 10:01:11.042443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 10:01:11.042520 ==
5366 10:01:11.045953 [Gating] SW mode calibration
5367 10:01:11.052938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5368 10:01:11.059485 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5369 10:01:11.063026 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5370 10:01:11.066444 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 10:01:11.072802 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 10:01:11.076305 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 10:01:11.079675 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 10:01:11.086805 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 10:01:11.089637 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 10:01:11.093154 0 14 28 | B1->B0 | 3232 3030 | 0 0 | (0 0) (1 1)
5377 10:01:11.096683 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (0 1) (0 0)
5378 10:01:11.102989 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 10:01:11.106721 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 10:01:11.109568 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 10:01:11.116548 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 10:01:11.120021 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 10:01:11.123276 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 10:01:11.129987 0 15 28 | B1->B0 | 2b2b 3939 | 0 0 | (1 1) (0 0)
5385 10:01:11.133413 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5386 10:01:11.136272 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 10:01:11.143135 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 10:01:11.146832 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 10:01:11.149617 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 10:01:11.156407 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 10:01:11.159845 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 10:01:11.163314 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5393 10:01:11.169761 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5394 10:01:11.173372 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 10:01:11.176515 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 10:01:11.179915 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 10:01:11.186294 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 10:01:11.190268 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 10:01:11.193263 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 10:01:11.200255 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 10:01:11.203093 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 10:01:11.206726 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 10:01:11.213608 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 10:01:11.216454 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 10:01:11.220436 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 10:01:11.226828 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 10:01:11.230449 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5408 10:01:11.233676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5409 10:01:11.240023 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5410 10:01:11.240099 Total UI for P1: 0, mck2ui 16
5411 10:01:11.243290 best dqsien dly found for B0: ( 1, 2, 26)
5412 10:01:11.250247 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5413 10:01:11.253922 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 10:01:11.256810 Total UI for P1: 0, mck2ui 16
5415 10:01:11.260673 best dqsien dly found for B1: ( 1, 3, 0)
5416 10:01:11.263484 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5417 10:01:11.266954 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5418 10:01:11.267032
5419 10:01:11.270372 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5420 10:01:11.273497 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5421 10:01:11.276881 [Gating] SW calibration Done
5422 10:01:11.276958 ==
5423 10:01:11.280288 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 10:01:11.283789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 10:01:11.286971 ==
5426 10:01:11.287050 RX Vref Scan: 0
5427 10:01:11.287112
5428 10:01:11.290719 RX Vref 0 -> 0, step: 1
5429 10:01:11.290789
5430 10:01:11.290846 RX Delay -80 -> 252, step: 8
5431 10:01:11.297039 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5432 10:01:11.300583 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5433 10:01:11.304099 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5434 10:01:11.307056 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5435 10:01:11.310541 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5436 10:01:11.314020 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5437 10:01:11.320799 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5438 10:01:11.323967 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5439 10:01:11.327534 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5440 10:01:11.330649 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5441 10:01:11.334083 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5442 10:01:11.337551 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5443 10:01:11.344164 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5444 10:01:11.347557 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5445 10:01:11.350768 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5446 10:01:11.353901 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5447 10:01:11.353988 ==
5448 10:01:11.357494 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 10:01:11.360647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 10:01:11.360769 ==
5451 10:01:11.363943 DQS Delay:
5452 10:01:11.364038 DQS0 = 0, DQS1 = 0
5453 10:01:11.367319 DQM Delay:
5454 10:01:11.367390 DQM0 = 97, DQM1 = 87
5455 10:01:11.367450 DQ Delay:
5456 10:01:11.370954 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5457 10:01:11.373805 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5458 10:01:11.377445 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5459 10:01:11.380892 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5460 10:01:11.380961
5461 10:01:11.381044
5462 10:01:11.383842 ==
5463 10:01:11.387773 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 10:01:11.390736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 10:01:11.390820 ==
5466 10:01:11.390905
5467 10:01:11.390985
5468 10:01:11.394211 TX Vref Scan disable
5469 10:01:11.394294 == TX Byte 0 ==
5470 10:01:11.397405 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5471 10:01:11.404176 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5472 10:01:11.404294 == TX Byte 1 ==
5473 10:01:11.407745 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5474 10:01:11.414239 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5475 10:01:11.414313 ==
5476 10:01:11.417733 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 10:01:11.421188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 10:01:11.421267 ==
5479 10:01:11.421328
5480 10:01:11.421385
5481 10:01:11.424508 TX Vref Scan disable
5482 10:01:11.427896 == TX Byte 0 ==
5483 10:01:11.430819 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5484 10:01:11.434395 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5485 10:01:11.437999 == TX Byte 1 ==
5486 10:01:11.440687 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5487 10:01:11.444509 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5488 10:01:11.444612
5489 10:01:11.444739 [DATLAT]
5490 10:01:11.447622 Freq=933, CH0 RK1
5491 10:01:11.447700
5492 10:01:11.450870 DATLAT Default: 0xb
5493 10:01:11.450945 0, 0xFFFF, sum = 0
5494 10:01:11.454481 1, 0xFFFF, sum = 0
5495 10:01:11.454553 2, 0xFFFF, sum = 0
5496 10:01:11.457368 3, 0xFFFF, sum = 0
5497 10:01:11.457438 4, 0xFFFF, sum = 0
5498 10:01:11.460713 5, 0xFFFF, sum = 0
5499 10:01:11.460799 6, 0xFFFF, sum = 0
5500 10:01:11.464386 7, 0xFFFF, sum = 0
5501 10:01:11.464469 8, 0xFFFF, sum = 0
5502 10:01:11.468136 9, 0xFFFF, sum = 0
5503 10:01:11.468207 10, 0x0, sum = 1
5504 10:01:11.471003 11, 0x0, sum = 2
5505 10:01:11.471074 12, 0x0, sum = 3
5506 10:01:11.474086 13, 0x0, sum = 4
5507 10:01:11.474163 best_step = 11
5508 10:01:11.474222
5509 10:01:11.474278 ==
5510 10:01:11.477801 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 10:01:11.481186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 10:01:11.481271 ==
5513 10:01:11.484175 RX Vref Scan: 0
5514 10:01:11.484251
5515 10:01:11.487635 RX Vref 0 -> 0, step: 1
5516 10:01:11.487708
5517 10:01:11.487768 RX Delay -61 -> 252, step: 4
5518 10:01:11.495286 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5519 10:01:11.498752 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5520 10:01:11.502132 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5521 10:01:11.505113 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5522 10:01:11.509075 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5523 10:01:11.512017 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5524 10:01:11.519214 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5525 10:01:11.522084 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5526 10:01:11.525258 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5527 10:01:11.529348 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5528 10:01:11.532073 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5529 10:01:11.535294 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5530 10:01:11.542042 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5531 10:01:11.545618 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5532 10:01:11.548797 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5533 10:01:11.552150 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5534 10:01:11.552229 ==
5535 10:01:11.555363 Dram Type= 6, Freq= 0, CH_0, rank 1
5536 10:01:11.558513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 10:01:11.561901 ==
5538 10:01:11.561980 DQS Delay:
5539 10:01:11.562043 DQS0 = 0, DQS1 = 0
5540 10:01:11.565527 DQM Delay:
5541 10:01:11.565602 DQM0 = 96, DQM1 = 89
5542 10:01:11.568538 DQ Delay:
5543 10:01:11.568651 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5544 10:01:11.572118 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5545 10:01:11.575333 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =82
5546 10:01:11.581901 DQ12 =92, DQ13 =94, DQ14 =100, DQ15 =96
5547 10:01:11.581974
5548 10:01:11.582035
5549 10:01:11.588698 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a07, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5550 10:01:11.592027 CH0 RK1: MR19=505, MR18=1A07
5551 10:01:11.598684 CH0_RK1: MR19=0x505, MR18=0x1A07, DQSOSC=413, MR23=63, INC=63, DEC=42
5552 10:01:11.601778 [RxdqsGatingPostProcess] freq 933
5553 10:01:11.605277 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5554 10:01:11.608642 best DQS0 dly(2T, 0.5T) = (0, 11)
5555 10:01:11.612059 best DQS1 dly(2T, 0.5T) = (0, 10)
5556 10:01:11.615645 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5557 10:01:11.618473 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5558 10:01:11.621984 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 10:01:11.625427 best DQS1 dly(2T, 0.5T) = (0, 11)
5560 10:01:11.628933 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 10:01:11.631920 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5562 10:01:11.635534 Pre-setting of DQS Precalculation
5563 10:01:11.638942 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5564 10:01:11.639015 ==
5565 10:01:11.642091 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 10:01:11.645335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 10:01:11.648780 ==
5568 10:01:11.652023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 10:01:11.658732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5570 10:01:11.662673 [CA 0] Center 36 (6~67) winsize 62
5571 10:01:11.665740 [CA 1] Center 36 (6~67) winsize 62
5572 10:01:11.669217 [CA 2] Center 34 (4~64) winsize 61
5573 10:01:11.672191 [CA 3] Center 33 (3~64) winsize 62
5574 10:01:11.675697 [CA 4] Center 34 (4~64) winsize 61
5575 10:01:11.678545 [CA 5] Center 33 (3~63) winsize 61
5576 10:01:11.678615
5577 10:01:11.681884 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5578 10:01:11.681974
5579 10:01:11.685584 [CATrainingPosCal] consider 1 rank data
5580 10:01:11.688823 u2DelayCellTimex100 = 270/100 ps
5581 10:01:11.692297 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5582 10:01:11.695613 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5583 10:01:11.698631 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5584 10:01:11.702023 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 10:01:11.705422 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5586 10:01:11.712368 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5587 10:01:11.712445
5588 10:01:11.715659 CA PerBit enable=1, Macro0, CA PI delay=33
5589 10:01:11.715730
5590 10:01:11.718890 [CBTSetCACLKResult] CA Dly = 33
5591 10:01:11.718961 CS Dly: 4 (0~35)
5592 10:01:11.719022 ==
5593 10:01:11.721915 Dram Type= 6, Freq= 0, CH_1, rank 1
5594 10:01:11.725364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 10:01:11.728822 ==
5596 10:01:11.732343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5597 10:01:11.738909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5598 10:01:11.742418 [CA 0] Center 36 (6~67) winsize 62
5599 10:01:11.745233 [CA 1] Center 37 (7~67) winsize 61
5600 10:01:11.748612 [CA 2] Center 33 (3~64) winsize 62
5601 10:01:11.752452 [CA 3] Center 33 (3~64) winsize 62
5602 10:01:11.755736 [CA 4] Center 34 (4~65) winsize 62
5603 10:01:11.758747 [CA 5] Center 32 (2~63) winsize 62
5604 10:01:11.758821
5605 10:01:11.762041 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5606 10:01:11.762155
5607 10:01:11.765589 [CATrainingPosCal] consider 2 rank data
5608 10:01:11.769059 u2DelayCellTimex100 = 270/100 ps
5609 10:01:11.772096 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5610 10:01:11.775576 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5611 10:01:11.778893 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5612 10:01:11.782286 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5613 10:01:11.785801 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5614 10:01:11.792110 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5615 10:01:11.792184
5616 10:01:11.795476 CA PerBit enable=1, Macro0, CA PI delay=33
5617 10:01:11.795548
5618 10:01:11.798768 [CBTSetCACLKResult] CA Dly = 33
5619 10:01:11.798851 CS Dly: 5 (0~38)
5620 10:01:11.798914
5621 10:01:11.802262 ----->DramcWriteLeveling(PI) begin...
5622 10:01:11.802363 ==
5623 10:01:11.805664 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 10:01:11.808985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 10:01:11.811880 ==
5626 10:01:11.811953 Write leveling (Byte 0): 26 => 26
5627 10:01:11.815651 Write leveling (Byte 1): 27 => 27
5628 10:01:11.818765 DramcWriteLeveling(PI) end<-----
5629 10:01:11.818841
5630 10:01:11.818902 ==
5631 10:01:11.822270 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 10:01:11.828803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 10:01:11.828879 ==
5634 10:01:11.828943 [Gating] SW mode calibration
5635 10:01:11.838851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5636 10:01:11.841925 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5637 10:01:11.845232 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5638 10:01:11.852331 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5639 10:01:11.855928 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 10:01:11.858591 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 10:01:11.865730 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 10:01:11.869115 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 10:01:11.872378 0 14 24 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5644 10:01:11.878882 0 14 28 | B1->B0 | 2f2f 3131 | 0 0 | (1 0) (1 0)
5645 10:01:11.881990 0 15 0 | B1->B0 | 2626 2727 | 1 0 | (1 0) (1 0)
5646 10:01:11.885662 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 10:01:11.892455 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 10:01:11.896132 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 10:01:11.899070 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5650 10:01:11.905839 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 10:01:11.909258 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 10:01:11.912224 0 15 28 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (0 0)
5653 10:01:11.915847 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
5654 10:01:11.922418 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 10:01:11.925882 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 10:01:11.929549 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 10:01:11.935742 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 10:01:11.939311 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 10:01:11.942272 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 10:01:11.949214 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5661 10:01:11.952787 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 10:01:11.955686 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 10:01:11.962839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 10:01:11.966020 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 10:01:11.969300 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 10:01:11.976266 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 10:01:11.978968 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 10:01:11.982511 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 10:01:11.989132 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 10:01:11.992615 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 10:01:11.995886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 10:01:11.998973 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 10:01:12.005748 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 10:01:12.009201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 10:01:12.012574 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5676 10:01:12.019497 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5677 10:01:12.022446 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 10:01:12.025750 Total UI for P1: 0, mck2ui 16
5679 10:01:12.029037 best dqsien dly found for B0: ( 1, 2, 26)
5680 10:01:12.032925 Total UI for P1: 0, mck2ui 16
5681 10:01:12.036405 best dqsien dly found for B1: ( 1, 2, 28)
5682 10:01:12.039581 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5683 10:01:12.042448 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5684 10:01:12.042558
5685 10:01:12.045744 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5686 10:01:12.049452 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5687 10:01:12.052938 [Gating] SW calibration Done
5688 10:01:12.053032 ==
5689 10:01:12.056173 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 10:01:12.059196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 10:01:12.062800 ==
5692 10:01:12.062873 RX Vref Scan: 0
5693 10:01:12.062934
5694 10:01:12.066068 RX Vref 0 -> 0, step: 1
5695 10:01:12.066139
5696 10:01:12.069574 RX Delay -80 -> 252, step: 8
5697 10:01:12.072340 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5698 10:01:12.075630 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5699 10:01:12.079266 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5700 10:01:12.082918 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5701 10:01:12.086377 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5702 10:01:12.089235 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5703 10:01:12.096248 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5704 10:01:12.099101 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5705 10:01:12.103028 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5706 10:01:12.106075 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5707 10:01:12.109609 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5708 10:01:12.115911 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5709 10:01:12.119125 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5710 10:01:12.122610 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5711 10:01:12.126060 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5712 10:01:12.129409 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5713 10:01:12.129486 ==
5714 10:01:12.132495 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 10:01:12.139445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 10:01:12.139524 ==
5717 10:01:12.139589 DQS Delay:
5718 10:01:12.142659 DQS0 = 0, DQS1 = 0
5719 10:01:12.142777 DQM Delay:
5720 10:01:12.142847 DQM0 = 96, DQM1 = 88
5721 10:01:12.146135 DQ Delay:
5722 10:01:12.149152 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5723 10:01:12.152497 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5724 10:01:12.156471 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5725 10:01:12.159560 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5726 10:01:12.159637
5727 10:01:12.159699
5728 10:01:12.159757 ==
5729 10:01:12.162568 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 10:01:12.165913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 10:01:12.165990 ==
5732 10:01:12.166052
5733 10:01:12.166110
5734 10:01:12.169475 TX Vref Scan disable
5735 10:01:12.169553 == TX Byte 0 ==
5736 10:01:12.176047 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5737 10:01:12.179548 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5738 10:01:12.179622 == TX Byte 1 ==
5739 10:01:12.186514 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5740 10:01:12.189641 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5741 10:01:12.189759 ==
5742 10:01:12.192794 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 10:01:12.196396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 10:01:12.196471 ==
5745 10:01:12.196534
5746 10:01:12.196602
5747 10:01:12.199799 TX Vref Scan disable
5748 10:01:12.203119 == TX Byte 0 ==
5749 10:01:12.206407 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5750 10:01:12.209469 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5751 10:01:12.213072 == TX Byte 1 ==
5752 10:01:12.216439 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5753 10:01:12.219276 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5754 10:01:12.219354
5755 10:01:12.222858 [DATLAT]
5756 10:01:12.222932 Freq=933, CH1 RK0
5757 10:01:12.222992
5758 10:01:12.226143 DATLAT Default: 0xd
5759 10:01:12.226220 0, 0xFFFF, sum = 0
5760 10:01:12.229268 1, 0xFFFF, sum = 0
5761 10:01:12.229403 2, 0xFFFF, sum = 0
5762 10:01:12.232806 3, 0xFFFF, sum = 0
5763 10:01:12.232893 4, 0xFFFF, sum = 0
5764 10:01:12.236165 5, 0xFFFF, sum = 0
5765 10:01:12.236242 6, 0xFFFF, sum = 0
5766 10:01:12.239854 7, 0xFFFF, sum = 0
5767 10:01:12.239932 8, 0xFFFF, sum = 0
5768 10:01:12.242971 9, 0xFFFF, sum = 0
5769 10:01:12.243049 10, 0x0, sum = 1
5770 10:01:12.246095 11, 0x0, sum = 2
5771 10:01:12.246177 12, 0x0, sum = 3
5772 10:01:12.249690 13, 0x0, sum = 4
5773 10:01:12.249766 best_step = 11
5774 10:01:12.249865
5775 10:01:12.249928 ==
5776 10:01:12.252902 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 10:01:12.256023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 10:01:12.259359 ==
5779 10:01:12.259436 RX Vref Scan: 1
5780 10:01:12.259497
5781 10:01:12.263028 RX Vref 0 -> 0, step: 1
5782 10:01:12.263098
5783 10:01:12.266432 RX Delay -61 -> 252, step: 4
5784 10:01:12.266506
5785 10:01:12.269413 Set Vref, RX VrefLevel [Byte0]: 57
5786 10:01:12.272760 [Byte1]: 52
5787 10:01:12.272832
5788 10:01:12.276278 Final RX Vref Byte 0 = 57 to rank0
5789 10:01:12.279839 Final RX Vref Byte 1 = 52 to rank0
5790 10:01:12.283010 Final RX Vref Byte 0 = 57 to rank1
5791 10:01:12.286266 Final RX Vref Byte 1 = 52 to rank1==
5792 10:01:12.289616 Dram Type= 6, Freq= 0, CH_1, rank 0
5793 10:01:12.292982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 10:01:12.293074 ==
5795 10:01:12.293137 DQS Delay:
5796 10:01:12.296377 DQS0 = 0, DQS1 = 0
5797 10:01:12.296456 DQM Delay:
5798 10:01:12.299776 DQM0 = 97, DQM1 = 90
5799 10:01:12.299853 DQ Delay:
5800 10:01:12.303010 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5801 10:01:12.306130 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5802 10:01:12.309413 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =86
5803 10:01:12.312948 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =94
5804 10:01:12.313026
5805 10:01:12.313091
5806 10:01:12.322820 [DQSOSCAuto] RK0, (LSB)MR18= 0x18f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 414 ps
5807 10:01:12.322898 CH1 RK0: MR19=504, MR18=18F6
5808 10:01:12.329370 CH1_RK0: MR19=0x504, MR18=0x18F6, DQSOSC=414, MR23=63, INC=63, DEC=42
5809 10:01:12.329448
5810 10:01:12.333397 ----->DramcWriteLeveling(PI) begin...
5811 10:01:12.333472 ==
5812 10:01:12.336245 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 10:01:12.342750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 10:01:12.342826 ==
5815 10:01:12.346045 Write leveling (Byte 0): 30 => 30
5816 10:01:12.349611 Write leveling (Byte 1): 29 => 29
5817 10:01:12.349684 DramcWriteLeveling(PI) end<-----
5818 10:01:12.349753
5819 10:01:12.352845 ==
5820 10:01:12.352916 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 10:01:12.359866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 10:01:12.359943 ==
5823 10:01:12.362950 [Gating] SW mode calibration
5824 10:01:12.369952 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5825 10:01:12.372808 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5826 10:01:12.379704 0 14 0 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5827 10:01:12.383942 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 10:01:12.386288 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 10:01:12.393061 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5830 10:01:12.396391 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 10:01:12.399929 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5832 10:01:12.402835 0 14 24 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (1 0)
5833 10:01:12.409585 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5834 10:01:12.412948 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5835 10:01:12.416402 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 10:01:12.423174 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 10:01:12.426337 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 10:01:12.429616 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 10:01:12.436774 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5840 10:01:12.440301 0 15 24 | B1->B0 | 2525 3333 | 0 0 | (0 0) (1 1)
5841 10:01:12.443283 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
5842 10:01:12.450104 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 10:01:12.453058 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 10:01:12.456541 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 10:01:12.462924 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 10:01:12.466654 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 10:01:12.469691 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5848 10:01:12.476345 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5849 10:01:12.479823 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 10:01:12.483256 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 10:01:12.489719 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 10:01:12.493097 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 10:01:12.496616 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 10:01:12.502986 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 10:01:12.506263 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 10:01:12.510037 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 10:01:12.512866 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 10:01:12.519790 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 10:01:12.523354 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 10:01:12.526168 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 10:01:12.532899 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 10:01:12.536620 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 10:01:12.540165 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 10:01:12.546587 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5865 10:01:12.549686 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 10:01:12.553370 Total UI for P1: 0, mck2ui 16
5867 10:01:12.556708 best dqsien dly found for B0: ( 1, 2, 24)
5868 10:01:12.559566 Total UI for P1: 0, mck2ui 16
5869 10:01:12.563049 best dqsien dly found for B1: ( 1, 2, 24)
5870 10:01:12.566641 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5871 10:01:12.570187 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5872 10:01:12.570271
5873 10:01:12.573489 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5874 10:01:12.576825 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5875 10:01:12.579605 [Gating] SW calibration Done
5876 10:01:12.579676 ==
5877 10:01:12.583499 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 10:01:12.586622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 10:01:12.586698 ==
5880 10:01:12.590091 RX Vref Scan: 0
5881 10:01:12.590187
5882 10:01:12.593099 RX Vref 0 -> 0, step: 1
5883 10:01:12.593194
5884 10:01:12.593255 RX Delay -80 -> 252, step: 8
5885 10:01:12.600200 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5886 10:01:12.603088 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5887 10:01:12.606721 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5888 10:01:12.609965 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5889 10:01:12.613349 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5890 10:01:12.617086 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5891 10:01:12.623015 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5892 10:01:12.626587 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5893 10:01:12.630137 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5894 10:01:12.633664 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5895 10:01:12.636812 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5896 10:01:12.640072 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5897 10:01:12.646918 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5898 10:01:12.649940 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5899 10:01:12.653268 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5900 10:01:12.656726 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5901 10:01:12.656830 ==
5902 10:01:12.659987 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 10:01:12.663905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 10:01:12.664016 ==
5905 10:01:12.666672 DQS Delay:
5906 10:01:12.666754 DQS0 = 0, DQS1 = 0
5907 10:01:12.670095 DQM Delay:
5908 10:01:12.670178 DQM0 = 94, DQM1 = 88
5909 10:01:12.670263 DQ Delay:
5910 10:01:12.673731 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5911 10:01:12.677008 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5912 10:01:12.679959 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5913 10:01:12.683547 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5914 10:01:12.683629
5915 10:01:12.686899
5916 10:01:12.687030 ==
5917 10:01:12.690334 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 10:01:12.693495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 10:01:12.693578 ==
5920 10:01:12.693663
5921 10:01:12.693742
5922 10:01:12.696651 TX Vref Scan disable
5923 10:01:12.696775 == TX Byte 0 ==
5924 10:01:12.700088 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5925 10:01:12.707109 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5926 10:01:12.707193 == TX Byte 1 ==
5927 10:01:12.710072 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5928 10:01:12.717310 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5929 10:01:12.717423 ==
5930 10:01:12.720470 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 10:01:12.723492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 10:01:12.723595 ==
5933 10:01:12.723695
5934 10:01:12.723794
5935 10:01:12.726756 TX Vref Scan disable
5936 10:01:12.730415 == TX Byte 0 ==
5937 10:01:12.734133 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5938 10:01:12.736969 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5939 10:01:12.740133 == TX Byte 1 ==
5940 10:01:12.743973 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5941 10:01:12.746959 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5942 10:01:12.747043
5943 10:01:12.747127 [DATLAT]
5944 10:01:12.750272 Freq=933, CH1 RK1
5945 10:01:12.750355
5946 10:01:12.753570 DATLAT Default: 0xb
5947 10:01:12.753653 0, 0xFFFF, sum = 0
5948 10:01:12.757003 1, 0xFFFF, sum = 0
5949 10:01:12.757091 2, 0xFFFF, sum = 0
5950 10:01:12.760303 3, 0xFFFF, sum = 0
5951 10:01:12.760387 4, 0xFFFF, sum = 0
5952 10:01:12.763760 5, 0xFFFF, sum = 0
5953 10:01:12.763843 6, 0xFFFF, sum = 0
5954 10:01:12.767096 7, 0xFFFF, sum = 0
5955 10:01:12.767179 8, 0xFFFF, sum = 0
5956 10:01:12.770133 9, 0xFFFF, sum = 0
5957 10:01:12.770217 10, 0x0, sum = 1
5958 10:01:12.773663 11, 0x0, sum = 2
5959 10:01:12.773747 12, 0x0, sum = 3
5960 10:01:12.777024 13, 0x0, sum = 4
5961 10:01:12.777111 best_step = 11
5962 10:01:12.777196
5963 10:01:12.777275 ==
5964 10:01:12.780683 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 10:01:12.784195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 10:01:12.784272 ==
5967 10:01:12.787045 RX Vref Scan: 0
5968 10:01:12.787128
5969 10:01:12.790497 RX Vref 0 -> 0, step: 1
5970 10:01:12.790579
5971 10:01:12.790664 RX Delay -61 -> 252, step: 4
5972 10:01:12.798348 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5973 10:01:12.801464 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5974 10:01:12.804740 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5975 10:01:12.808474 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5976 10:01:12.811342 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5977 10:01:12.814670 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5978 10:01:12.821152 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5979 10:01:12.824614 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5980 10:01:12.828337 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5981 10:01:12.831709 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5982 10:01:12.835133 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5983 10:01:12.841253 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5984 10:01:12.844771 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5985 10:01:12.848077 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5986 10:01:12.851204 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5987 10:01:12.854598 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5988 10:01:12.854672 ==
5989 10:01:12.858300 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 10:01:12.861404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 10:01:12.864662 ==
5992 10:01:12.864767 DQS Delay:
5993 10:01:12.864833 DQS0 = 0, DQS1 = 0
5994 10:01:12.868436 DQM Delay:
5995 10:01:12.868543 DQM0 = 95, DQM1 = 90
5996 10:01:12.871424 DQ Delay:
5997 10:01:12.871501 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5998 10:01:12.875279 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5999 10:01:12.878264 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
6000 10:01:12.881557 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
6001 10:01:12.881633
6002 10:01:12.885094
6003 10:01:12.891451 [DQSOSCAuto] RK1, (LSB)MR18= 0x111b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
6004 10:01:12.894933 CH1 RK1: MR19=505, MR18=111B
6005 10:01:12.901528 CH1_RK1: MR19=0x505, MR18=0x111B, DQSOSC=413, MR23=63, INC=63, DEC=42
6006 10:01:12.901607 [RxdqsGatingPostProcess] freq 933
6007 10:01:12.908644 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6008 10:01:12.911627 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 10:01:12.915069 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 10:01:12.918759 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 10:01:12.922191 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 10:01:12.925379 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 10:01:12.928811 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 10:01:12.931806 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 10:01:12.935058 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 10:01:12.938798 Pre-setting of DQS Precalculation
6017 10:01:12.941788 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6018 10:01:12.948832 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6019 10:01:12.955110 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6020 10:01:12.955193
6021 10:01:12.955278
6022 10:01:12.959094 [Calibration Summary] 1866 Mbps
6023 10:01:12.961894 CH 0, Rank 0
6024 10:01:12.961974 SW Impedance : PASS
6025 10:01:12.965404 DUTY Scan : NO K
6026 10:01:12.968938 ZQ Calibration : PASS
6027 10:01:12.969015 Jitter Meter : NO K
6028 10:01:12.972110 CBT Training : PASS
6029 10:01:12.972185 Write leveling : PASS
6030 10:01:12.975231 RX DQS gating : PASS
6031 10:01:12.978715 RX DQ/DQS(RDDQC) : PASS
6032 10:01:12.978787 TX DQ/DQS : PASS
6033 10:01:12.981920 RX DATLAT : PASS
6034 10:01:12.985180 RX DQ/DQS(Engine): PASS
6035 10:01:12.985253 TX OE : NO K
6036 10:01:12.988980 All Pass.
6037 10:01:12.989075
6038 10:01:12.989142 CH 0, Rank 1
6039 10:01:12.991875 SW Impedance : PASS
6040 10:01:12.991946 DUTY Scan : NO K
6041 10:01:12.995278 ZQ Calibration : PASS
6042 10:01:12.998385 Jitter Meter : NO K
6043 10:01:12.998460 CBT Training : PASS
6044 10:01:13.001831 Write leveling : PASS
6045 10:01:13.005338 RX DQS gating : PASS
6046 10:01:13.005413 RX DQ/DQS(RDDQC) : PASS
6047 10:01:13.008819 TX DQ/DQS : PASS
6048 10:01:13.011828 RX DATLAT : PASS
6049 10:01:13.011904 RX DQ/DQS(Engine): PASS
6050 10:01:13.015262 TX OE : NO K
6051 10:01:13.015343 All Pass.
6052 10:01:13.015404
6053 10:01:13.015462 CH 1, Rank 0
6054 10:01:13.018765 SW Impedance : PASS
6055 10:01:13.022340 DUTY Scan : NO K
6056 10:01:13.022415 ZQ Calibration : PASS
6057 10:01:13.025603 Jitter Meter : NO K
6058 10:01:13.028688 CBT Training : PASS
6059 10:01:13.028762 Write leveling : PASS
6060 10:01:13.031930 RX DQS gating : PASS
6061 10:01:13.035691 RX DQ/DQS(RDDQC) : PASS
6062 10:01:13.035771 TX DQ/DQS : PASS
6063 10:01:13.038948 RX DATLAT : PASS
6064 10:01:13.041870 RX DQ/DQS(Engine): PASS
6065 10:01:13.041944 TX OE : NO K
6066 10:01:13.045168 All Pass.
6067 10:01:13.045272
6068 10:01:13.045389 CH 1, Rank 1
6069 10:01:13.048630 SW Impedance : PASS
6070 10:01:13.048762 DUTY Scan : NO K
6071 10:01:13.052173 ZQ Calibration : PASS
6072 10:01:13.055466 Jitter Meter : NO K
6073 10:01:13.055548 CBT Training : PASS
6074 10:01:13.059046 Write leveling : PASS
6075 10:01:13.059130 RX DQS gating : PASS
6076 10:01:13.062174 RX DQ/DQS(RDDQC) : PASS
6077 10:01:13.065666 TX DQ/DQS : PASS
6078 10:01:13.065750 RX DATLAT : PASS
6079 10:01:13.068613 RX DQ/DQS(Engine): PASS
6080 10:01:13.072169 TX OE : NO K
6081 10:01:13.072250 All Pass.
6082 10:01:13.072315
6083 10:01:13.075188 DramC Write-DBI off
6084 10:01:13.075261 PER_BANK_REFRESH: Hybrid Mode
6085 10:01:13.078790 TX_TRACKING: ON
6086 10:01:13.085370 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6087 10:01:13.091972 [FAST_K] Save calibration result to emmc
6088 10:01:13.095506 dramc_set_vcore_voltage set vcore to 650000
6089 10:01:13.095583 Read voltage for 400, 6
6090 10:01:13.098687 Vio18 = 0
6091 10:01:13.098765 Vcore = 650000
6092 10:01:13.098857 Vdram = 0
6093 10:01:13.102266 Vddq = 0
6094 10:01:13.102348 Vmddr = 0
6095 10:01:13.105265 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6096 10:01:13.112283 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6097 10:01:13.115714 MEM_TYPE=3, freq_sel=20
6098 10:01:13.119165 sv_algorithm_assistance_LP4_800
6099 10:01:13.122507 ============ PULL DRAM RESETB DOWN ============
6100 10:01:13.125676 ========== PULL DRAM RESETB DOWN end =========
6101 10:01:13.128983 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6102 10:01:13.132438 ===================================
6103 10:01:13.135516 LPDDR4 DRAM CONFIGURATION
6104 10:01:13.139331 ===================================
6105 10:01:13.142374 EX_ROW_EN[0] = 0x0
6106 10:01:13.142447 EX_ROW_EN[1] = 0x0
6107 10:01:13.145795 LP4Y_EN = 0x0
6108 10:01:13.145872 WORK_FSP = 0x0
6109 10:01:13.148735 WL = 0x2
6110 10:01:13.148819 RL = 0x2
6111 10:01:13.152363 BL = 0x2
6112 10:01:13.152465 RPST = 0x0
6113 10:01:13.155760 RD_PRE = 0x0
6114 10:01:13.155839 WR_PRE = 0x1
6115 10:01:13.159161 WR_PST = 0x0
6116 10:01:13.159234 DBI_WR = 0x0
6117 10:01:13.161968 DBI_RD = 0x0
6118 10:01:13.162048 OTF = 0x1
6119 10:01:13.165546 ===================================
6120 10:01:13.168701 ===================================
6121 10:01:13.172196 ANA top config
6122 10:01:13.175796 ===================================
6123 10:01:13.178590 DLL_ASYNC_EN = 0
6124 10:01:13.178670 ALL_SLAVE_EN = 1
6125 10:01:13.182175 NEW_RANK_MODE = 1
6126 10:01:13.185538 DLL_IDLE_MODE = 1
6127 10:01:13.188751 LP45_APHY_COMB_EN = 1
6128 10:01:13.192181 TX_ODT_DIS = 1
6129 10:01:13.192288 NEW_8X_MODE = 1
6130 10:01:13.195463 ===================================
6131 10:01:13.198604 ===================================
6132 10:01:13.201747 data_rate = 800
6133 10:01:13.205337 CKR = 1
6134 10:01:13.209239 DQ_P2S_RATIO = 4
6135 10:01:13.212176 ===================================
6136 10:01:13.215067 CA_P2S_RATIO = 4
6137 10:01:13.215181 DQ_CA_OPEN = 0
6138 10:01:13.218572 DQ_SEMI_OPEN = 1
6139 10:01:13.222123 CA_SEMI_OPEN = 1
6140 10:01:13.225448 CA_FULL_RATE = 0
6141 10:01:13.228963 DQ_CKDIV4_EN = 0
6142 10:01:13.231994 CA_CKDIV4_EN = 1
6143 10:01:13.232073 CA_PREDIV_EN = 0
6144 10:01:13.235321 PH8_DLY = 0
6145 10:01:13.238328 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6146 10:01:13.242486 DQ_AAMCK_DIV = 0
6147 10:01:13.245525 CA_AAMCK_DIV = 0
6148 10:01:13.248532 CA_ADMCK_DIV = 4
6149 10:01:13.248639 DQ_TRACK_CA_EN = 0
6150 10:01:13.251868 CA_PICK = 800
6151 10:01:13.255480 CA_MCKIO = 400
6152 10:01:13.258528 MCKIO_SEMI = 400
6153 10:01:13.261977 PLL_FREQ = 3016
6154 10:01:13.265215 DQ_UI_PI_RATIO = 32
6155 10:01:13.269112 CA_UI_PI_RATIO = 32
6156 10:01:13.271682 ===================================
6157 10:01:13.275113 ===================================
6158 10:01:13.275186 memory_type:LPDDR4
6159 10:01:13.278499 GP_NUM : 10
6160 10:01:13.282161 SRAM_EN : 1
6161 10:01:13.282231 MD32_EN : 0
6162 10:01:13.284854 ===================================
6163 10:01:13.288431 [ANA_INIT] >>>>>>>>>>>>>>
6164 10:01:13.291959 <<<<<< [CONFIGURE PHASE]: ANA_TX
6165 10:01:13.295527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6166 10:01:13.298418 ===================================
6167 10:01:13.301798 data_rate = 800,PCW = 0X7400
6168 10:01:13.305344 ===================================
6169 10:01:13.308582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6170 10:01:13.311786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 10:01:13.325465 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 10:01:13.328695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6173 10:01:13.332229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6174 10:01:13.335906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6175 10:01:13.338574 [ANA_INIT] flow start
6176 10:01:13.338649 [ANA_INIT] PLL >>>>>>>>
6177 10:01:13.342167 [ANA_INIT] PLL <<<<<<<<
6178 10:01:13.345839 [ANA_INIT] MIDPI >>>>>>>>
6179 10:01:13.345984 [ANA_INIT] MIDPI <<<<<<<<
6180 10:01:13.349125 [ANA_INIT] DLL >>>>>>>>
6181 10:01:13.351989 [ANA_INIT] flow end
6182 10:01:13.355421 ============ LP4 DIFF to SE enter ============
6183 10:01:13.358848 ============ LP4 DIFF to SE exit ============
6184 10:01:13.362182 [ANA_INIT] <<<<<<<<<<<<<
6185 10:01:13.365483 [Flow] Enable top DCM control >>>>>
6186 10:01:13.368978 [Flow] Enable top DCM control <<<<<
6187 10:01:13.372273 Enable DLL master slave shuffle
6188 10:01:13.375772 ==============================================================
6189 10:01:13.378649 Gating Mode config
6190 10:01:13.385431 ==============================================================
6191 10:01:13.385507 Config description:
6192 10:01:13.395690 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6193 10:01:13.402258 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6194 10:01:13.405264 SELPH_MODE 0: By rank 1: By Phase
6195 10:01:13.412111 ==============================================================
6196 10:01:13.415521 GAT_TRACK_EN = 0
6197 10:01:13.418669 RX_GATING_MODE = 2
6198 10:01:13.422296 RX_GATING_TRACK_MODE = 2
6199 10:01:13.425315 SELPH_MODE = 1
6200 10:01:13.428891 PICG_EARLY_EN = 1
6201 10:01:13.432204 VALID_LAT_VALUE = 1
6202 10:01:13.435788 ==============================================================
6203 10:01:13.438642 Enter into Gating configuration >>>>
6204 10:01:13.442274 Exit from Gating configuration <<<<
6205 10:01:13.445722 Enter into DVFS_PRE_config >>>>>
6206 10:01:13.455469 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6207 10:01:13.458944 Exit from DVFS_PRE_config <<<<<
6208 10:01:13.461984 Enter into PICG configuration >>>>
6209 10:01:13.465866 Exit from PICG configuration <<<<
6210 10:01:13.468893 [RX_INPUT] configuration >>>>>
6211 10:01:13.472479 [RX_INPUT] configuration <<<<<
6212 10:01:13.476041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6213 10:01:13.482301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6214 10:01:13.488984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 10:01:13.495934 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 10:01:13.502355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 10:01:13.505686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 10:01:13.512161 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6219 10:01:13.515595 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6220 10:01:13.518975 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6221 10:01:13.522570 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6222 10:01:13.529162 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6223 10:01:13.532424 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 10:01:13.535698 ===================================
6225 10:01:13.539311 LPDDR4 DRAM CONFIGURATION
6226 10:01:13.542738 ===================================
6227 10:01:13.542810 EX_ROW_EN[0] = 0x0
6228 10:01:13.546002 EX_ROW_EN[1] = 0x0
6229 10:01:13.546114 LP4Y_EN = 0x0
6230 10:01:13.549206 WORK_FSP = 0x0
6231 10:01:13.549286 WL = 0x2
6232 10:01:13.552782 RL = 0x2
6233 10:01:13.552851 BL = 0x2
6234 10:01:13.556081 RPST = 0x0
6235 10:01:13.556152 RD_PRE = 0x0
6236 10:01:13.559499 WR_PRE = 0x1
6237 10:01:13.559566 WR_PST = 0x0
6238 10:01:13.563009 DBI_WR = 0x0
6239 10:01:13.563146 DBI_RD = 0x0
6240 10:01:13.565988 OTF = 0x1
6241 10:01:13.569464 ===================================
6242 10:01:13.572914 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6243 10:01:13.576565 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6244 10:01:13.583018 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 10:01:13.586343 ===================================
6246 10:01:13.586439 LPDDR4 DRAM CONFIGURATION
6247 10:01:13.589918 ===================================
6248 10:01:13.592938 EX_ROW_EN[0] = 0x10
6249 10:01:13.596508 EX_ROW_EN[1] = 0x0
6250 10:01:13.596614 LP4Y_EN = 0x0
6251 10:01:13.599867 WORK_FSP = 0x0
6252 10:01:13.599977 WL = 0x2
6253 10:01:13.602765 RL = 0x2
6254 10:01:13.602845 BL = 0x2
6255 10:01:13.606325 RPST = 0x0
6256 10:01:13.606426 RD_PRE = 0x0
6257 10:01:13.609512 WR_PRE = 0x1
6258 10:01:13.609586 WR_PST = 0x0
6259 10:01:13.612953 DBI_WR = 0x0
6260 10:01:13.613040 DBI_RD = 0x0
6261 10:01:13.616470 OTF = 0x1
6262 10:01:13.619644 ===================================
6263 10:01:13.626089 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6264 10:01:13.629594 nWR fixed to 30
6265 10:01:13.629696 [ModeRegInit_LP4] CH0 RK0
6266 10:01:13.632640 [ModeRegInit_LP4] CH0 RK1
6267 10:01:13.636146 [ModeRegInit_LP4] CH1 RK0
6268 10:01:13.636232 [ModeRegInit_LP4] CH1 RK1
6269 10:01:13.639880 match AC timing 19
6270 10:01:13.643154 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6271 10:01:13.646540 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6272 10:01:13.652969 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6273 10:01:13.656258 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6274 10:01:13.663160 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6275 10:01:13.663302 ==
6276 10:01:13.666372 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 10:01:13.669234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 10:01:13.669309 ==
6279 10:01:13.676087 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 10:01:13.679617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6281 10:01:13.683103 [CA 0] Center 36 (8~64) winsize 57
6282 10:01:13.685914 [CA 1] Center 36 (8~64) winsize 57
6283 10:01:13.689463 [CA 2] Center 36 (8~64) winsize 57
6284 10:01:13.692922 [CA 3] Center 36 (8~64) winsize 57
6285 10:01:13.696300 [CA 4] Center 36 (8~64) winsize 57
6286 10:01:13.699741 [CA 5] Center 36 (8~64) winsize 57
6287 10:01:13.699826
6288 10:01:13.702635 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6289 10:01:13.702724
6290 10:01:13.706455 [CATrainingPosCal] consider 1 rank data
6291 10:01:13.709809 u2DelayCellTimex100 = 270/100 ps
6292 10:01:13.713269 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 10:01:13.716031 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 10:01:13.719552 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 10:01:13.723144 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 10:01:13.729502 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 10:01:13.732950 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 10:01:13.733050
6299 10:01:13.736150 CA PerBit enable=1, Macro0, CA PI delay=36
6300 10:01:13.736312
6301 10:01:13.739718 [CBTSetCACLKResult] CA Dly = 36
6302 10:01:13.739794 CS Dly: 1 (0~32)
6303 10:01:13.739868 ==
6304 10:01:13.743175 Dram Type= 6, Freq= 0, CH_0, rank 1
6305 10:01:13.746491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 10:01:13.749669 ==
6307 10:01:13.752907 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 10:01:13.759731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6309 10:01:13.763312 [CA 0] Center 36 (8~64) winsize 57
6310 10:01:13.766562 [CA 1] Center 36 (8~64) winsize 57
6311 10:01:13.769803 [CA 2] Center 36 (8~64) winsize 57
6312 10:01:13.773104 [CA 3] Center 36 (8~64) winsize 57
6313 10:01:13.776633 [CA 4] Center 36 (8~64) winsize 57
6314 10:01:13.780062 [CA 5] Center 36 (8~64) winsize 57
6315 10:01:13.780138
6316 10:01:13.783551 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6317 10:01:13.783621
6318 10:01:13.786486 [CATrainingPosCal] consider 2 rank data
6319 10:01:13.790004 u2DelayCellTimex100 = 270/100 ps
6320 10:01:13.793018 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 10:01:13.796372 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 10:01:13.799934 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 10:01:13.803019 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 10:01:13.806343 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 10:01:13.809800 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 10:01:13.809876
6327 10:01:13.813085 CA PerBit enable=1, Macro0, CA PI delay=36
6328 10:01:13.813160
6329 10:01:13.816419 [CBTSetCACLKResult] CA Dly = 36
6330 10:01:13.819988 CS Dly: 1 (0~32)
6331 10:01:13.820072
6332 10:01:13.823050 ----->DramcWriteLeveling(PI) begin...
6333 10:01:13.823124 ==
6334 10:01:13.826349 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 10:01:13.829891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 10:01:13.829969 ==
6337 10:01:13.833370 Write leveling (Byte 0): 40 => 8
6338 10:01:13.836352 Write leveling (Byte 1): 32 => 0
6339 10:01:13.839685 DramcWriteLeveling(PI) end<-----
6340 10:01:13.839759
6341 10:01:13.839832 ==
6342 10:01:13.843186 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 10:01:13.846714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 10:01:13.846797 ==
6345 10:01:13.849799 [Gating] SW mode calibration
6346 10:01:13.856318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6347 10:01:13.863265 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6348 10:01:13.866552 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 10:01:13.870034 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 10:01:13.876432 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 10:01:13.880094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 10:01:13.883508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 10:01:13.889843 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 10:01:13.893336 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 10:01:13.896416 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 10:01:13.903384 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 10:01:13.903464 Total UI for P1: 0, mck2ui 16
6358 10:01:13.910375 best dqsien dly found for B0: ( 0, 14, 24)
6359 10:01:13.910455 Total UI for P1: 0, mck2ui 16
6360 10:01:13.913207 best dqsien dly found for B1: ( 0, 14, 24)
6361 10:01:13.920300 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6362 10:01:13.923151 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6363 10:01:13.923230
6364 10:01:13.926746 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 10:01:13.929872 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 10:01:13.933244 [Gating] SW calibration Done
6367 10:01:13.933326 ==
6368 10:01:13.936759 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 10:01:13.940078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 10:01:13.940154 ==
6371 10:01:13.943064 RX Vref Scan: 0
6372 10:01:13.943136
6373 10:01:13.943228 RX Vref 0 -> 0, step: 1
6374 10:01:13.943289
6375 10:01:13.946638 RX Delay -410 -> 252, step: 16
6376 10:01:13.950212 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6377 10:01:13.956997 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6378 10:01:13.960236 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6379 10:01:13.963448 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6380 10:01:13.966616 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6381 10:01:13.973651 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6382 10:01:13.976575 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6383 10:01:13.979822 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6384 10:01:13.983373 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6385 10:01:13.990480 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6386 10:01:13.993769 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6387 10:01:13.997221 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6388 10:01:14.000313 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6389 10:01:14.006796 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6390 10:01:14.010235 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6391 10:01:14.013444 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6392 10:01:14.013525 ==
6393 10:01:14.017172 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 10:01:14.020179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 10:01:14.024371 ==
6396 10:01:14.024459 DQS Delay:
6397 10:01:14.024521 DQS0 = 35, DQS1 = 51
6398 10:01:14.027127 DQM Delay:
6399 10:01:14.027204 DQM0 = 6, DQM1 = 10
6400 10:01:14.030302 DQ Delay:
6401 10:01:14.030377 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6402 10:01:14.033441 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6403 10:01:14.036854 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6404 10:01:14.040521 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6405 10:01:14.040597
6406 10:01:14.040687
6407 10:01:14.040767 ==
6408 10:01:14.043833 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 10:01:14.049855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 10:01:14.049941 ==
6411 10:01:14.050009
6412 10:01:14.050068
6413 10:01:14.050125 TX Vref Scan disable
6414 10:01:14.053305 == TX Byte 0 ==
6415 10:01:14.056926 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 10:01:14.060340 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 10:01:14.063697 == TX Byte 1 ==
6418 10:01:14.066679 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6419 10:01:14.070332 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6420 10:01:14.070417 ==
6421 10:01:14.074016 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 10:01:14.080557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 10:01:14.080678 ==
6424 10:01:14.080839
6425 10:01:14.080911
6426 10:01:14.080977 TX Vref Scan disable
6427 10:01:14.083801 == TX Byte 0 ==
6428 10:01:14.087009 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 10:01:14.090568 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 10:01:14.094131 == TX Byte 1 ==
6431 10:01:14.097504 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6432 10:01:14.100596 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6433 10:01:14.100693
6434 10:01:14.103926 [DATLAT]
6435 10:01:14.104006 Freq=400, CH0 RK0
6436 10:01:14.104075
6437 10:01:14.107475 DATLAT Default: 0xf
6438 10:01:14.107553 0, 0xFFFF, sum = 0
6439 10:01:14.110665 1, 0xFFFF, sum = 0
6440 10:01:14.110777 2, 0xFFFF, sum = 0
6441 10:01:14.114100 3, 0xFFFF, sum = 0
6442 10:01:14.114251 4, 0xFFFF, sum = 0
6443 10:01:14.117655 5, 0xFFFF, sum = 0
6444 10:01:14.117737 6, 0xFFFF, sum = 0
6445 10:01:14.120529 7, 0xFFFF, sum = 0
6446 10:01:14.120638 8, 0xFFFF, sum = 0
6447 10:01:14.123829 9, 0xFFFF, sum = 0
6448 10:01:14.127512 10, 0xFFFF, sum = 0
6449 10:01:14.127594 11, 0xFFFF, sum = 0
6450 10:01:14.130645 12, 0xFFFF, sum = 0
6451 10:01:14.130727 13, 0x0, sum = 1
6452 10:01:14.133936 14, 0x0, sum = 2
6453 10:01:14.134037 15, 0x0, sum = 3
6454 10:01:14.134103 16, 0x0, sum = 4
6455 10:01:14.137487 best_step = 14
6456 10:01:14.137567
6457 10:01:14.137630 ==
6458 10:01:14.140452 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 10:01:14.143846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 10:01:14.143928 ==
6461 10:01:14.147216 RX Vref Scan: 1
6462 10:01:14.147313
6463 10:01:14.147377 RX Vref 0 -> 0, step: 1
6464 10:01:14.147436
6465 10:01:14.150851 RX Delay -343 -> 252, step: 8
6466 10:01:14.150931
6467 10:01:14.154113 Set Vref, RX VrefLevel [Byte0]: 53
6468 10:01:14.157074 [Byte1]: 56
6469 10:01:14.162254
6470 10:01:14.162367 Final RX Vref Byte 0 = 53 to rank0
6471 10:01:14.165531 Final RX Vref Byte 1 = 56 to rank0
6472 10:01:14.169102 Final RX Vref Byte 0 = 53 to rank1
6473 10:01:14.172699 Final RX Vref Byte 1 = 56 to rank1==
6474 10:01:14.175512 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 10:01:14.182216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 10:01:14.182325 ==
6477 10:01:14.182428 DQS Delay:
6478 10:01:14.182527 DQS0 = 44, DQS1 = 60
6479 10:01:14.185467 DQM Delay:
6480 10:01:14.185541 DQM0 = 11, DQM1 = 14
6481 10:01:14.189128 DQ Delay:
6482 10:01:14.192215 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6483 10:01:14.192316 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6484 10:01:14.195923 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6485 10:01:14.199141 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6486 10:01:14.199245
6487 10:01:14.202190
6488 10:01:14.209020 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6489 10:01:14.212303 CH0 RK0: MR19=C0C, MR18=8D5B
6490 10:01:14.218806 CH0_RK0: MR19=0xC0C, MR18=0x8D5B, DQSOSC=392, MR23=63, INC=384, DEC=256
6491 10:01:14.218889 ==
6492 10:01:14.222577 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 10:01:14.225606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 10:01:14.225706 ==
6495 10:01:14.229293 [Gating] SW mode calibration
6496 10:01:14.235770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 10:01:14.239285 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6498 10:01:14.245487 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 10:01:14.248970 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 10:01:14.252268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 10:01:14.259374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 10:01:14.262282 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 10:01:14.265804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 10:01:14.272479 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 10:01:14.275770 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 10:01:14.278966 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 10:01:14.282286 Total UI for P1: 0, mck2ui 16
6508 10:01:14.286071 best dqsien dly found for B0: ( 0, 14, 24)
6509 10:01:14.288928 Total UI for P1: 0, mck2ui 16
6510 10:01:14.292604 best dqsien dly found for B1: ( 0, 14, 24)
6511 10:01:14.295694 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6512 10:01:14.299342 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6513 10:01:14.299448
6514 10:01:14.305868 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 10:01:14.309045 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 10:01:14.309128 [Gating] SW calibration Done
6517 10:01:14.312253 ==
6518 10:01:14.315720 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 10:01:14.319243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 10:01:14.319322 ==
6521 10:01:14.319403 RX Vref Scan: 0
6522 10:01:14.319481
6523 10:01:14.322809 RX Vref 0 -> 0, step: 1
6524 10:01:14.322909
6525 10:01:14.325803 RX Delay -410 -> 252, step: 16
6526 10:01:14.329387 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6527 10:01:14.332227 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6528 10:01:14.338970 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6529 10:01:14.342833 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6530 10:01:14.346074 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6531 10:01:14.349384 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6532 10:01:14.355723 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6533 10:01:14.359282 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6534 10:01:14.362664 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6535 10:01:14.365746 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6536 10:01:14.372572 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6537 10:01:14.375882 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6538 10:01:14.379393 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6539 10:01:14.382409 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6540 10:01:14.389207 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6541 10:01:14.392603 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6542 10:01:14.392707 ==
6543 10:01:14.396013 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 10:01:14.399371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 10:01:14.399453 ==
6546 10:01:14.402791 DQS Delay:
6547 10:01:14.402872 DQS0 = 35, DQS1 = 51
6548 10:01:14.402936 DQM Delay:
6549 10:01:14.406274 DQM0 = 4, DQM1 = 10
6550 10:01:14.406355 DQ Delay:
6551 10:01:14.409445 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6552 10:01:14.412605 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6553 10:01:14.415984 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6554 10:01:14.419648 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6555 10:01:14.419748
6556 10:01:14.419813
6557 10:01:14.419874 ==
6558 10:01:14.422864 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 10:01:14.425930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 10:01:14.426012 ==
6561 10:01:14.426077
6562 10:01:14.429317
6563 10:01:14.429398 TX Vref Scan disable
6564 10:01:14.433315 == TX Byte 0 ==
6565 10:01:14.436260 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6566 10:01:14.439697 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6567 10:01:14.442927 == TX Byte 1 ==
6568 10:01:14.446510 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6569 10:01:14.449329 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6570 10:01:14.449410 ==
6571 10:01:14.452956 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 10:01:14.456576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 10:01:14.456741 ==
6574 10:01:14.456838
6575 10:01:14.459524
6576 10:01:14.459604 TX Vref Scan disable
6577 10:01:14.462752 == TX Byte 0 ==
6578 10:01:14.466206 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6579 10:01:14.469782 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6580 10:01:14.472784 == TX Byte 1 ==
6581 10:01:14.476058 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6582 10:01:14.479474 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6583 10:01:14.479570
6584 10:01:14.479649 [DATLAT]
6585 10:01:14.482877 Freq=400, CH0 RK1
6586 10:01:14.482958
6587 10:01:14.483020 DATLAT Default: 0xe
6588 10:01:14.486592 0, 0xFFFF, sum = 0
6589 10:01:14.486674 1, 0xFFFF, sum = 0
6590 10:01:14.489972 2, 0xFFFF, sum = 0
6591 10:01:14.490052 3, 0xFFFF, sum = 0
6592 10:01:14.492792 4, 0xFFFF, sum = 0
6593 10:01:14.492873 5, 0xFFFF, sum = 0
6594 10:01:14.496134 6, 0xFFFF, sum = 0
6595 10:01:14.496215 7, 0xFFFF, sum = 0
6596 10:01:14.499907 8, 0xFFFF, sum = 0
6597 10:01:14.503413 9, 0xFFFF, sum = 0
6598 10:01:14.503493 10, 0xFFFF, sum = 0
6599 10:01:14.506214 11, 0xFFFF, sum = 0
6600 10:01:14.506295 12, 0xFFFF, sum = 0
6601 10:01:14.509791 13, 0x0, sum = 1
6602 10:01:14.509879 14, 0x0, sum = 2
6603 10:01:14.512808 15, 0x0, sum = 3
6604 10:01:14.512888 16, 0x0, sum = 4
6605 10:01:14.512953 best_step = 14
6606 10:01:14.513018
6607 10:01:14.516216 ==
6608 10:01:14.519616 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 10:01:14.522769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 10:01:14.522850 ==
6611 10:01:14.522913 RX Vref Scan: 0
6612 10:01:14.522972
6613 10:01:14.526148 RX Vref 0 -> 0, step: 1
6614 10:01:14.526285
6615 10:01:14.529845 RX Delay -343 -> 252, step: 8
6616 10:01:14.536561 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6617 10:01:14.540141 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6618 10:01:14.543725 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6619 10:01:14.546730 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6620 10:01:14.553289 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6621 10:01:14.556935 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6622 10:01:14.560348 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6623 10:01:14.563140 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6624 10:01:14.570069 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6625 10:01:14.573469 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6626 10:01:14.576991 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6627 10:01:14.580442 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6628 10:01:14.586671 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6629 10:01:14.590334 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6630 10:01:14.593840 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6631 10:01:14.597049 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6632 10:01:14.600677 ==
6633 10:01:14.600773 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 10:01:14.607003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 10:01:14.607085 ==
6636 10:01:14.607149 DQS Delay:
6637 10:01:14.609960 DQS0 = 48, DQS1 = 56
6638 10:01:14.610042 DQM Delay:
6639 10:01:14.613631 DQM0 = 13, DQM1 = 10
6640 10:01:14.613713 DQ Delay:
6641 10:01:14.616566 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6642 10:01:14.620223 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6643 10:01:14.623077 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6644 10:01:14.626779 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6645 10:01:14.626861
6646 10:01:14.626925
6647 10:01:14.633569 [DQSOSCAuto] RK1, (LSB)MR18= 0x9566, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6648 10:01:14.636648 CH0 RK1: MR19=C0C, MR18=9566
6649 10:01:14.643776 CH0_RK1: MR19=0xC0C, MR18=0x9566, DQSOSC=391, MR23=63, INC=386, DEC=257
6650 10:01:14.646761 [RxdqsGatingPostProcess] freq 400
6651 10:01:14.650250 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6652 10:01:14.653692 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 10:01:14.657097 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 10:01:14.660663 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 10:01:14.663574 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 10:01:14.666890 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 10:01:14.670280 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 10:01:14.673407 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 10:01:14.676884 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 10:01:14.680449 Pre-setting of DQS Precalculation
6661 10:01:14.683841 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6662 10:01:14.683912 ==
6663 10:01:14.687388 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 10:01:14.693854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 10:01:14.693928 ==
6666 10:01:14.696771 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 10:01:14.703792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6668 10:01:14.706815 [CA 0] Center 36 (8~64) winsize 57
6669 10:01:14.710176 [CA 1] Center 36 (8~64) winsize 57
6670 10:01:14.713782 [CA 2] Center 36 (8~64) winsize 57
6671 10:01:14.716858 [CA 3] Center 36 (8~64) winsize 57
6672 10:01:14.720429 [CA 4] Center 36 (8~64) winsize 57
6673 10:01:14.723988 [CA 5] Center 36 (8~64) winsize 57
6674 10:01:14.724058
6675 10:01:14.727275 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6676 10:01:14.727353
6677 10:01:14.730407 [CATrainingPosCal] consider 1 rank data
6678 10:01:14.733887 u2DelayCellTimex100 = 270/100 ps
6679 10:01:14.737007 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 10:01:14.740421 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 10:01:14.743469 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 10:01:14.747170 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 10:01:14.750427 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 10:01:14.753943 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 10:01:14.754023
6686 10:01:14.757353 CA PerBit enable=1, Macro0, CA PI delay=36
6687 10:01:14.760387
6688 10:01:14.760493 [CBTSetCACLKResult] CA Dly = 36
6689 10:01:14.763973 CS Dly: 1 (0~32)
6690 10:01:14.764053 ==
6691 10:01:14.767186 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 10:01:14.770324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 10:01:14.770405 ==
6694 10:01:14.777142 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 10:01:14.783603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6696 10:01:14.787073 [CA 0] Center 36 (8~64) winsize 57
6697 10:01:14.790368 [CA 1] Center 36 (8~64) winsize 57
6698 10:01:14.790452 [CA 2] Center 36 (8~64) winsize 57
6699 10:01:14.794009 [CA 3] Center 36 (8~64) winsize 57
6700 10:01:14.797397 [CA 4] Center 36 (8~64) winsize 57
6701 10:01:14.800883 [CA 5] Center 36 (8~64) winsize 57
6702 10:01:14.800968
6703 10:01:14.803632 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6704 10:01:14.803716
6705 10:01:14.807132 [CATrainingPosCal] consider 2 rank data
6706 10:01:14.810645 u2DelayCellTimex100 = 270/100 ps
6707 10:01:14.814026 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 10:01:14.820566 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 10:01:14.823961 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 10:01:14.827497 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 10:01:14.830394 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 10:01:14.834099 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 10:01:14.834183
6714 10:01:14.837628 CA PerBit enable=1, Macro0, CA PI delay=36
6715 10:01:14.837712
6716 10:01:14.840543 [CBTSetCACLKResult] CA Dly = 36
6717 10:01:14.840630 CS Dly: 1 (0~32)
6718 10:01:14.840756
6719 10:01:14.844212 ----->DramcWriteLeveling(PI) begin...
6720 10:01:14.847614 ==
6721 10:01:14.850521 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 10:01:14.854089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 10:01:14.854174 ==
6724 10:01:14.857158 Write leveling (Byte 0): 40 => 8
6725 10:01:14.860616 Write leveling (Byte 1): 40 => 8
6726 10:01:14.864055 DramcWriteLeveling(PI) end<-----
6727 10:01:14.864139
6728 10:01:14.864253 ==
6729 10:01:14.867475 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 10:01:14.871101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 10:01:14.871190 ==
6732 10:01:14.874080 [Gating] SW mode calibration
6733 10:01:14.880535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6734 10:01:14.883954 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6735 10:01:14.890802 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 10:01:14.894111 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 10:01:14.897449 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 10:01:14.904062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 10:01:14.907565 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 10:01:14.911110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 10:01:14.917529 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 10:01:14.920985 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 10:01:14.924351 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 10:01:14.927432 Total UI for P1: 0, mck2ui 16
6745 10:01:14.931000 best dqsien dly found for B0: ( 0, 14, 24)
6746 10:01:14.934558 Total UI for P1: 0, mck2ui 16
6747 10:01:14.937360 best dqsien dly found for B1: ( 0, 14, 24)
6748 10:01:14.940903 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6749 10:01:14.944473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6750 10:01:14.944557
6751 10:01:14.947401 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 10:01:14.954036 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 10:01:14.954121 [Gating] SW calibration Done
6754 10:01:14.957445 ==
6755 10:01:14.957530 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 10:01:14.964331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 10:01:14.964416 ==
6758 10:01:14.964518 RX Vref Scan: 0
6759 10:01:14.964618
6760 10:01:14.967875 RX Vref 0 -> 0, step: 1
6761 10:01:14.967959
6762 10:01:14.970746 RX Delay -410 -> 252, step: 16
6763 10:01:14.974569 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6764 10:01:14.977423 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6765 10:01:14.984155 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6766 10:01:14.987236 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6767 10:01:14.990916 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6768 10:01:14.993845 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6769 10:01:15.000661 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6770 10:01:15.003835 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6771 10:01:15.007352 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6772 10:01:15.011132 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6773 10:01:15.017430 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6774 10:01:15.020703 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6775 10:01:15.024043 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6776 10:01:15.027371 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6777 10:01:15.034471 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6778 10:01:15.037835 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6779 10:01:15.037920 ==
6780 10:01:15.040939 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 10:01:15.043996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 10:01:15.044081 ==
6783 10:01:15.047336 DQS Delay:
6784 10:01:15.047420 DQS0 = 51, DQS1 = 59
6785 10:01:15.050745 DQM Delay:
6786 10:01:15.050829 DQM0 = 19, DQM1 = 16
6787 10:01:15.050915 DQ Delay:
6788 10:01:15.054349 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6789 10:01:15.057773 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6790 10:01:15.060580 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6791 10:01:15.064107 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6792 10:01:15.064191
6793 10:01:15.064276
6794 10:01:15.064357 ==
6795 10:01:15.067525 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 10:01:15.073941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 10:01:15.074026 ==
6798 10:01:15.074112
6799 10:01:15.074193
6800 10:01:15.074273 TX Vref Scan disable
6801 10:01:15.077263 == TX Byte 0 ==
6802 10:01:15.080798 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 10:01:15.084262 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 10:01:15.087791 == TX Byte 1 ==
6805 10:01:15.091121 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 10:01:15.094494 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 10:01:15.094578 ==
6808 10:01:15.097594 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 10:01:15.103986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 10:01:15.104071 ==
6811 10:01:15.104157
6812 10:01:15.104238
6813 10:01:15.104318 TX Vref Scan disable
6814 10:01:15.107767 == TX Byte 0 ==
6815 10:01:15.111270 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 10:01:15.114115 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 10:01:15.117711 == TX Byte 1 ==
6818 10:01:15.120934 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 10:01:15.124460 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 10:01:15.124544
6821 10:01:15.128078 [DATLAT]
6822 10:01:15.128162 Freq=400, CH1 RK0
6823 10:01:15.128248
6824 10:01:15.131390 DATLAT Default: 0xf
6825 10:01:15.131474 0, 0xFFFF, sum = 0
6826 10:01:15.134312 1, 0xFFFF, sum = 0
6827 10:01:15.134398 2, 0xFFFF, sum = 0
6828 10:01:15.137961 3, 0xFFFF, sum = 0
6829 10:01:15.138047 4, 0xFFFF, sum = 0
6830 10:01:15.141562 5, 0xFFFF, sum = 0
6831 10:01:15.141647 6, 0xFFFF, sum = 0
6832 10:01:15.144487 7, 0xFFFF, sum = 0
6833 10:01:15.144572 8, 0xFFFF, sum = 0
6834 10:01:15.147961 9, 0xFFFF, sum = 0
6835 10:01:15.148047 10, 0xFFFF, sum = 0
6836 10:01:15.151301 11, 0xFFFF, sum = 0
6837 10:01:15.151390 12, 0xFFFF, sum = 0
6838 10:01:15.154427 13, 0x0, sum = 1
6839 10:01:15.154513 14, 0x0, sum = 2
6840 10:01:15.157700 15, 0x0, sum = 3
6841 10:01:15.157785 16, 0x0, sum = 4
6842 10:01:15.161454 best_step = 14
6843 10:01:15.161555
6844 10:01:15.161656 ==
6845 10:01:15.164744 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 10:01:15.168043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 10:01:15.168128 ==
6848 10:01:15.171059 RX Vref Scan: 1
6849 10:01:15.171143
6850 10:01:15.171231 RX Vref 0 -> 0, step: 1
6851 10:01:15.171312
6852 10:01:15.174601 RX Delay -359 -> 252, step: 8
6853 10:01:15.174685
6854 10:01:15.178083 Set Vref, RX VrefLevel [Byte0]: 57
6855 10:01:15.181135 [Byte1]: 52
6856 10:01:15.185735
6857 10:01:15.185820 Final RX Vref Byte 0 = 57 to rank0
6858 10:01:15.188970 Final RX Vref Byte 1 = 52 to rank0
6859 10:01:15.192059 Final RX Vref Byte 0 = 57 to rank1
6860 10:01:15.195681 Final RX Vref Byte 1 = 52 to rank1==
6861 10:01:15.198803 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 10:01:15.205650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 10:01:15.205731 ==
6864 10:01:15.205794 DQS Delay:
6865 10:01:15.209395 DQS0 = 48, DQS1 = 60
6866 10:01:15.209475 DQM Delay:
6867 10:01:15.209538 DQM0 = 12, DQM1 = 13
6868 10:01:15.212090 DQ Delay:
6869 10:01:15.215509 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6870 10:01:15.215589 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6871 10:01:15.219058 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6872 10:01:15.222136 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6873 10:01:15.222216
6874 10:01:15.222279
6875 10:01:15.232472 [DQSOSCAuto] RK0, (LSB)MR18= 0x862e, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6876 10:01:15.235587 CH1 RK0: MR19=C0C, MR18=862E
6877 10:01:15.242429 CH1_RK0: MR19=0xC0C, MR18=0x862E, DQSOSC=393, MR23=63, INC=382, DEC=254
6878 10:01:15.242510 ==
6879 10:01:15.245447 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 10:01:15.249055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 10:01:15.249142 ==
6882 10:01:15.252517 [Gating] SW mode calibration
6883 10:01:15.259319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6884 10:01:15.262211 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6885 10:01:15.269212 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 10:01:15.272740 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 10:01:15.275863 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 10:01:15.282244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 10:01:15.285836 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 10:01:15.288722 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 10:01:15.295845 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 10:01:15.299084 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 10:01:15.302414 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 10:01:15.305712 Total UI for P1: 0, mck2ui 16
6895 10:01:15.309037 best dqsien dly found for B0: ( 0, 14, 24)
6896 10:01:15.312551 Total UI for P1: 0, mck2ui 16
6897 10:01:15.316070 best dqsien dly found for B1: ( 0, 14, 24)
6898 10:01:15.319171 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6899 10:01:15.322321 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6900 10:01:15.322401
6901 10:01:15.329420 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 10:01:15.332396 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 10:01:15.332477 [Gating] SW calibration Done
6904 10:01:15.335644 ==
6905 10:01:15.335724 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 10:01:15.342447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 10:01:15.342528 ==
6908 10:01:15.342591 RX Vref Scan: 0
6909 10:01:15.342650
6910 10:01:15.345752 RX Vref 0 -> 0, step: 1
6911 10:01:15.345832
6912 10:01:15.349016 RX Delay -410 -> 252, step: 16
6913 10:01:15.352634 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6914 10:01:15.355778 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6915 10:01:15.362407 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6916 10:01:15.365588 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6917 10:01:15.369044 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6918 10:01:15.372423 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6919 10:01:15.379074 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6920 10:01:15.382399 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6921 10:01:15.386030 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6922 10:01:15.389086 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6923 10:01:15.395993 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6924 10:01:15.398967 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6925 10:01:15.402289 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6926 10:01:15.405830 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6927 10:01:15.412272 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6928 10:01:15.415949 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6929 10:01:15.416034 ==
6930 10:01:15.419559 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 10:01:15.422384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 10:01:15.422469 ==
6933 10:01:15.425794 DQS Delay:
6934 10:01:15.425878 DQS0 = 43, DQS1 = 59
6935 10:01:15.425965 DQM Delay:
6936 10:01:15.429294 DQM0 = 10, DQM1 = 18
6937 10:01:15.429375 DQ Delay:
6938 10:01:15.432496 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6939 10:01:15.435715 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6940 10:01:15.439226 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6941 10:01:15.442668 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6942 10:01:15.442749
6943 10:01:15.442813
6944 10:01:15.442876 ==
6945 10:01:15.445692 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 10:01:15.448939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 10:01:15.452531 ==
6948 10:01:15.452638
6949 10:01:15.452752
6950 10:01:15.452813 TX Vref Scan disable
6951 10:01:15.455885 == TX Byte 0 ==
6952 10:01:15.458973 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6953 10:01:15.462375 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6954 10:01:15.465857 == TX Byte 1 ==
6955 10:01:15.468955 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6956 10:01:15.472234 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6957 10:01:15.472346 ==
6958 10:01:15.475503 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 10:01:15.479426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 10:01:15.482316 ==
6961 10:01:15.482397
6962 10:01:15.482460
6963 10:01:15.482519 TX Vref Scan disable
6964 10:01:15.485728 == TX Byte 0 ==
6965 10:01:15.489419 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6966 10:01:15.492505 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6967 10:01:15.496039 == TX Byte 1 ==
6968 10:01:15.499497 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6969 10:01:15.502386 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6970 10:01:15.502466
6971 10:01:15.502530 [DATLAT]
6972 10:01:15.505972 Freq=400, CH1 RK1
6973 10:01:15.506053
6974 10:01:15.506116 DATLAT Default: 0xe
6975 10:01:15.509386 0, 0xFFFF, sum = 0
6976 10:01:15.512479 1, 0xFFFF, sum = 0
6977 10:01:15.512582 2, 0xFFFF, sum = 0
6978 10:01:15.515836 3, 0xFFFF, sum = 0
6979 10:01:15.515917 4, 0xFFFF, sum = 0
6980 10:01:15.519517 5, 0xFFFF, sum = 0
6981 10:01:15.519598 6, 0xFFFF, sum = 0
6982 10:01:15.522662 7, 0xFFFF, sum = 0
6983 10:01:15.522744 8, 0xFFFF, sum = 0
6984 10:01:15.525955 9, 0xFFFF, sum = 0
6985 10:01:15.526036 10, 0xFFFF, sum = 0
6986 10:01:15.529015 11, 0xFFFF, sum = 0
6987 10:01:15.529097 12, 0xFFFF, sum = 0
6988 10:01:15.532555 13, 0x0, sum = 1
6989 10:01:15.532663 14, 0x0, sum = 2
6990 10:01:15.536414 15, 0x0, sum = 3
6991 10:01:15.536526 16, 0x0, sum = 4
6992 10:01:15.539361 best_step = 14
6993 10:01:15.539441
6994 10:01:15.539504 ==
6995 10:01:15.542625 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 10:01:15.546009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 10:01:15.546090 ==
6998 10:01:15.546162 RX Vref Scan: 0
6999 10:01:15.546252
7000 10:01:15.549360 RX Vref 0 -> 0, step: 1
7001 10:01:15.549476
7002 10:01:15.552879 RX Delay -359 -> 252, step: 8
7003 10:01:15.559606 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
7004 10:01:15.563355 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7005 10:01:15.566764 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7006 10:01:15.570279 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
7007 10:01:15.576576 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7008 10:01:15.580296 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7009 10:01:15.583408 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7010 10:01:15.586686 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7011 10:01:15.593806 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7012 10:01:15.596896 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
7013 10:01:15.599904 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7014 10:01:15.603272 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7015 10:01:15.610424 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7016 10:01:15.613241 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7017 10:01:15.616616 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7018 10:01:15.620257 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7019 10:01:15.623316 ==
7020 10:01:15.626596 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 10:01:15.629839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 10:01:15.629920 ==
7023 10:01:15.629984 DQS Delay:
7024 10:01:15.633184 DQS0 = 52, DQS1 = 60
7025 10:01:15.633265 DQM Delay:
7026 10:01:15.636802 DQM0 = 13, DQM1 = 12
7027 10:01:15.636882 DQ Delay:
7028 10:01:15.639811 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7029 10:01:15.643202 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7030 10:01:15.646480 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
7031 10:01:15.650035 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
7032 10:01:15.650116
7033 10:01:15.650180
7034 10:01:15.656819 [DQSOSCAuto] RK1, (LSB)MR18= 0x7a90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
7035 10:01:15.660389 CH1 RK1: MR19=C0C, MR18=7A90
7036 10:01:15.666686 CH1_RK1: MR19=0xC0C, MR18=0x7A90, DQSOSC=391, MR23=63, INC=386, DEC=257
7037 10:01:15.670253 [RxdqsGatingPostProcess] freq 400
7038 10:01:15.673681 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7039 10:01:15.676601 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 10:01:15.680118 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 10:01:15.683636 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 10:01:15.686953 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 10:01:15.690278 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 10:01:15.693666 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 10:01:15.696924 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 10:01:15.700119 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 10:01:15.703577 Pre-setting of DQS Precalculation
7048 10:01:15.706728 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7049 10:01:15.713448 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7050 10:01:15.724007 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7051 10:01:15.724088
7052 10:01:15.724151
7053 10:01:15.724209 [Calibration Summary] 800 Mbps
7054 10:01:15.726959 CH 0, Rank 0
7055 10:01:15.727039 SW Impedance : PASS
7056 10:01:15.730292 DUTY Scan : NO K
7057 10:01:15.733525 ZQ Calibration : PASS
7058 10:01:15.733606 Jitter Meter : NO K
7059 10:01:15.737248 CBT Training : PASS
7060 10:01:15.740207 Write leveling : PASS
7061 10:01:15.740287 RX DQS gating : PASS
7062 10:01:15.743600 RX DQ/DQS(RDDQC) : PASS
7063 10:01:15.747202 TX DQ/DQS : PASS
7064 10:01:15.747282 RX DATLAT : PASS
7065 10:01:15.750636 RX DQ/DQS(Engine): PASS
7066 10:01:15.754038 TX OE : NO K
7067 10:01:15.754118 All Pass.
7068 10:01:15.754182
7069 10:01:15.754242 CH 0, Rank 1
7070 10:01:15.756980 SW Impedance : PASS
7071 10:01:15.760235 DUTY Scan : NO K
7072 10:01:15.760342 ZQ Calibration : PASS
7073 10:01:15.763704 Jitter Meter : NO K
7074 10:01:15.763784 CBT Training : PASS
7075 10:01:15.767371 Write leveling : NO K
7076 10:01:15.770376 RX DQS gating : PASS
7077 10:01:15.770462 RX DQ/DQS(RDDQC) : PASS
7078 10:01:15.773840 TX DQ/DQS : PASS
7079 10:01:15.777081 RX DATLAT : PASS
7080 10:01:15.777161 RX DQ/DQS(Engine): PASS
7081 10:01:15.780655 TX OE : NO K
7082 10:01:15.780777 All Pass.
7083 10:01:15.780840
7084 10:01:15.783721 CH 1, Rank 0
7085 10:01:15.783801 SW Impedance : PASS
7086 10:01:15.787180 DUTY Scan : NO K
7087 10:01:15.790461 ZQ Calibration : PASS
7088 10:01:15.790542 Jitter Meter : NO K
7089 10:01:15.793872 CBT Training : PASS
7090 10:01:15.797321 Write leveling : PASS
7091 10:01:15.797409 RX DQS gating : PASS
7092 10:01:15.801033 RX DQ/DQS(RDDQC) : PASS
7093 10:01:15.801118 TX DQ/DQS : PASS
7094 10:01:15.803852 RX DATLAT : PASS
7095 10:01:15.807496 RX DQ/DQS(Engine): PASS
7096 10:01:15.807576 TX OE : NO K
7097 10:01:15.810602 All Pass.
7098 10:01:15.810689
7099 10:01:15.810752 CH 1, Rank 1
7100 10:01:15.814054 SW Impedance : PASS
7101 10:01:15.814133 DUTY Scan : NO K
7102 10:01:15.817390 ZQ Calibration : PASS
7103 10:01:15.820565 Jitter Meter : NO K
7104 10:01:15.820678 CBT Training : PASS
7105 10:01:15.824191 Write leveling : NO K
7106 10:01:15.827617 RX DQS gating : PASS
7107 10:01:15.827697 RX DQ/DQS(RDDQC) : PASS
7108 10:01:15.831176 TX DQ/DQS : PASS
7109 10:01:15.833997 RX DATLAT : PASS
7110 10:01:15.834077 RX DQ/DQS(Engine): PASS
7111 10:01:15.837213 TX OE : NO K
7112 10:01:15.837294 All Pass.
7113 10:01:15.837357
7114 10:01:15.840879 DramC Write-DBI off
7115 10:01:15.844368 PER_BANK_REFRESH: Hybrid Mode
7116 10:01:15.844448 TX_TRACKING: ON
7117 10:01:15.854304 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7118 10:01:15.857457 [FAST_K] Save calibration result to emmc
7119 10:01:15.861028 dramc_set_vcore_voltage set vcore to 725000
7120 10:01:15.864436 Read voltage for 1600, 0
7121 10:01:15.864542 Vio18 = 0
7122 10:01:15.864635 Vcore = 725000
7123 10:01:15.867327 Vdram = 0
7124 10:01:15.867410 Vddq = 0
7125 10:01:15.867473 Vmddr = 0
7126 10:01:15.873995 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7127 10:01:15.877424 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7128 10:01:15.881200 MEM_TYPE=3, freq_sel=13
7129 10:01:15.884029 sv_algorithm_assistance_LP4_3733
7130 10:01:15.887887 ============ PULL DRAM RESETB DOWN ============
7131 10:01:15.891030 ========== PULL DRAM RESETB DOWN end =========
7132 10:01:15.897690 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7133 10:01:15.900957 ===================================
7134 10:01:15.901038 LPDDR4 DRAM CONFIGURATION
7135 10:01:15.904298 ===================================
7136 10:01:15.907403 EX_ROW_EN[0] = 0x0
7137 10:01:15.907479 EX_ROW_EN[1] = 0x0
7138 10:01:15.911030 LP4Y_EN = 0x0
7139 10:01:15.911103 WORK_FSP = 0x1
7140 10:01:15.914416 WL = 0x5
7141 10:01:15.914485 RL = 0x5
7142 10:01:15.917930 BL = 0x2
7143 10:01:15.920832 RPST = 0x0
7144 10:01:15.920912 RD_PRE = 0x0
7145 10:01:15.924476 WR_PRE = 0x1
7146 10:01:15.924556 WR_PST = 0x1
7147 10:01:15.927913 DBI_WR = 0x0
7148 10:01:15.927993 DBI_RD = 0x0
7149 10:01:15.931501 OTF = 0x1
7150 10:01:15.934211 ===================================
7151 10:01:15.937794 ===================================
7152 10:01:15.937882 ANA top config
7153 10:01:15.940964 ===================================
7154 10:01:15.944285 DLL_ASYNC_EN = 0
7155 10:01:15.947750 ALL_SLAVE_EN = 0
7156 10:01:15.947831 NEW_RANK_MODE = 1
7157 10:01:15.951251 DLL_IDLE_MODE = 1
7158 10:01:15.954888 LP45_APHY_COMB_EN = 1
7159 10:01:15.957795 TX_ODT_DIS = 0
7160 10:01:15.957876 NEW_8X_MODE = 1
7161 10:01:15.961122 ===================================
7162 10:01:15.964538 ===================================
7163 10:01:15.968091 data_rate = 3200
7164 10:01:15.971090 CKR = 1
7165 10:01:15.974472 DQ_P2S_RATIO = 8
7166 10:01:15.977946 ===================================
7167 10:01:15.981200 CA_P2S_RATIO = 8
7168 10:01:15.984493 DQ_CA_OPEN = 0
7169 10:01:15.984599 DQ_SEMI_OPEN = 0
7170 10:01:15.987768 CA_SEMI_OPEN = 0
7171 10:01:15.991436 CA_FULL_RATE = 0
7172 10:01:15.994369 DQ_CKDIV4_EN = 0
7173 10:01:15.997751 CA_CKDIV4_EN = 0
7174 10:01:15.997831 CA_PREDIV_EN = 0
7175 10:01:16.001153 PH8_DLY = 12
7176 10:01:16.004600 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7177 10:01:16.007605 DQ_AAMCK_DIV = 4
7178 10:01:16.011388 CA_AAMCK_DIV = 4
7179 10:01:16.014605 CA_ADMCK_DIV = 4
7180 10:01:16.014729 DQ_TRACK_CA_EN = 0
7181 10:01:16.017738 CA_PICK = 1600
7182 10:01:16.021633 CA_MCKIO = 1600
7183 10:01:16.024495 MCKIO_SEMI = 0
7184 10:01:16.028143 PLL_FREQ = 3068
7185 10:01:16.031373 DQ_UI_PI_RATIO = 32
7186 10:01:16.034748 CA_UI_PI_RATIO = 0
7187 10:01:16.037928 ===================================
7188 10:01:16.041497 ===================================
7189 10:01:16.041578 memory_type:LPDDR4
7190 10:01:16.044445 GP_NUM : 10
7191 10:01:16.047802 SRAM_EN : 1
7192 10:01:16.047878 MD32_EN : 0
7193 10:01:16.051438 ===================================
7194 10:01:16.055005 [ANA_INIT] >>>>>>>>>>>>>>
7195 10:01:16.057828 <<<<<< [CONFIGURE PHASE]: ANA_TX
7196 10:01:16.061534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7197 10:01:16.064894 ===================================
7198 10:01:16.068318 data_rate = 3200,PCW = 0X7600
7199 10:01:16.071589 ===================================
7200 10:01:16.074628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7201 10:01:16.078034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 10:01:16.084900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 10:01:16.088379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7204 10:01:16.091438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7205 10:01:16.094754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7206 10:01:16.098165 [ANA_INIT] flow start
7207 10:01:16.101660 [ANA_INIT] PLL >>>>>>>>
7208 10:01:16.101740 [ANA_INIT] PLL <<<<<<<<
7209 10:01:16.104654 [ANA_INIT] MIDPI >>>>>>>>
7210 10:01:16.107955 [ANA_INIT] MIDPI <<<<<<<<
7211 10:01:16.108035 [ANA_INIT] DLL >>>>>>>>
7212 10:01:16.111381 [ANA_INIT] DLL <<<<<<<<
7213 10:01:16.115047 [ANA_INIT] flow end
7214 10:01:16.118062 ============ LP4 DIFF to SE enter ============
7215 10:01:16.121323 ============ LP4 DIFF to SE exit ============
7216 10:01:16.125011 [ANA_INIT] <<<<<<<<<<<<<
7217 10:01:16.128344 [Flow] Enable top DCM control >>>>>
7218 10:01:16.131422 [Flow] Enable top DCM control <<<<<
7219 10:01:16.134866 Enable DLL master slave shuffle
7220 10:01:16.138461 ==============================================================
7221 10:01:16.142000 Gating Mode config
7222 10:01:16.144876 ==============================================================
7223 10:01:16.148533 Config description:
7224 10:01:16.158154 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7225 10:01:16.165209 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7226 10:01:16.168567 SELPH_MODE 0: By rank 1: By Phase
7227 10:01:16.175439 ==============================================================
7228 10:01:16.178251 GAT_TRACK_EN = 1
7229 10:01:16.181804 RX_GATING_MODE = 2
7230 10:01:16.185378 RX_GATING_TRACK_MODE = 2
7231 10:01:16.188291 SELPH_MODE = 1
7232 10:01:16.188398 PICG_EARLY_EN = 1
7233 10:01:16.192076 VALID_LAT_VALUE = 1
7234 10:01:16.198292 ==============================================================
7235 10:01:16.202129 Enter into Gating configuration >>>>
7236 10:01:16.205265 Exit from Gating configuration <<<<
7237 10:01:16.208567 Enter into DVFS_PRE_config >>>>>
7238 10:01:16.218524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7239 10:01:16.221993 Exit from DVFS_PRE_config <<<<<
7240 10:01:16.225435 Enter into PICG configuration >>>>
7241 10:01:16.228250 Exit from PICG configuration <<<<
7242 10:01:16.231657 [RX_INPUT] configuration >>>>>
7243 10:01:16.234992 [RX_INPUT] configuration <<<<<
7244 10:01:16.238222 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7245 10:01:16.244855 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7246 10:01:16.251770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 10:01:16.258703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 10:01:16.265545 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 10:01:16.268619 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 10:01:16.275502 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7251 10:01:16.278411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7252 10:01:16.281749 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7253 10:01:16.285579 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7254 10:01:16.288544 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7255 10:01:16.295523 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 10:01:16.299390 ===================================
7257 10:01:16.299471 LPDDR4 DRAM CONFIGURATION
7258 10:01:16.302016 ===================================
7259 10:01:16.305481 EX_ROW_EN[0] = 0x0
7260 10:01:16.308613 EX_ROW_EN[1] = 0x0
7261 10:01:16.308728 LP4Y_EN = 0x0
7262 10:01:16.312292 WORK_FSP = 0x1
7263 10:01:16.312400 WL = 0x5
7264 10:01:16.314876 RL = 0x5
7265 10:01:16.314949 BL = 0x2
7266 10:01:16.318311 RPST = 0x0
7267 10:01:16.318391 RD_PRE = 0x0
7268 10:01:16.321896 WR_PRE = 0x1
7269 10:01:16.321977 WR_PST = 0x1
7270 10:01:16.325481 DBI_WR = 0x0
7271 10:01:16.325561 DBI_RD = 0x0
7272 10:01:16.328891 OTF = 0x1
7273 10:01:16.331533 ===================================
7274 10:01:16.335269 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7275 10:01:16.338282 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7276 10:01:16.345025 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 10:01:16.348631 ===================================
7278 10:01:16.348762 LPDDR4 DRAM CONFIGURATION
7279 10:01:16.352032 ===================================
7280 10:01:16.355079 EX_ROW_EN[0] = 0x10
7281 10:01:16.358463 EX_ROW_EN[1] = 0x0
7282 10:01:16.358544 LP4Y_EN = 0x0
7283 10:01:16.361695 WORK_FSP = 0x1
7284 10:01:16.361776 WL = 0x5
7285 10:01:16.365177 RL = 0x5
7286 10:01:16.365257 BL = 0x2
7287 10:01:16.368644 RPST = 0x0
7288 10:01:16.368773 RD_PRE = 0x0
7289 10:01:16.372045 WR_PRE = 0x1
7290 10:01:16.372125 WR_PST = 0x1
7291 10:01:16.375361 DBI_WR = 0x0
7292 10:01:16.375441 DBI_RD = 0x0
7293 10:01:16.378703 OTF = 0x1
7294 10:01:16.382254 ===================================
7295 10:01:16.388660 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7296 10:01:16.388749 ==
7297 10:01:16.391807 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 10:01:16.395344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 10:01:16.395425 ==
7300 10:01:16.398982 [Duty_Offset_Calibration]
7301 10:01:16.399063 B0:2 B1:-1 CA:1
7302 10:01:16.399126
7303 10:01:16.402004 [DutyScan_Calibration_Flow] k_type=0
7304 10:01:16.411188
7305 10:01:16.411268 ==CLK 0==
7306 10:01:16.414882 Final CLK duty delay cell = -4
7307 10:01:16.417908 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7308 10:01:16.421291 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7309 10:01:16.424871 [-4] AVG Duty = 4937%(X100)
7310 10:01:16.424952
7311 10:01:16.427811 CH0 CLK Duty spec in!! Max-Min= 187%
7312 10:01:16.431280 [DutyScan_Calibration_Flow] ====Done====
7313 10:01:16.431361
7314 10:01:16.434747 [DutyScan_Calibration_Flow] k_type=1
7315 10:01:16.450668
7316 10:01:16.450775 ==DQS 0 ==
7317 10:01:16.454191 Final DQS duty delay cell = 0
7318 10:01:16.457767 [0] MAX Duty = 5125%(X100), DQS PI = 20
7319 10:01:16.461267 [0] MIN Duty = 5000%(X100), DQS PI = 14
7320 10:01:16.461347 [0] AVG Duty = 5062%(X100)
7321 10:01:16.464280
7322 10:01:16.464360 ==DQS 1 ==
7323 10:01:16.467680 Final DQS duty delay cell = -4
7324 10:01:16.471062 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7325 10:01:16.474697 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7326 10:01:16.478071 [-4] AVG Duty = 5046%(X100)
7327 10:01:16.478151
7328 10:01:16.480997 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7329 10:01:16.481078
7330 10:01:16.484359 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7331 10:01:16.487756 [DutyScan_Calibration_Flow] ====Done====
7332 10:01:16.487836
7333 10:01:16.491334 [DutyScan_Calibration_Flow] k_type=3
7334 10:01:16.508377
7335 10:01:16.508456 ==DQM 0 ==
7336 10:01:16.511600 Final DQM duty delay cell = 0
7337 10:01:16.515048 [0] MAX Duty = 5000%(X100), DQS PI = 20
7338 10:01:16.518386 [0] MIN Duty = 4875%(X100), DQS PI = 4
7339 10:01:16.518466 [0] AVG Duty = 4937%(X100)
7340 10:01:16.521475
7341 10:01:16.521555 ==DQM 1 ==
7342 10:01:16.525202 Final DQM duty delay cell = 0
7343 10:01:16.528562 [0] MAX Duty = 5218%(X100), DQS PI = 58
7344 10:01:16.531663 [0] MIN Duty = 4969%(X100), DQS PI = 18
7345 10:01:16.531744 [0] AVG Duty = 5093%(X100)
7346 10:01:16.531806
7347 10:01:16.538450 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7348 10:01:16.538531
7349 10:01:16.541888 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7350 10:01:16.545413 [DutyScan_Calibration_Flow] ====Done====
7351 10:01:16.545493
7352 10:01:16.548406 [DutyScan_Calibration_Flow] k_type=2
7353 10:01:16.564621
7354 10:01:16.564753 ==DQ 0 ==
7355 10:01:16.568058 Final DQ duty delay cell = -4
7356 10:01:16.571564 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7357 10:01:16.574826 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7358 10:01:16.578041 [-4] AVG Duty = 4937%(X100)
7359 10:01:16.578120
7360 10:01:16.578183 ==DQ 1 ==
7361 10:01:16.581448 Final DQ duty delay cell = 0
7362 10:01:16.584828 [0] MAX Duty = 5000%(X100), DQS PI = 0
7363 10:01:16.588282 [0] MIN Duty = 4907%(X100), DQS PI = 18
7364 10:01:16.588361 [0] AVG Duty = 4953%(X100)
7365 10:01:16.591499
7366 10:01:16.595089 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7367 10:01:16.595168
7368 10:01:16.597900 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7369 10:01:16.601268 [DutyScan_Calibration_Flow] ====Done====
7370 10:01:16.601351 ==
7371 10:01:16.604627 Dram Type= 6, Freq= 0, CH_1, rank 0
7372 10:01:16.608295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7373 10:01:16.608375 ==
7374 10:01:16.611301 [Duty_Offset_Calibration]
7375 10:01:16.611380 B0:1 B1:1 CA:2
7376 10:01:16.611442
7377 10:01:16.615116 [DutyScan_Calibration_Flow] k_type=0
7378 10:01:16.625230
7379 10:01:16.625309 ==CLK 0==
7380 10:01:16.628463 Final CLK duty delay cell = 0
7381 10:01:16.631781 [0] MAX Duty = 5187%(X100), DQS PI = 24
7382 10:01:16.635327 [0] MIN Duty = 4938%(X100), DQS PI = 50
7383 10:01:16.635414 [0] AVG Duty = 5062%(X100)
7384 10:01:16.635484
7385 10:01:16.638248 CH1 CLK Duty spec in!! Max-Min= 249%
7386 10:01:16.645176 [DutyScan_Calibration_Flow] ====Done====
7387 10:01:16.645261
7388 10:01:16.648688 [DutyScan_Calibration_Flow] k_type=1
7389 10:01:16.665097
7390 10:01:16.665216 ==DQS 0 ==
7391 10:01:16.668074 Final DQS duty delay cell = 0
7392 10:01:16.671473 [0] MAX Duty = 5062%(X100), DQS PI = 20
7393 10:01:16.674959 [0] MIN Duty = 4813%(X100), DQS PI = 52
7394 10:01:16.678586 [0] AVG Duty = 4937%(X100)
7395 10:01:16.678755
7396 10:01:16.678886 ==DQS 1 ==
7397 10:01:16.681577 Final DQS duty delay cell = 0
7398 10:01:16.684894 [0] MAX Duty = 5031%(X100), DQS PI = 34
7399 10:01:16.688200 [0] MIN Duty = 4938%(X100), DQS PI = 14
7400 10:01:16.691529 [0] AVG Duty = 4984%(X100)
7401 10:01:16.691609
7402 10:01:16.694919 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7403 10:01:16.694995
7404 10:01:16.698000 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7405 10:01:16.701231 [DutyScan_Calibration_Flow] ====Done====
7406 10:01:16.701299
7407 10:01:16.704617 [DutyScan_Calibration_Flow] k_type=3
7408 10:01:16.721410
7409 10:01:16.721566 ==DQM 0 ==
7410 10:01:16.724999 Final DQM duty delay cell = 0
7411 10:01:16.728150 [0] MAX Duty = 5156%(X100), DQS PI = 22
7412 10:01:16.731825 [0] MIN Duty = 4813%(X100), DQS PI = 50
7413 10:01:16.735256 [0] AVG Duty = 4984%(X100)
7414 10:01:16.735329
7415 10:01:16.735406 ==DQM 1 ==
7416 10:01:16.738312 Final DQM duty delay cell = 0
7417 10:01:16.741447 [0] MAX Duty = 5125%(X100), DQS PI = 10
7418 10:01:16.744990 [0] MIN Duty = 4875%(X100), DQS PI = 22
7419 10:01:16.745064 [0] AVG Duty = 5000%(X100)
7420 10:01:16.748407
7421 10:01:16.751636 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7422 10:01:16.751741
7423 10:01:16.755093 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7424 10:01:16.758594 [DutyScan_Calibration_Flow] ====Done====
7425 10:01:16.758691
7426 10:01:16.761566 [DutyScan_Calibration_Flow] k_type=2
7427 10:01:16.778759
7428 10:01:16.778839 ==DQ 0 ==
7429 10:01:16.782238 Final DQ duty delay cell = 0
7430 10:01:16.784989 [0] MAX Duty = 5156%(X100), DQS PI = 20
7431 10:01:16.788440 [0] MIN Duty = 4907%(X100), DQS PI = 52
7432 10:01:16.788509 [0] AVG Duty = 5031%(X100)
7433 10:01:16.792025
7434 10:01:16.792094 ==DQ 1 ==
7435 10:01:16.794941 Final DQ duty delay cell = 0
7436 10:01:16.798355 [0] MAX Duty = 5124%(X100), DQS PI = 42
7437 10:01:16.801917 [0] MIN Duty = 5031%(X100), DQS PI = 0
7438 10:01:16.801990 [0] AVG Duty = 5077%(X100)
7439 10:01:16.802051
7440 10:01:16.805348 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7441 10:01:16.805417
7442 10:01:16.808461 CH1 DQ 1 Duty spec in!! Max-Min= 93%
7443 10:01:16.815213 [DutyScan_Calibration_Flow] ====Done====
7444 10:01:16.818773 nWR fixed to 30
7445 10:01:16.818846 [ModeRegInit_LP4] CH0 RK0
7446 10:01:16.821692 [ModeRegInit_LP4] CH0 RK1
7447 10:01:16.825278 [ModeRegInit_LP4] CH1 RK0
7448 10:01:16.825354 [ModeRegInit_LP4] CH1 RK1
7449 10:01:16.828571 match AC timing 5
7450 10:01:16.832099 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7451 10:01:16.834949 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7452 10:01:16.842178 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7453 10:01:16.845552 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7454 10:01:16.852159 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7455 10:01:16.852263 [MiockJmeterHQA]
7456 10:01:16.852354
7457 10:01:16.855039 [DramcMiockJmeter] u1RxGatingPI = 0
7458 10:01:16.855108 0 : 4257, 4029
7459 10:01:16.858842 4 : 4252, 4027
7460 10:01:16.858915 8 : 4255, 4029
7461 10:01:16.861675 12 : 4257, 4031
7462 10:01:16.861742 16 : 4365, 4140
7463 10:01:16.865324 20 : 4253, 4026
7464 10:01:16.865399 24 : 4252, 4027
7465 10:01:16.868854 28 : 4252, 4027
7466 10:01:16.868952 32 : 4253, 4027
7467 10:01:16.869046 36 : 4363, 4138
7468 10:01:16.872200 40 : 4253, 4026
7469 10:01:16.872302 44 : 4363, 4137
7470 10:01:16.875681 48 : 4252, 4027
7471 10:01:16.875756 52 : 4253, 4027
7472 10:01:16.878601 56 : 4250, 4027
7473 10:01:16.878698 60 : 4364, 4137
7474 10:01:16.878787 64 : 4252, 4029
7475 10:01:16.881987 68 : 4360, 4138
7476 10:01:16.882088 72 : 4252, 4030
7477 10:01:16.885235 76 : 4250, 4026
7478 10:01:16.885305 80 : 4249, 4027
7479 10:01:16.888607 84 : 4250, 4027
7480 10:01:16.888742 88 : 4361, 4138
7481 10:01:16.891917 92 : 4250, 4027
7482 10:01:16.891988 96 : 4361, 3443
7483 10:01:16.892051 100 : 4250, 0
7484 10:01:16.895801 104 : 4250, 0
7485 10:01:16.895872 108 : 4250, 0
7486 10:01:16.898706 112 : 4250, 0
7487 10:01:16.898775 116 : 4250, 0
7488 10:01:16.898835 120 : 4252, 0
7489 10:01:16.902261 124 : 4250, 0
7490 10:01:16.902341 128 : 4249, 0
7491 10:01:16.902418 132 : 4252, 0
7492 10:01:16.905320 136 : 4361, 0
7493 10:01:16.905388 140 : 4363, 0
7494 10:01:16.908856 144 : 4363, 0
7495 10:01:16.908922 148 : 4250, 0
7496 10:01:16.908978 152 : 4250, 0
7497 10:01:16.912489 156 : 4250, 0
7498 10:01:16.912575 160 : 4250, 0
7499 10:01:16.915593 164 : 4250, 0
7500 10:01:16.915663 168 : 4250, 0
7501 10:01:16.915722 172 : 4252, 0
7502 10:01:16.918704 176 : 4250, 0
7503 10:01:16.918769 180 : 4250, 0
7504 10:01:16.918849 184 : 4252, 0
7505 10:01:16.922023 188 : 4363, 0
7506 10:01:16.922123 192 : 4360, 0
7507 10:01:16.925357 196 : 4363, 0
7508 10:01:16.925452 200 : 4250, 0
7509 10:01:16.925540 204 : 4250, 0
7510 10:01:16.928854 208 : 4250, 0
7511 10:01:16.928928 212 : 4250, 178
7512 10:01:16.932543 216 : 4250, 3799
7513 10:01:16.932641 220 : 4252, 4029
7514 10:01:16.935848 224 : 4250, 4026
7515 10:01:16.935936 228 : 4250, 4027
7516 10:01:16.936001 232 : 4250, 4027
7517 10:01:16.938788 236 : 4361, 4138
7518 10:01:16.938870 240 : 4360, 4137
7519 10:01:16.942058 244 : 4248, 4024
7520 10:01:16.942141 248 : 4361, 4137
7521 10:01:16.945584 252 : 4361, 4138
7522 10:01:16.945670 256 : 4249, 4027
7523 10:01:16.948662 260 : 4249, 4027
7524 10:01:16.948792 264 : 4253, 4029
7525 10:01:16.952230 268 : 4250, 4027
7526 10:01:16.952369 272 : 4250, 4027
7527 10:01:16.955782 276 : 4250, 4026
7528 10:01:16.955865 280 : 4250, 4026
7529 10:01:16.959043 284 : 4250, 4027
7530 10:01:16.959125 288 : 4361, 4138
7531 10:01:16.962519 292 : 4361, 4137
7532 10:01:16.962615 296 : 4248, 4024
7533 10:01:16.962709 300 : 4361, 4137
7534 10:01:16.965472 304 : 4361, 4138
7535 10:01:16.965557 308 : 4249, 4027
7536 10:01:16.968960 312 : 4250, 4026
7537 10:01:16.969042 316 : 4250, 4027
7538 10:01:16.972303 320 : 4250, 4027
7539 10:01:16.972384 324 : 4249, 4027
7540 10:01:16.975723 328 : 4250, 4026
7541 10:01:16.975811 332 : 4250, 3168
7542 10:01:16.979042 336 : 4250, 67
7543 10:01:16.979123
7544 10:01:16.979186 MIOCK jitter meter ch=0
7545 10:01:16.979246
7546 10:01:16.982552 1T = (336-100) = 236 dly cells
7547 10:01:16.989422 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7548 10:01:16.989567 ==
7549 10:01:16.992546 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 10:01:16.995847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 10:01:16.995941 ==
7552 10:01:17.002336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7553 10:01:17.006107 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7554 10:01:17.008956 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7555 10:01:17.015590 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7556 10:01:17.025032 [CA 0] Center 44 (14~75) winsize 62
7557 10:01:17.028359 [CA 1] Center 44 (13~75) winsize 63
7558 10:01:17.031857 [CA 2] Center 40 (11~69) winsize 59
7559 10:01:17.034900 [CA 3] Center 39 (10~69) winsize 60
7560 10:01:17.038438 [CA 4] Center 37 (8~67) winsize 60
7561 10:01:17.041977 [CA 5] Center 37 (7~67) winsize 61
7562 10:01:17.042060
7563 10:01:17.045284 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7564 10:01:17.045366
7565 10:01:17.048593 [CATrainingPosCal] consider 1 rank data
7566 10:01:17.051867 u2DelayCellTimex100 = 275/100 ps
7567 10:01:17.055038 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7568 10:01:17.061750 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7569 10:01:17.065256 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7570 10:01:17.069035 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7571 10:01:17.071814 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7572 10:01:17.075526 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7573 10:01:17.075609
7574 10:01:17.078399 CA PerBit enable=1, Macro0, CA PI delay=37
7575 10:01:17.078482
7576 10:01:17.081798 [CBTSetCACLKResult] CA Dly = 37
7577 10:01:17.085136 CS Dly: 11 (0~42)
7578 10:01:17.088589 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7579 10:01:17.092060 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7580 10:01:17.092144 ==
7581 10:01:17.095421 Dram Type= 6, Freq= 0, CH_0, rank 1
7582 10:01:17.098527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 10:01:17.098611 ==
7584 10:01:17.105503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7585 10:01:17.108930 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7586 10:01:17.115497 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7587 10:01:17.118248 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7588 10:01:17.128975 [CA 0] Center 43 (13~74) winsize 62
7589 10:01:17.132399 [CA 1] Center 43 (13~74) winsize 62
7590 10:01:17.135768 [CA 2] Center 39 (10~69) winsize 60
7591 10:01:17.138723 [CA 3] Center 38 (9~68) winsize 60
7592 10:01:17.142273 [CA 4] Center 37 (7~67) winsize 61
7593 10:01:17.145686 [CA 5] Center 37 (7~67) winsize 61
7594 10:01:17.145767
7595 10:01:17.148813 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7596 10:01:17.148894
7597 10:01:17.152212 [CATrainingPosCal] consider 2 rank data
7598 10:01:17.155241 u2DelayCellTimex100 = 275/100 ps
7599 10:01:17.158574 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7600 10:01:17.165619 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7601 10:01:17.168707 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7602 10:01:17.172444 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7603 10:01:17.175613 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7604 10:01:17.179465 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7605 10:01:17.179546
7606 10:01:17.182591 CA PerBit enable=1, Macro0, CA PI delay=37
7607 10:01:17.182673
7608 10:01:17.185603 [CBTSetCACLKResult] CA Dly = 37
7609 10:01:17.188865 CS Dly: 12 (0~44)
7610 10:01:17.192563 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7611 10:01:17.195499 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7612 10:01:17.195580
7613 10:01:17.198814 ----->DramcWriteLeveling(PI) begin...
7614 10:01:17.198896 ==
7615 10:01:17.202211 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 10:01:17.205742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 10:01:17.208827 ==
7618 10:01:17.212186 Write leveling (Byte 0): 32 => 32
7619 10:01:17.212291 Write leveling (Byte 1): 27 => 27
7620 10:01:17.215842 DramcWriteLeveling(PI) end<-----
7621 10:01:17.215925
7622 10:01:17.215990 ==
7623 10:01:17.218728 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 10:01:17.225761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 10:01:17.225843 ==
7626 10:01:17.229266 [Gating] SW mode calibration
7627 10:01:17.235845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7628 10:01:17.239281 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7629 10:01:17.245739 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 10:01:17.248772 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 10:01:17.252205 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 10:01:17.256014 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 10:01:17.262215 1 4 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7634 10:01:17.265326 1 4 20 | B1->B0 | 2424 3434 | 1 0 | (0 0) (0 0)
7635 10:01:17.268801 1 4 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7636 10:01:17.275738 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 10:01:17.278670 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 10:01:17.282615 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 10:01:17.288896 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 10:01:17.292219 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7641 10:01:17.295681 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7642 10:01:17.302039 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
7643 10:01:17.305468 1 5 24 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7644 10:01:17.308594 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 10:01:17.315192 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 10:01:17.318842 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 10:01:17.321742 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 10:01:17.328529 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 10:01:17.332069 1 6 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7650 10:01:17.335419 1 6 20 | B1->B0 | 2929 4545 | 1 0 | (0 0) (0 0)
7651 10:01:17.341976 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7652 10:01:17.345457 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 10:01:17.348893 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 10:01:17.355238 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 10:01:17.358739 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 10:01:17.361922 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 10:01:17.368736 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7658 10:01:17.371646 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7659 10:01:17.375113 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7660 10:01:17.378823 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 10:01:17.385594 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 10:01:17.388637 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 10:01:17.392236 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 10:01:17.399022 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 10:01:17.402087 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 10:01:17.405696 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 10:01:17.412096 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 10:01:17.415676 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 10:01:17.418542 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 10:01:17.425629 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 10:01:17.428912 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 10:01:17.432486 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 10:01:17.438991 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7674 10:01:17.442454 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7675 10:01:17.445983 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7676 10:01:17.448883 Total UI for P1: 0, mck2ui 16
7677 10:01:17.452788 best dqsien dly found for B0: ( 1, 9, 18)
7678 10:01:17.455775 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 10:01:17.459437 Total UI for P1: 0, mck2ui 16
7680 10:01:17.462353 best dqsien dly found for B1: ( 1, 9, 24)
7681 10:01:17.465722 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7682 10:01:17.469459 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7683 10:01:17.469541
7684 10:01:17.476138 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7685 10:01:17.479344 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7686 10:01:17.482612 [Gating] SW calibration Done
7687 10:01:17.482725 ==
7688 10:01:17.485919 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 10:01:17.489116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 10:01:17.489200 ==
7691 10:01:17.489266 RX Vref Scan: 0
7692 10:01:17.489328
7693 10:01:17.492653 RX Vref 0 -> 0, step: 1
7694 10:01:17.492746
7695 10:01:17.495934 RX Delay 0 -> 252, step: 8
7696 10:01:17.499443 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7697 10:01:17.502592 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7698 10:01:17.505983 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7699 10:01:17.512402 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7700 10:01:17.516407 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7701 10:01:17.519160 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7702 10:01:17.522346 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7703 10:01:17.526517 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7704 10:01:17.532565 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7705 10:01:17.536269 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7706 10:01:17.539173 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7707 10:01:17.542932 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7708 10:01:17.546363 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7709 10:01:17.552528 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
7710 10:01:17.556324 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7711 10:01:17.559182 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7712 10:01:17.559266 ==
7713 10:01:17.562609 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 10:01:17.565935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 10:01:17.566018 ==
7716 10:01:17.569029 DQS Delay:
7717 10:01:17.569112 DQS0 = 0, DQS1 = 0
7718 10:01:17.572470 DQM Delay:
7719 10:01:17.572553 DQM0 = 132, DQM1 = 123
7720 10:01:17.575989 DQ Delay:
7721 10:01:17.579096 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7722 10:01:17.582582 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7723 10:01:17.585899 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7724 10:01:17.589013 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7725 10:01:17.589097
7726 10:01:17.589162
7727 10:01:17.589223 ==
7728 10:01:17.592389 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 10:01:17.595969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 10:01:17.596053 ==
7731 10:01:17.596118
7732 10:01:17.596179
7733 10:01:17.599556 TX Vref Scan disable
7734 10:01:17.602435 == TX Byte 0 ==
7735 10:01:17.605923 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7736 10:01:17.609457 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7737 10:01:17.612802 == TX Byte 1 ==
7738 10:01:17.615743 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7739 10:01:17.618987 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7740 10:01:17.619070 ==
7741 10:01:17.622612 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 10:01:17.626353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 10:01:17.629208 ==
7744 10:01:17.641014
7745 10:01:17.644450 TX Vref early break, caculate TX vref
7746 10:01:17.647497 TX Vref=16, minBit 0, minWin=21, winSum=354
7747 10:01:17.651030 TX Vref=18, minBit 1, minWin=21, winSum=366
7748 10:01:17.654225 TX Vref=20, minBit 4, minWin=21, winSum=373
7749 10:01:17.657575 TX Vref=22, minBit 4, minWin=22, winSum=386
7750 10:01:17.660659 TX Vref=24, minBit 0, minWin=24, winSum=393
7751 10:01:17.667876 TX Vref=26, minBit 1, minWin=24, winSum=407
7752 10:01:17.670700 TX Vref=28, minBit 4, minWin=24, winSum=410
7753 10:01:17.674366 TX Vref=30, minBit 0, minWin=25, winSum=418
7754 10:01:17.677606 TX Vref=32, minBit 4, minWin=23, winSum=403
7755 10:01:17.680898 TX Vref=34, minBit 0, minWin=23, winSum=395
7756 10:01:17.687571 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 30
7757 10:01:17.687653
7758 10:01:17.691084 Final TX Range 0 Vref 30
7759 10:01:17.691166
7760 10:01:17.691230 ==
7761 10:01:17.694467 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 10:01:17.697502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 10:01:17.697601 ==
7764 10:01:17.697713
7765 10:01:17.697833
7766 10:01:17.700937 TX Vref Scan disable
7767 10:01:17.707496 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7768 10:01:17.707604 == TX Byte 0 ==
7769 10:01:17.710870 u2DelayCellOfst[0]=14 cells (4 PI)
7770 10:01:17.713946 u2DelayCellOfst[1]=17 cells (5 PI)
7771 10:01:17.717479 u2DelayCellOfst[2]=10 cells (3 PI)
7772 10:01:17.720777 u2DelayCellOfst[3]=14 cells (4 PI)
7773 10:01:17.724173 u2DelayCellOfst[4]=7 cells (2 PI)
7774 10:01:17.727278 u2DelayCellOfst[5]=0 cells (0 PI)
7775 10:01:17.727360 u2DelayCellOfst[6]=21 cells (6 PI)
7776 10:01:17.730705 u2DelayCellOfst[7]=17 cells (5 PI)
7777 10:01:17.737526 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7778 10:01:17.740627 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7779 10:01:17.740732 == TX Byte 1 ==
7780 10:01:17.744207 u2DelayCellOfst[8]=0 cells (0 PI)
7781 10:01:17.747328 u2DelayCellOfst[9]=0 cells (0 PI)
7782 10:01:17.750780 u2DelayCellOfst[10]=7 cells (2 PI)
7783 10:01:17.754355 u2DelayCellOfst[11]=0 cells (0 PI)
7784 10:01:17.757667 u2DelayCellOfst[12]=10 cells (3 PI)
7785 10:01:17.760659 u2DelayCellOfst[13]=14 cells (4 PI)
7786 10:01:17.764797 u2DelayCellOfst[14]=17 cells (5 PI)
7787 10:01:17.767611 u2DelayCellOfst[15]=10 cells (3 PI)
7788 10:01:17.770955 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7789 10:01:17.774105 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7790 10:01:17.777645 DramC Write-DBI on
7791 10:01:17.777755 ==
7792 10:01:17.780785 Dram Type= 6, Freq= 0, CH_0, rank 0
7793 10:01:17.784160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7794 10:01:17.784270 ==
7795 10:01:17.784364
7796 10:01:17.784454
7797 10:01:17.787793 TX Vref Scan disable
7798 10:01:17.790899 == TX Byte 0 ==
7799 10:01:17.794170 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7800 10:01:17.797818 == TX Byte 1 ==
7801 10:01:17.801191 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7802 10:01:17.801295 DramC Write-DBI off
7803 10:01:17.801392
7804 10:01:17.804308 [DATLAT]
7805 10:01:17.804384 Freq=1600, CH0 RK0
7806 10:01:17.804447
7807 10:01:17.807686 DATLAT Default: 0xf
7808 10:01:17.807772 0, 0xFFFF, sum = 0
7809 10:01:17.811117 1, 0xFFFF, sum = 0
7810 10:01:17.811222 2, 0xFFFF, sum = 0
7811 10:01:17.814626 3, 0xFFFF, sum = 0
7812 10:01:17.814718 4, 0xFFFF, sum = 0
7813 10:01:17.818186 5, 0xFFFF, sum = 0
7814 10:01:17.818270 6, 0xFFFF, sum = 0
7815 10:01:17.821198 7, 0xFFFF, sum = 0
7816 10:01:17.821282 8, 0xFFFF, sum = 0
7817 10:01:17.824363 9, 0xFFFF, sum = 0
7818 10:01:17.824448 10, 0xFFFF, sum = 0
7819 10:01:17.827925 11, 0xFFFF, sum = 0
7820 10:01:17.828009 12, 0xFFFF, sum = 0
7821 10:01:17.831179 13, 0xFFFF, sum = 0
7822 10:01:17.831264 14, 0x0, sum = 1
7823 10:01:17.834560 15, 0x0, sum = 2
7824 10:01:17.834645 16, 0x0, sum = 3
7825 10:01:17.838024 17, 0x0, sum = 4
7826 10:01:17.838107 best_step = 15
7827 10:01:17.838173
7828 10:01:17.838234 ==
7829 10:01:17.841550 Dram Type= 6, Freq= 0, CH_0, rank 0
7830 10:01:17.848155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7831 10:01:17.848239 ==
7832 10:01:17.848306 RX Vref Scan: 1
7833 10:01:17.848367
7834 10:01:17.851531 Set Vref Range= 24 -> 127
7835 10:01:17.851615
7836 10:01:17.854715 RX Vref 24 -> 127, step: 1
7837 10:01:17.854805
7838 10:01:17.854904 RX Delay 11 -> 252, step: 4
7839 10:01:17.857964
7840 10:01:17.858075 Set Vref, RX VrefLevel [Byte0]: 24
7841 10:01:17.861231 [Byte1]: 24
7842 10:01:17.865663
7843 10:01:17.865746 Set Vref, RX VrefLevel [Byte0]: 25
7844 10:01:17.868884 [Byte1]: 25
7845 10:01:17.873157
7846 10:01:17.873240 Set Vref, RX VrefLevel [Byte0]: 26
7847 10:01:17.876253 [Byte1]: 26
7848 10:01:17.880948
7849 10:01:17.881031 Set Vref, RX VrefLevel [Byte0]: 27
7850 10:01:17.884191 [Byte1]: 27
7851 10:01:17.888422
7852 10:01:17.888506 Set Vref, RX VrefLevel [Byte0]: 28
7853 10:01:17.891669 [Byte1]: 28
7854 10:01:17.895837
7855 10:01:17.895919 Set Vref, RX VrefLevel [Byte0]: 29
7856 10:01:17.899312 [Byte1]: 29
7857 10:01:17.903551
7858 10:01:17.903633 Set Vref, RX VrefLevel [Byte0]: 30
7859 10:01:17.907115 [Byte1]: 30
7860 10:01:17.910939
7861 10:01:17.911022 Set Vref, RX VrefLevel [Byte0]: 31
7862 10:01:17.914491 [Byte1]: 31
7863 10:01:17.918812
7864 10:01:17.918894 Set Vref, RX VrefLevel [Byte0]: 32
7865 10:01:17.922284 [Byte1]: 32
7866 10:01:17.926225
7867 10:01:17.926308 Set Vref, RX VrefLevel [Byte0]: 33
7868 10:01:17.929624 [Byte1]: 33
7869 10:01:17.933787
7870 10:01:17.933869 Set Vref, RX VrefLevel [Byte0]: 34
7871 10:01:17.937292 [Byte1]: 34
7872 10:01:17.941802
7873 10:01:17.941885 Set Vref, RX VrefLevel [Byte0]: 35
7874 10:01:17.944627 [Byte1]: 35
7875 10:01:17.949103
7876 10:01:17.949185 Set Vref, RX VrefLevel [Byte0]: 36
7877 10:01:17.952652 [Byte1]: 36
7878 10:01:17.956849
7879 10:01:17.956932 Set Vref, RX VrefLevel [Byte0]: 37
7880 10:01:17.960266 [Byte1]: 37
7881 10:01:17.964384
7882 10:01:17.964466 Set Vref, RX VrefLevel [Byte0]: 38
7883 10:01:17.967593 [Byte1]: 38
7884 10:01:17.972238
7885 10:01:17.972321 Set Vref, RX VrefLevel [Byte0]: 39
7886 10:01:17.975503 [Byte1]: 39
7887 10:01:17.979487
7888 10:01:17.979570 Set Vref, RX VrefLevel [Byte0]: 40
7889 10:01:17.982967 [Byte1]: 40
7890 10:01:17.987047
7891 10:01:17.987130 Set Vref, RX VrefLevel [Byte0]: 41
7892 10:01:17.990690 [Byte1]: 41
7893 10:01:17.994663
7894 10:01:17.994746 Set Vref, RX VrefLevel [Byte0]: 42
7895 10:01:17.998622 [Byte1]: 42
7896 10:01:18.002646
7897 10:01:18.002732 Set Vref, RX VrefLevel [Byte0]: 43
7898 10:01:18.005789 [Byte1]: 43
7899 10:01:18.009908
7900 10:01:18.009991 Set Vref, RX VrefLevel [Byte0]: 44
7901 10:01:18.013262 [Byte1]: 44
7902 10:01:18.017708
7903 10:01:18.017791 Set Vref, RX VrefLevel [Byte0]: 45
7904 10:01:18.020941 [Byte1]: 45
7905 10:01:18.025794
7906 10:01:18.025876 Set Vref, RX VrefLevel [Byte0]: 46
7907 10:01:18.028743 [Byte1]: 46
7908 10:01:18.032860
7909 10:01:18.032943 Set Vref, RX VrefLevel [Byte0]: 47
7910 10:01:18.036281 [Byte1]: 47
7911 10:01:18.040528
7912 10:01:18.040635 Set Vref, RX VrefLevel [Byte0]: 48
7913 10:01:18.043953 [Byte1]: 48
7914 10:01:18.048193
7915 10:01:18.048293 Set Vref, RX VrefLevel [Byte0]: 49
7916 10:01:18.051494 [Byte1]: 49
7917 10:01:18.055910
7918 10:01:18.056014 Set Vref, RX VrefLevel [Byte0]: 50
7919 10:01:18.059038 [Byte1]: 50
7920 10:01:18.063216
7921 10:01:18.066730 Set Vref, RX VrefLevel [Byte0]: 51
7922 10:01:18.066836 [Byte1]: 51
7923 10:01:18.070928
7924 10:01:18.071037 Set Vref, RX VrefLevel [Byte0]: 52
7925 10:01:18.074074 [Byte1]: 52
7926 10:01:18.078695
7927 10:01:18.078794 Set Vref, RX VrefLevel [Byte0]: 53
7928 10:01:18.082108 [Byte1]: 53
7929 10:01:18.086299
7930 10:01:18.086375 Set Vref, RX VrefLevel [Byte0]: 54
7931 10:01:18.089551 [Byte1]: 54
7932 10:01:18.093675
7933 10:01:18.093750 Set Vref, RX VrefLevel [Byte0]: 55
7934 10:01:18.096946 [Byte1]: 55
7935 10:01:18.101138
7936 10:01:18.101254 Set Vref, RX VrefLevel [Byte0]: 56
7937 10:01:18.104849 [Byte1]: 56
7938 10:01:18.109394
7939 10:01:18.109494 Set Vref, RX VrefLevel [Byte0]: 57
7940 10:01:18.112292 [Byte1]: 57
7941 10:01:18.116574
7942 10:01:18.116683 Set Vref, RX VrefLevel [Byte0]: 58
7943 10:01:18.119966 [Byte1]: 58
7944 10:01:18.124613
7945 10:01:18.124703 Set Vref, RX VrefLevel [Byte0]: 59
7946 10:01:18.127919 [Byte1]: 59
7947 10:01:18.132185
7948 10:01:18.132266 Set Vref, RX VrefLevel [Byte0]: 60
7949 10:01:18.135214 [Byte1]: 60
7950 10:01:18.139388
7951 10:01:18.139468 Set Vref, RX VrefLevel [Byte0]: 61
7952 10:01:18.142750 [Byte1]: 61
7953 10:01:18.146961
7954 10:01:18.147061 Set Vref, RX VrefLevel [Byte0]: 62
7955 10:01:18.150143 [Byte1]: 62
7956 10:01:18.154819
7957 10:01:18.154901 Set Vref, RX VrefLevel [Byte0]: 63
7958 10:01:18.158048 [Byte1]: 63
7959 10:01:18.162364
7960 10:01:18.162449 Set Vref, RX VrefLevel [Byte0]: 64
7961 10:01:18.165705 [Byte1]: 64
7962 10:01:18.170043
7963 10:01:18.170125 Set Vref, RX VrefLevel [Byte0]: 65
7964 10:01:18.173453 [Byte1]: 65
7965 10:01:18.177755
7966 10:01:18.177837 Set Vref, RX VrefLevel [Byte0]: 66
7967 10:01:18.181081 [Byte1]: 66
7968 10:01:18.185159
7969 10:01:18.185240 Set Vref, RX VrefLevel [Byte0]: 67
7970 10:01:18.188551 [Byte1]: 67
7971 10:01:18.193027
7972 10:01:18.193108 Set Vref, RX VrefLevel [Byte0]: 68
7973 10:01:18.199341 [Byte1]: 68
7974 10:01:18.199480
7975 10:01:18.202977 Set Vref, RX VrefLevel [Byte0]: 69
7976 10:01:18.205902 [Byte1]: 69
7977 10:01:18.205984
7978 10:01:18.209322 Set Vref, RX VrefLevel [Byte0]: 70
7979 10:01:18.212890 [Byte1]: 70
7980 10:01:18.212988
7981 10:01:18.216179 Set Vref, RX VrefLevel [Byte0]: 71
7982 10:01:18.219407 [Byte1]: 71
7983 10:01:18.223734
7984 10:01:18.223841 Set Vref, RX VrefLevel [Byte0]: 72
7985 10:01:18.226307 [Byte1]: 72
7986 10:01:18.231384
7987 10:01:18.231464 Set Vref, RX VrefLevel [Byte0]: 73
7988 10:01:18.234438 [Byte1]: 73
7989 10:01:18.238747
7990 10:01:18.238828 Set Vref, RX VrefLevel [Byte0]: 74
7991 10:01:18.241587 [Byte1]: 74
7992 10:01:18.246273
7993 10:01:18.246390 Set Vref, RX VrefLevel [Byte0]: 75
7994 10:01:18.249170 [Byte1]: 75
7995 10:01:18.253686
7996 10:01:18.253795 Set Vref, RX VrefLevel [Byte0]: 76
7997 10:01:18.256885 [Byte1]: 76
7998 10:01:18.261350
7999 10:01:18.261446 Set Vref, RX VrefLevel [Byte0]: 77
8000 10:01:18.264747 [Byte1]: 77
8001 10:01:18.268963
8002 10:01:18.269086 Final RX Vref Byte 0 = 62 to rank0
8003 10:01:18.272264 Final RX Vref Byte 1 = 63 to rank0
8004 10:01:18.275592 Final RX Vref Byte 0 = 62 to rank1
8005 10:01:18.279170 Final RX Vref Byte 1 = 63 to rank1==
8006 10:01:18.282110 Dram Type= 6, Freq= 0, CH_0, rank 0
8007 10:01:18.289310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 10:01:18.289392 ==
8009 10:01:18.289457 DQS Delay:
8010 10:01:18.289517 DQS0 = 0, DQS1 = 0
8011 10:01:18.292216 DQM Delay:
8012 10:01:18.292297 DQM0 = 130, DQM1 = 121
8013 10:01:18.295174 DQ Delay:
8014 10:01:18.298950 DQ0 =132, DQ1 =132, DQ2 =126, DQ3 =126
8015 10:01:18.302217 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =140
8016 10:01:18.305774 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
8017 10:01:18.308509 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8018 10:01:18.308618
8019 10:01:18.308711
8020 10:01:18.308773
8021 10:01:18.312083 [DramC_TX_OE_Calibration] TA2
8022 10:01:18.315500 Original DQ_B0 (3 6) =30, OEN = 27
8023 10:01:18.318895 Original DQ_B1 (3 6) =30, OEN = 27
8024 10:01:18.321858 24, 0x0, End_B0=24 End_B1=24
8025 10:01:18.321941 25, 0x0, End_B0=25 End_B1=25
8026 10:01:18.325631 26, 0x0, End_B0=26 End_B1=26
8027 10:01:18.328982 27, 0x0, End_B0=27 End_B1=27
8028 10:01:18.332326 28, 0x0, End_B0=28 End_B1=28
8029 10:01:18.332408 29, 0x0, End_B0=29 End_B1=29
8030 10:01:18.335215 30, 0x0, End_B0=30 End_B1=30
8031 10:01:18.338811 31, 0x4141, End_B0=30 End_B1=30
8032 10:01:18.342147 Byte0 end_step=30 best_step=27
8033 10:01:18.345527 Byte1 end_step=30 best_step=27
8034 10:01:18.348625 Byte0 TX OE(2T, 0.5T) = (3, 3)
8035 10:01:18.348735 Byte1 TX OE(2T, 0.5T) = (3, 3)
8036 10:01:18.352383
8037 10:01:18.352463
8038 10:01:18.358744 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8039 10:01:18.362367 CH0 RK0: MR19=303, MR18=1509
8040 10:01:18.368796 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8041 10:01:18.368879
8042 10:01:18.372403 ----->DramcWriteLeveling(PI) begin...
8043 10:01:18.372482 ==
8044 10:01:18.375820 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 10:01:18.378765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 10:01:18.378839 ==
8047 10:01:18.382222 Write leveling (Byte 0): 34 => 34
8048 10:01:18.385636 Write leveling (Byte 1): 27 => 27
8049 10:01:18.388769 DramcWriteLeveling(PI) end<-----
8050 10:01:18.388842
8051 10:01:18.388902 ==
8052 10:01:18.391931 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 10:01:18.395383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 10:01:18.395476 ==
8055 10:01:18.399040 [Gating] SW mode calibration
8056 10:01:18.405358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8057 10:01:18.412333 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8058 10:01:18.415540 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 10:01:18.419122 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 10:01:18.425557 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8061 10:01:18.429259 1 4 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8062 10:01:18.432578 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8063 10:01:18.439292 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
8064 10:01:18.442600 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 10:01:18.445676 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 10:01:18.449194 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 10:01:18.455915 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 10:01:18.459382 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8069 10:01:18.462809 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8070 10:01:18.469126 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8071 10:01:18.472488 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8072 10:01:18.476124 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8073 10:01:18.482512 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 10:01:18.485954 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 10:01:18.488988 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 10:01:18.495674 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8077 10:01:18.499032 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8078 10:01:18.502442 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8079 10:01:18.509058 1 6 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8080 10:01:18.512447 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 10:01:18.515722 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 10:01:18.522381 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 10:01:18.526106 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 10:01:18.529429 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 10:01:18.532443 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 10:01:18.539402 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 10:01:18.542359 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8088 10:01:18.545946 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8089 10:01:18.552882 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 10:01:18.555763 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 10:01:18.559034 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 10:01:18.565901 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 10:01:18.569463 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 10:01:18.572814 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 10:01:18.579148 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 10:01:18.582690 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 10:01:18.586190 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 10:01:18.593176 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 10:01:18.596052 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 10:01:18.599367 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 10:01:18.602890 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8102 10:01:18.605997 Total UI for P1: 0, mck2ui 16
8103 10:01:18.609603 best dqsien dly found for B0: ( 1, 9, 8)
8104 10:01:18.616398 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8105 10:01:18.619633 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 10:01:18.622582 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8107 10:01:18.629101 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 10:01:18.632424 Total UI for P1: 0, mck2ui 16
8109 10:01:18.636085 best dqsien dly found for B1: ( 1, 9, 22)
8110 10:01:18.639624 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8111 10:01:18.643000 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8112 10:01:18.643082
8113 10:01:18.646157 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8114 10:01:18.649775 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8115 10:01:18.652763 [Gating] SW calibration Done
8116 10:01:18.652872 ==
8117 10:01:18.656315 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 10:01:18.659360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 10:01:18.659469 ==
8120 10:01:18.662400 RX Vref Scan: 0
8121 10:01:18.662496
8122 10:01:18.662585 RX Vref 0 -> 0, step: 1
8123 10:01:18.665837
8124 10:01:18.665916 RX Delay 0 -> 252, step: 8
8125 10:01:18.669291 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8126 10:01:18.675707 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8127 10:01:18.679147 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8128 10:01:18.682328 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8129 10:01:18.686241 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8130 10:01:18.689482 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8131 10:01:18.696050 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8132 10:01:18.698865 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8133 10:01:18.702436 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8134 10:01:18.705790 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8135 10:01:18.709275 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8136 10:01:18.715882 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8137 10:01:18.718903 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8138 10:01:18.722769 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8139 10:01:18.725588 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8140 10:01:18.732283 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8141 10:01:18.732356 ==
8142 10:01:18.735505 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 10:01:18.738853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 10:01:18.738935 ==
8145 10:01:18.738997 DQS Delay:
8146 10:01:18.742594 DQS0 = 0, DQS1 = 0
8147 10:01:18.742736 DQM Delay:
8148 10:01:18.745389 DQM0 = 131, DQM1 = 123
8149 10:01:18.745485 DQ Delay:
8150 10:01:18.749471 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8151 10:01:18.752148 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8152 10:01:18.755755 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8153 10:01:18.759351 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8154 10:01:18.759430
8155 10:01:18.759493
8156 10:01:18.759551 ==
8157 10:01:18.762159 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 10:01:18.769141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 10:01:18.769218 ==
8160 10:01:18.769287
8161 10:01:18.769347
8162 10:01:18.769404 TX Vref Scan disable
8163 10:01:18.772755 == TX Byte 0 ==
8164 10:01:18.775864 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8165 10:01:18.779286 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8166 10:01:18.782458 == TX Byte 1 ==
8167 10:01:18.786146 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8168 10:01:18.792656 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8169 10:01:18.792804 ==
8170 10:01:18.796125 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 10:01:18.799107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 10:01:18.799208 ==
8173 10:01:18.813182
8174 10:01:18.816830 TX Vref early break, caculate TX vref
8175 10:01:18.820394 TX Vref=16, minBit 4, minWin=22, winSum=370
8176 10:01:18.823906 TX Vref=18, minBit 5, minWin=22, winSum=382
8177 10:01:18.826701 TX Vref=20, minBit 1, minWin=23, winSum=390
8178 10:01:18.830035 TX Vref=22, minBit 2, minWin=24, winSum=396
8179 10:01:18.833291 TX Vref=24, minBit 0, minWin=24, winSum=404
8180 10:01:18.839932 TX Vref=26, minBit 4, minWin=24, winSum=413
8181 10:01:18.843319 TX Vref=28, minBit 2, minWin=25, winSum=418
8182 10:01:18.846743 TX Vref=30, minBit 0, minWin=25, winSum=416
8183 10:01:18.850360 TX Vref=32, minBit 0, minWin=24, winSum=412
8184 10:01:18.853666 TX Vref=34, minBit 0, minWin=24, winSum=400
8185 10:01:18.856895 TX Vref=36, minBit 4, minWin=23, winSum=394
8186 10:01:18.863902 [TxChooseVref] Worse bit 2, Min win 25, Win sum 418, Final Vref 28
8187 10:01:18.864019
8188 10:01:18.867371 Final TX Range 0 Vref 28
8189 10:01:18.867483
8190 10:01:18.867576 ==
8191 10:01:18.870296 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 10:01:18.873665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 10:01:18.873744 ==
8194 10:01:18.873850
8195 10:01:18.873945
8196 10:01:18.877126 TX Vref Scan disable
8197 10:01:18.883668 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8198 10:01:18.883746 == TX Byte 0 ==
8199 10:01:18.887184 u2DelayCellOfst[0]=10 cells (3 PI)
8200 10:01:18.890740 u2DelayCellOfst[1]=17 cells (5 PI)
8201 10:01:18.893735 u2DelayCellOfst[2]=10 cells (3 PI)
8202 10:01:18.897154 u2DelayCellOfst[3]=10 cells (3 PI)
8203 10:01:18.900469 u2DelayCellOfst[4]=10 cells (3 PI)
8204 10:01:18.904175 u2DelayCellOfst[5]=0 cells (0 PI)
8205 10:01:18.906845 u2DelayCellOfst[6]=17 cells (5 PI)
8206 10:01:18.906922 u2DelayCellOfst[7]=17 cells (5 PI)
8207 10:01:18.914202 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8208 10:01:18.916933 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8209 10:01:18.917021 == TX Byte 1 ==
8210 10:01:18.920579 u2DelayCellOfst[8]=0 cells (0 PI)
8211 10:01:18.924442 u2DelayCellOfst[9]=0 cells (0 PI)
8212 10:01:18.927009 u2DelayCellOfst[10]=7 cells (2 PI)
8213 10:01:18.930625 u2DelayCellOfst[11]=0 cells (0 PI)
8214 10:01:18.933600 u2DelayCellOfst[12]=10 cells (3 PI)
8215 10:01:18.937014 u2DelayCellOfst[13]=10 cells (3 PI)
8216 10:01:18.940500 u2DelayCellOfst[14]=14 cells (4 PI)
8217 10:01:18.943963 u2DelayCellOfst[15]=10 cells (3 PI)
8218 10:01:18.947294 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8219 10:01:18.950503 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8220 10:01:18.953770 DramC Write-DBI on
8221 10:01:18.953865 ==
8222 10:01:18.957160 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 10:01:18.960703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 10:01:18.960788 ==
8225 10:01:18.960855
8226 10:01:18.963954
8227 10:01:18.964059 TX Vref Scan disable
8228 10:01:18.967029 == TX Byte 0 ==
8229 10:01:18.970576 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8230 10:01:18.973979 == TX Byte 1 ==
8231 10:01:18.977501 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8232 10:01:18.977579 DramC Write-DBI off
8233 10:01:18.977644
8234 10:01:18.980892 [DATLAT]
8235 10:01:18.980969 Freq=1600, CH0 RK1
8236 10:01:18.981032
8237 10:01:18.983862 DATLAT Default: 0xf
8238 10:01:18.983933 0, 0xFFFF, sum = 0
8239 10:01:18.987430 1, 0xFFFF, sum = 0
8240 10:01:18.987523 2, 0xFFFF, sum = 0
8241 10:01:18.990364 3, 0xFFFF, sum = 0
8242 10:01:18.990468 4, 0xFFFF, sum = 0
8243 10:01:18.993696 5, 0xFFFF, sum = 0
8244 10:01:18.997184 6, 0xFFFF, sum = 0
8245 10:01:18.997266 7, 0xFFFF, sum = 0
8246 10:01:19.000347 8, 0xFFFF, sum = 0
8247 10:01:19.000445 9, 0xFFFF, sum = 0
8248 10:01:19.004206 10, 0xFFFF, sum = 0
8249 10:01:19.004305 11, 0xFFFF, sum = 0
8250 10:01:19.007168 12, 0xFFFF, sum = 0
8251 10:01:19.007248 13, 0xFFFF, sum = 0
8252 10:01:19.010478 14, 0x0, sum = 1
8253 10:01:19.010562 15, 0x0, sum = 2
8254 10:01:19.013602 16, 0x0, sum = 3
8255 10:01:19.013685 17, 0x0, sum = 4
8256 10:01:19.013749 best_step = 15
8257 10:01:19.017301
8258 10:01:19.017375 ==
8259 10:01:19.020688 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 10:01:19.024125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 10:01:19.024219 ==
8262 10:01:19.024284 RX Vref Scan: 0
8263 10:01:19.024344
8264 10:01:19.027713 RX Vref 0 -> 0, step: 1
8265 10:01:19.027796
8266 10:01:19.030494 RX Delay 11 -> 252, step: 4
8267 10:01:19.034163 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8268 10:01:19.037676 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8269 10:01:19.044023 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8270 10:01:19.047634 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8271 10:01:19.050686 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8272 10:01:19.053972 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8273 10:01:19.057365 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8274 10:01:19.064237 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8275 10:01:19.067827 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8276 10:01:19.071281 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8277 10:01:19.074240 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8278 10:01:19.077702 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8279 10:01:19.084390 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8280 10:01:19.087776 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8281 10:01:19.091692 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8282 10:01:19.094193 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8283 10:01:19.094284 ==
8284 10:01:19.097817 Dram Type= 6, Freq= 0, CH_0, rank 1
8285 10:01:19.100864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 10:01:19.104295 ==
8287 10:01:19.104376 DQS Delay:
8288 10:01:19.104440 DQS0 = 0, DQS1 = 0
8289 10:01:19.107631 DQM Delay:
8290 10:01:19.107712 DQM0 = 127, DQM1 = 122
8291 10:01:19.111173 DQ Delay:
8292 10:01:19.114138 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8293 10:01:19.117725 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8294 10:01:19.121013 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8295 10:01:19.124375 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8296 10:01:19.124457
8297 10:01:19.124521
8298 10:01:19.124580
8299 10:01:19.127731 [DramC_TX_OE_Calibration] TA2
8300 10:01:19.131055 Original DQ_B0 (3 6) =30, OEN = 27
8301 10:01:19.134814 Original DQ_B1 (3 6) =30, OEN = 27
8302 10:01:19.134921 24, 0x0, End_B0=24 End_B1=24
8303 10:01:19.137624 25, 0x0, End_B0=25 End_B1=25
8304 10:01:19.141256 26, 0x0, End_B0=26 End_B1=26
8305 10:01:19.144614 27, 0x0, End_B0=27 End_B1=27
8306 10:01:19.147654 28, 0x0, End_B0=28 End_B1=28
8307 10:01:19.147736 29, 0x0, End_B0=29 End_B1=29
8308 10:01:19.151195 30, 0x0, End_B0=30 End_B1=30
8309 10:01:19.154668 31, 0x4141, End_B0=30 End_B1=30
8310 10:01:19.158014 Byte0 end_step=30 best_step=27
8311 10:01:19.161587 Byte1 end_step=30 best_step=27
8312 10:01:19.161669 Byte0 TX OE(2T, 0.5T) = (3, 3)
8313 10:01:19.164842 Byte1 TX OE(2T, 0.5T) = (3, 3)
8314 10:01:19.164924
8315 10:01:19.164988
8316 10:01:19.174529 [DQSOSCAuto] RK1, (LSB)MR18= 0x170a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8317 10:01:19.177946 CH0 RK1: MR19=303, MR18=170A
8318 10:01:19.181588 CH0_RK1: MR19=0x303, MR18=0x170A, DQSOSC=398, MR23=63, INC=23, DEC=15
8319 10:01:19.184488 [RxdqsGatingPostProcess] freq 1600
8320 10:01:19.191453 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8321 10:01:19.194794 best DQS0 dly(2T, 0.5T) = (1, 1)
8322 10:01:19.198470 best DQS1 dly(2T, 0.5T) = (1, 1)
8323 10:01:19.201483 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8324 10:01:19.204650 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8325 10:01:19.208525 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 10:01:19.208606 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 10:01:19.211711 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 10:01:19.214748 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 10:01:19.217806 Pre-setting of DQS Precalculation
8330 10:01:19.224994 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8331 10:01:19.225075 ==
8332 10:01:19.227961 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 10:01:19.231255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 10:01:19.231337 ==
8335 10:01:19.238103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8336 10:01:19.241277 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8337 10:01:19.245004 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8338 10:01:19.251614 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8339 10:01:19.260183 [CA 0] Center 43 (14~72) winsize 59
8340 10:01:19.263606 [CA 1] Center 43 (14~72) winsize 59
8341 10:01:19.266735 [CA 2] Center 38 (10~67) winsize 58
8342 10:01:19.269923 [CA 3] Center 37 (8~66) winsize 59
8343 10:01:19.273767 [CA 4] Center 38 (9~68) winsize 60
8344 10:01:19.276960 [CA 5] Center 37 (8~66) winsize 59
8345 10:01:19.277043
8346 10:01:19.280080 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8347 10:01:19.280160
8348 10:01:19.283662 [CATrainingPosCal] consider 1 rank data
8349 10:01:19.286722 u2DelayCellTimex100 = 275/100 ps
8350 10:01:19.290181 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8351 10:01:19.296488 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8352 10:01:19.300104 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8353 10:01:19.303561 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8354 10:01:19.306624 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8355 10:01:19.310237 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8356 10:01:19.310318
8357 10:01:19.313853 CA PerBit enable=1, Macro0, CA PI delay=37
8358 10:01:19.313944
8359 10:01:19.317043 [CBTSetCACLKResult] CA Dly = 37
8360 10:01:19.317124 CS Dly: 8 (0~39)
8361 10:01:19.323334 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8362 10:01:19.326883 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8363 10:01:19.326964 ==
8364 10:01:19.330246 Dram Type= 6, Freq= 0, CH_1, rank 1
8365 10:01:19.333738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 10:01:19.333819 ==
8367 10:01:19.340358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8368 10:01:19.343647 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8369 10:01:19.350636 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8370 10:01:19.353502 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8371 10:01:19.363212 [CA 0] Center 42 (13~72) winsize 60
8372 10:01:19.366658 [CA 1] Center 43 (14~72) winsize 59
8373 10:01:19.370031 [CA 2] Center 37 (9~66) winsize 58
8374 10:01:19.373486 [CA 3] Center 36 (7~66) winsize 60
8375 10:01:19.376596 [CA 4] Center 38 (9~67) winsize 59
8376 10:01:19.380485 [CA 5] Center 36 (7~66) winsize 60
8377 10:01:19.380582
8378 10:01:19.383627 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8379 10:01:19.383708
8380 10:01:19.386848 [CATrainingPosCal] consider 2 rank data
8381 10:01:19.389876 u2DelayCellTimex100 = 275/100 ps
8382 10:01:19.393546 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8383 10:01:19.400243 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8384 10:01:19.403687 CA2 delay=38 (10~66),Diff = 1 PI (3 cell)
8385 10:01:19.407064 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8386 10:01:19.409902 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8387 10:01:19.413649 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8388 10:01:19.413730
8389 10:01:19.416614 CA PerBit enable=1, Macro0, CA PI delay=37
8390 10:01:19.416759
8391 10:01:19.420021 [CBTSetCACLKResult] CA Dly = 37
8392 10:01:19.420101 CS Dly: 10 (0~43)
8393 10:01:19.427056 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8394 10:01:19.430070 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8395 10:01:19.430150
8396 10:01:19.433341 ----->DramcWriteLeveling(PI) begin...
8397 10:01:19.433422 ==
8398 10:01:19.437124 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 10:01:19.440416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 10:01:19.440497 ==
8401 10:01:19.443772 Write leveling (Byte 0): 25 => 25
8402 10:01:19.447024 Write leveling (Byte 1): 28 => 28
8403 10:01:19.450157 DramcWriteLeveling(PI) end<-----
8404 10:01:19.450237
8405 10:01:19.450301 ==
8406 10:01:19.453552 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 10:01:19.457328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 10:01:19.460213 ==
8409 10:01:19.460302 [Gating] SW mode calibration
8410 10:01:19.467012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8411 10:01:19.473819 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8412 10:01:19.476925 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 10:01:19.483987 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 10:01:19.486892 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 10:01:19.490446 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 10:01:19.496993 1 4 16 | B1->B0 | 2e2e 2727 | 1 0 | (1 1) (1 1)
8417 10:01:19.500180 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 10:01:19.503772 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 10:01:19.510383 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 10:01:19.514006 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 10:01:19.517128 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 10:01:19.520649 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 10:01:19.527078 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8424 10:01:19.530745 1 5 16 | B1->B0 | 2828 3131 | 0 1 | (0 0) (1 0)
8425 10:01:19.534346 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8426 10:01:19.540607 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 10:01:19.544011 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 10:01:19.547111 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 10:01:19.553830 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 10:01:19.557457 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 10:01:19.560652 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 10:01:19.567303 1 6 16 | B1->B0 | 3f3f 3232 | 0 0 | (0 0) (1 1)
8433 10:01:19.570625 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 10:01:19.574242 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 10:01:19.580851 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 10:01:19.584464 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 10:01:19.587199 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 10:01:19.590749 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 10:01:19.597738 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 10:01:19.600573 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8441 10:01:19.604068 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 10:01:19.610937 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 10:01:19.613982 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 10:01:19.617394 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 10:01:19.624018 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 10:01:19.627222 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 10:01:19.630653 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 10:01:19.637481 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 10:01:19.640792 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 10:01:19.644314 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 10:01:19.650647 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 10:01:19.653991 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 10:01:19.657856 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 10:01:19.664517 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 10:01:19.667481 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8456 10:01:19.670628 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8457 10:01:19.674339 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 10:01:19.677843 Total UI for P1: 0, mck2ui 16
8459 10:01:19.681381 best dqsien dly found for B0: ( 1, 9, 14)
8460 10:01:19.684494 Total UI for P1: 0, mck2ui 16
8461 10:01:19.687448 best dqsien dly found for B1: ( 1, 9, 14)
8462 10:01:19.690939 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8463 10:01:19.694335 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8464 10:01:19.694417
8465 10:01:19.701180 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8466 10:01:19.704642 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8467 10:01:19.707540 [Gating] SW calibration Done
8468 10:01:19.707623 ==
8469 10:01:19.710763 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 10:01:19.714250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 10:01:19.714333 ==
8472 10:01:19.714398 RX Vref Scan: 0
8473 10:01:19.714459
8474 10:01:19.717753 RX Vref 0 -> 0, step: 1
8475 10:01:19.717834
8476 10:01:19.721625 RX Delay 0 -> 252, step: 8
8477 10:01:19.724350 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8478 10:01:19.727418 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8479 10:01:19.734463 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8480 10:01:19.737426 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8481 10:01:19.740819 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8482 10:01:19.744261 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8483 10:01:19.747798 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8484 10:01:19.751288 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8485 10:01:19.757507 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8486 10:01:19.760875 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8487 10:01:19.764618 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8488 10:01:19.767800 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8489 10:01:19.770931 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8490 10:01:19.777892 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8491 10:01:19.780982 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8492 10:01:19.784081 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8493 10:01:19.784191 ==
8494 10:01:19.787326 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 10:01:19.790878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 10:01:19.794455 ==
8497 10:01:19.794551 DQS Delay:
8498 10:01:19.794619 DQS0 = 0, DQS1 = 0
8499 10:01:19.797814 DQM Delay:
8500 10:01:19.797917 DQM0 = 134, DQM1 = 127
8501 10:01:19.801182 DQ Delay:
8502 10:01:19.804608 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8503 10:01:19.807711 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8504 10:01:19.811177 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8505 10:01:19.814464 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8506 10:01:19.814538
8507 10:01:19.814601
8508 10:01:19.814689 ==
8509 10:01:19.817867 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 10:01:19.820838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 10:01:19.820916 ==
8512 10:01:19.820981
8513 10:01:19.821064
8514 10:01:19.824504 TX Vref Scan disable
8515 10:01:19.827964 == TX Byte 0 ==
8516 10:01:19.830815 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8517 10:01:19.834295 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8518 10:01:19.837735 == TX Byte 1 ==
8519 10:01:19.841486 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8520 10:01:19.844214 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8521 10:01:19.844310 ==
8522 10:01:19.847852 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 10:01:19.851294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 10:01:19.854354 ==
8525 10:01:19.866494
8526 10:01:19.869698 TX Vref early break, caculate TX vref
8527 10:01:19.873260 TX Vref=16, minBit 8, minWin=20, winSum=362
8528 10:01:19.876928 TX Vref=18, minBit 8, minWin=21, winSum=371
8529 10:01:19.879805 TX Vref=20, minBit 8, minWin=22, winSum=384
8530 10:01:19.883349 TX Vref=22, minBit 5, minWin=23, winSum=395
8531 10:01:19.886777 TX Vref=24, minBit 8, minWin=23, winSum=397
8532 10:01:19.893308 TX Vref=26, minBit 8, minWin=24, winSum=411
8533 10:01:19.896511 TX Vref=28, minBit 8, minWin=25, winSum=419
8534 10:01:19.900061 TX Vref=30, minBit 9, minWin=25, winSum=417
8535 10:01:19.903569 TX Vref=32, minBit 0, minWin=24, winSum=407
8536 10:01:19.906592 TX Vref=34, minBit 3, minWin=24, winSum=400
8537 10:01:19.910012 TX Vref=36, minBit 8, minWin=23, winSum=387
8538 10:01:19.916866 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
8539 10:01:19.916952
8540 10:01:19.920149 Final TX Range 0 Vref 28
8541 10:01:19.920221
8542 10:01:19.920281 ==
8543 10:01:19.923391 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 10:01:19.926742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 10:01:19.926837 ==
8546 10:01:19.926929
8547 10:01:19.927014
8548 10:01:19.930068 TX Vref Scan disable
8549 10:01:19.936822 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8550 10:01:19.936904 == TX Byte 0 ==
8551 10:01:19.939874 u2DelayCellOfst[0]=17 cells (5 PI)
8552 10:01:19.943473 u2DelayCellOfst[1]=10 cells (3 PI)
8553 10:01:19.946944 u2DelayCellOfst[2]=0 cells (0 PI)
8554 10:01:19.950413 u2DelayCellOfst[3]=7 cells (2 PI)
8555 10:01:19.953205 u2DelayCellOfst[4]=7 cells (2 PI)
8556 10:01:19.956779 u2DelayCellOfst[5]=17 cells (5 PI)
8557 10:01:19.960230 u2DelayCellOfst[6]=17 cells (5 PI)
8558 10:01:19.960353 u2DelayCellOfst[7]=7 cells (2 PI)
8559 10:01:19.966997 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8560 10:01:19.970370 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8561 10:01:19.970478 == TX Byte 1 ==
8562 10:01:19.973270 u2DelayCellOfst[8]=0 cells (0 PI)
8563 10:01:19.976725 u2DelayCellOfst[9]=7 cells (2 PI)
8564 10:01:19.980315 u2DelayCellOfst[10]=10 cells (3 PI)
8565 10:01:19.983633 u2DelayCellOfst[11]=7 cells (2 PI)
8566 10:01:19.987101 u2DelayCellOfst[12]=14 cells (4 PI)
8567 10:01:19.990148 u2DelayCellOfst[13]=17 cells (5 PI)
8568 10:01:19.993353 u2DelayCellOfst[14]=17 cells (5 PI)
8569 10:01:19.996875 u2DelayCellOfst[15]=17 cells (5 PI)
8570 10:01:20.000220 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8571 10:01:20.003652 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8572 10:01:20.006704 DramC Write-DBI on
8573 10:01:20.006785 ==
8574 10:01:20.010308 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 10:01:20.013669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 10:01:20.013751 ==
8577 10:01:20.013815
8578 10:01:20.017207
8579 10:01:20.017288 TX Vref Scan disable
8580 10:01:20.020413 == TX Byte 0 ==
8581 10:01:20.023992 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8582 10:01:20.024125 == TX Byte 1 ==
8583 10:01:20.030449 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8584 10:01:20.030531 DramC Write-DBI off
8585 10:01:20.030596
8586 10:01:20.033791 [DATLAT]
8587 10:01:20.033872 Freq=1600, CH1 RK0
8588 10:01:20.033937
8589 10:01:20.036899 DATLAT Default: 0xf
8590 10:01:20.036980 0, 0xFFFF, sum = 0
8591 10:01:20.040380 1, 0xFFFF, sum = 0
8592 10:01:20.040463 2, 0xFFFF, sum = 0
8593 10:01:20.044025 3, 0xFFFF, sum = 0
8594 10:01:20.044133 4, 0xFFFF, sum = 0
8595 10:01:20.047339 5, 0xFFFF, sum = 0
8596 10:01:20.047414 6, 0xFFFF, sum = 0
8597 10:01:20.050242 7, 0xFFFF, sum = 0
8598 10:01:20.050314 8, 0xFFFF, sum = 0
8599 10:01:20.053552 9, 0xFFFF, sum = 0
8600 10:01:20.053623 10, 0xFFFF, sum = 0
8601 10:01:20.057178 11, 0xFFFF, sum = 0
8602 10:01:20.060526 12, 0xFFFF, sum = 0
8603 10:01:20.060639 13, 0xFFFF, sum = 0
8604 10:01:20.063989 14, 0x0, sum = 1
8605 10:01:20.064075 15, 0x0, sum = 2
8606 10:01:20.064141 16, 0x0, sum = 3
8607 10:01:20.067257 17, 0x0, sum = 4
8608 10:01:20.067340 best_step = 15
8609 10:01:20.067405
8610 10:01:20.067466 ==
8611 10:01:20.070634 Dram Type= 6, Freq= 0, CH_1, rank 0
8612 10:01:20.076983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8613 10:01:20.077063 ==
8614 10:01:20.077128 RX Vref Scan: 1
8615 10:01:20.077222
8616 10:01:20.080237 Set Vref Range= 24 -> 127
8617 10:01:20.080308
8618 10:01:20.083845 RX Vref 24 -> 127, step: 1
8619 10:01:20.083940
8620 10:01:20.086836 RX Delay 11 -> 252, step: 4
8621 10:01:20.086905
8622 10:01:20.090265 Set Vref, RX VrefLevel [Byte0]: 24
8623 10:01:20.093883 [Byte1]: 24
8624 10:01:20.093952
8625 10:01:20.097122 Set Vref, RX VrefLevel [Byte0]: 25
8626 10:01:20.100597 [Byte1]: 25
8627 10:01:20.100677
8628 10:01:20.104125 Set Vref, RX VrefLevel [Byte0]: 26
8629 10:01:20.107347 [Byte1]: 26
8630 10:01:20.107447
8631 10:01:20.110626 Set Vref, RX VrefLevel [Byte0]: 27
8632 10:01:20.114040 [Byte1]: 27
8633 10:01:20.118148
8634 10:01:20.118226 Set Vref, RX VrefLevel [Byte0]: 28
8635 10:01:20.121312 [Byte1]: 28
8636 10:01:20.125582
8637 10:01:20.125658 Set Vref, RX VrefLevel [Byte0]: 29
8638 10:01:20.128967 [Byte1]: 29
8639 10:01:20.133106
8640 10:01:20.133202 Set Vref, RX VrefLevel [Byte0]: 30
8641 10:01:20.136572 [Byte1]: 30
8642 10:01:20.140393
8643 10:01:20.140463 Set Vref, RX VrefLevel [Byte0]: 31
8644 10:01:20.143912 [Byte1]: 31
8645 10:01:20.148599
8646 10:01:20.148700 Set Vref, RX VrefLevel [Byte0]: 32
8647 10:01:20.151573 [Byte1]: 32
8648 10:01:20.155921
8649 10:01:20.155990 Set Vref, RX VrefLevel [Byte0]: 33
8650 10:01:20.159340 [Byte1]: 33
8651 10:01:20.163252
8652 10:01:20.163360 Set Vref, RX VrefLevel [Byte0]: 34
8653 10:01:20.166683 [Byte1]: 34
8654 10:01:20.170876
8655 10:01:20.170949 Set Vref, RX VrefLevel [Byte0]: 35
8656 10:01:20.174319 [Byte1]: 35
8657 10:01:20.178913
8658 10:01:20.178984 Set Vref, RX VrefLevel [Byte0]: 36
8659 10:01:20.182191 [Byte1]: 36
8660 10:01:20.186465
8661 10:01:20.186539 Set Vref, RX VrefLevel [Byte0]: 37
8662 10:01:20.189847 [Byte1]: 37
8663 10:01:20.193966
8664 10:01:20.194042 Set Vref, RX VrefLevel [Byte0]: 38
8665 10:01:20.197542 [Byte1]: 38
8666 10:01:20.201318
8667 10:01:20.201392 Set Vref, RX VrefLevel [Byte0]: 39
8668 10:01:20.204693 [Byte1]: 39
8669 10:01:20.209380
8670 10:01:20.209455 Set Vref, RX VrefLevel [Byte0]: 40
8671 10:01:20.212243 [Byte1]: 40
8672 10:01:20.216583
8673 10:01:20.216720 Set Vref, RX VrefLevel [Byte0]: 41
8674 10:01:20.219799 [Byte1]: 41
8675 10:01:20.224126
8676 10:01:20.224201 Set Vref, RX VrefLevel [Byte0]: 42
8677 10:01:20.227551 [Byte1]: 42
8678 10:01:20.231789
8679 10:01:20.231871 Set Vref, RX VrefLevel [Byte0]: 43
8680 10:01:20.235258 [Byte1]: 43
8681 10:01:20.239312
8682 10:01:20.239393 Set Vref, RX VrefLevel [Byte0]: 44
8683 10:01:20.242817 [Byte1]: 44
8684 10:01:20.247414
8685 10:01:20.247496 Set Vref, RX VrefLevel [Byte0]: 45
8686 10:01:20.250501 [Byte1]: 45
8687 10:01:20.254855
8688 10:01:20.254936 Set Vref, RX VrefLevel [Byte0]: 46
8689 10:01:20.258251 [Byte1]: 46
8690 10:01:20.262432
8691 10:01:20.262514 Set Vref, RX VrefLevel [Byte0]: 47
8692 10:01:20.265741 [Byte1]: 47
8693 10:01:20.269900
8694 10:01:20.269981 Set Vref, RX VrefLevel [Byte0]: 48
8695 10:01:20.273282 [Byte1]: 48
8696 10:01:20.277469
8697 10:01:20.277549 Set Vref, RX VrefLevel [Byte0]: 49
8698 10:01:20.281347 [Byte1]: 49
8699 10:01:20.285415
8700 10:01:20.285497 Set Vref, RX VrefLevel [Byte0]: 50
8701 10:01:20.288339 [Byte1]: 50
8702 10:01:20.293192
8703 10:01:20.293274 Set Vref, RX VrefLevel [Byte0]: 51
8704 10:01:20.296286 [Byte1]: 51
8705 10:01:20.300555
8706 10:01:20.300663 Set Vref, RX VrefLevel [Byte0]: 52
8707 10:01:20.303868 [Byte1]: 52
8708 10:01:20.308476
8709 10:01:20.308580 Set Vref, RX VrefLevel [Byte0]: 53
8710 10:01:20.311271 [Byte1]: 53
8711 10:01:20.315604
8712 10:01:20.315686 Set Vref, RX VrefLevel [Byte0]: 54
8713 10:01:20.319204 [Byte1]: 54
8714 10:01:20.323138
8715 10:01:20.323219 Set Vref, RX VrefLevel [Byte0]: 55
8716 10:01:20.326837 [Byte1]: 55
8717 10:01:20.331176
8718 10:01:20.331258 Set Vref, RX VrefLevel [Byte0]: 56
8719 10:01:20.334078 [Byte1]: 56
8720 10:01:20.338318
8721 10:01:20.338400 Set Vref, RX VrefLevel [Byte0]: 57
8722 10:01:20.341782 [Byte1]: 57
8723 10:01:20.346696
8724 10:01:20.346777 Set Vref, RX VrefLevel [Byte0]: 58
8725 10:01:20.349618 [Byte1]: 58
8726 10:01:20.353612
8727 10:01:20.353693 Set Vref, RX VrefLevel [Byte0]: 59
8728 10:01:20.356883 [Byte1]: 59
8729 10:01:20.361744
8730 10:01:20.361825 Set Vref, RX VrefLevel [Byte0]: 60
8731 10:01:20.364765 [Byte1]: 60
8732 10:01:20.368989
8733 10:01:20.369086 Set Vref, RX VrefLevel [Byte0]: 61
8734 10:01:20.372054 [Byte1]: 61
8735 10:01:20.376611
8736 10:01:20.376742 Set Vref, RX VrefLevel [Byte0]: 62
8737 10:01:20.380008 [Byte1]: 62
8738 10:01:20.384114
8739 10:01:20.384185 Set Vref, RX VrefLevel [Byte0]: 63
8740 10:01:20.387578 [Byte1]: 63
8741 10:01:20.391693
8742 10:01:20.391789 Set Vref, RX VrefLevel [Byte0]: 64
8743 10:01:20.395247 [Byte1]: 64
8744 10:01:20.399523
8745 10:01:20.399596 Set Vref, RX VrefLevel [Byte0]: 65
8746 10:01:20.402975 [Byte1]: 65
8747 10:01:20.407349
8748 10:01:20.407422 Set Vref, RX VrefLevel [Byte0]: 66
8749 10:01:20.410379 [Byte1]: 66
8750 10:01:20.414476
8751 10:01:20.418117 Set Vref, RX VrefLevel [Byte0]: 67
8752 10:01:20.418191 [Byte1]: 67
8753 10:01:20.422075
8754 10:01:20.422144 Set Vref, RX VrefLevel [Byte0]: 68
8755 10:01:20.425284 [Byte1]: 68
8756 10:01:20.429892
8757 10:01:20.429967 Set Vref, RX VrefLevel [Byte0]: 69
8758 10:01:20.433155 [Byte1]: 69
8759 10:01:20.437461
8760 10:01:20.437556 Set Vref, RX VrefLevel [Byte0]: 70
8761 10:01:20.440550 [Byte1]: 70
8762 10:01:20.444896
8763 10:01:20.444995 Set Vref, RX VrefLevel [Byte0]: 71
8764 10:01:20.448176 [Byte1]: 71
8765 10:01:20.453132
8766 10:01:20.453213 Set Vref, RX VrefLevel [Byte0]: 72
8767 10:01:20.455838 [Byte1]: 72
8768 10:01:20.460563
8769 10:01:20.460661 Set Vref, RX VrefLevel [Byte0]: 73
8770 10:01:20.463900 [Byte1]: 73
8771 10:01:20.467979
8772 10:01:20.468061 Final RX Vref Byte 0 = 52 to rank0
8773 10:01:20.471427 Final RX Vref Byte 1 = 59 to rank0
8774 10:01:20.474366 Final RX Vref Byte 0 = 52 to rank1
8775 10:01:20.477884 Final RX Vref Byte 1 = 59 to rank1==
8776 10:01:20.481458 Dram Type= 6, Freq= 0, CH_1, rank 0
8777 10:01:20.487756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 10:01:20.487841 ==
8779 10:01:20.487906 DQS Delay:
8780 10:01:20.487966 DQS0 = 0, DQS1 = 0
8781 10:01:20.491052 DQM Delay:
8782 10:01:20.491134 DQM0 = 130, DQM1 = 124
8783 10:01:20.494587 DQ Delay:
8784 10:01:20.497984 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8785 10:01:20.501232 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8786 10:01:20.504432 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
8787 10:01:20.507943 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8788 10:01:20.508046
8789 10:01:20.508128
8790 10:01:20.508190
8791 10:01:20.511494 [DramC_TX_OE_Calibration] TA2
8792 10:01:20.514489 Original DQ_B0 (3 6) =30, OEN = 27
8793 10:01:20.517892 Original DQ_B1 (3 6) =30, OEN = 27
8794 10:01:20.520985 24, 0x0, End_B0=24 End_B1=24
8795 10:01:20.521067 25, 0x0, End_B0=25 End_B1=25
8796 10:01:20.524641 26, 0x0, End_B0=26 End_B1=26
8797 10:01:20.527666 27, 0x0, End_B0=27 End_B1=27
8798 10:01:20.531225 28, 0x0, End_B0=28 End_B1=28
8799 10:01:20.531334 29, 0x0, End_B0=29 End_B1=29
8800 10:01:20.534765 30, 0x0, End_B0=30 End_B1=30
8801 10:01:20.538206 31, 0x4545, End_B0=30 End_B1=30
8802 10:01:20.541536 Byte0 end_step=30 best_step=27
8803 10:01:20.544646 Byte1 end_step=30 best_step=27
8804 10:01:20.547766 Byte0 TX OE(2T, 0.5T) = (3, 3)
8805 10:01:20.547874 Byte1 TX OE(2T, 0.5T) = (3, 3)
8806 10:01:20.548069
8807 10:01:20.548176
8808 10:01:20.558372 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8809 10:01:20.561209 CH1 RK0: MR19=302, MR18=12FE
8810 10:01:20.568148 CH1_RK0: MR19=0x302, MR18=0x12FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8811 10:01:20.568231
8812 10:01:20.571610 ----->DramcWriteLeveling(PI) begin...
8813 10:01:20.571693 ==
8814 10:01:20.574585 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 10:01:20.578025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 10:01:20.578150 ==
8817 10:01:20.581348 Write leveling (Byte 0): 28 => 28
8818 10:01:20.585180 Write leveling (Byte 1): 28 => 28
8819 10:01:20.588315 DramcWriteLeveling(PI) end<-----
8820 10:01:20.588396
8821 10:01:20.588460 ==
8822 10:01:20.591792 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 10:01:20.594800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 10:01:20.594883 ==
8825 10:01:20.598238 [Gating] SW mode calibration
8826 10:01:20.605138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8827 10:01:20.608447 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8828 10:01:20.614887 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 10:01:20.618503 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 10:01:20.621725 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8831 10:01:20.628537 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (1 1) (1 1)
8832 10:01:20.631494 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 10:01:20.634987 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 10:01:20.641576 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 10:01:20.644925 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 10:01:20.648231 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 10:01:20.655231 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8838 10:01:20.658289 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
8839 10:01:20.662035 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8840 10:01:20.668377 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8841 10:01:20.671880 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 10:01:20.674743 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 10:01:20.681649 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 10:01:20.684781 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 10:01:20.688146 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 10:01:20.694808 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8847 10:01:20.698221 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8848 10:01:20.701760 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 10:01:20.704970 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 10:01:20.711833 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 10:01:20.715202 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 10:01:20.718772 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 10:01:20.725218 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 10:01:20.728904 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8855 10:01:20.731569 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8856 10:01:20.738540 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8857 10:01:20.742104 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 10:01:20.745129 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 10:01:20.751950 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 10:01:20.755290 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 10:01:20.758579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 10:01:20.765367 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 10:01:20.768598 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 10:01:20.772104 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 10:01:20.775643 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 10:01:20.781927 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 10:01:20.785428 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 10:01:20.788921 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 10:01:20.795241 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8870 10:01:20.798943 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8871 10:01:20.802238 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8872 10:01:20.805279 Total UI for P1: 0, mck2ui 16
8873 10:01:20.808680 best dqsien dly found for B0: ( 1, 9, 6)
8874 10:01:20.815108 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8875 10:01:20.818767 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 10:01:20.821852 Total UI for P1: 0, mck2ui 16
8877 10:01:20.825364 best dqsien dly found for B1: ( 1, 9, 14)
8878 10:01:20.829016 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8879 10:01:20.832067 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8880 10:01:20.832308
8881 10:01:20.835558 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8882 10:01:20.838801 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8883 10:01:20.842739 [Gating] SW calibration Done
8884 10:01:20.843125 ==
8885 10:01:20.845633 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 10:01:20.848924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 10:01:20.852599 ==
8888 10:01:20.853063 RX Vref Scan: 0
8889 10:01:20.853398
8890 10:01:20.855694 RX Vref 0 -> 0, step: 1
8891 10:01:20.856112
8892 10:01:20.856442 RX Delay 0 -> 252, step: 8
8893 10:01:20.862655 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8894 10:01:20.865612 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8895 10:01:20.869197 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8896 10:01:20.872378 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8897 10:01:20.875928 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8898 10:01:20.882455 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8899 10:01:20.885960 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8900 10:01:20.889339 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8901 10:01:20.892861 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8902 10:01:20.895744 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8903 10:01:20.902648 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8904 10:01:20.906224 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8905 10:01:20.908839 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8906 10:01:20.912709 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8907 10:01:20.916196 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8908 10:01:20.922866 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8909 10:01:20.923289 ==
8910 10:01:20.926119 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 10:01:20.929699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 10:01:20.930125 ==
8913 10:01:20.930461 DQS Delay:
8914 10:01:20.932765 DQS0 = 0, DQS1 = 0
8915 10:01:20.933340 DQM Delay:
8916 10:01:20.936088 DQM0 = 132, DQM1 = 128
8917 10:01:20.936508 DQ Delay:
8918 10:01:20.939270 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8919 10:01:20.942750 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8920 10:01:20.945753 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8921 10:01:20.949157 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8922 10:01:20.949610
8923 10:01:20.949944
8924 10:01:20.952977 ==
8925 10:01:20.953397 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 10:01:20.959345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 10:01:20.959862 ==
8928 10:01:20.960206
8929 10:01:20.960517
8930 10:01:20.962802 TX Vref Scan disable
8931 10:01:20.963218 == TX Byte 0 ==
8932 10:01:20.966180 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8933 10:01:20.972935 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8934 10:01:20.973360 == TX Byte 1 ==
8935 10:01:20.976217 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8936 10:01:20.982831 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8937 10:01:20.983369 ==
8938 10:01:20.986086 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 10:01:20.989108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 10:01:20.989531 ==
8941 10:01:21.002779
8942 10:01:21.006362 TX Vref early break, caculate TX vref
8943 10:01:21.009839 TX Vref=16, minBit 1, minWin=22, winSum=370
8944 10:01:21.013214 TX Vref=18, minBit 0, minWin=23, winSum=383
8945 10:01:21.016490 TX Vref=20, minBit 6, minWin=23, winSum=387
8946 10:01:21.019748 TX Vref=22, minBit 8, minWin=23, winSum=392
8947 10:01:21.023243 TX Vref=24, minBit 6, minWin=24, winSum=408
8948 10:01:21.029730 TX Vref=26, minBit 0, minWin=25, winSum=415
8949 10:01:21.032923 TX Vref=28, minBit 4, minWin=25, winSum=417
8950 10:01:21.036353 TX Vref=30, minBit 4, minWin=25, winSum=417
8951 10:01:21.039710 TX Vref=32, minBit 0, minWin=25, winSum=410
8952 10:01:21.043397 TX Vref=34, minBit 0, minWin=24, winSum=401
8953 10:01:21.046120 TX Vref=36, minBit 0, minWin=23, winSum=389
8954 10:01:21.052979 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 28
8955 10:01:21.053400
8956 10:01:21.056435 Final TX Range 0 Vref 28
8957 10:01:21.056892
8958 10:01:21.057228 ==
8959 10:01:21.059770 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 10:01:21.062940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 10:01:21.063362 ==
8962 10:01:21.063697
8963 10:01:21.064006
8964 10:01:21.066551 TX Vref Scan disable
8965 10:01:21.072822 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8966 10:01:21.073244 == TX Byte 0 ==
8967 10:01:21.076374 u2DelayCellOfst[0]=17 cells (5 PI)
8968 10:01:21.079569 u2DelayCellOfst[1]=14 cells (4 PI)
8969 10:01:21.083207 u2DelayCellOfst[2]=0 cells (0 PI)
8970 10:01:21.086285 u2DelayCellOfst[3]=7 cells (2 PI)
8971 10:01:21.090001 u2DelayCellOfst[4]=10 cells (3 PI)
8972 10:01:21.092822 u2DelayCellOfst[5]=17 cells (5 PI)
8973 10:01:21.096456 u2DelayCellOfst[6]=17 cells (5 PI)
8974 10:01:21.096925 u2DelayCellOfst[7]=7 cells (2 PI)
8975 10:01:21.103289 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8976 10:01:21.106196 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8977 10:01:21.106618 == TX Byte 1 ==
8978 10:01:21.109771 u2DelayCellOfst[8]=0 cells (0 PI)
8979 10:01:21.113157 u2DelayCellOfst[9]=3 cells (1 PI)
8980 10:01:21.116624 u2DelayCellOfst[10]=10 cells (3 PI)
8981 10:01:21.119836 u2DelayCellOfst[11]=7 cells (2 PI)
8982 10:01:21.123352 u2DelayCellOfst[12]=14 cells (4 PI)
8983 10:01:21.126661 u2DelayCellOfst[13]=17 cells (5 PI)
8984 10:01:21.130197 u2DelayCellOfst[14]=17 cells (5 PI)
8985 10:01:21.133571 u2DelayCellOfst[15]=17 cells (5 PI)
8986 10:01:21.136539 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8987 10:01:21.139754 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8988 10:01:21.143109 DramC Write-DBI on
8989 10:01:21.143625 ==
8990 10:01:21.146135 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 10:01:21.149840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 10:01:21.150321 ==
8993 10:01:21.150688
8994 10:01:21.153185
8995 10:01:21.153605 TX Vref Scan disable
8996 10:01:21.156377 == TX Byte 0 ==
8997 10:01:21.159961 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8998 10:01:21.163116 == TX Byte 1 ==
8999 10:01:21.166577 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9000 10:01:21.167027 DramC Write-DBI off
9001 10:01:21.167393
9002 10:01:21.169594 [DATLAT]
9003 10:01:21.170049 Freq=1600, CH1 RK1
9004 10:01:21.170419
9005 10:01:21.173162 DATLAT Default: 0xf
9006 10:01:21.173610 0, 0xFFFF, sum = 0
9007 10:01:21.176517 1, 0xFFFF, sum = 0
9008 10:01:21.177016 2, 0xFFFF, sum = 0
9009 10:01:21.180109 3, 0xFFFF, sum = 0
9010 10:01:21.180562 4, 0xFFFF, sum = 0
9011 10:01:21.183014 5, 0xFFFF, sum = 0
9012 10:01:21.183467 6, 0xFFFF, sum = 0
9013 10:01:21.186680 7, 0xFFFF, sum = 0
9014 10:01:21.187134 8, 0xFFFF, sum = 0
9015 10:01:21.189971 9, 0xFFFF, sum = 0
9016 10:01:21.193556 10, 0xFFFF, sum = 0
9017 10:01:21.194031 11, 0xFFFF, sum = 0
9018 10:01:21.196661 12, 0xFFFF, sum = 0
9019 10:01:21.197193 13, 0xFFFF, sum = 0
9020 10:01:21.199756 14, 0x0, sum = 1
9021 10:01:21.200251 15, 0x0, sum = 2
9022 10:01:21.200620 16, 0x0, sum = 3
9023 10:01:21.203200 17, 0x0, sum = 4
9024 10:01:21.203652 best_step = 15
9025 10:01:21.204018
9026 10:01:21.206677 ==
9027 10:01:21.207126 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 10:01:21.213358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 10:01:21.213826 ==
9030 10:01:21.214200 RX Vref Scan: 0
9031 10:01:21.214546
9032 10:01:21.216622 RX Vref 0 -> 0, step: 1
9033 10:01:21.217211
9034 10:01:21.220125 RX Delay 11 -> 252, step: 4
9035 10:01:21.222896 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9036 10:01:21.226456 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9037 10:01:21.233182 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9038 10:01:21.236686 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9039 10:01:21.240096 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9040 10:01:21.242860 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9041 10:01:21.246148 iDelay=195, Bit 6, Center 136 (87 ~ 186) 100
9042 10:01:21.252851 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9043 10:01:21.256454 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9044 10:01:21.259479 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9045 10:01:21.262903 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9046 10:01:21.266467 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9047 10:01:21.273192 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9048 10:01:21.276606 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
9049 10:01:21.280190 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
9050 10:01:21.283479 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9051 10:01:21.283900 ==
9052 10:01:21.286786 Dram Type= 6, Freq= 0, CH_1, rank 1
9053 10:01:21.290187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9054 10:01:21.293151 ==
9055 10:01:21.293640 DQS Delay:
9056 10:01:21.294078 DQS0 = 0, DQS1 = 0
9057 10:01:21.296438 DQM Delay:
9058 10:01:21.296920 DQM0 = 128, DQM1 = 126
9059 10:01:21.300092 DQ Delay:
9060 10:01:21.303534 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
9061 10:01:21.306751 DQ4 =128, DQ5 =142, DQ6 =136, DQ7 =124
9062 10:01:21.310156 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120
9063 10:01:21.313437 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =136
9064 10:01:21.313867
9065 10:01:21.314309
9066 10:01:21.314720
9067 10:01:21.316803 [DramC_TX_OE_Calibration] TA2
9068 10:01:21.320257 Original DQ_B0 (3 6) =30, OEN = 27
9069 10:01:21.323503 Original DQ_B1 (3 6) =30, OEN = 27
9070 10:01:21.323880 24, 0x0, End_B0=24 End_B1=24
9071 10:01:21.326936 25, 0x0, End_B0=25 End_B1=25
9072 10:01:21.330338 26, 0x0, End_B0=26 End_B1=26
9073 10:01:21.333292 27, 0x0, End_B0=27 End_B1=27
9074 10:01:21.336452 28, 0x0, End_B0=28 End_B1=28
9075 10:01:21.336925 29, 0x0, End_B0=29 End_B1=29
9076 10:01:21.340149 30, 0x0, End_B0=30 End_B1=30
9077 10:01:21.343499 31, 0x4545, End_B0=30 End_B1=30
9078 10:01:21.347001 Byte0 end_step=30 best_step=27
9079 10:01:21.349889 Byte1 end_step=30 best_step=27
9080 10:01:21.353309 Byte0 TX OE(2T, 0.5T) = (3, 3)
9081 10:01:21.353793 Byte1 TX OE(2T, 0.5T) = (3, 3)
9082 10:01:21.354376
9083 10:01:21.354744
9084 10:01:21.363448 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9085 10:01:21.366810 CH1 RK1: MR19=303, MR18=1117
9086 10:01:21.369898 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9087 10:01:21.373566 [RxdqsGatingPostProcess] freq 1600
9088 10:01:21.380440 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9089 10:01:21.383313 best DQS0 dly(2T, 0.5T) = (1, 1)
9090 10:01:21.386671 best DQS1 dly(2T, 0.5T) = (1, 1)
9091 10:01:21.390215 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9092 10:01:21.393569 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9093 10:01:21.396870 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 10:01:21.400311 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 10:01:21.400865 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 10:01:21.403336 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 10:01:21.407098 Pre-setting of DQS Precalculation
9098 10:01:21.413985 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9099 10:01:21.420041 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9100 10:01:21.427080 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9101 10:01:21.427495
9102 10:01:21.427820
9103 10:01:21.430263 [Calibration Summary] 3200 Mbps
9104 10:01:21.430676 CH 0, Rank 0
9105 10:01:21.433458 SW Impedance : PASS
9106 10:01:21.436662 DUTY Scan : NO K
9107 10:01:21.437114 ZQ Calibration : PASS
9108 10:01:21.440246 Jitter Meter : NO K
9109 10:01:21.443635 CBT Training : PASS
9110 10:01:21.444047 Write leveling : PASS
9111 10:01:21.446676 RX DQS gating : PASS
9112 10:01:21.450402 RX DQ/DQS(RDDQC) : PASS
9113 10:01:21.450807 TX DQ/DQS : PASS
9114 10:01:21.453542 RX DATLAT : PASS
9115 10:01:21.456919 RX DQ/DQS(Engine): PASS
9116 10:01:21.457331 TX OE : PASS
9117 10:01:21.457659 All Pass.
9118 10:01:21.460807
9119 10:01:21.461476 CH 0, Rank 1
9120 10:01:21.463587 SW Impedance : PASS
9121 10:01:21.463963 DUTY Scan : NO K
9122 10:01:21.467007 ZQ Calibration : PASS
9123 10:01:21.467433 Jitter Meter : NO K
9124 10:01:21.470433 CBT Training : PASS
9125 10:01:21.473675 Write leveling : PASS
9126 10:01:21.474257 RX DQS gating : PASS
9127 10:01:21.476728 RX DQ/DQS(RDDQC) : PASS
9128 10:01:21.480256 TX DQ/DQS : PASS
9129 10:01:21.480878 RX DATLAT : PASS
9130 10:01:21.483836 RX DQ/DQS(Engine): PASS
9131 10:01:21.487308 TX OE : PASS
9132 10:01:21.487911 All Pass.
9133 10:01:21.488334
9134 10:01:21.488871 CH 1, Rank 0
9135 10:01:21.490136 SW Impedance : PASS
9136 10:01:21.493649 DUTY Scan : NO K
9137 10:01:21.494225 ZQ Calibration : PASS
9138 10:01:21.496996 Jitter Meter : NO K
9139 10:01:21.500715 CBT Training : PASS
9140 10:01:21.501130 Write leveling : PASS
9141 10:01:21.503872 RX DQS gating : PASS
9142 10:01:21.506867 RX DQ/DQS(RDDQC) : PASS
9143 10:01:21.507276 TX DQ/DQS : PASS
9144 10:01:21.510252 RX DATLAT : PASS
9145 10:01:21.510667 RX DQ/DQS(Engine): PASS
9146 10:01:21.513386 TX OE : PASS
9147 10:01:21.513797 All Pass.
9148 10:01:21.514226
9149 10:01:21.516821 CH 1, Rank 1
9150 10:01:21.517391 SW Impedance : PASS
9151 10:01:21.520200 DUTY Scan : NO K
9152 10:01:21.523806 ZQ Calibration : PASS
9153 10:01:21.524204 Jitter Meter : NO K
9154 10:01:21.527136 CBT Training : PASS
9155 10:01:21.530700 Write leveling : PASS
9156 10:01:21.531077 RX DQS gating : PASS
9157 10:01:21.534076 RX DQ/DQS(RDDQC) : PASS
9158 10:01:21.537258 TX DQ/DQS : PASS
9159 10:01:21.537649 RX DATLAT : PASS
9160 10:01:21.540270 RX DQ/DQS(Engine): PASS
9161 10:01:21.543615 TX OE : PASS
9162 10:01:21.544070 All Pass.
9163 10:01:21.544492
9164 10:01:21.544906 DramC Write-DBI on
9165 10:01:21.546830 PER_BANK_REFRESH: Hybrid Mode
9166 10:01:21.550461 TX_TRACKING: ON
9167 10:01:21.557238 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9168 10:01:21.567328 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9169 10:01:21.573969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9170 10:01:21.577434 [FAST_K] Save calibration result to emmc
9171 10:01:21.580953 sync common calibartion params.
9172 10:01:21.581362 sync cbt_mode0:1, 1:1
9173 10:01:21.583704 dram_init: ddr_geometry: 2
9174 10:01:21.587105 dram_init: ddr_geometry: 2
9175 10:01:21.590503 dram_init: ddr_geometry: 2
9176 10:01:21.590901 0:dram_rank_size:100000000
9177 10:01:21.593601 1:dram_rank_size:100000000
9178 10:01:21.600550 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9179 10:01:21.601045 DFS_SHUFFLE_HW_MODE: ON
9180 10:01:21.606964 dramc_set_vcore_voltage set vcore to 725000
9181 10:01:21.607358 Read voltage for 1600, 0
9182 10:01:21.607694 Vio18 = 0
9183 10:01:21.610820 Vcore = 725000
9184 10:01:21.611194 Vdram = 0
9185 10:01:21.611565 Vddq = 0
9186 10:01:21.613732 Vmddr = 0
9187 10:01:21.614084 switch to 3200 Mbps bootup
9188 10:01:21.617239 [DramcRunTimeConfig]
9189 10:01:21.617607 PHYPLL
9190 10:01:21.620662 DPM_CONTROL_AFTERK: ON
9191 10:01:21.621073 PER_BANK_REFRESH: ON
9192 10:01:21.623914 REFRESH_OVERHEAD_REDUCTION: ON
9193 10:01:21.627198 CMD_PICG_NEW_MODE: OFF
9194 10:01:21.627566 XRTWTW_NEW_MODE: ON
9195 10:01:21.630758 XRTRTR_NEW_MODE: ON
9196 10:01:21.631118 TX_TRACKING: ON
9197 10:01:21.634041 RDSEL_TRACKING: OFF
9198 10:01:21.637219 DQS Precalculation for DVFS: ON
9199 10:01:21.637618 RX_TRACKING: OFF
9200 10:01:21.640325 HW_GATING DBG: ON
9201 10:01:21.640738 ZQCS_ENABLE_LP4: ON
9202 10:01:21.643826 RX_PICG_NEW_MODE: ON
9203 10:01:21.644215 TX_PICG_NEW_MODE: ON
9204 10:01:21.646883 ENABLE_RX_DCM_DPHY: ON
9205 10:01:21.650376 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9206 10:01:21.653643 DUMMY_READ_FOR_TRACKING: OFF
9207 10:01:21.657290 !!! SPM_CONTROL_AFTERK: OFF
9208 10:01:21.657784 !!! SPM could not control APHY
9209 10:01:21.660601 IMPEDANCE_TRACKING: ON
9210 10:01:21.661229 TEMP_SENSOR: ON
9211 10:01:21.663704 HW_SAVE_FOR_SR: OFF
9212 10:01:21.666982 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9213 10:01:21.670233 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9214 10:01:21.673672 Read ODT Tracking: ON
9215 10:01:21.674099 Refresh Rate DeBounce: ON
9216 10:01:21.677275 DFS_NO_QUEUE_FLUSH: ON
9217 10:01:21.680374 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9218 10:01:21.683766 ENABLE_DFS_RUNTIME_MRW: OFF
9219 10:01:21.684192 DDR_RESERVE_NEW_MODE: ON
9220 10:01:21.686762 MR_CBT_SWITCH_FREQ: ON
9221 10:01:21.690120 =========================
9222 10:01:21.707835 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9223 10:01:21.711371 dram_init: ddr_geometry: 2
9224 10:01:21.729526 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9225 10:01:21.732463 dram_init: dram init end (result: 0)
9226 10:01:21.739797 DRAM-K: Full calibration passed in 24583 msecs
9227 10:01:21.742954 MRC: failed to locate region type 0.
9228 10:01:21.743397 DRAM rank0 size:0x100000000,
9229 10:01:21.746050 DRAM rank1 size=0x100000000
9230 10:01:21.755690 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9231 10:01:21.762650 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9232 10:01:21.769363 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9233 10:01:21.775944 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9234 10:01:21.779085 DRAM rank0 size:0x100000000,
9235 10:01:21.782555 DRAM rank1 size=0x100000000
9236 10:01:21.783021 CBMEM:
9237 10:01:21.785984 IMD: root @ 0xfffff000 254 entries.
9238 10:01:21.789040 IMD: root @ 0xffffec00 62 entries.
9239 10:01:21.792462 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9240 10:01:21.796019 WARNING: RO_VPD is uninitialized or empty.
9241 10:01:21.802790 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9242 10:01:21.809378 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9243 10:01:21.822253 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9244 10:01:21.833282 BS: romstage times (exec / console): total (unknown) / 24087 ms
9245 10:01:21.833797
9246 10:01:21.834240
9247 10:01:21.843349 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9248 10:01:21.846950 ARM64: Exception handlers installed.
9249 10:01:21.850382 ARM64: Testing exception
9250 10:01:21.853489 ARM64: Done test exception
9251 10:01:21.854033 Enumerating buses...
9252 10:01:21.856640 Show all devs... Before device enumeration.
9253 10:01:21.860194 Root Device: enabled 1
9254 10:01:21.863862 CPU_CLUSTER: 0: enabled 1
9255 10:01:21.864290 CPU: 00: enabled 1
9256 10:01:21.866912 Compare with tree...
9257 10:01:21.867335 Root Device: enabled 1
9258 10:01:21.870336 CPU_CLUSTER: 0: enabled 1
9259 10:01:21.873600 CPU: 00: enabled 1
9260 10:01:21.874018 Root Device scanning...
9261 10:01:21.876964 scan_static_bus for Root Device
9262 10:01:21.880228 CPU_CLUSTER: 0 enabled
9263 10:01:21.883570 scan_static_bus for Root Device done
9264 10:01:21.886885 scan_bus: bus Root Device finished in 8 msecs
9265 10:01:21.887310 done
9266 10:01:21.893812 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9267 10:01:21.897363 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9268 10:01:21.903613 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9269 10:01:21.906880 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9270 10:01:21.910240 Allocating resources...
9271 10:01:21.910659 Reading resources...
9272 10:01:21.917099 Root Device read_resources bus 0 link: 0
9273 10:01:21.917535 DRAM rank0 size:0x100000000,
9274 10:01:21.920333 DRAM rank1 size=0x100000000
9275 10:01:21.923577 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9276 10:01:21.927120 CPU: 00 missing read_resources
9277 10:01:21.930476 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9278 10:01:21.936854 Root Device read_resources bus 0 link: 0 done
9279 10:01:21.937277 Done reading resources.
9280 10:01:21.943421 Show resources in subtree (Root Device)...After reading.
9281 10:01:21.946974 Root Device child on link 0 CPU_CLUSTER: 0
9282 10:01:21.950245 CPU_CLUSTER: 0 child on link 0 CPU: 00
9283 10:01:21.960509 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9284 10:01:21.960975 CPU: 00
9285 10:01:21.963594 Root Device assign_resources, bus 0 link: 0
9286 10:01:21.966941 CPU_CLUSTER: 0 missing set_resources
9287 10:01:21.970205 Root Device assign_resources, bus 0 link: 0 done
9288 10:01:21.973570 Done setting resources.
9289 10:01:21.980099 Show resources in subtree (Root Device)...After assigning values.
9290 10:01:21.983336 Root Device child on link 0 CPU_CLUSTER: 0
9291 10:01:21.987063 CPU_CLUSTER: 0 child on link 0 CPU: 00
9292 10:01:21.996828 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9293 10:01:21.997368 CPU: 00
9294 10:01:22.000145 Done allocating resources.
9295 10:01:22.003485 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9296 10:01:22.007226 Enabling resources...
9297 10:01:22.007749 done.
9298 10:01:22.010051 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9299 10:01:22.013505 Initializing devices...
9300 10:01:22.013981 Root Device init
9301 10:01:22.016985 init hardware done!
9302 10:01:22.020644 0x00000018: ctrlr->caps
9303 10:01:22.021173 52.000 MHz: ctrlr->f_max
9304 10:01:22.023954 0.400 MHz: ctrlr->f_min
9305 10:01:22.027103 0x40ff8080: ctrlr->voltages
9306 10:01:22.027584 sclk: 390625
9307 10:01:22.030511 Bus Width = 1
9308 10:01:22.030923 sclk: 390625
9309 10:01:22.031251 Bus Width = 1
9310 10:01:22.033678 Early init status = 3
9311 10:01:22.037145 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9312 10:01:22.041240 in-header: 03 fb 00 00 01 00 00 00
9313 10:01:22.044777 in-data: 01
9314 10:01:22.047819 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 10:01:22.052336 in-header: 03 fb 00 00 01 00 00 00
9316 10:01:22.056071 in-data: 01
9317 10:01:22.059472 [SSUSB] Setting up USB HOST controller...
9318 10:01:22.062911 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9319 10:01:22.065865 [SSUSB] phy power-on done.
9320 10:01:22.069478 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9321 10:01:22.075727 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9322 10:01:22.079155 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9323 10:01:22.085991 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9324 10:01:22.092785 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9325 10:01:22.099053 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9326 10:01:22.105873 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9327 10:01:22.112541 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9328 10:01:22.116103 SPM: binary array size = 0x9dc
9329 10:01:22.119581 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9330 10:01:22.125964 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9331 10:01:22.132355 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9332 10:01:22.136164 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9333 10:01:22.139462 configure_display: Starting display init
9334 10:01:22.175809 anx7625_power_on_init: Init interface.
9335 10:01:22.179037 anx7625_disable_pd_protocol: Disabled PD feature.
9336 10:01:22.182611 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9337 10:01:22.210042 anx7625_start_dp_work: Secure OCM version=00
9338 10:01:22.213465 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9339 10:01:22.228359 sp_tx_get_edid_block: EDID Block = 1
9340 10:01:22.331244 Extracted contents:
9341 10:01:22.334397 header: 00 ff ff ff ff ff ff 00
9342 10:01:22.337699 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9343 10:01:22.340703 version: 01 04
9344 10:01:22.344274 basic params: 95 1f 11 78 0a
9345 10:01:22.347744 chroma info: 76 90 94 55 54 90 27 21 50 54
9346 10:01:22.350959 established: 00 00 00
9347 10:01:22.357694 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9348 10:01:22.360979 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9349 10:01:22.367797 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 10:01:22.374123 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9351 10:01:22.380897 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9352 10:01:22.383949 extensions: 00
9353 10:01:22.384244 checksum: fb
9354 10:01:22.384482
9355 10:01:22.387495 Manufacturer: IVO Model 57d Serial Number 0
9356 10:01:22.390868 Made week 0 of 2020
9357 10:01:22.391166 EDID version: 1.4
9358 10:01:22.394345 Digital display
9359 10:01:22.397590 6 bits per primary color channel
9360 10:01:22.397894 DisplayPort interface
9361 10:01:22.400989 Maximum image size: 31 cm x 17 cm
9362 10:01:22.401288 Gamma: 220%
9363 10:01:22.404692 Check DPMS levels
9364 10:01:22.407923 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9365 10:01:22.410732 First detailed timing is preferred timing
9366 10:01:22.414206 Established timings supported:
9367 10:01:22.417809 Standard timings supported:
9368 10:01:22.418226 Detailed timings
9369 10:01:22.424576 Hex of detail: 383680a07038204018303c0035ae10000019
9370 10:01:22.427559 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9371 10:01:22.431058 0780 0798 07c8 0820 hborder 0
9372 10:01:22.438048 0438 043b 0447 0458 vborder 0
9373 10:01:22.438495 -hsync -vsync
9374 10:01:22.441164 Did detailed timing
9375 10:01:22.444708 Hex of detail: 000000000000000000000000000000000000
9376 10:01:22.448072 Manufacturer-specified data, tag 0
9377 10:01:22.454795 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9378 10:01:22.455308 ASCII string: InfoVision
9379 10:01:22.461249 Hex of detail: 000000fe00523134304e574635205248200a
9380 10:01:22.461668 ASCII string: R140NWF5 RH
9381 10:01:22.464593 Checksum
9382 10:01:22.465068 Checksum: 0xfb (valid)
9383 10:01:22.471508 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9384 10:01:22.471946 DSI data_rate: 832800000 bps
9385 10:01:22.478715 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9386 10:01:22.481795 anx7625_parse_edid: pixelclock(138800).
9387 10:01:22.485208 hactive(1920), hsync(48), hfp(24), hbp(88)
9388 10:01:22.488779 vactive(1080), vsync(12), vfp(3), vbp(17)
9389 10:01:22.491789 anx7625_dsi_config: config dsi.
9390 10:01:22.498788 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9391 10:01:22.513236 anx7625_dsi_config: success to config DSI
9392 10:01:22.516413 anx7625_dp_start: MIPI phy setup OK.
9393 10:01:22.519823 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9394 10:01:22.523385 mtk_ddp_mode_set invalid vrefresh 60
9395 10:01:22.526317 main_disp_path_setup
9396 10:01:22.526729 ovl_layer_smi_id_en
9397 10:01:22.529889 ovl_layer_smi_id_en
9398 10:01:22.530405 ccorr_config
9399 10:01:22.530810 aal_config
9400 10:01:22.533423 gamma_config
9401 10:01:22.533927 postmask_config
9402 10:01:22.536270 dither_config
9403 10:01:22.539762 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9404 10:01:22.546392 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9405 10:01:22.549508 Root Device init finished in 530 msecs
9406 10:01:22.549964 CPU_CLUSTER: 0 init
9407 10:01:22.559885 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9408 10:01:22.563457 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9409 10:01:22.566332 APU_MBOX 0x190000b0 = 0x10001
9410 10:01:22.569829 APU_MBOX 0x190001b0 = 0x10001
9411 10:01:22.573248 APU_MBOX 0x190005b0 = 0x10001
9412 10:01:22.576392 APU_MBOX 0x190006b0 = 0x10001
9413 10:01:22.579985 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9414 10:01:22.592238 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9415 10:01:22.604632 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9416 10:01:22.611455 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9417 10:01:22.622685 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9418 10:01:22.632189 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9419 10:01:22.635711 CPU_CLUSTER: 0 init finished in 81 msecs
9420 10:01:22.638500 Devices initialized
9421 10:01:22.641898 Show all devs... After init.
9422 10:01:22.642412 Root Device: enabled 1
9423 10:01:22.645499 CPU_CLUSTER: 0: enabled 1
9424 10:01:22.649191 CPU: 00: enabled 1
9425 10:01:22.651851 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9426 10:01:22.655252 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9427 10:01:22.658872 ELOG: NV offset 0x57f000 size 0x1000
9428 10:01:22.665313 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9429 10:01:22.671884 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9430 10:01:22.675566 ELOG: Event(17) added with size 13 at 2023-08-23 10:01:23 UTC
9431 10:01:22.678580 out: cmd=0x121: 03 db 21 01 00 00 00 00
9432 10:01:22.683107 in-header: 03 e2 00 00 2c 00 00 00
9433 10:01:22.696271 in-data: 7d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9434 10:01:22.704037 ELOG: Event(A1) added with size 10 at 2023-08-23 10:01:23 UTC
9435 10:01:22.710003 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9436 10:01:22.716290 ELOG: Event(A0) added with size 9 at 2023-08-23 10:01:23 UTC
9437 10:01:22.719976 elog_add_boot_reason: Logged dev mode boot
9438 10:01:22.723331 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9439 10:01:22.726672 Finalize devices...
9440 10:01:22.727091 Devices finalized
9441 10:01:22.733135 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9442 10:01:22.736232 Writing coreboot table at 0xffe64000
9443 10:01:22.739626 0. 000000000010a000-0000000000113fff: RAMSTAGE
9444 10:01:22.742644 1. 0000000040000000-00000000400fffff: RAM
9445 10:01:22.745889 2. 0000000040100000-000000004032afff: RAMSTAGE
9446 10:01:22.752906 3. 000000004032b000-00000000545fffff: RAM
9447 10:01:22.756430 4. 0000000054600000-000000005465ffff: BL31
9448 10:01:22.759396 5. 0000000054660000-00000000ffe63fff: RAM
9449 10:01:22.762657 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9450 10:01:22.769536 7. 0000000100000000-000000023fffffff: RAM
9451 10:01:22.769624 Passing 5 GPIOs to payload:
9452 10:01:22.776095 NAME | PORT | POLARITY | VALUE
9453 10:01:22.779714 EC in RW | 0x000000aa | low | undefined
9454 10:01:22.785910 EC interrupt | 0x00000005 | low | undefined
9455 10:01:22.789292 TPM interrupt | 0x000000ab | high | undefined
9456 10:01:22.792882 SD card detect | 0x00000011 | high | undefined
9457 10:01:22.799843 speaker enable | 0x00000093 | high | undefined
9458 10:01:22.802903 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9459 10:01:22.806178 in-header: 03 f9 00 00 02 00 00 00
9460 10:01:22.806260 in-data: 02 00
9461 10:01:22.809761 ADC[4]: Raw value=900221 ID=7
9462 10:01:22.812739 ADC[3]: Raw value=213336 ID=1
9463 10:01:22.812820 RAM Code: 0x71
9464 10:01:22.816077 ADC[6]: Raw value=74926 ID=0
9465 10:01:22.819413 ADC[5]: Raw value=211860 ID=1
9466 10:01:22.819494 SKU Code: 0x1
9467 10:01:22.825933 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae81
9468 10:01:22.829511 coreboot table: 964 bytes.
9469 10:01:22.832729 IMD ROOT 0. 0xfffff000 0x00001000
9470 10:01:22.836116 IMD SMALL 1. 0xffffe000 0x00001000
9471 10:01:22.839631 RO MCACHE 2. 0xffffc000 0x00001104
9472 10:01:22.842613 CONSOLE 3. 0xfff7c000 0x00080000
9473 10:01:22.846062 FMAP 4. 0xfff7b000 0x00000452
9474 10:01:22.849451 TIME STAMP 5. 0xfff7a000 0x00000910
9475 10:01:22.852938 VBOOT WORK 6. 0xfff66000 0x00014000
9476 10:01:22.856292 RAMOOPS 7. 0xffe66000 0x00100000
9477 10:01:22.859827 COREBOOT 8. 0xffe64000 0x00002000
9478 10:01:22.859908 IMD small region:
9479 10:01:22.862705 IMD ROOT 0. 0xffffec00 0x00000400
9480 10:01:22.866226 VPD 1. 0xffffeb80 0x0000006c
9481 10:01:22.869583 MMC STATUS 2. 0xffffeb60 0x00000004
9482 10:01:22.876496 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9483 10:01:22.876598 Probing TPM: done!
9484 10:01:22.882811 Connected to device vid:did:rid of 1ae0:0028:00
9485 10:01:22.889490 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9486 10:01:22.893255 Initialized TPM device CR50 revision 0
9487 10:01:22.896646 Checking cr50 for pending updates
9488 10:01:22.902254 Reading cr50 TPM mode
9489 10:01:22.910735 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9490 10:01:22.917614 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9491 10:01:22.957865 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9492 10:01:22.961421 Checking segment from ROM address 0x40100000
9493 10:01:22.964709 Checking segment from ROM address 0x4010001c
9494 10:01:22.971361 Loading segment from ROM address 0x40100000
9495 10:01:22.971444 code (compression=0)
9496 10:01:22.977906 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9497 10:01:22.987729 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9498 10:01:22.987810 it's not compressed!
9499 10:01:22.994770 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9500 10:01:22.997821 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9501 10:01:23.018357 Loading segment from ROM address 0x4010001c
9502 10:01:23.018438 Entry Point 0x80000000
9503 10:01:23.021664 Loaded segments
9504 10:01:23.024815 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9505 10:01:23.031568 Jumping to boot code at 0x80000000(0xffe64000)
9506 10:01:23.038132 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9507 10:01:23.044972 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9508 10:01:23.052838 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9509 10:01:23.056291 Checking segment from ROM address 0x40100000
9510 10:01:23.059353 Checking segment from ROM address 0x4010001c
9511 10:01:23.065811 Loading segment from ROM address 0x40100000
9512 10:01:23.065886 code (compression=1)
9513 10:01:23.072511 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9514 10:01:23.082688 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9515 10:01:23.082799 using LZMA
9516 10:01:23.090878 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9517 10:01:23.097809 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9518 10:01:23.101215 Loading segment from ROM address 0x4010001c
9519 10:01:23.101319 Entry Point 0x54601000
9520 10:01:23.104342 Loaded segments
9521 10:01:23.107506 NOTICE: MT8192 bl31_setup
9522 10:01:23.114553 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9523 10:01:23.118173 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9524 10:01:23.120948 WARNING: region 0:
9525 10:01:23.124374 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 10:01:23.124444 WARNING: region 1:
9527 10:01:23.131215 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9528 10:01:23.134704 WARNING: region 2:
9529 10:01:23.138394 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9530 10:01:23.141294 WARNING: region 3:
9531 10:01:23.144640 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9532 10:01:23.148210 WARNING: region 4:
9533 10:01:23.151234 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9534 10:01:23.154830 WARNING: region 5:
9535 10:01:23.158085 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 10:01:23.161522 WARNING: region 6:
9537 10:01:23.164604 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 10:01:23.164720 WARNING: region 7:
9539 10:01:23.171430 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 10:01:23.178200 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9541 10:01:23.181588 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9542 10:01:23.184946 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9543 10:01:23.191472 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9544 10:01:23.195301 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9545 10:01:23.198147 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9546 10:01:23.204840 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9547 10:01:23.208296 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9548 10:01:23.211643 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9549 10:01:23.218702 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9550 10:01:23.222136 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9551 10:01:23.224980 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9552 10:01:23.232229 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9553 10:01:23.235012 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9554 10:01:23.241959 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9555 10:01:23.245071 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9556 10:01:23.248354 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9557 10:01:23.255405 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9558 10:01:23.258619 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9559 10:01:23.261978 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9560 10:01:23.268926 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9561 10:01:23.271922 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9562 10:01:23.278743 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9563 10:01:23.282464 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9564 10:01:23.285811 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9565 10:01:23.292375 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9566 10:01:23.295532 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9567 10:01:23.298980 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9568 10:01:23.305728 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9569 10:01:23.309479 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9570 10:01:23.315904 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9571 10:01:23.319175 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9572 10:01:23.322619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9573 10:01:23.325899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9574 10:01:23.332480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9575 10:01:23.335863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9576 10:01:23.339373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9577 10:01:23.342379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9578 10:01:23.349029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9579 10:01:23.352640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9580 10:01:23.355880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9581 10:01:23.359386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9582 10:01:23.366016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9583 10:01:23.369424 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9584 10:01:23.372828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9585 10:01:23.376315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9586 10:01:23.382734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9587 10:01:23.386317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9588 10:01:23.389521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9589 10:01:23.396494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9590 10:01:23.399344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9591 10:01:23.402839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9592 10:01:23.409652 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9593 10:01:23.412958 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9594 10:01:23.419528 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9595 10:01:23.423011 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9596 10:01:23.429913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9597 10:01:23.433040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9598 10:01:23.436246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9599 10:01:23.443243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9600 10:01:23.446706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9601 10:01:23.453277 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9602 10:01:23.456756 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9603 10:01:23.463039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9604 10:01:23.466437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9605 10:01:23.470318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9606 10:01:23.476596 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9607 10:01:23.479923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9608 10:01:23.486861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9609 10:01:23.490319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9610 10:01:23.493649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9611 10:01:23.499934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9612 10:01:23.503239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9613 10:01:23.510264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9614 10:01:23.513774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9615 10:01:23.519985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9616 10:01:23.523418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9617 10:01:23.526931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9618 10:01:23.533308 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9619 10:01:23.536841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9620 10:01:23.543647 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9621 10:01:23.546701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9622 10:01:23.553391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9623 10:01:23.556854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9624 10:01:23.560703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9625 10:01:23.567283 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9626 10:01:23.570251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9627 10:01:23.577492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9628 10:01:23.580408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9629 10:01:23.584343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9630 10:01:23.590525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9631 10:01:23.594131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9632 10:01:23.600879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9633 10:01:23.604172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9634 10:01:23.610672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9635 10:01:23.614396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9636 10:01:23.617391 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9637 10:01:23.624477 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9638 10:01:23.627762 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9639 10:01:23.630898 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9640 10:01:23.634240 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9641 10:01:23.640701 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9642 10:01:23.644149 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9643 10:01:23.651173 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9644 10:01:23.654472 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9645 10:01:23.657944 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9646 10:01:23.664632 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9647 10:01:23.667858 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9648 10:01:23.671300 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9649 10:01:23.677767 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9650 10:01:23.681161 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9651 10:01:23.688157 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9652 10:01:23.691147 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9653 10:01:23.695206 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9654 10:01:23.701574 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9655 10:01:23.705168 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9656 10:01:23.707962 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9657 10:01:23.714879 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9658 10:01:23.718417 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9659 10:01:23.721535 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9660 10:01:23.725159 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9661 10:01:23.731500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9662 10:01:23.735177 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9663 10:01:23.738475 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9664 10:01:23.742031 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9665 10:01:23.748582 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9666 10:01:23.751531 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9667 10:01:23.758457 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9668 10:01:23.762007 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9669 10:01:23.765374 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9670 10:01:23.771975 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9671 10:01:23.775490 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9672 10:01:23.782264 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9673 10:01:23.785525 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9674 10:01:23.788830 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9675 10:01:23.795336 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9676 10:01:23.798706 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9677 10:01:23.802324 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9678 10:01:23.808907 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9679 10:01:23.812087 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9680 10:01:23.815655 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9681 10:01:23.822423 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9682 10:01:23.825676 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9683 10:01:23.832266 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9684 10:01:23.836127 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9685 10:01:23.839124 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9686 10:01:23.845573 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9687 10:01:23.849653 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9688 10:01:23.852427 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9689 10:01:23.859120 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9690 10:01:23.862542 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9691 10:01:23.869336 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9692 10:01:23.872430 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9693 10:01:23.876530 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9694 10:01:23.882465 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9695 10:01:23.886105 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9696 10:01:23.892301 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9697 10:01:23.895935 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9698 10:01:23.899285 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9699 10:01:23.905947 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9700 10:01:23.909420 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9701 10:01:23.912822 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9702 10:01:23.920008 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9703 10:01:23.922751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9704 10:01:23.929701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9705 10:01:23.932882 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9706 10:01:23.935981 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9707 10:01:23.942758 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9708 10:01:23.946132 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9709 10:01:23.949312 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9710 10:01:23.956214 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9711 10:01:23.959537 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9712 10:01:23.966435 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9713 10:01:23.969498 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9714 10:01:23.972830 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9715 10:01:23.979612 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9716 10:01:23.983211 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9717 10:01:23.989512 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9718 10:01:23.992759 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9719 10:01:23.996112 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9720 10:01:24.002973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9721 10:01:24.006252 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9722 10:01:24.009403 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9723 10:01:24.016575 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9724 10:01:24.019347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9725 10:01:24.026343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9726 10:01:24.029307 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9727 10:01:24.032677 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9728 10:01:24.039820 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9729 10:01:24.043324 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9730 10:01:24.049511 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9731 10:01:24.052645 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9732 10:01:24.056159 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9733 10:01:24.062604 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9734 10:01:24.066593 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9735 10:01:24.072764 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9736 10:01:24.076352 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9737 10:01:24.082739 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9738 10:01:24.086088 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9739 10:01:24.089497 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9740 10:01:24.096183 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9741 10:01:24.099788 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9742 10:01:24.106515 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9743 10:01:24.109777 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9744 10:01:24.112900 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9745 10:01:24.119790 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9746 10:01:24.123051 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9747 10:01:24.129681 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9748 10:01:24.133041 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9749 10:01:24.136485 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9750 10:01:24.143331 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9751 10:01:24.146510 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9752 10:01:24.152857 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9753 10:01:24.156313 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9754 10:01:24.159948 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9755 10:01:24.166254 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9756 10:01:24.169906 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9757 10:01:24.176683 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9758 10:01:24.179557 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9759 10:01:24.186629 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9760 10:01:24.189840 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9761 10:01:24.192949 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9762 10:01:24.199871 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9763 10:01:24.203200 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9764 10:01:24.209684 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9765 10:01:24.213174 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9766 10:01:24.216401 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9767 10:01:24.223060 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9768 10:01:24.226171 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9769 10:01:24.229637 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9770 10:01:24.236605 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9771 10:01:24.239970 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9772 10:01:24.242786 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9773 10:01:24.246454 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9774 10:01:24.252954 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9775 10:01:24.256445 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9776 10:01:24.259944 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9777 10:01:24.266364 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9778 10:01:24.269613 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9779 10:01:24.273387 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9780 10:01:24.279717 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9781 10:01:24.283485 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9782 10:01:24.289713 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9783 10:01:24.293387 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9784 10:01:24.296826 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9785 10:01:24.303517 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9786 10:01:24.307024 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9787 10:01:24.310172 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9788 10:01:24.316589 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9789 10:01:24.319967 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9790 10:01:24.323190 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9791 10:01:24.330291 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9792 10:01:24.333612 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9793 10:01:24.336783 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9794 10:01:24.343340 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9795 10:01:24.346696 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9796 10:01:24.353187 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9797 10:01:24.356624 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9798 10:01:24.360137 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9799 10:01:24.366484 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9800 10:01:24.369773 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9801 10:01:24.373477 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9802 10:01:24.380065 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9803 10:01:24.383338 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9804 10:01:24.386353 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9805 10:01:24.393084 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9806 10:01:24.396417 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9807 10:01:24.403040 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9808 10:01:24.406456 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9809 10:01:24.409966 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9810 10:01:24.413486 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9811 10:01:24.416410 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9812 10:01:24.423335 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9813 10:01:24.426537 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9814 10:01:24.429660 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9815 10:01:24.433270 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9816 10:01:24.439677 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9817 10:01:24.443316 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9818 10:01:24.446439 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9819 10:01:24.449942 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9820 10:01:24.456833 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9821 10:01:24.459709 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9822 10:01:24.463028 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9823 10:01:24.470072 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9824 10:01:24.473361 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9825 10:01:24.479923 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9826 10:01:24.483442 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9827 10:01:24.486862 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9828 10:01:24.493290 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9829 10:01:24.496736 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9830 10:01:24.503002 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9831 10:01:24.506725 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9832 10:01:24.510120 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9833 10:01:24.516901 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9834 10:01:24.519750 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9835 10:01:24.526675 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9836 10:01:24.529726 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9837 10:01:24.533169 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9838 10:01:24.539616 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9839 10:01:24.543443 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9840 10:01:24.550177 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9841 10:01:24.553341 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9842 10:01:24.556951 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9843 10:01:24.563025 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9844 10:01:24.566769 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9845 10:01:24.573176 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9846 10:01:24.576597 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9847 10:01:24.580334 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9848 10:01:24.586571 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9849 10:01:24.590193 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9850 10:01:24.596470 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9851 10:01:24.600095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9852 10:01:24.603536 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9853 10:01:24.609875 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9854 10:01:24.613254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9855 10:01:24.620009 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9856 10:01:24.623573 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9857 10:01:24.626837 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9858 10:01:24.633597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9859 10:01:24.637183 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9860 10:01:24.643464 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9861 10:01:24.646814 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9862 10:01:24.650186 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9863 10:01:24.657496 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9864 10:01:24.660303 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9865 10:01:24.666926 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9866 10:01:24.670591 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9867 10:01:24.673524 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9868 10:01:24.680233 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9869 10:01:24.683707 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9870 10:01:24.687139 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9871 10:01:24.693747 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9872 10:01:24.697068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9873 10:01:24.704208 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9874 10:01:24.707562 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9875 10:01:24.713903 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9876 10:01:24.717116 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9877 10:01:24.720501 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9878 10:01:24.727018 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9879 10:01:24.730429 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9880 10:01:24.734155 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9881 10:01:24.740807 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9882 10:01:24.744250 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9883 10:01:24.750512 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9884 10:01:24.754155 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9885 10:01:24.757482 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9886 10:01:24.764241 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9887 10:01:24.767256 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9888 10:01:24.774139 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9889 10:01:24.777252 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9890 10:01:24.784372 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9891 10:01:24.787563 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9892 10:01:24.790991 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9893 10:01:24.797333 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9894 10:01:24.800814 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9895 10:01:24.807733 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9896 10:01:24.811123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9897 10:01:24.813950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9898 10:01:24.820952 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9899 10:01:24.824551 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9900 10:01:24.830763 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9901 10:01:24.833868 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9902 10:01:24.837392 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9903 10:01:24.844165 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9904 10:01:24.847506 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9905 10:01:24.854170 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9906 10:01:24.857458 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9907 10:01:24.864429 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9908 10:01:24.867860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9909 10:01:24.871010 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9910 10:01:24.877338 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9911 10:01:24.880944 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9912 10:01:24.887559 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9913 10:01:24.890793 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9914 10:01:24.898272 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9915 10:01:24.901119 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9916 10:01:24.907936 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9917 10:01:24.911006 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9918 10:01:24.914515 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9919 10:01:24.920859 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9920 10:01:24.924165 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9921 10:01:24.930776 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9922 10:01:24.934175 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9923 10:01:24.941249 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9924 10:01:24.944169 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9925 10:01:24.947602 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9926 10:01:24.954191 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9927 10:01:24.957808 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9928 10:01:24.964221 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9929 10:01:24.967629 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9930 10:01:24.971276 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9931 10:01:24.977515 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9932 10:01:24.981119 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9933 10:01:24.987649 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9934 10:01:24.990934 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9935 10:01:24.997698 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9936 10:01:25.000890 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9937 10:01:25.004732 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9938 10:01:25.010874 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9939 10:01:25.014460 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9940 10:01:25.021119 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9941 10:01:25.024087 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9942 10:01:25.027388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9943 10:01:25.034317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9944 10:01:25.038039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9945 10:01:25.044324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9946 10:01:25.047879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9947 10:01:25.054296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9948 10:01:25.058187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9949 10:01:25.064639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9950 10:01:25.067586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9951 10:01:25.074521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9952 10:01:25.078061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9953 10:01:25.084409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9954 10:01:25.087907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9955 10:01:25.091658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9956 10:01:25.097653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9957 10:01:25.101013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9958 10:01:25.107600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9959 10:01:25.111143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9960 10:01:25.117778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9961 10:01:25.121500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9962 10:01:25.128019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9963 10:01:25.131291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9964 10:01:25.137778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9965 10:01:25.141442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9966 10:01:25.147980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9967 10:01:25.151595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9968 10:01:25.157887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9969 10:01:25.161390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9970 10:01:25.168143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9971 10:01:25.171314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9972 10:01:25.178372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9973 10:01:25.181141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9974 10:01:25.184690 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9975 10:01:25.188108 INFO: [APUAPC] vio 0
9976 10:01:25.194552 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9977 10:01:25.197992 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9978 10:01:25.201709 INFO: [APUAPC] D0_APC_0: 0x400510
9979 10:01:25.204849 INFO: [APUAPC] D0_APC_1: 0x0
9980 10:01:25.208249 INFO: [APUAPC] D0_APC_2: 0x1540
9981 10:01:25.211308 INFO: [APUAPC] D0_APC_3: 0x0
9982 10:01:25.214588 INFO: [APUAPC] D1_APC_0: 0xffffffff
9983 10:01:25.217937 INFO: [APUAPC] D1_APC_1: 0xffffffff
9984 10:01:25.221185 INFO: [APUAPC] D1_APC_2: 0x3fffff
9985 10:01:25.224661 INFO: [APUAPC] D1_APC_3: 0x0
9986 10:01:25.228178 INFO: [APUAPC] D2_APC_0: 0xffffffff
9987 10:01:25.231121 INFO: [APUAPC] D2_APC_1: 0xffffffff
9988 10:01:25.235181 INFO: [APUAPC] D2_APC_2: 0x3fffff
9989 10:01:25.235250 INFO: [APUAPC] D2_APC_3: 0x0
9990 10:01:25.237901 INFO: [APUAPC] D3_APC_0: 0xffffffff
9991 10:01:25.241295 INFO: [APUAPC] D3_APC_1: 0xffffffff
9992 10:01:25.245093 INFO: [APUAPC] D3_APC_2: 0x3fffff
9993 10:01:25.248206 INFO: [APUAPC] D3_APC_3: 0x0
9994 10:01:25.251430 INFO: [APUAPC] D4_APC_0: 0xffffffff
9995 10:01:25.254751 INFO: [APUAPC] D4_APC_1: 0xffffffff
9996 10:01:25.258045 INFO: [APUAPC] D4_APC_2: 0x3fffff
9997 10:01:25.261541 INFO: [APUAPC] D4_APC_3: 0x0
9998 10:01:25.264914 INFO: [APUAPC] D5_APC_0: 0xffffffff
9999 10:01:25.267952 INFO: [APUAPC] D5_APC_1: 0xffffffff
10000 10:01:25.271325 INFO: [APUAPC] D5_APC_2: 0x3fffff
10001 10:01:25.274981 INFO: [APUAPC] D5_APC_3: 0x0
10002 10:01:25.277991 INFO: [APUAPC] D6_APC_0: 0xffffffff
10003 10:01:25.281419 INFO: [APUAPC] D6_APC_1: 0xffffffff
10004 10:01:25.284822 INFO: [APUAPC] D6_APC_2: 0x3fffff
10005 10:01:25.288459 INFO: [APUAPC] D6_APC_3: 0x0
10006 10:01:25.291864 INFO: [APUAPC] D7_APC_0: 0xffffffff
10007 10:01:25.294795 INFO: [APUAPC] D7_APC_1: 0xffffffff
10008 10:01:25.298404 INFO: [APUAPC] D7_APC_2: 0x3fffff
10009 10:01:25.301837 INFO: [APUAPC] D7_APC_3: 0x0
10010 10:01:25.304758 INFO: [APUAPC] D8_APC_0: 0xffffffff
10011 10:01:25.308323 INFO: [APUAPC] D8_APC_1: 0xffffffff
10012 10:01:25.311621 INFO: [APUAPC] D8_APC_2: 0x3fffff
10013 10:01:25.315195 INFO: [APUAPC] D8_APC_3: 0x0
10014 10:01:25.318085 INFO: [APUAPC] D9_APC_0: 0xffffffff
10015 10:01:25.321761 INFO: [APUAPC] D9_APC_1: 0xffffffff
10016 10:01:25.325259 INFO: [APUAPC] D9_APC_2: 0x3fffff
10017 10:01:25.328773 INFO: [APUAPC] D9_APC_3: 0x0
10018 10:01:25.331532 INFO: [APUAPC] D10_APC_0: 0xffffffff
10019 10:01:25.335171 INFO: [APUAPC] D10_APC_1: 0xffffffff
10020 10:01:25.338261 INFO: [APUAPC] D10_APC_2: 0x3fffff
10021 10:01:25.341692 INFO: [APUAPC] D10_APC_3: 0x0
10022 10:01:25.345027 INFO: [APUAPC] D11_APC_0: 0xffffffff
10023 10:01:25.348100 INFO: [APUAPC] D11_APC_1: 0xffffffff
10024 10:01:25.351502 INFO: [APUAPC] D11_APC_2: 0x3fffff
10025 10:01:25.354900 INFO: [APUAPC] D11_APC_3: 0x0
10026 10:01:25.358572 INFO: [APUAPC] D12_APC_0: 0xffffffff
10027 10:01:25.361747 INFO: [APUAPC] D12_APC_1: 0xffffffff
10028 10:01:25.365050 INFO: [APUAPC] D12_APC_2: 0x3fffff
10029 10:01:25.369067 INFO: [APUAPC] D12_APC_3: 0x0
10030 10:01:25.371916 INFO: [APUAPC] D13_APC_0: 0xffffffff
10031 10:01:25.375198 INFO: [APUAPC] D13_APC_1: 0xffffffff
10032 10:01:25.378453 INFO: [APUAPC] D13_APC_2: 0x3fffff
10033 10:01:25.381670 INFO: [APUAPC] D13_APC_3: 0x0
10034 10:01:25.385330 INFO: [APUAPC] D14_APC_0: 0xffffffff
10035 10:01:25.388289 INFO: [APUAPC] D14_APC_1: 0xffffffff
10036 10:01:25.391927 INFO: [APUAPC] D14_APC_2: 0x3fffff
10037 10:01:25.395429 INFO: [APUAPC] D14_APC_3: 0x0
10038 10:01:25.398910 INFO: [APUAPC] D15_APC_0: 0xffffffff
10039 10:01:25.401827 INFO: [APUAPC] D15_APC_1: 0xffffffff
10040 10:01:25.405186 INFO: [APUAPC] D15_APC_2: 0x3fffff
10041 10:01:25.408618 INFO: [APUAPC] D15_APC_3: 0x0
10042 10:01:25.408697 INFO: [APUAPC] APC_CON: 0x4
10043 10:01:25.412290 INFO: [NOCDAPC] D0_APC_0: 0x0
10044 10:01:25.415452 INFO: [NOCDAPC] D0_APC_1: 0x0
10045 10:01:25.418458 INFO: [NOCDAPC] D1_APC_0: 0x0
10046 10:01:25.421759 INFO: [NOCDAPC] D1_APC_1: 0xfff
10047 10:01:25.425177 INFO: [NOCDAPC] D2_APC_0: 0x0
10048 10:01:25.428432 INFO: [NOCDAPC] D2_APC_1: 0xfff
10049 10:01:25.431723 INFO: [NOCDAPC] D3_APC_0: 0x0
10050 10:01:25.435123 INFO: [NOCDAPC] D3_APC_1: 0xfff
10051 10:01:25.438639 INFO: [NOCDAPC] D4_APC_0: 0x0
10052 10:01:25.438707 INFO: [NOCDAPC] D4_APC_1: 0xfff
10053 10:01:25.441640 INFO: [NOCDAPC] D5_APC_0: 0x0
10054 10:01:25.445196 INFO: [NOCDAPC] D5_APC_1: 0xfff
10055 10:01:25.448376 INFO: [NOCDAPC] D6_APC_0: 0x0
10056 10:01:25.451869 INFO: [NOCDAPC] D6_APC_1: 0xfff
10057 10:01:25.455628 INFO: [NOCDAPC] D7_APC_0: 0x0
10058 10:01:25.458493 INFO: [NOCDAPC] D7_APC_1: 0xfff
10059 10:01:25.461744 INFO: [NOCDAPC] D8_APC_0: 0x0
10060 10:01:25.465414 INFO: [NOCDAPC] D8_APC_1: 0xfff
10061 10:01:25.468245 INFO: [NOCDAPC] D9_APC_0: 0x0
10062 10:01:25.471713 INFO: [NOCDAPC] D9_APC_1: 0xfff
10063 10:01:25.471790 INFO: [NOCDAPC] D10_APC_0: 0x0
10064 10:01:25.475230 INFO: [NOCDAPC] D10_APC_1: 0xfff
10065 10:01:25.478796 INFO: [NOCDAPC] D11_APC_0: 0x0
10066 10:01:25.482115 INFO: [NOCDAPC] D11_APC_1: 0xfff
10067 10:01:25.485338 INFO: [NOCDAPC] D12_APC_0: 0x0
10068 10:01:25.488673 INFO: [NOCDAPC] D12_APC_1: 0xfff
10069 10:01:25.491818 INFO: [NOCDAPC] D13_APC_0: 0x0
10070 10:01:25.495230 INFO: [NOCDAPC] D13_APC_1: 0xfff
10071 10:01:25.498494 INFO: [NOCDAPC] D14_APC_0: 0x0
10072 10:01:25.502133 INFO: [NOCDAPC] D14_APC_1: 0xfff
10073 10:01:25.505892 INFO: [NOCDAPC] D15_APC_0: 0x0
10074 10:01:25.508642 INFO: [NOCDAPC] D15_APC_1: 0xfff
10075 10:01:25.508767 INFO: [NOCDAPC] APC_CON: 0x4
10076 10:01:25.515691 INFO: [APUAPC] set_apusys_apc done
10077 10:01:25.515767 INFO: [DEVAPC] devapc_init done
10078 10:01:25.521877 INFO: GICv3 without legacy support detected.
10079 10:01:25.525318 INFO: ARM GICv3 driver initialized in EL3
10080 10:01:25.528703 INFO: Maximum SPI INTID supported: 639
10081 10:01:25.532114 INFO: BL31: Initializing runtime services
10082 10:01:25.538799 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10083 10:01:25.542407 INFO: SPM: enable CPC mode
10084 10:01:25.545450 INFO: mcdi ready for mcusys-off-idle and system suspend
10085 10:01:25.551874 INFO: BL31: Preparing for EL3 exit to normal world
10086 10:01:25.555366 INFO: Entry point address = 0x80000000
10087 10:01:25.555439 INFO: SPSR = 0x8
10088 10:01:25.562408
10089 10:01:25.562480
10090 10:01:25.562556
10091 10:01:25.565613 Starting depthcharge on Spherion...
10092 10:01:25.565694
10093 10:01:25.565756 Wipe memory regions:
10094 10:01:25.565813
10095 10:01:25.566613 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10096 10:01:25.566750 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10097 10:01:25.567154 Setting prompt string to ['asurada:']
10098 10:01:25.567274 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10099 10:01:25.568951 [0x00000040000000, 0x00000054600000)
10100 10:01:25.691282
10101 10:01:25.691433 [0x00000054660000, 0x00000080000000)
10102 10:01:25.952244
10103 10:01:25.952396 [0x000000821a7280, 0x000000ffe64000)
10104 10:01:26.696375
10105 10:01:26.696513 [0x00000100000000, 0x00000240000000)
10106 10:01:28.587477
10107 10:01:28.590624 Initializing XHCI USB controller at 0x11200000.
10108 10:01:29.628240
10109 10:01:29.631558 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10110 10:01:29.631678
10111 10:01:29.631773
10112 10:01:29.631864
10113 10:01:29.632177 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10115 10:01:29.732585 asurada: tftpboot 192.168.201.1 11336442/tftp-deploy-pqke0388/kernel/image.itb 11336442/tftp-deploy-pqke0388/kernel/cmdline
10116 10:01:29.732755 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10117 10:01:29.732898 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10118 10:01:29.737512 tftpboot 192.168.201.1 11336442/tftp-deploy-pqke0388/kernel/image.ittp-deploy-pqke0388/kernel/cmdline
10119 10:01:29.737594
10120 10:01:29.737659 Waiting for link
10121 10:01:29.897644
10122 10:01:29.897767 R8152: Initializing
10123 10:01:29.897842
10124 10:01:29.901129 Version 6 (ocp_data = 5c30)
10125 10:01:29.901230
10126 10:01:29.904028 R8152: Done initializing
10127 10:01:29.904125
10128 10:01:29.904218 Adding net device
10129 10:01:31.948774
10130 10:01:31.949366 done.
10131 10:01:31.949821
10132 10:01:31.950264 MAC: 00:24:32:30:78:52
10133 10:01:31.950686
10134 10:01:31.951822 Sending DHCP discover... done.
10135 10:01:31.952368
10136 10:01:36.179232 Waiting for reply... done.
10137 10:01:36.179885
10138 10:01:36.180535 Sending DHCP request... done.
10139 10:01:36.182569
10140 10:01:36.187225 Waiting for reply... done.
10141 10:01:36.187670
10142 10:01:36.188004 My ip is 192.168.201.14
10143 10:01:36.188381
10144 10:01:36.190812 The DHCP server ip is 192.168.201.1
10145 10:01:36.191229
10146 10:01:36.197374 TFTP server IP predefined by user: 192.168.201.1
10147 10:01:36.197939
10148 10:01:36.200975 Bootfile predefined by user: 11336442/tftp-deploy-pqke0388/kernel/image.itb
10149 10:01:36.203974
10150 10:01:36.204421 Sending tftp read request... done.
10151 10:01:36.205084
10152 10:01:36.214419 Waiting for the transfer...
10153 10:01:36.214756
10154 10:01:36.759382 00000000 ################################################################
10155 10:01:36.759522
10156 10:01:37.327285 00080000 ################################################################
10157 10:01:37.327429
10158 10:01:37.869002 00100000 ################################################################
10159 10:01:37.869140
10160 10:01:38.407895 00180000 ################################################################
10161 10:01:38.408033
10162 10:01:38.946677 00200000 ################################################################
10163 10:01:38.946843
10164 10:01:39.479995 00280000 ################################################################
10165 10:01:39.480126
10166 10:01:40.006769 00300000 ################################################################
10167 10:01:40.006947
10168 10:01:40.619679 00380000 ################################################################
10169 10:01:40.619828
10170 10:01:41.247799 00400000 ################################################################
10171 10:01:41.247937
10172 10:01:41.815496 00480000 ################################################################
10173 10:01:41.815632
10174 10:01:42.361004 00500000 ################################################################
10175 10:01:42.361143
10176 10:01:42.918287 00580000 ################################################################
10177 10:01:42.918450
10178 10:01:43.475573 00600000 ################################################################
10179 10:01:43.475734
10180 10:01:44.028673 00680000 ################################################################
10181 10:01:44.028866
10182 10:01:44.581005 00700000 ################################################################
10183 10:01:44.581171
10184 10:01:45.120806 00780000 ################################################################
10185 10:01:45.120944
10186 10:01:45.660580 00800000 ################################################################
10187 10:01:45.660760
10188 10:01:46.189089 00880000 ################################################################
10189 10:01:46.189226
10190 10:01:46.718729 00900000 ################################################################
10191 10:01:46.718891
10192 10:01:47.248246 00980000 ################################################################
10193 10:01:47.248420
10194 10:01:47.781930 00a00000 ################################################################
10195 10:01:47.782083
10196 10:01:48.301260 00a80000 ################################################################
10197 10:01:48.301412
10198 10:01:48.819967 00b00000 ################################################################
10199 10:01:48.820110
10200 10:01:49.341075 00b80000 ################################################################
10201 10:01:49.341222
10202 10:01:49.862322 00c00000 ################################################################
10203 10:01:49.862463
10204 10:01:50.391894 00c80000 ################################################################
10205 10:01:50.392042
10206 10:01:50.918941 00d00000 ################################################################
10207 10:01:50.919083
10208 10:01:51.443769 00d80000 ################################################################
10209 10:01:51.443912
10210 10:01:51.980596 00e00000 ################################################################
10211 10:01:51.980783
10212 10:01:52.501851 00e80000 ################################################################
10213 10:01:52.501990
10214 10:01:53.032624 00f00000 ################################################################
10215 10:01:53.032785
10216 10:01:53.565818 00f80000 ################################################################
10217 10:01:53.565958
10218 10:01:54.092446 01000000 ################################################################
10219 10:01:54.092576
10220 10:01:54.612037 01080000 ################################################################
10221 10:01:54.612213
10222 10:01:55.146312 01100000 ################################################################
10223 10:01:55.146455
10224 10:01:55.674182 01180000 ################################################################
10225 10:01:55.674326
10226 10:01:56.204811 01200000 ################################################################
10227 10:01:56.204952
10228 10:01:56.726234 01280000 ################################################################
10229 10:01:56.726409
10230 10:01:57.244203 01300000 ################################################################
10231 10:01:57.244343
10232 10:01:57.773114 01380000 ################################################################
10233 10:01:57.773258
10234 10:01:58.306598 01400000 ################################################################
10235 10:01:58.306737
10236 10:01:58.829950 01480000 ################################################################
10237 10:01:58.830083
10238 10:01:59.351146 01500000 ################################################################
10239 10:01:59.351280
10240 10:01:59.872190 01580000 ################################################################
10241 10:01:59.872354
10242 10:02:00.394660 01600000 ################################################################
10243 10:02:00.394794
10244 10:02:00.919719 01680000 ################################################################
10245 10:02:00.919879
10246 10:02:01.449071 01700000 ################################################################
10247 10:02:01.449204
10248 10:02:01.977378 01780000 ################################################################
10249 10:02:01.977510
10250 10:02:02.509786 01800000 ################################################################
10251 10:02:02.509922
10252 10:02:03.150184 01880000 ################################################################
10253 10:02:03.150701
10254 10:02:03.839122 01900000 ################################################################
10255 10:02:03.839626
10256 10:02:04.566177 01980000 ################################################################
10257 10:02:04.566666
10258 10:02:05.286661 01a00000 ################################################################
10259 10:02:05.287143
10260 10:02:05.993120 01a80000 ################################################################
10261 10:02:05.993725
10262 10:02:06.709140 01b00000 ################################################################
10263 10:02:06.709685
10264 10:02:06.732083 01b80000 ### done.
10265 10:02:06.732607
10266 10:02:06.735740 The bootfile was 28854074 bytes long.
10267 10:02:06.736333
10268 10:02:06.738888 Sending tftp read request... done.
10269 10:02:06.739343
10270 10:02:06.742574 Waiting for the transfer...
10271 10:02:06.745787
10272 10:02:06.746260 00000000 # done.
10273 10:02:06.746746
10274 10:02:06.752290 Command line loaded dynamically from TFTP file: 11336442/tftp-deploy-pqke0388/kernel/cmdline
10275 10:02:06.752876
10276 10:02:06.775630 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11336442/extract-nfsrootfs-f56f79f8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10277 10:02:06.776212
10278 10:02:06.776829 Loading FIT.
10279 10:02:06.777286
10280 10:02:06.779273 Image ramdisk-1 has 17767501 bytes.
10281 10:02:06.779745
10282 10:02:06.782197 Image fdt-1 has 47278 bytes.
10283 10:02:06.782671
10284 10:02:06.785693 Image kernel-1 has 11037260 bytes.
10285 10:02:06.786167
10286 10:02:06.795649 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10287 10:02:06.796373
10288 10:02:06.812372 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10289 10:02:06.813017
10290 10:02:06.815832 Choosing best match conf-1 for compat google,spherion-rev2.
10291 10:02:06.821616
10292 10:02:06.826306 Connected to device vid:did:rid of 1ae0:0028:00
10293 10:02:06.832966
10294 10:02:06.836217 tpm_get_response: command 0x17b, return code 0x0
10295 10:02:06.836634
10296 10:02:06.840035 ec_init: CrosEC protocol v3 supported (256, 248)
10297 10:02:06.844729
10298 10:02:06.847779 tpm_cleanup: add release locality here.
10299 10:02:06.848267
10300 10:02:06.848605 Shutting down all USB controllers.
10301 10:02:06.851772
10302 10:02:06.852278 Removing current net device
10303 10:02:06.852615
10304 10:02:06.858239 Exiting depthcharge with code 4 at timestamp: 70678197
10305 10:02:06.858774
10306 10:02:06.861514 LZMA decompressing kernel-1 to 0x821a6718
10307 10:02:06.861927
10308 10:02:06.864903 LZMA decompressing kernel-1 to 0x40000000
10309 10:02:08.252148
10310 10:02:08.252742 jumping to kernel
10311 10:02:08.254201 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10312 10:02:08.254713 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10313 10:02:08.255120 Setting prompt string to ['Linux version [0-9]']
10314 10:02:08.255499 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10315 10:02:08.255866 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10316 10:02:08.335302
10317 10:02:08.338682 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10318 10:02:08.342263 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10319 10:02:08.342778 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10320 10:02:08.343174 Setting prompt string to []
10321 10:02:08.343600 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10322 10:02:08.344004 Using line separator: #'\n'#
10323 10:02:08.344341 No login prompt set.
10324 10:02:08.344888 Parsing kernel messages
10325 10:02:08.345243 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10326 10:02:08.345810 [login-action] Waiting for messages, (timeout 00:03:42)
10327 10:02:08.362218 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j18697-arm64-gcc-10-defconfig-arm64-chromebook-vvl9c) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 23 09:52:58 UTC 2023
10328 10:02:08.365144 [ 0.000000] random: crng init done
10329 10:02:08.368519 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10330 10:02:08.372121 [ 0.000000] efi: UEFI not found.
10331 10:02:08.382479 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10332 10:02:08.388540 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10333 10:02:08.398441 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10334 10:02:08.408354 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10335 10:02:08.415071 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10336 10:02:08.418879 [ 0.000000] printk: bootconsole [mtk8250] enabled
10337 10:02:08.427063 [ 0.000000] NUMA: No NUMA configuration found
10338 10:02:08.433660 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10339 10:02:08.440022 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10340 10:02:08.440549 [ 0.000000] Zone ranges:
10341 10:02:08.446603 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10342 10:02:08.450302 [ 0.000000] DMA32 empty
10343 10:02:08.457082 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10344 10:02:08.460180 [ 0.000000] Movable zone start for each node
10345 10:02:08.463728 [ 0.000000] Early memory node ranges
10346 10:02:08.470621 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10347 10:02:08.476642 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10348 10:02:08.483425 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10349 10:02:08.490332 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10350 10:02:08.493646 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10351 10:02:08.503209 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10352 10:02:08.559737 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10353 10:02:08.566427 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10354 10:02:08.573258 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10355 10:02:08.575848 [ 0.000000] psci: probing for conduit method from DT.
10356 10:02:08.582681 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10357 10:02:08.586050 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10358 10:02:08.592476 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10359 10:02:08.596060 [ 0.000000] psci: SMC Calling Convention v1.2
10360 10:02:08.603119 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10361 10:02:08.605893 [ 0.000000] Detected VIPT I-cache on CPU0
10362 10:02:08.612422 [ 0.000000] CPU features: detected: GIC system register CPU interface
10363 10:02:08.619495 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10364 10:02:08.626331 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10365 10:02:08.633066 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10366 10:02:08.639531 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10367 10:02:08.646385 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10368 10:02:08.652918 [ 0.000000] alternatives: applying boot alternatives
10369 10:02:08.656085 [ 0.000000] Fallback order for Node 0: 0
10370 10:02:08.663183 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10371 10:02:08.666357 [ 0.000000] Policy zone: Normal
10372 10:02:08.689401 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11336442/extract-nfsrootfs-f56f79f8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10373 10:02:08.699985 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10374 10:02:08.711961 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10375 10:02:08.722537 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10376 10:02:08.728985 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10377 10:02:08.732194 <6>[ 0.000000] software IO TLB: area num 8.
10378 10:02:08.788556 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10379 10:02:08.938265 <6>[ 0.000000] Memory: 7952204K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 400564K reserved, 32768K cma-reserved)
10380 10:02:08.944583 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10381 10:02:08.951427 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10382 10:02:08.954822 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10383 10:02:08.961719 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10384 10:02:08.968581 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10385 10:02:08.971733 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10386 10:02:08.981649 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10387 10:02:08.988219 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10388 10:02:08.991674 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10389 10:02:08.999274 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10390 10:02:09.002665 <6>[ 0.000000] GICv3: 608 SPIs implemented
10391 10:02:09.009460 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10392 10:02:09.012599 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10393 10:02:09.015856 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10394 10:02:09.022838 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10395 10:02:09.036404 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10396 10:02:09.049389 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10397 10:02:09.056117 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10398 10:02:09.064521 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10399 10:02:09.077728 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10400 10:02:09.084620 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10401 10:02:09.091188 <6>[ 0.009236] Console: colour dummy device 80x25
10402 10:02:09.100860 <6>[ 0.013992] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10403 10:02:09.108056 <6>[ 0.024501] pid_max: default: 32768 minimum: 301
10404 10:02:09.111373 <6>[ 0.029372] LSM: Security Framework initializing
10405 10:02:09.118228 <6>[ 0.034310] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10406 10:02:09.127770 <6>[ 0.042122] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10407 10:02:09.134573 <6>[ 0.051607] cblist_init_generic: Setting adjustable number of callback queues.
10408 10:02:09.141326 <6>[ 0.059054] cblist_init_generic: Setting shift to 3 and lim to 1.
10409 10:02:09.151198 <6>[ 0.065432] cblist_init_generic: Setting adjustable number of callback queues.
10410 10:02:09.154753 <6>[ 0.072858] cblist_init_generic: Setting shift to 3 and lim to 1.
10411 10:02:09.160996 <6>[ 0.079258] rcu: Hierarchical SRCU implementation.
10412 10:02:09.168095 <6>[ 0.084272] rcu: Max phase no-delay instances is 1000.
10413 10:02:09.174371 <6>[ 0.091334] EFI services will not be available.
10414 10:02:09.177468 <6>[ 0.096309] smp: Bringing up secondary CPUs ...
10415 10:02:09.185870 <6>[ 0.101363] Detected VIPT I-cache on CPU1
10416 10:02:09.192845 <6>[ 0.101433] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10417 10:02:09.199233 <6>[ 0.101464] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10418 10:02:09.202768 <6>[ 0.101802] Detected VIPT I-cache on CPU2
10419 10:02:09.208828 <6>[ 0.101856] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10420 10:02:09.215954 <6>[ 0.101875] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10421 10:02:09.222713 <6>[ 0.102133] Detected VIPT I-cache on CPU3
10422 10:02:09.229695 <6>[ 0.102179] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10423 10:02:09.236372 <6>[ 0.102193] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10424 10:02:09.238898 <6>[ 0.102499] CPU features: detected: Spectre-v4
10425 10:02:09.245972 <6>[ 0.102505] CPU features: detected: Spectre-BHB
10426 10:02:09.248965 <6>[ 0.102510] Detected PIPT I-cache on CPU4
10427 10:02:09.255778 <6>[ 0.102566] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10428 10:02:09.262151 <6>[ 0.102583] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10429 10:02:09.265411 <6>[ 0.102878] Detected PIPT I-cache on CPU5
10430 10:02:09.275670 <6>[ 0.102940] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10431 10:02:09.282094 <6>[ 0.102957] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10432 10:02:09.285557 <6>[ 0.103241] Detected PIPT I-cache on CPU6
10433 10:02:09.292606 <6>[ 0.103306] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10434 10:02:09.298843 <6>[ 0.103323] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10435 10:02:09.302636 <6>[ 0.103620] Detected PIPT I-cache on CPU7
10436 10:02:09.312510 <6>[ 0.103685] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10437 10:02:09.319264 <6>[ 0.103702] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10438 10:02:09.322589 <6>[ 0.103750] smp: Brought up 1 node, 8 CPUs
10439 10:02:09.325479 <6>[ 0.245153] SMP: Total of 8 processors activated.
10440 10:02:09.331977 <6>[ 0.250074] CPU features: detected: 32-bit EL0 Support
10441 10:02:09.342241 <6>[ 0.255470] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10442 10:02:09.348994 <6>[ 0.264270] CPU features: detected: Common not Private translations
10443 10:02:09.352249 <6>[ 0.270746] CPU features: detected: CRC32 instructions
10444 10:02:09.358913 <6>[ 0.276130] CPU features: detected: RCpc load-acquire (LDAPR)
10445 10:02:09.365258 <6>[ 0.282127] CPU features: detected: LSE atomic instructions
10446 10:02:09.371978 <6>[ 0.287909] CPU features: detected: Privileged Access Never
10447 10:02:09.375253 <6>[ 0.293688] CPU features: detected: RAS Extension Support
10448 10:02:09.382283 <6>[ 0.299332] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10449 10:02:09.388795 <6>[ 0.306551] CPU: All CPU(s) started at EL2
10450 10:02:09.392290 <6>[ 0.310894] alternatives: applying system-wide alternatives
10451 10:02:09.403678 <6>[ 0.321610] devtmpfs: initialized
10452 10:02:09.415876 <6>[ 0.330602] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10453 10:02:09.425875 <6>[ 0.340561] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10454 10:02:09.432100 <6>[ 0.348571] pinctrl core: initialized pinctrl subsystem
10455 10:02:09.435628 <6>[ 0.355248] DMI not present or invalid.
10456 10:02:09.442012 <6>[ 0.359660] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10457 10:02:09.452470 <6>[ 0.366458] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10458 10:02:09.459117 <6>[ 0.374042] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10459 10:02:09.468783 <6>[ 0.382255] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10460 10:02:09.472478 <6>[ 0.390497] audit: initializing netlink subsys (disabled)
10461 10:02:09.481988 <5>[ 0.396191] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10462 10:02:09.485636 <6>[ 0.396912] thermal_sys: Registered thermal governor 'step_wise'
10463 10:02:09.495506 <6>[ 0.404158] thermal_sys: Registered thermal governor 'power_allocator'
10464 10:02:09.499038 <6>[ 0.410415] cpuidle: using governor menu
10465 10:02:09.502489 <6>[ 0.421376] NET: Registered PF_QIPCRTR protocol family
10466 10:02:09.512175 <6>[ 0.426864] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10467 10:02:09.515230 <6>[ 0.433974] ASID allocator initialised with 32768 entries
10468 10:02:09.522196 <6>[ 0.440555] Serial: AMBA PL011 UART driver
10469 10:02:09.531269 <4>[ 0.449361] Trying to register duplicate clock ID: 134
10470 10:02:09.585613 <6>[ 0.506862] KASLR enabled
10471 10:02:09.599881 <6>[ 0.514605] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10472 10:02:09.606180 <6>[ 0.521620] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10473 10:02:09.613195 <6>[ 0.528109] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10474 10:02:09.619627 <6>[ 0.535117] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10475 10:02:09.626607 <6>[ 0.541602] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10476 10:02:09.633754 <6>[ 0.548604] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10477 10:02:09.640007 <6>[ 0.555090] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10478 10:02:09.646421 <6>[ 0.562094] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10479 10:02:09.649953 <6>[ 0.569683] ACPI: Interpreter disabled.
10480 10:02:09.657818 <6>[ 0.576088] iommu: Default domain type: Translated
10481 10:02:09.665075 <6>[ 0.581201] iommu: DMA domain TLB invalidation policy: strict mode
10482 10:02:09.667903 <5>[ 0.587857] SCSI subsystem initialized
10483 10:02:09.674551 <6>[ 0.592018] usbcore: registered new interface driver usbfs
10484 10:02:09.681356 <6>[ 0.597749] usbcore: registered new interface driver hub
10485 10:02:09.684609 <6>[ 0.603297] usbcore: registered new device driver usb
10486 10:02:09.691168 <6>[ 0.609408] pps_core: LinuxPPS API ver. 1 registered
10487 10:02:09.701421 <6>[ 0.614601] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10488 10:02:09.704202 <6>[ 0.623944] PTP clock support registered
10489 10:02:09.707880 <6>[ 0.628181] EDAC MC: Ver: 3.0.0
10490 10:02:09.715543 <6>[ 0.633344] FPGA manager framework
10491 10:02:09.718722 <6>[ 0.637028] Advanced Linux Sound Architecture Driver Initialized.
10492 10:02:09.722339 <6>[ 0.643789] vgaarb: loaded
10493 10:02:09.728969 <6>[ 0.646963] clocksource: Switched to clocksource arch_sys_counter
10494 10:02:09.735394 <5>[ 0.653411] VFS: Disk quotas dquot_6.6.0
10495 10:02:09.742127 <6>[ 0.657596] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10496 10:02:09.745701 <6>[ 0.664788] pnp: PnP ACPI: disabled
10497 10:02:09.753742 <6>[ 0.671512] NET: Registered PF_INET protocol family
10498 10:02:09.760837 <6>[ 0.677118] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10499 10:02:09.774915 <6>[ 0.689439] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10500 10:02:09.784370 <6>[ 0.698252] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10501 10:02:09.791207 <6>[ 0.706222] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10502 10:02:09.798429 <6>[ 0.714918] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10503 10:02:09.809524 <6>[ 0.724651] TCP: Hash tables configured (established 65536 bind 65536)
10504 10:02:09.816634 <6>[ 0.731509] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10505 10:02:09.823474 <6>[ 0.738707] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10506 10:02:09.830087 <6>[ 0.746406] NET: Registered PF_UNIX/PF_LOCAL protocol family
10507 10:02:09.836831 <6>[ 0.752507] RPC: Registered named UNIX socket transport module.
10508 10:02:09.839908 <6>[ 0.758662] RPC: Registered udp transport module.
10509 10:02:09.846802 <6>[ 0.763595] RPC: Registered tcp transport module.
10510 10:02:09.853493 <6>[ 0.768526] RPC: Registered tcp NFSv4.1 backchannel transport module.
10511 10:02:09.856423 <6>[ 0.775195] PCI: CLS 0 bytes, default 64
10512 10:02:09.860432 <6>[ 0.779611] Unpacking initramfs...
10513 10:02:09.884057 <6>[ 0.799095] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10514 10:02:09.894297 <6>[ 0.807740] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10515 10:02:09.897726 <6>[ 0.816585] kvm [1]: IPA Size Limit: 40 bits
10516 10:02:09.904396 <6>[ 0.821110] kvm [1]: GICv3: no GICV resource entry
10517 10:02:09.907934 <6>[ 0.826130] kvm [1]: disabling GICv2 emulation
10518 10:02:09.914330 <6>[ 0.830821] kvm [1]: GIC system register CPU interface enabled
10519 10:02:09.917320 <6>[ 0.836988] kvm [1]: vgic interrupt IRQ18
10520 10:02:09.924662 <6>[ 0.841350] kvm [1]: VHE mode initialized successfully
10521 10:02:09.931175 <5>[ 0.847740] Initialise system trusted keyrings
10522 10:02:09.937567 <6>[ 0.852557] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10523 10:02:09.944774 <6>[ 0.862607] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10524 10:02:09.951391 <5>[ 0.868949] NFS: Registering the id_resolver key type
10525 10:02:09.954271 <5>[ 0.874247] Key type id_resolver registered
10526 10:02:09.960913 <5>[ 0.878661] Key type id_legacy registered
10527 10:02:09.968013 <6>[ 0.882944] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10528 10:02:09.974786 <6>[ 0.889867] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10529 10:02:09.980929 <6>[ 0.897588] 9p: Installing v9fs 9p2000 file system support
10530 10:02:10.016443 <5>[ 0.934777] Key type asymmetric registered
10531 10:02:10.019766 <5>[ 0.939109] Asymmetric key parser 'x509' registered
10532 10:02:10.030315 <6>[ 0.944241] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10533 10:02:10.033638 <6>[ 0.951861] io scheduler mq-deadline registered
10534 10:02:10.036924 <6>[ 0.956636] io scheduler kyber registered
10535 10:02:10.052831 <6>[ 0.973551] EINJ: ACPI disabled.
10536 10:02:10.087641 <4>[ 0.999145] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10537 10:02:10.097538 <4>[ 1.009774] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 10:02:10.112186 <6>[ 1.030354] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10539 10:02:10.120258 <6>[ 1.038258] printk: console [ttyS0] disabled
10540 10:02:10.148076 <6>[ 1.062908] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10541 10:02:10.154730 <6>[ 1.072378] printk: console [ttyS0] enabled
10542 10:02:10.157864 <6>[ 1.072378] printk: console [ttyS0] enabled
10543 10:02:10.164763 <6>[ 1.081277] printk: bootconsole [mtk8250] disabled
10544 10:02:10.168576 <6>[ 1.081277] printk: bootconsole [mtk8250] disabled
10545 10:02:10.174434 <6>[ 1.092316] SuperH (H)SCI(F) driver initialized
10546 10:02:10.178212 <6>[ 1.097588] msm_serial: driver initialized
10547 10:02:10.191419 <6>[ 1.106507] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10548 10:02:10.201781 <6>[ 1.115053] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10549 10:02:10.208250 <6>[ 1.123595] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10550 10:02:10.218374 <6>[ 1.132223] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10551 10:02:10.228208 <6>[ 1.140935] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10552 10:02:10.234944 <6>[ 1.149648] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10553 10:02:10.244812 <6>[ 1.158188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10554 10:02:10.251729 <6>[ 1.166990] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10555 10:02:10.261413 <6>[ 1.175534] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10556 10:02:10.272418 <6>[ 1.190847] loop: module loaded
10557 10:02:10.279505 <6>[ 1.196927] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10558 10:02:10.301907 <4>[ 1.220103] mtk-pmic-keys: Failed to locate of_node [id: -1]
10559 10:02:10.308643 <6>[ 1.226801] megasas: 07.719.03.00-rc1
10560 10:02:10.317644 <6>[ 1.236348] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10561 10:02:10.328771 <6>[ 1.246340] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10562 10:02:10.344846 <6>[ 1.262926] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10563 10:02:10.400806 <6>[ 1.312728] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10564 10:02:10.599911 <6>[ 1.518221] Freeing initrd memory: 17348K
10565 10:02:10.610700 <6>[ 1.528582] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10566 10:02:10.621436 <6>[ 1.539387] tun: Universal TUN/TAP device driver, 1.6
10567 10:02:10.624857 <6>[ 1.545442] thunder_xcv, ver 1.0
10568 10:02:10.627692 <6>[ 1.548944] thunder_bgx, ver 1.0
10569 10:02:10.631307 <6>[ 1.552438] nicpf, ver 1.0
10570 10:02:10.641978 <6>[ 1.556448] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10571 10:02:10.645102 <6>[ 1.563925] hns3: Copyright (c) 2017 Huawei Corporation.
10572 10:02:10.648579 <6>[ 1.569512] hclge is initializing
10573 10:02:10.655213 <6>[ 1.573086] e1000: Intel(R) PRO/1000 Network Driver
10574 10:02:10.661878 <6>[ 1.578215] e1000: Copyright (c) 1999-2006 Intel Corporation.
10575 10:02:10.665223 <6>[ 1.584231] e1000e: Intel(R) PRO/1000 Network Driver
10576 10:02:10.672117 <6>[ 1.589446] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10577 10:02:10.678203 <6>[ 1.595632] igb: Intel(R) Gigabit Ethernet Network Driver
10578 10:02:10.685145 <6>[ 1.601281] igb: Copyright (c) 2007-2014 Intel Corporation.
10579 10:02:10.691909 <6>[ 1.607117] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10580 10:02:10.695545 <6>[ 1.613635] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10581 10:02:10.702239 <6>[ 1.620104] sky2: driver version 1.30
10582 10:02:10.708399 <6>[ 1.625095] VFIO - User Level meta-driver version: 0.3
10583 10:02:10.715564 <6>[ 1.633337] usbcore: registered new interface driver usb-storage
10584 10:02:10.721760 <6>[ 1.639779] usbcore: registered new device driver onboard-usb-hub
10585 10:02:10.730630 <6>[ 1.648885] mt6397-rtc mt6359-rtc: registered as rtc0
10586 10:02:10.740861 <6>[ 1.654353] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-23T10:02:11 UTC (1692784931)
10587 10:02:10.744093 <6>[ 1.663917] i2c_dev: i2c /dev entries driver
10588 10:02:10.760876 <6>[ 1.675667] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10589 10:02:10.781652 <6>[ 1.699672] cpu cpu0: EM: created perf domain
10590 10:02:10.784791 <6>[ 1.704794] cpu cpu4: EM: created perf domain
10591 10:02:10.791981 <6>[ 1.710399] sdhci: Secure Digital Host Controller Interface driver
10592 10:02:10.798634 <6>[ 1.716831] sdhci: Copyright(c) Pierre Ossman
10593 10:02:10.805670 <6>[ 1.721790] Synopsys Designware Multimedia Card Interface Driver
10594 10:02:10.812112 <6>[ 1.728444] sdhci-pltfm: SDHCI platform and OF driver helper
10595 10:02:10.815509 <6>[ 1.728484] mmc0: CQHCI version 5.10
10596 10:02:10.821902 <6>[ 1.738311] ledtrig-cpu: registered to indicate activity on CPUs
10597 10:02:10.829041 <6>[ 1.745273] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10598 10:02:10.835733 <6>[ 1.752326] usbcore: registered new interface driver usbhid
10599 10:02:10.838701 <6>[ 1.758148] usbhid: USB HID core driver
10600 10:02:10.845199 <6>[ 1.762333] spi_master spi0: will run message pump with realtime priority
10601 10:02:10.887916 <6>[ 1.799504] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10602 10:02:10.902857 <6>[ 1.814464] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10603 10:02:10.910520 <6>[ 1.828060] mmc0: Command Queue Engine enabled
10604 10:02:10.917084 <6>[ 1.832838] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10605 10:02:10.923259 <6>[ 1.839753] cros-ec-spi spi0.0: Chrome EC device registered
10606 10:02:10.926894 <6>[ 1.840054] mmcblk0: mmc0:0001 DA4128 116 GiB
10607 10:02:10.937727 <6>[ 1.856335] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10608 10:02:10.945654 <6>[ 1.863442] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10609 10:02:10.952235 <6>[ 1.869444] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10610 10:02:10.962120 <6>[ 1.874872] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10611 10:02:10.969020 <6>[ 1.875376] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10612 10:02:10.972193 <6>[ 1.885450] NET: Registered PF_PACKET protocol family
10613 10:02:10.978901 <6>[ 1.896102] 9pnet: Installing 9P2000 support
10614 10:02:10.982157 <5>[ 1.900675] Key type dns_resolver registered
10615 10:02:10.985296 <6>[ 1.905662] registered taskstats version 1
10616 10:02:10.992107 <5>[ 1.910053] Loading compiled-in X.509 certificates
10617 10:02:11.022757 <4>[ 1.934238] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 10:02:11.032785 <4>[ 1.945012] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 10:02:11.039490 <3>[ 1.955567] debugfs: File 'uA_load' in directory '/' already present!
10620 10:02:11.046479 <3>[ 1.962273] debugfs: File 'min_uV' in directory '/' already present!
10621 10:02:11.052781 <3>[ 1.968898] debugfs: File 'max_uV' in directory '/' already present!
10622 10:02:11.059158 <3>[ 1.975520] debugfs: File 'constraint_flags' in directory '/' already present!
10623 10:02:11.070500 <3>[ 1.985486] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10624 10:02:11.083149 <6>[ 2.001170] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10625 10:02:11.089631 <6>[ 2.008023] xhci-mtk 11200000.usb: xHCI Host Controller
10626 10:02:11.096613 <6>[ 2.013532] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10627 10:02:11.107025 <6>[ 2.021459] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10628 10:02:11.113424 <6>[ 2.030895] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10629 10:02:11.120235 <6>[ 2.036975] xhci-mtk 11200000.usb: xHCI Host Controller
10630 10:02:11.126615 <6>[ 2.042455] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10631 10:02:11.133300 <6>[ 2.050105] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10632 10:02:11.140318 <6>[ 2.057905] hub 1-0:1.0: USB hub found
10633 10:02:11.143235 <6>[ 2.061932] hub 1-0:1.0: 1 port detected
10634 10:02:11.150498 <6>[ 2.066232] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10635 10:02:11.157115 <6>[ 2.074932] hub 2-0:1.0: USB hub found
10636 10:02:11.160127 <6>[ 2.078957] hub 2-0:1.0: 1 port detected
10637 10:02:11.167895 <6>[ 2.085927] mtk-msdc 11f70000.mmc: Got CD GPIO
10638 10:02:11.180198 <6>[ 2.094842] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10639 10:02:11.186756 <6>[ 2.102877] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10640 10:02:11.196476 <4>[ 2.110817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10641 10:02:11.206965 <6>[ 2.120379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10642 10:02:11.213677 <6>[ 2.128456] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10643 10:02:11.220720 <6>[ 2.136468] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10644 10:02:11.230650 <6>[ 2.144391] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10645 10:02:11.237559 <6>[ 2.152215] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10646 10:02:11.246917 <6>[ 2.160032] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10647 10:02:11.256809 <6>[ 2.170446] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10648 10:02:11.263948 <6>[ 2.178807] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10649 10:02:11.273555 <6>[ 2.187162] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10650 10:02:11.280132 <6>[ 2.195500] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10651 10:02:11.290146 <6>[ 2.203838] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10652 10:02:11.296983 <6>[ 2.212179] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10653 10:02:11.307531 <6>[ 2.220517] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10654 10:02:11.313776 <6>[ 2.228854] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10655 10:02:11.323610 <6>[ 2.237192] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10656 10:02:11.330613 <6>[ 2.245530] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10657 10:02:11.340593 <6>[ 2.253876] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10658 10:02:11.347270 <6>[ 2.262228] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10659 10:02:11.356964 <6>[ 2.270566] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10660 10:02:11.364240 <6>[ 2.278905] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10661 10:02:11.373759 <6>[ 2.287243] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10662 10:02:11.380648 <6>[ 2.295987] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10663 10:02:11.387127 <6>[ 2.303153] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10664 10:02:11.393402 <6>[ 2.309915] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10665 10:02:11.399754 <6>[ 2.316674] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10666 10:02:11.406379 <6>[ 2.323615] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10667 10:02:11.416523 <6>[ 2.330472] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10668 10:02:11.427084 <6>[ 2.339605] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10669 10:02:11.433360 <6>[ 2.348725] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10670 10:02:11.443442 <6>[ 2.358022] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10671 10:02:11.453278 <6>[ 2.367497] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10672 10:02:11.463129 <6>[ 2.376967] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10673 10:02:11.473072 <6>[ 2.386087] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10674 10:02:11.479578 <6>[ 2.395554] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10675 10:02:11.489953 <6>[ 2.404674] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10676 10:02:11.499970 <6>[ 2.413969] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10677 10:02:11.509752 <6>[ 2.424130] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10678 10:02:11.520393 <6>[ 2.435620] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10679 10:02:11.527295 <6>[ 2.444993] Trying to probe devices needed for running init ...
10680 10:02:11.572408 <6>[ 2.487233] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10681 10:02:11.727716 <6>[ 2.645258] hub 1-1:1.0: USB hub found
10682 10:02:11.730510 <6>[ 2.649810] hub 1-1:1.0: 4 ports detected
10683 10:02:11.852143 <6>[ 2.767503] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10684 10:02:11.877856 <6>[ 2.796314] hub 2-1:1.0: USB hub found
10685 10:02:11.881541 <6>[ 2.800758] hub 2-1:1.0: 3 ports detected
10686 10:02:12.052337 <6>[ 2.967315] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10687 10:02:12.184797 <6>[ 3.102868] hub 1-1.4:1.0: USB hub found
10688 10:02:12.187893 <6>[ 3.107543] hub 1-1.4:1.0: 2 ports detected
10689 10:02:12.264724 <6>[ 3.179408] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10690 10:02:12.484346 <6>[ 3.399288] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10691 10:02:12.676794 <6>[ 3.591272] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10692 10:02:23.813330 <6>[ 14.736246] ALSA device list:
10693 10:02:23.819617 <6>[ 14.739543] No soundcards found.
10694 10:02:23.827758 <6>[ 14.747507] Freeing unused kernel memory: 8384K
10695 10:02:23.830946 <6>[ 14.752513] Run /init as init process
10696 10:02:23.842350 Loading, please wait...
10697 10:02:23.862524 Starting version 247.3-7+deb11u2
10698 10:02:24.065623 <6>[ 14.982319] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10699 10:02:24.080331 <6>[ 15.000227] remoteproc remoteproc0: scp is available
10700 10:02:24.087203 <6>[ 15.005917] remoteproc remoteproc0: powering up scp
10701 10:02:24.094235 <6>[ 15.011096] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10702 10:02:24.100278 <6>[ 15.019621] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10703 10:02:24.110845 <3>[ 15.026358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 10:02:24.116913 <3>[ 15.034484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 10:02:24.127200 <3>[ 15.042576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 10:02:24.133615 <4>[ 15.044302] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10707 10:02:24.140619 <6>[ 15.045855] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10708 10:02:24.150464 <6>[ 15.045910] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10709 10:02:24.156746 <6>[ 15.045926] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10710 10:02:24.166828 <3>[ 15.058795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 10:02:24.173925 <4>[ 15.068114] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10712 10:02:24.180545 <3>[ 15.074396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 10:02:24.187183 <6>[ 15.082129] mc: Linux media interface: v0.10
10714 10:02:24.193628 <6>[ 15.110439] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10715 10:02:24.203167 <3>[ 15.111046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 10:02:24.210147 <3>[ 15.126791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 10:02:24.216383 <6>[ 15.127835] videodev: Linux video capture interface: v2.00
10718 10:02:24.223037 <3>[ 15.134885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 10:02:24.232919 <3>[ 15.135058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 10:02:24.239991 <4>[ 15.137768] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10721 10:02:24.246514 <4>[ 15.137768] Fallback method does not support PEC.
10722 10:02:24.253179 <6>[ 15.146457] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10723 10:02:24.260166 <3>[ 15.148824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 10:02:24.270489 <6>[ 15.156958] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10725 10:02:24.276807 <3>[ 15.170529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 10:02:24.283868 <3>[ 15.170531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 10:02:24.294094 <3>[ 15.170587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 10:02:24.300778 <6>[ 15.172239] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10729 10:02:24.307451 <6>[ 15.172244] pci_bus 0000:00: root bus resource [bus 00-ff]
10730 10:02:24.313576 <6>[ 15.172248] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10731 10:02:24.323742 <6>[ 15.172251] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10732 10:02:24.330580 <6>[ 15.172281] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10733 10:02:24.336837 <6>[ 15.172294] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10734 10:02:24.340320 <6>[ 15.172367] pci 0000:00:00.0: supports D1 D2
10735 10:02:24.347012 <6>[ 15.172371] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10736 10:02:24.356772 <6>[ 15.173272] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10737 10:02:24.363894 <6>[ 15.173351] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10738 10:02:24.370180 <6>[ 15.173375] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10739 10:02:24.376980 <6>[ 15.173391] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10740 10:02:24.387941 <6>[ 15.173406] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10741 10:02:24.390460 <6>[ 15.173509] pci 0000:01:00.0: supports D1 D2
10742 10:02:24.396919 <6>[ 15.173511] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10743 10:02:24.404030 <6>[ 15.177770] remoteproc remoteproc0: remote processor scp is now up
10744 10:02:24.410310 <3>[ 15.185668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 10:02:24.420444 <3>[ 15.185671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 10:02:24.427162 <3>[ 15.185674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 10:02:24.436663 <3>[ 15.185676] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 10:02:24.443340 <3>[ 15.185695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 10:02:24.449973 <6>[ 15.187011] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10750 10:02:24.460270 <6>[ 15.187039] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10751 10:02:24.466610 <6>[ 15.187042] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10752 10:02:24.473243 <6>[ 15.187050] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10753 10:02:24.483064 <6>[ 15.187063] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10754 10:02:24.490132 <6>[ 15.187076] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10755 10:02:24.497002 <6>[ 15.187088] pci 0000:00:00.0: PCI bridge to [bus 01]
10756 10:02:24.503470 <6>[ 15.187094] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10757 10:02:24.509825 <6>[ 15.187208] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10758 10:02:24.516748 <6>[ 15.187676] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10759 10:02:24.523395 <6>[ 15.188127] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10760 10:02:24.533103 <6>[ 15.198205] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10761 10:02:24.539586 <3>[ 15.210477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10762 10:02:24.545947 <6>[ 15.218647] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10763 10:02:24.555661 <6>[ 15.219848] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10764 10:02:24.562418 <6>[ 15.222503] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10765 10:02:24.572605 <6>[ 15.227043] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10766 10:02:24.583760 <6>[ 15.500098] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10767 10:02:24.593391 <4>[ 15.501815] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10768 10:02:24.600342 <4>[ 15.518233] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10769 10:02:24.610404 <5>[ 15.519946] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10770 10:02:24.622134 <6>[ 15.544694] Bluetooth: Core ver 2.22
10771 10:02:24.629191 <6>[ 15.546474] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10772 10:02:24.635913 <6>[ 15.548742] NET: Registered PF_BLUETOOTH protocol family
10773 10:02:24.642566 <5>[ 15.557129] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10774 10:02:24.648576 <6>[ 15.561177] Bluetooth: HCI device and connection manager initialized
10775 10:02:24.658811 <3>[ 15.567961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10776 10:02:24.671798 <6>[ 15.568795] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10777 10:02:24.675133 <6>[ 15.569351] usbcore: registered new interface driver uvcvideo
10778 10:02:24.681964 <6>[ 15.571300] r8152 2-1.3:1.0 eth0: v1.12.13
10779 10:02:24.685048 <6>[ 15.571435] usbcore: registered new interface driver r8152
10780 10:02:24.691767 <6>[ 15.574575] Bluetooth: HCI socket layer initialized
10781 10:02:24.698255 <6>[ 15.575793] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10782 10:02:24.708827 <4>[ 15.583421] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10783 10:02:24.711771 <6>[ 15.595759] Bluetooth: L2CAP socket layer initialized
10784 10:02:24.718605 <6>[ 15.595768] Bluetooth: SCO socket layer initialized
10785 10:02:24.725544 <6>[ 15.595997] usbcore: registered new interface driver cdc_ether
10786 10:02:24.728886 <6>[ 15.601777] cfg80211: failed to load regulatory.db
10787 10:02:24.735674 <6>[ 15.601981] usbcore: registered new interface driver r8153_ecm
10788 10:02:24.741675 <6>[ 15.610635] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10789 10:02:24.748215 <6>[ 15.638190] usbcore: registered new interface driver btusb
10790 10:02:24.758518 <4>[ 15.638687] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10791 10:02:24.764704 <3>[ 15.638693] Bluetooth: hci0: Failed to load firmware file (-2)
10792 10:02:24.768374 <3>[ 15.638697] Bluetooth: hci0: Failed to set up firmware (-2)
10793 10:02:24.781174 <4>[ 15.638700] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10794 10:02:24.852652 <6>[ 15.769325] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10795 10:02:24.859417 <6>[ 15.776833] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10796 10:02:24.883740 <6>[ 15.803491] mt7921e 0000:01:00.0: ASIC revision: 79610010
10797 10:02:24.989256 <4>[ 15.902653] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 10:02:25.006582 Begin: Loading essential drivers ... done.
10799 10:02:25.009896 Begin: Running /scripts/init-premount ... done.
10800 10:02:25.016420 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10801 10:02:25.026447 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10802 10:02:25.030372 Device /sys/class/net/enx002432307852 found
10803 10:02:25.030907 done.
10804 10:02:25.114655 <4>[ 16.027699] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 10:02:25.121298 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10806 10:02:25.237086 <4>[ 16.150370] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 10:02:25.357334 <4>[ 16.270805] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 10:02:25.477535 <4>[ 16.390781] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 10:02:25.597108 <4>[ 16.510746] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 10:02:25.717476 <4>[ 16.630788] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 10:02:25.837452 <4>[ 16.750847] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 10:02:25.957276 <4>[ 16.870865] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 10:02:26.077572 <4>[ 16.990822] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 10:02:26.188716 <3>[ 17.108760] mt7921e 0000:01:00.0: hardware init failed
10815 10:02:26.234452 IP-Config: no response after 2 secs - giving up
10816 10:02:26.278511 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10817 10:02:26.341832 <6>[ 17.261574] r8152 2-1.3:1.0 enx002432307852: carrier on
10818 10:02:27.384412 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10819 10:02:27.391242 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10820 10:02:27.398110 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10821 10:02:27.404656 host : mt8192-asurada-spherion-r0-cbg-3
10822 10:02:27.411596 domain : lava-rack
10823 10:02:27.414356 rootserver: 192.168.201.1 rootpath:
10824 10:02:27.417722 filename :
10825 10:02:27.498330 done.
10826 10:02:27.507746 Begin: Running /scripts/nfs-bottom ... done.
10827 10:02:27.526847 Begin: Running /scripts/init-bottom ... done.
10828 10:02:28.793238 <6>[ 19.713274] NET: Registered PF_INET6 protocol family
10829 10:02:28.800160 <6>[ 19.720189] Segment Routing with IPv6
10830 10:02:28.803153 <6>[ 19.724154] In-situ OAM (IOAM) with IPv6
10831 10:02:28.940229 <30>[ 19.840640] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10832 10:02:28.943297 <30>[ 19.865031] systemd[1]: Detected architecture arm64.
10833 10:02:28.967979
10834 10:02:28.971315 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10835 10:02:28.971848
10836 10:02:28.989821 <30>[ 19.910356] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10837 10:02:29.973614 <30>[ 20.890129] systemd[1]: Queued start job for default target Graphical Interface.
10838 10:02:30.000796 <30>[ 20.921628] systemd[1]: Created slice system-getty.slice.
10839 10:02:30.007569 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10840 10:02:30.024394 <30>[ 20.944665] systemd[1]: Created slice system-modprobe.slice.
10841 10:02:30.030575 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10842 10:02:30.048778 <30>[ 20.969374] systemd[1]: Created slice system-serial\x2dgetty.slice.
10843 10:02:30.058922 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10844 10:02:30.071961 <30>[ 20.992311] systemd[1]: Created slice User and Session Slice.
10845 10:02:30.078659 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10846 10:02:30.099222 <30>[ 21.016110] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10847 10:02:30.108397 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10848 10:02:30.126906 <30>[ 21.044013] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10849 10:02:30.133412 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10850 10:02:30.157764 <30>[ 21.071393] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10851 10:02:30.164180 <30>[ 21.083539] systemd[1]: Reached target Local Encrypted Volumes.
10852 10:02:30.170833 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10853 10:02:30.187402 <30>[ 21.107663] systemd[1]: Reached target Paths.
10854 10:02:30.190837 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10855 10:02:30.206950 <30>[ 21.127250] systemd[1]: Reached target Remote File Systems.
10856 10:02:30.213496 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10857 10:02:30.231120 <30>[ 21.151622] systemd[1]: Reached target Slices.
10858 10:02:30.238410 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10859 10:02:30.251064 <30>[ 21.171261] systemd[1]: Reached target Swap.
10860 10:02:30.254099 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10861 10:02:30.274851 <30>[ 21.191759] systemd[1]: Listening on initctl Compatibility Named Pipe.
10862 10:02:30.281043 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10863 10:02:30.288275 <30>[ 21.208101] systemd[1]: Listening on Journal Audit Socket.
10864 10:02:30.294701 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10865 10:02:30.312558 <30>[ 21.232834] systemd[1]: Listening on Journal Socket (/dev/log).
10866 10:02:30.319378 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10867 10:02:30.335318 <30>[ 21.255797] systemd[1]: Listening on Journal Socket.
10868 10:02:30.341774 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10869 10:02:30.357428 <30>[ 21.276961] systemd[1]: Listening on Network Service Netlink Socket.
10870 10:02:30.366908 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10871 10:02:30.382233 <30>[ 21.302846] systemd[1]: Listening on udev Control Socket.
10872 10:02:30.389210 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10873 10:02:30.403221 <30>[ 21.323686] systemd[1]: Listening on udev Kernel Socket.
10874 10:02:30.409588 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10875 10:02:30.454823 <30>[ 21.375360] systemd[1]: Mounting Huge Pages File System...
10876 10:02:30.461173 Mounting [0;1;39mHuge Pages File System[0m...
10877 10:02:30.479101 <30>[ 21.399717] systemd[1]: Mounting POSIX Message Queue File System...
10878 10:02:30.485825 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10879 10:02:30.522769 <30>[ 21.443475] systemd[1]: Mounting Kernel Debug File System...
10880 10:02:30.529177 Mounting [0;1;39mKernel Debug File System[0m...
10881 10:02:30.550448 <30>[ 21.467774] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10882 10:02:30.574626 <30>[ 21.491927] systemd[1]: Starting Create list of static device nodes for the current kernel...
10883 10:02:30.581197 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10884 10:02:30.627702 <30>[ 21.548015] systemd[1]: Starting Load Kernel Module configfs...
10885 10:02:30.633977 Starting [0;1;39mLoad Kernel Module configfs[0m...
10886 10:02:30.651822 <30>[ 21.572476] systemd[1]: Starting Load Kernel Module drm...
10887 10:02:30.658234 Starting [0;1;39mLoad Kernel Module drm[0m...
10888 10:02:30.675578 <30>[ 21.596106] systemd[1]: Starting Load Kernel Module fuse...
10889 10:02:30.682024 Starting [0;1;39mLoad Kernel Module fuse[0m...
10890 10:02:30.705391 <30>[ 21.622800] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10891 10:02:30.722082 <6>[ 21.642719] fuse: init (API version 7.37)
10892 10:02:30.747502 <30>[ 21.668151] systemd[1]: Starting Journal Service...
10893 10:02:30.751198 Starting [0;1;39mJournal Service[0m...
10894 10:02:30.779020 <30>[ 21.699637] systemd[1]: Starting Load Kernel Modules...
10895 10:02:30.785562 Starting [0;1;39mLoad Kernel Modules[0m...
10896 10:02:30.806206 <30>[ 21.723952] systemd[1]: Starting Remount Root and Kernel File Systems...
10897 10:02:30.812784 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10898 10:02:30.830804 <30>[ 21.751237] systemd[1]: Starting Coldplug All udev Devices...
10899 10:02:30.837232 Starting [0;1;39mColdplug All udev Devices[0m...
10900 10:02:30.854386 <30>[ 21.774925] systemd[1]: Mounted Huge Pages File System.
10901 10:02:30.860764 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10902 10:02:30.879307 <30>[ 21.799849] systemd[1]: Mounted POSIX Message Queue File System.
10903 10:02:30.885808 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10904 10:02:30.903235 <30>[ 21.823731] systemd[1]: Mounted Kernel Debug File System.
10905 10:02:30.913258 <3>[ 21.827751] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 10:02:30.919756 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10907 10:02:30.939874 <30>[ 21.856476] systemd[1]: Finished Create list of static device nodes for the current kernel.
10908 10:02:30.946364 <3>[ 21.862239] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 10:02:30.956392 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10910 10:02:30.972155 <30>[ 21.892056] systemd[1]: modprobe@configfs.service: Succeeded.
10911 10:02:30.978572 <30>[ 21.898787] systemd[1]: Finished Load Kernel Module configfs.
10912 10:02:30.988598 <3>[ 21.903922] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 10:02:30.995389 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10914 10:02:31.011899 <30>[ 21.932183] systemd[1]: modprobe@drm.service: Succeeded.
10915 10:02:31.021643 <3>[ 21.934105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 10:02:31.025107 <30>[ 21.938785] systemd[1]: Finished Load Kernel Module drm.
10917 10:02:31.031908 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10918 10:02:31.050736 <3>[ 21.968255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 10:02:31.057358 <30>[ 21.969164] systemd[1]: modprobe@fuse.service: Succeeded.
10920 10:02:31.064257 <30>[ 21.984113] systemd[1]: Finished Load Kernel Module fuse.
10921 10:02:31.071255 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10922 10:02:31.081772 <3>[ 21.999072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 10:02:31.092308 <30>[ 22.013071] systemd[1]: Finished Load Kernel Modules.
10924 10:02:31.099243 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10925 10:02:31.112503 <3>[ 22.030050] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 10:02:31.123826 <30>[ 22.040756] systemd[1]: Finished Remount Root and Kernel File Systems.
10927 10:02:31.130587 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10928 10:02:31.145037 <3>[ 22.062248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 10:02:31.173482 <30>[ 22.093610] systemd[1]: Mounting FUSE Control File System...
10930 10:02:31.183739 <3>[ 22.096213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 10:02:31.187111 Mounting [0;1;39mFUSE Control File System[0m...
10932 10:02:31.207360 <30>[ 22.127571] systemd[1]: Mounting Kernel Configuration File System...
10933 10:02:31.217654 <3>[ 22.131645] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 10:02:31.223701 Mounting [0;1;39mKernel Configuration File System[0m...
10935 10:02:31.250013 <30>[ 22.167476] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10936 10:02:31.260225 <30>[ 22.176778] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10937 10:02:31.290935 <30>[ 22.211750] systemd[1]: Starting Load/Save Random Seed...
10938 10:02:31.297400 Starting [0;1;39mLoad/Save Random Seed[0m...
10939 10:02:31.316074 <30>[ 22.236536] systemd[1]: Starting Apply Kernel Variables...
10940 10:02:31.322147 Starting [0;1;39mApply Kernel Variables[0m...
10941 10:02:31.338104 <30>[ 22.258565] systemd[1]: Starting Create System Users...
10942 10:02:31.354247 <4>[ 22.258800] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10943 10:02:31.364623 Startin<3>[ 22.280765] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10944 10:02:31.367496 g [0;1;39mCreate System Users[0m...
10945 10:02:31.389385 <30>[ 22.309391] systemd[1]: Started Journal Service.
10946 10:02:31.392347 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10947 10:02:31.417232 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10948 10:02:31.430717 See 'systemctl status systemd-udev-trigger.service' for details.
10949 10:02:31.446996 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10950 10:02:31.462848 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10951 10:02:31.479190 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10952 10:02:31.495149 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10953 10:02:31.512239 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10954 10:02:31.567924 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10955 10:02:31.584589 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10956 10:02:31.639002 <46>[ 22.556370] systemd-journald[301]: Received client request to flush runtime journal.
10957 10:02:31.879180 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10958 10:02:31.895134 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10959 10:02:31.909986 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10960 10:02:31.958152 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10961 10:02:33.044649 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10962 10:02:33.095141 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10963 10:02:33.167266 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10964 10:02:33.227454 Starting [0;1;39mNetwork Service[0m...
10965 10:02:33.529553 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10966 10:02:33.559799 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10967 10:02:33.617844 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10968 10:02:33.927036 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10969 10:02:33.945488 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10970 10:02:33.966901 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10971 10:02:33.982340 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10972 10:02:34.023074 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10973 10:02:34.043889 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10974 10:02:34.103204 Starting [0;1;39mNetwork Name Resolution[0m...
10975 10:02:34.131983 Starting [0;1;39mNetwork Time Synchronization[0m...
10976 10:02:34.150045 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10977 10:02:34.166644 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10978 10:02:34.210165 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10979 10:02:34.356080 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10980 10:02:34.375005 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10981 10:02:34.398159 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10982 10:02:34.410480 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10983 10:02:34.430422 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10984 10:02:34.460857 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10985 10:02:34.537398 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10986 10:02:34.612494 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10987 10:02:34.651817 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10988 10:02:34.661907 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10989 10:02:34.863570 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10990 10:02:34.877964 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10991 10:02:34.893361 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10992 10:02:34.946550 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10993 10:02:35.434425 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10994 10:02:35.800889 Starting [0;1;39mUser Login Management[0m...
10995 10:02:35.821468 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10996 10:02:35.843711 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10997 10:02:35.866125 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10998 10:02:35.917124 Starting [0;1;39mPermit User Sessions[0m...
10999 10:02:36.069278 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11000 10:02:36.102431 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11001 10:02:36.123167 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11002 10:02:36.129872 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11003 10:02:36.153620 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11004 10:02:36.219132 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11005 10:02:36.227163 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11006 10:02:36.243144 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11007 10:02:36.284581 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11008 10:02:36.340996 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11009 10:02:36.460472
11010 10:02:36.460707
11011 10:02:36.463705 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11012 10:02:36.463841
11013 10:02:36.467055 debian-bullseye-arm64 login: root (automatic login)
11014 10:02:36.467197
11015 10:02:36.467314
11016 10:02:36.858139 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Wed Aug 23 09:52:58 UTC 2023 aarch64
11017 10:02:36.858672
11018 10:02:36.864825 The programs included with the Debian GNU/Linux system are free software;
11019 10:02:36.871737 the exact distribution terms for each program are described in the
11020 10:02:36.874985 individual files in /usr/share/doc/*/copyright.
11021 10:02:36.875429
11022 10:02:36.881572 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11023 10:02:36.884530 permitted by applicable law.
11024 10:02:37.013030 Matched prompt #10: / #
11026 10:02:37.014178 Setting prompt string to ['/ #']
11027 10:02:37.014604 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11029 10:02:37.015548 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11030 10:02:37.015974 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11031 10:02:37.016319 Setting prompt string to ['/ #']
11032 10:02:37.016622 Forcing a shell prompt, looking for ['/ #']
11034 10:02:37.067531 / #
11035 10:02:37.068189 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11036 10:02:37.068780 Waiting using forced prompt support (timeout 00:02:30)
11037 10:02:37.074254
11038 10:02:37.075080 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11039 10:02:37.075591 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11041 10:02:37.176857 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11336442/extract-nfsrootfs-f56f79f8'
11042 10:02:37.183862 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11336442/extract-nfsrootfs-f56f79f8'
11044 10:02:37.285742 / # export NFS_SERVER_IP='192.168.201.1'
11045 10:02:37.292185 export NFS_SERVER_IP='192.168.201.1'
11046 10:02:37.293187 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11047 10:02:37.293716 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
11048 10:02:37.294186 end: 2 depthcharge-action (duration 00:01:47) [common]
11049 10:02:37.294743 start: 3 lava-test-retry (timeout 00:01:00) [common]
11050 10:02:37.295224 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11051 10:02:37.295640 Using namespace: common
11053 10:02:37.396893 / # #
11054 10:02:37.397740 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11055 10:02:37.403913 #
11056 10:02:37.404843 Using /lava-11336442
11058 10:02:37.505991 / # export SHELL=/bin/sh
11059 10:02:37.512233 export SHELL=/bin/sh
11061 10:02:37.614131 / # . /lava-11336442/environment
11062 10:02:37.620535 . /lava-11336442/environment
11064 10:02:37.730077 / # /lava-11336442/bin/lava-test-runner /lava-11336442/0
11065 10:02:37.730726 Test shell timeout: 10s (minimum of the action and connection timeout)
11066 10:02:37.736865 /lava-11336442/bin/lava-test-runner /lava-11336442/0
11067 10:02:38.041974 + export TESTRUN_ID=0_dmesg
11068 10:02:38.045046 + cd /lava-11336442/0/tests/0_dmesg
11069 10:02:38.048587 + cat uuid
11070 10:02:38.066197 + UUID=11336442_1.<8>[ 28.984659] <LAVA_SIGNAL_STARTRUN 0_dmesg 11336442_1.6.2.3.1>
11071 10:02:38.066674 6.2.3.1
11072 10:02:38.067135 + set +x
11073 10:02:38.067959 Received signal: <STARTRUN> 0_dmesg 11336442_1.6.2.3.1
11074 10:02:38.068388 Starting test lava.0_dmesg (11336442_1.6.2.3.1)
11075 10:02:38.068820 Skipping test definition patterns.
11076 10:02:38.072750 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11077 10:02:38.215310 <8>[ 29.133676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11078 10:02:38.216141 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11080 10:02:38.316726 <8>[ 29.234607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11081 10:02:38.317593 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11083 10:02:38.429196 <8>[ 29.347255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11084 10:02:38.430037 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11086 10:02:38.432363 + set +x
11087 10:02:38.435878 <8>[ 29.357027] <LAVA_SIGNAL_ENDRUN 0_dmesg 11336442_1.6.2.3.1>
11088 10:02:38.436824 Received signal: <ENDRUN> 0_dmesg 11336442_1.6.2.3.1
11089 10:02:38.437322 Ending use of test pattern.
11090 10:02:38.437841 Ending test lava.0_dmesg (11336442_1.6.2.3.1), duration 0.37
11092 10:02:38.442806 <LAVA_TEST_RUNNER EXIT>
11093 10:02:38.443650 ok: lava_test_shell seems to have completed
11094 10:02:38.444252 alert: pass
crit: pass
emerg: pass
11095 10:02:38.444765 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11096 10:02:38.445433 end: 3 lava-test-retry (duration 00:00:01) [common]
11097 10:02:38.445921 start: 4 lava-test-retry (timeout 00:01:00) [common]
11098 10:02:38.446430 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11099 10:02:38.446796 Using namespace: common
11101 10:02:38.547982 / # #
11102 10:02:38.548649 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11103 10:02:38.549362 Using /lava-11336442
11105 10:02:38.650630 export SHELL=/bin/sh
11106 10:02:38.651517 #
11108 10:02:38.753041 / # export SHELL=/bin/sh. /lava-11336442/environment
11109 10:02:38.754019
11111 10:02:38.855727 / # . /lava-11336442/environment/lava-11336442/bin/lava-test-runner /lava-11336442/1
11112 10:02:38.856373 Test shell timeout: 10s (minimum of the action and connection timeout)
11113 10:02:38.857048
11114 10:02:38.862671 / # /lava-11336442/bin/lava-test-runner /lava-11336442/1
11115 10:02:39.042168 + export TESTRUN_ID=1_bootrr
11116 10:02:39.045266 + cd /lava-11336442/1/tests/1_bootrr
11117 10:02:39.048190 + cat uuid
11118 10:02:39.067545 + UUID=11336442_1.<8>[ 29.985918] <LAVA_SIGNAL_STARTRUN 1_bootrr 11336442_1.6.2.3.5>
11119 10:02:39.068142 6.2.3.5
11120 10:02:39.068503 + set +x
11121 10:02:39.069205 Received signal: <STARTRUN> 1_bootrr 11336442_1.6.2.3.5
11122 10:02:39.069703 Starting test lava.1_bootrr (11336442_1.6.2.3.5)
11123 10:02:39.070265 Skipping test definition patterns.
11124 10:02:39.081004 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11336442/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11125 10:02:39.084167 + cd /opt/bootrr/libexec/bootrr
11126 10:02:39.084590 + sh helpers/bootrr-auto
11127 10:02:39.184298 /lava-11336442/1/../bin/lava-test-case
11128 10:02:39.228035 <8>[ 30.146182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11129 10:02:39.228821 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11131 10:02:39.287445 /lava-11336442/1/../bin/lava-test-case
11132 10:02:39.323271 <8>[ 30.241728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11133 10:02:39.324209 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11135 10:02:39.361220 /lava-11336442/1/../bin/lava-test-case
11136 10:02:39.401142 <8>[ 30.319935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11137 10:02:39.401923 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11139 10:02:39.474532 /lava-11336442/1/../bin/lava-test-case
11140 10:02:39.509916 <8>[ 30.428441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11141 10:02:39.510619 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11143 10:02:39.557538 /lava-11336442/1/../bin/lava-test-case
11144 10:02:39.598109 <8>[ 30.516520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11145 10:02:39.598963 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11147 10:02:39.641977 /lava-11336442/1/../bin/lava-test-case
11148 10:02:39.682527 <8>[ 30.600548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11149 10:02:39.683261 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11151 10:02:39.734692 /lava-11336442/1/../bin/lava-test-case
11152 10:02:39.775489 <8>[ 30.693844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11153 10:02:39.776411 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11155 10:02:39.826452 /lava-11336442/1/../bin/lava-test-case
11156 10:02:39.868749 <8>[ 30.787277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11157 10:02:39.869603 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11159 10:02:39.899491 /lava-11336442/1/../bin/lava-test-case
11160 10:02:39.942913 <8>[ 30.861376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11161 10:02:39.943776 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11163 10:02:39.992133 /lava-11336442/1/../bin/lava-test-case
11164 10:02:40.032470 <8>[ 30.950947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11165 10:02:40.033289 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11167 10:02:40.064423 /lava-11336442/1/../bin/lava-test-case
11168 10:02:40.105011 <8>[ 31.023137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11169 10:02:40.105825 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11171 10:02:40.151184 /lava-11336442/1/../bin/lava-test-case
11172 10:02:40.191570 <8>[ 31.110272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11173 10:02:40.192279 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11175 10:02:40.236316 /lava-11336442/1/../bin/lava-test-case
11176 10:02:40.276715 <8>[ 31.195236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11177 10:02:40.277598 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11179 10:02:40.327485 /lava-11336442/1/../bin/lava-test-case
11180 10:02:40.370241 <8>[ 31.288705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11181 10:02:40.371047 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11183 10:02:40.418146 /lava-11336442/1/../bin/lava-test-case
11184 10:02:40.456006 <8>[ 31.374738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11185 10:02:40.456756 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11187 10:02:40.487274 /lava-11336442/1/../bin/lava-test-case
11188 10:02:40.527316 <8>[ 31.445869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11189 10:02:40.528253 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11191 10:02:40.574315 /lava-11336442/1/../bin/lava-test-case
11192 10:02:40.615238 <8>[ 31.533712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11193 10:02:40.616079 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11195 10:02:40.644095 /lava-11336442/1/../bin/lava-test-case
11196 10:02:40.681244 <8>[ 31.599746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11197 10:02:40.682123 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11199 10:02:40.724439 /lava-11336442/1/../bin/lava-test-case
11200 10:02:40.759616 <8>[ 31.678244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11201 10:02:40.760576 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11203 10:02:40.794000 /lava-11336442/1/../bin/lava-test-case
11204 10:02:40.835315 <8>[ 31.753882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11205 10:02:40.836248 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11207 10:02:40.879715 /lava-11336442/1/../bin/lava-test-case
11208 10:02:40.921043 <8>[ 31.839573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11209 10:02:40.921841 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11211 10:02:40.951319 /lava-11336442/1/../bin/lava-test-case
11212 10:02:40.991137 <8>[ 31.909648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11213 10:02:40.991935 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11215 10:02:41.038362 /lava-11336442/1/../bin/lava-test-case
11216 10:02:41.076069 <8>[ 31.994627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11217 10:02:41.076798 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11219 10:02:41.104033 /lava-11336442/1/../bin/lava-test-case
11220 10:02:41.144245 <8>[ 32.062671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11221 10:02:41.145069 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11223 10:02:41.193704 /lava-11336442/1/../bin/lava-test-case
11224 10:02:41.229044 <8>[ 32.148009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11225 10:02:41.229801 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11227 10:02:41.279482 /lava-11336442/1/../bin/lava-test-case
11228 10:02:41.320179 <8>[ 32.238690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11229 10:02:41.321130 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11231 10:02:41.349920 /lava-11336442/1/../bin/lava-test-case
11232 10:02:41.389585 <8>[ 32.308101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11233 10:02:41.390286 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11235 10:02:41.435653 /lava-11336442/1/../bin/lava-test-case
11236 10:02:41.472399 <8>[ 32.391363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11237 10:02:41.473256 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11239 10:02:41.500942 /lava-11336442/1/../bin/lava-test-case
11240 10:02:41.538628 <8>[ 32.456910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11241 10:02:41.539486 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11243 10:02:41.588414 /lava-11336442/1/../bin/lava-test-case
11244 10:02:41.627554 <8>[ 32.546187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11245 10:02:41.628387 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11247 10:02:41.675982 /lava-11336442/1/../bin/lava-test-case
11248 10:02:41.714234 <8>[ 32.632957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11249 10:02:41.715026 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11251 10:02:41.759126 /lava-11336442/1/../bin/lava-test-case
11252 10:02:41.799622 <8>[ 32.718359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11253 10:02:41.800451 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11255 10:02:41.847562 /lava-11336442/1/../bin/lava-test-case
11256 10:02:41.886729 <8>[ 32.805783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11257 10:02:41.887537 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11259 10:02:41.921918 /lava-11336442/1/../bin/lava-test-case
11260 10:02:41.960436 <8>[ 32.879306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11261 10:02:41.961294 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11263 10:02:42.008197 /lava-11336442/1/../bin/lava-test-case
11264 10:02:42.049871 <8>[ 32.968611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11265 10:02:42.050709 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11267 10:02:42.093714 /lava-11336442/1/../bin/lava-test-case
11268 10:02:42.130491 <8>[ 33.049436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11269 10:02:42.131274 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11271 10:02:42.161212 /lava-11336442/1/../bin/lava-test-case
11272 10:02:42.201680 <8>[ 33.120324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11273 10:02:42.202503 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11275 10:02:42.246334 /lava-11336442/1/../bin/lava-test-case
11276 10:02:42.284389 <8>[ 33.203105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11277 10:02:42.285330 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11279 10:02:42.319045 /lava-11336442/1/../bin/lava-test-case
11280 10:02:42.359872 <8>[ 33.278663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11281 10:02:42.360585 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11283 10:02:42.404188 /lava-11336442/1/../bin/lava-test-case
11284 10:02:42.442300 <8>[ 33.361029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11285 10:02:42.443060 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11287 10:02:42.472289 /lava-11336442/1/../bin/lava-test-case
11288 10:02:42.508791 <8>[ 33.427329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11289 10:02:42.509621 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11291 10:02:42.553759 /lava-11336442/1/../bin/lava-test-case
11292 10:02:42.589446 <8>[ 33.507953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11293 10:02:42.590268 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11295 10:02:42.618528 /lava-11336442/1/../bin/lava-test-case
11296 10:02:42.654506 <8>[ 33.573451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11297 10:02:42.655612 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11299 10:02:42.704722 /lava-11336442/1/../bin/lava-test-case
11300 10:02:42.741806 <8>[ 33.660287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11301 10:02:42.742618 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11303 10:02:42.771327 /lava-11336442/1/../bin/lava-test-case
11304 10:02:42.808902 <8>[ 33.728036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11305 10:02:42.809669 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11307 10:02:42.855586 /lava-11336442/1/../bin/lava-test-case
11308 10:02:42.895415 <8>[ 33.814107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11309 10:02:42.896358 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11311 10:02:42.926292 /lava-11336442/1/../bin/lava-test-case
11312 10:02:42.966096 <8>[ 33.884604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11313 10:02:42.966787 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11315 10:02:43.009005 /lava-11336442/1/../bin/lava-test-case
11316 10:02:43.052875 <8>[ 33.971783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11317 10:02:43.053664 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11319 10:02:43.086710 /lava-11336442/1/../bin/lava-test-case
11320 10:02:43.120329 <8>[ 34.039342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11321 10:02:43.121065 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11323 10:02:43.162374 /lava-11336442/1/../bin/lava-test-case
11324 10:02:43.200535 <8>[ 34.119610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11325 10:02:43.201278 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11327 10:02:43.245556 /lava-11336442/1/../bin/lava-test-case
11328 10:02:43.284651 <8>[ 34.203375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11329 10:02:43.285545 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11331 10:02:43.313223 /lava-11336442/1/../bin/lava-test-case
11332 10:02:43.349685 <8>[ 34.267861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11333 10:02:43.350624 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11335 10:02:43.395583 /lava-11336442/1/../bin/lava-test-case
11336 10:02:43.433043 <8>[ 34.351481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11337 10:02:43.433912 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11339 10:02:43.465602 /lava-11336442/1/../bin/lava-test-case
11340 10:02:43.505477 <8>[ 34.424502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11341 10:02:43.506204 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11343 10:02:43.550843 /lava-11336442/1/../bin/lava-test-case
11344 10:02:43.587670 <8>[ 34.506456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11345 10:02:43.588390 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11347 10:02:43.631784 /lava-11336442/1/../bin/lava-test-case
11348 10:02:43.669206 <8>[ 34.587868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11349 10:02:43.670092 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11351 10:02:43.716611 /lava-11336442/1/../bin/lava-test-case
11352 10:02:43.756260 <8>[ 34.675276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11353 10:02:43.756992 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11355 10:02:43.801732 /lava-11336442/1/../bin/lava-test-case
11356 10:02:43.835803 <8>[ 34.754894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11357 10:02:43.836066 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11359 10:02:43.886484 /lava-11336442/1/../bin/lava-test-case
11360 10:02:43.924328 <8>[ 34.843026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11361 10:02:43.925168 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11363 10:02:43.955539 /lava-11336442/1/../bin/lava-test-case
11364 10:02:43.990885 <8>[ 34.910084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11365 10:02:43.991594 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11367 10:02:44.031277 /lava-11336442/1/../bin/lava-test-case
11368 10:02:44.071970 <8>[ 34.990891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11369 10:02:44.072663 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11371 10:02:44.114036 /lava-11336442/1/../bin/lava-test-case
11372 10:02:44.149569 <8>[ 35.068509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11373 10:02:44.150305 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11375 10:02:44.174756 /lava-11336442/1/../bin/lava-test-case
11376 10:02:44.213738 <8>[ 35.132589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11377 10:02:44.214551 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11379 10:02:44.259698 /lava-11336442/1/../bin/lava-test-case
11380 10:02:44.292054 <8>[ 35.211210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11381 10:02:44.292796 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11383 10:02:44.323437 /lava-11336442/1/../bin/lava-test-case
11384 10:02:44.364589 <8>[ 35.283671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11385 10:02:44.365507 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11387 10:02:44.412330 /lava-11336442/1/../bin/lava-test-case
11388 10:02:44.452064 <8>[ 35.370870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11389 10:02:44.452981 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11391 10:02:44.480983 /lava-11336442/1/../bin/lava-test-case
11392 10:02:44.519184 <8>[ 35.437947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11393 10:02:44.520045 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11395 10:02:44.562622 /lava-11336442/1/../bin/lava-test-case
11396 10:02:44.599528 <8>[ 35.518318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11397 10:02:44.600338 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11399 10:02:44.651446 /lava-11336442/1/../bin/lava-test-case
11400 10:02:44.691975 <8>[ 35.610610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11401 10:02:44.692799 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11403 10:02:44.739111 /lava-11336442/1/../bin/lava-test-case
11404 10:02:44.776773 <8>[ 35.695888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11405 10:02:44.777580 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11407 10:02:44.821068 /lava-11336442/1/../bin/lava-test-case
11408 10:02:44.859864 <8>[ 35.779188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11409 10:02:44.860706 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11411 10:02:44.906423 /lava-11336442/1/../bin/lava-test-case
11412 10:02:44.946202 <8>[ 35.865283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11413 10:02:44.947266 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11415 10:02:44.998403 /lava-11336442/1/../bin/lava-test-case
11416 10:02:45.037245 <8>[ 35.956242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11417 10:02:45.038042 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11419 10:02:45.083404 /lava-11336442/1/../bin/lava-test-case
11420 10:02:45.120761 <8>[ 36.039840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11421 10:02:45.121571 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11423 10:02:45.170932 /lava-11336442/1/../bin/lava-test-case
11424 10:02:45.211888 <8>[ 36.130775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11425 10:02:45.212794 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11427 10:02:45.259186 /lava-11336442/1/../bin/lava-test-case
11428 10:02:45.297677 <8>[ 36.216941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11429 10:02:45.298665 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11431 10:02:45.346343 /lava-11336442/1/../bin/lava-test-case
11432 10:02:45.385077 <8>[ 36.304220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11433 10:02:45.385836 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11435 10:02:45.431003 /lava-11336442/1/../bin/lava-test-case
11436 10:02:45.469158 <8>[ 36.388312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11437 10:02:45.470092 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11439 10:02:45.517117 /lava-11336442/1/../bin/lava-test-case
11440 10:02:45.555682 <8>[ 36.475014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11441 10:02:45.556369 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11443 10:02:45.603381 /lava-11336442/1/../bin/lava-test-case
11444 10:02:45.644765 <8>[ 36.563731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11445 10:02:45.645559 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11447 10:02:45.694314 /lava-11336442/1/../bin/lava-test-case
11448 10:02:45.734934 <8>[ 36.654147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11449 10:02:45.735725 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11451 10:02:45.780985 /lava-11336442/1/../bin/lava-test-case
11452 10:02:45.817148 <8>[ 36.736114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11453 10:02:45.817923 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11455 10:02:45.846874 /lava-11336442/1/../bin/lava-test-case
11456 10:02:45.886753 <8>[ 36.805598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11457 10:02:45.887586 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11459 10:02:45.932731 /lava-11336442/1/../bin/lava-test-case
11460 10:02:45.967802 <8>[ 36.887142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11461 10:02:45.968561 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11463 10:02:45.994437 /lava-11336442/1/../bin/lava-test-case
11464 10:02:46.032380 <8>[ 36.951457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11465 10:02:46.033235 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11467 10:02:46.082304 /lava-11336442/1/../bin/lava-test-case
11468 10:02:46.119466 <8>[ 37.038536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11469 10:02:46.120253 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11471 10:02:46.148631 /lava-11336442/1/../bin/lava-test-case
11472 10:02:46.186738 <8>[ 37.105881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11473 10:02:46.187607 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11475 10:02:46.233380 /lava-11336442/1/../bin/lava-test-case
11476 10:02:46.267359 <8>[ 37.186784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11477 10:02:46.268081 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11479 10:02:46.295362 /lava-11336442/1/../bin/lava-test-case
11480 10:02:46.331423 <8>[ 37.250333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11481 10:02:46.332207 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11483 10:02:46.375956 /lava-11336442/1/../bin/lava-test-case
11484 10:02:46.413703 <8>[ 37.332939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11485 10:02:46.414555 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11487 10:02:46.447987 /lava-11336442/1/../bin/lava-test-case
11488 10:02:46.486570 <8>[ 37.405775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11489 10:02:46.487687 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11491 10:02:46.531766 /lava-11336442/1/../bin/lava-test-case
11492 10:02:46.569984 <8>[ 37.488846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11493 10:02:46.570830 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11495 10:02:46.596736 /lava-11336442/1/../bin/lava-test-case
11496 10:02:46.634651 <8>[ 37.553313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11497 10:02:46.635592 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11499 10:02:46.679626 /lava-11336442/1/../bin/lava-test-case
11500 10:02:46.716784 <8>[ 37.636106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11501 10:02:46.717661 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11503 10:02:46.763753 /lava-11336442/1/../bin/lava-test-case
11504 10:02:46.805694 <8>[ 37.724716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11505 10:02:46.806603 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11507 10:02:46.839985 /lava-11336442/1/../bin/lava-test-case
11508 10:02:46.877839 <8>[ 37.797349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11509 10:02:46.878596 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11511 10:02:46.926558 /lava-11336442/1/../bin/lava-test-case
11512 10:02:46.964900 <8>[ 37.884365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11513 10:02:46.965701 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11515 10:02:46.994653 /lava-11336442/1/../bin/lava-test-case
11516 10:02:47.034671 <8>[ 37.953878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11517 10:02:47.035377 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11519 10:02:47.079510 /lava-11336442/1/../bin/lava-test-case
11520 10:02:47.115328 <8>[ 38.034821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11521 10:02:47.116146 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11523 10:02:47.144280 /lava-11336442/1/../bin/lava-test-case
11524 10:02:47.181061 <8>[ 38.100800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11525 10:02:47.181795 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11527 10:02:48.257174 /lava-11336442/1/../bin/lava-test-case
11528 10:02:48.296279 <8>[ 39.215880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11529 10:02:48.297076 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11531 10:02:48.326068 /lava-11336442/1/../bin/lava-test-case
11532 10:02:48.365080 <8>[ 39.284724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11533 10:02:48.365823 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11535 10:02:49.425044 /lava-11336442/1/../bin/lava-test-case
11536 10:02:49.467359 <8>[ 40.387263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11537 10:02:49.468100 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11539 10:02:49.496636 /lava-11336442/1/../bin/lava-test-case
11540 10:02:49.531268 <8>[ 40.451242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11541 10:02:49.531955 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11543 10:02:50.596262 /lava-11336442/1/../bin/lava-test-case
11544 10:02:50.639647 <8>[ 41.559038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11545 10:02:50.640499 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11547 10:02:50.670185 /lava-11336442/1/../bin/lava-test-case
11548 10:02:50.708498 <8>[ 41.628392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11549 10:02:50.709342 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11551 10:02:51.768186 /lava-11336442/1/../bin/lava-test-case
11552 10:02:51.808612 <8>[ 42.728662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11553 10:02:51.809505 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11555 10:02:51.837137 /lava-11336442/1/../bin/lava-test-case
11556 10:02:51.872811 <8>[ 42.793048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11557 10:02:51.873168 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11559 10:02:52.929081 /lava-11336442/1/../bin/lava-test-case
11560 10:02:52.971023 <8>[ 43.891053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11561 10:02:52.971983 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11563 10:02:53.001188 /lava-11336442/1/../bin/lava-test-case
11564 10:02:53.042860 <8>[ 43.962849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11565 10:02:53.043665 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11567 10:02:54.106604 /lava-11336442/1/../bin/lava-test-case
11568 10:02:54.148393 <8>[ 45.068372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11569 10:02:54.149284 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11571 10:02:54.177941 /lava-11336442/1/../bin/lava-test-case
11572 10:02:54.218685 <8>[ 45.138843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11573 10:02:54.219748 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11575 10:02:55.232229 <6>[ 46.159306] vpu: disabling
11576 10:02:55.235433 <6>[ 46.162414] vproc2: disabling
11577 10:02:55.239260 <6>[ 46.165751] vproc1: disabling
11578 10:02:55.242161 <6>[ 46.169093] vaud18: disabling
11579 10:02:55.248892 <6>[ 46.172613] vsram_others: disabling
11580 10:02:55.252469 <6>[ 46.176614] va09: disabling
11581 10:02:55.255586 <6>[ 46.179783] vsram_md: disabling
11582 10:02:55.258860 <6>[ 46.183378] Vgpu: disabling
11583 10:02:55.280538 /lava-11336442/1/../bin/lava-test-case
11584 10:02:55.325824 <8>[ 46.246021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11585 10:02:55.326651 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11587 10:02:55.353843 /lava-11336442/1/../bin/lava-test-case
11588 10:02:55.390555 <8>[ 46.310782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11589 10:02:55.391350 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11591 10:02:55.420840 /lava-11336442/1/../bin/lava-test-case
11592 10:02:55.457222 <8>[ 46.377354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11593 10:02:55.458020 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11595 10:02:56.520995 /lava-11336442/1/../bin/lava-test-case
11596 10:02:56.565158 <8>[ 47.485228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11597 10:02:56.565973 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11599 10:02:56.593806 /lava-11336442/1/../bin/lava-test-case
11600 10:02:56.634998 <8>[ 47.555574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11601 10:02:56.635843 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11603 10:02:56.682244 /lava-11336442/1/../bin/lava-test-case
11604 10:02:56.720851 <8>[ 47.641459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11605 10:02:56.721544 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11607 10:02:56.751042 /lava-11336442/1/../bin/lava-test-case
11608 10:02:56.789365 <8>[ 47.710088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11609 10:02:56.790149 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11611 10:02:56.838430 /lava-11336442/1/../bin/lava-test-case
11612 10:02:56.876933 <8>[ 47.797369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11613 10:02:56.877656 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11615 10:02:56.926453 /lava-11336442/1/../bin/lava-test-case
11616 10:02:56.968744 <8>[ 47.889314] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11617 10:02:56.969537 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11619 10:02:57.018135 /lava-11336442/1/../bin/lava-test-case
11620 10:02:57.062116 <8>[ 47.982539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11621 10:02:57.062971 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11623 10:02:57.091594 /lava-11336442/1/../bin/lava-test-case
11624 10:02:57.130509 <8>[ 48.051174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11625 10:02:57.131382 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11627 10:02:57.178115 /lava-11336442/1/../bin/lava-test-case
11628 10:02:57.216374 <8>[ 48.137052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11629 10:02:57.217232 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11631 10:02:57.264367 /lava-11336442/1/../bin/lava-test-case
11632 10:02:57.301986 <8>[ 48.222708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11633 10:02:57.302684 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11635 10:02:57.338077 /lava-11336442/1/../bin/lava-test-case
11636 10:02:57.376703 <8>[ 48.297274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11637 10:02:57.377525 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11639 10:02:57.423506 /lava-11336442/1/../bin/lava-test-case
11640 10:02:57.460482 <8>[ 48.380982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11641 10:02:57.461404 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11643 10:02:57.490998 /lava-11336442/1/../bin/lava-test-case
11644 10:02:57.530221 <8>[ 48.450882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11645 10:02:57.531028 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11647 10:02:57.576851 /lava-11336442/1/../bin/lava-test-case
11648 10:02:57.614632 <8>[ 48.534950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11649 10:02:57.615336 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11651 10:02:57.642601 /lava-11336442/1/../bin/lava-test-case
11652 10:02:57.680738 <8>[ 48.601417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11653 10:02:57.681535 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11655 10:02:57.732589 /lava-11336442/1/../bin/lava-test-case
11656 10:02:57.770738 <8>[ 48.691153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11657 10:02:57.771544 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11659 10:02:57.800598 /lava-11336442/1/../bin/lava-test-case
11660 10:02:57.840011 <8>[ 48.760642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11661 10:02:57.840813 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11663 10:02:57.886393 /lava-11336442/1/../bin/lava-test-case
11664 10:02:57.926372 <8>[ 48.846856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11665 10:02:57.927206 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11667 10:02:57.954064 /lava-11336442/1/../bin/lava-test-case
11668 10:02:57.993490 <8>[ 48.913929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11669 10:02:57.994364 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11671 10:02:58.039085 /lava-11336442/1/../bin/lava-test-case
11672 10:02:58.075835 <8>[ 48.996218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11673 10:02:58.076644 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11675 10:02:58.112318 /lava-11336442/1/../bin/lava-test-case
11676 10:02:58.150734 <8>[ 49.071083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11677 10:02:58.151547 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11679 10:02:59.208720 /lava-11336442/1/../bin/lava-test-case
11680 10:02:59.250552 <8>[ 50.171283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11681 10:02:59.251420 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11683 10:03:00.311388 /lava-11336442/1/../bin/lava-test-case
11684 10:03:00.350757 <8>[ 51.271605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11685 10:03:00.351544 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11687 10:03:00.377714 /lava-11336442/1/../bin/lava-test-case
11688 10:03:00.416742 <8>[ 51.337773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11689 10:03:00.417473 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11691 10:03:00.461204 /lava-11336442/1/../bin/lava-test-case
11692 10:03:00.497323 <8>[ 51.418433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11693 10:03:00.498134 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11695 10:03:00.527656 /lava-11336442/1/../bin/lava-test-case
11696 10:03:00.564034 <8>[ 51.484770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11697 10:03:00.564848 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11699 10:03:00.609075 /lava-11336442/1/../bin/lava-test-case
11700 10:03:00.642883 <8>[ 51.563860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11701 10:03:00.643588 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11703 10:03:00.677373 /lava-11336442/1/../bin/lava-test-case
11704 10:03:00.715474 <8>[ 51.636386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11705 10:03:00.716291 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11707 10:03:00.759361 /lava-11336442/1/../bin/lava-test-case
11708 10:03:00.790537 <8>[ 51.712055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11709 10:03:00.790811 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11711 10:03:00.815808 /lava-11336442/1/../bin/lava-test-case
11712 10:03:00.844389 <8>[ 51.765457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11713 10:03:00.845121 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11715 10:03:00.887149 /lava-11336442/1/../bin/lava-test-case
11716 10:03:00.922210 <8>[ 51.843815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11717 10:03:00.922475 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11719 10:03:00.948146 /lava-11336442/1/../bin/lava-test-case
11720 10:03:00.982416 <8>[ 51.903669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11721 10:03:00.982787 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11723 10:03:01.033687 /lava-11336442/1/../bin/lava-test-case
11724 10:03:01.073270 <8>[ 51.994393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11725 10:03:01.074049 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11727 10:03:01.109034 /lava-11336442/1/../bin/lava-test-case
11728 10:03:01.152245 <8>[ 52.073337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11729 10:03:01.152973 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11731 10:03:01.195995 /lava-11336442/1/../bin/lava-test-case
11732 10:03:01.232953 <8>[ 52.153818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11733 10:03:01.233787 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11735 10:03:01.260854 /lava-11336442/1/../bin/lava-test-case
11736 10:03:01.299596 <8>[ 52.220459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11737 10:03:01.300418 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11739 10:03:01.342886 /lava-11336442/1/../bin/lava-test-case
11740 10:03:01.384574 <8>[ 52.305407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11741 10:03:01.385442 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11743 10:03:01.413164 /lava-11336442/1/../bin/lava-test-case
11744 10:03:01.451323 <8>[ 52.372060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11745 10:03:01.452457 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11747 10:03:01.495992 /lava-11336442/1/../bin/lava-test-case
11748 10:03:01.531807 <8>[ 52.453156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11749 10:03:01.532310 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11751 10:03:01.560182 /lava-11336442/1/../bin/lava-test-case
11752 10:03:01.596621 <8>[ 52.517738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11753 10:03:01.597712 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11755 10:03:01.646730 /lava-11336442/1/../bin/lava-test-case
11756 10:03:01.686270 <8>[ 52.607321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11757 10:03:01.687295 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11759 10:03:01.719593 /lava-11336442/1/../bin/lava-test-case
11760 10:03:01.759160 <8>[ 52.679968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11761 10:03:01.759985 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11763 10:03:01.807995 /lava-11336442/1/../bin/lava-test-case
11764 10:03:01.847385 <8>[ 52.768481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11765 10:03:01.848425 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11767 10:03:02.893044 /lava-11336442/1/../bin/lava-test-case
11768 10:03:02.934773 <8>[ 53.855681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11769 10:03:02.935574 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11771 10:03:03.980928 /lava-11336442/1/../bin/lava-test-case
11772 10:03:04.022182 <8>[ 54.943548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11773 10:03:04.023078 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11774 10:03:04.023497 Bad test result: blocked
11775 10:03:04.050966 /lava-11336442/1/../bin/lava-test-case
11776 10:03:04.087874 <8>[ 55.008824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11777 10:03:04.088719 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11779 10:03:05.153285 /lava-11336442/1/../bin/lava-test-case
11780 10:03:05.198458 <8>[ 56.119689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11781 10:03:05.199293 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11783 10:03:05.226199 /lava-11336442/1/../bin/lava-test-case
11784 10:03:05.264923 <8>[ 56.186435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11785 10:03:05.265769 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11787 10:03:05.310561 /lava-11336442/1/../bin/lava-test-case
11788 10:03:05.351350 <8>[ 56.272407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11789 10:03:05.352344 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11791 10:03:05.396847 /lava-11336442/1/../bin/lava-test-case
11792 10:03:05.433760 <8>[ 56.355211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11793 10:03:05.434542 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11795 10:03:05.463644 /lava-11336442/1/../bin/lava-test-case
11796 10:03:05.502212 <8>[ 56.423127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11797 10:03:05.503111 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11799 10:03:05.553417 /lava-11336442/1/../bin/lava-test-case
11800 10:03:05.596446 <8>[ 56.518154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11801 10:03:05.597349 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11803 10:03:05.628136 /lava-11336442/1/../bin/lava-test-case
11804 10:03:05.665962 <8>[ 56.587281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11805 10:03:05.666761 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11807 10:03:06.729790 /lava-11336442/1/../bin/lava-test-case
11808 10:03:06.772631 <8>[ 57.693999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11809 10:03:06.773492 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11811 10:03:06.802669 /lava-11336442/1/../bin/lava-test-case
11812 10:03:06.842036 <8>[ 57.763520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11813 10:03:06.842732 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11815 10:03:07.906328 /lava-11336442/1/../bin/lava-test-case
11816 10:03:07.955860 <8>[ 58.877949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11817 10:03:07.956727 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11819 10:03:07.981025 /lava-11336442/1/../bin/lava-test-case
11820 10:03:08.019118 <8>[ 58.940928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11821 10:03:08.019932 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11823 10:03:09.079804 /lava-11336442/1/../bin/lava-test-case
11824 10:03:09.121139 <8>[ 60.043082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11825 10:03:09.121857 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11827 10:03:09.148539 /lava-11336442/1/../bin/lava-test-case
11828 10:03:09.184861 <8>[ 60.106945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11829 10:03:09.185650 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11831 10:03:10.244338 /lava-11336442/1/../bin/lava-test-case
11832 10:03:10.284809 <8>[ 61.207091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11833 10:03:10.285572 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11835 10:03:10.314822 /lava-11336442/1/../bin/lava-test-case
11836 10:03:10.353436 <8>[ 61.275030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11837 10:03:10.354210 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11839 10:03:10.395949 /lava-11336442/1/../bin/lava-test-case
11840 10:03:10.436806 <8>[ 61.358706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11841 10:03:10.437697 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11843 10:03:10.481257 /lava-11336442/1/../bin/lava-test-case
11844 10:03:10.519417 <8>[ 61.441627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11845 10:03:10.520114 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11847 10:03:10.548635 /lava-11336442/1/../bin/lava-test-case
11848 10:03:10.587968 <8>[ 61.509879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11849 10:03:10.588813 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11851 10:03:10.637989 /lava-11336442/1/../bin/lava-test-case
11852 10:03:10.678094 <8>[ 61.600351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11853 10:03:10.678355 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11855 10:03:10.703417 /lava-11336442/1/../bin/lava-test-case
11856 10:03:10.733707 <8>[ 61.656086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11857 10:03:10.733978 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11859 10:03:10.776102 /lava-11336442/1/../bin/lava-test-case
11860 10:03:10.812149 <8>[ 61.734389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11861 10:03:10.812829 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11863 10:03:10.841448 /lava-11336442/1/../bin/lava-test-case
11864 10:03:10.880837 <8>[ 61.802767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11865 10:03:10.881605 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11867 10:03:10.925014 /lava-11336442/1/../bin/lava-test-case
11868 10:03:10.962240 <8>[ 61.884169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11869 10:03:10.963026 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11871 10:03:10.978229 + <8>[ 61.903792] <LAVA_SIGNAL_ENDRUN 1_bootrr 11336442_1.6.2.3.5>
11872 10:03:10.978918 Received signal: <ENDRUN> 1_bootrr 11336442_1.6.2.3.5
11873 10:03:10.979321 Ending use of test pattern.
11874 10:03:10.979641 Ending test lava.1_bootrr (11336442_1.6.2.3.5), duration 31.91
11876 10:03:10.981499 set +x
11877 10:03:10.987159 <LAVA_TEST_RUNNER EXIT>
11878 10:03:10.987822 ok: lava_test_shell seems to have completed
11879 10:03:10.992796 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11880 10:03:10.993506 end: 4.1 lava-test-shell (duration 00:00:33) [common]
11881 10:03:10.993943 end: 4 lava-test-retry (duration 00:00:33) [common]
11882 10:03:10.994381 start: 5 finalize (timeout 00:07:12) [common]
11883 10:03:10.994825 start: 5.1 power-off (timeout 00:00:30) [common]
11884 10:03:10.995573 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11885 10:03:11.080850 >> Command sent successfully.
11886 10:03:11.085582 Returned 0 in 0 seconds
11887 10:03:11.186642 end: 5.1 power-off (duration 00:00:00) [common]
11889 10:03:11.188636 start: 5.2 read-feedback (timeout 00:07:12) [common]
11890 10:03:11.190124 Listened to connection for namespace 'common' for up to 1s
11891 10:03:11.191076 Listened to connection for namespace 'common' for up to 1s
11892 10:03:12.190764 Finalising connection for namespace 'common'
11893 10:03:12.191491 Disconnecting from shell: Finalise
11894 10:03:12.192013 / #
11895 10:03:12.293133 end: 5.2 read-feedback (duration 00:00:01) [common]
11896 10:03:12.293858 end: 5 finalize (duration 00:00:01) [common]
11897 10:03:12.294558 Cleaning after the job
11898 10:03:12.295162 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/ramdisk
11899 10:03:12.308108 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/kernel
11900 10:03:12.343247 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/dtb
11901 10:03:12.343626 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/nfsrootfs
11902 10:03:12.416196 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336442/tftp-deploy-pqke0388/modules
11903 10:03:12.422887 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11336442
11904 10:03:12.789350 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11336442
11905 10:03:12.789534 Job finished correctly