Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 25
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 43
- Errors: 1
1 10:00:06.403184 lava-dispatcher, installed at version: 2023.06
2 10:00:06.403395 start: 0 validate
3 10:00:06.403539 Start time: 2023-08-23 10:00:06.403532+00:00 (UTC)
4 10:00:06.403673 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:06.403822 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 10:00:06.679504 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:06.679791 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:00:06.948732 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:00:06.949496 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:00:45.292215 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:00:45.292899 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:00:45.820685 validate duration: 39.42
14 10:00:45.820950 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:00:45.821046 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:00:45.821132 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:00:45.821263 Not decompressing ramdisk as can be used compressed.
18 10:00:45.821348 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 10:00:45.821421 saving as /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/ramdisk/rootfs.cpio.gz
20 10:00:45.821486 total size: 34390042 (32 MB)
21 10:00:48.935974 progress 0 % (0 MB)
22 10:00:48.948452 progress 5 % (1 MB)
23 10:00:48.957761 progress 10 % (3 MB)
24 10:00:48.967231 progress 15 % (4 MB)
25 10:00:48.976065 progress 20 % (6 MB)
26 10:00:48.984864 progress 25 % (8 MB)
27 10:00:48.993491 progress 30 % (9 MB)
28 10:00:49.002357 progress 35 % (11 MB)
29 10:00:49.011162 progress 40 % (13 MB)
30 10:00:49.020204 progress 45 % (14 MB)
31 10:00:49.029183 progress 50 % (16 MB)
32 10:00:49.038117 progress 55 % (18 MB)
33 10:00:49.047055 progress 60 % (19 MB)
34 10:00:49.056282 progress 65 % (21 MB)
35 10:00:49.065203 progress 70 % (22 MB)
36 10:00:49.074199 progress 75 % (24 MB)
37 10:00:49.083246 progress 80 % (26 MB)
38 10:00:49.092150 progress 85 % (27 MB)
39 10:00:49.100895 progress 90 % (29 MB)
40 10:00:49.109624 progress 95 % (31 MB)
41 10:00:49.118220 progress 100 % (32 MB)
42 10:00:49.118401 32 MB downloaded in 3.30 s (9.95 MB/s)
43 10:00:49.118552 end: 1.1.1 http-download (duration 00:00:03) [common]
45 10:00:49.118838 end: 1.1 download-retry (duration 00:00:03) [common]
46 10:00:49.118925 start: 1.2 download-retry (timeout 00:09:57) [common]
47 10:00:49.119009 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 10:00:49.119151 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:00:49.119223 saving as /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/kernel/Image
50 10:00:49.119285 total size: 49220096 (46 MB)
51 10:00:49.119347 No compression specified
52 10:00:49.120476 progress 0 % (0 MB)
53 10:00:49.133302 progress 5 % (2 MB)
54 10:00:49.146263 progress 10 % (4 MB)
55 10:00:49.159158 progress 15 % (7 MB)
56 10:00:49.171921 progress 20 % (9 MB)
57 10:00:49.184644 progress 25 % (11 MB)
58 10:00:49.197395 progress 30 % (14 MB)
59 10:00:49.210062 progress 35 % (16 MB)
60 10:00:49.223090 progress 40 % (18 MB)
61 10:00:49.235857 progress 45 % (21 MB)
62 10:00:49.248878 progress 50 % (23 MB)
63 10:00:49.261758 progress 55 % (25 MB)
64 10:00:49.274509 progress 60 % (28 MB)
65 10:00:49.287275 progress 65 % (30 MB)
66 10:00:49.300006 progress 70 % (32 MB)
67 10:00:49.312870 progress 75 % (35 MB)
68 10:00:49.325667 progress 80 % (37 MB)
69 10:00:49.338479 progress 85 % (39 MB)
70 10:00:49.351335 progress 90 % (42 MB)
71 10:00:49.364202 progress 95 % (44 MB)
72 10:00:49.377011 progress 100 % (46 MB)
73 10:00:49.377163 46 MB downloaded in 0.26 s (182.03 MB/s)
74 10:00:49.377315 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:00:49.377546 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:00:49.377634 start: 1.3 download-retry (timeout 00:09:56) [common]
78 10:00:49.377727 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 10:00:49.377875 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:00:49.377946 saving as /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/dtb/mt8192-asurada-spherion-r0.dtb
81 10:00:49.378008 total size: 47278 (0 MB)
82 10:00:49.378070 No compression specified
83 10:00:49.386654 progress 69 % (0 MB)
84 10:00:49.386948 progress 100 % (0 MB)
85 10:00:49.387107 0 MB downloaded in 0.01 s (4.96 MB/s)
86 10:00:49.387232 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:00:49.387455 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:00:49.387540 start: 1.4 download-retry (timeout 00:09:56) [common]
90 10:00:49.387622 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 10:00:49.387744 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:00:49.387813 saving as /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/modules/modules.tar
93 10:00:49.387874 total size: 8617228 (8 MB)
94 10:00:49.387934 Using unxz to decompress xz
95 10:00:49.392232 progress 0 % (0 MB)
96 10:00:49.413764 progress 5 % (0 MB)
97 10:00:49.435786 progress 10 % (0 MB)
98 10:00:49.461674 progress 15 % (1 MB)
99 10:00:49.487051 progress 20 % (1 MB)
100 10:00:49.512332 progress 25 % (2 MB)
101 10:00:49.539183 progress 30 % (2 MB)
102 10:00:49.565923 progress 35 % (2 MB)
103 10:00:49.590584 progress 40 % (3 MB)
104 10:00:49.615038 progress 45 % (3 MB)
105 10:00:49.641370 progress 50 % (4 MB)
106 10:00:49.666623 progress 55 % (4 MB)
107 10:00:49.691122 progress 60 % (4 MB)
108 10:00:49.713526 progress 65 % (5 MB)
109 10:00:49.741183 progress 70 % (5 MB)
110 10:00:49.765243 progress 75 % (6 MB)
111 10:00:49.791411 progress 80 % (6 MB)
112 10:00:49.821139 progress 85 % (7 MB)
113 10:00:49.847716 progress 90 % (7 MB)
114 10:00:49.871942 progress 95 % (7 MB)
115 10:00:49.894759 progress 100 % (8 MB)
116 10:00:49.901188 8 MB downloaded in 0.51 s (16.01 MB/s)
117 10:00:49.901440 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:00:49.901703 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:00:49.901797 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 10:00:49.901892 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 10:00:49.901975 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:00:49.902066 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 10:00:49.902301 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1
125 10:00:49.902442 makedir: /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin
126 10:00:49.902556 makedir: /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/tests
127 10:00:49.902695 makedir: /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/results
128 10:00:49.902813 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-add-keys
129 10:00:49.902963 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-add-sources
130 10:00:49.903097 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-background-process-start
131 10:00:49.903226 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-background-process-stop
132 10:00:49.903352 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-common-functions
133 10:00:49.903476 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-echo-ipv4
134 10:00:49.903603 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-install-packages
135 10:00:49.903728 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-installed-packages
136 10:00:49.903853 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-os-build
137 10:00:49.903977 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-probe-channel
138 10:00:49.904100 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-probe-ip
139 10:00:49.904224 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-target-ip
140 10:00:49.904347 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-target-mac
141 10:00:49.904470 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-target-storage
142 10:00:49.904601 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-test-case
143 10:00:49.904731 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-test-event
144 10:00:49.904856 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-test-feedback
145 10:00:49.904981 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-test-raise
146 10:00:49.905107 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-test-reference
147 10:00:49.905231 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-test-runner
148 10:00:49.905355 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-test-set
149 10:00:49.905481 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-test-shell
150 10:00:49.905609 Updating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-install-packages (oe)
151 10:00:49.905764 Updating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/bin/lava-installed-packages (oe)
152 10:00:49.905887 Creating /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/environment
153 10:00:49.905997 LAVA metadata
154 10:00:49.906072 - LAVA_JOB_ID=11336431
155 10:00:49.906138 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:00:49.906271 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 10:00:49.906340 skipped lava-vland-overlay
158 10:00:49.906413 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:00:49.906490 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 10:00:49.906555 skipped lava-multinode-overlay
161 10:00:49.906654 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:00:49.906750 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 10:00:49.906828 Loading test definitions
164 10:00:49.906916 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 10:00:49.906989 Using /lava-11336431 at stage 0
166 10:00:49.907315 uuid=11336431_1.5.2.3.1 testdef=None
167 10:00:49.907404 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:00:49.907487 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 10:00:49.908014 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:00:49.908232 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 10:00:49.908841 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:00:49.909070 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 10:00:49.909658 runner path: /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/0/tests/0_cros-ec test_uuid 11336431_1.5.2.3.1
176 10:00:49.909811 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:00:49.910015 Creating lava-test-runner.conf files
179 10:00:49.910077 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11336431/lava-overlay-buku8yv1/lava-11336431/0 for stage 0
180 10:00:49.910166 - 0_cros-ec
181 10:00:49.910264 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:00:49.910350 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 10:00:49.917057 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:00:49.917165 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 10:00:49.917252 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:00:49.917338 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:00:49.917422 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 10:00:50.939939 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:00:50.940337 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 10:00:50.940459 extracting modules file /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11336431/extract-overlay-ramdisk-4bvf8eqy/ramdisk
191 10:00:51.172474 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:00:51.172644 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 10:00:51.172739 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11336431/compress-overlay-wnx9y4_n/overlay-1.5.2.4.tar.gz to ramdisk
194 10:00:51.172810 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11336431/compress-overlay-wnx9y4_n/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11336431/extract-overlay-ramdisk-4bvf8eqy/ramdisk
195 10:00:51.179617 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:00:51.179731 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 10:00:51.179822 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:00:51.179912 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 10:00:51.179988 Building ramdisk /var/lib/lava/dispatcher/tmp/11336431/extract-overlay-ramdisk-4bvf8eqy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11336431/extract-overlay-ramdisk-4bvf8eqy/ramdisk
200 10:00:51.931079 >> 270881 blocks
201 10:00:56.642286 rename /var/lib/lava/dispatcher/tmp/11336431/extract-overlay-ramdisk-4bvf8eqy/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/ramdisk/ramdisk.cpio.gz
202 10:00:56.642792 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 10:00:56.642928 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 10:00:56.643028 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 10:00:56.643144 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/kernel/Image'
206 10:01:09.069207 Returned 0 in 12 seconds
207 10:01:09.170239 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/kernel/image.itb
208 10:01:09.899189 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:01:09.899571 output: Created: Wed Aug 23 11:01:09 2023
210 10:01:09.899656 output: Image 0 (kernel-1)
211 10:01:09.899725 output: Description:
212 10:01:09.899787 output: Created: Wed Aug 23 11:01:09 2023
213 10:01:09.899850 output: Type: Kernel Image
214 10:01:09.899911 output: Compression: lzma compressed
215 10:01:09.899969 output: Data Size: 11037260 Bytes = 10778.57 KiB = 10.53 MiB
216 10:01:09.900027 output: Architecture: AArch64
217 10:01:09.900086 output: OS: Linux
218 10:01:09.900141 output: Load Address: 0x00000000
219 10:01:09.900194 output: Entry Point: 0x00000000
220 10:01:09.900246 output: Hash algo: crc32
221 10:01:09.900299 output: Hash value: 17b65cb3
222 10:01:09.900351 output: Image 1 (fdt-1)
223 10:01:09.900402 output: Description: mt8192-asurada-spherion-r0
224 10:01:09.900454 output: Created: Wed Aug 23 11:01:09 2023
225 10:01:09.900506 output: Type: Flat Device Tree
226 10:01:09.900558 output: Compression: uncompressed
227 10:01:09.900610 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 10:01:09.900662 output: Architecture: AArch64
229 10:01:09.900714 output: Hash algo: crc32
230 10:01:09.900765 output: Hash value: cc4352de
231 10:01:09.900817 output: Image 2 (ramdisk-1)
232 10:01:09.900868 output: Description: unavailable
233 10:01:09.900920 output: Created: Wed Aug 23 11:01:09 2023
234 10:01:09.900985 output: Type: RAMDisk Image
235 10:01:09.901045 output: Compression: Unknown Compression
236 10:01:09.901097 output: Data Size: 47513522 Bytes = 46399.92 KiB = 45.31 MiB
237 10:01:09.901166 output: Architecture: AArch64
238 10:01:09.901230 output: OS: Linux
239 10:01:09.901282 output: Load Address: unavailable
240 10:01:09.901333 output: Entry Point: unavailable
241 10:01:09.901385 output: Hash algo: crc32
242 10:01:09.901436 output: Hash value: 340f9d4f
243 10:01:09.901487 output: Default Configuration: 'conf-1'
244 10:01:09.901539 output: Configuration 0 (conf-1)
245 10:01:09.901590 output: Description: mt8192-asurada-spherion-r0
246 10:01:09.901642 output: Kernel: kernel-1
247 10:01:09.901693 output: Init Ramdisk: ramdisk-1
248 10:01:09.901744 output: FDT: fdt-1
249 10:01:09.901795 output: Loadables: kernel-1
250 10:01:09.901846 output:
251 10:01:09.902041 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 10:01:09.902138 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 10:01:09.902236 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 10:01:09.902329 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 10:01:09.902408 No LXC device requested
256 10:01:09.902485 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:01:09.902570 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 10:01:09.902684 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:01:09.902753 Checking files for TFTP limit of 4294967296 bytes.
260 10:01:09.903239 end: 1 tftp-deploy (duration 00:00:24) [common]
261 10:01:09.903385 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:01:09.903496 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:01:09.903619 substitutions:
264 10:01:09.903684 - {DTB}: 11336431/tftp-deploy-jgneaz_9/dtb/mt8192-asurada-spherion-r0.dtb
265 10:01:09.903747 - {INITRD}: 11336431/tftp-deploy-jgneaz_9/ramdisk/ramdisk.cpio.gz
266 10:01:09.903805 - {KERNEL}: 11336431/tftp-deploy-jgneaz_9/kernel/Image
267 10:01:09.903861 - {LAVA_MAC}: None
268 10:01:09.903915 - {PRESEED_CONFIG}: None
269 10:01:09.903969 - {PRESEED_LOCAL}: None
270 10:01:09.904022 - {RAMDISK}: 11336431/tftp-deploy-jgneaz_9/ramdisk/ramdisk.cpio.gz
271 10:01:09.904075 - {ROOT_PART}: None
272 10:01:09.904128 - {ROOT}: None
273 10:01:09.904181 - {SERVER_IP}: 192.168.201.1
274 10:01:09.904233 - {TEE}: None
275 10:01:09.904285 Parsed boot commands:
276 10:01:09.904337 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:01:09.904514 Parsed boot commands: tftpboot 192.168.201.1 11336431/tftp-deploy-jgneaz_9/kernel/image.itb 11336431/tftp-deploy-jgneaz_9/kernel/cmdline
278 10:01:09.904601 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:01:09.904683 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:01:09.904772 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:01:09.904857 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:01:09.904925 Not connected, no need to disconnect.
283 10:01:09.904997 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:01:09.905079 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:01:09.905146 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 10:01:09.909087 Setting prompt string to ['lava-test: # ']
287 10:01:09.909440 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:01:09.909544 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:01:09.909645 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:01:09.909779 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:01:09.910019 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 10:01:15.060927 >> Command sent successfully.
293 10:01:15.072709 Returned 0 in 5 seconds
294 10:01:15.173920 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:01:15.175437 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:01:15.175934 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:01:15.176353 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:01:15.176763 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:01:15.177192 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:01:15.178418 [Enter `^Ec?' for help]
302 10:01:15.338948
303 10:01:15.339502
304 10:01:15.339870 F0: 102B 0000
305 10:01:15.340217
306 10:01:15.340546 F3: 1001 0000 [0200]
307 10:01:15.340868
308 10:01:15.342306 F3: 1001 0000
309 10:01:15.342811
310 10:01:15.343182 F7: 102D 0000
311 10:01:15.343529
312 10:01:15.343856 F1: 0000 0000
313 10:01:15.345967
314 10:01:15.346382 V0: 0000 0000 [0001]
315 10:01:15.346753
316 10:01:15.347068 00: 0007 8000
317 10:01:15.347424
318 10:01:15.349585 01: 0000 0000
319 10:01:15.350009
320 10:01:15.350340 BP: 0C00 0209 [0000]
321 10:01:15.350683
322 10:01:15.353439 G0: 1182 0000
323 10:01:15.353855
324 10:01:15.354187 EC: 0000 0021 [4000]
325 10:01:15.354497
326 10:01:15.356807 S7: 0000 0000 [0000]
327 10:01:15.357236
328 10:01:15.357571 CC: 0000 0000 [0001]
329 10:01:15.357883
330 10:01:15.360648 T0: 0000 0040 [010F]
331 10:01:15.361068
332 10:01:15.361404 Jump to BL
333 10:01:15.361713
334 10:01:15.385513
335 10:01:15.386020
336 10:01:15.386355
337 10:01:15.392370 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:01:15.395797 ARM64: Exception handlers installed.
339 10:01:15.399569 ARM64: Testing exception
340 10:01:15.402749 ARM64: Done test exception
341 10:01:15.409895 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:01:15.420552 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:01:15.427551 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:01:15.438504 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:01:15.444720 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:01:15.451573 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:01:15.462059 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:01:15.468472 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:01:15.488897 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:01:15.491573 WDT: Last reset was cold boot
351 10:01:15.495261 SPI1(PAD0) initialized at 2873684 Hz
352 10:01:15.498785 SPI5(PAD0) initialized at 992727 Hz
353 10:01:15.501723 VBOOT: Loading verstage.
354 10:01:15.507855 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:01:15.511622 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:01:15.514240 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:01:15.518009 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:01:15.525996 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:01:15.532468 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:01:15.543513 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 10:01:15.544074
362 10:01:15.544441
363 10:01:15.553532 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:01:15.556633 ARM64: Exception handlers installed.
365 10:01:15.559736 ARM64: Testing exception
366 10:01:15.560199 ARM64: Done test exception
367 10:01:15.566801 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:01:15.569708 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:01:15.584379 Probing TPM: . done!
370 10:01:15.584932 TPM ready after 0 ms
371 10:01:15.591142 Connected to device vid:did:rid of 1ae0:0028:00
372 10:01:15.600630 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 10:01:15.670344 Initialized TPM device CR50 revision 0
374 10:01:15.682098 tlcl_send_startup: Startup return code is 0
375 10:01:15.682737 TPM: setup succeeded
376 10:01:15.693278 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:01:15.701985 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:01:15.708683 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:01:15.720830 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:01:15.723832 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:01:15.727555 in-header: 03 07 00 00 08 00 00 00
382 10:01:15.730954 in-data: aa e4 47 04 13 02 00 00
383 10:01:15.734529 Chrome EC: UHEPI supported
384 10:01:15.740553 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:01:15.744494 in-header: 03 ad 00 00 08 00 00 00
386 10:01:15.747390 in-data: 00 20 20 08 00 00 00 00
387 10:01:15.747950 Phase 1
388 10:01:15.750981 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:01:15.757782 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:01:15.764309 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:01:15.767388 Recovery requested (1009000e)
392 10:01:15.774756 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:01:15.779659 tlcl_extend: response is 0
394 10:01:15.788297 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:01:15.793265 tlcl_extend: response is 0
396 10:01:15.799962 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:01:15.820871 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 10:01:15.827758 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:01:15.828513
400 10:01:15.829130
401 10:01:15.838235 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:01:15.842744 ARM64: Exception handlers installed.
403 10:01:15.843529 ARM64: Testing exception
404 10:01:15.845447 ARM64: Done test exception
405 10:01:15.866118 pmic_efuse_setting: Set efuses in 11 msecs
406 10:01:15.869337 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:01:15.876196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:01:15.879072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:01:15.885909 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:01:15.889054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:01:15.895859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:01:15.898862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:01:15.905733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:01:15.909420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:01:15.911955 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:01:15.919061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:01:15.922817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:01:15.928846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:01:15.932461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:01:15.938874 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:01:15.945288 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:01:15.948487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:01:15.955677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:01:15.958828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:01:15.966731 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:01:15.973213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:01:15.976788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:01:15.983336 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:01:15.990732 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:01:15.994224 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:01:16.001294 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:01:16.004641 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:01:16.010766 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:01:16.014228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:01:16.021255 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:01:16.024343 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:01:16.031598 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:01:16.035168 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:01:16.042042 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:01:16.045099 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:01:16.048924 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:01:16.055542 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:01:16.058942 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:01:16.066256 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:01:16.069995 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:01:16.072515 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:01:16.079258 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:01:16.082963 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:01:16.085663 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:01:16.092685 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:01:16.095893 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:01:16.098846 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:01:16.102994 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:01:16.109508 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:01:16.112129 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:01:16.115257 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:01:16.122168 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:01:16.129235 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:01:16.135535 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:01:16.142288 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:01:16.149459 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:01:16.158936 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:01:16.162235 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:01:16.168964 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:01:16.172439 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:01:16.178948 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x26
467 10:01:16.185726 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:01:16.189316 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 10:01:16.192142 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:01:16.202906 [RTC]rtc_get_frequency_meter,154: input=15, output=836
471 10:01:16.212332 [RTC]rtc_get_frequency_meter,154: input=7, output=710
472 10:01:16.221737 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 10:01:16.231481 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 10:01:16.241604 [RTC]rtc_get_frequency_meter,154: input=12, output=789
475 10:01:16.250758 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 10:01:16.260615 [RTC]rtc_get_frequency_meter,154: input=13, output=804
477 10:01:16.263379 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 10:01:16.270920 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 10:01:16.274328 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:01:16.277637 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:01:16.283910 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:01:16.287360 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:01:16.291008 ADC[4]: Raw value=905988 ID=7
484 10:01:16.291567 ADC[3]: Raw value=212543 ID=1
485 10:01:16.293955 RAM Code: 0x71
486 10:01:16.297362 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:01:16.303798 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:01:16.310711 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:01:16.317049 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:01:16.320104 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:01:16.323334 in-header: 03 07 00 00 08 00 00 00
492 10:01:16.326802 in-data: aa e4 47 04 13 02 00 00
493 10:01:16.330546 Chrome EC: UHEPI supported
494 10:01:16.336896 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:01:16.340214 in-header: 03 dd 00 00 08 00 00 00
496 10:01:16.343534 in-data: 90 20 60 08 00 00 00 00
497 10:01:16.347003 MRC: failed to locate region type 0.
498 10:01:16.353806 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:01:16.357104 DRAM-K: Running full calibration
500 10:01:16.363875 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:01:16.364344 header.status = 0x0
502 10:01:16.366725 header.version = 0x6 (expected: 0x6)
503 10:01:16.370652 header.size = 0xd00 (expected: 0xd00)
504 10:01:16.373595 header.flags = 0x0
505 10:01:16.380500 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:01:16.397313 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 10:01:16.403526 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:01:16.407276 dram_init: ddr_geometry: 2
509 10:01:16.410786 [EMI] MDL number = 2
510 10:01:16.411343 [EMI] Get MDL freq = 0
511 10:01:16.413448 dram_init: ddr_type: 0
512 10:01:16.413891 is_discrete_lpddr4: 1
513 10:01:16.416911 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:01:16.417468
515 10:01:16.417840
516 10:01:16.420444 [Bian_co] ETT version 0.0.0.1
517 10:01:16.426764 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:01:16.427327
519 10:01:16.430514 dramc_set_vcore_voltage set vcore to 650000
520 10:01:16.431134 Read voltage for 800, 4
521 10:01:16.433955 Vio18 = 0
522 10:01:16.434527 Vcore = 650000
523 10:01:16.434948 Vdram = 0
524 10:01:16.436842 Vddq = 0
525 10:01:16.437410 Vmddr = 0
526 10:01:16.439953 dram_init: config_dvfs: 1
527 10:01:16.443657 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:01:16.450440 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:01:16.453417 [SwImpedanceCal] DRVP=8, DRVN=15, ODTN=9
530 10:01:16.456943 freq_region=0, Reg: DRVP=8, DRVN=15, ODTN=9
531 10:01:16.460205 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 10:01:16.463653 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 10:01:16.466467 MEM_TYPE=3, freq_sel=18
534 10:01:16.470829 sv_algorithm_assistance_LP4_1600
535 10:01:16.473468 ============ PULL DRAM RESETB DOWN ============
536 10:01:16.480037 ========== PULL DRAM RESETB DOWN end =========
537 10:01:16.483814 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:01:16.486547 ===================================
539 10:01:16.490401 LPDDR4 DRAM CONFIGURATION
540 10:01:16.493567 ===================================
541 10:01:16.494138 EX_ROW_EN[0] = 0x0
542 10:01:16.497127 EX_ROW_EN[1] = 0x0
543 10:01:16.497694 LP4Y_EN = 0x0
544 10:01:16.500411 WORK_FSP = 0x0
545 10:01:16.500981 WL = 0x2
546 10:01:16.503431 RL = 0x2
547 10:01:16.503897 BL = 0x2
548 10:01:16.506430 RPST = 0x0
549 10:01:16.507087 RD_PRE = 0x0
550 10:01:16.510011 WR_PRE = 0x1
551 10:01:16.510579 WR_PST = 0x0
552 10:01:16.512875 DBI_WR = 0x0
553 10:01:16.516353 DBI_RD = 0x0
554 10:01:16.516818 OTF = 0x1
555 10:01:16.519468 ===================================
556 10:01:16.523259 ===================================
557 10:01:16.523842 ANA top config
558 10:01:16.526475 ===================================
559 10:01:16.530010 DLL_ASYNC_EN = 0
560 10:01:16.533705 ALL_SLAVE_EN = 1
561 10:01:16.536804 NEW_RANK_MODE = 1
562 10:01:16.539901 DLL_IDLE_MODE = 1
563 10:01:16.540406 LP45_APHY_COMB_EN = 1
564 10:01:16.542660 TX_ODT_DIS = 1
565 10:01:16.546258 NEW_8X_MODE = 1
566 10:01:16.549404 ===================================
567 10:01:16.552772 ===================================
568 10:01:16.555970 data_rate = 1600
569 10:01:16.559697 CKR = 1
570 10:01:16.560254 DQ_P2S_RATIO = 8
571 10:01:16.562559 ===================================
572 10:01:16.566165 CA_P2S_RATIO = 8
573 10:01:16.569577 DQ_CA_OPEN = 0
574 10:01:16.572559 DQ_SEMI_OPEN = 0
575 10:01:16.576219 CA_SEMI_OPEN = 0
576 10:01:16.579365 CA_FULL_RATE = 0
577 10:01:16.579969 DQ_CKDIV4_EN = 1
578 10:01:16.582962 CA_CKDIV4_EN = 1
579 10:01:16.586163 CA_PREDIV_EN = 0
580 10:01:16.589297 PH8_DLY = 0
581 10:01:16.592630 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:01:16.593308 DQ_AAMCK_DIV = 4
583 10:01:16.595784 CA_AAMCK_DIV = 4
584 10:01:16.599078 CA_ADMCK_DIV = 4
585 10:01:16.602551 DQ_TRACK_CA_EN = 0
586 10:01:16.605517 CA_PICK = 800
587 10:01:16.608620 CA_MCKIO = 800
588 10:01:16.612355 MCKIO_SEMI = 0
589 10:01:16.612472 PLL_FREQ = 3068
590 10:01:16.615601 DQ_UI_PI_RATIO = 32
591 10:01:16.619040 CA_UI_PI_RATIO = 0
592 10:01:16.622573 ===================================
593 10:01:16.625779 ===================================
594 10:01:16.628817 memory_type:LPDDR4
595 10:01:16.632011 GP_NUM : 10
596 10:01:16.632083 SRAM_EN : 1
597 10:01:16.635620 MD32_EN : 0
598 10:01:16.638554 ===================================
599 10:01:16.638685 [ANA_INIT] >>>>>>>>>>>>>>
600 10:01:16.642303 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:01:16.645701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:01:16.648446 ===================================
603 10:01:16.652158 data_rate = 1600,PCW = 0X7600
604 10:01:16.655128 ===================================
605 10:01:16.658504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:01:16.664981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:01:16.672129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:01:16.675373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:01:16.678555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:01:16.681792 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:01:16.685380 [ANA_INIT] flow start
612 10:01:16.685483 [ANA_INIT] PLL >>>>>>>>
613 10:01:16.688285 [ANA_INIT] PLL <<<<<<<<
614 10:01:16.691827 [ANA_INIT] MIDPI >>>>>>>>
615 10:01:16.691936 [ANA_INIT] MIDPI <<<<<<<<
616 10:01:16.694848 [ANA_INIT] DLL >>>>>>>>
617 10:01:16.698316 [ANA_INIT] flow end
618 10:01:16.701319 ============ LP4 DIFF to SE enter ============
619 10:01:16.705220 ============ LP4 DIFF to SE exit ============
620 10:01:16.708289 [ANA_INIT] <<<<<<<<<<<<<
621 10:01:16.711671 [Flow] Enable top DCM control >>>>>
622 10:01:16.715022 [Flow] Enable top DCM control <<<<<
623 10:01:16.718115 Enable DLL master slave shuffle
624 10:01:16.721498 ==============================================================
625 10:01:16.724645 Gating Mode config
626 10:01:16.731387 ==============================================================
627 10:01:16.731479 Config description:
628 10:01:16.741932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:01:16.747788 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:01:16.754599 SELPH_MODE 0: By rank 1: By Phase
631 10:01:16.757979 ==============================================================
632 10:01:16.761246 GAT_TRACK_EN = 1
633 10:01:16.764456 RX_GATING_MODE = 2
634 10:01:16.767932 RX_GATING_TRACK_MODE = 2
635 10:01:16.771208 SELPH_MODE = 1
636 10:01:16.774765 PICG_EARLY_EN = 1
637 10:01:16.777618 VALID_LAT_VALUE = 1
638 10:01:16.780697 ==============================================================
639 10:01:16.784423 Enter into Gating configuration >>>>
640 10:01:16.787654 Exit from Gating configuration <<<<
641 10:01:16.791289 Enter into DVFS_PRE_config >>>>>
642 10:01:16.804797 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:01:16.804908 Exit from DVFS_PRE_config <<<<<
644 10:01:16.808433 Enter into PICG configuration >>>>
645 10:01:16.812163 Exit from PICG configuration <<<<
646 10:01:16.815821 [RX_INPUT] configuration >>>>>
647 10:01:16.820026 [RX_INPUT] configuration <<<<<
648 10:01:16.823510 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:01:16.830913 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:01:16.834244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:01:16.841600 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:01:16.848812 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:01:16.852401 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:01:16.855875 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:01:16.862552 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:01:16.866339 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:01:16.870054 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:01:16.873480 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:01:16.876958 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:01:16.880956 ===================================
661 10:01:16.884529 LPDDR4 DRAM CONFIGURATION
662 10:01:16.888374 ===================================
663 10:01:16.888490 EX_ROW_EN[0] = 0x0
664 10:01:16.892139 EX_ROW_EN[1] = 0x0
665 10:01:16.892221 LP4Y_EN = 0x0
666 10:01:16.895667 WORK_FSP = 0x0
667 10:01:16.895749 WL = 0x2
668 10:01:16.899282 RL = 0x2
669 10:01:16.899364 BL = 0x2
670 10:01:16.902873 RPST = 0x0
671 10:01:16.902955 RD_PRE = 0x0
672 10:01:16.906098 WR_PRE = 0x1
673 10:01:16.906179 WR_PST = 0x0
674 10:01:16.910037 DBI_WR = 0x0
675 10:01:16.910119 DBI_RD = 0x0
676 10:01:16.913567 OTF = 0x1
677 10:01:16.913650 ===================================
678 10:01:16.920667 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:01:16.924371 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:01:16.928176 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:01:16.932107 ===================================
682 10:01:16.932224 LPDDR4 DRAM CONFIGURATION
683 10:01:16.935993 ===================================
684 10:01:16.938970 EX_ROW_EN[0] = 0x10
685 10:01:16.939052 EX_ROW_EN[1] = 0x0
686 10:01:16.943007 LP4Y_EN = 0x0
687 10:01:16.943121 WORK_FSP = 0x0
688 10:01:16.946766 WL = 0x2
689 10:01:16.946860 RL = 0x2
690 10:01:16.950756 BL = 0x2
691 10:01:16.950838 RPST = 0x0
692 10:01:16.954055 RD_PRE = 0x0
693 10:01:16.954137 WR_PRE = 0x1
694 10:01:16.957680 WR_PST = 0x0
695 10:01:16.957762 DBI_WR = 0x0
696 10:01:16.962069 DBI_RD = 0x0
697 10:01:16.962151 OTF = 0x1
698 10:01:16.965255 ===================================
699 10:01:16.971465 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:01:16.975221 nWR fixed to 40
701 10:01:16.978102 [ModeRegInit_LP4] CH0 RK0
702 10:01:16.978184 [ModeRegInit_LP4] CH0 RK1
703 10:01:16.981677 [ModeRegInit_LP4] CH1 RK0
704 10:01:16.985065 [ModeRegInit_LP4] CH1 RK1
705 10:01:16.985152 match AC timing 13
706 10:01:16.991609 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:01:16.995069 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:01:16.998266 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:01:17.004827 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:01:17.008421 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:01:17.008503 [EMI DOE] emi_dcm 0
712 10:01:17.015122 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:01:17.015205 ==
714 10:01:17.018443 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:01:17.021376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:01:17.021459 ==
717 10:01:17.029209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:01:17.032338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:01:17.042324 [CA 0] Center 37 (6~68) winsize 63
720 10:01:17.045827 [CA 1] Center 37 (6~68) winsize 63
721 10:01:17.048736 [CA 2] Center 34 (4~65) winsize 62
722 10:01:17.051964 [CA 3] Center 34 (4~65) winsize 62
723 10:01:17.055396 [CA 4] Center 33 (3~64) winsize 62
724 10:01:17.058844 [CA 5] Center 33 (3~64) winsize 62
725 10:01:17.058926
726 10:01:17.061946 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 10:01:17.062028
728 10:01:17.065496 [CATrainingPosCal] consider 1 rank data
729 10:01:17.069083 u2DelayCellTimex100 = 270/100 ps
730 10:01:17.071852 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 10:01:17.078864 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 10:01:17.082095 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 10:01:17.085030 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 10:01:17.088873 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 10:01:17.091932 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 10:01:17.092014
737 10:01:17.094958 CA PerBit enable=1, Macro0, CA PI delay=33
738 10:01:17.095040
739 10:01:17.098272 [CBTSetCACLKResult] CA Dly = 33
740 10:01:17.101444 CS Dly: 6 (0~37)
741 10:01:17.101526 ==
742 10:01:17.104953 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:01:17.108707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:01:17.108856 ==
745 10:01:17.115040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:01:17.118063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:01:17.128230 [CA 0] Center 37 (6~68) winsize 63
748 10:01:17.131863 [CA 1] Center 37 (7~68) winsize 62
749 10:01:17.135069 [CA 2] Center 34 (4~65) winsize 62
750 10:01:17.138604 [CA 3] Center 34 (4~65) winsize 62
751 10:01:17.141884 [CA 4] Center 33 (3~64) winsize 62
752 10:01:17.145753 [CA 5] Center 33 (2~64) winsize 63
753 10:01:17.145834
754 10:01:17.149135 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 10:01:17.149218
756 10:01:17.152758 [CATrainingPosCal] consider 2 rank data
757 10:01:17.156302 u2DelayCellTimex100 = 270/100 ps
758 10:01:17.160092 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 10:01:17.163930 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 10:01:17.167105 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 10:01:17.170405 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 10:01:17.173849 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 10:01:17.177473 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 10:01:17.177556
765 10:01:17.180455 CA PerBit enable=1, Macro0, CA PI delay=33
766 10:01:17.180537
767 10:01:17.183787 [CBTSetCACLKResult] CA Dly = 33
768 10:01:17.187031 CS Dly: 6 (0~38)
769 10:01:17.187112
770 10:01:17.190206 ----->DramcWriteLeveling(PI) begin...
771 10:01:17.190289 ==
772 10:01:17.193703 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:01:17.197130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:01:17.197213 ==
775 10:01:17.200385 Write leveling (Byte 0): 35 => 35
776 10:01:17.203340 Write leveling (Byte 1): 28 => 28
777 10:01:17.206899 DramcWriteLeveling(PI) end<-----
778 10:01:17.206981
779 10:01:17.207045 ==
780 10:01:17.210313 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:01:17.213474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:01:17.213557 ==
783 10:01:17.217250 [Gating] SW mode calibration
784 10:01:17.223622 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:01:17.229920 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:01:17.233554 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 10:01:17.240056 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 10:01:17.243543 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 10:01:17.246551 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:01:17.253349 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:01:17.256763 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:01:17.260174 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:01:17.266413 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:01:17.269841 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:01:17.272897 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:01:17.280021 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:01:17.283067 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:01:17.286060 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:01:17.292819 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:01:17.295958 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:01:17.299469 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:01:17.302912 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:01:17.309290 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 10:01:17.312650 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 10:01:17.316020 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 10:01:17.322516 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:01:17.326040 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:01:17.329629 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:01:17.336075 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:01:17.339220 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:01:17.342530 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 10:01:17.349507 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
813 10:01:17.353002 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
814 10:01:17.356208 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:01:17.362744 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:01:17.365638 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:01:17.368955 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:01:17.375814 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 10:01:17.379473 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
820 10:01:17.382461 0 10 8 | B1->B0 | 3333 2828 | 0 0 | (0 0) (0 0)
821 10:01:17.388933 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
822 10:01:17.392616 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:01:17.395680 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:01:17.402772 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:01:17.405835 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:01:17.409281 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 10:01:17.415702 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
828 10:01:17.419386 0 11 8 | B1->B0 | 2424 3737 | 1 1 | (0 0) (0 0)
829 10:01:17.422803 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
830 10:01:17.428790 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:01:17.432412 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:01:17.435875 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:01:17.439104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:01:17.445617 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:01:17.449050 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 10:01:17.452648 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 10:01:17.458847 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 10:01:17.461840 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:01:17.465278 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:01:17.472190 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:01:17.475406 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:01:17.478447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:01:17.485495 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:01:17.488386 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:01:17.491882 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:01:17.498983 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:01:17.501841 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:01:17.505410 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:01:17.513091 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:01:17.516288 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:01:17.520114 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 10:01:17.523425 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 10:01:17.530897 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 10:01:17.531021 Total UI for P1: 0, mck2ui 16
855 10:01:17.534535 best dqsien dly found for B0: ( 0, 14, 8)
856 10:01:17.538263 Total UI for P1: 0, mck2ui 16
857 10:01:17.541357 best dqsien dly found for B1: ( 0, 14, 10)
858 10:01:17.544805 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 10:01:17.548463 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 10:01:17.548545
861 10:01:17.552453 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 10:01:17.555805 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 10:01:17.559204 [Gating] SW calibration Done
864 10:01:17.559286 ==
865 10:01:17.562885 Dram Type= 6, Freq= 0, CH_0, rank 0
866 10:01:17.566798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 10:01:17.566881 ==
868 10:01:17.566946 RX Vref Scan: 0
869 10:01:17.570760
870 10:01:17.570841 RX Vref 0 -> 0, step: 1
871 10:01:17.570907
872 10:01:17.574233 RX Delay -130 -> 252, step: 16
873 10:01:17.577674 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 10:01:17.581104 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 10:01:17.584571 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 10:01:17.587736 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 10:01:17.594481 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 10:01:17.598086 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 10:01:17.601209 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 10:01:17.604660 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 10:01:17.610923 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 10:01:17.614439 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
883 10:01:17.617889 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
884 10:01:17.621645 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
885 10:01:17.625510 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
886 10:01:17.629060 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 10:01:17.632771 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 10:01:17.636623 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 10:01:17.636721 ==
890 10:01:17.640408 Dram Type= 6, Freq= 0, CH_0, rank 0
891 10:01:17.643720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 10:01:17.647717 ==
893 10:01:17.647801 DQS Delay:
894 10:01:17.647866 DQS0 = 0, DQS1 = 0
895 10:01:17.650901 DQM Delay:
896 10:01:17.650981 DQM0 = 87, DQM1 = 71
897 10:01:17.651045 DQ Delay:
898 10:01:17.654291 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 10:01:17.657796 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
900 10:01:17.661042 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
901 10:01:17.663979 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
902 10:01:17.664060
903 10:01:17.664124
904 10:01:17.667397 ==
905 10:01:17.670552 Dram Type= 6, Freq= 0, CH_0, rank 0
906 10:01:17.674039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 10:01:17.674121 ==
908 10:01:17.674185
909 10:01:17.674245
910 10:01:17.677592 TX Vref Scan disable
911 10:01:17.677672 == TX Byte 0 ==
912 10:01:17.683833 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
913 10:01:17.687158 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
914 10:01:17.687240 == TX Byte 1 ==
915 10:01:17.693966 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 10:01:17.697395 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 10:01:17.697476 ==
918 10:01:17.700816 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:01:17.704154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:01:17.704235 ==
921 10:01:17.718190 TX Vref=22, minBit 1, minWin=27, winSum=439
922 10:01:17.721216 TX Vref=24, minBit 2, minWin=27, winSum=439
923 10:01:17.724681 TX Vref=26, minBit 5, minWin=27, winSum=444
924 10:01:17.728290 TX Vref=28, minBit 2, minWin=27, winSum=441
925 10:01:17.731978 TX Vref=30, minBit 9, minWin=26, winSum=446
926 10:01:17.738094 TX Vref=32, minBit 11, minWin=26, winSum=443
927 10:01:17.741392 [TxChooseVref] Worse bit 5, Min win 27, Win sum 444, Final Vref 26
928 10:01:17.741474
929 10:01:17.745072 Final TX Range 1 Vref 26
930 10:01:17.745152
931 10:01:17.745216 ==
932 10:01:17.747868 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:01:17.751537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:01:17.751619 ==
935 10:01:17.755040
936 10:01:17.755124
937 10:01:17.755222 TX Vref Scan disable
938 10:01:17.758035 == TX Byte 0 ==
939 10:01:17.761837 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 10:01:17.764881 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 10:01:17.768074 == TX Byte 1 ==
942 10:01:17.771412 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 10:01:17.774936 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 10:01:17.778140
945 10:01:17.778225 [DATLAT]
946 10:01:17.778290 Freq=800, CH0 RK0
947 10:01:17.778349
948 10:01:17.781645 DATLAT Default: 0xa
949 10:01:17.781726 0, 0xFFFF, sum = 0
950 10:01:17.784711 1, 0xFFFF, sum = 0
951 10:01:17.784793 2, 0xFFFF, sum = 0
952 10:01:17.788452 3, 0xFFFF, sum = 0
953 10:01:17.788533 4, 0xFFFF, sum = 0
954 10:01:17.791243 5, 0xFFFF, sum = 0
955 10:01:17.794700 6, 0xFFFF, sum = 0
956 10:01:17.794782 7, 0xFFFF, sum = 0
957 10:01:17.798123 8, 0xFFFF, sum = 0
958 10:01:17.798204 9, 0x0, sum = 1
959 10:01:17.798269 10, 0x0, sum = 2
960 10:01:17.801607 11, 0x0, sum = 3
961 10:01:17.801688 12, 0x0, sum = 4
962 10:01:17.804697 best_step = 10
963 10:01:17.804777
964 10:01:17.804841 ==
965 10:01:17.808102 Dram Type= 6, Freq= 0, CH_0, rank 0
966 10:01:17.811112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 10:01:17.811193 ==
968 10:01:17.814558 RX Vref Scan: 1
969 10:01:17.814685
970 10:01:17.814749 Set Vref Range= 32 -> 127
971 10:01:17.818090
972 10:01:17.818170 RX Vref 32 -> 127, step: 1
973 10:01:17.818234
974 10:01:17.821134 RX Delay -111 -> 252, step: 8
975 10:01:17.821214
976 10:01:17.824696 Set Vref, RX VrefLevel [Byte0]: 32
977 10:01:17.827659 [Byte1]: 32
978 10:01:17.827739
979 10:01:17.831556 Set Vref, RX VrefLevel [Byte0]: 33
980 10:01:17.834432 [Byte1]: 33
981 10:01:17.838675
982 10:01:17.838755 Set Vref, RX VrefLevel [Byte0]: 34
983 10:01:17.841799 [Byte1]: 34
984 10:01:17.846387
985 10:01:17.846493 Set Vref, RX VrefLevel [Byte0]: 35
986 10:01:17.849968 [Byte1]: 35
987 10:01:17.853767
988 10:01:17.853847 Set Vref, RX VrefLevel [Byte0]: 36
989 10:01:17.857191 [Byte1]: 36
990 10:01:17.861985
991 10:01:17.862065 Set Vref, RX VrefLevel [Byte0]: 37
992 10:01:17.864798 [Byte1]: 37
993 10:01:17.869261
994 10:01:17.869340 Set Vref, RX VrefLevel [Byte0]: 38
995 10:01:17.872924 [Byte1]: 38
996 10:01:17.876793
997 10:01:17.876899 Set Vref, RX VrefLevel [Byte0]: 39
998 10:01:17.880062 [Byte1]: 39
999 10:01:17.884241
1000 10:01:17.884321 Set Vref, RX VrefLevel [Byte0]: 40
1001 10:01:17.887722 [Byte1]: 40
1002 10:01:17.892055
1003 10:01:17.892135 Set Vref, RX VrefLevel [Byte0]: 41
1004 10:01:17.895870 [Byte1]: 41
1005 10:01:17.899672
1006 10:01:17.899752 Set Vref, RX VrefLevel [Byte0]: 42
1007 10:01:17.903062 [Byte1]: 42
1008 10:01:17.907688
1009 10:01:17.907767 Set Vref, RX VrefLevel [Byte0]: 43
1010 10:01:17.910750 [Byte1]: 43
1011 10:01:17.914797
1012 10:01:17.914878 Set Vref, RX VrefLevel [Byte0]: 44
1013 10:01:17.918154 [Byte1]: 44
1014 10:01:17.922904
1015 10:01:17.923013 Set Vref, RX VrefLevel [Byte0]: 45
1016 10:01:17.926220 [Byte1]: 45
1017 10:01:17.930301
1018 10:01:17.930413 Set Vref, RX VrefLevel [Byte0]: 46
1019 10:01:17.933947 [Byte1]: 46
1020 10:01:17.938470
1021 10:01:17.938551 Set Vref, RX VrefLevel [Byte0]: 47
1022 10:01:17.941497 [Byte1]: 47
1023 10:01:17.945756
1024 10:01:17.945837 Set Vref, RX VrefLevel [Byte0]: 48
1025 10:01:17.949207 [Byte1]: 48
1026 10:01:17.953399
1027 10:01:17.953479 Set Vref, RX VrefLevel [Byte0]: 49
1028 10:01:17.956621 [Byte1]: 49
1029 10:01:17.960836
1030 10:01:17.960916 Set Vref, RX VrefLevel [Byte0]: 50
1031 10:01:17.964215 [Byte1]: 50
1032 10:01:17.968951
1033 10:01:17.969031 Set Vref, RX VrefLevel [Byte0]: 51
1034 10:01:17.972045 [Byte1]: 51
1035 10:01:17.976162
1036 10:01:17.976241 Set Vref, RX VrefLevel [Byte0]: 52
1037 10:01:17.979334 [Byte1]: 52
1038 10:01:17.984065
1039 10:01:17.984145 Set Vref, RX VrefLevel [Byte0]: 53
1040 10:01:17.987350 [Byte1]: 53
1041 10:01:17.991646
1042 10:01:17.991725 Set Vref, RX VrefLevel [Byte0]: 54
1043 10:01:17.995040 [Byte1]: 54
1044 10:01:17.999822
1045 10:01:17.999901 Set Vref, RX VrefLevel [Byte0]: 55
1046 10:01:18.002247 [Byte1]: 55
1047 10:01:18.007080
1048 10:01:18.007159 Set Vref, RX VrefLevel [Byte0]: 56
1049 10:01:18.010456 [Byte1]: 56
1050 10:01:18.014548
1051 10:01:18.014636 Set Vref, RX VrefLevel [Byte0]: 57
1052 10:01:18.017615 [Byte1]: 57
1053 10:01:18.022238
1054 10:01:18.022316 Set Vref, RX VrefLevel [Byte0]: 58
1055 10:01:18.025446 [Byte1]: 58
1056 10:01:18.029671
1057 10:01:18.029749 Set Vref, RX VrefLevel [Byte0]: 59
1058 10:01:18.033107 [Byte1]: 59
1059 10:01:18.037474
1060 10:01:18.037553 Set Vref, RX VrefLevel [Byte0]: 60
1061 10:01:18.040925 [Byte1]: 60
1062 10:01:18.045335
1063 10:01:18.045413 Set Vref, RX VrefLevel [Byte0]: 61
1064 10:01:18.048687 [Byte1]: 61
1065 10:01:18.052742
1066 10:01:18.052820 Set Vref, RX VrefLevel [Byte0]: 62
1067 10:01:18.055930 [Byte1]: 62
1068 10:01:18.060297
1069 10:01:18.060375 Set Vref, RX VrefLevel [Byte0]: 63
1070 10:01:18.063616 [Byte1]: 63
1071 10:01:18.068448
1072 10:01:18.068526 Set Vref, RX VrefLevel [Byte0]: 64
1073 10:01:18.072146 [Byte1]: 64
1074 10:01:18.075444
1075 10:01:18.075524 Set Vref, RX VrefLevel [Byte0]: 65
1076 10:01:18.078716 [Byte1]: 65
1077 10:01:18.083496
1078 10:01:18.083579 Set Vref, RX VrefLevel [Byte0]: 66
1079 10:01:18.086809 [Byte1]: 66
1080 10:01:18.091115
1081 10:01:18.091193 Set Vref, RX VrefLevel [Byte0]: 67
1082 10:01:18.093975 [Byte1]: 67
1083 10:01:18.098532
1084 10:01:18.098668 Set Vref, RX VrefLevel [Byte0]: 68
1085 10:01:18.102235 [Byte1]: 68
1086 10:01:18.106143
1087 10:01:18.106247 Set Vref, RX VrefLevel [Byte0]: 69
1088 10:01:18.109721 [Byte1]: 69
1089 10:01:18.113758
1090 10:01:18.113837 Set Vref, RX VrefLevel [Byte0]: 70
1091 10:01:18.117148 [Byte1]: 70
1092 10:01:18.121255
1093 10:01:18.121333 Set Vref, RX VrefLevel [Byte0]: 71
1094 10:01:18.124817 [Byte1]: 71
1095 10:01:18.129498
1096 10:01:18.129577 Set Vref, RX VrefLevel [Byte0]: 72
1097 10:01:18.132808 [Byte1]: 72
1098 10:01:18.137305
1099 10:01:18.137383 Set Vref, RX VrefLevel [Byte0]: 73
1100 10:01:18.140279 [Byte1]: 73
1101 10:01:18.144867
1102 10:01:18.144945 Set Vref, RX VrefLevel [Byte0]: 74
1103 10:01:18.148291 [Byte1]: 74
1104 10:01:18.152444
1105 10:01:18.152523 Set Vref, RX VrefLevel [Byte0]: 75
1106 10:01:18.155820 [Byte1]: 75
1107 10:01:18.159947
1108 10:01:18.160026 Set Vref, RX VrefLevel [Byte0]: 76
1109 10:01:18.163263 [Byte1]: 76
1110 10:01:18.167402
1111 10:01:18.167480 Set Vref, RX VrefLevel [Byte0]: 77
1112 10:01:18.170976 [Byte1]: 77
1113 10:01:18.175562
1114 10:01:18.175641 Set Vref, RX VrefLevel [Byte0]: 78
1115 10:01:18.179074 [Byte1]: 78
1116 10:01:18.183110
1117 10:01:18.183189 Set Vref, RX VrefLevel [Byte0]: 79
1118 10:01:18.186365 [Byte1]: 79
1119 10:01:18.190528
1120 10:01:18.190670 Set Vref, RX VrefLevel [Byte0]: 80
1121 10:01:18.193808 [Byte1]: 80
1122 10:01:18.197941
1123 10:01:18.198046 Final RX Vref Byte 0 = 65 to rank0
1124 10:01:18.201967 Final RX Vref Byte 1 = 60 to rank0
1125 10:01:18.205545 Final RX Vref Byte 0 = 65 to rank1
1126 10:01:18.208963 Final RX Vref Byte 1 = 60 to rank1==
1127 10:01:18.212674 Dram Type= 6, Freq= 0, CH_0, rank 0
1128 10:01:18.216172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 10:01:18.216252 ==
1130 10:01:18.216319 DQS Delay:
1131 10:01:18.219933 DQS0 = 0, DQS1 = 0
1132 10:01:18.220041 DQM Delay:
1133 10:01:18.223919 DQM0 = 87, DQM1 = 76
1134 10:01:18.223998 DQ Delay:
1135 10:01:18.226907 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1136 10:01:18.230815 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1137 10:01:18.234516 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
1138 10:01:18.238046 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1139 10:01:18.238126
1140 10:01:18.238189
1141 10:01:18.244203 [DQSOSCAuto] RK0, (LSB)MR18= 0x4325, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1142 10:01:18.247684 CH0 RK0: MR19=606, MR18=4325
1143 10:01:18.255439 CH0_RK0: MR19=0x606, MR18=0x4325, DQSOSC=393, MR23=63, INC=95, DEC=63
1144 10:01:18.255521
1145 10:01:18.298977 ----->DramcWriteLeveling(PI) begin...
1146 10:01:18.299096 ==
1147 10:01:18.299188 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 10:01:18.299460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 10:01:18.299557 ==
1150 10:01:18.299816 Write leveling (Byte 0): 32 => 32
1151 10:01:18.299899 Write leveling (Byte 1): 28 => 28
1152 10:01:18.300029 DramcWriteLeveling(PI) end<-----
1153 10:01:18.300132
1154 10:01:18.300197 ==
1155 10:01:18.300283 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 10:01:18.300380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 10:01:18.300467 ==
1158 10:01:18.300744 [Gating] SW mode calibration
1159 10:01:18.301136 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 10:01:18.301693 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 10:01:18.343013 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1162 10:01:18.343102 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 10:01:18.343632 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1164 10:01:18.344161 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:01:18.344919 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 10:01:18.345183 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:01:18.345273 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:01:18.345358 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:01:18.345429 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:01:18.345680 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:01:18.360934 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:01:18.361015 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:01:18.361568 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:01:18.362348 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 10:01:18.364663 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 10:01:18.367897 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 10:01:18.371289 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 10:01:18.377752 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1179 10:01:18.381109 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1180 10:01:18.384580 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1181 10:01:18.387614 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 10:01:18.394374 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 10:01:18.397841 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 10:01:18.401080 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 10:01:18.407786 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 10:01:18.410910 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:01:18.414169 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1188 10:01:18.420585 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1189 10:01:18.423742 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 10:01:18.427416 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 10:01:18.434180 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 10:01:18.437043 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 10:01:18.440230 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 10:01:18.446959 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 10:01:18.450648 0 10 8 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
1196 10:01:18.453696 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 10:01:18.460433 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 10:01:18.464097 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 10:01:18.467187 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 10:01:18.473955 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 10:01:18.477880 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 10:01:18.481424 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1203 10:01:18.485261 0 11 8 | B1->B0 | 3131 3e3e | 0 0 | (0 0) (0 0)
1204 10:01:18.488647 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1205 10:01:18.495752 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 10:01:18.499153 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 10:01:18.503230 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 10:01:18.506812 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 10:01:18.514402 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 10:01:18.517524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1211 10:01:18.521116 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1212 10:01:18.524819 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:01:18.528749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:01:18.535998 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 10:01:18.539732 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 10:01:18.543402 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 10:01:18.547119 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 10:01:18.550124 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 10:01:18.557689 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 10:01:18.561765 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 10:01:18.565246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 10:01:18.568883 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 10:01:18.572700 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 10:01:18.576525 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 10:01:18.584057 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 10:01:18.587612 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1227 10:01:18.591555 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 10:01:18.595100 Total UI for P1: 0, mck2ui 16
1229 10:01:18.598999 best dqsien dly found for B0: ( 0, 14, 6)
1230 10:01:18.602504 Total UI for P1: 0, mck2ui 16
1231 10:01:18.606104 best dqsien dly found for B1: ( 0, 14, 4)
1232 10:01:18.610189 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1233 10:01:18.610268 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1234 10:01:18.613506
1235 10:01:18.616871 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1236 10:01:18.620599 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1237 10:01:18.620679 [Gating] SW calibration Done
1238 10:01:18.620743 ==
1239 10:01:18.624673 Dram Type= 6, Freq= 0, CH_0, rank 1
1240 10:01:18.628253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1241 10:01:18.628333 ==
1242 10:01:18.632146 RX Vref Scan: 0
1243 10:01:18.632226
1244 10:01:18.632291 RX Vref 0 -> 0, step: 1
1245 10:01:18.635627
1246 10:01:18.635707 RX Delay -130 -> 252, step: 16
1247 10:01:18.639250 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1248 10:01:18.642622 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1249 10:01:18.646805 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1250 10:01:18.654362 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1251 10:01:18.657926 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1252 10:01:18.661567 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1253 10:01:18.665091 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1254 10:01:18.669116 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1255 10:01:18.672652 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1256 10:01:18.676414 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1257 10:01:18.679435 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1258 10:01:18.683241 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1259 10:01:18.686541 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1260 10:01:18.694145 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1261 10:01:18.697688 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1262 10:01:18.701161 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1263 10:01:18.701242 ==
1264 10:01:18.705122 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 10:01:18.708428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 10:01:18.708509 ==
1267 10:01:18.708573 DQS Delay:
1268 10:01:18.712180 DQS0 = 0, DQS1 = 0
1269 10:01:18.712260 DQM Delay:
1270 10:01:18.716187 DQM0 = 87, DQM1 = 77
1271 10:01:18.716267 DQ Delay:
1272 10:01:18.719531 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1273 10:01:18.723093 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1274 10:01:18.723175 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1275 10:01:18.726653 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1276 10:01:18.726733
1277 10:01:18.726797
1278 10:01:18.730411 ==
1279 10:01:18.730492 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 10:01:18.737424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 10:01:18.737505 ==
1282 10:01:18.737569
1283 10:01:18.737628
1284 10:01:18.737685 TX Vref Scan disable
1285 10:01:18.741479 == TX Byte 0 ==
1286 10:01:18.745472 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1287 10:01:18.749225 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1288 10:01:18.752628 == TX Byte 1 ==
1289 10:01:18.756079 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1290 10:01:18.759618 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1291 10:01:18.759726 ==
1292 10:01:18.763118 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 10:01:18.766730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 10:01:18.766813 ==
1295 10:01:18.781224 TX Vref=22, minBit 8, minWin=26, winSum=444
1296 10:01:18.785494 TX Vref=24, minBit 8, minWin=26, winSum=442
1297 10:01:18.788804 TX Vref=26, minBit 9, minWin=27, winSum=447
1298 10:01:18.792550 TX Vref=28, minBit 9, minWin=27, winSum=448
1299 10:01:18.796195 TX Vref=30, minBit 9, minWin=27, winSum=448
1300 10:01:18.799871 TX Vref=32, minBit 9, minWin=27, winSum=447
1301 10:01:18.803849 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 28
1302 10:01:18.804019
1303 10:01:18.806457 Final TX Range 1 Vref 28
1304 10:01:18.806687
1305 10:01:18.806823 ==
1306 10:01:18.810487 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 10:01:18.814010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 10:01:18.816835 ==
1309 10:01:18.817119
1310 10:01:18.817351
1311 10:01:18.817568 TX Vref Scan disable
1312 10:01:18.820920 == TX Byte 0 ==
1313 10:01:18.824221 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1314 10:01:18.830910 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1315 10:01:18.831326 == TX Byte 1 ==
1316 10:01:18.834023 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1317 10:01:18.840629 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1318 10:01:18.841045
1319 10:01:18.841370 [DATLAT]
1320 10:01:18.841670 Freq=800, CH0 RK1
1321 10:01:18.841966
1322 10:01:18.843604 DATLAT Default: 0xa
1323 10:01:18.846974 0, 0xFFFF, sum = 0
1324 10:01:18.847394 1, 0xFFFF, sum = 0
1325 10:01:18.850202 2, 0xFFFF, sum = 0
1326 10:01:18.850678 3, 0xFFFF, sum = 0
1327 10:01:18.853606 4, 0xFFFF, sum = 0
1328 10:01:18.854020 5, 0xFFFF, sum = 0
1329 10:01:18.857126 6, 0xFFFF, sum = 0
1330 10:01:18.857543 7, 0xFFFF, sum = 0
1331 10:01:18.860614 8, 0xFFFF, sum = 0
1332 10:01:18.861033 9, 0x0, sum = 1
1333 10:01:18.863398 10, 0x0, sum = 2
1334 10:01:18.863479 11, 0x0, sum = 3
1335 10:01:18.866972 12, 0x0, sum = 4
1336 10:01:18.867053 best_step = 10
1337 10:01:18.867117
1338 10:01:18.867176 ==
1339 10:01:18.870209 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 10:01:18.873708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 10:01:18.873788 ==
1342 10:01:18.876588 RX Vref Scan: 0
1343 10:01:18.876694
1344 10:01:18.879933 RX Vref 0 -> 0, step: 1
1345 10:01:18.880012
1346 10:01:18.880076 RX Delay -111 -> 252, step: 8
1347 10:01:18.887537 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1348 10:01:18.890542 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1349 10:01:18.894160 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1350 10:01:18.897113 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1351 10:01:18.900530 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1352 10:01:18.907337 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1353 10:01:18.910528 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1354 10:01:18.914368 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1355 10:01:18.917231 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1356 10:01:18.920931 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1357 10:01:18.926910 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1358 10:01:18.930408 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1359 10:01:18.933500 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1360 10:01:18.936951 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1361 10:01:18.943499 iDelay=217, Bit 14, Center 88 (-31 ~ 208) 240
1362 10:01:18.946806 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1363 10:01:18.946887 ==
1364 10:01:18.950370 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 10:01:18.953576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 10:01:18.953656 ==
1367 10:01:18.953720 DQS Delay:
1368 10:01:18.957415 DQS0 = 0, DQS1 = 0
1369 10:01:18.957495 DQM Delay:
1370 10:01:18.960191 DQM0 = 85, DQM1 = 77
1371 10:01:18.960271 DQ Delay:
1372 10:01:18.963650 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1373 10:01:18.967017 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1374 10:01:18.970314 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1375 10:01:18.973558 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1376 10:01:18.973638
1377 10:01:18.973700
1378 10:01:18.983951 [DQSOSCAuto] RK1, (LSB)MR18= 0x4309, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1379 10:01:18.984032 CH0 RK1: MR19=606, MR18=4309
1380 10:01:18.990171 CH0_RK1: MR19=0x606, MR18=0x4309, DQSOSC=393, MR23=63, INC=95, DEC=63
1381 10:01:18.993746 [RxdqsGatingPostProcess] freq 800
1382 10:01:19.000352 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1383 10:01:19.003566 Pre-setting of DQS Precalculation
1384 10:01:19.006850 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1385 10:01:19.006931 ==
1386 10:01:19.009995 Dram Type= 6, Freq= 0, CH_1, rank 0
1387 10:01:19.013525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 10:01:19.016747 ==
1389 10:01:19.020203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1390 10:01:19.026670 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1391 10:01:19.035298 [CA 0] Center 36 (6~67) winsize 62
1392 10:01:19.038770 [CA 1] Center 36 (6~67) winsize 62
1393 10:01:19.042250 [CA 2] Center 34 (4~65) winsize 62
1394 10:01:19.045431 [CA 3] Center 34 (3~65) winsize 63
1395 10:01:19.048817 [CA 4] Center 34 (4~65) winsize 62
1396 10:01:19.052008 [CA 5] Center 34 (3~65) winsize 63
1397 10:01:19.052089
1398 10:01:19.055426 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1399 10:01:19.055506
1400 10:01:19.058826 [CATrainingPosCal] consider 1 rank data
1401 10:01:19.061957 u2DelayCellTimex100 = 270/100 ps
1402 10:01:19.065275 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1403 10:01:19.072236 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1404 10:01:19.075008 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 10:01:19.078936 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1406 10:01:19.082077 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 10:01:19.085200 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1408 10:01:19.085281
1409 10:01:19.088952 CA PerBit enable=1, Macro0, CA PI delay=34
1410 10:01:19.089032
1411 10:01:19.092031 [CBTSetCACLKResult] CA Dly = 34
1412 10:01:19.092111 CS Dly: 5 (0~36)
1413 10:01:19.095468 ==
1414 10:01:19.095555 Dram Type= 6, Freq= 0, CH_1, rank 1
1415 10:01:19.102277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 10:01:19.102360 ==
1417 10:01:19.105122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 10:01:19.112117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 10:01:19.121706 [CA 0] Center 36 (6~67) winsize 62
1420 10:01:19.125333 [CA 1] Center 36 (6~67) winsize 62
1421 10:01:19.128292 [CA 2] Center 34 (4~65) winsize 62
1422 10:01:19.131922 [CA 3] Center 34 (3~65) winsize 63
1423 10:01:19.135420 [CA 4] Center 34 (4~65) winsize 62
1424 10:01:19.138390 [CA 5] Center 34 (3~65) winsize 63
1425 10:01:19.138496
1426 10:01:19.141723 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1427 10:01:19.141804
1428 10:01:19.145327 [CATrainingPosCal] consider 2 rank data
1429 10:01:19.148142 u2DelayCellTimex100 = 270/100 ps
1430 10:01:19.151901 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1431 10:01:19.158399 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 10:01:19.161454 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 10:01:19.164744 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1434 10:01:19.168440 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 10:01:19.171514 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1436 10:01:19.171595
1437 10:01:19.174851 CA PerBit enable=1, Macro0, CA PI delay=34
1438 10:01:19.174957
1439 10:01:19.178242 [CBTSetCACLKResult] CA Dly = 34
1440 10:01:19.178348 CS Dly: 6 (0~38)
1441 10:01:19.181534
1442 10:01:19.184699 ----->DramcWriteLeveling(PI) begin...
1443 10:01:19.184807 ==
1444 10:01:19.188275 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 10:01:19.191348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 10:01:19.191429 ==
1447 10:01:19.194722 Write leveling (Byte 0): 28 => 28
1448 10:01:19.197846 Write leveling (Byte 1): 28 => 28
1449 10:01:19.201249 DramcWriteLeveling(PI) end<-----
1450 10:01:19.201371
1451 10:01:19.201441 ==
1452 10:01:19.204533 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 10:01:19.207654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 10:01:19.207734 ==
1455 10:01:19.211308 [Gating] SW mode calibration
1456 10:01:19.217573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1457 10:01:19.224558 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1458 10:01:19.227933 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1459 10:01:19.231076 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1460 10:01:19.237965 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:01:19.240711 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:01:19.244177 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:01:19.251117 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 10:01:19.254284 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:01:19.257296 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:01:19.264152 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:01:19.267575 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:01:19.270563 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:01:19.277432 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:01:19.281224 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:01:19.284098 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 10:01:19.287537 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 10:01:19.294639 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 10:01:19.297603 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1475 10:01:19.301193 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1476 10:01:19.307549 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 10:01:19.310799 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 10:01:19.314510 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 10:01:19.321130 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 10:01:19.324063 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:01:19.327468 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 10:01:19.334069 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 10:01:19.337151 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 10:01:19.340486 0 9 8 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
1485 10:01:19.347155 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 10:01:19.350721 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 10:01:19.354437 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 10:01:19.360696 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 10:01:19.363894 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 10:01:19.367140 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1491 10:01:19.373571 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (0 0) (1 0)
1492 10:01:19.377097 0 10 8 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
1493 10:01:19.380487 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 10:01:19.386718 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 10:01:19.389911 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 10:01:19.393437 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 10:01:19.400163 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 10:01:19.403566 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 10:01:19.406464 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1500 10:01:19.413878 0 11 8 | B1->B0 | 3a3a 3d3d | 0 0 | (0 0) (0 0)
1501 10:01:19.416770 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 10:01:19.420035 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 10:01:19.426724 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 10:01:19.429861 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 10:01:19.433208 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 10:01:19.439907 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 10:01:19.443130 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1508 10:01:19.446326 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:01:19.453307 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:01:19.456565 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 10:01:19.460016 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 10:01:19.463049 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 10:01:19.469639 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 10:01:19.473312 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 10:01:19.476688 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 10:01:19.482810 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 10:01:19.486405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 10:01:19.489726 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 10:01:19.496147 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 10:01:19.499698 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 10:01:19.502763 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 10:01:19.509499 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1523 10:01:19.512842 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1524 10:01:19.516172 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 10:01:19.519693 Total UI for P1: 0, mck2ui 16
1526 10:01:19.523095 best dqsien dly found for B0: ( 0, 14, 2)
1527 10:01:19.526286 Total UI for P1: 0, mck2ui 16
1528 10:01:19.529369 best dqsien dly found for B1: ( 0, 14, 6)
1529 10:01:19.532792 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1530 10:01:19.536246 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1531 10:01:19.536325
1532 10:01:19.542999 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1533 10:01:19.546011 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1534 10:01:19.546090 [Gating] SW calibration Done
1535 10:01:19.549882 ==
1536 10:01:19.553142 Dram Type= 6, Freq= 0, CH_1, rank 0
1537 10:01:19.555818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1538 10:01:19.555909 ==
1539 10:01:19.555973 RX Vref Scan: 0
1540 10:01:19.556044
1541 10:01:19.559347 RX Vref 0 -> 0, step: 1
1542 10:01:19.559475
1543 10:01:19.562826 RX Delay -130 -> 252, step: 16
1544 10:01:19.565816 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1545 10:01:19.569260 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1546 10:01:19.575988 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1547 10:01:19.579154 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1548 10:01:19.583020 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1549 10:01:19.585762 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1550 10:01:19.588927 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1551 10:01:19.595899 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1552 10:01:19.599111 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1553 10:01:19.602528 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1554 10:01:19.606056 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1555 10:01:19.608951 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1556 10:01:19.616163 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1557 10:01:19.618836 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1558 10:01:19.622259 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1559 10:01:19.625876 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1560 10:01:19.625955 ==
1561 10:01:19.629241 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 10:01:19.635730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 10:01:19.635824 ==
1564 10:01:19.635916 DQS Delay:
1565 10:01:19.636006 DQS0 = 0, DQS1 = 0
1566 10:01:19.639189 DQM Delay:
1567 10:01:19.639279 DQM0 = 88, DQM1 = 79
1568 10:01:19.642777 DQ Delay:
1569 10:01:19.645765 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1570 10:01:19.649127 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1571 10:01:19.652486 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1572 10:01:19.655808 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1573 10:01:19.655900
1574 10:01:19.655963
1575 10:01:19.656022 ==
1576 10:01:19.658866 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 10:01:19.662748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 10:01:19.662835 ==
1579 10:01:19.662925
1580 10:01:19.663012
1581 10:01:19.665688 TX Vref Scan disable
1582 10:01:19.665767 == TX Byte 0 ==
1583 10:01:19.672644 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1584 10:01:19.675963 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1585 10:01:19.676043 == TX Byte 1 ==
1586 10:01:19.682218 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1587 10:01:19.685463 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1588 10:01:19.685572 ==
1589 10:01:19.689003 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 10:01:19.692550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 10:01:19.692630 ==
1592 10:01:19.706406 TX Vref=22, minBit 10, minWin=26, winSum=441
1593 10:01:19.709502 TX Vref=24, minBit 13, minWin=26, winSum=444
1594 10:01:19.712873 TX Vref=26, minBit 8, minWin=27, winSum=448
1595 10:01:19.716204 TX Vref=28, minBit 0, minWin=28, winSum=452
1596 10:01:19.719722 TX Vref=30, minBit 9, minWin=27, winSum=452
1597 10:01:19.726196 TX Vref=32, minBit 8, minWin=27, winSum=448
1598 10:01:19.729562 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
1599 10:01:19.729664
1600 10:01:19.732526 Final TX Range 1 Vref 28
1601 10:01:19.732606
1602 10:01:19.732669 ==
1603 10:01:19.735892 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 10:01:19.739577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 10:01:19.742473 ==
1606 10:01:19.742551
1607 10:01:19.742651
1608 10:01:19.742710 TX Vref Scan disable
1609 10:01:19.746051 == TX Byte 0 ==
1610 10:01:19.749546 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1611 10:01:19.756429 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1612 10:01:19.756514 == TX Byte 1 ==
1613 10:01:19.759932 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1614 10:01:19.765928 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1615 10:01:19.766012
1616 10:01:19.766098 [DATLAT]
1617 10:01:19.766179 Freq=800, CH1 RK0
1618 10:01:19.766259
1619 10:01:19.769455 DATLAT Default: 0xa
1620 10:01:19.769551 0, 0xFFFF, sum = 0
1621 10:01:19.772825 1, 0xFFFF, sum = 0
1622 10:01:19.776177 2, 0xFFFF, sum = 0
1623 10:01:19.776262 3, 0xFFFF, sum = 0
1624 10:01:19.779600 4, 0xFFFF, sum = 0
1625 10:01:19.779685 5, 0xFFFF, sum = 0
1626 10:01:19.783074 6, 0xFFFF, sum = 0
1627 10:01:19.783159 7, 0xFFFF, sum = 0
1628 10:01:19.786124 8, 0xFFFF, sum = 0
1629 10:01:19.786208 9, 0x0, sum = 1
1630 10:01:19.789478 10, 0x0, sum = 2
1631 10:01:19.789562 11, 0x0, sum = 3
1632 10:01:19.789649 12, 0x0, sum = 4
1633 10:01:19.792596 best_step = 10
1634 10:01:19.792679
1635 10:01:19.792764 ==
1636 10:01:19.796080 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 10:01:19.799499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 10:01:19.799583 ==
1639 10:01:19.802906 RX Vref Scan: 1
1640 10:01:19.802988
1641 10:01:19.806385 Set Vref Range= 32 -> 127
1642 10:01:19.806468
1643 10:01:19.806569 RX Vref 32 -> 127, step: 1
1644 10:01:19.806662
1645 10:01:19.809739 RX Delay -95 -> 252, step: 8
1646 10:01:19.809821
1647 10:01:19.812498 Set Vref, RX VrefLevel [Byte0]: 32
1648 10:01:19.815962 [Byte1]: 32
1649 10:01:19.816045
1650 10:01:19.819358 Set Vref, RX VrefLevel [Byte0]: 33
1651 10:01:19.822423 [Byte1]: 33
1652 10:01:19.826471
1653 10:01:19.826553 Set Vref, RX VrefLevel [Byte0]: 34
1654 10:01:19.829756 [Byte1]: 34
1655 10:01:19.834326
1656 10:01:19.834409 Set Vref, RX VrefLevel [Byte0]: 35
1657 10:01:19.837670 [Byte1]: 35
1658 10:01:19.841783
1659 10:01:19.845008 Set Vref, RX VrefLevel [Byte0]: 36
1660 10:01:19.848812 [Byte1]: 36
1661 10:01:19.848894
1662 10:01:19.851460 Set Vref, RX VrefLevel [Byte0]: 37
1663 10:01:19.854789 [Byte1]: 37
1664 10:01:19.854871
1665 10:01:19.858488 Set Vref, RX VrefLevel [Byte0]: 38
1666 10:01:19.861645 [Byte1]: 38
1667 10:01:19.861728
1668 10:01:19.864874 Set Vref, RX VrefLevel [Byte0]: 39
1669 10:01:19.868400 [Byte1]: 39
1670 10:01:19.872338
1671 10:01:19.872420 Set Vref, RX VrefLevel [Byte0]: 40
1672 10:01:19.875523 [Byte1]: 40
1673 10:01:19.879584
1674 10:01:19.879666 Set Vref, RX VrefLevel [Byte0]: 41
1675 10:01:19.883350 [Byte1]: 41
1676 10:01:19.887341
1677 10:01:19.887424 Set Vref, RX VrefLevel [Byte0]: 42
1678 10:01:19.890543 [Byte1]: 42
1679 10:01:19.894978
1680 10:01:19.895063 Set Vref, RX VrefLevel [Byte0]: 43
1681 10:01:19.898473 [Byte1]: 43
1682 10:01:19.902416
1683 10:01:19.902498 Set Vref, RX VrefLevel [Byte0]: 44
1684 10:01:19.905912 [Byte1]: 44
1685 10:01:19.910253
1686 10:01:19.910335 Set Vref, RX VrefLevel [Byte0]: 45
1687 10:01:19.913916 [Byte1]: 45
1688 10:01:19.917812
1689 10:01:19.917894 Set Vref, RX VrefLevel [Byte0]: 46
1690 10:01:19.924077 [Byte1]: 46
1691 10:01:19.924161
1692 10:01:19.927605 Set Vref, RX VrefLevel [Byte0]: 47
1693 10:01:19.930627 [Byte1]: 47
1694 10:01:19.930723
1695 10:01:19.934299 Set Vref, RX VrefLevel [Byte0]: 48
1696 10:01:19.937873 [Byte1]: 48
1697 10:01:19.937956
1698 10:01:19.941009 Set Vref, RX VrefLevel [Byte0]: 49
1699 10:01:19.943968 [Byte1]: 49
1700 10:01:19.948743
1701 10:01:19.948824 Set Vref, RX VrefLevel [Byte0]: 50
1702 10:01:19.951505 [Byte1]: 50
1703 10:01:19.956061
1704 10:01:19.956143 Set Vref, RX VrefLevel [Byte0]: 51
1705 10:01:19.959487 [Byte1]: 51
1706 10:01:19.963481
1707 10:01:19.963563 Set Vref, RX VrefLevel [Byte0]: 52
1708 10:01:19.966905 [Byte1]: 52
1709 10:01:19.971109
1710 10:01:19.971187 Set Vref, RX VrefLevel [Byte0]: 53
1711 10:01:19.974412 [Byte1]: 53
1712 10:01:19.978987
1713 10:01:19.979065 Set Vref, RX VrefLevel [Byte0]: 54
1714 10:01:19.982241 [Byte1]: 54
1715 10:01:19.986032
1716 10:01:19.986111 Set Vref, RX VrefLevel [Byte0]: 55
1717 10:01:19.989397 [Byte1]: 55
1718 10:01:19.993858
1719 10:01:19.993954 Set Vref, RX VrefLevel [Byte0]: 56
1720 10:01:19.996995 [Byte1]: 56
1721 10:01:20.001508
1722 10:01:20.001587 Set Vref, RX VrefLevel [Byte0]: 57
1723 10:01:20.004614 [Byte1]: 57
1724 10:01:20.008965
1725 10:01:20.009043 Set Vref, RX VrefLevel [Byte0]: 58
1726 10:01:20.012435 [Byte1]: 58
1727 10:01:20.016975
1728 10:01:20.017063 Set Vref, RX VrefLevel [Byte0]: 59
1729 10:01:20.023204 [Byte1]: 59
1730 10:01:20.023283
1731 10:01:20.026094 Set Vref, RX VrefLevel [Byte0]: 60
1732 10:01:20.029591 [Byte1]: 60
1733 10:01:20.029691
1734 10:01:20.032965 Set Vref, RX VrefLevel [Byte0]: 61
1735 10:01:20.036715 [Byte1]: 61
1736 10:01:20.036794
1737 10:01:20.039770 Set Vref, RX VrefLevel [Byte0]: 62
1738 10:01:20.042532 [Byte1]: 62
1739 10:01:20.046917
1740 10:01:20.046995 Set Vref, RX VrefLevel [Byte0]: 63
1741 10:01:20.050128 [Byte1]: 63
1742 10:01:20.054508
1743 10:01:20.054588 Set Vref, RX VrefLevel [Byte0]: 64
1744 10:01:20.057874 [Byte1]: 64
1745 10:01:20.062451
1746 10:01:20.062530 Set Vref, RX VrefLevel [Byte0]: 65
1747 10:01:20.065221 [Byte1]: 65
1748 10:01:20.069901
1749 10:01:20.069981 Set Vref, RX VrefLevel [Byte0]: 66
1750 10:01:20.072899 [Byte1]: 66
1751 10:01:20.077844
1752 10:01:20.077924 Set Vref, RX VrefLevel [Byte0]: 67
1753 10:01:20.080616 [Byte1]: 67
1754 10:01:20.085113
1755 10:01:20.085193 Set Vref, RX VrefLevel [Byte0]: 68
1756 10:01:20.088252 [Byte1]: 68
1757 10:01:20.092433
1758 10:01:20.092512 Set Vref, RX VrefLevel [Byte0]: 69
1759 10:01:20.096223 [Byte1]: 69
1760 10:01:20.100165
1761 10:01:20.100246 Set Vref, RX VrefLevel [Byte0]: 70
1762 10:01:20.103449 [Byte1]: 70
1763 10:01:20.107869
1764 10:01:20.107947 Set Vref, RX VrefLevel [Byte0]: 71
1765 10:01:20.111189 [Byte1]: 71
1766 10:01:20.115437
1767 10:01:20.115515 Set Vref, RX VrefLevel [Byte0]: 72
1768 10:01:20.121531 [Byte1]: 72
1769 10:01:20.121611
1770 10:01:20.125384 Set Vref, RX VrefLevel [Byte0]: 73
1771 10:01:20.128627 [Byte1]: 73
1772 10:01:20.128707
1773 10:01:20.131593 Set Vref, RX VrefLevel [Byte0]: 74
1774 10:01:20.135180 [Byte1]: 74
1775 10:01:20.135259
1776 10:01:20.138561 Final RX Vref Byte 0 = 56 to rank0
1777 10:01:20.141975 Final RX Vref Byte 1 = 63 to rank0
1778 10:01:20.144823 Final RX Vref Byte 0 = 56 to rank1
1779 10:01:20.148047 Final RX Vref Byte 1 = 63 to rank1==
1780 10:01:20.151512 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 10:01:20.155120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 10:01:20.158434 ==
1783 10:01:20.158516 DQS Delay:
1784 10:01:20.158653 DQS0 = 0, DQS1 = 0
1785 10:01:20.161600 DQM Delay:
1786 10:01:20.161679 DQM0 = 86, DQM1 = 79
1787 10:01:20.164715 DQ Delay:
1788 10:01:20.168134 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1789 10:01:20.171769 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1790 10:01:20.174824 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1791 10:01:20.178094 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1792 10:01:20.178175
1793 10:01:20.178238
1794 10:01:20.184371 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1795 10:01:20.187677 CH1 RK0: MR19=606, MR18=301C
1796 10:01:20.194451 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1797 10:01:20.194532
1798 10:01:20.197746 ----->DramcWriteLeveling(PI) begin...
1799 10:01:20.197828 ==
1800 10:01:20.201600 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 10:01:20.204401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 10:01:20.204482 ==
1803 10:01:20.207838 Write leveling (Byte 0): 26 => 26
1804 10:01:20.211129 Write leveling (Byte 1): 27 => 27
1805 10:01:20.214446 DramcWriteLeveling(PI) end<-----
1806 10:01:20.214526
1807 10:01:20.214597 ==
1808 10:01:20.217690 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 10:01:20.220984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 10:01:20.221064 ==
1811 10:01:20.224529 [Gating] SW mode calibration
1812 10:01:20.231145 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 10:01:20.237766 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 10:01:20.241075 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 10:01:20.247967 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1816 10:01:20.251038 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1817 10:01:20.254501 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:01:20.257648 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:01:20.264342 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 10:01:20.267779 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:01:20.270743 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:01:20.277890 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:01:20.280719 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:01:20.283822 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:01:20.290513 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:01:20.294043 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:01:20.297365 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:01:20.304024 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:01:20.307155 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:01:20.310324 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1831 10:01:20.317282 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1832 10:01:20.320749 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1833 10:01:20.323922 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 10:01:20.330788 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 10:01:20.333916 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 10:01:20.337264 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 10:01:20.343435 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 10:01:20.347106 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 10:01:20.350713 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 10:01:20.356592 0 9 8 | B1->B0 | 3333 2e2e | 1 0 | (1 1) (0 0)
1841 10:01:20.360413 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 10:01:20.363245 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 10:01:20.370125 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 10:01:20.373510 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 10:01:20.376621 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 10:01:20.383552 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1847 10:01:20.386703 0 10 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1848 10:01:20.389895 0 10 8 | B1->B0 | 2424 2d2d | 0 1 | (0 0) (1 0)
1849 10:01:20.396826 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 10:01:20.399598 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 10:01:20.402894 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 10:01:20.409562 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 10:01:20.413248 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 10:01:20.416252 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 10:01:20.423195 0 11 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1856 10:01:20.426442 0 11 8 | B1->B0 | 4343 3535 | 0 1 | (0 0) (0 0)
1857 10:01:20.429593 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 10:01:20.436438 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 10:01:20.439860 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 10:01:20.442902 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 10:01:20.449542 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 10:01:20.453152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 10:01:20.456125 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 10:01:20.462709 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 10:01:20.466239 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:01:20.469623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:01:20.475957 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 10:01:20.479304 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:01:20.483169 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 10:01:20.488975 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 10:01:20.492624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 10:01:20.495990 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 10:01:20.502368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 10:01:20.505873 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 10:01:20.509070 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 10:01:20.512171 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 10:01:20.518942 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 10:01:20.522237 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 10:01:20.525484 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1880 10:01:20.532571 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 10:01:20.535547 Total UI for P1: 0, mck2ui 16
1882 10:01:20.539067 best dqsien dly found for B0: ( 0, 14, 6)
1883 10:01:20.543056 Total UI for P1: 0, mck2ui 16
1884 10:01:20.545532 best dqsien dly found for B1: ( 0, 14, 4)
1885 10:01:20.548871 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1886 10:01:20.552159 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1887 10:01:20.552240
1888 10:01:20.555467 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1889 10:01:20.558953 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 10:01:20.562224 [Gating] SW calibration Done
1891 10:01:20.562305 ==
1892 10:01:20.565720 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 10:01:20.568673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 10:01:20.568754 ==
1895 10:01:20.572278 RX Vref Scan: 0
1896 10:01:20.572359
1897 10:01:20.572444 RX Vref 0 -> 0, step: 1
1898 10:01:20.572523
1899 10:01:20.575399 RX Delay -130 -> 252, step: 16
1900 10:01:20.582134 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1901 10:01:20.585283 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1902 10:01:20.588494 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1903 10:01:20.592190 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1904 10:01:20.595170 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1905 10:01:20.602072 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1906 10:01:20.605555 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1907 10:01:20.608377 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1908 10:01:20.612029 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1909 10:01:20.615194 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1910 10:01:20.621706 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1911 10:01:20.624831 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1912 10:01:20.628307 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1913 10:01:20.631935 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1914 10:01:20.635152 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1915 10:01:20.641670 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1916 10:01:20.641753 ==
1917 10:01:20.644946 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 10:01:20.648027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 10:01:20.648108 ==
1920 10:01:20.648172 DQS Delay:
1921 10:01:20.651912 DQS0 = 0, DQS1 = 0
1922 10:01:20.651992 DQM Delay:
1923 10:01:20.654706 DQM0 = 86, DQM1 = 78
1924 10:01:20.654785 DQ Delay:
1925 10:01:20.658211 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1926 10:01:20.661867 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1927 10:01:20.664738 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1928 10:01:20.668661 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1929 10:01:20.668744
1930 10:01:20.668829
1931 10:01:20.668910 ==
1932 10:01:20.671827 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 10:01:20.674635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 10:01:20.678175 ==
1935 10:01:20.678257
1936 10:01:20.678341
1937 10:01:20.678422 TX Vref Scan disable
1938 10:01:20.681519 == TX Byte 0 ==
1939 10:01:20.684980 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1940 10:01:20.687899 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1941 10:01:20.691416 == TX Byte 1 ==
1942 10:01:20.694851 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1943 10:01:20.698247 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1944 10:01:20.701190 ==
1945 10:01:20.704634 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 10:01:20.708063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 10:01:20.708147 ==
1948 10:01:20.720607 TX Vref=22, minBit 1, minWin=27, winSum=442
1949 10:01:20.723897 TX Vref=24, minBit 1, minWin=27, winSum=446
1950 10:01:20.727279 TX Vref=26, minBit 8, minWin=27, winSum=448
1951 10:01:20.730319 TX Vref=28, minBit 15, minWin=27, winSum=454
1952 10:01:20.733866 TX Vref=30, minBit 13, minWin=27, winSum=449
1953 10:01:20.740193 TX Vref=32, minBit 12, minWin=27, winSum=447
1954 10:01:20.743869 [TxChooseVref] Worse bit 15, Min win 27, Win sum 454, Final Vref 28
1955 10:01:20.743952
1956 10:01:20.746731 Final TX Range 1 Vref 28
1957 10:01:20.746814
1958 10:01:20.746909 ==
1959 10:01:20.750388 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 10:01:20.756594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 10:01:20.756678 ==
1962 10:01:20.756753
1963 10:01:20.756817
1964 10:01:20.756875 TX Vref Scan disable
1965 10:01:20.760852 == TX Byte 0 ==
1966 10:01:20.764169 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1967 10:01:20.770580 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1968 10:01:20.770669 == TX Byte 1 ==
1969 10:01:20.773901 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1970 10:01:20.780737 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1971 10:01:20.780815
1972 10:01:20.780878 [DATLAT]
1973 10:01:20.780936 Freq=800, CH1 RK1
1974 10:01:20.781000
1975 10:01:20.783765 DATLAT Default: 0xa
1976 10:01:20.783847 0, 0xFFFF, sum = 0
1977 10:01:20.787315 1, 0xFFFF, sum = 0
1978 10:01:20.790604 2, 0xFFFF, sum = 0
1979 10:01:20.790675 3, 0xFFFF, sum = 0
1980 10:01:20.793469 4, 0xFFFF, sum = 0
1981 10:01:20.793543 5, 0xFFFF, sum = 0
1982 10:01:20.797006 6, 0xFFFF, sum = 0
1983 10:01:20.797075 7, 0xFFFF, sum = 0
1984 10:01:20.800456 8, 0xFFFF, sum = 0
1985 10:01:20.800536 9, 0x0, sum = 1
1986 10:01:20.803732 10, 0x0, sum = 2
1987 10:01:20.803808 11, 0x0, sum = 3
1988 10:01:20.806693 12, 0x0, sum = 4
1989 10:01:20.806766 best_step = 10
1990 10:01:20.806829
1991 10:01:20.806885 ==
1992 10:01:20.810312 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 10:01:20.813605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 10:01:20.813678 ==
1995 10:01:20.816822 RX Vref Scan: 0
1996 10:01:20.816893
1997 10:01:20.820165 RX Vref 0 -> 0, step: 1
1998 10:01:20.820280
1999 10:01:20.820386 RX Delay -95 -> 252, step: 8
2000 10:01:20.827328 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2001 10:01:20.830901 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2002 10:01:20.833793 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2003 10:01:20.837571 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2004 10:01:20.840797 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2005 10:01:20.847167 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2006 10:01:20.850404 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2007 10:01:20.853517 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2008 10:01:20.856687 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2009 10:01:20.863937 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2010 10:01:20.867006 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2011 10:01:20.870195 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2012 10:01:20.873248 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2013 10:01:20.877094 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2014 10:01:20.883291 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2015 10:01:20.887021 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2016 10:01:20.887105 ==
2017 10:01:20.890191 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 10:01:20.893726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 10:01:20.893810 ==
2020 10:01:20.896663 DQS Delay:
2021 10:01:20.896745 DQS0 = 0, DQS1 = 0
2022 10:01:20.896831 DQM Delay:
2023 10:01:20.899844 DQM0 = 87, DQM1 = 78
2024 10:01:20.899927 DQ Delay:
2025 10:01:20.903212 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2026 10:01:20.906962 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2027 10:01:20.910463 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2028 10:01:20.913701 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2029 10:01:20.913784
2030 10:01:20.913869
2031 10:01:20.922864 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2032 10:01:20.926973 CH1 RK1: MR19=606, MR18=1E16
2033 10:01:20.929438 CH1_RK1: MR19=0x606, MR18=0x1E16, DQSOSC=402, MR23=63, INC=91, DEC=60
2034 10:01:20.933171 [RxdqsGatingPostProcess] freq 800
2035 10:01:20.939770 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 10:01:20.943009 Pre-setting of DQS Precalculation
2037 10:01:20.946163 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 10:01:20.956123 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 10:01:20.963188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 10:01:20.963271
2041 10:01:20.963355
2042 10:01:20.966367 [Calibration Summary] 1600 Mbps
2043 10:01:20.966451 CH 0, Rank 0
2044 10:01:20.969651 SW Impedance : PASS
2045 10:01:20.969734 DUTY Scan : NO K
2046 10:01:20.973080 ZQ Calibration : PASS
2047 10:01:20.976166 Jitter Meter : NO K
2048 10:01:20.976250 CBT Training : PASS
2049 10:01:20.979604 Write leveling : PASS
2050 10:01:20.982292 RX DQS gating : PASS
2051 10:01:20.982374 RX DQ/DQS(RDDQC) : PASS
2052 10:01:20.985855 TX DQ/DQS : PASS
2053 10:01:20.989335 RX DATLAT : PASS
2054 10:01:20.989418 RX DQ/DQS(Engine): PASS
2055 10:01:20.992839 TX OE : NO K
2056 10:01:20.992923 All Pass.
2057 10:01:20.993009
2058 10:01:20.995941 CH 0, Rank 1
2059 10:01:20.996025 SW Impedance : PASS
2060 10:01:20.999094 DUTY Scan : NO K
2061 10:01:21.002747 ZQ Calibration : PASS
2062 10:01:21.002831 Jitter Meter : NO K
2063 10:01:21.005498 CBT Training : PASS
2064 10:01:21.008941 Write leveling : PASS
2065 10:01:21.009024 RX DQS gating : PASS
2066 10:01:21.012390 RX DQ/DQS(RDDQC) : PASS
2067 10:01:21.015435 TX DQ/DQS : PASS
2068 10:01:21.015518 RX DATLAT : PASS
2069 10:01:21.018813 RX DQ/DQS(Engine): PASS
2070 10:01:21.022321 TX OE : NO K
2071 10:01:21.022403 All Pass.
2072 10:01:21.022504
2073 10:01:21.022642 CH 1, Rank 0
2074 10:01:21.025985 SW Impedance : PASS
2075 10:01:21.028987 DUTY Scan : NO K
2076 10:01:21.029070 ZQ Calibration : PASS
2077 10:01:21.032366 Jitter Meter : NO K
2078 10:01:21.032449 CBT Training : PASS
2079 10:01:21.035426 Write leveling : PASS
2080 10:01:21.038612 RX DQS gating : PASS
2081 10:01:21.038695 RX DQ/DQS(RDDQC) : PASS
2082 10:01:21.042318 TX DQ/DQS : PASS
2083 10:01:21.045073 RX DATLAT : PASS
2084 10:01:21.045156 RX DQ/DQS(Engine): PASS
2085 10:01:21.048891 TX OE : NO K
2086 10:01:21.048978 All Pass.
2087 10:01:21.049064
2088 10:01:21.051875 CH 1, Rank 1
2089 10:01:21.051958 SW Impedance : PASS
2090 10:01:21.054920 DUTY Scan : NO K
2091 10:01:21.058487 ZQ Calibration : PASS
2092 10:01:21.058570 Jitter Meter : NO K
2093 10:01:21.061628 CBT Training : PASS
2094 10:01:21.065239 Write leveling : PASS
2095 10:01:21.065322 RX DQS gating : PASS
2096 10:01:21.068725 RX DQ/DQS(RDDQC) : PASS
2097 10:01:21.072216 TX DQ/DQS : PASS
2098 10:01:21.072300 RX DATLAT : PASS
2099 10:01:21.074852 RX DQ/DQS(Engine): PASS
2100 10:01:21.078258 TX OE : NO K
2101 10:01:21.078341 All Pass.
2102 10:01:21.078426
2103 10:01:21.078524 DramC Write-DBI off
2104 10:01:21.081327 PER_BANK_REFRESH: Hybrid Mode
2105 10:01:21.084897 TX_TRACKING: ON
2106 10:01:21.088007 [GetDramInforAfterCalByMRR] Vendor 6.
2107 10:01:21.091335 [GetDramInforAfterCalByMRR] Revision 606.
2108 10:01:21.094801 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 10:01:21.094876 MR0 0x3b3b
2110 10:01:21.098155 MR8 0x5151
2111 10:01:21.101419 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 10:01:21.101491
2113 10:01:21.101552 MR0 0x3b3b
2114 10:01:21.101616 MR8 0x5151
2115 10:01:21.108047 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 10:01:21.108124
2117 10:01:21.114625 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 10:01:21.117991 [FAST_K] Save calibration result to emmc
2119 10:01:21.120987 [FAST_K] Save calibration result to emmc
2120 10:01:21.124571 dram_init: config_dvfs: 1
2121 10:01:21.128072 dramc_set_vcore_voltage set vcore to 662500
2122 10:01:21.131291 Read voltage for 1200, 2
2123 10:01:21.131363 Vio18 = 0
2124 10:01:21.134493 Vcore = 662500
2125 10:01:21.134564 Vdram = 0
2126 10:01:21.134672 Vddq = 0
2127 10:01:21.137972 Vmddr = 0
2128 10:01:21.141446 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 10:01:21.147686 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 10:01:21.147762 MEM_TYPE=3, freq_sel=15
2131 10:01:21.150627 sv_algorithm_assistance_LP4_1600
2132 10:01:21.157480 ============ PULL DRAM RESETB DOWN ============
2133 10:01:21.160826 ========== PULL DRAM RESETB DOWN end =========
2134 10:01:21.164467 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 10:01:21.167479 ===================================
2136 10:01:21.170861 LPDDR4 DRAM CONFIGURATION
2137 10:01:21.174010 ===================================
2138 10:01:21.174087 EX_ROW_EN[0] = 0x0
2139 10:01:21.177362 EX_ROW_EN[1] = 0x0
2140 10:01:21.180704 LP4Y_EN = 0x0
2141 10:01:21.180775 WORK_FSP = 0x0
2142 10:01:21.183695 WL = 0x4
2143 10:01:21.183769 RL = 0x4
2144 10:01:21.187173 BL = 0x2
2145 10:01:21.187244 RPST = 0x0
2146 10:01:21.190437 RD_PRE = 0x0
2147 10:01:21.190514 WR_PRE = 0x1
2148 10:01:21.193766 WR_PST = 0x0
2149 10:01:21.193839 DBI_WR = 0x0
2150 10:01:21.196778 DBI_RD = 0x0
2151 10:01:21.196848 OTF = 0x1
2152 10:01:21.200421 ===================================
2153 10:01:21.203903 ===================================
2154 10:01:21.206902 ANA top config
2155 10:01:21.210173 ===================================
2156 10:01:21.213653 DLL_ASYNC_EN = 0
2157 10:01:21.213741 ALL_SLAVE_EN = 0
2158 10:01:21.216886 NEW_RANK_MODE = 1
2159 10:01:21.220338 DLL_IDLE_MODE = 1
2160 10:01:21.223332 LP45_APHY_COMB_EN = 1
2161 10:01:21.223410 TX_ODT_DIS = 1
2162 10:01:21.227136 NEW_8X_MODE = 1
2163 10:01:21.230158 ===================================
2164 10:01:21.233332 ===================================
2165 10:01:21.236680 data_rate = 2400
2166 10:01:21.240345 CKR = 1
2167 10:01:21.243359 DQ_P2S_RATIO = 8
2168 10:01:21.246447 ===================================
2169 10:01:21.249896 CA_P2S_RATIO = 8
2170 10:01:21.249976 DQ_CA_OPEN = 0
2171 10:01:21.253228 DQ_SEMI_OPEN = 0
2172 10:01:21.256530 CA_SEMI_OPEN = 0
2173 10:01:21.260024 CA_FULL_RATE = 0
2174 10:01:21.263459 DQ_CKDIV4_EN = 0
2175 10:01:21.266613 CA_CKDIV4_EN = 0
2176 10:01:21.266687 CA_PREDIV_EN = 0
2177 10:01:21.269673 PH8_DLY = 17
2178 10:01:21.273581 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 10:01:21.276565 DQ_AAMCK_DIV = 4
2180 10:01:21.279809 CA_AAMCK_DIV = 4
2181 10:01:21.282775 CA_ADMCK_DIV = 4
2182 10:01:21.286632 DQ_TRACK_CA_EN = 0
2183 10:01:21.286714 CA_PICK = 1200
2184 10:01:21.289613 CA_MCKIO = 1200
2185 10:01:21.292931 MCKIO_SEMI = 0
2186 10:01:21.296304 PLL_FREQ = 2366
2187 10:01:21.299672 DQ_UI_PI_RATIO = 32
2188 10:01:21.303176 CA_UI_PI_RATIO = 0
2189 10:01:21.305850 ===================================
2190 10:01:21.309207 ===================================
2191 10:01:21.312820 memory_type:LPDDR4
2192 10:01:21.312903 GP_NUM : 10
2193 10:01:21.315815 SRAM_EN : 1
2194 10:01:21.315897 MD32_EN : 0
2195 10:01:21.319330 ===================================
2196 10:01:21.322507 [ANA_INIT] >>>>>>>>>>>>>>
2197 10:01:21.326156 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 10:01:21.329496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 10:01:21.332765 ===================================
2200 10:01:21.335691 data_rate = 2400,PCW = 0X5b00
2201 10:01:21.339299 ===================================
2202 10:01:21.342558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 10:01:21.346173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 10:01:21.352521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 10:01:21.359005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 10:01:21.362135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 10:01:21.365475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 10:01:21.365558 [ANA_INIT] flow start
2209 10:01:21.369189 [ANA_INIT] PLL >>>>>>>>
2210 10:01:21.372509 [ANA_INIT] PLL <<<<<<<<
2211 10:01:21.372592 [ANA_INIT] MIDPI >>>>>>>>
2212 10:01:21.375679 [ANA_INIT] MIDPI <<<<<<<<
2213 10:01:21.378420 [ANA_INIT] DLL >>>>>>>>
2214 10:01:21.378502 [ANA_INIT] DLL <<<<<<<<
2215 10:01:21.381906 [ANA_INIT] flow end
2216 10:01:21.385210 ============ LP4 DIFF to SE enter ============
2217 10:01:21.391757 ============ LP4 DIFF to SE exit ============
2218 10:01:21.391841 [ANA_INIT] <<<<<<<<<<<<<
2219 10:01:21.395450 [Flow] Enable top DCM control >>>>>
2220 10:01:21.398658 [Flow] Enable top DCM control <<<<<
2221 10:01:21.402061 Enable DLL master slave shuffle
2222 10:01:21.408358 ==============================================================
2223 10:01:21.408441 Gating Mode config
2224 10:01:21.414788 ==============================================================
2225 10:01:21.418470 Config description:
2226 10:01:21.425243 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 10:01:21.431515 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 10:01:21.438359 SELPH_MODE 0: By rank 1: By Phase
2229 10:01:21.444618 ==============================================================
2230 10:01:21.448454 GAT_TRACK_EN = 1
2231 10:01:21.448533 RX_GATING_MODE = 2
2232 10:01:21.451595 RX_GATING_TRACK_MODE = 2
2233 10:01:21.455372 SELPH_MODE = 1
2234 10:01:21.458043 PICG_EARLY_EN = 1
2235 10:01:21.461697 VALID_LAT_VALUE = 1
2236 10:01:21.468593 ==============================================================
2237 10:01:21.471750 Enter into Gating configuration >>>>
2238 10:01:21.475146 Exit from Gating configuration <<<<
2239 10:01:21.478552 Enter into DVFS_PRE_config >>>>>
2240 10:01:21.488513 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 10:01:21.491633 Exit from DVFS_PRE_config <<<<<
2242 10:01:21.494574 Enter into PICG configuration >>>>
2243 10:01:21.498338 Exit from PICG configuration <<<<
2244 10:01:21.501295 [RX_INPUT] configuration >>>>>
2245 10:01:21.501379 [RX_INPUT] configuration <<<<<
2246 10:01:21.507960 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 10:01:21.514394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 10:01:21.520990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 10:01:21.527938 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 10:01:21.531122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 10:01:21.537743 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 10:01:21.540736 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 10:01:21.547374 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 10:01:21.550793 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 10:01:21.554222 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 10:01:21.557683 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 10:01:21.564075 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 10:01:21.567557 ===================================
2259 10:01:21.567640 LPDDR4 DRAM CONFIGURATION
2260 10:01:21.571137 ===================================
2261 10:01:21.573953 EX_ROW_EN[0] = 0x0
2262 10:01:21.577007 EX_ROW_EN[1] = 0x0
2263 10:01:21.577090 LP4Y_EN = 0x0
2264 10:01:21.580633 WORK_FSP = 0x0
2265 10:01:21.580716 WL = 0x4
2266 10:01:21.583998 RL = 0x4
2267 10:01:21.584081 BL = 0x2
2268 10:01:21.587386 RPST = 0x0
2269 10:01:21.587468 RD_PRE = 0x0
2270 10:01:21.590389 WR_PRE = 0x1
2271 10:01:21.590506 WR_PST = 0x0
2272 10:01:21.593667 DBI_WR = 0x0
2273 10:01:21.593750 DBI_RD = 0x0
2274 10:01:21.597024 OTF = 0x1
2275 10:01:21.600246 ===================================
2276 10:01:21.603759 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 10:01:21.606688 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 10:01:21.613746 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 10:01:21.616849 ===================================
2280 10:01:21.616932 LPDDR4 DRAM CONFIGURATION
2281 10:01:21.620234 ===================================
2282 10:01:21.623367 EX_ROW_EN[0] = 0x10
2283 10:01:21.626574 EX_ROW_EN[1] = 0x0
2284 10:01:21.626698 LP4Y_EN = 0x0
2285 10:01:21.630000 WORK_FSP = 0x0
2286 10:01:21.630083 WL = 0x4
2287 10:01:21.633188 RL = 0x4
2288 10:01:21.633271 BL = 0x2
2289 10:01:21.636480 RPST = 0x0
2290 10:01:21.636563 RD_PRE = 0x0
2291 10:01:21.639847 WR_PRE = 0x1
2292 10:01:21.639930 WR_PST = 0x0
2293 10:01:21.643062 DBI_WR = 0x0
2294 10:01:21.643168 DBI_RD = 0x0
2295 10:01:21.646443 OTF = 0x1
2296 10:01:21.649892 ===================================
2297 10:01:21.656791 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 10:01:21.656871 ==
2299 10:01:21.660020 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 10:01:21.663429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 10:01:21.663509 ==
2302 10:01:21.666506 [Duty_Offset_Calibration]
2303 10:01:21.666585 B0:1 B1:-1 CA:0
2304 10:01:21.666658
2305 10:01:21.670086 [DutyScan_Calibration_Flow] k_type=0
2306 10:01:21.680817
2307 10:01:21.680896 ==CLK 0==
2308 10:01:21.683881 Final CLK duty delay cell = 0
2309 10:01:21.687020 [0] MAX Duty = 5125%(X100), DQS PI = 24
2310 10:01:21.690409 [0] MIN Duty = 4907%(X100), DQS PI = 8
2311 10:01:21.690488 [0] AVG Duty = 5016%(X100)
2312 10:01:21.693775
2313 10:01:21.693854 CH0 CLK Duty spec in!! Max-Min= 218%
2314 10:01:21.700411 [DutyScan_Calibration_Flow] ====Done====
2315 10:01:21.700490
2316 10:01:21.703719 [DutyScan_Calibration_Flow] k_type=1
2317 10:01:21.718214
2318 10:01:21.718293 ==DQS 0 ==
2319 10:01:21.721335 Final DQS duty delay cell = -4
2320 10:01:21.724813 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2321 10:01:21.728206 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2322 10:01:21.731487 [-4] AVG Duty = 4968%(X100)
2323 10:01:21.731567
2324 10:01:21.731628 ==DQS 1 ==
2325 10:01:21.734928 Final DQS duty delay cell = -4
2326 10:01:21.737836 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2327 10:01:21.741167 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2328 10:01:21.744208 [-4] AVG Duty = 4938%(X100)
2329 10:01:21.744289
2330 10:01:21.747763 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2331 10:01:21.747835
2332 10:01:21.751119 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2333 10:01:21.754978 [DutyScan_Calibration_Flow] ====Done====
2334 10:01:21.755056
2335 10:01:21.757446 [DutyScan_Calibration_Flow] k_type=3
2336 10:01:21.775989
2337 10:01:21.776068 ==DQM 0 ==
2338 10:01:21.779658 Final DQM duty delay cell = 0
2339 10:01:21.782897 [0] MAX Duty = 5062%(X100), DQS PI = 40
2340 10:01:21.785890 [0] MIN Duty = 4875%(X100), DQS PI = 8
2341 10:01:21.789191 [0] AVG Duty = 4968%(X100)
2342 10:01:21.789269
2343 10:01:21.789331 ==DQM 1 ==
2344 10:01:21.792642 Final DQM duty delay cell = 4
2345 10:01:21.796181 [4] MAX Duty = 5187%(X100), DQS PI = 14
2346 10:01:21.799314 [4] MIN Duty = 5000%(X100), DQS PI = 24
2347 10:01:21.802359 [4] AVG Duty = 5093%(X100)
2348 10:01:21.802437
2349 10:01:21.806022 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2350 10:01:21.806101
2351 10:01:21.808999 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2352 10:01:21.812344 [DutyScan_Calibration_Flow] ====Done====
2353 10:01:21.812423
2354 10:01:21.815839 [DutyScan_Calibration_Flow] k_type=2
2355 10:01:21.831421
2356 10:01:21.831501 ==DQ 0 ==
2357 10:01:21.834505 Final DQ duty delay cell = -4
2358 10:01:21.837757 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2359 10:01:21.840904 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2360 10:01:21.844294 [-4] AVG Duty = 4969%(X100)
2361 10:01:21.844373
2362 10:01:21.844436 ==DQ 1 ==
2363 10:01:21.847783 Final DQ duty delay cell = -4
2364 10:01:21.850882 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2365 10:01:21.853939 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2366 10:01:21.857474 [-4] AVG Duty = 4938%(X100)
2367 10:01:21.857544
2368 10:01:21.860745 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2369 10:01:21.860824
2370 10:01:21.864312 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2371 10:01:21.867323 [DutyScan_Calibration_Flow] ====Done====
2372 10:01:21.867402 ==
2373 10:01:21.870816 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 10:01:21.874001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 10:01:21.874081 ==
2376 10:01:21.877591 [Duty_Offset_Calibration]
2377 10:01:21.877700 B0:-1 B1:1 CA:1
2378 10:01:21.880371
2379 10:01:21.883783 [DutyScan_Calibration_Flow] k_type=0
2380 10:01:21.891696
2381 10:01:21.891775 ==CLK 0==
2382 10:01:21.894716 Final CLK duty delay cell = 0
2383 10:01:21.898798 [0] MAX Duty = 5156%(X100), DQS PI = 4
2384 10:01:21.901195 [0] MIN Duty = 5000%(X100), DQS PI = 28
2385 10:01:21.901274 [0] AVG Duty = 5078%(X100)
2386 10:01:21.904970
2387 10:01:21.908333 CH1 CLK Duty spec in!! Max-Min= 156%
2388 10:01:21.911700 [DutyScan_Calibration_Flow] ====Done====
2389 10:01:21.911779
2390 10:01:21.914595 [DutyScan_Calibration_Flow] k_type=1
2391 10:01:21.930882
2392 10:01:21.930963 ==DQS 0 ==
2393 10:01:21.934103 Final DQS duty delay cell = 0
2394 10:01:21.937313 [0] MAX Duty = 5156%(X100), DQS PI = 16
2395 10:01:21.940435 [0] MIN Duty = 4907%(X100), DQS PI = 38
2396 10:01:21.943777 [0] AVG Duty = 5031%(X100)
2397 10:01:21.943857
2398 10:01:21.943920 ==DQS 1 ==
2399 10:01:21.947333 Final DQS duty delay cell = 0
2400 10:01:21.950438 [0] MAX Duty = 5094%(X100), DQS PI = 42
2401 10:01:21.953939 [0] MIN Duty = 4969%(X100), DQS PI = 28
2402 10:01:21.957735 [0] AVG Duty = 5031%(X100)
2403 10:01:21.957814
2404 10:01:21.960401 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2405 10:01:21.960480
2406 10:01:21.963541 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2407 10:01:21.967265 [DutyScan_Calibration_Flow] ====Done====
2408 10:01:21.967343
2409 10:01:21.970533 [DutyScan_Calibration_Flow] k_type=3
2410 10:01:21.986283
2411 10:01:21.986397 ==DQM 0 ==
2412 10:01:21.989861 Final DQM duty delay cell = -4
2413 10:01:21.993517 [-4] MAX Duty = 5062%(X100), DQS PI = 2
2414 10:01:21.996412 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2415 10:01:21.999709 [-4] AVG Duty = 4969%(X100)
2416 10:01:21.999788
2417 10:01:21.999852 ==DQM 1 ==
2418 10:01:22.003198 Final DQM duty delay cell = 0
2419 10:01:22.006259 [0] MAX Duty = 5187%(X100), DQS PI = 34
2420 10:01:22.009478 [0] MIN Duty = 4969%(X100), DQS PI = 2
2421 10:01:22.013291 [0] AVG Duty = 5078%(X100)
2422 10:01:22.013370
2423 10:01:22.016463 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2424 10:01:22.016551
2425 10:01:22.019658 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2426 10:01:22.023276 [DutyScan_Calibration_Flow] ====Done====
2427 10:01:22.023355
2428 10:01:22.026036 [DutyScan_Calibration_Flow] k_type=2
2429 10:01:22.043323
2430 10:01:22.043402 ==DQ 0 ==
2431 10:01:22.046571 Final DQ duty delay cell = 0
2432 10:01:22.049636 [0] MAX Duty = 5156%(X100), DQS PI = 60
2433 10:01:22.053195 [0] MIN Duty = 4907%(X100), DQS PI = 38
2434 10:01:22.053274 [0] AVG Duty = 5031%(X100)
2435 10:01:22.056758
2436 10:01:22.056837 ==DQ 1 ==
2437 10:01:22.059961 Final DQ duty delay cell = 0
2438 10:01:22.063133 [0] MAX Duty = 5124%(X100), DQS PI = 42
2439 10:01:22.066408 [0] MIN Duty = 4969%(X100), DQS PI = 0
2440 10:01:22.066491 [0] AVG Duty = 5046%(X100)
2441 10:01:22.066553
2442 10:01:22.070065 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2443 10:01:22.073433
2444 10:01:22.076400 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2445 10:01:22.079617 [DutyScan_Calibration_Flow] ====Done====
2446 10:01:22.083185 nWR fixed to 30
2447 10:01:22.083265 [ModeRegInit_LP4] CH0 RK0
2448 10:01:22.086290 [ModeRegInit_LP4] CH0 RK1
2449 10:01:22.089581 [ModeRegInit_LP4] CH1 RK0
2450 10:01:22.092768 [ModeRegInit_LP4] CH1 RK1
2451 10:01:22.092872 match AC timing 7
2452 10:01:22.097108 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 10:01:22.102539 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 10:01:22.106214 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 10:01:22.112647 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 10:01:22.116211 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 10:01:22.116292 ==
2458 10:01:22.119414 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 10:01:22.122531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 10:01:22.122677 ==
2461 10:01:22.129211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 10:01:22.135891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2463 10:01:22.143093 [CA 0] Center 39 (9~70) winsize 62
2464 10:01:22.146540 [CA 1] Center 38 (8~69) winsize 62
2465 10:01:22.149840 [CA 2] Center 35 (5~66) winsize 62
2466 10:01:22.153134 [CA 3] Center 35 (5~65) winsize 61
2467 10:01:22.156863 [CA 4] Center 33 (3~63) winsize 61
2468 10:01:22.159752 [CA 5] Center 33 (3~63) winsize 61
2469 10:01:22.159832
2470 10:01:22.163356 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2471 10:01:22.163436
2472 10:01:22.166524 [CATrainingPosCal] consider 1 rank data
2473 10:01:22.169544 u2DelayCellTimex100 = 270/100 ps
2474 10:01:22.173126 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2475 10:01:22.176447 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2476 10:01:22.183059 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 10:01:22.186445 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2478 10:01:22.189848 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 10:01:22.193448 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2480 10:01:22.193528
2481 10:01:22.196318 CA PerBit enable=1, Macro0, CA PI delay=33
2482 10:01:22.196397
2483 10:01:22.199698 [CBTSetCACLKResult] CA Dly = 33
2484 10:01:22.199777 CS Dly: 8 (0~39)
2485 10:01:22.202857 ==
2486 10:01:22.202937 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 10:01:22.209664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 10:01:22.209745 ==
2489 10:01:22.213161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 10:01:22.219704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2491 10:01:22.229285 [CA 0] Center 38 (8~69) winsize 62
2492 10:01:22.232609 [CA 1] Center 39 (9~70) winsize 62
2493 10:01:22.235701 [CA 2] Center 35 (5~66) winsize 62
2494 10:01:22.238984 [CA 3] Center 34 (4~65) winsize 62
2495 10:01:22.242490 [CA 4] Center 33 (3~64) winsize 62
2496 10:01:22.245395 [CA 5] Center 33 (3~63) winsize 61
2497 10:01:22.245475
2498 10:01:22.248827 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2499 10:01:22.248907
2500 10:01:22.252276 [CATrainingPosCal] consider 2 rank data
2501 10:01:22.255503 u2DelayCellTimex100 = 270/100 ps
2502 10:01:22.258868 CA0 delay=39 (9~69),Diff = 6 PI (28 cell)
2503 10:01:22.265163 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2504 10:01:22.268699 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 10:01:22.271720 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2506 10:01:22.275046 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
2507 10:01:22.278464 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2508 10:01:22.278543
2509 10:01:22.281645 CA PerBit enable=1, Macro0, CA PI delay=33
2510 10:01:22.281733
2511 10:01:22.285406 [CBTSetCACLKResult] CA Dly = 33
2512 10:01:22.285485 CS Dly: 8 (0~40)
2513 10:01:22.288831
2514 10:01:22.292064 ----->DramcWriteLeveling(PI) begin...
2515 10:01:22.292144 ==
2516 10:01:22.295421 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 10:01:22.298538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 10:01:22.298641 ==
2519 10:01:22.301900 Write leveling (Byte 0): 34 => 34
2520 10:01:22.305275 Write leveling (Byte 1): 30 => 30
2521 10:01:22.308516 DramcWriteLeveling(PI) end<-----
2522 10:01:22.308595
2523 10:01:22.308657 ==
2524 10:01:22.311658 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 10:01:22.314937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 10:01:22.315017 ==
2527 10:01:22.318531 [Gating] SW mode calibration
2528 10:01:22.325131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 10:01:22.331739 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 10:01:22.334888 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2531 10:01:22.338550 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2532 10:01:22.345479 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 10:01:22.348510 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 10:01:22.351534 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 10:01:22.358151 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 10:01:22.362202 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2537 10:01:22.365225 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
2538 10:01:22.368104 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2539 10:01:22.375388 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2540 10:01:22.377951 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 10:01:22.381516 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 10:01:22.388323 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 10:01:22.391606 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 10:01:22.394917 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 10:01:22.401630 1 0 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2546 10:01:22.404670 1 1 0 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2547 10:01:22.408137 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2548 10:01:22.414489 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 10:01:22.418110 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 10:01:22.421293 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 10:01:22.427812 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 10:01:22.431363 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 10:01:22.434930 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2554 10:01:22.441358 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 10:01:22.444782 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:01:22.448101 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:01:22.454264 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 10:01:22.457689 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 10:01:22.461321 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 10:01:22.467883 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:01:22.470911 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 10:01:22.474211 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 10:01:22.481313 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 10:01:22.484141 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 10:01:22.488021 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 10:01:22.493980 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 10:01:22.497451 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 10:01:22.500777 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 10:01:22.507397 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 10:01:22.507476 Total UI for P1: 0, mck2ui 16
2571 10:01:22.514289 best dqsien dly found for B0: ( 1, 3, 26)
2572 10:01:22.517793 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 10:01:22.520602 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 10:01:22.524040 Total UI for P1: 0, mck2ui 16
2575 10:01:22.527346 best dqsien dly found for B1: ( 1, 3, 30)
2576 10:01:22.530581 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2577 10:01:22.533959 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2578 10:01:22.534038
2579 10:01:22.537269 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2580 10:01:22.543750 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2581 10:01:22.543829 [Gating] SW calibration Done
2582 10:01:22.543892 ==
2583 10:01:22.547379 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 10:01:22.553899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 10:01:22.553979 ==
2586 10:01:22.554041 RX Vref Scan: 0
2587 10:01:22.554100
2588 10:01:22.557290 RX Vref 0 -> 0, step: 1
2589 10:01:22.557368
2590 10:01:22.560560 RX Delay -40 -> 252, step: 8
2591 10:01:22.564102 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2592 10:01:22.567473 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2593 10:01:22.570684 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2594 10:01:22.576921 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2595 10:01:22.580452 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2596 10:01:22.583679 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2597 10:01:22.587314 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2598 10:01:22.590198 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2599 10:01:22.597261 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2600 10:01:22.599857 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2601 10:01:22.603263 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2602 10:01:22.606611 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2603 10:01:22.610102 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2604 10:01:22.616819 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2605 10:01:22.619755 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2606 10:01:22.623239 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2607 10:01:22.623319 ==
2608 10:01:22.626785 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 10:01:22.629787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 10:01:22.633349 ==
2611 10:01:22.633428 DQS Delay:
2612 10:01:22.633490 DQS0 = 0, DQS1 = 0
2613 10:01:22.636746 DQM Delay:
2614 10:01:22.636824 DQM0 = 119, DQM1 = 106
2615 10:01:22.639899 DQ Delay:
2616 10:01:22.643369 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2617 10:01:22.646572 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2618 10:01:22.649792 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2619 10:01:22.653401 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2620 10:01:22.653482
2621 10:01:22.653546
2622 10:01:22.653604 ==
2623 10:01:22.656757 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 10:01:22.659674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 10:01:22.659754 ==
2626 10:01:22.659817
2627 10:01:22.662927
2628 10:01:22.663005 TX Vref Scan disable
2629 10:01:22.666542 == TX Byte 0 ==
2630 10:01:22.669738 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2631 10:01:22.672861 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2632 10:01:22.676131 == TX Byte 1 ==
2633 10:01:22.679752 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2634 10:01:22.683207 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2635 10:01:22.683286 ==
2636 10:01:22.686617 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 10:01:22.692984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 10:01:22.693063 ==
2639 10:01:22.703463 TX Vref=22, minBit 13, minWin=25, winSum=418
2640 10:01:22.706902 TX Vref=24, minBit 13, minWin=25, winSum=417
2641 10:01:22.709962 TX Vref=26, minBit 1, minWin=26, winSum=431
2642 10:01:22.713495 TX Vref=28, minBit 13, minWin=26, winSum=434
2643 10:01:22.716812 TX Vref=30, minBit 8, minWin=26, winSum=432
2644 10:01:22.723611 TX Vref=32, minBit 4, minWin=26, winSum=438
2645 10:01:22.726987 [TxChooseVref] Worse bit 4, Min win 26, Win sum 438, Final Vref 32
2646 10:01:22.727092
2647 10:01:22.729817 Final TX Range 1 Vref 32
2648 10:01:22.729897
2649 10:01:22.729959 ==
2650 10:01:22.733740 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 10:01:22.737088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 10:01:22.739769 ==
2653 10:01:22.739847
2654 10:01:22.739909
2655 10:01:22.739967 TX Vref Scan disable
2656 10:01:22.743804 == TX Byte 0 ==
2657 10:01:22.747119 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2658 10:01:22.753341 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2659 10:01:22.753420 == TX Byte 1 ==
2660 10:01:22.756697 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2661 10:01:22.763415 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2662 10:01:22.763494
2663 10:01:22.763556 [DATLAT]
2664 10:01:22.763613 Freq=1200, CH0 RK0
2665 10:01:22.763670
2666 10:01:22.766452 DATLAT Default: 0xd
2667 10:01:22.766556 0, 0xFFFF, sum = 0
2668 10:01:22.769884 1, 0xFFFF, sum = 0
2669 10:01:22.773729 2, 0xFFFF, sum = 0
2670 10:01:22.773810 3, 0xFFFF, sum = 0
2671 10:01:22.776538 4, 0xFFFF, sum = 0
2672 10:01:22.776618 5, 0xFFFF, sum = 0
2673 10:01:22.779930 6, 0xFFFF, sum = 0
2674 10:01:22.780010 7, 0xFFFF, sum = 0
2675 10:01:22.783300 8, 0xFFFF, sum = 0
2676 10:01:22.783379 9, 0xFFFF, sum = 0
2677 10:01:22.786781 10, 0xFFFF, sum = 0
2678 10:01:22.786861 11, 0xFFFF, sum = 0
2679 10:01:22.789721 12, 0x0, sum = 1
2680 10:01:22.789801 13, 0x0, sum = 2
2681 10:01:22.793039 14, 0x0, sum = 3
2682 10:01:22.793119 15, 0x0, sum = 4
2683 10:01:22.796654 best_step = 13
2684 10:01:22.796732
2685 10:01:22.796794 ==
2686 10:01:22.800064 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 10:01:22.803559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 10:01:22.803639 ==
2689 10:01:22.803702 RX Vref Scan: 1
2690 10:01:22.803760
2691 10:01:22.806393 Set Vref Range= 32 -> 127
2692 10:01:22.806472
2693 10:01:22.809772 RX Vref 32 -> 127, step: 1
2694 10:01:22.809851
2695 10:01:22.812932 RX Delay -21 -> 252, step: 4
2696 10:01:22.813010
2697 10:01:22.816459 Set Vref, RX VrefLevel [Byte0]: 32
2698 10:01:22.819895 [Byte1]: 32
2699 10:01:22.819974
2700 10:01:22.823325 Set Vref, RX VrefLevel [Byte0]: 33
2701 10:01:22.826459 [Byte1]: 33
2702 10:01:22.830185
2703 10:01:22.830264 Set Vref, RX VrefLevel [Byte0]: 34
2704 10:01:22.833412 [Byte1]: 34
2705 10:01:22.837884
2706 10:01:22.837962 Set Vref, RX VrefLevel [Byte0]: 35
2707 10:01:22.841133 [Byte1]: 35
2708 10:01:22.845605
2709 10:01:22.845688 Set Vref, RX VrefLevel [Byte0]: 36
2710 10:01:22.849260 [Byte1]: 36
2711 10:01:22.853648
2712 10:01:22.853727 Set Vref, RX VrefLevel [Byte0]: 37
2713 10:01:22.857397 [Byte1]: 37
2714 10:01:22.861758
2715 10:01:22.864969 Set Vref, RX VrefLevel [Byte0]: 38
2716 10:01:22.868133 [Byte1]: 38
2717 10:01:22.868212
2718 10:01:22.871624 Set Vref, RX VrefLevel [Byte0]: 39
2719 10:01:22.874913 [Byte1]: 39
2720 10:01:22.874992
2721 10:01:22.877932 Set Vref, RX VrefLevel [Byte0]: 40
2722 10:01:22.881081 [Byte1]: 40
2723 10:01:22.885665
2724 10:01:22.885744 Set Vref, RX VrefLevel [Byte0]: 41
2725 10:01:22.888667 [Byte1]: 41
2726 10:01:22.893400
2727 10:01:22.893479 Set Vref, RX VrefLevel [Byte0]: 42
2728 10:01:22.896933 [Byte1]: 42
2729 10:01:22.901166
2730 10:01:22.901244 Set Vref, RX VrefLevel [Byte0]: 43
2731 10:01:22.904571 [Byte1]: 43
2732 10:01:22.909128
2733 10:01:22.909206 Set Vref, RX VrefLevel [Byte0]: 44
2734 10:01:22.912834 [Byte1]: 44
2735 10:01:22.917306
2736 10:01:22.917384 Set Vref, RX VrefLevel [Byte0]: 45
2737 10:01:22.920583 [Byte1]: 45
2738 10:01:22.925162
2739 10:01:22.925244 Set Vref, RX VrefLevel [Byte0]: 46
2740 10:01:22.928504 [Byte1]: 46
2741 10:01:22.933210
2742 10:01:22.933288 Set Vref, RX VrefLevel [Byte0]: 47
2743 10:01:22.936303 [Byte1]: 47
2744 10:01:22.940767
2745 10:01:22.940846 Set Vref, RX VrefLevel [Byte0]: 48
2746 10:01:22.944334 [Byte1]: 48
2747 10:01:22.949093
2748 10:01:22.949171 Set Vref, RX VrefLevel [Byte0]: 49
2749 10:01:22.952168 [Byte1]: 49
2750 10:01:22.956748
2751 10:01:22.956826 Set Vref, RX VrefLevel [Byte0]: 50
2752 10:01:22.960196 [Byte1]: 50
2753 10:01:22.964949
2754 10:01:22.965027 Set Vref, RX VrefLevel [Byte0]: 51
2755 10:01:22.967837 [Byte1]: 51
2756 10:01:22.972407
2757 10:01:22.972486 Set Vref, RX VrefLevel [Byte0]: 52
2758 10:01:22.976115 [Byte1]: 52
2759 10:01:22.980464
2760 10:01:22.980543 Set Vref, RX VrefLevel [Byte0]: 53
2761 10:01:22.984019 [Byte1]: 53
2762 10:01:22.988744
2763 10:01:22.988823 Set Vref, RX VrefLevel [Byte0]: 54
2764 10:01:22.991832 [Byte1]: 54
2765 10:01:22.996892
2766 10:01:22.996970 Set Vref, RX VrefLevel [Byte0]: 55
2767 10:01:23.000225 [Byte1]: 55
2768 10:01:23.004597
2769 10:01:23.004675 Set Vref, RX VrefLevel [Byte0]: 56
2770 10:01:23.008076 [Byte1]: 56
2771 10:01:23.012057
2772 10:01:23.012136 Set Vref, RX VrefLevel [Byte0]: 57
2773 10:01:23.015668 [Byte1]: 57
2774 10:01:23.020160
2775 10:01:23.020238 Set Vref, RX VrefLevel [Byte0]: 58
2776 10:01:23.023321 [Byte1]: 58
2777 10:01:23.028674
2778 10:01:23.028753 Set Vref, RX VrefLevel [Byte0]: 59
2779 10:01:23.031395 [Byte1]: 59
2780 10:01:23.036072
2781 10:01:23.036150 Set Vref, RX VrefLevel [Byte0]: 60
2782 10:01:23.039603 [Byte1]: 60
2783 10:01:23.044038
2784 10:01:23.044116 Set Vref, RX VrefLevel [Byte0]: 61
2785 10:01:23.047228 [Byte1]: 61
2786 10:01:23.051862
2787 10:01:23.051940 Set Vref, RX VrefLevel [Byte0]: 62
2788 10:01:23.055175 [Byte1]: 62
2789 10:01:23.060080
2790 10:01:23.060158 Set Vref, RX VrefLevel [Byte0]: 63
2791 10:01:23.063277 [Byte1]: 63
2792 10:01:23.067967
2793 10:01:23.068046 Set Vref, RX VrefLevel [Byte0]: 64
2794 10:01:23.071177 [Byte1]: 64
2795 10:01:23.075587
2796 10:01:23.075662 Set Vref, RX VrefLevel [Byte0]: 65
2797 10:01:23.079065 [Byte1]: 65
2798 10:01:23.083347
2799 10:01:23.083427 Set Vref, RX VrefLevel [Byte0]: 66
2800 10:01:23.086863 [Byte1]: 66
2801 10:01:23.091873
2802 10:01:23.091951 Set Vref, RX VrefLevel [Byte0]: 67
2803 10:01:23.095044 [Byte1]: 67
2804 10:01:23.099623
2805 10:01:23.099701 Set Vref, RX VrefLevel [Byte0]: 68
2806 10:01:23.102630 [Byte1]: 68
2807 10:01:23.107547
2808 10:01:23.107625 Set Vref, RX VrefLevel [Byte0]: 69
2809 10:01:23.110532 [Byte1]: 69
2810 10:01:23.115245
2811 10:01:23.115323 Set Vref, RX VrefLevel [Byte0]: 70
2812 10:01:23.118890 [Byte1]: 70
2813 10:01:23.123159
2814 10:01:23.123237 Set Vref, RX VrefLevel [Byte0]: 71
2815 10:01:23.126457 [Byte1]: 71
2816 10:01:23.131352
2817 10:01:23.131431 Set Vref, RX VrefLevel [Byte0]: 72
2818 10:01:23.134371 [Byte1]: 72
2819 10:01:23.139543
2820 10:01:23.139620 Set Vref, RX VrefLevel [Byte0]: 73
2821 10:01:23.142514 [Byte1]: 73
2822 10:01:23.147123
2823 10:01:23.147200 Set Vref, RX VrefLevel [Byte0]: 74
2824 10:01:23.150582 [Byte1]: 74
2825 10:01:23.154730
2826 10:01:23.154807 Set Vref, RX VrefLevel [Byte0]: 75
2827 10:01:23.161439 [Byte1]: 75
2828 10:01:23.161518
2829 10:01:23.164401 Set Vref, RX VrefLevel [Byte0]: 76
2830 10:01:23.168234 [Byte1]: 76
2831 10:01:23.168312
2832 10:01:23.171126 Set Vref, RX VrefLevel [Byte0]: 77
2833 10:01:23.174552 [Byte1]: 77
2834 10:01:23.178707
2835 10:01:23.178786 Set Vref, RX VrefLevel [Byte0]: 78
2836 10:01:23.181886 [Byte1]: 78
2837 10:01:23.186568
2838 10:01:23.186684 Final RX Vref Byte 0 = 61 to rank0
2839 10:01:23.190347 Final RX Vref Byte 1 = 47 to rank0
2840 10:01:23.193184 Final RX Vref Byte 0 = 61 to rank1
2841 10:01:23.196604 Final RX Vref Byte 1 = 47 to rank1==
2842 10:01:23.200125 Dram Type= 6, Freq= 0, CH_0, rank 0
2843 10:01:23.206877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 10:01:23.206956 ==
2845 10:01:23.207020 DQS Delay:
2846 10:01:23.210057 DQS0 = 0, DQS1 = 0
2847 10:01:23.210135 DQM Delay:
2848 10:01:23.210198 DQM0 = 119, DQM1 = 105
2849 10:01:23.212855 DQ Delay:
2850 10:01:23.217020 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2851 10:01:23.219704 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =126
2852 10:01:23.222966 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =98
2853 10:01:23.226434 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =116
2854 10:01:23.226513
2855 10:01:23.226575
2856 10:01:23.232879 [DQSOSCAuto] RK0, (LSB)MR18= 0xffa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2857 10:01:23.236207 CH0 RK0: MR19=403, MR18=FFA
2858 10:01:23.243314 CH0_RK0: MR19=0x403, MR18=0xFFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2859 10:01:23.243393
2860 10:01:23.246101 ----->DramcWriteLeveling(PI) begin...
2861 10:01:23.246181 ==
2862 10:01:23.249549 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 10:01:23.253042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2864 10:01:23.256008 ==
2865 10:01:23.256087 Write leveling (Byte 0): 31 => 31
2866 10:01:23.259238 Write leveling (Byte 1): 30 => 30
2867 10:01:23.262529 DramcWriteLeveling(PI) end<-----
2868 10:01:23.262645
2869 10:01:23.262707 ==
2870 10:01:23.265853 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 10:01:23.272560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 10:01:23.272639 ==
2873 10:01:23.275896 [Gating] SW mode calibration
2874 10:01:23.282713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2875 10:01:23.285916 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2876 10:01:23.292778 0 15 0 | B1->B0 | 2525 3232 | 1 0 | (0 0) (0 0)
2877 10:01:23.295803 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 10:01:23.299230 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 10:01:23.305606 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 10:01:23.308900 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 10:01:23.312295 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 10:01:23.319206 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 10:01:23.322990 0 15 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2884 10:01:23.325601 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2885 10:01:23.329056 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 10:01:23.335434 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 10:01:23.339066 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 10:01:23.342076 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 10:01:23.348922 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 10:01:23.352264 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 10:01:23.355374 1 0 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2892 10:01:23.362007 1 1 0 | B1->B0 | 3b3a 4646 | 1 0 | (0 0) (0 0)
2893 10:01:23.365515 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 10:01:23.369037 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 10:01:23.375454 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 10:01:23.379173 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 10:01:23.382183 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 10:01:23.388630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 10:01:23.392276 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2900 10:01:23.395714 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 10:01:23.401701 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 10:01:23.405534 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 10:01:23.408841 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 10:01:23.415426 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 10:01:23.418699 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 10:01:23.421649 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 10:01:23.428344 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 10:01:23.431769 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 10:01:23.435331 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 10:01:23.441528 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 10:01:23.444993 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 10:01:23.448490 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 10:01:23.454711 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 10:01:23.457910 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2915 10:01:23.461417 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2916 10:01:23.468171 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2917 10:01:23.468250 Total UI for P1: 0, mck2ui 16
2918 10:01:23.474635 best dqsien dly found for B0: ( 1, 3, 26)
2919 10:01:23.477825 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 10:01:23.481067 Total UI for P1: 0, mck2ui 16
2921 10:01:23.484646 best dqsien dly found for B1: ( 1, 3, 30)
2922 10:01:23.487736 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2923 10:01:23.491098 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2924 10:01:23.491177
2925 10:01:23.494351 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2926 10:01:23.497772 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2927 10:01:23.501132 [Gating] SW calibration Done
2928 10:01:23.501211 ==
2929 10:01:23.504460 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 10:01:23.507583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 10:01:23.511229 ==
2932 10:01:23.511307 RX Vref Scan: 0
2933 10:01:23.511369
2934 10:01:23.514494 RX Vref 0 -> 0, step: 1
2935 10:01:23.514572
2936 10:01:23.517740 RX Delay -40 -> 252, step: 8
2937 10:01:23.521153 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2938 10:01:23.524635 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2939 10:01:23.527481 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2940 10:01:23.531141 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2941 10:01:23.537546 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2942 10:01:23.540845 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2943 10:01:23.544355 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2944 10:01:23.547667 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2945 10:01:23.550959 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2946 10:01:23.554527 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2947 10:01:23.560743 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2948 10:01:23.564073 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2949 10:01:23.567432 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2950 10:01:23.571112 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2951 10:01:23.577811 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2952 10:01:23.580838 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2953 10:01:23.580917 ==
2954 10:01:23.584011 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 10:01:23.587365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 10:01:23.587444 ==
2957 10:01:23.590949 DQS Delay:
2958 10:01:23.591028 DQS0 = 0, DQS1 = 0
2959 10:01:23.591090 DQM Delay:
2960 10:01:23.594053 DQM0 = 116, DQM1 = 108
2961 10:01:23.594131 DQ Delay:
2962 10:01:23.597659 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2963 10:01:23.600554 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2964 10:01:23.603890 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2965 10:01:23.610545 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2966 10:01:23.610633
2967 10:01:23.610696
2968 10:01:23.610754 ==
2969 10:01:23.613744 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 10:01:23.617423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 10:01:23.617502 ==
2972 10:01:23.617565
2973 10:01:23.617623
2974 10:01:23.620786 TX Vref Scan disable
2975 10:01:23.620864 == TX Byte 0 ==
2976 10:01:23.627319 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2977 10:01:23.630979 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2978 10:01:23.631059 == TX Byte 1 ==
2979 10:01:23.637521 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2980 10:01:23.640844 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2981 10:01:23.640922 ==
2982 10:01:23.644140 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 10:01:23.646889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 10:01:23.646968 ==
2985 10:01:23.659824 TX Vref=22, minBit 3, minWin=25, winSum=417
2986 10:01:23.663355 TX Vref=24, minBit 0, minWin=26, winSum=422
2987 10:01:23.666419 TX Vref=26, minBit 1, minWin=26, winSum=425
2988 10:01:23.669891 TX Vref=28, minBit 1, minWin=26, winSum=424
2989 10:01:23.673425 TX Vref=30, minBit 10, minWin=26, winSum=429
2990 10:01:23.680227 TX Vref=32, minBit 13, minWin=25, winSum=429
2991 10:01:23.682944 [TxChooseVref] Worse bit 10, Min win 26, Win sum 429, Final Vref 30
2992 10:01:23.683023
2993 10:01:23.686290 Final TX Range 1 Vref 30
2994 10:01:23.686368
2995 10:01:23.686430 ==
2996 10:01:23.689564 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 10:01:23.692987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 10:01:23.696098 ==
2999 10:01:23.696176
3000 10:01:23.696237
3001 10:01:23.696295 TX Vref Scan disable
3002 10:01:23.699747 == TX Byte 0 ==
3003 10:01:23.702915 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3004 10:01:23.706767 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3005 10:01:23.709599 == TX Byte 1 ==
3006 10:01:23.713040 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3007 10:01:23.719461 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3008 10:01:23.719540
3009 10:01:23.719603 [DATLAT]
3010 10:01:23.719661 Freq=1200, CH0 RK1
3011 10:01:23.719717
3012 10:01:23.723154 DATLAT Default: 0xd
3013 10:01:23.723232 0, 0xFFFF, sum = 0
3014 10:01:23.726257 1, 0xFFFF, sum = 0
3015 10:01:23.729615 2, 0xFFFF, sum = 0
3016 10:01:23.729695 3, 0xFFFF, sum = 0
3017 10:01:23.732801 4, 0xFFFF, sum = 0
3018 10:01:23.732881 5, 0xFFFF, sum = 0
3019 10:01:23.736068 6, 0xFFFF, sum = 0
3020 10:01:23.736148 7, 0xFFFF, sum = 0
3021 10:01:23.739458 8, 0xFFFF, sum = 0
3022 10:01:23.739538 9, 0xFFFF, sum = 0
3023 10:01:23.743351 10, 0xFFFF, sum = 0
3024 10:01:23.743431 11, 0xFFFF, sum = 0
3025 10:01:23.746007 12, 0x0, sum = 1
3026 10:01:23.746086 13, 0x0, sum = 2
3027 10:01:23.749446 14, 0x0, sum = 3
3028 10:01:23.749526 15, 0x0, sum = 4
3029 10:01:23.752837 best_step = 13
3030 10:01:23.752915
3031 10:01:23.752976 ==
3032 10:01:23.756545 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 10:01:23.759410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 10:01:23.759489 ==
3035 10:01:23.759552 RX Vref Scan: 0
3036 10:01:23.759610
3037 10:01:23.762971 RX Vref 0 -> 0, step: 1
3038 10:01:23.763049
3039 10:01:23.766178 RX Delay -21 -> 252, step: 4
3040 10:01:23.769598 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3041 10:01:23.776391 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3042 10:01:23.779188 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3043 10:01:23.782711 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3044 10:01:23.786234 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3045 10:01:23.789026 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3046 10:01:23.796319 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3047 10:01:23.799019 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3048 10:01:23.802476 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3049 10:01:23.806013 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3050 10:01:23.809221 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3051 10:01:23.815364 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3052 10:01:23.818718 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3053 10:01:23.822326 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3054 10:01:23.825533 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3055 10:01:23.832441 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3056 10:01:23.832520 ==
3057 10:01:23.835807 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 10:01:23.839114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 10:01:23.839194 ==
3060 10:01:23.839256 DQS Delay:
3061 10:01:23.842177 DQS0 = 0, DQS1 = 0
3062 10:01:23.842256 DQM Delay:
3063 10:01:23.845541 DQM0 = 116, DQM1 = 106
3064 10:01:23.845619 DQ Delay:
3065 10:01:23.848928 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3066 10:01:23.851794 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3067 10:01:23.855388 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3068 10:01:23.859044 DQ12 =110, DQ13 =112, DQ14 =118, DQ15 =116
3069 10:01:23.859124
3070 10:01:23.859186
3071 10:01:23.868505 [DQSOSCAuto] RK1, (LSB)MR18= 0xce6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3072 10:01:23.872060 CH0 RK1: MR19=403, MR18=CE6
3073 10:01:23.875166 CH0_RK1: MR19=0x403, MR18=0xCE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3074 10:01:23.878498 [RxdqsGatingPostProcess] freq 1200
3075 10:01:23.885536 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3076 10:01:23.888356 best DQS0 dly(2T, 0.5T) = (0, 11)
3077 10:01:23.891930 best DQS1 dly(2T, 0.5T) = (0, 11)
3078 10:01:23.895051 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3079 10:01:23.898389 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3080 10:01:23.901893 best DQS0 dly(2T, 0.5T) = (0, 11)
3081 10:01:23.905152 best DQS1 dly(2T, 0.5T) = (0, 11)
3082 10:01:23.908372 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3083 10:01:23.911482 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3084 10:01:23.914910 Pre-setting of DQS Precalculation
3085 10:01:23.918169 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3086 10:01:23.918248 ==
3087 10:01:23.921477 Dram Type= 6, Freq= 0, CH_1, rank 0
3088 10:01:23.924899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 10:01:23.924979 ==
3090 10:01:23.931352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3091 10:01:23.938179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3092 10:01:23.945963 [CA 0] Center 37 (7~67) winsize 61
3093 10:01:23.949158 [CA 1] Center 37 (7~68) winsize 62
3094 10:01:23.952591 [CA 2] Center 34 (4~64) winsize 61
3095 10:01:23.955872 [CA 3] Center 33 (3~64) winsize 62
3096 10:01:23.959398 [CA 4] Center 34 (4~64) winsize 61
3097 10:01:23.962711 [CA 5] Center 33 (3~64) winsize 62
3098 10:01:23.962790
3099 10:01:23.966005 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3100 10:01:23.966085
3101 10:01:23.968994 [CATrainingPosCal] consider 1 rank data
3102 10:01:23.972709 u2DelayCellTimex100 = 270/100 ps
3103 10:01:23.975622 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3104 10:01:23.982448 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3105 10:01:23.985852 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 10:01:23.988793 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3107 10:01:23.992158 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 10:01:23.995658 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3109 10:01:23.995737
3110 10:01:23.998730 CA PerBit enable=1, Macro0, CA PI delay=33
3111 10:01:23.998838
3112 10:01:24.002376 [CBTSetCACLKResult] CA Dly = 33
3113 10:01:24.005510 CS Dly: 5 (0~36)
3114 10:01:24.005589 ==
3115 10:01:24.009103 Dram Type= 6, Freq= 0, CH_1, rank 1
3116 10:01:24.012583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 10:01:24.012663 ==
3118 10:01:24.018609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3119 10:01:24.022094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3120 10:01:24.031500 [CA 0] Center 37 (7~67) winsize 61
3121 10:01:24.035314 [CA 1] Center 37 (7~68) winsize 62
3122 10:01:24.038148 [CA 2] Center 34 (3~65) winsize 63
3123 10:01:24.041716 [CA 3] Center 33 (3~64) winsize 62
3124 10:01:24.044931 [CA 4] Center 33 (3~64) winsize 62
3125 10:01:24.048011 [CA 5] Center 33 (3~64) winsize 62
3126 10:01:24.048090
3127 10:01:24.051734 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3128 10:01:24.051813
3129 10:01:24.054642 [CATrainingPosCal] consider 2 rank data
3130 10:01:24.058489 u2DelayCellTimex100 = 270/100 ps
3131 10:01:24.061653 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3132 10:01:24.068141 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 10:01:24.071485 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 10:01:24.074860 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3135 10:01:24.077728 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 10:01:24.081218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3137 10:01:24.081298
3138 10:01:24.084665 CA PerBit enable=1, Macro0, CA PI delay=33
3139 10:01:24.084745
3140 10:01:24.087770 [CBTSetCACLKResult] CA Dly = 33
3141 10:01:24.087850 CS Dly: 7 (0~40)
3142 10:01:24.091215
3143 10:01:24.094889 ----->DramcWriteLeveling(PI) begin...
3144 10:01:24.094970 ==
3145 10:01:24.097621 Dram Type= 6, Freq= 0, CH_1, rank 0
3146 10:01:24.101133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 10:01:24.101217 ==
3148 10:01:24.104597 Write leveling (Byte 0): 25 => 25
3149 10:01:24.107954 Write leveling (Byte 1): 29 => 29
3150 10:01:24.111529 DramcWriteLeveling(PI) end<-----
3151 10:01:24.111608
3152 10:01:24.111672 ==
3153 10:01:24.114754 Dram Type= 6, Freq= 0, CH_1, rank 0
3154 10:01:24.117448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3155 10:01:24.117528 ==
3156 10:01:24.121177 [Gating] SW mode calibration
3157 10:01:24.127435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3158 10:01:24.134550 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3159 10:01:24.137380 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3160 10:01:24.141001 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 10:01:24.147585 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 10:01:24.151167 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 10:01:24.154304 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 10:01:24.160979 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 10:01:24.164386 0 15 24 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
3166 10:01:24.167466 0 15 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
3167 10:01:24.174056 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 10:01:24.177786 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 10:01:24.180721 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 10:01:24.187712 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 10:01:24.190830 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 10:01:24.194278 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 10:01:24.200612 1 0 24 | B1->B0 | 2626 4141 | 0 0 | (0 0) (0 0)
3174 10:01:24.203968 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3175 10:01:24.207090 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 10:01:24.213841 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 10:01:24.217428 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 10:01:24.220102 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 10:01:24.226748 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 10:01:24.230305 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 10:01:24.233565 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3182 10:01:24.236661 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3183 10:01:24.243231 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 10:01:24.246864 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 10:01:24.250523 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 10:01:24.257055 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 10:01:24.259887 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 10:01:24.263595 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 10:01:24.270237 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 10:01:24.273352 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 10:01:24.276733 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 10:01:24.283557 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 10:01:24.286911 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 10:01:24.289681 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 10:01:24.296462 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 10:01:24.300121 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 10:01:24.303538 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3198 10:01:24.309927 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 10:01:24.310006 Total UI for P1: 0, mck2ui 16
3200 10:01:24.316358 best dqsien dly found for B0: ( 1, 3, 24)
3201 10:01:24.316437 Total UI for P1: 0, mck2ui 16
3202 10:01:24.323179 best dqsien dly found for B1: ( 1, 3, 26)
3203 10:01:24.326469 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3204 10:01:24.329837 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3205 10:01:24.329916
3206 10:01:24.333229 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3207 10:01:24.336544 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3208 10:01:24.340267 [Gating] SW calibration Done
3209 10:01:24.340345 ==
3210 10:01:24.343513 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 10:01:24.346446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 10:01:24.346551 ==
3213 10:01:24.349806 RX Vref Scan: 0
3214 10:01:24.349883
3215 10:01:24.349945 RX Vref 0 -> 0, step: 1
3216 10:01:24.350003
3217 10:01:24.353051 RX Delay -40 -> 252, step: 8
3218 10:01:24.356409 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3219 10:01:24.363095 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3220 10:01:24.366933 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3221 10:01:24.369473 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3222 10:01:24.372916 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3223 10:01:24.376738 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3224 10:01:24.382998 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3225 10:01:24.386857 iDelay=208, Bit 7, Center 119 (56 ~ 183) 128
3226 10:01:24.389535 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3227 10:01:24.393592 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3228 10:01:24.396010 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3229 10:01:24.402881 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3230 10:01:24.406261 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3231 10:01:24.409756 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3232 10:01:24.413049 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3233 10:01:24.416428 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3234 10:01:24.419506 ==
3235 10:01:24.423085 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 10:01:24.426164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 10:01:24.426244 ==
3238 10:01:24.426306 DQS Delay:
3239 10:01:24.429595 DQS0 = 0, DQS1 = 0
3240 10:01:24.429674 DQM Delay:
3241 10:01:24.432942 DQM0 = 120, DQM1 = 111
3242 10:01:24.433021 DQ Delay:
3243 10:01:24.436133 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3244 10:01:24.439677 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =119
3245 10:01:24.443132 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =99
3246 10:01:24.446039 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3247 10:01:24.446118
3248 10:01:24.446181
3249 10:01:24.446238 ==
3250 10:01:24.449466 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 10:01:24.456132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 10:01:24.456214 ==
3253 10:01:24.456276
3254 10:01:24.456334
3255 10:01:24.456389 TX Vref Scan disable
3256 10:01:24.459379 == TX Byte 0 ==
3257 10:01:24.463059 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3258 10:01:24.466535 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3259 10:01:24.469947 == TX Byte 1 ==
3260 10:01:24.472674 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3261 10:01:24.476583 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3262 10:01:24.479555 ==
3263 10:01:24.482845 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 10:01:24.486213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 10:01:24.486292 ==
3266 10:01:24.497586 TX Vref=22, minBit 11, minWin=24, winSum=416
3267 10:01:24.500853 TX Vref=24, minBit 0, minWin=25, winSum=420
3268 10:01:24.503977 TX Vref=26, minBit 11, minWin=25, winSum=426
3269 10:01:24.507145 TX Vref=28, minBit 10, minWin=25, winSum=427
3270 10:01:24.510514 TX Vref=30, minBit 0, minWin=26, winSum=429
3271 10:01:24.517140 TX Vref=32, minBit 7, minWin=26, winSum=430
3272 10:01:24.520371 [TxChooseVref] Worse bit 7, Min win 26, Win sum 430, Final Vref 32
3273 10:01:24.520450
3274 10:01:24.523725 Final TX Range 1 Vref 32
3275 10:01:24.523805
3276 10:01:24.523867 ==
3277 10:01:24.527132 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 10:01:24.534088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 10:01:24.534167 ==
3280 10:01:24.534230
3281 10:01:24.534288
3282 10:01:24.534343 TX Vref Scan disable
3283 10:01:24.537289 == TX Byte 0 ==
3284 10:01:24.541091 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3285 10:01:24.547276 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3286 10:01:24.547356 == TX Byte 1 ==
3287 10:01:24.550885 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3288 10:01:24.553987 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3289 10:01:24.557562
3290 10:01:24.557640 [DATLAT]
3291 10:01:24.557702 Freq=1200, CH1 RK0
3292 10:01:24.557760
3293 10:01:24.560407 DATLAT Default: 0xd
3294 10:01:24.560484 0, 0xFFFF, sum = 0
3295 10:01:24.564114 1, 0xFFFF, sum = 0
3296 10:01:24.564193 2, 0xFFFF, sum = 0
3297 10:01:24.567210 3, 0xFFFF, sum = 0
3298 10:01:24.570497 4, 0xFFFF, sum = 0
3299 10:01:24.570576 5, 0xFFFF, sum = 0
3300 10:01:24.573935 6, 0xFFFF, sum = 0
3301 10:01:24.574013 7, 0xFFFF, sum = 0
3302 10:01:24.577245 8, 0xFFFF, sum = 0
3303 10:01:24.577324 9, 0xFFFF, sum = 0
3304 10:01:24.580939 10, 0xFFFF, sum = 0
3305 10:01:24.581018 11, 0xFFFF, sum = 0
3306 10:01:24.583738 12, 0x0, sum = 1
3307 10:01:24.583817 13, 0x0, sum = 2
3308 10:01:24.587323 14, 0x0, sum = 3
3309 10:01:24.587403 15, 0x0, sum = 4
3310 10:01:24.587465 best_step = 13
3311 10:01:24.590698
3312 10:01:24.590775 ==
3313 10:01:24.594220 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 10:01:24.597074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 10:01:24.597152 ==
3316 10:01:24.597214 RX Vref Scan: 1
3317 10:01:24.597271
3318 10:01:24.600700 Set Vref Range= 32 -> 127
3319 10:01:24.600778
3320 10:01:24.604291 RX Vref 32 -> 127, step: 1
3321 10:01:24.604369
3322 10:01:24.607463 RX Delay -13 -> 252, step: 4
3323 10:01:24.607540
3324 10:01:24.610595 Set Vref, RX VrefLevel [Byte0]: 32
3325 10:01:24.613864 [Byte1]: 32
3326 10:01:24.613941
3327 10:01:24.617408 Set Vref, RX VrefLevel [Byte0]: 33
3328 10:01:24.620940 [Byte1]: 33
3329 10:01:24.623686
3330 10:01:24.623764 Set Vref, RX VrefLevel [Byte0]: 34
3331 10:01:24.627046 [Byte1]: 34
3332 10:01:24.631509
3333 10:01:24.631587 Set Vref, RX VrefLevel [Byte0]: 35
3334 10:01:24.635054 [Byte1]: 35
3335 10:01:24.639431
3336 10:01:24.639508 Set Vref, RX VrefLevel [Byte0]: 36
3337 10:01:24.642953 [Byte1]: 36
3338 10:01:24.647145
3339 10:01:24.647223 Set Vref, RX VrefLevel [Byte0]: 37
3340 10:01:24.650554 [Byte1]: 37
3341 10:01:24.655255
3342 10:01:24.655333 Set Vref, RX VrefLevel [Byte0]: 38
3343 10:01:24.658952 [Byte1]: 38
3344 10:01:24.662911
3345 10:01:24.662988 Set Vref, RX VrefLevel [Byte0]: 39
3346 10:01:24.666730 [Byte1]: 39
3347 10:01:24.670805
3348 10:01:24.670882 Set Vref, RX VrefLevel [Byte0]: 40
3349 10:01:24.674144 [Byte1]: 40
3350 10:01:24.679113
3351 10:01:24.682211 Set Vref, RX VrefLevel [Byte0]: 41
3352 10:01:24.682290 [Byte1]: 41
3353 10:01:24.686541
3354 10:01:24.686626 Set Vref, RX VrefLevel [Byte0]: 42
3355 10:01:24.689944 [Byte1]: 42
3356 10:01:24.694556
3357 10:01:24.694688 Set Vref, RX VrefLevel [Byte0]: 43
3358 10:01:24.698124 [Byte1]: 43
3359 10:01:24.702391
3360 10:01:24.702468 Set Vref, RX VrefLevel [Byte0]: 44
3361 10:01:24.705985 [Byte1]: 44
3362 10:01:24.710334
3363 10:01:24.710411 Set Vref, RX VrefLevel [Byte0]: 45
3364 10:01:24.713481 [Byte1]: 45
3365 10:01:24.718093
3366 10:01:24.718178 Set Vref, RX VrefLevel [Byte0]: 46
3367 10:01:24.722034 [Byte1]: 46
3368 10:01:24.726403
3369 10:01:24.726481 Set Vref, RX VrefLevel [Byte0]: 47
3370 10:01:24.729547 [Byte1]: 47
3371 10:01:24.734063
3372 10:01:24.734142 Set Vref, RX VrefLevel [Byte0]: 48
3373 10:01:24.737356 [Byte1]: 48
3374 10:01:24.741915
3375 10:01:24.741994 Set Vref, RX VrefLevel [Byte0]: 49
3376 10:01:24.745262 [Byte1]: 49
3377 10:01:24.749882
3378 10:01:24.749962 Set Vref, RX VrefLevel [Byte0]: 50
3379 10:01:24.753018 [Byte1]: 50
3380 10:01:24.757529
3381 10:01:24.757607 Set Vref, RX VrefLevel [Byte0]: 51
3382 10:01:24.760980 [Byte1]: 51
3383 10:01:24.765721
3384 10:01:24.765799 Set Vref, RX VrefLevel [Byte0]: 52
3385 10:01:24.769440 [Byte1]: 52
3386 10:01:24.773516
3387 10:01:24.773596 Set Vref, RX VrefLevel [Byte0]: 53
3388 10:01:24.777303 [Byte1]: 53
3389 10:01:24.781423
3390 10:01:24.781502 Set Vref, RX VrefLevel [Byte0]: 54
3391 10:01:24.784960 [Byte1]: 54
3392 10:01:24.789503
3393 10:01:24.789583 Set Vref, RX VrefLevel [Byte0]: 55
3394 10:01:24.792611 [Byte1]: 55
3395 10:01:24.797004
3396 10:01:24.800561 Set Vref, RX VrefLevel [Byte0]: 56
3397 10:01:24.803567 [Byte1]: 56
3398 10:01:24.803647
3399 10:01:24.807105 Set Vref, RX VrefLevel [Byte0]: 57
3400 10:01:24.810394 [Byte1]: 57
3401 10:01:24.810473
3402 10:01:24.813242 Set Vref, RX VrefLevel [Byte0]: 58
3403 10:01:24.816550 [Byte1]: 58
3404 10:01:24.820546
3405 10:01:24.820624 Set Vref, RX VrefLevel [Byte0]: 59
3406 10:01:24.824154 [Byte1]: 59
3407 10:01:24.828706
3408 10:01:24.828785 Set Vref, RX VrefLevel [Byte0]: 60
3409 10:01:24.832127 [Byte1]: 60
3410 10:01:24.836867
3411 10:01:24.836945 Set Vref, RX VrefLevel [Byte0]: 61
3412 10:01:24.839644 [Byte1]: 61
3413 10:01:24.844275
3414 10:01:24.844354 Set Vref, RX VrefLevel [Byte0]: 62
3415 10:01:24.847718 [Byte1]: 62
3416 10:01:24.852335
3417 10:01:24.852413 Set Vref, RX VrefLevel [Byte0]: 63
3418 10:01:24.855709 [Byte1]: 63
3419 10:01:24.860565
3420 10:01:24.860643 Set Vref, RX VrefLevel [Byte0]: 64
3421 10:01:24.863518 [Byte1]: 64
3422 10:01:24.868008
3423 10:01:24.868086 Set Vref, RX VrefLevel [Byte0]: 65
3424 10:01:24.871761 [Byte1]: 65
3425 10:01:24.875651
3426 10:01:24.875729 Set Vref, RX VrefLevel [Byte0]: 66
3427 10:01:24.879390 [Byte1]: 66
3428 10:01:24.884151
3429 10:01:24.884229 Set Vref, RX VrefLevel [Byte0]: 67
3430 10:01:24.886953 [Byte1]: 67
3431 10:01:24.891590
3432 10:01:24.891669 Set Vref, RX VrefLevel [Byte0]: 68
3433 10:01:24.895034 [Byte1]: 68
3434 10:01:24.899782
3435 10:01:24.899894 Final RX Vref Byte 0 = 48 to rank0
3436 10:01:24.903026 Final RX Vref Byte 1 = 54 to rank0
3437 10:01:24.906364 Final RX Vref Byte 0 = 48 to rank1
3438 10:01:24.909509 Final RX Vref Byte 1 = 54 to rank1==
3439 10:01:24.912399 Dram Type= 6, Freq= 0, CH_1, rank 0
3440 10:01:24.919255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 10:01:24.919335 ==
3442 10:01:24.919398 DQS Delay:
3443 10:01:24.922581 DQS0 = 0, DQS1 = 0
3444 10:01:24.922668 DQM Delay:
3445 10:01:24.925884 DQM0 = 117, DQM1 = 112
3446 10:01:24.925962 DQ Delay:
3447 10:01:24.929230 DQ0 =122, DQ1 =112, DQ2 =108, DQ3 =114
3448 10:01:24.932454 DQ4 =116, DQ5 =128, DQ6 =126, DQ7 =116
3449 10:01:24.935574 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =100
3450 10:01:24.939405 DQ12 =120, DQ13 =120, DQ14 =122, DQ15 =120
3451 10:01:24.939484
3452 10:01:24.939546
3453 10:01:24.948891 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3454 10:01:24.948971 CH1 RK0: MR19=403, MR18=6F9
3455 10:01:24.955676 CH1_RK0: MR19=0x403, MR18=0x6F9, DQSOSC=407, MR23=63, INC=39, DEC=26
3456 10:01:24.955755
3457 10:01:24.959369 ----->DramcWriteLeveling(PI) begin...
3458 10:01:24.959449 ==
3459 10:01:24.962087 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 10:01:24.968966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 10:01:24.969045 ==
3462 10:01:24.971898 Write leveling (Byte 0): 23 => 23
3463 10:01:24.975369 Write leveling (Byte 1): 28 => 28
3464 10:01:24.975447 DramcWriteLeveling(PI) end<-----
3465 10:01:24.975509
3466 10:01:24.978851 ==
3467 10:01:24.981810 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 10:01:24.985077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 10:01:24.985156 ==
3470 10:01:24.988962 [Gating] SW mode calibration
3471 10:01:24.995244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3472 10:01:24.998578 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3473 10:01:25.005255 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 10:01:25.008064 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 10:01:25.011494 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 10:01:25.018678 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 10:01:25.021643 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 10:01:25.024861 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 10:01:25.031456 0 15 24 | B1->B0 | 2f2f 3333 | 1 0 | (1 1) (0 1)
3480 10:01:25.034516 0 15 28 | B1->B0 | 2626 2828 | 0 0 | (1 0) (1 0)
3481 10:01:25.038007 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 10:01:25.044543 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 10:01:25.047863 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 10:01:25.051545 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 10:01:25.057559 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 10:01:25.061152 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3487 10:01:25.064366 1 0 24 | B1->B0 | 2f2f 2727 | 1 0 | (0 0) (0 0)
3488 10:01:25.070778 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 10:01:25.074549 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 10:01:25.077613 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 10:01:25.084520 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 10:01:25.087753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 10:01:25.090464 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 10:01:25.097717 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 10:01:25.101029 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3496 10:01:25.103823 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3497 10:01:25.110612 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 10:01:25.114247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 10:01:25.117088 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 10:01:25.123877 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 10:01:25.127238 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 10:01:25.130201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 10:01:25.137111 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 10:01:25.140406 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 10:01:25.143949 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 10:01:25.149980 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 10:01:25.153357 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 10:01:25.156899 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 10:01:25.163171 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 10:01:25.166440 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 10:01:25.169820 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3512 10:01:25.176345 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3513 10:01:25.176429 Total UI for P1: 0, mck2ui 16
3514 10:01:25.183149 best dqsien dly found for B1: ( 1, 3, 24)
3515 10:01:25.186304 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 10:01:25.189731 Total UI for P1: 0, mck2ui 16
3517 10:01:25.193117 best dqsien dly found for B0: ( 1, 3, 26)
3518 10:01:25.196288 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3519 10:01:25.199791 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3520 10:01:25.199916
3521 10:01:25.203215 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3522 10:01:25.206217 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3523 10:01:25.209370 [Gating] SW calibration Done
3524 10:01:25.209448 ==
3525 10:01:25.212555 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 10:01:25.219525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 10:01:25.219605 ==
3528 10:01:25.219668 RX Vref Scan: 0
3529 10:01:25.219726
3530 10:01:25.222571 RX Vref 0 -> 0, step: 1
3531 10:01:25.222689
3532 10:01:25.226004 RX Delay -40 -> 252, step: 8
3533 10:01:25.229562 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3534 10:01:25.233002 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3535 10:01:25.236003 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3536 10:01:25.239676 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3537 10:01:25.246047 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3538 10:01:25.249182 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3539 10:01:25.252445 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3540 10:01:25.255908 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3541 10:01:25.258983 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3542 10:01:25.265597 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3543 10:01:25.268894 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3544 10:01:25.272290 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3545 10:01:25.275727 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3546 10:01:25.279204 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3547 10:01:25.285891 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3548 10:01:25.288935 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3549 10:01:25.289014 ==
3550 10:01:25.292783 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 10:01:25.295406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 10:01:25.295486 ==
3553 10:01:25.298989 DQS Delay:
3554 10:01:25.299067 DQS0 = 0, DQS1 = 0
3555 10:01:25.302151 DQM Delay:
3556 10:01:25.302229 DQM0 = 117, DQM1 = 110
3557 10:01:25.302291 DQ Delay:
3558 10:01:25.305916 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3559 10:01:25.311865 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3560 10:01:25.315644 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3561 10:01:25.318670 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3562 10:01:25.318773
3563 10:01:25.318865
3564 10:01:25.318926 ==
3565 10:01:25.322325 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 10:01:25.325352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 10:01:25.325431 ==
3568 10:01:25.325493
3569 10:01:25.325551
3570 10:01:25.328991 TX Vref Scan disable
3571 10:01:25.331595 == TX Byte 0 ==
3572 10:01:25.335252 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3573 10:01:25.338433 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3574 10:01:25.341893 == TX Byte 1 ==
3575 10:01:25.345089 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3576 10:01:25.347930 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3577 10:01:25.348009 ==
3578 10:01:25.351485 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 10:01:25.354764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 10:01:25.358192 ==
3581 10:01:25.368482 TX Vref=22, minBit 0, minWin=26, winSum=422
3582 10:01:25.372096 TX Vref=24, minBit 0, minWin=25, winSum=424
3583 10:01:25.374952 TX Vref=26, minBit 3, minWin=26, winSum=431
3584 10:01:25.378470 TX Vref=28, minBit 3, minWin=26, winSum=429
3585 10:01:25.381882 TX Vref=30, minBit 7, minWin=26, winSum=431
3586 10:01:25.388497 TX Vref=32, minBit 1, minWin=25, winSum=429
3587 10:01:25.392133 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 26
3588 10:01:25.392212
3589 10:01:25.394885 Final TX Range 1 Vref 26
3590 10:01:25.394964
3591 10:01:25.395025 ==
3592 10:01:25.398233 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 10:01:25.401473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 10:01:25.405038 ==
3595 10:01:25.405116
3596 10:01:25.405178
3597 10:01:25.405235 TX Vref Scan disable
3598 10:01:25.408044 == TX Byte 0 ==
3599 10:01:25.411504 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3600 10:01:25.418392 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3601 10:01:25.418471 == TX Byte 1 ==
3602 10:01:25.421576 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3603 10:01:25.428434 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3604 10:01:25.428513
3605 10:01:25.428575 [DATLAT]
3606 10:01:25.428633 Freq=1200, CH1 RK1
3607 10:01:25.428690
3608 10:01:25.431360 DATLAT Default: 0xd
3609 10:01:25.431439 0, 0xFFFF, sum = 0
3610 10:01:25.434871 1, 0xFFFF, sum = 0
3611 10:01:25.438048 2, 0xFFFF, sum = 0
3612 10:01:25.438128 3, 0xFFFF, sum = 0
3613 10:01:25.441774 4, 0xFFFF, sum = 0
3614 10:01:25.441853 5, 0xFFFF, sum = 0
3615 10:01:25.444664 6, 0xFFFF, sum = 0
3616 10:01:25.444744 7, 0xFFFF, sum = 0
3617 10:01:25.448052 8, 0xFFFF, sum = 0
3618 10:01:25.448132 9, 0xFFFF, sum = 0
3619 10:01:25.451189 10, 0xFFFF, sum = 0
3620 10:01:25.451268 11, 0xFFFF, sum = 0
3621 10:01:25.454431 12, 0x0, sum = 1
3622 10:01:25.454511 13, 0x0, sum = 2
3623 10:01:25.458059 14, 0x0, sum = 3
3624 10:01:25.458139 15, 0x0, sum = 4
3625 10:01:25.461221 best_step = 13
3626 10:01:25.461299
3627 10:01:25.461361 ==
3628 10:01:25.464624 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 10:01:25.467933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 10:01:25.468012 ==
3631 10:01:25.468075 RX Vref Scan: 0
3632 10:01:25.471242
3633 10:01:25.471320 RX Vref 0 -> 0, step: 1
3634 10:01:25.471382
3635 10:01:25.474374 RX Delay -21 -> 252, step: 4
3636 10:01:25.481270 iDelay=199, Bit 0, Center 122 (55 ~ 190) 136
3637 10:01:25.484714 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3638 10:01:25.487925 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3639 10:01:25.491200 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3640 10:01:25.494570 iDelay=199, Bit 4, Center 118 (51 ~ 186) 136
3641 10:01:25.501088 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3642 10:01:25.504277 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3643 10:01:25.507312 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3644 10:01:25.510919 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3645 10:01:25.513840 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3646 10:01:25.520748 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3647 10:01:25.523842 iDelay=199, Bit 11, Center 102 (39 ~ 166) 128
3648 10:01:25.526980 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3649 10:01:25.530465 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3650 10:01:25.533695 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3651 10:01:25.540438 iDelay=199, Bit 15, Center 120 (55 ~ 186) 132
3652 10:01:25.540519 ==
3653 10:01:25.543186 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 10:01:25.546615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 10:01:25.546736 ==
3656 10:01:25.550089 DQS Delay:
3657 10:01:25.550169 DQS0 = 0, DQS1 = 0
3658 10:01:25.550233 DQM Delay:
3659 10:01:25.553557 DQM0 = 118, DQM1 = 111
3660 10:01:25.553668 DQ Delay:
3661 10:01:25.556820 DQ0 =122, DQ1 =112, DQ2 =108, DQ3 =114
3662 10:01:25.560068 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3663 10:01:25.563527 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3664 10:01:25.569996 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3665 10:01:25.570077
3666 10:01:25.570140
3667 10:01:25.576531 [DQSOSCAuto] RK1, (LSB)MR18= 0xf9f3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 412 ps
3668 10:01:25.580250 CH1 RK1: MR19=303, MR18=F9F3
3669 10:01:25.586618 CH1_RK1: MR19=0x303, MR18=0xF9F3, DQSOSC=412, MR23=63, INC=38, DEC=25
3670 10:01:25.590024 [RxdqsGatingPostProcess] freq 1200
3671 10:01:25.593535 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3672 10:01:25.596235 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 10:01:25.599691 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 10:01:25.603135 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 10:01:25.606555 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 10:01:25.609456 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 10:01:25.612804 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 10:01:25.616517 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 10:01:25.619587 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 10:01:25.622549 Pre-setting of DQS Precalculation
3681 10:01:25.626084 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3682 10:01:25.635928 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3683 10:01:25.642581 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3684 10:01:25.642701
3685 10:01:25.642763
3686 10:01:25.646299 [Calibration Summary] 2400 Mbps
3687 10:01:25.646378 CH 0, Rank 0
3688 10:01:25.649740 SW Impedance : PASS
3689 10:01:25.649818 DUTY Scan : NO K
3690 10:01:25.652416 ZQ Calibration : PASS
3691 10:01:25.656062 Jitter Meter : NO K
3692 10:01:25.656140 CBT Training : PASS
3693 10:01:25.658856 Write leveling : PASS
3694 10:01:25.662944 RX DQS gating : PASS
3695 10:01:25.663021 RX DQ/DQS(RDDQC) : PASS
3696 10:01:25.665850 TX DQ/DQS : PASS
3697 10:01:25.669447 RX DATLAT : PASS
3698 10:01:25.669525 RX DQ/DQS(Engine): PASS
3699 10:01:25.672237 TX OE : NO K
3700 10:01:25.672316 All Pass.
3701 10:01:25.672378
3702 10:01:25.675590 CH 0, Rank 1
3703 10:01:25.675669 SW Impedance : PASS
3704 10:01:25.679188 DUTY Scan : NO K
3705 10:01:25.682308 ZQ Calibration : PASS
3706 10:01:25.682386 Jitter Meter : NO K
3707 10:01:25.685997 CBT Training : PASS
3708 10:01:25.689176 Write leveling : PASS
3709 10:01:25.689255 RX DQS gating : PASS
3710 10:01:25.692308 RX DQ/DQS(RDDQC) : PASS
3711 10:01:25.695569 TX DQ/DQS : PASS
3712 10:01:25.695649 RX DATLAT : PASS
3713 10:01:25.699207 RX DQ/DQS(Engine): PASS
3714 10:01:25.699285 TX OE : NO K
3715 10:01:25.701891 All Pass.
3716 10:01:25.701969
3717 10:01:25.702031 CH 1, Rank 0
3718 10:01:25.705181 SW Impedance : PASS
3719 10:01:25.708701 DUTY Scan : NO K
3720 10:01:25.708785 ZQ Calibration : PASS
3721 10:01:25.711948 Jitter Meter : NO K
3722 10:01:25.712026 CBT Training : PASS
3723 10:01:25.715562 Write leveling : PASS
3724 10:01:25.718649 RX DQS gating : PASS
3725 10:01:25.718728 RX DQ/DQS(RDDQC) : PASS
3726 10:01:25.722160 TX DQ/DQS : PASS
3727 10:01:25.725787 RX DATLAT : PASS
3728 10:01:25.725865 RX DQ/DQS(Engine): PASS
3729 10:01:25.728385 TX OE : NO K
3730 10:01:25.728463 All Pass.
3731 10:01:25.728525
3732 10:01:25.731544 CH 1, Rank 1
3733 10:01:25.731622 SW Impedance : PASS
3734 10:01:25.734852 DUTY Scan : NO K
3735 10:01:25.738387 ZQ Calibration : PASS
3736 10:01:25.738492 Jitter Meter : NO K
3737 10:01:25.741532 CBT Training : PASS
3738 10:01:25.745226 Write leveling : PASS
3739 10:01:25.745304 RX DQS gating : PASS
3740 10:01:25.748011 RX DQ/DQS(RDDQC) : PASS
3741 10:01:25.751482 TX DQ/DQS : PASS
3742 10:01:25.751562 RX DATLAT : PASS
3743 10:01:25.755187 RX DQ/DQS(Engine): PASS
3744 10:01:25.758451 TX OE : NO K
3745 10:01:25.758530 All Pass.
3746 10:01:25.758597
3747 10:01:25.758656 DramC Write-DBI off
3748 10:01:25.761277 PER_BANK_REFRESH: Hybrid Mode
3749 10:01:25.764591 TX_TRACKING: ON
3750 10:01:25.771370 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3751 10:01:25.778105 [FAST_K] Save calibration result to emmc
3752 10:01:25.781492 dramc_set_vcore_voltage set vcore to 650000
3753 10:01:25.781570 Read voltage for 600, 5
3754 10:01:25.784704 Vio18 = 0
3755 10:01:25.784781 Vcore = 650000
3756 10:01:25.784843 Vdram = 0
3757 10:01:25.787895 Vddq = 0
3758 10:01:25.787973 Vmddr = 0
3759 10:01:25.791435 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3760 10:01:25.797827 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3761 10:01:25.800900 MEM_TYPE=3, freq_sel=19
3762 10:01:25.804219 sv_algorithm_assistance_LP4_1600
3763 10:01:25.807744 ============ PULL DRAM RESETB DOWN ============
3764 10:01:25.810983 ========== PULL DRAM RESETB DOWN end =========
3765 10:01:25.817399 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3766 10:01:25.821127 ===================================
3767 10:01:25.821207 LPDDR4 DRAM CONFIGURATION
3768 10:01:25.823995 ===================================
3769 10:01:25.827520 EX_ROW_EN[0] = 0x0
3770 10:01:25.827598 EX_ROW_EN[1] = 0x0
3771 10:01:25.830639 LP4Y_EN = 0x0
3772 10:01:25.830719 WORK_FSP = 0x0
3773 10:01:25.833986 WL = 0x2
3774 10:01:25.834064 RL = 0x2
3775 10:01:25.837253 BL = 0x2
3776 10:01:25.840705 RPST = 0x0
3777 10:01:25.840783 RD_PRE = 0x0
3778 10:01:25.844242 WR_PRE = 0x1
3779 10:01:25.844321 WR_PST = 0x0
3780 10:01:25.847238 DBI_WR = 0x0
3781 10:01:25.847316 DBI_RD = 0x0
3782 10:01:25.850386 OTF = 0x1
3783 10:01:25.854366 ===================================
3784 10:01:25.857045 ===================================
3785 10:01:25.857124 ANA top config
3786 10:01:25.860366 ===================================
3787 10:01:25.864016 DLL_ASYNC_EN = 0
3788 10:01:25.866938 ALL_SLAVE_EN = 1
3789 10:01:25.867017 NEW_RANK_MODE = 1
3790 10:01:25.870424 DLL_IDLE_MODE = 1
3791 10:01:25.873626 LP45_APHY_COMB_EN = 1
3792 10:01:25.876856 TX_ODT_DIS = 1
3793 10:01:25.880108 NEW_8X_MODE = 1
3794 10:01:25.883618 ===================================
3795 10:01:25.887168 ===================================
3796 10:01:25.887248 data_rate = 1200
3797 10:01:25.890146 CKR = 1
3798 10:01:25.893449 DQ_P2S_RATIO = 8
3799 10:01:25.896539 ===================================
3800 10:01:25.900106 CA_P2S_RATIO = 8
3801 10:01:25.903606 DQ_CA_OPEN = 0
3802 10:01:25.906841 DQ_SEMI_OPEN = 0
3803 10:01:25.910043 CA_SEMI_OPEN = 0
3804 10:01:25.910125 CA_FULL_RATE = 0
3805 10:01:25.913299 DQ_CKDIV4_EN = 1
3806 10:01:25.916485 CA_CKDIV4_EN = 1
3807 10:01:25.920013 CA_PREDIV_EN = 0
3808 10:01:25.923010 PH8_DLY = 0
3809 10:01:25.926400 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3810 10:01:25.926504 DQ_AAMCK_DIV = 4
3811 10:01:25.929739 CA_AAMCK_DIV = 4
3812 10:01:25.933029 CA_ADMCK_DIV = 4
3813 10:01:25.936429 DQ_TRACK_CA_EN = 0
3814 10:01:25.939642 CA_PICK = 600
3815 10:01:25.942764 CA_MCKIO = 600
3816 10:01:25.942843 MCKIO_SEMI = 0
3817 10:01:25.945988 PLL_FREQ = 2288
3818 10:01:25.949352 DQ_UI_PI_RATIO = 32
3819 10:01:25.952571 CA_UI_PI_RATIO = 0
3820 10:01:25.956281 ===================================
3821 10:01:25.959239 ===================================
3822 10:01:25.962967 memory_type:LPDDR4
3823 10:01:25.963070 GP_NUM : 10
3824 10:01:25.966120 SRAM_EN : 1
3825 10:01:25.969192 MD32_EN : 0
3826 10:01:25.972524 ===================================
3827 10:01:25.972604 [ANA_INIT] >>>>>>>>>>>>>>
3828 10:01:25.976268 <<<<<< [CONFIGURE PHASE]: ANA_TX
3829 10:01:25.979323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3830 10:01:25.982750 ===================================
3831 10:01:25.985683 data_rate = 1200,PCW = 0X5800
3832 10:01:25.988877 ===================================
3833 10:01:25.992364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3834 10:01:25.998941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 10:01:26.005873 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 10:01:26.008902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3837 10:01:26.012215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3838 10:01:26.015203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3839 10:01:26.018993 [ANA_INIT] flow start
3840 10:01:26.019071 [ANA_INIT] PLL >>>>>>>>
3841 10:01:26.021902 [ANA_INIT] PLL <<<<<<<<
3842 10:01:26.025594 [ANA_INIT] MIDPI >>>>>>>>
3843 10:01:26.025672 [ANA_INIT] MIDPI <<<<<<<<
3844 10:01:26.028964 [ANA_INIT] DLL >>>>>>>>
3845 10:01:26.031634 [ANA_INIT] flow end
3846 10:01:26.035054 ============ LP4 DIFF to SE enter ============
3847 10:01:26.038183 ============ LP4 DIFF to SE exit ============
3848 10:01:26.042033 [ANA_INIT] <<<<<<<<<<<<<
3849 10:01:26.044872 [Flow] Enable top DCM control >>>>>
3850 10:01:26.048515 [Flow] Enable top DCM control <<<<<
3851 10:01:26.051349 Enable DLL master slave shuffle
3852 10:01:26.055126 ==============================================================
3853 10:01:26.058421 Gating Mode config
3854 10:01:26.064694 ==============================================================
3855 10:01:26.064775 Config description:
3856 10:01:26.074796 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3857 10:01:26.081227 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3858 10:01:26.087631 SELPH_MODE 0: By rank 1: By Phase
3859 10:01:26.090913 ==============================================================
3860 10:01:26.094103 GAT_TRACK_EN = 1
3861 10:01:26.097795 RX_GATING_MODE = 2
3862 10:01:26.101151 RX_GATING_TRACK_MODE = 2
3863 10:01:26.104104 SELPH_MODE = 1
3864 10:01:26.107816 PICG_EARLY_EN = 1
3865 10:01:26.110517 VALID_LAT_VALUE = 1
3866 10:01:26.117632 ==============================================================
3867 10:01:26.120979 Enter into Gating configuration >>>>
3868 10:01:26.124362 Exit from Gating configuration <<<<
3869 10:01:26.124442 Enter into DVFS_PRE_config >>>>>
3870 10:01:26.137193 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3871 10:01:26.140808 Exit from DVFS_PRE_config <<<<<
3872 10:01:26.144210 Enter into PICG configuration >>>>
3873 10:01:26.147335 Exit from PICG configuration <<<<
3874 10:01:26.150499 [RX_INPUT] configuration >>>>>
3875 10:01:26.150579 [RX_INPUT] configuration <<<<<
3876 10:01:26.157334 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3877 10:01:26.163461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3878 10:01:26.166835 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3879 10:01:26.173757 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3880 10:01:26.180124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3881 10:01:26.186980 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3882 10:01:26.190162 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3883 10:01:26.193578 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3884 10:01:26.199772 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3885 10:01:26.203449 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3886 10:01:26.206869 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3887 10:01:26.213200 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 10:01:26.216951 ===================================
3889 10:01:26.217031 LPDDR4 DRAM CONFIGURATION
3890 10:01:26.220033 ===================================
3891 10:01:26.222917 EX_ROW_EN[0] = 0x0
3892 10:01:26.226495 EX_ROW_EN[1] = 0x0
3893 10:01:26.226574 LP4Y_EN = 0x0
3894 10:01:26.229395 WORK_FSP = 0x0
3895 10:01:26.229475 WL = 0x2
3896 10:01:26.232748 RL = 0x2
3897 10:01:26.232829 BL = 0x2
3898 10:01:26.236051 RPST = 0x0
3899 10:01:26.236131 RD_PRE = 0x0
3900 10:01:26.239776 WR_PRE = 0x1
3901 10:01:26.239859 WR_PST = 0x0
3902 10:01:26.242585 DBI_WR = 0x0
3903 10:01:26.242703 DBI_RD = 0x0
3904 10:01:26.246138 OTF = 0x1
3905 10:01:26.249457 ===================================
3906 10:01:26.252826 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3907 10:01:26.256101 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3908 10:01:26.263041 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 10:01:26.266005 ===================================
3910 10:01:26.266085 LPDDR4 DRAM CONFIGURATION
3911 10:01:26.269209 ===================================
3912 10:01:26.272356 EX_ROW_EN[0] = 0x10
3913 10:01:26.275609 EX_ROW_EN[1] = 0x0
3914 10:01:26.275688 LP4Y_EN = 0x0
3915 10:01:26.279224 WORK_FSP = 0x0
3916 10:01:26.279304 WL = 0x2
3917 10:01:26.282242 RL = 0x2
3918 10:01:26.282322 BL = 0x2
3919 10:01:26.285586 RPST = 0x0
3920 10:01:26.285666 RD_PRE = 0x0
3921 10:01:26.288669 WR_PRE = 0x1
3922 10:01:26.288749 WR_PST = 0x0
3923 10:01:26.292337 DBI_WR = 0x0
3924 10:01:26.292416 DBI_RD = 0x0
3925 10:01:26.295247 OTF = 0x1
3926 10:01:26.299044 ===================================
3927 10:01:26.305363 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3928 10:01:26.308847 nWR fixed to 30
3929 10:01:26.308928 [ModeRegInit_LP4] CH0 RK0
3930 10:01:26.311966 [ModeRegInit_LP4] CH0 RK1
3931 10:01:26.315313 [ModeRegInit_LP4] CH1 RK0
3932 10:01:26.318508 [ModeRegInit_LP4] CH1 RK1
3933 10:01:26.318587 match AC timing 17
3934 10:01:26.325459 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3935 10:01:26.328764 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3936 10:01:26.331819 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3937 10:01:26.338646 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3938 10:01:26.341665 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3939 10:01:26.341745 ==
3940 10:01:26.345287 Dram Type= 6, Freq= 0, CH_0, rank 0
3941 10:01:26.348373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 10:01:26.348477 ==
3943 10:01:26.354893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 10:01:26.361420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3945 10:01:26.364847 [CA 0] Center 36 (6~66) winsize 61
3946 10:01:26.367873 [CA 1] Center 36 (6~66) winsize 61
3947 10:01:26.371318 [CA 2] Center 34 (4~65) winsize 62
3948 10:01:26.374559 [CA 3] Center 34 (3~65) winsize 63
3949 10:01:26.377752 [CA 4] Center 33 (3~64) winsize 62
3950 10:01:26.381142 [CA 5] Center 33 (2~64) winsize 63
3951 10:01:26.381220
3952 10:01:26.384837 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3953 10:01:26.384915
3954 10:01:26.387807 [CATrainingPosCal] consider 1 rank data
3955 10:01:26.391445 u2DelayCellTimex100 = 270/100 ps
3956 10:01:26.394735 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 10:01:26.398254 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3958 10:01:26.400926 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 10:01:26.404184 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3960 10:01:26.407855 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 10:01:26.414968 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3962 10:01:26.415047
3963 10:01:26.417648 CA PerBit enable=1, Macro0, CA PI delay=33
3964 10:01:26.417727
3965 10:01:26.420851 [CBTSetCACLKResult] CA Dly = 33
3966 10:01:26.420930 CS Dly: 4 (0~35)
3967 10:01:26.420992 ==
3968 10:01:26.424646 Dram Type= 6, Freq= 0, CH_0, rank 1
3969 10:01:26.427757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 10:01:26.430724 ==
3971 10:01:26.434193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 10:01:26.440546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3973 10:01:26.444040 [CA 0] Center 36 (6~66) winsize 61
3974 10:01:26.447678 [CA 1] Center 36 (6~66) winsize 61
3975 10:01:26.450503 [CA 2] Center 33 (3~64) winsize 62
3976 10:01:26.453879 [CA 3] Center 33 (3~64) winsize 62
3977 10:01:26.457015 [CA 4] Center 33 (2~64) winsize 63
3978 10:01:26.460360 [CA 5] Center 33 (2~64) winsize 63
3979 10:01:26.460440
3980 10:01:26.463572 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3981 10:01:26.463651
3982 10:01:26.466893 [CATrainingPosCal] consider 2 rank data
3983 10:01:26.470256 u2DelayCellTimex100 = 270/100 ps
3984 10:01:26.473502 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 10:01:26.476843 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3986 10:01:26.483442 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3987 10:01:26.486645 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 10:01:26.490385 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 10:01:26.493843 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3990 10:01:26.493951
3991 10:01:26.496594 CA PerBit enable=1, Macro0, CA PI delay=33
3992 10:01:26.496673
3993 10:01:26.500042 [CBTSetCACLKResult] CA Dly = 33
3994 10:01:26.500121 CS Dly: 5 (0~38)
3995 10:01:26.500184
3996 10:01:26.506415 ----->DramcWriteLeveling(PI) begin...
3997 10:01:26.506498 ==
3998 10:01:26.509768 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 10:01:26.513100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 10:01:26.513181 ==
4001 10:01:26.516614 Write leveling (Byte 0): 36 => 36
4002 10:01:26.519479 Write leveling (Byte 1): 29 => 29
4003 10:01:26.522859 DramcWriteLeveling(PI) end<-----
4004 10:01:26.522939
4005 10:01:26.523002 ==
4006 10:01:26.526655 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 10:01:26.529859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 10:01:26.529985 ==
4009 10:01:26.533456 [Gating] SW mode calibration
4010 10:01:26.539626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4011 10:01:26.546757 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4012 10:01:26.550582 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 10:01:26.552951 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 10:01:26.560080 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 10:01:26.563158 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4016 10:01:26.566385 0 9 16 | B1->B0 | 3030 2828 | 0 0 | (0 1) (1 1)
4017 10:01:26.572935 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 10:01:26.576257 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 10:01:26.579353 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 10:01:26.586052 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 10:01:26.589505 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 10:01:26.592700 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 10:01:26.599263 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4024 10:01:26.602541 0 10 16 | B1->B0 | 3737 4242 | 0 0 | (0 0) (0 0)
4025 10:01:26.605814 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 10:01:26.612540 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 10:01:26.615512 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 10:01:26.618914 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 10:01:26.625671 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 10:01:26.628621 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 10:01:26.631897 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4032 10:01:26.638781 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4033 10:01:26.641766 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 10:01:26.645310 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 10:01:26.651701 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 10:01:26.655038 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 10:01:26.658427 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 10:01:26.665348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 10:01:26.668568 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 10:01:26.671674 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 10:01:26.678513 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 10:01:26.681681 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 10:01:26.684818 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 10:01:26.691243 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 10:01:26.694859 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 10:01:26.698357 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 10:01:26.704841 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 10:01:26.708124 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 10:01:26.711410 Total UI for P1: 0, mck2ui 16
4050 10:01:26.714435 best dqsien dly found for B0: ( 0, 13, 14)
4051 10:01:26.718125 Total UI for P1: 0, mck2ui 16
4052 10:01:26.721581 best dqsien dly found for B1: ( 0, 13, 14)
4053 10:01:26.724266 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4054 10:01:26.727602 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4055 10:01:26.727683
4056 10:01:26.731033 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4057 10:01:26.734177 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4058 10:01:26.737612 [Gating] SW calibration Done
4059 10:01:26.737714 ==
4060 10:01:26.740737 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 10:01:26.744006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 10:01:26.747512 ==
4063 10:01:26.747613 RX Vref Scan: 0
4064 10:01:26.747706
4065 10:01:26.750946 RX Vref 0 -> 0, step: 1
4066 10:01:26.751034
4067 10:01:26.753857 RX Delay -230 -> 252, step: 16
4068 10:01:26.757109 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4069 10:01:26.760796 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4070 10:01:26.763729 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4071 10:01:26.770732 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4072 10:01:26.774060 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4073 10:01:26.777279 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4074 10:01:26.780200 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4075 10:01:26.787216 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4076 10:01:26.789984 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4077 10:01:26.793430 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4078 10:01:26.796797 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4079 10:01:26.799881 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4080 10:01:26.806536 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4081 10:01:26.810103 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4082 10:01:26.813631 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4083 10:01:26.816654 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4084 10:01:26.819898 ==
4085 10:01:26.823352 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 10:01:26.826575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 10:01:26.826695 ==
4088 10:01:26.826760 DQS Delay:
4089 10:01:26.829941 DQS0 = 0, DQS1 = 0
4090 10:01:26.830020 DQM Delay:
4091 10:01:26.833393 DQM0 = 41, DQM1 = 29
4092 10:01:26.833473 DQ Delay:
4093 10:01:26.836622 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4094 10:01:26.839962 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4095 10:01:26.843136 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4096 10:01:26.846994 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4097 10:01:26.847075
4098 10:01:26.847138
4099 10:01:26.847197 ==
4100 10:01:26.849887 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 10:01:26.852945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 10:01:26.853026 ==
4103 10:01:26.853089
4104 10:01:26.853148
4105 10:01:26.856221 TX Vref Scan disable
4106 10:01:26.859605 == TX Byte 0 ==
4107 10:01:26.862732 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4108 10:01:26.866093 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4109 10:01:26.869363 == TX Byte 1 ==
4110 10:01:26.872850 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4111 10:01:26.875946 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4112 10:01:26.876027 ==
4113 10:01:26.879473 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 10:01:26.886290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 10:01:26.886371 ==
4116 10:01:26.886434
4117 10:01:26.886493
4118 10:01:26.889322 TX Vref Scan disable
4119 10:01:26.889402 == TX Byte 0 ==
4120 10:01:26.895959 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4121 10:01:26.898873 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4122 10:01:26.898954 == TX Byte 1 ==
4123 10:01:26.905966 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4124 10:01:26.909118 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4125 10:01:26.909203
4126 10:01:26.909273 [DATLAT]
4127 10:01:26.912431 Freq=600, CH0 RK0
4128 10:01:26.912512
4129 10:01:26.912575 DATLAT Default: 0x9
4130 10:01:26.915637 0, 0xFFFF, sum = 0
4131 10:01:26.915718 1, 0xFFFF, sum = 0
4132 10:01:26.918989 2, 0xFFFF, sum = 0
4133 10:01:26.922189 3, 0xFFFF, sum = 0
4134 10:01:26.922270 4, 0xFFFF, sum = 0
4135 10:01:26.925960 5, 0xFFFF, sum = 0
4136 10:01:26.926042 6, 0xFFFF, sum = 0
4137 10:01:26.929161 7, 0xFFFF, sum = 0
4138 10:01:26.929242 8, 0x0, sum = 1
4139 10:01:26.929307 9, 0x0, sum = 2
4140 10:01:26.932165 10, 0x0, sum = 3
4141 10:01:26.932278 11, 0x0, sum = 4
4142 10:01:26.935525 best_step = 9
4143 10:01:26.935605
4144 10:01:26.935668 ==
4145 10:01:26.938976 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 10:01:26.942250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 10:01:26.942356 ==
4148 10:01:26.945091 RX Vref Scan: 1
4149 10:01:26.945171
4150 10:01:26.945233 RX Vref 0 -> 0, step: 1
4151 10:01:26.948863
4152 10:01:26.948942 RX Delay -195 -> 252, step: 8
4153 10:01:26.949006
4154 10:01:26.952211 Set Vref, RX VrefLevel [Byte0]: 61
4155 10:01:26.954870 [Byte1]: 47
4156 10:01:26.959482
4157 10:01:26.959562 Final RX Vref Byte 0 = 61 to rank0
4158 10:01:26.962987 Final RX Vref Byte 1 = 47 to rank0
4159 10:01:26.966235 Final RX Vref Byte 0 = 61 to rank1
4160 10:01:26.969920 Final RX Vref Byte 1 = 47 to rank1==
4161 10:01:26.973369 Dram Type= 6, Freq= 0, CH_0, rank 0
4162 10:01:26.979747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 10:01:26.979827 ==
4164 10:01:26.979891 DQS Delay:
4165 10:01:26.979950 DQS0 = 0, DQS1 = 0
4166 10:01:26.983222 DQM Delay:
4167 10:01:26.983302 DQM0 = 43, DQM1 = 33
4168 10:01:26.986089 DQ Delay:
4169 10:01:26.989219 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4170 10:01:26.993270 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4171 10:01:26.996011 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4172 10:01:26.999506 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4173 10:01:26.999586
4174 10:01:26.999649
4175 10:01:27.006041 [DQSOSCAuto] RK0, (LSB)MR18= 0x683f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4176 10:01:27.009343 CH0 RK0: MR19=808, MR18=683F
4177 10:01:27.016072 CH0_RK0: MR19=0x808, MR18=0x683F, DQSOSC=390, MR23=63, INC=172, DEC=114
4178 10:01:27.016153
4179 10:01:27.018900 ----->DramcWriteLeveling(PI) begin...
4180 10:01:27.018982 ==
4181 10:01:27.022241 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 10:01:27.025562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 10:01:27.025642 ==
4184 10:01:27.028820 Write leveling (Byte 0): 32 => 32
4185 10:01:27.032183 Write leveling (Byte 1): 30 => 30
4186 10:01:27.036178 DramcWriteLeveling(PI) end<-----
4187 10:01:27.036259
4188 10:01:27.036323 ==
4189 10:01:27.038735 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 10:01:27.042161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 10:01:27.045613 ==
4192 10:01:27.045693 [Gating] SW mode calibration
4193 10:01:27.055355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4194 10:01:27.058536 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4195 10:01:27.061609 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4196 10:01:27.068558 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 10:01:27.071771 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 10:01:27.074772 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
4199 10:01:27.081767 0 9 16 | B1->B0 | 3030 2a2a | 1 1 | (1 0) (1 0)
4200 10:01:27.084959 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 10:01:27.087988 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 10:01:27.094953 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 10:01:27.098294 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 10:01:27.101484 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 10:01:27.107990 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 10:01:27.111226 0 10 12 | B1->B0 | 2424 2b2b | 1 0 | (0 0) (0 0)
4207 10:01:27.114457 0 10 16 | B1->B0 | 3939 4040 | 0 0 | (0 0) (0 0)
4208 10:01:27.121328 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 10:01:27.124723 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 10:01:27.128094 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 10:01:27.134635 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 10:01:27.137706 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 10:01:27.140942 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 10:01:27.147860 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 10:01:27.150914 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4216 10:01:27.154707 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 10:01:27.160752 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 10:01:27.163977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 10:01:27.167592 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 10:01:27.173804 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 10:01:27.177343 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 10:01:27.180722 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 10:01:27.187261 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 10:01:27.190767 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 10:01:27.193620 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 10:01:27.200538 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 10:01:27.204253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 10:01:27.207092 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 10:01:27.213844 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 10:01:27.217181 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 10:01:27.220224 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4232 10:01:27.223595 Total UI for P1: 0, mck2ui 16
4233 10:01:27.226759 best dqsien dly found for B0: ( 0, 13, 14)
4234 10:01:27.233772 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 10:01:27.233854 Total UI for P1: 0, mck2ui 16
4236 10:01:27.240165 best dqsien dly found for B1: ( 0, 13, 16)
4237 10:01:27.243673 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4238 10:01:27.246747 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4239 10:01:27.246833
4240 10:01:27.250106 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4241 10:01:27.253412 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4242 10:01:27.257085 [Gating] SW calibration Done
4243 10:01:27.257165 ==
4244 10:01:27.259762 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 10:01:27.263124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 10:01:27.263230 ==
4247 10:01:27.266227 RX Vref Scan: 0
4248 10:01:27.266307
4249 10:01:27.266370 RX Vref 0 -> 0, step: 1
4250 10:01:27.269946
4251 10:01:27.270026 RX Delay -230 -> 252, step: 16
4252 10:01:27.276642 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4253 10:01:27.280187 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4254 10:01:27.282878 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4255 10:01:27.286374 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4256 10:01:27.293031 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4257 10:01:27.296228 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4258 10:01:27.299275 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4259 10:01:27.302601 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4260 10:01:27.306230 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4261 10:01:27.312653 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4262 10:01:27.316011 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4263 10:01:27.319416 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4264 10:01:27.322893 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4265 10:01:27.329139 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4266 10:01:27.332569 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4267 10:01:27.335650 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4268 10:01:27.335731 ==
4269 10:01:27.339153 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 10:01:27.345768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 10:01:27.345850 ==
4272 10:01:27.345914 DQS Delay:
4273 10:01:27.345973 DQS0 = 0, DQS1 = 0
4274 10:01:27.349056 DQM Delay:
4275 10:01:27.349137 DQM0 = 42, DQM1 = 35
4276 10:01:27.352726 DQ Delay:
4277 10:01:27.355873 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4278 10:01:27.358890 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4279 10:01:27.358970 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4280 10:01:27.365376 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4281 10:01:27.365456
4282 10:01:27.365520
4283 10:01:27.365578 ==
4284 10:01:27.368997 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 10:01:27.371944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 10:01:27.372026 ==
4287 10:01:27.372090
4288 10:01:27.372148
4289 10:01:27.375261 TX Vref Scan disable
4290 10:01:27.375345 == TX Byte 0 ==
4291 10:01:27.382236 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4292 10:01:27.385652 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4293 10:01:27.385732 == TX Byte 1 ==
4294 10:01:27.392240 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4295 10:01:27.395531 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4296 10:01:27.395611 ==
4297 10:01:27.399050 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 10:01:27.402037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 10:01:27.402122 ==
4300 10:01:27.402186
4301 10:01:27.405483
4302 10:01:27.405562 TX Vref Scan disable
4303 10:01:27.408676 == TX Byte 0 ==
4304 10:01:27.412176 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4305 10:01:27.418747 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4306 10:01:27.418827 == TX Byte 1 ==
4307 10:01:27.421892 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4308 10:01:27.428427 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4309 10:01:27.428507
4310 10:01:27.428570 [DATLAT]
4311 10:01:27.428628 Freq=600, CH0 RK1
4312 10:01:27.428686
4313 10:01:27.431752 DATLAT Default: 0x9
4314 10:01:27.431831 0, 0xFFFF, sum = 0
4315 10:01:27.435201 1, 0xFFFF, sum = 0
4316 10:01:27.438229 2, 0xFFFF, sum = 0
4317 10:01:27.438309 3, 0xFFFF, sum = 0
4318 10:01:27.441879 4, 0xFFFF, sum = 0
4319 10:01:27.441961 5, 0xFFFF, sum = 0
4320 10:01:27.445211 6, 0xFFFF, sum = 0
4321 10:01:27.445292 7, 0xFFFF, sum = 0
4322 10:01:27.448249 8, 0x0, sum = 1
4323 10:01:27.448329 9, 0x0, sum = 2
4324 10:01:27.448392 10, 0x0, sum = 3
4325 10:01:27.451715 11, 0x0, sum = 4
4326 10:01:27.451796 best_step = 9
4327 10:01:27.451859
4328 10:01:27.455180 ==
4329 10:01:27.455260 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 10:01:27.461651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 10:01:27.461731 ==
4332 10:01:27.461794 RX Vref Scan: 0
4333 10:01:27.461853
4334 10:01:27.464892 RX Vref 0 -> 0, step: 1
4335 10:01:27.464976
4336 10:01:27.468340 RX Delay -179 -> 252, step: 8
4337 10:01:27.475096 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4338 10:01:27.477851 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4339 10:01:27.481134 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4340 10:01:27.484396 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4341 10:01:27.488264 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4342 10:01:27.494408 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4343 10:01:27.497784 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4344 10:01:27.500933 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4345 10:01:27.504481 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4346 10:01:27.511311 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4347 10:01:27.514373 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4348 10:01:27.517802 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4349 10:01:27.520766 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4350 10:01:27.527575 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4351 10:01:27.530559 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4352 10:01:27.534175 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4353 10:01:27.534255 ==
4354 10:01:27.537269 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 10:01:27.540887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 10:01:27.540967 ==
4357 10:01:27.543840 DQS Delay:
4358 10:01:27.543919 DQS0 = 0, DQS1 = 0
4359 10:01:27.547315 DQM Delay:
4360 10:01:27.547394 DQM0 = 41, DQM1 = 37
4361 10:01:27.547457 DQ Delay:
4362 10:01:27.550622 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =40
4363 10:01:27.553576 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4364 10:01:27.557081 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4365 10:01:27.560442 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4366 10:01:27.560522
4367 10:01:27.563832
4368 10:01:27.570483 [DQSOSCAuto] RK1, (LSB)MR18= 0x6112, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4369 10:01:27.573902 CH0 RK1: MR19=808, MR18=6112
4370 10:01:27.580111 CH0_RK1: MR19=0x808, MR18=0x6112, DQSOSC=391, MR23=63, INC=171, DEC=114
4371 10:01:27.583522 [RxdqsGatingPostProcess] freq 600
4372 10:01:27.586953 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4373 10:01:27.590199 Pre-setting of DQS Precalculation
4374 10:01:27.596777 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4375 10:01:27.596857 ==
4376 10:01:27.600259 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 10:01:27.603408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 10:01:27.603492 ==
4379 10:01:27.610439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 10:01:27.613174 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4381 10:01:27.617442 [CA 0] Center 35 (5~66) winsize 62
4382 10:01:27.620861 [CA 1] Center 35 (5~66) winsize 62
4383 10:01:27.623820 [CA 2] Center 34 (4~65) winsize 62
4384 10:01:27.627266 [CA 3] Center 33 (3~64) winsize 62
4385 10:01:27.630920 [CA 4] Center 34 (4~65) winsize 62
4386 10:01:27.634190 [CA 5] Center 33 (3~64) winsize 62
4387 10:01:27.634270
4388 10:01:27.637306 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4389 10:01:27.637386
4390 10:01:27.640545 [CATrainingPosCal] consider 1 rank data
4391 10:01:27.644052 u2DelayCellTimex100 = 270/100 ps
4392 10:01:27.647393 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 10:01:27.653802 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 10:01:27.657275 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 10:01:27.660192 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 10:01:27.663248 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4397 10:01:27.666933 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 10:01:27.667039
4399 10:01:27.669990 CA PerBit enable=1, Macro0, CA PI delay=33
4400 10:01:27.670070
4401 10:01:27.673463 [CBTSetCACLKResult] CA Dly = 33
4402 10:01:27.676547 CS Dly: 5 (0~36)
4403 10:01:27.676627 ==
4404 10:01:27.680360 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 10:01:27.683519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 10:01:27.683601 ==
4407 10:01:27.689869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 10:01:27.692929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4409 10:01:27.697936 [CA 0] Center 35 (5~66) winsize 62
4410 10:01:27.700952 [CA 1] Center 36 (6~66) winsize 61
4411 10:01:27.704188 [CA 2] Center 34 (4~65) winsize 62
4412 10:01:27.707555 [CA 3] Center 34 (3~65) winsize 63
4413 10:01:27.711112 [CA 4] Center 34 (4~65) winsize 62
4414 10:01:27.714325 [CA 5] Center 34 (3~65) winsize 63
4415 10:01:27.714408
4416 10:01:27.717554 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4417 10:01:27.717634
4418 10:01:27.720519 [CATrainingPosCal] consider 2 rank data
4419 10:01:27.724023 u2DelayCellTimex100 = 270/100 ps
4420 10:01:27.727495 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 10:01:27.733819 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4422 10:01:27.737298 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4423 10:01:27.740713 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4424 10:01:27.743946 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 10:01:27.747342 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 10:01:27.747426
4427 10:01:27.750806 CA PerBit enable=1, Macro0, CA PI delay=33
4428 10:01:27.750887
4429 10:01:27.753841 [CBTSetCACLKResult] CA Dly = 33
4430 10:01:27.757198 CS Dly: 5 (0~36)
4431 10:01:27.757278
4432 10:01:27.760299 ----->DramcWriteLeveling(PI) begin...
4433 10:01:27.760381 ==
4434 10:01:27.763734 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 10:01:27.767222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 10:01:27.767303 ==
4437 10:01:27.770008 Write leveling (Byte 0): 29 => 29
4438 10:01:27.773771 Write leveling (Byte 1): 29 => 29
4439 10:01:27.777076 DramcWriteLeveling(PI) end<-----
4440 10:01:27.777156
4441 10:01:27.777220 ==
4442 10:01:27.780131 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 10:01:27.783645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 10:01:27.783727 ==
4445 10:01:27.787308 [Gating] SW mode calibration
4446 10:01:27.793240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4447 10:01:27.800198 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4448 10:01:27.803197 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 10:01:27.806544 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 10:01:27.813260 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 10:01:27.816242 0 9 12 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 1)
4452 10:01:27.819454 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 10:01:27.826235 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 10:01:27.829281 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 10:01:27.832584 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 10:01:27.839119 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 10:01:27.842774 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 10:01:27.846146 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 10:01:27.852778 0 10 12 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
4460 10:01:27.855924 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 10:01:27.859283 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 10:01:27.865540 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 10:01:27.868834 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 10:01:27.872426 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 10:01:27.879105 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 10:01:27.881972 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 10:01:27.885716 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4468 10:01:27.892222 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 10:01:27.895580 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 10:01:27.898714 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 10:01:27.905555 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 10:01:27.908950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 10:01:27.911965 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 10:01:27.918849 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 10:01:27.922057 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 10:01:27.925219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 10:01:27.931597 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 10:01:27.935203 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 10:01:27.938531 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 10:01:27.945167 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 10:01:27.948187 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 10:01:27.951537 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 10:01:27.958296 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4484 10:01:27.958402 Total UI for P1: 0, mck2ui 16
4485 10:01:27.964970 best dqsien dly found for B1: ( 0, 13, 10)
4486 10:01:27.968523 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 10:01:27.971552 Total UI for P1: 0, mck2ui 16
4488 10:01:27.975142 best dqsien dly found for B0: ( 0, 13, 12)
4489 10:01:27.978704 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4490 10:01:27.981770 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4491 10:01:27.981849
4492 10:01:27.984977 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4493 10:01:27.988451 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4494 10:01:27.991655 [Gating] SW calibration Done
4495 10:01:27.991735 ==
4496 10:01:27.995171 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 10:01:27.998050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 10:01:28.001583 ==
4499 10:01:28.001663 RX Vref Scan: 0
4500 10:01:28.001728
4501 10:01:28.005265 RX Vref 0 -> 0, step: 1
4502 10:01:28.005346
4503 10:01:28.008211 RX Delay -230 -> 252, step: 16
4504 10:01:28.011620 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4505 10:01:28.014873 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4506 10:01:28.018478 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4507 10:01:28.024655 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4508 10:01:28.027998 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4509 10:01:28.031503 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4510 10:01:28.034546 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4511 10:01:28.037695 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4512 10:01:28.044477 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4513 10:01:28.047933 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4514 10:01:28.051674 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4515 10:01:28.054257 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4516 10:01:28.060877 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4517 10:01:28.064235 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4518 10:01:28.067707 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4519 10:01:28.071172 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4520 10:01:28.071252 ==
4521 10:01:28.074284 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 10:01:28.081126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 10:01:28.081206 ==
4524 10:01:28.081269 DQS Delay:
4525 10:01:28.084374 DQS0 = 0, DQS1 = 0
4526 10:01:28.084454 DQM Delay:
4527 10:01:28.087697 DQM0 = 45, DQM1 = 37
4528 10:01:28.087809 DQ Delay:
4529 10:01:28.090805 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4530 10:01:28.093968 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4531 10:01:28.097404 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4532 10:01:28.100454 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4533 10:01:28.100527
4534 10:01:28.100588
4535 10:01:28.100645 ==
4536 10:01:28.104109 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 10:01:28.107698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 10:01:28.107778 ==
4539 10:01:28.107839
4540 10:01:28.107895
4541 10:01:28.110405 TX Vref Scan disable
4542 10:01:28.113705 == TX Byte 0 ==
4543 10:01:28.117541 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 10:01:28.120480 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 10:01:28.123641 == TX Byte 1 ==
4546 10:01:28.127272 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4547 10:01:28.130608 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4548 10:01:28.130723 ==
4549 10:01:28.133760 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 10:01:28.140211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 10:01:28.140313 ==
4552 10:01:28.140401
4553 10:01:28.140494
4554 10:01:28.140580 TX Vref Scan disable
4555 10:01:28.144340 == TX Byte 0 ==
4556 10:01:28.147730 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4557 10:01:28.154208 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4558 10:01:28.154306 == TX Byte 1 ==
4559 10:01:28.157667 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4560 10:01:28.163953 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4561 10:01:28.164057
4562 10:01:28.164122 [DATLAT]
4563 10:01:28.164180 Freq=600, CH1 RK0
4564 10:01:28.164256
4565 10:01:28.167648 DATLAT Default: 0x9
4566 10:01:28.167716 0, 0xFFFF, sum = 0
4567 10:01:28.171155 1, 0xFFFF, sum = 0
4568 10:01:28.174327 2, 0xFFFF, sum = 0
4569 10:01:28.174422 3, 0xFFFF, sum = 0
4570 10:01:28.177111 4, 0xFFFF, sum = 0
4571 10:01:28.177207 5, 0xFFFF, sum = 0
4572 10:01:28.180782 6, 0xFFFF, sum = 0
4573 10:01:28.180885 7, 0xFFFF, sum = 0
4574 10:01:28.183807 8, 0x0, sum = 1
4575 10:01:28.183903 9, 0x0, sum = 2
4576 10:01:28.187053 10, 0x0, sum = 3
4577 10:01:28.187129 11, 0x0, sum = 4
4578 10:01:28.187199 best_step = 9
4579 10:01:28.187265
4580 10:01:28.190328 ==
4581 10:01:28.193750 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 10:01:28.197186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 10:01:28.197260 ==
4584 10:01:28.197321 RX Vref Scan: 1
4585 10:01:28.197379
4586 10:01:28.200597 RX Vref 0 -> 0, step: 1
4587 10:01:28.200674
4588 10:01:28.203640 RX Delay -179 -> 252, step: 8
4589 10:01:28.203707
4590 10:01:28.207090 Set Vref, RX VrefLevel [Byte0]: 48
4591 10:01:28.210117 [Byte1]: 54
4592 10:01:28.210219
4593 10:01:28.213748 Final RX Vref Byte 0 = 48 to rank0
4594 10:01:28.217357 Final RX Vref Byte 1 = 54 to rank0
4595 10:01:28.220284 Final RX Vref Byte 0 = 48 to rank1
4596 10:01:28.223553 Final RX Vref Byte 1 = 54 to rank1==
4597 10:01:28.226572 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 10:01:28.230115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 10:01:28.233420 ==
4600 10:01:28.233528 DQS Delay:
4601 10:01:28.233617 DQS0 = 0, DQS1 = 0
4602 10:01:28.236418 DQM Delay:
4603 10:01:28.236488 DQM0 = 47, DQM1 = 38
4604 10:01:28.239938 DQ Delay:
4605 10:01:28.240010 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4606 10:01:28.243354 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4607 10:01:28.246484 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =28
4608 10:01:28.249937 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4609 10:01:28.253116
4610 10:01:28.253191
4611 10:01:28.260078 [DQSOSCAuto] RK0, (LSB)MR18= 0x553a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 393 ps
4612 10:01:28.263433 CH1 RK0: MR19=808, MR18=553A
4613 10:01:28.269629 CH1_RK0: MR19=0x808, MR18=0x553A, DQSOSC=393, MR23=63, INC=169, DEC=113
4614 10:01:28.269707
4615 10:01:28.273163 ----->DramcWriteLeveling(PI) begin...
4616 10:01:28.273274 ==
4617 10:01:28.276522 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 10:01:28.279681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 10:01:28.279752 ==
4620 10:01:28.282867 Write leveling (Byte 0): 30 => 30
4621 10:01:28.286745 Write leveling (Byte 1): 30 => 30
4622 10:01:28.289445 DramcWriteLeveling(PI) end<-----
4623 10:01:28.289523
4624 10:01:28.289585 ==
4625 10:01:28.292634 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 10:01:28.296162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 10:01:28.296257 ==
4628 10:01:28.299643 [Gating] SW mode calibration
4629 10:01:28.305986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4630 10:01:28.312579 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4631 10:01:28.315598 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 10:01:28.322479 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 10:01:28.325755 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4634 10:01:28.328791 0 9 12 | B1->B0 | 2e2e 3333 | 1 0 | (1 0) (0 0)
4635 10:01:28.335353 0 9 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4636 10:01:28.338512 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 10:01:28.342082 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 10:01:28.348841 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 10:01:28.352283 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 10:01:28.355584 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 10:01:28.361838 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 10:01:28.365407 0 10 12 | B1->B0 | 3232 2929 | 1 0 | (0 0) (0 0)
4643 10:01:28.368524 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4644 10:01:28.375281 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 10:01:28.378542 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 10:01:28.381978 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 10:01:28.388437 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 10:01:28.391812 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 10:01:28.394912 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 10:01:28.402020 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 10:01:28.404816 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4652 10:01:28.408636 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 10:01:28.414812 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 10:01:28.418027 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 10:01:28.421343 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 10:01:28.428156 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 10:01:28.431464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 10:01:28.434826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 10:01:28.441516 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 10:01:28.444612 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 10:01:28.447744 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 10:01:28.454486 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 10:01:28.457331 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 10:01:28.461028 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 10:01:28.467691 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 10:01:28.471013 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4667 10:01:28.473919 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 10:01:28.477369 Total UI for P1: 0, mck2ui 16
4669 10:01:28.480689 best dqsien dly found for B0: ( 0, 13, 14)
4670 10:01:28.484132 Total UI for P1: 0, mck2ui 16
4671 10:01:28.487189 best dqsien dly found for B1: ( 0, 13, 12)
4672 10:01:28.490431 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4673 10:01:28.494109 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4674 10:01:28.494188
4675 10:01:28.500741 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4676 10:01:28.503792 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4677 10:01:28.503872 [Gating] SW calibration Done
4678 10:01:28.506990 ==
4679 10:01:28.510768 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 10:01:28.513536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 10:01:28.513626 ==
4682 10:01:28.513694 RX Vref Scan: 0
4683 10:01:28.513754
4684 10:01:28.516956 RX Vref 0 -> 0, step: 1
4685 10:01:28.517036
4686 10:01:28.520090 RX Delay -230 -> 252, step: 16
4687 10:01:28.523842 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4688 10:01:28.526920 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4689 10:01:28.533619 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4690 10:01:28.536652 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4691 10:01:28.539911 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4692 10:01:28.543316 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4693 10:01:28.549940 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4694 10:01:28.553125 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4695 10:01:28.556412 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4696 10:01:28.559964 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4697 10:01:28.566977 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4698 10:01:28.569768 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4699 10:01:28.573071 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4700 10:01:28.576080 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4701 10:01:28.583001 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4702 10:01:28.586290 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4703 10:01:28.586396 ==
4704 10:01:28.589777 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 10:01:28.592927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 10:01:28.593025 ==
4707 10:01:28.596099 DQS Delay:
4708 10:01:28.596172 DQS0 = 0, DQS1 = 0
4709 10:01:28.596268 DQM Delay:
4710 10:01:28.599711 DQM0 = 43, DQM1 = 36
4711 10:01:28.599784 DQ Delay:
4712 10:01:28.602549 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4713 10:01:28.606249 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4714 10:01:28.609153 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4715 10:01:28.612617 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4716 10:01:28.612714
4717 10:01:28.612809
4718 10:01:28.612896 ==
4719 10:01:28.615939 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 10:01:28.622126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 10:01:28.622228 ==
4722 10:01:28.622362
4723 10:01:28.622447
4724 10:01:28.622539 TX Vref Scan disable
4725 10:01:28.626221 == TX Byte 0 ==
4726 10:01:28.629417 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4727 10:01:28.636213 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4728 10:01:28.636291 == TX Byte 1 ==
4729 10:01:28.639731 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4730 10:01:28.645774 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4731 10:01:28.645858 ==
4732 10:01:28.649428 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 10:01:28.652794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 10:01:28.652863 ==
4735 10:01:28.652929
4736 10:01:28.652989
4737 10:01:28.656010 TX Vref Scan disable
4738 10:01:28.659279 == TX Byte 0 ==
4739 10:01:28.662369 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4740 10:01:28.666263 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4741 10:01:28.669077 == TX Byte 1 ==
4742 10:01:28.672582 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4743 10:01:28.676158 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4744 10:01:28.676232
4745 10:01:28.676293 [DATLAT]
4746 10:01:28.679021 Freq=600, CH1 RK1
4747 10:01:28.679087
4748 10:01:28.679146 DATLAT Default: 0x9
4749 10:01:28.682212 0, 0xFFFF, sum = 0
4750 10:01:28.685713 1, 0xFFFF, sum = 0
4751 10:01:28.685794 2, 0xFFFF, sum = 0
4752 10:01:28.688886 3, 0xFFFF, sum = 0
4753 10:01:28.688960 4, 0xFFFF, sum = 0
4754 10:01:28.692859 5, 0xFFFF, sum = 0
4755 10:01:28.692936 6, 0xFFFF, sum = 0
4756 10:01:28.696125 7, 0xFFFF, sum = 0
4757 10:01:28.696196 8, 0x0, sum = 1
4758 10:01:28.699474 9, 0x0, sum = 2
4759 10:01:28.699544 10, 0x0, sum = 3
4760 10:01:28.699604 11, 0x0, sum = 4
4761 10:01:28.702101 best_step = 9
4762 10:01:28.702168
4763 10:01:28.702224 ==
4764 10:01:28.705527 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 10:01:28.708770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 10:01:28.708846 ==
4767 10:01:28.712172 RX Vref Scan: 0
4768 10:01:28.712241
4769 10:01:28.712306 RX Vref 0 -> 0, step: 1
4770 10:01:28.716286
4771 10:01:28.716362 RX Delay -195 -> 252, step: 8
4772 10:01:28.723203 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4773 10:01:28.726272 iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296
4774 10:01:28.729676 iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296
4775 10:01:28.733275 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4776 10:01:28.739449 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4777 10:01:28.742673 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4778 10:01:28.746042 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4779 10:01:28.749691 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4780 10:01:28.752694 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4781 10:01:28.759364 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4782 10:01:28.762846 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4783 10:01:28.765919 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4784 10:01:28.769462 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4785 10:01:28.775588 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4786 10:01:28.779337 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4787 10:01:28.782113 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4788 10:01:28.782190 ==
4789 10:01:28.785655 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 10:01:28.792358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 10:01:28.792442 ==
4792 10:01:28.792528 DQS Delay:
4793 10:01:28.795752 DQS0 = 0, DQS1 = 0
4794 10:01:28.795826 DQM Delay:
4795 10:01:28.795907 DQM0 = 45, DQM1 = 36
4796 10:01:28.798902 DQ Delay:
4797 10:01:28.802689 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4798 10:01:28.805815 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4799 10:01:28.809111 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4800 10:01:28.812041 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4801 10:01:28.812120
4802 10:01:28.812193
4803 10:01:28.818498 [DQSOSCAuto] RK1, (LSB)MR18= 0x3024, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4804 10:01:28.821648 CH1 RK1: MR19=808, MR18=3024
4805 10:01:28.828926 CH1_RK1: MR19=0x808, MR18=0x3024, DQSOSC=400, MR23=63, INC=163, DEC=109
4806 10:01:28.831640 [RxdqsGatingPostProcess] freq 600
4807 10:01:28.835353 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4808 10:01:28.838477 Pre-setting of DQS Precalculation
4809 10:01:28.845457 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4810 10:01:28.851924 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4811 10:01:28.858223 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4812 10:01:28.858303
4813 10:01:28.858369
4814 10:01:28.861936 [Calibration Summary] 1200 Mbps
4815 10:01:28.862010 CH 0, Rank 0
4816 10:01:28.865128 SW Impedance : PASS
4817 10:01:28.868053 DUTY Scan : NO K
4818 10:01:28.868129 ZQ Calibration : PASS
4819 10:01:28.871519 Jitter Meter : NO K
4820 10:01:28.875038 CBT Training : PASS
4821 10:01:28.875117 Write leveling : PASS
4822 10:01:28.877907 RX DQS gating : PASS
4823 10:01:28.881580 RX DQ/DQS(RDDQC) : PASS
4824 10:01:28.881650 TX DQ/DQS : PASS
4825 10:01:28.884796 RX DATLAT : PASS
4826 10:01:28.888044 RX DQ/DQS(Engine): PASS
4827 10:01:28.888120 TX OE : NO K
4828 10:01:28.891429 All Pass.
4829 10:01:28.891507
4830 10:01:28.891571 CH 0, Rank 1
4831 10:01:28.894541 SW Impedance : PASS
4832 10:01:28.894619 DUTY Scan : NO K
4833 10:01:28.898208 ZQ Calibration : PASS
4834 10:01:28.901534 Jitter Meter : NO K
4835 10:01:28.901610 CBT Training : PASS
4836 10:01:28.904685 Write leveling : PASS
4837 10:01:28.907653 RX DQS gating : PASS
4838 10:01:28.907726 RX DQ/DQS(RDDQC) : PASS
4839 10:01:28.911550 TX DQ/DQS : PASS
4840 10:01:28.911623 RX DATLAT : PASS
4841 10:01:28.914562 RX DQ/DQS(Engine): PASS
4842 10:01:28.918166 TX OE : NO K
4843 10:01:28.918245 All Pass.
4844 10:01:28.918328
4845 10:01:28.921049 CH 1, Rank 0
4846 10:01:28.921126 SW Impedance : PASS
4847 10:01:28.924359 DUTY Scan : NO K
4848 10:01:28.924431 ZQ Calibration : PASS
4849 10:01:28.927781 Jitter Meter : NO K
4850 10:01:28.930869 CBT Training : PASS
4851 10:01:28.930950 Write leveling : PASS
4852 10:01:28.934326 RX DQS gating : PASS
4853 10:01:28.937446 RX DQ/DQS(RDDQC) : PASS
4854 10:01:28.937524 TX DQ/DQS : PASS
4855 10:01:28.940651 RX DATLAT : PASS
4856 10:01:28.944280 RX DQ/DQS(Engine): PASS
4857 10:01:28.944357 TX OE : NO K
4858 10:01:28.947505 All Pass.
4859 10:01:28.947583
4860 10:01:28.947663 CH 1, Rank 1
4861 10:01:28.950681 SW Impedance : PASS
4862 10:01:28.950754 DUTY Scan : NO K
4863 10:01:28.953746 ZQ Calibration : PASS
4864 10:01:28.957439 Jitter Meter : NO K
4865 10:01:28.957514 CBT Training : PASS
4866 10:01:28.960896 Write leveling : PASS
4867 10:01:28.964400 RX DQS gating : PASS
4868 10:01:28.964476 RX DQ/DQS(RDDQC) : PASS
4869 10:01:28.967403 TX DQ/DQS : PASS
4870 10:01:28.970395 RX DATLAT : PASS
4871 10:01:28.970467 RX DQ/DQS(Engine): PASS
4872 10:01:28.973806 TX OE : NO K
4873 10:01:28.973894 All Pass.
4874 10:01:28.973957
4875 10:01:28.977380 DramC Write-DBI off
4876 10:01:28.980168 PER_BANK_REFRESH: Hybrid Mode
4877 10:01:28.980269 TX_TRACKING: ON
4878 10:01:28.989992 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4879 10:01:28.993711 [FAST_K] Save calibration result to emmc
4880 10:01:28.997010 dramc_set_vcore_voltage set vcore to 662500
4881 10:01:29.000155 Read voltage for 933, 3
4882 10:01:29.000228 Vio18 = 0
4883 10:01:29.000287 Vcore = 662500
4884 10:01:29.003903 Vdram = 0
4885 10:01:29.003987 Vddq = 0
4886 10:01:29.004048 Vmddr = 0
4887 10:01:29.010359 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4888 10:01:29.013666 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4889 10:01:29.016712 MEM_TYPE=3, freq_sel=17
4890 10:01:29.020157 sv_algorithm_assistance_LP4_1600
4891 10:01:29.023423 ============ PULL DRAM RESETB DOWN ============
4892 10:01:29.026689 ========== PULL DRAM RESETB DOWN end =========
4893 10:01:29.033854 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4894 10:01:29.037002 ===================================
4895 10:01:29.037107 LPDDR4 DRAM CONFIGURATION
4896 10:01:29.039907 ===================================
4897 10:01:29.043550 EX_ROW_EN[0] = 0x0
4898 10:01:29.046293 EX_ROW_EN[1] = 0x0
4899 10:01:29.046387 LP4Y_EN = 0x0
4900 10:01:29.049905 WORK_FSP = 0x0
4901 10:01:29.049991 WL = 0x3
4902 10:01:29.053040 RL = 0x3
4903 10:01:29.053136 BL = 0x2
4904 10:01:29.056263 RPST = 0x0
4905 10:01:29.056333 RD_PRE = 0x0
4906 10:01:29.059419 WR_PRE = 0x1
4907 10:01:29.059490 WR_PST = 0x0
4908 10:01:29.062969 DBI_WR = 0x0
4909 10:01:29.063041 DBI_RD = 0x0
4910 10:01:29.066400 OTF = 0x1
4911 10:01:29.069225 ===================================
4912 10:01:29.072948 ===================================
4913 10:01:29.073048 ANA top config
4914 10:01:29.075926 ===================================
4915 10:01:29.079123 DLL_ASYNC_EN = 0
4916 10:01:29.082614 ALL_SLAVE_EN = 1
4917 10:01:29.086426 NEW_RANK_MODE = 1
4918 10:01:29.089315 DLL_IDLE_MODE = 1
4919 10:01:29.089412 LP45_APHY_COMB_EN = 1
4920 10:01:29.092332 TX_ODT_DIS = 1
4921 10:01:29.095688 NEW_8X_MODE = 1
4922 10:01:29.099133 ===================================
4923 10:01:29.102064 ===================================
4924 10:01:29.105753 data_rate = 1866
4925 10:01:29.108835 CKR = 1
4926 10:01:29.112316 DQ_P2S_RATIO = 8
4927 10:01:29.115412 ===================================
4928 10:01:29.115518 CA_P2S_RATIO = 8
4929 10:01:29.118537 DQ_CA_OPEN = 0
4930 10:01:29.121867 DQ_SEMI_OPEN = 0
4931 10:01:29.125450 CA_SEMI_OPEN = 0
4932 10:01:29.128327 CA_FULL_RATE = 0
4933 10:01:29.131960 DQ_CKDIV4_EN = 1
4934 10:01:29.132040 CA_CKDIV4_EN = 1
4935 10:01:29.135423 CA_PREDIV_EN = 0
4936 10:01:29.138930 PH8_DLY = 0
4937 10:01:29.141770 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4938 10:01:29.145107 DQ_AAMCK_DIV = 4
4939 10:01:29.148470 CA_AAMCK_DIV = 4
4940 10:01:29.148549 CA_ADMCK_DIV = 4
4941 10:01:29.152017 DQ_TRACK_CA_EN = 0
4942 10:01:29.155349 CA_PICK = 933
4943 10:01:29.158473 CA_MCKIO = 933
4944 10:01:29.161650 MCKIO_SEMI = 0
4945 10:01:29.164897 PLL_FREQ = 3732
4946 10:01:29.168815 DQ_UI_PI_RATIO = 32
4947 10:01:29.168895 CA_UI_PI_RATIO = 0
4948 10:01:29.171529 ===================================
4949 10:01:29.175011 ===================================
4950 10:01:29.178700 memory_type:LPDDR4
4951 10:01:29.181508 GP_NUM : 10
4952 10:01:29.181588 SRAM_EN : 1
4953 10:01:29.185114 MD32_EN : 0
4954 10:01:29.188040 ===================================
4955 10:01:29.191511 [ANA_INIT] >>>>>>>>>>>>>>
4956 10:01:29.194937 <<<<<< [CONFIGURE PHASE]: ANA_TX
4957 10:01:29.198129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4958 10:01:29.201470 ===================================
4959 10:01:29.201550 data_rate = 1866,PCW = 0X8f00
4960 10:01:29.205302 ===================================
4961 10:01:29.207929 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4962 10:01:29.214945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 10:01:29.220958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4964 10:01:29.224610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4965 10:01:29.227989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4966 10:01:29.230802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4967 10:01:29.234246 [ANA_INIT] flow start
4968 10:01:29.237528 [ANA_INIT] PLL >>>>>>>>
4969 10:01:29.237608 [ANA_INIT] PLL <<<<<<<<
4970 10:01:29.240801 [ANA_INIT] MIDPI >>>>>>>>
4971 10:01:29.244230 [ANA_INIT] MIDPI <<<<<<<<
4972 10:01:29.244310 [ANA_INIT] DLL >>>>>>>>
4973 10:01:29.247397 [ANA_INIT] flow end
4974 10:01:29.250761 ============ LP4 DIFF to SE enter ============
4975 10:01:29.254056 ============ LP4 DIFF to SE exit ============
4976 10:01:29.257473 [ANA_INIT] <<<<<<<<<<<<<
4977 10:01:29.260980 [Flow] Enable top DCM control >>>>>
4978 10:01:29.264466 [Flow] Enable top DCM control <<<<<
4979 10:01:29.267417 Enable DLL master slave shuffle
4980 10:01:29.274089 ==============================================================
4981 10:01:29.274173 Gating Mode config
4982 10:01:29.280896 ==============================================================
4983 10:01:29.283813 Config description:
4984 10:01:29.290445 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4985 10:01:29.297231 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4986 10:01:29.303651 SELPH_MODE 0: By rank 1: By Phase
4987 10:01:29.310099 ==============================================================
4988 10:01:29.310182 GAT_TRACK_EN = 1
4989 10:01:29.313470 RX_GATING_MODE = 2
4990 10:01:29.317226 RX_GATING_TRACK_MODE = 2
4991 10:01:29.320406 SELPH_MODE = 1
4992 10:01:29.323346 PICG_EARLY_EN = 1
4993 10:01:29.326698 VALID_LAT_VALUE = 1
4994 10:01:29.333452 ==============================================================
4995 10:01:29.336600 Enter into Gating configuration >>>>
4996 10:01:29.339747 Exit from Gating configuration <<<<
4997 10:01:29.342975 Enter into DVFS_PRE_config >>>>>
4998 10:01:29.353101 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4999 10:01:29.356476 Exit from DVFS_PRE_config <<<<<
5000 10:01:29.359461 Enter into PICG configuration >>>>
5001 10:01:29.363320 Exit from PICG configuration <<<<
5002 10:01:29.366366 [RX_INPUT] configuration >>>>>
5003 10:01:29.369952 [RX_INPUT] configuration <<<<<
5004 10:01:29.372850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5005 10:01:29.379616 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5006 10:01:29.386546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5007 10:01:29.393016 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5008 10:01:29.396420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 10:01:29.402444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 10:01:29.405936 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5011 10:01:29.412342 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5012 10:01:29.416009 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5013 10:01:29.418845 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5014 10:01:29.425243 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5015 10:01:29.428628 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 10:01:29.432012 ===================================
5017 10:01:29.435411 LPDDR4 DRAM CONFIGURATION
5018 10:01:29.438822 ===================================
5019 10:01:29.438927 EX_ROW_EN[0] = 0x0
5020 10:01:29.442488 EX_ROW_EN[1] = 0x0
5021 10:01:29.442595 LP4Y_EN = 0x0
5022 10:01:29.445524 WORK_FSP = 0x0
5023 10:01:29.445618 WL = 0x3
5024 10:01:29.448361 RL = 0x3
5025 10:01:29.448454 BL = 0x2
5026 10:01:29.452153 RPST = 0x0
5027 10:01:29.452250 RD_PRE = 0x0
5028 10:01:29.455563 WR_PRE = 0x1
5029 10:01:29.455660 WR_PST = 0x0
5030 10:01:29.458973 DBI_WR = 0x0
5031 10:01:29.462047 DBI_RD = 0x0
5032 10:01:29.462118 OTF = 0x1
5033 10:01:29.465180 ===================================
5034 10:01:29.468844 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5035 10:01:29.471658 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5036 10:01:29.478528 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 10:01:29.482025 ===================================
5038 10:01:29.485406 LPDDR4 DRAM CONFIGURATION
5039 10:01:29.488552 ===================================
5040 10:01:29.488631 EX_ROW_EN[0] = 0x10
5041 10:01:29.491767 EX_ROW_EN[1] = 0x0
5042 10:01:29.491847 LP4Y_EN = 0x0
5043 10:01:29.495161 WORK_FSP = 0x0
5044 10:01:29.495239 WL = 0x3
5045 10:01:29.498553 RL = 0x3
5046 10:01:29.498668 BL = 0x2
5047 10:01:29.502301 RPST = 0x0
5048 10:01:29.502381 RD_PRE = 0x0
5049 10:01:29.505185 WR_PRE = 0x1
5050 10:01:29.505264 WR_PST = 0x0
5051 10:01:29.508682 DBI_WR = 0x0
5052 10:01:29.508762 DBI_RD = 0x0
5053 10:01:29.511666 OTF = 0x1
5054 10:01:29.515084 ===================================
5055 10:01:29.521439 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5056 10:01:29.525171 nWR fixed to 30
5057 10:01:29.528008 [ModeRegInit_LP4] CH0 RK0
5058 10:01:29.528089 [ModeRegInit_LP4] CH0 RK1
5059 10:01:29.531465 [ModeRegInit_LP4] CH1 RK0
5060 10:01:29.535089 [ModeRegInit_LP4] CH1 RK1
5061 10:01:29.535166 match AC timing 9
5062 10:01:29.541663 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5063 10:01:29.544623 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5064 10:01:29.547934 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5065 10:01:29.554513 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5066 10:01:29.558033 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5067 10:01:29.558132 ==
5068 10:01:29.561395 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 10:01:29.564843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 10:01:29.564920 ==
5071 10:01:29.571181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 10:01:29.577434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5073 10:01:29.580829 [CA 0] Center 37 (7~68) winsize 62
5074 10:01:29.584242 [CA 1] Center 37 (7~68) winsize 62
5075 10:01:29.588077 [CA 2] Center 34 (4~65) winsize 62
5076 10:01:29.590859 [CA 3] Center 35 (5~65) winsize 61
5077 10:01:29.594372 [CA 4] Center 33 (3~64) winsize 62
5078 10:01:29.597551 [CA 5] Center 33 (3~63) winsize 61
5079 10:01:29.597669
5080 10:01:29.600775 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5081 10:01:29.600850
5082 10:01:29.603918 [CATrainingPosCal] consider 1 rank data
5083 10:01:29.607204 u2DelayCellTimex100 = 270/100 ps
5084 10:01:29.610613 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5085 10:01:29.613926 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5086 10:01:29.617361 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5087 10:01:29.620341 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5088 10:01:29.627375 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5089 10:01:29.630344 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5090 10:01:29.630418
5091 10:01:29.633623 CA PerBit enable=1, Macro0, CA PI delay=33
5092 10:01:29.633731
5093 10:01:29.637069 [CBTSetCACLKResult] CA Dly = 33
5094 10:01:29.637157 CS Dly: 7 (0~38)
5095 10:01:29.637227 ==
5096 10:01:29.640163 Dram Type= 6, Freq= 0, CH_0, rank 1
5097 10:01:29.647025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 10:01:29.647102 ==
5099 10:01:29.650237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 10:01:29.656925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5101 10:01:29.659913 [CA 0] Center 37 (7~68) winsize 62
5102 10:01:29.663489 [CA 1] Center 37 (7~68) winsize 62
5103 10:01:29.666580 [CA 2] Center 34 (4~65) winsize 62
5104 10:01:29.670398 [CA 3] Center 34 (4~65) winsize 62
5105 10:01:29.673373 [CA 4] Center 33 (3~64) winsize 62
5106 10:01:29.676505 [CA 5] Center 32 (2~63) winsize 62
5107 10:01:29.676589
5108 10:01:29.680278 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5109 10:01:29.680349
5110 10:01:29.683368 [CATrainingPosCal] consider 2 rank data
5111 10:01:29.686512 u2DelayCellTimex100 = 270/100 ps
5112 10:01:29.689770 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5113 10:01:29.696308 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5114 10:01:29.699683 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5115 10:01:29.702942 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5116 10:01:29.706474 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5117 10:01:29.709703 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5118 10:01:29.709786
5119 10:01:29.712747 CA PerBit enable=1, Macro0, CA PI delay=33
5120 10:01:29.712828
5121 10:01:29.716034 [CBTSetCACLKResult] CA Dly = 33
5122 10:01:29.719481 CS Dly: 7 (0~39)
5123 10:01:29.719564
5124 10:01:29.722817 ----->DramcWriteLeveling(PI) begin...
5125 10:01:29.722900 ==
5126 10:01:29.725889 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 10:01:29.729750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 10:01:29.729832 ==
5129 10:01:29.732524 Write leveling (Byte 0): 30 => 30
5130 10:01:29.735739 Write leveling (Byte 1): 30 => 30
5131 10:01:29.739254 DramcWriteLeveling(PI) end<-----
5132 10:01:29.739336
5133 10:01:29.739419 ==
5134 10:01:29.742714 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 10:01:29.745746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 10:01:29.745827 ==
5137 10:01:29.749443 [Gating] SW mode calibration
5138 10:01:29.756074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5139 10:01:29.762459 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5140 10:01:29.766016 0 14 0 | B1->B0 | 2323 3232 | 1 0 | (1 1) (0 0)
5141 10:01:29.769171 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5142 10:01:29.775412 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 10:01:29.778919 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 10:01:29.782109 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 10:01:29.789058 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 10:01:29.792405 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 10:01:29.795769 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
5148 10:01:29.802031 0 15 0 | B1->B0 | 3131 2424 | 0 0 | (0 1) (1 0)
5149 10:01:29.805082 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5150 10:01:29.808780 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 10:01:29.815199 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 10:01:29.818477 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 10:01:29.822234 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 10:01:29.828539 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 10:01:29.831885 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
5156 10:01:29.835019 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
5157 10:01:29.841555 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 10:01:29.844895 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 10:01:29.847943 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 10:01:29.854732 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 10:01:29.857755 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 10:01:29.861146 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 10:01:29.868229 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5164 10:01:29.871314 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5165 10:01:29.874802 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5166 10:01:29.881502 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 10:01:29.884751 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 10:01:29.887879 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 10:01:29.894581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 10:01:29.897703 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 10:01:29.901006 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 10:01:29.907414 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 10:01:29.910766 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 10:01:29.914116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 10:01:29.920867 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 10:01:29.923934 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 10:01:29.926978 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 10:01:29.934015 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 10:01:29.936920 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5180 10:01:29.940666 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5181 10:01:29.943854 Total UI for P1: 0, mck2ui 16
5182 10:01:29.947165 best dqsien dly found for B0: ( 1, 2, 28)
5183 10:01:29.953964 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5184 10:01:29.956885 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 10:01:29.960610 Total UI for P1: 0, mck2ui 16
5186 10:01:29.963530 best dqsien dly found for B1: ( 1, 3, 2)
5187 10:01:29.967002 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5188 10:01:29.970500 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5189 10:01:29.970642
5190 10:01:29.973307 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5191 10:01:29.976779 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5192 10:01:29.980409 [Gating] SW calibration Done
5193 10:01:29.980481 ==
5194 10:01:29.983601 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 10:01:29.986721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 10:01:29.990430 ==
5197 10:01:29.990545 RX Vref Scan: 0
5198 10:01:29.990635
5199 10:01:29.993307 RX Vref 0 -> 0, step: 1
5200 10:01:29.993373
5201 10:01:29.996519 RX Delay -80 -> 252, step: 8
5202 10:01:29.999910 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5203 10:01:30.003266 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5204 10:01:30.006302 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5205 10:01:30.010138 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5206 10:01:30.013398 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5207 10:01:30.019423 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5208 10:01:30.022865 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5209 10:01:30.026345 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5210 10:01:30.029358 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5211 10:01:30.032720 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5212 10:01:30.039675 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5213 10:01:30.042802 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5214 10:01:30.047169 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5215 10:01:30.049662 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5216 10:01:30.052646 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5217 10:01:30.059303 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5218 10:01:30.059411 ==
5219 10:01:30.062422 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 10:01:30.066076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 10:01:30.066152 ==
5222 10:01:30.066215 DQS Delay:
5223 10:01:30.069547 DQS0 = 0, DQS1 = 0
5224 10:01:30.069624 DQM Delay:
5225 10:01:30.072865 DQM0 = 97, DQM1 = 86
5226 10:01:30.072944 DQ Delay:
5227 10:01:30.075979 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5228 10:01:30.079027 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5229 10:01:30.082606 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5230 10:01:30.085815 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5231 10:01:30.085912
5232 10:01:30.085989
5233 10:01:30.086052 ==
5234 10:01:30.088866 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 10:01:30.092369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 10:01:30.095542 ==
5237 10:01:30.095647
5238 10:01:30.095714
5239 10:01:30.095772 TX Vref Scan disable
5240 10:01:30.098975 == TX Byte 0 ==
5241 10:01:30.102292 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5242 10:01:30.105677 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5243 10:01:30.108862 == TX Byte 1 ==
5244 10:01:30.112493 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5245 10:01:30.115622 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5246 10:01:30.118946 ==
5247 10:01:30.119024 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 10:01:30.125653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 10:01:30.125732 ==
5250 10:01:30.125793
5251 10:01:30.125859
5252 10:01:30.129052 TX Vref Scan disable
5253 10:01:30.129150 == TX Byte 0 ==
5254 10:01:30.135571 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5255 10:01:30.138402 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5256 10:01:30.138483 == TX Byte 1 ==
5257 10:01:30.145377 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5258 10:01:30.148556 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5259 10:01:30.148639
5260 10:01:30.148702 [DATLAT]
5261 10:01:30.151790 Freq=933, CH0 RK0
5262 10:01:30.151867
5263 10:01:30.151930 DATLAT Default: 0xd
5264 10:01:30.155270 0, 0xFFFF, sum = 0
5265 10:01:30.155346 1, 0xFFFF, sum = 0
5266 10:01:30.158731 2, 0xFFFF, sum = 0
5267 10:01:30.158808 3, 0xFFFF, sum = 0
5268 10:01:30.161693 4, 0xFFFF, sum = 0
5269 10:01:30.161774 5, 0xFFFF, sum = 0
5270 10:01:30.165113 6, 0xFFFF, sum = 0
5271 10:01:30.168347 7, 0xFFFF, sum = 0
5272 10:01:30.168427 8, 0xFFFF, sum = 0
5273 10:01:30.171506 9, 0xFFFF, sum = 0
5274 10:01:30.171586 10, 0x0, sum = 1
5275 10:01:30.171650 11, 0x0, sum = 2
5276 10:01:30.174998 12, 0x0, sum = 3
5277 10:01:30.175073 13, 0x0, sum = 4
5278 10:01:30.178150 best_step = 11
5279 10:01:30.178220
5280 10:01:30.178279 ==
5281 10:01:30.181421 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 10:01:30.184974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 10:01:30.185054 ==
5284 10:01:30.188547 RX Vref Scan: 1
5285 10:01:30.188623
5286 10:01:30.188684 RX Vref 0 -> 0, step: 1
5287 10:01:30.191718
5288 10:01:30.191791 RX Delay -61 -> 252, step: 4
5289 10:01:30.191853
5290 10:01:30.194999 Set Vref, RX VrefLevel [Byte0]: 61
5291 10:01:30.198154 [Byte1]: 47
5292 10:01:30.202320
5293 10:01:30.202418 Final RX Vref Byte 0 = 61 to rank0
5294 10:01:30.205870 Final RX Vref Byte 1 = 47 to rank0
5295 10:01:30.208935 Final RX Vref Byte 0 = 61 to rank1
5296 10:01:30.212597 Final RX Vref Byte 1 = 47 to rank1==
5297 10:01:30.215917 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 10:01:30.222168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 10:01:30.222251 ==
5300 10:01:30.222315 DQS Delay:
5301 10:01:30.225894 DQS0 = 0, DQS1 = 0
5302 10:01:30.225970 DQM Delay:
5303 10:01:30.226031 DQM0 = 96, DQM1 = 84
5304 10:01:30.229178 DQ Delay:
5305 10:01:30.232378 DQ0 =94, DQ1 =96, DQ2 =94, DQ3 =94
5306 10:01:30.235418 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5307 10:01:30.238930 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =78
5308 10:01:30.242464 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5309 10:01:30.242538
5310 10:01:30.242642
5311 10:01:30.249035 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5312 10:01:30.252503 CH0 RK0: MR19=505, MR18=2E15
5313 10:01:30.258737 CH0_RK0: MR19=0x505, MR18=0x2E15, DQSOSC=407, MR23=63, INC=65, DEC=43
5314 10:01:30.258815
5315 10:01:30.262327 ----->DramcWriteLeveling(PI) begin...
5316 10:01:30.262406 ==
5317 10:01:30.265265 Dram Type= 6, Freq= 0, CH_0, rank 1
5318 10:01:30.268831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 10:01:30.268907 ==
5320 10:01:30.271951 Write leveling (Byte 0): 33 => 33
5321 10:01:30.275163 Write leveling (Byte 1): 31 => 31
5322 10:01:30.278398 DramcWriteLeveling(PI) end<-----
5323 10:01:30.278484
5324 10:01:30.278547 ==
5325 10:01:30.281733 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 10:01:30.285123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 10:01:30.288652 ==
5328 10:01:30.288731 [Gating] SW mode calibration
5329 10:01:30.298002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5330 10:01:30.301471 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5331 10:01:30.304793 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5332 10:01:30.311758 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 10:01:30.314994 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 10:01:30.318359 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 10:01:30.324449 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 10:01:30.327946 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 10:01:30.331381 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 10:01:30.337753 0 14 28 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 0)
5339 10:01:30.341484 0 15 0 | B1->B0 | 2d2d 2525 | 0 0 | (0 1) (0 0)
5340 10:01:30.344434 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 10:01:30.350899 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 10:01:30.354587 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 10:01:30.357608 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 10:01:30.364196 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 10:01:30.367883 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 10:01:30.371249 0 15 28 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
5347 10:01:30.377649 1 0 0 | B1->B0 | 3737 3e3e | 0 0 | (0 0) (0 0)
5348 10:01:30.380681 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 10:01:30.384011 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 10:01:30.390926 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 10:01:30.394183 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 10:01:30.397862 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 10:01:30.403616 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 10:01:30.407431 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5355 10:01:30.410533 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5356 10:01:30.416955 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 10:01:30.420231 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 10:01:30.424165 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 10:01:30.430275 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 10:01:30.433656 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 10:01:30.437086 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 10:01:30.443351 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 10:01:30.446586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 10:01:30.449884 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 10:01:30.456658 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 10:01:30.459892 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 10:01:30.463606 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 10:01:30.469972 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 10:01:30.473171 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 10:01:30.476549 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5371 10:01:30.483115 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5372 10:01:30.483195 Total UI for P1: 0, mck2ui 16
5373 10:01:30.489864 best dqsien dly found for B0: ( 1, 2, 28)
5374 10:01:30.493406 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 10:01:30.496558 Total UI for P1: 0, mck2ui 16
5376 10:01:30.499894 best dqsien dly found for B1: ( 1, 3, 0)
5377 10:01:30.503519 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5378 10:01:30.506359 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5379 10:01:30.506436
5380 10:01:30.509805 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5381 10:01:30.513321 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5382 10:01:30.516260 [Gating] SW calibration Done
5383 10:01:30.516335 ==
5384 10:01:30.519592 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 10:01:30.523111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 10:01:30.523196 ==
5387 10:01:30.526079 RX Vref Scan: 0
5388 10:01:30.526152
5389 10:01:30.529301 RX Vref 0 -> 0, step: 1
5390 10:01:30.529376
5391 10:01:30.529456 RX Delay -80 -> 252, step: 8
5392 10:01:30.536446 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5393 10:01:30.539319 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5394 10:01:30.542823 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5395 10:01:30.546482 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5396 10:01:30.549693 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5397 10:01:30.555992 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5398 10:01:30.559386 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5399 10:01:30.562793 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5400 10:01:30.566150 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5401 10:01:30.569380 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5402 10:01:30.572657 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5403 10:01:30.578953 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5404 10:01:30.582665 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5405 10:01:30.585910 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5406 10:01:30.589124 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5407 10:01:30.592378 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5408 10:01:30.595464 ==
5409 10:01:30.595548 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 10:01:30.602403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 10:01:30.602484 ==
5412 10:01:30.602603 DQS Delay:
5413 10:01:30.605546 DQS0 = 0, DQS1 = 0
5414 10:01:30.605625 DQM Delay:
5415 10:01:30.608882 DQM0 = 96, DQM1 = 88
5416 10:01:30.608958 DQ Delay:
5417 10:01:30.611921 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5418 10:01:30.615537 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5419 10:01:30.618744 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5420 10:01:30.621952 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5421 10:01:30.622028
5422 10:01:30.622114
5423 10:01:30.622194 ==
5424 10:01:30.625453 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 10:01:30.628461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 10:01:30.628545 ==
5427 10:01:30.628630
5428 10:01:30.628707
5429 10:01:30.631776 TX Vref Scan disable
5430 10:01:30.635245 == TX Byte 0 ==
5431 10:01:30.638488 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5432 10:01:30.641550 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5433 10:01:30.645048 == TX Byte 1 ==
5434 10:01:30.648444 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5435 10:01:30.651475 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5436 10:01:30.651555 ==
5437 10:01:30.655073 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 10:01:30.661148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 10:01:30.661231 ==
5440 10:01:30.661313
5441 10:01:30.661391
5442 10:01:30.661488 TX Vref Scan disable
5443 10:01:30.665811 == TX Byte 0 ==
5444 10:01:30.669140 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5445 10:01:30.675814 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5446 10:01:30.675905 == TX Byte 1 ==
5447 10:01:30.679219 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5448 10:01:30.685666 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5449 10:01:30.685750
5450 10:01:30.685840 [DATLAT]
5451 10:01:30.685917 Freq=933, CH0 RK1
5452 10:01:30.685994
5453 10:01:30.688957 DATLAT Default: 0xb
5454 10:01:30.689039 0, 0xFFFF, sum = 0
5455 10:01:30.692217 1, 0xFFFF, sum = 0
5456 10:01:30.695313 2, 0xFFFF, sum = 0
5457 10:01:30.695394 3, 0xFFFF, sum = 0
5458 10:01:30.698830 4, 0xFFFF, sum = 0
5459 10:01:30.698912 5, 0xFFFF, sum = 0
5460 10:01:30.702053 6, 0xFFFF, sum = 0
5461 10:01:30.702133 7, 0xFFFF, sum = 0
5462 10:01:30.705802 8, 0xFFFF, sum = 0
5463 10:01:30.705889 9, 0xFFFF, sum = 0
5464 10:01:30.708625 10, 0x0, sum = 1
5465 10:01:30.708700 11, 0x0, sum = 2
5466 10:01:30.712084 12, 0x0, sum = 3
5467 10:01:30.712161 13, 0x0, sum = 4
5468 10:01:30.712250 best_step = 11
5469 10:01:30.712330
5470 10:01:30.715549 ==
5471 10:01:30.718957 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 10:01:30.721762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 10:01:30.721837 ==
5474 10:01:30.721925 RX Vref Scan: 0
5475 10:01:30.722005
5476 10:01:30.724965 RX Vref 0 -> 0, step: 1
5477 10:01:30.725041
5478 10:01:30.728708 RX Delay -61 -> 252, step: 4
5479 10:01:30.735226 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5480 10:01:30.738420 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5481 10:01:30.741700 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5482 10:01:30.745490 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5483 10:01:30.748828 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5484 10:01:30.751623 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5485 10:01:30.758496 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5486 10:01:30.761301 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5487 10:01:30.764832 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5488 10:01:30.768230 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5489 10:01:30.771550 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5490 10:01:30.778217 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5491 10:01:30.781230 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5492 10:01:30.785184 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5493 10:01:30.788086 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5494 10:01:30.791942 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5495 10:01:30.792025 ==
5496 10:01:30.794813 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 10:01:30.801374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 10:01:30.801461 ==
5499 10:01:30.801566 DQS Delay:
5500 10:01:30.804211 DQS0 = 0, DQS1 = 0
5501 10:01:30.804286 DQM Delay:
5502 10:01:30.807623 DQM0 = 95, DQM1 = 86
5503 10:01:30.807700 DQ Delay:
5504 10:01:30.810835 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =92
5505 10:01:30.814584 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5506 10:01:30.817516 DQ8 =76, DQ9 =74, DQ10 =88, DQ11 =78
5507 10:01:30.821366 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5508 10:01:30.821442
5509 10:01:30.821531
5510 10:01:30.827493 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cfb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5511 10:01:30.830848 CH0 RK1: MR19=504, MR18=2CFB
5512 10:01:30.837529 CH0_RK1: MR19=0x504, MR18=0x2CFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5513 10:01:30.840534 [RxdqsGatingPostProcess] freq 933
5514 10:01:30.847005 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5515 10:01:30.850502 best DQS0 dly(2T, 0.5T) = (0, 10)
5516 10:01:30.853484 best DQS1 dly(2T, 0.5T) = (0, 11)
5517 10:01:30.856836 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5518 10:01:30.856916 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5519 10:01:30.860395 best DQS0 dly(2T, 0.5T) = (0, 10)
5520 10:01:30.864186 best DQS1 dly(2T, 0.5T) = (0, 11)
5521 10:01:30.866967 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5522 10:01:30.870523 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5523 10:01:30.873418 Pre-setting of DQS Precalculation
5524 10:01:30.880350 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5525 10:01:30.880430 ==
5526 10:01:30.883265 Dram Type= 6, Freq= 0, CH_1, rank 0
5527 10:01:30.886530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 10:01:30.886645 ==
5529 10:01:30.893060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5530 10:01:30.899924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5531 10:01:30.903256 [CA 0] Center 36 (6~67) winsize 62
5532 10:01:30.906293 [CA 1] Center 37 (6~68) winsize 63
5533 10:01:30.909813 [CA 2] Center 34 (4~65) winsize 62
5534 10:01:30.912912 [CA 3] Center 33 (3~64) winsize 62
5535 10:01:30.916108 [CA 4] Center 34 (4~65) winsize 62
5536 10:01:30.919625 [CA 5] Center 33 (3~64) winsize 62
5537 10:01:30.919700
5538 10:01:30.923099 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5539 10:01:30.923174
5540 10:01:30.926168 [CATrainingPosCal] consider 1 rank data
5541 10:01:30.929517 u2DelayCellTimex100 = 270/100 ps
5542 10:01:30.932473 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 10:01:30.935905 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5544 10:01:30.939392 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5545 10:01:30.942421 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5546 10:01:30.945942 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5547 10:01:30.949103 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5548 10:01:30.949176
5549 10:01:30.955854 CA PerBit enable=1, Macro0, CA PI delay=33
5550 10:01:30.955928
5551 10:01:30.959306 [CBTSetCACLKResult] CA Dly = 33
5552 10:01:30.959384 CS Dly: 6 (0~37)
5553 10:01:30.959453 ==
5554 10:01:30.962396 Dram Type= 6, Freq= 0, CH_1, rank 1
5555 10:01:30.965796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 10:01:30.965872 ==
5557 10:01:30.971999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5558 10:01:30.979345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5559 10:01:30.982065 [CA 0] Center 36 (6~67) winsize 62
5560 10:01:30.985499 [CA 1] Center 37 (7~68) winsize 62
5561 10:01:30.988848 [CA 2] Center 34 (4~65) winsize 62
5562 10:01:30.992510 [CA 3] Center 34 (4~65) winsize 62
5563 10:01:30.995229 [CA 4] Center 34 (4~65) winsize 62
5564 10:01:30.998781 [CA 5] Center 33 (3~64) winsize 62
5565 10:01:30.998858
5566 10:01:31.002035 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5567 10:01:31.002108
5568 10:01:31.005614 [CATrainingPosCal] consider 2 rank data
5569 10:01:31.008854 u2DelayCellTimex100 = 270/100 ps
5570 10:01:31.012414 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5571 10:01:31.015498 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5572 10:01:31.018559 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5573 10:01:31.021885 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5574 10:01:31.025165 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5575 10:01:31.031918 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5576 10:01:31.032008
5577 10:01:31.035608 CA PerBit enable=1, Macro0, CA PI delay=33
5578 10:01:31.035689
5579 10:01:31.038323 [CBTSetCACLKResult] CA Dly = 33
5580 10:01:31.038429 CS Dly: 7 (0~39)
5581 10:01:31.038528
5582 10:01:31.042200 ----->DramcWriteLeveling(PI) begin...
5583 10:01:31.042283 ==
5584 10:01:31.045007 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 10:01:31.051493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 10:01:31.051576 ==
5587 10:01:31.055528 Write leveling (Byte 0): 26 => 26
5588 10:01:31.055609 Write leveling (Byte 1): 27 => 27
5589 10:01:31.058097 DramcWriteLeveling(PI) end<-----
5590 10:01:31.058171
5591 10:01:31.061910 ==
5592 10:01:31.061992 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 10:01:31.068722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 10:01:31.068805 ==
5595 10:01:31.071786 [Gating] SW mode calibration
5596 10:01:31.078142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5597 10:01:31.081449 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5598 10:01:31.088055 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 10:01:31.091571 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 10:01:31.094955 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 10:01:31.101387 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 10:01:31.104874 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 10:01:31.108085 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 10:01:31.114734 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
5605 10:01:31.118367 0 14 28 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (1 1)
5606 10:01:31.120904 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 10:01:31.127445 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 10:01:31.130778 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 10:01:31.134211 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 10:01:31.140824 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 10:01:31.144044 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 10:01:31.147802 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5613 10:01:31.154045 0 15 28 | B1->B0 | 3838 4242 | 1 1 | (0 0) (0 0)
5614 10:01:31.157321 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 10:01:31.160371 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 10:01:31.167453 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 10:01:31.170553 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 10:01:31.173684 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 10:01:31.180646 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 10:01:31.183892 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5621 10:01:31.186854 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5622 10:01:31.193294 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 10:01:31.196735 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 10:01:31.200512 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 10:01:31.206552 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 10:01:31.210210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 10:01:31.213370 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 10:01:31.219880 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 10:01:31.223204 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 10:01:31.226838 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 10:01:31.233475 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 10:01:31.236313 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 10:01:31.239496 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 10:01:31.246322 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 10:01:31.249513 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 10:01:31.252935 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5637 10:01:31.256046 Total UI for P1: 0, mck2ui 16
5638 10:01:31.259180 best dqsien dly found for B1: ( 1, 2, 22)
5639 10:01:31.266336 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 10:01:31.266416 Total UI for P1: 0, mck2ui 16
5641 10:01:31.272677 best dqsien dly found for B0: ( 1, 2, 24)
5642 10:01:31.275942 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5643 10:01:31.279222 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5644 10:01:31.279301
5645 10:01:31.282712 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5646 10:01:31.285838 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5647 10:01:31.288686 [Gating] SW calibration Done
5648 10:01:31.288765 ==
5649 10:01:31.292061 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 10:01:31.295667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 10:01:31.295747 ==
5652 10:01:31.298681 RX Vref Scan: 0
5653 10:01:31.298760
5654 10:01:31.302224 RX Vref 0 -> 0, step: 1
5655 10:01:31.302304
5656 10:01:31.302366 RX Delay -80 -> 252, step: 8
5657 10:01:31.309153 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5658 10:01:31.311835 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5659 10:01:31.315379 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5660 10:01:31.318573 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5661 10:01:31.321916 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5662 10:01:31.324910 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5663 10:01:31.331463 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5664 10:01:31.334971 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5665 10:01:31.338358 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5666 10:01:31.341818 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5667 10:01:31.344762 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5668 10:01:31.351588 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5669 10:01:31.355002 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5670 10:01:31.357965 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5671 10:01:31.361313 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5672 10:01:31.364462 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5673 10:01:31.364541 ==
5674 10:01:31.368398 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 10:01:31.374749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 10:01:31.374830 ==
5677 10:01:31.374894 DQS Delay:
5678 10:01:31.377922 DQS0 = 0, DQS1 = 0
5679 10:01:31.378002 DQM Delay:
5680 10:01:31.378065 DQM0 = 102, DQM1 = 92
5681 10:01:31.381591 DQ Delay:
5682 10:01:31.384758 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5683 10:01:31.388119 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5684 10:01:31.391115 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5685 10:01:31.394361 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5686 10:01:31.394441
5687 10:01:31.394504
5688 10:01:31.394562 ==
5689 10:01:31.397962 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 10:01:31.401185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 10:01:31.401264 ==
5692 10:01:31.401328
5693 10:01:31.401386
5694 10:01:31.404668 TX Vref Scan disable
5695 10:01:31.408148 == TX Byte 0 ==
5696 10:01:31.411312 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5697 10:01:31.414448 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5698 10:01:31.417805 == TX Byte 1 ==
5699 10:01:31.421223 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5700 10:01:31.424352 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5701 10:01:31.424431 ==
5702 10:01:31.427662 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 10:01:31.434232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 10:01:31.434312 ==
5705 10:01:31.434375
5706 10:01:31.434433
5707 10:01:31.434488 TX Vref Scan disable
5708 10:01:31.437782 == TX Byte 0 ==
5709 10:01:31.441683 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5710 10:01:31.448041 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5711 10:01:31.448139 == TX Byte 1 ==
5712 10:01:31.451316 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5713 10:01:31.458210 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5714 10:01:31.458289
5715 10:01:31.458352 [DATLAT]
5716 10:01:31.458411 Freq=933, CH1 RK0
5717 10:01:31.458469
5718 10:01:31.460996 DATLAT Default: 0xd
5719 10:01:31.464292 0, 0xFFFF, sum = 0
5720 10:01:31.464374 1, 0xFFFF, sum = 0
5721 10:01:31.467741 2, 0xFFFF, sum = 0
5722 10:01:31.467822 3, 0xFFFF, sum = 0
5723 10:01:31.470866 4, 0xFFFF, sum = 0
5724 10:01:31.470946 5, 0xFFFF, sum = 0
5725 10:01:31.474111 6, 0xFFFF, sum = 0
5726 10:01:31.474191 7, 0xFFFF, sum = 0
5727 10:01:31.477686 8, 0xFFFF, sum = 0
5728 10:01:31.477767 9, 0xFFFF, sum = 0
5729 10:01:31.481134 10, 0x0, sum = 1
5730 10:01:31.481215 11, 0x0, sum = 2
5731 10:01:31.484185 12, 0x0, sum = 3
5732 10:01:31.484265 13, 0x0, sum = 4
5733 10:01:31.487706 best_step = 11
5734 10:01:31.487785
5735 10:01:31.487848 ==
5736 10:01:31.490810 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 10:01:31.493808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 10:01:31.493888 ==
5739 10:01:31.493951 RX Vref Scan: 1
5740 10:01:31.497215
5741 10:01:31.497294 RX Vref 0 -> 0, step: 1
5742 10:01:31.497358
5743 10:01:31.500847 RX Delay -61 -> 252, step: 4
5744 10:01:31.500927
5745 10:01:31.504158 Set Vref, RX VrefLevel [Byte0]: 48
5746 10:01:31.507450 [Byte1]: 54
5747 10:01:31.510737
5748 10:01:31.510816 Final RX Vref Byte 0 = 48 to rank0
5749 10:01:31.514495 Final RX Vref Byte 1 = 54 to rank0
5750 10:01:31.517262 Final RX Vref Byte 0 = 48 to rank1
5751 10:01:31.520583 Final RX Vref Byte 1 = 54 to rank1==
5752 10:01:31.524297 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 10:01:31.530581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 10:01:31.530700 ==
5755 10:01:31.530763 DQS Delay:
5756 10:01:31.533435 DQS0 = 0, DQS1 = 0
5757 10:01:31.533514 DQM Delay:
5758 10:01:31.533577 DQM0 = 101, DQM1 = 95
5759 10:01:31.537017 DQ Delay:
5760 10:01:31.540316 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5761 10:01:31.543653 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5762 10:01:31.547109 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =86
5763 10:01:31.550000 DQ12 =102, DQ13 =98, DQ14 =106, DQ15 =104
5764 10:01:31.550083
5765 10:01:31.550146
5766 10:01:31.556596 [DQSOSCAuto] RK0, (LSB)MR18= 0x2010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 411 ps
5767 10:01:31.559867 CH1 RK0: MR19=505, MR18=2010
5768 10:01:31.566494 CH1_RK0: MR19=0x505, MR18=0x2010, DQSOSC=411, MR23=63, INC=64, DEC=42
5769 10:01:31.566575
5770 10:01:31.569763 ----->DramcWriteLeveling(PI) begin...
5771 10:01:31.569844 ==
5772 10:01:31.573337 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 10:01:31.576849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 10:01:31.576930 ==
5775 10:01:31.579908 Write leveling (Byte 0): 26 => 26
5776 10:01:31.582965 Write leveling (Byte 1): 25 => 25
5777 10:01:31.586269 DramcWriteLeveling(PI) end<-----
5778 10:01:31.586348
5779 10:01:31.586410 ==
5780 10:01:31.589601 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 10:01:31.596492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 10:01:31.596572 ==
5783 10:01:31.596636 [Gating] SW mode calibration
5784 10:01:31.606400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5785 10:01:31.609513 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5786 10:01:31.615919 0 14 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5787 10:01:31.619746 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 10:01:31.622842 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 10:01:31.629117 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 10:01:31.632497 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 10:01:31.636062 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 10:01:31.642438 0 14 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 1)
5793 10:01:31.646034 0 14 28 | B1->B0 | 2626 3030 | 0 0 | (0 0) (1 0)
5794 10:01:31.649337 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5795 10:01:31.652904 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 10:01:31.659469 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 10:01:31.662743 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 10:01:31.665883 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 10:01:31.672304 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 10:01:31.676257 0 15 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5801 10:01:31.679067 0 15 28 | B1->B0 | 3a3a 2a2a | 0 0 | (1 1) (0 0)
5802 10:01:31.685967 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5803 10:01:31.689363 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 10:01:31.692714 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 10:01:31.699134 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 10:01:31.702083 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 10:01:31.705372 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 10:01:31.712055 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5809 10:01:31.715398 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5810 10:01:31.718748 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 10:01:31.725334 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 10:01:31.728621 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 10:01:31.732008 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 10:01:31.738318 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 10:01:31.741729 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 10:01:31.744956 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 10:01:31.751533 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 10:01:31.755063 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 10:01:31.758515 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 10:01:31.765392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 10:01:31.768340 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 10:01:31.772005 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 10:01:31.778475 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 10:01:31.781985 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5825 10:01:31.784984 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5826 10:01:31.791322 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 10:01:31.791405 Total UI for P1: 0, mck2ui 16
5828 10:01:31.798183 best dqsien dly found for B0: ( 1, 2, 28)
5829 10:01:31.798264 Total UI for P1: 0, mck2ui 16
5830 10:01:31.804583 best dqsien dly found for B1: ( 1, 2, 26)
5831 10:01:31.808198 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5832 10:01:31.811266 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5833 10:01:31.811347
5834 10:01:31.814961 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5835 10:01:31.817992 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5836 10:01:31.821640 [Gating] SW calibration Done
5837 10:01:31.821722 ==
5838 10:01:31.824322 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 10:01:31.828173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 10:01:31.828273 ==
5841 10:01:31.831153 RX Vref Scan: 0
5842 10:01:31.831234
5843 10:01:31.831317 RX Vref 0 -> 0, step: 1
5844 10:01:31.831395
5845 10:01:31.834995 RX Delay -80 -> 252, step: 8
5846 10:01:31.841024 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5847 10:01:31.844285 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5848 10:01:31.847731 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5849 10:01:31.851181 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5850 10:01:31.854416 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5851 10:01:31.857777 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5852 10:01:31.864256 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5853 10:01:31.867485 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5854 10:01:31.870862 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5855 10:01:31.873778 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5856 10:01:31.877338 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5857 10:01:31.880730 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5858 10:01:31.887049 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5859 10:01:31.890481 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5860 10:01:31.893817 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5861 10:01:31.896886 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5862 10:01:31.896968 ==
5863 10:01:31.900652 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 10:01:31.907222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 10:01:31.907304 ==
5866 10:01:31.907388 DQS Delay:
5867 10:01:31.907466 DQS0 = 0, DQS1 = 0
5868 10:01:31.910137 DQM Delay:
5869 10:01:31.910218 DQM0 = 100, DQM1 = 91
5870 10:01:31.913693 DQ Delay:
5871 10:01:31.917311 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5872 10:01:31.920494 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5873 10:01:31.923479 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5874 10:01:31.926896 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5875 10:01:31.926977
5876 10:01:31.927060
5877 10:01:31.927138 ==
5878 10:01:31.929894 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 10:01:31.933348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 10:01:31.933430 ==
5881 10:01:31.933512
5882 10:01:31.933590
5883 10:01:31.936900 TX Vref Scan disable
5884 10:01:31.940250 == TX Byte 0 ==
5885 10:01:31.943077 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5886 10:01:31.946452 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5887 10:01:31.949572 == TX Byte 1 ==
5888 10:01:31.953407 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5889 10:01:31.956593 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5890 10:01:31.956675 ==
5891 10:01:31.959710 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 10:01:31.963154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 10:01:31.966419 ==
5894 10:01:31.966530
5895 10:01:31.966665
5896 10:01:31.966744 TX Vref Scan disable
5897 10:01:31.969786 == TX Byte 0 ==
5898 10:01:31.973153 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5899 10:01:31.976697 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5900 10:01:31.980074 == TX Byte 1 ==
5901 10:01:31.983534 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5902 10:01:31.986322 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5903 10:01:31.990008
5904 10:01:31.990088 [DATLAT]
5905 10:01:31.990171 Freq=933, CH1 RK1
5906 10:01:31.990250
5907 10:01:31.993297 DATLAT Default: 0xb
5908 10:01:31.993378 0, 0xFFFF, sum = 0
5909 10:01:31.996478 1, 0xFFFF, sum = 0
5910 10:01:31.996561 2, 0xFFFF, sum = 0
5911 10:01:31.999792 3, 0xFFFF, sum = 0
5912 10:01:31.999901 4, 0xFFFF, sum = 0
5913 10:01:32.003249 5, 0xFFFF, sum = 0
5914 10:01:32.006747 6, 0xFFFF, sum = 0
5915 10:01:32.006830 7, 0xFFFF, sum = 0
5916 10:01:32.009558 8, 0xFFFF, sum = 0
5917 10:01:32.009640 9, 0xFFFF, sum = 0
5918 10:01:32.013027 10, 0x0, sum = 1
5919 10:01:32.013110 11, 0x0, sum = 2
5920 10:01:32.016556 12, 0x0, sum = 3
5921 10:01:32.016639 13, 0x0, sum = 4
5922 10:01:32.016723 best_step = 11
5923 10:01:32.016801
5924 10:01:32.020543 ==
5925 10:01:32.023186 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 10:01:32.026568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 10:01:32.026663 ==
5928 10:01:32.026746 RX Vref Scan: 0
5929 10:01:32.026824
5930 10:01:32.029513 RX Vref 0 -> 0, step: 1
5931 10:01:32.029594
5932 10:01:32.032928 RX Delay -61 -> 252, step: 4
5933 10:01:32.039453 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5934 10:01:32.042894 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5935 10:01:32.045779 iDelay=207, Bit 2, Center 92 (7 ~ 178) 172
5936 10:01:32.049478 iDelay=207, Bit 3, Center 100 (19 ~ 182) 164
5937 10:01:32.052331 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5938 10:01:32.056146 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5939 10:01:32.062344 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5940 10:01:32.065845 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5941 10:01:32.068760 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5942 10:01:32.072470 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5943 10:01:32.075774 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5944 10:01:32.082580 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5945 10:01:32.085393 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5946 10:01:32.089297 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5947 10:01:32.092487 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5948 10:01:32.095346 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5949 10:01:32.099042 ==
5950 10:01:32.099123 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 10:01:32.105497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 10:01:32.105580 ==
5953 10:01:32.105663 DQS Delay:
5954 10:01:32.108733 DQS0 = 0, DQS1 = 0
5955 10:01:32.108845 DQM Delay:
5956 10:01:32.111880 DQM0 = 102, DQM1 = 93
5957 10:01:32.111961 DQ Delay:
5958 10:01:32.115333 DQ0 =106, DQ1 =94, DQ2 =92, DQ3 =100
5959 10:01:32.118468 DQ4 =100, DQ5 =110, DQ6 =116, DQ7 =98
5960 10:01:32.122248 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
5961 10:01:32.125263 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5962 10:01:32.125345
5963 10:01:32.125427
5964 10:01:32.135220 [DQSOSCAuto] RK1, (LSB)MR18= 0xe07, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 417 ps
5965 10:01:32.135329 CH1 RK1: MR19=505, MR18=E07
5966 10:01:32.141700 CH1_RK1: MR19=0x505, MR18=0xE07, DQSOSC=417, MR23=63, INC=62, DEC=41
5967 10:01:32.145262 [RxdqsGatingPostProcess] freq 933
5968 10:01:32.151900 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5969 10:01:32.155130 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 10:01:32.157965 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 10:01:32.161471 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 10:01:32.165031 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 10:01:32.167965 best DQS0 dly(2T, 0.5T) = (0, 10)
5974 10:01:32.168047 best DQS1 dly(2T, 0.5T) = (0, 10)
5975 10:01:32.171194 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5976 10:01:32.174850 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5977 10:01:32.178279 Pre-setting of DQS Precalculation
5978 10:01:32.184983 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5979 10:01:32.191457 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5980 10:01:32.198218 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5981 10:01:32.198300
5982 10:01:32.198398
5983 10:01:32.201357 [Calibration Summary] 1866 Mbps
5984 10:01:32.201439 CH 0, Rank 0
5985 10:01:32.204738 SW Impedance : PASS
5986 10:01:32.208058 DUTY Scan : NO K
5987 10:01:32.208140 ZQ Calibration : PASS
5988 10:01:32.211446 Jitter Meter : NO K
5989 10:01:32.214543 CBT Training : PASS
5990 10:01:32.214688 Write leveling : PASS
5991 10:01:32.217942 RX DQS gating : PASS
5992 10:01:32.221062 RX DQ/DQS(RDDQC) : PASS
5993 10:01:32.221141 TX DQ/DQS : PASS
5994 10:01:32.224160 RX DATLAT : PASS
5995 10:01:32.227965 RX DQ/DQS(Engine): PASS
5996 10:01:32.228044 TX OE : NO K
5997 10:01:32.230992 All Pass.
5998 10:01:32.231070
5999 10:01:32.231131 CH 0, Rank 1
6000 10:01:32.234114 SW Impedance : PASS
6001 10:01:32.234192 DUTY Scan : NO K
6002 10:01:32.237389 ZQ Calibration : PASS
6003 10:01:32.240742 Jitter Meter : NO K
6004 10:01:32.240821 CBT Training : PASS
6005 10:01:32.243964 Write leveling : PASS
6006 10:01:32.247595 RX DQS gating : PASS
6007 10:01:32.247674 RX DQ/DQS(RDDQC) : PASS
6008 10:01:32.250944 TX DQ/DQS : PASS
6009 10:01:32.254438 RX DATLAT : PASS
6010 10:01:32.254543 RX DQ/DQS(Engine): PASS
6011 10:01:32.257604 TX OE : NO K
6012 10:01:32.257684 All Pass.
6013 10:01:32.257746
6014 10:01:32.260992 CH 1, Rank 0
6015 10:01:32.261071 SW Impedance : PASS
6016 10:01:32.264387 DUTY Scan : NO K
6017 10:01:32.264465 ZQ Calibration : PASS
6018 10:01:32.267448 Jitter Meter : NO K
6019 10:01:32.271053 CBT Training : PASS
6020 10:01:32.271132 Write leveling : PASS
6021 10:01:32.274109 RX DQS gating : PASS
6022 10:01:32.277324 RX DQ/DQS(RDDQC) : PASS
6023 10:01:32.277402 TX DQ/DQS : PASS
6024 10:01:32.280567 RX DATLAT : PASS
6025 10:01:32.283809 RX DQ/DQS(Engine): PASS
6026 10:01:32.283888 TX OE : NO K
6027 10:01:32.287497 All Pass.
6028 10:01:32.287576
6029 10:01:32.287639 CH 1, Rank 1
6030 10:01:32.290528 SW Impedance : PASS
6031 10:01:32.290613 DUTY Scan : NO K
6032 10:01:32.293456 ZQ Calibration : PASS
6033 10:01:32.297086 Jitter Meter : NO K
6034 10:01:32.297164 CBT Training : PASS
6035 10:01:32.300498 Write leveling : PASS
6036 10:01:32.303699 RX DQS gating : PASS
6037 10:01:32.303778 RX DQ/DQS(RDDQC) : PASS
6038 10:01:32.306940 TX DQ/DQS : PASS
6039 10:01:32.310552 RX DATLAT : PASS
6040 10:01:32.310649 RX DQ/DQS(Engine): PASS
6041 10:01:32.313367 TX OE : NO K
6042 10:01:32.313445 All Pass.
6043 10:01:32.313507
6044 10:01:32.316864 DramC Write-DBI off
6045 10:01:32.320722 PER_BANK_REFRESH: Hybrid Mode
6046 10:01:32.320801 TX_TRACKING: ON
6047 10:01:32.329905 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6048 10:01:32.333382 [FAST_K] Save calibration result to emmc
6049 10:01:32.336309 dramc_set_vcore_voltage set vcore to 650000
6050 10:01:32.339721 Read voltage for 400, 6
6051 10:01:32.339800 Vio18 = 0
6052 10:01:32.339863 Vcore = 650000
6053 10:01:32.343071 Vdram = 0
6054 10:01:32.343149 Vddq = 0
6055 10:01:32.343211 Vmddr = 0
6056 10:01:32.349476 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6057 10:01:32.353011 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6058 10:01:32.356665 MEM_TYPE=3, freq_sel=20
6059 10:01:32.359554 sv_algorithm_assistance_LP4_800
6060 10:01:32.362853 ============ PULL DRAM RESETB DOWN ============
6061 10:01:32.366320 ========== PULL DRAM RESETB DOWN end =========
6062 10:01:32.372531 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6063 10:01:32.375987 ===================================
6064 10:01:32.379373 LPDDR4 DRAM CONFIGURATION
6065 10:01:32.382575 ===================================
6066 10:01:32.382692 EX_ROW_EN[0] = 0x0
6067 10:01:32.386212 EX_ROW_EN[1] = 0x0
6068 10:01:32.386290 LP4Y_EN = 0x0
6069 10:01:32.389284 WORK_FSP = 0x0
6070 10:01:32.389362 WL = 0x2
6071 10:01:32.392515 RL = 0x2
6072 10:01:32.392620 BL = 0x2
6073 10:01:32.396023 RPST = 0x0
6074 10:01:32.396102 RD_PRE = 0x0
6075 10:01:32.399415 WR_PRE = 0x1
6076 10:01:32.399493 WR_PST = 0x0
6077 10:01:32.402485 DBI_WR = 0x0
6078 10:01:32.402563 DBI_RD = 0x0
6079 10:01:32.405760 OTF = 0x1
6080 10:01:32.409408 ===================================
6081 10:01:32.412384 ===================================
6082 10:01:32.412464 ANA top config
6083 10:01:32.415770 ===================================
6084 10:01:32.418939 DLL_ASYNC_EN = 0
6085 10:01:32.422269 ALL_SLAVE_EN = 1
6086 10:01:32.425396 NEW_RANK_MODE = 1
6087 10:01:32.428885 DLL_IDLE_MODE = 1
6088 10:01:32.428963 LP45_APHY_COMB_EN = 1
6089 10:01:32.432599 TX_ODT_DIS = 1
6090 10:01:32.435633 NEW_8X_MODE = 1
6091 10:01:32.438829 ===================================
6092 10:01:32.442308 ===================================
6093 10:01:32.445323 data_rate = 800
6094 10:01:32.448663 CKR = 1
6095 10:01:32.448742 DQ_P2S_RATIO = 4
6096 10:01:32.452346 ===================================
6097 10:01:32.455401 CA_P2S_RATIO = 4
6098 10:01:32.458966 DQ_CA_OPEN = 0
6099 10:01:32.462173 DQ_SEMI_OPEN = 1
6100 10:01:32.465159 CA_SEMI_OPEN = 1
6101 10:01:32.468516 CA_FULL_RATE = 0
6102 10:01:32.468595 DQ_CKDIV4_EN = 0
6103 10:01:32.472106 CA_CKDIV4_EN = 1
6104 10:01:32.475014 CA_PREDIV_EN = 0
6105 10:01:32.478323 PH8_DLY = 0
6106 10:01:32.481567 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6107 10:01:32.484893 DQ_AAMCK_DIV = 0
6108 10:01:32.484997 CA_AAMCK_DIV = 0
6109 10:01:32.488154 CA_ADMCK_DIV = 4
6110 10:01:32.491933 DQ_TRACK_CA_EN = 0
6111 10:01:32.494913 CA_PICK = 800
6112 10:01:32.499183 CA_MCKIO = 400
6113 10:01:32.501533 MCKIO_SEMI = 400
6114 10:01:32.505030 PLL_FREQ = 3016
6115 10:01:32.508160 DQ_UI_PI_RATIO = 32
6116 10:01:32.508241 CA_UI_PI_RATIO = 32
6117 10:01:32.511356 ===================================
6118 10:01:32.514760 ===================================
6119 10:01:32.518349 memory_type:LPDDR4
6120 10:01:32.521571 GP_NUM : 10
6121 10:01:32.521649 SRAM_EN : 1
6122 10:01:32.524399 MD32_EN : 0
6123 10:01:32.527704 ===================================
6124 10:01:32.531329 [ANA_INIT] >>>>>>>>>>>>>>
6125 10:01:32.534766 <<<<<< [CONFIGURE PHASE]: ANA_TX
6126 10:01:32.538077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6127 10:01:32.541072 ===================================
6128 10:01:32.541151 data_rate = 800,PCW = 0X7400
6129 10:01:32.544430 ===================================
6130 10:01:32.547633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6131 10:01:32.554412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 10:01:32.567723 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6133 10:01:32.570526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6134 10:01:32.574076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6135 10:01:32.577412 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6136 10:01:32.580965 [ANA_INIT] flow start
6137 10:01:32.581044 [ANA_INIT] PLL >>>>>>>>
6138 10:01:32.584209 [ANA_INIT] PLL <<<<<<<<
6139 10:01:32.587386 [ANA_INIT] MIDPI >>>>>>>>
6140 10:01:32.590386 [ANA_INIT] MIDPI <<<<<<<<
6141 10:01:32.590465 [ANA_INIT] DLL >>>>>>>>
6142 10:01:32.593731 [ANA_INIT] flow end
6143 10:01:32.597183 ============ LP4 DIFF to SE enter ============
6144 10:01:32.600355 ============ LP4 DIFF to SE exit ============
6145 10:01:32.603902 [ANA_INIT] <<<<<<<<<<<<<
6146 10:01:32.607230 [Flow] Enable top DCM control >>>>>
6147 10:01:32.610510 [Flow] Enable top DCM control <<<<<
6148 10:01:32.613499 Enable DLL master slave shuffle
6149 10:01:32.620810 ==============================================================
6150 10:01:32.620889 Gating Mode config
6151 10:01:32.626942 ==============================================================
6152 10:01:32.627021 Config description:
6153 10:01:32.636803 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6154 10:01:32.643369 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6155 10:01:32.650207 SELPH_MODE 0: By rank 1: By Phase
6156 10:01:32.653636 ==============================================================
6157 10:01:32.656855 GAT_TRACK_EN = 0
6158 10:01:32.659742 RX_GATING_MODE = 2
6159 10:01:32.663445 RX_GATING_TRACK_MODE = 2
6160 10:01:32.666558 SELPH_MODE = 1
6161 10:01:32.669574 PICG_EARLY_EN = 1
6162 10:01:32.673112 VALID_LAT_VALUE = 1
6163 10:01:32.679333 ==============================================================
6164 10:01:32.682763 Enter into Gating configuration >>>>
6165 10:01:32.685984 Exit from Gating configuration <<<<
6166 10:01:32.689438 Enter into DVFS_PRE_config >>>>>
6167 10:01:32.699239 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6168 10:01:32.702731 Exit from DVFS_PRE_config <<<<<
6169 10:01:32.706314 Enter into PICG configuration >>>>
6170 10:01:32.709366 Exit from PICG configuration <<<<
6171 10:01:32.712775 [RX_INPUT] configuration >>>>>
6172 10:01:32.712854 [RX_INPUT] configuration <<<<<
6173 10:01:32.719309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6174 10:01:32.725800 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6175 10:01:32.732569 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 10:01:32.735871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 10:01:32.742733 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 10:01:32.748882 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 10:01:32.752327 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6180 10:01:32.755705 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6181 10:01:32.762364 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6182 10:01:32.765691 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6183 10:01:32.768748 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6184 10:01:32.775810 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6185 10:01:32.778714 ===================================
6186 10:01:32.778793 LPDDR4 DRAM CONFIGURATION
6187 10:01:32.782544 ===================================
6188 10:01:32.785141 EX_ROW_EN[0] = 0x0
6189 10:01:32.788474 EX_ROW_EN[1] = 0x0
6190 10:01:32.788556 LP4Y_EN = 0x0
6191 10:01:32.791833 WORK_FSP = 0x0
6192 10:01:32.791912 WL = 0x2
6193 10:01:32.795394 RL = 0x2
6194 10:01:32.795472 BL = 0x2
6195 10:01:32.798511 RPST = 0x0
6196 10:01:32.798648 RD_PRE = 0x0
6197 10:01:32.801956 WR_PRE = 0x1
6198 10:01:32.802034 WR_PST = 0x0
6199 10:01:32.805317 DBI_WR = 0x0
6200 10:01:32.805396 DBI_RD = 0x0
6201 10:01:32.808488 OTF = 0x1
6202 10:01:32.811591 ===================================
6203 10:01:32.815032 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6204 10:01:32.818333 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6205 10:01:32.825021 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 10:01:32.828211 ===================================
6207 10:01:32.828291 LPDDR4 DRAM CONFIGURATION
6208 10:01:32.831622 ===================================
6209 10:01:32.834553 EX_ROW_EN[0] = 0x10
6210 10:01:32.837936 EX_ROW_EN[1] = 0x0
6211 10:01:32.838015 LP4Y_EN = 0x0
6212 10:01:32.841355 WORK_FSP = 0x0
6213 10:01:32.841433 WL = 0x2
6214 10:01:32.844786 RL = 0x2
6215 10:01:32.844865 BL = 0x2
6216 10:01:32.848137 RPST = 0x0
6217 10:01:32.848216 RD_PRE = 0x0
6218 10:01:32.851231 WR_PRE = 0x1
6219 10:01:32.851309 WR_PST = 0x0
6220 10:01:32.854190 DBI_WR = 0x0
6221 10:01:32.854267 DBI_RD = 0x0
6222 10:01:32.857941 OTF = 0x1
6223 10:01:32.861059 ===================================
6224 10:01:32.867755 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6225 10:01:32.870775 nWR fixed to 30
6226 10:01:32.873953 [ModeRegInit_LP4] CH0 RK0
6227 10:01:32.874032 [ModeRegInit_LP4] CH0 RK1
6228 10:01:32.877450 [ModeRegInit_LP4] CH1 RK0
6229 10:01:32.881122 [ModeRegInit_LP4] CH1 RK1
6230 10:01:32.881201 match AC timing 19
6231 10:01:32.887582 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6232 10:01:32.890847 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6233 10:01:32.893884 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6234 10:01:32.900722 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6235 10:01:32.904090 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6236 10:01:32.904170 ==
6237 10:01:32.907151 Dram Type= 6, Freq= 0, CH_0, rank 0
6238 10:01:32.910168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6239 10:01:32.910248 ==
6240 10:01:32.916903 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6241 10:01:32.923371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6242 10:01:32.926623 [CA 0] Center 36 (8~64) winsize 57
6243 10:01:32.929981 [CA 1] Center 36 (8~64) winsize 57
6244 10:01:32.933561 [CA 2] Center 36 (8~64) winsize 57
6245 10:01:32.936644 [CA 3] Center 36 (8~64) winsize 57
6246 10:01:32.939999 [CA 4] Center 36 (8~64) winsize 57
6247 10:01:32.943170 [CA 5] Center 36 (8~64) winsize 57
6248 10:01:32.943249
6249 10:01:32.946479 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6250 10:01:32.946583
6251 10:01:32.949611 [CATrainingPosCal] consider 1 rank data
6252 10:01:32.952846 u2DelayCellTimex100 = 270/100 ps
6253 10:01:32.956392 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 10:01:32.959812 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 10:01:32.963374 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 10:01:32.966705 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 10:01:32.969809 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 10:01:32.972986 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 10:01:32.973065
6260 10:01:32.979633 CA PerBit enable=1, Macro0, CA PI delay=36
6261 10:01:32.979711
6262 10:01:32.979774 [CBTSetCACLKResult] CA Dly = 36
6263 10:01:32.982403 CS Dly: 1 (0~32)
6264 10:01:32.982481 ==
6265 10:01:32.986352 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 10:01:32.989057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 10:01:32.989137 ==
6268 10:01:32.995877 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6269 10:01:33.002377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6270 10:01:33.005809 [CA 0] Center 36 (8~64) winsize 57
6271 10:01:33.009276 [CA 1] Center 36 (8~64) winsize 57
6272 10:01:33.012103 [CA 2] Center 36 (8~64) winsize 57
6273 10:01:33.015750 [CA 3] Center 36 (8~64) winsize 57
6274 10:01:33.018512 [CA 4] Center 36 (8~64) winsize 57
6275 10:01:33.018652 [CA 5] Center 36 (8~64) winsize 57
6276 10:01:33.022275
6277 10:01:33.025829 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6278 10:01:33.025907
6279 10:01:33.028622 [CATrainingPosCal] consider 2 rank data
6280 10:01:33.031926 u2DelayCellTimex100 = 270/100 ps
6281 10:01:33.035380 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 10:01:33.038699 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 10:01:33.041861 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 10:01:33.045277 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 10:01:33.048451 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 10:01:33.051665 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 10:01:33.051744
6288 10:01:33.055094 CA PerBit enable=1, Macro0, CA PI delay=36
6289 10:01:33.055174
6290 10:01:33.058561 [CBTSetCACLKResult] CA Dly = 36
6291 10:01:33.062138 CS Dly: 1 (0~32)
6292 10:01:33.062216
6293 10:01:33.065700 ----->DramcWriteLeveling(PI) begin...
6294 10:01:33.065780 ==
6295 10:01:33.068566 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 10:01:33.071750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 10:01:33.071829 ==
6298 10:01:33.075591 Write leveling (Byte 0): 40 => 8
6299 10:01:33.078780 Write leveling (Byte 1): 32 => 0
6300 10:01:33.081793 DramcWriteLeveling(PI) end<-----
6301 10:01:33.081871
6302 10:01:33.081932 ==
6303 10:01:33.085364 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 10:01:33.088740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 10:01:33.088819 ==
6306 10:01:33.091993 [Gating] SW mode calibration
6307 10:01:33.098248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6308 10:01:33.105311 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6309 10:01:33.108347 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 10:01:33.114930 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6311 10:01:33.118021 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 10:01:33.121452 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 10:01:33.128625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 10:01:33.131197 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 10:01:33.134839 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 10:01:33.141212 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 10:01:33.144649 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 10:01:33.147848 Total UI for P1: 0, mck2ui 16
6319 10:01:33.151313 best dqsien dly found for B0: ( 0, 14, 24)
6320 10:01:33.154642 Total UI for P1: 0, mck2ui 16
6321 10:01:33.157746 best dqsien dly found for B1: ( 0, 14, 24)
6322 10:01:33.161302 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6323 10:01:33.164665 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6324 10:01:33.164743
6325 10:01:33.167576 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 10:01:33.171209 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6327 10:01:33.174525 [Gating] SW calibration Done
6328 10:01:33.174608 ==
6329 10:01:33.177938 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 10:01:33.180844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 10:01:33.183934 ==
6332 10:01:33.184012 RX Vref Scan: 0
6333 10:01:33.184073
6334 10:01:33.187583 RX Vref 0 -> 0, step: 1
6335 10:01:33.187661
6336 10:01:33.190705 RX Delay -410 -> 252, step: 16
6337 10:01:33.193992 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6338 10:01:33.197432 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6339 10:01:33.200411 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6340 10:01:33.207323 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6341 10:01:33.210449 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6342 10:01:33.213870 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6343 10:01:33.217413 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6344 10:01:33.223985 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6345 10:01:33.227123 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6346 10:01:33.230742 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6347 10:01:33.233388 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6348 10:01:33.240212 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6349 10:01:33.243654 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6350 10:01:33.246978 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6351 10:01:33.253523 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6352 10:01:33.256800 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6353 10:01:33.256878 ==
6354 10:01:33.259758 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 10:01:33.263395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 10:01:33.263475 ==
6357 10:01:33.266343 DQS Delay:
6358 10:01:33.266422 DQS0 = 43, DQS1 = 59
6359 10:01:33.269855 DQM Delay:
6360 10:01:33.269934 DQM0 = 10, DQM1 = 12
6361 10:01:33.269997 DQ Delay:
6362 10:01:33.273353 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6363 10:01:33.276442 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6364 10:01:33.279330 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6365 10:01:33.282828 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6366 10:01:33.282907
6367 10:01:33.282969
6368 10:01:33.283027 ==
6369 10:01:33.286018 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 10:01:33.293025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 10:01:33.293104 ==
6372 10:01:33.293166
6373 10:01:33.293222
6374 10:01:33.293276 TX Vref Scan disable
6375 10:01:33.295987 == TX Byte 0 ==
6376 10:01:33.299361 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 10:01:33.302885 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 10:01:33.306406 == TX Byte 1 ==
6379 10:01:33.309521 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6380 10:01:33.312890 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6381 10:01:33.312969 ==
6382 10:01:33.315851 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 10:01:33.322623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 10:01:33.322703 ==
6385 10:01:33.322765
6386 10:01:33.322822
6387 10:01:33.326060 TX Vref Scan disable
6388 10:01:33.326139 == TX Byte 0 ==
6389 10:01:33.329153 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 10:01:33.335883 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 10:01:33.335962 == TX Byte 1 ==
6392 10:01:33.339016 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6393 10:01:33.345319 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6394 10:01:33.345399
6395 10:01:33.345461 [DATLAT]
6396 10:01:33.345519 Freq=400, CH0 RK0
6397 10:01:33.345575
6398 10:01:33.348695 DATLAT Default: 0xf
6399 10:01:33.348774 0, 0xFFFF, sum = 0
6400 10:01:33.352058 1, 0xFFFF, sum = 0
6401 10:01:33.355596 2, 0xFFFF, sum = 0
6402 10:01:33.355675 3, 0xFFFF, sum = 0
6403 10:01:33.359067 4, 0xFFFF, sum = 0
6404 10:01:33.359147 5, 0xFFFF, sum = 0
6405 10:01:33.361897 6, 0xFFFF, sum = 0
6406 10:01:33.361977 7, 0xFFFF, sum = 0
6407 10:01:33.365441 8, 0xFFFF, sum = 0
6408 10:01:33.365520 9, 0xFFFF, sum = 0
6409 10:01:33.368572 10, 0xFFFF, sum = 0
6410 10:01:33.368651 11, 0xFFFF, sum = 0
6411 10:01:33.372473 12, 0xFFFF, sum = 0
6412 10:01:33.372553 13, 0x0, sum = 1
6413 10:01:33.375599 14, 0x0, sum = 2
6414 10:01:33.375679 15, 0x0, sum = 3
6415 10:01:33.379088 16, 0x0, sum = 4
6416 10:01:33.379168 best_step = 14
6417 10:01:33.379230
6418 10:01:33.379288 ==
6419 10:01:33.381966 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 10:01:33.388384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 10:01:33.388463 ==
6422 10:01:33.388526 RX Vref Scan: 1
6423 10:01:33.388584
6424 10:01:33.391629 RX Vref 0 -> 0, step: 1
6425 10:01:33.391707
6426 10:01:33.395098 RX Delay -359 -> 252, step: 8
6427 10:01:33.395176
6428 10:01:33.398172 Set Vref, RX VrefLevel [Byte0]: 61
6429 10:01:33.401725 [Byte1]: 47
6430 10:01:33.401803
6431 10:01:33.405252 Final RX Vref Byte 0 = 61 to rank0
6432 10:01:33.408529 Final RX Vref Byte 1 = 47 to rank0
6433 10:01:33.411851 Final RX Vref Byte 0 = 61 to rank1
6434 10:01:33.415106 Final RX Vref Byte 1 = 47 to rank1==
6435 10:01:33.418174 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 10:01:33.421668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 10:01:33.424983 ==
6438 10:01:33.425062 DQS Delay:
6439 10:01:33.425124 DQS0 = 44, DQS1 = 60
6440 10:01:33.428357 DQM Delay:
6441 10:01:33.428435 DQM0 = 8, DQM1 = 13
6442 10:01:33.431241 DQ Delay:
6443 10:01:33.431319 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6444 10:01:33.434962 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6445 10:01:33.438266 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6446 10:01:33.441314 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6447 10:01:33.441429
6448 10:01:33.441495
6449 10:01:33.451525 [DQSOSCAuto] RK0, (LSB)MR18= 0xc78a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6450 10:01:33.454813 CH0 RK0: MR19=C0C, MR18=C78A
6451 10:01:33.461176 CH0_RK0: MR19=0xC0C, MR18=0xC78A, DQSOSC=385, MR23=63, INC=398, DEC=265
6452 10:01:33.461256 ==
6453 10:01:33.464570 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 10:01:33.468053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 10:01:33.468132 ==
6456 10:01:33.471182 [Gating] SW mode calibration
6457 10:01:33.477429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6458 10:01:33.480800 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6459 10:01:33.487308 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 10:01:33.491052 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6461 10:01:33.494565 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 10:01:33.500582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 10:01:33.503827 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 10:01:33.507185 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 10:01:33.514168 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 10:01:33.517593 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 10:01:33.520715 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 10:01:33.524382 Total UI for P1: 0, mck2ui 16
6469 10:01:33.527191 best dqsien dly found for B0: ( 0, 14, 24)
6470 10:01:33.530403 Total UI for P1: 0, mck2ui 16
6471 10:01:33.533773 best dqsien dly found for B1: ( 0, 14, 24)
6472 10:01:33.537169 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6473 10:01:33.540754 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6474 10:01:33.544063
6475 10:01:33.546953 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 10:01:33.550213 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6477 10:01:33.553811 [Gating] SW calibration Done
6478 10:01:33.553917 ==
6479 10:01:33.556751 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 10:01:33.560305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 10:01:33.560388 ==
6482 10:01:33.563515 RX Vref Scan: 0
6483 10:01:33.563596
6484 10:01:33.563679 RX Vref 0 -> 0, step: 1
6485 10:01:33.563757
6486 10:01:33.566971 RX Delay -410 -> 252, step: 16
6487 10:01:33.570281 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6488 10:01:33.576870 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6489 10:01:33.580635 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6490 10:01:33.583406 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6491 10:01:33.586729 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6492 10:01:33.593543 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6493 10:01:33.596624 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6494 10:01:33.600063 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6495 10:01:33.606193 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6496 10:01:33.610027 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6497 10:01:33.612851 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6498 10:01:33.616262 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6499 10:01:33.622862 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6500 10:01:33.626391 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6501 10:01:33.629324 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6502 10:01:33.632670 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6503 10:01:33.636102 ==
6504 10:01:33.639508 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 10:01:33.642528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 10:01:33.642688 ==
6507 10:01:33.642773 DQS Delay:
6508 10:01:33.646143 DQS0 = 43, DQS1 = 51
6509 10:01:33.646224 DQM Delay:
6510 10:01:33.649048 DQM0 = 10, DQM1 = 9
6511 10:01:33.649154 DQ Delay:
6512 10:01:33.652893 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6513 10:01:33.655957 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6514 10:01:33.659262 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6515 10:01:33.662302 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6516 10:01:33.662383
6517 10:01:33.662486
6518 10:01:33.662582 ==
6519 10:01:33.665594 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 10:01:33.669108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 10:01:33.669189 ==
6522 10:01:33.669273
6523 10:01:33.669350
6524 10:01:33.672093 TX Vref Scan disable
6525 10:01:33.672174 == TX Byte 0 ==
6526 10:01:33.678790 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6527 10:01:33.682486 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6528 10:01:33.682599 == TX Byte 1 ==
6529 10:01:33.688590 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6530 10:01:33.691856 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6531 10:01:33.691937 ==
6532 10:01:33.695312 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 10:01:33.698578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 10:01:33.698670 ==
6535 10:01:33.698753
6536 10:01:33.698831
6537 10:01:33.701711 TX Vref Scan disable
6538 10:01:33.701792 == TX Byte 0 ==
6539 10:01:33.708116 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6540 10:01:33.711487 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6541 10:01:33.711569 == TX Byte 1 ==
6542 10:01:33.718711 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6543 10:01:33.721568 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6544 10:01:33.721673
6545 10:01:33.721773 [DATLAT]
6546 10:01:33.725053 Freq=400, CH0 RK1
6547 10:01:33.725135
6548 10:01:33.725218 DATLAT Default: 0xe
6549 10:01:33.728267 0, 0xFFFF, sum = 0
6550 10:01:33.728370 1, 0xFFFF, sum = 0
6551 10:01:33.731235 2, 0xFFFF, sum = 0
6552 10:01:33.731343 3, 0xFFFF, sum = 0
6553 10:01:33.734694 4, 0xFFFF, sum = 0
6554 10:01:33.734793 5, 0xFFFF, sum = 0
6555 10:01:33.737930 6, 0xFFFF, sum = 0
6556 10:01:33.741361 7, 0xFFFF, sum = 0
6557 10:01:33.741442 8, 0xFFFF, sum = 0
6558 10:01:33.744747 9, 0xFFFF, sum = 0
6559 10:01:33.744828 10, 0xFFFF, sum = 0
6560 10:01:33.748131 11, 0xFFFF, sum = 0
6561 10:01:33.748211 12, 0xFFFF, sum = 0
6562 10:01:33.751558 13, 0x0, sum = 1
6563 10:01:33.751665 14, 0x0, sum = 2
6564 10:01:33.754707 15, 0x0, sum = 3
6565 10:01:33.754789 16, 0x0, sum = 4
6566 10:01:33.754854 best_step = 14
6567 10:01:33.757832
6568 10:01:33.757912 ==
6569 10:01:33.761567 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 10:01:33.764512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 10:01:33.764596 ==
6572 10:01:33.764661 RX Vref Scan: 0
6573 10:01:33.764720
6574 10:01:33.767782 RX Vref 0 -> 0, step: 1
6575 10:01:33.767862
6576 10:01:33.771174 RX Delay -343 -> 252, step: 8
6577 10:01:33.778214 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6578 10:01:33.781679 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6579 10:01:33.784912 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6580 10:01:33.791554 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6581 10:01:33.795097 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6582 10:01:33.798576 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6583 10:01:33.801563 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6584 10:01:33.804957 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6585 10:01:33.811473 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6586 10:01:33.814831 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6587 10:01:33.818164 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6588 10:01:33.824416 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6589 10:01:33.828035 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6590 10:01:33.831262 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6591 10:01:33.834729 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6592 10:01:33.841470 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6593 10:01:33.841550 ==
6594 10:01:33.844646 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 10:01:33.847940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 10:01:33.848058 ==
6597 10:01:33.848162 DQS Delay:
6598 10:01:33.851599 DQS0 = 44, DQS1 = 56
6599 10:01:33.851677 DQM Delay:
6600 10:01:33.854565 DQM0 = 8, DQM1 = 12
6601 10:01:33.854703 DQ Delay:
6602 10:01:33.857730 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6603 10:01:33.861084 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6604 10:01:33.864299 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6605 10:01:33.867826 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6606 10:01:33.867980
6607 10:01:33.868093
6608 10:01:33.874626 [DQSOSCAuto] RK1, (LSB)MR18= 0xb943, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6609 10:01:33.877585 CH0 RK1: MR19=C0C, MR18=B943
6610 10:01:33.883975 CH0_RK1: MR19=0xC0C, MR18=0xB943, DQSOSC=386, MR23=63, INC=396, DEC=264
6611 10:01:33.887373 [RxdqsGatingPostProcess] freq 400
6612 10:01:33.894488 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6613 10:01:33.897397 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 10:01:33.901155 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 10:01:33.901419 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 10:01:33.904607 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 10:01:33.907679 best DQS0 dly(2T, 0.5T) = (0, 10)
6618 10:01:33.911275 best DQS1 dly(2T, 0.5T) = (0, 10)
6619 10:01:33.914654 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6620 10:01:33.917356 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6621 10:01:33.920563 Pre-setting of DQS Precalculation
6622 10:01:33.927606 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6623 10:01:33.928169 ==
6624 10:01:33.930547 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 10:01:33.934360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 10:01:33.934978 ==
6627 10:01:33.940842 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6628 10:01:33.947112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6629 10:01:33.950183 [CA 0] Center 36 (8~64) winsize 57
6630 10:01:33.950795 [CA 1] Center 36 (8~64) winsize 57
6631 10:01:33.953810 [CA 2] Center 36 (8~64) winsize 57
6632 10:01:33.957307 [CA 3] Center 36 (8~64) winsize 57
6633 10:01:33.960666 [CA 4] Center 36 (8~64) winsize 57
6634 10:01:33.963792 [CA 5] Center 36 (8~64) winsize 57
6635 10:01:33.964435
6636 10:01:33.967144 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6637 10:01:33.967647
6638 10:01:33.973612 [CATrainingPosCal] consider 1 rank data
6639 10:01:33.974176 u2DelayCellTimex100 = 270/100 ps
6640 10:01:33.980223 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 10:01:33.983806 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 10:01:33.986910 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 10:01:33.990379 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 10:01:33.993722 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 10:01:33.997093 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 10:01:33.997659
6647 10:01:34.000094 CA PerBit enable=1, Macro0, CA PI delay=36
6648 10:01:34.000659
6649 10:01:34.003186 [CBTSetCACLKResult] CA Dly = 36
6650 10:01:34.006623 CS Dly: 1 (0~32)
6651 10:01:34.007237 ==
6652 10:01:34.009838 Dram Type= 6, Freq= 0, CH_1, rank 1
6653 10:01:34.013380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 10:01:34.013946 ==
6655 10:01:34.019928 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6656 10:01:34.023036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6657 10:01:34.026966 [CA 0] Center 36 (8~64) winsize 57
6658 10:01:34.029973 [CA 1] Center 36 (8~64) winsize 57
6659 10:01:34.032558 [CA 2] Center 36 (8~64) winsize 57
6660 10:01:34.036429 [CA 3] Center 36 (8~64) winsize 57
6661 10:01:34.039274 [CA 4] Center 36 (8~64) winsize 57
6662 10:01:34.042827 [CA 5] Center 36 (8~64) winsize 57
6663 10:01:34.043340
6664 10:01:34.046087 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6665 10:01:34.046641
6666 10:01:34.049187 [CATrainingPosCal] consider 2 rank data
6667 10:01:34.053032 u2DelayCellTimex100 = 270/100 ps
6668 10:01:34.055743 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 10:01:34.059215 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 10:01:34.066256 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 10:01:34.069737 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 10:01:34.072394 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 10:01:34.076210 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 10:01:34.076760
6675 10:01:34.078901 CA PerBit enable=1, Macro0, CA PI delay=36
6676 10:01:34.079369
6677 10:01:34.082903 [CBTSetCACLKResult] CA Dly = 36
6678 10:01:34.083373 CS Dly: 1 (0~32)
6679 10:01:34.085472
6680 10:01:34.089268 ----->DramcWriteLeveling(PI) begin...
6681 10:01:34.089816 ==
6682 10:01:34.092363 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 10:01:34.095600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 10:01:34.096114 ==
6685 10:01:34.099066 Write leveling (Byte 0): 40 => 8
6686 10:01:34.102243 Write leveling (Byte 1): 40 => 8
6687 10:01:34.106079 DramcWriteLeveling(PI) end<-----
6688 10:01:34.106714
6689 10:01:34.107095 ==
6690 10:01:34.108935 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 10:01:34.112139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 10:01:34.112593 ==
6693 10:01:34.115846 [Gating] SW mode calibration
6694 10:01:34.122065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6695 10:01:34.129238 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6696 10:01:34.131794 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 10:01:34.135223 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6698 10:01:34.141693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 10:01:34.144874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 10:01:34.148074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 10:01:34.155178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 10:01:34.158240 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 10:01:34.161758 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 10:01:34.168950 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 10:01:34.169495 Total UI for P1: 0, mck2ui 16
6706 10:01:34.175118 best dqsien dly found for B0: ( 0, 14, 24)
6707 10:01:34.175661 Total UI for P1: 0, mck2ui 16
6708 10:01:34.181472 best dqsien dly found for B1: ( 0, 14, 24)
6709 10:01:34.185013 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6710 10:01:34.188687 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6711 10:01:34.189256
6712 10:01:34.191283 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 10:01:34.194769 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6714 10:01:34.197985 [Gating] SW calibration Done
6715 10:01:34.198545 ==
6716 10:01:34.201259 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 10:01:34.204818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 10:01:34.205334 ==
6719 10:01:34.207841 RX Vref Scan: 0
6720 10:01:34.208297
6721 10:01:34.208658 RX Vref 0 -> 0, step: 1
6722 10:01:34.208998
6723 10:01:34.210892 RX Delay -410 -> 252, step: 16
6724 10:01:34.217937 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6725 10:01:34.220772 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6726 10:01:34.224195 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6727 10:01:34.227564 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6728 10:01:34.234294 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6729 10:01:34.237113 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6730 10:01:34.240699 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6731 10:01:34.244005 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6732 10:01:34.250858 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6733 10:01:34.253576 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6734 10:01:34.257287 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6735 10:01:34.263566 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6736 10:01:34.267138 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6737 10:01:34.270699 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6738 10:01:34.273700 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6739 10:01:34.280243 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6740 10:01:34.280668 ==
6741 10:01:34.283656 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 10:01:34.286845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 10:01:34.287308 ==
6744 10:01:34.287637 DQS Delay:
6745 10:01:34.290312 DQS0 = 43, DQS1 = 51
6746 10:01:34.290752 DQM Delay:
6747 10:01:34.293536 DQM0 = 12, DQM1 = 14
6748 10:01:34.293948 DQ Delay:
6749 10:01:34.296910 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6750 10:01:34.300156 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6751 10:01:34.303993 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6752 10:01:34.306681 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6753 10:01:34.307109
6754 10:01:34.307434
6755 10:01:34.307734 ==
6756 10:01:34.310174 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 10:01:34.313536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 10:01:34.314049 ==
6759 10:01:34.314374
6760 10:01:34.314714
6761 10:01:34.316720 TX Vref Scan disable
6762 10:01:34.319785 == TX Byte 0 ==
6763 10:01:34.323106 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 10:01:34.326468 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 10:01:34.330056 == TX Byte 1 ==
6766 10:01:34.333237 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 10:01:34.336892 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 10:01:34.337404 ==
6769 10:01:34.340257 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 10:01:34.343051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 10:01:34.343569 ==
6772 10:01:34.343923
6773 10:01:34.346618
6774 10:01:34.347033 TX Vref Scan disable
6775 10:01:34.349603 == TX Byte 0 ==
6776 10:01:34.353135 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 10:01:34.356424 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 10:01:34.359219 == TX Byte 1 ==
6779 10:01:34.362578 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 10:01:34.365816 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 10:01:34.366269
6782 10:01:34.366693 [DATLAT]
6783 10:01:34.369233 Freq=400, CH1 RK0
6784 10:01:34.369787
6785 10:01:34.372748 DATLAT Default: 0xf
6786 10:01:34.373201 0, 0xFFFF, sum = 0
6787 10:01:34.375992 1, 0xFFFF, sum = 0
6788 10:01:34.376451 2, 0xFFFF, sum = 0
6789 10:01:34.378827 3, 0xFFFF, sum = 0
6790 10:01:34.379246 4, 0xFFFF, sum = 0
6791 10:01:34.382320 5, 0xFFFF, sum = 0
6792 10:01:34.382766 6, 0xFFFF, sum = 0
6793 10:01:34.385753 7, 0xFFFF, sum = 0
6794 10:01:34.386203 8, 0xFFFF, sum = 0
6795 10:01:34.389268 9, 0xFFFF, sum = 0
6796 10:01:34.389681 10, 0xFFFF, sum = 0
6797 10:01:34.392421 11, 0xFFFF, sum = 0
6798 10:01:34.392842 12, 0xFFFF, sum = 0
6799 10:01:34.395394 13, 0x0, sum = 1
6800 10:01:34.395926 14, 0x0, sum = 2
6801 10:01:34.398701 15, 0x0, sum = 3
6802 10:01:34.399137 16, 0x0, sum = 4
6803 10:01:34.401813 best_step = 14
6804 10:01:34.402218
6805 10:01:34.402543 ==
6806 10:01:34.405857 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 10:01:34.409237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 10:01:34.409671 ==
6809 10:01:34.411960 RX Vref Scan: 1
6810 10:01:34.412368
6811 10:01:34.412692 RX Vref 0 -> 0, step: 1
6812 10:01:34.413039
6813 10:01:34.415238 RX Delay -343 -> 252, step: 8
6814 10:01:34.415671
6815 10:01:34.418121 Set Vref, RX VrefLevel [Byte0]: 48
6816 10:01:34.421599 [Byte1]: 54
6817 10:01:34.426810
6818 10:01:34.427225 Final RX Vref Byte 0 = 48 to rank0
6819 10:01:34.430032 Final RX Vref Byte 1 = 54 to rank0
6820 10:01:34.433593 Final RX Vref Byte 0 = 48 to rank1
6821 10:01:34.437003 Final RX Vref Byte 1 = 54 to rank1==
6822 10:01:34.439720 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 10:01:34.446898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 10:01:34.447313 ==
6825 10:01:34.447663 DQS Delay:
6826 10:01:34.450119 DQS0 = 44, DQS1 = 56
6827 10:01:34.450529 DQM Delay:
6828 10:01:34.450899 DQM0 = 7, DQM1 = 12
6829 10:01:34.452973 DQ Delay:
6830 10:01:34.456478 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6831 10:01:34.460179 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6832 10:01:34.460712 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6833 10:01:34.463389 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6834 10:01:34.463795
6835 10:01:34.466292
6836 10:01:34.473612 [DQSOSCAuto] RK0, (LSB)MR18= 0xa379, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 389 ps
6837 10:01:34.476858 CH1 RK0: MR19=C0C, MR18=A379
6838 10:01:34.483381 CH1_RK0: MR19=0xC0C, MR18=0xA379, DQSOSC=389, MR23=63, INC=390, DEC=260
6839 10:01:34.483941 ==
6840 10:01:34.486432 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 10:01:34.489956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 10:01:34.490509 ==
6843 10:01:34.493274 [Gating] SW mode calibration
6844 10:01:34.500025 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6845 10:01:34.506754 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6846 10:01:34.509627 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 10:01:34.512835 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6848 10:01:34.519583 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 10:01:34.523278 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 10:01:34.526104 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 10:01:34.532900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 10:01:34.536671 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 10:01:34.539223 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 10:01:34.545763 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 10:01:34.546303 Total UI for P1: 0, mck2ui 16
6856 10:01:34.552353 best dqsien dly found for B0: ( 0, 14, 24)
6857 10:01:34.552808 Total UI for P1: 0, mck2ui 16
6858 10:01:34.555795 best dqsien dly found for B1: ( 0, 14, 24)
6859 10:01:34.562443 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6860 10:01:34.566082 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6861 10:01:34.566678
6862 10:01:34.569140 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 10:01:34.572205 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6864 10:01:34.575548 [Gating] SW calibration Done
6865 10:01:34.576095 ==
6866 10:01:34.578546 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 10:01:34.581978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 10:01:34.582437 ==
6869 10:01:34.585414 RX Vref Scan: 0
6870 10:01:34.585955
6871 10:01:34.586315 RX Vref 0 -> 0, step: 1
6872 10:01:34.586730
6873 10:01:34.588767 RX Delay -410 -> 252, step: 16
6874 10:01:34.595655 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6875 10:01:34.599023 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6876 10:01:34.602379 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6877 10:01:34.605038 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6878 10:01:34.611660 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6879 10:01:34.615208 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6880 10:01:34.618856 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6881 10:01:34.621998 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6882 10:01:34.628161 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6883 10:01:34.631460 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6884 10:01:34.635515 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6885 10:01:34.638532 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6886 10:01:34.644463 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6887 10:01:34.647863 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6888 10:01:34.651081 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6889 10:01:34.658120 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6890 10:01:34.658650 ==
6891 10:01:34.661171 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 10:01:34.665035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 10:01:34.665588 ==
6894 10:01:34.665948 DQS Delay:
6895 10:01:34.667829 DQS0 = 51, DQS1 = 51
6896 10:01:34.668278 DQM Delay:
6897 10:01:34.671077 DQM0 = 19, DQM1 = 14
6898 10:01:34.671530 DQ Delay:
6899 10:01:34.674835 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6900 10:01:34.678191 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6901 10:01:34.681480 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6902 10:01:34.684684 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6903 10:01:34.685139
6904 10:01:34.685493
6905 10:01:34.685827 ==
6906 10:01:34.687838 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 10:01:34.691306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 10:01:34.691830 ==
6909 10:01:34.692363
6910 10:01:34.692717
6911 10:01:34.694683 TX Vref Scan disable
6912 10:01:34.697926 == TX Byte 0 ==
6913 10:01:34.701253 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6914 10:01:34.704777 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6915 10:01:34.707773 == TX Byte 1 ==
6916 10:01:34.711311 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6917 10:01:34.714508 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6918 10:01:34.715105 ==
6919 10:01:34.717389 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 10:01:34.721025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 10:01:34.721573 ==
6922 10:01:34.721938
6923 10:01:34.724523
6924 10:01:34.725069 TX Vref Scan disable
6925 10:01:34.727557 == TX Byte 0 ==
6926 10:01:34.730867 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6927 10:01:34.734014 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6928 10:01:34.737570 == TX Byte 1 ==
6929 10:01:34.740535 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6930 10:01:34.743962 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6931 10:01:34.744419
6932 10:01:34.744779 [DATLAT]
6933 10:01:34.747016 Freq=400, CH1 RK1
6934 10:01:34.747499
6935 10:01:34.747993 DATLAT Default: 0xe
6936 10:01:34.750464 0, 0xFFFF, sum = 0
6937 10:01:34.754089 1, 0xFFFF, sum = 0
6938 10:01:34.754545 2, 0xFFFF, sum = 0
6939 10:01:34.757243 3, 0xFFFF, sum = 0
6940 10:01:34.757699 4, 0xFFFF, sum = 0
6941 10:01:34.760503 5, 0xFFFF, sum = 0
6942 10:01:34.760964 6, 0xFFFF, sum = 0
6943 10:01:34.763898 7, 0xFFFF, sum = 0
6944 10:01:34.764451 8, 0xFFFF, sum = 0
6945 10:01:34.766821 9, 0xFFFF, sum = 0
6946 10:01:34.767280 10, 0xFFFF, sum = 0
6947 10:01:34.770090 11, 0xFFFF, sum = 0
6948 10:01:34.770586 12, 0xFFFF, sum = 0
6949 10:01:34.773650 13, 0x0, sum = 1
6950 10:01:34.774107 14, 0x0, sum = 2
6951 10:01:34.777314 15, 0x0, sum = 3
6952 10:01:34.777871 16, 0x0, sum = 4
6953 10:01:34.780136 best_step = 14
6954 10:01:34.780637
6955 10:01:34.781113 ==
6956 10:01:34.783497 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 10:01:34.786765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 10:01:34.787225 ==
6959 10:01:34.790230 RX Vref Scan: 0
6960 10:01:34.790808
6961 10:01:34.791178 RX Vref 0 -> 0, step: 1
6962 10:01:34.791512
6963 10:01:34.793096 RX Delay -343 -> 252, step: 8
6964 10:01:34.801191 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6965 10:01:34.804859 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6966 10:01:34.808117 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6967 10:01:34.811300 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
6968 10:01:34.817537 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6969 10:01:34.821102 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6970 10:01:34.824222 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6971 10:01:34.831567 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6972 10:01:34.834062 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6973 10:01:34.837757 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6974 10:01:34.841133 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6975 10:01:34.846991 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6976 10:01:34.850759 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6977 10:01:34.853996 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6978 10:01:34.860328 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6979 10:01:34.863469 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6980 10:01:34.863932 ==
6981 10:01:34.866918 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 10:01:34.869854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 10:01:34.870259 ==
6984 10:01:34.873165 DQS Delay:
6985 10:01:34.873587 DQS0 = 48, DQS1 = 56
6986 10:01:34.874018 DQM Delay:
6987 10:01:34.876664 DQM0 = 13, DQM1 = 11
6988 10:01:34.877082 DQ Delay:
6989 10:01:34.880009 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6990 10:01:34.883183 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6991 10:01:34.886960 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6992 10:01:34.890334 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6993 10:01:34.890905
6994 10:01:34.891339
6995 10:01:34.900074 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
6996 10:01:34.900606 CH1 RK1: MR19=C0C, MR18=6E5E
6997 10:01:34.906378 CH1_RK1: MR19=0xC0C, MR18=0x6E5E, DQSOSC=395, MR23=63, INC=378, DEC=252
6998 10:01:34.909532 [RxdqsGatingPostProcess] freq 400
6999 10:01:34.916333 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7000 10:01:34.919557 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 10:01:34.923075 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 10:01:34.926515 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 10:01:34.929180 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 10:01:34.932644 best DQS0 dly(2T, 0.5T) = (0, 10)
7005 10:01:34.936509 best DQS1 dly(2T, 0.5T) = (0, 10)
7006 10:01:34.939498 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7007 10:01:34.942572 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7008 10:01:34.943053 Pre-setting of DQS Precalculation
7009 10:01:34.949398 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7010 10:01:34.956378 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7011 10:01:34.962410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7012 10:01:34.963002
7013 10:01:34.963364
7014 10:01:34.965489 [Calibration Summary] 800 Mbps
7015 10:01:34.969215 CH 0, Rank 0
7016 10:01:34.969759 SW Impedance : PASS
7017 10:01:34.972715 DUTY Scan : NO K
7018 10:01:34.975740 ZQ Calibration : PASS
7019 10:01:34.976208 Jitter Meter : NO K
7020 10:01:34.979217 CBT Training : PASS
7021 10:01:34.982389 Write leveling : PASS
7022 10:01:34.982973 RX DQS gating : PASS
7023 10:01:34.985741 RX DQ/DQS(RDDQC) : PASS
7024 10:01:34.989001 TX DQ/DQS : PASS
7025 10:01:34.989551 RX DATLAT : PASS
7026 10:01:34.992375 RX DQ/DQS(Engine): PASS
7027 10:01:34.992924 TX OE : NO K
7028 10:01:34.995908 All Pass.
7029 10:01:34.996459
7030 10:01:34.996817 CH 0, Rank 1
7031 10:01:34.999049 SW Impedance : PASS
7032 10:01:34.999605 DUTY Scan : NO K
7033 10:01:35.002703 ZQ Calibration : PASS
7034 10:01:35.005654 Jitter Meter : NO K
7035 10:01:35.006202 CBT Training : PASS
7036 10:01:35.008788 Write leveling : NO K
7037 10:01:35.012246 RX DQS gating : PASS
7038 10:01:35.012796 RX DQ/DQS(RDDQC) : PASS
7039 10:01:35.015288 TX DQ/DQS : PASS
7040 10:01:35.019102 RX DATLAT : PASS
7041 10:01:35.019549 RX DQ/DQS(Engine): PASS
7042 10:01:35.022195 TX OE : NO K
7043 10:01:35.022667 All Pass.
7044 10:01:35.023024
7045 10:01:35.025295 CH 1, Rank 0
7046 10:01:35.025869 SW Impedance : PASS
7047 10:01:35.028937 DUTY Scan : NO K
7048 10:01:35.032190 ZQ Calibration : PASS
7049 10:01:35.032638 Jitter Meter : NO K
7050 10:01:35.035300 CBT Training : PASS
7051 10:01:35.038497 Write leveling : PASS
7052 10:01:35.039085 RX DQS gating : PASS
7053 10:01:35.042263 RX DQ/DQS(RDDQC) : PASS
7054 10:01:35.045242 TX DQ/DQS : PASS
7055 10:01:35.045731 RX DATLAT : PASS
7056 10:01:35.048433 RX DQ/DQS(Engine): PASS
7057 10:01:35.048909 TX OE : NO K
7058 10:01:35.052034 All Pass.
7059 10:01:35.052484
7060 10:01:35.052838 CH 1, Rank 1
7061 10:01:35.055247 SW Impedance : PASS
7062 10:01:35.055696 DUTY Scan : NO K
7063 10:01:35.058988 ZQ Calibration : PASS
7064 10:01:35.062436 Jitter Meter : NO K
7065 10:01:35.063037 CBT Training : PASS
7066 10:01:35.065414 Write leveling : NO K
7067 10:01:35.068860 RX DQS gating : PASS
7068 10:01:35.069410 RX DQ/DQS(RDDQC) : PASS
7069 10:01:35.072003 TX DQ/DQS : PASS
7070 10:01:35.075233 RX DATLAT : PASS
7071 10:01:35.075681 RX DQ/DQS(Engine): PASS
7072 10:01:35.078677 TX OE : NO K
7073 10:01:35.079126 All Pass.
7074 10:01:35.079479
7075 10:01:35.081770 DramC Write-DBI off
7076 10:01:35.084920 PER_BANK_REFRESH: Hybrid Mode
7077 10:01:35.085374 TX_TRACKING: ON
7078 10:01:35.094987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7079 10:01:35.098514 [FAST_K] Save calibration result to emmc
7080 10:01:35.101570 dramc_set_vcore_voltage set vcore to 725000
7081 10:01:35.104945 Read voltage for 1600, 0
7082 10:01:35.105353 Vio18 = 0
7083 10:01:35.108521 Vcore = 725000
7084 10:01:35.109027 Vdram = 0
7085 10:01:35.109521 Vddq = 0
7086 10:01:35.109851 Vmddr = 0
7087 10:01:35.114689 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7088 10:01:35.120869 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7089 10:01:35.121412 MEM_TYPE=3, freq_sel=13
7090 10:01:35.124424 sv_algorithm_assistance_LP4_3733
7091 10:01:35.128058 ============ PULL DRAM RESETB DOWN ============
7092 10:01:35.134208 ========== PULL DRAM RESETB DOWN end =========
7093 10:01:35.138268 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7094 10:01:35.141047 ===================================
7095 10:01:35.144074 LPDDR4 DRAM CONFIGURATION
7096 10:01:35.147639 ===================================
7097 10:01:35.148057 EX_ROW_EN[0] = 0x0
7098 10:01:35.150915 EX_ROW_EN[1] = 0x0
7099 10:01:35.151323 LP4Y_EN = 0x0
7100 10:01:35.154018 WORK_FSP = 0x1
7101 10:01:35.154478 WL = 0x5
7102 10:01:35.157611 RL = 0x5
7103 10:01:35.160747 BL = 0x2
7104 10:01:35.161155 RPST = 0x0
7105 10:01:35.163766 RD_PRE = 0x0
7106 10:01:35.164174 WR_PRE = 0x1
7107 10:01:35.167294 WR_PST = 0x1
7108 10:01:35.167704 DBI_WR = 0x0
7109 10:01:35.170572 DBI_RD = 0x0
7110 10:01:35.171106 OTF = 0x1
7111 10:01:35.173835 ===================================
7112 10:01:35.177385 ===================================
7113 10:01:35.180815 ANA top config
7114 10:01:35.183624 ===================================
7115 10:01:35.184034 DLL_ASYNC_EN = 0
7116 10:01:35.187063 ALL_SLAVE_EN = 0
7117 10:01:35.190392 NEW_RANK_MODE = 1
7118 10:01:35.193602 DLL_IDLE_MODE = 1
7119 10:01:35.194011 LP45_APHY_COMB_EN = 1
7120 10:01:35.197042 TX_ODT_DIS = 0
7121 10:01:35.200351 NEW_8X_MODE = 1
7122 10:01:35.203656 ===================================
7123 10:01:35.207303 ===================================
7124 10:01:35.210433 data_rate = 3200
7125 10:01:35.213832 CKR = 1
7126 10:01:35.217594 DQ_P2S_RATIO = 8
7127 10:01:35.220300 ===================================
7128 10:01:35.220755 CA_P2S_RATIO = 8
7129 10:01:35.223430 DQ_CA_OPEN = 0
7130 10:01:35.226766 DQ_SEMI_OPEN = 0
7131 10:01:35.230403 CA_SEMI_OPEN = 0
7132 10:01:35.233840 CA_FULL_RATE = 0
7133 10:01:35.236837 DQ_CKDIV4_EN = 0
7134 10:01:35.237382 CA_CKDIV4_EN = 0
7135 10:01:35.240425 CA_PREDIV_EN = 0
7136 10:01:35.243477 PH8_DLY = 12
7137 10:01:35.247152 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7138 10:01:35.250043 DQ_AAMCK_DIV = 4
7139 10:01:35.253330 CA_AAMCK_DIV = 4
7140 10:01:35.253777 CA_ADMCK_DIV = 4
7141 10:01:35.256885 DQ_TRACK_CA_EN = 0
7142 10:01:35.260085 CA_PICK = 1600
7143 10:01:35.263002 CA_MCKIO = 1600
7144 10:01:35.266545 MCKIO_SEMI = 0
7145 10:01:35.269664 PLL_FREQ = 3068
7146 10:01:35.273346 DQ_UI_PI_RATIO = 32
7147 10:01:35.276569 CA_UI_PI_RATIO = 0
7148 10:01:35.279385 ===================================
7149 10:01:35.283162 ===================================
7150 10:01:35.283719 memory_type:LPDDR4
7151 10:01:35.286201 GP_NUM : 10
7152 10:01:35.289891 SRAM_EN : 1
7153 10:01:35.290434 MD32_EN : 0
7154 10:01:35.292966 ===================================
7155 10:01:35.295976 [ANA_INIT] >>>>>>>>>>>>>>
7156 10:01:35.299605 <<<<<< [CONFIGURE PHASE]: ANA_TX
7157 10:01:35.302896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7158 10:01:35.305780 ===================================
7159 10:01:35.309455 data_rate = 3200,PCW = 0X7600
7160 10:01:35.312730 ===================================
7161 10:01:35.316381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7162 10:01:35.319862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 10:01:35.326059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7164 10:01:35.329376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7165 10:01:35.333077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7166 10:01:35.335742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7167 10:01:35.339481 [ANA_INIT] flow start
7168 10:01:35.342567 [ANA_INIT] PLL >>>>>>>>
7169 10:01:35.343088 [ANA_INIT] PLL <<<<<<<<
7170 10:01:35.345742 [ANA_INIT] MIDPI >>>>>>>>
7171 10:01:35.348920 [ANA_INIT] MIDPI <<<<<<<<
7172 10:01:35.351983 [ANA_INIT] DLL >>>>>>>>
7173 10:01:35.352435 [ANA_INIT] DLL <<<<<<<<
7174 10:01:35.355308 [ANA_INIT] flow end
7175 10:01:35.359171 ============ LP4 DIFF to SE enter ============
7176 10:01:35.362105 ============ LP4 DIFF to SE exit ============
7177 10:01:35.365743 [ANA_INIT] <<<<<<<<<<<<<
7178 10:01:35.369139 [Flow] Enable top DCM control >>>>>
7179 10:01:35.372143 [Flow] Enable top DCM control <<<<<
7180 10:01:35.375413 Enable DLL master slave shuffle
7181 10:01:35.382344 ==============================================================
7182 10:01:35.383006 Gating Mode config
7183 10:01:35.388371 ==============================================================
7184 10:01:35.388919 Config description:
7185 10:01:35.398574 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7186 10:01:35.404658 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7187 10:01:35.411246 SELPH_MODE 0: By rank 1: By Phase
7188 10:01:35.418259 ==============================================================
7189 10:01:35.418866 GAT_TRACK_EN = 1
7190 10:01:35.421196 RX_GATING_MODE = 2
7191 10:01:35.424785 RX_GATING_TRACK_MODE = 2
7192 10:01:35.428074 SELPH_MODE = 1
7193 10:01:35.431376 PICG_EARLY_EN = 1
7194 10:01:35.434863 VALID_LAT_VALUE = 1
7195 10:01:35.441260 ==============================================================
7196 10:01:35.444094 Enter into Gating configuration >>>>
7197 10:01:35.447813 Exit from Gating configuration <<<<
7198 10:01:35.451111 Enter into DVFS_PRE_config >>>>>
7199 10:01:35.461136 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7200 10:01:35.464273 Exit from DVFS_PRE_config <<<<<
7201 10:01:35.467293 Enter into PICG configuration >>>>
7202 10:01:35.470816 Exit from PICG configuration <<<<
7203 10:01:35.474054 [RX_INPUT] configuration >>>>>
7204 10:01:35.477552 [RX_INPUT] configuration <<<<<
7205 10:01:35.480453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7206 10:01:35.487624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7207 10:01:35.494085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 10:01:35.500474 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 10:01:35.503857 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 10:01:35.510397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 10:01:35.513799 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7212 10:01:35.520474 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7213 10:01:35.523322 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7214 10:01:35.527002 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7215 10:01:35.530189 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7216 10:01:35.536404 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7217 10:01:35.539646 ===================================
7218 10:01:35.542875 LPDDR4 DRAM CONFIGURATION
7219 10:01:35.546777 ===================================
7220 10:01:35.547341 EX_ROW_EN[0] = 0x0
7221 10:01:35.549815 EX_ROW_EN[1] = 0x0
7222 10:01:35.550343 LP4Y_EN = 0x0
7223 10:01:35.552787 WORK_FSP = 0x1
7224 10:01:35.553245 WL = 0x5
7225 10:01:35.556310 RL = 0x5
7226 10:01:35.556851 BL = 0x2
7227 10:01:35.559921 RPST = 0x0
7228 10:01:35.560465 RD_PRE = 0x0
7229 10:01:35.562912 WR_PRE = 0x1
7230 10:01:35.565952 WR_PST = 0x1
7231 10:01:35.566475 DBI_WR = 0x0
7232 10:01:35.569301 DBI_RD = 0x0
7233 10:01:35.569843 OTF = 0x1
7234 10:01:35.573229 ===================================
7235 10:01:35.575983 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7236 10:01:35.579287 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7237 10:01:35.586236 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 10:01:35.589483 ===================================
7239 10:01:35.592698 LPDDR4 DRAM CONFIGURATION
7240 10:01:35.596180 ===================================
7241 10:01:35.596722 EX_ROW_EN[0] = 0x10
7242 10:01:35.599338 EX_ROW_EN[1] = 0x0
7243 10:01:35.599875 LP4Y_EN = 0x0
7244 10:01:35.602328 WORK_FSP = 0x1
7245 10:01:35.602920 WL = 0x5
7246 10:01:35.605730 RL = 0x5
7247 10:01:35.606180 BL = 0x2
7248 10:01:35.608811 RPST = 0x0
7249 10:01:35.612573 RD_PRE = 0x0
7250 10:01:35.613119 WR_PRE = 0x1
7251 10:01:35.615283 WR_PST = 0x1
7252 10:01:35.615770 DBI_WR = 0x0
7253 10:01:35.619225 DBI_RD = 0x0
7254 10:01:35.619791 OTF = 0x1
7255 10:01:35.622495 ===================================
7256 10:01:35.628754 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7257 10:01:35.629320 ==
7258 10:01:35.632160 Dram Type= 6, Freq= 0, CH_0, rank 0
7259 10:01:35.635512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7260 10:01:35.635995 ==
7261 10:01:35.638444 [Duty_Offset_Calibration]
7262 10:01:35.642196 B0:1 B1:-1 CA:0
7263 10:01:35.642896
7264 10:01:35.645177 [DutyScan_Calibration_Flow] k_type=0
7265 10:01:35.654079
7266 10:01:35.654647 ==CLK 0==
7267 10:01:35.657153 Final CLK duty delay cell = 0
7268 10:01:35.660206 [0] MAX Duty = 5125%(X100), DQS PI = 20
7269 10:01:35.663704 [0] MIN Duty = 4907%(X100), DQS PI = 4
7270 10:01:35.667075 [0] AVG Duty = 5016%(X100)
7271 10:01:35.667540
7272 10:01:35.669794 CH0 CLK Duty spec in!! Max-Min= 218%
7273 10:01:35.673661 [DutyScan_Calibration_Flow] ====Done====
7274 10:01:35.674218
7275 10:01:35.676389 [DutyScan_Calibration_Flow] k_type=1
7276 10:01:35.692634
7277 10:01:35.693190 ==DQS 0 ==
7278 10:01:35.696280 Final DQS duty delay cell = -4
7279 10:01:35.699521 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7280 10:01:35.702773 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7281 10:01:35.706512 [-4] AVG Duty = 4922%(X100)
7282 10:01:35.707130
7283 10:01:35.707609 ==DQS 1 ==
7284 10:01:35.709779 Final DQS duty delay cell = 0
7285 10:01:35.712662 [0] MAX Duty = 5156%(X100), DQS PI = 2
7286 10:01:35.716152 [0] MIN Duty = 5031%(X100), DQS PI = 18
7287 10:01:35.719369 [0] AVG Duty = 5093%(X100)
7288 10:01:35.719821
7289 10:01:35.722841 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7290 10:01:35.723390
7291 10:01:35.725935 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7292 10:01:35.729568 [DutyScan_Calibration_Flow] ====Done====
7293 10:01:35.730016
7294 10:01:35.732327 [DutyScan_Calibration_Flow] k_type=3
7295 10:01:35.750149
7296 10:01:35.750463 ==DQM 0 ==
7297 10:01:35.753394 Final DQM duty delay cell = 0
7298 10:01:35.757049 [0] MAX Duty = 5124%(X100), DQS PI = 22
7299 10:01:35.759897 [0] MIN Duty = 4907%(X100), DQS PI = 10
7300 10:01:35.763100 [0] AVG Duty = 5015%(X100)
7301 10:01:35.763340
7302 10:01:35.763526 ==DQM 1 ==
7303 10:01:35.766716 Final DQM duty delay cell = 0
7304 10:01:35.769761 [0] MAX Duty = 5000%(X100), DQS PI = 6
7305 10:01:35.773023 [0] MIN Duty = 4813%(X100), DQS PI = 20
7306 10:01:35.776948 [0] AVG Duty = 4906%(X100)
7307 10:01:35.777273
7308 10:01:35.779463 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7309 10:01:35.779698
7310 10:01:35.782735 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7311 10:01:35.786569 [DutyScan_Calibration_Flow] ====Done====
7312 10:01:35.787033
7313 10:01:35.789465 [DutyScan_Calibration_Flow] k_type=2
7314 10:01:35.807109
7315 10:01:35.807652 ==DQ 0 ==
7316 10:01:35.810050 Final DQ duty delay cell = -4
7317 10:01:35.813242 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7318 10:01:35.816525 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7319 10:01:35.820015 [-4] AVG Duty = 4953%(X100)
7320 10:01:35.820565
7321 10:01:35.821023 ==DQ 1 ==
7322 10:01:35.823234 Final DQ duty delay cell = 0
7323 10:01:35.826114 [0] MAX Duty = 5125%(X100), DQS PI = 2
7324 10:01:35.829572 [0] MIN Duty = 5000%(X100), DQS PI = 36
7325 10:01:35.832873 [0] AVG Duty = 5062%(X100)
7326 10:01:35.833477
7327 10:01:35.836094 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7328 10:01:35.836553
7329 10:01:35.839370 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7330 10:01:35.842823 [DutyScan_Calibration_Flow] ====Done====
7331 10:01:35.843270 ==
7332 10:01:35.845732 Dram Type= 6, Freq= 0, CH_1, rank 0
7333 10:01:35.849559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7334 10:01:35.850208 ==
7335 10:01:35.852746 [Duty_Offset_Calibration]
7336 10:01:35.853351 B0:-1 B1:1 CA:2
7337 10:01:35.853974
7338 10:01:35.855861 [DutyScan_Calibration_Flow] k_type=0
7339 10:01:35.867328
7340 10:01:35.867817 ==CLK 0==
7341 10:01:35.870702 Final CLK duty delay cell = 0
7342 10:01:35.873801 [0] MAX Duty = 5218%(X100), DQS PI = 24
7343 10:01:35.877027 [0] MIN Duty = 4969%(X100), DQS PI = 0
7344 10:01:35.877432 [0] AVG Duty = 5093%(X100)
7345 10:01:35.877750
7346 10:01:35.880772 CH1 CLK Duty spec in!! Max-Min= 249%
7347 10:01:35.886844 [DutyScan_Calibration_Flow] ====Done====
7348 10:01:35.887252
7349 10:01:35.890492 [DutyScan_Calibration_Flow] k_type=1
7350 10:01:35.906844
7351 10:01:35.907250 ==DQS 0 ==
7352 10:01:35.909954 Final DQS duty delay cell = 0
7353 10:01:35.913197 [0] MAX Duty = 5156%(X100), DQS PI = 18
7354 10:01:35.916937 [0] MIN Duty = 4938%(X100), DQS PI = 8
7355 10:01:35.917350 [0] AVG Duty = 5047%(X100)
7356 10:01:35.919777
7357 10:01:35.920235 ==DQS 1 ==
7358 10:01:35.923495 Final DQS duty delay cell = 0
7359 10:01:35.926851 [0] MAX Duty = 5093%(X100), DQS PI = 24
7360 10:01:35.929700 [0] MIN Duty = 4969%(X100), DQS PI = 54
7361 10:01:35.933210 [0] AVG Duty = 5031%(X100)
7362 10:01:35.933780
7363 10:01:35.936091 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7364 10:01:35.936742
7365 10:01:35.939741 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7366 10:01:35.943251 [DutyScan_Calibration_Flow] ====Done====
7367 10:01:35.943709
7368 10:01:35.946017 [DutyScan_Calibration_Flow] k_type=3
7369 10:01:35.962557
7370 10:01:35.963031 ==DQM 0 ==
7371 10:01:35.966376 Final DQM duty delay cell = -4
7372 10:01:35.969474 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7373 10:01:35.972457 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7374 10:01:35.976056 [-4] AVG Duty = 4922%(X100)
7375 10:01:35.976475
7376 10:01:35.976801 ==DQM 1 ==
7377 10:01:35.979248 Final DQM duty delay cell = 0
7378 10:01:35.982667 [0] MAX Duty = 5156%(X100), DQS PI = 0
7379 10:01:35.986060 [0] MIN Duty = 4969%(X100), DQS PI = 34
7380 10:01:35.989358 [0] AVG Duty = 5062%(X100)
7381 10:01:35.989764
7382 10:01:35.992727 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7383 10:01:35.993136
7384 10:01:35.996088 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7385 10:01:35.999016 [DutyScan_Calibration_Flow] ====Done====
7386 10:01:35.999431
7387 10:01:36.002422 [DutyScan_Calibration_Flow] k_type=2
7388 10:01:36.019598
7389 10:01:36.020188 ==DQ 0 ==
7390 10:01:36.023083 Final DQ duty delay cell = 0
7391 10:01:36.026374 [0] MAX Duty = 5187%(X100), DQS PI = 32
7392 10:01:36.029720 [0] MIN Duty = 4906%(X100), DQS PI = 10
7393 10:01:36.030320 [0] AVG Duty = 5046%(X100)
7394 10:01:36.032978
7395 10:01:36.033580 ==DQ 1 ==
7396 10:01:36.036677 Final DQ duty delay cell = 0
7397 10:01:36.039993 [0] MAX Duty = 5156%(X100), DQS PI = 10
7398 10:01:36.042819 [0] MIN Duty = 4938%(X100), DQS PI = 58
7399 10:01:36.043331 [0] AVG Duty = 5047%(X100)
7400 10:01:36.046482
7401 10:01:36.049511 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7402 10:01:36.050034
7403 10:01:36.053107 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7404 10:01:36.056398 [DutyScan_Calibration_Flow] ====Done====
7405 10:01:36.059570 nWR fixed to 30
7406 10:01:36.060108 [ModeRegInit_LP4] CH0 RK0
7407 10:01:36.062717 [ModeRegInit_LP4] CH0 RK1
7408 10:01:36.066014 [ModeRegInit_LP4] CH1 RK0
7409 10:01:36.069483 [ModeRegInit_LP4] CH1 RK1
7410 10:01:36.069890 match AC timing 5
7411 10:01:36.076044 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7412 10:01:36.079689 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7413 10:01:36.082982 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7414 10:01:36.089565 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7415 10:01:36.092788 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7416 10:01:36.093314 [MiockJmeterHQA]
7417 10:01:36.093888
7418 10:01:36.096345 [DramcMiockJmeter] u1RxGatingPI = 0
7419 10:01:36.099314 0 : 4252, 4027
7420 10:01:36.099885 4 : 4252, 4027
7421 10:01:36.102455 8 : 4252, 4027
7422 10:01:36.103057 12 : 4363, 4137
7423 10:01:36.103572 16 : 4253, 4027
7424 10:01:36.105841 20 : 4253, 4026
7425 10:01:36.106404 24 : 4252, 4027
7426 10:01:36.108704 28 : 4363, 4137
7427 10:01:36.109112 32 : 4363, 4137
7428 10:01:36.112209 36 : 4252, 4027
7429 10:01:36.112442 40 : 4253, 4026
7430 10:01:36.115531 44 : 4252, 4027
7431 10:01:36.115821 48 : 4252, 4027
7432 10:01:36.116007 52 : 4255, 4029
7433 10:01:36.119185 56 : 4363, 4138
7434 10:01:36.119265 60 : 4252, 4027
7435 10:01:36.122623 64 : 4253, 4027
7436 10:01:36.122718 68 : 4249, 4027
7437 10:01:36.125248 72 : 4253, 4029
7438 10:01:36.125329 76 : 4250, 4027
7439 10:01:36.128750 80 : 4363, 4137
7440 10:01:36.128831 84 : 4361, 4137
7441 10:01:36.128925 88 : 4252, 4024
7442 10:01:36.131921 92 : 4253, 753
7443 10:01:36.132028 96 : 4360, 0
7444 10:01:36.135646 100 : 4361, 0
7445 10:01:36.135721 104 : 4252, 0
7446 10:01:36.135786 108 : 4252, 0
7447 10:01:36.138582 112 : 4249, 0
7448 10:01:36.138691 116 : 4252, 0
7449 10:01:36.141742 120 : 4252, 0
7450 10:01:36.141812 124 : 4251, 0
7451 10:01:36.141871 128 : 4252, 0
7452 10:01:36.145380 132 : 4253, 0
7453 10:01:36.145461 136 : 4360, 0
7454 10:01:36.149109 140 : 4250, 0
7455 10:01:36.149268 144 : 4252, 0
7456 10:01:36.149343 148 : 4253, 0
7457 10:01:36.151896 152 : 4249, 0
7458 10:01:36.152061 156 : 4253, 0
7459 10:01:36.152144 160 : 4253, 0
7460 10:01:36.155598 164 : 4250, 0
7461 10:01:36.155753 168 : 4253, 0
7462 10:01:36.158472 172 : 4363, 0
7463 10:01:36.158670 176 : 4250, 0
7464 10:01:36.158754 180 : 4250, 0
7465 10:01:36.161871 184 : 4250, 0
7466 10:01:36.161982 188 : 4360, 0
7467 10:01:36.164822 192 : 4360, 0
7468 10:01:36.164923 196 : 4250, 0
7469 10:01:36.165060 200 : 4250, 0
7470 10:01:36.168592 204 : 4249, 0
7471 10:01:36.168702 208 : 4250, 0
7472 10:01:36.171558 212 : 4250, 0
7473 10:01:36.171667 216 : 4249, 0
7474 10:01:36.171753 220 : 4253, 0
7475 10:01:36.175398 224 : 4250, 436
7476 10:01:36.175518 228 : 4361, 3614
7477 10:01:36.178089 232 : 4250, 4027
7478 10:01:36.178221 236 : 4253, 4027
7479 10:01:36.181712 240 : 4253, 4026
7480 10:01:36.181845 244 : 4253, 4029
7481 10:01:36.185195 248 : 4250, 4027
7482 10:01:36.185345 252 : 4252, 4027
7483 10:01:36.188544 256 : 4360, 4137
7484 10:01:36.188714 260 : 4250, 4026
7485 10:01:36.188850 264 : 4250, 4027
7486 10:01:36.191498 268 : 4361, 4138
7487 10:01:36.191668 272 : 4250, 4027
7488 10:01:36.194868 276 : 4253, 4026
7489 10:01:36.195068 280 : 4363, 4140
7490 10:01:36.198458 284 : 4250, 4027
7491 10:01:36.198716 288 : 4249, 4027
7492 10:01:36.201484 292 : 4250, 4026
7493 10:01:36.201719 296 : 4253, 4029
7494 10:01:36.204704 300 : 4250, 4027
7495 10:01:36.204999 304 : 4252, 4027
7496 10:01:36.208235 308 : 4360, 4137
7497 10:01:36.208689 312 : 4250, 4027
7498 10:01:36.211624 316 : 4250, 4027
7499 10:01:36.212187 320 : 4360, 4138
7500 10:01:36.214551 324 : 4251, 4027
7501 10:01:36.214689 328 : 4250, 4026
7502 10:01:36.214768 332 : 4363, 4140
7503 10:01:36.217817 336 : 4250, 3655
7504 10:01:36.217897 340 : 4250, 1794
7505 10:01:36.217962
7506 10:01:36.221264 MIOCK jitter meter ch=0
7507 10:01:36.221344
7508 10:01:36.224314 1T = (340-92) = 248 dly cells
7509 10:01:36.231563 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7510 10:01:36.231647 ==
7511 10:01:36.234214 Dram Type= 6, Freq= 0, CH_0, rank 0
7512 10:01:36.237461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7513 10:01:36.237541 ==
7514 10:01:36.244286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7515 10:01:36.247674 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7516 10:01:36.250948 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7517 10:01:36.257664 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7518 10:01:36.267172 [CA 0] Center 43 (12~74) winsize 63
7519 10:01:36.269738 [CA 1] Center 42 (12~73) winsize 62
7520 10:01:36.273140 [CA 2] Center 38 (9~68) winsize 60
7521 10:01:36.276412 [CA 3] Center 38 (8~68) winsize 61
7522 10:01:36.280118 [CA 4] Center 36 (7~66) winsize 60
7523 10:01:36.283275 [CA 5] Center 35 (6~65) winsize 60
7524 10:01:36.283362
7525 10:01:36.286670 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7526 10:01:36.286743
7527 10:01:36.289513 [CATrainingPosCal] consider 1 rank data
7528 10:01:36.292973 u2DelayCellTimex100 = 262/100 ps
7529 10:01:36.299639 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7530 10:01:36.302689 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7531 10:01:36.306223 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7532 10:01:36.309537 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7533 10:01:36.312779 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7534 10:01:36.315963 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7535 10:01:36.316140
7536 10:01:36.319119 CA PerBit enable=1, Macro0, CA PI delay=35
7537 10:01:36.319286
7538 10:01:36.322632 [CBTSetCACLKResult] CA Dly = 35
7539 10:01:36.326205 CS Dly: 12 (0~43)
7540 10:01:36.329447 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7541 10:01:36.332638 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7542 10:01:36.332800 ==
7543 10:01:36.336220 Dram Type= 6, Freq= 0, CH_0, rank 1
7544 10:01:36.342363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 10:01:36.342652 ==
7546 10:01:36.345577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7547 10:01:36.352628 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7548 10:01:36.355526 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7549 10:01:36.361989 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7550 10:01:36.370696 [CA 0] Center 42 (12~73) winsize 62
7551 10:01:36.373362 [CA 1] Center 43 (13~73) winsize 61
7552 10:01:36.376590 [CA 2] Center 37 (8~67) winsize 60
7553 10:01:36.380120 [CA 3] Center 37 (7~67) winsize 61
7554 10:01:36.383360 [CA 4] Center 35 (6~65) winsize 60
7555 10:01:36.386965 [CA 5] Center 35 (5~65) winsize 61
7556 10:01:36.387045
7557 10:01:36.389768 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7558 10:01:36.389848
7559 10:01:36.393528 [CATrainingPosCal] consider 2 rank data
7560 10:01:36.396358 u2DelayCellTimex100 = 262/100 ps
7561 10:01:36.403411 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7562 10:01:36.406469 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7563 10:01:36.409854 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7564 10:01:36.412856 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7565 10:01:36.416809 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7566 10:01:36.420007 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7567 10:01:36.420116
7568 10:01:36.422818 CA PerBit enable=1, Macro0, CA PI delay=35
7569 10:01:36.422928
7570 10:01:36.425916 [CBTSetCACLKResult] CA Dly = 35
7571 10:01:36.429233 CS Dly: 12 (0~44)
7572 10:01:36.432772 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7573 10:01:36.435949 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7574 10:01:36.436056
7575 10:01:36.439478 ----->DramcWriteLeveling(PI) begin...
7576 10:01:36.439584 ==
7577 10:01:36.442567 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 10:01:36.449588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 10:01:36.449684 ==
7580 10:01:36.452573 Write leveling (Byte 0): 37 => 37
7581 10:01:36.456285 Write leveling (Byte 1): 28 => 28
7582 10:01:36.456391 DramcWriteLeveling(PI) end<-----
7583 10:01:36.459257
7584 10:01:36.459366 ==
7585 10:01:36.462491 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 10:01:36.465578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 10:01:36.465688 ==
7588 10:01:36.469249 [Gating] SW mode calibration
7589 10:01:36.476009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7590 10:01:36.478720 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7591 10:01:36.485701 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 10:01:36.488986 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 10:01:36.492504 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 10:01:36.498864 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7595 10:01:36.502192 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7596 10:01:36.505167 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
7597 10:01:36.512246 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 10:01:36.515173 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 10:01:36.518755 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 10:01:36.525397 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 10:01:36.528901 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 10:01:36.531705 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7603 10:01:36.538290 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7604 10:01:36.541591 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7605 10:01:36.544723 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7606 10:01:36.551909 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 10:01:36.555091 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 10:01:36.558082 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 10:01:36.564911 1 6 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7610 10:01:36.567757 1 6 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7611 10:01:36.571508 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7612 10:01:36.578466 1 6 20 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
7613 10:01:36.581226 1 6 24 | B1->B0 | 403f 4646 | 1 0 | (0 0) (0 0)
7614 10:01:36.584663 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 10:01:36.591508 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 10:01:36.594538 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 10:01:36.597441 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 10:01:36.604384 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7619 10:01:36.607531 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7620 10:01:36.610578 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7621 10:01:36.617361 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 10:01:36.620981 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 10:01:36.627343 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 10:01:36.630420 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 10:01:36.634077 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 10:01:36.640476 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 10:01:36.644028 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 10:01:36.646868 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 10:01:36.653792 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 10:01:36.656853 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 10:01:36.660264 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 10:01:36.667112 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 10:01:36.670237 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7634 10:01:36.673825 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7635 10:01:36.680598 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7636 10:01:36.680747 Total UI for P1: 0, mck2ui 16
7637 10:01:36.683080 best dqsien dly found for B0: ( 1, 9, 10)
7638 10:01:36.690297 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7639 10:01:36.693175 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7640 10:01:36.696806 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 10:01:36.699951 Total UI for P1: 0, mck2ui 16
7642 10:01:36.703400 best dqsien dly found for B1: ( 1, 9, 22)
7643 10:01:36.706890 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7644 10:01:36.713353 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7645 10:01:36.713443
7646 10:01:36.716296 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7647 10:01:36.719763 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7648 10:01:36.722806 [Gating] SW calibration Done
7649 10:01:36.722910 ==
7650 10:01:36.726578 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 10:01:36.729875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 10:01:36.729961 ==
7653 10:01:36.732914 RX Vref Scan: 0
7654 10:01:36.733004
7655 10:01:36.733077 RX Vref 0 -> 0, step: 1
7656 10:01:36.733144
7657 10:01:36.736663 RX Delay 0 -> 252, step: 8
7658 10:01:36.739991 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7659 10:01:36.742818 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7660 10:01:36.749774 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7661 10:01:36.752910 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7662 10:01:36.756550 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7663 10:01:36.759355 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7664 10:01:36.762571 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7665 10:01:36.769609 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7666 10:01:36.772578 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7667 10:01:36.775915 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7668 10:01:36.779773 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7669 10:01:36.786095 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7670 10:01:36.789620 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7671 10:01:36.792806 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7672 10:01:36.795870 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7673 10:01:36.799454 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7674 10:01:36.802297 ==
7675 10:01:36.805424 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 10:01:36.809119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 10:01:36.809634 ==
7678 10:01:36.810099 DQS Delay:
7679 10:01:36.812320 DQS0 = 0, DQS1 = 0
7680 10:01:36.812838 DQM Delay:
7681 10:01:36.815527 DQM0 = 136, DQM1 = 126
7682 10:01:36.816065 DQ Delay:
7683 10:01:36.818954 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7684 10:01:36.822261 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7685 10:01:36.825316 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7686 10:01:36.828879 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7687 10:01:36.829341
7688 10:01:36.829795
7689 10:01:36.832251 ==
7690 10:01:36.832784 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 10:01:36.838511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 10:01:36.838922 ==
7693 10:01:36.839271
7694 10:01:36.839601
7695 10:01:36.841918 TX Vref Scan disable
7696 10:01:36.842294 == TX Byte 0 ==
7697 10:01:36.845294 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7698 10:01:36.851813 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7699 10:01:36.852036 == TX Byte 1 ==
7700 10:01:36.855087 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7701 10:01:36.861554 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7702 10:01:36.861764 ==
7703 10:01:36.864933 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 10:01:36.867898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 10:01:36.868184 ==
7706 10:01:36.882062
7707 10:01:36.885587 TX Vref early break, caculate TX vref
7708 10:01:36.888676 TX Vref=16, minBit 4, minWin=22, winSum=369
7709 10:01:36.892100 TX Vref=18, minBit 4, minWin=22, winSum=379
7710 10:01:36.895610 TX Vref=20, minBit 1, minWin=23, winSum=395
7711 10:01:36.898390 TX Vref=22, minBit 3, minWin=24, winSum=403
7712 10:01:36.901530 TX Vref=24, minBit 3, minWin=24, winSum=405
7713 10:01:36.908780 TX Vref=26, minBit 0, minWin=25, winSum=416
7714 10:01:36.911747 TX Vref=28, minBit 4, minWin=24, winSum=418
7715 10:01:36.914751 TX Vref=30, minBit 0, minWin=24, winSum=409
7716 10:01:36.918223 TX Vref=32, minBit 0, minWin=24, winSum=404
7717 10:01:36.921643 TX Vref=34, minBit 7, minWin=23, winSum=393
7718 10:01:36.928416 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
7719 10:01:36.928626
7720 10:01:36.931091 Final TX Range 0 Vref 26
7721 10:01:36.931171
7722 10:01:36.931235 ==
7723 10:01:36.934542 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 10:01:36.937855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 10:01:36.937935 ==
7726 10:01:36.937999
7727 10:01:36.938058
7728 10:01:36.941193 TX Vref Scan disable
7729 10:01:36.947776 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7730 10:01:36.947877 == TX Byte 0 ==
7731 10:01:36.951208 u2DelayCellOfst[0]=11 cells (3 PI)
7732 10:01:36.954225 u2DelayCellOfst[1]=14 cells (4 PI)
7733 10:01:36.957641 u2DelayCellOfst[2]=11 cells (3 PI)
7734 10:01:36.961231 u2DelayCellOfst[3]=11 cells (3 PI)
7735 10:01:36.964280 u2DelayCellOfst[4]=11 cells (3 PI)
7736 10:01:36.967660 u2DelayCellOfst[5]=0 cells (0 PI)
7737 10:01:36.971378 u2DelayCellOfst[6]=18 cells (5 PI)
7738 10:01:36.973976 u2DelayCellOfst[7]=18 cells (5 PI)
7739 10:01:36.977574 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7740 10:01:36.980914 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7741 10:01:36.984153 == TX Byte 1 ==
7742 10:01:36.987749 u2DelayCellOfst[8]=0 cells (0 PI)
7743 10:01:36.990745 u2DelayCellOfst[9]=0 cells (0 PI)
7744 10:01:36.993930 u2DelayCellOfst[10]=7 cells (2 PI)
7745 10:01:36.997151 u2DelayCellOfst[11]=0 cells (0 PI)
7746 10:01:36.997389 u2DelayCellOfst[12]=11 cells (3 PI)
7747 10:01:37.000985 u2DelayCellOfst[13]=11 cells (3 PI)
7748 10:01:37.004107 u2DelayCellOfst[14]=11 cells (3 PI)
7749 10:01:37.007435 u2DelayCellOfst[15]=11 cells (3 PI)
7750 10:01:37.013923 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7751 10:01:37.017754 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7752 10:01:37.017990 DramC Write-DBI on
7753 10:01:37.020680 ==
7754 10:01:37.023850 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 10:01:37.026948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 10:01:37.027186 ==
7757 10:01:37.027372
7758 10:01:37.027544
7759 10:01:37.030418 TX Vref Scan disable
7760 10:01:37.030670 == TX Byte 0 ==
7761 10:01:37.037195 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7762 10:01:37.037431 == TX Byte 1 ==
7763 10:01:37.040639 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7764 10:01:37.044025 DramC Write-DBI off
7765 10:01:37.044281
7766 10:01:37.044482 [DATLAT]
7767 10:01:37.046910 Freq=1600, CH0 RK0
7768 10:01:37.047144
7769 10:01:37.047329 DATLAT Default: 0xf
7770 10:01:37.050076 0, 0xFFFF, sum = 0
7771 10:01:37.050363 1, 0xFFFF, sum = 0
7772 10:01:37.053738 2, 0xFFFF, sum = 0
7773 10:01:37.053975 3, 0xFFFF, sum = 0
7774 10:01:37.056669 4, 0xFFFF, sum = 0
7775 10:01:37.059974 5, 0xFFFF, sum = 0
7776 10:01:37.060212 6, 0xFFFF, sum = 0
7777 10:01:37.063359 7, 0xFFFF, sum = 0
7778 10:01:37.063440 8, 0xFFFF, sum = 0
7779 10:01:37.066753 9, 0xFFFF, sum = 0
7780 10:01:37.066834 10, 0xFFFF, sum = 0
7781 10:01:37.070020 11, 0xFFFF, sum = 0
7782 10:01:37.070101 12, 0xFFFF, sum = 0
7783 10:01:37.073101 13, 0xFFFF, sum = 0
7784 10:01:37.073181 14, 0x0, sum = 1
7785 10:01:37.076584 15, 0x0, sum = 2
7786 10:01:37.076664 16, 0x0, sum = 3
7787 10:01:37.080009 17, 0x0, sum = 4
7788 10:01:37.080089 best_step = 15
7789 10:01:37.080152
7790 10:01:37.080210 ==
7791 10:01:37.082882 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 10:01:37.086383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 10:01:37.089769 ==
7794 10:01:37.090175 RX Vref Scan: 1
7795 10:01:37.090643
7796 10:01:37.093759 Set Vref Range= 24 -> 127
7797 10:01:37.094209
7798 10:01:37.096847 RX Vref 24 -> 127, step: 1
7799 10:01:37.097339
7800 10:01:37.097786 RX Delay 19 -> 252, step: 4
7801 10:01:37.098214
7802 10:01:37.099777 Set Vref, RX VrefLevel [Byte0]: 24
7803 10:01:37.103248 [Byte1]: 24
7804 10:01:37.106719
7805 10:01:37.107249 Set Vref, RX VrefLevel [Byte0]: 25
7806 10:01:37.110263 [Byte1]: 25
7807 10:01:37.114746
7808 10:01:37.115221 Set Vref, RX VrefLevel [Byte0]: 26
7809 10:01:37.117784 [Byte1]: 26
7810 10:01:37.122269
7811 10:01:37.122717 Set Vref, RX VrefLevel [Byte0]: 27
7812 10:01:37.125233 [Byte1]: 27
7813 10:01:37.129329
7814 10:01:37.129547 Set Vref, RX VrefLevel [Byte0]: 28
7815 10:01:37.133210 [Byte1]: 28
7816 10:01:37.137115
7817 10:01:37.137291 Set Vref, RX VrefLevel [Byte0]: 29
7818 10:01:37.140322 [Byte1]: 29
7819 10:01:37.144808
7820 10:01:37.144955 Set Vref, RX VrefLevel [Byte0]: 30
7821 10:01:37.148193 [Byte1]: 30
7822 10:01:37.151913
7823 10:01:37.152059 Set Vref, RX VrefLevel [Byte0]: 31
7824 10:01:37.155377 [Byte1]: 31
7825 10:01:37.160221
7826 10:01:37.160368 Set Vref, RX VrefLevel [Byte0]: 32
7827 10:01:37.162827 [Byte1]: 32
7828 10:01:37.167691
7829 10:01:37.167931 Set Vref, RX VrefLevel [Byte0]: 33
7830 10:01:37.171016 [Byte1]: 33
7831 10:01:37.175237
7832 10:01:37.175445 Set Vref, RX VrefLevel [Byte0]: 34
7833 10:01:37.178523 [Byte1]: 34
7834 10:01:37.182510
7835 10:01:37.182764 Set Vref, RX VrefLevel [Byte0]: 35
7836 10:01:37.185917 [Byte1]: 35
7837 10:01:37.190168
7838 10:01:37.190500 Set Vref, RX VrefLevel [Byte0]: 36
7839 10:01:37.193859 [Byte1]: 36
7840 10:01:37.198018
7841 10:01:37.198415 Set Vref, RX VrefLevel [Byte0]: 37
7842 10:01:37.201333 [Byte1]: 37
7843 10:01:37.205236
7844 10:01:37.205626 Set Vref, RX VrefLevel [Byte0]: 38
7845 10:01:37.208893 [Byte1]: 38
7846 10:01:37.212830
7847 10:01:37.213121 Set Vref, RX VrefLevel [Byte0]: 39
7848 10:01:37.216158 [Byte1]: 39
7849 10:01:37.220638
7850 10:01:37.221040 Set Vref, RX VrefLevel [Byte0]: 40
7851 10:01:37.227100 [Byte1]: 40
7852 10:01:37.227525
7853 10:01:37.230652 Set Vref, RX VrefLevel [Byte0]: 41
7854 10:01:37.233676 [Byte1]: 41
7855 10:01:37.233968
7856 10:01:37.237502 Set Vref, RX VrefLevel [Byte0]: 42
7857 10:01:37.240062 [Byte1]: 42
7858 10:01:37.240355
7859 10:01:37.243552 Set Vref, RX VrefLevel [Byte0]: 43
7860 10:01:37.246642 [Byte1]: 43
7861 10:01:37.250921
7862 10:01:37.251211 Set Vref, RX VrefLevel [Byte0]: 44
7863 10:01:37.254121 [Byte1]: 44
7864 10:01:37.258466
7865 10:01:37.258827 Set Vref, RX VrefLevel [Byte0]: 45
7866 10:01:37.261881 [Byte1]: 45
7867 10:01:37.266226
7868 10:01:37.266665 Set Vref, RX VrefLevel [Byte0]: 46
7869 10:01:37.269404 [Byte1]: 46
7870 10:01:37.273515
7871 10:01:37.273803 Set Vref, RX VrefLevel [Byte0]: 47
7872 10:01:37.276872 [Byte1]: 47
7873 10:01:37.281338
7874 10:01:37.281693 Set Vref, RX VrefLevel [Byte0]: 48
7875 10:01:37.284220 [Byte1]: 48
7876 10:01:37.288850
7877 10:01:37.289257 Set Vref, RX VrefLevel [Byte0]: 49
7878 10:01:37.292062 [Byte1]: 49
7879 10:01:37.296470
7880 10:01:37.296877 Set Vref, RX VrefLevel [Byte0]: 50
7881 10:01:37.299942 [Byte1]: 50
7882 10:01:37.303989
7883 10:01:37.304494 Set Vref, RX VrefLevel [Byte0]: 51
7884 10:01:37.307498 [Byte1]: 51
7885 10:01:37.311751
7886 10:01:37.312504 Set Vref, RX VrefLevel [Byte0]: 52
7887 10:01:37.315233 [Byte1]: 52
7888 10:01:37.319224
7889 10:01:37.319814 Set Vref, RX VrefLevel [Byte0]: 53
7890 10:01:37.322105 [Byte1]: 53
7891 10:01:37.326939
7892 10:01:37.327516 Set Vref, RX VrefLevel [Byte0]: 54
7893 10:01:37.329640 [Byte1]: 54
7894 10:01:37.333950
7895 10:01:37.334538 Set Vref, RX VrefLevel [Byte0]: 55
7896 10:01:37.337404 [Byte1]: 55
7897 10:01:37.341554
7898 10:01:37.341854 Set Vref, RX VrefLevel [Byte0]: 56
7899 10:01:37.344705 [Byte1]: 56
7900 10:01:37.348997
7901 10:01:37.349241 Set Vref, RX VrefLevel [Byte0]: 57
7902 10:01:37.352454 [Byte1]: 57
7903 10:01:37.356790
7904 10:01:37.356964 Set Vref, RX VrefLevel [Byte0]: 58
7905 10:01:37.360214 [Byte1]: 58
7906 10:01:37.364118
7907 10:01:37.364343 Set Vref, RX VrefLevel [Byte0]: 59
7908 10:01:37.367347 [Byte1]: 59
7909 10:01:37.371914
7910 10:01:37.372146 Set Vref, RX VrefLevel [Byte0]: 60
7911 10:01:37.374760 [Byte1]: 60
7912 10:01:37.379473
7913 10:01:37.379647 Set Vref, RX VrefLevel [Byte0]: 61
7914 10:01:37.382640 [Byte1]: 61
7915 10:01:37.386999
7916 10:01:37.387232 Set Vref, RX VrefLevel [Byte0]: 62
7917 10:01:37.390379 [Byte1]: 62
7918 10:01:37.394953
7919 10:01:37.395199 Set Vref, RX VrefLevel [Byte0]: 63
7920 10:01:37.397620 [Byte1]: 63
7921 10:01:37.402185
7922 10:01:37.402366 Set Vref, RX VrefLevel [Byte0]: 64
7923 10:01:37.405391 [Byte1]: 64
7924 10:01:37.410347
7925 10:01:37.410583 Set Vref, RX VrefLevel [Byte0]: 65
7926 10:01:37.412880 [Byte1]: 65
7927 10:01:37.417389
7928 10:01:37.417630 Set Vref, RX VrefLevel [Byte0]: 66
7929 10:01:37.420498 [Byte1]: 66
7930 10:01:37.425068
7931 10:01:37.425296 Set Vref, RX VrefLevel [Byte0]: 67
7932 10:01:37.428124 [Byte1]: 67
7933 10:01:37.432699
7934 10:01:37.432905 Set Vref, RX VrefLevel [Byte0]: 68
7935 10:01:37.435997 [Byte1]: 68
7936 10:01:37.439781
7937 10:01:37.439956 Set Vref, RX VrefLevel [Byte0]: 69
7938 10:01:37.443579 [Byte1]: 69
7939 10:01:37.447803
7940 10:01:37.447984 Set Vref, RX VrefLevel [Byte0]: 70
7941 10:01:37.450971 [Byte1]: 70
7942 10:01:37.455174
7943 10:01:37.455248 Set Vref, RX VrefLevel [Byte0]: 71
7944 10:01:37.458545 [Byte1]: 71
7945 10:01:37.462517
7946 10:01:37.462634 Set Vref, RX VrefLevel [Byte0]: 72
7947 10:01:37.465832 [Byte1]: 72
7948 10:01:37.470355
7949 10:01:37.470533 Set Vref, RX VrefLevel [Byte0]: 73
7950 10:01:37.473714 [Byte1]: 73
7951 10:01:37.477801
7952 10:01:37.477991 Set Vref, RX VrefLevel [Byte0]: 74
7953 10:01:37.481334 [Byte1]: 74
7954 10:01:37.485746
7955 10:01:37.485961 Set Vref, RX VrefLevel [Byte0]: 75
7956 10:01:37.488949 [Byte1]: 75
7957 10:01:37.493192
7958 10:01:37.493425 Set Vref, RX VrefLevel [Byte0]: 76
7959 10:01:37.496737 [Byte1]: 76
7960 10:01:37.500846
7961 10:01:37.501135 Set Vref, RX VrefLevel [Byte0]: 77
7962 10:01:37.504003 [Byte1]: 77
7963 10:01:37.508591
7964 10:01:37.508958 Set Vref, RX VrefLevel [Byte0]: 78
7965 10:01:37.511600 [Byte1]: 78
7966 10:01:37.516187
7967 10:01:37.516661 Set Vref, RX VrefLevel [Byte0]: 79
7968 10:01:37.519788 [Byte1]: 79
7969 10:01:37.523620
7970 10:01:37.524171 Final RX Vref Byte 0 = 67 to rank0
7971 10:01:37.527090 Final RX Vref Byte 1 = 59 to rank0
7972 10:01:37.530115 Final RX Vref Byte 0 = 67 to rank1
7973 10:01:37.533763 Final RX Vref Byte 1 = 59 to rank1==
7974 10:01:37.537205 Dram Type= 6, Freq= 0, CH_0, rank 0
7975 10:01:37.543583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 10:01:37.544044 ==
7977 10:01:37.544408 DQS Delay:
7978 10:01:37.546675 DQS0 = 0, DQS1 = 0
7979 10:01:37.547131 DQM Delay:
7980 10:01:37.547490 DQM0 = 134, DQM1 = 123
7981 10:01:37.549950 DQ Delay:
7982 10:01:37.553699 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =134
7983 10:01:37.556530 DQ4 =134, DQ5 =122, DQ6 =142, DQ7 =144
7984 10:01:37.559928 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
7985 10:01:37.563834 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
7986 10:01:37.564287
7987 10:01:37.564641
7988 10:01:37.564970
7989 10:01:37.566539 [DramC_TX_OE_Calibration] TA2
7990 10:01:37.570153 Original DQ_B0 (3 6) =30, OEN = 27
7991 10:01:37.573049 Original DQ_B1 (3 6) =30, OEN = 27
7992 10:01:37.576295 24, 0x0, End_B0=24 End_B1=24
7993 10:01:37.579764 25, 0x0, End_B0=25 End_B1=25
7994 10:01:37.580183 26, 0x0, End_B0=26 End_B1=26
7995 10:01:37.582959 27, 0x0, End_B0=27 End_B1=27
7996 10:01:37.586064 28, 0x0, End_B0=28 End_B1=28
7997 10:01:37.589539 29, 0x0, End_B0=29 End_B1=29
7998 10:01:37.589958 30, 0x0, End_B0=30 End_B1=30
7999 10:01:37.592870 31, 0x4141, End_B0=30 End_B1=30
8000 10:01:37.596504 Byte0 end_step=30 best_step=27
8001 10:01:37.598969 Byte1 end_step=30 best_step=27
8002 10:01:37.602624 Byte0 TX OE(2T, 0.5T) = (3, 3)
8003 10:01:37.606044 Byte1 TX OE(2T, 0.5T) = (3, 3)
8004 10:01:37.606449
8005 10:01:37.606812
8006 10:01:37.612482 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8007 10:01:37.616230 CH0 RK0: MR19=303, MR18=2415
8008 10:01:37.622831 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8009 10:01:37.623342
8010 10:01:37.626544 ----->DramcWriteLeveling(PI) begin...
8011 10:01:37.627097 ==
8012 10:01:37.629181 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 10:01:37.632641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 10:01:37.633147 ==
8015 10:01:37.635606 Write leveling (Byte 0): 36 => 36
8016 10:01:37.639284 Write leveling (Byte 1): 28 => 28
8017 10:01:37.642354 DramcWriteLeveling(PI) end<-----
8018 10:01:37.642906
8019 10:01:37.643239 ==
8020 10:01:37.645693 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 10:01:37.652105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 10:01:37.652628 ==
8023 10:01:37.652963 [Gating] SW mode calibration
8024 10:01:37.662103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8025 10:01:37.665222 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8026 10:01:37.668615 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 10:01:37.675398 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 10:01:37.678198 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 10:01:37.681831 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8030 10:01:37.688407 1 4 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8031 10:01:37.691574 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8032 10:01:37.694622 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 10:01:37.701479 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8034 10:01:37.705082 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 10:01:37.708090 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 10:01:37.714502 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8037 10:01:37.717899 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 1)
8038 10:01:37.724912 1 5 16 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (1 0)
8039 10:01:37.727819 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8040 10:01:37.730987 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 10:01:37.737935 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 10:01:37.741154 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 10:01:37.744253 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 10:01:37.750580 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 10:01:37.753818 1 6 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
8046 10:01:37.757143 1 6 16 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
8047 10:01:37.763950 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 10:01:37.767047 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 10:01:37.769918 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 10:01:37.776661 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 10:01:37.779706 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 10:01:37.783210 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 10:01:37.790083 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8054 10:01:37.792839 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8055 10:01:37.796317 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8056 10:01:37.803111 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 10:01:37.806445 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 10:01:37.809461 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 10:01:37.816323 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 10:01:37.819566 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 10:01:37.823001 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 10:01:37.829402 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 10:01:37.832921 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 10:01:37.836081 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 10:01:37.839531 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 10:01:37.846196 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 10:01:37.849489 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 10:01:37.852582 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8069 10:01:37.859195 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8070 10:01:37.862556 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8071 10:01:37.865811 Total UI for P1: 0, mck2ui 16
8072 10:01:37.869311 best dqsien dly found for B0: ( 1, 9, 10)
8073 10:01:37.872423 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 10:01:37.876124 Total UI for P1: 0, mck2ui 16
8075 10:01:37.879366 best dqsien dly found for B1: ( 1, 9, 16)
8076 10:01:37.882242 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8077 10:01:37.889359 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8078 10:01:37.889481
8079 10:01:37.892249 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8080 10:01:37.895787 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8081 10:01:37.899211 [Gating] SW calibration Done
8082 10:01:37.899309 ==
8083 10:01:37.902257 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 10:01:37.905815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 10:01:37.905900 ==
8086 10:01:37.908617 RX Vref Scan: 0
8087 10:01:37.908693
8088 10:01:37.908757 RX Vref 0 -> 0, step: 1
8089 10:01:37.908825
8090 10:01:37.912257 RX Delay 0 -> 252, step: 8
8091 10:01:37.915426 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8092 10:01:37.922403 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8093 10:01:37.925393 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8094 10:01:37.928626 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8095 10:01:37.932649 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8096 10:01:37.935435 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8097 10:01:37.942507 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8098 10:01:37.945812 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8099 10:01:37.948965 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8100 10:01:37.951982 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8101 10:01:37.955420 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8102 10:01:37.962252 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8103 10:01:37.965949 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8104 10:01:37.968911 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8105 10:01:37.971844 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8106 10:01:37.975128 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8107 10:01:37.979125 ==
8108 10:01:37.981942 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 10:01:37.985386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 10:01:37.985893 ==
8111 10:01:37.986224 DQS Delay:
8112 10:01:37.988321 DQS0 = 0, DQS1 = 0
8113 10:01:37.988729 DQM Delay:
8114 10:01:37.991923 DQM0 = 133, DQM1 = 129
8115 10:01:37.992432 DQ Delay:
8116 10:01:37.995061 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8117 10:01:37.998965 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8118 10:01:38.001703 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8119 10:01:38.005344 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8120 10:01:38.005851
8121 10:01:38.006179
8122 10:01:38.007929 ==
8123 10:01:38.011122 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 10:01:38.014434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 10:01:38.014923 ==
8126 10:01:38.015282
8127 10:01:38.015615
8128 10:01:38.017809 TX Vref Scan disable
8129 10:01:38.018260 == TX Byte 0 ==
8130 10:01:38.024597 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8131 10:01:38.027491 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8132 10:01:38.027948 == TX Byte 1 ==
8133 10:01:38.034751 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8134 10:01:38.037480 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8135 10:01:38.037917 ==
8136 10:01:38.041017 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 10:01:38.044541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 10:01:38.044956 ==
8139 10:01:38.058657
8140 10:01:38.061619 TX Vref early break, caculate TX vref
8141 10:01:38.065176 TX Vref=16, minBit 2, minWin=21, winSum=377
8142 10:01:38.068501 TX Vref=18, minBit 0, minWin=23, winSum=388
8143 10:01:38.071536 TX Vref=20, minBit 0, minWin=23, winSum=394
8144 10:01:38.074911 TX Vref=22, minBit 0, minWin=24, winSum=401
8145 10:01:38.078183 TX Vref=24, minBit 2, minWin=24, winSum=409
8146 10:01:38.084883 TX Vref=26, minBit 0, minWin=25, winSum=413
8147 10:01:38.087956 TX Vref=28, minBit 0, minWin=25, winSum=414
8148 10:01:38.091303 TX Vref=30, minBit 1, minWin=24, winSum=405
8149 10:01:38.095013 TX Vref=32, minBit 1, minWin=23, winSum=393
8150 10:01:38.097676 TX Vref=34, minBit 1, minWin=22, winSum=385
8151 10:01:38.104302 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8152 10:01:38.104691
8153 10:01:38.107853 Final TX Range 0 Vref 28
8154 10:01:38.108308
8155 10:01:38.108654 ==
8156 10:01:38.110864 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 10:01:38.114344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 10:01:38.114785 ==
8159 10:01:38.115114
8160 10:01:38.115339
8161 10:01:38.117884 TX Vref Scan disable
8162 10:01:38.124296 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8163 10:01:38.124680 == TX Byte 0 ==
8164 10:01:38.127812 u2DelayCellOfst[0]=11 cells (3 PI)
8165 10:01:38.130758 u2DelayCellOfst[1]=18 cells (5 PI)
8166 10:01:38.134255 u2DelayCellOfst[2]=11 cells (3 PI)
8167 10:01:38.137684 u2DelayCellOfst[3]=11 cells (3 PI)
8168 10:01:38.140679 u2DelayCellOfst[4]=7 cells (2 PI)
8169 10:01:38.144099 u2DelayCellOfst[5]=0 cells (0 PI)
8170 10:01:38.147573 u2DelayCellOfst[6]=14 cells (4 PI)
8171 10:01:38.150645 u2DelayCellOfst[7]=18 cells (5 PI)
8172 10:01:38.153753 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8173 10:01:38.157275 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8174 10:01:38.160681 == TX Byte 1 ==
8175 10:01:38.163790 u2DelayCellOfst[8]=0 cells (0 PI)
8176 10:01:38.164081 u2DelayCellOfst[9]=3 cells (1 PI)
8177 10:01:38.167326 u2DelayCellOfst[10]=7 cells (2 PI)
8178 10:01:38.170798 u2DelayCellOfst[11]=3 cells (1 PI)
8179 10:01:38.174071 u2DelayCellOfst[12]=11 cells (3 PI)
8180 10:01:38.177482 u2DelayCellOfst[13]=11 cells (3 PI)
8181 10:01:38.180385 u2DelayCellOfst[14]=18 cells (5 PI)
8182 10:01:38.183341 u2DelayCellOfst[15]=11 cells (3 PI)
8183 10:01:38.190077 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8184 10:01:38.193578 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8185 10:01:38.193871 DramC Write-DBI on
8186 10:01:38.196594 ==
8187 10:01:38.196886 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 10:01:38.203460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 10:01:38.203754 ==
8190 10:01:38.203987
8191 10:01:38.204201
8192 10:01:38.206560 TX Vref Scan disable
8193 10:01:38.206864 == TX Byte 0 ==
8194 10:01:38.213004 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8195 10:01:38.213393 == TX Byte 1 ==
8196 10:01:38.216451 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8197 10:01:38.220127 DramC Write-DBI off
8198 10:01:38.220592
8199 10:01:38.220893 [DATLAT]
8200 10:01:38.223324 Freq=1600, CH0 RK1
8201 10:01:38.223701
8202 10:01:38.224001 DATLAT Default: 0xf
8203 10:01:38.226338 0, 0xFFFF, sum = 0
8204 10:01:38.226748 1, 0xFFFF, sum = 0
8205 10:01:38.229805 2, 0xFFFF, sum = 0
8206 10:01:38.230184 3, 0xFFFF, sum = 0
8207 10:01:38.233149 4, 0xFFFF, sum = 0
8208 10:01:38.236647 5, 0xFFFF, sum = 0
8209 10:01:38.237028 6, 0xFFFF, sum = 0
8210 10:01:38.239342 7, 0xFFFF, sum = 0
8211 10:01:38.239722 8, 0xFFFF, sum = 0
8212 10:01:38.242875 9, 0xFFFF, sum = 0
8213 10:01:38.243255 10, 0xFFFF, sum = 0
8214 10:01:38.246165 11, 0xFFFF, sum = 0
8215 10:01:38.246545 12, 0xFFFF, sum = 0
8216 10:01:38.249203 13, 0xFFFF, sum = 0
8217 10:01:38.249599 14, 0x0, sum = 1
8218 10:01:38.253343 15, 0x0, sum = 2
8219 10:01:38.253829 16, 0x0, sum = 3
8220 10:01:38.255713 17, 0x0, sum = 4
8221 10:01:38.256093 best_step = 15
8222 10:01:38.256391
8223 10:01:38.256669 ==
8224 10:01:38.259333 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 10:01:38.265797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 10:01:38.266176 ==
8227 10:01:38.266475 RX Vref Scan: 0
8228 10:01:38.266813
8229 10:01:38.269015 RX Vref 0 -> 0, step: 1
8230 10:01:38.269389
8231 10:01:38.272223 RX Delay 11 -> 252, step: 4
8232 10:01:38.275812 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8233 10:01:38.279318 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8234 10:01:38.282523 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8235 10:01:38.289003 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8236 10:01:38.292643 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8237 10:01:38.295418 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8238 10:01:38.298926 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8239 10:01:38.301832 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8240 10:01:38.309018 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8241 10:01:38.312188 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8242 10:01:38.315238 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8243 10:01:38.318746 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8244 10:01:38.325774 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8245 10:01:38.328414 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8246 10:01:38.331833 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8247 10:01:38.334892 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8248 10:01:38.335347 ==
8249 10:01:38.338338 Dram Type= 6, Freq= 0, CH_0, rank 1
8250 10:01:38.344857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 10:01:38.345312 ==
8252 10:01:38.345676 DQS Delay:
8253 10:01:38.346009 DQS0 = 0, DQS1 = 0
8254 10:01:38.348263 DQM Delay:
8255 10:01:38.348713 DQM0 = 130, DQM1 = 125
8256 10:01:38.351529 DQ Delay:
8257 10:01:38.355135 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =126
8258 10:01:38.358401 DQ4 =130, DQ5 =120, DQ6 =140, DQ7 =140
8259 10:01:38.361563 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8260 10:01:38.364997 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =134
8261 10:01:38.365404
8262 10:01:38.365730
8263 10:01:38.366030
8264 10:01:38.368283 [DramC_TX_OE_Calibration] TA2
8265 10:01:38.371376 Original DQ_B0 (3 6) =30, OEN = 27
8266 10:01:38.374913 Original DQ_B1 (3 6) =30, OEN = 27
8267 10:01:38.377864 24, 0x0, End_B0=24 End_B1=24
8268 10:01:38.378283 25, 0x0, End_B0=25 End_B1=25
8269 10:01:38.380913 26, 0x0, End_B0=26 End_B1=26
8270 10:01:38.384670 27, 0x0, End_B0=27 End_B1=27
8271 10:01:38.387573 28, 0x0, End_B0=28 End_B1=28
8272 10:01:38.391354 29, 0x0, End_B0=29 End_B1=29
8273 10:01:38.391771 30, 0x0, End_B0=30 End_B1=30
8274 10:01:38.394635 31, 0x4141, End_B0=30 End_B1=30
8275 10:01:38.397672 Byte0 end_step=30 best_step=27
8276 10:01:38.401374 Byte1 end_step=30 best_step=27
8277 10:01:38.404394 Byte0 TX OE(2T, 0.5T) = (3, 3)
8278 10:01:38.407442 Byte1 TX OE(2T, 0.5T) = (3, 3)
8279 10:01:38.407853
8280 10:01:38.408175
8281 10:01:38.414421 [DQSOSCAuto] RK1, (LSB)MR18= 0x2306, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
8282 10:01:38.418064 CH0 RK1: MR19=303, MR18=2306
8283 10:01:38.424984 CH0_RK1: MR19=0x303, MR18=0x2306, DQSOSC=392, MR23=63, INC=24, DEC=16
8284 10:01:38.427425 [RxdqsGatingPostProcess] freq 1600
8285 10:01:38.430676 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8286 10:01:38.434162 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 10:01:38.437412 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 10:01:38.440570 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 10:01:38.443904 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 10:01:38.447157 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 10:01:38.450761 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 10:01:38.454118 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 10:01:38.457236 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 10:01:38.460496 Pre-setting of DQS Precalculation
8295 10:01:38.464134 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8296 10:01:38.464564 ==
8297 10:01:38.466931 Dram Type= 6, Freq= 0, CH_1, rank 0
8298 10:01:38.473539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 10:01:38.473961 ==
8300 10:01:38.476992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8301 10:01:38.483877 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8302 10:01:38.487137 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8303 10:01:38.493591 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8304 10:01:38.500956 [CA 0] Center 41 (12~71) winsize 60
8305 10:01:38.504169 [CA 1] Center 42 (12~72) winsize 61
8306 10:01:38.507867 [CA 2] Center 37 (8~66) winsize 59
8307 10:01:38.511194 [CA 3] Center 36 (7~65) winsize 59
8308 10:01:38.513946 [CA 4] Center 37 (8~66) winsize 59
8309 10:01:38.517992 [CA 5] Center 36 (7~66) winsize 60
8310 10:01:38.518497
8311 10:01:38.521128 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8312 10:01:38.521629
8313 10:01:38.527477 [CATrainingPosCal] consider 1 rank data
8314 10:01:38.527981 u2DelayCellTimex100 = 262/100 ps
8315 10:01:38.534099 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8316 10:01:38.537415 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8317 10:01:38.540562 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8318 10:01:38.544166 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8319 10:01:38.547239 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 10:01:38.550725 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8321 10:01:38.551274
8322 10:01:38.553876 CA PerBit enable=1, Macro0, CA PI delay=36
8323 10:01:38.554417
8324 10:01:38.557286 [CBTSetCACLKResult] CA Dly = 36
8325 10:01:38.560738 CS Dly: 10 (0~41)
8326 10:01:38.563786 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8327 10:01:38.567004 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8328 10:01:38.567455 ==
8329 10:01:38.570441 Dram Type= 6, Freq= 0, CH_1, rank 1
8330 10:01:38.576835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 10:01:38.577389 ==
8332 10:01:38.579819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8333 10:01:38.586570 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8334 10:01:38.589948 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8335 10:01:38.596536 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8336 10:01:38.604149 [CA 0] Center 43 (14~72) winsize 59
8337 10:01:38.607709 [CA 1] Center 43 (13~73) winsize 61
8338 10:01:38.611154 [CA 2] Center 38 (9~67) winsize 59
8339 10:01:38.614133 [CA 3] Center 37 (8~67) winsize 60
8340 10:01:38.617694 [CA 4] Center 37 (8~67) winsize 60
8341 10:01:38.620967 [CA 5] Center 37 (8~66) winsize 59
8342 10:01:38.621419
8343 10:01:38.624205 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8344 10:01:38.624650
8345 10:01:38.627901 [CATrainingPosCal] consider 2 rank data
8346 10:01:38.631184 u2DelayCellTimex100 = 262/100 ps
8347 10:01:38.637719 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8348 10:01:38.640660 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8349 10:01:38.644043 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8350 10:01:38.647404 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8351 10:01:38.650960 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8352 10:01:38.653986 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8353 10:01:38.654538
8354 10:01:38.657533 CA PerBit enable=1, Macro0, CA PI delay=36
8355 10:01:38.658085
8356 10:01:38.660602 [CBTSetCACLKResult] CA Dly = 36
8357 10:01:38.663555 CS Dly: 11 (0~44)
8358 10:01:38.667142 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8359 10:01:38.670655 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8360 10:01:38.671108
8361 10:01:38.674074 ----->DramcWriteLeveling(PI) begin...
8362 10:01:38.674533 ==
8363 10:01:38.676968 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 10:01:38.683522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 10:01:38.683995 ==
8366 10:01:38.686955 Write leveling (Byte 0): 24 => 24
8367 10:01:38.690639 Write leveling (Byte 1): 27 => 27
8368 10:01:38.691249 DramcWriteLeveling(PI) end<-----
8369 10:01:38.691710
8370 10:01:38.693167 ==
8371 10:01:38.696786 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 10:01:38.700067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 10:01:38.700668 ==
8374 10:01:38.703321 [Gating] SW mode calibration
8375 10:01:38.710184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8376 10:01:38.713813 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8377 10:01:38.719969 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 10:01:38.723240 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 10:01:38.726425 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8380 10:01:38.732948 1 4 12 | B1->B0 | 2d2d 3131 | 0 1 | (1 1) (1 1)
8381 10:01:38.736624 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 10:01:38.739722 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 10:01:38.746193 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 10:01:38.749394 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 10:01:38.752663 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 10:01:38.759669 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 10:01:38.762884 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8388 10:01:38.766098 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
8389 10:01:38.772549 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8390 10:01:38.776100 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 10:01:38.779382 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 10:01:38.786016 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 10:01:38.789151 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 10:01:38.792442 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 10:01:38.798722 1 6 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8396 10:01:38.802103 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8397 10:01:38.805460 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 10:01:38.812080 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 10:01:38.815766 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 10:01:38.818808 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 10:01:38.825592 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 10:01:38.828832 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 10:01:38.832089 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 10:01:38.839106 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8405 10:01:38.841729 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 10:01:38.845287 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 10:01:38.851716 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 10:01:38.855334 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 10:01:38.858968 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 10:01:38.865243 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 10:01:38.868593 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 10:01:38.871619 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 10:01:38.878679 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 10:01:38.881544 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 10:01:38.884989 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 10:01:38.891473 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 10:01:38.894685 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 10:01:38.898349 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 10:01:38.904363 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8420 10:01:38.907955 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8421 10:01:38.911195 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 10:01:38.914416 Total UI for P1: 0, mck2ui 16
8423 10:01:38.917820 best dqsien dly found for B0: ( 1, 9, 10)
8424 10:01:38.921083 Total UI for P1: 0, mck2ui 16
8425 10:01:38.924077 best dqsien dly found for B1: ( 1, 9, 12)
8426 10:01:38.927171 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8427 10:01:38.930936 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8428 10:01:38.931251
8429 10:01:38.937426 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8430 10:01:38.941145 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8431 10:01:38.943982 [Gating] SW calibration Done
8432 10:01:38.944275 ==
8433 10:01:38.947407 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 10:01:38.950463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 10:01:38.950860 ==
8436 10:01:38.951138 RX Vref Scan: 0
8437 10:01:38.954044
8438 10:01:38.954277 RX Vref 0 -> 0, step: 1
8439 10:01:38.954452
8440 10:01:38.957326 RX Delay 0 -> 252, step: 8
8441 10:01:38.960763 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8442 10:01:38.963822 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8443 10:01:38.970836 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8444 10:01:38.973660 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8445 10:01:38.976976 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8446 10:01:38.980132 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8447 10:01:38.983497 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8448 10:01:38.989949 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8449 10:01:38.993383 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8450 10:01:38.996789 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8451 10:01:39.000134 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8452 10:01:39.003955 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8453 10:01:39.010481 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8454 10:01:39.014076 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8455 10:01:39.017601 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8456 10:01:39.020368 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8457 10:01:39.020787 ==
8458 10:01:39.023722 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 10:01:39.030245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 10:01:39.030722 ==
8461 10:01:39.031065 DQS Delay:
8462 10:01:39.033135 DQS0 = 0, DQS1 = 0
8463 10:01:39.033544 DQM Delay:
8464 10:01:39.037086 DQM0 = 138, DQM1 = 130
8465 10:01:39.037500 DQ Delay:
8466 10:01:39.039646 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8467 10:01:39.042962 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8468 10:01:39.046313 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8469 10:01:39.049547 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8470 10:01:39.049963
8471 10:01:39.050288
8472 10:01:39.050838 ==
8473 10:01:39.053309 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 10:01:39.059654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 10:01:39.060103 ==
8476 10:01:39.060477
8477 10:01:39.060848
8478 10:01:39.061306 TX Vref Scan disable
8479 10:01:39.063018 == TX Byte 0 ==
8480 10:01:39.066372 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8481 10:01:39.073133 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8482 10:01:39.073621 == TX Byte 1 ==
8483 10:01:39.076585 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8484 10:01:39.082985 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8485 10:01:39.083401 ==
8486 10:01:39.086318 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 10:01:39.089410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 10:01:39.089827 ==
8489 10:01:39.102077
8490 10:01:39.105339 TX Vref early break, caculate TX vref
8491 10:01:39.108451 TX Vref=16, minBit 0, minWin=22, winSum=374
8492 10:01:39.111766 TX Vref=18, minBit 0, minWin=23, winSum=386
8493 10:01:39.115220 TX Vref=20, minBit 0, minWin=24, winSum=393
8494 10:01:39.118076 TX Vref=22, minBit 0, minWin=24, winSum=403
8495 10:01:39.121254 TX Vref=24, minBit 0, minWin=24, winSum=413
8496 10:01:39.128391 TX Vref=26, minBit 0, minWin=25, winSum=420
8497 10:01:39.131337 TX Vref=28, minBit 0, minWin=25, winSum=418
8498 10:01:39.134684 TX Vref=30, minBit 1, minWin=23, winSum=407
8499 10:01:39.137860 TX Vref=32, minBit 5, minWin=23, winSum=400
8500 10:01:39.141566 TX Vref=34, minBit 0, minWin=23, winSum=391
8501 10:01:39.148026 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8502 10:01:39.148321
8503 10:01:39.151233 Final TX Range 0 Vref 26
8504 10:01:39.151525
8505 10:01:39.151760 ==
8506 10:01:39.154550 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 10:01:39.157481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 10:01:39.157833 ==
8509 10:01:39.158077
8510 10:01:39.158296
8511 10:01:39.160752 TX Vref Scan disable
8512 10:01:39.168113 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8513 10:01:39.168408 == TX Byte 0 ==
8514 10:01:39.170860 u2DelayCellOfst[0]=18 cells (5 PI)
8515 10:01:39.174639 u2DelayCellOfst[1]=14 cells (4 PI)
8516 10:01:39.178043 u2DelayCellOfst[2]=0 cells (0 PI)
8517 10:01:39.180874 u2DelayCellOfst[3]=7 cells (2 PI)
8518 10:01:39.184516 u2DelayCellOfst[4]=11 cells (3 PI)
8519 10:01:39.187333 u2DelayCellOfst[5]=26 cells (7 PI)
8520 10:01:39.191156 u2DelayCellOfst[6]=22 cells (6 PI)
8521 10:01:39.193738 u2DelayCellOfst[7]=7 cells (2 PI)
8522 10:01:39.197276 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8523 10:01:39.200571 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8524 10:01:39.203612 == TX Byte 1 ==
8525 10:01:39.206715 u2DelayCellOfst[8]=0 cells (0 PI)
8526 10:01:39.209929 u2DelayCellOfst[9]=3 cells (1 PI)
8527 10:01:39.213363 u2DelayCellOfst[10]=11 cells (3 PI)
8528 10:01:39.216867 u2DelayCellOfst[11]=3 cells (1 PI)
8529 10:01:39.216948 u2DelayCellOfst[12]=14 cells (4 PI)
8530 10:01:39.219791 u2DelayCellOfst[13]=18 cells (5 PI)
8531 10:01:39.223000 u2DelayCellOfst[14]=18 cells (5 PI)
8532 10:01:39.226360 u2DelayCellOfst[15]=18 cells (5 PI)
8533 10:01:39.232818 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8534 10:01:39.236250 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8535 10:01:39.236330 DramC Write-DBI on
8536 10:01:39.239502 ==
8537 10:01:39.243157 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 10:01:39.246314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 10:01:39.246395 ==
8540 10:01:39.246458
8541 10:01:39.246518
8542 10:01:39.249318 TX Vref Scan disable
8543 10:01:39.249439 == TX Byte 0 ==
8544 10:01:39.256408 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8545 10:01:39.256502 == TX Byte 1 ==
8546 10:01:39.259918 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8547 10:01:39.262704 DramC Write-DBI off
8548 10:01:39.262796
8549 10:01:39.262870 [DATLAT]
8550 10:01:39.266084 Freq=1600, CH1 RK0
8551 10:01:39.266184
8552 10:01:39.266264 DATLAT Default: 0xf
8553 10:01:39.269362 0, 0xFFFF, sum = 0
8554 10:01:39.269472 1, 0xFFFF, sum = 0
8555 10:01:39.272861 2, 0xFFFF, sum = 0
8556 10:01:39.273047 3, 0xFFFF, sum = 0
8557 10:01:39.276225 4, 0xFFFF, sum = 0
8558 10:01:39.279674 5, 0xFFFF, sum = 0
8559 10:01:39.279880 6, 0xFFFF, sum = 0
8560 10:01:39.282537 7, 0xFFFF, sum = 0
8561 10:01:39.282695 8, 0xFFFF, sum = 0
8562 10:01:39.286102 9, 0xFFFF, sum = 0
8563 10:01:39.286332 10, 0xFFFF, sum = 0
8564 10:01:39.289260 11, 0xFFFF, sum = 0
8565 10:01:39.289476 12, 0xFFFF, sum = 0
8566 10:01:39.292559 13, 0xFFFF, sum = 0
8567 10:01:39.292818 14, 0x0, sum = 1
8568 10:01:39.295872 15, 0x0, sum = 2
8569 10:01:39.296081 16, 0x0, sum = 3
8570 10:01:39.299548 17, 0x0, sum = 4
8571 10:01:39.299874 best_step = 15
8572 10:01:39.300079
8573 10:01:39.300262 ==
8574 10:01:39.302675 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 10:01:39.309366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 10:01:39.309918 ==
8577 10:01:39.310357 RX Vref Scan: 1
8578 10:01:39.310731
8579 10:01:39.312087 Set Vref Range= 24 -> 127
8580 10:01:39.312464
8581 10:01:39.315411 RX Vref 24 -> 127, step: 1
8582 10:01:39.315930
8583 10:01:39.316329 RX Delay 19 -> 252, step: 4
8584 10:01:39.318791
8585 10:01:39.319244 Set Vref, RX VrefLevel [Byte0]: 24
8586 10:01:39.322732 [Byte1]: 24
8587 10:01:39.326572
8588 10:01:39.327172 Set Vref, RX VrefLevel [Byte0]: 25
8589 10:01:39.329739 [Byte1]: 25
8590 10:01:39.333956
8591 10:01:39.334407 Set Vref, RX VrefLevel [Byte0]: 26
8592 10:01:39.337431 [Byte1]: 26
8593 10:01:39.341755
8594 10:01:39.342311 Set Vref, RX VrefLevel [Byte0]: 27
8595 10:01:39.345073 [Byte1]: 27
8596 10:01:39.349770
8597 10:01:39.350323 Set Vref, RX VrefLevel [Byte0]: 28
8598 10:01:39.352412 [Byte1]: 28
8599 10:01:39.357379
8600 10:01:39.357926 Set Vref, RX VrefLevel [Byte0]: 29
8601 10:01:39.360668 [Byte1]: 29
8602 10:01:39.364004
8603 10:01:39.364458 Set Vref, RX VrefLevel [Byte0]: 30
8604 10:01:39.367363 [Byte1]: 30
8605 10:01:39.371621
8606 10:01:39.372071 Set Vref, RX VrefLevel [Byte0]: 31
8607 10:01:39.375153 [Byte1]: 31
8608 10:01:39.379940
8609 10:01:39.380494 Set Vref, RX VrefLevel [Byte0]: 32
8610 10:01:39.382582 [Byte1]: 32
8611 10:01:39.387236
8612 10:01:39.387785 Set Vref, RX VrefLevel [Byte0]: 33
8613 10:01:39.390492 [Byte1]: 33
8614 10:01:39.394999
8615 10:01:39.395541 Set Vref, RX VrefLevel [Byte0]: 34
8616 10:01:39.398296 [Byte1]: 34
8617 10:01:39.402448
8618 10:01:39.405426 Set Vref, RX VrefLevel [Byte0]: 35
8619 10:01:39.408445 [Byte1]: 35
8620 10:01:39.408899
8621 10:01:39.412079 Set Vref, RX VrefLevel [Byte0]: 36
8622 10:01:39.415465 [Byte1]: 36
8623 10:01:39.416009
8624 10:01:39.418923 Set Vref, RX VrefLevel [Byte0]: 37
8625 10:01:39.422313 [Byte1]: 37
8626 10:01:39.422911
8627 10:01:39.425901 Set Vref, RX VrefLevel [Byte0]: 38
8628 10:01:39.428630 [Byte1]: 38
8629 10:01:39.432477
8630 10:01:39.433153 Set Vref, RX VrefLevel [Byte0]: 39
8631 10:01:39.435803 [Byte1]: 39
8632 10:01:39.440463
8633 10:01:39.441010 Set Vref, RX VrefLevel [Byte0]: 40
8634 10:01:39.443368 [Byte1]: 40
8635 10:01:39.447607
8636 10:01:39.448161 Set Vref, RX VrefLevel [Byte0]: 41
8637 10:01:39.450795 [Byte1]: 41
8638 10:01:39.455439
8639 10:01:39.455988 Set Vref, RX VrefLevel [Byte0]: 42
8640 10:01:39.458795 [Byte1]: 42
8641 10:01:39.462707
8642 10:01:39.463278 Set Vref, RX VrefLevel [Byte0]: 43
8643 10:01:39.466063 [Byte1]: 43
8644 10:01:39.470561
8645 10:01:39.471058 Set Vref, RX VrefLevel [Byte0]: 44
8646 10:01:39.473427 [Byte1]: 44
8647 10:01:39.477730
8648 10:01:39.478211 Set Vref, RX VrefLevel [Byte0]: 45
8649 10:01:39.481451 [Byte1]: 45
8650 10:01:39.486041
8651 10:01:39.486589 Set Vref, RX VrefLevel [Byte0]: 46
8652 10:01:39.488546 [Byte1]: 46
8653 10:01:39.493071
8654 10:01:39.493523 Set Vref, RX VrefLevel [Byte0]: 47
8655 10:01:39.496098 [Byte1]: 47
8656 10:01:39.501112
8657 10:01:39.501659 Set Vref, RX VrefLevel [Byte0]: 48
8658 10:01:39.504110 [Byte1]: 48
8659 10:01:39.508178
8660 10:01:39.508737 Set Vref, RX VrefLevel [Byte0]: 49
8661 10:01:39.511506 [Byte1]: 49
8662 10:01:39.515644
8663 10:01:39.516097 Set Vref, RX VrefLevel [Byte0]: 50
8664 10:01:39.519102 [Byte1]: 50
8665 10:01:39.523569
8666 10:01:39.524120 Set Vref, RX VrefLevel [Byte0]: 51
8667 10:01:39.526851 [Byte1]: 51
8668 10:01:39.531208
8669 10:01:39.531762 Set Vref, RX VrefLevel [Byte0]: 52
8670 10:01:39.537417 [Byte1]: 52
8671 10:01:39.537969
8672 10:01:39.540482 Set Vref, RX VrefLevel [Byte0]: 53
8673 10:01:39.544204 [Byte1]: 53
8674 10:01:39.544754
8675 10:01:39.547759 Set Vref, RX VrefLevel [Byte0]: 54
8676 10:01:39.551127 [Byte1]: 54
8677 10:01:39.551581
8678 10:01:39.554224 Set Vref, RX VrefLevel [Byte0]: 55
8679 10:01:39.557289 [Byte1]: 55
8680 10:01:39.561330
8681 10:01:39.561898 Set Vref, RX VrefLevel [Byte0]: 56
8682 10:01:39.564725 [Byte1]: 56
8683 10:01:39.568509
8684 10:01:39.568959 Set Vref, RX VrefLevel [Byte0]: 57
8685 10:01:39.572357 [Byte1]: 57
8686 10:01:39.576932
8687 10:01:39.577478 Set Vref, RX VrefLevel [Byte0]: 58
8688 10:01:39.579634 [Byte1]: 58
8689 10:01:39.583905
8690 10:01:39.584451 Set Vref, RX VrefLevel [Byte0]: 59
8691 10:01:39.587039 [Byte1]: 59
8692 10:01:39.591813
8693 10:01:39.592266 Set Vref, RX VrefLevel [Byte0]: 60
8694 10:01:39.594489 [Byte1]: 60
8695 10:01:39.599116
8696 10:01:39.599572 Set Vref, RX VrefLevel [Byte0]: 61
8697 10:01:39.601964 [Byte1]: 61
8698 10:01:39.606655
8699 10:01:39.607110 Set Vref, RX VrefLevel [Byte0]: 62
8700 10:01:39.609791 [Byte1]: 62
8701 10:01:39.614258
8702 10:01:39.614750 Set Vref, RX VrefLevel [Byte0]: 63
8703 10:01:39.617490 [Byte1]: 63
8704 10:01:39.621755
8705 10:01:39.622166 Set Vref, RX VrefLevel [Byte0]: 64
8706 10:01:39.624965 [Byte1]: 64
8707 10:01:39.629535
8708 10:01:39.629946 Set Vref, RX VrefLevel [Byte0]: 65
8709 10:01:39.632781 [Byte1]: 65
8710 10:01:39.636943
8711 10:01:39.637353 Set Vref, RX VrefLevel [Byte0]: 66
8712 10:01:39.639991 [Byte1]: 66
8713 10:01:39.644424
8714 10:01:39.644836 Set Vref, RX VrefLevel [Byte0]: 67
8715 10:01:39.647750 [Byte1]: 67
8716 10:01:39.652399
8717 10:01:39.652813 Set Vref, RX VrefLevel [Byte0]: 68
8718 10:01:39.655457 [Byte1]: 68
8719 10:01:39.659467
8720 10:01:39.659889 Set Vref, RX VrefLevel [Byte0]: 69
8721 10:01:39.663203 [Byte1]: 69
8722 10:01:39.667282
8723 10:01:39.667700 Set Vref, RX VrefLevel [Byte0]: 70
8724 10:01:39.670368 [Byte1]: 70
8725 10:01:39.674801
8726 10:01:39.675261 Set Vref, RX VrefLevel [Byte0]: 71
8727 10:01:39.678141 [Byte1]: 71
8728 10:01:39.682447
8729 10:01:39.683041 Set Vref, RX VrefLevel [Byte0]: 72
8730 10:01:39.685801 [Byte1]: 72
8731 10:01:39.690034
8732 10:01:39.690581 Set Vref, RX VrefLevel [Byte0]: 73
8733 10:01:39.693452 [Byte1]: 73
8734 10:01:39.698162
8735 10:01:39.698752 Final RX Vref Byte 0 = 56 to rank0
8736 10:01:39.701014 Final RX Vref Byte 1 = 59 to rank0
8737 10:01:39.704836 Final RX Vref Byte 0 = 56 to rank1
8738 10:01:39.707951 Final RX Vref Byte 1 = 59 to rank1==
8739 10:01:39.710764 Dram Type= 6, Freq= 0, CH_1, rank 0
8740 10:01:39.717800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 10:01:39.718337 ==
8742 10:01:39.718758 DQS Delay:
8743 10:01:39.720940 DQS0 = 0, DQS1 = 0
8744 10:01:39.721543 DQM Delay:
8745 10:01:39.721918 DQM0 = 134, DQM1 = 129
8746 10:01:39.724238 DQ Delay:
8747 10:01:39.727581 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8748 10:01:39.730762 DQ4 =132, DQ5 =146, DQ6 =144, DQ7 =130
8749 10:01:39.733909 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8750 10:01:39.736715 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =138
8751 10:01:39.737165
8752 10:01:39.737525
8753 10:01:39.737858
8754 10:01:39.740600 [DramC_TX_OE_Calibration] TA2
8755 10:01:39.743873 Original DQ_B0 (3 6) =30, OEN = 27
8756 10:01:39.747016 Original DQ_B1 (3 6) =30, OEN = 27
8757 10:01:39.750494 24, 0x0, End_B0=24 End_B1=24
8758 10:01:39.753724 25, 0x0, End_B0=25 End_B1=25
8759 10:01:39.754206 26, 0x0, End_B0=26 End_B1=26
8760 10:01:39.756783 27, 0x0, End_B0=27 End_B1=27
8761 10:01:39.760066 28, 0x0, End_B0=28 End_B1=28
8762 10:01:39.763636 29, 0x0, End_B0=29 End_B1=29
8763 10:01:39.764111 30, 0x0, End_B0=30 End_B1=30
8764 10:01:39.767087 31, 0x5151, End_B0=30 End_B1=30
8765 10:01:39.769906 Byte0 end_step=30 best_step=27
8766 10:01:39.773237 Byte1 end_step=30 best_step=27
8767 10:01:39.777346 Byte0 TX OE(2T, 0.5T) = (3, 3)
8768 10:01:39.780196 Byte1 TX OE(2T, 0.5T) = (3, 3)
8769 10:01:39.780670
8770 10:01:39.781150
8771 10:01:39.786990 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c12, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
8772 10:01:39.790129 CH1 RK0: MR19=303, MR18=1C12
8773 10:01:39.796560 CH1_RK0: MR19=0x303, MR18=0x1C12, DQSOSC=395, MR23=63, INC=23, DEC=15
8774 10:01:39.797131
8775 10:01:39.800157 ----->DramcWriteLeveling(PI) begin...
8776 10:01:39.800726 ==
8777 10:01:39.803549 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 10:01:39.806796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 10:01:39.807267 ==
8780 10:01:39.810058 Write leveling (Byte 0): 24 => 24
8781 10:01:39.812978 Write leveling (Byte 1): 26 => 26
8782 10:01:39.816399 DramcWriteLeveling(PI) end<-----
8783 10:01:39.816867
8784 10:01:39.817340 ==
8785 10:01:39.819984 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 10:01:39.823459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 10:01:39.826441 ==
8788 10:01:39.827071 [Gating] SW mode calibration
8789 10:01:39.833030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8790 10:01:39.839369 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8791 10:01:39.842698 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 10:01:39.849431 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 10:01:39.852895 1 4 8 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
8794 10:01:39.856259 1 4 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8795 10:01:39.862710 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8796 10:01:39.866104 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 10:01:39.869338 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 10:01:39.875774 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 10:01:39.879052 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 10:01:39.882581 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8801 10:01:39.888931 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8802 10:01:39.892572 1 5 12 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 0)
8803 10:01:39.895803 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8804 10:01:39.902372 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 10:01:39.905469 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 10:01:39.909196 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 10:01:39.915579 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 10:01:39.919192 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 10:01:39.922768 1 6 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8810 10:01:39.928519 1 6 12 | B1->B0 | 4646 2727 | 0 0 | (0 0) (0 0)
8811 10:01:39.931984 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 10:01:39.935402 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 10:01:39.942286 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 10:01:39.945477 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 10:01:39.948886 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 10:01:39.954939 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 10:01:39.959011 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8818 10:01:39.962002 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8819 10:01:39.968601 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8820 10:01:39.971740 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 10:01:39.975515 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 10:01:39.981688 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 10:01:39.985234 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 10:01:39.988722 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 10:01:39.995172 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 10:01:39.998008 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 10:01:40.001288 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 10:01:40.008047 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 10:01:40.011638 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 10:01:40.015195 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 10:01:40.021627 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 10:01:40.025036 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 10:01:40.027952 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8834 10:01:40.035067 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8835 10:01:40.037729 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 10:01:40.041270 Total UI for P1: 0, mck2ui 16
8837 10:01:40.044633 best dqsien dly found for B0: ( 1, 9, 12)
8838 10:01:40.047579 Total UI for P1: 0, mck2ui 16
8839 10:01:40.051100 best dqsien dly found for B1: ( 1, 9, 10)
8840 10:01:40.054309 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8841 10:01:40.058104 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8842 10:01:40.058645
8843 10:01:40.060704 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8844 10:01:40.064184 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8845 10:01:40.067572 [Gating] SW calibration Done
8846 10:01:40.068082 ==
8847 10:01:40.070530 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 10:01:40.074196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 10:01:40.077141 ==
8850 10:01:40.077645 RX Vref Scan: 0
8851 10:01:40.077969
8852 10:01:40.080430 RX Vref 0 -> 0, step: 1
8853 10:01:40.080837
8854 10:01:40.081159 RX Delay 0 -> 252, step: 8
8855 10:01:40.087507 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8856 10:01:40.090630 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8857 10:01:40.094150 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8858 10:01:40.097405 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8859 10:01:40.100972 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8860 10:01:40.107279 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8861 10:01:40.110751 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8862 10:01:40.114144 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8863 10:01:40.117169 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8864 10:01:40.120908 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8865 10:01:40.126858 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8866 10:01:40.130684 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8867 10:01:40.133755 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8868 10:01:40.137058 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8869 10:01:40.144056 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8870 10:01:40.147104 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8871 10:01:40.147520 ==
8872 10:01:40.150088 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 10:01:40.153775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 10:01:40.154293 ==
8875 10:01:40.157041 DQS Delay:
8876 10:01:40.157554 DQS0 = 0, DQS1 = 0
8877 10:01:40.157887 DQM Delay:
8878 10:01:40.160309 DQM0 = 136, DQM1 = 129
8879 10:01:40.160812 DQ Delay:
8880 10:01:40.163703 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8881 10:01:40.166427 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8882 10:01:40.173551 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8883 10:01:40.176719 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8884 10:01:40.177184
8885 10:01:40.177520
8886 10:01:40.177825 ==
8887 10:01:40.179764 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 10:01:40.183088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 10:01:40.183500 ==
8890 10:01:40.183826
8891 10:01:40.184125
8892 10:01:40.186400 TX Vref Scan disable
8893 10:01:40.189587 == TX Byte 0 ==
8894 10:01:40.192721 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8895 10:01:40.196539 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8896 10:01:40.199797 == TX Byte 1 ==
8897 10:01:40.202696 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8898 10:01:40.206412 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8899 10:01:40.206862 ==
8900 10:01:40.209289 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 10:01:40.212435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 10:01:40.215881 ==
8903 10:01:40.228366
8904 10:01:40.231591 TX Vref early break, caculate TX vref
8905 10:01:40.235061 TX Vref=16, minBit 5, minWin=22, winSum=382
8906 10:01:40.238101 TX Vref=18, minBit 0, minWin=23, winSum=392
8907 10:01:40.241798 TX Vref=20, minBit 1, minWin=23, winSum=402
8908 10:01:40.244710 TX Vref=22, minBit 1, minWin=24, winSum=409
8909 10:01:40.247984 TX Vref=24, minBit 0, minWin=25, winSum=421
8910 10:01:40.254497 TX Vref=26, minBit 0, minWin=25, winSum=422
8911 10:01:40.257603 TX Vref=28, minBit 0, minWin=24, winSum=421
8912 10:01:40.261443 TX Vref=30, minBit 1, minWin=24, winSum=411
8913 10:01:40.264600 TX Vref=32, minBit 0, minWin=23, winSum=406
8914 10:01:40.268401 TX Vref=34, minBit 0, minWin=24, winSum=403
8915 10:01:40.270908 TX Vref=36, minBit 0, minWin=22, winSum=390
8916 10:01:40.278073 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8917 10:01:40.278683
8918 10:01:40.281475 Final TX Range 0 Vref 26
8919 10:01:40.282028
8920 10:01:40.282391 ==
8921 10:01:40.284489 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 10:01:40.288204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 10:01:40.288754 ==
8924 10:01:40.290856
8925 10:01:40.291305
8926 10:01:40.291663 TX Vref Scan disable
8927 10:01:40.297750 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8928 10:01:40.298302 == TX Byte 0 ==
8929 10:01:40.300554 u2DelayCellOfst[0]=22 cells (6 PI)
8930 10:01:40.303964 u2DelayCellOfst[1]=14 cells (4 PI)
8931 10:01:40.307609 u2DelayCellOfst[2]=0 cells (0 PI)
8932 10:01:40.310960 u2DelayCellOfst[3]=11 cells (3 PI)
8933 10:01:40.314398 u2DelayCellOfst[4]=11 cells (3 PI)
8934 10:01:40.317139 u2DelayCellOfst[5]=22 cells (6 PI)
8935 10:01:40.320635 u2DelayCellOfst[6]=22 cells (6 PI)
8936 10:01:40.324152 u2DelayCellOfst[7]=11 cells (3 PI)
8937 10:01:40.327551 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8938 10:01:40.330416 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8939 10:01:40.334120 == TX Byte 1 ==
8940 10:01:40.337034 u2DelayCellOfst[8]=0 cells (0 PI)
8941 10:01:40.340325 u2DelayCellOfst[9]=3 cells (1 PI)
8942 10:01:40.343896 u2DelayCellOfst[10]=11 cells (3 PI)
8943 10:01:40.346974 u2DelayCellOfst[11]=7 cells (2 PI)
8944 10:01:40.350052 u2DelayCellOfst[12]=18 cells (5 PI)
8945 10:01:40.353697 u2DelayCellOfst[13]=14 cells (4 PI)
8946 10:01:40.357391 u2DelayCellOfst[14]=18 cells (5 PI)
8947 10:01:40.357953 u2DelayCellOfst[15]=18 cells (5 PI)
8948 10:01:40.363737 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8949 10:01:40.366967 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8950 10:01:40.370125 DramC Write-DBI on
8951 10:01:40.370711 ==
8952 10:01:40.373325 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 10:01:40.376945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 10:01:40.377559 ==
8955 10:01:40.377927
8956 10:01:40.378262
8957 10:01:40.380119 TX Vref Scan disable
8958 10:01:40.380642 == TX Byte 0 ==
8959 10:01:40.386820 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8960 10:01:40.387276 == TX Byte 1 ==
8961 10:01:40.390378 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8962 10:01:40.393074 DramC Write-DBI off
8963 10:01:40.393524
8964 10:01:40.393880 [DATLAT]
8965 10:01:40.396644 Freq=1600, CH1 RK1
8966 10:01:40.397204
8967 10:01:40.397569 DATLAT Default: 0xf
8968 10:01:40.400053 0, 0xFFFF, sum = 0
8969 10:01:40.400517 1, 0xFFFF, sum = 0
8970 10:01:40.403145 2, 0xFFFF, sum = 0
8971 10:01:40.406554 3, 0xFFFF, sum = 0
8972 10:01:40.407052 4, 0xFFFF, sum = 0
8973 10:01:40.409739 5, 0xFFFF, sum = 0
8974 10:01:40.410197 6, 0xFFFF, sum = 0
8975 10:01:40.412744 7, 0xFFFF, sum = 0
8976 10:01:40.413204 8, 0xFFFF, sum = 0
8977 10:01:40.415928 9, 0xFFFF, sum = 0
8978 10:01:40.416590 10, 0xFFFF, sum = 0
8979 10:01:40.419598 11, 0xFFFF, sum = 0
8980 10:01:40.420062 12, 0xFFFF, sum = 0
8981 10:01:40.422750 13, 0xFFFF, sum = 0
8982 10:01:40.423214 14, 0x0, sum = 1
8983 10:01:40.426385 15, 0x0, sum = 2
8984 10:01:40.426832 16, 0x0, sum = 3
8985 10:01:40.429075 17, 0x0, sum = 4
8986 10:01:40.429494 best_step = 15
8987 10:01:40.429820
8988 10:01:40.430129 ==
8989 10:01:40.432544 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 10:01:40.439437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 10:01:40.439850 ==
8992 10:01:40.440186 RX Vref Scan: 0
8993 10:01:40.440492
8994 10:01:40.442950 RX Vref 0 -> 0, step: 1
8995 10:01:40.443456
8996 10:01:40.446219 RX Delay 11 -> 252, step: 4
8997 10:01:40.449071 iDelay=203, Bit 0, Center 138 (83 ~ 194) 112
8998 10:01:40.452617 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
8999 10:01:40.455669 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9000 10:01:40.462515 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9001 10:01:40.465580 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9002 10:01:40.468914 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9003 10:01:40.472230 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9004 10:01:40.475508 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9005 10:01:40.482105 iDelay=203, Bit 8, Center 114 (59 ~ 170) 112
9006 10:01:40.485160 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9007 10:01:40.489119 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9008 10:01:40.492269 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9009 10:01:40.498771 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9010 10:01:40.502565 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9011 10:01:40.505483 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9012 10:01:40.508599 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9013 10:01:40.509149 ==
9014 10:01:40.512054 Dram Type= 6, Freq= 0, CH_1, rank 1
9015 10:01:40.518160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9016 10:01:40.518777 ==
9017 10:01:40.519162 DQS Delay:
9018 10:01:40.521901 DQS0 = 0, DQS1 = 0
9019 10:01:40.522445 DQM Delay:
9020 10:01:40.522851 DQM0 = 134, DQM1 = 127
9021 10:01:40.525480 DQ Delay:
9022 10:01:40.528069 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9023 10:01:40.531893 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9024 10:01:40.534716 DQ8 =114, DQ9 =116, DQ10 =126, DQ11 =118
9025 10:01:40.538113 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9026 10:01:40.538567
9027 10:01:40.538965
9028 10:01:40.539296
9029 10:01:40.541402 [DramC_TX_OE_Calibration] TA2
9030 10:01:40.544876 Original DQ_B0 (3 6) =30, OEN = 27
9031 10:01:40.548282 Original DQ_B1 (3 6) =30, OEN = 27
9032 10:01:40.551230 24, 0x0, End_B0=24 End_B1=24
9033 10:01:40.554519 25, 0x0, End_B0=25 End_B1=25
9034 10:01:40.555012 26, 0x0, End_B0=26 End_B1=26
9035 10:01:40.558441 27, 0x0, End_B0=27 End_B1=27
9036 10:01:40.561722 28, 0x0, End_B0=28 End_B1=28
9037 10:01:40.564933 29, 0x0, End_B0=29 End_B1=29
9038 10:01:40.565402 30, 0x0, End_B0=30 End_B1=30
9039 10:01:40.568043 31, 0x4141, End_B0=30 End_B1=30
9040 10:01:40.571335 Byte0 end_step=30 best_step=27
9041 10:01:40.574322 Byte1 end_step=30 best_step=27
9042 10:01:40.577755 Byte0 TX OE(2T, 0.5T) = (3, 3)
9043 10:01:40.580931 Byte1 TX OE(2T, 0.5T) = (3, 3)
9044 10:01:40.581355
9045 10:01:40.581711
9046 10:01:40.588130 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9047 10:01:40.591099 CH1 RK1: MR19=303, MR18=D09
9048 10:01:40.597813 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9049 10:01:40.600717 [RxdqsGatingPostProcess] freq 1600
9050 10:01:40.604084 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9051 10:01:40.607440 best DQS0 dly(2T, 0.5T) = (1, 1)
9052 10:01:40.610581 best DQS1 dly(2T, 0.5T) = (1, 1)
9053 10:01:40.613854 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9054 10:01:40.617516 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9055 10:01:40.620822 best DQS0 dly(2T, 0.5T) = (1, 1)
9056 10:01:40.624066 best DQS1 dly(2T, 0.5T) = (1, 1)
9057 10:01:40.627123 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9058 10:01:40.630419 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9059 10:01:40.633912 Pre-setting of DQS Precalculation
9060 10:01:40.636921 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9061 10:01:40.646854 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9062 10:01:40.653406 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9063 10:01:40.653894
9064 10:01:40.654282
9065 10:01:40.656596 [Calibration Summary] 3200 Mbps
9066 10:01:40.657004 CH 0, Rank 0
9067 10:01:40.659801 SW Impedance : PASS
9068 10:01:40.660214 DUTY Scan : NO K
9069 10:01:40.663666 ZQ Calibration : PASS
9070 10:01:40.666258 Jitter Meter : NO K
9071 10:01:40.666697 CBT Training : PASS
9072 10:01:40.669953 Write leveling : PASS
9073 10:01:40.672963 RX DQS gating : PASS
9074 10:01:40.673441 RX DQ/DQS(RDDQC) : PASS
9075 10:01:40.675989 TX DQ/DQS : PASS
9076 10:01:40.679542 RX DATLAT : PASS
9077 10:01:40.679765 RX DQ/DQS(Engine): PASS
9078 10:01:40.682587 TX OE : PASS
9079 10:01:40.682834 All Pass.
9080 10:01:40.683008
9081 10:01:40.686203 CH 0, Rank 1
9082 10:01:40.686380 SW Impedance : PASS
9083 10:01:40.688988 DUTY Scan : NO K
9084 10:01:40.692661 ZQ Calibration : PASS
9085 10:01:40.692809 Jitter Meter : NO K
9086 10:01:40.695605 CBT Training : PASS
9087 10:01:40.698931 Write leveling : PASS
9088 10:01:40.699043 RX DQS gating : PASS
9089 10:01:40.702446 RX DQ/DQS(RDDQC) : PASS
9090 10:01:40.705239 TX DQ/DQS : PASS
9091 10:01:40.705398 RX DATLAT : PASS
9092 10:01:40.708795 RX DQ/DQS(Engine): PASS
9093 10:01:40.712463 TX OE : PASS
9094 10:01:40.712654 All Pass.
9095 10:01:40.712757
9096 10:01:40.712848 CH 1, Rank 0
9097 10:01:40.715797 SW Impedance : PASS
9098 10:01:40.718667 DUTY Scan : NO K
9099 10:01:40.718855 ZQ Calibration : PASS
9100 10:01:40.722140 Jitter Meter : NO K
9101 10:01:40.725773 CBT Training : PASS
9102 10:01:40.725963 Write leveling : PASS
9103 10:01:40.728732 RX DQS gating : PASS
9104 10:01:40.728922 RX DQ/DQS(RDDQC) : PASS
9105 10:01:40.732110 TX DQ/DQS : PASS
9106 10:01:40.735289 RX DATLAT : PASS
9107 10:01:40.735466 RX DQ/DQS(Engine): PASS
9108 10:01:40.738640 TX OE : PASS
9109 10:01:40.738829 All Pass.
9110 10:01:40.738955
9111 10:01:40.741878 CH 1, Rank 1
9112 10:01:40.742096 SW Impedance : PASS
9113 10:01:40.745220 DUTY Scan : NO K
9114 10:01:40.748646 ZQ Calibration : PASS
9115 10:01:40.748900 Jitter Meter : NO K
9116 10:01:40.751659 CBT Training : PASS
9117 10:01:40.755347 Write leveling : PASS
9118 10:01:40.755648 RX DQS gating : PASS
9119 10:01:40.758333 RX DQ/DQS(RDDQC) : PASS
9120 10:01:40.761717 TX DQ/DQS : PASS
9121 10:01:40.762026 RX DATLAT : PASS
9122 10:01:40.765306 RX DQ/DQS(Engine): PASS
9123 10:01:40.768642 TX OE : PASS
9124 10:01:40.769097 All Pass.
9125 10:01:40.769429
9126 10:01:40.769734 DramC Write-DBI on
9127 10:01:40.771922 PER_BANK_REFRESH: Hybrid Mode
9128 10:01:40.775176 TX_TRACKING: ON
9129 10:01:40.781730 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9130 10:01:40.791323 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9131 10:01:40.798348 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9132 10:01:40.801796 [FAST_K] Save calibration result to emmc
9133 10:01:40.805233 sync common calibartion params.
9134 10:01:40.808332 sync cbt_mode0:1, 1:1
9135 10:01:40.808882 dram_init: ddr_geometry: 2
9136 10:01:40.811609 dram_init: ddr_geometry: 2
9137 10:01:40.815029 dram_init: ddr_geometry: 2
9138 10:01:40.818354 0:dram_rank_size:100000000
9139 10:01:40.818963 1:dram_rank_size:100000000
9140 10:01:40.825004 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9141 10:01:40.827681 DFS_SHUFFLE_HW_MODE: ON
9142 10:01:40.831129 dramc_set_vcore_voltage set vcore to 725000
9143 10:01:40.831630 Read voltage for 1600, 0
9144 10:01:40.835128 Vio18 = 0
9145 10:01:40.835579 Vcore = 725000
9146 10:01:40.835938 Vdram = 0
9147 10:01:40.837943 Vddq = 0
9148 10:01:40.838394 Vmddr = 0
9149 10:01:40.841666 switch to 3200 Mbps bootup
9150 10:01:40.842211 [DramcRunTimeConfig]
9151 10:01:40.844763 PHYPLL
9152 10:01:40.845303 DPM_CONTROL_AFTERK: ON
9153 10:01:40.847939 PER_BANK_REFRESH: ON
9154 10:01:40.850952 REFRESH_OVERHEAD_REDUCTION: ON
9155 10:01:40.851408 CMD_PICG_NEW_MODE: OFF
9156 10:01:40.854815 XRTWTW_NEW_MODE: ON
9157 10:01:40.855366 XRTRTR_NEW_MODE: ON
9158 10:01:40.858164 TX_TRACKING: ON
9159 10:01:40.858791 RDSEL_TRACKING: OFF
9160 10:01:40.861287 DQS Precalculation for DVFS: ON
9161 10:01:40.864103 RX_TRACKING: OFF
9162 10:01:40.864754 HW_GATING DBG: ON
9163 10:01:40.867351 ZQCS_ENABLE_LP4: ON
9164 10:01:40.867801 RX_PICG_NEW_MODE: ON
9165 10:01:40.871215 TX_PICG_NEW_MODE: ON
9166 10:01:40.871766 ENABLE_RX_DCM_DPHY: ON
9167 10:01:40.874275 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9168 10:01:40.877411 DUMMY_READ_FOR_TRACKING: OFF
9169 10:01:40.880894 !!! SPM_CONTROL_AFTERK: OFF
9170 10:01:40.884090 !!! SPM could not control APHY
9171 10:01:40.884543 IMPEDANCE_TRACKING: ON
9172 10:01:40.887670 TEMP_SENSOR: ON
9173 10:01:40.888120 HW_SAVE_FOR_SR: OFF
9174 10:01:40.890804 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9175 10:01:40.893876 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9176 10:01:40.897637 Read ODT Tracking: ON
9177 10:01:40.900826 Refresh Rate DeBounce: ON
9178 10:01:40.901373 DFS_NO_QUEUE_FLUSH: ON
9179 10:01:40.903584 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9180 10:01:40.907111 ENABLE_DFS_RUNTIME_MRW: OFF
9181 10:01:40.910278 DDR_RESERVE_NEW_MODE: ON
9182 10:01:40.910789 MR_CBT_SWITCH_FREQ: ON
9183 10:01:40.913850 =========================
9184 10:01:40.933047 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9185 10:01:40.936339 dram_init: ddr_geometry: 2
9186 10:01:40.954423 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9187 10:01:40.957505 dram_init: dram init end (result: 0)
9188 10:01:40.964778 DRAM-K: Full calibration passed in 24595 msecs
9189 10:01:40.968205 MRC: failed to locate region type 0.
9190 10:01:40.968757 DRAM rank0 size:0x100000000,
9191 10:01:40.970960 DRAM rank1 size=0x100000000
9192 10:01:40.980678 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9193 10:01:40.987716 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9194 10:01:40.994272 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9195 10:01:41.000466 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9196 10:01:41.003976 DRAM rank0 size:0x100000000,
9197 10:01:41.007629 DRAM rank1 size=0x100000000
9198 10:01:41.008103 CBMEM:
9199 10:01:41.010574 IMD: root @ 0xfffff000 254 entries.
9200 10:01:41.014033 IMD: root @ 0xffffec00 62 entries.
9201 10:01:41.017294 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9202 10:01:41.020607 WARNING: RO_VPD is uninitialized or empty.
9203 10:01:41.026956 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9204 10:01:41.034399 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9205 10:01:41.047129 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9206 10:01:41.058528 BS: romstage times (exec / console): total (unknown) / 24093 ms
9207 10:01:41.059119
9208 10:01:41.059481
9209 10:01:41.068485 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9210 10:01:41.071829 ARM64: Exception handlers installed.
9211 10:01:41.075151 ARM64: Testing exception
9212 10:01:41.077862 ARM64: Done test exception
9213 10:01:41.078357 Enumerating buses...
9214 10:01:41.081248 Show all devs... Before device enumeration.
9215 10:01:41.084970 Root Device: enabled 1
9216 10:01:41.087938 CPU_CLUSTER: 0: enabled 1
9217 10:01:41.088395 CPU: 00: enabled 1
9218 10:01:41.091321 Compare with tree...
9219 10:01:41.091772 Root Device: enabled 1
9220 10:01:41.095026 CPU_CLUSTER: 0: enabled 1
9221 10:01:41.098230 CPU: 00: enabled 1
9222 10:01:41.098942 Root Device scanning...
9223 10:01:41.101531 scan_static_bus for Root Device
9224 10:01:41.104721 CPU_CLUSTER: 0 enabled
9225 10:01:41.107772 scan_static_bus for Root Device done
9226 10:01:41.111447 scan_bus: bus Root Device finished in 8 msecs
9227 10:01:41.111906 done
9228 10:01:41.117904 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9229 10:01:41.121268 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9230 10:01:41.128042 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9231 10:01:41.131147 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9232 10:01:41.134213 Allocating resources...
9233 10:01:41.137566 Reading resources...
9234 10:01:41.141244 Root Device read_resources bus 0 link: 0
9235 10:01:41.144426 DRAM rank0 size:0x100000000,
9236 10:01:41.144836 DRAM rank1 size=0x100000000
9237 10:01:41.147762 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9238 10:01:41.151193 CPU: 00 missing read_resources
9239 10:01:41.157757 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9240 10:01:41.160909 Root Device read_resources bus 0 link: 0 done
9241 10:01:41.164248 Done reading resources.
9242 10:01:41.167686 Show resources in subtree (Root Device)...After reading.
9243 10:01:41.170736 Root Device child on link 0 CPU_CLUSTER: 0
9244 10:01:41.174033 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 10:01:41.184345 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 10:01:41.184808 CPU: 00
9247 10:01:41.186942 Root Device assign_resources, bus 0 link: 0
9248 10:01:41.190269 CPU_CLUSTER: 0 missing set_resources
9249 10:01:41.197683 Root Device assign_resources, bus 0 link: 0 done
9250 10:01:41.198241 Done setting resources.
9251 10:01:41.203963 Show resources in subtree (Root Device)...After assigning values.
9252 10:01:41.206977 Root Device child on link 0 CPU_CLUSTER: 0
9253 10:01:41.210585 CPU_CLUSTER: 0 child on link 0 CPU: 00
9254 10:01:41.220150 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9255 10:01:41.220694 CPU: 00
9256 10:01:41.223409 Done allocating resources.
9257 10:01:41.230654 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9258 10:01:41.231234 Enabling resources...
9259 10:01:41.231637 done.
9260 10:01:41.237021 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9261 10:01:41.239966 Initializing devices...
9262 10:01:41.240419 Root Device init
9263 10:01:41.243638 init hardware done!
9264 10:01:41.244184 0x00000018: ctrlr->caps
9265 10:01:41.247019 52.000 MHz: ctrlr->f_max
9266 10:01:41.250487 0.400 MHz: ctrlr->f_min
9267 10:01:41.251249 0x40ff8080: ctrlr->voltages
9268 10:01:41.253343 sclk: 390625
9269 10:01:41.253891 Bus Width = 1
9270 10:01:41.254386 sclk: 390625
9271 10:01:41.256882 Bus Width = 1
9272 10:01:41.259688 Early init status = 3
9273 10:01:41.263608 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9274 10:01:41.266777 in-header: 03 fc 00 00 01 00 00 00
9275 10:01:41.269799 in-data: 00
9276 10:01:41.273200 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9277 10:01:41.277057 in-header: 03 fd 00 00 00 00 00 00
9278 10:01:41.280388 in-data:
9279 10:01:41.283974 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9280 10:01:41.288115 in-header: 03 fc 00 00 01 00 00 00
9281 10:01:41.291480 in-data: 00
9282 10:01:41.294532 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9283 10:01:41.300466 in-header: 03 fd 00 00 00 00 00 00
9284 10:01:41.303346 in-data:
9285 10:01:41.306767 [SSUSB] Setting up USB HOST controller...
9286 10:01:41.310068 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9287 10:01:41.313247 [SSUSB] phy power-on done.
9288 10:01:41.316508 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9289 10:01:41.323115 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9290 10:01:41.326353 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9291 10:01:41.333184 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9292 10:01:41.339976 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9293 10:01:41.346001 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9294 10:01:41.352771 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9295 10:01:41.359596 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9296 10:01:41.362679 SPM: binary array size = 0x9dc
9297 10:01:41.366104 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9298 10:01:41.372613 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9299 10:01:41.379521 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9300 10:01:41.386062 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9301 10:01:41.389010 configure_display: Starting display init
9302 10:01:41.423343 anx7625_power_on_init: Init interface.
9303 10:01:41.427056 anx7625_disable_pd_protocol: Disabled PD feature.
9304 10:01:41.430063 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9305 10:01:41.457931 anx7625_start_dp_work: Secure OCM version=00
9306 10:01:41.461279 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9307 10:01:41.475621 sp_tx_get_edid_block: EDID Block = 1
9308 10:01:41.578325 Extracted contents:
9309 10:01:41.582173 header: 00 ff ff ff ff ff ff 00
9310 10:01:41.585220 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9311 10:01:41.588278 version: 01 04
9312 10:01:41.591329 basic params: 95 1f 11 78 0a
9313 10:01:41.595037 chroma info: 76 90 94 55 54 90 27 21 50 54
9314 10:01:41.598588 established: 00 00 00
9315 10:01:41.604867 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9316 10:01:41.608077 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9317 10:01:41.614702 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9318 10:01:41.621396 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9319 10:01:41.627843 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9320 10:01:41.631256 extensions: 00
9321 10:01:41.631708 checksum: fb
9322 10:01:41.632075
9323 10:01:41.634867 Manufacturer: IVO Model 57d Serial Number 0
9324 10:01:41.638228 Made week 0 of 2020
9325 10:01:41.640764 EDID version: 1.4
9326 10:01:41.641219 Digital display
9327 10:01:41.644373 6 bits per primary color channel
9328 10:01:41.644928 DisplayPort interface
9329 10:01:41.647709 Maximum image size: 31 cm x 17 cm
9330 10:01:41.651164 Gamma: 220%
9331 10:01:41.651704 Check DPMS levels
9332 10:01:41.654200 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9333 10:01:41.661231 First detailed timing is preferred timing
9334 10:01:41.661779 Established timings supported:
9335 10:01:41.664629 Standard timings supported:
9336 10:01:41.667502 Detailed timings
9337 10:01:41.671176 Hex of detail: 383680a07038204018303c0035ae10000019
9338 10:01:41.677754 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9339 10:01:41.680609 0780 0798 07c8 0820 hborder 0
9340 10:01:41.683790 0438 043b 0447 0458 vborder 0
9341 10:01:41.687657 -hsync -vsync
9342 10:01:41.688111 Did detailed timing
9343 10:01:41.694379 Hex of detail: 000000000000000000000000000000000000
9344 10:01:41.696980 Manufacturer-specified data, tag 0
9345 10:01:41.700519 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9346 10:01:41.703698 ASCII string: InfoVision
9347 10:01:41.706987 Hex of detail: 000000fe00523134304e574635205248200a
9348 10:01:41.710581 ASCII string: R140NWF5 RH
9349 10:01:41.711175 Checksum
9350 10:01:41.713795 Checksum: 0xfb (valid)
9351 10:01:41.717203 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9352 10:01:41.720333 DSI data_rate: 832800000 bps
9353 10:01:41.727631 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9354 10:01:41.730585 anx7625_parse_edid: pixelclock(138800).
9355 10:01:41.733529 hactive(1920), hsync(48), hfp(24), hbp(88)
9356 10:01:41.737053 vactive(1080), vsync(12), vfp(3), vbp(17)
9357 10:01:41.739967 anx7625_dsi_config: config dsi.
9358 10:01:41.747133 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9359 10:01:41.760728 anx7625_dsi_config: success to config DSI
9360 10:01:41.763555 anx7625_dp_start: MIPI phy setup OK.
9361 10:01:41.766909 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9362 10:01:41.769821 mtk_ddp_mode_set invalid vrefresh 60
9363 10:01:41.773589 main_disp_path_setup
9364 10:01:41.774040 ovl_layer_smi_id_en
9365 10:01:41.776846 ovl_layer_smi_id_en
9366 10:01:41.777299 ccorr_config
9367 10:01:41.777660 aal_config
9368 10:01:41.780183 gamma_config
9369 10:01:41.780692 postmask_config
9370 10:01:41.783331 dither_config
9371 10:01:41.786705 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9372 10:01:41.793311 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9373 10:01:41.796283 Root Device init finished in 553 msecs
9374 10:01:41.799817 CPU_CLUSTER: 0 init
9375 10:01:41.806184 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9376 10:01:41.812765 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9377 10:01:41.813171 APU_MBOX 0x190000b0 = 0x10001
9378 10:01:41.816355 APU_MBOX 0x190001b0 = 0x10001
9379 10:01:41.819693 APU_MBOX 0x190005b0 = 0x10001
9380 10:01:41.823147 APU_MBOX 0x190006b0 = 0x10001
9381 10:01:41.829456 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9382 10:01:41.839444 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9383 10:01:41.851973 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9384 10:01:41.858403 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9385 10:01:41.870216 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9386 10:01:41.879276 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9387 10:01:41.882545 CPU_CLUSTER: 0 init finished in 81 msecs
9388 10:01:41.885991 Devices initialized
9389 10:01:41.889095 Show all devs... After init.
9390 10:01:41.889551 Root Device: enabled 1
9391 10:01:41.892104 CPU_CLUSTER: 0: enabled 1
9392 10:01:41.895923 CPU: 00: enabled 1
9393 10:01:41.898864 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9394 10:01:41.902338 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9395 10:01:41.905910 ELOG: NV offset 0x57f000 size 0x1000
9396 10:01:41.912200 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9397 10:01:41.919217 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9398 10:01:41.922369 ELOG: Event(17) added with size 13 at 2023-08-23 10:01:41 UTC
9399 10:01:41.928881 out: cmd=0x121: 03 db 21 01 00 00 00 00
9400 10:01:41.932017 in-header: 03 c1 00 00 2c 00 00 00
9401 10:01:41.942689 in-data: 9e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9402 10:01:41.948667 ELOG: Event(A1) added with size 10 at 2023-08-23 10:01:41 UTC
9403 10:01:41.955311 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9404 10:01:41.961854 ELOG: Event(A0) added with size 9 at 2023-08-23 10:01:41 UTC
9405 10:01:41.965221 elog_add_boot_reason: Logged dev mode boot
9406 10:01:41.971855 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9407 10:01:41.972407 Finalize devices...
9408 10:01:41.975493 Devices finalized
9409 10:01:41.979088 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9410 10:01:41.981595 Writing coreboot table at 0xffe64000
9411 10:01:41.984721 0. 000000000010a000-0000000000113fff: RAMSTAGE
9412 10:01:41.991934 1. 0000000040000000-00000000400fffff: RAM
9413 10:01:41.994832 2. 0000000040100000-000000004032afff: RAMSTAGE
9414 10:01:41.998341 3. 000000004032b000-00000000545fffff: RAM
9415 10:01:42.001557 4. 0000000054600000-000000005465ffff: BL31
9416 10:01:42.005119 5. 0000000054660000-00000000ffe63fff: RAM
9417 10:01:42.011130 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9418 10:01:42.014747 7. 0000000100000000-000000023fffffff: RAM
9419 10:01:42.018114 Passing 5 GPIOs to payload:
9420 10:01:42.020808 NAME | PORT | POLARITY | VALUE
9421 10:01:42.027366 EC in RW | 0x000000aa | low | undefined
9422 10:01:42.031179 EC interrupt | 0x00000005 | low | undefined
9423 10:01:42.034653 TPM interrupt | 0x000000ab | high | undefined
9424 10:01:42.040922 SD card detect | 0x00000011 | high | undefined
9425 10:01:42.043865 speaker enable | 0x00000093 | high | undefined
9426 10:01:42.047425 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9427 10:01:42.052555 in-header: 03 f9 00 00 02 00 00 00
9428 10:01:42.055822 in-data: 02 00
9429 10:01:42.059115 ADC[4]: Raw value=900813 ID=7
9430 10:01:42.062554 ADC[3]: Raw value=212912 ID=1
9431 10:01:42.063006 RAM Code: 0x71
9432 10:01:42.065765 ADC[6]: Raw value=75036 ID=0
9433 10:01:42.069385 ADC[5]: Raw value=212543 ID=1
9434 10:01:42.069893 SKU Code: 0x1
9435 10:01:42.075599 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9436 10:01:42.076111 coreboot table: 964 bytes.
9437 10:01:42.078847 IMD ROOT 0. 0xfffff000 0x00001000
9438 10:01:42.082173 IMD SMALL 1. 0xffffe000 0x00001000
9439 10:01:42.085874 RO MCACHE 2. 0xffffc000 0x00001104
9440 10:01:42.088629 CONSOLE 3. 0xfff7c000 0x00080000
9441 10:01:42.091944 FMAP 4. 0xfff7b000 0x00000452
9442 10:01:42.095779 TIME STAMP 5. 0xfff7a000 0x00000910
9443 10:01:42.098816 VBOOT WORK 6. 0xfff66000 0x00014000
9444 10:01:42.101888 RAMOOPS 7. 0xffe66000 0x00100000
9445 10:01:42.105542 COREBOOT 8. 0xffe64000 0x00002000
9446 10:01:42.108563 IMD small region:
9447 10:01:42.112157 IMD ROOT 0. 0xffffec00 0x00000400
9448 10:01:42.115207 VPD 1. 0xffffeb80 0x0000006c
9449 10:01:42.118367 MMC STATUS 2. 0xffffeb60 0x00000004
9450 10:01:42.125137 BS: BS_WRITE_TABLES run times (exec / console): 3 / 137 ms
9451 10:01:42.125687 Probing TPM: done!
9452 10:01:42.131822 Connected to device vid:did:rid of 1ae0:0028:00
9453 10:01:42.138347 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9454 10:01:42.141437 Initialized TPM device CR50 revision 0
9455 10:01:42.145585 Checking cr50 for pending updates
9456 10:01:42.150924 Reading cr50 TPM mode
9457 10:01:42.159212 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9458 10:01:42.166181 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9459 10:01:42.206141 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9460 10:01:42.209671 Checking segment from ROM address 0x40100000
9461 10:01:42.212518 Checking segment from ROM address 0x4010001c
9462 10:01:42.219479 Loading segment from ROM address 0x40100000
9463 10:01:42.220073 code (compression=0)
9464 10:01:42.229189 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9465 10:01:42.236120 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9466 10:01:42.236671 it's not compressed!
9467 10:01:42.242999 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9468 10:01:42.249385 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9469 10:01:42.266917 Loading segment from ROM address 0x4010001c
9470 10:01:42.267463 Entry Point 0x80000000
9471 10:01:42.269771 Loaded segments
9472 10:01:42.273209 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9473 10:01:42.280115 Jumping to boot code at 0x80000000(0xffe64000)
9474 10:01:42.286219 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9475 10:01:42.293030 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9476 10:01:42.301066 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9477 10:01:42.304628 Checking segment from ROM address 0x40100000
9478 10:01:42.307586 Checking segment from ROM address 0x4010001c
9479 10:01:42.314301 Loading segment from ROM address 0x40100000
9480 10:01:42.314802 code (compression=1)
9481 10:01:42.320915 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9482 10:01:42.330464 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9483 10:01:42.331060 using LZMA
9484 10:01:42.339322 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9485 10:01:42.345478 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9486 10:01:42.349583 Loading segment from ROM address 0x4010001c
9487 10:01:42.350136 Entry Point 0x54601000
9488 10:01:42.352815 Loaded segments
9489 10:01:42.356313 NOTICE: MT8192 bl31_setup
9490 10:01:42.362711 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9491 10:01:42.366171 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9492 10:01:42.370170 WARNING: region 0:
9493 10:01:42.373004 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 10:01:42.373606 WARNING: region 1:
9495 10:01:42.379160 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9496 10:01:42.383051 WARNING: region 2:
9497 10:01:42.386100 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9498 10:01:42.389262 WARNING: region 3:
9499 10:01:42.392429 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 10:01:42.395736 WARNING: region 4:
9501 10:01:42.402513 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9502 10:01:42.403136 WARNING: region 5:
9503 10:01:42.406006 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 10:01:42.409296 WARNING: region 6:
9505 10:01:42.412323 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 10:01:42.415549 WARNING: region 7:
9507 10:01:42.419339 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 10:01:42.425889 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9509 10:01:42.428804 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9510 10:01:42.435386 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9511 10:01:42.438635 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9512 10:01:42.441853 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9513 10:01:42.448384 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9514 10:01:42.451863 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9515 10:01:42.455321 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9516 10:01:42.461862 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9517 10:01:42.464982 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9518 10:01:42.471487 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9519 10:01:42.474922 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9520 10:01:42.477955 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9521 10:01:42.484732 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9522 10:01:42.488221 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9523 10:01:42.495046 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9524 10:01:42.498321 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9525 10:01:42.501491 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9526 10:01:42.508443 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9527 10:01:42.511198 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9528 10:01:42.517983 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9529 10:01:42.521593 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9530 10:01:42.524287 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9531 10:01:42.531497 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9532 10:01:42.534623 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9533 10:01:42.540774 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9534 10:01:42.544599 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9535 10:01:42.547557 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9536 10:01:42.554188 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9537 10:01:42.557335 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9538 10:01:42.564085 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9539 10:01:42.567572 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9540 10:01:42.570881 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9541 10:01:42.573821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9542 10:01:42.580503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9543 10:01:42.583908 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9544 10:01:42.587029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9545 10:01:42.590367 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9546 10:01:42.597381 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9547 10:01:42.600436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9548 10:01:42.603669 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9549 10:01:42.607262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9550 10:01:42.614049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9551 10:01:42.617613 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9552 10:01:42.620008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9553 10:01:42.627014 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9554 10:01:42.630316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9555 10:01:42.633592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9556 10:01:42.640364 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9557 10:01:42.643252 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9558 10:01:42.647246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9559 10:01:42.653472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9560 10:01:42.657143 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9561 10:01:42.663577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9562 10:01:42.666642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9563 10:01:42.673597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9564 10:01:42.676976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9565 10:01:42.679930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9566 10:01:42.686399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9567 10:01:42.689603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9568 10:01:42.696054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9569 10:01:42.699814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9570 10:01:42.706327 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9571 10:01:42.709505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9572 10:01:42.716544 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9573 10:01:42.719517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9574 10:01:42.726280 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9575 10:01:42.729705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9576 10:01:42.732548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9577 10:01:42.739235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9578 10:01:42.742273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9579 10:01:42.748976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9580 10:01:42.752271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9581 10:01:42.758890 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9582 10:01:42.762532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9583 10:01:42.768822 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9584 10:01:42.772078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9585 10:01:42.775473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9586 10:01:42.782104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9587 10:01:42.784960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9588 10:01:42.791868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9589 10:01:42.795273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9590 10:01:42.802473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9591 10:01:42.805485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9592 10:01:42.811623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9593 10:01:42.814778 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9594 10:01:42.818625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9595 10:01:42.825063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9596 10:01:42.828375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9597 10:01:42.835341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9598 10:01:42.838212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9599 10:01:42.845128 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9600 10:01:42.848366 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9601 10:01:42.851589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9602 10:01:42.858334 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9603 10:01:42.861762 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9604 10:01:42.868314 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9605 10:01:42.871461 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9606 10:01:42.875189 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9607 10:01:42.878348 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9608 10:01:42.884423 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9609 10:01:42.888030 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9610 10:01:42.894773 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9611 10:01:42.898210 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9612 10:01:42.901473 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9613 10:01:42.908115 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9614 10:01:42.911652 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9615 10:01:42.917794 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9616 10:01:42.921667 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9617 10:01:42.924116 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9618 10:01:42.930967 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9619 10:01:42.934576 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9620 10:01:42.941314 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9621 10:01:42.944264 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9622 10:01:42.947774 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9623 10:01:42.954502 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9624 10:01:42.957922 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9625 10:01:42.961328 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9626 10:01:42.967608 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9627 10:01:42.970349 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9628 10:01:42.973856 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9629 10:01:42.976984 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9630 10:01:42.983346 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9631 10:01:42.986692 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9632 10:01:42.990381 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9633 10:01:42.996943 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9634 10:01:43.000386 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9635 10:01:43.006776 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9636 10:01:43.010574 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9637 10:01:43.013338 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9638 10:01:43.020197 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9639 10:01:43.023476 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9640 10:01:43.030431 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9641 10:01:43.033478 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9642 10:01:43.036935 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9643 10:01:43.043378 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9644 10:01:43.046922 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9645 10:01:43.050547 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9646 10:01:43.056579 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9647 10:01:43.059976 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9648 10:01:43.066864 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9649 10:01:43.070279 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9650 10:01:43.072930 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9651 10:01:43.079849 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9652 10:01:43.083233 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9653 10:01:43.090208 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9654 10:01:43.093051 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9655 10:01:43.096867 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9656 10:01:43.103174 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9657 10:01:43.106334 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9658 10:01:43.113129 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9659 10:01:43.116320 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9660 10:01:43.119758 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9661 10:01:43.126564 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9662 10:01:43.130277 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9663 10:01:43.136158 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9664 10:01:43.139833 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9665 10:01:43.143594 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9666 10:01:43.149518 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9667 10:01:43.152851 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9668 10:01:43.156479 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9669 10:01:43.162646 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9670 10:01:43.166757 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9671 10:01:43.172760 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9672 10:01:43.176247 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9673 10:01:43.179645 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9674 10:01:43.185644 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9675 10:01:43.189593 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9676 10:01:43.195755 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9677 10:01:43.199598 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9678 10:01:43.202384 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9679 10:01:43.209097 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9680 10:01:43.212114 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9681 10:01:43.219100 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9682 10:01:43.222443 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9683 10:01:43.225318 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9684 10:01:43.232203 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9685 10:01:43.235807 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9686 10:01:43.241744 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9687 10:01:43.245727 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9688 10:01:43.248557 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9689 10:01:43.255563 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9690 10:01:43.259066 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9691 10:01:43.265420 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9692 10:01:43.268714 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9693 10:01:43.271621 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9694 10:01:43.278909 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9695 10:01:43.282191 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9696 10:01:43.288733 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9697 10:01:43.291448 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9698 10:01:43.298487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9699 10:01:43.302003 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9700 10:01:43.305188 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9701 10:01:43.311584 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9702 10:01:43.314796 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9703 10:01:43.321159 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9704 10:01:43.324813 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9705 10:01:43.328137 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9706 10:01:43.335252 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9707 10:01:43.337808 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9708 10:01:43.344833 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9709 10:01:43.348034 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9710 10:01:43.354337 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9711 10:01:43.358289 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9712 10:01:43.361505 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9713 10:01:43.367858 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9714 10:01:43.371559 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9715 10:01:43.377491 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9716 10:01:43.381346 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9717 10:01:43.387465 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9718 10:01:43.390806 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9719 10:01:43.394321 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9720 10:01:43.400691 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9721 10:01:43.404488 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9722 10:01:43.410681 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9723 10:01:43.414101 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9724 10:01:43.420750 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9725 10:01:43.424173 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9726 10:01:43.427599 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9727 10:01:43.433498 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9728 10:01:43.437077 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9729 10:01:43.443636 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9730 10:01:43.446812 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9731 10:01:43.450378 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9732 10:01:43.456943 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9733 10:01:43.459911 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9734 10:01:43.466984 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9735 10:01:43.470419 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9736 10:01:43.477156 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9737 10:01:43.479994 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9738 10:01:43.483272 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9739 10:01:43.486709 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9740 10:01:43.492954 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9741 10:01:43.496255 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9742 10:01:43.499437 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9743 10:01:43.506562 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9744 10:01:43.509109 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9745 10:01:43.512972 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9746 10:01:43.519494 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9747 10:01:43.522290 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9748 10:01:43.525764 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9749 10:01:43.532422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9750 10:01:43.535813 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9751 10:01:43.542632 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9752 10:01:43.545853 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9753 10:01:43.548573 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9754 10:01:43.555278 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9755 10:01:43.558718 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9756 10:01:43.561756 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9757 10:01:43.568773 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9758 10:01:43.572074 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9759 10:01:43.578720 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9760 10:01:43.581443 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9761 10:01:43.584963 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9762 10:01:43.591637 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9763 10:01:43.594528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9764 10:01:43.601755 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9765 10:01:43.604537 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9766 10:01:43.607989 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9767 10:01:43.614472 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9768 10:01:43.618110 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9769 10:01:43.621454 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9770 10:01:43.627914 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9771 10:01:43.631184 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9772 10:01:43.634686 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9773 10:01:43.640852 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9774 10:01:43.644712 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9775 10:01:43.651237 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9776 10:01:43.654155 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9777 10:01:43.657489 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9778 10:01:43.661014 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9779 10:01:43.667425 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9780 10:01:43.671097 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9781 10:01:43.673740 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9782 10:01:43.677380 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9783 10:01:43.684104 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9784 10:01:43.687267 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9785 10:01:43.690124 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9786 10:01:43.694178 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9787 10:01:43.700283 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9788 10:01:43.703407 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9789 10:01:43.706588 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9790 10:01:43.713526 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9791 10:01:43.716412 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9792 10:01:43.723551 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9793 10:01:43.726837 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9794 10:01:43.733351 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9795 10:01:43.736617 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9796 10:01:43.739876 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9797 10:01:43.746423 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9798 10:01:43.749709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9799 10:01:43.756361 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9800 10:01:43.759305 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9801 10:01:43.762798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9802 10:01:43.769177 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9803 10:01:43.772625 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9804 10:01:43.779109 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9805 10:01:43.782371 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9806 10:01:43.789271 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9807 10:01:43.792236 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9808 10:01:43.795488 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9809 10:01:43.801928 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9810 10:01:43.805588 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9811 10:01:43.811880 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9812 10:01:43.815203 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9813 10:01:43.818692 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9814 10:01:43.824754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9815 10:01:43.828523 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9816 10:01:43.835064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9817 10:01:43.838358 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9818 10:01:43.844515 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9819 10:01:43.848136 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9820 10:01:43.854739 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9821 10:01:43.857692 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9822 10:01:43.861438 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9823 10:01:43.867707 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9824 10:01:43.871269 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9825 10:01:43.878046 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9826 10:01:43.881524 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9827 10:01:43.884896 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9828 10:01:43.890849 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9829 10:01:43.894265 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9830 10:01:43.900851 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9831 10:01:43.904011 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9832 10:01:43.907902 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9833 10:01:43.913980 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9834 10:01:43.917602 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9835 10:01:43.923950 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9836 10:01:43.927569 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9837 10:01:43.934167 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9838 10:01:43.937256 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9839 10:01:43.940629 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9840 10:01:43.947059 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9841 10:01:43.950242 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9842 10:01:43.956976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9843 10:01:43.960363 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9844 10:01:43.967368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9845 10:01:43.970182 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9846 10:01:43.973921 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9847 10:01:43.980486 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9848 10:01:43.983129 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9849 10:01:43.989894 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9850 10:01:43.993160 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9851 10:01:43.996524 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9852 10:01:44.003863 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9853 10:01:44.006358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9854 10:01:44.013127 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9855 10:01:44.016182 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9856 10:01:44.019415 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9857 10:01:44.026392 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9858 10:01:44.029569 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9859 10:01:44.036264 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9860 10:01:44.039605 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9861 10:01:44.045837 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9862 10:01:44.049326 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9863 10:01:44.052876 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9864 10:01:44.059237 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9865 10:01:44.062467 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9866 10:01:44.068947 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9867 10:01:44.072388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9868 10:01:44.079103 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9869 10:01:44.082325 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9870 10:01:44.085767 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9871 10:01:44.092382 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9872 10:01:44.095443 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9873 10:01:44.102476 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9874 10:01:44.105780 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9875 10:01:44.111975 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9876 10:01:44.115492 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9877 10:01:44.122349 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9878 10:01:44.125419 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9879 10:01:44.128622 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9880 10:01:44.135727 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9881 10:01:44.138702 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9882 10:01:44.145148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9883 10:01:44.148691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9884 10:01:44.154868 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9885 10:01:44.158385 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9886 10:01:44.164822 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9887 10:01:44.168338 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9888 10:01:44.174524 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9889 10:01:44.177815 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9890 10:01:44.180951 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9891 10:01:44.188167 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9892 10:01:44.191001 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9893 10:01:44.197392 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9894 10:01:44.200997 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9895 10:01:44.207328 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9896 10:01:44.211006 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9897 10:01:44.217386 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9898 10:01:44.220868 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9899 10:01:44.227656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9900 10:01:44.230540 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9901 10:01:44.234113 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9902 10:01:44.240933 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9903 10:01:44.244202 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9904 10:01:44.250491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9905 10:01:44.253801 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9906 10:01:44.260585 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9907 10:01:44.264060 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9908 10:01:44.267618 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9909 10:01:44.273896 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9910 10:01:44.277100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9911 10:01:44.283634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9912 10:01:44.286701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9913 10:01:44.293256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9914 10:01:44.296884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9915 10:01:44.300371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9916 10:01:44.306882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9917 10:01:44.310172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9918 10:01:44.316493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9919 10:01:44.320016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9920 10:01:44.326662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9921 10:01:44.330290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9922 10:01:44.336864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9923 10:01:44.340000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9924 10:01:44.346547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9925 10:01:44.349756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9926 10:01:44.356400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9927 10:01:44.359590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9928 10:01:44.366029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9929 10:01:44.369462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9930 10:01:44.375783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9931 10:01:44.379300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9932 10:01:44.385975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9933 10:01:44.388980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9934 10:01:44.395848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9935 10:01:44.399352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9936 10:01:44.405712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9937 10:01:44.408887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9938 10:01:44.415544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9939 10:01:44.419130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9940 10:01:44.425938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9941 10:01:44.432172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9942 10:01:44.435134 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9943 10:01:44.435718 INFO: [APUAPC] vio 0
9944 10:01:44.442544 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9945 10:01:44.446055 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9946 10:01:44.449037 INFO: [APUAPC] D0_APC_0: 0x400510
9947 10:01:44.452662 INFO: [APUAPC] D0_APC_1: 0x0
9948 10:01:44.456033 INFO: [APUAPC] D0_APC_2: 0x1540
9949 10:01:44.458901 INFO: [APUAPC] D0_APC_3: 0x0
9950 10:01:44.462558 INFO: [APUAPC] D1_APC_0: 0xffffffff
9951 10:01:44.465668 INFO: [APUAPC] D1_APC_1: 0xffffffff
9952 10:01:44.469510 INFO: [APUAPC] D1_APC_2: 0x3fffff
9953 10:01:44.471919 INFO: [APUAPC] D1_APC_3: 0x0
9954 10:01:44.475891 INFO: [APUAPC] D2_APC_0: 0xffffffff
9955 10:01:44.478873 INFO: [APUAPC] D2_APC_1: 0xffffffff
9956 10:01:44.482340 INFO: [APUAPC] D2_APC_2: 0x3fffff
9957 10:01:44.485419 INFO: [APUAPC] D2_APC_3: 0x0
9958 10:01:44.488700 INFO: [APUAPC] D3_APC_0: 0xffffffff
9959 10:01:44.492533 INFO: [APUAPC] D3_APC_1: 0xffffffff
9960 10:01:44.495588 INFO: [APUAPC] D3_APC_2: 0x3fffff
9961 10:01:44.498330 INFO: [APUAPC] D3_APC_3: 0x0
9962 10:01:44.501803 INFO: [APUAPC] D4_APC_0: 0xffffffff
9963 10:01:44.505397 INFO: [APUAPC] D4_APC_1: 0xffffffff
9964 10:01:44.508487 INFO: [APUAPC] D4_APC_2: 0x3fffff
9965 10:01:44.512174 INFO: [APUAPC] D4_APC_3: 0x0
9966 10:01:44.515155 INFO: [APUAPC] D5_APC_0: 0xffffffff
9967 10:01:44.518183 INFO: [APUAPC] D5_APC_1: 0xffffffff
9968 10:01:44.521231 INFO: [APUAPC] D5_APC_2: 0x3fffff
9969 10:01:44.525086 INFO: [APUAPC] D5_APC_3: 0x0
9970 10:01:44.528446 INFO: [APUAPC] D6_APC_0: 0xffffffff
9971 10:01:44.531852 INFO: [APUAPC] D6_APC_1: 0xffffffff
9972 10:01:44.534885 INFO: [APUAPC] D6_APC_2: 0x3fffff
9973 10:01:44.538002 INFO: [APUAPC] D6_APC_3: 0x0
9974 10:01:44.541221 INFO: [APUAPC] D7_APC_0: 0xffffffff
9975 10:01:44.544325 INFO: [APUAPC] D7_APC_1: 0xffffffff
9976 10:01:44.548024 INFO: [APUAPC] D7_APC_2: 0x3fffff
9977 10:01:44.550961 INFO: [APUAPC] D7_APC_3: 0x0
9978 10:01:44.554816 INFO: [APUAPC] D8_APC_0: 0xffffffff
9979 10:01:44.557581 INFO: [APUAPC] D8_APC_1: 0xffffffff
9980 10:01:44.561005 INFO: [APUAPC] D8_APC_2: 0x3fffff
9981 10:01:44.561567 INFO: [APUAPC] D8_APC_3: 0x0
9982 10:01:44.567940 INFO: [APUAPC] D9_APC_0: 0xffffffff
9983 10:01:44.570957 INFO: [APUAPC] D9_APC_1: 0xffffffff
9984 10:01:44.575105 INFO: [APUAPC] D9_APC_2: 0x3fffff
9985 10:01:44.575652 INFO: [APUAPC] D9_APC_3: 0x0
9986 10:01:44.577773 INFO: [APUAPC] D10_APC_0: 0xffffffff
9987 10:01:44.583821 INFO: [APUAPC] D10_APC_1: 0xffffffff
9988 10:01:44.587581 INFO: [APUAPC] D10_APC_2: 0x3fffff
9989 10:01:44.588134 INFO: [APUAPC] D10_APC_3: 0x0
9990 10:01:44.594746 INFO: [APUAPC] D11_APC_0: 0xffffffff
9991 10:01:44.597495 INFO: [APUAPC] D11_APC_1: 0xffffffff
9992 10:01:44.600524 INFO: [APUAPC] D11_APC_2: 0x3fffff
9993 10:01:44.600970 INFO: [APUAPC] D11_APC_3: 0x0
9994 10:01:44.607667 INFO: [APUAPC] D12_APC_0: 0xffffffff
9995 10:01:44.610387 INFO: [APUAPC] D12_APC_1: 0xffffffff
9996 10:01:44.614060 INFO: [APUAPC] D12_APC_2: 0x3fffff
9997 10:01:44.617810 INFO: [APUAPC] D12_APC_3: 0x0
9998 10:01:44.620546 INFO: [APUAPC] D13_APC_0: 0xffffffff
9999 10:01:44.623559 INFO: [APUAPC] D13_APC_1: 0xffffffff
10000 10:01:44.626727 INFO: [APUAPC] D13_APC_2: 0x3fffff
10001 10:01:44.630454 INFO: [APUAPC] D13_APC_3: 0x0
10002 10:01:44.634071 INFO: [APUAPC] D14_APC_0: 0xffffffff
10003 10:01:44.637014 INFO: [APUAPC] D14_APC_1: 0xffffffff
10004 10:01:44.640382 INFO: [APUAPC] D14_APC_2: 0x3fffff
10005 10:01:44.643607 INFO: [APUAPC] D14_APC_3: 0x0
10006 10:01:44.647424 INFO: [APUAPC] D15_APC_0: 0xffffffff
10007 10:01:44.650386 INFO: [APUAPC] D15_APC_1: 0xffffffff
10008 10:01:44.653430 INFO: [APUAPC] D15_APC_2: 0x3fffff
10009 10:01:44.656656 INFO: [APUAPC] D15_APC_3: 0x0
10010 10:01:44.660077 INFO: [APUAPC] APC_CON: 0x4
10011 10:01:44.660527 INFO: [NOCDAPC] D0_APC_0: 0x0
10012 10:01:44.663582 INFO: [NOCDAPC] D0_APC_1: 0x0
10013 10:01:44.667040 INFO: [NOCDAPC] D1_APC_0: 0x0
10014 10:01:44.670219 INFO: [NOCDAPC] D1_APC_1: 0xfff
10015 10:01:44.673228 INFO: [NOCDAPC] D2_APC_0: 0x0
10016 10:01:44.676601 INFO: [NOCDAPC] D2_APC_1: 0xfff
10017 10:01:44.679904 INFO: [NOCDAPC] D3_APC_0: 0x0
10018 10:01:44.683309 INFO: [NOCDAPC] D3_APC_1: 0xfff
10019 10:01:44.686583 INFO: [NOCDAPC] D4_APC_0: 0x0
10020 10:01:44.689568 INFO: [NOCDAPC] D4_APC_1: 0xfff
10021 10:01:44.690244 INFO: [NOCDAPC] D5_APC_0: 0x0
10022 10:01:44.693028 INFO: [NOCDAPC] D5_APC_1: 0xfff
10023 10:01:44.696566 INFO: [NOCDAPC] D6_APC_0: 0x0
10024 10:01:44.699490 INFO: [NOCDAPC] D6_APC_1: 0xfff
10025 10:01:44.702949 INFO: [NOCDAPC] D7_APC_0: 0x0
10026 10:01:44.706352 INFO: [NOCDAPC] D7_APC_1: 0xfff
10027 10:01:44.709898 INFO: [NOCDAPC] D8_APC_0: 0x0
10028 10:01:44.712629 INFO: [NOCDAPC] D8_APC_1: 0xfff
10029 10:01:44.716027 INFO: [NOCDAPC] D9_APC_0: 0x0
10030 10:01:44.719351 INFO: [NOCDAPC] D9_APC_1: 0xfff
10031 10:01:44.722971 INFO: [NOCDAPC] D10_APC_0: 0x0
10032 10:01:44.725937 INFO: [NOCDAPC] D10_APC_1: 0xfff
10033 10:01:44.726378 INFO: [NOCDAPC] D11_APC_0: 0x0
10034 10:01:44.729795 INFO: [NOCDAPC] D11_APC_1: 0xfff
10035 10:01:44.732819 INFO: [NOCDAPC] D12_APC_0: 0x0
10036 10:01:44.736131 INFO: [NOCDAPC] D12_APC_1: 0xfff
10037 10:01:44.739567 INFO: [NOCDAPC] D13_APC_0: 0x0
10038 10:01:44.742728 INFO: [NOCDAPC] D13_APC_1: 0xfff
10039 10:01:44.745914 INFO: [NOCDAPC] D14_APC_0: 0x0
10040 10:01:44.749318 INFO: [NOCDAPC] D14_APC_1: 0xfff
10041 10:01:44.752838 INFO: [NOCDAPC] D15_APC_0: 0x0
10042 10:01:44.756027 INFO: [NOCDAPC] D15_APC_1: 0xfff
10043 10:01:44.759516 INFO: [NOCDAPC] APC_CON: 0x4
10044 10:01:44.762503 INFO: [APUAPC] set_apusys_apc done
10045 10:01:44.765651 INFO: [DEVAPC] devapc_init done
10046 10:01:44.769499 INFO: GICv3 without legacy support detected.
10047 10:01:44.773065 INFO: ARM GICv3 driver initialized in EL3
10048 10:01:44.775833 INFO: Maximum SPI INTID supported: 639
10049 10:01:44.782428 INFO: BL31: Initializing runtime services
10050 10:01:44.786101 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10051 10:01:44.789006 INFO: SPM: enable CPC mode
10052 10:01:44.795594 INFO: mcdi ready for mcusys-off-idle and system suspend
10053 10:01:44.798841 INFO: BL31: Preparing for EL3 exit to normal world
10054 10:01:44.803040 INFO: Entry point address = 0x80000000
10055 10:01:44.805599 INFO: SPSR = 0x8
10056 10:01:44.810691
10057 10:01:44.811137
10058 10:01:44.811489
10059 10:01:44.814039 Starting depthcharge on Spherion...
10060 10:01:44.814446
10061 10:01:44.814822 Wipe memory regions:
10062 10:01:44.815133
10063 10:01:44.817759 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10064 10:01:44.818267 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10065 10:01:44.818724 Setting prompt string to ['asurada:']
10066 10:01:44.819119 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10067 10:01:44.819810 [0x00000040000000, 0x00000054600000)
10068 10:01:44.939903
10069 10:01:44.940450 [0x00000054660000, 0x00000080000000)
10070 10:01:45.200201
10071 10:01:45.200901 [0x000000821a7280, 0x000000ffe64000)
10072 10:01:45.944978
10073 10:01:45.945526 [0x00000100000000, 0x00000240000000)
10074 10:01:47.834499
10075 10:01:47.837220 Initializing XHCI USB controller at 0x11200000.
10076 10:01:48.818938
10077 10:01:48.819489 R8152: Initializing
10078 10:01:48.819854
10079 10:01:48.822268 Version 9 (ocp_data = 6010)
10080 10:01:48.822802
10081 10:01:48.825270 R8152: Done initializing
10082 10:01:48.825717
10083 10:01:48.826071 Adding net device
10084 10:01:49.347940
10085 10:01:49.350689 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10086 10:01:49.351242
10087 10:01:49.351602
10088 10:01:49.351933
10089 10:01:49.352729 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 10:01:49.453959 asurada: tftpboot 192.168.201.1 11336431/tftp-deploy-jgneaz_9/kernel/image.itb 11336431/tftp-deploy-jgneaz_9/kernel/cmdline
10092 10:01:49.454674 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10093 10:01:49.455193 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10094 10:01:49.459812 tftpboot 192.168.201.1 11336431/tftp-deploy-jgneaz_9/kernel/image.itp-deploy-jgneaz_9/kernel/cmdline
10095 10:01:49.460288
10096 10:01:49.460645 Waiting for link
10097 10:01:49.662518
10098 10:01:49.663145 done.
10099 10:01:49.663514
10100 10:01:49.663847 MAC: f4:f5:e8:50:de:0a
10101 10:01:49.664235
10102 10:01:49.665559 Sending DHCP discover... done.
10103 10:01:49.666008
10104 10:01:49.668265 Waiting for reply... done.
10105 10:01:49.668825
10106 10:01:49.671982 Sending DHCP request... done.
10107 10:01:49.672572
10108 10:01:49.677286 Waiting for reply... done.
10109 10:01:49.677838
10110 10:01:49.678198 My ip is 192.168.201.14
10111 10:01:49.678535
10112 10:01:49.680524 The DHCP server ip is 192.168.201.1
10113 10:01:49.681170
10114 10:01:49.687273 TFTP server IP predefined by user: 192.168.201.1
10115 10:01:49.687825
10116 10:01:49.693995 Bootfile predefined by user: 11336431/tftp-deploy-jgneaz_9/kernel/image.itb
10117 10:01:49.694542
10118 10:01:49.696795 Sending tftp read request... done.
10119 10:01:49.697259
10120 10:01:49.703777 Waiting for the transfer...
10121 10:01:49.704548
10122 10:01:50.065042 00000000 ################################################################
10123 10:01:50.065540
10124 10:01:50.423000 00080000 ################################################################
10125 10:01:50.423487
10126 10:01:50.697333 00100000 ################################################################
10127 10:01:50.697475
10128 10:01:50.958415 00180000 ################################################################
10129 10:01:50.958573
10130 10:01:51.210992 00200000 ################################################################
10131 10:01:51.211139
10132 10:01:51.466581 00280000 ################################################################
10133 10:01:51.466726
10134 10:01:51.724380 00300000 ################################################################
10135 10:01:51.724523
10136 10:01:51.968485 00380000 ################################################################
10137 10:01:51.968623
10138 10:01:52.211407 00400000 ################################################################
10139 10:01:52.211549
10140 10:01:52.446150 00480000 ################################################################
10141 10:01:52.446287
10142 10:01:52.702708 00500000 ################################################################
10143 10:01:52.702849
10144 10:01:52.934624 00580000 ################################################################
10145 10:01:52.934761
10146 10:01:53.179272 00600000 ################################################################
10147 10:01:53.179428
10148 10:01:53.414504 00680000 ################################################################
10149 10:01:53.414677
10150 10:01:53.651813 00700000 ################################################################
10151 10:01:53.651961
10152 10:01:53.885401 00780000 ################################################################
10153 10:01:53.885538
10154 10:01:54.143035 00800000 ################################################################
10155 10:01:54.143180
10156 10:01:54.377391 00880000 ################################################################
10157 10:01:54.377529
10158 10:01:54.627096 00900000 ################################################################
10159 10:01:54.627227
10160 10:01:54.882286 00980000 ################################################################
10161 10:01:54.882433
10162 10:01:55.126579 00a00000 ################################################################
10163 10:01:55.126753
10164 10:01:55.357274 00a80000 ################################################################
10165 10:01:55.357410
10166 10:01:55.617151 00b00000 ################################################################
10167 10:01:55.617286
10168 10:01:55.888844 00b80000 ################################################################
10169 10:01:55.888987
10170 10:01:56.154011 00c00000 ################################################################
10171 10:01:56.154152
10172 10:01:56.384088 00c80000 ################################################################
10173 10:01:56.384230
10174 10:01:56.655710 00d00000 ################################################################
10175 10:01:56.655852
10176 10:01:56.927968 00d80000 ################################################################
10177 10:01:56.928106
10178 10:01:57.191101 00e00000 ################################################################
10179 10:01:57.191241
10180 10:01:57.422554 00e80000 ################################################################
10181 10:01:57.422720
10182 10:01:57.653657 00f00000 ################################################################
10183 10:01:57.653785
10184 10:01:57.893881 00f80000 ################################################################
10185 10:01:57.894037
10186 10:01:58.160153 01000000 ################################################################
10187 10:01:58.160307
10188 10:01:58.387184 01080000 ################################################################
10189 10:01:58.387317
10190 10:01:58.622998 01100000 ################################################################
10191 10:01:58.623128
10192 10:01:58.865231 01180000 ################################################################
10193 10:01:58.865387
10194 10:01:59.110750 01200000 ################################################################
10195 10:01:59.110881
10196 10:01:59.347310 01280000 ################################################################
10197 10:01:59.347449
10198 10:01:59.574761 01300000 ################################################################
10199 10:01:59.574923
10200 10:01:59.840223 01380000 ################################################################
10201 10:01:59.840381
10202 10:02:00.100994 01400000 ################################################################
10203 10:02:00.101152
10204 10:02:00.362790 01480000 ################################################################
10205 10:02:00.362933
10206 10:02:00.618155 01500000 ################################################################
10207 10:02:00.618319
10208 10:02:00.864638 01580000 ################################################################
10209 10:02:00.864803
10210 10:02:01.120789 01600000 ################################################################
10211 10:02:01.120932
10212 10:02:01.371964 01680000 ################################################################
10213 10:02:01.372104
10214 10:02:01.611762 01700000 ################################################################
10215 10:02:01.611919
10216 10:02:01.877652 01780000 ################################################################
10217 10:02:01.877785
10218 10:02:02.140900 01800000 ################################################################
10219 10:02:02.141069
10220 10:02:02.374709 01880000 ################################################################
10221 10:02:02.374874
10222 10:02:02.646032 01900000 ################################################################
10223 10:02:02.646193
10224 10:02:02.903914 01980000 ################################################################
10225 10:02:02.904060
10226 10:02:03.174278 01a00000 ################################################################
10227 10:02:03.174446
10228 10:02:03.420749 01a80000 ################################################################
10229 10:02:03.420889
10230 10:02:03.662564 01b00000 ################################################################
10231 10:02:03.662753
10232 10:02:03.914184 01b80000 ################################################################
10233 10:02:03.914349
10234 10:02:04.156101 01c00000 ################################################################
10235 10:02:04.156265
10236 10:02:04.413082 01c80000 ################################################################
10237 10:02:04.413215
10238 10:02:04.650486 01d00000 ################################################################
10239 10:02:04.650658
10240 10:02:04.896981 01d80000 ################################################################
10241 10:02:04.897152
10242 10:02:05.140773 01e00000 ################################################################
10243 10:02:05.140941
10244 10:02:05.402363 01e80000 ################################################################
10245 10:02:05.402518
10246 10:02:05.673330 01f00000 ################################################################
10247 10:02:05.673493
10248 10:02:05.931243 01f80000 ################################################################
10249 10:02:05.931381
10250 10:02:06.158627 02000000 ################################################################
10251 10:02:06.158774
10252 10:02:06.402862 02080000 ################################################################
10253 10:02:06.403005
10254 10:02:06.629675 02100000 ################################################################
10255 10:02:06.629837
10256 10:02:06.878254 02180000 ################################################################
10257 10:02:06.878402
10258 10:02:07.123072 02200000 ################################################################
10259 10:02:07.123242
10260 10:02:07.381281 02280000 ################################################################
10261 10:02:07.381426
10262 10:02:07.644019 02300000 ################################################################
10263 10:02:07.644192
10264 10:02:07.876391 02380000 ################################################################
10265 10:02:07.876533
10266 10:02:08.146450 02400000 ################################################################
10267 10:02:08.146626
10268 10:02:08.410362 02480000 ################################################################
10269 10:02:08.410506
10270 10:02:08.667340 02500000 ################################################################
10271 10:02:08.667481
10272 10:02:08.923757 02580000 ################################################################
10273 10:02:08.923896
10274 10:02:09.167532 02600000 ################################################################
10275 10:02:09.167664
10276 10:02:09.415689 02680000 ################################################################
10277 10:02:09.415846
10278 10:02:09.677886 02700000 ################################################################
10279 10:02:09.678019
10280 10:02:09.906906 02780000 ################################################################
10281 10:02:09.907033
10282 10:02:10.162720 02800000 ################################################################
10283 10:02:10.162886
10284 10:02:10.486146 02880000 ################################################################
10285 10:02:10.486281
10286 10:02:10.730021 02900000 ################################################################
10287 10:02:10.730158
10288 10:02:10.956774 02980000 ################################################################
10289 10:02:10.956903
10290 10:02:11.182534 02a00000 ################################################################
10291 10:02:11.182722
10292 10:02:11.429712 02a80000 ################################################################
10293 10:02:11.429848
10294 10:02:11.682915 02b00000 ################################################################
10295 10:02:11.683063
10296 10:02:11.952172 02b80000 ################################################################
10297 10:02:11.952309
10298 10:02:12.205600 02c00000 ################################################################
10299 10:02:12.205745
10300 10:02:12.474269 02c80000 ################################################################
10301 10:02:12.474406
10302 10:02:12.736522 02d00000 ################################################################
10303 10:02:12.736665
10304 10:02:13.008391 02d80000 ################################################################
10305 10:02:13.008519
10306 10:02:13.271796 02e00000 ################################################################
10307 10:02:13.271941
10308 10:02:13.539475 02e80000 ################################################################
10309 10:02:13.539607
10310 10:02:13.811107 02f00000 ################################################################
10311 10:02:13.811253
10312 10:02:14.076709 02f80000 ################################################################
10313 10:02:14.076854
10314 10:02:14.341315 03000000 ################################################################
10315 10:02:14.341459
10316 10:02:14.611802 03080000 ################################################################
10317 10:02:14.611941
10318 10:02:14.861107 03100000 ################################################################
10319 10:02:14.861244
10320 10:02:15.124513 03180000 ################################################################
10321 10:02:15.124650
10322 10:02:15.389449 03200000 ################################################################
10323 10:02:15.389592
10324 10:02:15.646931 03280000 ################################################################
10325 10:02:15.647071
10326 10:02:15.915780 03300000 ################################################################
10327 10:02:15.915915
10328 10:02:16.157653 03380000 ################################################################
10329 10:02:16.157802
10330 10:02:16.389045 03400000 ################################################################
10331 10:02:16.389190
10332 10:02:16.616063 03480000 ################################################################
10333 10:02:16.616202
10334 10:02:16.856549 03500000 ################################################################
10335 10:02:16.856692
10336 10:02:17.101702 03580000 ################################################################
10337 10:02:17.101842
10338 10:02:17.338909 03600000 ################################################################
10339 10:02:17.339052
10340 10:02:17.584503 03680000 ################################################################
10341 10:02:17.584641
10342 10:02:17.848349 03700000 ################################################################
10343 10:02:17.848509
10344 10:02:18.029274 03780000 ################################################## done.
10345 10:02:18.029403
10346 10:02:18.032914 The bootfile was 58600094 bytes long.
10347 10:02:18.033003
10348 10:02:18.035613 Sending tftp read request... done.
10349 10:02:18.035700
10350 10:02:18.039188 Waiting for the transfer...
10351 10:02:18.039282
10352 10:02:18.039358 00000000 # done.
10353 10:02:18.039429
10354 10:02:18.049187 Command line loaded dynamically from TFTP file: 11336431/tftp-deploy-jgneaz_9/kernel/cmdline
10355 10:02:18.049373
10356 10:02:18.062452 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10357 10:02:18.062701
10358 10:02:18.062848 Loading FIT.
10359 10:02:18.062962
10360 10:02:18.065756 Image ramdisk-1 has 47513522 bytes.
10361 10:02:18.065906
10362 10:02:18.068621 Image fdt-1 has 47278 bytes.
10363 10:02:18.068794
10364 10:02:18.072018 Image kernel-1 has 11037260 bytes.
10365 10:02:18.072189
10366 10:02:18.078809 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10367 10:02:18.082249
10368 10:02:18.099038 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10369 10:02:18.099612
10370 10:02:18.102201 Choosing best match conf-1 for compat google,spherion-rev2.
10371 10:02:18.108380
10372 10:02:18.112152 Connected to device vid:did:rid of 1ae0:0028:00
10373 10:02:18.119340
10374 10:02:18.123140 tpm_get_response: command 0x17b, return code 0x0
10375 10:02:18.123706
10376 10:02:18.129297 ec_init: CrosEC protocol v3 supported (256, 248)
10377 10:02:18.129838
10378 10:02:18.132878 tpm_cleanup: add release locality here.
10379 10:02:18.133435
10380 10:02:18.136122 Shutting down all USB controllers.
10381 10:02:18.136676
10382 10:02:18.138918 Removing current net device
10383 10:02:18.139375
10384 10:02:18.142942 Exiting depthcharge with code 4 at timestamp: 62754943
10385 10:02:18.143525
10386 10:02:18.145674 LZMA decompressing kernel-1 to 0x821a6718
10387 10:02:18.146134
10388 10:02:18.149077 LZMA decompressing kernel-1 to 0x40000000
10389 10:02:19.538431
10390 10:02:19.539066 jumping to kernel
10391 10:02:19.540641 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10392 10:02:19.541172 start: 2.2.5 auto-login-action (timeout 00:03:50) [common]
10393 10:02:19.541577 Setting prompt string to ['Linux version [0-9]']
10394 10:02:19.542019 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10395 10:02:19.542407 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10396 10:02:19.621186
10397 10:02:19.624717 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10398 10:02:19.627813 start: 2.2.5.1 login-action (timeout 00:03:50) [common]
10399 10:02:19.628311 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10400 10:02:19.628709 Setting prompt string to []
10401 10:02:19.629135 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10402 10:02:19.629534 Using line separator: #'\n'#
10403 10:02:19.629869 No login prompt set.
10404 10:02:19.630206 Parsing kernel messages
10405 10:02:19.630772 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10406 10:02:19.631363 [login-action] Waiting for messages, (timeout 00:03:50)
10407 10:02:19.647743 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j18697-arm64-gcc-10-defconfig-arm64-chromebook-vvl9c) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 23 09:52:58 UTC 2023
10408 10:02:19.650453 [ 0.000000] random: crng init done
10409 10:02:19.657502 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10410 10:02:19.658054 [ 0.000000] efi: UEFI not found.
10411 10:02:19.667187 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10412 10:02:19.673804 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10413 10:02:19.684158 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10414 10:02:19.693634 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10415 10:02:19.700412 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10416 10:02:19.706987 [ 0.000000] printk: bootconsole [mtk8250] enabled
10417 10:02:19.713695 [ 0.000000] NUMA: No NUMA configuration found
10418 10:02:19.719968 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10419 10:02:19.722819 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10420 10:02:19.726504 [ 0.000000] Zone ranges:
10421 10:02:19.733224 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10422 10:02:19.736540 [ 0.000000] DMA32 empty
10423 10:02:19.742684 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10424 10:02:19.746316 [ 0.000000] Movable zone start for each node
10425 10:02:19.749735 [ 0.000000] Early memory node ranges
10426 10:02:19.755927 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10427 10:02:19.762816 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10428 10:02:19.769666 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10429 10:02:19.775855 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10430 10:02:19.782157 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10431 10:02:19.789371 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10432 10:02:19.845097 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10433 10:02:19.851938 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10434 10:02:19.858364 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10435 10:02:19.861635 [ 0.000000] psci: probing for conduit method from DT.
10436 10:02:19.867957 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10437 10:02:19.871179 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10438 10:02:19.878018 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10439 10:02:19.881135 [ 0.000000] psci: SMC Calling Convention v1.2
10440 10:02:19.888291 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10441 10:02:19.891376 [ 0.000000] Detected VIPT I-cache on CPU0
10442 10:02:19.897800 [ 0.000000] CPU features: detected: GIC system register CPU interface
10443 10:02:19.904307 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10444 10:02:19.910815 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10445 10:02:19.917874 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10446 10:02:19.927529 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10447 10:02:19.933822 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10448 10:02:19.937366 [ 0.000000] alternatives: applying boot alternatives
10449 10:02:19.943919 [ 0.000000] Fallback order for Node 0: 0
10450 10:02:19.950779 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10451 10:02:19.954007 [ 0.000000] Policy zone: Normal
10452 10:02:19.967601 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10453 10:02:19.977045 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10454 10:02:19.989568 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10455 10:02:19.999049 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10456 10:02:20.005910 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10457 10:02:20.008589 <6>[ 0.000000] software IO TLB: area num 8.
10458 10:02:20.065543 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10459 10:02:20.214912 <6>[ 0.000000] Memory: 7923156K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 429612K reserved, 32768K cma-reserved)
10460 10:02:20.221450 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10461 10:02:20.227608 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10462 10:02:20.231119 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10463 10:02:20.238392 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10464 10:02:20.244349 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10465 10:02:20.248016 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10466 10:02:20.257601 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10467 10:02:20.264431 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10468 10:02:20.271160 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10469 10:02:20.277241 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10470 10:02:20.280550 <6>[ 0.000000] GICv3: 608 SPIs implemented
10471 10:02:20.283879 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10472 10:02:20.290392 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10473 10:02:20.293917 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10474 10:02:20.300376 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10475 10:02:20.314287 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10476 10:02:20.327050 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10477 10:02:20.333695 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10478 10:02:20.341435 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10479 10:02:20.354845 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10480 10:02:20.361568 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10481 10:02:20.368122 <6>[ 0.009228] Console: colour dummy device 80x25
10482 10:02:20.377939 <6>[ 0.013983] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10483 10:02:20.384764 <6>[ 0.024424] pid_max: default: 32768 minimum: 301
10484 10:02:20.387412 <6>[ 0.029326] LSM: Security Framework initializing
10485 10:02:20.394584 <6>[ 0.034265] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10486 10:02:20.404363 <6>[ 0.042046] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10487 10:02:20.414410 <6>[ 0.051476] cblist_init_generic: Setting adjustable number of callback queues.
10488 10:02:20.417537 <6>[ 0.058919] cblist_init_generic: Setting shift to 3 and lim to 1.
10489 10:02:20.427509 <6>[ 0.065258] cblist_init_generic: Setting adjustable number of callback queues.
10490 10:02:20.434048 <6>[ 0.072683] cblist_init_generic: Setting shift to 3 and lim to 1.
10491 10:02:20.437617 <6>[ 0.079082] rcu: Hierarchical SRCU implementation.
10492 10:02:20.444342 <6>[ 0.084095] rcu: Max phase no-delay instances is 1000.
10493 10:02:20.450194 <6>[ 0.091128] EFI services will not be available.
10494 10:02:20.453410 <6>[ 0.096103] smp: Bringing up secondary CPUs ...
10495 10:02:20.462560 <6>[ 0.101186] Detected VIPT I-cache on CPU1
10496 10:02:20.468917 <6>[ 0.101256] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10497 10:02:20.475281 <6>[ 0.101286] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10498 10:02:20.478837 <6>[ 0.101619] Detected VIPT I-cache on CPU2
10499 10:02:20.485606 <6>[ 0.101667] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10500 10:02:20.495199 <6>[ 0.101683] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10501 10:02:20.498396 <6>[ 0.101937] Detected VIPT I-cache on CPU3
10502 10:02:20.505226 <6>[ 0.101983] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10503 10:02:20.511919 <6>[ 0.101997] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10504 10:02:20.514987 <6>[ 0.102303] CPU features: detected: Spectre-v4
10505 10:02:20.522059 <6>[ 0.102310] CPU features: detected: Spectre-BHB
10506 10:02:20.525408 <6>[ 0.102314] Detected PIPT I-cache on CPU4
10507 10:02:20.531854 <6>[ 0.102371] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10508 10:02:20.539052 <6>[ 0.102389] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10509 10:02:20.545291 <6>[ 0.102683] Detected PIPT I-cache on CPU5
10510 10:02:20.551824 <6>[ 0.102745] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10511 10:02:20.558417 <6>[ 0.102762] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10512 10:02:20.561264 <6>[ 0.103045] Detected PIPT I-cache on CPU6
10513 10:02:20.568157 <6>[ 0.103110] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10514 10:02:20.578013 <6>[ 0.103126] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10515 10:02:20.580991 <6>[ 0.103422] Detected PIPT I-cache on CPU7
10516 10:02:20.587748 <6>[ 0.103485] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10517 10:02:20.594147 <6>[ 0.103502] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10518 10:02:20.597803 <6>[ 0.103549] smp: Brought up 1 node, 8 CPUs
10519 10:02:20.604068 <6>[ 0.244968] SMP: Total of 8 processors activated.
10520 10:02:20.607287 <6>[ 0.249888] CPU features: detected: 32-bit EL0 Support
10521 10:02:20.617448 <6>[ 0.255285] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10522 10:02:20.623901 <6>[ 0.264140] CPU features: detected: Common not Private translations
10523 10:02:20.630738 <6>[ 0.270615] CPU features: detected: CRC32 instructions
10524 10:02:20.637113 <6>[ 0.275967] CPU features: detected: RCpc load-acquire (LDAPR)
10525 10:02:20.640046 <6>[ 0.281927] CPU features: detected: LSE atomic instructions
10526 10:02:20.646991 <6>[ 0.287709] CPU features: detected: Privileged Access Never
10527 10:02:20.653930 <6>[ 0.293524] CPU features: detected: RAS Extension Support
10528 10:02:20.660338 <6>[ 0.299133] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10529 10:02:20.663607 <6>[ 0.306354] CPU: All CPU(s) started at EL2
10530 10:02:20.670389 <6>[ 0.310670] alternatives: applying system-wide alternatives
10531 10:02:20.679871 <6>[ 0.321413] devtmpfs: initialized
10532 10:02:20.692284 <6>[ 0.330259] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10533 10:02:20.702514 <6>[ 0.340219] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10534 10:02:20.708619 <6>[ 0.348268] pinctrl core: initialized pinctrl subsystem
10535 10:02:20.712062 <6>[ 0.354945] DMI not present or invalid.
10536 10:02:20.718665 <6>[ 0.359349] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10537 10:02:20.729066 <6>[ 0.366197] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10538 10:02:20.735205 <6>[ 0.373779] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10539 10:02:20.744806 <6>[ 0.382004] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10540 10:02:20.748361 <6>[ 0.390247] audit: initializing netlink subsys (disabled)
10541 10:02:20.758287 <5>[ 0.395940] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10542 10:02:20.765210 <6>[ 0.396651] thermal_sys: Registered thermal governor 'step_wise'
10543 10:02:20.771561 <6>[ 0.403909] thermal_sys: Registered thermal governor 'power_allocator'
10544 10:02:20.774929 <6>[ 0.410165] cpuidle: using governor menu
10545 10:02:20.781520 <6>[ 0.421125] NET: Registered PF_QIPCRTR protocol family
10546 10:02:20.788181 <6>[ 0.426606] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10547 10:02:20.794872 <6>[ 0.433709] ASID allocator initialised with 32768 entries
10548 10:02:20.797724 <6>[ 0.440276] Serial: AMBA PL011 UART driver
10549 10:02:20.808050 <4>[ 0.449093] Trying to register duplicate clock ID: 134
10550 10:02:20.862184 <6>[ 0.506449] KASLR enabled
10551 10:02:20.876358 <6>[ 0.514153] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10552 10:02:20.882809 <6>[ 0.521167] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10553 10:02:20.889198 <6>[ 0.527657] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10554 10:02:20.895973 <6>[ 0.534661] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10555 10:02:20.902661 <6>[ 0.541150] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10556 10:02:20.908832 <6>[ 0.548156] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10557 10:02:20.915948 <6>[ 0.554645] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10558 10:02:20.922410 <6>[ 0.561650] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10559 10:02:20.925779 <6>[ 0.569149] ACPI: Interpreter disabled.
10560 10:02:20.934135 <6>[ 0.575535] iommu: Default domain type: Translated
10561 10:02:20.941039 <6>[ 0.580647] iommu: DMA domain TLB invalidation policy: strict mode
10562 10:02:20.944283 <5>[ 0.587301] SCSI subsystem initialized
10563 10:02:20.950565 <6>[ 0.591468] usbcore: registered new interface driver usbfs
10564 10:02:20.957548 <6>[ 0.597200] usbcore: registered new interface driver hub
10565 10:02:20.960388 <6>[ 0.602750] usbcore: registered new device driver usb
10566 10:02:20.967819 <6>[ 0.608841] pps_core: LinuxPPS API ver. 1 registered
10567 10:02:20.977338 <6>[ 0.614034] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10568 10:02:20.980820 <6>[ 0.623383] PTP clock support registered
10569 10:02:20.984324 <6>[ 0.627625] EDAC MC: Ver: 3.0.0
10570 10:02:20.991272 <6>[ 0.632775] FPGA manager framework
10571 10:02:20.998666 <6>[ 0.636455] Advanced Linux Sound Architecture Driver Initialized.
10572 10:02:21.000855 <6>[ 0.643223] vgaarb: loaded
10573 10:02:21.007756 <6>[ 0.646402] clocksource: Switched to clocksource arch_sys_counter
10574 10:02:21.011237 <5>[ 0.652835] VFS: Disk quotas dquot_6.6.0
10575 10:02:21.018095 <6>[ 0.657020] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10576 10:02:21.020716 <6>[ 0.664208] pnp: PnP ACPI: disabled
10577 10:02:21.029839 <6>[ 0.670912] NET: Registered PF_INET protocol family
10578 10:02:21.039393 <6>[ 0.676512] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10579 10:02:21.050751 <6>[ 0.688826] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10580 10:02:21.060572 <6>[ 0.697640] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10581 10:02:21.067219 <6>[ 0.705608] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10582 10:02:21.077008 <6>[ 0.714304] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10583 10:02:21.083700 <6>[ 0.724047] TCP: Hash tables configured (established 65536 bind 65536)
10584 10:02:21.090094 <6>[ 0.730912] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10585 10:02:21.099980 <6>[ 0.738113] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10586 10:02:21.106753 <6>[ 0.745790] NET: Registered PF_UNIX/PF_LOCAL protocol family
10587 10:02:21.113599 <6>[ 0.751952] RPC: Registered named UNIX socket transport module.
10588 10:02:21.116608 <6>[ 0.758108] RPC: Registered udp transport module.
10589 10:02:21.123513 <6>[ 0.763043] RPC: Registered tcp transport module.
10590 10:02:21.130221 <6>[ 0.767976] RPC: Registered tcp NFSv4.1 backchannel transport module.
10591 10:02:21.133372 <6>[ 0.774643] PCI: CLS 0 bytes, default 64
10592 10:02:21.136771 <6>[ 0.779043] Unpacking initramfs...
10593 10:02:21.152949 <6>[ 0.791016] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10594 10:02:21.162790 <6>[ 0.799676] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10595 10:02:21.166302 <6>[ 0.808527] kvm [1]: IPA Size Limit: 40 bits
10596 10:02:21.172789 <6>[ 0.813045] kvm [1]: GICv3: no GICV resource entry
10597 10:02:21.176267 <6>[ 0.818068] kvm [1]: disabling GICv2 emulation
10598 10:02:21.182856 <6>[ 0.822756] kvm [1]: GIC system register CPU interface enabled
10599 10:02:21.189407 <6>[ 0.830474] kvm [1]: vgic interrupt IRQ18
10600 10:02:21.192273 <6>[ 0.834878] kvm [1]: VHE mode initialized successfully
10601 10:02:21.200228 <5>[ 0.841263] Initialise system trusted keyrings
10602 10:02:21.206706 <6>[ 0.846046] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10603 10:02:21.214786 <6>[ 0.855979] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10604 10:02:21.221603 <5>[ 0.862353] NFS: Registering the id_resolver key type
10605 10:02:21.224528 <5>[ 0.867650] Key type id_resolver registered
10606 10:02:21.231322 <5>[ 0.872066] Key type id_legacy registered
10607 10:02:21.237718 <6>[ 0.876345] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10608 10:02:21.244562 <6>[ 0.883267] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10609 10:02:21.251472 <6>[ 0.890963] 9p: Installing v9fs 9p2000 file system support
10610 10:02:21.287000 <5>[ 0.928126] Key type asymmetric registered
10611 10:02:21.289954 <5>[ 0.932457] Asymmetric key parser 'x509' registered
10612 10:02:21.300840 <6>[ 0.937595] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10613 10:02:21.303152 <6>[ 0.945209] io scheduler mq-deadline registered
10614 10:02:21.306356 <6>[ 0.949983] io scheduler kyber registered
10615 10:02:21.325484 <6>[ 0.966759] EINJ: ACPI disabled.
10616 10:02:21.357522 <4>[ 0.991977] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 10:02:21.367147 <4>[ 1.002607] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 10:02:21.381993 <6>[ 1.023275] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10619 10:02:21.389679 <6>[ 1.031190] printk: console [ttyS0] disabled
10620 10:02:21.417736 <6>[ 1.055836] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10621 10:02:21.424866 <6>[ 1.065309] printk: console [ttyS0] enabled
10622 10:02:21.427766 <6>[ 1.065309] printk: console [ttyS0] enabled
10623 10:02:21.434439 <6>[ 1.074203] printk: bootconsole [mtk8250] disabled
10624 10:02:21.437686 <6>[ 1.074203] printk: bootconsole [mtk8250] disabled
10625 10:02:21.444201 <6>[ 1.085426] SuperH (H)SCI(F) driver initialized
10626 10:02:21.447588 <6>[ 1.090716] msm_serial: driver initialized
10627 10:02:21.461419 <6>[ 1.099698] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10628 10:02:21.471695 <6>[ 1.108243] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10629 10:02:21.478445 <6>[ 1.116788] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10630 10:02:21.487854 <6>[ 1.125418] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10631 10:02:21.498317 <6>[ 1.134125] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10632 10:02:21.504404 <6>[ 1.142846] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10633 10:02:21.514798 <6>[ 1.151387] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10634 10:02:21.521421 <6>[ 1.160188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10635 10:02:21.530708 <6>[ 1.168731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10636 10:02:21.542702 <6>[ 1.184150] loop: module loaded
10637 10:02:21.549639 <6>[ 1.190136] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10638 10:02:21.572297 <4>[ 1.213684] mtk-pmic-keys: Failed to locate of_node [id: -1]
10639 10:02:21.579487 <6>[ 1.220741] megasas: 07.719.03.00-rc1
10640 10:02:21.588913 <6>[ 1.230408] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10641 10:02:21.596796 <6>[ 1.237782] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10642 10:02:21.613106 <6>[ 1.254463] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10643 10:02:21.674093 <6>[ 1.308583] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10644 10:02:23.119219 <6>[ 2.760890] Freeing initrd memory: 46396K
10645 10:02:23.130068 <6>[ 2.771320] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10646 10:02:23.140531 <6>[ 2.782152] tun: Universal TUN/TAP device driver, 1.6
10647 10:02:23.143596 <6>[ 2.788211] thunder_xcv, ver 1.0
10648 10:02:23.147161 <6>[ 2.791715] thunder_bgx, ver 1.0
10649 10:02:23.150425 <6>[ 2.795208] nicpf, ver 1.0
10650 10:02:23.160826 <6>[ 2.799244] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10651 10:02:23.167471 <6>[ 2.806720] hns3: Copyright (c) 2017 Huawei Corporation.
10652 10:02:23.170569 <6>[ 2.812308] hclge is initializing
10653 10:02:23.174562 <6>[ 2.815883] e1000: Intel(R) PRO/1000 Network Driver
10654 10:02:23.180665 <6>[ 2.821012] e1000: Copyright (c) 1999-2006 Intel Corporation.
10655 10:02:23.187130 <6>[ 2.827028] e1000e: Intel(R) PRO/1000 Network Driver
10656 10:02:23.190480 <6>[ 2.832243] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10657 10:02:23.197349 <6>[ 2.838429] igb: Intel(R) Gigabit Ethernet Network Driver
10658 10:02:23.203708 <6>[ 2.844079] igb: Copyright (c) 2007-2014 Intel Corporation.
10659 10:02:23.210202 <6>[ 2.849913] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10660 10:02:23.217133 <6>[ 2.856431] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10661 10:02:23.220302 <6>[ 2.862898] sky2: driver version 1.30
10662 10:02:23.226897 <6>[ 2.867897] VFIO - User Level meta-driver version: 0.3
10663 10:02:23.234661 <6>[ 2.876128] usbcore: registered new interface driver usb-storage
10664 10:02:23.241540 <6>[ 2.882574] usbcore: registered new device driver onboard-usb-hub
10665 10:02:23.250128 <6>[ 2.891657] mt6397-rtc mt6359-rtc: registered as rtc0
10666 10:02:23.259573 <6>[ 2.897121] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-23T10:02:22 UTC (1692784942)
10667 10:02:23.263158 <6>[ 2.906693] i2c_dev: i2c /dev entries driver
10668 10:02:23.280796 <6>[ 2.918404] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10669 10:02:23.301213 <6>[ 2.942396] cpu cpu0: EM: created perf domain
10670 10:02:23.304084 <6>[ 2.947396] cpu cpu4: EM: created perf domain
10671 10:02:23.311822 <6>[ 2.952990] sdhci: Secure Digital Host Controller Interface driver
10672 10:02:23.318114 <6>[ 2.959423] sdhci: Copyright(c) Pierre Ossman
10673 10:02:23.324568 <6>[ 2.964386] Synopsys Designware Multimedia Card Interface Driver
10674 10:02:23.331249 <6>[ 2.971020] sdhci-pltfm: SDHCI platform and OF driver helper
10675 10:02:23.334619 <6>[ 2.971086] mmc0: CQHCI version 5.10
10676 10:02:23.341521 <6>[ 2.981370] ledtrig-cpu: registered to indicate activity on CPUs
10677 10:02:23.348071 <6>[ 2.988390] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10678 10:02:23.354558 <6>[ 2.995453] usbcore: registered new interface driver usbhid
10679 10:02:23.357824 <6>[ 3.001275] usbhid: USB HID core driver
10680 10:02:23.364498 <6>[ 3.005472] spi_master spi0: will run message pump with realtime priority
10681 10:02:23.408775 <6>[ 3.043496] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10682 10:02:23.427822 <6>[ 3.059090] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10683 10:02:23.434384 <6>[ 3.074146] cros-ec-spi spi0.0: Chrome EC device registered
10684 10:02:23.437840 <6>[ 3.080178] mmc0: Command Queue Engine enabled
10685 10:02:23.443992 <6>[ 3.084930] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10686 10:02:23.450897 <6>[ 3.092304] mmcblk0: mmc0:0001 DA4128 116 GiB
10687 10:02:23.460552 <6>[ 3.098454] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10688 10:02:23.467393 <6>[ 3.101760] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10689 10:02:23.474059 <6>[ 3.108762] NET: Registered PF_PACKET protocol family
10690 10:02:23.477085 <6>[ 3.114546] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10691 10:02:23.483576 <6>[ 3.119111] 9pnet: Installing 9P2000 support
10692 10:02:23.487146 <6>[ 3.124811] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10693 10:02:23.490156 <5>[ 3.128773] Key type dns_resolver registered
10694 10:02:23.496702 <6>[ 3.134567] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10695 10:02:23.503294 <6>[ 3.138961] registered taskstats version 1
10696 10:02:23.506747 <5>[ 3.149393] Loading compiled-in X.509 certificates
10697 10:02:23.545135 <4>[ 3.179873] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10698 10:02:23.554861 <4>[ 3.190667] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10699 10:02:23.561573 <3>[ 3.201201] debugfs: File 'uA_load' in directory '/' already present!
10700 10:02:23.568559 <3>[ 3.207960] debugfs: File 'min_uV' in directory '/' already present!
10701 10:02:23.574849 <3>[ 3.214592] debugfs: File 'max_uV' in directory '/' already present!
10702 10:02:23.581157 <3>[ 3.221200] debugfs: File 'constraint_flags' in directory '/' already present!
10703 10:02:23.592828 <3>[ 3.230988] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10704 10:02:23.604789 <6>[ 3.246430] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10705 10:02:23.611463 <6>[ 3.253167] xhci-mtk 11200000.usb: xHCI Host Controller
10706 10:02:23.618386 <6>[ 3.258666] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10707 10:02:23.628573 <6>[ 3.266558] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10708 10:02:23.634864 <6>[ 3.275988] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10709 10:02:23.641551 <6>[ 3.282220] xhci-mtk 11200000.usb: xHCI Host Controller
10710 10:02:23.647960 <6>[ 3.287737] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10711 10:02:23.654878 <6>[ 3.295395] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10712 10:02:23.661779 <6>[ 3.303279] hub 1-0:1.0: USB hub found
10713 10:02:23.665443 <6>[ 3.307304] hub 1-0:1.0: 1 port detected
10714 10:02:23.675156 <6>[ 3.311603] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10715 10:02:23.678140 <6>[ 3.320401] hub 2-0:1.0: USB hub found
10716 10:02:23.681375 <6>[ 3.324425] hub 2-0:1.0: 1 port detected
10717 10:02:23.691069 <6>[ 3.332562] mtk-msdc 11f70000.mmc: Got CD GPIO
10718 10:02:23.703034 <6>[ 3.341450] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10719 10:02:23.709793 <6>[ 3.349520] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10720 10:02:23.719971 <4>[ 3.357463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10721 10:02:23.730386 <6>[ 3.367030] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10722 10:02:23.736053 <6>[ 3.375108] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10723 10:02:23.743294 <6>[ 3.383114] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10724 10:02:23.752840 <6>[ 3.391032] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10725 10:02:23.759215 <6>[ 3.398850] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10726 10:02:23.769502 <6>[ 3.406669] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10727 10:02:23.779211 <6>[ 3.417080] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10728 10:02:23.785411 <6>[ 3.425441] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10729 10:02:23.795936 <6>[ 3.433790] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10730 10:02:23.802775 <6>[ 3.442128] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10731 10:02:23.811977 <6>[ 3.450466] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10732 10:02:23.822211 <6>[ 3.458809] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10733 10:02:23.829135 <6>[ 3.467147] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10734 10:02:23.838780 <6>[ 3.475485] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10735 10:02:23.845095 <6>[ 3.483823] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10736 10:02:23.855260 <6>[ 3.492162] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10737 10:02:23.861706 <6>[ 3.500500] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10738 10:02:23.871533 <6>[ 3.508837] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10739 10:02:23.878330 <6>[ 3.517175] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10740 10:02:23.888305 <6>[ 3.525513] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10741 10:02:23.895118 <6>[ 3.533851] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10742 10:02:23.901360 <6>[ 3.542601] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10743 10:02:23.908136 <6>[ 3.549758] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10744 10:02:23.914569 <6>[ 3.556520] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10745 10:02:23.925379 <6>[ 3.563280] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10746 10:02:23.931354 <6>[ 3.570218] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10747 10:02:23.938035 <6>[ 3.577078] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10748 10:02:23.947948 <6>[ 3.586209] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10749 10:02:23.958109 <6>[ 3.595328] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10750 10:02:23.968000 <6>[ 3.604622] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10751 10:02:23.978101 <6>[ 3.614092] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10752 10:02:23.987515 <6>[ 3.623559] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10753 10:02:23.994196 <6>[ 3.632679] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10754 10:02:24.004168 <6>[ 3.642146] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10755 10:02:24.014088 <6>[ 3.651266] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10756 10:02:24.023783 <6>[ 3.660570] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10757 10:02:24.033704 <6>[ 3.670730] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10758 10:02:24.043905 <6>[ 3.682585] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10759 10:02:24.095980 <6>[ 3.734670] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10760 10:02:24.250392 <6>[ 3.892178] hub 1-1:1.0: USB hub found
10761 10:02:24.253649 <6>[ 3.896633] hub 1-1:1.0: 4 ports detected
10762 10:02:24.376364 <6>[ 4.014683] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10763 10:02:24.402575 <6>[ 4.044412] hub 2-1:1.0: USB hub found
10764 10:02:24.405815 <6>[ 4.048907] hub 2-1:1.0: 3 ports detected
10765 10:02:24.576144 <6>[ 4.214719] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10766 10:02:24.708002 <6>[ 4.348903] hub 1-1.1:1.0: USB hub found
10767 10:02:24.710370 <6>[ 4.353246] hub 1-1.1:1.0: 4 ports detected
10768 10:02:24.824290 <6>[ 4.462762] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10769 10:02:24.956958 <6>[ 4.598593] hub 1-1.4:1.0: USB hub found
10770 10:02:24.959986 <6>[ 4.603265] hub 1-1.4:1.0: 2 ports detected
10771 10:02:25.040428 <6>[ 4.678726] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10772 10:02:25.228292 <6>[ 4.866706] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10773 10:02:25.313170 <3>[ 4.954966] usb 1-1.1.4: device descriptor read/64, error -32
10774 10:02:25.504934 <3>[ 5.146839] usb 1-1.1.4: device descriptor read/64, error -32
10775 10:02:25.700242 <6>[ 5.338734] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10776 10:02:25.887943 <6>[ 5.526695] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10777 10:02:25.972618 <3>[ 5.614862] usb 1-1.1.4: device descriptor read/64, error -32
10778 10:02:26.164436 <3>[ 5.806756] usb 1-1.1.4: device descriptor read/64, error -32
10779 10:02:26.277104 <6>[ 5.919255] usb 1-1.1-port4: attempt power cycle
10780 10:02:26.364656 <6>[ 6.002661] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10781 10:02:26.888731 <6>[ 6.526780] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10782 10:02:26.894676 <4>[ 6.534187] usb 1-1.1.4: Device not responding to setup address.
10783 10:02:27.105048 <4>[ 6.746946] usb 1-1.1.4: Device not responding to setup address.
10784 10:02:27.316703 <3>[ 6.958760] usb 1-1.1.4: device not accepting address 10, error -71
10785 10:02:27.403812 <6>[ 7.042724] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10786 10:02:27.410758 <4>[ 7.050129] usb 1-1.1.4: Device not responding to setup address.
10787 10:02:27.621123 <4>[ 7.262950] usb 1-1.1.4: Device not responding to setup address.
10788 10:02:27.832869 <3>[ 7.474718] usb 1-1.1.4: device not accepting address 11, error -71
10789 10:02:27.839507 <3>[ 7.481758] usb 1-1.1-port4: unable to enumerate USB device
10790 10:02:36.337417 <6>[ 15.983699] ALSA device list:
10791 10:02:36.344020 <6>[ 15.986997] No soundcards found.
10792 10:02:36.351783 <6>[ 15.994968] Freeing unused kernel memory: 8384K
10793 10:02:36.355113 <6>[ 16.000078] Run /init as init process
10794 10:02:36.404255 <6>[ 16.047045] NET: Registered PF_INET6 protocol family
10795 10:02:36.410281 <6>[ 16.053545] Segment Routing with IPv6
10796 10:02:36.413706 <6>[ 16.057497] In-situ OAM (IOAM) with IPv6
10797 10:02:36.448157 <30>[ 16.071282] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10798 10:02:36.451481 <30>[ 16.095067] systemd[1]: Detected architecture arm64.
10799 10:02:36.451953
10800 10:02:36.458252 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10801 10:02:36.458904
10802 10:02:36.471235 <30>[ 16.114677] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10803 10:02:36.639480 <30>[ 16.279123] systemd[1]: Queued start job for default target Graphical Interface.
10804 10:02:36.684199 <30>[ 16.327281] systemd[1]: Created slice system-getty.slice.
10805 10:02:36.691414 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10806 10:02:36.708468 <30>[ 16.351222] systemd[1]: Created slice system-modprobe.slice.
10807 10:02:36.714630 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10808 10:02:36.733191 <30>[ 16.376012] systemd[1]: Created slice system-serial\x2dgetty.slice.
10809 10:02:36.743575 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10810 10:02:36.756230 <30>[ 16.399223] systemd[1]: Created slice User and Session Slice.
10811 10:02:36.762671 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10812 10:02:36.783567 <30>[ 16.423406] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10813 10:02:36.793459 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10814 10:02:36.810721 <30>[ 16.450763] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10815 10:02:36.817337 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10816 10:02:36.838072 <30>[ 16.474723] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10817 10:02:36.844482 <30>[ 16.486833] systemd[1]: Reached target Local Encrypted Volumes.
10818 10:02:36.851314 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10819 10:02:36.868049 <30>[ 16.511203] systemd[1]: Reached target Paths.
10820 10:02:36.871395 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10821 10:02:36.887463 <30>[ 16.530665] systemd[1]: Reached target Remote File Systems.
10822 10:02:36.893962 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10823 10:02:36.907266 <30>[ 16.550628] systemd[1]: Reached target Slices.
10824 10:02:36.910490 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10825 10:02:36.927410 <30>[ 16.570663] systemd[1]: Reached target Swap.
10826 10:02:36.930908 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10827 10:02:36.951248 <30>[ 16.591119] systemd[1]: Listening on initctl Compatibility Named Pipe.
10828 10:02:36.957619 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10829 10:02:36.972662 <30>[ 16.616117] systemd[1]: Listening on Journal Audit Socket.
10830 10:02:36.979159 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10831 10:02:36.996330 <30>[ 16.639811] systemd[1]: Listening on Journal Socket (/dev/log).
10832 10:02:37.002926 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10833 10:02:37.020854 <30>[ 16.663858] systemd[1]: Listening on Journal Socket.
10834 10:02:37.027180 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10835 10:02:37.043472 <30>[ 16.683325] systemd[1]: Listening on Network Service Netlink Socket.
10836 10:02:37.050370 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10837 10:02:37.064908 <30>[ 16.707864] systemd[1]: Listening on udev Control Socket.
10838 10:02:37.071229 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10839 10:02:37.088519 <30>[ 16.731717] systemd[1]: Listening on udev Kernel Socket.
10840 10:02:37.094928 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10841 10:02:37.135658 <30>[ 16.778816] systemd[1]: Mounting Huge Pages File System...
10842 10:02:37.142639 Mounting [0;1;39mHuge Pages File System[0m...
10843 10:02:37.157220 <30>[ 16.800433] systemd[1]: Mounting POSIX Message Queue File System...
10844 10:02:37.164328 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10845 10:02:37.181715 <30>[ 16.824622] systemd[1]: Mounting Kernel Debug File System...
10846 10:02:37.187751 Mounting [0;1;39mKernel Debug File System[0m...
10847 10:02:37.207511 <30>[ 16.846946] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10848 10:02:37.219207 <30>[ 16.858846] systemd[1]: Starting Create list of static device nodes for the current kernel...
10849 10:02:37.225739 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10850 10:02:37.247784 <30>[ 16.890925] systemd[1]: Starting Load Kernel Module configfs...
10851 10:02:37.254906 Starting [0;1;39mLoad Kernel Module configfs[0m...
10852 10:02:37.272201 <30>[ 16.915238] systemd[1]: Starting Load Kernel Module drm...
10853 10:02:37.278915 Starting [0;1;39mLoad Kernel Module drm[0m...
10854 10:02:37.295142 <30>[ 16.935121] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10855 10:02:37.340536 <30>[ 16.983517] systemd[1]: Starting Journal Service...
10856 10:02:37.346863 Starting [0;1;39mJournal Service[0m...
10857 10:02:37.364150 <30>[ 17.007464] systemd[1]: Starting Load Kernel Modules...
10858 10:02:37.370908 Starting [0;1;39mLoad Kernel Modules[0m...
10859 10:02:37.391986 <30>[ 17.031667] systemd[1]: Starting Remount Root and Kernel File Systems...
10860 10:02:37.398457 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10861 10:02:37.414285 <30>[ 17.057485] systemd[1]: Starting Coldplug All udev Devices...
10862 10:02:37.421199 Starting [0;1;39mColdplug All udev Devices[0m...
10863 10:02:37.438784 <30>[ 17.081440] systemd[1]: Started Journal Service.
10864 10:02:37.444805 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10865 10:02:37.461628 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10866 10:02:37.476550 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10867 10:02:37.492120 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10868 10:02:37.512034 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10869 10:02:37.531076 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10870 10:02:37.550084 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10871 10:02:37.569724 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10872 10:02:37.613995 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10873 10:02:37.627615 See 'systemctl status systemd-remount-fs.service' for details.
10874 10:02:37.651575 Mounting [0;1;39mKernel Configuration File System[0m...
10875 10:02:37.672868 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10876 10:02:37.684117 <46>[ 17.324054] systemd-journald[177]: Received client request to flush runtime journal.
10877 10:02:37.695525 Starting [0;1;39mLoad/Save Random Seed[0m...
10878 10:02:37.716889 Starting [0;1;39mApply Kernel Variables[0m...
10879 10:02:37.736570 Starting [0;1;39mCreate System Users[0m...
10880 10:02:37.756699 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10881 10:02:37.773366 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10882 10:02:37.792466 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10883 10:02:37.805030 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10884 10:02:37.820903 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10885 10:02:37.837108 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10886 10:02:37.892225 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10887 10:02:37.915183 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10888 10:02:37.927404 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10889 10:02:37.943501 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10890 10:02:37.992812 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10891 10:02:38.018841 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10892 10:02:38.040850 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10893 10:02:38.063990 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10894 10:02:38.140730 Starting [0;1;39mNetwork Service[0m...
10895 10:02:38.156815 Starting [0;1;39mNetwork Time Synchronization[0m...
10896 10:02:38.178733 Starting [0;1;39mUpdat<6>[ 17.818058] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10897 10:02:38.182406 e UTMP about System Boot/Shutdown[0m...
10898 10:02:38.188471 <6>[ 17.831464] remoteproc remoteproc0: scp is available
10899 10:02:38.195225 <6>[ 17.836787] remoteproc remoteproc0: powering up scp
10900 10:02:38.201947 <4>[ 17.837610] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10901 10:02:38.208553 <6>[ 17.842007] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10902 10:02:38.214783 <6>[ 17.842035] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10903 10:02:38.255591 <4>[ 17.895204] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10904 10:02:38.261869 [[0;32m OK [0m] Finished [0<6>[ 17.904918] mc: Linux media interface: v0.10
10905 10:02:38.272087 ;1;39mUpdate UTMP about System B<6>[ 17.912634] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10906 10:02:38.281760 oot/Shutdown[0m<6>[ 17.921738] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10907 10:02:38.282328 .
10908 10:02:38.291964 <6>[ 17.931652] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10909 10:02:38.301432 <3>[ 17.940410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10910 10:02:38.308332 <3>[ 17.948672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 10:02:38.318019 <3>[ 17.956971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10912 10:02:38.324698 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10913 10:02:38.334757 <3>[ 17.973142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 10:02:38.341252 <3>[ 17.981348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 10:02:38.350981 <3>[ 17.990179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 10:02:38.357387 <6>[ 17.991967] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10917 10:02:38.367532 <6>[ 17.998364] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10918 10:02:38.370893 <6>[ 17.998385] remoteproc remoteproc0: remote processor scp is now up
10919 10:02:38.380762 <3>[ 17.998522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 10:02:38.387276 <6>[ 17.999199] videodev: Linux video capture interface: v2.00
10921 10:02:38.390454 <6>[ 18.006270] usbcore: registered new interface driver r8152
10922 10:02:38.400290 <6>[ 18.007405] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10923 10:02:38.411131 <6>[ 18.010010] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10924 10:02:38.417295 <3>[ 18.014149] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10925 10:02:38.426862 <4>[ 18.036166] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10926 10:02:38.430386 <4>[ 18.036166] Fallback method does not support PEC.
10927 10:02:38.437038 <3>[ 18.040229] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 10:02:38.446713 <6>[ 18.064768] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10929 10:02:38.453327 <3>[ 18.065225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 10:02:38.463594 <3>[ 18.078858] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 10:02:38.466680 <6>[ 18.079576] pci_bus 0000:00: root bus resource [bus 00-ff]
10932 10:02:38.476415 <6>[ 18.079584] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10933 10:02:38.486460 <6>[ 18.079587] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10934 10:02:38.489375 <6>[ 18.079625] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10935 10:02:38.499579 <6>[ 18.079640] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10936 10:02:38.503316 <6>[ 18.079717] pci 0000:00:00.0: supports D1 D2
10937 10:02:38.509771 <6>[ 18.079719] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10938 10:02:38.519477 <6>[ 18.080803] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10939 10:02:38.526293 <6>[ 18.080876] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10940 10:02:38.532906 <6>[ 18.080900] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10941 10:02:38.539708 <6>[ 18.080916] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10942 10:02:38.546053 <6>[ 18.080931] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10943 10:02:38.553073 <6>[ 18.081032] pci 0000:01:00.0: supports D1 D2
10944 10:02:38.559249 <6>[ 18.081034] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10945 10:02:38.566317 <3>[ 18.086882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 10:02:38.575797 <3>[ 18.086885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10947 10:02:38.583168 <3>[ 18.086924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 10:02:38.592511 <6>[ 18.091080] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10949 10:02:38.602477 <6>[ 18.091337] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10950 10:02:38.609348 <6>[ 18.095829] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10951 10:02:38.615953 <3>[ 18.101880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10952 10:02:38.626546 <6>[ 18.110942] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10953 10:02:38.632719 <6>[ 18.111199] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10954 10:02:38.639503 <6>[ 18.111205] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10955 10:02:38.648920 <6>[ 18.111214] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10956 10:02:38.655883 <6>[ 18.111227] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10957 10:02:38.665766 <6>[ 18.111239] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10958 10:02:38.669323 <6>[ 18.111252] pci 0000:00:00.0: PCI bridge to [bus 01]
10959 10:02:38.676237 <6>[ 18.111261] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10960 10:02:38.682716 <6>[ 18.111433] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10961 10:02:38.689685 <6>[ 18.111962] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10962 10:02:38.696203 <6>[ 18.112154] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10963 10:02:38.702441 <3>[ 18.116382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10964 10:02:38.713027 <6>[ 18.117858] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10965 10:02:38.719961 <6>[ 18.122247] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10966 10:02:38.726865 <6>[ 18.134126] usbcore: registered new interface driver cdc_ether
10967 10:02:38.736327 <3>[ 18.139671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10968 10:02:38.743523 <3>[ 18.139684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10969 10:02:38.749580 <6>[ 18.141505] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10970 10:02:38.759579 <5>[ 18.142179] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10971 10:02:38.769445 <6>[ 18.143164] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10972 10:02:38.775989 <6>[ 18.143361] usbcore: registered new interface driver uvcvideo
10973 10:02:38.778877 <6>[ 18.149728] Bluetooth: Core ver 2.22
10974 10:02:38.788995 <3>[ 18.151757] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10975 10:02:38.795709 <6>[ 18.152085] usbcore: registered new interface driver r8153_ecm
10976 10:02:38.803016 <5>[ 18.157687] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10977 10:02:38.808960 <4>[ 18.157764] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10978 10:02:38.815710 <6>[ 18.157772] cfg80211: failed to load regulatory.db
10979 10:02:38.821984 <6>[ 18.158725] NET: Registered PF_BLUETOOTH protocol family
10980 10:02:38.828736 <6>[ 18.176735] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10981 10:02:38.835550 <6>[ 18.180788] Bluetooth: HCI device and connection manager initialized
10982 10:02:38.842026 <6>[ 18.242425] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10983 10:02:38.844962 <6>[ 18.250662] Bluetooth: HCI socket layer initialized
10984 10:02:38.855528 <6>[ 18.255966] r8152 1-1.1.1:1.0: load rtl8153b-2 v1 10/23/19 successfully
10985 10:02:38.858339 <6>[ 18.257498] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10986 10:02:38.868120 <3>[ 18.262761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 10:02:38.874727 <6>[ 18.265515] Bluetooth: L2CAP socket layer initialized
10988 10:02:38.877960 <6>[ 18.290548] mt7921e 0000:01:00.0: ASIC revision: 79610010
10989 10:02:38.884580 <6>[ 18.296879] Bluetooth: SCO socket layer initialized
10990 10:02:38.887457 <6>[ 18.302546] r8152 1-1.1.1:1.0 eth0: v1.12.13
10991 10:02:38.897766 <3>[ 18.329237] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 10:02:38.904373 <6>[ 18.329517] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10993 10:02:38.914057 <3>[ 18.344721] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10994 10:02:38.921319 <3>[ 18.363374] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 10:02:38.930724 <3>[ 18.369787] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10996 10:02:38.934144 <6>[ 18.376038] usbcore: registered new interface driver btusb
10997 10:02:38.947081 <4>[ 18.376850] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10998 10:02:38.950494 <3>[ 18.376859] Bluetooth: hci0: Failed to load firmware file (-2)
10999 10:02:38.957590 <3>[ 18.376862] Bluetooth: hci0: Failed to set up firmware (-2)
11000 10:02:38.967140 <4>[ 18.376865] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11001 10:02:38.980055 <4>[ 18.403516] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11002 10:02:38.986562 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11003 10:02:39.015709 <3>[ 18.656002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 10:02:39.022550 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11005 10:02:39.048260 <3>[ 18.687823] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11006 10:02:39.078570 <3>[ 18.719006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 10:02:39.099925 <4>[ 18.736907] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 10:02:39.145525 <3>[ 18.785522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 10:02:39.172555 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11010 10:02:39.187564 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11011 10:02:39.205584 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11012 10:02:39.222506 [[0;32m OK [0m] Reached targ<4>[ 18.857174] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11013 10:02:39.225317 et [0;1;39mSystem Time Synchronized[0m.
11014 10:02:39.244753 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11015 10:02:39.291955 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11016 10:02:39.314712 Starting [0;1;39mNetwork Name Resolution[0m...
11017 10:02:39.339857 [[0;32m OK [<4>[ 18.977644] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11018 10:02:39.346491 0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11019 10:02:39.364526 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11020 10:02:39.383430 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11021 10:02:39.398728 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11022 10:02:39.416163 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11023 10:02:39.436737 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11024 10:02:39.450257 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11025 10:02:39.463206 <4>[ 19.099078] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11026 10:02:39.470202 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11027 10:02:39.524378 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11028 10:02:39.558770 Starting [0;1;39mUser Login Management[0m...
11029 10:02:39.580948 <4>[ 19.217776] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11030 10:02:39.587785 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11031 10:02:39.604789 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11032 10:02:39.620832 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11033 10:02:39.640918 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11034 10:02:39.659302 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11035 10:02:39.700714 <4>[ 19.337194] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11036 10:02:39.707181 Starting [0;1;39mPermit User Sessions[0m...
11037 10:02:39.723071 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11038 10:02:39.743345 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11039 10:02:39.789149 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11040 10:02:39.821684 <4>[ 19.458185] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11041 10:02:39.827826 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11042 10:02:39.836103 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11043 10:02:39.852104 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11044 10:02:39.867932 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11045 10:02:39.931393 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11046 10:02:39.941324 <4>[ 19.579372] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11047 10:02:39.974874 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11048 10:02:40.028683
11049 10:02:40.029233
11050 10:02:40.031939 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11051 10:02:40.032497
11052 10:02:40.035187 debian-bullseye-arm64 login: root (automatic login)
11053 10:02:40.035639
11054 10:02:40.036011
11055 10:02:40.066758 Linux debian-bullseye-arm64 6.1.<4>[ 19.702210] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11056 10:02:40.070062 45-cip3 #1 SMP PREEMPT Wed Aug 23 09:52:58 UTC 2023 aarch64
11057 10:02:40.070483
11058 10:02:40.076814 The programs included with the Debian GNU/Linux system are free software;
11059 10:02:40.083527 the exact distribution terms for each program are described in the
11060 10:02:40.090270 individual files in /usr/share/doc/*/copyright.
11061 10:02:40.090936
11062 10:02:40.093163 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11063 10:02:40.096438 permitted by applicable law.
11064 10:02:40.097569 Matched prompt #10: / #
11066 10:02:40.098797 Setting prompt string to ['/ #']
11067 10:02:40.099272 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11069 10:02:40.100312 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11070 10:02:40.100890 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
11071 10:02:40.101247 Setting prompt string to ['/ #']
11072 10:02:40.101554 Forcing a shell prompt, looking for ['/ #']
11074 10:02:40.152345 / #
11075 10:02:40.152885 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11076 10:02:40.153427 Waiting using forced prompt support (timeout 00:02:30)
11077 10:02:40.158909
11078 10:02:40.159651 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11079 10:02:40.160114 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11080 10:02:40.160570 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11081 10:02:40.160996 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11082 10:02:40.161413 end: 2 depthcharge-action (duration 00:01:30) [common]
11083 10:02:40.161852 start: 3 lava-test-retry (timeout 00:05:00) [common]
11084 10:02:40.162284 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11085 10:02:40.162662 Using namespace: common
11087 10:02:40.263794 / # #
11088 10:02:40.264396 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11089 10:02:40.265020 <3>[ 19.823044] mt7921e 0000:01:00.0: hardware init failed
11090 10:02:40.270174 #
11091 10:02:40.270877 Using /lava-11336431
11093 10:02:40.371998 / # export SHELL=/bin/sh
11094 10:02:40.372852 export SHELL=/bin/sh<6>[ 19.996872] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11095 10:02:40.373364 <6>[ 20.004982] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11096 10:02:40.378350
11098 10:02:40.479917 / # . /lava-11336431/environment
11099 10:02:40.486446 . /lava-11336431/environment
11101 10:02:40.588326 / # /lava-11336431/bin/lava-test-runner /lava-11336431/0
11102 10:02:40.588901 Test shell timeout: 10s (minimum of the action and connection timeout)
11103 10:02:40.594861 /lava-11336431/bin/lava-test-runner /lava-11336431/0
11104 10:02:40.617156 + export TESTRUN_ID=0_cros-ec
11105 10:02:40.623680 +<8>[ 20.265555] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11336431_1.5.2.3.1>
11106 10:02:40.624376 Received signal: <STARTRUN> 0_cros-ec 11336431_1.5.2.3.1
11107 10:02:40.624767 Starting test lava.0_cros-ec (11336431_1.5.2.3.1)
11108 10:02:40.625176 Skipping test definition patterns.
11109 10:02:40.627135 cd /lava-11336431/0/tests/0_cros-ec
11110 10:02:40.630386 + cat uuid
11111 10:02:40.630829 + UUID=11336431_1.5.2.3.1
11112 10:02:40.633470 + set +x
11113 10:02:40.636649 + python3 -m cros.runners.lava_runner -v
11114 10:02:41.007893 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11115 10:02:41.018116 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11116 10:02:41.018726
11117 10:02:41.024647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11118 10:02:41.025484 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11120 10:02:41.031125 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11121 10:02:41.040887 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11122 10:02:41.041354
11123 10:02:41.047761 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8
11124 10:02:41.048506 Bad test result: ski<8
11125 10:02:41.054081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8>[ 20.694219] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11336431_1.5.2.3.1>
11126 10:02:41.054664 p>
11127 10:02:41.055314 Received signal: <ENDRUN> 0_cros-ec 11336431_1.5.2.3.1
11128 10:02:41.055746 Ending use of test pattern.
11129 10:02:41.056083 Ending test lava.0_cros-ec (11336431_1.5.2.3.1), duration 0.43
11131 10:02:41.057756 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11132 10:02:41.063981 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11133 10:02:41.067112
11134 10:02:41.070813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11135 10:02:41.071592 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11137 10:02:41.077348 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11138 10:02:41.083794 Checks the standard ABI for the main Embedded Controller. ... ok
11139 10:02:41.084356
11140 10:02:41.087395 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11142 10:02:41.090249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11143 10:02:41.093568 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11144 10:02:41.100106 Checks the main Embedded controller character device. ... ok
11145 10:02:41.100517
11146 10:02:41.106880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11147 10:02:41.107548 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11149 10:02:41.109966 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11150 10:02:41.116701 Checks basic comunication with the main Embedded controller. ... ok
11151 10:02:41.117115
11152 10:02:41.123447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11153 10:02:41.124113 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11155 10:02:41.126711 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11156 10:02:41.137026 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11157 10:02:41.137551
11158 10:02:41.139907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11159 10:02:41.140701 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11161 10:02:41.146426 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11162 10:02:41.156242 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11163 10:02:41.156658
11164 10:02:41.159347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11165 10:02:41.160015 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11167 10:02:41.165788 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11168 10:02:41.172920 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11169 10:02:41.173336
11170 10:02:41.179302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11171 10:02:41.179969 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11173 10:02:41.182756 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11174 10:02:41.192488 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11175 10:02:41.192966
11176 10:02:41.199181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11177 10:02:41.199982 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11179 10:02:41.202368 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11180 10:02:41.212072 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11181 10:02:41.212553
11182 10:02:41.218759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11183 10:02:41.219422 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11185 10:02:41.222204 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11186 10:02:41.228459 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11187 10:02:41.228869
11188 10:02:41.235707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11189 10:02:41.236365 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11191 10:02:41.242072 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11192 10:02:41.248619 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11193 10:02:41.249128
11194 10:02:41.255253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11195 10:02:41.255925 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11197 10:02:41.261650 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11198 10:02:41.268533 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11199 10:02:41.271477
11200 10:02:41.275263 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11202 10:02:41.278438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11203 10:02:41.281662 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11204 10:02:41.288177 Check the cros battery ABI. ... skipped 'No BAT found'
11205 10:02:41.288590
11206 10:02:41.294700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11207 10:02:41.295378 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11209 10:02:41.301121 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11210 10:02:41.307862 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11211 10:02:41.308277
11212 10:02:41.315277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11213 10:02:41.316048 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11215 10:02:41.321373 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11216 10:02:41.327602 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11217 10:02:41.328099
11218 10:02:41.331297 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11220 10:02:41.334367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11221 10:02:41.337719 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11222 10:02:41.344014 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11223 10:02:41.344424
11224 10:02:41.350851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11225 10:02:41.351290
11226 10:02:41.351876 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11228 10:02:41.357552 ----------------------------------------------------------------------
11229 10:02:41.360461 Ran 18 tests in 0.008s
11230 10:02:41.360872
11231 10:02:41.361194 OK (skipped=15)
11232 10:02:41.363766 + set +x
11233 10:02:41.364204 <LAVA_TEST_RUNNER EXIT>
11234 10:02:41.364800 ok: lava_test_shell seems to have completed
11235 10:02:41.365671 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11236 10:02:41.366127 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11237 10:02:41.366627 end: 3 lava-test-retry (duration 00:00:01) [common]
11238 10:02:41.367084 start: 4 finalize (timeout 00:08:04) [common]
11239 10:02:41.367604 start: 4.1 power-off (timeout 00:00:30) [common]
11240 10:02:41.368331 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11241 10:02:41.492851 >> Command sent successfully.
11242 10:02:41.504297 Returned 0 in 0 seconds
11243 10:02:41.605575 end: 4.1 power-off (duration 00:00:00) [common]
11245 10:02:41.607090 start: 4.2 read-feedback (timeout 00:08:04) [common]
11246 10:02:41.608310 Listened to connection for namespace 'common' for up to 1s
11247 10:02:42.608952 Finalising connection for namespace 'common'
11248 10:02:42.609674 Disconnecting from shell: Finalise
11249 10:02:42.610148 / #
11250 10:02:42.711167 end: 4.2 read-feedback (duration 00:00:01) [common]
11251 10:02:42.711881 end: 4 finalize (duration 00:00:01) [common]
11252 10:02:42.712533 Cleaning after the job
11253 10:02:42.713129 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/ramdisk
11254 10:02:42.744143 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/kernel
11255 10:02:42.762068 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/dtb
11256 10:02:42.762339 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336431/tftp-deploy-jgneaz_9/modules
11257 10:02:42.772442 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11336431
11258 10:02:42.892000 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11336431
11259 10:02:42.892183 Job finished correctly