Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 24
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 136
- Errors: 0
1 10:00:05.132916 lava-dispatcher, installed at version: 2023.06
2 10:00:05.133169 start: 0 validate
3 10:00:05.133311 Start time: 2023-08-23 10:00:05.133301+00:00 (UTC)
4 10:00:05.133447 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:05.133596 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 10:00:05.403866 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:05.404600 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:00:08.913123 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:00:08.913893 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:00:09.188230 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:00:09.188921 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:00:12.460705 validate duration: 7.33
14 10:00:12.460969 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:00:12.461064 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:00:12.461151 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:00:12.461287 Not decompressing ramdisk as can be used compressed.
18 10:00:12.461370 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 10:00:12.461433 saving as /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/ramdisk/rootfs.cpio.gz
20 10:00:12.461498 total size: 84918747 (80 MB)
21 10:00:12.462554 progress 0 % (0 MB)
22 10:00:12.485247 progress 5 % (4 MB)
23 10:00:12.507189 progress 10 % (8 MB)
24 10:00:12.528689 progress 15 % (12 MB)
25 10:00:12.550134 progress 20 % (16 MB)
26 10:00:12.571407 progress 25 % (20 MB)
27 10:00:12.593214 progress 30 % (24 MB)
28 10:00:12.615106 progress 35 % (28 MB)
29 10:00:12.636572 progress 40 % (32 MB)
30 10:00:12.658161 progress 45 % (36 MB)
31 10:00:12.687121 progress 50 % (40 MB)
32 10:00:12.722016 progress 55 % (44 MB)
33 10:00:12.744792 progress 60 % (48 MB)
34 10:00:12.766732 progress 65 % (52 MB)
35 10:00:12.788406 progress 70 % (56 MB)
36 10:00:12.810161 progress 75 % (60 MB)
37 10:00:12.832470 progress 80 % (64 MB)
38 10:00:12.854075 progress 85 % (68 MB)
39 10:00:12.875703 progress 90 % (72 MB)
40 10:00:12.897264 progress 95 % (76 MB)
41 10:00:12.918837 progress 100 % (80 MB)
42 10:00:12.919062 80 MB downloaded in 0.46 s (176.99 MB/s)
43 10:00:12.919222 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:00:12.919467 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:00:12.919552 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:00:12.919635 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:00:12.919775 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:00:12.919846 saving as /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/kernel/Image
50 10:00:12.919915 total size: 49220096 (46 MB)
51 10:00:12.920014 No compression specified
52 10:00:12.921117 progress 0 % (0 MB)
53 10:00:12.933890 progress 5 % (2 MB)
54 10:00:12.946640 progress 10 % (4 MB)
55 10:00:12.959347 progress 15 % (7 MB)
56 10:00:12.971891 progress 20 % (9 MB)
57 10:00:12.984453 progress 25 % (11 MB)
58 10:00:12.997152 progress 30 % (14 MB)
59 10:00:13.009846 progress 35 % (16 MB)
60 10:00:13.022564 progress 40 % (18 MB)
61 10:00:13.035351 progress 45 % (21 MB)
62 10:00:13.050231 progress 50 % (23 MB)
63 10:00:13.064336 progress 55 % (25 MB)
64 10:00:13.078577 progress 60 % (28 MB)
65 10:00:13.091909 progress 65 % (30 MB)
66 10:00:13.104875 progress 70 % (32 MB)
67 10:00:13.117629 progress 75 % (35 MB)
68 10:00:13.130295 progress 80 % (37 MB)
69 10:00:13.142952 progress 85 % (39 MB)
70 10:00:13.155626 progress 90 % (42 MB)
71 10:00:13.168225 progress 95 % (44 MB)
72 10:00:13.180732 progress 100 % (46 MB)
73 10:00:13.180882 46 MB downloaded in 0.26 s (179.87 MB/s)
74 10:00:13.181035 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:00:13.181330 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:00:13.181415 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:00:13.181507 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:00:13.181652 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:00:13.181723 saving as /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/dtb/mt8192-asurada-spherion-r0.dtb
81 10:00:13.181784 total size: 47278 (0 MB)
82 10:00:13.181844 No compression specified
83 10:00:13.182924 progress 69 % (0 MB)
84 10:00:13.183195 progress 100 % (0 MB)
85 10:00:13.183350 0 MB downloaded in 0.00 s (28.84 MB/s)
86 10:00:13.183471 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:00:13.183689 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:00:13.183774 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:00:13.183856 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:00:13.184049 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:00:13.184117 saving as /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/modules/modules.tar
93 10:00:13.184178 total size: 8617228 (8 MB)
94 10:00:13.184239 Using unxz to decompress xz
95 10:00:13.188070 progress 0 % (0 MB)
96 10:00:13.209452 progress 5 % (0 MB)
97 10:00:13.231602 progress 10 % (0 MB)
98 10:00:13.257289 progress 15 % (1 MB)
99 10:00:13.282464 progress 20 % (1 MB)
100 10:00:13.308146 progress 25 % (2 MB)
101 10:00:13.334386 progress 30 % (2 MB)
102 10:00:13.360923 progress 35 % (2 MB)
103 10:00:13.385393 progress 40 % (3 MB)
104 10:00:13.409708 progress 45 % (3 MB)
105 10:00:13.436155 progress 50 % (4 MB)
106 10:00:13.460939 progress 55 % (4 MB)
107 10:00:13.485096 progress 60 % (4 MB)
108 10:00:13.507583 progress 65 % (5 MB)
109 10:00:13.535266 progress 70 % (5 MB)
110 10:00:13.559279 progress 75 % (6 MB)
111 10:00:13.585046 progress 80 % (6 MB)
112 10:00:13.614702 progress 85 % (7 MB)
113 10:00:13.641288 progress 90 % (7 MB)
114 10:00:13.665075 progress 95 % (7 MB)
115 10:00:13.687650 progress 100 % (8 MB)
116 10:00:13.693995 8 MB downloaded in 0.51 s (16.12 MB/s)
117 10:00:13.694241 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:00:13.694502 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:00:13.694596 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:00:13.694696 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:00:13.694806 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:00:13.694933 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:00:13.695166 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq
125 10:00:13.695307 makedir: /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin
126 10:00:13.695417 makedir: /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/tests
127 10:00:13.695518 makedir: /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/results
128 10:00:13.695634 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-add-keys
129 10:00:13.695783 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-add-sources
130 10:00:13.695963 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-background-process-start
131 10:00:13.696183 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-background-process-stop
132 10:00:13.696323 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-common-functions
133 10:00:13.696452 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-echo-ipv4
134 10:00:13.696580 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-install-packages
135 10:00:13.696706 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-installed-packages
136 10:00:13.696833 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-os-build
137 10:00:13.696959 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-probe-channel
138 10:00:13.697085 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-probe-ip
139 10:00:13.697210 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-target-ip
140 10:00:13.697339 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-target-mac
141 10:00:13.697465 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-target-storage
142 10:00:13.697595 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-test-case
143 10:00:13.697720 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-test-event
144 10:00:13.697845 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-test-feedback
145 10:00:13.697975 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-test-raise
146 10:00:13.698101 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-test-reference
147 10:00:13.698226 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-test-runner
148 10:00:13.698350 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-test-set
149 10:00:13.698478 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-test-shell
150 10:00:13.698607 Updating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-install-packages (oe)
151 10:00:13.698763 Updating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/bin/lava-installed-packages (oe)
152 10:00:13.698888 Creating /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/environment
153 10:00:13.698999 LAVA metadata
154 10:00:13.699074 - LAVA_JOB_ID=11336450
155 10:00:13.699141 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:00:13.699245 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:00:13.699313 skipped lava-vland-overlay
158 10:00:13.699387 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:00:13.699469 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:00:13.699531 skipped lava-multinode-overlay
161 10:00:13.699606 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:00:13.699689 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:00:13.699762 Loading test definitions
164 10:00:13.699849 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 10:00:13.699955 Using /lava-11336450 at stage 0
166 10:00:13.700066 Fetching tests from https://github.com/kernelci/kernelci-core
167 10:00:13.700151 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/0/tests/0_sleep'
168 10:00:14.936574 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/0/tests/0_sleep
169 10:00:14.938824 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 10:00:14.939597 uuid=11336450_1.5.2.3.1 testdef=None
171 10:00:14.939863 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 10:00:14.940473 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 10:00:14.941704 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 10:00:14.942263 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 10:00:14.943821 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 10:00:14.944412 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 10:00:14.945909 runner path: /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/0/tests/0_sleep test_uuid 11336450_1.5.2.3.1
181 10:00:14.946080 sleep_params='mem freeze'
182 10:00:14.946350 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 10:00:14.946880 Creating lava-test-runner.conf files
185 10:00:14.947023 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11336450/lava-overlay-yki5h3kq/lava-11336450/0 for stage 0
186 10:00:14.947212 - 0_sleep
187 10:00:14.947421 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 10:00:14.947603 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 10:00:15.094611 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 10:00:15.094771 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
191 10:00:15.094865 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 10:00:15.094966 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 10:00:15.095056 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
194 10:00:17.515122 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 10:00:17.515522 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 10:00:17.515642 extracting modules file /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11336450/extract-overlay-ramdisk-4mza9oos/ramdisk
197 10:00:17.742881 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 10:00:17.743054 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 10:00:17.743147 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11336450/compress-overlay-rxqoei29/overlay-1.5.2.4.tar.gz to ramdisk
200 10:00:17.743224 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11336450/compress-overlay-rxqoei29/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11336450/extract-overlay-ramdisk-4mza9oos/ramdisk
201 10:00:17.837071 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 10:00:17.837238 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 10:00:17.837340 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 10:00:17.837434 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 10:00:17.837522 Building ramdisk /var/lib/lava/dispatcher/tmp/11336450/extract-overlay-ramdisk-4mza9oos/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11336450/extract-overlay-ramdisk-4mza9oos/ramdisk
206 10:00:19.357176 >> 563301 blocks
207 10:00:28.831202 rename /var/lib/lava/dispatcher/tmp/11336450/extract-overlay-ramdisk-4mza9oos/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/ramdisk/ramdisk.cpio.gz
208 10:00:28.831654 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 10:00:28.831775 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 10:00:28.831876 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 10:00:28.832041 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/kernel/Image'
212 10:00:40.934259 Returned 0 in 12 seconds
213 10:00:41.035178 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/kernel/image.itb
214 10:00:42.397985 output: FIT description: Kernel Image image with one or more FDT blobs
215 10:00:42.398356 output: Created: Wed Aug 23 11:00:42 2023
216 10:00:42.398436 output: Image 0 (kernel-1)
217 10:00:42.398501 output: Description:
218 10:00:42.398564 output: Created: Wed Aug 23 11:00:42 2023
219 10:00:42.398644 output: Type: Kernel Image
220 10:00:42.398710 output: Compression: lzma compressed
221 10:00:42.398770 output: Data Size: 11037260 Bytes = 10778.57 KiB = 10.53 MiB
222 10:00:42.398832 output: Architecture: AArch64
223 10:00:42.398892 output: OS: Linux
224 10:00:42.398968 output: Load Address: 0x00000000
225 10:00:42.399024 output: Entry Point: 0x00000000
226 10:00:42.399079 output: Hash algo: crc32
227 10:00:42.399132 output: Hash value: 17b65cb3
228 10:00:42.399186 output: Image 1 (fdt-1)
229 10:00:42.399239 output: Description: mt8192-asurada-spherion-r0
230 10:00:42.399308 output: Created: Wed Aug 23 11:00:42 2023
231 10:00:42.399365 output: Type: Flat Device Tree
232 10:00:42.399418 output: Compression: uncompressed
233 10:00:42.399472 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 10:00:42.399526 output: Architecture: AArch64
235 10:00:42.399603 output: Hash algo: crc32
236 10:00:42.399687 output: Hash value: cc4352de
237 10:00:42.399769 output: Image 2 (ramdisk-1)
238 10:00:42.399851 output: Description: unavailable
239 10:00:42.399966 output: Created: Wed Aug 23 11:00:42 2023
240 10:00:42.400052 output: Type: RAMDisk Image
241 10:00:42.400119 output: Compression: Unknown Compression
242 10:00:42.400214 output: Data Size: 98294362 Bytes = 95990.59 KiB = 93.74 MiB
243 10:00:42.400274 output: Architecture: AArch64
244 10:00:42.400340 output: OS: Linux
245 10:00:42.400399 output: Load Address: unavailable
246 10:00:42.400453 output: Entry Point: unavailable
247 10:00:42.400507 output: Hash algo: crc32
248 10:00:42.400560 output: Hash value: 3a0bff53
249 10:00:42.400614 output: Default Configuration: 'conf-1'
250 10:00:42.400685 output: Configuration 0 (conf-1)
251 10:00:42.400741 output: Description: mt8192-asurada-spherion-r0
252 10:00:42.400795 output: Kernel: kernel-1
253 10:00:42.400848 output: Init Ramdisk: ramdisk-1
254 10:00:42.400902 output: FDT: fdt-1
255 10:00:42.400963 output: Loadables: kernel-1
256 10:00:42.401022 output:
257 10:00:42.401221 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 10:00:42.401323 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 10:00:42.401430 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 10:00:42.401524 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:30) [common]
261 10:00:42.401605 No LXC device requested
262 10:00:42.401726 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 10:00:42.401847 start: 1.7 deploy-device-env (timeout 00:09:30) [common]
264 10:00:42.401969 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 10:00:42.402067 Checking files for TFTP limit of 4294967296 bytes.
266 10:00:42.402730 end: 1 tftp-deploy (duration 00:00:30) [common]
267 10:00:42.402866 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 10:00:42.402991 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 10:00:42.403119 substitutions:
270 10:00:42.403189 - {DTB}: 11336450/tftp-deploy-8bjmnj5a/dtb/mt8192-asurada-spherion-r0.dtb
271 10:00:42.403255 - {INITRD}: 11336450/tftp-deploy-8bjmnj5a/ramdisk/ramdisk.cpio.gz
272 10:00:42.403318 - {KERNEL}: 11336450/tftp-deploy-8bjmnj5a/kernel/Image
273 10:00:42.403387 - {LAVA_MAC}: None
274 10:00:42.403445 - {PRESEED_CONFIG}: None
275 10:00:42.403501 - {PRESEED_LOCAL}: None
276 10:00:42.403556 - {RAMDISK}: 11336450/tftp-deploy-8bjmnj5a/ramdisk/ramdisk.cpio.gz
277 10:00:42.403612 - {ROOT_PART}: None
278 10:00:42.403667 - {ROOT}: None
279 10:00:42.403735 - {SERVER_IP}: 192.168.201.1
280 10:00:42.403822 - {TEE}: None
281 10:00:42.403913 Parsed boot commands:
282 10:00:42.404011 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 10:00:42.404201 Parsed boot commands: tftpboot 192.168.201.1 11336450/tftp-deploy-8bjmnj5a/kernel/image.itb 11336450/tftp-deploy-8bjmnj5a/kernel/cmdline
284 10:00:42.404300 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 10:00:42.404385 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 10:00:42.404487 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 10:00:42.404576 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 10:00:42.404648 Not connected, no need to disconnect.
289 10:00:42.404724 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 10:00:42.404813 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 10:00:42.404886 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
292 10:00:42.408722 Setting prompt string to ['lava-test: # ']
293 10:00:42.409118 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 10:00:42.409227 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 10:00:42.409334 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 10:00:42.409434 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 10:00:42.409721 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
298 10:00:47.542492 >> Command sent successfully.
299 10:00:47.544981 Returned 0 in 5 seconds
300 10:00:47.645336 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 10:00:47.645659 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 10:00:47.645755 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 10:00:47.645843 Setting prompt string to 'Starting depthcharge on Spherion...'
305 10:00:47.645912 Changing prompt to 'Starting depthcharge on Spherion...'
306 10:00:47.645983 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 10:00:47.646258 [Enter `^Ec?' for help]
308 10:00:47.822122
309 10:00:47.822253
310 10:00:47.822322 F0: 102B 0000
311 10:00:47.822386
312 10:00:47.822447 F3: 1001 0000 [0200]
313 10:00:47.822506
314 10:00:47.825385 F3: 1001 0000
315 10:00:47.825462
316 10:00:47.825526 F7: 102D 0000
317 10:00:47.825585
318 10:00:47.828791 F1: 0000 0000
319 10:00:47.828857
320 10:00:47.828918 V0: 0000 0000 [0001]
321 10:00:47.828977
322 10:00:47.832171 00: 0007 8000
323 10:00:47.832257
324 10:00:47.832323 01: 0000 0000
325 10:00:47.832386
326 10:00:47.835682 BP: 0C00 0209 [0000]
327 10:00:47.835764
328 10:00:47.835830 G0: 1182 0000
329 10:00:47.835892
330 10:00:47.838761 EC: 0000 0021 [4000]
331 10:00:47.838843
332 10:00:47.838908 S7: 0000 0000 [0000]
333 10:00:47.838968
334 10:00:47.842238 CC: 0000 0000 [0001]
335 10:00:47.842321
336 10:00:47.842386 T0: 0000 0040 [010F]
337 10:00:47.842448
338 10:00:47.842506 Jump to BL
339 10:00:47.845428
340 10:00:47.868975
341 10:00:47.869060
342 10:00:47.869127
343 10:00:47.876290 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 10:00:47.879242 ARM64: Exception handlers installed.
345 10:00:47.883427 ARM64: Testing exception
346 10:00:47.886966 ARM64: Done test exception
347 10:00:47.893109 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 10:00:47.903431 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 10:00:47.909917 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 10:00:47.919561 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 10:00:47.926441 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 10:00:47.936447 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 10:00:47.947058 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 10:00:47.953379 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 10:00:47.972161 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 10:00:47.974769 WDT: Last reset was cold boot
357 10:00:47.978193 SPI1(PAD0) initialized at 2873684 Hz
358 10:00:47.981478 SPI5(PAD0) initialized at 992727 Hz
359 10:00:47.985006 VBOOT: Loading verstage.
360 10:00:47.991593 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 10:00:47.994869 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 10:00:47.998121 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 10:00:48.001756 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 10:00:48.009238 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 10:00:48.015822 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 10:00:48.026567 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
367 10:00:48.026655
368 10:00:48.026742
369 10:00:48.036888 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 10:00:48.040242 ARM64: Exception handlers installed.
371 10:00:48.043408 ARM64: Testing exception
372 10:00:48.043494 ARM64: Done test exception
373 10:00:48.050872 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 10:00:48.053787 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 10:00:48.067972 Probing TPM: . done!
376 10:00:48.068060 TPM ready after 0 ms
377 10:00:48.075347 Connected to device vid:did:rid of 1ae0:0028:00
378 10:00:48.081798 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
379 10:00:48.140591 Initialized TPM device CR50 revision 0
380 10:00:48.152318 tlcl_send_startup: Startup return code is 0
381 10:00:48.152409 TPM: setup succeeded
382 10:00:48.163192 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 10:00:48.172070 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 10:00:48.185579 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 10:00:48.193413 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 10:00:48.196523 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 10:00:48.203252 in-header: 03 07 00 00 08 00 00 00
388 10:00:48.206236 in-data: aa e4 47 04 13 02 00 00
389 10:00:48.210036 Chrome EC: UHEPI supported
390 10:00:48.217452 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 10:00:48.221085 in-header: 03 95 00 00 08 00 00 00
392 10:00:48.221174 in-data: 18 20 20 08 00 00 00 00
393 10:00:48.224651 Phase 1
394 10:00:48.228297 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 10:00:48.231980 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 10:00:48.239748 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 10:00:48.243289 Recovery requested (1009000e)
398 10:00:48.250682 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 10:00:48.256300 tlcl_extend: response is 0
400 10:00:48.265856 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 10:00:48.271122 tlcl_extend: response is 0
402 10:00:48.278543 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 10:00:48.298279 read SPI 0x210d4 0x2173b: 15143 us, 9048 KB/s, 72.384 Mbps
404 10:00:48.304609 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 10:00:48.304687
406 10:00:48.304752
407 10:00:48.314500 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 10:00:48.318017 ARM64: Exception handlers installed.
409 10:00:48.321119 ARM64: Testing exception
410 10:00:48.321202 ARM64: Done test exception
411 10:00:48.343582 pmic_efuse_setting: Set efuses in 11 msecs
412 10:00:48.347115 pmwrap_interface_init: Select PMIF_VLD_RDY
413 10:00:48.353742 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 10:00:48.356943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 10:00:48.363963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 10:00:48.367400 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 10:00:48.371174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 10:00:48.378450 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 10:00:48.382609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 10:00:48.385927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 10:00:48.389932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 10:00:48.396790 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 10:00:48.400209 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 10:00:48.404105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 10:00:48.412126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 10:00:48.415556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 10:00:48.422671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 10:00:48.426734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 10:00:48.433934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 10:00:48.438137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 10:00:48.445446 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 10:00:48.449187 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 10:00:48.456144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 10:00:48.460426 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 10:00:48.467033 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 10:00:48.471008 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 10:00:48.478300 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 10:00:48.482422 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 10:00:48.489382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 10:00:48.493352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 10:00:48.496546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 10:00:48.504107 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 10:00:48.508274 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 10:00:48.511517 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 10:00:48.518941 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 10:00:48.522235 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 10:00:48.525794 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 10:00:48.533266 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 10:00:48.536878 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 10:00:48.544416 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 10:00:48.547417 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 10:00:48.551260 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 10:00:48.555027 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 10:00:48.562445 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 10:00:48.565635 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 10:00:48.569188 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 10:00:48.572950 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 10:00:48.576862 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 10:00:48.580251 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 10:00:48.587758 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 10:00:48.591042 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 10:00:48.594483 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 10:00:48.599057 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 10:00:48.606184 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 10:00:48.616733 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 10:00:48.620665 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 10:00:48.627568 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 10:00:48.634909 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 10:00:48.642520 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 10:00:48.646502 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 10:00:48.649698 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 10:00:48.657430 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x1b
473 10:00:48.660616 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 10:00:48.668886 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
475 10:00:48.671844 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 10:00:48.681509 [RTC]rtc_get_frequency_meter,154: input=15, output=853
477 10:00:48.691005 [RTC]rtc_get_frequency_meter,154: input=7, output=725
478 10:00:48.700480 [RTC]rtc_get_frequency_meter,154: input=11, output=789
479 10:00:48.709467 [RTC]rtc_get_frequency_meter,154: input=13, output=821
480 10:00:48.719051 [RTC]rtc_get_frequency_meter,154: input=12, output=805
481 10:00:48.728528 [RTC]rtc_get_frequency_meter,154: input=11, output=789
482 10:00:48.738034 [RTC]rtc_get_frequency_meter,154: input=12, output=806
483 10:00:48.741687 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
484 10:00:48.748684 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
485 10:00:48.752244 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 10:00:48.755862 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 10:00:48.759605 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 10:00:48.763200 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 10:00:48.766827 ADC[4]: Raw value=903694 ID=7
490 10:00:48.769913 ADC[3]: Raw value=213546 ID=1
491 10:00:48.770037 RAM Code: 0x71
492 10:00:48.774360 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 10:00:48.781394 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 10:00:48.789072 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 10:00:48.795667 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 10:00:48.799955 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 10:00:48.803334 in-header: 03 07 00 00 08 00 00 00
498 10:00:48.807347 in-data: aa e4 47 04 13 02 00 00
499 10:00:48.807429 Chrome EC: UHEPI supported
500 10:00:48.814391 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 10:00:48.818042 in-header: 03 95 00 00 08 00 00 00
502 10:00:48.821534 in-data: 18 20 20 08 00 00 00 00
503 10:00:48.825361 MRC: failed to locate region type 0.
504 10:00:48.832843 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 10:00:48.836782 DRAM-K: Running full calibration
506 10:00:48.839910 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 10:00:48.844077 header.status = 0x0
508 10:00:48.847266 header.version = 0x6 (expected: 0x6)
509 10:00:48.851316 header.size = 0xd00 (expected: 0xd00)
510 10:00:48.851398 header.flags = 0x0
511 10:00:48.858399 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 10:00:48.875177 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
513 10:00:48.882499 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 10:00:48.886477 dram_init: ddr_geometry: 2
515 10:00:48.886559 [EMI] MDL number = 2
516 10:00:48.889843 [EMI] Get MDL freq = 0
517 10:00:48.889926 dram_init: ddr_type: 0
518 10:00:48.893766 is_discrete_lpddr4: 1
519 10:00:48.897293 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 10:00:48.897375
521 10:00:48.897439
522 10:00:48.897500 [Bian_co] ETT version 0.0.0.1
523 10:00:48.904926 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 10:00:48.905008
525 10:00:48.908942 dramc_set_vcore_voltage set vcore to 650000
526 10:00:48.909023 Read voltage for 800, 4
527 10:00:48.912270 Vio18 = 0
528 10:00:48.912352 Vcore = 650000
529 10:00:48.912417 Vdram = 0
530 10:00:48.915726 Vddq = 0
531 10:00:48.915834 Vmddr = 0
532 10:00:48.918611 dram_init: config_dvfs: 1
533 10:00:48.921933 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 10:00:48.928854 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 10:00:48.932599 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
536 10:00:48.936454 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
537 10:00:48.940592 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
538 10:00:48.943425 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
539 10:00:48.943507 MEM_TYPE=3, freq_sel=18
540 10:00:48.947315 sv_algorithm_assistance_LP4_1600
541 10:00:48.950486 ============ PULL DRAM RESETB DOWN ============
542 10:00:48.957366 ========== PULL DRAM RESETB DOWN end =========
543 10:00:48.960789 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 10:00:48.964147 ===================================
545 10:00:48.967457 LPDDR4 DRAM CONFIGURATION
546 10:00:48.970484 ===================================
547 10:00:48.970567 EX_ROW_EN[0] = 0x0
548 10:00:48.974036 EX_ROW_EN[1] = 0x0
549 10:00:48.974124 LP4Y_EN = 0x0
550 10:00:48.977436 WORK_FSP = 0x0
551 10:00:48.980571 WL = 0x2
552 10:00:48.980653 RL = 0x2
553 10:00:48.983822 BL = 0x2
554 10:00:48.983967 RPST = 0x0
555 10:00:48.987454 RD_PRE = 0x0
556 10:00:48.987536 WR_PRE = 0x1
557 10:00:48.990410 WR_PST = 0x0
558 10:00:48.990493 DBI_WR = 0x0
559 10:00:48.993985 DBI_RD = 0x0
560 10:00:48.994067 OTF = 0x1
561 10:00:48.997274 ===================================
562 10:00:49.000276 ===================================
563 10:00:49.003725 ANA top config
564 10:00:49.007344 ===================================
565 10:00:49.007426 DLL_ASYNC_EN = 0
566 10:00:49.010670 ALL_SLAVE_EN = 1
567 10:00:49.014000 NEW_RANK_MODE = 1
568 10:00:49.017479 DLL_IDLE_MODE = 1
569 10:00:49.017561 LP45_APHY_COMB_EN = 1
570 10:00:49.020533 TX_ODT_DIS = 1
571 10:00:49.023798 NEW_8X_MODE = 1
572 10:00:49.027300 ===================================
573 10:00:49.030287 ===================================
574 10:00:49.033561 data_rate = 1600
575 10:00:49.036981 CKR = 1
576 10:00:49.040428 DQ_P2S_RATIO = 8
577 10:00:49.043673 ===================================
578 10:00:49.043755 CA_P2S_RATIO = 8
579 10:00:49.047603 DQ_CA_OPEN = 0
580 10:00:49.051180 DQ_SEMI_OPEN = 0
581 10:00:49.053976 CA_SEMI_OPEN = 0
582 10:00:49.057424 CA_FULL_RATE = 0
583 10:00:49.057506 DQ_CKDIV4_EN = 1
584 10:00:49.060952 CA_CKDIV4_EN = 1
585 10:00:49.064371 CA_PREDIV_EN = 0
586 10:00:49.067762 PH8_DLY = 0
587 10:00:49.070914 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 10:00:49.073879 DQ_AAMCK_DIV = 4
589 10:00:49.073962 CA_AAMCK_DIV = 4
590 10:00:49.077965 CA_ADMCK_DIV = 4
591 10:00:49.080516 DQ_TRACK_CA_EN = 0
592 10:00:49.084271 CA_PICK = 800
593 10:00:49.087436 CA_MCKIO = 800
594 10:00:49.090836 MCKIO_SEMI = 0
595 10:00:49.090918 PLL_FREQ = 3068
596 10:00:49.094685 DQ_UI_PI_RATIO = 32
597 10:00:49.098183 CA_UI_PI_RATIO = 0
598 10:00:49.101713 ===================================
599 10:00:49.105663 ===================================
600 10:00:49.105745 memory_type:LPDDR4
601 10:00:49.109597 GP_NUM : 10
602 10:00:49.113061 SRAM_EN : 1
603 10:00:49.113143 MD32_EN : 0
604 10:00:49.116822 ===================================
605 10:00:49.120177 [ANA_INIT] >>>>>>>>>>>>>>
606 10:00:49.120259 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 10:00:49.123865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 10:00:49.127320 ===================================
609 10:00:49.130687 data_rate = 1600,PCW = 0X7600
610 10:00:49.134109 ===================================
611 10:00:49.137362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 10:00:49.144023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 10:00:49.147461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 10:00:49.154280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 10:00:49.157673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 10:00:49.161056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 10:00:49.164359 [ANA_INIT] flow start
618 10:00:49.164441 [ANA_INIT] PLL >>>>>>>>
619 10:00:49.167073 [ANA_INIT] PLL <<<<<<<<
620 10:00:49.170620 [ANA_INIT] MIDPI >>>>>>>>
621 10:00:49.170701 [ANA_INIT] MIDPI <<<<<<<<
622 10:00:49.174051 [ANA_INIT] DLL >>>>>>>>
623 10:00:49.177136 [ANA_INIT] flow end
624 10:00:49.180089 ============ LP4 DIFF to SE enter ============
625 10:00:49.183625 ============ LP4 DIFF to SE exit ============
626 10:00:49.186761 [ANA_INIT] <<<<<<<<<<<<<
627 10:00:49.190628 [Flow] Enable top DCM control >>>>>
628 10:00:49.193412 [Flow] Enable top DCM control <<<<<
629 10:00:49.196995 Enable DLL master slave shuffle
630 10:00:49.199993 ==============================================================
631 10:00:49.203621 Gating Mode config
632 10:00:49.210405 ==============================================================
633 10:00:49.210488 Config description:
634 10:00:49.220215 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 10:00:49.226639 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 10:00:49.229858 SELPH_MODE 0: By rank 1: By Phase
637 10:00:49.236616 ==============================================================
638 10:00:49.239985 GAT_TRACK_EN = 1
639 10:00:49.243598 RX_GATING_MODE = 2
640 10:00:49.246960 RX_GATING_TRACK_MODE = 2
641 10:00:49.249727 SELPH_MODE = 1
642 10:00:49.253522 PICG_EARLY_EN = 1
643 10:00:49.256842 VALID_LAT_VALUE = 1
644 10:00:49.260005 ==============================================================
645 10:00:49.262995 Enter into Gating configuration >>>>
646 10:00:49.266702 Exit from Gating configuration <<<<
647 10:00:49.270043 Enter into DVFS_PRE_config >>>>>
648 10:00:49.283028 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 10:00:49.283118 Exit from DVFS_PRE_config <<<<<
650 10:00:49.286760 Enter into PICG configuration >>>>
651 10:00:49.289898 Exit from PICG configuration <<<<
652 10:00:49.293480 [RX_INPUT] configuration >>>>>
653 10:00:49.297046 [RX_INPUT] configuration <<<<<
654 10:00:49.303391 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 10:00:49.306373 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 10:00:49.313158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 10:00:49.319798 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 10:00:49.326373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 10:00:49.332908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 10:00:49.336514 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 10:00:49.339789 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 10:00:49.342745 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 10:00:49.349575 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 10:00:49.352734 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 10:00:49.356177 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 10:00:49.359746 ===================================
667 10:00:49.362807 LPDDR4 DRAM CONFIGURATION
668 10:00:49.365902 ===================================
669 10:00:49.365985 EX_ROW_EN[0] = 0x0
670 10:00:49.369656 EX_ROW_EN[1] = 0x0
671 10:00:49.372799 LP4Y_EN = 0x0
672 10:00:49.372881 WORK_FSP = 0x0
673 10:00:49.376173 WL = 0x2
674 10:00:49.376254 RL = 0x2
675 10:00:49.379749 BL = 0x2
676 10:00:49.379831 RPST = 0x0
677 10:00:49.382912 RD_PRE = 0x0
678 10:00:49.382994 WR_PRE = 0x1
679 10:00:49.385717 WR_PST = 0x0
680 10:00:49.385798 DBI_WR = 0x0
681 10:00:49.389580 DBI_RD = 0x0
682 10:00:49.389662 OTF = 0x1
683 10:00:49.392934 ===================================
684 10:00:49.396178 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 10:00:49.402897 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 10:00:49.405807 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 10:00:49.409331 ===================================
688 10:00:49.412672 LPDDR4 DRAM CONFIGURATION
689 10:00:49.415758 ===================================
690 10:00:49.415840 EX_ROW_EN[0] = 0x10
691 10:00:49.419232 EX_ROW_EN[1] = 0x0
692 10:00:49.422396 LP4Y_EN = 0x0
693 10:00:49.422477 WORK_FSP = 0x0
694 10:00:49.425878 WL = 0x2
695 10:00:49.425959 RL = 0x2
696 10:00:49.429345 BL = 0x2
697 10:00:49.429427 RPST = 0x0
698 10:00:49.432777 RD_PRE = 0x0
699 10:00:49.432859 WR_PRE = 0x1
700 10:00:49.435869 WR_PST = 0x0
701 10:00:49.435986 DBI_WR = 0x0
702 10:00:49.439345 DBI_RD = 0x0
703 10:00:49.439426 OTF = 0x1
704 10:00:49.442763 ===================================
705 10:00:49.449149 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 10:00:49.453140 nWR fixed to 40
707 10:00:49.456513 [ModeRegInit_LP4] CH0 RK0
708 10:00:49.456595 [ModeRegInit_LP4] CH0 RK1
709 10:00:49.460042 [ModeRegInit_LP4] CH1 RK0
710 10:00:49.463362 [ModeRegInit_LP4] CH1 RK1
711 10:00:49.463443 match AC timing 13
712 10:00:49.470060 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 10:00:49.473233 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 10:00:49.476852 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 10:00:49.483297 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 10:00:49.486726 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 10:00:49.486802 [EMI DOE] emi_dcm 0
718 10:00:49.493399 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 10:00:49.493483 ==
720 10:00:49.496836 Dram Type= 6, Freq= 0, CH_0, rank 0
721 10:00:49.499844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 10:00:49.499968 ==
723 10:00:49.506535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 10:00:49.512874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 10:00:49.520536 [CA 0] Center 37 (7~68) winsize 62
726 10:00:49.524019 [CA 1] Center 37 (7~68) winsize 62
727 10:00:49.527711 [CA 2] Center 34 (4~65) winsize 62
728 10:00:49.530877 [CA 3] Center 34 (4~65) winsize 62
729 10:00:49.533789 [CA 4] Center 33 (3~64) winsize 62
730 10:00:49.537100 [CA 5] Center 33 (3~64) winsize 62
731 10:00:49.537208
732 10:00:49.540493 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 10:00:49.540575
734 10:00:49.544078 [CATrainingPosCal] consider 1 rank data
735 10:00:49.547485 u2DelayCellTimex100 = 270/100 ps
736 10:00:49.550597 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 10:00:49.554105 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
738 10:00:49.560731 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 10:00:49.563579 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 10:00:49.567093 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 10:00:49.570481 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 10:00:49.570563
743 10:00:49.573719 CA PerBit enable=1, Macro0, CA PI delay=33
744 10:00:49.573801
745 10:00:49.577500 [CBTSetCACLKResult] CA Dly = 33
746 10:00:49.577582 CS Dly: 6 (0~37)
747 10:00:49.580664 ==
748 10:00:49.580748 Dram Type= 6, Freq= 0, CH_0, rank 1
749 10:00:49.587361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 10:00:49.587446 ==
751 10:00:49.590382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 10:00:49.597352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 10:00:49.606851 [CA 0] Center 38 (7~69) winsize 63
754 10:00:49.610466 [CA 1] Center 37 (7~68) winsize 62
755 10:00:49.613727 [CA 2] Center 35 (5~66) winsize 62
756 10:00:49.617067 [CA 3] Center 35 (4~66) winsize 63
757 10:00:49.620351 [CA 4] Center 34 (3~65) winsize 63
758 10:00:49.623634 [CA 5] Center 33 (3~64) winsize 62
759 10:00:49.623716
760 10:00:49.626835 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 10:00:49.626917
762 10:00:49.630348 [CATrainingPosCal] consider 2 rank data
763 10:00:49.633772 u2DelayCellTimex100 = 270/100 ps
764 10:00:49.636645 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 10:00:49.643849 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 10:00:49.646735 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
767 10:00:49.650296 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 10:00:49.653357 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 10:00:49.656846 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 10:00:49.656928
771 10:00:49.660161 CA PerBit enable=1, Macro0, CA PI delay=33
772 10:00:49.660243
773 10:00:49.663586 [CBTSetCACLKResult] CA Dly = 33
774 10:00:49.663667 CS Dly: 6 (0~38)
775 10:00:49.666914
776 10:00:49.669796 ----->DramcWriteLeveling(PI) begin...
777 10:00:49.669882 ==
778 10:00:49.673625 Dram Type= 6, Freq= 0, CH_0, rank 0
779 10:00:49.677594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 10:00:49.677677 ==
781 10:00:49.680614 Write leveling (Byte 0): 31 => 31
782 10:00:49.680696 Write leveling (Byte 1): 26 => 26
783 10:00:49.684932 DramcWriteLeveling(PI) end<-----
784 10:00:49.685013
785 10:00:49.685078 ==
786 10:00:49.687844 Dram Type= 6, Freq= 0, CH_0, rank 0
787 10:00:49.694682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 10:00:49.694764 ==
789 10:00:49.694829 [Gating] SW mode calibration
790 10:00:49.702098 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 10:00:49.708527 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 10:00:49.712282 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 10:00:49.718366 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 10:00:49.721715 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 10:00:49.724978 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:00:49.731633 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:00:49.734976 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:00:49.738141 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:00:49.744737 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:00:49.747966 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:00:49.751558 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:00:49.758240 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:00:49.761193 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 10:00:49.764824 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 10:00:49.771808 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:00:49.774473 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:00:49.778088 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:00:49.784508 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
809 10:00:49.787857 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 10:00:49.791227 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:00:49.795019 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
812 10:00:49.801097 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 10:00:49.804660 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 10:00:49.807769 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 10:00:49.814847 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 10:00:49.817780 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 10:00:49.820988 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
818 10:00:49.827816 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
819 10:00:49.831173 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
820 10:00:49.834451 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 10:00:49.841097 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 10:00:49.844327 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 10:00:49.847552 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 10:00:49.854275 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 10:00:49.857678 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
826 10:00:49.861087 0 10 8 | B1->B0 | 3131 2929 | 0 0 | (1 0) (1 1)
827 10:00:49.867926 0 10 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
828 10:00:49.871066 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 10:00:49.874443 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 10:00:49.880758 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 10:00:49.884256 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 10:00:49.887855 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 10:00:49.894537 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
834 10:00:49.897663 0 11 8 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
835 10:00:49.901665 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
836 10:00:49.907735 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 10:00:49.911240 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 10:00:49.914454 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 10:00:49.921099 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 10:00:49.924396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 10:00:49.927430 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
842 10:00:49.933990 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
843 10:00:49.937242 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:00:49.940716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:00:49.947099 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:00:49.950735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:00:49.954474 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:00:49.957297 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:00:49.963642 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:00:49.967395 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 10:00:49.970612 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 10:00:49.977502 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 10:00:49.980727 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 10:00:49.983769 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 10:00:49.990184 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 10:00:49.994030 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 10:00:49.997190 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 10:00:50.003859 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 10:00:50.003980 Total UI for P1: 0, mck2ui 16
860 10:00:50.010514 best dqsien dly found for B0: ( 0, 14, 4)
861 10:00:50.014274 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
862 10:00:50.017271 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 10:00:50.020505 Total UI for P1: 0, mck2ui 16
864 10:00:50.023940 best dqsien dly found for B1: ( 0, 14, 10)
865 10:00:50.026808 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
866 10:00:50.030635 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
867 10:00:50.030717
868 10:00:50.037163 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
869 10:00:50.040101 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
870 10:00:50.040183 [Gating] SW calibration Done
871 10:00:50.043709 ==
872 10:00:50.047123 Dram Type= 6, Freq= 0, CH_0, rank 0
873 10:00:50.051078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
874 10:00:50.051160 ==
875 10:00:50.051225 RX Vref Scan: 0
876 10:00:50.051286
877 10:00:50.054600 RX Vref 0 -> 0, step: 1
878 10:00:50.054682
879 10:00:50.057818 RX Delay -130 -> 252, step: 16
880 10:00:50.061569 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
881 10:00:50.064481 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
882 10:00:50.067726 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
883 10:00:50.071373 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
884 10:00:50.078447 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
885 10:00:50.081369 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
886 10:00:50.084790 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
887 10:00:50.087844 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
888 10:00:50.090988 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
889 10:00:50.097671 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
890 10:00:50.101370 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
891 10:00:50.104243 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
892 10:00:50.107714 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
893 10:00:50.111049 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
894 10:00:50.117534 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
895 10:00:50.121319 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
896 10:00:50.121400 ==
897 10:00:50.124603 Dram Type= 6, Freq= 0, CH_0, rank 0
898 10:00:50.127762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 10:00:50.127845 ==
900 10:00:50.131337 DQS Delay:
901 10:00:50.131420 DQS0 = 0, DQS1 = 0
902 10:00:50.131486 DQM Delay:
903 10:00:50.134422 DQM0 = 88, DQM1 = 75
904 10:00:50.134504 DQ Delay:
905 10:00:50.137652 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
906 10:00:50.141187 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
907 10:00:50.144401 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
908 10:00:50.147824 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
909 10:00:50.147912
910 10:00:50.147978
911 10:00:50.148038 ==
912 10:00:50.151190 Dram Type= 6, Freq= 0, CH_0, rank 0
913 10:00:50.157590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 10:00:50.157675 ==
915 10:00:50.157739
916 10:00:50.157799
917 10:00:50.160559 TX Vref Scan disable
918 10:00:50.160641 == TX Byte 0 ==
919 10:00:50.163733 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
920 10:00:50.170395 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
921 10:00:50.170478 == TX Byte 1 ==
922 10:00:50.173913 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
923 10:00:50.180632 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
924 10:00:50.180725 ==
925 10:00:50.184284 Dram Type= 6, Freq= 0, CH_0, rank 0
926 10:00:50.187025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 10:00:50.187107 ==
928 10:00:50.200845 TX Vref=22, minBit 1, minWin=26, winSum=435
929 10:00:50.204333 TX Vref=24, minBit 1, minWin=27, winSum=441
930 10:00:50.207400 TX Vref=26, minBit 2, minWin=27, winSum=447
931 10:00:50.211020 TX Vref=28, minBit 3, minWin=27, winSum=449
932 10:00:50.214052 TX Vref=30, minBit 0, minWin=28, winSum=451
933 10:00:50.217836 TX Vref=32, minBit 2, minWin=27, winSum=449
934 10:00:50.223755 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
935 10:00:50.223864
936 10:00:50.227485 Final TX Range 1 Vref 30
937 10:00:50.227567
938 10:00:50.227631 ==
939 10:00:50.230727 Dram Type= 6, Freq= 0, CH_0, rank 0
940 10:00:50.234246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 10:00:50.234325 ==
942 10:00:50.237207
943 10:00:50.237289
944 10:00:50.237354 TX Vref Scan disable
945 10:00:50.240689 == TX Byte 0 ==
946 10:00:50.243934 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
947 10:00:50.250848 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
948 10:00:50.250930 == TX Byte 1 ==
949 10:00:50.254415 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
950 10:00:50.260714 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
951 10:00:50.260797
952 10:00:50.260862 [DATLAT]
953 10:00:50.260923 Freq=800, CH0 RK0
954 10:00:50.260984
955 10:00:50.264155 DATLAT Default: 0xa
956 10:00:50.264236 0, 0xFFFF, sum = 0
957 10:00:50.267291 1, 0xFFFF, sum = 0
958 10:00:50.267375 2, 0xFFFF, sum = 0
959 10:00:50.270578 3, 0xFFFF, sum = 0
960 10:00:50.273695 4, 0xFFFF, sum = 0
961 10:00:50.273779 5, 0xFFFF, sum = 0
962 10:00:50.277251 6, 0xFFFF, sum = 0
963 10:00:50.277334 7, 0xFFFF, sum = 0
964 10:00:50.280596 8, 0xFFFF, sum = 0
965 10:00:50.280680 9, 0x0, sum = 1
966 10:00:50.280746 10, 0x0, sum = 2
967 10:00:50.283991 11, 0x0, sum = 3
968 10:00:50.284075 12, 0x0, sum = 4
969 10:00:50.287699 best_step = 10
970 10:00:50.287780
971 10:00:50.287845 ==
972 10:00:50.290725 Dram Type= 6, Freq= 0, CH_0, rank 0
973 10:00:50.294012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 10:00:50.294097 ==
975 10:00:50.297500 RX Vref Scan: 1
976 10:00:50.297582
977 10:00:50.300293 Set Vref Range= 32 -> 127
978 10:00:50.300375
979 10:00:50.300440 RX Vref 32 -> 127, step: 1
980 10:00:50.300500
981 10:00:50.304008 RX Delay -111 -> 252, step: 8
982 10:00:50.304090
983 10:00:50.307136 Set Vref, RX VrefLevel [Byte0]: 32
984 10:00:50.310814 [Byte1]: 32
985 10:00:50.313449
986 10:00:50.313531 Set Vref, RX VrefLevel [Byte0]: 33
987 10:00:50.317161 [Byte1]: 33
988 10:00:50.321670
989 10:00:50.321752 Set Vref, RX VrefLevel [Byte0]: 34
990 10:00:50.324354 [Byte1]: 34
991 10:00:50.328882
992 10:00:50.328963 Set Vref, RX VrefLevel [Byte0]: 35
993 10:00:50.332601 [Byte1]: 35
994 10:00:50.336917
995 10:00:50.336999 Set Vref, RX VrefLevel [Byte0]: 36
996 10:00:50.340249 [Byte1]: 36
997 10:00:50.344600
998 10:00:50.344690 Set Vref, RX VrefLevel [Byte0]: 37
999 10:00:50.347813 [Byte1]: 37
1000 10:00:50.352310
1001 10:00:50.352397 Set Vref, RX VrefLevel [Byte0]: 38
1002 10:00:50.355621 [Byte1]: 38
1003 10:00:50.359732
1004 10:00:50.359813 Set Vref, RX VrefLevel [Byte0]: 39
1005 10:00:50.363514 [Byte1]: 39
1006 10:00:50.367272
1007 10:00:50.367353 Set Vref, RX VrefLevel [Byte0]: 40
1008 10:00:50.370694 [Byte1]: 40
1009 10:00:50.375241
1010 10:00:50.375322 Set Vref, RX VrefLevel [Byte0]: 41
1011 10:00:50.378225 [Byte1]: 41
1012 10:00:50.382597
1013 10:00:50.382678 Set Vref, RX VrefLevel [Byte0]: 42
1014 10:00:50.385591 [Byte1]: 42
1015 10:00:50.390393
1016 10:00:50.390474 Set Vref, RX VrefLevel [Byte0]: 43
1017 10:00:50.393113 [Byte1]: 43
1018 10:00:50.397711
1019 10:00:50.397792 Set Vref, RX VrefLevel [Byte0]: 44
1020 10:00:50.401018 [Byte1]: 44
1021 10:00:50.405401
1022 10:00:50.405481 Set Vref, RX VrefLevel [Byte0]: 45
1023 10:00:50.408829 [Byte1]: 45
1024 10:00:50.413026
1025 10:00:50.413114 Set Vref, RX VrefLevel [Byte0]: 46
1026 10:00:50.416406 [Byte1]: 46
1027 10:00:50.421074
1028 10:00:50.421154 Set Vref, RX VrefLevel [Byte0]: 47
1029 10:00:50.423682 [Byte1]: 47
1030 10:00:50.428328
1031 10:00:50.428408 Set Vref, RX VrefLevel [Byte0]: 48
1032 10:00:50.431912 [Byte1]: 48
1033 10:00:50.436180
1034 10:00:50.436261 Set Vref, RX VrefLevel [Byte0]: 49
1035 10:00:50.439276 [Byte1]: 49
1036 10:00:50.443787
1037 10:00:50.443887 Set Vref, RX VrefLevel [Byte0]: 50
1038 10:00:50.446967 [Byte1]: 50
1039 10:00:50.451287
1040 10:00:50.451367 Set Vref, RX VrefLevel [Byte0]: 51
1041 10:00:50.454564 [Byte1]: 51
1042 10:00:50.458778
1043 10:00:50.458858 Set Vref, RX VrefLevel [Byte0]: 52
1044 10:00:50.462199 [Byte1]: 52
1045 10:00:50.466839
1046 10:00:50.466920 Set Vref, RX VrefLevel [Byte0]: 53
1047 10:00:50.469964 [Byte1]: 53
1048 10:00:50.473930
1049 10:00:50.474010 Set Vref, RX VrefLevel [Byte0]: 54
1050 10:00:50.477411 [Byte1]: 54
1051 10:00:50.482142
1052 10:00:50.482223 Set Vref, RX VrefLevel [Byte0]: 55
1053 10:00:50.485292 [Byte1]: 55
1054 10:00:50.489185
1055 10:00:50.489265 Set Vref, RX VrefLevel [Byte0]: 56
1056 10:00:50.495707 [Byte1]: 56
1057 10:00:50.495789
1058 10:00:50.499435 Set Vref, RX VrefLevel [Byte0]: 57
1059 10:00:50.502339 [Byte1]: 57
1060 10:00:50.502420
1061 10:00:50.505688 Set Vref, RX VrefLevel [Byte0]: 58
1062 10:00:50.509229 [Byte1]: 58
1063 10:00:50.512227
1064 10:00:50.512308 Set Vref, RX VrefLevel [Byte0]: 59
1065 10:00:50.515402 [Byte1]: 59
1066 10:00:50.519855
1067 10:00:50.519956 Set Vref, RX VrefLevel [Byte0]: 60
1068 10:00:50.523305 [Byte1]: 60
1069 10:00:50.527620
1070 10:00:50.527700 Set Vref, RX VrefLevel [Byte0]: 61
1071 10:00:50.530853 [Byte1]: 61
1072 10:00:50.535540
1073 10:00:50.535620 Set Vref, RX VrefLevel [Byte0]: 62
1074 10:00:50.538587 [Byte1]: 62
1075 10:00:50.542771
1076 10:00:50.542851 Set Vref, RX VrefLevel [Byte0]: 63
1077 10:00:50.546442 [Byte1]: 63
1078 10:00:50.550810
1079 10:00:50.550891 Set Vref, RX VrefLevel [Byte0]: 64
1080 10:00:50.554295 [Byte1]: 64
1081 10:00:50.558150
1082 10:00:50.558231 Set Vref, RX VrefLevel [Byte0]: 65
1083 10:00:50.561358 [Byte1]: 65
1084 10:00:50.565625
1085 10:00:50.565705 Set Vref, RX VrefLevel [Byte0]: 66
1086 10:00:50.569096 [Byte1]: 66
1087 10:00:50.573629
1088 10:00:50.573709 Set Vref, RX VrefLevel [Byte0]: 67
1089 10:00:50.577119 [Byte1]: 67
1090 10:00:50.581415
1091 10:00:50.581495 Set Vref, RX VrefLevel [Byte0]: 68
1092 10:00:50.584264 [Byte1]: 68
1093 10:00:50.588894
1094 10:00:50.588974 Set Vref, RX VrefLevel [Byte0]: 69
1095 10:00:50.592299 [Byte1]: 69
1096 10:00:50.596209
1097 10:00:50.596289 Set Vref, RX VrefLevel [Byte0]: 70
1098 10:00:50.599706 [Byte1]: 70
1099 10:00:50.604016
1100 10:00:50.604096 Set Vref, RX VrefLevel [Byte0]: 71
1101 10:00:50.607467 [Byte1]: 71
1102 10:00:50.611947
1103 10:00:50.612028 Set Vref, RX VrefLevel [Byte0]: 72
1104 10:00:50.615085 [Byte1]: 72
1105 10:00:50.619140
1106 10:00:50.619220 Set Vref, RX VrefLevel [Byte0]: 73
1107 10:00:50.622467 [Byte1]: 73
1108 10:00:50.626789
1109 10:00:50.626869 Final RX Vref Byte 0 = 58 to rank0
1110 10:00:50.630530 Final RX Vref Byte 1 = 58 to rank0
1111 10:00:50.633719 Final RX Vref Byte 0 = 58 to rank1
1112 10:00:50.636648 Final RX Vref Byte 1 = 58 to rank1==
1113 10:00:50.640496 Dram Type= 6, Freq= 0, CH_0, rank 0
1114 10:00:50.646738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1115 10:00:50.646822 ==
1116 10:00:50.646887 DQS Delay:
1117 10:00:50.646948 DQS0 = 0, DQS1 = 0
1118 10:00:50.650394 DQM Delay:
1119 10:00:50.650475 DQM0 = 88, DQM1 = 75
1120 10:00:50.653740 DQ Delay:
1121 10:00:50.656721 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1122 10:00:50.660335 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1123 10:00:50.663520 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1124 10:00:50.666944 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1125 10:00:50.667025
1126 10:00:50.667089
1127 10:00:50.673555 [DQSOSCAuto] RK0, (LSB)MR18= 0x322c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1128 10:00:50.676444 CH0 RK0: MR19=606, MR18=322C
1129 10:00:50.683589 CH0_RK0: MR19=0x606, MR18=0x322C, DQSOSC=397, MR23=63, INC=93, DEC=62
1130 10:00:50.683670
1131 10:00:50.686710 ----->DramcWriteLeveling(PI) begin...
1132 10:00:50.686792 ==
1133 10:00:50.690019 Dram Type= 6, Freq= 0, CH_0, rank 1
1134 10:00:50.693258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1135 10:00:50.693340 ==
1136 10:00:50.696789 Write leveling (Byte 0): 32 => 32
1137 10:00:50.700211 Write leveling (Byte 1): 27 => 27
1138 10:00:50.703838 DramcWriteLeveling(PI) end<-----
1139 10:00:50.703947
1140 10:00:50.704013 ==
1141 10:00:50.707109 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 10:00:50.710444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 10:00:50.710526 ==
1144 10:00:50.713145 [Gating] SW mode calibration
1145 10:00:50.719890 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1146 10:00:50.726689 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1147 10:00:50.729877 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1148 10:00:50.733298 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 10:00:50.780892 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1150 10:00:50.780987 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 10:00:50.781384 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 10:00:50.781766 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 10:00:50.782059 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 10:00:50.782307 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 10:00:50.782394 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 10:00:50.782471 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:00:50.782710 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:00:50.782953 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:00:50.824742 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:00:50.824824 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:00:50.825069 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:00:50.825162 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:00:50.825248 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:00:50.825487 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1165 10:00:50.825549 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1166 10:00:50.825784 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 10:00:50.825844 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 10:00:50.825947 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:00:50.858384 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:00:50.858466 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:00:50.858710 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:00:50.859399 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1173 10:00:50.859737 0 9 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
1174 10:00:50.859808 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1175 10:00:50.859870 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 10:00:50.860121 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 10:00:50.863029 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 10:00:50.866636 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 10:00:50.869863 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 10:00:50.876664 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
1181 10:00:50.879998 0 10 8 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
1182 10:00:50.883224 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1183 10:00:50.889460 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 10:00:50.893235 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 10:00:50.896596 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 10:00:50.903024 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:00:50.906399 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:00:50.909472 0 11 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
1189 10:00:50.916080 0 11 8 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
1190 10:00:50.919570 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 10:00:50.923477 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 10:00:50.927533 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 10:00:50.930780 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 10:00:50.938174 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 10:00:50.941096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 10:00:50.944851 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1197 10:00:50.948568 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 10:00:50.955239 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1199 10:00:50.958858 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 10:00:50.961660 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 10:00:50.968750 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 10:00:50.972059 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 10:00:50.975014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 10:00:50.981710 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:00:50.984897 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:00:50.988701 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:00:50.995021 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:00:50.999043 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:00:51.002070 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:00:51.008907 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:00:51.011748 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:00:51.014909 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1213 10:00:51.021709 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1214 10:00:51.021795 Total UI for P1: 0, mck2ui 16
1215 10:00:51.028408 best dqsien dly found for B0: ( 0, 14, 4)
1216 10:00:51.031761 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 10:00:51.035093 Total UI for P1: 0, mck2ui 16
1218 10:00:51.038356 best dqsien dly found for B1: ( 0, 14, 8)
1219 10:00:51.041679 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1220 10:00:51.045369 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1221 10:00:51.045451
1222 10:00:51.048358 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1223 10:00:51.051597 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1224 10:00:51.054828 [Gating] SW calibration Done
1225 10:00:51.054910 ==
1226 10:00:51.058393 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 10:00:51.061600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1228 10:00:51.061682 ==
1229 10:00:51.064847 RX Vref Scan: 0
1230 10:00:51.064928
1231 10:00:51.068403 RX Vref 0 -> 0, step: 1
1232 10:00:51.068484
1233 10:00:51.068549 RX Delay -130 -> 252, step: 16
1234 10:00:51.074565 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1235 10:00:51.078331 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1236 10:00:51.081300 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1237 10:00:51.084824 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1238 10:00:51.088137 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1239 10:00:51.094538 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1240 10:00:51.098201 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1241 10:00:51.101253 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1242 10:00:51.104953 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1243 10:00:51.108007 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1244 10:00:51.114392 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1245 10:00:51.117778 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1246 10:00:51.121234 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1247 10:00:51.124294 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1248 10:00:51.130762 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1249 10:00:51.134446 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1250 10:00:51.134528 ==
1251 10:00:51.137722 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 10:00:51.140830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1253 10:00:51.140913 ==
1254 10:00:51.143998 DQS Delay:
1255 10:00:51.144080 DQS0 = 0, DQS1 = 0
1256 10:00:51.144145 DQM Delay:
1257 10:00:51.147542 DQM0 = 87, DQM1 = 78
1258 10:00:51.147623 DQ Delay:
1259 10:00:51.150859 DQ0 =85, DQ1 =93, DQ2 =77, DQ3 =85
1260 10:00:51.154179 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1261 10:00:51.157447 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1262 10:00:51.160948 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1263 10:00:51.161030
1264 10:00:51.161095
1265 10:00:51.161155 ==
1266 10:00:51.163897 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 10:00:51.170935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 10:00:51.171046 ==
1269 10:00:51.171140
1270 10:00:51.171229
1271 10:00:51.171315 TX Vref Scan disable
1272 10:00:51.174313 == TX Byte 0 ==
1273 10:00:51.177331 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1274 10:00:51.184477 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1275 10:00:51.184559 == TX Byte 1 ==
1276 10:00:51.187487 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1277 10:00:51.193968 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1278 10:00:51.194052 ==
1279 10:00:51.197357 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 10:00:51.200670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 10:00:51.200755 ==
1282 10:00:51.213768 TX Vref=22, minBit 1, minWin=27, winSum=441
1283 10:00:51.216951 TX Vref=24, minBit 1, minWin=27, winSum=444
1284 10:00:51.220486 TX Vref=26, minBit 2, minWin=27, winSum=447
1285 10:00:51.223754 TX Vref=28, minBit 9, minWin=27, winSum=451
1286 10:00:51.227062 TX Vref=30, minBit 1, minWin=27, winSum=452
1287 10:00:51.230467 TX Vref=32, minBit 4, minWin=27, winSum=450
1288 10:00:51.236885 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1289 10:00:51.236994
1290 10:00:51.239958 Final TX Range 1 Vref 30
1291 10:00:51.240055
1292 10:00:51.240130 ==
1293 10:00:51.243558 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 10:00:51.246800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 10:00:51.246903 ==
1296 10:00:51.249983
1297 10:00:51.250068
1298 10:00:51.250134 TX Vref Scan disable
1299 10:00:51.253360 == TX Byte 0 ==
1300 10:00:51.257535 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1301 10:00:51.263394 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1302 10:00:51.263528 == TX Byte 1 ==
1303 10:00:51.266691 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1304 10:00:51.273429 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1305 10:00:51.273536
1306 10:00:51.273603 [DATLAT]
1307 10:00:51.273663 Freq=800, CH0 RK1
1308 10:00:51.273723
1309 10:00:51.276669 DATLAT Default: 0xa
1310 10:00:51.276749 0, 0xFFFF, sum = 0
1311 10:00:51.280466 1, 0xFFFF, sum = 0
1312 10:00:51.283640 2, 0xFFFF, sum = 0
1313 10:00:51.283738 3, 0xFFFF, sum = 0
1314 10:00:51.286676 4, 0xFFFF, sum = 0
1315 10:00:51.286758 5, 0xFFFF, sum = 0
1316 10:00:51.289879 6, 0xFFFF, sum = 0
1317 10:00:51.289961 7, 0xFFFF, sum = 0
1318 10:00:51.293471 8, 0xFFFF, sum = 0
1319 10:00:51.293554 9, 0x0, sum = 1
1320 10:00:51.296709 10, 0x0, sum = 2
1321 10:00:51.296791 11, 0x0, sum = 3
1322 10:00:51.296856 12, 0x0, sum = 4
1323 10:00:51.299898 best_step = 10
1324 10:00:51.300018
1325 10:00:51.300083 ==
1326 10:00:51.303430 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 10:00:51.306580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 10:00:51.306676 ==
1329 10:00:51.309849 RX Vref Scan: 0
1330 10:00:51.309931
1331 10:00:51.309995 RX Vref 0 -> 0, step: 1
1332 10:00:51.313075
1333 10:00:51.313155 RX Delay -95 -> 252, step: 8
1334 10:00:51.320761 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1335 10:00:51.323781 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1336 10:00:51.326733 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1337 10:00:51.330061 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1338 10:00:51.333549 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1339 10:00:51.340106 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1340 10:00:51.343475 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1341 10:00:51.346953 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1342 10:00:51.350002 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1343 10:00:51.353743 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1344 10:00:51.360243 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1345 10:00:51.363346 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1346 10:00:51.366372 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1347 10:00:51.379343 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1348 10:00:51.379463 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1349 10:00:51.379814 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1350 10:00:51.379938 ==
1351 10:00:51.383088 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 10:00:51.386635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 10:00:51.386721 ==
1354 10:00:51.389890 DQS Delay:
1355 10:00:51.389972 DQS0 = 0, DQS1 = 0
1356 10:00:51.390038 DQM Delay:
1357 10:00:51.392890 DQM0 = 87, DQM1 = 77
1358 10:00:51.392974 DQ Delay:
1359 10:00:51.396264 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1360 10:00:51.399662 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1361 10:00:51.402988 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1362 10:00:51.406399 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1363 10:00:51.406488
1364 10:00:51.406556
1365 10:00:51.416468 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1366 10:00:51.416557 CH0 RK1: MR19=606, MR18=2F2B
1367 10:00:51.423600 CH0_RK1: MR19=0x606, MR18=0x2F2B, DQSOSC=397, MR23=63, INC=93, DEC=62
1368 10:00:51.426247 [RxdqsGatingPostProcess] freq 800
1369 10:00:51.433026 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1370 10:00:51.436499 Pre-setting of DQS Precalculation
1371 10:00:51.439845 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1372 10:00:51.439936 ==
1373 10:00:51.443363 Dram Type= 6, Freq= 0, CH_1, rank 0
1374 10:00:51.449819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 10:00:51.449917 ==
1376 10:00:51.453489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1377 10:00:51.459486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1378 10:00:51.469065 [CA 0] Center 37 (6~68) winsize 63
1379 10:00:51.471935 [CA 1] Center 37 (6~68) winsize 63
1380 10:00:51.475327 [CA 2] Center 35 (5~65) winsize 61
1381 10:00:51.478892 [CA 3] Center 34 (4~65) winsize 62
1382 10:00:51.481977 [CA 4] Center 34 (4~65) winsize 62
1383 10:00:51.485241 [CA 5] Center 33 (3~64) winsize 62
1384 10:00:51.485355
1385 10:00:51.488764 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1386 10:00:51.488879
1387 10:00:51.491962 [CATrainingPosCal] consider 1 rank data
1388 10:00:51.495414 u2DelayCellTimex100 = 270/100 ps
1389 10:00:51.498352 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1390 10:00:51.505463 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1391 10:00:51.508407 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1392 10:00:51.511843 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 10:00:51.515135 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1394 10:00:51.518441 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 10:00:51.518522
1396 10:00:51.522247 CA PerBit enable=1, Macro0, CA PI delay=33
1397 10:00:51.522328
1398 10:00:51.525141 [CBTSetCACLKResult] CA Dly = 33
1399 10:00:51.525222 CS Dly: 4 (0~35)
1400 10:00:51.528467 ==
1401 10:00:51.531953 Dram Type= 6, Freq= 0, CH_1, rank 1
1402 10:00:51.534923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 10:00:51.535004 ==
1404 10:00:51.538564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1405 10:00:51.545140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1406 10:00:51.555280 [CA 0] Center 36 (6~67) winsize 62
1407 10:00:51.558493 [CA 1] Center 36 (6~67) winsize 62
1408 10:00:51.561800 [CA 2] Center 34 (4~65) winsize 62
1409 10:00:51.565128 [CA 3] Center 34 (3~65) winsize 63
1410 10:00:51.567922 [CA 4] Center 34 (4~65) winsize 62
1411 10:00:51.571835 [CA 5] Center 34 (3~65) winsize 63
1412 10:00:51.571962
1413 10:00:51.575075 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1414 10:00:51.575160
1415 10:00:51.578070 [CATrainingPosCal] consider 2 rank data
1416 10:00:51.581453 u2DelayCellTimex100 = 270/100 ps
1417 10:00:51.585210 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1418 10:00:51.589387 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1419 10:00:51.592163 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1420 10:00:51.596007 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1421 10:00:51.599531 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1422 10:00:51.603384 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 10:00:51.603470
1424 10:00:51.607346 CA PerBit enable=1, Macro0, CA PI delay=33
1425 10:00:51.607431
1426 10:00:51.610246 [CBTSetCACLKResult] CA Dly = 33
1427 10:00:51.614064 CS Dly: 5 (0~37)
1428 10:00:51.614155
1429 10:00:51.617593 ----->DramcWriteLeveling(PI) begin...
1430 10:00:51.617684 ==
1431 10:00:51.620748 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 10:00:51.624170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 10:00:51.624248 ==
1434 10:00:51.627363 Write leveling (Byte 0): 27 => 27
1435 10:00:51.631025 Write leveling (Byte 1): 27 => 27
1436 10:00:51.634078 DramcWriteLeveling(PI) end<-----
1437 10:00:51.634152
1438 10:00:51.634215 ==
1439 10:00:51.637463 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 10:00:51.640591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 10:00:51.640661 ==
1442 10:00:51.644486 [Gating] SW mode calibration
1443 10:00:51.650599 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1444 10:00:51.657498 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1445 10:00:51.660776 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1446 10:00:51.664247 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1447 10:00:51.670722 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1448 10:00:51.674222 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 10:00:51.677338 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 10:00:51.683818 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 10:00:51.686926 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 10:00:51.690312 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 10:00:51.697287 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 10:00:51.700674 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:00:51.703988 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:00:51.710170 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:00:51.713760 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:00:51.716982 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:00:51.723537 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:00:51.726856 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:00:51.730033 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 10:00:51.737136 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1463 10:00:51.740381 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1464 10:00:51.743716 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 10:00:51.747001 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:00:51.753411 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:00:51.757440 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:00:51.760361 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:00:51.766935 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:00:51.770244 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:00:51.773710 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
1472 10:00:51.779937 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 10:00:51.783778 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 10:00:51.786886 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 10:00:51.793275 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 10:00:51.796636 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 10:00:51.799877 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1478 10:00:51.806298 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1479 10:00:51.809934 0 10 8 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
1480 10:00:51.813339 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:00:51.819445 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 10:00:51.822770 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 10:00:51.826332 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 10:00:51.833192 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:00:51.836407 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:00:51.839420 0 11 4 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
1487 10:00:51.845938 0 11 8 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
1488 10:00:51.849279 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 10:00:51.852883 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 10:00:51.859706 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 10:00:51.862832 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 10:00:51.866357 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 10:00:51.873014 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 10:00:51.876693 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1495 10:00:51.879801 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 10:00:51.886268 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 10:00:51.889466 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 10:00:51.892837 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 10:00:51.899352 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 10:00:51.902958 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 10:00:51.906617 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 10:00:51.912649 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 10:00:51.916243 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:00:51.919699 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:00:51.922812 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:00:51.929670 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:00:51.932873 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:00:51.936076 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:00:51.942536 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:00:51.945820 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1511 10:00:51.949207 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1512 10:00:51.952549 Total UI for P1: 0, mck2ui 16
1513 10:00:51.956180 best dqsien dly found for B0: ( 0, 14, 4)
1514 10:00:51.962343 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 10:00:51.966119 Total UI for P1: 0, mck2ui 16
1516 10:00:51.969080 best dqsien dly found for B1: ( 0, 14, 6)
1517 10:00:51.972108 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1518 10:00:51.975992 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1519 10:00:51.976077
1520 10:00:51.978843 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1521 10:00:51.982118 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 10:00:51.985654 [Gating] SW calibration Done
1523 10:00:51.985738 ==
1524 10:00:51.989488 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 10:00:51.992492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 10:00:51.992578 ==
1527 10:00:51.995353 RX Vref Scan: 0
1528 10:00:51.995438
1529 10:00:51.995561 RX Vref 0 -> 0, step: 1
1530 10:00:51.999012
1531 10:00:51.999088 RX Delay -130 -> 252, step: 16
1532 10:00:52.005589 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1533 10:00:52.008600 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1534 10:00:52.012039 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1535 10:00:52.015626 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1536 10:00:52.018682 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1537 10:00:52.025470 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1538 10:00:52.029098 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1539 10:00:52.032311 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1540 10:00:52.035443 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1541 10:00:52.038959 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1542 10:00:52.045416 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1543 10:00:52.048443 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1544 10:00:52.051746 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1545 10:00:52.055204 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1546 10:00:52.062214 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1547 10:00:52.065229 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1548 10:00:52.065313 ==
1549 10:00:52.069154 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 10:00:52.072080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 10:00:52.072165 ==
1552 10:00:52.072252 DQS Delay:
1553 10:00:52.075099 DQS0 = 0, DQS1 = 0
1554 10:00:52.075183 DQM Delay:
1555 10:00:52.078253 DQM0 = 87, DQM1 = 82
1556 10:00:52.078337 DQ Delay:
1557 10:00:52.082242 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1558 10:00:52.085022 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1559 10:00:52.088273 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1560 10:00:52.091436 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 10:00:52.091520
1562 10:00:52.091607
1563 10:00:52.091688 ==
1564 10:00:52.095206 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 10:00:52.101369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 10:00:52.101454 ==
1567 10:00:52.101540
1568 10:00:52.101622
1569 10:00:52.101702 TX Vref Scan disable
1570 10:00:52.104840 == TX Byte 0 ==
1571 10:00:52.108675 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1572 10:00:52.115041 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1573 10:00:52.115127 == TX Byte 1 ==
1574 10:00:52.118066 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1575 10:00:52.121307 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1576 10:00:52.124788 ==
1577 10:00:52.128295 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 10:00:52.131944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 10:00:52.132030 ==
1580 10:00:52.143622 TX Vref=22, minBit 1, minWin=27, winSum=445
1581 10:00:52.147133 TX Vref=24, minBit 2, minWin=27, winSum=448
1582 10:00:52.150206 TX Vref=26, minBit 0, minWin=27, winSum=451
1583 10:00:52.153669 TX Vref=28, minBit 0, minWin=28, winSum=457
1584 10:00:52.156994 TX Vref=30, minBit 1, minWin=27, winSum=457
1585 10:00:52.164031 TX Vref=32, minBit 1, minWin=27, winSum=451
1586 10:00:52.167714 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1587 10:00:52.167799
1588 10:00:52.171056 Final TX Range 1 Vref 28
1589 10:00:52.171141
1590 10:00:52.171228 ==
1591 10:00:52.174342 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 10:00:52.177645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 10:00:52.177746 ==
1594 10:00:52.177849
1595 10:00:52.177933
1596 10:00:52.181096 TX Vref Scan disable
1597 10:00:52.184562 == TX Byte 0 ==
1598 10:00:52.187773 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1599 10:00:52.191173 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1600 10:00:52.194135 == TX Byte 1 ==
1601 10:00:52.197709 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1602 10:00:52.201096 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1603 10:00:52.201181
1604 10:00:52.204190 [DATLAT]
1605 10:00:52.204274 Freq=800, CH1 RK0
1606 10:00:52.204361
1607 10:00:52.207910 DATLAT Default: 0xa
1608 10:00:52.207995 0, 0xFFFF, sum = 0
1609 10:00:52.210957 1, 0xFFFF, sum = 0
1610 10:00:52.211044 2, 0xFFFF, sum = 0
1611 10:00:52.214583 3, 0xFFFF, sum = 0
1612 10:00:52.214669 4, 0xFFFF, sum = 0
1613 10:00:52.217968 5, 0xFFFF, sum = 0
1614 10:00:52.218054 6, 0xFFFF, sum = 0
1615 10:00:52.220967 7, 0xFFFF, sum = 0
1616 10:00:52.221053 8, 0xFFFF, sum = 0
1617 10:00:52.224879 9, 0x0, sum = 1
1618 10:00:52.224965 10, 0x0, sum = 2
1619 10:00:52.227868 11, 0x0, sum = 3
1620 10:00:52.227962 12, 0x0, sum = 4
1621 10:00:52.231090 best_step = 10
1622 10:00:52.231174
1623 10:00:52.231260 ==
1624 10:00:52.234536 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 10:00:52.237680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 10:00:52.237783 ==
1627 10:00:52.237870 RX Vref Scan: 1
1628 10:00:52.241138
1629 10:00:52.241222 Set Vref Range= 32 -> 127
1630 10:00:52.241309
1631 10:00:52.244206 RX Vref 32 -> 127, step: 1
1632 10:00:52.244291
1633 10:00:52.247256 RX Delay -95 -> 252, step: 8
1634 10:00:52.247368
1635 10:00:52.250678 Set Vref, RX VrefLevel [Byte0]: 32
1636 10:00:52.253994 [Byte1]: 32
1637 10:00:52.254079
1638 10:00:52.257152 Set Vref, RX VrefLevel [Byte0]: 33
1639 10:00:52.260538 [Byte1]: 33
1640 10:00:52.263949
1641 10:00:52.264034 Set Vref, RX VrefLevel [Byte0]: 34
1642 10:00:52.267276 [Byte1]: 34
1643 10:00:52.271620
1644 10:00:52.271704 Set Vref, RX VrefLevel [Byte0]: 35
1645 10:00:52.275157 [Byte1]: 35
1646 10:00:52.279400
1647 10:00:52.279484 Set Vref, RX VrefLevel [Byte0]: 36
1648 10:00:52.282556 [Byte1]: 36
1649 10:00:52.286630
1650 10:00:52.286715 Set Vref, RX VrefLevel [Byte0]: 37
1651 10:00:52.289983 [Byte1]: 37
1652 10:00:52.294036
1653 10:00:52.294120 Set Vref, RX VrefLevel [Byte0]: 38
1654 10:00:52.297765 [Byte1]: 38
1655 10:00:52.302009
1656 10:00:52.302093 Set Vref, RX VrefLevel [Byte0]: 39
1657 10:00:52.305257 [Byte1]: 39
1658 10:00:52.309364
1659 10:00:52.309449 Set Vref, RX VrefLevel [Byte0]: 40
1660 10:00:52.312801 [Byte1]: 40
1661 10:00:52.317128
1662 10:00:52.317212 Set Vref, RX VrefLevel [Byte0]: 41
1663 10:00:52.320166 [Byte1]: 41
1664 10:00:52.324731
1665 10:00:52.324814 Set Vref, RX VrefLevel [Byte0]: 42
1666 10:00:52.327742 [Byte1]: 42
1667 10:00:52.332690
1668 10:00:52.332774 Set Vref, RX VrefLevel [Byte0]: 43
1669 10:00:52.335584 [Byte1]: 43
1670 10:00:52.340025
1671 10:00:52.343298 Set Vref, RX VrefLevel [Byte0]: 44
1672 10:00:52.343383 [Byte1]: 44
1673 10:00:52.347363
1674 10:00:52.347448 Set Vref, RX VrefLevel [Byte0]: 45
1675 10:00:52.350836 [Byte1]: 45
1676 10:00:52.355433
1677 10:00:52.355517 Set Vref, RX VrefLevel [Byte0]: 46
1678 10:00:52.358643 [Byte1]: 46
1679 10:00:52.363229
1680 10:00:52.363313 Set Vref, RX VrefLevel [Byte0]: 47
1681 10:00:52.366110 [Byte1]: 47
1682 10:00:52.370434
1683 10:00:52.370519 Set Vref, RX VrefLevel [Byte0]: 48
1684 10:00:52.373394 [Byte1]: 48
1685 10:00:52.377921
1686 10:00:52.378005 Set Vref, RX VrefLevel [Byte0]: 49
1687 10:00:52.381163 [Byte1]: 49
1688 10:00:52.385506
1689 10:00:52.385590 Set Vref, RX VrefLevel [Byte0]: 50
1690 10:00:52.389064 [Byte1]: 50
1691 10:00:52.393245
1692 10:00:52.393330 Set Vref, RX VrefLevel [Byte0]: 51
1693 10:00:52.396759 [Byte1]: 51
1694 10:00:52.400736
1695 10:00:52.400820 Set Vref, RX VrefLevel [Byte0]: 52
1696 10:00:52.404161 [Byte1]: 52
1697 10:00:52.408337
1698 10:00:52.408421 Set Vref, RX VrefLevel [Byte0]: 53
1699 10:00:52.411477 [Byte1]: 53
1700 10:00:52.415749
1701 10:00:52.415832 Set Vref, RX VrefLevel [Byte0]: 54
1702 10:00:52.418951 [Byte1]: 54
1703 10:00:52.423383
1704 10:00:52.423467 Set Vref, RX VrefLevel [Byte0]: 55
1705 10:00:52.426847 [Byte1]: 55
1706 10:00:52.431364
1707 10:00:52.431448 Set Vref, RX VrefLevel [Byte0]: 56
1708 10:00:52.434654 [Byte1]: 56
1709 10:00:52.438789
1710 10:00:52.441933 Set Vref, RX VrefLevel [Byte0]: 57
1711 10:00:52.442019 [Byte1]: 57
1712 10:00:52.446601
1713 10:00:52.446685 Set Vref, RX VrefLevel [Byte0]: 58
1714 10:00:52.449410 [Byte1]: 58
1715 10:00:52.453719
1716 10:00:52.453803 Set Vref, RX VrefLevel [Byte0]: 59
1717 10:00:52.457122 [Byte1]: 59
1718 10:00:52.461694
1719 10:00:52.461779 Set Vref, RX VrefLevel [Byte0]: 60
1720 10:00:52.464518 [Byte1]: 60
1721 10:00:52.469253
1722 10:00:52.469337 Set Vref, RX VrefLevel [Byte0]: 61
1723 10:00:52.472445 [Byte1]: 61
1724 10:00:52.477044
1725 10:00:52.477128 Set Vref, RX VrefLevel [Byte0]: 62
1726 10:00:52.479776 [Byte1]: 62
1727 10:00:52.484074
1728 10:00:52.484159 Set Vref, RX VrefLevel [Byte0]: 63
1729 10:00:52.487437 [Byte1]: 63
1730 10:00:52.491771
1731 10:00:52.491856 Set Vref, RX VrefLevel [Byte0]: 64
1732 10:00:52.495184 [Byte1]: 64
1733 10:00:52.499148
1734 10:00:52.499232 Set Vref, RX VrefLevel [Byte0]: 65
1735 10:00:52.502553 [Byte1]: 65
1736 10:00:52.507031
1737 10:00:52.507115 Set Vref, RX VrefLevel [Byte0]: 66
1738 10:00:52.510173 [Byte1]: 66
1739 10:00:52.514658
1740 10:00:52.514742 Set Vref, RX VrefLevel [Byte0]: 67
1741 10:00:52.517897 [Byte1]: 67
1742 10:00:52.522099
1743 10:00:52.522183 Set Vref, RX VrefLevel [Byte0]: 68
1744 10:00:52.525556 [Byte1]: 68
1745 10:00:52.529662
1746 10:00:52.529746 Set Vref, RX VrefLevel [Byte0]: 69
1747 10:00:52.533212 [Byte1]: 69
1748 10:00:52.537591
1749 10:00:52.537675 Set Vref, RX VrefLevel [Byte0]: 70
1750 10:00:52.541001 [Byte1]: 70
1751 10:00:52.545382
1752 10:00:52.545466 Set Vref, RX VrefLevel [Byte0]: 71
1753 10:00:52.548331 [Byte1]: 71
1754 10:00:52.552774
1755 10:00:52.552858 Set Vref, RX VrefLevel [Byte0]: 72
1756 10:00:52.555764 [Byte1]: 72
1757 10:00:52.560264
1758 10:00:52.560348 Set Vref, RX VrefLevel [Byte0]: 73
1759 10:00:52.563588 [Byte1]: 73
1760 10:00:52.568318
1761 10:00:52.568403 Set Vref, RX VrefLevel [Byte0]: 74
1762 10:00:52.571332 [Byte1]: 74
1763 10:00:52.575259
1764 10:00:52.575343 Set Vref, RX VrefLevel [Byte0]: 75
1765 10:00:52.578658 [Byte1]: 75
1766 10:00:52.582979
1767 10:00:52.583063 Final RX Vref Byte 0 = 55 to rank0
1768 10:00:52.586138 Final RX Vref Byte 1 = 52 to rank0
1769 10:00:52.589369 Final RX Vref Byte 0 = 55 to rank1
1770 10:00:52.593230 Final RX Vref Byte 1 = 52 to rank1==
1771 10:00:52.596302 Dram Type= 6, Freq= 0, CH_1, rank 0
1772 10:00:52.602896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 10:00:52.602979 ==
1774 10:00:52.603045 DQS Delay:
1775 10:00:52.603106 DQS0 = 0, DQS1 = 0
1776 10:00:52.606117 DQM Delay:
1777 10:00:52.606186 DQM0 = 85, DQM1 = 80
1778 10:00:52.609932 DQ Delay:
1779 10:00:52.612767 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1780 10:00:52.616232 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1781 10:00:52.619431 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1782 10:00:52.622815 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1783 10:00:52.622896
1784 10:00:52.622961
1785 10:00:52.629333 [DQSOSCAuto] RK0, (LSB)MR18= 0x182b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1786 10:00:52.632930 CH1 RK0: MR19=606, MR18=182B
1787 10:00:52.639301 CH1_RK0: MR19=0x606, MR18=0x182B, DQSOSC=398, MR23=63, INC=93, DEC=62
1788 10:00:52.639383
1789 10:00:52.642332 ----->DramcWriteLeveling(PI) begin...
1790 10:00:52.642415 ==
1791 10:00:52.645496 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 10:00:52.649099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 10:00:52.649180 ==
1794 10:00:52.652267 Write leveling (Byte 0): 26 => 26
1795 10:00:52.655621 Write leveling (Byte 1): 28 => 28
1796 10:00:52.659000 DramcWriteLeveling(PI) end<-----
1797 10:00:52.659081
1798 10:00:52.659145 ==
1799 10:00:52.662670 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 10:00:52.665888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 10:00:52.666006 ==
1802 10:00:52.669033 [Gating] SW mode calibration
1803 10:00:52.675577 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1804 10:00:52.682544 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1805 10:00:52.685475 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1806 10:00:52.692338 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1807 10:00:52.695229 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 10:00:52.698648 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 10:00:52.705489 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 10:00:52.708579 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 10:00:52.711878 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 10:00:52.718482 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 10:00:52.721803 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 10:00:52.725033 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 10:00:52.731773 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:00:52.735136 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:00:52.738057 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:00:52.745136 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:00:52.747898 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 10:00:52.751535 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:00:52.758168 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1822 10:00:52.761581 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1823 10:00:52.764891 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:00:52.771319 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:00:52.774852 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 10:00:52.777855 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:00:52.784604 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:00:52.788562 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:00:52.791304 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:00:52.797941 0 9 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1831 10:00:52.801323 0 9 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
1832 10:00:52.804335 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 10:00:52.811088 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 10:00:52.814258 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 10:00:52.817647 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 10:00:52.820918 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 10:00:52.827550 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1838 10:00:52.830894 0 10 4 | B1->B0 | 3232 2626 | 1 0 | (1 0) (0 0)
1839 10:00:52.834020 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1840 10:00:52.840681 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 10:00:52.844385 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 10:00:52.847478 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 10:00:52.853855 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 10:00:52.857677 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 10:00:52.860887 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 10:00:52.867813 0 11 4 | B1->B0 | 2929 3737 | 0 1 | (0 0) (0 0)
1847 10:00:52.870524 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
1848 10:00:52.874220 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 10:00:52.880392 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 10:00:52.883798 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 10:00:52.887265 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 10:00:52.893915 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 10:00:52.897256 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1854 10:00:52.900589 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1855 10:00:52.907184 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 10:00:52.910439 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 10:00:52.913986 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 10:00:52.920516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 10:00:52.923603 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 10:00:52.927363 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 10:00:52.933709 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 10:00:52.937238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 10:00:52.940502 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 10:00:52.947114 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 10:00:52.950637 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:00:52.953576 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:00:52.960372 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 10:00:52.963758 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:00:52.966567 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1870 10:00:52.973432 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1871 10:00:52.973514 Total UI for P1: 0, mck2ui 16
1872 10:00:52.980072 best dqsien dly found for B0: ( 0, 14, 0)
1873 10:00:52.984152 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1874 10:00:52.986624 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 10:00:52.990076 Total UI for P1: 0, mck2ui 16
1876 10:00:52.993261 best dqsien dly found for B1: ( 0, 14, 6)
1877 10:00:52.996808 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1878 10:00:53.000179 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1879 10:00:53.000261
1880 10:00:53.003652 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1881 10:00:53.009975 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1882 10:00:53.010057 [Gating] SW calibration Done
1883 10:00:53.010122 ==
1884 10:00:53.013380 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 10:00:53.019876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 10:00:53.019972 ==
1887 10:00:53.020039 RX Vref Scan: 0
1888 10:00:53.020101
1889 10:00:53.023178 RX Vref 0 -> 0, step: 1
1890 10:00:53.023287
1891 10:00:53.026269 RX Delay -130 -> 252, step: 16
1892 10:00:53.029926 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1893 10:00:53.033269 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1894 10:00:53.036711 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1895 10:00:53.042991 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1896 10:00:53.046448 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1897 10:00:53.049800 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1898 10:00:53.053053 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1899 10:00:53.056427 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1900 10:00:53.062944 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1901 10:00:53.065962 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1902 10:00:53.069520 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1903 10:00:53.072662 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1904 10:00:53.076519 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1905 10:00:53.082873 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1906 10:00:53.085946 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1907 10:00:53.090368 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1908 10:00:53.090449 ==
1909 10:00:53.092766 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 10:00:53.095918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 10:00:53.099856 ==
1912 10:00:53.099961 DQS Delay:
1913 10:00:53.100027 DQS0 = 0, DQS1 = 0
1914 10:00:53.102597 DQM Delay:
1915 10:00:53.102684 DQM0 = 83, DQM1 = 79
1916 10:00:53.105793 DQ Delay:
1917 10:00:53.105874 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1918 10:00:53.109278 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1919 10:00:53.112517 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1920 10:00:53.115885 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1921 10:00:53.115973
1922 10:00:53.116037
1923 10:00:53.119373 ==
1924 10:00:53.122855 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 10:00:53.125954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 10:00:53.126036 ==
1927 10:00:53.126101
1928 10:00:53.126161
1929 10:00:53.129288 TX Vref Scan disable
1930 10:00:53.129369 == TX Byte 0 ==
1931 10:00:53.132607 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1932 10:00:53.139431 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1933 10:00:53.139515 == TX Byte 1 ==
1934 10:00:53.145929 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1935 10:00:53.149408 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1936 10:00:53.149493 ==
1937 10:00:53.152555 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 10:00:53.155941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 10:00:53.156026 ==
1940 10:00:53.169311 TX Vref=22, minBit 1, minWin=27, winSum=447
1941 10:00:53.172991 TX Vref=24, minBit 1, minWin=27, winSum=451
1942 10:00:53.176026 TX Vref=26, minBit 0, minWin=27, winSum=451
1943 10:00:53.179550 TX Vref=28, minBit 4, minWin=27, winSum=453
1944 10:00:53.182867 TX Vref=30, minBit 0, minWin=28, winSum=457
1945 10:00:53.186273 TX Vref=32, minBit 2, minWin=27, winSum=453
1946 10:00:53.192390 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1947 10:00:53.192475
1948 10:00:53.195575 Final TX Range 1 Vref 30
1949 10:00:53.195659
1950 10:00:53.195745 ==
1951 10:00:53.199169 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 10:00:53.202925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 10:00:53.203010 ==
1954 10:00:53.205758
1955 10:00:53.205842
1956 10:00:53.205929 TX Vref Scan disable
1957 10:00:53.209447 == TX Byte 0 ==
1958 10:00:53.212269 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1959 10:00:53.218880 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1960 10:00:53.218965 == TX Byte 1 ==
1961 10:00:53.222476 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1962 10:00:53.228960 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1963 10:00:53.229045
1964 10:00:53.229131 [DATLAT]
1965 10:00:53.229212 Freq=800, CH1 RK1
1966 10:00:53.229292
1967 10:00:53.232240 DATLAT Default: 0xa
1968 10:00:53.232324 0, 0xFFFF, sum = 0
1969 10:00:53.235792 1, 0xFFFF, sum = 0
1970 10:00:53.239147 2, 0xFFFF, sum = 0
1971 10:00:53.239233 3, 0xFFFF, sum = 0
1972 10:00:53.242606 4, 0xFFFF, sum = 0
1973 10:00:53.242692 5, 0xFFFF, sum = 0
1974 10:00:53.245794 6, 0xFFFF, sum = 0
1975 10:00:53.245880 7, 0xFFFF, sum = 0
1976 10:00:53.248840 8, 0xFFFF, sum = 0
1977 10:00:53.248925 9, 0x0, sum = 1
1978 10:00:53.252264 10, 0x0, sum = 2
1979 10:00:53.252350 11, 0x0, sum = 3
1980 10:00:53.252438 12, 0x0, sum = 4
1981 10:00:53.255894 best_step = 10
1982 10:00:53.256019
1983 10:00:53.256105 ==
1984 10:00:53.259379 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 10:00:53.262615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 10:00:53.262700 ==
1987 10:00:53.265383 RX Vref Scan: 0
1988 10:00:53.265468
1989 10:00:53.265554 RX Vref 0 -> 0, step: 1
1990 10:00:53.268927
1991 10:00:53.269043 RX Delay -95 -> 252, step: 8
1992 10:00:53.276147 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1993 10:00:53.279491 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1994 10:00:53.282732 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1995 10:00:53.285775 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1996 10:00:53.288952 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1997 10:00:53.295676 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1998 10:00:53.299335 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1999 10:00:53.302258 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2000 10:00:53.305497 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2001 10:00:53.309031 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2002 10:00:53.315507 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2003 10:00:53.318918 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2004 10:00:53.322017 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2005 10:00:53.325669 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2006 10:00:53.332468 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2007 10:00:53.335896 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2008 10:00:53.335987 ==
2009 10:00:53.339159 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 10:00:53.342464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 10:00:53.342550 ==
2012 10:00:53.342637 DQS Delay:
2013 10:00:53.345567 DQS0 = 0, DQS1 = 0
2014 10:00:53.345651 DQM Delay:
2015 10:00:53.348767 DQM0 = 86, DQM1 = 81
2016 10:00:53.348851 DQ Delay:
2017 10:00:53.352306 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2018 10:00:53.355346 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2019 10:00:53.358616 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2020 10:00:53.362457 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2021 10:00:53.362542
2022 10:00:53.362629
2023 10:00:53.372529 [DQSOSCAuto] RK1, (LSB)MR18= 0x203d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2024 10:00:53.372616 CH1 RK1: MR19=606, MR18=203D
2025 10:00:53.378740 CH1_RK1: MR19=0x606, MR18=0x203D, DQSOSC=394, MR23=63, INC=95, DEC=63
2026 10:00:53.381889 [RxdqsGatingPostProcess] freq 800
2027 10:00:53.389011 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 10:00:53.392148 Pre-setting of DQS Precalculation
2029 10:00:53.395224 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 10:00:53.401973 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 10:00:53.411933 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 10:00:53.412018
2033 10:00:53.412106
2034 10:00:53.415138 [Calibration Summary] 1600 Mbps
2035 10:00:53.415223 CH 0, Rank 0
2036 10:00:53.418885 SW Impedance : PASS
2037 10:00:53.418970 DUTY Scan : NO K
2038 10:00:53.421794 ZQ Calibration : PASS
2039 10:00:53.421879 Jitter Meter : NO K
2040 10:00:53.425273 CBT Training : PASS
2041 10:00:53.428493 Write leveling : PASS
2042 10:00:53.428578 RX DQS gating : PASS
2043 10:00:53.431799 RX DQ/DQS(RDDQC) : PASS
2044 10:00:53.435329 TX DQ/DQS : PASS
2045 10:00:53.435413 RX DATLAT : PASS
2046 10:00:53.438572 RX DQ/DQS(Engine): PASS
2047 10:00:53.442135 TX OE : NO K
2048 10:00:53.442219 All Pass.
2049 10:00:53.442305
2050 10:00:53.442387 CH 0, Rank 1
2051 10:00:53.445190 SW Impedance : PASS
2052 10:00:53.448291 DUTY Scan : NO K
2053 10:00:53.448376 ZQ Calibration : PASS
2054 10:00:53.452067 Jitter Meter : NO K
2055 10:00:53.455080 CBT Training : PASS
2056 10:00:53.455235 Write leveling : PASS
2057 10:00:53.458990 RX DQS gating : PASS
2058 10:00:53.461806 RX DQ/DQS(RDDQC) : PASS
2059 10:00:53.461891 TX DQ/DQS : PASS
2060 10:00:53.465193 RX DATLAT : PASS
2061 10:00:53.465278 RX DQ/DQS(Engine): PASS
2062 10:00:53.468710 TX OE : NO K
2063 10:00:53.468794 All Pass.
2064 10:00:53.468881
2065 10:00:53.471839 CH 1, Rank 0
2066 10:00:53.471977 SW Impedance : PASS
2067 10:00:53.475174 DUTY Scan : NO K
2068 10:00:53.478408 ZQ Calibration : PASS
2069 10:00:53.478493 Jitter Meter : NO K
2070 10:00:53.482164 CBT Training : PASS
2071 10:00:53.485071 Write leveling : PASS
2072 10:00:53.485155 RX DQS gating : PASS
2073 10:00:53.488417 RX DQ/DQS(RDDQC) : PASS
2074 10:00:53.491715 TX DQ/DQS : PASS
2075 10:00:53.491800 RX DATLAT : PASS
2076 10:00:53.495280 RX DQ/DQS(Engine): PASS
2077 10:00:53.498238 TX OE : NO K
2078 10:00:53.498323 All Pass.
2079 10:00:53.498409
2080 10:00:53.498490 CH 1, Rank 1
2081 10:00:53.501431 SW Impedance : PASS
2082 10:00:53.505082 DUTY Scan : NO K
2083 10:00:53.505166 ZQ Calibration : PASS
2084 10:00:53.508489 Jitter Meter : NO K
2085 10:00:53.511660 CBT Training : PASS
2086 10:00:53.511744 Write leveling : PASS
2087 10:00:53.515219 RX DQS gating : PASS
2088 10:00:53.515303 RX DQ/DQS(RDDQC) : PASS
2089 10:00:53.518015 TX DQ/DQS : PASS
2090 10:00:53.521722 RX DATLAT : PASS
2091 10:00:53.521807 RX DQ/DQS(Engine): PASS
2092 10:00:53.525292 TX OE : NO K
2093 10:00:53.525377 All Pass.
2094 10:00:53.525463
2095 10:00:53.527995 DramC Write-DBI off
2096 10:00:53.531114 PER_BANK_REFRESH: Hybrid Mode
2097 10:00:53.531199 TX_TRACKING: ON
2098 10:00:53.534931 [GetDramInforAfterCalByMRR] Vendor 6.
2099 10:00:53.537626 [GetDramInforAfterCalByMRR] Revision 606.
2100 10:00:53.544682 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 10:00:53.544769 MR0 0x3b3b
2102 10:00:53.544857 MR8 0x5151
2103 10:00:53.547899 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 10:00:53.547992
2105 10:00:53.550813 MR0 0x3b3b
2106 10:00:53.550897 MR8 0x5151
2107 10:00:53.554329 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 10:00:53.554414
2109 10:00:53.564040 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 10:00:53.567656 [FAST_K] Save calibration result to emmc
2111 10:00:53.571168 [FAST_K] Save calibration result to emmc
2112 10:00:53.574535 dram_init: config_dvfs: 1
2113 10:00:53.577305 dramc_set_vcore_voltage set vcore to 662500
2114 10:00:53.580766 Read voltage for 1200, 2
2115 10:00:53.580850 Vio18 = 0
2116 10:00:53.580939 Vcore = 662500
2117 10:00:53.584239 Vdram = 0
2118 10:00:53.584323 Vddq = 0
2119 10:00:53.584410 Vmddr = 0
2120 10:00:53.590662 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 10:00:53.594043 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 10:00:53.597683 MEM_TYPE=3, freq_sel=15
2123 10:00:53.600728 sv_algorithm_assistance_LP4_1600
2124 10:00:53.604268 ============ PULL DRAM RESETB DOWN ============
2125 10:00:53.607366 ========== PULL DRAM RESETB DOWN end =========
2126 10:00:53.613849 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 10:00:53.617188 ===================================
2128 10:00:53.617273 LPDDR4 DRAM CONFIGURATION
2129 10:00:53.620841 ===================================
2130 10:00:53.624208 EX_ROW_EN[0] = 0x0
2131 10:00:53.627645 EX_ROW_EN[1] = 0x0
2132 10:00:53.627730 LP4Y_EN = 0x0
2133 10:00:53.630837 WORK_FSP = 0x0
2134 10:00:53.630922 WL = 0x4
2135 10:00:53.634139 RL = 0x4
2136 10:00:53.634223 BL = 0x2
2137 10:00:53.637475 RPST = 0x0
2138 10:00:53.637560 RD_PRE = 0x0
2139 10:00:53.640588 WR_PRE = 0x1
2140 10:00:53.640674 WR_PST = 0x0
2141 10:00:53.643893 DBI_WR = 0x0
2142 10:00:53.643987 DBI_RD = 0x0
2143 10:00:53.647340 OTF = 0x1
2144 10:00:53.650736 ===================================
2145 10:00:53.654141 ===================================
2146 10:00:53.654227 ANA top config
2147 10:00:53.657380 ===================================
2148 10:00:53.660786 DLL_ASYNC_EN = 0
2149 10:00:53.663830 ALL_SLAVE_EN = 0
2150 10:00:53.667054 NEW_RANK_MODE = 1
2151 10:00:53.667138 DLL_IDLE_MODE = 1
2152 10:00:53.670553 LP45_APHY_COMB_EN = 1
2153 10:00:53.673527 TX_ODT_DIS = 1
2154 10:00:53.677456 NEW_8X_MODE = 1
2155 10:00:53.680286 ===================================
2156 10:00:53.683645 ===================================
2157 10:00:53.687242 data_rate = 2400
2158 10:00:53.687327 CKR = 1
2159 10:00:53.690614 DQ_P2S_RATIO = 8
2160 10:00:53.694041 ===================================
2161 10:00:53.697476 CA_P2S_RATIO = 8
2162 10:00:53.700610 DQ_CA_OPEN = 0
2163 10:00:53.703840 DQ_SEMI_OPEN = 0
2164 10:00:53.703972 CA_SEMI_OPEN = 0
2165 10:00:53.706835 CA_FULL_RATE = 0
2166 10:00:53.710274 DQ_CKDIV4_EN = 0
2167 10:00:53.713713 CA_CKDIV4_EN = 0
2168 10:00:53.717051 CA_PREDIV_EN = 0
2169 10:00:53.720300 PH8_DLY = 17
2170 10:00:53.720384 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 10:00:53.723666 DQ_AAMCK_DIV = 4
2172 10:00:53.726926 CA_AAMCK_DIV = 4
2173 10:00:53.730249 CA_ADMCK_DIV = 4
2174 10:00:53.733676 DQ_TRACK_CA_EN = 0
2175 10:00:53.736895 CA_PICK = 1200
2176 10:00:53.740668 CA_MCKIO = 1200
2177 10:00:53.740748 MCKIO_SEMI = 0
2178 10:00:53.743752 PLL_FREQ = 2366
2179 10:00:53.747465 DQ_UI_PI_RATIO = 32
2180 10:00:53.750215 CA_UI_PI_RATIO = 0
2181 10:00:53.753601 ===================================
2182 10:00:53.757006 ===================================
2183 10:00:53.760313 memory_type:LPDDR4
2184 10:00:53.760394 GP_NUM : 10
2185 10:00:53.764176 SRAM_EN : 1
2186 10:00:53.764257 MD32_EN : 0
2187 10:00:53.767209 ===================================
2188 10:00:53.770618 [ANA_INIT] >>>>>>>>>>>>>>
2189 10:00:53.774017 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 10:00:53.776963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 10:00:53.780838 ===================================
2192 10:00:53.783945 data_rate = 2400,PCW = 0X5b00
2193 10:00:53.787229 ===================================
2194 10:00:53.790795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 10:00:53.797069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 10:00:53.800221 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 10:00:53.807109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 10:00:53.810207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 10:00:53.813628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 10:00:53.813714 [ANA_INIT] flow start
2201 10:00:53.816648 [ANA_INIT] PLL >>>>>>>>
2202 10:00:53.820275 [ANA_INIT] PLL <<<<<<<<
2203 10:00:53.820360 [ANA_INIT] MIDPI >>>>>>>>
2204 10:00:53.823483 [ANA_INIT] MIDPI <<<<<<<<
2205 10:00:53.826729 [ANA_INIT] DLL >>>>>>>>
2206 10:00:53.829865 [ANA_INIT] DLL <<<<<<<<
2207 10:00:53.829950 [ANA_INIT] flow end
2208 10:00:53.833505 ============ LP4 DIFF to SE enter ============
2209 10:00:53.840177 ============ LP4 DIFF to SE exit ============
2210 10:00:53.840262 [ANA_INIT] <<<<<<<<<<<<<
2211 10:00:53.843459 [Flow] Enable top DCM control >>>>>
2212 10:00:53.846676 [Flow] Enable top DCM control <<<<<
2213 10:00:53.850156 Enable DLL master slave shuffle
2214 10:00:53.856660 ==============================================================
2215 10:00:53.856745 Gating Mode config
2216 10:00:53.863273 ==============================================================
2217 10:00:53.866794 Config description:
2218 10:00:53.873566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 10:00:53.880066 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 10:00:53.886464 SELPH_MODE 0: By rank 1: By Phase
2221 10:00:53.893058 ==============================================================
2222 10:00:53.893143 GAT_TRACK_EN = 1
2223 10:00:53.896554 RX_GATING_MODE = 2
2224 10:00:53.899947 RX_GATING_TRACK_MODE = 2
2225 10:00:53.902948 SELPH_MODE = 1
2226 10:00:53.906398 PICG_EARLY_EN = 1
2227 10:00:53.910172 VALID_LAT_VALUE = 1
2228 10:00:53.916681 ==============================================================
2229 10:00:53.920063 Enter into Gating configuration >>>>
2230 10:00:53.923272 Exit from Gating configuration <<<<
2231 10:00:53.926554 Enter into DVFS_PRE_config >>>>>
2232 10:00:53.936585 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 10:00:53.939669 Exit from DVFS_PRE_config <<<<<
2234 10:00:53.942972 Enter into PICG configuration >>>>
2235 10:00:53.946296 Exit from PICG configuration <<<<
2236 10:00:53.949745 [RX_INPUT] configuration >>>>>
2237 10:00:53.952782 [RX_INPUT] configuration <<<<<
2238 10:00:53.956078 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 10:00:53.962738 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 10:00:53.969352 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 10:00:53.973008 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 10:00:53.979355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 10:00:53.986147 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 10:00:53.989314 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 10:00:53.992608 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 10:00:53.999139 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 10:00:54.002438 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 10:00:54.006010 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 10:00:54.012894 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 10:00:54.016009 ===================================
2251 10:00:54.016095 LPDDR4 DRAM CONFIGURATION
2252 10:00:54.019189 ===================================
2253 10:00:54.022504 EX_ROW_EN[0] = 0x0
2254 10:00:54.025890 EX_ROW_EN[1] = 0x0
2255 10:00:54.025974 LP4Y_EN = 0x0
2256 10:00:54.029075 WORK_FSP = 0x0
2257 10:00:54.029159 WL = 0x4
2258 10:00:54.032170 RL = 0x4
2259 10:00:54.032254 BL = 0x2
2260 10:00:54.036237 RPST = 0x0
2261 10:00:54.036321 RD_PRE = 0x0
2262 10:00:54.038936 WR_PRE = 0x1
2263 10:00:54.039019 WR_PST = 0x0
2264 10:00:54.042186 DBI_WR = 0x0
2265 10:00:54.042270 DBI_RD = 0x0
2266 10:00:54.045914 OTF = 0x1
2267 10:00:54.048758 ===================================
2268 10:00:54.052574 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 10:00:54.055777 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 10:00:54.062460 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 10:00:54.065916 ===================================
2272 10:00:54.066001 LPDDR4 DRAM CONFIGURATION
2273 10:00:54.068948 ===================================
2274 10:00:54.072185 EX_ROW_EN[0] = 0x10
2275 10:00:54.072269 EX_ROW_EN[1] = 0x0
2276 10:00:54.075839 LP4Y_EN = 0x0
2277 10:00:54.078711 WORK_FSP = 0x0
2278 10:00:54.078796 WL = 0x4
2279 10:00:54.082152 RL = 0x4
2280 10:00:54.082237 BL = 0x2
2281 10:00:54.085681 RPST = 0x0
2282 10:00:54.085765 RD_PRE = 0x0
2283 10:00:54.088847 WR_PRE = 0x1
2284 10:00:54.088931 WR_PST = 0x0
2285 10:00:54.092606 DBI_WR = 0x0
2286 10:00:54.092690 DBI_RD = 0x0
2287 10:00:54.095743 OTF = 0x1
2288 10:00:54.099150 ===================================
2289 10:00:54.102645 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 10:00:54.105995 ==
2291 10:00:54.109105 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 10:00:54.112155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 10:00:54.112229 ==
2294 10:00:54.115571 [Duty_Offset_Calibration]
2295 10:00:54.115638 B0:2 B1:0 CA:4
2296 10:00:54.115699
2297 10:00:54.118887 [DutyScan_Calibration_Flow] k_type=0
2298 10:00:54.127908
2299 10:00:54.127990 ==CLK 0==
2300 10:00:54.130981 Final CLK duty delay cell = -4
2301 10:00:54.134615 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2302 10:00:54.137465 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2303 10:00:54.141571 [-4] AVG Duty = 4937%(X100)
2304 10:00:54.141650
2305 10:00:54.144451 CH0 CLK Duty spec in!! Max-Min= 187%
2306 10:00:54.147566 [DutyScan_Calibration_Flow] ====Done====
2307 10:00:54.147649
2308 10:00:54.150723 [DutyScan_Calibration_Flow] k_type=1
2309 10:00:54.167439
2310 10:00:54.167524 ==DQS 0 ==
2311 10:00:54.170671 Final DQS duty delay cell = 0
2312 10:00:54.174241 [0] MAX Duty = 5156%(X100), DQS PI = 18
2313 10:00:54.177084 [0] MIN Duty = 5093%(X100), DQS PI = 2
2314 10:00:54.180827 [0] AVG Duty = 5124%(X100)
2315 10:00:54.180910
2316 10:00:54.180974 ==DQS 1 ==
2317 10:00:54.183869 Final DQS duty delay cell = 0
2318 10:00:54.187364 [0] MAX Duty = 5125%(X100), DQS PI = 4
2319 10:00:54.190583 [0] MIN Duty = 5000%(X100), DQS PI = 0
2320 10:00:54.190681 [0] AVG Duty = 5062%(X100)
2321 10:00:54.193889
2322 10:00:54.197305 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2323 10:00:54.197387
2324 10:00:54.200338 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2325 10:00:54.203582 [DutyScan_Calibration_Flow] ====Done====
2326 10:00:54.203662
2327 10:00:54.206890 [DutyScan_Calibration_Flow] k_type=3
2328 10:00:54.223521
2329 10:00:54.223601 ==DQM 0 ==
2330 10:00:54.226861 Final DQM duty delay cell = 0
2331 10:00:54.230017 [0] MAX Duty = 5125%(X100), DQS PI = 20
2332 10:00:54.233418 [0] MIN Duty = 4844%(X100), DQS PI = 52
2333 10:00:54.236745 [0] AVG Duty = 4984%(X100)
2334 10:00:54.236825
2335 10:00:54.236888 ==DQM 1 ==
2336 10:00:54.240119 Final DQM duty delay cell = 0
2337 10:00:54.243880 [0] MAX Duty = 4969%(X100), DQS PI = 0
2338 10:00:54.246628 [0] MIN Duty = 4875%(X100), DQS PI = 20
2339 10:00:54.249891 [0] AVG Duty = 4922%(X100)
2340 10:00:54.249963
2341 10:00:54.253786 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2342 10:00:54.253867
2343 10:00:54.256635 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2344 10:00:54.260429 [DutyScan_Calibration_Flow] ====Done====
2345 10:00:54.260510
2346 10:00:54.263394 [DutyScan_Calibration_Flow] k_type=2
2347 10:00:54.280009
2348 10:00:54.280089 ==DQ 0 ==
2349 10:00:54.283269 Final DQ duty delay cell = 0
2350 10:00:54.286381 [0] MAX Duty = 5125%(X100), DQS PI = 18
2351 10:00:54.289993 [0] MIN Duty = 4938%(X100), DQS PI = 58
2352 10:00:54.290073 [0] AVG Duty = 5031%(X100)
2353 10:00:54.293116
2354 10:00:54.293196 ==DQ 1 ==
2355 10:00:54.296943 Final DQ duty delay cell = 0
2356 10:00:54.300093 [0] MAX Duty = 5156%(X100), DQS PI = 4
2357 10:00:54.303142 [0] MIN Duty = 4938%(X100), DQS PI = 16
2358 10:00:54.303223 [0] AVG Duty = 5047%(X100)
2359 10:00:54.303288
2360 10:00:54.306655 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2361 10:00:54.309869
2362 10:00:54.313802 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2363 10:00:54.316455 [DutyScan_Calibration_Flow] ====Done====
2364 10:00:54.316535 ==
2365 10:00:54.319820 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 10:00:54.323389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 10:00:54.323472 ==
2368 10:00:54.326385 [Duty_Offset_Calibration]
2369 10:00:54.326465 B0:0 B1:-1 CA:3
2370 10:00:54.326531
2371 10:00:54.330002 [DutyScan_Calibration_Flow] k_type=0
2372 10:00:54.339315
2373 10:00:54.339395 ==CLK 0==
2374 10:00:54.343182 Final CLK duty delay cell = -4
2375 10:00:54.346395 [-4] MAX Duty = 5031%(X100), DQS PI = 44
2376 10:00:54.349007 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2377 10:00:54.352415 [-4] AVG Duty = 4953%(X100)
2378 10:00:54.352496
2379 10:00:54.355475 CH1 CLK Duty spec in!! Max-Min= 155%
2380 10:00:54.359052 [DutyScan_Calibration_Flow] ====Done====
2381 10:00:54.359134
2382 10:00:54.362184 [DutyScan_Calibration_Flow] k_type=1
2383 10:00:54.378382
2384 10:00:54.378463 ==DQS 0 ==
2385 10:00:54.381381 Final DQS duty delay cell = 0
2386 10:00:54.385057 [0] MAX Duty = 5187%(X100), DQS PI = 28
2387 10:00:54.388009 [0] MIN Duty = 4907%(X100), DQS PI = 38
2388 10:00:54.388091 [0] AVG Duty = 5047%(X100)
2389 10:00:54.391195
2390 10:00:54.391268 ==DQS 1 ==
2391 10:00:54.394903 Final DQS duty delay cell = -4
2392 10:00:54.398000 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2393 10:00:54.401701 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2394 10:00:54.404949 [-4] AVG Duty = 4937%(X100)
2395 10:00:54.405030
2396 10:00:54.408123 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2397 10:00:54.408204
2398 10:00:54.411019 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2399 10:00:54.414732 [DutyScan_Calibration_Flow] ====Done====
2400 10:00:54.414813
2401 10:00:54.417823 [DutyScan_Calibration_Flow] k_type=3
2402 10:00:54.434770
2403 10:00:54.434850 ==DQM 0 ==
2404 10:00:54.438147 Final DQM duty delay cell = 0
2405 10:00:54.441378 [0] MAX Duty = 5031%(X100), DQS PI = 26
2406 10:00:54.444470 [0] MIN Duty = 4813%(X100), DQS PI = 38
2407 10:00:54.448282 [0] AVG Duty = 4922%(X100)
2408 10:00:54.448362
2409 10:00:54.448427 ==DQM 1 ==
2410 10:00:54.451745 Final DQM duty delay cell = 0
2411 10:00:54.454848 [0] MAX Duty = 5000%(X100), DQS PI = 34
2412 10:00:54.458014 [0] MIN Duty = 4844%(X100), DQS PI = 0
2413 10:00:54.461460 [0] AVG Duty = 4922%(X100)
2414 10:00:54.461541
2415 10:00:54.464498 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2416 10:00:54.464580
2417 10:00:54.467631 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2418 10:00:54.471263 [DutyScan_Calibration_Flow] ====Done====
2419 10:00:54.471345
2420 10:00:54.474472 [DutyScan_Calibration_Flow] k_type=2
2421 10:00:54.490675
2422 10:00:54.490757 ==DQ 0 ==
2423 10:00:54.493997 Final DQ duty delay cell = -4
2424 10:00:54.497244 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2425 10:00:54.500698 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2426 10:00:54.504231 [-4] AVG Duty = 4937%(X100)
2427 10:00:54.504313
2428 10:00:54.504378 ==DQ 1 ==
2429 10:00:54.506816 Final DQ duty delay cell = 0
2430 10:00:54.510632 [0] MAX Duty = 5031%(X100), DQS PI = 34
2431 10:00:54.513427 [0] MIN Duty = 4844%(X100), DQS PI = 62
2432 10:00:54.517230 [0] AVG Duty = 4937%(X100)
2433 10:00:54.517311
2434 10:00:54.520284 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2435 10:00:54.520365
2436 10:00:54.523937 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2437 10:00:54.527087 [DutyScan_Calibration_Flow] ====Done====
2438 10:00:54.530097 nWR fixed to 30
2439 10:00:54.533271 [ModeRegInit_LP4] CH0 RK0
2440 10:00:54.533347 [ModeRegInit_LP4] CH0 RK1
2441 10:00:54.536760 [ModeRegInit_LP4] CH1 RK0
2442 10:00:54.540009 [ModeRegInit_LP4] CH1 RK1
2443 10:00:54.540085 match AC timing 7
2444 10:00:54.546661 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 10:00:54.550243 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 10:00:54.553487 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 10:00:54.559694 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 10:00:54.563131 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 10:00:54.563205 ==
2450 10:00:54.566497 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 10:00:54.569740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 10:00:54.569811 ==
2453 10:00:54.576333 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 10:00:54.583063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2455 10:00:54.590614 [CA 0] Center 39 (9~70) winsize 62
2456 10:00:54.594356 [CA 1] Center 39 (9~69) winsize 61
2457 10:00:54.597187 [CA 2] Center 35 (5~66) winsize 62
2458 10:00:54.600815 [CA 3] Center 35 (5~66) winsize 62
2459 10:00:54.604310 [CA 4] Center 33 (3~64) winsize 62
2460 10:00:54.607529 [CA 5] Center 33 (3~64) winsize 62
2461 10:00:54.607610
2462 10:00:54.610421 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2463 10:00:54.610502
2464 10:00:54.614241 [CATrainingPosCal] consider 1 rank data
2465 10:00:54.617142 u2DelayCellTimex100 = 270/100 ps
2466 10:00:54.620413 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2467 10:00:54.626930 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2468 10:00:54.630852 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2469 10:00:54.633672 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2470 10:00:54.636925 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2471 10:00:54.640226 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2472 10:00:54.640307
2473 10:00:54.643621 CA PerBit enable=1, Macro0, CA PI delay=33
2474 10:00:54.643702
2475 10:00:54.647131 [CBTSetCACLKResult] CA Dly = 33
2476 10:00:54.650451 CS Dly: 7 (0~38)
2477 10:00:54.650532 ==
2478 10:00:54.653858 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 10:00:54.657110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 10:00:54.657192 ==
2481 10:00:54.663276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 10:00:54.667301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2483 10:00:54.676395 [CA 0] Center 39 (9~70) winsize 62
2484 10:00:54.679841 [CA 1] Center 39 (9~70) winsize 62
2485 10:00:54.683410 [CA 2] Center 35 (5~66) winsize 62
2486 10:00:54.686813 [CA 3] Center 35 (5~66) winsize 62
2487 10:00:54.689582 [CA 4] Center 34 (3~65) winsize 63
2488 10:00:54.692906 [CA 5] Center 33 (3~63) winsize 61
2489 10:00:54.692987
2490 10:00:54.696286 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 10:00:54.696394
2492 10:00:54.699774 [CATrainingPosCal] consider 2 rank data
2493 10:00:54.703107 u2DelayCellTimex100 = 270/100 ps
2494 10:00:54.706388 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2495 10:00:54.712666 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2496 10:00:54.716294 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 10:00:54.719671 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 10:00:54.722721 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2499 10:00:54.726392 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 10:00:54.726473
2501 10:00:54.729383 CA PerBit enable=1, Macro0, CA PI delay=33
2502 10:00:54.729463
2503 10:00:54.732636 [CBTSetCACLKResult] CA Dly = 33
2504 10:00:54.736156 CS Dly: 8 (0~41)
2505 10:00:54.736236
2506 10:00:54.740037 ----->DramcWriteLeveling(PI) begin...
2507 10:00:54.740119 ==
2508 10:00:54.742635 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 10:00:54.745751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 10:00:54.745837 ==
2511 10:00:54.749225 Write leveling (Byte 0): 33 => 33
2512 10:00:54.752780 Write leveling (Byte 1): 27 => 27
2513 10:00:54.755928 DramcWriteLeveling(PI) end<-----
2514 10:00:54.756026
2515 10:00:54.756090 ==
2516 10:00:54.759265 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 10:00:54.762688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 10:00:54.762770 ==
2519 10:00:54.765615 [Gating] SW mode calibration
2520 10:00:54.773018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 10:00:54.779239 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 10:00:54.782806 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2523 10:00:54.785669 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2524 10:00:54.792825 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 10:00:54.795546 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 10:00:54.798979 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 10:00:54.805631 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 10:00:54.808736 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2529 10:00:54.812218 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
2530 10:00:54.818929 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2531 10:00:54.821984 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2532 10:00:54.825512 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 10:00:54.832101 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 10:00:54.835808 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 10:00:54.838796 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 10:00:54.845399 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
2537 10:00:54.848554 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2538 10:00:54.851972 1 1 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2539 10:00:54.858722 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2540 10:00:54.861535 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 10:00:54.865147 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 10:00:54.871552 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 10:00:54.874941 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 10:00:54.878336 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2545 10:00:54.884895 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 10:00:54.888248 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 10:00:54.891556 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 10:00:54.895524 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 10:00:54.901706 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 10:00:54.905090 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 10:00:54.908196 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 10:00:54.915055 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 10:00:54.917858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 10:00:54.921224 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 10:00:54.928424 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:00:54.931175 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:00:54.934601 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 10:00:54.941462 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 10:00:54.944842 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 10:00:54.948005 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:00:54.954600 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 10:00:54.957995 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2563 10:00:54.961735 Total UI for P1: 0, mck2ui 16
2564 10:00:54.964558 best dqsien dly found for B0: ( 1, 3, 28)
2565 10:00:54.968286 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 10:00:54.971047 Total UI for P1: 0, mck2ui 16
2567 10:00:54.974557 best dqsien dly found for B1: ( 1, 4, 0)
2568 10:00:54.977942 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2569 10:00:54.982032 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2570 10:00:54.982135
2571 10:00:54.987742 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2572 10:00:54.991120 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2573 10:00:54.991202 [Gating] SW calibration Done
2574 10:00:54.994952 ==
2575 10:00:54.998623 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 10:00:55.001326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 10:00:55.001408 ==
2578 10:00:55.001473 RX Vref Scan: 0
2579 10:00:55.001534
2580 10:00:55.004581 RX Vref 0 -> 0, step: 1
2581 10:00:55.004661
2582 10:00:55.008084 RX Delay -40 -> 252, step: 8
2583 10:00:55.011283 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2584 10:00:55.014323 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2585 10:00:55.017863 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2586 10:00:55.024621 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2587 10:00:55.027872 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2588 10:00:55.031486 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2589 10:00:55.034809 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2590 10:00:55.037545 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2591 10:00:55.044542 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2592 10:00:55.047664 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2593 10:00:55.050822 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2594 10:00:55.054748 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2595 10:00:55.058111 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2596 10:00:55.064144 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2597 10:00:55.067531 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2598 10:00:55.070915 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2599 10:00:55.070996 ==
2600 10:00:55.074066 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 10:00:55.077536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 10:00:55.080737 ==
2603 10:00:55.080818 DQS Delay:
2604 10:00:55.080882 DQS0 = 0, DQS1 = 0
2605 10:00:55.084283 DQM Delay:
2606 10:00:55.084364 DQM0 = 118, DQM1 = 108
2607 10:00:55.087241 DQ Delay:
2608 10:00:55.090658 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2609 10:00:55.094052 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2610 10:00:55.097479 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2611 10:00:55.101093 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2612 10:00:55.101174
2613 10:00:55.101238
2614 10:00:55.101297 ==
2615 10:00:55.104036 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 10:00:55.107723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 10:00:55.107804 ==
2618 10:00:55.107868
2619 10:00:55.107960
2620 10:00:55.110561 TX Vref Scan disable
2621 10:00:55.113862 == TX Byte 0 ==
2622 10:00:55.117466 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2623 10:00:55.120924 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2624 10:00:55.124099 == TX Byte 1 ==
2625 10:00:55.127347 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2626 10:00:55.130691 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2627 10:00:55.130773 ==
2628 10:00:55.133977 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 10:00:55.137295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 10:00:55.140630 ==
2631 10:00:55.151092 TX Vref=22, minBit 1, minWin=25, winSum=411
2632 10:00:55.154355 TX Vref=24, minBit 8, minWin=25, winSum=419
2633 10:00:55.157861 TX Vref=26, minBit 10, minWin=25, winSum=428
2634 10:00:55.161106 TX Vref=28, minBit 5, minWin=26, winSum=428
2635 10:00:55.164378 TX Vref=30, minBit 5, minWin=26, winSum=431
2636 10:00:55.171317 TX Vref=32, minBit 5, minWin=26, winSum=431
2637 10:00:55.174574 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 30
2638 10:00:55.174649
2639 10:00:55.177753 Final TX Range 1 Vref 30
2640 10:00:55.177830
2641 10:00:55.177894 ==
2642 10:00:55.181340 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 10:00:55.184821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 10:00:55.187425 ==
2645 10:00:55.187496
2646 10:00:55.187556
2647 10:00:55.187618 TX Vref Scan disable
2648 10:00:55.191373 == TX Byte 0 ==
2649 10:00:55.194600 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2650 10:00:55.201084 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2651 10:00:55.201163 == TX Byte 1 ==
2652 10:00:55.204423 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2653 10:00:55.211020 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2654 10:00:55.211101
2655 10:00:55.211166 [DATLAT]
2656 10:00:55.211226 Freq=1200, CH0 RK0
2657 10:00:55.211282
2658 10:00:55.214636 DATLAT Default: 0xd
2659 10:00:55.214707 0, 0xFFFF, sum = 0
2660 10:00:55.217956 1, 0xFFFF, sum = 0
2661 10:00:55.218056 2, 0xFFFF, sum = 0
2662 10:00:55.220816 3, 0xFFFF, sum = 0
2663 10:00:55.224662 4, 0xFFFF, sum = 0
2664 10:00:55.224739 5, 0xFFFF, sum = 0
2665 10:00:55.227371 6, 0xFFFF, sum = 0
2666 10:00:55.227469 7, 0xFFFF, sum = 0
2667 10:00:55.231108 8, 0xFFFF, sum = 0
2668 10:00:55.231185 9, 0xFFFF, sum = 0
2669 10:00:55.234159 10, 0xFFFF, sum = 0
2670 10:00:55.234235 11, 0xFFFF, sum = 0
2671 10:00:55.237749 12, 0x0, sum = 1
2672 10:00:55.237822 13, 0x0, sum = 2
2673 10:00:55.241174 14, 0x0, sum = 3
2674 10:00:55.241247 15, 0x0, sum = 4
2675 10:00:55.244074 best_step = 13
2676 10:00:55.244155
2677 10:00:55.244221 ==
2678 10:00:55.247784 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 10:00:55.250801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 10:00:55.250873 ==
2681 10:00:55.250934 RX Vref Scan: 1
2682 10:00:55.250992
2683 10:00:55.254098 Set Vref Range= 32 -> 127
2684 10:00:55.254178
2685 10:00:55.257774 RX Vref 32 -> 127, step: 1
2686 10:00:55.257855
2687 10:00:55.260994 RX Delay -21 -> 252, step: 4
2688 10:00:55.261075
2689 10:00:55.264313 Set Vref, RX VrefLevel [Byte0]: 32
2690 10:00:55.267573 [Byte1]: 32
2691 10:00:55.267654
2692 10:00:55.270659 Set Vref, RX VrefLevel [Byte0]: 33
2693 10:00:55.273914 [Byte1]: 33
2694 10:00:55.277781
2695 10:00:55.277862 Set Vref, RX VrefLevel [Byte0]: 34
2696 10:00:55.281225 [Byte1]: 34
2697 10:00:55.285471
2698 10:00:55.285552 Set Vref, RX VrefLevel [Byte0]: 35
2699 10:00:55.288727 [Byte1]: 35
2700 10:00:55.293864
2701 10:00:55.293945 Set Vref, RX VrefLevel [Byte0]: 36
2702 10:00:55.296988 [Byte1]: 36
2703 10:00:55.301398
2704 10:00:55.301479 Set Vref, RX VrefLevel [Byte0]: 37
2705 10:00:55.304691 [Byte1]: 37
2706 10:00:55.309224
2707 10:00:55.309305 Set Vref, RX VrefLevel [Byte0]: 38
2708 10:00:55.312487 [Byte1]: 38
2709 10:00:55.317345
2710 10:00:55.317425 Set Vref, RX VrefLevel [Byte0]: 39
2711 10:00:55.320623 [Byte1]: 39
2712 10:00:55.324940
2713 10:00:55.325020 Set Vref, RX VrefLevel [Byte0]: 40
2714 10:00:55.328487 [Byte1]: 40
2715 10:00:55.332819
2716 10:00:55.332903 Set Vref, RX VrefLevel [Byte0]: 41
2717 10:00:55.336221 [Byte1]: 41
2718 10:00:55.341213
2719 10:00:55.341294 Set Vref, RX VrefLevel [Byte0]: 42
2720 10:00:55.344240 [Byte1]: 42
2721 10:00:55.349218
2722 10:00:55.349298 Set Vref, RX VrefLevel [Byte0]: 43
2723 10:00:55.352041 [Byte1]: 43
2724 10:00:55.357101
2725 10:00:55.357181 Set Vref, RX VrefLevel [Byte0]: 44
2726 10:00:55.360112 [Byte1]: 44
2727 10:00:55.365283
2728 10:00:55.365364 Set Vref, RX VrefLevel [Byte0]: 45
2729 10:00:55.371198 [Byte1]: 45
2730 10:00:55.371279
2731 10:00:55.374497 Set Vref, RX VrefLevel [Byte0]: 46
2732 10:00:55.377983 [Byte1]: 46
2733 10:00:55.378063
2734 10:00:55.380969 Set Vref, RX VrefLevel [Byte0]: 47
2735 10:00:55.384184 [Byte1]: 47
2736 10:00:55.388598
2737 10:00:55.388679 Set Vref, RX VrefLevel [Byte0]: 48
2738 10:00:55.391628 [Byte1]: 48
2739 10:00:55.396385
2740 10:00:55.396465 Set Vref, RX VrefLevel [Byte0]: 49
2741 10:00:55.400480 [Byte1]: 49
2742 10:00:55.404347
2743 10:00:55.404427 Set Vref, RX VrefLevel [Byte0]: 50
2744 10:00:55.407659 [Byte1]: 50
2745 10:00:55.412654
2746 10:00:55.412734 Set Vref, RX VrefLevel [Byte0]: 51
2747 10:00:55.415892 [Byte1]: 51
2748 10:00:55.420249
2749 10:00:55.420336 Set Vref, RX VrefLevel [Byte0]: 52
2750 10:00:55.423682 [Byte1]: 52
2751 10:00:55.428213
2752 10:00:55.428295 Set Vref, RX VrefLevel [Byte0]: 53
2753 10:00:55.431538 [Byte1]: 53
2754 10:00:55.436327
2755 10:00:55.436399 Set Vref, RX VrefLevel [Byte0]: 54
2756 10:00:55.439720 [Byte1]: 54
2757 10:00:55.444075
2758 10:00:55.444156 Set Vref, RX VrefLevel [Byte0]: 55
2759 10:00:55.447521 [Byte1]: 55
2760 10:00:55.451901
2761 10:00:55.451982 Set Vref, RX VrefLevel [Byte0]: 56
2762 10:00:55.455365 [Byte1]: 56
2763 10:00:55.460359
2764 10:00:55.460431 Set Vref, RX VrefLevel [Byte0]: 57
2765 10:00:55.463242 [Byte1]: 57
2766 10:00:55.467848
2767 10:00:55.467977 Set Vref, RX VrefLevel [Byte0]: 58
2768 10:00:55.470976 [Byte1]: 58
2769 10:00:55.475814
2770 10:00:55.475927 Set Vref, RX VrefLevel [Byte0]: 59
2771 10:00:55.479151 [Byte1]: 59
2772 10:00:55.483641
2773 10:00:55.483743 Set Vref, RX VrefLevel [Byte0]: 60
2774 10:00:55.486863 [Byte1]: 60
2775 10:00:55.491363
2776 10:00:55.491441 Set Vref, RX VrefLevel [Byte0]: 61
2777 10:00:55.495161 [Byte1]: 61
2778 10:00:55.499269
2779 10:00:55.499345 Set Vref, RX VrefLevel [Byte0]: 62
2780 10:00:55.502911 [Byte1]: 62
2781 10:00:55.507443
2782 10:00:55.507521 Set Vref, RX VrefLevel [Byte0]: 63
2783 10:00:55.510602 [Byte1]: 63
2784 10:00:55.515517
2785 10:00:55.515618 Set Vref, RX VrefLevel [Byte0]: 64
2786 10:00:55.518720 [Byte1]: 64
2787 10:00:55.523234
2788 10:00:55.523310 Set Vref, RX VrefLevel [Byte0]: 65
2789 10:00:55.526529 [Byte1]: 65
2790 10:00:55.531224
2791 10:00:55.531298 Set Vref, RX VrefLevel [Byte0]: 66
2792 10:00:55.534233 [Byte1]: 66
2793 10:00:55.538863
2794 10:00:55.538940 Set Vref, RX VrefLevel [Byte0]: 67
2795 10:00:55.542304 [Byte1]: 67
2796 10:00:55.547057
2797 10:00:55.547132 Set Vref, RX VrefLevel [Byte0]: 68
2798 10:00:55.550172 [Byte1]: 68
2799 10:00:55.554740
2800 10:00:55.554840 Set Vref, RX VrefLevel [Byte0]: 69
2801 10:00:55.558336 [Byte1]: 69
2802 10:00:55.563150
2803 10:00:55.563224 Final RX Vref Byte 0 = 57 to rank0
2804 10:00:55.565995 Final RX Vref Byte 1 = 59 to rank0
2805 10:00:55.569775 Final RX Vref Byte 0 = 57 to rank1
2806 10:00:55.572617 Final RX Vref Byte 1 = 59 to rank1==
2807 10:00:55.576237 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 10:00:55.582600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 10:00:55.582703 ==
2810 10:00:55.582795 DQS Delay:
2811 10:00:55.582887 DQS0 = 0, DQS1 = 0
2812 10:00:55.585980 DQM Delay:
2813 10:00:55.586051 DQM0 = 117, DQM1 = 105
2814 10:00:55.589140 DQ Delay:
2815 10:00:55.592569 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =112
2816 10:00:55.596193 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =120
2817 10:00:55.599604 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2818 10:00:55.602954 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2819 10:00:55.603035
2820 10:00:55.603100
2821 10:00:55.609203 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2822 10:00:55.612600 CH0 RK0: MR19=403, MR18=1FC
2823 10:00:55.619117 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2824 10:00:55.619199
2825 10:00:55.622539 ----->DramcWriteLeveling(PI) begin...
2826 10:00:55.622621 ==
2827 10:00:55.625692 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 10:00:55.629396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 10:00:55.632668 ==
2830 10:00:55.632749 Write leveling (Byte 0): 32 => 32
2831 10:00:55.635814 Write leveling (Byte 1): 26 => 26
2832 10:00:55.639250 DramcWriteLeveling(PI) end<-----
2833 10:00:55.639331
2834 10:00:55.639395 ==
2835 10:00:55.642528 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 10:00:55.649286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 10:00:55.649371 ==
2838 10:00:55.649436 [Gating] SW mode calibration
2839 10:00:55.658815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 10:00:55.662545 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 10:00:55.669146 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2842 10:00:55.672436 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2843 10:00:55.675780 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 10:00:55.679062 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 10:00:55.685434 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 10:00:55.688917 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 10:00:55.692524 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2848 10:00:55.699157 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
2849 10:00:55.702266 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2850 10:00:55.705769 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2851 10:00:55.712368 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 10:00:55.715827 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 10:00:55.719093 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 10:00:55.725704 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 10:00:55.729076 1 0 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2856 10:00:55.732425 1 0 28 | B1->B0 | 2827 4646 | 1 0 | (0 0) (0 0)
2857 10:00:55.738895 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2858 10:00:55.742434 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 10:00:55.745186 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 10:00:55.752043 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 10:00:55.755271 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 10:00:55.758565 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 10:00:55.765329 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 10:00:55.768540 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2865 10:00:55.771841 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2866 10:00:55.778658 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 10:00:55.782446 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 10:00:55.785272 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 10:00:55.792067 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 10:00:55.795228 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 10:00:55.798484 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 10:00:55.802310 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 10:00:55.808550 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 10:00:55.812162 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 10:00:55.815356 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 10:00:55.822163 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 10:00:55.825517 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 10:00:55.828369 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 10:00:55.835042 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2880 10:00:55.838581 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2881 10:00:55.841977 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2882 10:00:55.845233 Total UI for P1: 0, mck2ui 16
2883 10:00:55.848587 best dqsien dly found for B0: ( 1, 3, 26)
2884 10:00:55.855222 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 10:00:55.855297 Total UI for P1: 0, mck2ui 16
2886 10:00:55.861657 best dqsien dly found for B1: ( 1, 4, 0)
2887 10:00:55.865069 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2888 10:00:55.868683 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2889 10:00:55.868784
2890 10:00:55.871981 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2891 10:00:55.875186 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2892 10:00:55.878224 [Gating] SW calibration Done
2893 10:00:55.878300 ==
2894 10:00:55.881444 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 10:00:55.885032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 10:00:55.885115 ==
2897 10:00:55.888334 RX Vref Scan: 0
2898 10:00:55.888410
2899 10:00:55.888474 RX Vref 0 -> 0, step: 1
2900 10:00:55.888533
2901 10:00:55.891824 RX Delay -40 -> 252, step: 8
2902 10:00:55.895102 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2903 10:00:55.901615 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2904 10:00:55.905078 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2905 10:00:55.908658 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2906 10:00:55.911568 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2907 10:00:55.915022 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2908 10:00:55.921825 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2909 10:00:55.925646 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2910 10:00:55.928036 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2911 10:00:55.931353 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2912 10:00:55.935154 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2913 10:00:55.938318 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2914 10:00:55.944819 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2915 10:00:55.948503 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2916 10:00:55.951740 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2917 10:00:55.954785 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2918 10:00:55.958194 ==
2919 10:00:55.958270 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 10:00:55.965282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 10:00:55.965357 ==
2922 10:00:55.965420 DQS Delay:
2923 10:00:55.968304 DQS0 = 0, DQS1 = 0
2924 10:00:55.968375 DQM Delay:
2925 10:00:55.971855 DQM0 = 116, DQM1 = 109
2926 10:00:55.972001 DQ Delay:
2927 10:00:55.974568 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2928 10:00:55.978258 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2929 10:00:55.981599 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2930 10:00:55.984687 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2931 10:00:55.984761
2932 10:00:55.984824
2933 10:00:55.984887 ==
2934 10:00:55.988289 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 10:00:55.994763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 10:00:55.994843 ==
2937 10:00:55.994906
2938 10:00:55.994968
2939 10:00:55.995026 TX Vref Scan disable
2940 10:00:55.997882 == TX Byte 0 ==
2941 10:00:56.001665 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2942 10:00:56.004661 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2943 10:00:56.008441 == TX Byte 1 ==
2944 10:00:56.011424 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2945 10:00:56.014894 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2946 10:00:56.018133 ==
2947 10:00:56.021684 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 10:00:56.024461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 10:00:56.024542 ==
2950 10:00:56.036292 TX Vref=22, minBit 13, minWin=25, winSum=417
2951 10:00:56.039768 TX Vref=24, minBit 12, minWin=25, winSum=420
2952 10:00:56.043063 TX Vref=26, minBit 10, minWin=25, winSum=425
2953 10:00:56.046307 TX Vref=28, minBit 10, minWin=26, winSum=429
2954 10:00:56.049441 TX Vref=30, minBit 5, minWin=26, winSum=429
2955 10:00:56.056145 TX Vref=32, minBit 2, minWin=26, winSum=424
2956 10:00:56.059776 [TxChooseVref] Worse bit 10, Min win 26, Win sum 429, Final Vref 28
2957 10:00:56.059896
2958 10:00:56.063240 Final TX Range 1 Vref 28
2959 10:00:56.063321
2960 10:00:56.063385 ==
2961 10:00:56.066074 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 10:00:56.069427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 10:00:56.072977 ==
2964 10:00:56.073057
2965 10:00:56.073121
2966 10:00:56.073180 TX Vref Scan disable
2967 10:00:56.076915 == TX Byte 0 ==
2968 10:00:56.079714 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2969 10:00:56.086240 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2970 10:00:56.086322 == TX Byte 1 ==
2971 10:00:56.089872 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2972 10:00:56.096550 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2973 10:00:56.096631
2974 10:00:56.096695 [DATLAT]
2975 10:00:56.096755 Freq=1200, CH0 RK1
2976 10:00:56.096813
2977 10:00:56.100144 DATLAT Default: 0xd
2978 10:00:56.100224 0, 0xFFFF, sum = 0
2979 10:00:56.102909 1, 0xFFFF, sum = 0
2980 10:00:56.106177 2, 0xFFFF, sum = 0
2981 10:00:56.106259 3, 0xFFFF, sum = 0
2982 10:00:56.109634 4, 0xFFFF, sum = 0
2983 10:00:56.109717 5, 0xFFFF, sum = 0
2984 10:00:56.112786 6, 0xFFFF, sum = 0
2985 10:00:56.112867 7, 0xFFFF, sum = 0
2986 10:00:56.116035 8, 0xFFFF, sum = 0
2987 10:00:56.116117 9, 0xFFFF, sum = 0
2988 10:00:56.119578 10, 0xFFFF, sum = 0
2989 10:00:56.119660 11, 0xFFFF, sum = 0
2990 10:00:56.122929 12, 0x0, sum = 1
2991 10:00:56.123011 13, 0x0, sum = 2
2992 10:00:56.126587 14, 0x0, sum = 3
2993 10:00:56.126668 15, 0x0, sum = 4
2994 10:00:56.129857 best_step = 13
2995 10:00:56.129937
2996 10:00:56.130002 ==
2997 10:00:56.133204 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 10:00:56.136380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 10:00:56.136461 ==
3000 10:00:56.136526 RX Vref Scan: 0
3001 10:00:56.136586
3002 10:00:56.139629 RX Vref 0 -> 0, step: 1
3003 10:00:56.139710
3004 10:00:56.142984 RX Delay -21 -> 252, step: 4
3005 10:00:56.146195 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3006 10:00:56.152977 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3007 10:00:56.156101 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3008 10:00:56.159620 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3009 10:00:56.162829 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3010 10:00:56.165934 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3011 10:00:56.172945 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3012 10:00:56.176274 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3013 10:00:56.179560 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3014 10:00:56.182636 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3015 10:00:56.185842 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3016 10:00:56.192317 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3017 10:00:56.196061 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3018 10:00:56.199684 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3019 10:00:56.202605 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3020 10:00:56.205986 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3021 10:00:56.209274 ==
3022 10:00:56.212546 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 10:00:56.216223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 10:00:56.216304 ==
3025 10:00:56.216369 DQS Delay:
3026 10:00:56.219347 DQS0 = 0, DQS1 = 0
3027 10:00:56.219427 DQM Delay:
3028 10:00:56.222642 DQM0 = 116, DQM1 = 106
3029 10:00:56.222743 DQ Delay:
3030 10:00:56.226077 DQ0 =114, DQ1 =118, DQ2 =112, DQ3 =112
3031 10:00:56.229065 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3032 10:00:56.232335 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3033 10:00:56.235522 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =112
3034 10:00:56.235604
3035 10:00:56.235668
3036 10:00:56.245759 [DQSOSCAuto] RK1, (LSB)MR18= 0x200, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3037 10:00:56.245836 CH0 RK1: MR19=404, MR18=200
3038 10:00:56.252616 CH0_RK1: MR19=0x404, MR18=0x200, DQSOSC=409, MR23=63, INC=39, DEC=26
3039 10:00:56.256111 [RxdqsGatingPostProcess] freq 1200
3040 10:00:56.262416 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3041 10:00:56.265728 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 10:00:56.269032 best DQS1 dly(2T, 0.5T) = (0, 12)
3043 10:00:56.272421 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 10:00:56.276157 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3045 10:00:56.279356 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 10:00:56.279437 best DQS1 dly(2T, 0.5T) = (0, 12)
3047 10:00:56.282668 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 10:00:56.285514 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3049 10:00:56.288759 Pre-setting of DQS Precalculation
3050 10:00:56.295488 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3051 10:00:56.295570 ==
3052 10:00:56.298789 Dram Type= 6, Freq= 0, CH_1, rank 0
3053 10:00:56.302328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 10:00:56.302440 ==
3055 10:00:56.309113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3056 10:00:56.315172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3057 10:00:56.322965 [CA 0] Center 38 (8~68) winsize 61
3058 10:00:56.325773 [CA 1] Center 37 (7~68) winsize 62
3059 10:00:56.329599 [CA 2] Center 35 (5~65) winsize 61
3060 10:00:56.332828 [CA 3] Center 34 (4~64) winsize 61
3061 10:00:56.335639 [CA 4] Center 34 (4~65) winsize 62
3062 10:00:56.338925 [CA 5] Center 33 (4~63) winsize 60
3063 10:00:56.339006
3064 10:00:56.342215 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3065 10:00:56.342296
3066 10:00:56.345553 [CATrainingPosCal] consider 1 rank data
3067 10:00:56.348963 u2DelayCellTimex100 = 270/100 ps
3068 10:00:56.352527 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3069 10:00:56.356143 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3070 10:00:56.362618 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3071 10:00:56.365927 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3072 10:00:56.368974 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3073 10:00:56.373557 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3074 10:00:56.373665
3075 10:00:56.375716 CA PerBit enable=1, Macro0, CA PI delay=33
3076 10:00:56.375797
3077 10:00:56.378872 [CBTSetCACLKResult] CA Dly = 33
3078 10:00:56.378953 CS Dly: 5 (0~36)
3079 10:00:56.382035 ==
3080 10:00:56.385641 Dram Type= 6, Freq= 0, CH_1, rank 1
3081 10:00:56.388925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 10:00:56.389006 ==
3083 10:00:56.392213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3084 10:00:56.398875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3085 10:00:56.408038 [CA 0] Center 37 (7~68) winsize 62
3086 10:00:56.411412 [CA 1] Center 38 (7~69) winsize 63
3087 10:00:56.415031 [CA 2] Center 34 (4~65) winsize 62
3088 10:00:56.418027 [CA 3] Center 34 (4~64) winsize 61
3089 10:00:56.421437 [CA 4] Center 34 (4~64) winsize 61
3090 10:00:56.424539 [CA 5] Center 33 (3~63) winsize 61
3091 10:00:56.424647
3092 10:00:56.428093 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3093 10:00:56.428174
3094 10:00:56.431331 [CATrainingPosCal] consider 2 rank data
3095 10:00:56.434807 u2DelayCellTimex100 = 270/100 ps
3096 10:00:56.437946 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3097 10:00:56.445336 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3098 10:00:56.448202 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3099 10:00:56.451568 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 10:00:56.454765 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3101 10:00:56.457878 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3102 10:00:56.457959
3103 10:00:56.461677 CA PerBit enable=1, Macro0, CA PI delay=33
3104 10:00:56.461758
3105 10:00:56.464998 [CBTSetCACLKResult] CA Dly = 33
3106 10:00:56.465090 CS Dly: 6 (0~39)
3107 10:00:56.465182
3108 10:00:56.467790 ----->DramcWriteLeveling(PI) begin...
3109 10:00:56.471139 ==
3110 10:00:56.475160 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 10:00:56.478146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 10:00:56.478227 ==
3113 10:00:56.481513 Write leveling (Byte 0): 26 => 26
3114 10:00:56.484827 Write leveling (Byte 1): 27 => 27
3115 10:00:56.488106 DramcWriteLeveling(PI) end<-----
3116 10:00:56.488187
3117 10:00:56.488250 ==
3118 10:00:56.491177 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 10:00:56.494951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 10:00:56.495032 ==
3121 10:00:56.498063 [Gating] SW mode calibration
3122 10:00:56.504532 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3123 10:00:56.510915 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3124 10:00:56.514419 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3125 10:00:56.517588 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 10:00:56.524877 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 10:00:56.528117 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 10:00:56.531395 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 10:00:56.534463 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 10:00:56.541003 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3131 10:00:56.544842 0 15 28 | B1->B0 | 2a2a 2424 | 0 0 | (1 0) (1 0)
3132 10:00:56.547946 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 10:00:56.554402 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 10:00:56.557832 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 10:00:56.561274 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 10:00:56.567723 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 10:00:56.571030 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 10:00:56.574307 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
3139 10:00:56.580910 1 0 28 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
3140 10:00:56.584418 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 10:00:56.587377 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 10:00:56.594053 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 10:00:56.597709 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 10:00:56.601181 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 10:00:56.607486 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 10:00:56.611027 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 10:00:56.614118 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3148 10:00:56.620739 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 10:00:56.624089 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 10:00:56.627342 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 10:00:56.634167 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 10:00:56.637823 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 10:00:56.640630 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 10:00:56.647653 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 10:00:56.650935 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 10:00:56.655020 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 10:00:56.657595 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 10:00:56.664306 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 10:00:56.667574 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 10:00:56.670888 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 10:00:56.677747 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 10:00:56.680635 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3163 10:00:56.683923 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3164 10:00:56.687654 Total UI for P1: 0, mck2ui 16
3165 10:00:56.690658 best dqsien dly found for B0: ( 1, 3, 24)
3166 10:00:56.697459 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 10:00:56.697541 Total UI for P1: 0, mck2ui 16
3168 10:00:56.704187 best dqsien dly found for B1: ( 1, 3, 26)
3169 10:00:56.707280 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3170 10:00:56.710805 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3171 10:00:56.710887
3172 10:00:56.714056 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3173 10:00:56.717062 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3174 10:00:56.720490 [Gating] SW calibration Done
3175 10:00:56.720571 ==
3176 10:00:56.724183 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 10:00:56.727153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 10:00:56.727234 ==
3179 10:00:56.730315 RX Vref Scan: 0
3180 10:00:56.730398
3181 10:00:56.730463 RX Vref 0 -> 0, step: 1
3182 10:00:56.733986
3183 10:00:56.734066 RX Delay -40 -> 252, step: 8
3184 10:00:56.740178 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3185 10:00:56.743811 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3186 10:00:56.747230 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3187 10:00:56.750354 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3188 10:00:56.753820 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3189 10:00:56.759872 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3190 10:00:56.763400 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3191 10:00:56.766906 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3192 10:00:56.769809 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3193 10:00:56.773780 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3194 10:00:56.780107 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3195 10:00:56.783594 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3196 10:00:56.786735 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3197 10:00:56.789800 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3198 10:00:56.793073 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3199 10:00:56.799798 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3200 10:00:56.799879 ==
3201 10:00:56.803324 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 10:00:56.806603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 10:00:56.806685 ==
3204 10:00:56.806750 DQS Delay:
3205 10:00:56.809933 DQS0 = 0, DQS1 = 0
3206 10:00:56.810014 DQM Delay:
3207 10:00:56.813213 DQM0 = 117, DQM1 = 112
3208 10:00:56.813294 DQ Delay:
3209 10:00:56.816217 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3210 10:00:56.819790 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3211 10:00:56.823523 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3212 10:00:56.826217 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3213 10:00:56.826299
3214 10:00:56.829851
3215 10:00:56.829931 ==
3216 10:00:56.833154 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 10:00:56.836633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 10:00:56.836714 ==
3219 10:00:56.836778
3220 10:00:56.836837
3221 10:00:56.839687 TX Vref Scan disable
3222 10:00:56.839767 == TX Byte 0 ==
3223 10:00:56.846750 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3224 10:00:56.849674 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3225 10:00:56.849755 == TX Byte 1 ==
3226 10:00:56.856036 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3227 10:00:56.859629 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3228 10:00:56.859709 ==
3229 10:00:56.862991 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 10:00:56.866366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 10:00:56.866447 ==
3232 10:00:56.878311 TX Vref=22, minBit 2, minWin=25, winSum=408
3233 10:00:56.881380 TX Vref=24, minBit 2, minWin=25, winSum=416
3234 10:00:56.884651 TX Vref=26, minBit 9, minWin=24, winSum=418
3235 10:00:56.888097 TX Vref=28, minBit 9, minWin=25, winSum=426
3236 10:00:56.891534 TX Vref=30, minBit 1, minWin=26, winSum=424
3237 10:00:56.897818 TX Vref=32, minBit 11, minWin=25, winSum=426
3238 10:00:56.901221 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 30
3239 10:00:56.901303
3240 10:00:56.904657 Final TX Range 1 Vref 30
3241 10:00:56.904739
3242 10:00:56.904803 ==
3243 10:00:56.908093 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 10:00:56.911101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 10:00:56.914430 ==
3246 10:00:56.914510
3247 10:00:56.914573
3248 10:00:56.914632 TX Vref Scan disable
3249 10:00:56.918137 == TX Byte 0 ==
3250 10:00:56.921179 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3251 10:00:56.927815 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3252 10:00:56.927926 == TX Byte 1 ==
3253 10:00:56.931122 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3254 10:00:56.934908 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3255 10:00:56.938080
3256 10:00:56.938160 [DATLAT]
3257 10:00:56.938224 Freq=1200, CH1 RK0
3258 10:00:56.938284
3259 10:00:56.941176 DATLAT Default: 0xd
3260 10:00:56.941256 0, 0xFFFF, sum = 0
3261 10:00:56.944505 1, 0xFFFF, sum = 0
3262 10:00:56.944588 2, 0xFFFF, sum = 0
3263 10:00:56.947832 3, 0xFFFF, sum = 0
3264 10:00:56.951141 4, 0xFFFF, sum = 0
3265 10:00:56.951221 5, 0xFFFF, sum = 0
3266 10:00:56.954251 6, 0xFFFF, sum = 0
3267 10:00:56.954333 7, 0xFFFF, sum = 0
3268 10:00:56.957871 8, 0xFFFF, sum = 0
3269 10:00:56.957952 9, 0xFFFF, sum = 0
3270 10:00:56.961398 10, 0xFFFF, sum = 0
3271 10:00:56.961480 11, 0xFFFF, sum = 0
3272 10:00:56.964890 12, 0x0, sum = 1
3273 10:00:56.964971 13, 0x0, sum = 2
3274 10:00:56.967716 14, 0x0, sum = 3
3275 10:00:56.967797 15, 0x0, sum = 4
3276 10:00:56.967862 best_step = 13
3277 10:00:56.971079
3278 10:00:56.971159 ==
3279 10:00:56.974208 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 10:00:56.977814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 10:00:56.977895 ==
3282 10:00:56.977959 RX Vref Scan: 1
3283 10:00:56.978018
3284 10:00:56.980923 Set Vref Range= 32 -> 127
3285 10:00:56.981003
3286 10:00:56.984513 RX Vref 32 -> 127, step: 1
3287 10:00:56.984606
3288 10:00:56.988056 RX Delay -13 -> 252, step: 4
3289 10:00:56.988136
3290 10:00:56.991496 Set Vref, RX VrefLevel [Byte0]: 32
3291 10:00:56.994048 [Byte1]: 32
3292 10:00:56.994129
3293 10:00:56.997978 Set Vref, RX VrefLevel [Byte0]: 33
3294 10:00:57.000592 [Byte1]: 33
3295 10:00:57.004703
3296 10:00:57.004783 Set Vref, RX VrefLevel [Byte0]: 34
3297 10:00:57.007532 [Byte1]: 34
3298 10:00:57.012081
3299 10:00:57.012161 Set Vref, RX VrefLevel [Byte0]: 35
3300 10:00:57.016027 [Byte1]: 35
3301 10:00:57.020301
3302 10:00:57.020380 Set Vref, RX VrefLevel [Byte0]: 36
3303 10:00:57.023678 [Byte1]: 36
3304 10:00:57.028115
3305 10:00:57.028193 Set Vref, RX VrefLevel [Byte0]: 37
3306 10:00:57.031475 [Byte1]: 37
3307 10:00:57.035848
3308 10:00:57.035966 Set Vref, RX VrefLevel [Byte0]: 38
3309 10:00:57.039226 [Byte1]: 38
3310 10:00:57.043710
3311 10:00:57.043790 Set Vref, RX VrefLevel [Byte0]: 39
3312 10:00:57.047081 [Byte1]: 39
3313 10:00:57.051803
3314 10:00:57.051882 Set Vref, RX VrefLevel [Byte0]: 40
3315 10:00:57.054994 [Byte1]: 40
3316 10:00:57.059643
3317 10:00:57.059722 Set Vref, RX VrefLevel [Byte0]: 41
3318 10:00:57.062969 [Byte1]: 41
3319 10:00:57.067582
3320 10:00:57.067660 Set Vref, RX VrefLevel [Byte0]: 42
3321 10:00:57.070809 [Byte1]: 42
3322 10:00:57.075274
3323 10:00:57.075352 Set Vref, RX VrefLevel [Byte0]: 43
3324 10:00:57.078869 [Byte1]: 43
3325 10:00:57.083145
3326 10:00:57.083223 Set Vref, RX VrefLevel [Byte0]: 44
3327 10:00:57.086702 [Byte1]: 44
3328 10:00:57.091377
3329 10:00:57.091455 Set Vref, RX VrefLevel [Byte0]: 45
3330 10:00:57.094687 [Byte1]: 45
3331 10:00:57.099257
3332 10:00:57.099335 Set Vref, RX VrefLevel [Byte0]: 46
3333 10:00:57.102333 [Byte1]: 46
3334 10:00:57.106725
3335 10:00:57.106805 Set Vref, RX VrefLevel [Byte0]: 47
3336 10:00:57.110346 [Byte1]: 47
3337 10:00:57.114838
3338 10:00:57.114920 Set Vref, RX VrefLevel [Byte0]: 48
3339 10:00:57.118128 [Byte1]: 48
3340 10:00:57.122823
3341 10:00:57.122902 Set Vref, RX VrefLevel [Byte0]: 49
3342 10:00:57.125873 [Byte1]: 49
3343 10:00:57.130871
3344 10:00:57.130949 Set Vref, RX VrefLevel [Byte0]: 50
3345 10:00:57.133777 [Byte1]: 50
3346 10:00:57.138627
3347 10:00:57.138706 Set Vref, RX VrefLevel [Byte0]: 51
3348 10:00:57.142113 [Byte1]: 51
3349 10:00:57.146368
3350 10:00:57.146447 Set Vref, RX VrefLevel [Byte0]: 52
3351 10:00:57.149446 [Byte1]: 52
3352 10:00:57.154322
3353 10:00:57.154401 Set Vref, RX VrefLevel [Byte0]: 53
3354 10:00:57.157296 [Byte1]: 53
3355 10:00:57.162247
3356 10:00:57.162325 Set Vref, RX VrefLevel [Byte0]: 54
3357 10:00:57.165391 [Byte1]: 54
3358 10:00:57.169849
3359 10:00:57.169927 Set Vref, RX VrefLevel [Byte0]: 55
3360 10:00:57.173503 [Byte1]: 55
3361 10:00:57.178092
3362 10:00:57.178171 Set Vref, RX VrefLevel [Byte0]: 56
3363 10:00:57.180855 [Byte1]: 56
3364 10:00:57.185620
3365 10:00:57.185699 Set Vref, RX VrefLevel [Byte0]: 57
3366 10:00:57.189312 [Byte1]: 57
3367 10:00:57.193368
3368 10:00:57.193448 Set Vref, RX VrefLevel [Byte0]: 58
3369 10:00:57.197253 [Byte1]: 58
3370 10:00:57.201347
3371 10:00:57.201426 Set Vref, RX VrefLevel [Byte0]: 59
3372 10:00:57.204594 [Byte1]: 59
3373 10:00:57.209121
3374 10:00:57.209204 Set Vref, RX VrefLevel [Byte0]: 60
3375 10:00:57.212817 [Byte1]: 60
3376 10:00:57.217015
3377 10:00:57.217094 Set Vref, RX VrefLevel [Byte0]: 61
3378 10:00:57.220397 [Byte1]: 61
3379 10:00:57.225205
3380 10:00:57.225284 Set Vref, RX VrefLevel [Byte0]: 62
3381 10:00:57.228640 [Byte1]: 62
3382 10:00:57.233161
3383 10:00:57.233240 Set Vref, RX VrefLevel [Byte0]: 63
3384 10:00:57.236096 [Byte1]: 63
3385 10:00:57.240834
3386 10:00:57.240912 Set Vref, RX VrefLevel [Byte0]: 64
3387 10:00:57.244162 [Byte1]: 64
3388 10:00:57.248770
3389 10:00:57.248849 Final RX Vref Byte 0 = 52 to rank0
3390 10:00:57.251861 Final RX Vref Byte 1 = 49 to rank0
3391 10:00:57.255401 Final RX Vref Byte 0 = 52 to rank1
3392 10:00:57.258843 Final RX Vref Byte 1 = 49 to rank1==
3393 10:00:57.261793 Dram Type= 6, Freq= 0, CH_1, rank 0
3394 10:00:57.268647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3395 10:00:57.268727 ==
3396 10:00:57.268790 DQS Delay:
3397 10:00:57.268849 DQS0 = 0, DQS1 = 0
3398 10:00:57.272062 DQM Delay:
3399 10:00:57.272141 DQM0 = 114, DQM1 = 112
3400 10:00:57.275028 DQ Delay:
3401 10:00:57.278492 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3402 10:00:57.281543 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3403 10:00:57.285084 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3404 10:00:57.288287 DQ12 =120, DQ13 =122, DQ14 =118, DQ15 =120
3405 10:00:57.288366
3406 10:00:57.288429
3407 10:00:57.298194 [DQSOSCAuto] RK0, (LSB)MR18= 0xf804, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3408 10:00:57.298275 CH1 RK0: MR19=304, MR18=F804
3409 10:00:57.304975 CH1_RK0: MR19=0x304, MR18=0xF804, DQSOSC=408, MR23=63, INC=39, DEC=26
3410 10:00:57.305057
3411 10:00:57.308185 ----->DramcWriteLeveling(PI) begin...
3412 10:00:57.308266 ==
3413 10:00:57.311623 Dram Type= 6, Freq= 0, CH_1, rank 1
3414 10:00:57.318458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 10:00:57.318539 ==
3416 10:00:57.321826 Write leveling (Byte 0): 25 => 25
3417 10:00:57.321906 Write leveling (Byte 1): 27 => 27
3418 10:00:57.325011 DramcWriteLeveling(PI) end<-----
3419 10:00:57.325091
3420 10:00:57.328306 ==
3421 10:00:57.328386 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 10:00:57.334532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 10:00:57.334612 ==
3424 10:00:57.338373 [Gating] SW mode calibration
3425 10:00:57.344858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3426 10:00:57.348059 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3427 10:00:57.354896 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 10:00:57.358119 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 10:00:57.361352 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 10:00:57.367878 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 10:00:57.371324 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 10:00:57.374787 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3433 10:00:57.381117 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
3434 10:00:57.384575 0 15 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
3435 10:00:57.388024 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 10:00:57.394360 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 10:00:57.397763 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 10:00:57.401326 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 10:00:57.407408 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 10:00:57.410811 1 0 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3441 10:00:57.414000 1 0 24 | B1->B0 | 2323 4444 | 0 1 | (0 0) (0 0)
3442 10:00:57.420890 1 0 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3443 10:00:57.424018 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 10:00:57.427650 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 10:00:57.433653 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 10:00:57.437312 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 10:00:57.440209 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 10:00:57.446717 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 10:00:57.449997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3450 10:00:57.453750 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3451 10:00:57.460589 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 10:00:57.463290 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 10:00:57.466549 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 10:00:57.473261 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 10:00:57.476991 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 10:00:57.479789 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 10:00:57.486149 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 10:00:57.489584 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 10:00:57.492813 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 10:00:57.499581 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 10:00:57.502675 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 10:00:57.506418 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 10:00:57.512626 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 10:00:57.515869 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3465 10:00:57.519689 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3466 10:00:57.525871 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3467 10:00:57.529084 Total UI for P1: 0, mck2ui 16
3468 10:00:57.532704 best dqsien dly found for B0: ( 1, 3, 22)
3469 10:00:57.535647 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 10:00:57.539186 Total UI for P1: 0, mck2ui 16
3471 10:00:57.542601 best dqsien dly found for B1: ( 1, 3, 28)
3472 10:00:57.545359 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3473 10:00:57.549217 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3474 10:00:57.549297
3475 10:00:57.552286 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3476 10:00:57.555709 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3477 10:00:57.558920 [Gating] SW calibration Done
3478 10:00:57.559003 ==
3479 10:00:57.562205 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 10:00:57.568890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 10:00:57.568981 ==
3482 10:00:57.569046 RX Vref Scan: 0
3483 10:00:57.569108
3484 10:00:57.571803 RX Vref 0 -> 0, step: 1
3485 10:00:57.571888
3486 10:00:57.575058 RX Delay -40 -> 252, step: 8
3487 10:00:57.578638 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3488 10:00:57.581921 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3489 10:00:57.585079 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3490 10:00:57.591816 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3491 10:00:57.594903 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3492 10:00:57.598125 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3493 10:00:57.601436 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3494 10:00:57.604538 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3495 10:00:57.611407 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3496 10:00:57.614846 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3497 10:00:57.618099 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3498 10:00:57.621474 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3499 10:00:57.624756 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3500 10:00:57.631077 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3501 10:00:57.634267 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3502 10:00:57.638249 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3503 10:00:57.638345 ==
3504 10:00:57.641575 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 10:00:57.644591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 10:00:57.647838 ==
3507 10:00:57.647961 DQS Delay:
3508 10:00:57.648051 DQS0 = 0, DQS1 = 0
3509 10:00:57.651335 DQM Delay:
3510 10:00:57.651405 DQM0 = 114, DQM1 = 111
3511 10:00:57.654032 DQ Delay:
3512 10:00:57.657979 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3513 10:00:57.660672 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3514 10:00:57.663884 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3515 10:00:57.667594 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3516 10:00:57.667692
3517 10:00:57.667780
3518 10:00:57.667872 ==
3519 10:00:57.670772 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 10:00:57.673909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 10:00:57.674014 ==
3522 10:00:57.674091
3523 10:00:57.677468
3524 10:00:57.677550 TX Vref Scan disable
3525 10:00:57.680794 == TX Byte 0 ==
3526 10:00:57.683844 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3527 10:00:57.687177 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3528 10:00:57.690966 == TX Byte 1 ==
3529 10:00:57.694207 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3530 10:00:57.697343 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3531 10:00:57.697425 ==
3532 10:00:57.700523 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 10:00:57.706841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 10:00:57.706949 ==
3535 10:00:57.718125 TX Vref=22, minBit 8, minWin=24, winSum=415
3536 10:00:57.721262 TX Vref=24, minBit 9, minWin=25, winSum=425
3537 10:00:57.724201 TX Vref=26, minBit 9, minWin=25, winSum=423
3538 10:00:57.727699 TX Vref=28, minBit 1, minWin=26, winSum=427
3539 10:00:57.731051 TX Vref=30, minBit 9, minWin=24, winSum=429
3540 10:00:57.737713 TX Vref=32, minBit 8, minWin=25, winSum=428
3541 10:00:57.740970 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3542 10:00:57.741042
3543 10:00:57.743982 Final TX Range 1 Vref 28
3544 10:00:57.744085
3545 10:00:57.744149 ==
3546 10:00:57.747310 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 10:00:57.750778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 10:00:57.750882 ==
3549 10:00:57.753989
3550 10:00:57.754085
3551 10:00:57.754172 TX Vref Scan disable
3552 10:00:57.757749 == TX Byte 0 ==
3553 10:00:57.760923 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3554 10:00:57.767015 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3555 10:00:57.767096 == TX Byte 1 ==
3556 10:00:57.770146 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3557 10:00:57.777281 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3558 10:00:57.777354
3559 10:00:57.777423 [DATLAT]
3560 10:00:57.777488 Freq=1200, CH1 RK1
3561 10:00:57.777546
3562 10:00:57.780097 DATLAT Default: 0xd
3563 10:00:57.783873 0, 0xFFFF, sum = 0
3564 10:00:57.783980 1, 0xFFFF, sum = 0
3565 10:00:57.786580 2, 0xFFFF, sum = 0
3566 10:00:57.786662 3, 0xFFFF, sum = 0
3567 10:00:57.790045 4, 0xFFFF, sum = 0
3568 10:00:57.790129 5, 0xFFFF, sum = 0
3569 10:00:57.793568 6, 0xFFFF, sum = 0
3570 10:00:57.793651 7, 0xFFFF, sum = 0
3571 10:00:57.796772 8, 0xFFFF, sum = 0
3572 10:00:57.796855 9, 0xFFFF, sum = 0
3573 10:00:57.800194 10, 0xFFFF, sum = 0
3574 10:00:57.800276 11, 0xFFFF, sum = 0
3575 10:00:57.803265 12, 0x0, sum = 1
3576 10:00:57.803347 13, 0x0, sum = 2
3577 10:00:57.806395 14, 0x0, sum = 3
3578 10:00:57.806478 15, 0x0, sum = 4
3579 10:00:57.809803 best_step = 13
3580 10:00:57.809885
3581 10:00:57.809952 ==
3582 10:00:57.813072 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 10:00:57.816667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 10:00:57.816749 ==
3585 10:00:57.819956 RX Vref Scan: 0
3586 10:00:57.820037
3587 10:00:57.820101 RX Vref 0 -> 0, step: 1
3588 10:00:57.820162
3589 10:00:57.823270 RX Delay -13 -> 252, step: 4
3590 10:00:57.829803 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3591 10:00:57.832807 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3592 10:00:57.836552 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3593 10:00:57.839624 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3594 10:00:57.843119 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3595 10:00:57.849777 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3596 10:00:57.852820 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3597 10:00:57.856257 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3598 10:00:57.859457 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3599 10:00:57.862812 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3600 10:00:57.869540 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3601 10:00:57.872751 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3602 10:00:57.875945 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3603 10:00:57.878914 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3604 10:00:57.885651 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3605 10:00:57.888902 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3606 10:00:57.888989 ==
3607 10:00:57.892239 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 10:00:57.895603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 10:00:57.895702 ==
3610 10:00:57.898842 DQS Delay:
3611 10:00:57.898913 DQS0 = 0, DQS1 = 0
3612 10:00:57.898973 DQM Delay:
3613 10:00:57.902059 DQM0 = 115, DQM1 = 111
3614 10:00:57.902127 DQ Delay:
3615 10:00:57.905400 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =114
3616 10:00:57.909216 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =112
3617 10:00:57.915411 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3618 10:00:57.918596 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =120
3619 10:00:57.918699
3620 10:00:57.918789
3621 10:00:57.925321 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3622 10:00:57.928735 CH1 RK1: MR19=304, MR18=F709
3623 10:00:57.935424 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3624 10:00:57.938520 [RxdqsGatingPostProcess] freq 1200
3625 10:00:57.945115 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3626 10:00:57.945189 best DQS0 dly(2T, 0.5T) = (0, 11)
3627 10:00:57.948129 best DQS1 dly(2T, 0.5T) = (0, 11)
3628 10:00:57.951583 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3629 10:00:57.955498 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3630 10:00:57.958152 best DQS0 dly(2T, 0.5T) = (0, 11)
3631 10:00:57.961311 best DQS1 dly(2T, 0.5T) = (0, 11)
3632 10:00:57.964828 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3633 10:00:57.968260 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3634 10:00:57.971403 Pre-setting of DQS Precalculation
3635 10:00:57.977916 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3636 10:00:57.984803 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3637 10:00:57.991562 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3638 10:00:57.991673
3639 10:00:57.991764
3640 10:00:57.994214 [Calibration Summary] 2400 Mbps
3641 10:00:57.994312 CH 0, Rank 0
3642 10:00:57.997866 SW Impedance : PASS
3643 10:00:58.001233 DUTY Scan : NO K
3644 10:00:58.001339 ZQ Calibration : PASS
3645 10:00:58.004532 Jitter Meter : NO K
3646 10:00:58.007470 CBT Training : PASS
3647 10:00:58.007554 Write leveling : PASS
3648 10:00:58.011329 RX DQS gating : PASS
3649 10:00:58.014577 RX DQ/DQS(RDDQC) : PASS
3650 10:00:58.014680 TX DQ/DQS : PASS
3651 10:00:58.017405 RX DATLAT : PASS
3652 10:00:58.017474 RX DQ/DQS(Engine): PASS
3653 10:00:58.020751 TX OE : NO K
3654 10:00:58.020914 All Pass.
3655 10:00:58.021074
3656 10:00:58.024384 CH 0, Rank 1
3657 10:00:58.024454 SW Impedance : PASS
3658 10:00:58.027475 DUTY Scan : NO K
3659 10:00:58.030603 ZQ Calibration : PASS
3660 10:00:58.030700 Jitter Meter : NO K
3661 10:00:58.034150 CBT Training : PASS
3662 10:00:58.037603 Write leveling : PASS
3663 10:00:58.037673 RX DQS gating : PASS
3664 10:00:58.040866 RX DQ/DQS(RDDQC) : PASS
3665 10:00:58.044155 TX DQ/DQS : PASS
3666 10:00:58.044260 RX DATLAT : PASS
3667 10:00:58.047663 RX DQ/DQS(Engine): PASS
3668 10:00:58.051100 TX OE : NO K
3669 10:00:58.051197 All Pass.
3670 10:00:58.051284
3671 10:00:58.051377 CH 1, Rank 0
3672 10:00:58.053754 SW Impedance : PASS
3673 10:00:58.057021 DUTY Scan : NO K
3674 10:00:58.057091 ZQ Calibration : PASS
3675 10:00:58.060784 Jitter Meter : NO K
3676 10:00:58.063843 CBT Training : PASS
3677 10:00:58.063970 Write leveling : PASS
3678 10:00:58.066980 RX DQS gating : PASS
3679 10:00:58.070057 RX DQ/DQS(RDDQC) : PASS
3680 10:00:58.070128 TX DQ/DQS : PASS
3681 10:00:58.073810 RX DATLAT : PASS
3682 10:00:58.077050 RX DQ/DQS(Engine): PASS
3683 10:00:58.077119 TX OE : NO K
3684 10:00:58.080371 All Pass.
3685 10:00:58.080453
3686 10:00:58.080517 CH 1, Rank 1
3687 10:00:58.083238 SW Impedance : PASS
3688 10:00:58.083348 DUTY Scan : NO K
3689 10:00:58.086816 ZQ Calibration : PASS
3690 10:00:58.090042 Jitter Meter : NO K
3691 10:00:58.090118 CBT Training : PASS
3692 10:00:58.093782 Write leveling : PASS
3693 10:00:58.093856 RX DQS gating : PASS
3694 10:00:58.096644 RX DQ/DQS(RDDQC) : PASS
3695 10:00:58.100070 TX DQ/DQS : PASS
3696 10:00:58.100175 RX DATLAT : PASS
3697 10:00:58.103482 RX DQ/DQS(Engine): PASS
3698 10:00:58.106548 TX OE : NO K
3699 10:00:58.106646 All Pass.
3700 10:00:58.106742
3701 10:00:58.109693 DramC Write-DBI off
3702 10:00:58.113224 PER_BANK_REFRESH: Hybrid Mode
3703 10:00:58.113306 TX_TRACKING: ON
3704 10:00:58.123348 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3705 10:00:58.126638 [FAST_K] Save calibration result to emmc
3706 10:00:58.129701 dramc_set_vcore_voltage set vcore to 650000
3707 10:00:58.133103 Read voltage for 600, 5
3708 10:00:58.133201 Vio18 = 0
3709 10:00:58.133267 Vcore = 650000
3710 10:00:58.136326 Vdram = 0
3711 10:00:58.136407 Vddq = 0
3712 10:00:58.136472 Vmddr = 0
3713 10:00:58.142877 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3714 10:00:58.146192 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3715 10:00:58.149644 MEM_TYPE=3, freq_sel=19
3716 10:00:58.152627 sv_algorithm_assistance_LP4_1600
3717 10:00:58.156298 ============ PULL DRAM RESETB DOWN ============
3718 10:00:58.159281 ========== PULL DRAM RESETB DOWN end =========
3719 10:00:58.165944 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3720 10:00:58.169173 ===================================
3721 10:00:58.169255 LPDDR4 DRAM CONFIGURATION
3722 10:00:58.172727 ===================================
3723 10:00:58.175872 EX_ROW_EN[0] = 0x0
3724 10:00:58.178858 EX_ROW_EN[1] = 0x0
3725 10:00:58.178939 LP4Y_EN = 0x0
3726 10:00:58.182580 WORK_FSP = 0x0
3727 10:00:58.182661 WL = 0x2
3728 10:00:58.185633 RL = 0x2
3729 10:00:58.185715 BL = 0x2
3730 10:00:58.189004 RPST = 0x0
3731 10:00:58.189085 RD_PRE = 0x0
3732 10:00:58.192577 WR_PRE = 0x1
3733 10:00:58.192659 WR_PST = 0x0
3734 10:00:58.195838 DBI_WR = 0x0
3735 10:00:58.195960 DBI_RD = 0x0
3736 10:00:58.199204 OTF = 0x1
3737 10:00:58.202191 ===================================
3738 10:00:58.205808 ===================================
3739 10:00:58.205891 ANA top config
3740 10:00:58.208764 ===================================
3741 10:00:58.212168 DLL_ASYNC_EN = 0
3742 10:00:58.215333 ALL_SLAVE_EN = 1
3743 10:00:58.218648 NEW_RANK_MODE = 1
3744 10:00:58.218731 DLL_IDLE_MODE = 1
3745 10:00:58.222128 LP45_APHY_COMB_EN = 1
3746 10:00:58.225421 TX_ODT_DIS = 1
3747 10:00:58.229037 NEW_8X_MODE = 1
3748 10:00:58.232439 ===================================
3749 10:00:58.235044 ===================================
3750 10:00:58.238552 data_rate = 1200
3751 10:00:58.241828 CKR = 1
3752 10:00:58.241910 DQ_P2S_RATIO = 8
3753 10:00:58.244779 ===================================
3754 10:00:58.248285 CA_P2S_RATIO = 8
3755 10:00:58.251689 DQ_CA_OPEN = 0
3756 10:00:58.255082 DQ_SEMI_OPEN = 0
3757 10:00:58.258008 CA_SEMI_OPEN = 0
3758 10:00:58.261421 CA_FULL_RATE = 0
3759 10:00:58.261502 DQ_CKDIV4_EN = 1
3760 10:00:58.264916 CA_CKDIV4_EN = 1
3761 10:00:58.268007 CA_PREDIV_EN = 0
3762 10:00:58.271634 PH8_DLY = 0
3763 10:00:58.274891 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3764 10:00:58.277710 DQ_AAMCK_DIV = 4
3765 10:00:58.277792 CA_AAMCK_DIV = 4
3766 10:00:58.281132 CA_ADMCK_DIV = 4
3767 10:00:58.284558 DQ_TRACK_CA_EN = 0
3768 10:00:58.287786 CA_PICK = 600
3769 10:00:58.291178 CA_MCKIO = 600
3770 10:00:58.294206 MCKIO_SEMI = 0
3771 10:00:58.298237 PLL_FREQ = 2288
3772 10:00:58.298319 DQ_UI_PI_RATIO = 32
3773 10:00:58.301097 CA_UI_PI_RATIO = 0
3774 10:00:58.304620 ===================================
3775 10:00:58.307525 ===================================
3776 10:00:58.311216 memory_type:LPDDR4
3777 10:00:58.314185 GP_NUM : 10
3778 10:00:58.314266 SRAM_EN : 1
3779 10:00:58.317634 MD32_EN : 0
3780 10:00:58.320797 ===================================
3781 10:00:58.323783 [ANA_INIT] >>>>>>>>>>>>>>
3782 10:00:58.327251 <<<<<< [CONFIGURE PHASE]: ANA_TX
3783 10:00:58.330858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3784 10:00:58.334061 ===================================
3785 10:00:58.334144 data_rate = 1200,PCW = 0X5800
3786 10:00:58.337018 ===================================
3787 10:00:58.340330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3788 10:00:58.347327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3789 10:00:58.353848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3790 10:00:58.357098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3791 10:00:58.359891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3792 10:00:58.363444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3793 10:00:58.366791 [ANA_INIT] flow start
3794 10:00:58.370203 [ANA_INIT] PLL >>>>>>>>
3795 10:00:58.370285 [ANA_INIT] PLL <<<<<<<<
3796 10:00:58.373756 [ANA_INIT] MIDPI >>>>>>>>
3797 10:00:58.376946 [ANA_INIT] MIDPI <<<<<<<<
3798 10:00:58.377028 [ANA_INIT] DLL >>>>>>>>
3799 10:00:58.380493 [ANA_INIT] flow end
3800 10:00:58.383442 ============ LP4 DIFF to SE enter ============
3801 10:00:58.390150 ============ LP4 DIFF to SE exit ============
3802 10:00:58.390233 [ANA_INIT] <<<<<<<<<<<<<
3803 10:00:58.392837 [Flow] Enable top DCM control >>>>>
3804 10:00:58.396124 [Flow] Enable top DCM control <<<<<
3805 10:00:58.399844 Enable DLL master slave shuffle
3806 10:00:58.406053 ==============================================================
3807 10:00:58.406157 Gating Mode config
3808 10:00:58.412491 ==============================================================
3809 10:00:58.415694 Config description:
3810 10:00:58.425984 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3811 10:00:58.432611 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3812 10:00:58.435793 SELPH_MODE 0: By rank 1: By Phase
3813 10:00:58.442088 ==============================================================
3814 10:00:58.445666 GAT_TRACK_EN = 1
3815 10:00:58.448884 RX_GATING_MODE = 2
3816 10:00:58.448981 RX_GATING_TRACK_MODE = 2
3817 10:00:58.452104 SELPH_MODE = 1
3818 10:00:58.455547 PICG_EARLY_EN = 1
3819 10:00:58.458852 VALID_LAT_VALUE = 1
3820 10:00:58.465638 ==============================================================
3821 10:00:58.468717 Enter into Gating configuration >>>>
3822 10:00:58.471837 Exit from Gating configuration <<<<
3823 10:00:58.475220 Enter into DVFS_PRE_config >>>>>
3824 10:00:58.485147 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3825 10:00:58.488357 Exit from DVFS_PRE_config <<<<<
3826 10:00:58.492026 Enter into PICG configuration >>>>
3827 10:00:58.494994 Exit from PICG configuration <<<<
3828 10:00:58.498016 [RX_INPUT] configuration >>>>>
3829 10:00:58.501332 [RX_INPUT] configuration <<<<<
3830 10:00:58.505059 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3831 10:00:58.511331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3832 10:00:58.517824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3833 10:00:58.525017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3834 10:00:58.530953 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3835 10:00:58.538232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3836 10:00:58.541211 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3837 10:00:58.545109 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3838 10:00:58.547749 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3839 10:00:58.554035 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3840 10:00:58.557924 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3841 10:00:58.560641 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3842 10:00:58.564118 ===================================
3843 10:00:58.567496 LPDDR4 DRAM CONFIGURATION
3844 10:00:58.570425 ===================================
3845 10:00:58.570506 EX_ROW_EN[0] = 0x0
3846 10:00:58.574014 EX_ROW_EN[1] = 0x0
3847 10:00:58.577195 LP4Y_EN = 0x0
3848 10:00:58.577276 WORK_FSP = 0x0
3849 10:00:58.580838 WL = 0x2
3850 10:00:58.580920 RL = 0x2
3851 10:00:58.583768 BL = 0x2
3852 10:00:58.583849 RPST = 0x0
3853 10:00:58.586943 RD_PRE = 0x0
3854 10:00:58.587024 WR_PRE = 0x1
3855 10:00:58.590416 WR_PST = 0x0
3856 10:00:58.590497 DBI_WR = 0x0
3857 10:00:58.593783 DBI_RD = 0x0
3858 10:00:58.593865 OTF = 0x1
3859 10:00:58.597041 ===================================
3860 10:00:58.600513 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3861 10:00:58.606697 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3862 10:00:58.609904 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3863 10:00:58.613257 ===================================
3864 10:00:58.616484 LPDDR4 DRAM CONFIGURATION
3865 10:00:58.619971 ===================================
3866 10:00:58.620054 EX_ROW_EN[0] = 0x10
3867 10:00:58.623409 EX_ROW_EN[1] = 0x0
3868 10:00:58.626445 LP4Y_EN = 0x0
3869 10:00:58.626527 WORK_FSP = 0x0
3870 10:00:58.629909 WL = 0x2
3871 10:00:58.629990 RL = 0x2
3872 10:00:58.633111 BL = 0x2
3873 10:00:58.633192 RPST = 0x0
3874 10:00:58.636686 RD_PRE = 0x0
3875 10:00:58.636767 WR_PRE = 0x1
3876 10:00:58.639690 WR_PST = 0x0
3877 10:00:58.639770 DBI_WR = 0x0
3878 10:00:58.643389 DBI_RD = 0x0
3879 10:00:58.643505 OTF = 0x1
3880 10:00:58.646119 ===================================
3881 10:00:58.653327 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3882 10:00:58.657529 nWR fixed to 30
3883 10:00:58.660689 [ModeRegInit_LP4] CH0 RK0
3884 10:00:58.660772 [ModeRegInit_LP4] CH0 RK1
3885 10:00:58.664286 [ModeRegInit_LP4] CH1 RK0
3886 10:00:58.667451 [ModeRegInit_LP4] CH1 RK1
3887 10:00:58.667533 match AC timing 17
3888 10:00:58.674236 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3889 10:00:58.677471 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3890 10:00:58.680807 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3891 10:00:58.687547 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3892 10:00:58.690221 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3893 10:00:58.690303 ==
3894 10:00:58.694079 Dram Type= 6, Freq= 0, CH_0, rank 0
3895 10:00:58.697168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3896 10:00:58.697251 ==
3897 10:00:58.703926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3898 10:00:58.710633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3899 10:00:58.713721 [CA 0] Center 36 (6~67) winsize 62
3900 10:00:58.716555 [CA 1] Center 35 (5~66) winsize 62
3901 10:00:58.720147 [CA 2] Center 34 (4~65) winsize 62
3902 10:00:58.723210 [CA 3] Center 34 (4~65) winsize 62
3903 10:00:58.726987 [CA 4] Center 33 (3~64) winsize 62
3904 10:00:58.729768 [CA 5] Center 33 (3~64) winsize 62
3905 10:00:58.729850
3906 10:00:58.733177 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3907 10:00:58.733259
3908 10:00:58.736524 [CATrainingPosCal] consider 1 rank data
3909 10:00:58.740066 u2DelayCellTimex100 = 270/100 ps
3910 10:00:58.742988 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3911 10:00:58.746306 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3912 10:00:58.749413 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3913 10:00:58.756229 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3914 10:00:58.760081 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3915 10:00:58.762954 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3916 10:00:58.763036
3917 10:00:58.766192 CA PerBit enable=1, Macro0, CA PI delay=33
3918 10:00:58.766275
3919 10:00:58.769961 [CBTSetCACLKResult] CA Dly = 33
3920 10:00:58.770042 CS Dly: 5 (0~36)
3921 10:00:58.770108 ==
3922 10:00:58.773212 Dram Type= 6, Freq= 0, CH_0, rank 1
3923 10:00:58.779814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3924 10:00:58.779897 ==
3925 10:00:58.783199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3926 10:00:58.789308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3927 10:00:58.792802 [CA 0] Center 36 (6~67) winsize 62
3928 10:00:58.796189 [CA 1] Center 36 (6~67) winsize 62
3929 10:00:58.799390 [CA 2] Center 34 (4~65) winsize 62
3930 10:00:58.802859 [CA 3] Center 34 (4~65) winsize 62
3931 10:00:58.805739 [CA 4] Center 34 (3~65) winsize 63
3932 10:00:58.809268 [CA 5] Center 33 (3~64) winsize 62
3933 10:00:58.809350
3934 10:00:58.812686 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3935 10:00:58.812768
3936 10:00:58.815952 [CATrainingPosCal] consider 2 rank data
3937 10:00:58.819211 u2DelayCellTimex100 = 270/100 ps
3938 10:00:58.822398 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3939 10:00:58.829090 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3940 10:00:58.832889 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3941 10:00:58.835641 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3942 10:00:58.839215 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 10:00:58.842370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3944 10:00:58.842453
3945 10:00:58.845783 CA PerBit enable=1, Macro0, CA PI delay=33
3946 10:00:58.845865
3947 10:00:58.849168 [CBTSetCACLKResult] CA Dly = 33
3948 10:00:58.852353 CS Dly: 5 (0~37)
3949 10:00:58.852434
3950 10:00:58.855369 ----->DramcWriteLeveling(PI) begin...
3951 10:00:58.855452 ==
3952 10:00:58.858957 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 10:00:58.862350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 10:00:58.862432 ==
3955 10:00:58.865396 Write leveling (Byte 0): 34 => 34
3956 10:00:58.868675 Write leveling (Byte 1): 31 => 31
3957 10:00:58.871789 DramcWriteLeveling(PI) end<-----
3958 10:00:58.871871
3959 10:00:58.871946 ==
3960 10:00:58.874965 Dram Type= 6, Freq= 0, CH_0, rank 0
3961 10:00:58.878640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 10:00:58.878722 ==
3963 10:00:58.881645 [Gating] SW mode calibration
3964 10:00:58.888160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3965 10:00:58.895213 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3966 10:00:58.898140 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 10:00:58.901392 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 10:00:58.908267 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3969 10:00:58.911550 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3970 10:00:58.915045 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3971 10:00:58.921418 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 10:00:58.924715 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 10:00:58.927758 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 10:00:58.934462 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 10:00:58.938557 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 10:00:58.941358 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 10:00:58.947499 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (1 1)
3978 10:00:58.950986 0 10 16 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
3979 10:00:58.954417 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 10:00:58.961197 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 10:00:58.964339 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 10:00:58.967471 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 10:00:58.974066 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 10:00:58.977517 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 10:00:58.980720 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3986 10:00:58.986945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3987 10:00:58.990281 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 10:00:58.994017 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 10:00:58.999894 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 10:00:59.003547 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 10:00:59.006854 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 10:00:59.013368 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 10:00:59.016726 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 10:00:59.020100 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 10:00:59.026558 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 10:00:59.029846 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 10:00:59.032958 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 10:00:59.039848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 10:00:59.043033 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 10:00:59.046461 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 10:00:59.052810 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 10:00:59.056179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4003 10:00:59.059539 Total UI for P1: 0, mck2ui 16
4004 10:00:59.062873 best dqsien dly found for B0: ( 0, 13, 14)
4005 10:00:59.065968 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 10:00:59.069553 Total UI for P1: 0, mck2ui 16
4007 10:00:59.072911 best dqsien dly found for B1: ( 0, 13, 16)
4008 10:00:59.079314 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4009 10:00:59.082333 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4010 10:00:59.082408
4011 10:00:59.085797 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4012 10:00:59.088929 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4013 10:00:59.092287 [Gating] SW calibration Done
4014 10:00:59.092369 ==
4015 10:00:59.096096 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 10:00:59.098753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 10:00:59.098839 ==
4018 10:00:59.102131 RX Vref Scan: 0
4019 10:00:59.102213
4020 10:00:59.102279 RX Vref 0 -> 0, step: 1
4021 10:00:59.102341
4022 10:00:59.105250 RX Delay -230 -> 252, step: 16
4023 10:00:59.112099 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4024 10:00:59.115534 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4025 10:00:59.118483 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4026 10:00:59.121946 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4027 10:00:59.125124 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4028 10:00:59.132100 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4029 10:00:59.134917 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4030 10:00:59.138073 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4031 10:00:59.141318 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4032 10:00:59.147889 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4033 10:00:59.151701 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4034 10:00:59.154807 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4035 10:00:59.158269 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4036 10:00:59.164523 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4037 10:00:59.168110 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4038 10:00:59.171057 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4039 10:00:59.171129 ==
4040 10:00:59.174183 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 10:00:59.181094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 10:00:59.181171 ==
4043 10:00:59.181234 DQS Delay:
4044 10:00:59.181293 DQS0 = 0, DQS1 = 0
4045 10:00:59.184554 DQM Delay:
4046 10:00:59.184651 DQM0 = 48, DQM1 = 35
4047 10:00:59.187641 DQ Delay:
4048 10:00:59.191074 DQ0 =41, DQ1 =49, DQ2 =49, DQ3 =41
4049 10:00:59.194087 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4050 10:00:59.194185 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4051 10:00:59.200801 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4052 10:00:59.200877
4053 10:00:59.200940
4054 10:00:59.200999 ==
4055 10:00:59.204298 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 10:00:59.207421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 10:00:59.207490 ==
4058 10:00:59.207549
4059 10:00:59.207604
4060 10:00:59.210535 TX Vref Scan disable
4061 10:00:59.210616 == TX Byte 0 ==
4062 10:00:59.217783 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4063 10:00:59.220950 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4064 10:00:59.223860 == TX Byte 1 ==
4065 10:00:59.227157 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4066 10:00:59.230457 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4067 10:00:59.230539 ==
4068 10:00:59.234159 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 10:00:59.237551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 10:00:59.240039 ==
4071 10:00:59.240119
4072 10:00:59.240184
4073 10:00:59.240243 TX Vref Scan disable
4074 10:00:59.244473 == TX Byte 0 ==
4075 10:00:59.247562 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4076 10:00:59.254680 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4077 10:00:59.254761 == TX Byte 1 ==
4078 10:00:59.257187 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4079 10:00:59.263774 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4080 10:00:59.263858
4081 10:00:59.263943 [DATLAT]
4082 10:00:59.264018 Freq=600, CH0 RK0
4083 10:00:59.264077
4084 10:00:59.267462 DATLAT Default: 0x9
4085 10:00:59.267543 0, 0xFFFF, sum = 0
4086 10:00:59.270571 1, 0xFFFF, sum = 0
4087 10:00:59.273859 2, 0xFFFF, sum = 0
4088 10:00:59.273941 3, 0xFFFF, sum = 0
4089 10:00:59.277480 4, 0xFFFF, sum = 0
4090 10:00:59.277563 5, 0xFFFF, sum = 0
4091 10:00:59.280347 6, 0xFFFF, sum = 0
4092 10:00:59.280429 7, 0xFFFF, sum = 0
4093 10:00:59.283508 8, 0x0, sum = 1
4094 10:00:59.283590 9, 0x0, sum = 2
4095 10:00:59.283655 10, 0x0, sum = 3
4096 10:00:59.286848 11, 0x0, sum = 4
4097 10:00:59.286930 best_step = 9
4098 10:00:59.286994
4099 10:00:59.290592 ==
4100 10:00:59.290685 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 10:00:59.296952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 10:00:59.297034 ==
4103 10:00:59.297100 RX Vref Scan: 1
4104 10:00:59.297159
4105 10:00:59.300407 RX Vref 0 -> 0, step: 1
4106 10:00:59.300488
4107 10:00:59.303379 RX Delay -195 -> 252, step: 8
4108 10:00:59.303460
4109 10:00:59.306832 Set Vref, RX VrefLevel [Byte0]: 57
4110 10:00:59.310157 [Byte1]: 59
4111 10:00:59.310241
4112 10:00:59.313113 Final RX Vref Byte 0 = 57 to rank0
4113 10:00:59.316840 Final RX Vref Byte 1 = 59 to rank0
4114 10:00:59.320066 Final RX Vref Byte 0 = 57 to rank1
4115 10:00:59.323234 Final RX Vref Byte 1 = 59 to rank1==
4116 10:00:59.326519 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 10:00:59.330066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 10:00:59.333165 ==
4119 10:00:59.333246 DQS Delay:
4120 10:00:59.333311 DQS0 = 0, DQS1 = 0
4121 10:00:59.336802 DQM Delay:
4122 10:00:59.336883 DQM0 = 41, DQM1 = 33
4123 10:00:59.340137 DQ Delay:
4124 10:00:59.342820 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4125 10:00:59.342900 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4126 10:00:59.346009 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =32
4127 10:00:59.352912 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4128 10:00:59.352993
4129 10:00:59.353057
4130 10:00:59.359481 [DQSOSCAuto] RK0, (LSB)MR18= 0x5148, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4131 10:00:59.363400 CH0 RK0: MR19=808, MR18=5148
4132 10:00:59.369937 CH0_RK0: MR19=0x808, MR18=0x5148, DQSOSC=394, MR23=63, INC=168, DEC=112
4133 10:00:59.370018
4134 10:00:59.372569 ----->DramcWriteLeveling(PI) begin...
4135 10:00:59.372651 ==
4136 10:00:59.375835 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 10:00:59.379761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 10:00:59.379843 ==
4139 10:00:59.382624 Write leveling (Byte 0): 36 => 36
4140 10:00:59.385669 Write leveling (Byte 1): 29 => 29
4141 10:00:59.389175 DramcWriteLeveling(PI) end<-----
4142 10:00:59.389255
4143 10:00:59.389319 ==
4144 10:00:59.392837 Dram Type= 6, Freq= 0, CH_0, rank 1
4145 10:00:59.395564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 10:00:59.395645 ==
4147 10:00:59.399169 [Gating] SW mode calibration
4148 10:00:59.405833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4149 10:00:59.412342 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4150 10:00:59.415327 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 10:00:59.422084 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4152 10:00:59.425496 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4153 10:00:59.428634 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4154 10:00:59.435472 0 9 16 | B1->B0 | 2e2e 2727 | 0 0 | (1 1) (0 0)
4155 10:00:59.438840 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 10:00:59.441834 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 10:00:59.448367 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 10:00:59.451697 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 10:00:59.454877 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 10:00:59.461591 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 10:00:59.464669 0 10 12 | B1->B0 | 2727 3939 | 1 0 | (0 0) (0 0)
4162 10:00:59.468079 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4163 10:00:59.474732 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 10:00:59.478215 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 10:00:59.481763 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 10:00:59.487823 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 10:00:59.491686 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 10:00:59.494182 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 10:00:59.500936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4170 10:00:59.504346 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4171 10:00:59.507604 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 10:00:59.514226 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 10:00:59.517789 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 10:00:59.520849 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 10:00:59.527454 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 10:00:59.530701 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 10:00:59.534079 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 10:00:59.540420 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 10:00:59.543687 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 10:00:59.547834 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 10:00:59.553874 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 10:00:59.557010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 10:00:59.560238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 10:00:59.567098 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 10:00:59.570526 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4186 10:00:59.573205 Total UI for P1: 0, mck2ui 16
4187 10:00:59.576749 best dqsien dly found for B0: ( 0, 13, 10)
4188 10:00:59.580031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 10:00:59.583331 Total UI for P1: 0, mck2ui 16
4190 10:00:59.586682 best dqsien dly found for B1: ( 0, 13, 12)
4191 10:00:59.590050 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4192 10:00:59.596364 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4193 10:00:59.596441
4194 10:00:59.599526 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4195 10:00:59.603204 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4196 10:00:59.606707 [Gating] SW calibration Done
4197 10:00:59.606808 ==
4198 10:00:59.610009 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 10:00:59.613266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 10:00:59.613339 ==
4201 10:00:59.616288 RX Vref Scan: 0
4202 10:00:59.616383
4203 10:00:59.616480 RX Vref 0 -> 0, step: 1
4204 10:00:59.616565
4205 10:00:59.619523 RX Delay -230 -> 252, step: 16
4206 10:00:59.622789 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4207 10:00:59.629801 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4208 10:00:59.632952 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4209 10:00:59.635993 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4210 10:00:59.639505 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4211 10:00:59.645748 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4212 10:00:59.649635 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4213 10:00:59.652859 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4214 10:00:59.656070 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4215 10:00:59.658917 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4216 10:00:59.665610 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4217 10:00:59.668791 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4218 10:00:59.672820 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4219 10:00:59.675575 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4220 10:00:59.682782 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4221 10:00:59.685575 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4222 10:00:59.685662 ==
4223 10:00:59.689046 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 10:00:59.692532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 10:00:59.692614 ==
4226 10:00:59.695917 DQS Delay:
4227 10:00:59.696030 DQS0 = 0, DQS1 = 0
4228 10:00:59.698678 DQM Delay:
4229 10:00:59.698759 DQM0 = 41, DQM1 = 33
4230 10:00:59.698825 DQ Delay:
4231 10:00:59.702111 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4232 10:00:59.705499 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4233 10:00:59.708742 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4234 10:00:59.712026 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =33
4235 10:00:59.712136
4236 10:00:59.712228
4237 10:00:59.712318 ==
4238 10:00:59.715263 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 10:00:59.722045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 10:00:59.722128 ==
4241 10:00:59.722193
4242 10:00:59.722253
4243 10:00:59.725464 TX Vref Scan disable
4244 10:00:59.725545 == TX Byte 0 ==
4245 10:00:59.731713 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4246 10:00:59.735239 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4247 10:00:59.735321 == TX Byte 1 ==
4248 10:00:59.741777 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4249 10:00:59.745220 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4250 10:00:59.745303 ==
4251 10:00:59.748544 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 10:00:59.751463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 10:00:59.751545 ==
4254 10:00:59.751610
4255 10:00:59.751669
4256 10:00:59.755185 TX Vref Scan disable
4257 10:00:59.758354 == TX Byte 0 ==
4258 10:00:59.761866 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4259 10:00:59.764836 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4260 10:00:59.768175 == TX Byte 1 ==
4261 10:00:59.771728 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4262 10:00:59.774895 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4263 10:00:59.777889
4264 10:00:59.777970 [DATLAT]
4265 10:00:59.778035 Freq=600, CH0 RK1
4266 10:00:59.778095
4267 10:00:59.781297 DATLAT Default: 0x9
4268 10:00:59.781378 0, 0xFFFF, sum = 0
4269 10:00:59.784650 1, 0xFFFF, sum = 0
4270 10:00:59.784733 2, 0xFFFF, sum = 0
4271 10:00:59.787848 3, 0xFFFF, sum = 0
4272 10:00:59.787988 4, 0xFFFF, sum = 0
4273 10:00:59.791495 5, 0xFFFF, sum = 0
4274 10:00:59.794678 6, 0xFFFF, sum = 0
4275 10:00:59.794760 7, 0xFFFF, sum = 0
4276 10:00:59.797896 8, 0x0, sum = 1
4277 10:00:59.797979 9, 0x0, sum = 2
4278 10:00:59.798046 10, 0x0, sum = 3
4279 10:00:59.801271 11, 0x0, sum = 4
4280 10:00:59.801353 best_step = 9
4281 10:00:59.801418
4282 10:00:59.801478 ==
4283 10:00:59.804634 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 10:00:59.810967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 10:00:59.811050 ==
4286 10:00:59.811115 RX Vref Scan: 0
4287 10:00:59.811206
4288 10:00:59.814101 RX Vref 0 -> 0, step: 1
4289 10:00:59.814182
4290 10:00:59.817923 RX Delay -179 -> 252, step: 8
4291 10:00:59.821041 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4292 10:00:59.827783 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4293 10:00:59.831232 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4294 10:00:59.833994 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4295 10:00:59.837754 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4296 10:00:59.844209 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4297 10:00:59.847546 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4298 10:00:59.850970 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4299 10:00:59.854153 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4300 10:00:59.857559 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4301 10:00:59.863703 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4302 10:00:59.866995 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4303 10:00:59.870322 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4304 10:00:59.873669 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4305 10:00:59.880536 iDelay=205, Bit 14, Center 44 (-115 ~ 204) 320
4306 10:00:59.883685 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4307 10:00:59.883793 ==
4308 10:00:59.887086 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 10:00:59.890738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 10:00:59.890820 ==
4311 10:00:59.893470 DQS Delay:
4312 10:00:59.893551 DQS0 = 0, DQS1 = 0
4313 10:00:59.896710 DQM Delay:
4314 10:00:59.896791 DQM0 = 40, DQM1 = 33
4315 10:00:59.896855 DQ Delay:
4316 10:00:59.900745 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4317 10:00:59.903431 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4318 10:00:59.906614 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4319 10:00:59.910156 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4320 10:00:59.910237
4321 10:00:59.910301
4322 10:00:59.920111 [DQSOSCAuto] RK1, (LSB)MR18= 0x413c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4323 10:00:59.923113 CH0 RK1: MR19=808, MR18=413C
4324 10:00:59.929887 CH0_RK1: MR19=0x808, MR18=0x413C, DQSOSC=397, MR23=63, INC=166, DEC=110
4325 10:00:59.933327 [RxdqsGatingPostProcess] freq 600
4326 10:00:59.936424 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4327 10:00:59.939630 Pre-setting of DQS Precalculation
4328 10:00:59.946197 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4329 10:00:59.946278 ==
4330 10:00:59.949306 Dram Type= 6, Freq= 0, CH_1, rank 0
4331 10:00:59.953024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 10:00:59.953106 ==
4333 10:00:59.959202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4334 10:00:59.962577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4335 10:00:59.966739 [CA 0] Center 35 (5~66) winsize 62
4336 10:00:59.970693 [CA 1] Center 35 (5~66) winsize 62
4337 10:00:59.973277 [CA 2] Center 34 (4~65) winsize 62
4338 10:00:59.976610 [CA 3] Center 34 (4~65) winsize 62
4339 10:00:59.979866 [CA 4] Center 34 (4~65) winsize 62
4340 10:00:59.983142 [CA 5] Center 33 (3~64) winsize 62
4341 10:00:59.983223
4342 10:00:59.986556 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4343 10:00:59.986638
4344 10:00:59.989828 [CATrainingPosCal] consider 1 rank data
4345 10:00:59.993871 u2DelayCellTimex100 = 270/100 ps
4346 10:00:59.996715 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4347 10:01:00.003393 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4348 10:01:00.006550 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4349 10:01:00.009708 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4350 10:01:00.013366 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4351 10:01:00.016659 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4352 10:01:00.016741
4353 10:01:00.020167 CA PerBit enable=1, Macro0, CA PI delay=33
4354 10:01:00.020248
4355 10:01:00.022990 [CBTSetCACLKResult] CA Dly = 33
4356 10:01:00.026190 CS Dly: 5 (0~36)
4357 10:01:00.026272 ==
4358 10:01:00.029646 Dram Type= 6, Freq= 0, CH_1, rank 1
4359 10:01:00.032675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 10:01:00.032757 ==
4361 10:01:00.039613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 10:01:00.042604 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4363 10:01:00.047168 [CA 0] Center 36 (6~66) winsize 61
4364 10:01:00.050254 [CA 1] Center 35 (5~66) winsize 62
4365 10:01:00.053589 [CA 2] Center 34 (4~65) winsize 62
4366 10:01:00.057009 [CA 3] Center 33 (3~64) winsize 62
4367 10:01:00.060222 [CA 4] Center 34 (4~65) winsize 62
4368 10:01:00.063630 [CA 5] Center 33 (3~64) winsize 62
4369 10:01:00.063711
4370 10:01:00.066707 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4371 10:01:00.066788
4372 10:01:00.070050 [CATrainingPosCal] consider 2 rank data
4373 10:01:00.073039 u2DelayCellTimex100 = 270/100 ps
4374 10:01:00.076687 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4375 10:01:00.083144 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4376 10:01:00.086587 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 10:01:00.089572 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4378 10:01:00.092936 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4379 10:01:00.096509 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4380 10:01:00.096591
4381 10:01:00.099873 CA PerBit enable=1, Macro0, CA PI delay=33
4382 10:01:00.099998
4383 10:01:00.103157 [CBTSetCACLKResult] CA Dly = 33
4384 10:01:00.106107 CS Dly: 5 (0~36)
4385 10:01:00.106187
4386 10:01:00.109350 ----->DramcWriteLeveling(PI) begin...
4387 10:01:00.109434 ==
4388 10:01:00.113211 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 10:01:00.116198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 10:01:00.116272 ==
4391 10:01:00.119131 Write leveling (Byte 0): 27 => 27
4392 10:01:00.122535 Write leveling (Byte 1): 30 => 30
4393 10:01:00.125810 DramcWriteLeveling(PI) end<-----
4394 10:01:00.125896
4395 10:01:00.125958 ==
4396 10:01:00.128801 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 10:01:00.132067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 10:01:00.132163 ==
4399 10:01:00.135727 [Gating] SW mode calibration
4400 10:01:00.142249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4401 10:01:00.148455 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4402 10:01:00.151930 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 10:01:00.158826 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4404 10:01:00.161922 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4405 10:01:00.165211 0 9 12 | B1->B0 | 3030 3131 | 0 0 | (0 1) (1 1)
4406 10:01:00.172391 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 10:01:00.175382 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 10:01:00.178263 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 10:01:00.185097 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 10:01:00.188685 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 10:01:00.191735 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 10:01:00.198171 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4413 10:01:00.201686 0 10 12 | B1->B0 | 2d2d 3636 | 1 0 | (0 0) (0 0)
4414 10:01:00.204967 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 10:01:00.211190 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 10:01:00.214459 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 10:01:00.217553 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 10:01:00.224439 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 10:01:00.227947 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 10:01:00.230700 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 10:01:00.237602 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4422 10:01:00.240975 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 10:01:00.244030 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 10:01:00.250627 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 10:01:00.254056 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 10:01:00.257343 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 10:01:00.263735 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 10:01:00.266965 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 10:01:00.270442 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 10:01:00.276732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 10:01:00.280777 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 10:01:00.283511 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 10:01:00.290263 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 10:01:00.293514 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 10:01:00.296636 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 10:01:00.303822 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 10:01:00.306720 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4438 10:01:00.310301 Total UI for P1: 0, mck2ui 16
4439 10:01:00.313239 best dqsien dly found for B1: ( 0, 13, 10)
4440 10:01:00.316536 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 10:01:00.320204 Total UI for P1: 0, mck2ui 16
4442 10:01:00.322977 best dqsien dly found for B0: ( 0, 13, 12)
4443 10:01:00.326462 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4444 10:01:00.329590 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4445 10:01:00.329671
4446 10:01:00.336236 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4447 10:01:00.339667 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4448 10:01:00.342828 [Gating] SW calibration Done
4449 10:01:00.342909 ==
4450 10:01:00.346036 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 10:01:00.349257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 10:01:00.349339 ==
4453 10:01:00.349403 RX Vref Scan: 0
4454 10:01:00.352820
4455 10:01:00.352925 RX Vref 0 -> 0, step: 1
4456 10:01:00.353017
4457 10:01:00.355875 RX Delay -230 -> 252, step: 16
4458 10:01:00.359474 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4459 10:01:00.365679 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4460 10:01:00.368964 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4461 10:01:00.372082 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4462 10:01:00.375714 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4463 10:01:00.382375 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4464 10:01:00.385535 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4465 10:01:00.388563 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4466 10:01:00.392052 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4467 10:01:00.395426 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4468 10:01:00.401948 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4469 10:01:00.405083 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4470 10:01:00.408512 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4471 10:01:00.411884 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4472 10:01:00.418803 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4473 10:01:00.422018 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4474 10:01:00.422114 ==
4475 10:01:00.425301 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 10:01:00.428510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 10:01:00.428582 ==
4478 10:01:00.431521 DQS Delay:
4479 10:01:00.431616 DQS0 = 0, DQS1 = 0
4480 10:01:00.435115 DQM Delay:
4481 10:01:00.435210 DQM0 = 41, DQM1 = 38
4482 10:01:00.435306 DQ Delay:
4483 10:01:00.438160 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4484 10:01:00.441065 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4485 10:01:00.444517 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4486 10:01:00.448114 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4487 10:01:00.448183
4488 10:01:00.451062
4489 10:01:00.451130 ==
4490 10:01:00.454861 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 10:01:00.457892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 10:01:00.458031 ==
4493 10:01:00.458118
4494 10:01:00.458202
4495 10:01:00.460968 TX Vref Scan disable
4496 10:01:00.461036 == TX Byte 0 ==
4497 10:01:00.467931 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4498 10:01:00.470837 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4499 10:01:00.470939 == TX Byte 1 ==
4500 10:01:00.477763 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4501 10:01:00.480869 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4502 10:01:00.480940 ==
4503 10:01:00.483888 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 10:01:00.487626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 10:01:00.487699 ==
4506 10:01:00.487761
4507 10:01:00.487818
4508 10:01:00.490474 TX Vref Scan disable
4509 10:01:00.493880 == TX Byte 0 ==
4510 10:01:00.497346 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4511 10:01:00.503956 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4512 10:01:00.504037 == TX Byte 1 ==
4513 10:01:00.507054 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4514 10:01:00.513735 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4515 10:01:00.513833
4516 10:01:00.513927 [DATLAT]
4517 10:01:00.513988 Freq=600, CH1 RK0
4518 10:01:00.514045
4519 10:01:00.517298 DATLAT Default: 0x9
4520 10:01:00.517367 0, 0xFFFF, sum = 0
4521 10:01:00.520765 1, 0xFFFF, sum = 0
4522 10:01:00.524101 2, 0xFFFF, sum = 0
4523 10:01:00.524170 3, 0xFFFF, sum = 0
4524 10:01:00.526763 4, 0xFFFF, sum = 0
4525 10:01:00.526859 5, 0xFFFF, sum = 0
4526 10:01:00.530665 6, 0xFFFF, sum = 0
4527 10:01:00.530769 7, 0xFFFF, sum = 0
4528 10:01:00.533343 8, 0x0, sum = 1
4529 10:01:00.533439 9, 0x0, sum = 2
4530 10:01:00.537126 10, 0x0, sum = 3
4531 10:01:00.537197 11, 0x0, sum = 4
4532 10:01:00.537257 best_step = 9
4533 10:01:00.537313
4534 10:01:00.539805 ==
4535 10:01:00.543429 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 10:01:00.546564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 10:01:00.546659 ==
4538 10:01:00.546747 RX Vref Scan: 1
4539 10:01:00.546837
4540 10:01:00.549992 RX Vref 0 -> 0, step: 1
4541 10:01:00.550061
4542 10:01:00.553552 RX Delay -179 -> 252, step: 8
4543 10:01:00.553621
4544 10:01:00.556339 Set Vref, RX VrefLevel [Byte0]: 52
4545 10:01:00.559765 [Byte1]: 49
4546 10:01:00.559860
4547 10:01:00.562909 Final RX Vref Byte 0 = 52 to rank0
4548 10:01:00.566495 Final RX Vref Byte 1 = 49 to rank0
4549 10:01:00.569780 Final RX Vref Byte 0 = 52 to rank1
4550 10:01:00.573297 Final RX Vref Byte 1 = 49 to rank1==
4551 10:01:00.575929 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 10:01:00.579504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 10:01:00.582725 ==
4554 10:01:00.582827 DQS Delay:
4555 10:01:00.582915 DQS0 = 0, DQS1 = 0
4556 10:01:00.586315 DQM Delay:
4557 10:01:00.586409 DQM0 = 41, DQM1 = 34
4558 10:01:00.589715 DQ Delay:
4559 10:01:00.592962 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =40
4560 10:01:00.593048 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4561 10:01:00.596065 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4562 10:01:00.602605 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4563 10:01:00.602702
4564 10:01:00.602799
4565 10:01:00.609120 [DQSOSCAuto] RK0, (LSB)MR18= 0x334c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4566 10:01:00.612426 CH1 RK0: MR19=808, MR18=334C
4567 10:01:00.618659 CH1_RK0: MR19=0x808, MR18=0x334C, DQSOSC=395, MR23=63, INC=168, DEC=112
4568 10:01:00.618761
4569 10:01:00.622536 ----->DramcWriteLeveling(PI) begin...
4570 10:01:00.622633 ==
4571 10:01:00.625534 Dram Type= 6, Freq= 0, CH_1, rank 1
4572 10:01:00.629069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 10:01:00.629139 ==
4574 10:01:00.632272 Write leveling (Byte 0): 30 => 30
4575 10:01:00.635628 Write leveling (Byte 1): 30 => 30
4576 10:01:00.638532 DramcWriteLeveling(PI) end<-----
4577 10:01:00.638627
4578 10:01:00.638722 ==
4579 10:01:00.641841 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 10:01:00.645404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 10:01:00.648822 ==
4582 10:01:00.648892 [Gating] SW mode calibration
4583 10:01:00.658746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4584 10:01:00.662106 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4585 10:01:00.665160 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 10:01:00.671632 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4587 10:01:00.674727 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4588 10:01:00.678652 0 9 12 | B1->B0 | 3131 2c2c | 0 1 | (0 1) (1 0)
4589 10:01:00.684734 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 10:01:00.687826 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 10:01:00.691579 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 10:01:00.697802 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 10:01:00.701090 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 10:01:00.704729 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 10:01:00.711168 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4596 10:01:00.714389 0 10 12 | B1->B0 | 3030 3d3d | 0 0 | (0 0) (0 0)
4597 10:01:00.717544 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 10:01:00.724512 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 10:01:00.727837 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 10:01:00.730955 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 10:01:00.737870 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 10:01:00.741116 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 10:01:00.743994 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 10:01:00.750506 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4605 10:01:00.754192 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 10:01:00.757048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 10:01:00.764203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 10:01:00.767259 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 10:01:00.770592 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 10:01:00.776852 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 10:01:00.780472 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 10:01:00.783620 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 10:01:00.790210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 10:01:00.793523 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 10:01:00.796866 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 10:01:00.803125 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 10:01:00.806437 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 10:01:00.809750 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 10:01:00.816106 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4620 10:01:00.819492 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4621 10:01:00.822948 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 10:01:00.826474 Total UI for P1: 0, mck2ui 16
4623 10:01:00.829570 best dqsien dly found for B0: ( 0, 13, 10)
4624 10:01:00.832824 Total UI for P1: 0, mck2ui 16
4625 10:01:00.836217 best dqsien dly found for B1: ( 0, 13, 14)
4626 10:01:00.839529 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4627 10:01:00.846090 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4628 10:01:00.846162
4629 10:01:00.849456 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4630 10:01:00.852728 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4631 10:01:00.855714 [Gating] SW calibration Done
4632 10:01:00.855816 ==
4633 10:01:00.859050 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 10:01:00.862530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 10:01:00.862625 ==
4636 10:01:00.865786 RX Vref Scan: 0
4637 10:01:00.865855
4638 10:01:00.865914 RX Vref 0 -> 0, step: 1
4639 10:01:00.865971
4640 10:01:00.868847 RX Delay -230 -> 252, step: 16
4641 10:01:00.872617 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4642 10:01:00.878871 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4643 10:01:00.882765 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4644 10:01:00.885388 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4645 10:01:00.889053 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4646 10:01:00.895239 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4647 10:01:00.898913 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4648 10:01:00.902689 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4649 10:01:00.905164 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4650 10:01:00.908514 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4651 10:01:00.915193 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4652 10:01:00.918648 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4653 10:01:00.922255 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4654 10:01:00.925561 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4655 10:01:00.931700 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4656 10:01:00.934728 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4657 10:01:00.934825 ==
4658 10:01:00.938074 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 10:01:00.941547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 10:01:00.941618 ==
4661 10:01:00.945125 DQS Delay:
4662 10:01:00.945194 DQS0 = 0, DQS1 = 0
4663 10:01:00.948462 DQM Delay:
4664 10:01:00.948553 DQM0 = 41, DQM1 = 39
4665 10:01:00.951227 DQ Delay:
4666 10:01:00.951322 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4667 10:01:00.954794 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4668 10:01:00.958067 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4669 10:01:00.961315 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4670 10:01:00.961386
4671 10:01:00.964727
4672 10:01:00.964821 ==
4673 10:01:00.968034 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 10:01:00.971706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 10:01:00.971791 ==
4676 10:01:00.971879
4677 10:01:00.971955
4678 10:01:00.974395 TX Vref Scan disable
4679 10:01:00.974493 == TX Byte 0 ==
4680 10:01:00.981038 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4681 10:01:00.984321 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4682 10:01:00.984393 == TX Byte 1 ==
4683 10:01:00.990674 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4684 10:01:00.994525 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4685 10:01:00.994627 ==
4686 10:01:00.997308 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 10:01:01.000824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 10:01:01.000899 ==
4689 10:01:01.000961
4690 10:01:01.001049
4691 10:01:01.003743 TX Vref Scan disable
4692 10:01:01.007172 == TX Byte 0 ==
4693 10:01:01.010801 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4694 10:01:01.017374 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4695 10:01:01.017476 == TX Byte 1 ==
4696 10:01:01.020276 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4697 10:01:01.027238 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4698 10:01:01.027311
4699 10:01:01.027372 [DATLAT]
4700 10:01:01.027459 Freq=600, CH1 RK1
4701 10:01:01.027544
4702 10:01:01.030354 DATLAT Default: 0x9
4703 10:01:01.033560 0, 0xFFFF, sum = 0
4704 10:01:01.033659 1, 0xFFFF, sum = 0
4705 10:01:01.036835 2, 0xFFFF, sum = 0
4706 10:01:01.036911 3, 0xFFFF, sum = 0
4707 10:01:01.040476 4, 0xFFFF, sum = 0
4708 10:01:01.040548 5, 0xFFFF, sum = 0
4709 10:01:01.043639 6, 0xFFFF, sum = 0
4710 10:01:01.043736 7, 0xFFFF, sum = 0
4711 10:01:01.047014 8, 0x0, sum = 1
4712 10:01:01.047086 9, 0x0, sum = 2
4713 10:01:01.050149 10, 0x0, sum = 3
4714 10:01:01.050220 11, 0x0, sum = 4
4715 10:01:01.050281 best_step = 9
4716 10:01:01.050341
4717 10:01:01.053258 ==
4718 10:01:01.057256 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 10:01:01.060052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 10:01:01.060121 ==
4721 10:01:01.060182 RX Vref Scan: 0
4722 10:01:01.060238
4723 10:01:01.063444 RX Vref 0 -> 0, step: 1
4724 10:01:01.063541
4725 10:01:01.066736 RX Delay -179 -> 252, step: 8
4726 10:01:01.073464 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4727 10:01:01.076221 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4728 10:01:01.079703 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4729 10:01:01.082754 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4730 10:01:01.086352 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4731 10:01:01.093230 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4732 10:01:01.096109 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4733 10:01:01.099378 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4734 10:01:01.102674 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4735 10:01:01.109064 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4736 10:01:01.112563 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4737 10:01:01.115847 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4738 10:01:01.119193 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4739 10:01:01.125982 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4740 10:01:01.128823 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4741 10:01:01.132063 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4742 10:01:01.132138 ==
4743 10:01:01.135823 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 10:01:01.142078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 10:01:01.142152 ==
4746 10:01:01.142212 DQS Delay:
4747 10:01:01.142271 DQS0 = 0, DQS1 = 0
4748 10:01:01.145430 DQM Delay:
4749 10:01:01.145498 DQM0 = 37, DQM1 = 34
4750 10:01:01.148685 DQ Delay:
4751 10:01:01.151714 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4752 10:01:01.155104 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4753 10:01:01.158629 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4754 10:01:01.162331 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4755 10:01:01.162413
4756 10:01:01.162505
4757 10:01:01.168445 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4758 10:01:01.172324 CH1 RK1: MR19=808, MR18=3B5F
4759 10:01:01.178385 CH1_RK1: MR19=0x808, MR18=0x3B5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4760 10:01:01.181578 [RxdqsGatingPostProcess] freq 600
4761 10:01:01.185325 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4762 10:01:01.188257 Pre-setting of DQS Precalculation
4763 10:01:01.195117 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4764 10:01:01.201707 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4765 10:01:01.207969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4766 10:01:01.208056
4767 10:01:01.208120
4768 10:01:01.211429 [Calibration Summary] 1200 Mbps
4769 10:01:01.211546 CH 0, Rank 0
4770 10:01:01.214699 SW Impedance : PASS
4771 10:01:01.218248 DUTY Scan : NO K
4772 10:01:01.218355 ZQ Calibration : PASS
4773 10:01:01.221170 Jitter Meter : NO K
4774 10:01:01.224395 CBT Training : PASS
4775 10:01:01.224467 Write leveling : PASS
4776 10:01:01.227614 RX DQS gating : PASS
4777 10:01:01.231124 RX DQ/DQS(RDDQC) : PASS
4778 10:01:01.231207 TX DQ/DQS : PASS
4779 10:01:01.234428 RX DATLAT : PASS
4780 10:01:01.238146 RX DQ/DQS(Engine): PASS
4781 10:01:01.238235 TX OE : NO K
4782 10:01:01.240732 All Pass.
4783 10:01:01.240803
4784 10:01:01.240881 CH 0, Rank 1
4785 10:01:01.244039 SW Impedance : PASS
4786 10:01:01.244129 DUTY Scan : NO K
4787 10:01:01.247300 ZQ Calibration : PASS
4788 10:01:01.251056 Jitter Meter : NO K
4789 10:01:01.251156 CBT Training : PASS
4790 10:01:01.254705 Write leveling : PASS
4791 10:01:01.257193 RX DQS gating : PASS
4792 10:01:01.257268 RX DQ/DQS(RDDQC) : PASS
4793 10:01:01.260843 TX DQ/DQS : PASS
4794 10:01:01.263611 RX DATLAT : PASS
4795 10:01:01.263694 RX DQ/DQS(Engine): PASS
4796 10:01:01.267042 TX OE : NO K
4797 10:01:01.267138 All Pass.
4798 10:01:01.267235
4799 10:01:01.270402 CH 1, Rank 0
4800 10:01:01.270501 SW Impedance : PASS
4801 10:01:01.273662 DUTY Scan : NO K
4802 10:01:01.277174 ZQ Calibration : PASS
4803 10:01:01.277255 Jitter Meter : NO K
4804 10:01:01.280085 CBT Training : PASS
4805 10:01:01.283461 Write leveling : PASS
4806 10:01:01.283531 RX DQS gating : PASS
4807 10:01:01.286724 RX DQ/DQS(RDDQC) : PASS
4808 10:01:01.290131 TX DQ/DQS : PASS
4809 10:01:01.290205 RX DATLAT : PASS
4810 10:01:01.293651 RX DQ/DQS(Engine): PASS
4811 10:01:01.296995 TX OE : NO K
4812 10:01:01.297067 All Pass.
4813 10:01:01.297143
4814 10:01:01.297202 CH 1, Rank 1
4815 10:01:01.299829 SW Impedance : PASS
4816 10:01:01.303083 DUTY Scan : NO K
4817 10:01:01.303179 ZQ Calibration : PASS
4818 10:01:01.306539 Jitter Meter : NO K
4819 10:01:01.306635 CBT Training : PASS
4820 10:01:01.309995 Write leveling : PASS
4821 10:01:01.313051 RX DQS gating : PASS
4822 10:01:01.313121 RX DQ/DQS(RDDQC) : PASS
4823 10:01:01.316544 TX DQ/DQS : PASS
4824 10:01:01.319870 RX DATLAT : PASS
4825 10:01:01.319972 RX DQ/DQS(Engine): PASS
4826 10:01:01.323245 TX OE : NO K
4827 10:01:01.323340 All Pass.
4828 10:01:01.323436
4829 10:01:01.326514 DramC Write-DBI off
4830 10:01:01.329585 PER_BANK_REFRESH: Hybrid Mode
4831 10:01:01.329684 TX_TRACKING: ON
4832 10:01:01.339789 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4833 10:01:01.343025 [FAST_K] Save calibration result to emmc
4834 10:01:01.346053 dramc_set_vcore_voltage set vcore to 662500
4835 10:01:01.349681 Read voltage for 933, 3
4836 10:01:01.349762 Vio18 = 0
4837 10:01:01.352845 Vcore = 662500
4838 10:01:01.352925 Vdram = 0
4839 10:01:01.352989 Vddq = 0
4840 10:01:01.353048 Vmddr = 0
4841 10:01:01.359236 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4842 10:01:01.365774 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4843 10:01:01.365855 MEM_TYPE=3, freq_sel=17
4844 10:01:01.369128 sv_algorithm_assistance_LP4_1600
4845 10:01:01.372699 ============ PULL DRAM RESETB DOWN ============
4846 10:01:01.379193 ========== PULL DRAM RESETB DOWN end =========
4847 10:01:01.382226 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4848 10:01:01.385490 ===================================
4849 10:01:01.389158 LPDDR4 DRAM CONFIGURATION
4850 10:01:01.392568 ===================================
4851 10:01:01.392649 EX_ROW_EN[0] = 0x0
4852 10:01:01.395329 EX_ROW_EN[1] = 0x0
4853 10:01:01.395409 LP4Y_EN = 0x0
4854 10:01:01.398663 WORK_FSP = 0x0
4855 10:01:01.398743 WL = 0x3
4856 10:01:01.402035 RL = 0x3
4857 10:01:01.405590 BL = 0x2
4858 10:01:01.405671 RPST = 0x0
4859 10:01:01.408750 RD_PRE = 0x0
4860 10:01:01.408830 WR_PRE = 0x1
4861 10:01:01.411792 WR_PST = 0x0
4862 10:01:01.411872 DBI_WR = 0x0
4863 10:01:01.415385 DBI_RD = 0x0
4864 10:01:01.415465 OTF = 0x1
4865 10:01:01.418628 ===================================
4866 10:01:01.421807 ===================================
4867 10:01:01.425191 ANA top config
4868 10:01:01.428413 ===================================
4869 10:01:01.428494 DLL_ASYNC_EN = 0
4870 10:01:01.431654 ALL_SLAVE_EN = 1
4871 10:01:01.435382 NEW_RANK_MODE = 1
4872 10:01:01.438801 DLL_IDLE_MODE = 1
4873 10:01:01.441614 LP45_APHY_COMB_EN = 1
4874 10:01:01.441694 TX_ODT_DIS = 1
4875 10:01:01.444768 NEW_8X_MODE = 1
4876 10:01:01.448040 ===================================
4877 10:01:01.451657 ===================================
4878 10:01:01.454873 data_rate = 1866
4879 10:01:01.458404 CKR = 1
4880 10:01:01.461347 DQ_P2S_RATIO = 8
4881 10:01:01.464271 ===================================
4882 10:01:01.468013 CA_P2S_RATIO = 8
4883 10:01:01.468094 DQ_CA_OPEN = 0
4884 10:01:01.471237 DQ_SEMI_OPEN = 0
4885 10:01:01.474430 CA_SEMI_OPEN = 0
4886 10:01:01.478040 CA_FULL_RATE = 0
4887 10:01:01.481446 DQ_CKDIV4_EN = 1
4888 10:01:01.484697 CA_CKDIV4_EN = 1
4889 10:01:01.484778 CA_PREDIV_EN = 0
4890 10:01:01.487359 PH8_DLY = 0
4891 10:01:01.491190 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4892 10:01:01.493986 DQ_AAMCK_DIV = 4
4893 10:01:01.497454 CA_AAMCK_DIV = 4
4894 10:01:01.500753 CA_ADMCK_DIV = 4
4895 10:01:01.500834 DQ_TRACK_CA_EN = 0
4896 10:01:01.503812 CA_PICK = 933
4897 10:01:01.507500 CA_MCKIO = 933
4898 10:01:01.510798 MCKIO_SEMI = 0
4899 10:01:01.513670 PLL_FREQ = 3732
4900 10:01:01.517264 DQ_UI_PI_RATIO = 32
4901 10:01:01.520352 CA_UI_PI_RATIO = 0
4902 10:01:01.523653 ===================================
4903 10:01:01.526914 ===================================
4904 10:01:01.526995 memory_type:LPDDR4
4905 10:01:01.530212 GP_NUM : 10
4906 10:01:01.533442 SRAM_EN : 1
4907 10:01:01.533536 MD32_EN : 0
4908 10:01:01.536797 ===================================
4909 10:01:01.540193 [ANA_INIT] >>>>>>>>>>>>>>
4910 10:01:01.543373 <<<<<< [CONFIGURE PHASE]: ANA_TX
4911 10:01:01.546991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4912 10:01:01.549968 ===================================
4913 10:01:01.553090 data_rate = 1866,PCW = 0X8f00
4914 10:01:01.556793 ===================================
4915 10:01:01.560070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4916 10:01:01.563602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4917 10:01:01.569524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4918 10:01:01.576949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4919 10:01:01.579669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4920 10:01:01.582893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4921 10:01:01.582992 [ANA_INIT] flow start
4922 10:01:01.586361 [ANA_INIT] PLL >>>>>>>>
4923 10:01:01.589752 [ANA_INIT] PLL <<<<<<<<
4924 10:01:01.589829 [ANA_INIT] MIDPI >>>>>>>>
4925 10:01:01.593016 [ANA_INIT] MIDPI <<<<<<<<
4926 10:01:01.596311 [ANA_INIT] DLL >>>>>>>>
4927 10:01:01.596383 [ANA_INIT] flow end
4928 10:01:01.602395 ============ LP4 DIFF to SE enter ============
4929 10:01:01.606020 ============ LP4 DIFF to SE exit ============
4930 10:01:01.609341 [ANA_INIT] <<<<<<<<<<<<<
4931 10:01:01.612408 [Flow] Enable top DCM control >>>>>
4932 10:01:01.615798 [Flow] Enable top DCM control <<<<<
4933 10:01:01.615876 Enable DLL master slave shuffle
4934 10:01:01.622378 ==============================================================
4935 10:01:01.625677 Gating Mode config
4936 10:01:01.628915 ==============================================================
4937 10:01:01.632353 Config description:
4938 10:01:01.641911 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4939 10:01:01.648757 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4940 10:01:01.651832 SELPH_MODE 0: By rank 1: By Phase
4941 10:01:01.658379 ==============================================================
4942 10:01:01.661656 GAT_TRACK_EN = 1
4943 10:01:01.665189 RX_GATING_MODE = 2
4944 10:01:01.669015 RX_GATING_TRACK_MODE = 2
4945 10:01:01.672019 SELPH_MODE = 1
4946 10:01:01.675400 PICG_EARLY_EN = 1
4947 10:01:01.678179 VALID_LAT_VALUE = 1
4948 10:01:01.681645 ==============================================================
4949 10:01:01.684916 Enter into Gating configuration >>>>
4950 10:01:01.688135 Exit from Gating configuration <<<<
4951 10:01:01.691785 Enter into DVFS_PRE_config >>>>>
4952 10:01:01.704828 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4953 10:01:01.704911 Exit from DVFS_PRE_config <<<<<
4954 10:01:01.708201 Enter into PICG configuration >>>>
4955 10:01:01.711667 Exit from PICG configuration <<<<
4956 10:01:01.715040 [RX_INPUT] configuration >>>>>
4957 10:01:01.717703 [RX_INPUT] configuration <<<<<
4958 10:01:01.724543 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4959 10:01:01.727657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4960 10:01:01.734313 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4961 10:01:01.741051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4962 10:01:01.748058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4963 10:01:01.754456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4964 10:01:01.757213 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4965 10:01:01.760946 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4966 10:01:01.764228 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4967 10:01:01.770721 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4968 10:01:01.773700 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4969 10:01:01.777136 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4970 10:01:01.780874 ===================================
4971 10:01:01.783392 LPDDR4 DRAM CONFIGURATION
4972 10:01:01.786999 ===================================
4973 10:01:01.790225 EX_ROW_EN[0] = 0x0
4974 10:01:01.790302 EX_ROW_EN[1] = 0x0
4975 10:01:01.793755 LP4Y_EN = 0x0
4976 10:01:01.793824 WORK_FSP = 0x0
4977 10:01:01.797380 WL = 0x3
4978 10:01:01.797467 RL = 0x3
4979 10:01:01.800247 BL = 0x2
4980 10:01:01.800321 RPST = 0x0
4981 10:01:01.803351 RD_PRE = 0x0
4982 10:01:01.803435 WR_PRE = 0x1
4983 10:01:01.807357 WR_PST = 0x0
4984 10:01:01.807429 DBI_WR = 0x0
4985 10:01:01.810030 DBI_RD = 0x0
4986 10:01:01.813288 OTF = 0x1
4987 10:01:01.816940 ===================================
4988 10:01:01.820078 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4989 10:01:01.823298 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4990 10:01:01.826427 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4991 10:01:01.829901 ===================================
4992 10:01:01.833376 LPDDR4 DRAM CONFIGURATION
4993 10:01:01.836675 ===================================
4994 10:01:01.839511 EX_ROW_EN[0] = 0x10
4995 10:01:01.839605 EX_ROW_EN[1] = 0x0
4996 10:01:01.842835 LP4Y_EN = 0x0
4997 10:01:01.842906 WORK_FSP = 0x0
4998 10:01:01.845946 WL = 0x3
4999 10:01:01.846014 RL = 0x3
5000 10:01:01.849251 BL = 0x2
5001 10:01:01.849316 RPST = 0x0
5002 10:01:01.852751 RD_PRE = 0x0
5003 10:01:01.856046 WR_PRE = 0x1
5004 10:01:01.856113 WR_PST = 0x0
5005 10:01:01.859123 DBI_WR = 0x0
5006 10:01:01.859194 DBI_RD = 0x0
5007 10:01:01.863037 OTF = 0x1
5008 10:01:01.865924 ===================================
5009 10:01:01.869377 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5010 10:01:01.874764 nWR fixed to 30
5011 10:01:01.877879 [ModeRegInit_LP4] CH0 RK0
5012 10:01:01.877977 [ModeRegInit_LP4] CH0 RK1
5013 10:01:01.881153 [ModeRegInit_LP4] CH1 RK0
5014 10:01:01.884405 [ModeRegInit_LP4] CH1 RK1
5015 10:01:01.884505 match AC timing 9
5016 10:01:01.891440 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5017 10:01:01.895696 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5018 10:01:01.898560 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5019 10:01:01.904229 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5020 10:01:01.907643 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5021 10:01:01.907746 ==
5022 10:01:01.911448 Dram Type= 6, Freq= 0, CH_0, rank 0
5023 10:01:01.914179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5024 10:01:01.914253 ==
5025 10:01:01.920806 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5026 10:01:01.927402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5027 10:01:01.930677 [CA 0] Center 37 (7~68) winsize 62
5028 10:01:01.934209 [CA 1] Center 37 (7~68) winsize 62
5029 10:01:01.937462 [CA 2] Center 34 (4~64) winsize 61
5030 10:01:01.940608 [CA 3] Center 34 (4~65) winsize 62
5031 10:01:01.943874 [CA 4] Center 32 (2~63) winsize 62
5032 10:01:01.947351 [CA 5] Center 32 (2~63) winsize 62
5033 10:01:01.947419
5034 10:01:01.950718 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5035 10:01:01.950812
5036 10:01:01.953867 [CATrainingPosCal] consider 1 rank data
5037 10:01:01.956939 u2DelayCellTimex100 = 270/100 ps
5038 10:01:01.960358 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5039 10:01:01.963758 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5040 10:01:01.967028 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5041 10:01:01.973798 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5042 10:01:01.977187 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5043 10:01:01.980098 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5044 10:01:01.980176
5045 10:01:01.983419 CA PerBit enable=1, Macro0, CA PI delay=32
5046 10:01:01.983494
5047 10:01:01.986643 [CBTSetCACLKResult] CA Dly = 32
5048 10:01:01.986744 CS Dly: 6 (0~37)
5049 10:01:01.986832 ==
5050 10:01:01.990308 Dram Type= 6, Freq= 0, CH_0, rank 1
5051 10:01:01.996766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 10:01:01.996844 ==
5053 10:01:02.000080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 10:01:02.006430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5055 10:01:02.009945 [CA 0] Center 37 (7~68) winsize 62
5056 10:01:02.012982 [CA 1] Center 37 (7~68) winsize 62
5057 10:01:02.016449 [CA 2] Center 34 (4~65) winsize 62
5058 10:01:02.019691 [CA 3] Center 34 (4~65) winsize 62
5059 10:01:02.023329 [CA 4] Center 33 (3~64) winsize 62
5060 10:01:02.026566 [CA 5] Center 32 (2~63) winsize 62
5061 10:01:02.026667
5062 10:01:02.029808 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5063 10:01:02.029884
5064 10:01:02.033096 [CATrainingPosCal] consider 2 rank data
5065 10:01:02.036387 u2DelayCellTimex100 = 270/100 ps
5066 10:01:02.039733 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5067 10:01:02.046091 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5068 10:01:02.049596 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5069 10:01:02.052859 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5070 10:01:02.056367 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5071 10:01:02.059167 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5072 10:01:02.059237
5073 10:01:02.062387 CA PerBit enable=1, Macro0, CA PI delay=32
5074 10:01:02.062491
5075 10:01:02.065712 [CBTSetCACLKResult] CA Dly = 32
5076 10:01:02.069489 CS Dly: 6 (0~38)
5077 10:01:02.069561
5078 10:01:02.072581 ----->DramcWriteLeveling(PI) begin...
5079 10:01:02.072654 ==
5080 10:01:02.076130 Dram Type= 6, Freq= 0, CH_0, rank 0
5081 10:01:02.079182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 10:01:02.079267 ==
5083 10:01:02.082519 Write leveling (Byte 0): 29 => 29
5084 10:01:02.085631 Write leveling (Byte 1): 26 => 26
5085 10:01:02.088936 DramcWriteLeveling(PI) end<-----
5086 10:01:02.089008
5087 10:01:02.089068 ==
5088 10:01:02.092726 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 10:01:02.095313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 10:01:02.095430 ==
5091 10:01:02.098750 [Gating] SW mode calibration
5092 10:01:02.105467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5093 10:01:02.112332 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5094 10:01:02.115531 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
5095 10:01:02.118575 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5096 10:01:02.125437 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 10:01:02.128552 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 10:01:02.135740 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 10:01:02.138250 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 10:01:02.141782 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5101 10:01:02.148509 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
5102 10:01:02.151697 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5103 10:01:02.154685 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 10:01:02.161575 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 10:01:02.164897 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 10:01:02.168162 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 10:01:02.174777 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 10:01:02.177994 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 10:01:02.181036 0 15 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5110 10:01:02.187798 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5111 10:01:02.191234 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 10:01:02.194346 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 10:01:02.200863 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 10:01:02.203781 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 10:01:02.207467 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 10:01:02.213844 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 10:01:02.217448 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5118 10:01:02.220808 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5119 10:01:02.227044 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 10:01:02.230272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 10:01:02.233634 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 10:01:02.240144 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 10:01:02.243594 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 10:01:02.247173 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 10:01:02.253594 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 10:01:02.256925 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 10:01:02.260115 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 10:01:02.266451 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 10:01:02.269750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 10:01:02.273379 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 10:01:02.279657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 10:01:02.283138 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5133 10:01:02.286413 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5134 10:01:02.292722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5135 10:01:02.292826 Total UI for P1: 0, mck2ui 16
5136 10:01:02.299960 best dqsien dly found for B0: ( 1, 2, 26)
5137 10:01:02.302534 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5138 10:01:02.305946 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 10:01:02.309494 Total UI for P1: 0, mck2ui 16
5140 10:01:02.313109 best dqsien dly found for B1: ( 1, 3, 2)
5141 10:01:02.316493 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5142 10:01:02.319656 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5143 10:01:02.319736
5144 10:01:02.322684 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5145 10:01:02.329452 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5146 10:01:02.329533 [Gating] SW calibration Done
5147 10:01:02.329596 ==
5148 10:01:02.332737 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 10:01:02.339012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 10:01:02.339117 ==
5151 10:01:02.339213 RX Vref Scan: 0
5152 10:01:02.339301
5153 10:01:02.342318 RX Vref 0 -> 0, step: 1
5154 10:01:02.342391
5155 10:01:02.345765 RX Delay -80 -> 252, step: 8
5156 10:01:02.349027 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5157 10:01:02.352221 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5158 10:01:02.355345 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5159 10:01:02.362236 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5160 10:01:02.365546 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5161 10:01:02.369089 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5162 10:01:02.372201 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5163 10:01:02.375729 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5164 10:01:02.378769 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5165 10:01:02.385600 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5166 10:01:02.388462 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5167 10:01:02.391965 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5168 10:01:02.395236 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5169 10:01:02.398808 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5170 10:01:02.405283 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5171 10:01:02.408031 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5172 10:01:02.408109 ==
5173 10:01:02.411525 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 10:01:02.414819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 10:01:02.414918 ==
5176 10:01:02.417818 DQS Delay:
5177 10:01:02.417913 DQS0 = 0, DQS1 = 0
5178 10:01:02.418003 DQM Delay:
5179 10:01:02.421177 DQM0 = 100, DQM1 = 88
5180 10:01:02.421274 DQ Delay:
5181 10:01:02.424942 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5182 10:01:02.427783 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =111
5183 10:01:02.431083 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5184 10:01:02.434288 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5185 10:01:02.434368
5186 10:01:02.434432
5187 10:01:02.434490 ==
5188 10:01:02.438140 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 10:01:02.444230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 10:01:02.444312 ==
5191 10:01:02.444375
5192 10:01:02.444435
5193 10:01:02.447432 TX Vref Scan disable
5194 10:01:02.447512 == TX Byte 0 ==
5195 10:01:02.451169 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5196 10:01:02.457748 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5197 10:01:02.457829 == TX Byte 1 ==
5198 10:01:02.461083 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5199 10:01:02.467384 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5200 10:01:02.467464 ==
5201 10:01:02.470859 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 10:01:02.473961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 10:01:02.474041 ==
5204 10:01:02.474104
5205 10:01:02.474163
5206 10:01:02.477413 TX Vref Scan disable
5207 10:01:02.480776 == TX Byte 0 ==
5208 10:01:02.484174 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5209 10:01:02.487784 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5210 10:01:02.490355 == TX Byte 1 ==
5211 10:01:02.493943 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5212 10:01:02.497163 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5213 10:01:02.497243
5214 10:01:02.500884 [DATLAT]
5215 10:01:02.500964 Freq=933, CH0 RK0
5216 10:01:02.501028
5217 10:01:02.503483 DATLAT Default: 0xd
5218 10:01:02.503563 0, 0xFFFF, sum = 0
5219 10:01:02.507194 1, 0xFFFF, sum = 0
5220 10:01:02.507274 2, 0xFFFF, sum = 0
5221 10:01:02.510760 3, 0xFFFF, sum = 0
5222 10:01:02.510842 4, 0xFFFF, sum = 0
5223 10:01:02.513278 5, 0xFFFF, sum = 0
5224 10:01:02.513359 6, 0xFFFF, sum = 0
5225 10:01:02.516701 7, 0xFFFF, sum = 0
5226 10:01:02.516782 8, 0xFFFF, sum = 0
5227 10:01:02.520081 9, 0xFFFF, sum = 0
5228 10:01:02.520162 10, 0x0, sum = 1
5229 10:01:02.523474 11, 0x0, sum = 2
5230 10:01:02.523555 12, 0x0, sum = 3
5231 10:01:02.526641 13, 0x0, sum = 4
5232 10:01:02.526736 best_step = 11
5233 10:01:02.526799
5234 10:01:02.526858 ==
5235 10:01:02.530044 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 10:01:02.536799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 10:01:02.536890 ==
5238 10:01:02.536955 RX Vref Scan: 1
5239 10:01:02.537015
5240 10:01:02.539847 RX Vref 0 -> 0, step: 1
5241 10:01:02.539978
5242 10:01:02.542846 RX Delay -61 -> 252, step: 4
5243 10:01:02.542935
5244 10:01:02.546188 Set Vref, RX VrefLevel [Byte0]: 57
5245 10:01:02.549441 [Byte1]: 59
5246 10:01:02.549521
5247 10:01:02.552860 Final RX Vref Byte 0 = 57 to rank0
5248 10:01:02.556600 Final RX Vref Byte 1 = 59 to rank0
5249 10:01:02.559561 Final RX Vref Byte 0 = 57 to rank1
5250 10:01:02.562546 Final RX Vref Byte 1 = 59 to rank1==
5251 10:01:02.566159 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 10:01:02.569241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 10:01:02.572719 ==
5254 10:01:02.572800 DQS Delay:
5255 10:01:02.572863 DQS0 = 0, DQS1 = 0
5256 10:01:02.576162 DQM Delay:
5257 10:01:02.576242 DQM0 = 99, DQM1 = 88
5258 10:01:02.576306 DQ Delay:
5259 10:01:02.579820 DQ0 =102, DQ1 =98, DQ2 =92, DQ3 =94
5260 10:01:02.582372 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =106
5261 10:01:02.585656 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =84
5262 10:01:02.592872 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5263 10:01:02.592953
5264 10:01:02.593016
5265 10:01:02.599028 [DQSOSCAuto] RK0, (LSB)MR18= 0x1913, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5266 10:01:02.602590 CH0 RK0: MR19=505, MR18=1913
5267 10:01:02.609281 CH0_RK0: MR19=0x505, MR18=0x1913, DQSOSC=413, MR23=63, INC=63, DEC=42
5268 10:01:02.609362
5269 10:01:02.612616 ----->DramcWriteLeveling(PI) begin...
5270 10:01:02.612698 ==
5271 10:01:02.615670 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 10:01:02.618509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 10:01:02.618589 ==
5274 10:01:02.622007 Write leveling (Byte 0): 33 => 33
5275 10:01:02.625276 Write leveling (Byte 1): 28 => 28
5276 10:01:02.628516 DramcWriteLeveling(PI) end<-----
5277 10:01:02.628596
5278 10:01:02.628659 ==
5279 10:01:02.632153 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 10:01:02.635153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 10:01:02.635243 ==
5282 10:01:02.638657 [Gating] SW mode calibration
5283 10:01:02.645069 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5284 10:01:02.651638 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5285 10:01:02.654888 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5286 10:01:02.661681 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 10:01:02.665008 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 10:01:02.668055 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 10:01:02.674979 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 10:01:02.678215 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 10:01:02.681353 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5292 10:01:02.688138 0 14 28 | B1->B0 | 3333 2828 | 1 1 | (1 1) (1 0)
5293 10:01:02.691345 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5294 10:01:02.694506 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 10:01:02.701327 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 10:01:02.704152 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 10:01:02.707508 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 10:01:02.714225 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 10:01:02.717381 0 15 24 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5300 10:01:02.720778 0 15 28 | B1->B0 | 2d2d 4141 | 1 1 | (0 0) (0 0)
5301 10:01:02.727836 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 10:01:02.731283 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 10:01:02.733749 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 10:01:02.740410 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 10:01:02.743860 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 10:01:02.747065 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 10:01:02.753701 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 10:01:02.757234 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5309 10:01:02.760237 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5310 10:01:02.767273 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 10:01:02.769939 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 10:01:02.773262 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 10:01:02.780069 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 10:01:02.783007 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 10:01:02.786834 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 10:01:02.793040 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 10:01:02.797078 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 10:01:02.799784 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 10:01:02.806505 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 10:01:02.809446 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 10:01:02.812871 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 10:01:02.819262 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 10:01:02.822651 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5324 10:01:02.826253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5325 10:01:02.832778 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5326 10:01:02.835521 Total UI for P1: 0, mck2ui 16
5327 10:01:02.839031 best dqsien dly found for B0: ( 1, 2, 26)
5328 10:01:02.842598 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5329 10:01:02.845709 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 10:01:02.849052 Total UI for P1: 0, mck2ui 16
5331 10:01:02.852232 best dqsien dly found for B1: ( 1, 3, 2)
5332 10:01:02.856556 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5333 10:01:02.862007 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5334 10:01:02.862087
5335 10:01:02.865420 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5336 10:01:02.868791 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5337 10:01:02.872072 [Gating] SW calibration Done
5338 10:01:02.872152 ==
5339 10:01:02.875654 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 10:01:02.878681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 10:01:02.878762 ==
5342 10:01:02.878825 RX Vref Scan: 0
5343 10:01:02.881857
5344 10:01:02.881937 RX Vref 0 -> 0, step: 1
5345 10:01:02.882002
5346 10:01:02.885079 RX Delay -80 -> 252, step: 8
5347 10:01:02.888394 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5348 10:01:02.891658 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5349 10:01:02.898630 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5350 10:01:02.901545 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5351 10:01:02.904549 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5352 10:01:02.908358 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5353 10:01:02.911653 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5354 10:01:02.914457 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5355 10:01:02.921286 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5356 10:01:02.924672 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5357 10:01:02.927944 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5358 10:01:02.930775 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5359 10:01:02.934967 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5360 10:01:02.940809 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5361 10:01:02.944235 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5362 10:01:02.947803 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5363 10:01:02.947883 ==
5364 10:01:02.951263 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 10:01:02.954337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 10:01:02.954417 ==
5367 10:01:02.957419 DQS Delay:
5368 10:01:02.957499 DQS0 = 0, DQS1 = 0
5369 10:01:02.960566 DQM Delay:
5370 10:01:02.960646 DQM0 = 98, DQM1 = 90
5371 10:01:02.960709 DQ Delay:
5372 10:01:02.964164 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5373 10:01:02.967541 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =111
5374 10:01:02.971200 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5375 10:01:02.973894 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5376 10:01:02.973974
5377 10:01:02.974037
5378 10:01:02.977868 ==
5379 10:01:02.980529 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 10:01:02.983887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 10:01:02.984007 ==
5382 10:01:02.984071
5383 10:01:02.984129
5384 10:01:02.986883 TX Vref Scan disable
5385 10:01:02.986962 == TX Byte 0 ==
5386 10:01:02.993967 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5387 10:01:02.996749 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5388 10:01:02.996832 == TX Byte 1 ==
5389 10:01:03.003782 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5390 10:01:03.006765 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5391 10:01:03.006849 ==
5392 10:01:03.010110 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 10:01:03.013368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 10:01:03.013452 ==
5395 10:01:03.013538
5396 10:01:03.013636
5397 10:01:03.016365 TX Vref Scan disable
5398 10:01:03.020026 == TX Byte 0 ==
5399 10:01:03.022907 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5400 10:01:03.026297 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5401 10:01:03.030031 == TX Byte 1 ==
5402 10:01:03.032886 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5403 10:01:03.036376 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5404 10:01:03.036474
5405 10:01:03.039980 [DATLAT]
5406 10:01:03.040070 Freq=933, CH0 RK1
5407 10:01:03.040156
5408 10:01:03.042840 DATLAT Default: 0xb
5409 10:01:03.042923 0, 0xFFFF, sum = 0
5410 10:01:03.046054 1, 0xFFFF, sum = 0
5411 10:01:03.046139 2, 0xFFFF, sum = 0
5412 10:01:03.049533 3, 0xFFFF, sum = 0
5413 10:01:03.049618 4, 0xFFFF, sum = 0
5414 10:01:03.052814 5, 0xFFFF, sum = 0
5415 10:01:03.052899 6, 0xFFFF, sum = 0
5416 10:01:03.056157 7, 0xFFFF, sum = 0
5417 10:01:03.059327 8, 0xFFFF, sum = 0
5418 10:01:03.059412 9, 0xFFFF, sum = 0
5419 10:01:03.062770 10, 0x0, sum = 1
5420 10:01:03.062854 11, 0x0, sum = 2
5421 10:01:03.062940 12, 0x0, sum = 3
5422 10:01:03.066120 13, 0x0, sum = 4
5423 10:01:03.066204 best_step = 11
5424 10:01:03.066289
5425 10:01:03.069214 ==
5426 10:01:03.069297 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 10:01:03.076307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 10:01:03.076391 ==
5429 10:01:03.076477 RX Vref Scan: 0
5430 10:01:03.076557
5431 10:01:03.079406 RX Vref 0 -> 0, step: 1
5432 10:01:03.079489
5433 10:01:03.082727 RX Delay -53 -> 252, step: 4
5434 10:01:03.086156 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5435 10:01:03.092770 iDelay=199, Bit 1, Center 100 (11 ~ 190) 180
5436 10:01:03.095464 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5437 10:01:03.098715 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5438 10:01:03.102463 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5439 10:01:03.105552 iDelay=199, Bit 5, Center 88 (-1 ~ 178) 180
5440 10:01:03.112083 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5441 10:01:03.115744 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5442 10:01:03.118951 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5443 10:01:03.121994 iDelay=199, Bit 9, Center 76 (-9 ~ 162) 172
5444 10:01:03.125374 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5445 10:01:03.128692 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5446 10:01:03.135033 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5447 10:01:03.138478 iDelay=199, Bit 13, Center 94 (3 ~ 186) 184
5448 10:01:03.142004 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5449 10:01:03.145213 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5450 10:01:03.145295 ==
5451 10:01:03.148539 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 10:01:03.154688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 10:01:03.154770 ==
5454 10:01:03.154835 DQS Delay:
5455 10:01:03.154896 DQS0 = 0, DQS1 = 0
5456 10:01:03.158328 DQM Delay:
5457 10:01:03.158409 DQM0 = 97, DQM1 = 88
5458 10:01:03.161370 DQ Delay:
5459 10:01:03.164802 DQ0 =96, DQ1 =100, DQ2 =92, DQ3 =94
5460 10:01:03.167962 DQ4 =100, DQ5 =88, DQ6 =108, DQ7 =104
5461 10:01:03.171291 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5462 10:01:03.175174 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =94
5463 10:01:03.175255
5464 10:01:03.175320
5465 10:01:03.181701 [DQSOSCAuto] RK1, (LSB)MR18= 0x1816, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5466 10:01:03.184960 CH0 RK1: MR19=505, MR18=1816
5467 10:01:03.191091 CH0_RK1: MR19=0x505, MR18=0x1816, DQSOSC=414, MR23=63, INC=63, DEC=42
5468 10:01:03.194360 [RxdqsGatingPostProcess] freq 933
5469 10:01:03.197924 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5470 10:01:03.201170 best DQS0 dly(2T, 0.5T) = (0, 10)
5471 10:01:03.204449 best DQS1 dly(2T, 0.5T) = (0, 11)
5472 10:01:03.207797 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5473 10:01:03.211195 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5474 10:01:03.214270 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 10:01:03.217469 best DQS1 dly(2T, 0.5T) = (0, 11)
5476 10:01:03.221069 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 10:01:03.224170 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5478 10:01:03.227863 Pre-setting of DQS Precalculation
5479 10:01:03.233872 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5480 10:01:03.233954 ==
5481 10:01:03.237383 Dram Type= 6, Freq= 0, CH_1, rank 0
5482 10:01:03.240348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 10:01:03.240430 ==
5484 10:01:03.247367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5485 10:01:03.250366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5486 10:01:03.254502 [CA 0] Center 36 (6~67) winsize 62
5487 10:01:03.257849 [CA 1] Center 36 (6~67) winsize 62
5488 10:01:03.261218 [CA 2] Center 34 (4~65) winsize 62
5489 10:01:03.264451 [CA 3] Center 34 (4~65) winsize 62
5490 10:01:03.267767 [CA 4] Center 34 (4~65) winsize 62
5491 10:01:03.270783 [CA 5] Center 33 (3~64) winsize 62
5492 10:01:03.270864
5493 10:01:03.274001 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5494 10:01:03.274083
5495 10:01:03.277415 [CATrainingPosCal] consider 1 rank data
5496 10:01:03.280881 u2DelayCellTimex100 = 270/100 ps
5497 10:01:03.284389 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5498 10:01:03.290929 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5499 10:01:03.294163 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5500 10:01:03.297036 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5501 10:01:03.300657 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5502 10:01:03.303932 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5503 10:01:03.304028
5504 10:01:03.307238 CA PerBit enable=1, Macro0, CA PI delay=33
5505 10:01:03.307320
5506 10:01:03.310249 [CBTSetCACLKResult] CA Dly = 33
5507 10:01:03.313626 CS Dly: 5 (0~36)
5508 10:01:03.313707 ==
5509 10:01:03.317238 Dram Type= 6, Freq= 0, CH_1, rank 1
5510 10:01:03.320513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 10:01:03.320595 ==
5512 10:01:03.326726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5513 10:01:03.330212 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5514 10:01:03.334662 [CA 0] Center 36 (6~66) winsize 61
5515 10:01:03.337665 [CA 1] Center 36 (6~67) winsize 62
5516 10:01:03.340757 [CA 2] Center 34 (4~65) winsize 62
5517 10:01:03.344397 [CA 3] Center 33 (3~64) winsize 62
5518 10:01:03.347383 [CA 4] Center 34 (4~64) winsize 61
5519 10:01:03.350636 [CA 5] Center 33 (3~64) winsize 62
5520 10:01:03.350717
5521 10:01:03.353899 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5522 10:01:03.353980
5523 10:01:03.357375 [CATrainingPosCal] consider 2 rank data
5524 10:01:03.360586 u2DelayCellTimex100 = 270/100 ps
5525 10:01:03.364050 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5526 10:01:03.371093 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5527 10:01:03.373962 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5528 10:01:03.377056 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5529 10:01:03.380542 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5530 10:01:03.384145 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5531 10:01:03.384226
5532 10:01:03.387745 CA PerBit enable=1, Macro0, CA PI delay=33
5533 10:01:03.387826
5534 10:01:03.390552 [CBTSetCACLKResult] CA Dly = 33
5535 10:01:03.393691 CS Dly: 6 (0~38)
5536 10:01:03.393772
5537 10:01:03.397275 ----->DramcWriteLeveling(PI) begin...
5538 10:01:03.397358 ==
5539 10:01:03.400673 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 10:01:03.403435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 10:01:03.403517 ==
5542 10:01:03.407164 Write leveling (Byte 0): 28 => 28
5543 10:01:03.410044 Write leveling (Byte 1): 30 => 30
5544 10:01:03.413591 DramcWriteLeveling(PI) end<-----
5545 10:01:03.413672
5546 10:01:03.413736 ==
5547 10:01:03.416879 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 10:01:03.420521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 10:01:03.420604 ==
5550 10:01:03.423331 [Gating] SW mode calibration
5551 10:01:03.429938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5552 10:01:03.436529 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5553 10:01:03.439828 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 10:01:03.446120 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 10:01:03.449441 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 10:01:03.452821 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 10:01:03.459454 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 10:01:03.462807 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 10:01:03.465962 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
5560 10:01:03.472423 0 14 28 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (1 0)
5561 10:01:03.475814 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5562 10:01:03.479199 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 10:01:03.485688 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 10:01:03.488816 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 10:01:03.492087 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 10:01:03.499063 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 10:01:03.502289 0 15 24 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
5568 10:01:03.505507 0 15 28 | B1->B0 | 3636 3c3c | 1 0 | (0 0) (0 0)
5569 10:01:03.512372 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 10:01:03.515229 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 10:01:03.518800 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 10:01:03.525134 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 10:01:03.528639 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 10:01:03.531847 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 10:01:03.538575 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5576 10:01:03.541491 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5577 10:01:03.544774 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 10:01:03.551611 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 10:01:03.554945 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 10:01:03.558002 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 10:01:03.564742 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 10:01:03.568054 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 10:01:03.571199 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 10:01:03.577849 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 10:01:03.581179 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 10:01:03.584779 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 10:01:03.591291 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 10:01:03.594654 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 10:01:03.598079 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 10:01:03.604650 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 10:01:03.608298 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5592 10:01:03.611100 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5593 10:01:03.614120 Total UI for P1: 0, mck2ui 16
5594 10:01:03.617995 best dqsien dly found for B0: ( 1, 2, 26)
5595 10:01:03.624053 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5596 10:01:03.627501 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 10:01:03.630694 Total UI for P1: 0, mck2ui 16
5598 10:01:03.634082 best dqsien dly found for B1: ( 1, 2, 28)
5599 10:01:03.637421 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5600 10:01:03.641050 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5601 10:01:03.641121
5602 10:01:03.643950 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5603 10:01:03.647499 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5604 10:01:03.650510 [Gating] SW calibration Done
5605 10:01:03.650580 ==
5606 10:01:03.654074 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 10:01:03.657164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 10:01:03.657243 ==
5609 10:01:03.660247 RX Vref Scan: 0
5610 10:01:03.660318
5611 10:01:03.663848 RX Vref 0 -> 0, step: 1
5612 10:01:03.663965
5613 10:01:03.664028 RX Delay -80 -> 252, step: 8
5614 10:01:03.670405 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5615 10:01:03.673858 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5616 10:01:03.677192 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5617 10:01:03.680250 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5618 10:01:03.683397 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5619 10:01:03.686777 iDelay=208, Bit 5, Center 103 (8 ~ 199) 192
5620 10:01:03.693524 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5621 10:01:03.696850 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5622 10:01:03.700383 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5623 10:01:03.703826 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5624 10:01:03.706969 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5625 10:01:03.710742 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5626 10:01:03.716989 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5627 10:01:03.720009 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5628 10:01:03.723448 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5629 10:01:03.726713 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5630 10:01:03.726786 ==
5631 10:01:03.730087 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 10:01:03.736646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 10:01:03.736723 ==
5634 10:01:03.736786 DQS Delay:
5635 10:01:03.740072 DQS0 = 0, DQS1 = 0
5636 10:01:03.740145 DQM Delay:
5637 10:01:03.740205 DQM0 = 99, DQM1 = 96
5638 10:01:03.743311 DQ Delay:
5639 10:01:03.746633 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5640 10:01:03.749867 DQ4 =99, DQ5 =103, DQ6 =111, DQ7 =95
5641 10:01:03.753195 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5642 10:01:03.756391 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5643 10:01:03.756489
5644 10:01:03.756562
5645 10:01:03.756621 ==
5646 10:01:03.759791 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 10:01:03.762975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 10:01:03.763055 ==
5649 10:01:03.763134
5650 10:01:03.763206
5651 10:01:03.766603 TX Vref Scan disable
5652 10:01:03.769236 == TX Byte 0 ==
5653 10:01:03.772548 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5654 10:01:03.776100 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5655 10:01:03.779026 == TX Byte 1 ==
5656 10:01:03.782454 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5657 10:01:03.785938 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5658 10:01:03.786012 ==
5659 10:01:03.789017 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 10:01:03.795553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 10:01:03.795631 ==
5662 10:01:03.795694
5663 10:01:03.795754
5664 10:01:03.795817 TX Vref Scan disable
5665 10:01:03.799969 == TX Byte 0 ==
5666 10:01:03.803665 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5667 10:01:03.810131 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5668 10:01:03.810207 == TX Byte 1 ==
5669 10:01:03.813400 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5670 10:01:03.819832 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5671 10:01:03.819943
5672 10:01:03.820020 [DATLAT]
5673 10:01:03.820079 Freq=933, CH1 RK0
5674 10:01:03.820137
5675 10:01:03.822986 DATLAT Default: 0xd
5676 10:01:03.823057 0, 0xFFFF, sum = 0
5677 10:01:03.826330 1, 0xFFFF, sum = 0
5678 10:01:03.829690 2, 0xFFFF, sum = 0
5679 10:01:03.829764 3, 0xFFFF, sum = 0
5680 10:01:03.833064 4, 0xFFFF, sum = 0
5681 10:01:03.833141 5, 0xFFFF, sum = 0
5682 10:01:03.836265 6, 0xFFFF, sum = 0
5683 10:01:03.836357 7, 0xFFFF, sum = 0
5684 10:01:03.839587 8, 0xFFFF, sum = 0
5685 10:01:03.839684 9, 0xFFFF, sum = 0
5686 10:01:03.842999 10, 0x0, sum = 1
5687 10:01:03.843074 11, 0x0, sum = 2
5688 10:01:03.845918 12, 0x0, sum = 3
5689 10:01:03.845986 13, 0x0, sum = 4
5690 10:01:03.849578 best_step = 11
5691 10:01:03.849679
5692 10:01:03.849766 ==
5693 10:01:03.852885 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 10:01:03.856619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 10:01:03.856691 ==
5696 10:01:03.856753 RX Vref Scan: 1
5697 10:01:03.856810
5698 10:01:03.859252 RX Vref 0 -> 0, step: 1
5699 10:01:03.859316
5700 10:01:03.862491 RX Delay -53 -> 252, step: 4
5701 10:01:03.862560
5702 10:01:03.865682 Set Vref, RX VrefLevel [Byte0]: 52
5703 10:01:03.869076 [Byte1]: 49
5704 10:01:03.872533
5705 10:01:03.872605 Final RX Vref Byte 0 = 52 to rank0
5706 10:01:03.875834 Final RX Vref Byte 1 = 49 to rank0
5707 10:01:03.879000 Final RX Vref Byte 0 = 52 to rank1
5708 10:01:03.882187 Final RX Vref Byte 1 = 49 to rank1==
5709 10:01:03.885610 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 10:01:03.892541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 10:01:03.892621 ==
5712 10:01:03.892705 DQS Delay:
5713 10:01:03.895420 DQS0 = 0, DQS1 = 0
5714 10:01:03.895524 DQM Delay:
5715 10:01:03.895614 DQM0 = 98, DQM1 = 94
5716 10:01:03.898736 DQ Delay:
5717 10:01:03.902029 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5718 10:01:03.905312 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5719 10:01:03.908562 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5720 10:01:03.912104 DQ12 =104, DQ13 =104, DQ14 =100, DQ15 =102
5721 10:01:03.912181
5722 10:01:03.912243
5723 10:01:03.918342 [DQSOSCAuto] RK0, (LSB)MR18= 0x616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 420 ps
5724 10:01:03.921803 CH1 RK0: MR19=505, MR18=616
5725 10:01:03.928481 CH1_RK0: MR19=0x505, MR18=0x616, DQSOSC=414, MR23=63, INC=63, DEC=42
5726 10:01:03.928552
5727 10:01:03.932064 ----->DramcWriteLeveling(PI) begin...
5728 10:01:03.932132 ==
5729 10:01:03.935214 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 10:01:03.938636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 10:01:03.938707 ==
5732 10:01:03.941500 Write leveling (Byte 0): 26 => 26
5733 10:01:03.945127 Write leveling (Byte 1): 25 => 25
5734 10:01:03.948594 DramcWriteLeveling(PI) end<-----
5735 10:01:03.948665
5736 10:01:03.948725 ==
5737 10:01:03.951583 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 10:01:03.958030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 10:01:03.958104 ==
5740 10:01:03.958164 [Gating] SW mode calibration
5741 10:01:03.968025 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5742 10:01:03.971302 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5743 10:01:03.978054 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 10:01:03.981083 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 10:01:03.984377 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 10:01:03.991073 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 10:01:03.994377 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 10:01:03.997391 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 10:01:04.004332 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5750 10:01:04.007384 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5751 10:01:04.010387 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 10:01:04.017226 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 10:01:04.020609 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 10:01:04.023536 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 10:01:04.030403 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 10:01:04.033757 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 10:01:04.036991 0 15 24 | B1->B0 | 2b2b 3535 | 1 0 | (0 0) (0 0)
5758 10:01:04.043679 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5759 10:01:04.046528 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 10:01:04.050409 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 10:01:04.056707 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 10:01:04.060391 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 10:01:04.063406 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 10:01:04.069799 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 10:01:04.073165 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5766 10:01:04.076331 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5767 10:01:04.083084 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5768 10:01:04.086502 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 10:01:04.089839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 10:01:04.096486 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 10:01:04.099659 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 10:01:04.102720 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 10:01:04.109333 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 10:01:04.112561 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 10:01:04.116153 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 10:01:04.122466 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 10:01:04.126032 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 10:01:04.129471 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 10:01:04.135663 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 10:01:04.139046 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 10:01:04.142309 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5782 10:01:04.148969 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5783 10:01:04.151910 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 10:01:04.155725 Total UI for P1: 0, mck2ui 16
5785 10:01:04.158711 best dqsien dly found for B0: ( 1, 2, 26)
5786 10:01:04.161782 Total UI for P1: 0, mck2ui 16
5787 10:01:04.165328 best dqsien dly found for B1: ( 1, 2, 26)
5788 10:01:04.168294 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5789 10:01:04.171678 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5790 10:01:04.171759
5791 10:01:04.175333 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5792 10:01:04.178486 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5793 10:01:04.181821 [Gating] SW calibration Done
5794 10:01:04.181901 ==
5795 10:01:04.184869 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 10:01:04.191551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 10:01:04.191633 ==
5798 10:01:04.191697 RX Vref Scan: 0
5799 10:01:04.191756
5800 10:01:04.194679 RX Vref 0 -> 0, step: 1
5801 10:01:04.194760
5802 10:01:04.198079 RX Delay -80 -> 252, step: 8
5803 10:01:04.201543 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5804 10:01:04.204938 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5805 10:01:04.207838 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5806 10:01:04.211239 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5807 10:01:04.217873 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5808 10:01:04.221116 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5809 10:01:04.224200 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5810 10:01:04.227868 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5811 10:01:04.231083 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5812 10:01:04.234149 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5813 10:01:04.241038 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5814 10:01:04.244545 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5815 10:01:04.248068 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5816 10:01:04.250714 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5817 10:01:04.254074 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5818 10:01:04.260937 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5819 10:01:04.261018 ==
5820 10:01:04.263745 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 10:01:04.267409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 10:01:04.267490 ==
5823 10:01:04.267555 DQS Delay:
5824 10:01:04.270556 DQS0 = 0, DQS1 = 0
5825 10:01:04.270637 DQM Delay:
5826 10:01:04.274079 DQM0 = 97, DQM1 = 94
5827 10:01:04.274159 DQ Delay:
5828 10:01:04.277015 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5829 10:01:04.280211 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5830 10:01:04.283561 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5831 10:01:04.286772 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5832 10:01:04.286878
5833 10:01:04.286969
5834 10:01:04.287058 ==
5835 10:01:04.290603 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 10:01:04.296651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 10:01:04.296733 ==
5838 10:01:04.296797
5839 10:01:04.296857
5840 10:01:04.296914 TX Vref Scan disable
5841 10:01:04.300409 == TX Byte 0 ==
5842 10:01:04.303448 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5843 10:01:04.310462 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5844 10:01:04.310543 == TX Byte 1 ==
5845 10:01:04.313313 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5846 10:01:04.320453 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5847 10:01:04.320530 ==
5848 10:01:04.323627 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 10:01:04.326934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 10:01:04.327007 ==
5851 10:01:04.327068
5852 10:01:04.327125
5853 10:01:04.330014 TX Vref Scan disable
5854 10:01:04.330085 == TX Byte 0 ==
5855 10:01:04.336372 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5856 10:01:04.340054 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5857 10:01:04.343547 == TX Byte 1 ==
5858 10:01:04.346385 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5859 10:01:04.349960 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5860 10:01:04.350030
5861 10:01:04.350092 [DATLAT]
5862 10:01:04.353114 Freq=933, CH1 RK1
5863 10:01:04.353180
5864 10:01:04.353242 DATLAT Default: 0xb
5865 10:01:04.356556 0, 0xFFFF, sum = 0
5866 10:01:04.359400 1, 0xFFFF, sum = 0
5867 10:01:04.359470 2, 0xFFFF, sum = 0
5868 10:01:04.362795 3, 0xFFFF, sum = 0
5869 10:01:04.362874 4, 0xFFFF, sum = 0
5870 10:01:04.366144 5, 0xFFFF, sum = 0
5871 10:01:04.366214 6, 0xFFFF, sum = 0
5872 10:01:04.369411 7, 0xFFFF, sum = 0
5873 10:01:04.369478 8, 0xFFFF, sum = 0
5874 10:01:04.372930 9, 0xFFFF, sum = 0
5875 10:01:04.372997 10, 0x0, sum = 1
5876 10:01:04.376213 11, 0x0, sum = 2
5877 10:01:04.376281 12, 0x0, sum = 3
5878 10:01:04.379602 13, 0x0, sum = 4
5879 10:01:04.379678 best_step = 11
5880 10:01:04.379744
5881 10:01:04.379805 ==
5882 10:01:04.382572 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 10:01:04.385931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 10:01:04.389283 ==
5885 10:01:04.389363 RX Vref Scan: 0
5886 10:01:04.389428
5887 10:01:04.392768 RX Vref 0 -> 0, step: 1
5888 10:01:04.392853
5889 10:01:04.395757 RX Delay -61 -> 252, step: 4
5890 10:01:04.399068 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5891 10:01:04.402365 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5892 10:01:04.408969 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5893 10:01:04.412056 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5894 10:01:04.415433 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5895 10:01:04.418997 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5896 10:01:04.421968 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5897 10:01:04.425436 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5898 10:01:04.431894 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5899 10:01:04.434938 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5900 10:01:04.438428 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5901 10:01:04.442132 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5902 10:01:04.445092 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5903 10:01:04.451846 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5904 10:01:04.455151 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5905 10:01:04.458039 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5906 10:01:04.458120 ==
5907 10:01:04.461436 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 10:01:04.465015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 10:01:04.468028 ==
5910 10:01:04.468109 DQS Delay:
5911 10:01:04.468173 DQS0 = 0, DQS1 = 0
5912 10:01:04.471341 DQM Delay:
5913 10:01:04.471422 DQM0 = 97, DQM1 = 92
5914 10:01:04.474501 DQ Delay:
5915 10:01:04.478106 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =94
5916 10:01:04.481426 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5917 10:01:04.484650 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5918 10:01:04.487689 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =100
5919 10:01:04.487792
5920 10:01:04.487881
5921 10:01:04.494311 [DQSOSCAuto] RK1, (LSB)MR18= 0x1027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5922 10:01:04.497531 CH1 RK1: MR19=505, MR18=1027
5923 10:01:04.504159 CH1_RK1: MR19=0x505, MR18=0x1027, DQSOSC=409, MR23=63, INC=64, DEC=43
5924 10:01:04.507654 [RxdqsGatingPostProcess] freq 933
5925 10:01:04.510986 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5926 10:01:04.514423 best DQS0 dly(2T, 0.5T) = (0, 10)
5927 10:01:04.517419 best DQS1 dly(2T, 0.5T) = (0, 10)
5928 10:01:04.520545 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5929 10:01:04.523924 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5930 10:01:04.527036 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 10:01:04.530577 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 10:01:04.533995 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 10:01:04.537246 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 10:01:04.540183 Pre-setting of DQS Precalculation
5935 10:01:04.546994 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5936 10:01:04.553740 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5937 10:01:04.560527 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5938 10:01:04.560603
5939 10:01:04.560669
5940 10:01:04.563499 [Calibration Summary] 1866 Mbps
5941 10:01:04.563565 CH 0, Rank 0
5942 10:01:04.566786 SW Impedance : PASS
5943 10:01:04.569972 DUTY Scan : NO K
5944 10:01:04.570050 ZQ Calibration : PASS
5945 10:01:04.573631 Jitter Meter : NO K
5946 10:01:04.576954 CBT Training : PASS
5947 10:01:04.577029 Write leveling : PASS
5948 10:01:04.580348 RX DQS gating : PASS
5949 10:01:04.583539 RX DQ/DQS(RDDQC) : PASS
5950 10:01:04.583645 TX DQ/DQS : PASS
5951 10:01:04.586803 RX DATLAT : PASS
5952 10:01:04.586909 RX DQ/DQS(Engine): PASS
5953 10:01:04.590113 TX OE : NO K
5954 10:01:04.590213 All Pass.
5955 10:01:04.590293
5956 10:01:04.593470 CH 0, Rank 1
5957 10:01:04.593554 SW Impedance : PASS
5958 10:01:04.596534 DUTY Scan : NO K
5959 10:01:04.599901 ZQ Calibration : PASS
5960 10:01:04.600011 Jitter Meter : NO K
5961 10:01:04.602689 CBT Training : PASS
5962 10:01:04.606523 Write leveling : PASS
5963 10:01:04.606595 RX DQS gating : PASS
5964 10:01:04.609590 RX DQ/DQS(RDDQC) : PASS
5965 10:01:04.612812 TX DQ/DQS : PASS
5966 10:01:04.612914 RX DATLAT : PASS
5967 10:01:04.616319 RX DQ/DQS(Engine): PASS
5968 10:01:04.619489 TX OE : NO K
5969 10:01:04.619595 All Pass.
5970 10:01:04.619690
5971 10:01:04.619777 CH 1, Rank 0
5972 10:01:04.622641 SW Impedance : PASS
5973 10:01:04.625981 DUTY Scan : NO K
5974 10:01:04.626050 ZQ Calibration : PASS
5975 10:01:04.629479 Jitter Meter : NO K
5976 10:01:04.632404 CBT Training : PASS
5977 10:01:04.632473 Write leveling : PASS
5978 10:01:04.636171 RX DQS gating : PASS
5979 10:01:04.639353 RX DQ/DQS(RDDQC) : PASS
5980 10:01:04.639422 TX DQ/DQS : PASS
5981 10:01:04.642518 RX DATLAT : PASS
5982 10:01:04.645560 RX DQ/DQS(Engine): PASS
5983 10:01:04.645632 TX OE : NO K
5984 10:01:04.649042 All Pass.
5985 10:01:04.649110
5986 10:01:04.649169 CH 1, Rank 1
5987 10:01:04.651872 SW Impedance : PASS
5988 10:01:04.651990 DUTY Scan : NO K
5989 10:01:04.655513 ZQ Calibration : PASS
5990 10:01:04.658699 Jitter Meter : NO K
5991 10:01:04.658776 CBT Training : PASS
5992 10:01:04.661918 Write leveling : PASS
5993 10:01:04.665303 RX DQS gating : PASS
5994 10:01:04.665407 RX DQ/DQS(RDDQC) : PASS
5995 10:01:04.668676 TX DQ/DQS : PASS
5996 10:01:04.672027 RX DATLAT : PASS
5997 10:01:04.672096 RX DQ/DQS(Engine): PASS
5998 10:01:04.675252 TX OE : NO K
5999 10:01:04.675321 All Pass.
6000 10:01:04.675380
6001 10:01:04.678617 DramC Write-DBI off
6002 10:01:04.681612 PER_BANK_REFRESH: Hybrid Mode
6003 10:01:04.681682 TX_TRACKING: ON
6004 10:01:04.691899 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6005 10:01:04.694567 [FAST_K] Save calibration result to emmc
6006 10:01:04.698206 dramc_set_vcore_voltage set vcore to 650000
6007 10:01:04.701378 Read voltage for 400, 6
6008 10:01:04.701457 Vio18 = 0
6009 10:01:04.701522 Vcore = 650000
6010 10:01:04.704941 Vdram = 0
6011 10:01:04.705044 Vddq = 0
6012 10:01:04.705135 Vmddr = 0
6013 10:01:04.710966 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6014 10:01:04.714465 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6015 10:01:04.717673 MEM_TYPE=3, freq_sel=20
6016 10:01:04.721365 sv_algorithm_assistance_LP4_800
6017 10:01:04.724430 ============ PULL DRAM RESETB DOWN ============
6018 10:01:04.727592 ========== PULL DRAM RESETB DOWN end =========
6019 10:01:04.734131 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6020 10:01:04.737776 ===================================
6021 10:01:04.741049 LPDDR4 DRAM CONFIGURATION
6022 10:01:04.743826 ===================================
6023 10:01:04.743958 EX_ROW_EN[0] = 0x0
6024 10:01:04.748214 EX_ROW_EN[1] = 0x0
6025 10:01:04.748295 LP4Y_EN = 0x0
6026 10:01:04.750550 WORK_FSP = 0x0
6027 10:01:04.750630 WL = 0x2
6028 10:01:04.754105 RL = 0x2
6029 10:01:04.754185 BL = 0x2
6030 10:01:04.757624 RPST = 0x0
6031 10:01:04.760531 RD_PRE = 0x0
6032 10:01:04.760612 WR_PRE = 0x1
6033 10:01:04.763526 WR_PST = 0x0
6034 10:01:04.763606 DBI_WR = 0x0
6035 10:01:04.767378 DBI_RD = 0x0
6036 10:01:04.767459 OTF = 0x1
6037 10:01:04.770486 ===================================
6038 10:01:04.773449 ===================================
6039 10:01:04.776765 ANA top config
6040 10:01:04.780180 ===================================
6041 10:01:04.780261 DLL_ASYNC_EN = 0
6042 10:01:04.783608 ALL_SLAVE_EN = 1
6043 10:01:04.786786 NEW_RANK_MODE = 1
6044 10:01:04.790304 DLL_IDLE_MODE = 1
6045 10:01:04.790385 LP45_APHY_COMB_EN = 1
6046 10:01:04.793343 TX_ODT_DIS = 1
6047 10:01:04.796875 NEW_8X_MODE = 1
6048 10:01:04.800046 ===================================
6049 10:01:04.803660 ===================================
6050 10:01:04.806172 data_rate = 800
6051 10:01:04.810205 CKR = 1
6052 10:01:04.813090 DQ_P2S_RATIO = 4
6053 10:01:04.816349 ===================================
6054 10:01:04.816430 CA_P2S_RATIO = 4
6055 10:01:04.819762 DQ_CA_OPEN = 0
6056 10:01:04.822720 DQ_SEMI_OPEN = 1
6057 10:01:04.826680 CA_SEMI_OPEN = 1
6058 10:01:04.829680 CA_FULL_RATE = 0
6059 10:01:04.832707 DQ_CKDIV4_EN = 0
6060 10:01:04.832789 CA_CKDIV4_EN = 1
6061 10:01:04.836187 CA_PREDIV_EN = 0
6062 10:01:04.839448 PH8_DLY = 0
6063 10:01:04.842659 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6064 10:01:04.846203 DQ_AAMCK_DIV = 0
6065 10:01:04.849079 CA_AAMCK_DIV = 0
6066 10:01:04.852718 CA_ADMCK_DIV = 4
6067 10:01:04.852800 DQ_TRACK_CA_EN = 0
6068 10:01:04.855676 CA_PICK = 800
6069 10:01:04.859381 CA_MCKIO = 400
6070 10:01:04.862308 MCKIO_SEMI = 400
6071 10:01:04.865579 PLL_FREQ = 3016
6072 10:01:04.869091 DQ_UI_PI_RATIO = 32
6073 10:01:04.872167 CA_UI_PI_RATIO = 32
6074 10:01:04.875636 ===================================
6075 10:01:04.878918 ===================================
6076 10:01:04.879016 memory_type:LPDDR4
6077 10:01:04.882471 GP_NUM : 10
6078 10:01:04.885724 SRAM_EN : 1
6079 10:01:04.885835 MD32_EN : 0
6080 10:01:04.889008 ===================================
6081 10:01:04.892098 [ANA_INIT] >>>>>>>>>>>>>>
6082 10:01:04.895405 <<<<<< [CONFIGURE PHASE]: ANA_TX
6083 10:01:04.899052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6084 10:01:04.901750 ===================================
6085 10:01:04.905316 data_rate = 800,PCW = 0X7400
6086 10:01:04.908364 ===================================
6087 10:01:04.912035 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6088 10:01:04.915495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6089 10:01:04.928448 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 10:01:04.931799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6091 10:01:04.934940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6092 10:01:04.938640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6093 10:01:04.941524 [ANA_INIT] flow start
6094 10:01:04.944533 [ANA_INIT] PLL >>>>>>>>
6095 10:01:04.944625 [ANA_INIT] PLL <<<<<<<<
6096 10:01:04.948093 [ANA_INIT] MIDPI >>>>>>>>
6097 10:01:04.951730 [ANA_INIT] MIDPI <<<<<<<<
6098 10:01:04.951803 [ANA_INIT] DLL >>>>>>>>
6099 10:01:04.955156 [ANA_INIT] flow end
6100 10:01:04.958515 ============ LP4 DIFF to SE enter ============
6101 10:01:04.964549 ============ LP4 DIFF to SE exit ============
6102 10:01:04.964635 [ANA_INIT] <<<<<<<<<<<<<
6103 10:01:04.968263 [Flow] Enable top DCM control >>>>>
6104 10:01:04.971565 [Flow] Enable top DCM control <<<<<
6105 10:01:04.974903 Enable DLL master slave shuffle
6106 10:01:04.981330 ==============================================================
6107 10:01:04.981412 Gating Mode config
6108 10:01:04.988059 ==============================================================
6109 10:01:04.991201 Config description:
6110 10:01:05.001077 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6111 10:01:05.007820 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6112 10:01:05.011569 SELPH_MODE 0: By rank 1: By Phase
6113 10:01:05.017243 ==============================================================
6114 10:01:05.020793 GAT_TRACK_EN = 0
6115 10:01:05.024289 RX_GATING_MODE = 2
6116 10:01:05.024361 RX_GATING_TRACK_MODE = 2
6117 10:01:05.027350 SELPH_MODE = 1
6118 10:01:05.030558 PICG_EARLY_EN = 1
6119 10:01:05.034030 VALID_LAT_VALUE = 1
6120 10:01:05.040195 ==============================================================
6121 10:01:05.043615 Enter into Gating configuration >>>>
6122 10:01:05.047074 Exit from Gating configuration <<<<
6123 10:01:05.050616 Enter into DVFS_PRE_config >>>>>
6124 10:01:05.060756 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6125 10:01:05.063622 Exit from DVFS_PRE_config <<<<<
6126 10:01:05.066873 Enter into PICG configuration >>>>
6127 10:01:05.069985 Exit from PICG configuration <<<<
6128 10:01:05.073103 [RX_INPUT] configuration >>>>>
6129 10:01:05.076652 [RX_INPUT] configuration <<<<<
6130 10:01:05.079833 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6131 10:01:05.086502 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6132 10:01:05.093223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6133 10:01:05.099396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6134 10:01:05.106113 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 10:01:05.112917 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 10:01:05.115940 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6137 10:01:05.119241 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6138 10:01:05.122723 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6139 10:01:05.128908 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6140 10:01:05.132551 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6141 10:01:05.135893 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6142 10:01:05.138804 ===================================
6143 10:01:05.142380 LPDDR4 DRAM CONFIGURATION
6144 10:01:05.145733 ===================================
6145 10:01:05.145802 EX_ROW_EN[0] = 0x0
6146 10:01:05.149074 EX_ROW_EN[1] = 0x0
6147 10:01:05.149142 LP4Y_EN = 0x0
6148 10:01:05.152335 WORK_FSP = 0x0
6149 10:01:05.155630 WL = 0x2
6150 10:01:05.155696 RL = 0x2
6151 10:01:05.158584 BL = 0x2
6152 10:01:05.158650 RPST = 0x0
6153 10:01:05.162029 RD_PRE = 0x0
6154 10:01:05.162099 WR_PRE = 0x1
6155 10:01:05.165372 WR_PST = 0x0
6156 10:01:05.165440 DBI_WR = 0x0
6157 10:01:05.168618 DBI_RD = 0x0
6158 10:01:05.168688 OTF = 0x1
6159 10:01:05.171788 ===================================
6160 10:01:05.175052 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6161 10:01:05.181664 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6162 10:01:05.185204 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6163 10:01:05.188428 ===================================
6164 10:01:05.191577 LPDDR4 DRAM CONFIGURATION
6165 10:01:05.195161 ===================================
6166 10:01:05.195262 EX_ROW_EN[0] = 0x10
6167 10:01:05.198428 EX_ROW_EN[1] = 0x0
6168 10:01:05.201360 LP4Y_EN = 0x0
6169 10:01:05.201431 WORK_FSP = 0x0
6170 10:01:05.204903 WL = 0x2
6171 10:01:05.205008 RL = 0x2
6172 10:01:05.207985 BL = 0x2
6173 10:01:05.208088 RPST = 0x0
6174 10:01:05.211058 RD_PRE = 0x0
6175 10:01:05.211153 WR_PRE = 0x1
6176 10:01:05.214704 WR_PST = 0x0
6177 10:01:05.214801 DBI_WR = 0x0
6178 10:01:05.217828 DBI_RD = 0x0
6179 10:01:05.217902 OTF = 0x1
6180 10:01:05.221040 ===================================
6181 10:01:05.227705 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6182 10:01:05.232170 nWR fixed to 30
6183 10:01:05.235489 [ModeRegInit_LP4] CH0 RK0
6184 10:01:05.235587 [ModeRegInit_LP4] CH0 RK1
6185 10:01:05.239180 [ModeRegInit_LP4] CH1 RK0
6186 10:01:05.242344 [ModeRegInit_LP4] CH1 RK1
6187 10:01:05.242440 match AC timing 19
6188 10:01:05.248856 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6189 10:01:05.252149 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6190 10:01:05.255412 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6191 10:01:05.261846 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6192 10:01:05.265084 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6193 10:01:05.265151 ==
6194 10:01:05.268480 Dram Type= 6, Freq= 0, CH_0, rank 0
6195 10:01:05.271811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6196 10:01:05.271913 ==
6197 10:01:05.278414 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6198 10:01:05.284802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6199 10:01:05.288586 [CA 0] Center 36 (8~64) winsize 57
6200 10:01:05.291417 [CA 1] Center 36 (8~64) winsize 57
6201 10:01:05.294837 [CA 2] Center 36 (8~64) winsize 57
6202 10:01:05.298568 [CA 3] Center 36 (8~64) winsize 57
6203 10:01:05.301454 [CA 4] Center 36 (8~64) winsize 57
6204 10:01:05.304643 [CA 5] Center 36 (8~64) winsize 57
6205 10:01:05.304715
6206 10:01:05.307973 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6207 10:01:05.308042
6208 10:01:05.311701 [CATrainingPosCal] consider 1 rank data
6209 10:01:05.314727 u2DelayCellTimex100 = 270/100 ps
6210 10:01:05.318333 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 10:01:05.321132 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 10:01:05.324334 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 10:01:05.327858 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 10:01:05.330989 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 10:01:05.334662 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 10:01:05.334734
6217 10:01:05.341275 CA PerBit enable=1, Macro0, CA PI delay=36
6218 10:01:05.341349
6219 10:01:05.341413 [CBTSetCACLKResult] CA Dly = 36
6220 10:01:05.344132 CS Dly: 1 (0~32)
6221 10:01:05.344204 ==
6222 10:01:05.347704 Dram Type= 6, Freq= 0, CH_0, rank 1
6223 10:01:05.350963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 10:01:05.351032 ==
6225 10:01:05.357705 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 10:01:05.363842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6227 10:01:05.367213 [CA 0] Center 36 (8~64) winsize 57
6228 10:01:05.370627 [CA 1] Center 36 (8~64) winsize 57
6229 10:01:05.374172 [CA 2] Center 36 (8~64) winsize 57
6230 10:01:05.377384 [CA 3] Center 36 (8~64) winsize 57
6231 10:01:05.377484 [CA 4] Center 36 (8~64) winsize 57
6232 10:01:05.380777 [CA 5] Center 36 (8~64) winsize 57
6233 10:01:05.380877
6234 10:01:05.387681 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6235 10:01:05.387783
6236 10:01:05.390754 [CATrainingPosCal] consider 2 rank data
6237 10:01:05.394002 u2DelayCellTimex100 = 270/100 ps
6238 10:01:05.397050 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 10:01:05.400593 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 10:01:05.403607 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 10:01:05.406993 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 10:01:05.410374 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 10:01:05.413523 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 10:01:05.413619
6245 10:01:05.416954 CA PerBit enable=1, Macro0, CA PI delay=36
6246 10:01:05.417028
6247 10:01:05.420089 [CBTSetCACLKResult] CA Dly = 36
6248 10:01:05.423402 CS Dly: 1 (0~32)
6249 10:01:05.423500
6250 10:01:05.426774 ----->DramcWriteLeveling(PI) begin...
6251 10:01:05.426844 ==
6252 10:01:05.429872 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 10:01:05.433827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 10:01:05.433899 ==
6255 10:01:05.436677 Write leveling (Byte 0): 40 => 8
6256 10:01:05.440017 Write leveling (Byte 1): 40 => 8
6257 10:01:05.443599 DramcWriteLeveling(PI) end<-----
6258 10:01:05.443676
6259 10:01:05.443738 ==
6260 10:01:05.446751 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 10:01:05.449985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 10:01:05.450060 ==
6263 10:01:05.452844 [Gating] SW mode calibration
6264 10:01:05.459551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6265 10:01:05.466022 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6266 10:01:05.469589 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 10:01:05.476181 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 10:01:05.480113 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 10:01:05.482334 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 10:01:05.489238 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 10:01:05.492221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 10:01:05.496173 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 10:01:05.502469 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 10:01:05.505561 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 10:01:05.509107 Total UI for P1: 0, mck2ui 16
6276 10:01:05.512329 best dqsien dly found for B0: ( 0, 14, 24)
6277 10:01:05.515708 Total UI for P1: 0, mck2ui 16
6278 10:01:05.518857 best dqsien dly found for B1: ( 0, 14, 24)
6279 10:01:05.522159 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6280 10:01:05.525751 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6281 10:01:05.525823
6282 10:01:05.528776 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6283 10:01:05.532538 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 10:01:05.535199 [Gating] SW calibration Done
6285 10:01:05.535269 ==
6286 10:01:05.538928 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 10:01:05.545422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 10:01:05.545526 ==
6289 10:01:05.545616 RX Vref Scan: 0
6290 10:01:05.545702
6291 10:01:05.548663 RX Vref 0 -> 0, step: 1
6292 10:01:05.548737
6293 10:01:05.552225 RX Delay -410 -> 252, step: 16
6294 10:01:05.555005 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6295 10:01:05.558480 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6296 10:01:05.565117 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6297 10:01:05.568320 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6298 10:01:05.571680 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6299 10:01:05.574906 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6300 10:01:05.581810 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6301 10:01:05.584938 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6302 10:01:05.588449 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6303 10:01:05.591792 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6304 10:01:05.598079 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6305 10:01:05.601635 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6306 10:01:05.604751 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6307 10:01:05.608029 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6308 10:01:05.614645 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6309 10:01:05.617784 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6310 10:01:05.617863 ==
6311 10:01:05.621045 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 10:01:05.624643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 10:01:05.624712 ==
6314 10:01:05.627562 DQS Delay:
6315 10:01:05.627628 DQS0 = 35, DQS1 = 51
6316 10:01:05.631053 DQM Delay:
6317 10:01:05.631120 DQM0 = 4, DQM1 = 9
6318 10:01:05.631177 DQ Delay:
6319 10:01:05.634275 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6320 10:01:05.638107 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6321 10:01:05.641197 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6322 10:01:05.644034 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6323 10:01:05.644132
6324 10:01:05.644220
6325 10:01:05.644308 ==
6326 10:01:05.647395 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 10:01:05.654289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 10:01:05.654389 ==
6329 10:01:05.654477
6330 10:01:05.654567
6331 10:01:05.654652 TX Vref Scan disable
6332 10:01:05.657537 == TX Byte 0 ==
6333 10:01:05.660693 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 10:01:05.664086 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 10:01:05.667441 == TX Byte 1 ==
6336 10:01:05.670596 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6337 10:01:05.674152 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6338 10:01:05.674220 ==
6339 10:01:05.676903 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 10:01:05.683894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 10:01:05.684031 ==
6342 10:01:05.684123
6343 10:01:05.684208
6344 10:01:05.684291 TX Vref Scan disable
6345 10:01:05.687176 == TX Byte 0 ==
6346 10:01:05.690758 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 10:01:05.693636 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 10:01:05.697291 == TX Byte 1 ==
6349 10:01:05.700161 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 10:01:05.703700 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 10:01:05.703813
6352 10:01:05.706762 [DATLAT]
6353 10:01:05.706833 Freq=400, CH0 RK0
6354 10:01:05.706897
6355 10:01:05.709958 DATLAT Default: 0xf
6356 10:01:05.710025 0, 0xFFFF, sum = 0
6357 10:01:05.713305 1, 0xFFFF, sum = 0
6358 10:01:05.713380 2, 0xFFFF, sum = 0
6359 10:01:05.716863 3, 0xFFFF, sum = 0
6360 10:01:05.716970 4, 0xFFFF, sum = 0
6361 10:01:05.720242 5, 0xFFFF, sum = 0
6362 10:01:05.723106 6, 0xFFFF, sum = 0
6363 10:01:05.723175 7, 0xFFFF, sum = 0
6364 10:01:05.726501 8, 0xFFFF, sum = 0
6365 10:01:05.726574 9, 0xFFFF, sum = 0
6366 10:01:05.730188 10, 0xFFFF, sum = 0
6367 10:01:05.730290 11, 0xFFFF, sum = 0
6368 10:01:05.733080 12, 0xFFFF, sum = 0
6369 10:01:05.733150 13, 0x0, sum = 1
6370 10:01:05.736315 14, 0x0, sum = 2
6371 10:01:05.736410 15, 0x0, sum = 3
6372 10:01:05.739994 16, 0x0, sum = 4
6373 10:01:05.740098 best_step = 14
6374 10:01:05.740184
6375 10:01:05.740271 ==
6376 10:01:05.743031 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 10:01:05.746385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 10:01:05.746483 ==
6379 10:01:05.750046 RX Vref Scan: 1
6380 10:01:05.750125
6381 10:01:05.753635 RX Vref 0 -> 0, step: 1
6382 10:01:05.753704
6383 10:01:05.753762 RX Delay -343 -> 252, step: 8
6384 10:01:05.756231
6385 10:01:05.756302 Set Vref, RX VrefLevel [Byte0]: 57
6386 10:01:05.759593 [Byte1]: 59
6387 10:01:05.765641
6388 10:01:05.765711 Final RX Vref Byte 0 = 57 to rank0
6389 10:01:05.769072 Final RX Vref Byte 1 = 59 to rank0
6390 10:01:05.771822 Final RX Vref Byte 0 = 57 to rank1
6391 10:01:05.775301 Final RX Vref Byte 1 = 59 to rank1==
6392 10:01:05.778695 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 10:01:05.785504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 10:01:05.785607 ==
6395 10:01:05.785698 DQS Delay:
6396 10:01:05.788185 DQS0 = 44, DQS1 = 60
6397 10:01:05.788286 DQM Delay:
6398 10:01:05.788375 DQM0 = 11, DQM1 = 16
6399 10:01:05.791574 DQ Delay:
6400 10:01:05.795267 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6401 10:01:05.798136 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6402 10:01:05.798207 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6403 10:01:05.804958 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6404 10:01:05.805041
6405 10:01:05.805122
6406 10:01:05.811665 [DQSOSCAuto] RK0, (LSB)MR18= 0x9387, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6407 10:01:05.814974 CH0 RK0: MR19=C0C, MR18=9387
6408 10:01:05.821490 CH0_RK0: MR19=0xC0C, MR18=0x9387, DQSOSC=391, MR23=63, INC=386, DEC=257
6409 10:01:05.821572 ==
6410 10:01:05.824460 Dram Type= 6, Freq= 0, CH_0, rank 1
6411 10:01:05.827913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 10:01:05.828008 ==
6413 10:01:05.831359 [Gating] SW mode calibration
6414 10:01:05.837844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6415 10:01:05.844379 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6416 10:01:05.847697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6417 10:01:05.851303 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 10:01:05.857801 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 10:01:05.860676 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 10:01:05.864477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 10:01:05.870578 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 10:01:05.874274 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 10:01:05.877626 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 10:01:05.883801 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 10:01:05.886977 Total UI for P1: 0, mck2ui 16
6426 10:01:05.890553 best dqsien dly found for B0: ( 0, 14, 24)
6427 10:01:05.894026 Total UI for P1: 0, mck2ui 16
6428 10:01:05.896854 best dqsien dly found for B1: ( 0, 14, 24)
6429 10:01:05.900212 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6430 10:01:05.903842 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6431 10:01:05.903981
6432 10:01:05.907091 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6433 10:01:05.910262 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 10:01:05.913402 [Gating] SW calibration Done
6435 10:01:05.913473 ==
6436 10:01:05.916589 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 10:01:05.919806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 10:01:05.919908 ==
6439 10:01:05.923217 RX Vref Scan: 0
6440 10:01:05.923284
6441 10:01:05.926484 RX Vref 0 -> 0, step: 1
6442 10:01:05.926552
6443 10:01:05.930300 RX Delay -410 -> 252, step: 16
6444 10:01:05.933220 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6445 10:01:05.936498 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6446 10:01:05.939925 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6447 10:01:05.946254 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6448 10:01:05.949560 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6449 10:01:05.953202 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6450 10:01:05.956327 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6451 10:01:05.963250 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6452 10:01:05.966004 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6453 10:01:05.969243 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6454 10:01:05.972540 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6455 10:01:05.979152 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6456 10:01:05.982703 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6457 10:01:05.985761 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6458 10:01:05.992276 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6459 10:01:05.995643 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6460 10:01:05.995742 ==
6461 10:01:05.999134 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 10:01:06.002558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 10:01:06.002627 ==
6464 10:01:06.005858 DQS Delay:
6465 10:01:06.005931 DQS0 = 35, DQS1 = 59
6466 10:01:06.009028 DQM Delay:
6467 10:01:06.009127 DQM0 = 5, DQM1 = 16
6468 10:01:06.009215 DQ Delay:
6469 10:01:06.012733 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6470 10:01:06.015400 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6471 10:01:06.018648 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6472 10:01:06.022062 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6473 10:01:06.022143
6474 10:01:06.022207
6475 10:01:06.022266 ==
6476 10:01:06.025514 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 10:01:06.032168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 10:01:06.032250 ==
6479 10:01:06.032315
6480 10:01:06.032374
6481 10:01:06.032446 TX Vref Scan disable
6482 10:01:06.035449 == TX Byte 0 ==
6483 10:01:06.038333 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6484 10:01:06.041875 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6485 10:01:06.045106 == TX Byte 1 ==
6486 10:01:06.048346 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6487 10:01:06.051765 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6488 10:01:06.051846 ==
6489 10:01:06.055244 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 10:01:06.061814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 10:01:06.061895 ==
6492 10:01:06.061959
6493 10:01:06.062018
6494 10:01:06.062074 TX Vref Scan disable
6495 10:01:06.064733 == TX Byte 0 ==
6496 10:01:06.067814 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6497 10:01:06.071078 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6498 10:01:06.074717 == TX Byte 1 ==
6499 10:01:06.078135 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6500 10:01:06.081175 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6501 10:01:06.084891
6502 10:01:06.084971 [DATLAT]
6503 10:01:06.085035 Freq=400, CH0 RK1
6504 10:01:06.085094
6505 10:01:06.087547 DATLAT Default: 0xe
6506 10:01:06.087626 0, 0xFFFF, sum = 0
6507 10:01:06.091126 1, 0xFFFF, sum = 0
6508 10:01:06.091204 2, 0xFFFF, sum = 0
6509 10:01:06.094322 3, 0xFFFF, sum = 0
6510 10:01:06.094427 4, 0xFFFF, sum = 0
6511 10:01:06.097657 5, 0xFFFF, sum = 0
6512 10:01:06.100787 6, 0xFFFF, sum = 0
6513 10:01:06.100865 7, 0xFFFF, sum = 0
6514 10:01:06.104087 8, 0xFFFF, sum = 0
6515 10:01:06.104184 9, 0xFFFF, sum = 0
6516 10:01:06.107334 10, 0xFFFF, sum = 0
6517 10:01:06.107412 11, 0xFFFF, sum = 0
6518 10:01:06.110859 12, 0xFFFF, sum = 0
6519 10:01:06.110929 13, 0x0, sum = 1
6520 10:01:06.114419 14, 0x0, sum = 2
6521 10:01:06.114490 15, 0x0, sum = 3
6522 10:01:06.117452 16, 0x0, sum = 4
6523 10:01:06.117552 best_step = 14
6524 10:01:06.117640
6525 10:01:06.117733 ==
6526 10:01:06.120795 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 10:01:06.124196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 10:01:06.127507 ==
6529 10:01:06.127602 RX Vref Scan: 0
6530 10:01:06.127690
6531 10:01:06.130694 RX Vref 0 -> 0, step: 1
6532 10:01:06.130762
6533 10:01:06.133888 RX Delay -359 -> 252, step: 8
6534 10:01:06.140618 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6535 10:01:06.143810 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6536 10:01:06.146619 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6537 10:01:06.150148 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6538 10:01:06.156467 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6539 10:01:06.160583 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6540 10:01:06.163184 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6541 10:01:06.166695 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6542 10:01:06.173206 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6543 10:01:06.176332 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6544 10:01:06.179930 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6545 10:01:06.183091 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6546 10:01:06.189797 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6547 10:01:06.192805 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6548 10:01:06.196067 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6549 10:01:06.203198 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6550 10:01:06.203273 ==
6551 10:01:06.206181 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 10:01:06.209847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 10:01:06.209923 ==
6554 10:01:06.209986 DQS Delay:
6555 10:01:06.212798 DQS0 = 40, DQS1 = 60
6556 10:01:06.212874 DQM Delay:
6557 10:01:06.215871 DQM0 = 6, DQM1 = 15
6558 10:01:06.215993 DQ Delay:
6559 10:01:06.219402 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6560 10:01:06.222860 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6561 10:01:06.225792 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6562 10:01:06.229226 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6563 10:01:06.229299
6564 10:01:06.229360
6565 10:01:06.236137 [DQSOSCAuto] RK1, (LSB)MR18= 0x8780, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6566 10:01:06.238911 CH0 RK1: MR19=C0C, MR18=8780
6567 10:01:06.245495 CH0_RK1: MR19=0xC0C, MR18=0x8780, DQSOSC=392, MR23=63, INC=384, DEC=256
6568 10:01:06.249074 [RxdqsGatingPostProcess] freq 400
6569 10:01:06.255667 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6570 10:01:06.255767 best DQS0 dly(2T, 0.5T) = (0, 10)
6571 10:01:06.258890 best DQS1 dly(2T, 0.5T) = (0, 10)
6572 10:01:06.262183 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6573 10:01:06.265972 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6574 10:01:06.268866 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 10:01:06.272142 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 10:01:06.275132 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 10:01:06.278499 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 10:01:06.281667 Pre-setting of DQS Precalculation
6579 10:01:06.288546 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6580 10:01:06.288623 ==
6581 10:01:06.291781 Dram Type= 6, Freq= 0, CH_1, rank 0
6582 10:01:06.295650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 10:01:06.295756 ==
6584 10:01:06.301940 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6585 10:01:06.305375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6586 10:01:06.308514 [CA 0] Center 36 (8~64) winsize 57
6587 10:01:06.311675 [CA 1] Center 36 (8~64) winsize 57
6588 10:01:06.314751 [CA 2] Center 36 (8~64) winsize 57
6589 10:01:06.318251 [CA 3] Center 36 (8~64) winsize 57
6590 10:01:06.321631 [CA 4] Center 36 (8~64) winsize 57
6591 10:01:06.324594 [CA 5] Center 36 (8~64) winsize 57
6592 10:01:06.324664
6593 10:01:06.327962 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6594 10:01:06.328030
6595 10:01:06.331257 [CATrainingPosCal] consider 1 rank data
6596 10:01:06.334491 u2DelayCellTimex100 = 270/100 ps
6597 10:01:06.338200 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 10:01:06.344479 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 10:01:06.348070 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 10:01:06.351217 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 10:01:06.354815 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 10:01:06.357500 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 10:01:06.357569
6604 10:01:06.361326 CA PerBit enable=1, Macro0, CA PI delay=36
6605 10:01:06.361395
6606 10:01:06.364343 [CBTSetCACLKResult] CA Dly = 36
6607 10:01:06.364415 CS Dly: 1 (0~32)
6608 10:01:06.367536 ==
6609 10:01:06.371291 Dram Type= 6, Freq= 0, CH_1, rank 1
6610 10:01:06.374473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 10:01:06.374543 ==
6612 10:01:06.380781 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 10:01:06.384057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6614 10:01:06.387338 [CA 0] Center 36 (8~64) winsize 57
6615 10:01:06.390649 [CA 1] Center 36 (8~64) winsize 57
6616 10:01:06.393988 [CA 2] Center 36 (8~64) winsize 57
6617 10:01:06.397196 [CA 3] Center 36 (8~64) winsize 57
6618 10:01:06.400528 [CA 4] Center 36 (8~64) winsize 57
6619 10:01:06.404062 [CA 5] Center 36 (8~64) winsize 57
6620 10:01:06.404161
6621 10:01:06.407365 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6622 10:01:06.407439
6623 10:01:06.411139 [CATrainingPosCal] consider 2 rank data
6624 10:01:06.413771 u2DelayCellTimex100 = 270/100 ps
6625 10:01:06.416952 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 10:01:06.420303 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 10:01:06.426821 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 10:01:06.430179 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 10:01:06.433429 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 10:01:06.437005 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 10:01:06.437079
6632 10:01:06.440300 CA PerBit enable=1, Macro0, CA PI delay=36
6633 10:01:06.440368
6634 10:01:06.443350 [CBTSetCACLKResult] CA Dly = 36
6635 10:01:06.443450 CS Dly: 1 (0~32)
6636 10:01:06.443538
6637 10:01:06.450352 ----->DramcWriteLeveling(PI) begin...
6638 10:01:06.450424 ==
6639 10:01:06.453145 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 10:01:06.456516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 10:01:06.456584 ==
6642 10:01:06.459868 Write leveling (Byte 0): 40 => 8
6643 10:01:06.462713 Write leveling (Byte 1): 40 => 8
6644 10:01:06.466169 DramcWriteLeveling(PI) end<-----
6645 10:01:06.466240
6646 10:01:06.466300 ==
6647 10:01:06.469826 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 10:01:06.472849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 10:01:06.472952 ==
6650 10:01:06.476034 [Gating] SW mode calibration
6651 10:01:06.482665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6652 10:01:06.489367 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6653 10:01:06.492879 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6654 10:01:06.495997 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 10:01:06.502748 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 10:01:06.505797 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 10:01:06.508860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 10:01:06.515620 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 10:01:06.518839 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 10:01:06.522376 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 10:01:06.529109 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 10:01:06.529186 Total UI for P1: 0, mck2ui 16
6663 10:01:06.535258 best dqsien dly found for B0: ( 0, 14, 24)
6664 10:01:06.535331 Total UI for P1: 0, mck2ui 16
6665 10:01:06.541830 best dqsien dly found for B1: ( 0, 14, 24)
6666 10:01:06.545461 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6667 10:01:06.548429 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6668 10:01:06.548503
6669 10:01:06.552060 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6670 10:01:06.554965 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 10:01:06.558365 [Gating] SW calibration Done
6672 10:01:06.558438 ==
6673 10:01:06.561675 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 10:01:06.565231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 10:01:06.565303 ==
6676 10:01:06.568588 RX Vref Scan: 0
6677 10:01:06.568662
6678 10:01:06.568728 RX Vref 0 -> 0, step: 1
6679 10:01:06.571703
6680 10:01:06.571800 RX Delay -410 -> 252, step: 16
6681 10:01:06.577961 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6682 10:01:06.581734 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6683 10:01:06.584718 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6684 10:01:06.591540 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6685 10:01:06.594766 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6686 10:01:06.597869 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6687 10:01:06.601647 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6688 10:01:06.607822 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6689 10:01:06.611303 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6690 10:01:06.614699 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6691 10:01:06.617881 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6692 10:01:06.624396 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6693 10:01:06.627639 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6694 10:01:06.630999 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6695 10:01:06.634385 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6696 10:01:06.640744 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6697 10:01:06.640846 ==
6698 10:01:06.644052 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 10:01:06.647486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 10:01:06.647557 ==
6701 10:01:06.647622 DQS Delay:
6702 10:01:06.650843 DQS0 = 43, DQS1 = 51
6703 10:01:06.650913 DQM Delay:
6704 10:01:06.654083 DQM0 = 13, DQM1 = 13
6705 10:01:06.654155 DQ Delay:
6706 10:01:06.656956 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6707 10:01:06.660512 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6708 10:01:06.663845 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6709 10:01:06.667219 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6710 10:01:06.667294
6711 10:01:06.667377
6712 10:01:06.667463 ==
6713 10:01:06.670482 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 10:01:06.674066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 10:01:06.674141 ==
6716 10:01:06.677234
6717 10:01:06.677306
6718 10:01:06.677366 TX Vref Scan disable
6719 10:01:06.680433 == TX Byte 0 ==
6720 10:01:06.683537 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 10:01:06.687064 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 10:01:06.689870 == TX Byte 1 ==
6723 10:01:06.693190 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6724 10:01:06.696531 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6725 10:01:06.696604 ==
6726 10:01:06.699825 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 10:01:06.706680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 10:01:06.706757 ==
6729 10:01:06.706820
6730 10:01:06.706883
6731 10:01:06.706939 TX Vref Scan disable
6732 10:01:06.709752 == TX Byte 0 ==
6733 10:01:06.713131 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 10:01:06.716119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 10:01:06.719645 == TX Byte 1 ==
6736 10:01:06.723034 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 10:01:06.726231 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 10:01:06.726313
6739 10:01:06.729380 [DATLAT]
6740 10:01:06.729460 Freq=400, CH1 RK0
6741 10:01:06.729524
6742 10:01:06.732709 DATLAT Default: 0xf
6743 10:01:06.732790 0, 0xFFFF, sum = 0
6744 10:01:06.736513 1, 0xFFFF, sum = 0
6745 10:01:06.736595 2, 0xFFFF, sum = 0
6746 10:01:06.739769 3, 0xFFFF, sum = 0
6747 10:01:06.739865 4, 0xFFFF, sum = 0
6748 10:01:06.742822 5, 0xFFFF, sum = 0
6749 10:01:06.742904 6, 0xFFFF, sum = 0
6750 10:01:06.746356 7, 0xFFFF, sum = 0
6751 10:01:06.746438 8, 0xFFFF, sum = 0
6752 10:01:06.749528 9, 0xFFFF, sum = 0
6753 10:01:06.753084 10, 0xFFFF, sum = 0
6754 10:01:06.753166 11, 0xFFFF, sum = 0
6755 10:01:06.755852 12, 0xFFFF, sum = 0
6756 10:01:06.755986 13, 0x0, sum = 1
6757 10:01:06.759158 14, 0x0, sum = 2
6758 10:01:06.759266 15, 0x0, sum = 3
6759 10:01:06.762679 16, 0x0, sum = 4
6760 10:01:06.762761 best_step = 14
6761 10:01:06.762825
6762 10:01:06.762884 ==
6763 10:01:06.766118 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 10:01:06.769399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 10:01:06.769483 ==
6766 10:01:06.772595 RX Vref Scan: 1
6767 10:01:06.772675
6768 10:01:06.776086 RX Vref 0 -> 0, step: 1
6769 10:01:06.776167
6770 10:01:06.776232 RX Delay -343 -> 252, step: 8
6771 10:01:06.776291
6772 10:01:06.779522 Set Vref, RX VrefLevel [Byte0]: 52
6773 10:01:06.782474 [Byte1]: 49
6774 10:01:06.788070
6775 10:01:06.788151 Final RX Vref Byte 0 = 52 to rank0
6776 10:01:06.791121 Final RX Vref Byte 1 = 49 to rank0
6777 10:01:06.794484 Final RX Vref Byte 0 = 52 to rank1
6778 10:01:06.797678 Final RX Vref Byte 1 = 49 to rank1==
6779 10:01:06.800684 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 10:01:06.807555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 10:01:06.807658 ==
6782 10:01:06.807748 DQS Delay:
6783 10:01:06.810800 DQS0 = 44, DQS1 = 56
6784 10:01:06.810871 DQM Delay:
6785 10:01:06.814127 DQM0 = 11, DQM1 = 14
6786 10:01:06.814197 DQ Delay:
6787 10:01:06.816962 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6788 10:01:06.821150 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6789 10:01:06.824096 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6790 10:01:06.827131 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6791 10:01:06.827234
6792 10:01:06.827324
6793 10:01:06.833699 [DQSOSCAuto] RK0, (LSB)MR18= 0x6990, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6794 10:01:06.836871 CH1 RK0: MR19=C0C, MR18=6990
6795 10:01:06.843633 CH1_RK0: MR19=0xC0C, MR18=0x6990, DQSOSC=391, MR23=63, INC=386, DEC=257
6796 10:01:06.843747 ==
6797 10:01:06.846831 Dram Type= 6, Freq= 0, CH_1, rank 1
6798 10:01:06.849981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 10:01:06.850057 ==
6800 10:01:06.853600 [Gating] SW mode calibration
6801 10:01:06.860222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6802 10:01:06.866388 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6803 10:01:06.870056 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6804 10:01:06.872980 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 10:01:06.879754 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 10:01:06.882746 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 10:01:06.889505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 10:01:06.892724 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 10:01:06.896061 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 10:01:06.902312 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 10:01:06.905939 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 10:01:06.909322 Total UI for P1: 0, mck2ui 16
6813 10:01:06.912140 best dqsien dly found for B0: ( 0, 14, 24)
6814 10:01:06.915542 Total UI for P1: 0, mck2ui 16
6815 10:01:06.919380 best dqsien dly found for B1: ( 0, 14, 24)
6816 10:01:06.922013 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6817 10:01:06.925963 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6818 10:01:06.926034
6819 10:01:06.928911 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6820 10:01:06.932080 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 10:01:06.935612 [Gating] SW calibration Done
6822 10:01:06.935710 ==
6823 10:01:06.938387 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 10:01:06.945562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 10:01:06.945639 ==
6826 10:01:06.945705 RX Vref Scan: 0
6827 10:01:06.945765
6828 10:01:06.948798 RX Vref 0 -> 0, step: 1
6829 10:01:06.948866
6830 10:01:06.951827 RX Delay -410 -> 252, step: 16
6831 10:01:06.955319 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6832 10:01:06.958618 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6833 10:01:06.964811 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6834 10:01:06.968054 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6835 10:01:06.971396 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6836 10:01:06.974736 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6837 10:01:06.981400 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6838 10:01:06.984879 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6839 10:01:06.988244 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6840 10:01:06.991213 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6841 10:01:06.997853 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6842 10:01:07.001298 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6843 10:01:07.004508 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6844 10:01:07.007605 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6845 10:01:07.014182 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6846 10:01:07.017791 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6847 10:01:07.017894 ==
6848 10:01:07.020988 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 10:01:07.024260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 10:01:07.024341 ==
6851 10:01:07.027589 DQS Delay:
6852 10:01:07.027670 DQS0 = 43, DQS1 = 51
6853 10:01:07.031211 DQM Delay:
6854 10:01:07.031291 DQM0 = 10, DQM1 = 13
6855 10:01:07.033950 DQ Delay:
6856 10:01:07.034030 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6857 10:01:07.037157 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6858 10:01:07.040524 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6859 10:01:07.044428 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6860 10:01:07.044510
6861 10:01:07.044573
6862 10:01:07.044633 ==
6863 10:01:07.047340 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 10:01:07.053733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 10:01:07.053814 ==
6866 10:01:07.053879
6867 10:01:07.053938
6868 10:01:07.054027 TX Vref Scan disable
6869 10:01:07.057129 == TX Byte 0 ==
6870 10:01:07.060468 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6871 10:01:07.063646 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6872 10:01:07.067531 == TX Byte 1 ==
6873 10:01:07.070274 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6874 10:01:07.073584 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6875 10:01:07.073665 ==
6876 10:01:07.077273 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 10:01:07.083923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 10:01:07.084004 ==
6879 10:01:07.084068
6880 10:01:07.084128
6881 10:01:07.087098 TX Vref Scan disable
6882 10:01:07.087178 == TX Byte 0 ==
6883 10:01:07.090474 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6884 10:01:07.096807 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6885 10:01:07.096888 == TX Byte 1 ==
6886 10:01:07.100229 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6887 10:01:07.103303 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6888 10:01:07.106550
6889 10:01:07.106630 [DATLAT]
6890 10:01:07.106694 Freq=400, CH1 RK1
6891 10:01:07.106754
6892 10:01:07.110134 DATLAT Default: 0xe
6893 10:01:07.110214 0, 0xFFFF, sum = 0
6894 10:01:07.113152 1, 0xFFFF, sum = 0
6895 10:01:07.113234 2, 0xFFFF, sum = 0
6896 10:01:07.116525 3, 0xFFFF, sum = 0
6897 10:01:07.119546 4, 0xFFFF, sum = 0
6898 10:01:07.119628 5, 0xFFFF, sum = 0
6899 10:01:07.123156 6, 0xFFFF, sum = 0
6900 10:01:07.123238 7, 0xFFFF, sum = 0
6901 10:01:07.126209 8, 0xFFFF, sum = 0
6902 10:01:07.126292 9, 0xFFFF, sum = 0
6903 10:01:07.129820 10, 0xFFFF, sum = 0
6904 10:01:07.129901 11, 0xFFFF, sum = 0
6905 10:01:07.132657 12, 0xFFFF, sum = 0
6906 10:01:07.132739 13, 0x0, sum = 1
6907 10:01:07.136549 14, 0x0, sum = 2
6908 10:01:07.136631 15, 0x0, sum = 3
6909 10:01:07.139349 16, 0x0, sum = 4
6910 10:01:07.139431 best_step = 14
6911 10:01:07.139496
6912 10:01:07.139554 ==
6913 10:01:07.142819 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 10:01:07.149321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 10:01:07.149403 ==
6916 10:01:07.149468 RX Vref Scan: 0
6917 10:01:07.149527
6918 10:01:07.152680 RX Vref 0 -> 0, step: 1
6919 10:01:07.152760
6920 10:01:07.155922 RX Delay -343 -> 252, step: 8
6921 10:01:07.162381 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6922 10:01:07.165614 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6923 10:01:07.169229 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6924 10:01:07.172526 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6925 10:01:07.178979 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6926 10:01:07.182628 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6927 10:01:07.186096 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6928 10:01:07.188898 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6929 10:01:07.195453 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6930 10:01:07.198767 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6931 10:01:07.201808 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6932 10:01:07.205722 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6933 10:01:07.211610 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6934 10:01:07.215062 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6935 10:01:07.218589 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6936 10:01:07.225129 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6937 10:01:07.225210 ==
6938 10:01:07.228757 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 10:01:07.231417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 10:01:07.231499 ==
6941 10:01:07.231563 DQS Delay:
6942 10:01:07.234946 DQS0 = 48, DQS1 = 56
6943 10:01:07.235027 DQM Delay:
6944 10:01:07.238000 DQM0 = 11, DQM1 = 14
6945 10:01:07.238081 DQ Delay:
6946 10:01:07.241604 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6947 10:01:07.245051 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6948 10:01:07.247869 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6949 10:01:07.251308 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6950 10:01:07.251388
6951 10:01:07.251452
6952 10:01:07.257903 [DQSOSCAuto] RK1, (LSB)MR18= 0x74ac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6953 10:01:07.261216 CH1 RK1: MR19=C0C, MR18=74AC
6954 10:01:07.267953 CH1_RK1: MR19=0xC0C, MR18=0x74AC, DQSOSC=388, MR23=63, INC=392, DEC=261
6955 10:01:07.270995 [RxdqsGatingPostProcess] freq 400
6956 10:01:07.277520 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6957 10:01:07.280989 best DQS0 dly(2T, 0.5T) = (0, 10)
6958 10:01:07.284346 best DQS1 dly(2T, 0.5T) = (0, 10)
6959 10:01:07.287571 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6960 10:01:07.290853 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6961 10:01:07.290927 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 10:01:07.294281 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 10:01:07.297256 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 10:01:07.300998 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 10:01:07.304179 Pre-setting of DQS Precalculation
6966 10:01:07.310669 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6967 10:01:07.317077 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6968 10:01:07.323744 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6969 10:01:07.323846
6970 10:01:07.323972
6971 10:01:07.327279 [Calibration Summary] 800 Mbps
6972 10:01:07.327349 CH 0, Rank 0
6973 10:01:07.330203 SW Impedance : PASS
6974 10:01:07.333811 DUTY Scan : NO K
6975 10:01:07.333885 ZQ Calibration : PASS
6976 10:01:07.337031 Jitter Meter : NO K
6977 10:01:07.339993 CBT Training : PASS
6978 10:01:07.340092 Write leveling : PASS
6979 10:01:07.343789 RX DQS gating : PASS
6980 10:01:07.346750 RX DQ/DQS(RDDQC) : PASS
6981 10:01:07.346849 TX DQ/DQS : PASS
6982 10:01:07.350562 RX DATLAT : PASS
6983 10:01:07.353561 RX DQ/DQS(Engine): PASS
6984 10:01:07.353630 TX OE : NO K
6985 10:01:07.356970 All Pass.
6986 10:01:07.357040
6987 10:01:07.357099 CH 0, Rank 1
6988 10:01:07.360213 SW Impedance : PASS
6989 10:01:07.360282 DUTY Scan : NO K
6990 10:01:07.363040 ZQ Calibration : PASS
6991 10:01:07.366617 Jitter Meter : NO K
6992 10:01:07.366688 CBT Training : PASS
6993 10:01:07.369880 Write leveling : NO K
6994 10:01:07.373125 RX DQS gating : PASS
6995 10:01:07.373192 RX DQ/DQS(RDDQC) : PASS
6996 10:01:07.376422 TX DQ/DQS : PASS
6997 10:01:07.379576 RX DATLAT : PASS
6998 10:01:07.379648 RX DQ/DQS(Engine): PASS
6999 10:01:07.383193 TX OE : NO K
7000 10:01:07.383261 All Pass.
7001 10:01:07.383320
7002 10:01:07.386481 CH 1, Rank 0
7003 10:01:07.386550 SW Impedance : PASS
7004 10:01:07.390267 DUTY Scan : NO K
7005 10:01:07.392936 ZQ Calibration : PASS
7006 10:01:07.393043 Jitter Meter : NO K
7007 10:01:07.396124 CBT Training : PASS
7008 10:01:07.396206 Write leveling : PASS
7009 10:01:07.399479 RX DQS gating : PASS
7010 10:01:07.402754 RX DQ/DQS(RDDQC) : PASS
7011 10:01:07.402855 TX DQ/DQS : PASS
7012 10:01:07.405981 RX DATLAT : PASS
7013 10:01:07.409497 RX DQ/DQS(Engine): PASS
7014 10:01:07.409575 TX OE : NO K
7015 10:01:07.412780 All Pass.
7016 10:01:07.412878
7017 10:01:07.412967 CH 1, Rank 1
7018 10:01:07.416093 SW Impedance : PASS
7019 10:01:07.416208 DUTY Scan : NO K
7020 10:01:07.419505 ZQ Calibration : PASS
7021 10:01:07.422776 Jitter Meter : NO K
7022 10:01:07.422857 CBT Training : PASS
7023 10:01:07.425651 Write leveling : NO K
7024 10:01:07.428975 RX DQS gating : PASS
7025 10:01:07.429056 RX DQ/DQS(RDDQC) : PASS
7026 10:01:07.432616 TX DQ/DQS : PASS
7027 10:01:07.435842 RX DATLAT : PASS
7028 10:01:07.435944 RX DQ/DQS(Engine): PASS
7029 10:01:07.438931 TX OE : NO K
7030 10:01:07.439012 All Pass.
7031 10:01:07.439076
7032 10:01:07.442439 DramC Write-DBI off
7033 10:01:07.445775 PER_BANK_REFRESH: Hybrid Mode
7034 10:01:07.445855 TX_TRACKING: ON
7035 10:01:07.455701 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7036 10:01:07.458828 [FAST_K] Save calibration result to emmc
7037 10:01:07.462431 dramc_set_vcore_voltage set vcore to 725000
7038 10:01:07.465290 Read voltage for 1600, 0
7039 10:01:07.465370 Vio18 = 0
7040 10:01:07.468459 Vcore = 725000
7041 10:01:07.468539 Vdram = 0
7042 10:01:07.468603 Vddq = 0
7043 10:01:07.468662 Vmddr = 0
7044 10:01:07.475232 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7045 10:01:07.481622 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7046 10:01:07.481703 MEM_TYPE=3, freq_sel=13
7047 10:01:07.484967 sv_algorithm_assistance_LP4_3733
7048 10:01:07.488341 ============ PULL DRAM RESETB DOWN ============
7049 10:01:07.494946 ========== PULL DRAM RESETB DOWN end =========
7050 10:01:07.498191 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7051 10:01:07.501604 ===================================
7052 10:01:07.504785 LPDDR4 DRAM CONFIGURATION
7053 10:01:07.508121 ===================================
7054 10:01:07.508201 EX_ROW_EN[0] = 0x0
7055 10:01:07.511324 EX_ROW_EN[1] = 0x0
7056 10:01:07.511404 LP4Y_EN = 0x0
7057 10:01:07.514716 WORK_FSP = 0x1
7058 10:01:07.514796 WL = 0x5
7059 10:01:07.517874 RL = 0x5
7060 10:01:07.521879 BL = 0x2
7061 10:01:07.521960 RPST = 0x0
7062 10:01:07.524588 RD_PRE = 0x0
7063 10:01:07.524669 WR_PRE = 0x1
7064 10:01:07.527846 WR_PST = 0x1
7065 10:01:07.527965 DBI_WR = 0x0
7066 10:01:07.531276 DBI_RD = 0x0
7067 10:01:07.531357 OTF = 0x1
7068 10:01:07.534826 ===================================
7069 10:01:07.537739 ===================================
7070 10:01:07.540782 ANA top config
7071 10:01:07.544256 ===================================
7072 10:01:07.544338 DLL_ASYNC_EN = 0
7073 10:01:07.547296 ALL_SLAVE_EN = 0
7074 10:01:07.550900 NEW_RANK_MODE = 1
7075 10:01:07.554064 DLL_IDLE_MODE = 1
7076 10:01:07.557645 LP45_APHY_COMB_EN = 1
7077 10:01:07.557726 TX_ODT_DIS = 0
7078 10:01:07.560424 NEW_8X_MODE = 1
7079 10:01:07.563783 ===================================
7080 10:01:07.567054 ===================================
7081 10:01:07.570717 data_rate = 3200
7082 10:01:07.573968 CKR = 1
7083 10:01:07.577737 DQ_P2S_RATIO = 8
7084 10:01:07.580205 ===================================
7085 10:01:07.583776 CA_P2S_RATIO = 8
7086 10:01:07.583876 DQ_CA_OPEN = 0
7087 10:01:07.587088 DQ_SEMI_OPEN = 0
7088 10:01:07.590315 CA_SEMI_OPEN = 0
7089 10:01:07.593690 CA_FULL_RATE = 0
7090 10:01:07.596790 DQ_CKDIV4_EN = 0
7091 10:01:07.600049 CA_CKDIV4_EN = 0
7092 10:01:07.600151 CA_PREDIV_EN = 0
7093 10:01:07.603589 PH8_DLY = 12
7094 10:01:07.606844 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7095 10:01:07.610407 DQ_AAMCK_DIV = 4
7096 10:01:07.613526 CA_AAMCK_DIV = 4
7097 10:01:07.616912 CA_ADMCK_DIV = 4
7098 10:01:07.617011 DQ_TRACK_CA_EN = 0
7099 10:01:07.619999 CA_PICK = 1600
7100 10:01:07.623287 CA_MCKIO = 1600
7101 10:01:07.626849 MCKIO_SEMI = 0
7102 10:01:07.629610 PLL_FREQ = 3068
7103 10:01:07.633238 DQ_UI_PI_RATIO = 32
7104 10:01:07.636781 CA_UI_PI_RATIO = 0
7105 10:01:07.639541 ===================================
7106 10:01:07.643563 ===================================
7107 10:01:07.643662 memory_type:LPDDR4
7108 10:01:07.646046 GP_NUM : 10
7109 10:01:07.649736 SRAM_EN : 1
7110 10:01:07.649807 MD32_EN : 0
7111 10:01:07.653181 ===================================
7112 10:01:07.656122 [ANA_INIT] >>>>>>>>>>>>>>
7113 10:01:07.659237 <<<<<< [CONFIGURE PHASE]: ANA_TX
7114 10:01:07.662796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7115 10:01:07.666286 ===================================
7116 10:01:07.669585 data_rate = 3200,PCW = 0X7600
7117 10:01:07.672434 ===================================
7118 10:01:07.675895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7119 10:01:07.682827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7120 10:01:07.685707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 10:01:07.692895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7122 10:01:07.695611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7123 10:01:07.698967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7124 10:01:07.699046 [ANA_INIT] flow start
7125 10:01:07.702198 [ANA_INIT] PLL >>>>>>>>
7126 10:01:07.705281 [ANA_INIT] PLL <<<<<<<<
7127 10:01:07.705380 [ANA_INIT] MIDPI >>>>>>>>
7128 10:01:07.708623 [ANA_INIT] MIDPI <<<<<<<<
7129 10:01:07.712168 [ANA_INIT] DLL >>>>>>>>
7130 10:01:07.712240 [ANA_INIT] DLL <<<<<<<<
7131 10:01:07.715635 [ANA_INIT] flow end
7132 10:01:07.718849 ============ LP4 DIFF to SE enter ============
7133 10:01:07.725056 ============ LP4 DIFF to SE exit ============
7134 10:01:07.725134 [ANA_INIT] <<<<<<<<<<<<<
7135 10:01:07.728917 [Flow] Enable top DCM control >>>>>
7136 10:01:07.732064 [Flow] Enable top DCM control <<<<<
7137 10:01:07.735204 Enable DLL master slave shuffle
7138 10:01:07.742076 ==============================================================
7139 10:01:07.742152 Gating Mode config
7140 10:01:07.748162 ==============================================================
7141 10:01:07.751701 Config description:
7142 10:01:07.761368 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7143 10:01:07.767979 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7144 10:01:07.771473 SELPH_MODE 0: By rank 1: By Phase
7145 10:01:07.778142 ==============================================================
7146 10:01:07.781289 GAT_TRACK_EN = 1
7147 10:01:07.784665 RX_GATING_MODE = 2
7148 10:01:07.784741 RX_GATING_TRACK_MODE = 2
7149 10:01:07.787901 SELPH_MODE = 1
7150 10:01:07.791169 PICG_EARLY_EN = 1
7151 10:01:07.794664 VALID_LAT_VALUE = 1
7152 10:01:07.801230 ==============================================================
7153 10:01:07.804675 Enter into Gating configuration >>>>
7154 10:01:07.807779 Exit from Gating configuration <<<<
7155 10:01:07.811265 Enter into DVFS_PRE_config >>>>>
7156 10:01:07.821157 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7157 10:01:07.824044 Exit from DVFS_PRE_config <<<<<
7158 10:01:07.827556 Enter into PICG configuration >>>>
7159 10:01:07.830606 Exit from PICG configuration <<<<
7160 10:01:07.833935 [RX_INPUT] configuration >>>>>
7161 10:01:07.837187 [RX_INPUT] configuration <<<<<
7162 10:01:07.840553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7163 10:01:07.846960 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7164 10:01:07.853592 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7165 10:01:07.860669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7166 10:01:07.866918 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 10:01:07.870570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 10:01:07.876889 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7169 10:01:07.880837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7170 10:01:07.883551 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7171 10:01:07.886638 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7172 10:01:07.893802 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7173 10:01:07.896898 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7174 10:01:07.900042 ===================================
7175 10:01:07.903342 LPDDR4 DRAM CONFIGURATION
7176 10:01:07.906431 ===================================
7177 10:01:07.906506 EX_ROW_EN[0] = 0x0
7178 10:01:07.909782 EX_ROW_EN[1] = 0x0
7179 10:01:07.909858 LP4Y_EN = 0x0
7180 10:01:07.913011 WORK_FSP = 0x1
7181 10:01:07.913110 WL = 0x5
7182 10:01:07.916771 RL = 0x5
7183 10:01:07.919570 BL = 0x2
7184 10:01:07.919671 RPST = 0x0
7185 10:01:07.923096 RD_PRE = 0x0
7186 10:01:07.923167 WR_PRE = 0x1
7187 10:01:07.926409 WR_PST = 0x1
7188 10:01:07.926479 DBI_WR = 0x0
7189 10:01:07.929990 DBI_RD = 0x0
7190 10:01:07.930058 OTF = 0x1
7191 10:01:07.932601 ===================================
7192 10:01:07.936172 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7193 10:01:07.942665 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7194 10:01:07.945804 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7195 10:01:07.949077 ===================================
7196 10:01:07.952970 LPDDR4 DRAM CONFIGURATION
7197 10:01:07.955912 ===================================
7198 10:01:07.955985 EX_ROW_EN[0] = 0x10
7199 10:01:07.959284 EX_ROW_EN[1] = 0x0
7200 10:01:07.959353 LP4Y_EN = 0x0
7201 10:01:07.962920 WORK_FSP = 0x1
7202 10:01:07.966195 WL = 0x5
7203 10:01:07.966266 RL = 0x5
7204 10:01:07.969024 BL = 0x2
7205 10:01:07.969094 RPST = 0x0
7206 10:01:07.972521 RD_PRE = 0x0
7207 10:01:07.972607 WR_PRE = 0x1
7208 10:01:07.975528 WR_PST = 0x1
7209 10:01:07.975609 DBI_WR = 0x0
7210 10:01:07.979173 DBI_RD = 0x0
7211 10:01:07.979254 OTF = 0x1
7212 10:01:07.982542 ===================================
7213 10:01:07.988804 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7214 10:01:07.988885 ==
7215 10:01:07.991918 Dram Type= 6, Freq= 0, CH_0, rank 0
7216 10:01:07.995594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7217 10:01:07.998808 ==
7218 10:01:07.998889 [Duty_Offset_Calibration]
7219 10:01:08.002214 B0:2 B1:0 CA:4
7220 10:01:08.002294
7221 10:01:08.005083 [DutyScan_Calibration_Flow] k_type=0
7222 10:01:08.013712
7223 10:01:08.013792 ==CLK 0==
7224 10:01:08.016495 Final CLK duty delay cell = -4
7225 10:01:08.020212 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7226 10:01:08.023383 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7227 10:01:08.026575 [-4] AVG Duty = 4922%(X100)
7228 10:01:08.026656
7229 10:01:08.029629 CH0 CLK Duty spec in!! Max-Min= 218%
7230 10:01:08.033559 [DutyScan_Calibration_Flow] ====Done====
7231 10:01:08.033639
7232 10:01:08.036296 [DutyScan_Calibration_Flow] k_type=1
7233 10:01:08.053528
7234 10:01:08.053608 ==DQS 0 ==
7235 10:01:08.056748 Final DQS duty delay cell = 0
7236 10:01:08.060272 [0] MAX Duty = 5218%(X100), DQS PI = 38
7237 10:01:08.063753 [0] MIN Duty = 5093%(X100), DQS PI = 14
7238 10:01:08.066966 [0] AVG Duty = 5155%(X100)
7239 10:01:08.067046
7240 10:01:08.067110 ==DQS 1 ==
7241 10:01:08.070186 Final DQS duty delay cell = 0
7242 10:01:08.073407 [0] MAX Duty = 5187%(X100), DQS PI = 2
7243 10:01:08.076585 [0] MIN Duty = 5000%(X100), DQS PI = 10
7244 10:01:08.080025 [0] AVG Duty = 5093%(X100)
7245 10:01:08.080105
7246 10:01:08.083439 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7247 10:01:08.083520
7248 10:01:08.086329 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7249 10:01:08.089926 [DutyScan_Calibration_Flow] ====Done====
7250 10:01:08.090007
7251 10:01:08.093264 [DutyScan_Calibration_Flow] k_type=3
7252 10:01:08.111025
7253 10:01:08.111107 ==DQM 0 ==
7254 10:01:08.113918 Final DQM duty delay cell = 0
7255 10:01:08.117618 [0] MAX Duty = 5124%(X100), DQS PI = 20
7256 10:01:08.120609 [0] MIN Duty = 4875%(X100), DQS PI = 56
7257 10:01:08.124082 [0] AVG Duty = 4999%(X100)
7258 10:01:08.124163
7259 10:01:08.124227 ==DQM 1 ==
7260 10:01:08.126964 Final DQM duty delay cell = 0
7261 10:01:08.130079 [0] MAX Duty = 5000%(X100), DQS PI = 2
7262 10:01:08.133655 [0] MIN Duty = 4844%(X100), DQS PI = 16
7263 10:01:08.137125 [0] AVG Duty = 4922%(X100)
7264 10:01:08.137206
7265 10:01:08.140526 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7266 10:01:08.140607
7267 10:01:08.143566 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7268 10:01:08.146867 [DutyScan_Calibration_Flow] ====Done====
7269 10:01:08.146948
7270 10:01:08.150222 [DutyScan_Calibration_Flow] k_type=2
7271 10:01:08.167718
7272 10:01:08.167798 ==DQ 0 ==
7273 10:01:08.171037 Final DQ duty delay cell = 0
7274 10:01:08.174493 [0] MAX Duty = 5124%(X100), DQS PI = 20
7275 10:01:08.177790 [0] MIN Duty = 4938%(X100), DQS PI = 12
7276 10:01:08.177871 [0] AVG Duty = 5031%(X100)
7277 10:01:08.181199
7278 10:01:08.181279 ==DQ 1 ==
7279 10:01:08.184221 Final DQ duty delay cell = 0
7280 10:01:08.187624 [0] MAX Duty = 5187%(X100), DQS PI = 2
7281 10:01:08.190887 [0] MIN Duty = 4938%(X100), DQS PI = 12
7282 10:01:08.190969 [0] AVG Duty = 5062%(X100)
7283 10:01:08.194139
7284 10:01:08.197584 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7285 10:01:08.197665
7286 10:01:08.200596 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7287 10:01:08.204306 [DutyScan_Calibration_Flow] ====Done====
7288 10:01:08.204387 ==
7289 10:01:08.207311 Dram Type= 6, Freq= 0, CH_1, rank 0
7290 10:01:08.210763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7291 10:01:08.210845 ==
7292 10:01:08.214076 [Duty_Offset_Calibration]
7293 10:01:08.214157 B0:0 B1:-1 CA:3
7294 10:01:08.214221
7295 10:01:08.217955 [DutyScan_Calibration_Flow] k_type=0
7296 10:01:08.227076
7297 10:01:08.227157 ==CLK 0==
7298 10:01:08.230897 Final CLK duty delay cell = -4
7299 10:01:08.234139 [-4] MAX Duty = 5031%(X100), DQS PI = 36
7300 10:01:08.237063 [-4] MIN Duty = 4813%(X100), DQS PI = 4
7301 10:01:08.240328 [-4] AVG Duty = 4922%(X100)
7302 10:01:08.240407
7303 10:01:08.243632 CH1 CLK Duty spec in!! Max-Min= 218%
7304 10:01:08.246753 [DutyScan_Calibration_Flow] ====Done====
7305 10:01:08.246833
7306 10:01:08.249983 [DutyScan_Calibration_Flow] k_type=1
7307 10:01:08.266343
7308 10:01:08.266422 ==DQS 0 ==
7309 10:01:08.269658 Final DQS duty delay cell = 0
7310 10:01:08.273269 [0] MAX Duty = 5187%(X100), DQS PI = 0
7311 10:01:08.276229 [0] MIN Duty = 4969%(X100), DQS PI = 8
7312 10:01:08.276309 [0] AVG Duty = 5078%(X100)
7313 10:01:08.279764
7314 10:01:08.279843 ==DQS 1 ==
7315 10:01:08.283053 Final DQS duty delay cell = -4
7316 10:01:08.286253 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7317 10:01:08.289452 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7318 10:01:08.293015 [-4] AVG Duty = 4937%(X100)
7319 10:01:08.293095
7320 10:01:08.296399 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7321 10:01:08.296480
7322 10:01:08.299643 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7323 10:01:08.302447 [DutyScan_Calibration_Flow] ====Done====
7324 10:01:08.302526
7325 10:01:08.305565 [DutyScan_Calibration_Flow] k_type=3
7326 10:01:08.323562
7327 10:01:08.323668 ==DQM 0 ==
7328 10:01:08.326912 Final DQM duty delay cell = 0
7329 10:01:08.330095 [0] MAX Duty = 5062%(X100), DQS PI = 62
7330 10:01:08.334055 [0] MIN Duty = 4813%(X100), DQS PI = 6
7331 10:01:08.337021 [0] AVG Duty = 4937%(X100)
7332 10:01:08.337100
7333 10:01:08.337163 ==DQM 1 ==
7334 10:01:08.340298 Final DQM duty delay cell = 0
7335 10:01:08.343371 [0] MAX Duty = 5000%(X100), DQS PI = 2
7336 10:01:08.346803 [0] MIN Duty = 4813%(X100), DQS PI = 30
7337 10:01:08.350011 [0] AVG Duty = 4906%(X100)
7338 10:01:08.350090
7339 10:01:08.353262 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7340 10:01:08.353342
7341 10:01:08.356457 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7342 10:01:08.359703 [DutyScan_Calibration_Flow] ====Done====
7343 10:01:08.359783
7344 10:01:08.362987 [DutyScan_Calibration_Flow] k_type=2
7345 10:01:08.380709
7346 10:01:08.380788 ==DQ 0 ==
7347 10:01:08.383642 Final DQ duty delay cell = 0
7348 10:01:08.386826 [0] MAX Duty = 5187%(X100), DQS PI = 0
7349 10:01:08.390037 [0] MIN Duty = 5031%(X100), DQS PI = 6
7350 10:01:08.390118 [0] AVG Duty = 5109%(X100)
7351 10:01:08.393359
7352 10:01:08.393438 ==DQ 1 ==
7353 10:01:08.396716 Final DQ duty delay cell = 0
7354 10:01:08.400368 [0] MAX Duty = 5031%(X100), DQS PI = 0
7355 10:01:08.403654 [0] MIN Duty = 4875%(X100), DQS PI = 28
7356 10:01:08.403734 [0] AVG Duty = 4953%(X100)
7357 10:01:08.403798
7358 10:01:08.406964 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7359 10:01:08.409933
7360 10:01:08.412972 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7361 10:01:08.416557 [DutyScan_Calibration_Flow] ====Done====
7362 10:01:08.419676 nWR fixed to 30
7363 10:01:08.419757 [ModeRegInit_LP4] CH0 RK0
7364 10:01:08.423093 [ModeRegInit_LP4] CH0 RK1
7365 10:01:08.426247 [ModeRegInit_LP4] CH1 RK0
7366 10:01:08.429848 [ModeRegInit_LP4] CH1 RK1
7367 10:01:08.429928 match AC timing 5
7368 10:01:08.436488 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7369 10:01:08.439596 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7370 10:01:08.443233 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7371 10:01:08.449278 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7372 10:01:08.453054 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7373 10:01:08.453134 [MiockJmeterHQA]
7374 10:01:08.453197
7375 10:01:08.456046 [DramcMiockJmeter] u1RxGatingPI = 0
7376 10:01:08.459298 0 : 4366, 4140
7377 10:01:08.459379 4 : 4368, 4143
7378 10:01:08.462646 8 : 4363, 4137
7379 10:01:08.462727 12 : 4366, 4140
7380 10:01:08.462792 16 : 4368, 4143
7381 10:01:08.466053 20 : 4257, 4029
7382 10:01:08.466133 24 : 4252, 4027
7383 10:01:08.469334 28 : 4252, 4027
7384 10:01:08.469415 32 : 4253, 4026
7385 10:01:08.472799 36 : 4257, 4032
7386 10:01:08.472880 40 : 4363, 4137
7387 10:01:08.476055 44 : 4252, 4027
7388 10:01:08.476135 48 : 4252, 4027
7389 10:01:08.476200 52 : 4255, 4030
7390 10:01:08.478930 56 : 4257, 4032
7391 10:01:08.479011 60 : 4253, 4026
7392 10:01:08.482350 64 : 4361, 4137
7393 10:01:08.482431 68 : 4363, 4138
7394 10:01:08.486106 72 : 4250, 4027
7395 10:01:08.486188 76 : 4252, 4029
7396 10:01:08.488872 80 : 4250, 4027
7397 10:01:08.488953 84 : 4250, 4026
7398 10:01:08.489018 88 : 4255, 4032
7399 10:01:08.492283 92 : 4360, 4137
7400 10:01:08.492364 96 : 4250, 3670
7401 10:01:08.495355 100 : 4250, 0
7402 10:01:08.495436 104 : 4250, 0
7403 10:01:08.498696 108 : 4360, 0
7404 10:01:08.498780 112 : 4250, 0
7405 10:01:08.498845 116 : 4250, 0
7406 10:01:08.502158 120 : 4250, 0
7407 10:01:08.502239 124 : 4361, 0
7408 10:01:08.505648 128 : 4250, 0
7409 10:01:08.505729 132 : 4363, 0
7410 10:01:08.505795 136 : 4361, 0
7411 10:01:08.508911 140 : 4365, 0
7412 10:01:08.508992 144 : 4250, 0
7413 10:01:08.509056 148 : 4250, 0
7414 10:01:08.512153 152 : 4255, 0
7415 10:01:08.512234 156 : 4250, 0
7416 10:01:08.515705 160 : 4250, 0
7417 10:01:08.515787 164 : 4255, 0
7418 10:01:08.515852 168 : 4255, 0
7419 10:01:08.518592 172 : 4253, 0
7420 10:01:08.518673 176 : 4250, 0
7421 10:01:08.522143 180 : 4252, 0
7422 10:01:08.522225 184 : 4361, 0
7423 10:01:08.522289 188 : 4360, 0
7424 10:01:08.525360 192 : 4361, 0
7425 10:01:08.525441 196 : 4250, 0
7426 10:01:08.528852 200 : 4250, 0
7427 10:01:08.528933 204 : 4250, 0
7428 10:01:08.528998 208 : 4250, 0
7429 10:01:08.532124 212 : 4250, 0
7430 10:01:08.532206 216 : 4250, 0
7431 10:01:08.535346 220 : 4252, 350
7432 10:01:08.535427 224 : 4250, 3950
7433 10:01:08.538721 228 : 4250, 4027
7434 10:01:08.538801 232 : 4253, 4029
7435 10:01:08.538865 236 : 4250, 4027
7436 10:01:08.541496 240 : 4250, 4027
7437 10:01:08.541577 244 : 4252, 4027
7438 10:01:08.545267 248 : 4361, 4137
7439 10:01:08.545348 252 : 4250, 4027
7440 10:01:08.548084 256 : 4250, 4027
7441 10:01:08.548166 260 : 4364, 4140
7442 10:01:08.551611 264 : 4361, 4137
7443 10:01:08.551692 268 : 4250, 4027
7444 10:01:08.555138 272 : 4361, 4138
7445 10:01:08.555219 276 : 4360, 4138
7446 10:01:08.558306 280 : 4250, 4026
7447 10:01:08.558391 284 : 4250, 4026
7448 10:01:08.561128 288 : 4250, 4026
7449 10:01:08.561209 292 : 4250, 4027
7450 10:01:08.564759 296 : 4250, 4026
7451 10:01:08.564839 300 : 4250, 4026
7452 10:01:08.567914 304 : 4250, 4026
7453 10:01:08.567996 308 : 4250, 4027
7454 10:01:08.568060 312 : 4360, 4137
7455 10:01:08.571251 316 : 4361, 4137
7456 10:01:08.571332 320 : 4248, 4024
7457 10:01:08.574623 324 : 4363, 4140
7458 10:01:08.574705 328 : 4250, 4027
7459 10:01:08.578119 332 : 4250, 4025
7460 10:01:08.578199 336 : 4250, 2115
7461 10:01:08.578264
7462 10:01:08.580989 MIOCK jitter meter ch=0
7463 10:01:08.581069
7464 10:01:08.584671 1T = (336-100) = 236 dly cells
7465 10:01:08.590999 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7466 10:01:08.591080 ==
7467 10:01:08.594604 Dram Type= 6, Freq= 0, CH_0, rank 0
7468 10:01:08.597723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7469 10:01:08.597830 ==
7470 10:01:08.604459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7471 10:01:08.607687 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7472 10:01:08.610926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7473 10:01:08.617120 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7474 10:01:08.626098 [CA 0] Center 43 (13~73) winsize 61
7475 10:01:08.629787 [CA 1] Center 42 (12~73) winsize 62
7476 10:01:08.632992 [CA 2] Center 37 (8~67) winsize 60
7477 10:01:08.636141 [CA 3] Center 37 (7~67) winsize 61
7478 10:01:08.639554 [CA 4] Center 36 (6~66) winsize 61
7479 10:01:08.643156 [CA 5] Center 35 (5~66) winsize 62
7480 10:01:08.643236
7481 10:01:08.646563 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7482 10:01:08.646644
7483 10:01:08.649545 [CATrainingPosCal] consider 1 rank data
7484 10:01:08.652859 u2DelayCellTimex100 = 275/100 ps
7485 10:01:08.656312 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7486 10:01:08.662910 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7487 10:01:08.665752 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7488 10:01:08.669094 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7489 10:01:08.672994 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7490 10:01:08.675891 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7491 10:01:08.675978
7492 10:01:08.679328 CA PerBit enable=1, Macro0, CA PI delay=35
7493 10:01:08.679408
7494 10:01:08.682344 [CBTSetCACLKResult] CA Dly = 35
7495 10:01:08.685749 CS Dly: 11 (0~42)
7496 10:01:08.689166 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7497 10:01:08.692552 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7498 10:01:08.692633 ==
7499 10:01:08.695411 Dram Type= 6, Freq= 0, CH_0, rank 1
7500 10:01:08.702409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 10:01:08.702490 ==
7502 10:01:08.705677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 10:01:08.709055 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 10:01:08.715619 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 10:01:08.722126 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 10:01:08.729898 [CA 0] Center 44 (14~74) winsize 61
7507 10:01:08.733003 [CA 1] Center 44 (14~74) winsize 61
7508 10:01:08.735930 [CA 2] Center 39 (10~69) winsize 60
7509 10:01:08.739469 [CA 3] Center 39 (10~68) winsize 59
7510 10:01:08.742674 [CA 4] Center 37 (7~67) winsize 61
7511 10:01:08.746083 [CA 5] Center 36 (6~66) winsize 61
7512 10:01:08.746164
7513 10:01:08.749373 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 10:01:08.752889
7515 10:01:08.756247 [CATrainingPosCal] consider 2 rank data
7516 10:01:08.756328 u2DelayCellTimex100 = 275/100 ps
7517 10:01:08.762466 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7518 10:01:08.765703 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7519 10:01:08.768920 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7520 10:01:08.772412 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7521 10:01:08.775491 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7522 10:01:08.779525 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7523 10:01:08.779606
7524 10:01:08.781942 CA PerBit enable=1, Macro0, CA PI delay=36
7525 10:01:08.785392
7526 10:01:08.785473 [CBTSetCACLKResult] CA Dly = 36
7527 10:01:08.788681 CS Dly: 12 (0~44)
7528 10:01:08.792054 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 10:01:08.795665 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 10:01:08.798812
7531 10:01:08.801980 ----->DramcWriteLeveling(PI) begin...
7532 10:01:08.802062 ==
7533 10:01:08.805173 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 10:01:08.808387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 10:01:08.808469 ==
7536 10:01:08.811880 Write leveling (Byte 0): 33 => 33
7537 10:01:08.815533 Write leveling (Byte 1): 27 => 27
7538 10:01:08.818207 DramcWriteLeveling(PI) end<-----
7539 10:01:08.818288
7540 10:01:08.818353 ==
7541 10:01:08.821681 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 10:01:08.824928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 10:01:08.825009 ==
7544 10:01:08.828325 [Gating] SW mode calibration
7545 10:01:08.834742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7546 10:01:08.841117 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7547 10:01:08.844446 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 10:01:08.848081 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 10:01:08.854631 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 10:01:08.857855 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7551 10:01:08.860954 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7552 10:01:08.867487 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7553 10:01:08.870585 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 10:01:08.874186 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 10:01:08.880971 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 10:01:08.883894 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 10:01:08.887458 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7558 10:01:08.893663 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7559 10:01:08.897043 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7560 10:01:08.900569 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7561 10:01:08.906996 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7562 10:01:08.910628 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 10:01:08.914020 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 10:01:08.920504 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 10:01:08.923577 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7566 10:01:08.926998 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7567 10:01:08.933783 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7568 10:01:08.937358 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7569 10:01:08.939852 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 10:01:08.946463 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 10:01:08.950044 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 10:01:08.953234 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 10:01:08.959879 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 10:01:08.963416 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 10:01:08.966307 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7576 10:01:08.973145 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7577 10:01:08.976723 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 10:01:08.980011 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 10:01:08.986010 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 10:01:08.989473 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 10:01:08.992630 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 10:01:08.999577 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 10:01:09.003117 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 10:01:09.005882 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 10:01:09.012717 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 10:01:09.015691 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 10:01:09.019032 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 10:01:09.025796 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 10:01:09.028841 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 10:01:09.032136 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 10:01:09.039018 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7592 10:01:09.042381 Total UI for P1: 0, mck2ui 16
7593 10:01:09.045699 best dqsien dly found for B0: ( 1, 9, 10)
7594 10:01:09.048889 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 10:01:09.052007 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 10:01:09.055234 Total UI for P1: 0, mck2ui 16
7597 10:01:09.058918 best dqsien dly found for B1: ( 1, 9, 18)
7598 10:01:09.062032 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7599 10:01:09.065569 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7600 10:01:09.068849
7601 10:01:09.071590 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7602 10:01:09.075030 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7603 10:01:09.078298 [Gating] SW calibration Done
7604 10:01:09.078369 ==
7605 10:01:09.081833 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 10:01:09.085131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 10:01:09.085244 ==
7608 10:01:09.088586 RX Vref Scan: 0
7609 10:01:09.088660
7610 10:01:09.088720 RX Vref 0 -> 0, step: 1
7611 10:01:09.088788
7612 10:01:09.091459 RX Delay 0 -> 252, step: 8
7613 10:01:09.095005 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7614 10:01:09.098131 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7615 10:01:09.104925 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7616 10:01:09.108586 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7617 10:01:09.111559 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7618 10:01:09.114928 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7619 10:01:09.118311 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7620 10:01:09.124574 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7621 10:01:09.128201 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7622 10:01:09.131725 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7623 10:01:09.134880 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7624 10:01:09.137826 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7625 10:01:09.144675 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7626 10:01:09.148002 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7627 10:01:09.151262 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7628 10:01:09.154556 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7629 10:01:09.157441 ==
7630 10:01:09.157515 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 10:01:09.164077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 10:01:09.164151 ==
7633 10:01:09.164213 DQS Delay:
7634 10:01:09.167629 DQS0 = 0, DQS1 = 0
7635 10:01:09.167699 DQM Delay:
7636 10:01:09.170576 DQM0 = 131, DQM1 = 127
7637 10:01:09.170646 DQ Delay:
7638 10:01:09.173888 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7639 10:01:09.177217 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7640 10:01:09.180584 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7641 10:01:09.183882 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
7642 10:01:09.184003
7643 10:01:09.184065
7644 10:01:09.184126 ==
7645 10:01:09.187314 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 10:01:09.193853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 10:01:09.193931 ==
7648 10:01:09.193998
7649 10:01:09.194057
7650 10:01:09.197334 TX Vref Scan disable
7651 10:01:09.197407 == TX Byte 0 ==
7652 10:01:09.200683 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7653 10:01:09.206986 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7654 10:01:09.207060 == TX Byte 1 ==
7655 10:01:09.210585 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7656 10:01:09.217201 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7657 10:01:09.217280 ==
7658 10:01:09.220275 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 10:01:09.223264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 10:01:09.223364 ==
7661 10:01:09.236838
7662 10:01:09.240277 TX Vref early break, caculate TX vref
7663 10:01:09.243600 TX Vref=16, minBit 1, minWin=22, winSum=369
7664 10:01:09.246856 TX Vref=18, minBit 8, minWin=22, winSum=383
7665 10:01:09.250446 TX Vref=20, minBit 1, minWin=24, winSum=393
7666 10:01:09.253811 TX Vref=22, minBit 1, minWin=24, winSum=401
7667 10:01:09.256818 TX Vref=24, minBit 0, minWin=25, winSum=412
7668 10:01:09.263753 TX Vref=26, minBit 1, minWin=25, winSum=419
7669 10:01:09.266452 TX Vref=28, minBit 2, minWin=25, winSum=422
7670 10:01:09.269807 TX Vref=30, minBit 2, minWin=25, winSum=417
7671 10:01:09.273030 TX Vref=32, minBit 4, minWin=24, winSum=412
7672 10:01:09.276769 TX Vref=34, minBit 0, minWin=23, winSum=395
7673 10:01:09.282976 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 28
7674 10:01:09.283080
7675 10:01:09.286745 Final TX Range 0 Vref 28
7676 10:01:09.286814
7677 10:01:09.286874 ==
7678 10:01:09.289798 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 10:01:09.293116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 10:01:09.293191 ==
7681 10:01:09.293254
7682 10:01:09.293311
7683 10:01:09.296310 TX Vref Scan disable
7684 10:01:09.303018 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7685 10:01:09.303095 == TX Byte 0 ==
7686 10:01:09.306223 u2DelayCellOfst[0]=14 cells (4 PI)
7687 10:01:09.309833 u2DelayCellOfst[1]=17 cells (5 PI)
7688 10:01:09.313005 u2DelayCellOfst[2]=10 cells (3 PI)
7689 10:01:09.316103 u2DelayCellOfst[3]=14 cells (4 PI)
7690 10:01:09.319239 u2DelayCellOfst[4]=10 cells (3 PI)
7691 10:01:09.322653 u2DelayCellOfst[5]=0 cells (0 PI)
7692 10:01:09.326018 u2DelayCellOfst[6]=17 cells (5 PI)
7693 10:01:09.329091 u2DelayCellOfst[7]=17 cells (5 PI)
7694 10:01:09.332388 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7695 10:01:09.335562 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7696 10:01:09.339087 == TX Byte 1 ==
7697 10:01:09.342048 u2DelayCellOfst[8]=0 cells (0 PI)
7698 10:01:09.345276 u2DelayCellOfst[9]=0 cells (0 PI)
7699 10:01:09.349085 u2DelayCellOfst[10]=7 cells (2 PI)
7700 10:01:09.351794 u2DelayCellOfst[11]=3 cells (1 PI)
7701 10:01:09.355766 u2DelayCellOfst[12]=10 cells (3 PI)
7702 10:01:09.358531 u2DelayCellOfst[13]=10 cells (3 PI)
7703 10:01:09.358608 u2DelayCellOfst[14]=14 cells (4 PI)
7704 10:01:09.361896 u2DelayCellOfst[15]=10 cells (3 PI)
7705 10:01:09.368611 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7706 10:01:09.372130 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7707 10:01:09.375202 DramC Write-DBI on
7708 10:01:09.375274 ==
7709 10:01:09.378714 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 10:01:09.381684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 10:01:09.381785 ==
7712 10:01:09.381873
7713 10:01:09.381941
7714 10:01:09.385324 TX Vref Scan disable
7715 10:01:09.385390 == TX Byte 0 ==
7716 10:01:09.391322 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7717 10:01:09.391435 == TX Byte 1 ==
7718 10:01:09.398961 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7719 10:01:09.399065 DramC Write-DBI off
7720 10:01:09.399160
7721 10:01:09.399254 [DATLAT]
7722 10:01:09.401711 Freq=1600, CH0 RK0
7723 10:01:09.401784
7724 10:01:09.404297 DATLAT Default: 0xf
7725 10:01:09.404364 0, 0xFFFF, sum = 0
7726 10:01:09.407643 1, 0xFFFF, sum = 0
7727 10:01:09.407748 2, 0xFFFF, sum = 0
7728 10:01:09.411552 3, 0xFFFF, sum = 0
7729 10:01:09.411652 4, 0xFFFF, sum = 0
7730 10:01:09.414847 5, 0xFFFF, sum = 0
7731 10:01:09.414922 6, 0xFFFF, sum = 0
7732 10:01:09.418017 7, 0xFFFF, sum = 0
7733 10:01:09.418087 8, 0xFFFF, sum = 0
7734 10:01:09.421284 9, 0xFFFF, sum = 0
7735 10:01:09.421382 10, 0xFFFF, sum = 0
7736 10:01:09.424338 11, 0xFFFF, sum = 0
7737 10:01:09.424415 12, 0xFFFF, sum = 0
7738 10:01:09.427369 13, 0xFFFF, sum = 0
7739 10:01:09.427469 14, 0x0, sum = 1
7740 10:01:09.430763 15, 0x0, sum = 2
7741 10:01:09.430832 16, 0x0, sum = 3
7742 10:01:09.434193 17, 0x0, sum = 4
7743 10:01:09.434291 best_step = 15
7744 10:01:09.434381
7745 10:01:09.434465 ==
7746 10:01:09.437960 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 10:01:09.444496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 10:01:09.444571 ==
7749 10:01:09.444632 RX Vref Scan: 1
7750 10:01:09.444695
7751 10:01:09.447764 Set Vref Range= 24 -> 127
7752 10:01:09.447859
7753 10:01:09.450403 RX Vref 24 -> 127, step: 1
7754 10:01:09.450472
7755 10:01:09.453886 RX Delay 19 -> 252, step: 4
7756 10:01:09.453953
7757 10:01:09.457486 Set Vref, RX VrefLevel [Byte0]: 24
7758 10:01:09.457573 [Byte1]: 24
7759 10:01:09.461748
7760 10:01:09.461828 Set Vref, RX VrefLevel [Byte0]: 25
7761 10:01:09.465069 [Byte1]: 25
7762 10:01:09.469635
7763 10:01:09.469715 Set Vref, RX VrefLevel [Byte0]: 26
7764 10:01:09.472972 [Byte1]: 26
7765 10:01:09.476837
7766 10:01:09.476918 Set Vref, RX VrefLevel [Byte0]: 27
7767 10:01:09.480480 [Byte1]: 27
7768 10:01:09.484196
7769 10:01:09.484276 Set Vref, RX VrefLevel [Byte0]: 28
7770 10:01:09.487796 [Byte1]: 28
7771 10:01:09.491848
7772 10:01:09.491969 Set Vref, RX VrefLevel [Byte0]: 29
7773 10:01:09.495048 [Byte1]: 29
7774 10:01:09.499389
7775 10:01:09.499469 Set Vref, RX VrefLevel [Byte0]: 30
7776 10:01:09.503336 [Byte1]: 30
7777 10:01:09.506989
7778 10:01:09.507069 Set Vref, RX VrefLevel [Byte0]: 31
7779 10:01:09.510341 [Byte1]: 31
7780 10:01:09.514874
7781 10:01:09.514954 Set Vref, RX VrefLevel [Byte0]: 32
7782 10:01:09.518150 [Byte1]: 32
7783 10:01:09.522358
7784 10:01:09.522438 Set Vref, RX VrefLevel [Byte0]: 33
7785 10:01:09.525867 [Byte1]: 33
7786 10:01:09.530017
7787 10:01:09.530098 Set Vref, RX VrefLevel [Byte0]: 34
7788 10:01:09.533394 [Byte1]: 34
7789 10:01:09.537495
7790 10:01:09.537602 Set Vref, RX VrefLevel [Byte0]: 35
7791 10:01:09.541188 [Byte1]: 35
7792 10:01:09.545216
7793 10:01:09.545297 Set Vref, RX VrefLevel [Byte0]: 36
7794 10:01:09.548203 [Byte1]: 36
7795 10:01:09.552604
7796 10:01:09.552676 Set Vref, RX VrefLevel [Byte0]: 37
7797 10:01:09.555812 [Byte1]: 37
7798 10:01:09.560236
7799 10:01:09.560304 Set Vref, RX VrefLevel [Byte0]: 38
7800 10:01:09.563312 [Byte1]: 38
7801 10:01:09.567672
7802 10:01:09.567770 Set Vref, RX VrefLevel [Byte0]: 39
7803 10:01:09.571139 [Byte1]: 39
7804 10:01:09.575658
7805 10:01:09.575744 Set Vref, RX VrefLevel [Byte0]: 40
7806 10:01:09.578376 [Byte1]: 40
7807 10:01:09.583183
7808 10:01:09.583264 Set Vref, RX VrefLevel [Byte0]: 41
7809 10:01:09.586298 [Byte1]: 41
7810 10:01:09.590407
7811 10:01:09.590487 Set Vref, RX VrefLevel [Byte0]: 42
7812 10:01:09.593496 [Byte1]: 42
7813 10:01:09.598399
7814 10:01:09.598483 Set Vref, RX VrefLevel [Byte0]: 43
7815 10:01:09.601059 [Byte1]: 43
7816 10:01:09.605880
7817 10:01:09.606418 Set Vref, RX VrefLevel [Byte0]: 44
7818 10:01:09.609223 [Byte1]: 44
7819 10:01:09.613883
7820 10:01:09.617289 Set Vref, RX VrefLevel [Byte0]: 45
7821 10:01:09.620485 [Byte1]: 45
7822 10:01:09.620903
7823 10:01:09.623167 Set Vref, RX VrefLevel [Byte0]: 46
7824 10:01:09.626926 [Byte1]: 46
7825 10:01:09.627343
7826 10:01:09.629901 Set Vref, RX VrefLevel [Byte0]: 47
7827 10:01:09.632991 [Byte1]: 47
7828 10:01:09.633411
7829 10:01:09.636646 Set Vref, RX VrefLevel [Byte0]: 48
7830 10:01:09.640294 [Byte1]: 48
7831 10:01:09.644009
7832 10:01:09.644425 Set Vref, RX VrefLevel [Byte0]: 49
7833 10:01:09.647237 [Byte1]: 49
7834 10:01:09.651272
7835 10:01:09.651713 Set Vref, RX VrefLevel [Byte0]: 50
7836 10:01:09.654570 [Byte1]: 50
7837 10:01:09.658928
7838 10:01:09.659340 Set Vref, RX VrefLevel [Byte0]: 51
7839 10:01:09.662296 [Byte1]: 51
7840 10:01:09.666285
7841 10:01:09.666700 Set Vref, RX VrefLevel [Byte0]: 52
7842 10:01:09.670176 [Byte1]: 52
7843 10:01:09.674178
7844 10:01:09.674655 Set Vref, RX VrefLevel [Byte0]: 53
7845 10:01:09.677933 [Byte1]: 53
7846 10:01:09.682280
7847 10:01:09.682795 Set Vref, RX VrefLevel [Byte0]: 54
7848 10:01:09.685324 [Byte1]: 54
7849 10:01:09.689419
7850 10:01:09.689834 Set Vref, RX VrefLevel [Byte0]: 55
7851 10:01:09.692371 [Byte1]: 55
7852 10:01:09.696579
7853 10:01:09.696991 Set Vref, RX VrefLevel [Byte0]: 56
7854 10:01:09.699944 [Byte1]: 56
7855 10:01:09.704421
7856 10:01:09.704838 Set Vref, RX VrefLevel [Byte0]: 57
7857 10:01:09.707522 [Byte1]: 57
7858 10:01:09.712334
7859 10:01:09.712747 Set Vref, RX VrefLevel [Byte0]: 58
7860 10:01:09.715714 [Byte1]: 58
7861 10:01:09.719850
7862 10:01:09.720418 Set Vref, RX VrefLevel [Byte0]: 59
7863 10:01:09.723059 [Byte1]: 59
7864 10:01:09.727430
7865 10:01:09.728141 Set Vref, RX VrefLevel [Byte0]: 60
7866 10:01:09.730760 [Byte1]: 60
7867 10:01:09.735477
7868 10:01:09.736034 Set Vref, RX VrefLevel [Byte0]: 61
7869 10:01:09.738589 [Byte1]: 61
7870 10:01:09.742719
7871 10:01:09.743251 Set Vref, RX VrefLevel [Byte0]: 62
7872 10:01:09.745849 [Byte1]: 62
7873 10:01:09.750594
7874 10:01:09.751114 Set Vref, RX VrefLevel [Byte0]: 63
7875 10:01:09.753526 [Byte1]: 63
7876 10:01:09.757863
7877 10:01:09.758380 Set Vref, RX VrefLevel [Byte0]: 64
7878 10:01:09.760879 [Byte1]: 64
7879 10:01:09.765278
7880 10:01:09.765802 Set Vref, RX VrefLevel [Byte0]: 65
7881 10:01:09.768612 [Byte1]: 65
7882 10:01:09.772820
7883 10:01:09.773374 Set Vref, RX VrefLevel [Byte0]: 66
7884 10:01:09.776332 [Byte1]: 66
7885 10:01:09.780499
7886 10:01:09.781060 Set Vref, RX VrefLevel [Byte0]: 67
7887 10:01:09.784006 [Byte1]: 67
7888 10:01:09.788206
7889 10:01:09.788665 Set Vref, RX VrefLevel [Byte0]: 68
7890 10:01:09.791396 [Byte1]: 68
7891 10:01:09.795499
7892 10:01:09.796105 Set Vref, RX VrefLevel [Byte0]: 69
7893 10:01:09.798479 [Byte1]: 69
7894 10:01:09.802879
7895 10:01:09.803334 Set Vref, RX VrefLevel [Byte0]: 70
7896 10:01:09.806667 [Byte1]: 70
7897 10:01:09.810659
7898 10:01:09.811283 Set Vref, RX VrefLevel [Byte0]: 71
7899 10:01:09.813726 [Byte1]: 71
7900 10:01:09.818381
7901 10:01:09.818933 Set Vref, RX VrefLevel [Byte0]: 72
7902 10:01:09.821675 [Byte1]: 72
7903 10:01:09.826075
7904 10:01:09.826529 Set Vref, RX VrefLevel [Byte0]: 73
7905 10:01:09.828668 [Byte1]: 73
7906 10:01:09.833077
7907 10:01:09.833621 Set Vref, RX VrefLevel [Byte0]: 74
7908 10:01:09.836536 [Byte1]: 74
7909 10:01:09.841008
7910 10:01:09.841555 Final RX Vref Byte 0 = 53 to rank0
7911 10:01:09.843667 Final RX Vref Byte 1 = 58 to rank0
7912 10:01:09.847521 Final RX Vref Byte 0 = 53 to rank1
7913 10:01:09.850757 Final RX Vref Byte 1 = 58 to rank1==
7914 10:01:09.853779 Dram Type= 6, Freq= 0, CH_0, rank 0
7915 10:01:09.860841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7916 10:01:09.861407 ==
7917 10:01:09.861776 DQS Delay:
7918 10:01:09.863850 DQS0 = 0, DQS1 = 0
7919 10:01:09.864449 DQM Delay:
7920 10:01:09.866973 DQM0 = 128, DQM1 = 124
7921 10:01:09.867528 DQ Delay:
7922 10:01:09.870032 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7923 10:01:09.873908 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =132
7924 10:01:09.876845 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7925 10:01:09.880728 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =130
7926 10:01:09.881288
7927 10:01:09.881653
7928 10:01:09.881987
7929 10:01:09.883732 [DramC_TX_OE_Calibration] TA2
7930 10:01:09.886907 Original DQ_B0 (3 6) =30, OEN = 27
7931 10:01:09.890516 Original DQ_B1 (3 6) =30, OEN = 27
7932 10:01:09.893494 24, 0x0, End_B0=24 End_B1=24
7933 10:01:09.896715 25, 0x0, End_B0=25 End_B1=25
7934 10:01:09.897233 26, 0x0, End_B0=26 End_B1=26
7935 10:01:09.900252 27, 0x0, End_B0=27 End_B1=27
7936 10:01:09.903424 28, 0x0, End_B0=28 End_B1=28
7937 10:01:09.906322 29, 0x0, End_B0=29 End_B1=29
7938 10:01:09.909576 30, 0x0, End_B0=30 End_B1=30
7939 10:01:09.910067 31, 0x4141, End_B0=30 End_B1=30
7940 10:01:09.912866 Byte0 end_step=30 best_step=27
7941 10:01:09.916052 Byte1 end_step=30 best_step=27
7942 10:01:09.919540 Byte0 TX OE(2T, 0.5T) = (3, 3)
7943 10:01:09.922557 Byte1 TX OE(2T, 0.5T) = (3, 3)
7944 10:01:09.923094
7945 10:01:09.923432
7946 10:01:09.929607 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7947 10:01:09.932660 CH0 RK0: MR19=303, MR18=1714
7948 10:01:09.939352 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
7949 10:01:09.939769
7950 10:01:09.942642 ----->DramcWriteLeveling(PI) begin...
7951 10:01:09.943061 ==
7952 10:01:09.945588 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 10:01:09.948937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 10:01:09.952221 ==
7955 10:01:09.952637 Write leveling (Byte 0): 34 => 34
7956 10:01:09.955591 Write leveling (Byte 1): 26 => 26
7957 10:01:09.958702 DramcWriteLeveling(PI) end<-----
7958 10:01:09.959117
7959 10:01:09.959446 ==
7960 10:01:09.962342 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 10:01:09.969037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 10:01:09.969455 ==
7963 10:01:09.972316 [Gating] SW mode calibration
7964 10:01:09.978895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7965 10:01:09.982183 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7966 10:01:09.988638 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 10:01:09.992143 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 10:01:09.995091 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7969 10:01:10.001721 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7970 10:01:10.005259 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (1 1) (1 1)
7971 10:01:10.008726 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 10:01:10.015219 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 10:01:10.018195 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7974 10:01:10.021645 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7975 10:01:10.028281 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7976 10:01:10.031959 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7977 10:01:10.034800 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7978 10:01:10.041862 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7979 10:01:10.044493 1 5 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
7980 10:01:10.047872 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 10:01:10.054867 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 10:01:10.057586 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 10:01:10.061255 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7984 10:01:10.068007 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7985 10:01:10.070910 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7986 10:01:10.074306 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7987 10:01:10.080870 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7988 10:01:10.084137 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 10:01:10.087303 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 10:01:10.093942 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 10:01:10.097037 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 10:01:10.100495 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7993 10:01:10.107214 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7994 10:01:10.110708 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7995 10:01:10.113582 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7996 10:01:10.120419 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 10:01:10.123511 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 10:01:10.126566 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 10:01:10.133339 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 10:01:10.136723 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 10:01:10.140068 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 10:01:10.146546 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 10:01:10.149641 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 10:01:10.153212 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 10:01:10.159682 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 10:01:10.162864 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 10:01:10.166243 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 10:01:10.172688 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8009 10:01:10.176578 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8010 10:01:10.179665 Total UI for P1: 0, mck2ui 16
8011 10:01:10.182946 best dqsien dly found for B0: ( 1, 9, 8)
8012 10:01:10.186013 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8013 10:01:10.192982 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8014 10:01:10.195997 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 10:01:10.199143 Total UI for P1: 0, mck2ui 16
8016 10:01:10.202424 best dqsien dly found for B1: ( 1, 9, 20)
8017 10:01:10.205819 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8018 10:01:10.209213 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8019 10:01:10.209760
8020 10:01:10.212786 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8021 10:01:10.215700 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8022 10:01:10.219235 [Gating] SW calibration Done
8023 10:01:10.219782 ==
8024 10:01:10.222261 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 10:01:10.229143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 10:01:10.229604 ==
8027 10:01:10.229968 RX Vref Scan: 0
8028 10:01:10.230305
8029 10:01:10.231983 RX Vref 0 -> 0, step: 1
8030 10:01:10.232441
8031 10:01:10.235763 RX Delay 0 -> 252, step: 8
8032 10:01:10.238801 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8033 10:01:10.242039 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8034 10:01:10.245092 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8035 10:01:10.248650 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8036 10:01:10.255468 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8037 10:01:10.258116 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8038 10:01:10.261652 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8039 10:01:10.264638 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8040 10:01:10.271427 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
8041 10:01:10.274737 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
8042 10:01:10.277990 iDelay=192, Bit 10, Center 131 (72 ~ 191) 120
8043 10:01:10.281391 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
8044 10:01:10.284237 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
8045 10:01:10.291413 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
8046 10:01:10.294342 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8047 10:01:10.297348 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
8048 10:01:10.297867 ==
8049 10:01:10.300793 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 10:01:10.304322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 10:01:10.307326 ==
8052 10:01:10.307934 DQS Delay:
8053 10:01:10.308306 DQS0 = 0, DQS1 = 0
8054 10:01:10.310581 DQM Delay:
8055 10:01:10.310995 DQM0 = 131, DQM1 = 124
8056 10:01:10.314100 DQ Delay:
8057 10:01:10.317490 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8058 10:01:10.320893 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8059 10:01:10.324010 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =115
8060 10:01:10.327337 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8061 10:01:10.327749
8062 10:01:10.328141
8063 10:01:10.328453 ==
8064 10:01:10.330832 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 10:01:10.333820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 10:01:10.334065 ==
8067 10:01:10.336992
8068 10:01:10.337212
8069 10:01:10.337388 TX Vref Scan disable
8070 10:01:10.340336 == TX Byte 0 ==
8071 10:01:10.343164 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8072 10:01:10.347313 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8073 10:01:10.349941 == TX Byte 1 ==
8074 10:01:10.353485 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8075 10:01:10.357073 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8076 10:01:10.360141 ==
8077 10:01:10.363362 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 10:01:10.366724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 10:01:10.367090 ==
8080 10:01:10.379859
8081 10:01:10.383210 TX Vref early break, caculate TX vref
8082 10:01:10.386431 TX Vref=16, minBit 3, minWin=23, winSum=381
8083 10:01:10.389547 TX Vref=18, minBit 8, minWin=23, winSum=390
8084 10:01:10.393194 TX Vref=20, minBit 2, minWin=24, winSum=395
8085 10:01:10.396219 TX Vref=22, minBit 2, minWin=24, winSum=404
8086 10:01:10.399398 TX Vref=24, minBit 1, minWin=25, winSum=410
8087 10:01:10.406496 TX Vref=26, minBit 4, minWin=25, winSum=422
8088 10:01:10.409357 TX Vref=28, minBit 10, minWin=25, winSum=419
8089 10:01:10.412572 TX Vref=30, minBit 0, minWin=25, winSum=411
8090 10:01:10.415814 TX Vref=32, minBit 7, minWin=24, winSum=403
8091 10:01:10.419371 TX Vref=34, minBit 1, minWin=24, winSum=399
8092 10:01:10.425693 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 26
8093 10:01:10.426150
8094 10:01:10.430031 Final TX Range 0 Vref 26
8095 10:01:10.430742
8096 10:01:10.431096 ==
8097 10:01:10.432386 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 10:01:10.436041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 10:01:10.436556 ==
8100 10:01:10.436912
8101 10:01:10.437249
8102 10:01:10.439276 TX Vref Scan disable
8103 10:01:10.445675 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8104 10:01:10.446223 == TX Byte 0 ==
8105 10:01:10.448559 u2DelayCellOfst[0]=10 cells (3 PI)
8106 10:01:10.452372 u2DelayCellOfst[1]=10 cells (3 PI)
8107 10:01:10.456084 u2DelayCellOfst[2]=7 cells (2 PI)
8108 10:01:10.458911 u2DelayCellOfst[3]=10 cells (3 PI)
8109 10:01:10.462338 u2DelayCellOfst[4]=3 cells (1 PI)
8110 10:01:10.465568 u2DelayCellOfst[5]=0 cells (0 PI)
8111 10:01:10.468985 u2DelayCellOfst[6]=14 cells (4 PI)
8112 10:01:10.472400 u2DelayCellOfst[7]=14 cells (4 PI)
8113 10:01:10.475782 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8114 10:01:10.478523 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8115 10:01:10.481862 == TX Byte 1 ==
8116 10:01:10.485401 u2DelayCellOfst[8]=0 cells (0 PI)
8117 10:01:10.488617 u2DelayCellOfst[9]=0 cells (0 PI)
8118 10:01:10.491815 u2DelayCellOfst[10]=3 cells (1 PI)
8119 10:01:10.495020 u2DelayCellOfst[11]=3 cells (1 PI)
8120 10:01:10.495434 u2DelayCellOfst[12]=7 cells (2 PI)
8121 10:01:10.498330 u2DelayCellOfst[13]=10 cells (3 PI)
8122 10:01:10.501564 u2DelayCellOfst[14]=14 cells (4 PI)
8123 10:01:10.504816 u2DelayCellOfst[15]=10 cells (3 PI)
8124 10:01:10.511699 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8125 10:01:10.515113 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8126 10:01:10.515625 DramC Write-DBI on
8127 10:01:10.518206 ==
8128 10:01:10.521717 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 10:01:10.524521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 10:01:10.525135 ==
8131 10:01:10.525489
8132 10:01:10.525796
8133 10:01:10.528008 TX Vref Scan disable
8134 10:01:10.528422 == TX Byte 0 ==
8135 10:01:10.534965 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8136 10:01:10.535667 == TX Byte 1 ==
8137 10:01:10.537931 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8138 10:01:10.541119 DramC Write-DBI off
8139 10:01:10.541629
8140 10:01:10.541960 [DATLAT]
8141 10:01:10.544479 Freq=1600, CH0 RK1
8142 10:01:10.544893
8143 10:01:10.545221 DATLAT Default: 0xf
8144 10:01:10.548119 0, 0xFFFF, sum = 0
8145 10:01:10.548707 1, 0xFFFF, sum = 0
8146 10:01:10.551205 2, 0xFFFF, sum = 0
8147 10:01:10.551723 3, 0xFFFF, sum = 0
8148 10:01:10.554302 4, 0xFFFF, sum = 0
8149 10:01:10.557707 5, 0xFFFF, sum = 0
8150 10:01:10.558221 6, 0xFFFF, sum = 0
8151 10:01:10.561265 7, 0xFFFF, sum = 0
8152 10:01:10.561781 8, 0xFFFF, sum = 0
8153 10:01:10.564025 9, 0xFFFF, sum = 0
8154 10:01:10.564459 10, 0xFFFF, sum = 0
8155 10:01:10.567462 11, 0xFFFF, sum = 0
8156 10:01:10.568026 12, 0xFFFF, sum = 0
8157 10:01:10.570783 13, 0xFFFF, sum = 0
8158 10:01:10.571318 14, 0x0, sum = 1
8159 10:01:10.574302 15, 0x0, sum = 2
8160 10:01:10.574822 16, 0x0, sum = 3
8161 10:01:10.577816 17, 0x0, sum = 4
8162 10:01:10.578337 best_step = 15
8163 10:01:10.578664
8164 10:01:10.578968 ==
8165 10:01:10.580643 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 10:01:10.587222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 10:01:10.587803 ==
8168 10:01:10.588202 RX Vref Scan: 0
8169 10:01:10.588516
8170 10:01:10.590203 RX Vref 0 -> 0, step: 1
8171 10:01:10.590613
8172 10:01:10.593544 RX Delay 11 -> 252, step: 4
8173 10:01:10.597204 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8174 10:01:10.600249 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8175 10:01:10.603208 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8176 10:01:10.610144 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8177 10:01:10.613555 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8178 10:01:10.616760 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8179 10:01:10.619860 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8180 10:01:10.623183 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8181 10:01:10.630325 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8182 10:01:10.633569 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8183 10:01:10.636216 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8184 10:01:10.639646 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8185 10:01:10.646277 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8186 10:01:10.649433 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8187 10:01:10.653693 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8188 10:01:10.656088 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8189 10:01:10.656502 ==
8190 10:01:10.659708 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 10:01:10.666073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 10:01:10.666587 ==
8193 10:01:10.666916 DQS Delay:
8194 10:01:10.670070 DQS0 = 0, DQS1 = 0
8195 10:01:10.670581 DQM Delay:
8196 10:01:10.670913 DQM0 = 128, DQM1 = 124
8197 10:01:10.672719 DQ Delay:
8198 10:01:10.676123 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8199 10:01:10.679540 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8200 10:01:10.683166 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8201 10:01:10.686023 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
8202 10:01:10.686534
8203 10:01:10.686861
8204 10:01:10.687163
8205 10:01:10.689665 [DramC_TX_OE_Calibration] TA2
8206 10:01:10.692252 Original DQ_B0 (3 6) =30, OEN = 27
8207 10:01:10.695561 Original DQ_B1 (3 6) =30, OEN = 27
8208 10:01:10.699326 24, 0x0, End_B0=24 End_B1=24
8209 10:01:10.702317 25, 0x0, End_B0=25 End_B1=25
8210 10:01:10.702737 26, 0x0, End_B0=26 End_B1=26
8211 10:01:10.705892 27, 0x0, End_B0=27 End_B1=27
8212 10:01:10.709283 28, 0x0, End_B0=28 End_B1=28
8213 10:01:10.713124 29, 0x0, End_B0=29 End_B1=29
8214 10:01:10.713645 30, 0x0, End_B0=30 End_B1=30
8215 10:01:10.715450 31, 0x5151, End_B0=30 End_B1=30
8216 10:01:10.718763 Byte0 end_step=30 best_step=27
8217 10:01:10.722782 Byte1 end_step=30 best_step=27
8218 10:01:10.725257 Byte0 TX OE(2T, 0.5T) = (3, 3)
8219 10:01:10.728588 Byte1 TX OE(2T, 0.5T) = (3, 3)
8220 10:01:10.729000
8221 10:01:10.729323
8222 10:01:10.735698 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8223 10:01:10.738830 CH0 RK1: MR19=303, MR18=1412
8224 10:01:10.745252 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8225 10:01:10.748577 [RxdqsGatingPostProcess] freq 1600
8226 10:01:10.755342 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8227 10:01:10.755958 best DQS0 dly(2T, 0.5T) = (1, 1)
8228 10:01:10.758700 best DQS1 dly(2T, 0.5T) = (1, 1)
8229 10:01:10.761389 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8230 10:01:10.765047 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8231 10:01:10.768015 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 10:01:10.771698 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 10:01:10.774584 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 10:01:10.777935 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 10:01:10.781562 Pre-setting of DQS Precalculation
8236 10:01:10.784493 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8237 10:01:10.787773 ==
8238 10:01:10.788337 Dram Type= 6, Freq= 0, CH_1, rank 0
8239 10:01:10.794400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 10:01:10.794912 ==
8241 10:01:10.797590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8242 10:01:10.804197 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8243 10:01:10.807393 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8244 10:01:10.813893 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8245 10:01:10.822153 [CA 0] Center 42 (12~72) winsize 61
8246 10:01:10.825376 [CA 1] Center 42 (12~72) winsize 61
8247 10:01:10.829606 [CA 2] Center 38 (9~67) winsize 59
8248 10:01:10.832037 [CA 3] Center 37 (8~66) winsize 59
8249 10:01:10.835887 [CA 4] Center 37 (7~67) winsize 61
8250 10:01:10.839207 [CA 5] Center 36 (7~66) winsize 60
8251 10:01:10.839762
8252 10:01:10.841989 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8253 10:01:10.842543
8254 10:01:10.848573 [CATrainingPosCal] consider 1 rank data
8255 10:01:10.849133 u2DelayCellTimex100 = 275/100 ps
8256 10:01:10.854806 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8257 10:01:10.858403 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8258 10:01:10.862384 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8259 10:01:10.864768 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8260 10:01:10.868806 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8261 10:01:10.872252 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8262 10:01:10.872783
8263 10:01:10.874809 CA PerBit enable=1, Macro0, CA PI delay=36
8264 10:01:10.875222
8265 10:01:10.878367 [CBTSetCACLKResult] CA Dly = 36
8266 10:01:10.881302 CS Dly: 8 (0~39)
8267 10:01:10.885134 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8268 10:01:10.888602 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8269 10:01:10.889281 ==
8270 10:01:10.891341 Dram Type= 6, Freq= 0, CH_1, rank 1
8271 10:01:10.897673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 10:01:10.898094 ==
8273 10:01:10.901037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8274 10:01:10.907938 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8275 10:01:10.911791 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8276 10:01:10.918044 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8277 10:01:10.925332 [CA 0] Center 42 (13~72) winsize 60
8278 10:01:10.928710 [CA 1] Center 43 (14~72) winsize 59
8279 10:01:10.932320 [CA 2] Center 38 (9~68) winsize 60
8280 10:01:10.935388 [CA 3] Center 37 (8~66) winsize 59
8281 10:01:10.938911 [CA 4] Center 38 (8~68) winsize 61
8282 10:01:10.941976 [CA 5] Center 37 (7~67) winsize 61
8283 10:01:10.942485
8284 10:01:10.945323 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8285 10:01:10.945738
8286 10:01:10.948718 [CATrainingPosCal] consider 2 rank data
8287 10:01:10.951803 u2DelayCellTimex100 = 275/100 ps
8288 10:01:10.958839 CA0 delay=42 (13~72),Diff = 6 PI (21 cell)
8289 10:01:10.961883 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8290 10:01:10.965179 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8291 10:01:10.968493 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8292 10:01:10.971976 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8293 10:01:10.975490 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8294 10:01:10.976047
8295 10:01:10.978324 CA PerBit enable=1, Macro0, CA PI delay=36
8296 10:01:10.978736
8297 10:01:10.981433 [CBTSetCACLKResult] CA Dly = 36
8298 10:01:10.984751 CS Dly: 9 (0~42)
8299 10:01:10.988000 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8300 10:01:10.991220 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8301 10:01:10.991629
8302 10:01:10.995282 ----->DramcWriteLeveling(PI) begin...
8303 10:01:10.995695 ==
8304 10:01:10.998244 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 10:01:11.005010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 10:01:11.005428 ==
8307 10:01:11.007808 Write leveling (Byte 0): 24 => 24
8308 10:01:11.008267 Write leveling (Byte 1): 26 => 26
8309 10:01:11.011898 DramcWriteLeveling(PI) end<-----
8310 10:01:11.012463
8311 10:01:11.014761 ==
8312 10:01:11.015170 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 10:01:11.020982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 10:01:11.021393 ==
8315 10:01:11.024916 [Gating] SW mode calibration
8316 10:01:11.031146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8317 10:01:11.034676 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8318 10:01:11.041323 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 10:01:11.044623 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 10:01:11.048168 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 10:01:11.054120 1 4 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8322 10:01:11.057721 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 10:01:11.060589 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 10:01:11.067559 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 10:01:11.070721 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 10:01:11.074213 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 10:01:11.080484 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 10:01:11.084049 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 10:01:11.086974 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8330 10:01:11.093765 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8331 10:01:11.096905 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 10:01:11.100261 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 10:01:11.106759 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 10:01:11.110588 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 10:01:11.114048 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 10:01:11.119817 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 10:01:11.123343 1 6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8338 10:01:11.126523 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 10:01:11.133438 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 10:01:11.136610 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 10:01:11.140059 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 10:01:11.146425 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 10:01:11.149231 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 10:01:11.152660 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 10:01:11.159605 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8346 10:01:11.162857 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8347 10:01:11.166026 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 10:01:11.172984 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 10:01:11.176182 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 10:01:11.180058 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 10:01:11.185920 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 10:01:11.189176 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 10:01:11.192566 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 10:01:11.198835 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 10:01:11.202185 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 10:01:11.205648 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 10:01:11.212347 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 10:01:11.215475 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 10:01:11.218423 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 10:01:11.225485 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 10:01:11.228783 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8362 10:01:11.232067 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8363 10:01:11.235579 Total UI for P1: 0, mck2ui 16
8364 10:01:11.238968 best dqsien dly found for B0: ( 1, 9, 12)
8365 10:01:11.245516 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 10:01:11.248417 Total UI for P1: 0, mck2ui 16
8367 10:01:11.251893 best dqsien dly found for B1: ( 1, 9, 14)
8368 10:01:11.255011 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8369 10:01:11.258635 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8370 10:01:11.259190
8371 10:01:11.261842 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8372 10:01:11.265512 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8373 10:01:11.268536 [Gating] SW calibration Done
8374 10:01:11.269102 ==
8375 10:01:11.271465 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 10:01:11.275238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 10:01:11.275798 ==
8378 10:01:11.277852 RX Vref Scan: 0
8379 10:01:11.278321
8380 10:01:11.281862 RX Vref 0 -> 0, step: 1
8381 10:01:11.282413
8382 10:01:11.282776 RX Delay 0 -> 252, step: 8
8383 10:01:11.288016 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8384 10:01:11.291287 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8385 10:01:11.295406 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8386 10:01:11.297913 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8387 10:01:11.301406 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8388 10:01:11.307887 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8389 10:01:11.311037 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8390 10:01:11.314258 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8391 10:01:11.317693 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8392 10:01:11.321091 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8393 10:01:11.327332 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8394 10:01:11.330561 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8395 10:01:11.334325 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8396 10:01:11.337612 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8397 10:01:11.344091 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8398 10:01:11.347590 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8399 10:01:11.348163 ==
8400 10:01:11.350679 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 10:01:11.353949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 10:01:11.354503 ==
8403 10:01:11.357095 DQS Delay:
8404 10:01:11.357567 DQS0 = 0, DQS1 = 0
8405 10:01:11.357929 DQM Delay:
8406 10:01:11.360405 DQM0 = 134, DQM1 = 129
8407 10:01:11.360819 DQ Delay:
8408 10:01:11.364130 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8409 10:01:11.367364 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8410 10:01:11.373936 DQ8 =115, DQ9 =119, DQ10 =127, DQ11 =123
8411 10:01:11.376964 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8412 10:01:11.377662
8413 10:01:11.378017
8414 10:01:11.378326 ==
8415 10:01:11.380270 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 10:01:11.383720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 10:01:11.384350 ==
8418 10:01:11.384694
8419 10:01:11.385002
8420 10:01:11.386902 TX Vref Scan disable
8421 10:01:11.390247 == TX Byte 0 ==
8422 10:01:11.393234 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8423 10:01:11.397130 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8424 10:01:11.400035 == TX Byte 1 ==
8425 10:01:11.403032 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8426 10:01:11.406197 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8427 10:01:11.406613 ==
8428 10:01:11.410041 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 10:01:11.412876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 10:01:11.416236 ==
8431 10:01:11.427500
8432 10:01:11.430614 TX Vref early break, caculate TX vref
8433 10:01:11.434622 TX Vref=16, minBit 6, minWin=22, winSum=372
8434 10:01:11.437433 TX Vref=18, minBit 9, minWin=22, winSum=381
8435 10:01:11.440358 TX Vref=20, minBit 8, minWin=23, winSum=391
8436 10:01:11.443524 TX Vref=22, minBit 9, minWin=23, winSum=397
8437 10:01:11.446998 TX Vref=24, minBit 9, minWin=24, winSum=408
8438 10:01:11.453876 TX Vref=26, minBit 9, minWin=24, winSum=414
8439 10:01:11.457063 TX Vref=28, minBit 15, minWin=25, winSum=422
8440 10:01:11.460180 TX Vref=30, minBit 0, minWin=25, winSum=410
8441 10:01:11.463945 TX Vref=32, minBit 0, minWin=24, winSum=401
8442 10:01:11.467187 TX Vref=34, minBit 1, minWin=23, winSum=393
8443 10:01:11.473671 [TxChooseVref] Worse bit 15, Min win 25, Win sum 422, Final Vref 28
8444 10:01:11.474183
8445 10:01:11.476712 Final TX Range 0 Vref 28
8446 10:01:11.477131
8447 10:01:11.477459 ==
8448 10:01:11.480265 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 10:01:11.483538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 10:01:11.484112 ==
8451 10:01:11.484453
8452 10:01:11.484758
8453 10:01:11.486653 TX Vref Scan disable
8454 10:01:11.493183 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8455 10:01:11.493677 == TX Byte 0 ==
8456 10:01:11.496778 u2DelayCellOfst[0]=14 cells (4 PI)
8457 10:01:11.499741 u2DelayCellOfst[1]=10 cells (3 PI)
8458 10:01:11.503077 u2DelayCellOfst[2]=0 cells (0 PI)
8459 10:01:11.506441 u2DelayCellOfst[3]=3 cells (1 PI)
8460 10:01:11.509912 u2DelayCellOfst[4]=7 cells (2 PI)
8461 10:01:11.513002 u2DelayCellOfst[5]=14 cells (4 PI)
8462 10:01:11.516329 u2DelayCellOfst[6]=14 cells (4 PI)
8463 10:01:11.519613 u2DelayCellOfst[7]=3 cells (1 PI)
8464 10:01:11.522831 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8465 10:01:11.526191 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8466 10:01:11.529408 == TX Byte 1 ==
8467 10:01:11.532700 u2DelayCellOfst[8]=0 cells (0 PI)
8468 10:01:11.536327 u2DelayCellOfst[9]=3 cells (1 PI)
8469 10:01:11.539408 u2DelayCellOfst[10]=10 cells (3 PI)
8470 10:01:11.539833 u2DelayCellOfst[11]=3 cells (1 PI)
8471 10:01:11.542658 u2DelayCellOfst[12]=14 cells (4 PI)
8472 10:01:11.546100 u2DelayCellOfst[13]=14 cells (4 PI)
8473 10:01:11.549623 u2DelayCellOfst[14]=17 cells (5 PI)
8474 10:01:11.553023 u2DelayCellOfst[15]=17 cells (5 PI)
8475 10:01:11.559448 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8476 10:01:11.562804 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8477 10:01:11.563441 DramC Write-DBI on
8478 10:01:11.563951 ==
8479 10:01:11.565575 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 10:01:11.572838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 10:01:11.573343 ==
8482 10:01:11.573679
8483 10:01:11.573984
8484 10:01:11.575702 TX Vref Scan disable
8485 10:01:11.576281 == TX Byte 0 ==
8486 10:01:11.582372 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8487 10:01:11.582789 == TX Byte 1 ==
8488 10:01:11.586048 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8489 10:01:11.588862 DramC Write-DBI off
8490 10:01:11.589310
8491 10:01:11.589642 [DATLAT]
8492 10:01:11.592210 Freq=1600, CH1 RK0
8493 10:01:11.592700
8494 10:01:11.593031 DATLAT Default: 0xf
8495 10:01:11.595754 0, 0xFFFF, sum = 0
8496 10:01:11.596224 1, 0xFFFF, sum = 0
8497 10:01:11.599084 2, 0xFFFF, sum = 0
8498 10:01:11.599575 3, 0xFFFF, sum = 0
8499 10:01:11.601915 4, 0xFFFF, sum = 0
8500 10:01:11.602413 5, 0xFFFF, sum = 0
8501 10:01:11.605288 6, 0xFFFF, sum = 0
8502 10:01:11.605798 7, 0xFFFF, sum = 0
8503 10:01:11.608545 8, 0xFFFF, sum = 0
8504 10:01:11.612207 9, 0xFFFF, sum = 0
8505 10:01:11.612633 10, 0xFFFF, sum = 0
8506 10:01:11.614967 11, 0xFFFF, sum = 0
8507 10:01:11.615398 12, 0xFFFF, sum = 0
8508 10:01:11.618696 13, 0xFFFF, sum = 0
8509 10:01:11.619373 14, 0x0, sum = 1
8510 10:01:11.621498 15, 0x0, sum = 2
8511 10:01:11.621920 16, 0x0, sum = 3
8512 10:01:11.625456 17, 0x0, sum = 4
8513 10:01:11.625950 best_step = 15
8514 10:01:11.626279
8515 10:01:11.626583 ==
8516 10:01:11.628607 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 10:01:11.632090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 10:01:11.635295 ==
8519 10:01:11.635901 RX Vref Scan: 1
8520 10:01:11.636307
8521 10:01:11.638548 Set Vref Range= 24 -> 127
8522 10:01:11.638992
8523 10:01:11.639326 RX Vref 24 -> 127, step: 1
8524 10:01:11.641759
8525 10:01:11.642207 RX Delay 19 -> 252, step: 4
8526 10:01:11.642541
8527 10:01:11.645536 Set Vref, RX VrefLevel [Byte0]: 24
8528 10:01:11.648322 [Byte1]: 24
8529 10:01:11.652001
8530 10:01:11.652448 Set Vref, RX VrefLevel [Byte0]: 25
8531 10:01:11.655084 [Byte1]: 25
8532 10:01:11.659582
8533 10:01:11.660151 Set Vref, RX VrefLevel [Byte0]: 26
8534 10:01:11.662592 [Byte1]: 26
8535 10:01:11.667334
8536 10:01:11.667865 Set Vref, RX VrefLevel [Byte0]: 27
8537 10:01:11.670454 [Byte1]: 27
8538 10:01:11.674649
8539 10:01:11.675182 Set Vref, RX VrefLevel [Byte0]: 28
8540 10:01:11.677948 [Byte1]: 28
8541 10:01:11.682548
8542 10:01:11.683071 Set Vref, RX VrefLevel [Byte0]: 29
8543 10:01:11.685580 [Byte1]: 29
8544 10:01:11.690178
8545 10:01:11.690677 Set Vref, RX VrefLevel [Byte0]: 30
8546 10:01:11.693184 [Byte1]: 30
8547 10:01:11.697183
8548 10:01:11.697666 Set Vref, RX VrefLevel [Byte0]: 31
8549 10:01:11.700337 [Byte1]: 31
8550 10:01:11.704974
8551 10:01:11.705422 Set Vref, RX VrefLevel [Byte0]: 32
8552 10:01:11.708681 [Byte1]: 32
8553 10:01:11.712282
8554 10:01:11.712886 Set Vref, RX VrefLevel [Byte0]: 33
8555 10:01:11.716009 [Byte1]: 33
8556 10:01:11.719849
8557 10:01:11.720311 Set Vref, RX VrefLevel [Byte0]: 34
8558 10:01:11.723488 [Byte1]: 34
8559 10:01:11.727792
8560 10:01:11.728279 Set Vref, RX VrefLevel [Byte0]: 35
8561 10:01:11.730730 [Byte1]: 35
8562 10:01:11.735266
8563 10:01:11.735673 Set Vref, RX VrefLevel [Byte0]: 36
8564 10:01:11.738948 [Byte1]: 36
8565 10:01:11.742857
8566 10:01:11.743368 Set Vref, RX VrefLevel [Byte0]: 37
8567 10:01:11.746091 [Byte1]: 37
8568 10:01:11.750483
8569 10:01:11.750996 Set Vref, RX VrefLevel [Byte0]: 38
8570 10:01:11.753859 [Byte1]: 38
8571 10:01:11.758095
8572 10:01:11.758607 Set Vref, RX VrefLevel [Byte0]: 39
8573 10:01:11.761459 [Byte1]: 39
8574 10:01:11.765625
8575 10:01:11.766235 Set Vref, RX VrefLevel [Byte0]: 40
8576 10:01:11.768879 [Byte1]: 40
8577 10:01:11.773458
8578 10:01:11.773970 Set Vref, RX VrefLevel [Byte0]: 41
8579 10:01:11.776525 [Byte1]: 41
8580 10:01:11.780501
8581 10:01:11.780911 Set Vref, RX VrefLevel [Byte0]: 42
8582 10:01:11.784064 [Byte1]: 42
8583 10:01:11.788151
8584 10:01:11.788607 Set Vref, RX VrefLevel [Byte0]: 43
8585 10:01:11.791197 [Byte1]: 43
8586 10:01:11.795612
8587 10:01:11.796245 Set Vref, RX VrefLevel [Byte0]: 44
8588 10:01:11.799512 [Byte1]: 44
8589 10:01:11.803160
8590 10:01:11.803593 Set Vref, RX VrefLevel [Byte0]: 45
8591 10:01:11.806346 [Byte1]: 45
8592 10:01:11.811369
8593 10:01:11.812017 Set Vref, RX VrefLevel [Byte0]: 46
8594 10:01:11.814540 [Byte1]: 46
8595 10:01:11.818584
8596 10:01:11.819098 Set Vref, RX VrefLevel [Byte0]: 47
8597 10:01:11.821805 [Byte1]: 47
8598 10:01:11.826108
8599 10:01:11.826525 Set Vref, RX VrefLevel [Byte0]: 48
8600 10:01:11.829578 [Byte1]: 48
8601 10:01:11.833644
8602 10:01:11.834057 Set Vref, RX VrefLevel [Byte0]: 49
8603 10:01:11.837030 [Byte1]: 49
8604 10:01:11.841727
8605 10:01:11.842242 Set Vref, RX VrefLevel [Byte0]: 50
8606 10:01:11.844248 [Byte1]: 50
8607 10:01:11.849027
8608 10:01:11.849533 Set Vref, RX VrefLevel [Byte0]: 51
8609 10:01:11.852016 [Byte1]: 51
8610 10:01:11.856464
8611 10:01:11.857009 Set Vref, RX VrefLevel [Byte0]: 52
8612 10:01:11.859520 [Byte1]: 52
8613 10:01:11.863676
8614 10:01:11.864205 Set Vref, RX VrefLevel [Byte0]: 53
8615 10:01:11.867492 [Byte1]: 53
8616 10:01:11.871351
8617 10:01:11.871831 Set Vref, RX VrefLevel [Byte0]: 54
8618 10:01:11.874959 [Byte1]: 54
8619 10:01:11.879405
8620 10:01:11.879882 Set Vref, RX VrefLevel [Byte0]: 55
8621 10:01:11.882413 [Byte1]: 55
8622 10:01:11.886993
8623 10:01:11.887504 Set Vref, RX VrefLevel [Byte0]: 56
8624 10:01:11.890087 [Byte1]: 56
8625 10:01:11.894164
8626 10:01:11.894676 Set Vref, RX VrefLevel [Byte0]: 57
8627 10:01:11.897438 [Byte1]: 57
8628 10:01:11.902147
8629 10:01:11.902558 Set Vref, RX VrefLevel [Byte0]: 58
8630 10:01:11.905129 [Byte1]: 58
8631 10:01:11.909048
8632 10:01:11.909489 Set Vref, RX VrefLevel [Byte0]: 59
8633 10:01:11.912936 [Byte1]: 59
8634 10:01:11.916595
8635 10:01:11.917154 Set Vref, RX VrefLevel [Byte0]: 60
8636 10:01:11.919798 [Byte1]: 60
8637 10:01:11.924244
8638 10:01:11.924669 Set Vref, RX VrefLevel [Byte0]: 61
8639 10:01:11.927726 [Byte1]: 61
8640 10:01:11.932375
8641 10:01:11.932886 Set Vref, RX VrefLevel [Byte0]: 62
8642 10:01:11.935683 [Byte1]: 62
8643 10:01:11.939262
8644 10:01:11.939673 Set Vref, RX VrefLevel [Byte0]: 63
8645 10:01:11.942913 [Byte1]: 63
8646 10:01:11.947317
8647 10:01:11.947822 Set Vref, RX VrefLevel [Byte0]: 64
8648 10:01:11.950505 [Byte1]: 64
8649 10:01:11.954855
8650 10:01:11.955425 Set Vref, RX VrefLevel [Byte0]: 65
8651 10:01:11.958235 [Byte1]: 65
8652 10:01:11.962617
8653 10:01:11.963128 Set Vref, RX VrefLevel [Byte0]: 66
8654 10:01:11.966069 [Byte1]: 66
8655 10:01:11.970002
8656 10:01:11.970750 Set Vref, RX VrefLevel [Byte0]: 67
8657 10:01:11.973101 [Byte1]: 67
8658 10:01:11.977316
8659 10:01:11.977970 Set Vref, RX VrefLevel [Byte0]: 68
8660 10:01:11.980825 [Byte1]: 68
8661 10:01:11.985006
8662 10:01:11.985418 Set Vref, RX VrefLevel [Byte0]: 69
8663 10:01:11.988177 [Byte1]: 69
8664 10:01:11.992546
8665 10:01:11.992957 Set Vref, RX VrefLevel [Byte0]: 70
8666 10:01:11.995711 [Byte1]: 70
8667 10:01:12.000246
8668 10:01:12.000466 Final RX Vref Byte 0 = 56 to rank0
8669 10:01:12.003749 Final RX Vref Byte 1 = 60 to rank0
8670 10:01:12.006296 Final RX Vref Byte 0 = 56 to rank1
8671 10:01:12.009734 Final RX Vref Byte 1 = 60 to rank1==
8672 10:01:12.013315 Dram Type= 6, Freq= 0, CH_1, rank 0
8673 10:01:12.019853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8674 10:01:12.020058 ==
8675 10:01:12.020202 DQS Delay:
8676 10:01:12.023062 DQS0 = 0, DQS1 = 0
8677 10:01:12.023241 DQM Delay:
8678 10:01:12.023382 DQM0 = 132, DQM1 = 128
8679 10:01:12.026975 DQ Delay:
8680 10:01:12.029552 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =130
8681 10:01:12.032952 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8682 10:01:12.035840 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8683 10:01:12.039412 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8684 10:01:12.039591
8685 10:01:12.039731
8686 10:01:12.039861
8687 10:01:12.042737 [DramC_TX_OE_Calibration] TA2
8688 10:01:12.046006 Original DQ_B0 (3 6) =30, OEN = 27
8689 10:01:12.048990 Original DQ_B1 (3 6) =30, OEN = 27
8690 10:01:12.052954 24, 0x0, End_B0=24 End_B1=24
8691 10:01:12.055599 25, 0x0, End_B0=25 End_B1=25
8692 10:01:12.055836 26, 0x0, End_B0=26 End_B1=26
8693 10:01:12.059258 27, 0x0, End_B0=27 End_B1=27
8694 10:01:12.062808 28, 0x0, End_B0=28 End_B1=28
8695 10:01:12.065502 29, 0x0, End_B0=29 End_B1=29
8696 10:01:12.069316 30, 0x0, End_B0=30 End_B1=30
8697 10:01:12.069742 31, 0x4141, End_B0=30 End_B1=30
8698 10:01:12.072328 Byte0 end_step=30 best_step=27
8699 10:01:12.076127 Byte1 end_step=30 best_step=27
8700 10:01:12.079314 Byte0 TX OE(2T, 0.5T) = (3, 3)
8701 10:01:12.082576 Byte1 TX OE(2T, 0.5T) = (3, 3)
8702 10:01:12.083100
8703 10:01:12.083449
8704 10:01:12.089317 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8705 10:01:12.092249 CH1 RK0: MR19=303, MR18=D17
8706 10:01:12.099005 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8707 10:01:12.099540
8708 10:01:12.102210 ----->DramcWriteLeveling(PI) begin...
8709 10:01:12.102634 ==
8710 10:01:12.104964 Dram Type= 6, Freq= 0, CH_1, rank 1
8711 10:01:12.108267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8712 10:01:12.108686 ==
8713 10:01:12.111615 Write leveling (Byte 0): 24 => 24
8714 10:01:12.114957 Write leveling (Byte 1): 26 => 26
8715 10:01:12.118382 DramcWriteLeveling(PI) end<-----
8716 10:01:12.118794
8717 10:01:12.119124 ==
8718 10:01:12.121707 Dram Type= 6, Freq= 0, CH_1, rank 1
8719 10:01:12.128377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 10:01:12.128812 ==
8721 10:01:12.129147 [Gating] SW mode calibration
8722 10:01:12.138538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8723 10:01:12.141919 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8724 10:01:12.148443 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8725 10:01:12.151604 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8726 10:01:12.154594 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8727 10:01:12.158850 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8728 10:01:12.164641 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8729 10:01:12.168187 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8730 10:01:12.174874 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8731 10:01:12.177909 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 10:01:12.181072 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 10:01:12.187268 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8734 10:01:12.190759 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8735 10:01:12.193956 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8736 10:01:12.200532 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 10:01:12.204082 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 10:01:12.207207 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 10:01:12.214228 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 10:01:12.217819 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 10:01:12.220422 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8742 10:01:12.227008 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8743 10:01:12.230320 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8744 10:01:12.233916 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8745 10:01:12.240512 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8746 10:01:12.243693 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8747 10:01:12.247046 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 10:01:12.253749 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 10:01:12.256985 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8750 10:01:12.260117 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8751 10:01:12.263845 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8752 10:01:12.269915 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8753 10:01:12.273185 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 10:01:12.276444 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 10:01:12.283492 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 10:01:12.286708 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 10:01:12.289986 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 10:01:12.296413 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 10:01:12.299892 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 10:01:12.303205 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 10:01:12.309906 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 10:01:12.313412 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 10:01:12.316355 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 10:01:12.323292 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 10:01:12.326113 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8766 10:01:12.332725 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8767 10:01:12.336477 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8768 10:01:12.339236 Total UI for P1: 0, mck2ui 16
8769 10:01:12.342945 best dqsien dly found for B0: ( 1, 9, 6)
8770 10:01:12.345873 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 10:01:12.349073 Total UI for P1: 0, mck2ui 16
8772 10:01:12.352541 best dqsien dly found for B1: ( 1, 9, 12)
8773 10:01:12.355802 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8774 10:01:12.358954 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8775 10:01:12.359370
8776 10:01:12.362463 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8777 10:01:12.369127 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8778 10:01:12.369642 [Gating] SW calibration Done
8779 10:01:12.369982 ==
8780 10:01:12.372717 Dram Type= 6, Freq= 0, CH_1, rank 1
8781 10:01:12.379078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8782 10:01:12.379555 ==
8783 10:01:12.379891 RX Vref Scan: 0
8784 10:01:12.380244
8785 10:01:12.382550 RX Vref 0 -> 0, step: 1
8786 10:01:12.383061
8787 10:01:12.385681 RX Delay 0 -> 252, step: 8
8788 10:01:12.389323 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8789 10:01:12.392574 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8790 10:01:12.395335 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8791 10:01:12.402361 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8792 10:01:12.405844 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8793 10:01:12.408509 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8794 10:01:12.412111 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8795 10:01:12.415516 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8796 10:01:12.422018 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8797 10:01:12.424869 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8798 10:01:12.428303 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8799 10:01:12.431526 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8800 10:01:12.435001 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8801 10:01:12.441758 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8802 10:01:12.445017 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8803 10:01:12.448008 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8804 10:01:12.448501 ==
8805 10:01:12.451623 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 10:01:12.454399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 10:01:12.458063 ==
8808 10:01:12.458583 DQS Delay:
8809 10:01:12.458921 DQS0 = 0, DQS1 = 0
8810 10:01:12.461154 DQM Delay:
8811 10:01:12.461644 DQM0 = 134, DQM1 = 131
8812 10:01:12.464317 DQ Delay:
8813 10:01:12.467632 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8814 10:01:12.471428 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =135
8815 10:01:12.474366 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8816 10:01:12.477807 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8817 10:01:12.478239
8818 10:01:12.478564
8819 10:01:12.478871 ==
8820 10:01:12.481527 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 10:01:12.484685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 10:01:12.487510 ==
8823 10:01:12.488113
8824 10:01:12.488490
8825 10:01:12.488828 TX Vref Scan disable
8826 10:01:12.490872 == TX Byte 0 ==
8827 10:01:12.494287 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8828 10:01:12.498041 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8829 10:01:12.500509 == TX Byte 1 ==
8830 10:01:12.504081 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8831 10:01:12.507037 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8832 10:01:12.510648 ==
8833 10:01:12.514082 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 10:01:12.516915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 10:01:12.517377 ==
8836 10:01:12.530700
8837 10:01:12.533526 TX Vref early break, caculate TX vref
8838 10:01:12.536986 TX Vref=16, minBit 9, minWin=22, winSum=381
8839 10:01:12.540212 TX Vref=18, minBit 9, minWin=22, winSum=388
8840 10:01:12.543656 TX Vref=20, minBit 9, minWin=22, winSum=392
8841 10:01:12.546764 TX Vref=22, minBit 9, minWin=23, winSum=402
8842 10:01:12.550296 TX Vref=24, minBit 9, minWin=24, winSum=412
8843 10:01:12.557053 TX Vref=26, minBit 9, minWin=23, winSum=416
8844 10:01:12.560488 TX Vref=28, minBit 9, minWin=24, winSum=421
8845 10:01:12.563550 TX Vref=30, minBit 0, minWin=25, winSum=417
8846 10:01:12.566857 TX Vref=32, minBit 5, minWin=24, winSum=410
8847 10:01:12.570066 TX Vref=34, minBit 0, minWin=23, winSum=401
8848 10:01:12.573566 TX Vref=36, minBit 9, minWin=22, winSum=392
8849 10:01:12.580057 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 30
8850 10:01:12.580577
8851 10:01:12.583556 Final TX Range 0 Vref 30
8852 10:01:12.584144
8853 10:01:12.584517 ==
8854 10:01:12.587052 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 10:01:12.589530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 10:01:12.589994 ==
8857 10:01:12.592831
8858 10:01:12.593290
8859 10:01:12.593652 TX Vref Scan disable
8860 10:01:12.599641 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8861 10:01:12.600086 == TX Byte 0 ==
8862 10:01:12.602704 u2DelayCellOfst[0]=17 cells (5 PI)
8863 10:01:12.606001 u2DelayCellOfst[1]=10 cells (3 PI)
8864 10:01:12.609299 u2DelayCellOfst[2]=0 cells (0 PI)
8865 10:01:12.612890 u2DelayCellOfst[3]=7 cells (2 PI)
8866 10:01:12.616113 u2DelayCellOfst[4]=7 cells (2 PI)
8867 10:01:12.618974 u2DelayCellOfst[5]=17 cells (5 PI)
8868 10:01:12.622736 u2DelayCellOfst[6]=17 cells (5 PI)
8869 10:01:12.625543 u2DelayCellOfst[7]=7 cells (2 PI)
8870 10:01:12.629614 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8871 10:01:12.632719 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8872 10:01:12.635585 == TX Byte 1 ==
8873 10:01:12.638711 u2DelayCellOfst[8]=0 cells (0 PI)
8874 10:01:12.642292 u2DelayCellOfst[9]=3 cells (1 PI)
8875 10:01:12.646026 u2DelayCellOfst[10]=14 cells (4 PI)
8876 10:01:12.648639 u2DelayCellOfst[11]=3 cells (1 PI)
8877 10:01:12.652018 u2DelayCellOfst[12]=14 cells (4 PI)
8878 10:01:12.655757 u2DelayCellOfst[13]=14 cells (4 PI)
8879 10:01:12.658750 u2DelayCellOfst[14]=17 cells (5 PI)
8880 10:01:12.662024 u2DelayCellOfst[15]=17 cells (5 PI)
8881 10:01:12.665395 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8882 10:01:12.668623 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8883 10:01:12.672287 DramC Write-DBI on
8884 10:01:12.672822 ==
8885 10:01:12.675100 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 10:01:12.678728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 10:01:12.679248 ==
8888 10:01:12.679584
8889 10:01:12.680060
8890 10:01:12.682217 TX Vref Scan disable
8891 10:01:12.682736 == TX Byte 0 ==
8892 10:01:12.689123 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8893 10:01:12.689715 == TX Byte 1 ==
8894 10:01:12.694735 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8895 10:01:12.695152 DramC Write-DBI off
8896 10:01:12.695482
8897 10:01:12.695789 [DATLAT]
8898 10:01:12.698344 Freq=1600, CH1 RK1
8899 10:01:12.698870
8900 10:01:12.701289 DATLAT Default: 0xf
8901 10:01:12.701789 0, 0xFFFF, sum = 0
8902 10:01:12.705134 1, 0xFFFF, sum = 0
8903 10:01:12.705755 2, 0xFFFF, sum = 0
8904 10:01:12.708439 3, 0xFFFF, sum = 0
8905 10:01:12.708885 4, 0xFFFF, sum = 0
8906 10:01:12.711416 5, 0xFFFF, sum = 0
8907 10:01:12.711838 6, 0xFFFF, sum = 0
8908 10:01:12.714588 7, 0xFFFF, sum = 0
8909 10:01:12.715009 8, 0xFFFF, sum = 0
8910 10:01:12.717893 9, 0xFFFF, sum = 0
8911 10:01:12.718317 10, 0xFFFF, sum = 0
8912 10:01:12.721410 11, 0xFFFF, sum = 0
8913 10:01:12.721831 12, 0xFFFF, sum = 0
8914 10:01:12.724538 13, 0xFFFF, sum = 0
8915 10:01:12.724960 14, 0x0, sum = 1
8916 10:01:12.728228 15, 0x0, sum = 2
8917 10:01:12.728705 16, 0x0, sum = 3
8918 10:01:12.730738 17, 0x0, sum = 4
8919 10:01:12.731289 best_step = 15
8920 10:01:12.731647
8921 10:01:12.731994 ==
8922 10:01:12.734617 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 10:01:12.740953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 10:01:12.741373 ==
8925 10:01:12.741703 RX Vref Scan: 0
8926 10:01:12.742013
8927 10:01:12.744360 RX Vref 0 -> 0, step: 1
8928 10:01:12.744793
8929 10:01:12.747528 RX Delay 11 -> 252, step: 4
8930 10:01:12.750708 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8931 10:01:12.754297 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8932 10:01:12.760640 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8933 10:01:12.764255 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8934 10:01:12.767014 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8935 10:01:12.770509 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8936 10:01:12.773931 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8937 10:01:12.780722 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8938 10:01:12.784051 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8939 10:01:12.787579 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8940 10:01:12.790898 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
8941 10:01:12.793605 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8942 10:01:12.800228 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8943 10:01:12.803634 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8944 10:01:12.806681 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8945 10:01:12.810343 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8946 10:01:12.810926 ==
8947 10:01:12.813522 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 10:01:12.820076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 10:01:12.820496 ==
8950 10:01:12.820828 DQS Delay:
8951 10:01:12.823666 DQS0 = 0, DQS1 = 0
8952 10:01:12.824212 DQM Delay:
8953 10:01:12.826635 DQM0 = 131, DQM1 = 127
8954 10:01:12.827049 DQ Delay:
8955 10:01:12.829688 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8956 10:01:12.833128 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =130
8957 10:01:12.836455 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8958 10:01:12.839677 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
8959 10:01:12.840207
8960 10:01:12.840541
8961 10:01:12.840851
8962 10:01:12.843355 [DramC_TX_OE_Calibration] TA2
8963 10:01:12.846398 Original DQ_B0 (3 6) =30, OEN = 27
8964 10:01:12.849646 Original DQ_B1 (3 6) =30, OEN = 27
8965 10:01:12.852621 24, 0x0, End_B0=24 End_B1=24
8966 10:01:12.856105 25, 0x0, End_B0=25 End_B1=25
8967 10:01:12.856530 26, 0x0, End_B0=26 End_B1=26
8968 10:01:12.859270 27, 0x0, End_B0=27 End_B1=27
8969 10:01:12.862736 28, 0x0, End_B0=28 End_B1=28
8970 10:01:12.866139 29, 0x0, End_B0=29 End_B1=29
8971 10:01:12.869238 30, 0x0, End_B0=30 End_B1=30
8972 10:01:12.869759 31, 0x5151, End_B0=30 End_B1=30
8973 10:01:12.872661 Byte0 end_step=30 best_step=27
8974 10:01:12.876359 Byte1 end_step=30 best_step=27
8975 10:01:12.879540 Byte0 TX OE(2T, 0.5T) = (3, 3)
8976 10:01:12.882718 Byte1 TX OE(2T, 0.5T) = (3, 3)
8977 10:01:12.883161
8978 10:01:12.883596
8979 10:01:12.889431 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
8980 10:01:12.892544 CH1 RK1: MR19=303, MR18=F1C
8981 10:01:12.899140 CH1_RK1: MR19=0x303, MR18=0xF1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8982 10:01:12.902485 [RxdqsGatingPostProcess] freq 1600
8983 10:01:12.908698 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8984 10:01:12.909131 best DQS0 dly(2T, 0.5T) = (1, 1)
8985 10:01:12.912139 best DQS1 dly(2T, 0.5T) = (1, 1)
8986 10:01:12.915237 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8987 10:01:12.918533 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8988 10:01:12.922352 best DQS0 dly(2T, 0.5T) = (1, 1)
8989 10:01:12.925521 best DQS1 dly(2T, 0.5T) = (1, 1)
8990 10:01:12.929042 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8991 10:01:12.931682 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8992 10:01:12.935303 Pre-setting of DQS Precalculation
8993 10:01:12.938586 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8994 10:01:12.948414 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8995 10:01:12.954709 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8996 10:01:12.955391
8997 10:01:12.955748
8998 10:01:12.958008 [Calibration Summary] 3200 Mbps
8999 10:01:12.958634 CH 0, Rank 0
9000 10:01:12.961311 SW Impedance : PASS
9001 10:01:12.964630 DUTY Scan : NO K
9002 10:01:12.965173 ZQ Calibration : PASS
9003 10:01:12.968514 Jitter Meter : NO K
9004 10:01:12.969031 CBT Training : PASS
9005 10:01:12.971804 Write leveling : PASS
9006 10:01:12.974815 RX DQS gating : PASS
9007 10:01:12.975333 RX DQ/DQS(RDDQC) : PASS
9008 10:01:12.977964 TX DQ/DQS : PASS
9009 10:01:12.981675 RX DATLAT : PASS
9010 10:01:12.982196 RX DQ/DQS(Engine): PASS
9011 10:01:12.984645 TX OE : PASS
9012 10:01:12.985063 All Pass.
9013 10:01:12.985395
9014 10:01:12.988367 CH 0, Rank 1
9015 10:01:12.988839 SW Impedance : PASS
9016 10:01:12.991133 DUTY Scan : NO K
9017 10:01:12.994555 ZQ Calibration : PASS
9018 10:01:12.995118 Jitter Meter : NO K
9019 10:01:12.998364 CBT Training : PASS
9020 10:01:13.000814 Write leveling : PASS
9021 10:01:13.001246 RX DQS gating : PASS
9022 10:01:13.004266 RX DQ/DQS(RDDQC) : PASS
9023 10:01:13.007404 TX DQ/DQS : PASS
9024 10:01:13.007820 RX DATLAT : PASS
9025 10:01:13.010900 RX DQ/DQS(Engine): PASS
9026 10:01:13.014395 TX OE : PASS
9027 10:01:13.014920 All Pass.
9028 10:01:13.015255
9029 10:01:13.015563 CH 1, Rank 0
9030 10:01:13.017602 SW Impedance : PASS
9031 10:01:13.020870 DUTY Scan : NO K
9032 10:01:13.021294 ZQ Calibration : PASS
9033 10:01:13.024355 Jitter Meter : NO K
9034 10:01:13.027662 CBT Training : PASS
9035 10:01:13.028125 Write leveling : PASS
9036 10:01:13.030780 RX DQS gating : PASS
9037 10:01:13.034189 RX DQ/DQS(RDDQC) : PASS
9038 10:01:13.034606 TX DQ/DQS : PASS
9039 10:01:13.038058 RX DATLAT : PASS
9040 10:01:13.038578 RX DQ/DQS(Engine): PASS
9041 10:01:13.041235 TX OE : PASS
9042 10:01:13.041756 All Pass.
9043 10:01:13.042088
9044 10:01:13.044040 CH 1, Rank 1
9045 10:01:13.044457 SW Impedance : PASS
9046 10:01:13.047261 DUTY Scan : NO K
9047 10:01:13.050413 ZQ Calibration : PASS
9048 10:01:13.050832 Jitter Meter : NO K
9049 10:01:13.054142 CBT Training : PASS
9050 10:01:13.057758 Write leveling : PASS
9051 10:01:13.058591 RX DQS gating : PASS
9052 10:01:13.060480 RX DQ/DQS(RDDQC) : PASS
9053 10:01:13.063977 TX DQ/DQS : PASS
9054 10:01:13.064394 RX DATLAT : PASS
9055 10:01:13.066847 RX DQ/DQS(Engine): PASS
9056 10:01:13.070660 TX OE : PASS
9057 10:01:13.071466 All Pass.
9058 10:01:13.072153
9059 10:01:13.073706 DramC Write-DBI on
9060 10:01:13.074147 PER_BANK_REFRESH: Hybrid Mode
9061 10:01:13.076768 TX_TRACKING: ON
9062 10:01:13.087207 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9063 10:01:13.093903 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9064 10:01:13.100431 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9065 10:01:13.103652 [FAST_K] Save calibration result to emmc
9066 10:01:13.106789 sync common calibartion params.
9067 10:01:13.109824 sync cbt_mode0:1, 1:1
9068 10:01:13.110239 dram_init: ddr_geometry: 2
9069 10:01:13.113002 dram_init: ddr_geometry: 2
9070 10:01:13.116573 dram_init: ddr_geometry: 2
9071 10:01:13.119624 0:dram_rank_size:100000000
9072 10:01:13.120084 1:dram_rank_size:100000000
9073 10:01:13.126377 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9074 10:01:13.129661 DFS_SHUFFLE_HW_MODE: ON
9075 10:01:13.132859 dramc_set_vcore_voltage set vcore to 725000
9076 10:01:13.136246 Read voltage for 1600, 0
9077 10:01:13.136660 Vio18 = 0
9078 10:01:13.137142 Vcore = 725000
9079 10:01:13.139095 Vdram = 0
9080 10:01:13.139507 Vddq = 0
9081 10:01:13.139836 Vmddr = 0
9082 10:01:13.142420 switch to 3200 Mbps bootup
9083 10:01:13.142832 [DramcRunTimeConfig]
9084 10:01:13.146322 PHYPLL
9085 10:01:13.146822 DPM_CONTROL_AFTERK: ON
9086 10:01:13.149473 PER_BANK_REFRESH: ON
9087 10:01:13.153142 REFRESH_OVERHEAD_REDUCTION: ON
9088 10:01:13.153653 CMD_PICG_NEW_MODE: OFF
9089 10:01:13.155628 XRTWTW_NEW_MODE: ON
9090 10:01:13.156084 XRTRTR_NEW_MODE: ON
9091 10:01:13.159032 TX_TRACKING: ON
9092 10:01:13.159451 RDSEL_TRACKING: OFF
9093 10:01:13.162483 DQS Precalculation for DVFS: ON
9094 10:01:13.165656 RX_TRACKING: OFF
9095 10:01:13.166071 HW_GATING DBG: ON
9096 10:01:13.169141 ZQCS_ENABLE_LP4: ON
9097 10:01:13.169557 RX_PICG_NEW_MODE: ON
9098 10:01:13.171994 TX_PICG_NEW_MODE: ON
9099 10:01:13.175678 ENABLE_RX_DCM_DPHY: ON
9100 10:01:13.178920 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9101 10:01:13.179341 DUMMY_READ_FOR_TRACKING: OFF
9102 10:01:13.182045 !!! SPM_CONTROL_AFTERK: OFF
9103 10:01:13.185663 !!! SPM could not control APHY
9104 10:01:13.188823 IMPEDANCE_TRACKING: ON
9105 10:01:13.189333 TEMP_SENSOR: ON
9106 10:01:13.191794 HW_SAVE_FOR_SR: OFF
9107 10:01:13.192345 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9108 10:01:13.198558 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9109 10:01:13.199071 Read ODT Tracking: ON
9110 10:01:13.201790 Refresh Rate DeBounce: ON
9111 10:01:13.205220 DFS_NO_QUEUE_FLUSH: ON
9112 10:01:13.205638 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9113 10:01:13.208403 ENABLE_DFS_RUNTIME_MRW: OFF
9114 10:01:13.211887 DDR_RESERVE_NEW_MODE: ON
9115 10:01:13.214837 MR_CBT_SWITCH_FREQ: ON
9116 10:01:13.215372 =========================
9117 10:01:13.234577 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9118 10:01:13.237599 dram_init: ddr_geometry: 2
9119 10:01:13.256726 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9120 10:01:13.259667 dram_init: dram init end (result: 0)
9121 10:01:13.266398 DRAM-K: Full calibration passed in 24419 msecs
9122 10:01:13.269740 MRC: failed to locate region type 0.
9123 10:01:13.270317 DRAM rank0 size:0x100000000,
9124 10:01:13.273140 DRAM rank1 size=0x100000000
9125 10:01:13.282748 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9126 10:01:13.289303 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9127 10:01:13.296054 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9128 10:01:13.305784 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9129 10:01:13.306333 DRAM rank0 size:0x100000000,
9130 10:01:13.309075 DRAM rank1 size=0x100000000
9131 10:01:13.309535 CBMEM:
9132 10:01:13.312561 IMD: root @ 0xfffff000 254 entries.
9133 10:01:13.315784 IMD: root @ 0xffffec00 62 entries.
9134 10:01:13.319068 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9135 10:01:13.325480 WARNING: RO_VPD is uninitialized or empty.
9136 10:01:13.328307 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9137 10:01:13.336582 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9138 10:01:13.348882 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9139 10:01:13.360590 BS: romstage times (exec / console): total (unknown) / 23955 ms
9140 10:01:13.361142
9141 10:01:13.361509
9142 10:01:13.370782 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9143 10:01:13.373654 ARM64: Exception handlers installed.
9144 10:01:13.377230 ARM64: Testing exception
9145 10:01:13.380245 ARM64: Done test exception
9146 10:01:13.380802 Enumerating buses...
9147 10:01:13.383974 Show all devs... Before device enumeration.
9148 10:01:13.386963 Root Device: enabled 1
9149 10:01:13.390179 CPU_CLUSTER: 0: enabled 1
9150 10:01:13.390740 CPU: 00: enabled 1
9151 10:01:13.393666 Compare with tree...
9152 10:01:13.394224 Root Device: enabled 1
9153 10:01:13.396794 CPU_CLUSTER: 0: enabled 1
9154 10:01:13.400016 CPU: 00: enabled 1
9155 10:01:13.400475 Root Device scanning...
9156 10:01:13.403543 scan_static_bus for Root Device
9157 10:01:13.406845 CPU_CLUSTER: 0 enabled
9158 10:01:13.409878 scan_static_bus for Root Device done
9159 10:01:13.413208 scan_bus: bus Root Device finished in 8 msecs
9160 10:01:13.413767 done
9161 10:01:13.419590 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9162 10:01:13.423894 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9163 10:01:13.429665 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9164 10:01:13.433010 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9165 10:01:13.436785 Allocating resources...
9166 10:01:13.440296 Reading resources...
9167 10:01:13.443129 Root Device read_resources bus 0 link: 0
9168 10:01:13.446647 DRAM rank0 size:0x100000000,
9169 10:01:13.447206 DRAM rank1 size=0x100000000
9170 10:01:13.449906 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9171 10:01:13.452791 CPU: 00 missing read_resources
9172 10:01:13.459941 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9173 10:01:13.463200 Root Device read_resources bus 0 link: 0 done
9174 10:01:13.466044 Done reading resources.
9175 10:01:13.469309 Show resources in subtree (Root Device)...After reading.
9176 10:01:13.472490 Root Device child on link 0 CPU_CLUSTER: 0
9177 10:01:13.475967 CPU_CLUSTER: 0 child on link 0 CPU: 00
9178 10:01:13.485962 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9179 10:01:13.486529 CPU: 00
9180 10:01:13.492416 Root Device assign_resources, bus 0 link: 0
9181 10:01:13.496225 CPU_CLUSTER: 0 missing set_resources
9182 10:01:13.499176 Root Device assign_resources, bus 0 link: 0 done
9183 10:01:13.499741 Done setting resources.
9184 10:01:13.505352 Show resources in subtree (Root Device)...After assigning values.
9185 10:01:13.508457 Root Device child on link 0 CPU_CLUSTER: 0
9186 10:01:13.515387 CPU_CLUSTER: 0 child on link 0 CPU: 00
9187 10:01:13.521971 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9188 10:01:13.525009 CPU: 00
9189 10:01:13.525565 Done allocating resources.
9190 10:01:13.531662 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9191 10:01:13.532182 Enabling resources...
9192 10:01:13.535310 done.
9193 10:01:13.538547 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9194 10:01:13.541675 Initializing devices...
9195 10:01:13.542230 Root Device init
9196 10:01:13.544967 init hardware done!
9197 10:01:13.545521 0x00000018: ctrlr->caps
9198 10:01:13.548357 52.000 MHz: ctrlr->f_max
9199 10:01:13.551762 0.400 MHz: ctrlr->f_min
9200 10:01:13.554933 0x40ff8080: ctrlr->voltages
9201 10:01:13.555497 sclk: 390625
9202 10:01:13.555868 Bus Width = 1
9203 10:01:13.558312 sclk: 390625
9204 10:01:13.558864 Bus Width = 1
9205 10:01:13.561228 Early init status = 3
9206 10:01:13.564815 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9207 10:01:13.568192 in-header: 03 fc 00 00 01 00 00 00
9208 10:01:13.571584 in-data: 00
9209 10:01:13.574507 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9210 10:01:13.579600 in-header: 03 fd 00 00 00 00 00 00
9211 10:01:13.582991 in-data:
9212 10:01:13.586191 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9213 10:01:13.589362 in-header: 03 fc 00 00 01 00 00 00
9214 10:01:13.592685 in-data: 00
9215 10:01:13.595995 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9216 10:01:13.600642 in-header: 03 fd 00 00 00 00 00 00
9217 10:01:13.603589 in-data:
9218 10:01:13.607281 [SSUSB] Setting up USB HOST controller...
9219 10:01:13.610319 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9220 10:01:13.613540 [SSUSB] phy power-on done.
9221 10:01:13.616996 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9222 10:01:13.623403 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9223 10:01:13.627141 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9224 10:01:13.633374 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9225 10:01:13.639888 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9226 10:01:13.646806 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9227 10:01:13.653908 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9228 10:01:13.660157 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9229 10:01:13.663346 SPM: binary array size = 0x9dc
9230 10:01:13.666821 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9231 10:01:13.673436 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9232 10:01:13.680090 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9233 10:01:13.686219 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9234 10:01:13.689871 configure_display: Starting display init
9235 10:01:13.723783 anx7625_power_on_init: Init interface.
9236 10:01:13.726997 anx7625_disable_pd_protocol: Disabled PD feature.
9237 10:01:13.730524 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9238 10:01:13.757995 anx7625_start_dp_work: Secure OCM version=00
9239 10:01:13.761268 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9240 10:01:13.776439 sp_tx_get_edid_block: EDID Block = 1
9241 10:01:13.879228 Extracted contents:
9242 10:01:13.882157 header: 00 ff ff ff ff ff ff 00
9243 10:01:13.885669 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9244 10:01:13.888780 version: 01 04
9245 10:01:13.892286 basic params: 95 1f 11 78 0a
9246 10:01:13.895610 chroma info: 76 90 94 55 54 90 27 21 50 54
9247 10:01:13.898601 established: 00 00 00
9248 10:01:13.905076 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9249 10:01:13.911577 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9250 10:01:13.915168 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9251 10:01:13.921385 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9252 10:01:13.928446 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9253 10:01:13.931096 extensions: 00
9254 10:01:13.931559 checksum: fb
9255 10:01:13.931986
9256 10:01:13.937936 Manufacturer: IVO Model 57d Serial Number 0
9257 10:01:13.938489 Made week 0 of 2020
9258 10:01:13.941203 EDID version: 1.4
9259 10:01:13.941667 Digital display
9260 10:01:13.944266 6 bits per primary color channel
9261 10:01:13.948033 DisplayPort interface
9262 10:01:13.948584 Maximum image size: 31 cm x 17 cm
9263 10:01:13.951444 Gamma: 220%
9264 10:01:13.952058 Check DPMS levels
9265 10:01:13.957873 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9266 10:01:13.961222 First detailed timing is preferred timing
9267 10:01:13.961778 Established timings supported:
9268 10:01:13.964853 Standard timings supported:
9269 10:01:13.967949 Detailed timings
9270 10:01:13.971447 Hex of detail: 383680a07038204018303c0035ae10000019
9271 10:01:13.977907 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9272 10:01:13.981026 0780 0798 07c8 0820 hborder 0
9273 10:01:13.984114 0438 043b 0447 0458 vborder 0
9274 10:01:13.987639 -hsync -vsync
9275 10:01:13.988239 Did detailed timing
9276 10:01:13.994135 Hex of detail: 000000000000000000000000000000000000
9277 10:01:13.997792 Manufacturer-specified data, tag 0
9278 10:01:14.000848 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9279 10:01:14.004214 ASCII string: InfoVision
9280 10:01:14.007574 Hex of detail: 000000fe00523134304e574635205248200a
9281 10:01:14.010554 ASCII string: R140NWF5 RH
9282 10:01:14.011043 Checksum
9283 10:01:14.013983 Checksum: 0xfb (valid)
9284 10:01:14.017261 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9285 10:01:14.020540 DSI data_rate: 832800000 bps
9286 10:01:14.027269 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9287 10:01:14.030482 anx7625_parse_edid: pixelclock(138800).
9288 10:01:14.033433 hactive(1920), hsync(48), hfp(24), hbp(88)
9289 10:01:14.037166 vactive(1080), vsync(12), vfp(3), vbp(17)
9290 10:01:14.040227 anx7625_dsi_config: config dsi.
9291 10:01:14.046583 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9292 10:01:14.060868 anx7625_dsi_config: success to config DSI
9293 10:01:14.063870 anx7625_dp_start: MIPI phy setup OK.
9294 10:01:14.067643 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9295 10:01:14.070390 mtk_ddp_mode_set invalid vrefresh 60
9296 10:01:14.073922 main_disp_path_setup
9297 10:01:14.074412 ovl_layer_smi_id_en
9298 10:01:14.077470 ovl_layer_smi_id_en
9299 10:01:14.077890 ccorr_config
9300 10:01:14.078225 aal_config
9301 10:01:14.080465 gamma_config
9302 10:01:14.080878 postmask_config
9303 10:01:14.083842 dither_config
9304 10:01:14.087068 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9305 10:01:14.093890 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9306 10:01:14.097035 Root Device init finished in 551 msecs
9307 10:01:14.100616 CPU_CLUSTER: 0 init
9308 10:01:14.107052 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9309 10:01:14.113606 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9310 10:01:14.114319 APU_MBOX 0x190000b0 = 0x10001
9311 10:01:14.116695 APU_MBOX 0x190001b0 = 0x10001
9312 10:01:14.120058 APU_MBOX 0x190005b0 = 0x10001
9313 10:01:14.123316 APU_MBOX 0x190006b0 = 0x10001
9314 10:01:14.130018 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9315 10:01:14.140061 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9316 10:01:14.152167 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9317 10:01:14.158791 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9318 10:01:14.170395 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9319 10:01:14.179737 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9320 10:01:14.182898 CPU_CLUSTER: 0 init finished in 81 msecs
9321 10:01:14.186347 Devices initialized
9322 10:01:14.189669 Show all devs... After init.
9323 10:01:14.190186 Root Device: enabled 1
9324 10:01:14.192985 CPU_CLUSTER: 0: enabled 1
9325 10:01:14.195755 CPU: 00: enabled 1
9326 10:01:14.199348 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9327 10:01:14.203099 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9328 10:01:14.205537 ELOG: NV offset 0x57f000 size 0x1000
9329 10:01:14.212392 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9330 10:01:14.219544 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9331 10:01:14.223179 ELOG: Event(17) added with size 13 at 2023-08-23 10:01:15 UTC
9332 10:01:14.229240 out: cmd=0x121: 03 db 21 01 00 00 00 00
9333 10:01:14.232462 in-header: 03 37 00 00 2c 00 00 00
9334 10:01:14.242589 in-data: 28 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9335 10:01:14.248700 ELOG: Event(A1) added with size 10 at 2023-08-23 10:01:15 UTC
9336 10:01:14.255239 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9337 10:01:14.261823 ELOG: Event(A0) added with size 9 at 2023-08-23 10:01:15 UTC
9338 10:01:14.265599 elog_add_boot_reason: Logged dev mode boot
9339 10:01:14.272149 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9340 10:01:14.272710 Finalize devices...
9341 10:01:14.275279 Devices finalized
9342 10:01:14.278878 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9343 10:01:14.282210 Writing coreboot table at 0xffe64000
9344 10:01:14.285275 0. 000000000010a000-0000000000113fff: RAMSTAGE
9345 10:01:14.291863 1. 0000000040000000-00000000400fffff: RAM
9346 10:01:14.295334 2. 0000000040100000-000000004032afff: RAMSTAGE
9347 10:01:14.298437 3. 000000004032b000-00000000545fffff: RAM
9348 10:01:14.301939 4. 0000000054600000-000000005465ffff: BL31
9349 10:01:14.305052 5. 0000000054660000-00000000ffe63fff: RAM
9350 10:01:14.311404 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9351 10:01:14.314942 7. 0000000100000000-000000023fffffff: RAM
9352 10:01:14.318652 Passing 5 GPIOs to payload:
9353 10:01:14.321405 NAME | PORT | POLARITY | VALUE
9354 10:01:14.327940 EC in RW | 0x000000aa | low | undefined
9355 10:01:14.331161 EC interrupt | 0x00000005 | low | undefined
9356 10:01:14.337963 TPM interrupt | 0x000000ab | high | undefined
9357 10:01:14.341040 SD card detect | 0x00000011 | high | undefined
9358 10:01:14.344602 speaker enable | 0x00000093 | high | undefined
9359 10:01:14.347638 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9360 10:01:14.351402 in-header: 03 f9 00 00 02 00 00 00
9361 10:01:14.355106 in-data: 02 00
9362 10:01:14.358462 ADC[4]: Raw value=903325 ID=7
9363 10:01:14.361842 ADC[3]: Raw value=213916 ID=1
9364 10:01:14.362460 RAM Code: 0x71
9365 10:01:14.364755 ADC[6]: Raw value=75000 ID=0
9366 10:01:14.368365 ADC[5]: Raw value=213546 ID=1
9367 10:01:14.368772 SKU Code: 0x1
9368 10:01:14.375014 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 955a
9369 10:01:14.375533 coreboot table: 964 bytes.
9370 10:01:14.377952 IMD ROOT 0. 0xfffff000 0x00001000
9371 10:01:14.381477 IMD SMALL 1. 0xffffe000 0x00001000
9372 10:01:14.384292 RO MCACHE 2. 0xffffc000 0x00001104
9373 10:01:14.388437 CONSOLE 3. 0xfff7c000 0x00080000
9374 10:01:14.391087 FMAP 4. 0xfff7b000 0x00000452
9375 10:01:14.394679 TIME STAMP 5. 0xfff7a000 0x00000910
9376 10:01:14.397639 VBOOT WORK 6. 0xfff66000 0x00014000
9377 10:01:14.400504 RAMOOPS 7. 0xffe66000 0x00100000
9378 10:01:14.404224 COREBOOT 8. 0xffe64000 0x00002000
9379 10:01:14.407354 IMD small region:
9380 10:01:14.410565 IMD ROOT 0. 0xffffec00 0x00000400
9381 10:01:14.413862 VPD 1. 0xffffeb80 0x0000006c
9382 10:01:14.417080 MMC STATUS 2. 0xffffeb60 0x00000004
9383 10:01:14.423754 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9384 10:01:14.424398 Probing TPM: done!
9385 10:01:14.430956 Connected to device vid:did:rid of 1ae0:0028:00
9386 10:01:14.437519 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9387 10:01:14.440480 Initialized TPM device CR50 revision 0
9388 10:01:14.444105 Checking cr50 for pending updates
9389 10:01:14.449884 Reading cr50 TPM mode
9390 10:01:14.458575 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9391 10:01:14.465011 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9392 10:01:14.505042 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9393 10:01:14.508362 Checking segment from ROM address 0x40100000
9394 10:01:14.511743 Checking segment from ROM address 0x4010001c
9395 10:01:14.518578 Loading segment from ROM address 0x40100000
9396 10:01:14.519119 code (compression=0)
9397 10:01:14.528199 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9398 10:01:14.535031 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9399 10:01:14.535456 it's not compressed!
9400 10:01:14.541990 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9401 10:01:14.548089 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9402 10:01:14.565979 Loading segment from ROM address 0x4010001c
9403 10:01:14.566563 Entry Point 0x80000000
9404 10:01:14.568866 Loaded segments
9405 10:01:14.572262 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9406 10:01:14.578979 Jumping to boot code at 0x80000000(0xffe64000)
9407 10:01:14.585481 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9408 10:01:14.592047 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9409 10:01:14.600644 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9410 10:01:14.603240 Checking segment from ROM address 0x40100000
9411 10:01:14.607305 Checking segment from ROM address 0x4010001c
9412 10:01:14.613005 Loading segment from ROM address 0x40100000
9413 10:01:14.613466 code (compression=1)
9414 10:01:14.620367 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9415 10:01:14.629634 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9416 10:01:14.630080 using LZMA
9417 10:01:14.638450 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9418 10:01:14.645068 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9419 10:01:14.648021 Loading segment from ROM address 0x4010001c
9420 10:01:14.648546 Entry Point 0x54601000
9421 10:01:14.651715 Loaded segments
9422 10:01:14.654716 NOTICE: MT8192 bl31_setup
9423 10:01:14.661859 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9424 10:01:14.665899 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9425 10:01:14.668535 WARNING: region 0:
9426 10:01:14.671730 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9427 10:01:14.672199 WARNING: region 1:
9428 10:01:14.678993 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9429 10:01:14.682055 WARNING: region 2:
9430 10:01:14.685832 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9431 10:01:14.689073 WARNING: region 3:
9432 10:01:14.692506 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9433 10:01:14.695817 WARNING: region 4:
9434 10:01:14.698540 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9435 10:01:14.702667 WARNING: region 5:
9436 10:01:14.705216 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 10:01:14.709327 WARNING: region 6:
9438 10:01:14.712452 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 10:01:14.712892 WARNING: region 7:
9440 10:01:14.719266 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 10:01:14.725194 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9442 10:01:14.728490 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9443 10:01:14.732529 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9444 10:01:14.738808 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9445 10:01:14.742197 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9446 10:01:14.745674 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9447 10:01:14.751986 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9448 10:01:14.755095 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9449 10:01:14.762324 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9450 10:01:14.766058 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9451 10:01:14.768992 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9452 10:01:14.775160 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9453 10:01:14.778615 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9454 10:01:14.781979 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9455 10:01:14.788485 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9456 10:01:14.791995 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9457 10:01:14.798341 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9458 10:01:14.801640 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9459 10:01:14.804987 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9460 10:01:14.812039 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9461 10:01:14.815011 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9462 10:01:14.818385 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9463 10:01:14.824924 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9464 10:01:14.828903 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9465 10:01:14.834945 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9466 10:01:14.838233 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9467 10:01:14.841621 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9468 10:01:14.848632 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9469 10:01:14.852066 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9470 10:01:14.858761 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9471 10:01:14.861613 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9472 10:01:14.864926 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9473 10:01:14.871599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9474 10:01:14.875141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9475 10:01:14.878254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9476 10:01:14.881483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9477 10:01:14.888557 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9478 10:01:14.891748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9479 10:01:14.894920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9480 10:01:14.898079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9481 10:01:14.904790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9482 10:01:14.908229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9483 10:01:14.911556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9484 10:01:14.914846 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9485 10:01:14.920979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9486 10:01:14.924287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9487 10:01:14.927716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9488 10:01:14.934349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9489 10:01:14.937717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9490 10:01:14.940843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9491 10:01:14.947881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9492 10:01:14.951105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9493 10:01:14.957525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9494 10:01:14.961055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9495 10:01:14.967626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9496 10:01:14.971120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9497 10:01:14.974062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9498 10:01:14.982014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9499 10:01:14.984198 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9500 10:01:14.990701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9501 10:01:14.994282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9502 10:01:15.000590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9503 10:01:15.004472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9504 10:01:15.010795 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9505 10:01:15.014287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9506 10:01:15.017973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9507 10:01:15.024195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9508 10:01:15.028094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9509 10:01:15.034069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9510 10:01:15.037474 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9511 10:01:15.044042 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9512 10:01:15.047788 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9513 10:01:15.051241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9514 10:01:15.057620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9515 10:01:15.060646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9516 10:01:15.067323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9517 10:01:15.070629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9518 10:01:15.077852 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9519 10:01:15.080643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9520 10:01:15.084122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9521 10:01:15.091346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9522 10:01:15.094114 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9523 10:01:15.100482 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9524 10:01:15.104074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9525 10:01:15.110363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9526 10:01:15.113963 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9527 10:01:15.120953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9528 10:01:15.123624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9529 10:01:15.127053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9530 10:01:15.133963 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9531 10:01:15.137212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9532 10:01:15.143899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9533 10:01:15.146926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9534 10:01:15.153674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9535 10:01:15.156745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9536 10:01:15.163673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9537 10:01:15.167062 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9538 10:01:15.169942 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9539 10:01:15.173374 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9540 10:01:15.180214 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9541 10:01:15.183024 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9542 10:01:15.186863 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9543 10:01:15.193589 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9544 10:01:15.196914 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9545 10:01:15.199788 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9546 10:01:15.206424 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9547 10:01:15.209914 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9548 10:01:15.216429 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9549 10:01:15.219514 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9550 10:01:15.226499 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9551 10:01:15.229649 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9552 10:01:15.233385 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9553 10:01:15.239606 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9554 10:01:15.243297 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9555 10:01:15.249553 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9556 10:01:15.252958 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9557 10:01:15.256318 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9558 10:01:15.259769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9559 10:01:15.266524 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9560 10:01:15.269734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9561 10:01:15.273138 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9562 10:01:15.276329 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9563 10:01:15.283278 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9564 10:01:15.286370 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9565 10:01:15.289535 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9566 10:01:15.295974 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9567 10:01:15.299500 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9568 10:01:15.306297 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9569 10:01:15.309848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9570 10:01:15.312550 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9571 10:01:15.319312 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9572 10:01:15.322607 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9573 10:01:15.329151 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9574 10:01:15.332622 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9575 10:01:15.336031 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9576 10:01:15.342621 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9577 10:01:15.346066 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9578 10:01:15.349021 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9579 10:01:15.356110 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9580 10:01:15.359722 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9581 10:01:15.365910 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9582 10:01:15.369344 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9583 10:01:15.376124 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9584 10:01:15.379457 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9585 10:01:15.382583 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9586 10:01:15.389278 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9587 10:01:15.392231 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9588 10:01:15.396140 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9589 10:01:15.402632 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9590 10:01:15.405633 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9591 10:01:15.412557 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9592 10:01:15.415548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9593 10:01:15.418990 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9594 10:01:15.425200 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9595 10:01:15.428665 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9596 10:01:15.435416 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9597 10:01:15.438996 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9598 10:01:15.442431 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9599 10:01:15.448544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9600 10:01:15.452240 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9601 10:01:15.458827 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9602 10:01:15.461867 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9603 10:01:15.465621 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9604 10:01:15.472073 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9605 10:01:15.475083 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9606 10:01:15.482375 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9607 10:01:15.485102 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9608 10:01:15.488585 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9609 10:01:15.494978 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9610 10:01:15.498092 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9611 10:01:15.505103 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9612 10:01:15.508080 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9613 10:01:15.511513 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9614 10:01:15.518089 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9615 10:01:15.521580 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9616 10:01:15.527601 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9617 10:01:15.531156 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9618 10:01:15.534384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9619 10:01:15.541292 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9620 10:01:15.544167 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9621 10:01:15.550565 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9622 10:01:15.554021 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9623 10:01:15.557300 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9624 10:01:15.564249 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9625 10:01:15.566961 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9626 10:01:15.573787 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9627 10:01:15.577372 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9628 10:01:15.580717 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9629 10:01:15.587303 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9630 10:01:15.590706 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9631 10:01:15.597248 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9632 10:01:15.600859 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9633 10:01:15.606964 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9634 10:01:15.610219 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9635 10:01:15.613694 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9636 10:01:15.620331 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9637 10:01:15.623394 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9638 10:01:15.630394 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9639 10:01:15.633630 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9640 10:01:15.639704 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9641 10:01:15.643004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9642 10:01:15.647039 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9643 10:01:15.653215 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9644 10:01:15.656543 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9645 10:01:15.663193 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9646 10:01:15.666379 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9647 10:01:15.669747 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9648 10:01:15.676541 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9649 10:01:15.679729 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9650 10:01:15.687056 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9651 10:01:15.689760 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9652 10:01:15.696637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9653 10:01:15.699819 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9654 10:01:15.702779 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9655 10:01:15.709063 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9656 10:01:15.712496 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9657 10:01:15.719087 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9658 10:01:15.723161 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9659 10:01:15.728643 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9660 10:01:15.732327 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9661 10:01:15.735372 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9662 10:01:15.741989 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9663 10:01:15.745693 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9664 10:01:15.752189 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9665 10:01:15.755497 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9666 10:01:15.762329 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9667 10:01:15.765454 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9668 10:01:15.768835 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9669 10:01:15.775154 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9670 10:01:15.778491 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9671 10:01:15.781770 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9672 10:01:15.785667 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9673 10:01:15.791807 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9674 10:01:15.795185 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9675 10:01:15.797912 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9676 10:01:15.805075 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9677 10:01:15.808283 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9678 10:01:15.814570 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9679 10:01:15.817904 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9680 10:01:15.821230 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9681 10:01:15.827834 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9682 10:01:15.831344 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9683 10:01:15.834256 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9684 10:01:15.840930 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9685 10:01:15.844107 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9686 10:01:15.851168 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9687 10:01:15.854578 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9688 10:01:15.857688 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9689 10:01:15.864361 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9690 10:01:15.867883 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9691 10:01:15.870969 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9692 10:01:15.877458 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9693 10:01:15.880441 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9694 10:01:15.883643 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9695 10:01:15.890549 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9696 10:01:15.893758 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9697 10:01:15.900653 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9698 10:01:15.903696 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9699 10:01:15.906990 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9700 10:01:15.914201 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9701 10:01:15.916977 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9702 10:01:15.923722 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9703 10:01:15.927052 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9704 10:01:15.930773 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9705 10:01:15.936783 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9706 10:01:15.940124 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9707 10:01:15.943438 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9708 10:01:15.950034 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9709 10:01:15.953303 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9710 10:01:15.956545 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9711 10:01:15.963204 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9712 10:01:15.966742 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9713 10:01:15.969621 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9714 10:01:15.973295 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9715 10:01:15.976544 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9716 10:01:15.983262 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9717 10:01:15.986529 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9718 10:01:15.989395 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9719 10:01:15.992629 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9720 10:01:15.999745 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9721 10:01:16.003052 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9722 10:01:16.006368 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9723 10:01:16.012506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9724 10:01:16.015433 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9725 10:01:16.022607 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9726 10:01:16.025711 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9727 10:01:16.032122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9728 10:01:16.035346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9729 10:01:16.038945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9730 10:01:16.045514 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9731 10:01:16.048765 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9732 10:01:16.055393 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9733 10:01:16.058860 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9734 10:01:16.062098 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9735 10:01:16.068515 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9736 10:01:16.072011 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9737 10:01:16.079119 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9738 10:01:16.082418 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9739 10:01:16.085008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9740 10:01:16.092068 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9741 10:01:16.095468 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9742 10:01:16.101680 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9743 10:01:16.105193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9744 10:01:16.111990 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9745 10:01:16.114552 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9746 10:01:16.117731 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9747 10:01:16.124822 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9748 10:01:16.127875 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9749 10:01:16.134428 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9750 10:01:16.138054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9751 10:01:16.144819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9752 10:01:16.148002 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9753 10:01:16.151680 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9754 10:01:16.157973 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9755 10:01:16.160806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9756 10:01:16.167427 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9757 10:01:16.170946 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9758 10:01:16.177637 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9759 10:01:16.180826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9760 10:01:16.183962 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9761 10:01:16.191044 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9762 10:01:16.194010 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9763 10:01:16.201232 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9764 10:01:16.203572 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9765 10:01:16.207129 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9766 10:01:16.214182 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9767 10:01:16.217538 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9768 10:01:16.224086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9769 10:01:16.226974 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9770 10:01:16.230523 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9771 10:01:16.237056 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9772 10:01:16.240456 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9773 10:01:16.247036 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9774 10:01:16.250671 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9775 10:01:16.257151 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9776 10:01:16.260610 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9777 10:01:16.264012 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9778 10:01:16.270065 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9779 10:01:16.273448 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9780 10:01:16.280308 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9781 10:01:16.283512 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9782 10:01:16.286527 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9783 10:01:16.293100 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9784 10:01:16.297069 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9785 10:01:16.303010 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9786 10:01:16.306326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9787 10:01:16.309325 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9788 10:01:16.315813 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9789 10:01:16.319288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9790 10:01:16.325844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9791 10:01:16.329452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9792 10:01:16.336144 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9793 10:01:16.339344 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9794 10:01:16.342564 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9795 10:01:16.349344 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9796 10:01:16.352692 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9797 10:01:16.359622 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9798 10:01:16.362407 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9799 10:01:16.368953 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9800 10:01:16.372514 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9801 10:01:16.379088 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9802 10:01:16.382136 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9803 10:01:16.385694 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9804 10:01:16.392641 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9805 10:01:16.395399 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9806 10:01:16.402444 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9807 10:01:16.405496 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9808 10:01:16.411749 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9809 10:01:16.414831 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9810 10:01:16.418323 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9811 10:01:16.425501 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9812 10:01:16.428741 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9813 10:01:16.435033 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9814 10:01:16.438263 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9815 10:01:16.444820 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9816 10:01:16.448072 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9817 10:01:16.454747 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9818 10:01:16.458015 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9819 10:01:16.461497 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9820 10:01:16.468513 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9821 10:01:16.471373 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9822 10:01:16.478011 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9823 10:01:16.480627 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9824 10:01:16.487726 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9825 10:01:16.491526 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9826 10:01:16.497539 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9827 10:01:16.501259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9828 10:01:16.504063 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9829 10:01:16.510635 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9830 10:01:16.513994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9831 10:01:16.520890 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9832 10:01:16.524188 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9833 10:01:16.531057 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9834 10:01:16.533824 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9835 10:01:16.540436 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9836 10:01:16.544102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9837 10:01:16.550860 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9838 10:01:16.553627 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9839 10:01:16.556597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9840 10:01:16.563189 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9841 10:01:16.566560 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9842 10:01:16.573506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9843 10:01:16.576924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9844 10:01:16.583768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9845 10:01:16.586583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9846 10:01:16.589729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9847 10:01:16.596672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9848 10:01:16.599541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9849 10:01:16.606349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9850 10:01:16.609413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9851 10:01:16.616150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9852 10:01:16.619687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9853 10:01:16.625943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9854 10:01:16.629327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9855 10:01:16.635807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9856 10:01:16.639219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9857 10:01:16.645812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9858 10:01:16.648810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9859 10:01:16.655889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9860 10:01:16.659154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9861 10:01:16.665494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9862 10:01:16.669155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9863 10:01:16.675332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9864 10:01:16.678965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9865 10:01:16.685374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9866 10:01:16.688562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9867 10:01:16.694771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9868 10:01:16.698537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9869 10:01:16.704938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9870 10:01:16.708626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9871 10:01:16.714545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9872 10:01:16.721251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9873 10:01:16.724972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9874 10:01:16.731345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9875 10:01:16.734565 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9876 10:01:16.735026 INFO: [APUAPC] vio 0
9877 10:01:16.742325 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9878 10:01:16.745198 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9879 10:01:16.748487 INFO: [APUAPC] D0_APC_0: 0x400510
9880 10:01:16.752151 INFO: [APUAPC] D0_APC_1: 0x0
9881 10:01:16.755727 INFO: [APUAPC] D0_APC_2: 0x1540
9882 10:01:16.758935 INFO: [APUAPC] D0_APC_3: 0x0
9883 10:01:16.762193 INFO: [APUAPC] D1_APC_0: 0xffffffff
9884 10:01:16.764989 INFO: [APUAPC] D1_APC_1: 0xffffffff
9885 10:01:16.768016 INFO: [APUAPC] D1_APC_2: 0x3fffff
9886 10:01:16.771733 INFO: [APUAPC] D1_APC_3: 0x0
9887 10:01:16.774875 INFO: [APUAPC] D2_APC_0: 0xffffffff
9888 10:01:16.778615 INFO: [APUAPC] D2_APC_1: 0xffffffff
9889 10:01:16.782279 INFO: [APUAPC] D2_APC_2: 0x3fffff
9890 10:01:16.785212 INFO: [APUAPC] D2_APC_3: 0x0
9891 10:01:16.788636 INFO: [APUAPC] D3_APC_0: 0xffffffff
9892 10:01:16.791659 INFO: [APUAPC] D3_APC_1: 0xffffffff
9893 10:01:16.795013 INFO: [APUAPC] D3_APC_2: 0x3fffff
9894 10:01:16.798394 INFO: [APUAPC] D3_APC_3: 0x0
9895 10:01:16.801839 INFO: [APUAPC] D4_APC_0: 0xffffffff
9896 10:01:16.804899 INFO: [APUAPC] D4_APC_1: 0xffffffff
9897 10:01:16.808321 INFO: [APUAPC] D4_APC_2: 0x3fffff
9898 10:01:16.811948 INFO: [APUAPC] D4_APC_3: 0x0
9899 10:01:16.814366 INFO: [APUAPC] D5_APC_0: 0xffffffff
9900 10:01:16.817606 INFO: [APUAPC] D5_APC_1: 0xffffffff
9901 10:01:16.820882 INFO: [APUAPC] D5_APC_2: 0x3fffff
9902 10:01:16.824583 INFO: [APUAPC] D5_APC_3: 0x0
9903 10:01:16.827673 INFO: [APUAPC] D6_APC_0: 0xffffffff
9904 10:01:16.830778 INFO: [APUAPC] D6_APC_1: 0xffffffff
9905 10:01:16.834127 INFO: [APUAPC] D6_APC_2: 0x3fffff
9906 10:01:16.834667 INFO: [APUAPC] D6_APC_3: 0x0
9907 10:01:16.840477 INFO: [APUAPC] D7_APC_0: 0xffffffff
9908 10:01:16.844356 INFO: [APUAPC] D7_APC_1: 0xffffffff
9909 10:01:16.847494 INFO: [APUAPC] D7_APC_2: 0x3fffff
9910 10:01:16.848103 INFO: [APUAPC] D7_APC_3: 0x0
9911 10:01:16.853871 INFO: [APUAPC] D8_APC_0: 0xffffffff
9912 10:01:16.856840 INFO: [APUAPC] D8_APC_1: 0xffffffff
9913 10:01:16.860532 INFO: [APUAPC] D8_APC_2: 0x3fffff
9914 10:01:16.861090 INFO: [APUAPC] D8_APC_3: 0x0
9915 10:01:16.863787 INFO: [APUAPC] D9_APC_0: 0xffffffff
9916 10:01:16.870791 INFO: [APUAPC] D9_APC_1: 0xffffffff
9917 10:01:16.871349 INFO: [APUAPC] D9_APC_2: 0x3fffff
9918 10:01:16.873699 INFO: [APUAPC] D9_APC_3: 0x0
9919 10:01:16.877278 INFO: [APUAPC] D10_APC_0: 0xffffffff
9920 10:01:16.884082 INFO: [APUAPC] D10_APC_1: 0xffffffff
9921 10:01:16.886826 INFO: [APUAPC] D10_APC_2: 0x3fffff
9922 10:01:16.887379 INFO: [APUAPC] D10_APC_3: 0x0
9923 10:01:16.890402 INFO: [APUAPC] D11_APC_0: 0xffffffff
9924 10:01:16.896499 INFO: [APUAPC] D11_APC_1: 0xffffffff
9925 10:01:16.900462 INFO: [APUAPC] D11_APC_2: 0x3fffff
9926 10:01:16.901021 INFO: [APUAPC] D11_APC_3: 0x0
9927 10:01:16.906488 INFO: [APUAPC] D12_APC_0: 0xffffffff
9928 10:01:16.909967 INFO: [APUAPC] D12_APC_1: 0xffffffff
9929 10:01:16.913867 INFO: [APUAPC] D12_APC_2: 0x3fffff
9930 10:01:16.916302 INFO: [APUAPC] D12_APC_3: 0x0
9931 10:01:16.920025 INFO: [APUAPC] D13_APC_0: 0xffffffff
9932 10:01:16.923038 INFO: [APUAPC] D13_APC_1: 0xffffffff
9933 10:01:16.926566 INFO: [APUAPC] D13_APC_2: 0x3fffff
9934 10:01:16.929338 INFO: [APUAPC] D13_APC_3: 0x0
9935 10:01:16.933244 INFO: [APUAPC] D14_APC_0: 0xffffffff
9936 10:01:16.936427 INFO: [APUAPC] D14_APC_1: 0xffffffff
9937 10:01:16.939542 INFO: [APUAPC] D14_APC_2: 0x3fffff
9938 10:01:16.942843 INFO: [APUAPC] D14_APC_3: 0x0
9939 10:01:16.946514 INFO: [APUAPC] D15_APC_0: 0xffffffff
9940 10:01:16.949635 INFO: [APUAPC] D15_APC_1: 0xffffffff
9941 10:01:16.952844 INFO: [APUAPC] D15_APC_2: 0x3fffff
9942 10:01:16.956506 INFO: [APUAPC] D15_APC_3: 0x0
9943 10:01:16.959225 INFO: [APUAPC] APC_CON: 0x4
9944 10:01:16.959781 INFO: [NOCDAPC] D0_APC_0: 0x0
9945 10:01:16.962611 INFO: [NOCDAPC] D0_APC_1: 0x0
9946 10:01:16.965779 INFO: [NOCDAPC] D1_APC_0: 0x0
9947 10:01:16.969194 INFO: [NOCDAPC] D1_APC_1: 0xfff
9948 10:01:16.972527 INFO: [NOCDAPC] D2_APC_0: 0x0
9949 10:01:16.975873 INFO: [NOCDAPC] D2_APC_1: 0xfff
9950 10:01:16.979262 INFO: [NOCDAPC] D3_APC_0: 0x0
9951 10:01:16.982386 INFO: [NOCDAPC] D3_APC_1: 0xfff
9952 10:01:16.985542 INFO: [NOCDAPC] D4_APC_0: 0x0
9953 10:01:16.989233 INFO: [NOCDAPC] D4_APC_1: 0xfff
9954 10:01:16.992305 INFO: [NOCDAPC] D5_APC_0: 0x0
9955 10:01:16.992861 INFO: [NOCDAPC] D5_APC_1: 0xfff
9956 10:01:16.995694 INFO: [NOCDAPC] D6_APC_0: 0x0
9957 10:01:16.999026 INFO: [NOCDAPC] D6_APC_1: 0xfff
9958 10:01:17.002833 INFO: [NOCDAPC] D7_APC_0: 0x0
9959 10:01:17.005845 INFO: [NOCDAPC] D7_APC_1: 0xfff
9960 10:01:17.008385 INFO: [NOCDAPC] D8_APC_0: 0x0
9961 10:01:17.012178 INFO: [NOCDAPC] D8_APC_1: 0xfff
9962 10:01:17.015449 INFO: [NOCDAPC] D9_APC_0: 0x0
9963 10:01:17.018663 INFO: [NOCDAPC] D9_APC_1: 0xfff
9964 10:01:17.022067 INFO: [NOCDAPC] D10_APC_0: 0x0
9965 10:01:17.025195 INFO: [NOCDAPC] D10_APC_1: 0xfff
9966 10:01:17.028599 INFO: [NOCDAPC] D11_APC_0: 0x0
9967 10:01:17.031673 INFO: [NOCDAPC] D11_APC_1: 0xfff
9968 10:01:17.032191 INFO: [NOCDAPC] D12_APC_0: 0x0
9969 10:01:17.034968 INFO: [NOCDAPC] D12_APC_1: 0xfff
9970 10:01:17.038492 INFO: [NOCDAPC] D13_APC_0: 0x0
9971 10:01:17.041374 INFO: [NOCDAPC] D13_APC_1: 0xfff
9972 10:01:17.044644 INFO: [NOCDAPC] D14_APC_0: 0x0
9973 10:01:17.048461 INFO: [NOCDAPC] D14_APC_1: 0xfff
9974 10:01:17.051033 INFO: [NOCDAPC] D15_APC_0: 0x0
9975 10:01:17.054929 INFO: [NOCDAPC] D15_APC_1: 0xfff
9976 10:01:17.058297 INFO: [NOCDAPC] APC_CON: 0x4
9977 10:01:17.061255 INFO: [APUAPC] set_apusys_apc done
9978 10:01:17.064698 INFO: [DEVAPC] devapc_init done
9979 10:01:17.067953 INFO: GICv3 without legacy support detected.
9980 10:01:17.071309 INFO: ARM GICv3 driver initialized in EL3
9981 10:01:17.078129 INFO: Maximum SPI INTID supported: 639
9982 10:01:17.081572 INFO: BL31: Initializing runtime services
9983 10:01:17.088002 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9984 10:01:17.088590 INFO: SPM: enable CPC mode
9985 10:01:17.094579 INFO: mcdi ready for mcusys-off-idle and system suspend
9986 10:01:17.097665 INFO: BL31: Preparing for EL3 exit to normal world
9987 10:01:17.101220 INFO: Entry point address = 0x80000000
9988 10:01:17.104655 INFO: SPSR = 0x8
9989 10:01:17.110351
9990 10:01:17.110917
9991 10:01:17.111286
9992 10:01:17.113649 Starting depthcharge on Spherion...
9993 10:01:17.114111
9994 10:01:17.114600 Wipe memory regions:
9995 10:01:17.114962
9996 10:01:17.117650 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9997 10:01:17.118216 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9998 10:01:17.118667 Setting prompt string to ['asurada:']
9999 10:01:17.119099 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10000 10:01:17.119833 [0x00000040000000, 0x00000054600000)
10001 10:01:17.238916
10002 10:01:17.239476 [0x00000054660000, 0x00000080000000)
10003 10:01:17.499693
10004 10:01:17.500304 [0x000000821a7280, 0x000000ffe64000)
10005 10:01:18.244659
10006 10:01:18.245309 [0x00000100000000, 0x00000240000000)
10007 10:01:20.135395
10008 10:01:20.138305 Initializing XHCI USB controller at 0x11200000.
10009 10:01:21.177317
10010 10:01:21.180382 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10011 10:01:21.180847
10012 10:01:21.181217
10013 10:01:21.181562
10014 10:01:21.182391 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10016 10:01:21.283787 asurada: tftpboot 192.168.201.1 11336450/tftp-deploy-8bjmnj5a/kernel/image.itb 11336450/tftp-deploy-8bjmnj5a/kernel/cmdline
10017 10:01:21.284499 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10018 10:01:21.284987 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10019 10:01:21.289804 tftpboot 192.168.201.1 11336450/tftp-deploy-8bjmnj5a/kernel/image.itp-deploy-8bjmnj5a/kernel/cmdline
10020 10:01:21.290281
10021 10:01:21.290649 Waiting for link
10022 10:01:21.447458
10023 10:01:21.448083 R8152: Initializing
10024 10:01:21.448510
10025 10:01:21.450564 Version 6 (ocp_data = 5c30)
10026 10:01:21.451028
10027 10:01:21.453945 R8152: Done initializing
10028 10:01:21.454460
10029 10:01:21.454841 Adding net device
10030 10:01:23.418223
10031 10:01:23.418792 done.
10032 10:01:23.419166
10033 10:01:23.419509 MAC: 00:24:32:30:7c:7b
10034 10:01:23.419847
10035 10:01:23.421243 Sending DHCP discover... done.
10036 10:01:23.421707
10037 10:01:23.424777 Waiting for reply... done.
10038 10:01:23.425333
10039 10:01:23.427589 Sending DHCP request... done.
10040 10:01:23.428092
10041 10:01:23.433900 Waiting for reply... done.
10042 10:01:23.434337
10043 10:01:23.434673 My ip is 192.168.201.14
10044 10:01:23.434988
10045 10:01:23.437132 The DHCP server ip is 192.168.201.1
10046 10:01:23.437558
10047 10:01:23.443577 TFTP server IP predefined by user: 192.168.201.1
10048 10:01:23.444021
10049 10:01:23.450221 Bootfile predefined by user: 11336450/tftp-deploy-8bjmnj5a/kernel/image.itb
10050 10:01:23.450647
10051 10:01:23.454010 Sending tftp read request... done.
10052 10:01:23.454438
10053 10:01:23.460126 Waiting for the transfer...
10054 10:01:23.460659
10055 10:01:24.156214 00000000 ################################################################
10056 10:01:24.156744
10057 10:01:24.857524 00080000 ################################################################
10058 10:01:24.858050
10059 10:01:25.575609 00100000 ################################################################
10060 10:01:25.576164
10061 10:01:26.304020 00180000 ################################################################
10062 10:01:26.304550
10063 10:01:27.032185 00200000 ################################################################
10064 10:01:27.032766
10065 10:01:27.757791 00280000 ################################################################
10066 10:01:27.758354
10067 10:01:28.475017 00300000 ################################################################
10068 10:01:28.475550
10069 10:01:29.186579 00380000 ################################################################
10070 10:01:29.187076
10071 10:01:29.905901 00400000 ################################################################
10072 10:01:29.906454
10073 10:01:30.613437 00480000 ################################################################
10074 10:01:30.613931
10075 10:01:31.317801 00500000 ################################################################
10076 10:01:31.318290
10077 10:01:32.012022 00580000 ################################################################
10078 10:01:32.012522
10079 10:01:32.704991 00600000 ################################################################
10080 10:01:32.705513
10081 10:01:33.416308 00680000 ################################################################
10082 10:01:33.416878
10083 10:01:34.136879 00700000 ################################################################
10084 10:01:34.137410
10085 10:01:34.859159 00780000 ################################################################
10086 10:01:34.859696
10087 10:01:35.585467 00800000 ################################################################
10088 10:01:35.585982
10089 10:01:36.294374 00880000 ################################################################
10090 10:01:36.294890
10091 10:01:37.011117 00900000 ################################################################
10092 10:01:37.011635
10093 10:01:37.692144 00980000 ################################################################
10094 10:01:37.692322
10095 10:01:38.374034 00a00000 ################################################################
10096 10:01:38.374553
10097 10:01:39.074829 00a80000 ################################################################
10098 10:01:39.075346
10099 10:01:39.789767 00b00000 ################################################################
10100 10:01:39.790285
10101 10:01:40.516437 00b80000 ################################################################
10102 10:01:40.516981
10103 10:01:41.244775 00c00000 ################################################################
10104 10:01:41.245371
10105 10:01:41.967199 00c80000 ################################################################
10106 10:01:41.967779
10107 10:01:42.666047 00d00000 ################################################################
10108 10:01:42.666561
10109 10:01:43.363469 00d80000 ################################################################
10110 10:01:43.364053
10111 10:01:44.040907 00e00000 ################################################################
10112 10:01:44.041486
10113 10:01:44.733390 00e80000 ################################################################
10114 10:01:44.733934
10115 10:01:45.418258 00f00000 ################################################################
10116 10:01:45.418804
10117 10:01:46.131246 00f80000 ################################################################
10118 10:01:46.131757
10119 10:01:46.859587 01000000 ################################################################
10120 10:01:46.860173
10121 10:01:47.577075 01080000 ################################################################
10122 10:01:47.577620
10123 10:01:48.295270 01100000 ################################################################
10124 10:01:48.295783
10125 10:01:49.015239 01180000 ################################################################
10126 10:01:49.015754
10127 10:01:49.723616 01200000 ################################################################
10128 10:01:49.724239
10129 10:01:50.446016 01280000 ################################################################
10130 10:01:50.446576
10131 10:01:51.178368 01300000 ################################################################
10132 10:01:51.178890
10133 10:01:51.911147 01380000 ################################################################
10134 10:01:51.911676
10135 10:01:52.646299 01400000 ################################################################
10136 10:01:52.646822
10137 10:01:53.372907 01480000 ################################################################
10138 10:01:53.373424
10139 10:01:54.089290 01500000 ################################################################
10140 10:01:54.089816
10141 10:01:54.801472 01580000 ################################################################
10142 10:01:54.802027
10143 10:01:55.511714 01600000 ################################################################
10144 10:01:55.512294
10145 10:01:56.237441 01680000 ################################################################
10146 10:01:56.237963
10147 10:01:56.959107 01700000 ################################################################
10148 10:01:56.959638
10149 10:01:57.661566 01780000 ################################################################
10150 10:01:57.662109
10151 10:01:58.343093 01800000 ################################################################
10152 10:01:58.343626
10153 10:01:59.059980 01880000 ################################################################
10154 10:01:59.060521
10155 10:01:59.773476 01900000 ################################################################
10156 10:01:59.774010
10157 10:02:00.478894 01980000 ################################################################
10158 10:02:00.479389
10159 10:02:01.187238 01a00000 ################################################################
10160 10:02:01.187751
10161 10:02:01.882669 01a80000 ################################################################
10162 10:02:01.883228
10163 10:02:02.611968 01b00000 ################################################################
10164 10:02:02.612554
10165 10:02:03.328874 01b80000 ################################################################
10166 10:02:03.329380
10167 10:02:04.034904 01c00000 ################################################################
10168 10:02:04.035435
10169 10:02:04.761822 01c80000 ################################################################
10170 10:02:04.762387
10171 10:02:05.473304 01d00000 ################################################################
10172 10:02:05.473833
10173 10:02:06.214616 01d80000 ################################################################
10174 10:02:06.215144
10175 10:02:06.899531 01e00000 ################################################################
10176 10:02:06.900104
10177 10:02:07.635233 01e80000 ################################################################
10178 10:02:07.635762
10179 10:02:08.366532 01f00000 ################################################################
10180 10:02:08.367088
10181 10:02:09.078089 01f80000 ################################################################
10182 10:02:09.078636
10183 10:02:09.784065 02000000 ################################################################
10184 10:02:09.784623
10185 10:02:10.468892 02080000 ################################################################
10186 10:02:10.469507
10187 10:02:11.181802 02100000 ################################################################
10188 10:02:11.182344
10189 10:02:11.891860 02180000 ################################################################
10190 10:02:11.892492
10191 10:02:12.601792 02200000 ################################################################
10192 10:02:12.602344
10193 10:02:13.320332 02280000 ################################################################
10194 10:02:13.321012
10195 10:02:14.044442 02300000 ################################################################
10196 10:02:14.044963
10197 10:02:14.748166 02380000 ################################################################
10198 10:02:14.748683
10199 10:02:15.442447 02400000 ################################################################
10200 10:02:15.442973
10201 10:02:16.132738 02480000 ################################################################
10202 10:02:16.133395
10203 10:02:16.823706 02500000 ################################################################
10204 10:02:16.824261
10205 10:02:17.523201 02580000 ################################################################
10206 10:02:17.523723
10207 10:02:18.207163 02600000 ################################################################
10208 10:02:18.207680
10209 10:02:18.894390 02680000 ################################################################
10210 10:02:18.894991
10211 10:02:19.598292 02700000 ################################################################
10212 10:02:19.598825
10213 10:02:20.307777 02780000 ################################################################
10214 10:02:20.308465
10215 10:02:21.032571 02800000 ################################################################
10216 10:02:21.033080
10217 10:02:21.735477 02880000 ################################################################
10218 10:02:21.736065
10219 10:02:22.466907 02900000 ################################################################
10220 10:02:22.467423
10221 10:02:23.185272 02980000 ################################################################
10222 10:02:23.185853
10223 10:02:23.914111 02a00000 ################################################################
10224 10:02:23.914698
10225 10:02:24.596581 02a80000 ################################################################
10226 10:02:24.596731
10227 10:02:25.252580 02b00000 ################################################################
10228 10:02:25.253090
10229 10:02:25.934529 02b80000 ################################################################
10230 10:02:25.934670
10231 10:02:26.535289 02c00000 ################################################################
10232 10:02:26.535424
10233 10:02:27.123042 02c80000 ################################################################
10234 10:02:27.123193
10235 10:02:27.721029 02d00000 ################################################################
10236 10:02:27.721182
10237 10:02:28.297194 02d80000 ################################################################
10238 10:02:28.297338
10239 10:02:28.855812 02e00000 ################################################################
10240 10:02:28.856014
10241 10:02:29.400173 02e80000 ################################################################
10242 10:02:29.400371
10243 10:02:29.960296 02f00000 ################################################################
10244 10:02:29.960446
10245 10:02:30.539285 02f80000 ################################################################
10246 10:02:30.539432
10247 10:02:31.099546 03000000 ################################################################
10248 10:02:31.099696
10249 10:02:31.661378 03080000 ################################################################
10250 10:02:31.661532
10251 10:02:32.233879 03100000 ################################################################
10252 10:02:32.234030
10253 10:02:32.814473 03180000 ################################################################
10254 10:02:32.814618
10255 10:02:33.371505 03200000 ################################################################
10256 10:02:33.371654
10257 10:02:33.943642 03280000 ################################################################
10258 10:02:33.943791
10259 10:02:34.519003 03300000 ################################################################
10260 10:02:34.519149
10261 10:02:35.098028 03380000 ################################################################
10262 10:02:35.098182
10263 10:02:35.681138 03400000 ################################################################
10264 10:02:35.681293
10265 10:02:36.254665 03480000 ################################################################
10266 10:02:36.254823
10267 10:02:36.831526 03500000 ################################################################
10268 10:02:36.831683
10269 10:02:37.408102 03580000 ################################################################
10270 10:02:37.408258
10271 10:02:37.967690 03600000 ################################################################
10272 10:02:37.967846
10273 10:02:38.540439 03680000 ################################################################
10274 10:02:38.540595
10275 10:02:39.118296 03700000 ################################################################
10276 10:02:39.118458
10277 10:02:39.694792 03780000 ################################################################
10278 10:02:39.694948
10279 10:02:40.276567 03800000 ################################################################
10280 10:02:40.276723
10281 10:02:40.851260 03880000 ################################################################
10282 10:02:40.851413
10283 10:02:41.430697 03900000 ################################################################
10284 10:02:41.430854
10285 10:02:42.002971 03980000 ################################################################
10286 10:02:42.003123
10287 10:02:42.574599 03a00000 ################################################################
10288 10:02:42.574772
10289 10:02:43.155666 03a80000 ################################################################
10290 10:02:43.155819
10291 10:02:43.747533 03b00000 ################################################################
10292 10:02:43.747688
10293 10:02:44.319607 03b80000 ################################################################
10294 10:02:44.319759
10295 10:02:44.880394 03c00000 ################################################################
10296 10:02:44.880557
10297 10:02:45.449129 03c80000 ################################################################
10298 10:02:45.449274
10299 10:02:46.028585 03d00000 ################################################################
10300 10:02:46.028750
10301 10:02:46.597895 03d80000 ################################################################
10302 10:02:46.598044
10303 10:02:47.168722 03e00000 ################################################################
10304 10:02:47.168867
10305 10:02:47.767633 03e80000 ################################################################
10306 10:02:47.767779
10307 10:02:48.364522 03f00000 ################################################################
10308 10:02:48.365024
10309 10:02:49.054983 03f80000 ################################################################
10310 10:02:49.055495
10311 10:02:49.771529 04000000 ################################################################
10312 10:02:49.772079
10313 10:02:50.491237 04080000 ################################################################
10314 10:02:50.491742
10315 10:02:51.221976 04100000 ################################################################
10316 10:02:51.222522
10317 10:02:51.940752 04180000 ################################################################
10318 10:02:51.941446
10319 10:02:52.670003 04200000 ################################################################
10320 10:02:52.670550
10321 10:02:53.389940 04280000 ################################################################
10322 10:02:53.390460
10323 10:02:54.090649 04300000 ################################################################
10324 10:02:54.091158
10325 10:02:54.795899 04380000 ################################################################
10326 10:02:54.796430
10327 10:02:55.503848 04400000 ################################################################
10328 10:02:55.504392
10329 10:02:56.210105 04480000 ################################################################
10330 10:02:56.210600
10331 10:02:56.936717 04500000 ################################################################
10332 10:02:56.937219
10333 10:02:57.672422 04580000 ################################################################
10334 10:02:57.672949
10335 10:02:58.279573 04600000 ################################################################
10336 10:02:58.279721
10337 10:02:58.821548 04680000 ################################################################
10338 10:02:58.821694
10339 10:02:59.380424 04700000 ################################################################
10340 10:02:59.380564
10341 10:02:59.941751 04780000 ################################################################
10342 10:02:59.941891
10343 10:03:00.484574 04800000 ################################################################
10344 10:03:00.484712
10345 10:03:01.035132 04880000 ################################################################
10346 10:03:01.035279
10347 10:03:01.591245 04900000 ################################################################
10348 10:03:01.591382
10349 10:03:02.130656 04980000 ################################################################
10350 10:03:02.130798
10351 10:03:02.672485 04a00000 ################################################################
10352 10:03:02.672626
10353 10:03:03.216173 04a80000 ################################################################
10354 10:03:03.216317
10355 10:03:03.763712 04b00000 ################################################################
10356 10:03:03.763853
10357 10:03:04.308477 04b80000 ################################################################
10358 10:03:04.308620
10359 10:03:04.837638 04c00000 ################################################################
10360 10:03:04.837784
10361 10:03:05.383805 04c80000 ################################################################
10362 10:03:05.383999
10363 10:03:05.916441 04d00000 ################################################################
10364 10:03:05.916573
10365 10:03:06.456335 04d80000 ################################################################
10366 10:03:06.456478
10367 10:03:06.995860 04e00000 ################################################################
10368 10:03:06.996010
10369 10:03:07.549153 04e80000 ################################################################
10370 10:03:07.549297
10371 10:03:08.111934 04f00000 ################################################################
10372 10:03:08.112091
10373 10:03:08.660753 04f80000 ################################################################
10374 10:03:08.660887
10375 10:03:09.198522 05000000 ################################################################
10376 10:03:09.198660
10377 10:03:09.733351 05080000 ################################################################
10378 10:03:09.733494
10379 10:03:10.273040 05100000 ################################################################
10380 10:03:10.273187
10381 10:03:10.829551 05180000 ################################################################
10382 10:03:10.829698
10383 10:03:11.377254 05200000 ################################################################
10384 10:03:11.377418
10385 10:03:11.916645 05280000 ################################################################
10386 10:03:11.916822
10387 10:03:12.469422 05300000 ################################################################
10388 10:03:12.469561
10389 10:03:13.030235 05380000 ################################################################
10390 10:03:13.030379
10391 10:03:13.600204 05400000 ################################################################
10392 10:03:13.600353
10393 10:03:14.170568 05480000 ################################################################
10394 10:03:14.170712
10395 10:03:14.726691 05500000 ################################################################
10396 10:03:14.726822
10397 10:03:15.271528 05580000 ################################################################
10398 10:03:15.271667
10399 10:03:15.812813 05600000 ################################################################
10400 10:03:15.812956
10401 10:03:16.357842 05680000 ################################################################
10402 10:03:16.357984
10403 10:03:16.908542 05700000 ################################################################
10404 10:03:16.908691
10405 10:03:17.456400 05780000 ################################################################
10406 10:03:17.456538
10407 10:03:18.023084 05800000 ################################################################
10408 10:03:18.023224
10409 10:03:18.569091 05880000 ################################################################
10410 10:03:18.569234
10411 10:03:19.098413 05900000 ################################################################
10412 10:03:19.098554
10413 10:03:19.657144 05980000 ################################################################
10414 10:03:19.657338
10415 10:03:20.198756 05a00000 ################################################################
10416 10:03:20.198913
10417 10:03:20.727668 05a80000 ################################################################
10418 10:03:20.727803
10419 10:03:21.284258 05b00000 ################################################################
10420 10:03:21.284395
10421 10:03:21.839576 05b80000 ################################################################
10422 10:03:21.839751
10423 10:03:22.395120 05c00000 ################################################################
10424 10:03:22.395269
10425 10:03:22.953423 05c80000 ################################################################
10426 10:03:22.953602
10427 10:03:23.512106 05d00000 ################################################################
10428 10:03:23.512242
10429 10:03:24.052033 05d80000 ################################################################
10430 10:03:24.052166
10431 10:03:24.594709 05e00000 ################################################################
10432 10:03:24.594852
10433 10:03:25.136919 05e80000 ################################################################
10434 10:03:25.137059
10435 10:03:25.689582 05f00000 ################################################################
10436 10:03:25.689714
10437 10:03:26.232077 05f80000 ################################################################
10438 10:03:26.232220
10439 10:03:26.781477 06000000 ################################################################
10440 10:03:26.781611
10441 10:03:27.336059 06080000 ################################################################
10442 10:03:27.336194
10443 10:03:27.881061 06100000 ################################################################
10444 10:03:27.881201
10445 10:03:28.418955 06180000 ################################################################
10446 10:03:28.419097
10447 10:03:28.992612 06200000 ################################################################
10448 10:03:28.992757
10449 10:03:29.535150 06280000 ################################################################
10450 10:03:29.535288
10451 10:03:30.102640 06300000 ################################################################
10452 10:03:30.102775
10453 10:03:30.779631 06380000 ################################################################
10454 10:03:30.780175
10455 10:03:31.473074 06400000 ################################################################
10456 10:03:31.473634
10457 10:03:32.143008 06480000 ################################################################
10458 10:03:32.143500
10459 10:03:32.858988 06500000 ################################################################
10460 10:03:32.859482
10461 10:03:33.577204 06580000 ################################################################
10462 10:03:33.577701
10463 10:03:34.296268 06600000 ################################################################
10464 10:03:34.296972
10465 10:03:35.004802 06680000 ################################################################
10466 10:03:35.005356
10467 10:03:35.699406 06700000 ################################################################
10468 10:03:35.699896
10469 10:03:36.405423 06780000 ################################################################
10470 10:03:36.405990
10471 10:03:36.848775 06800000 ######################################### done.
10472 10:03:36.849347
10473 10:03:36.851657 The bootfile was 109380934 bytes long.
10474 10:03:36.852158
10475 10:03:36.854912 Sending tftp read request... done.
10476 10:03:36.855345
10477 10:03:36.858031 Waiting for the transfer...
10478 10:03:36.858449
10479 10:03:36.861821 00000000 # done.
10480 10:03:36.862268
10481 10:03:36.867779 Command line loaded dynamically from TFTP file: 11336450/tftp-deploy-8bjmnj5a/kernel/cmdline
10482 10:03:36.868235
10483 10:03:36.881384 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10484 10:03:36.881918
10485 10:03:36.884443 Loading FIT.
10486 10:03:36.884964
10487 10:03:36.887956 Image ramdisk-1 has 98294362 bytes.
10488 10:03:36.888501
10489 10:03:36.891121 Image fdt-1 has 47278 bytes.
10490 10:03:36.891637
10491 10:03:36.892017 Image kernel-1 has 11037260 bytes.
10492 10:03:36.894356
10493 10:03:36.900930 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10494 10:03:36.901440
10495 10:03:36.917718 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10496 10:03:36.920388
10497 10:03:36.924371 Choosing best match conf-1 for compat google,spherion-rev2.
10498 10:03:36.928590
10499 10:03:36.932978 Connected to device vid:did:rid of 1ae0:0028:00
10500 10:03:36.941413
10501 10:03:36.944738 tpm_get_response: command 0x17b, return code 0x0
10502 10:03:36.945365
10503 10:03:36.948317 ec_init: CrosEC protocol v3 supported (256, 248)
10504 10:03:36.952061
10505 10:03:36.955466 tpm_cleanup: add release locality here.
10506 10:03:36.956348
10507 10:03:36.956749 Shutting down all USB controllers.
10508 10:03:36.958452
10509 10:03:36.958928 Removing current net device
10510 10:03:36.959298
10511 10:03:36.964785 Exiting depthcharge with code 4 at timestamp: 169091861
10512 10:03:36.965259
10513 10:03:36.968064 LZMA decompressing kernel-1 to 0x821a6718
10514 10:03:36.968528
10515 10:03:36.971853 LZMA decompressing kernel-1 to 0x40000000
10516 10:03:38.359433
10517 10:03:38.360043 jumping to kernel
10518 10:03:38.361901 end: 2.2.4 bootloader-commands (duration 00:02:21) [common]
10519 10:03:38.362517 start: 2.2.5 auto-login-action (timeout 00:02:04) [common]
10520 10:03:38.362930 Setting prompt string to ['Linux version [0-9]']
10521 10:03:38.363331 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10522 10:03:38.363711 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10523 10:03:38.441163
10524 10:03:38.444574 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10525 10:03:38.448317 start: 2.2.5.1 login-action (timeout 00:02:04) [common]
10526 10:03:38.448901 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10527 10:03:38.449297 Setting prompt string to []
10528 10:03:38.449729 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10529 10:03:38.450130 Using line separator: #'\n'#
10530 10:03:38.450502 No login prompt set.
10531 10:03:38.450851 Parsing kernel messages
10532 10:03:38.451165 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10533 10:03:38.451713 [login-action] Waiting for messages, (timeout 00:02:04)
10534 10:03:38.467375 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j18697-arm64-gcc-10-defconfig-arm64-chromebook-vvl9c) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 23 09:52:58 UTC 2023
10535 10:03:38.470837 [ 0.000000] random: crng init done
10536 10:03:38.477587 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10537 10:03:38.480599 [ 0.000000] efi: UEFI not found.
10538 10:03:38.486977 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10539 10:03:38.494105 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10540 10:03:38.503656 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10541 10:03:38.513946 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10542 10:03:38.520786 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10543 10:03:38.527123 [ 0.000000] printk: bootconsole [mtk8250] enabled
10544 10:03:38.533466 [ 0.000000] NUMA: No NUMA configuration found
10545 10:03:38.540409 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10546 10:03:38.543578 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10547 10:03:38.547217 [ 0.000000] Zone ranges:
10548 10:03:38.553531 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10549 10:03:38.556745 [ 0.000000] DMA32 empty
10550 10:03:38.563216 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10551 10:03:38.566249 [ 0.000000] Movable zone start for each node
10552 10:03:38.569523 [ 0.000000] Early memory node ranges
10553 10:03:38.576631 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10554 10:03:38.583275 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10555 10:03:38.589845 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10556 10:03:38.596051 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10557 10:03:38.603185 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10558 10:03:38.609121 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10559 10:03:38.665211 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10560 10:03:38.672271 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10561 10:03:38.679134 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10562 10:03:38.682347 [ 0.000000] psci: probing for conduit method from DT.
10563 10:03:38.688354 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10564 10:03:38.692021 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10565 10:03:38.698456 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10566 10:03:38.701510 [ 0.000000] psci: SMC Calling Convention v1.2
10567 10:03:38.708287 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10568 10:03:38.711304 [ 0.000000] Detected VIPT I-cache on CPU0
10569 10:03:38.717974 [ 0.000000] CPU features: detected: GIC system register CPU interface
10570 10:03:38.724601 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10571 10:03:38.731183 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10572 10:03:38.737752 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10573 10:03:38.747534 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10574 10:03:38.755011 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10575 10:03:38.758203 [ 0.000000] alternatives: applying boot alternatives
10576 10:03:38.763962 [ 0.000000] Fallback order for Node 0: 0
10577 10:03:38.770709 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10578 10:03:38.773890 [ 0.000000] Policy zone: Normal
10579 10:03:38.787805 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10580 10:03:38.797504 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10581 10:03:38.808508 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10582 10:03:38.818526 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10583 10:03:38.826005 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10584 10:03:38.828521 <6>[ 0.000000] software IO TLB: area num 8.
10585 10:03:38.885271 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10586 10:03:39.034677 <6>[ 0.000000] Memory: 7873560K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 479208K reserved, 32768K cma-reserved)
10587 10:03:39.040673 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10588 10:03:39.047844 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10589 10:03:39.051311 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10590 10:03:39.057366 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10591 10:03:39.063858 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10592 10:03:39.067355 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10593 10:03:39.076747 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10594 10:03:39.083827 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10595 10:03:39.090560 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10596 10:03:39.096665 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10597 10:03:39.100254 <6>[ 0.000000] GICv3: 608 SPIs implemented
10598 10:03:39.103623 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10599 10:03:39.110451 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10600 10:03:39.113618 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10601 10:03:39.119688 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10602 10:03:39.133196 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10603 10:03:39.146550 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10604 10:03:39.152853 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10605 10:03:39.160923 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10606 10:03:39.173975 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10607 10:03:39.180712 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10608 10:03:39.187387 <6>[ 0.009183] Console: colour dummy device 80x25
10609 10:03:39.197020 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10610 10:03:39.203640 <6>[ 0.024417] pid_max: default: 32768 minimum: 301
10611 10:03:39.206746 <6>[ 0.029282] LSM: Security Framework initializing
10612 10:03:39.213448 <6>[ 0.034219] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10613 10:03:39.224004 <6>[ 0.042031] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10614 10:03:39.233485 <6>[ 0.051468] cblist_init_generic: Setting adjustable number of callback queues.
10615 10:03:39.237202 <6>[ 0.058959] cblist_init_generic: Setting shift to 3 and lim to 1.
10616 10:03:39.246742 <6>[ 0.065298] cblist_init_generic: Setting adjustable number of callback queues.
10617 10:03:39.253333 <6>[ 0.072724] cblist_init_generic: Setting shift to 3 and lim to 1.
10618 10:03:39.256517 <6>[ 0.079123] rcu: Hierarchical SRCU implementation.
10619 10:03:39.263476 <6>[ 0.084136] rcu: Max phase no-delay instances is 1000.
10620 10:03:39.269634 <6>[ 0.091167] EFI services will not be available.
10621 10:03:39.272575 <6>[ 0.096114] smp: Bringing up secondary CPUs ...
10622 10:03:39.282088 <6>[ 0.101167] Detected VIPT I-cache on CPU1
10623 10:03:39.288602 <6>[ 0.101237] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10624 10:03:39.294782 <6>[ 0.101268] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10625 10:03:39.298545 <6>[ 0.101598] Detected VIPT I-cache on CPU2
10626 10:03:39.308041 <6>[ 0.101646] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10627 10:03:39.314866 <6>[ 0.101662] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10628 10:03:39.318041 <6>[ 0.101919] Detected VIPT I-cache on CPU3
10629 10:03:39.324552 <6>[ 0.101965] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10630 10:03:39.331204 <6>[ 0.101979] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10631 10:03:39.337665 <6>[ 0.102283] CPU features: detected: Spectre-v4
10632 10:03:39.340726 <6>[ 0.102289] CPU features: detected: Spectre-BHB
10633 10:03:39.343855 <6>[ 0.102294] Detected PIPT I-cache on CPU4
10634 10:03:39.350693 <6>[ 0.102350] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10635 10:03:39.360425 <6>[ 0.102368] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10636 10:03:39.364004 <6>[ 0.102665] Detected PIPT I-cache on CPU5
10637 10:03:39.370476 <6>[ 0.102727] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10638 10:03:39.377296 <6>[ 0.102744] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10639 10:03:39.380294 <6>[ 0.103024] Detected PIPT I-cache on CPU6
10640 10:03:39.390568 <6>[ 0.103089] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10641 10:03:39.396996 <6>[ 0.103106] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10642 10:03:39.400070 <6>[ 0.103407] Detected PIPT I-cache on CPU7
10643 10:03:39.406538 <6>[ 0.103470] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10644 10:03:39.412866 <6>[ 0.103486] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10645 10:03:39.416203 <6>[ 0.103533] smp: Brought up 1 node, 8 CPUs
10646 10:03:39.422785 <6>[ 0.244814] SMP: Total of 8 processors activated.
10647 10:03:39.429826 <6>[ 0.249734] CPU features: detected: 32-bit EL0 Support
10648 10:03:39.436391 <6>[ 0.255098] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10649 10:03:39.442814 <6>[ 0.263898] CPU features: detected: Common not Private translations
10650 10:03:39.449229 <6>[ 0.270374] CPU features: detected: CRC32 instructions
10651 10:03:39.456755 <6>[ 0.275758] CPU features: detected: RCpc load-acquire (LDAPR)
10652 10:03:39.459642 <6>[ 0.281718] CPU features: detected: LSE atomic instructions
10653 10:03:39.465749 <6>[ 0.287499] CPU features: detected: Privileged Access Never
10654 10:03:39.472499 <6>[ 0.293279] CPU features: detected: RAS Extension Support
10655 10:03:39.479376 <6>[ 0.298888] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10656 10:03:39.482341 <6>[ 0.306108] CPU: All CPU(s) started at EL2
10657 10:03:39.488540 <6>[ 0.310424] alternatives: applying system-wide alternatives
10658 10:03:39.499224 <6>[ 0.321168] devtmpfs: initialized
10659 10:03:39.511597 <6>[ 0.330068] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10660 10:03:39.521997 <6>[ 0.340032] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10661 10:03:39.525095 <6>[ 0.347699] pinctrl core: initialized pinctrl subsystem
10662 10:03:39.532952 <6>[ 0.354370] DMI not present or invalid.
10663 10:03:39.539735 <6>[ 0.358776] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10664 10:03:39.545945 <6>[ 0.365626] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10665 10:03:39.555974 <6>[ 0.373207] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10666 10:03:39.562137 <6>[ 0.381419] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10667 10:03:39.568600 <6>[ 0.389661] audit: initializing netlink subsys (disabled)
10668 10:03:39.575179 <5>[ 0.395353] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10669 10:03:39.581981 <6>[ 0.396061] thermal_sys: Registered thermal governor 'step_wise'
10670 10:03:39.588337 <6>[ 0.403319] thermal_sys: Registered thermal governor 'power_allocator'
10671 10:03:39.595481 <6>[ 0.409572] cpuidle: using governor menu
10672 10:03:39.598521 <6>[ 0.420536] NET: Registered PF_QIPCRTR protocol family
10673 10:03:39.604804 <6>[ 0.426014] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10674 10:03:39.611594 <6>[ 0.433120] ASID allocator initialised with 32768 entries
10675 10:03:39.618487 <6>[ 0.439690] Serial: AMBA PL011 UART driver
10676 10:03:39.626893 <4>[ 0.448509] Trying to register duplicate clock ID: 134
10677 10:03:39.680434 <6>[ 0.505870] KASLR enabled
10678 10:03:39.694804 <6>[ 0.513553] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10679 10:03:39.701119 <6>[ 0.520569] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10680 10:03:39.707967 <6>[ 0.527062] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10681 10:03:39.714474 <6>[ 0.534069] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10682 10:03:39.721585 <6>[ 0.540558] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10683 10:03:39.727818 <6>[ 0.547561] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10684 10:03:39.734704 <6>[ 0.554047] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10685 10:03:39.740801 <6>[ 0.561053] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10686 10:03:39.743880 <6>[ 0.568551] ACPI: Interpreter disabled.
10687 10:03:39.752831 <6>[ 0.574946] iommu: Default domain type: Translated
10688 10:03:39.759776 <6>[ 0.580058] iommu: DMA domain TLB invalidation policy: strict mode
10689 10:03:39.763052 <5>[ 0.586709] SCSI subsystem initialized
10690 10:03:39.769404 <6>[ 0.590870] usbcore: registered new interface driver usbfs
10691 10:03:39.776104 <6>[ 0.596604] usbcore: registered new interface driver hub
10692 10:03:39.779035 <6>[ 0.602156] usbcore: registered new device driver usb
10693 10:03:39.786602 <6>[ 0.608249] pps_core: LinuxPPS API ver. 1 registered
10694 10:03:39.796282 <6>[ 0.613445] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10695 10:03:39.799454 <6>[ 0.622792] PTP clock support registered
10696 10:03:39.802873 <6>[ 0.627034] EDAC MC: Ver: 3.0.0
10697 10:03:39.809821 <6>[ 0.632175] FPGA manager framework
10698 10:03:39.816823 <6>[ 0.635854] Advanced Linux Sound Architecture Driver Initialized.
10699 10:03:39.820241 <6>[ 0.642628] vgaarb: loaded
10700 10:03:39.826839 <6>[ 0.645801] clocksource: Switched to clocksource arch_sys_counter
10701 10:03:39.830094 <5>[ 0.652230] VFS: Disk quotas dquot_6.6.0
10702 10:03:39.836464 <6>[ 0.656413] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10703 10:03:39.839753 <6>[ 0.663603] pnp: PnP ACPI: disabled
10704 10:03:39.848594 <6>[ 0.670270] NET: Registered PF_INET protocol family
10705 10:03:39.858044 <6>[ 0.675852] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10706 10:03:39.869329 <6>[ 0.688144] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10707 10:03:39.879447 <6>[ 0.696958] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10708 10:03:39.885682 <6>[ 0.704928] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10709 10:03:39.895600 <6>[ 0.713630] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10710 10:03:39.902268 <6>[ 0.723376] TCP: Hash tables configured (established 65536 bind 65536)
10711 10:03:39.908881 <6>[ 0.730232] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10712 10:03:39.919323 <6>[ 0.737431] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10713 10:03:39.925272 <6>[ 0.745134] NET: Registered PF_UNIX/PF_LOCAL protocol family
10714 10:03:39.928601 <6>[ 0.751305] RPC: Registered named UNIX socket transport module.
10715 10:03:39.935637 <6>[ 0.757460] RPC: Registered udp transport module.
10716 10:03:39.938660 <6>[ 0.762394] RPC: Registered tcp transport module.
10717 10:03:39.945200 <6>[ 0.767327] RPC: Registered tcp NFSv4.1 backchannel transport module.
10718 10:03:39.952226 <6>[ 0.773996] PCI: CLS 0 bytes, default 64
10719 10:03:39.955344 <6>[ 0.778388] Unpacking initramfs...
10720 10:03:39.979278 <6>[ 0.798024] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10721 10:03:39.989170 <6>[ 0.806693] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10722 10:03:39.992707 <6>[ 0.815551] kvm [1]: IPA Size Limit: 40 bits
10723 10:03:39.999420 <6>[ 0.820081] kvm [1]: GICv3: no GICV resource entry
10724 10:03:40.002556 <6>[ 0.825104] kvm [1]: disabling GICv2 emulation
10725 10:03:40.009047 <6>[ 0.829797] kvm [1]: GIC system register CPU interface enabled
10726 10:03:40.012273 <6>[ 0.835977] kvm [1]: vgic interrupt IRQ18
10727 10:03:40.018697 <6>[ 0.840336] kvm [1]: VHE mode initialized successfully
10728 10:03:40.026532 <5>[ 0.846976] Initialise system trusted keyrings
10729 10:03:40.031971 <6>[ 0.851799] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10730 10:03:40.039969 <6>[ 0.861769] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10731 10:03:40.046243 <5>[ 0.868164] NFS: Registering the id_resolver key type
10732 10:03:40.049620 <5>[ 0.873468] Key type id_resolver registered
10733 10:03:40.056189 <5>[ 0.877885] Key type id_legacy registered
10734 10:03:40.062978 <6>[ 0.882181] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10735 10:03:40.069272 <6>[ 0.889102] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10736 10:03:40.075851 <6>[ 0.896839] 9p: Installing v9fs 9p2000 file system support
10737 10:03:40.113301 <5>[ 0.935158] Key type asymmetric registered
10738 10:03:40.116641 <5>[ 0.939491] Asymmetric key parser 'x509' registered
10739 10:03:40.126616 <6>[ 0.944686] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10740 10:03:40.130200 <6>[ 0.952307] io scheduler mq-deadline registered
10741 10:03:40.132782 <6>[ 0.957079] io scheduler kyber registered
10742 10:03:40.152264 <6>[ 0.974136] EINJ: ACPI disabled.
10743 10:03:40.184884 <4>[ 0.999991] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10744 10:03:40.194766 <4>[ 1.010646] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10745 10:03:40.209300 <6>[ 1.031510] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10746 10:03:40.217438 <6>[ 1.039615] printk: console [ttyS0] disabled
10747 10:03:40.245840 <6>[ 1.064263] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10748 10:03:40.252790 <6>[ 1.073759] printk: console [ttyS0] enabled
10749 10:03:40.255647 <6>[ 1.073759] printk: console [ttyS0] enabled
10750 10:03:40.262188 <6>[ 1.082653] printk: bootconsole [mtk8250] disabled
10751 10:03:40.265188 <6>[ 1.082653] printk: bootconsole [mtk8250] disabled
10752 10:03:40.272080 <6>[ 1.093957] SuperH (H)SCI(F) driver initialized
10753 10:03:40.275287 <6>[ 1.099223] msm_serial: driver initialized
10754 10:03:40.289720 <6>[ 1.108278] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10755 10:03:40.299648 <6>[ 1.116829] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10756 10:03:40.306408 <6>[ 1.125372] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10757 10:03:40.315859 <6>[ 1.134001] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10758 10:03:40.322921 <6>[ 1.142707] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10759 10:03:40.333188 <6>[ 1.151420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10760 10:03:40.342645 <6>[ 1.159968] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10761 10:03:40.349902 <6>[ 1.168761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10762 10:03:40.359175 <6>[ 1.177310] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10763 10:03:40.371341 <6>[ 1.192942] loop: module loaded
10764 10:03:40.377734 <6>[ 1.198854] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10765 10:03:40.400059 <4>[ 1.222187] mtk-pmic-keys: Failed to locate of_node [id: -1]
10766 10:03:40.407222 <6>[ 1.229031] megasas: 07.719.03.00-rc1
10767 10:03:40.416704 <6>[ 1.238664] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10768 10:03:40.423264 <6>[ 1.245182] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10769 10:03:40.440201 <6>[ 1.261955] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10770 10:03:40.497051 <6>[ 1.312151] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10771 10:03:43.985229 <6>[ 4.807436] Freeing initrd memory: 95988K
10772 10:03:43.995710 <6>[ 4.817962] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10773 10:03:44.006738 <6>[ 4.828911] tun: Universal TUN/TAP device driver, 1.6
10774 10:03:44.009650 <6>[ 4.834982] thunder_xcv, ver 1.0
10775 10:03:44.012864 <6>[ 4.838486] thunder_bgx, ver 1.0
10776 10:03:44.016067 <6>[ 4.841979] nicpf, ver 1.0
10777 10:03:44.027286 <6>[ 4.846025] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10778 10:03:44.030469 <6>[ 4.853500] hns3: Copyright (c) 2017 Huawei Corporation.
10779 10:03:44.037486 <6>[ 4.859089] hclge is initializing
10780 10:03:44.040500 <6>[ 4.862665] e1000: Intel(R) PRO/1000 Network Driver
10781 10:03:44.046958 <6>[ 4.867794] e1000: Copyright (c) 1999-2006 Intel Corporation.
10782 10:03:44.050058 <6>[ 4.873807] e1000e: Intel(R) PRO/1000 Network Driver
10783 10:03:44.057003 <6>[ 4.879023] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10784 10:03:44.063585 <6>[ 4.885211] igb: Intel(R) Gigabit Ethernet Network Driver
10785 10:03:44.069644 <6>[ 4.890860] igb: Copyright (c) 2007-2014 Intel Corporation.
10786 10:03:44.076562 <6>[ 4.896696] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10787 10:03:44.083154 <6>[ 4.903213] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10788 10:03:44.086419 <6>[ 4.909686] sky2: driver version 1.30
10789 10:03:44.093379 <6>[ 4.914696] VFIO - User Level meta-driver version: 0.3
10790 10:03:44.100238 <6>[ 4.922965] usbcore: registered new interface driver usb-storage
10791 10:03:44.106917 <6>[ 4.929413] usbcore: registered new device driver onboard-usb-hub
10792 10:03:44.115858 <6>[ 4.938564] mt6397-rtc mt6359-rtc: registered as rtc0
10793 10:03:44.125780 <6>[ 4.944030] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-23T10:03:45 UTC (1692785025)
10794 10:03:44.129294 <6>[ 4.953604] i2c_dev: i2c /dev entries driver
10795 10:03:44.146332 <6>[ 4.965459] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10796 10:03:44.166102 <6>[ 4.988466] cpu cpu0: EM: created perf domain
10797 10:03:44.169790 <6>[ 4.993450] cpu cpu4: EM: created perf domain
10798 10:03:44.176613 <6>[ 4.999100] sdhci: Secure Digital Host Controller Interface driver
10799 10:03:44.183556 <6>[ 5.005533] sdhci: Copyright(c) Pierre Ossman
10800 10:03:44.189868 <6>[ 5.010495] Synopsys Designware Multimedia Card Interface Driver
10801 10:03:44.196798 <6>[ 5.017128] sdhci-pltfm: SDHCI platform and OF driver helper
10802 10:03:44.199665 <6>[ 5.017161] mmc0: CQHCI version 5.10
10803 10:03:44.206733 <6>[ 5.027494] ledtrig-cpu: registered to indicate activity on CPUs
10804 10:03:44.213451 <6>[ 5.034597] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10805 10:03:44.219686 <6>[ 5.041660] usbcore: registered new interface driver usbhid
10806 10:03:44.223277 <6>[ 5.047482] usbhid: USB HID core driver
10807 10:03:44.229741 <6>[ 5.051680] spi_master spi0: will run message pump with realtime priority
10808 10:03:44.275324 <6>[ 5.091359] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10809 10:03:44.295608 <6>[ 5.107786] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10810 10:03:44.299075 <6>[ 5.121914] mmc0: Command Queue Engine enabled
10811 10:03:44.305875 <6>[ 5.123872] cros-ec-spi spi0.0: Chrome EC device registered
10812 10:03:44.312101 <6>[ 5.126670] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10813 10:03:44.315456 <6>[ 5.139864] mmcblk0: mmc0:0001 DA4128 116 GiB
10814 10:03:44.326898 <6>[ 5.145997] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10815 10:03:44.333437 <6>[ 5.149829] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10816 10:03:44.340391 <6>[ 5.156452] NET: Registered PF_PACKET protocol family
10817 10:03:44.343882 <6>[ 5.162099] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10818 10:03:44.349993 <6>[ 5.166624] 9pnet: Installing 9P2000 support
10819 10:03:44.353525 <6>[ 5.172393] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10820 10:03:44.360347 <5>[ 5.176326] Key type dns_resolver registered
10821 10:03:44.366992 <6>[ 5.182082] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10822 10:03:44.370259 <6>[ 5.186598] registered taskstats version 1
10823 10:03:44.373362 <5>[ 5.196944] Loading compiled-in X.509 certificates
10824 10:03:44.402863 <4>[ 5.218720] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10825 10:03:44.412655 <4>[ 5.229420] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10826 10:03:44.419842 <3>[ 5.239947] debugfs: File 'uA_load' in directory '/' already present!
10827 10:03:44.425866 <3>[ 5.246647] debugfs: File 'min_uV' in directory '/' already present!
10828 10:03:44.433054 <3>[ 5.253260] debugfs: File 'max_uV' in directory '/' already present!
10829 10:03:44.439523 <3>[ 5.259923] debugfs: File 'constraint_flags' in directory '/' already present!
10830 10:03:44.450187 <3>[ 5.269515] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10831 10:03:44.463025 <6>[ 5.285498] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10832 10:03:44.470518 <6>[ 5.292348] xhci-mtk 11200000.usb: xHCI Host Controller
10833 10:03:44.476301 <6>[ 5.297862] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10834 10:03:44.486697 <6>[ 5.305804] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10835 10:03:44.493208 <6>[ 5.315240] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10836 10:03:44.500246 <6>[ 5.321329] xhci-mtk 11200000.usb: xHCI Host Controller
10837 10:03:44.506666 <6>[ 5.326810] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10838 10:03:44.512726 <6>[ 5.334460] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10839 10:03:44.520183 <6>[ 5.342226] hub 1-0:1.0: USB hub found
10840 10:03:44.523145 <6>[ 5.346256] hub 1-0:1.0: 1 port detected
10841 10:03:44.533630 <6>[ 5.350561] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10842 10:03:44.536619 <6>[ 5.359286] hub 2-0:1.0: USB hub found
10843 10:03:44.539480 <6>[ 5.363310] hub 2-0:1.0: 1 port detected
10844 10:03:44.547986 <6>[ 5.370383] mtk-msdc 11f70000.mmc: Got CD GPIO
10845 10:03:44.559401 <6>[ 5.377966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10846 10:03:44.565434 <6>[ 5.386013] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10847 10:03:44.575444 <4>[ 5.393994] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10848 10:03:44.584987 <6>[ 5.403539] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10849 10:03:44.591716 <6>[ 5.411618] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10850 10:03:44.598157 <6>[ 5.419631] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10851 10:03:44.608311 <6>[ 5.427550] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10852 10:03:44.614603 <6>[ 5.435366] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10853 10:03:44.624843 <6>[ 5.443183] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10854 10:03:44.634883 <6>[ 5.453613] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10855 10:03:44.641293 <6>[ 5.461978] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10856 10:03:44.651335 <6>[ 5.470327] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10857 10:03:44.658437 <6>[ 5.478667] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10858 10:03:44.668253 <6>[ 5.487005] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10859 10:03:44.677544 <6>[ 5.495344] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10860 10:03:44.684455 <6>[ 5.503682] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10861 10:03:44.694232 <6>[ 5.512019] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10862 10:03:44.700762 <6>[ 5.520357] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10863 10:03:44.710645 <6>[ 5.528696] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10864 10:03:44.717220 <6>[ 5.537033] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10865 10:03:44.727482 <6>[ 5.545371] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10866 10:03:44.733777 <6>[ 5.553708] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10867 10:03:44.744010 <6>[ 5.562046] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10868 10:03:44.750381 <6>[ 5.570383] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10869 10:03:44.756799 <6>[ 5.579188] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10870 10:03:44.764099 <6>[ 5.586347] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10871 10:03:44.770450 <6>[ 5.593082] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10872 10:03:44.780487 <6>[ 5.599841] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10873 10:03:44.787314 <6>[ 5.606777] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10874 10:03:44.793939 <6>[ 5.613628] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10875 10:03:44.803850 <6>[ 5.622765] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10876 10:03:44.813906 <6>[ 5.631885] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10877 10:03:44.823315 <6>[ 5.641179] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10878 10:03:44.833888 <6>[ 5.650648] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10879 10:03:44.840060 <6>[ 5.660116] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10880 10:03:44.850395 <6>[ 5.669236] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10881 10:03:44.860276 <6>[ 5.678705] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10882 10:03:44.869825 <6>[ 5.687824] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10883 10:03:44.879770 <6>[ 5.697119] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10884 10:03:44.889862 <6>[ 5.707278] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10885 10:03:44.899539 <6>[ 5.718945] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10886 10:03:44.930980 <6>[ 5.750141] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10887 10:03:44.959293 <6>[ 5.781464] hub 2-1:1.0: USB hub found
10888 10:03:44.962758 <6>[ 5.785926] hub 2-1:1.0: 3 ports detected
10889 10:03:45.083109 <6>[ 5.902091] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10890 10:03:45.237696 <6>[ 6.060017] hub 1-1:1.0: USB hub found
10891 10:03:45.240853 <6>[ 6.064468] hub 1-1:1.0: 4 ports detected
10892 10:03:45.315272 <6>[ 6.134347] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10893 10:03:45.562811 <6>[ 6.382126] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10894 10:03:45.695767 <6>[ 6.517753] hub 1-1.4:1.0: USB hub found
10895 10:03:45.698533 <6>[ 6.522424] hub 1-1.4:1.0: 2 ports detected
10896 10:03:45.994884 <6>[ 6.814098] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10897 10:03:46.187248 <6>[ 7.006098] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10898 10:03:57.172127 <6>[ 17.999090] ALSA device list:
10899 10:03:57.178324 <6>[ 18.002381] No soundcards found.
10900 10:03:57.186464 <6>[ 18.010396] Freeing unused kernel memory: 8384K
10901 10:03:57.189858 <6>[ 18.015431] Run /init as init process
10902 10:03:57.235978 <6>[ 18.059443] NET: Registered PF_INET6 protocol family
10903 10:03:57.242100 <6>[ 18.065755] Segment Routing with IPv6
10904 10:03:57.245614 <6>[ 18.069702] In-situ OAM (IOAM) with IPv6
10905 10:03:57.279293 <30>[ 18.083260] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10906 10:03:57.282557 <30>[ 18.106987] systemd[1]: Detected architecture arm64.
10907 10:03:57.283267
10908 10:03:57.289166 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10909 10:03:57.289741
10910 10:03:57.302493 <30>[ 18.126079] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10911 10:03:57.467688 <30>[ 18.288248] systemd[1]: Queued start job for default target Graphical Interface.
10912 10:03:57.507409 <30>[ 18.331157] systemd[1]: Created slice system-getty.slice.
10913 10:03:57.513946 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10914 10:03:57.531163 <30>[ 18.354699] systemd[1]: Created slice system-modprobe.slice.
10915 10:03:57.537608 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10916 10:03:57.555097 <30>[ 18.378650] systemd[1]: Created slice system-serial\x2dgetty.slice.
10917 10:03:57.564662 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10918 10:03:57.579556 <30>[ 18.403520] systemd[1]: Created slice User and Session Slice.
10919 10:03:57.586213 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10920 10:03:57.606332 <30>[ 18.426811] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10921 10:03:57.616118 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10922 10:03:57.634250 <30>[ 18.454864] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10923 10:03:57.640624 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10924 10:03:57.664954 <30>[ 18.482582] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10925 10:03:57.671874 <30>[ 18.494883] systemd[1]: Reached target Local Encrypted Volumes.
10926 10:03:57.678299 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10927 10:03:57.694630 <30>[ 18.518605] systemd[1]: Reached target Paths.
10928 10:03:57.698100 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10929 10:03:57.713963 <30>[ 18.538089] systemd[1]: Reached target Remote File Systems.
10930 10:03:57.720361 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10931 10:03:57.734423 <30>[ 18.558061] systemd[1]: Reached target Slices.
10932 10:03:57.737763 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10933 10:03:57.754520 <30>[ 18.578103] systemd[1]: Reached target Swap.
10934 10:03:57.757149 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10935 10:03:57.778200 <30>[ 18.598577] systemd[1]: Listening on initctl Compatibility Named Pipe.
10936 10:03:57.784659 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10937 10:03:57.799631 <30>[ 18.623535] systemd[1]: Listening on Journal Audit Socket.
10938 10:03:57.805845 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10939 10:03:57.823500 <30>[ 18.647231] systemd[1]: Listening on Journal Socket (/dev/log).
10940 10:03:57.830089 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10941 10:03:57.847283 <30>[ 18.671284] systemd[1]: Listening on Journal Socket.
10942 10:03:57.853758 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10943 10:03:57.866668 <30>[ 18.690648] systemd[1]: Listening on udev Control Socket.
10944 10:03:57.873291 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10945 10:03:57.891164 <30>[ 18.715142] systemd[1]: Listening on udev Kernel Socket.
10946 10:03:57.897646 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10947 10:03:57.954341 <30>[ 18.778288] systemd[1]: Mounting Huge Pages File System...
10948 10:03:57.960818 Mounting [0;1;39mHuge Pages File System[0m...
10949 10:03:57.978221 <30>[ 18.802046] systemd[1]: Mounting POSIX Message Queue File System...
10950 10:03:57.984666 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10951 10:03:58.014461 <30>[ 18.838129] systemd[1]: Mounting Kernel Debug File System...
10952 10:03:58.020856 Mounting [0;1;39mKernel Debug File System[0m...
10953 10:03:58.037257 <30>[ 18.858495] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10954 10:03:58.050402 <30>[ 18.871372] systemd[1]: Starting Create list of static device nodes for the current kernel...
10955 10:03:58.056543 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10956 10:03:58.077704 <30>[ 18.902357] systemd[1]: Starting Load Kernel Module configfs...
10957 10:03:58.084307 Starting [0;1;39mLoad Kernel Module configfs[0m...
10958 10:03:58.101510 <30>[ 18.926060] systemd[1]: Starting Load Kernel Module drm...
10959 10:03:58.108221 Starting [0;1;39mLoad Kernel Module drm[0m...
10960 10:03:58.124743 <30>[ 18.946163] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10961 10:03:58.166133 <30>[ 18.990732] systemd[1]: Starting Journal Service...
10962 10:03:58.169256 Starting [0;1;39mJournal Service[0m...
10963 10:03:58.188749 <30>[ 19.012986] systemd[1]: Starting Load Kernel Modules...
10964 10:03:58.194786 Starting [0;1;39mLoad Kernel Modules[0m...
10965 10:03:58.215830 <30>[ 19.036699] systemd[1]: Starting Remount Root and Kernel File Systems...
10966 10:03:58.222481 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10967 10:03:58.237287 <30>[ 19.061076] systemd[1]: Starting Coldplug All udev Devices...
10968 10:03:58.243435 Starting [0;1;39mColdplug All udev Devices[0m...
10969 10:03:58.260905 <30>[ 19.084969] systemd[1]: Started Journal Service.
10970 10:03:58.267608 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10971 10:03:58.284610 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10972 10:03:58.302481 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10973 10:03:58.319186 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10974 10:03:58.338758 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10975 10:03:58.360442 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10976 10:03:58.380072 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10977 10:03:58.396150 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10978 10:03:58.415704 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10979 10:03:58.430416 See 'systemctl status systemd-remount-fs.service' for details.
10980 10:03:58.486655 Mounting [0;1;39mKernel Configuration File System[0m...
10981 10:03:58.506633 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10982 10:03:58.519256 <46>[ 19.340372] systemd-journald[182]: Received client request to flush runtime journal.
10983 10:03:58.530596 Starting [0;1;39mLoad/Save Random Seed[0m...
10984 10:03:58.549752 Starting [0;1;39mApply Kernel Variables[0m...
10985 10:03:58.570977 Starting [0;1;39mCreate System Users[0m...
10986 10:03:58.595716 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10987 10:03:58.615204 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10988 10:03:58.639153 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10989 10:03:58.655886 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10990 10:03:58.672098 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10991 10:03:58.687975 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10992 10:03:58.735037 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10993 10:03:58.756396 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10994 10:03:58.770503 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10995 10:03:58.790538 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10996 10:03:58.831319 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10997 10:03:58.858912 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10998 10:03:58.879318 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10999 10:03:58.900632 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11000 10:03:58.943258 Starting [0;1;39mNetwork Time Synchronization[0m...
11001 10:03:58.965169 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11002 10:03:59.016572 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11003 10:03:59.034187 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11004 10:03:59.064112 <6>[ 19.884692] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11005 10:03:59.074148 <6>[ 19.892913] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11006 10:03:59.083842 <6>[ 19.902389] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11007 10:03:59.090441 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11008 10:03:59.109862 [[0;32m OK [0m] Reached targ<6>[ 19.932675] usbcore: registered new interface driver r8152
11009 10:03:59.112873 et [0;1;39mSystem Time Set[0m.
11010 10:03:59.124507 <3>[ 19.945023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11011 10:03:59.131184 <3>[ 19.953305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11012 10:03:59.140513 <3>[ 19.961452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11013 10:03:59.147732 <6>[ 19.964872] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11014 10:03:59.154051 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11015 10:03:59.163645 <3>[ 19.982792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11016 10:03:59.167003 <6>[ 19.983554] remoteproc remoteproc0: scp is available
11017 10:03:59.176980 <3>[ 19.991919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11018 10:03:59.183430 <3>[ 19.991926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11019 10:03:59.190474 <6>[ 19.997411] remoteproc remoteproc0: powering up scp
11020 10:03:59.196673 <3>[ 20.005293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11021 10:03:59.203772 <6>[ 20.012351] usbcore: registered new interface driver cdc_ether
11022 10:03:59.213715 <6>[ 20.013394] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11023 10:03:59.220272 <3>[ 20.018507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11024 10:03:59.226900 <6>[ 20.026636] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11025 10:03:59.233441 <3>[ 20.041969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11026 10:03:59.240190 <6>[ 20.042992] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11027 10:03:59.246887 <6>[ 20.044368] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11028 10:03:59.253508 <6>[ 20.044382] pci_bus 0000:00: root bus resource [bus 00-ff]
11029 10:03:59.260392 <6>[ 20.044389] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11030 10:03:59.269724 <6>[ 20.044395] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11031 10:03:59.276680 <6>[ 20.044434] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11032 10:03:59.286618 <6>[ 20.044448] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11033 10:03:59.289961 <6>[ 20.044530] pci 0000:00:00.0: supports D1 D2
11034 10:03:59.296134 <6>[ 20.044533] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11035 10:03:59.299526 <6>[ 20.051617] mc: Linux media interface: v0.10
11036 10:03:59.302739 <6>[ 20.055554] Bluetooth: Core ver 2.22
11037 10:03:59.312713 <3>[ 20.057911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11038 10:03:59.319754 <3>[ 20.057937] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11039 10:03:59.329719 <3>[ 20.057943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11040 10:03:59.337100 <6>[ 20.059137] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11041 10:03:59.345685 <3>[ 20.059385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11042 10:03:59.352292 <3>[ 20.059391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11043 10:03:59.362857 <3>[ 20.059394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11044 10:03:59.368551 <3>[ 20.059398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11045 10:03:59.378931 <3>[ 20.059400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11046 10:03:59.385300 <3>[ 20.059422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11047 10:03:59.391655 <6>[ 20.061573] usbcore: registered new interface driver r8153_ecm
11048 10:03:59.398764 <6>[ 20.065498] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11049 10:03:59.401728 <6>[ 20.070864] NET: Registered PF_BLUETOOTH protocol family
11050 10:03:59.411475 <4>[ 20.075434] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11051 10:03:59.418240 <4>[ 20.076130] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11052 10:03:59.425052 <6>[ 20.077212] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11053 10:03:59.431498 <6>[ 20.082925] Bluetooth: HCI device and connection manager initialized
11054 10:03:59.441493 <4>[ 20.089612] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11055 10:03:59.448588 <4>[ 20.089619] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11056 10:03:59.457815 <6>[ 20.090121] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11057 10:03:59.461847 <6>[ 20.092406] videodev: Linux video capture interface: v2.00
11058 10:03:59.467875 <6>[ 20.100010] Bluetooth: HCI socket layer initialized
11059 10:03:59.474790 <6>[ 20.106300] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11060 10:03:59.481625 <6>[ 20.106474] pci 0000:01:00.0: supports D1 D2
11061 10:03:59.484665 <6>[ 20.113897] Bluetooth: L2CAP socket layer initialized
11062 10:03:59.490837 <6>[ 20.118607] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11063 10:03:59.497897 <6>[ 20.125709] Bluetooth: SCO socket layer initialized
11064 10:03:59.504489 <6>[ 20.146002] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11065 10:03:59.510948 <6>[ 20.170996] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11066 10:03:59.520673 <6>[ 20.174286] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11067 10:03:59.527733 <6>[ 20.174690] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11068 10:03:59.534350 <6>[ 20.174701] remoteproc remoteproc0: remote processor scp is now up
11069 10:03:59.540547 <6>[ 20.174699] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11070 10:03:59.550868 <6>[ 20.182271] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11071 10:03:59.553842 <6>[ 20.193768] r8152 2-1.3:1.0 eth0: v1.12.13
11072 10:03:59.564744 <6>[ 20.199260] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11073 10:03:59.573458 <6>[ 20.266742] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11074 10:03:59.580481 <6>[ 20.270352] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11075 10:03:59.590313 <6>[ 20.271716] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11076 10:03:59.596859 <6>[ 20.272785] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
11077 10:03:59.603480 <6>[ 20.273133] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11078 10:03:59.613358 <6>[ 20.278853] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11079 10:03:59.620725 <6>[ 20.285895] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11080 10:03:59.630292 <6>[ 20.285910] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11081 10:03:59.633424 <6>[ 20.285924] pci 0000:00:00.0: PCI bridge to [bus 01]
11082 10:03:59.643609 <6>[ 20.285932] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11083 10:03:59.650243 <6>[ 20.286198] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11084 10:03:59.658011 <6>[ 20.335343] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11085 10:03:59.660955 <6>[ 20.341559] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11086 10:03:59.667732 <6>[ 20.341645] usbcore: registered new interface driver btusb
11087 10:03:59.679172 <4>[ 20.343664] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11088 10:03:59.682895 <3>[ 20.343685] Bluetooth: hci0: Failed to load firmware file (-2)
11089 10:03:59.689709 <3>[ 20.343690] Bluetooth: hci0: Failed to set up firmware (-2)
11090 10:03:59.700203 <4>[ 20.343696] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11091 10:03:59.713436 <6>[ 20.350620] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11092 10:03:59.720090 <6>[ 20.358627] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11093 10:03:59.726585 <6>[ 20.358908] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11094 10:03:59.730071 <6>[ 20.364246] usbcore: registered new interface driver uvcvideo
11095 10:03:59.740275 <5>[ 20.386428] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11096 10:03:59.749996 <4>[ 20.411078] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11097 10:03:59.753407 <4>[ 20.411078] Fallback method does not support PEC.
11098 10:03:59.763242 <3>[ 20.443934] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11099 10:03:59.769565 <3>[ 20.444662] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11100 10:03:59.776628 <5>[ 20.451637] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11101 10:03:59.786309 <3>[ 20.498656] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11102 10:03:59.793129 <3>[ 20.504843] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11103 10:03:59.802780 <3>[ 20.505662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11104 10:03:59.812893 <4>[ 20.507298] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11105 10:03:59.820025 <3>[ 20.529727] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11106 10:03:59.826672 <6>[ 20.542034] cfg80211: failed to load regulatory.db
11107 10:03:59.833783 <6>[ 20.595460] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11108 10:03:59.840360 <3>[ 20.620102] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11109 10:03:59.847295 <6>[ 20.623177] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11110 10:03:59.856507 <3>[ 20.652053] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11111 10:03:59.863542 <6>[ 20.674883] mt7921e 0000:01:00.0: ASIC revision: 79610010
11112 10:03:59.869933 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11113 10:03:59.880990 <3>[ 20.701823] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11114 10:03:59.892021 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11115 10:03:59.913503 <3>[ 20.734383] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11116 10:03:59.920233 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11117 10:03:59.969171 <4>[ 20.786562] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11118 10:04:00.062077 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11119 10:04:00.092726 [[0;32m OK [0m] Reached target [0;1;39mSystem Initializatio<4>[ 20.908364] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11120 10:04:00.093301 n[0m.
11121 10:04:00.110664 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11122 10:04:00.129718 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11123 10:04:00.142356 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11124 10:04:00.165875 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11125 10:04:00.178466 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11126 10:04:00.194655 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11127 10:04:00.210806 <4>[ 21.028291] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11128 10:04:00.220070 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11129 10:04:00.290050 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11130 10:04:00.330632 <4>[ 21.148618] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11131 10:04:00.343566 Starting [0;1;39mUser Login Management[0m...
11132 10:04:00.363435 Starting [0;1;39mPermit User Sessions[0m...
11133 10:04:00.382316 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11134 10:04:00.450800 <4>[ 21.268523] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11135 10:04:00.457188 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11136 10:04:00.476224 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11137 10:04:00.494276 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11138 10:04:00.514277 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11139 10:04:00.535299 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11140 10:04:00.556550 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11141 10:04:00.570952 <4>[ 21.388704] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11142 10:04:00.577480 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11143 10:04:00.599173 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11144 10:04:00.654382 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11145 10:04:00.691230 <4>[ 21.509004] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11146 10:04:00.697856 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11147 10:04:00.735404
11148 10:04:00.736001
11149 10:04:00.738980 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11150 10:04:00.739545
11151 10:04:00.742141 debian-bullseye-arm64 login: root (automatic login)
11152 10:04:00.742702
11153 10:04:00.743067
11154 10:04:00.759247 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Wed Aug 23 09:52:58 UTC 2023 aarch64
11155 10:04:00.759810
11156 10:04:00.765657 The programs included with the Debian GNU/Linux system are free software;
11157 10:04:00.771696 the exact distribution terms for each program are described in the
11158 10:04:00.775715 individual files in /usr/share/doc/*/copyright.
11159 10:04:00.776370
11160 10:04:00.782117 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11161 10:04:00.785736 permitted by applicable law.
11162 10:04:00.787003 Matched prompt #10: / #
11164 10:04:00.788230 Setting prompt string to ['/ #']
11165 10:04:00.788715 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11167 10:04:00.789804 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11168 10:04:00.790350 start: 2.2.6 expect-shell-connection (timeout 00:01:42) [common]
11169 10:04:00.790745 Setting prompt string to ['/ #']
11170 10:04:00.791088 Forcing a shell prompt, looking for ['/ #']
11172 10:04:00.841946 / #
11173 10:04:00.842603 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11174 10:04:00.843030 Waiting using forced prompt support (timeout 00:02:30)
11175 10:04:00.843545 <4>[ 21.628893] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11176 10:04:00.848441
11177 10:04:00.849377 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11178 10:04:00.849895 start: 2.2.7 export-device-env (timeout 00:01:42) [common]
11179 10:04:00.850410 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11180 10:04:00.850925 end: 2.2 depthcharge-retry (duration 00:03:18) [common]
11181 10:04:00.851432 end: 2 depthcharge-action (duration 00:03:18) [common]
11182 10:04:00.851875 start: 3 lava-test-retry (timeout 00:05:00) [common]
11183 10:04:00.852348 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11184 10:04:00.852710 Using namespace: common
11186 10:04:00.953966 / # #
11187 10:04:00.954604 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11188 10:04:00.955213 #<4>[ 21.752245] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11189 10:04:00.960112
11190 10:04:00.960826 Using /lava-11336450
11192 10:04:01.062258 / # export SHELL=/bin/sh
11193 10:04:01.063040 export SHELL=/bin/sh<4>[ 21.872754] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11194 10:04:01.068749
11196 10:04:01.213898 / # . /lava-11336450/environment
11197 10:04:01.214753 <3>[ 21.989872] mt7921e 0000:01:00.0: hardware init failed
11198 10:04:01.220748 . /lava-11336450/environment
11200 10:04:01.322566 / # /lava-11336450/bin/lava-test-runner /lava-11336450/0
11201 10:04:01.323200 Test shell timeout: 10s (minimum of the action and connection timeout)
11202 10:04:01.329431 /lava-11336450/bin/lava-test-runner /lava-11336450/0
11203 10:04:01.349086 + export TESTRUN_ID=0_sleep
11204 10:04:01.352717 + cd /lava-11336450/0/tests/0_sleep
11205 10:04:01.355937 + cat uuid
11206 10:04:01.356523 + UUID=11336450_1.5.2.3.1
11207 10:04:01.356939 + set +x
11208 10:04:01.362437 <LAVA_SIGNAL_STARTRUN 0_sleep 11336450_1.5.2.3.1>
11209 10:04:01.363333 Received signal: <STARTRUN> 0_sleep 11336450_1.5.2.3.1
11210 10:04:01.363739 Starting test lava.0_sleep (11336450_1.5.2.3.1)
11211 10:04:01.364241 Skipping test definition patterns.
11212 10:04:01.365561 + ./config/lava/sleep/sleep.sh mem freeze
11213 10:04:01.369721 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11215 10:04:01.372257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11216 10:04:01.375592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11217 10:04:01.376373 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11219 10:04:01.379198 rtcwake: assuming RTC uses UTC ...
11220 10:04:01.388696 rtcwake: wakeup from "mem" using rtc0 at Wed<6>[ 22.212798] PM: suspend entry (deep)
11221 10:04:01.392168 Aug 23 10:04:08<6>[ 22.216852] Filesystems sync: 0.000 seconds
11222 10:04:01.395374 2023
11223 10:04:01.398429 <6>[ 22.224634] Freezing user space processes
11224 10:04:01.409372 <6>[ 22.230526] Freezing user space processes completed (elapsed 0.001 seconds)
11225 10:04:01.412920 <6>[ 22.237745] OOM killer disabled.
11226 10:04:01.415793 <6>[ 22.241229] Freezing remaining freezable tasks
11227 10:04:01.426306 <6>[ 22.247281] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11228 10:04:01.433372 <6>[ 22.254958] printk: Suspending console(s) (use no_console_suspend to debug)
11229 10:04:04.827315 <3>[ 25.422156] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11230 10:04:04.837125 <3>[ 25.422197] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11231 10:04:04.847224 <3>[ 25.422244] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11232 10:04:04.853626 <3>[ 25.422281] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11233 10:04:04.864083 <3>[ 25.422845] PM: Some devices failed to suspend, or early wake event detected
11234 10:04:04.870440 <4>[ 25.439064] typec port0-partner: PM: parent port0 should not be sleeping
11235 10:04:04.873228 <6>[ 25.698852] OOM killer enabled.
11236 10:04:04.877384 <6>[ 25.702263] Restarting tasks ... done.
11237 10:04:04.885094 <5>[ 25.709484] random: crng reseeded on system resumption
11238 10:04:04.887852 <6>[ 25.716150] PM: suspend exit
11239 10:04:04.891203 rtcwake: write error
11240 10:04:04.898770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11241 10:04:04.899614 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11243 10:04:04.901824 rtcwake: assuming RTC uses UTC ...
11244 10:04:04.909139 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 23 10:04:11 2023
11245 10:04:04.920820 <6>[ 25.745639] PM: suspend entry (deep)
11246 10:04:04.923947 <6>[ 25.749527] Filesystems sync: 0.000 seconds
11247 10:04:04.927228 <6>[ 25.754533] Freezing user space processes
11248 10:04:04.938983 <6>[ 25.760555] Freezing user space processes completed (elapsed 0.001 seconds)
11249 10:04:04.942362 <6>[ 25.767796] OOM killer disabled.
11250 10:04:04.945770 <6>[ 25.771279] Freezing remaining freezable tasks
11251 10:04:04.955848 <6>[ 25.777232] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11252 10:04:04.962074 <6>[ 25.784887] printk: Suspending console(s) (use no_console_suspend to debug)
11253 10:04:08.407296 <3>[ 29.006131] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11254 10:04:08.416637 <3>[ 29.006167] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11255 10:04:08.427362 <3>[ 29.006217] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11256 10:04:08.433984 <3>[ 29.006260] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11257 10:04:08.439688 <3>[ 29.006645] PM: Some devices failed to suspend, or early wake event detected
11258 10:04:08.446573 <6>[ 29.271940] OOM killer enabled.
11259 10:04:08.453547 <6>[ 29.275357] Restarting tasks ... done.
11260 10:04:08.456437 <5>[ 29.282748] random: crng reseeded on system resumption
11261 10:04:08.460896 <6>[ 29.289517] PM: suspend exit
11262 10:04:08.464104 rtcwake: write error
11263 10:04:08.471687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11264 10:04:08.472626 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11266 10:04:08.474495 rtcwake: assuming RTC uses UTC ...
11267 10:04:08.481238 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 23 10:04:15 2023
11268 10:04:08.493848 <6>[ 29.318704] PM: suspend entry (deep)
11269 10:04:08.496726 <6>[ 29.322587] Filesystems sync: 0.000 seconds
11270 10:04:08.500067 <6>[ 29.327620] Freezing user space processes
11271 10:04:08.511643 <6>[ 29.333464] Freezing user space processes completed (elapsed 0.001 seconds)
11272 10:04:08.515082 <6>[ 29.340683] OOM killer disabled.
11273 10:04:08.518638 <6>[ 29.344163] Freezing remaining freezable tasks
11274 10:04:08.528034 <6>[ 29.349831] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11275 10:04:08.534855 <6>[ 29.357481] printk: Suspending console(s) (use no_console_suspend to debug)
11276 10:04:11.998705 <3>[ 32.590117] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11277 10:04:12.008270 <3>[ 32.590146] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11278 10:04:12.018458 <3>[ 32.590187] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11279 10:04:12.025488 <3>[ 32.590224] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11280 10:04:12.032076 <3>[ 32.590519] PM: Some devices failed to suspend, or early wake event detected
11281 10:04:12.038529 <6>[ 32.864015] OOM killer enabled.
11282 10:04:12.041944 <6>[ 32.867426] Restarting tasks ... done.
11283 10:04:12.049291 <5>[ 32.875035] random: crng reseeded on system resumption
11284 10:04:12.053092 <6>[ 32.881698] PM: suspend exit
11285 10:04:12.056325 rtcwake: write error
11286 10:04:12.065868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11287 10:04:12.066720 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11289 10:04:12.068962 rtcwake: assuming RTC uses UTC ...
11290 10:04:12.075654 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 23 10:04:19 2023
11291 10:04:12.090477 <6>[ 32.915850] PM: suspend entry (deep)
11292 10:04:12.093456 <6>[ 32.919820] Filesystems sync: 0.000 seconds
11293 10:04:12.100133 <6>[ 32.924992] Freezing user space processes
11294 10:04:12.107282 <6>[ 32.931142] Freezing user space processes completed (elapsed 0.001 seconds)
11295 10:04:12.110198 <6>[ 32.938386] OOM killer disabled.
11296 10:04:12.116681 <6>[ 32.941874] Freezing remaining freezable tasks
11297 10:04:12.123381 <6>[ 32.947816] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11298 10:04:12.133580 <6>[ 32.955479] printk: Suspending console(s) (use no_console_suspend to debug)
11299 10:04:15.582223 <3>[ 36.174084] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11300 10:04:15.591462 <3>[ 36.174109] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11301 10:04:15.601610 <3>[ 36.174141] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11302 10:04:15.608523 <3>[ 36.174170] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11303 10:04:15.618153 <3>[ 36.174396] PM: Some devices failed to suspend, or early wake event detected
11304 10:04:15.622198 <6>[ 36.447804] OOM killer enabled.
11305 10:04:15.625592 <6>[ 36.451218] Restarting tasks ... done.
11306 10:04:15.632281 <5>[ 36.457404] random: crng reseeded on system resumption
11307 10:04:15.635158 <6>[ 36.464162] PM: suspend exit
11308 10:04:15.638136 rtcwake: write error
11309 10:04:15.645545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11310 10:04:15.646394 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11312 10:04:15.648734 rtcwake: assuming RTC uses UTC ...
11313 10:04:15.655249 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 23 10:04:22 2023
11314 10:04:15.667578 <6>[ 36.493436] PM: suspend entry (deep)
11315 10:04:15.670932 <6>[ 36.497323] Filesystems sync: 0.000 seconds
11316 10:04:15.677436 <6>[ 36.502422] Freezing user space processes
11317 10:04:15.685021 <6>[ 36.508427] Freezing user space processes completed (elapsed 0.001 seconds)
11318 10:04:15.687184 <6>[ 36.515657] OOM killer disabled.
11319 10:04:15.693822 <6>[ 36.519137] Freezing remaining freezable tasks
11320 10:04:15.700127 <6>[ 36.525202] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11321 10:04:15.710380 <6>[ 36.532875] printk: Suspending console(s) (use no_console_suspend to debug)
11322 10:04:19.165640 <3>[ 39.758106] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11323 10:04:19.178754 <3>[ 39.758137] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11324 10:04:19.185060 <3>[ 39.758181] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11325 10:04:19.192235 <3>[ 39.758220] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11326 10:04:19.201976 <3>[ 39.758460] PM: Some devices failed to suspend, or early wake event detected
11327 10:04:19.205128 <6>[ 40.031971] OOM killer enabled.
11328 10:04:19.208184 <6>[ 40.035381] Restarting tasks ... done.
11329 10:04:19.216508 <5>[ 40.042904] random: crng reseeded on system resumption
11330 10:04:19.219989 <6>[ 40.049530] PM: suspend exit
11331 10:04:19.222966 rtcwake: write error
11332 10:04:19.230498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11333 10:04:19.231351 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11335 10:04:19.233248 rtcwake: assuming RTC uses UTC ...
11336 10:04:19.240056 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 23 10:04:26 2023
11337 10:04:19.252532 <6>[ 40.078685] PM: suspend entry (deep)
11338 10:04:19.256074 <6>[ 40.082586] Filesystems sync: 0.000 seconds
11339 10:04:19.258852 <6>[ 40.087610] Freezing user space processes
11340 10:04:19.270567 <6>[ 40.093454] Freezing user space processes completed (elapsed 0.001 seconds)
11341 10:04:19.273563 <6>[ 40.100673] OOM killer disabled.
11342 10:04:19.276798 <6>[ 40.104154] Freezing remaining freezable tasks
11343 10:04:19.286957 <6>[ 40.109828] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11344 10:04:19.293765 <6>[ 40.117478] printk: Suspending console(s) (use no_console_suspend to debug)
11345 10:04:22.749383 <3>[ 43.342136] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11346 10:04:22.759828 <3>[ 43.342166] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11347 10:04:22.769167 <3>[ 43.342209] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11348 10:04:22.776279 <3>[ 43.342249] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11349 10:04:22.782725 <3>[ 43.342563] PM: Some devices failed to suspend, or early wake event detected
11350 10:04:22.789554 <6>[ 43.616220] OOM killer enabled.
11351 10:04:22.792663 <6>[ 43.619630] Restarting tasks ... done.
11352 10:04:22.799586 <5>[ 43.625857] random: crng reseeded on system resumption
11353 10:04:22.803402 <6>[ 43.633426] PM: suspend exit
11354 10:04:22.806612 rtcwake: write error
11355 10:04:22.816078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11356 10:04:22.816925 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11358 10:04:22.818595 rtcwake: assuming RTC uses UTC ...
11359 10:04:22.825188 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 23 10:04:29 2023
11360 10:04:22.837736 <6>[ 43.664763] PM: suspend entry (deep)
11361 10:04:22.841374 <6>[ 43.668667] Filesystems sync: 0.000 seconds
11362 10:04:22.844847 <6>[ 43.673720] Freezing user space processes
11363 10:04:22.856065 <6>[ 43.679610] Freezing user space processes completed (elapsed 0.001 seconds)
11364 10:04:22.859529 <6>[ 43.686835] OOM killer disabled.
11365 10:04:22.862924 <6>[ 43.690316] Freezing remaining freezable tasks
11366 10:04:22.873206 <6>[ 43.696180] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11367 10:04:22.879193 <6>[ 43.703829] printk: Suspending console(s) (use no_console_suspend to debug)
11368 10:04:26.328422 <3>[ 46.926107] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11369 10:04:26.338596 <3>[ 46.926137] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11370 10:04:26.348225 <3>[ 46.926180] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11371 10:04:26.354794 <3>[ 46.926220] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11372 10:04:26.364728 <3>[ 46.926518] PM: Some devices failed to suspend, or early wake event detected
11373 10:04:26.368306 <6>[ 47.196218] OOM killer enabled.
11374 10:04:26.371863 <6>[ 47.199629] Restarting tasks ... done.
11375 10:04:26.378204 <5>[ 47.205669] random: crng reseeded on system resumption
11376 10:04:26.381388 <6>[ 47.212340] PM: suspend exit
11377 10:04:26.385220 rtcwake: write error
11378 10:04:26.391584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11379 10:04:26.391847 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11381 10:04:26.394813 rtcwake: assuming RTC uses UTC ...
11382 10:04:26.401391 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 23 10:04:33 2023
11383 10:04:26.414000 <6>[ 47.241895] PM: suspend entry (deep)
11384 10:04:26.417472 <6>[ 47.245773] Filesystems sync: 0.000 seconds
11385 10:04:26.420949 <6>[ 47.250795] Freezing user space processes
11386 10:04:26.432287 <6>[ 47.256804] Freezing user space processes completed (elapsed 0.001 seconds)
11387 10:04:26.435740 <6>[ 47.264041] OOM killer disabled.
11388 10:04:26.438738 <6>[ 47.267523] Freezing remaining freezable tasks
11389 10:04:26.449294 <6>[ 47.273537] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11390 10:04:26.456069 <6>[ 47.281212] printk: Suspending console(s) (use no_console_suspend to debug)
11391 10:04:29.908565 <6>[ 48.206284] vpu: disabling
11392 10:04:29.912160 <6>[ 48.206462] vproc2: disabling
11393 10:04:29.915168 <6>[ 48.206517] vproc1: disabling
11394 10:04:29.918828 <6>[ 48.206572] vaud18: disabling
11395 10:04:29.922079 <6>[ 48.206820] vsram_others: disabling
11396 10:04:29.925185 <6>[ 48.207018] va09: disabling
11397 10:04:29.928494 <6>[ 48.207096] vsram_md: disabling
11398 10:04:29.932039 <6>[ 48.207224] Vgpu: disabling
11399 10:04:29.938946 <3>[ 50.510122] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11400 10:04:29.949169 <3>[ 50.510154] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11401 10:04:29.958591 <3>[ 50.510196] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11402 10:04:29.964928 <3>[ 50.510236] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11403 10:04:29.972263 <3>[ 50.510497] PM: Some devices failed to suspend, or early wake event detected
11404 10:04:29.975152 <6>[ 50.806106] OOM killer enabled.
11405 10:04:29.983093 <6>[ 50.809504] Restarting tasks ... done.
11406 10:04:29.986485 <5>[ 50.815316] random: crng reseeded on system resumption
11407 10:04:29.990815 <6>[ 50.821946] PM: suspend exit
11408 10:04:29.993423 rtcwake: write error
11409 10:04:30.000355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11410 10:04:30.000613 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11412 10:04:30.004130 rtcwake: assuming RTC uses UTC ...
11413 10:04:30.010629 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 23 10:04:37 2023
11414 10:04:30.022460 <6>[ 50.850931] PM: suspend entry (deep)
11415 10:04:30.025989 <6>[ 50.854825] Filesystems sync: 0.000 seconds
11416 10:04:30.029298 <6>[ 50.859901] Freezing user space processes
11417 10:04:30.040856 <6>[ 50.865768] Freezing user space processes completed (elapsed 0.001 seconds)
11418 10:04:30.044165 <6>[ 50.873007] OOM killer disabled.
11419 10:04:30.047280 <6>[ 50.876488] Freezing remaining freezable tasks
11420 10:04:30.057434 <6>[ 50.882385] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11421 10:04:30.064671 <6>[ 50.890037] printk: Suspending console(s) (use no_console_suspend to debug)
11422 10:04:33.499634 <3>[ 54.094142] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11423 10:04:33.513223 <3>[ 54.094173] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11424 10:04:33.519953 <3>[ 54.094217] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11425 10:04:33.526259 <3>[ 54.094256] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11426 10:04:33.533219 <3>[ 54.094497] PM: Some devices failed to suspend, or early wake event detected
11427 10:04:33.540245 <6>[ 54.368254] OOM killer enabled.
11428 10:04:33.543391 <6>[ 54.371664] Restarting tasks ... done.
11429 10:04:33.549680 <5>[ 54.377849] random: crng reseeded on system resumption
11430 10:04:33.553069 <6>[ 54.384539] PM: suspend exit
11431 10:04:33.556396 rtcwake: write error
11432 10:04:33.562984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11433 10:04:33.563272 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11435 10:04:33.566082 rtcwake: assuming RTC uses UTC ...
11436 10:04:33.573044 rtcwake: wakeup from "mem" using rtc0 at Wed Aug 23 10:04:40 2023
11437 10:04:33.585878 <6>[ 54.414043] PM: suspend entry (deep)
11438 10:04:33.588674 <6>[ 54.417994] Filesystems sync: 0.000 seconds
11439 10:04:33.596286 <6>[ 54.423038] Freezing user space processes
11440 10:04:33.601816 <6>[ 54.428944] Freezing user space processes completed (elapsed 0.001 seconds)
11441 10:04:33.605415 <6>[ 54.436172] OOM killer disabled.
11442 10:04:33.611893 <6>[ 54.439654] Freezing remaining freezable tasks
11443 10:04:33.618721 <6>[ 54.445699] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11444 10:04:33.628892 <6>[ 54.453376] printk: Suspending console(s) (use no_console_suspend to debug)
11445 10:04:37.075214 <3>[ 57.678104] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11446 10:04:37.088186 <3>[ 57.678135] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11447 10:04:37.094885 <3>[ 57.678178] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11448 10:04:37.101605 <3>[ 57.678218] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11449 10:04:37.111426 <3>[ 57.678459] PM: Some devices failed to suspend, or early wake event detected
11450 10:04:37.114792 <6>[ 57.944024] OOM killer enabled.
11451 10:04:37.125090 <6>[ 57.947436] Restarting tasks ... done.
11452 10:04:37.128344 <5>[ 57.958092] random: crng reseeded on system resumption
11453 10:04:37.133044 <6>[ 57.965122] PM: suspend exit
11454 10:04:37.136141 rtcwake: write error
11455 10:04:37.143418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11456 10:04:37.143732 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11458 10:04:37.146694 rtcwake: assuming RTC uses UTC ...
11459 10:04:37.153658 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:04:44 2023
11460 10:04:37.167196 <6>[ 57.995966] PM: suspend entry (s2idle)
11461 10:04:37.170136 <6>[ 58.000040] Filesystems sync: 0.000 seconds
11462 10:04:37.176790 <6>[ 58.005099] Freezing user space processes
11463 10:04:37.183322 <6>[ 58.011031] Freezing user space processes completed (elapsed 0.001 seconds)
11464 10:04:37.187281 <6>[ 58.018291] OOM killer disabled.
11465 10:04:37.193544 <6>[ 58.021769] Freezing remaining freezable tasks
11466 10:04:37.199942 <6>[ 58.027866] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11467 10:04:37.209988 <6>[ 58.035542] printk: Suspending console(s) (use no_console_suspend to debug)
11468 10:04:40.662494 <3>[ 61.262107] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11469 10:04:40.672696 <3>[ 61.262137] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11470 10:04:40.682861 <3>[ 61.262180] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11471 10:04:40.689200 <3>[ 61.262220] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11472 10:04:40.696807 <3>[ 61.262466] PM: Some devices failed to suspend, or early wake event detected
11473 10:04:40.702329 <6>[ 61.531876] OOM killer enabled.
11474 10:04:40.712256 <6>[ 61.535287] Restarting tasks ... done.
11475 10:04:40.715893 <5>[ 61.545834] random: crng reseeded on system resumption
11476 10:04:40.719816 <6>[ 61.552503] PM: suspend exit
11477 10:04:40.722994 rtcwake: write error
11478 10:04:40.729968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11479 10:04:40.730228 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11481 10:04:40.733272 rtcwake: assuming RTC uses UTC ...
11482 10:04:40.740340 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:04:47 2023
11483 10:04:40.752100 <6>[ 61.581646] PM: suspend entry (s2idle)
11484 10:04:40.755291 <6>[ 61.585714] Filesystems sync: 0.000 seconds
11485 10:04:40.762372 <6>[ 61.590768] Freezing user space processes
11486 10:04:40.768723 <6>[ 61.596675] Freezing user space processes completed (elapsed 0.001 seconds)
11487 10:04:40.772100 <6>[ 61.603908] OOM killer disabled.
11488 10:04:40.779087 <6>[ 61.607391] Freezing remaining freezable tasks
11489 10:04:40.785541 <6>[ 61.613445] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11490 10:04:40.795266 <6>[ 61.621119] printk: Suspending console(s) (use no_console_suspend to debug)
11491 10:04:44.250522 <3>[ 64.846147] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11492 10:04:44.260456 <3>[ 64.846177] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11493 10:04:44.270403 <3>[ 64.846222] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11494 10:04:44.276918 <3>[ 64.846262] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11495 10:04:44.283759 <3>[ 64.846557] PM: Some devices failed to suspend, or early wake event detected
11496 10:04:44.290345 <6>[ 65.120122] OOM killer enabled.
11497 10:04:44.293740 <6>[ 65.123533] Restarting tasks ... done.
11498 10:04:44.300302 <5>[ 65.129564] random: crng reseeded on system resumption
11499 10:04:44.303649 <6>[ 65.136209] PM: suspend exit
11500 10:04:44.306752 rtcwake: write error
11501 10:04:44.313737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11502 10:04:44.313997 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11504 10:04:44.317147 rtcwake: assuming RTC uses UTC ...
11505 10:04:44.323583 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:04:51 2023
11506 10:04:44.335495 <6>[ 65.165426] PM: suspend entry (s2idle)
11507 10:04:44.339029 <6>[ 65.169511] Filesystems sync: 0.000 seconds
11508 10:04:44.345334 <6>[ 65.174544] Freezing user space processes
11509 10:04:44.352289 <6>[ 65.180445] Freezing user space processes completed (elapsed 0.001 seconds)
11510 10:04:44.355499 <6>[ 65.187673] OOM killer disabled.
11511 10:04:44.361866 <6>[ 65.191154] Freezing remaining freezable tasks
11512 10:04:44.369085 <6>[ 65.197174] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11513 10:04:44.378872 <6>[ 65.204848] printk: Suspending console(s) (use no_console_suspend to debug)
11514 10:04:47.834442 <3>[ 68.430201] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11515 10:04:47.844817 <3>[ 68.430231] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11516 10:04:47.854658 <3>[ 68.430275] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11517 10:04:47.861151 <3>[ 68.430315] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11518 10:04:47.867981 <3>[ 68.430616] PM: Some devices failed to suspend, or early wake event detected
11519 10:04:47.874508 <6>[ 68.704130] OOM killer enabled.
11520 10:04:47.877581 <6>[ 68.707540] Restarting tasks ... done.
11521 10:04:47.884523 <5>[ 68.713499] random: crng reseeded on system resumption
11522 10:04:47.888040 <6>[ 68.720142] PM: suspend exit
11523 10:04:47.891176 rtcwake: write error
11524 10:04:47.897814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11525 10:04:47.898638 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11527 10:04:47.901279 rtcwake: assuming RTC uses UTC ...
11528 10:04:47.907326 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:04:54 2023
11529 10:04:47.919840 <6>[ 68.749467] PM: suspend entry (s2idle)
11530 10:04:47.923066 <6>[ 68.753541] Filesystems sync: 0.000 seconds
11531 10:04:47.930092 <6>[ 68.758567] Freezing user space processes
11532 10:04:47.936712 <6>[ 68.764382] Freezing user space processes completed (elapsed 0.001 seconds)
11533 10:04:47.940062 <6>[ 68.771602] OOM killer disabled.
11534 10:04:47.946369 <6>[ 68.775084] Freezing remaining freezable tasks
11535 10:04:47.953175 <6>[ 68.780959] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11536 10:04:47.959815 <6>[ 68.788612] printk: Suspending console(s) (use no_console_suspend to debug)
11537 10:04:51.418270 <3>[ 72.014108] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11538 10:04:51.428331 <3>[ 72.014137] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11539 10:04:51.438198 <3>[ 72.014182] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11540 10:04:51.444718 <3>[ 72.014222] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11541 10:04:51.454487 <3>[ 72.014521] PM: Some devices failed to suspend, or early wake event detected
11542 10:04:51.457878 <6>[ 72.288124] OOM killer enabled.
11543 10:04:51.461150 <6>[ 72.291535] Restarting tasks ... done.
11544 10:04:51.467845 <5>[ 72.297446] random: crng reseeded on system resumption
11545 10:04:51.471445 <6>[ 72.304868] PM: suspend exit
11546 10:04:51.474700 rtcwake: write error
11547 10:04:51.481435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11548 10:04:51.482268 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11550 10:04:51.484907 rtcwake: assuming RTC uses UTC ...
11551 10:04:51.491750 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:04:58 2023
11552 10:04:51.504299 <6>[ 72.334077] PM: suspend entry (s2idle)
11553 10:04:51.507584 <6>[ 72.338136] Filesystems sync: 0.000 seconds
11554 10:04:51.513594 <6>[ 72.343152] Freezing user space processes
11555 10:04:51.520066 <6>[ 72.348963] Freezing user space processes completed (elapsed 0.001 seconds)
11556 10:04:51.523544 <6>[ 72.356185] OOM killer disabled.
11557 10:04:51.529971 <6>[ 72.359664] Freezing remaining freezable tasks
11558 10:04:51.536815 <6>[ 72.365547] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11559 10:04:51.546666 <6>[ 72.373207] printk: Suspending console(s) (use no_console_suspend to debug)
11560 10:04:55.001666 <3>[ 75.598122] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11561 10:04:55.011987 <3>[ 75.598152] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11562 10:04:55.021538 <3>[ 75.598197] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11563 10:04:55.027961 <3>[ 75.598241] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11564 10:04:55.037971 <3>[ 75.598498] PM: Some devices failed to suspend, or early wake event detected
11565 10:04:55.041373 <6>[ 75.872146] OOM killer enabled.
11566 10:04:55.044625 <6>[ 75.875558] Restarting tasks ... done.
11567 10:04:55.051091 <5>[ 75.881666] random: crng reseeded on system resumption
11568 10:04:55.054766 <6>[ 75.888966] PM: suspend exit
11569 10:04:55.058069 rtcwake: write error
11570 10:04:55.065469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11571 10:04:55.066269 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11573 10:04:55.069149 rtcwake: assuming RTC uses UTC ...
11574 10:04:55.075164 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:05:02 2023
11575 10:04:55.087632 <6>[ 75.918255] PM: suspend entry (s2idle)
11576 10:04:55.090808 <6>[ 75.922324] Filesystems sync: 0.000 seconds
11577 10:04:55.097820 <6>[ 75.927359] Freezing user space processes
11578 10:04:55.104509 <6>[ 75.933134] Freezing user space processes completed (elapsed 0.001 seconds)
11579 10:04:55.107745 <6>[ 75.940354] OOM killer disabled.
11580 10:04:55.114087 <6>[ 75.943835] Freezing remaining freezable tasks
11581 10:04:55.120855 <6>[ 75.949698] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11582 10:04:55.127286 <6>[ 75.957351] printk: Suspending console(s) (use no_console_suspend to debug)
11583 10:04:58.576754 <3>[ 79.182107] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11584 10:04:58.586463 <3>[ 79.182138] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11585 10:04:58.596587 <3>[ 79.182181] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11586 10:04:58.603007 <3>[ 79.182224] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11587 10:04:58.609692 <3>[ 79.182414] PM: Some devices failed to suspend, or early wake event detected
11588 10:04:58.616284 <6>[ 79.447956] OOM killer enabled.
11589 10:04:58.619516 <6>[ 79.451368] Restarting tasks ... done.
11590 10:04:58.626075 <5>[ 79.457565] random: crng reseeded on system resumption
11591 10:04:58.629539 <6>[ 79.464500] PM: suspend exit
11592 10:04:58.632896 rtcwake: write error
11593 10:04:58.639847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11594 10:04:58.640132 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11596 10:04:58.643235 rtcwake: assuming RTC uses UTC ...
11597 10:04:58.649775 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:05:05 2023
11598 10:04:58.662259 <6>[ 79.493804] PM: suspend entry (s2idle)
11599 10:04:58.665764 <6>[ 79.497867] Filesystems sync: 0.000 seconds
11600 10:04:58.672393 <6>[ 79.502892] Freezing user space processes
11601 10:04:58.678835 <6>[ 79.508797] Freezing user space processes completed (elapsed 0.001 seconds)
11602 10:04:58.682371 <6>[ 79.516037] OOM killer disabled.
11603 10:04:58.689079 <6>[ 79.519521] Freezing remaining freezable tasks
11604 10:04:58.695105 <6>[ 79.525571] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11605 10:04:58.705836 <6>[ 79.533244] printk: Suspending console(s) (use no_console_suspend to debug)
11606 10:05:02.160119 <3>[ 82.766159] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11607 10:05:02.170236 <3>[ 82.766189] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11608 10:05:02.179701 <3>[ 82.766234] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11609 10:05:02.186581 <3>[ 82.766273] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11610 10:05:02.193493 <3>[ 82.766651] PM: Some devices failed to suspend, or early wake event detected
11611 10:05:02.199804 <6>[ 83.031985] OOM killer enabled.
11612 10:05:02.209529 <6>[ 83.035397] Restarting tasks ... done.
11613 10:05:02.212541 <5>[ 83.045527] random: crng reseeded on system resumption
11614 10:05:02.217585 <6>[ 83.052653] PM: suspend exit
11615 10:05:02.220776 rtcwake: write error
11616 10:05:02.227768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11617 10:05:02.228051 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11619 10:05:02.231185 rtcwake: assuming RTC uses UTC ...
11620 10:05:02.237419 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:05:09 2023
11621 10:05:02.250368 <6>[ 83.082019] PM: suspend entry (s2idle)
11622 10:05:02.253228 <6>[ 83.086075] Filesystems sync: 0.000 seconds
11623 10:05:02.259831 <6>[ 83.091154] Freezing user space processes
11624 10:05:02.266618 <6>[ 83.097010] Freezing user space processes completed (elapsed 0.001 seconds)
11625 10:05:02.270017 <6>[ 83.104243] OOM killer disabled.
11626 10:05:02.276242 <6>[ 83.107727] Freezing remaining freezable tasks
11627 10:05:02.283046 <6>[ 83.113759] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11628 10:05:02.292951 <6>[ 83.121431] printk: Suspending console(s) (use no_console_suspend to debug)
11629 10:05:05.752057 <3>[ 86.350101] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11630 10:05:05.762603 <3>[ 86.350131] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11631 10:05:05.771773 <3>[ 86.350176] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11632 10:05:05.779184 <3>[ 86.350216] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11633 10:05:05.788533 <3>[ 86.350513] PM: Some devices failed to suspend, or early wake event detected
11634 10:05:05.791584 <6>[ 86.624129] OOM killer enabled.
11635 10:05:05.804242 <6>[ 86.627539] Restarting tasks ... done.
11636 10:05:05.806782 <5>[ 86.640150] random: crng reseeded on system resumption
11637 10:05:05.811237 <6>[ 86.647200] PM: suspend exit
11638 10:05:05.814796 rtcwake: write error
11639 10:05:05.822280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11640 10:05:05.822560 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11642 10:05:05.825465 rtcwake: assuming RTC uses UTC ...
11643 10:05:05.831899 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:05:12 2023
11644 10:05:05.844168 <6>[ 86.676670] PM: suspend entry (s2idle)
11645 10:05:05.847850 <6>[ 86.680764] Filesystems sync: 0.000 seconds
11646 10:05:05.854536 <6>[ 86.685747] Freezing user space processes
11647 10:05:05.861013 <6>[ 86.691543] Freezing user space processes completed (elapsed 0.001 seconds)
11648 10:05:05.863846 <6>[ 86.698764] OOM killer disabled.
11649 10:05:05.870524 <6>[ 86.702245] Freezing remaining freezable tasks
11650 10:05:05.877167 <6>[ 86.708123] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11651 10:05:05.886894 <6>[ 86.715773] printk: Suspending console(s) (use no_console_suspend to debug)
11652 10:05:09.335444 <3>[ 89.934184] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11653 10:05:09.345610 <3>[ 89.934222] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11654 10:05:09.355698 <3>[ 89.934271] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11655 10:05:09.361850 <3>[ 89.934315] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11656 10:05:09.372075 <3>[ 89.934596] PM: Some devices failed to suspend, or early wake event detected
11657 10:05:09.375463 <6>[ 90.208134] OOM killer enabled.
11658 10:05:09.378612 <6>[ 90.211550] Restarting tasks ... done.
11659 10:05:09.385446 <5>[ 90.217248] random: crng reseeded on system resumption
11660 10:05:09.388693 <6>[ 90.223897] PM: suspend exit
11661 10:05:09.391880 rtcwake: write error
11662 10:05:09.398337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11663 10:05:09.398622 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11665 10:05:09.401634 rtcwake: assuming RTC uses UTC ...
11666 10:05:09.408523 rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 23 10:05:16 2023
11667 10:05:09.420262 <6>[ 90.253010] PM: suspend entry (s2idle)
11668 10:05:09.423845 <6>[ 90.257078] Filesystems sync: 0.000 seconds
11669 10:05:09.430420 <6>[ 90.262179] Freezing user space processes
11670 10:05:09.436642 <6>[ 90.267966] Freezing user space processes completed (elapsed 0.001 seconds)
11671 10:05:09.439707 <6>[ 90.275185] OOM killer disabled.
11672 10:05:09.446471 <6>[ 90.278665] Freezing remaining freezable tasks
11673 10:05:09.453362 <6>[ 90.284554] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11674 10:05:09.462938 <6>[ 90.292202] printk: Suspending console(s) (use no_console_suspend to debug)
11675 10:05:12.918951 <3>[ 93.518115] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11676 10:05:12.929226 <3>[ 93.518145] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11677 10:05:12.939261 <3>[ 93.518189] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11678 10:05:12.945677 <3>[ 93.518233] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11679 10:05:12.955626 <3>[ 93.518489] PM: Some devices failed to suspend, or early wake event detected
11680 10:05:12.958928 <6>[ 93.792222] OOM killer enabled.
11681 10:05:12.962232 <6>[ 93.795632] Restarting tasks ... done.
11682 10:05:12.968757 <5>[ 93.801355] random: crng reseeded on system resumption
11683 10:05:12.971863 <6>[ 93.808660] PM: suspend exit
11684 10:05:12.975360 rtcwake: write error
11685 10:05:12.982794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11686 10:05:12.983084 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11688 10:05:12.986053 + set +x
11689 10:05:12.989500 <LAVA_SIGNAL_ENDRUN 0_sleep 11336450_1.5.2.3.1>
11690 10:05:12.989609 <LAVA_TEST_RUNNER EXIT>
11691 10:05:12.989873 Received signal: <ENDRUN> 0_sleep 11336450_1.5.2.3.1
11692 10:05:12.989982 Ending use of test pattern.
11693 10:05:12.990077 Ending test lava.0_sleep (11336450_1.5.2.3.1), duration 71.63
11695 10:05:12.990444 ok: lava_test_shell seems to have completed
11696 10:05:12.990805 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11697 10:05:12.990945 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11698 10:05:12.991062 end: 3 lava-test-retry (duration 00:01:12) [common]
11699 10:05:12.991189 start: 4 finalize (timeout 00:04:59) [common]
11700 10:05:12.991307 start: 4.1 power-off (timeout 00:00:30) [common]
11701 10:05:12.991598 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11702 10:05:13.068172 >> Command sent successfully.
11703 10:05:13.070588 Returned 0 in 0 seconds
11704 10:05:13.170967 end: 4.1 power-off (duration 00:00:00) [common]
11706 10:05:13.171277 start: 4.2 read-feedback (timeout 00:04:59) [common]
11707 10:05:13.171537 Listened to connection for namespace 'common' for up to 1s
11708 10:05:13.171821 Listened to connection for namespace 'common' for up to 1s
11709 10:05:14.172028 Finalising connection for namespace 'common'
11710 10:05:14.172194 Disconnecting from shell: Finalise
11711 10:05:14.172273 / #
11712 10:05:14.272581 end: 4.2 read-feedback (duration 00:00:01) [common]
11713 10:05:14.272737 end: 4 finalize (duration 00:00:01) [common]
11714 10:05:14.272847 Cleaning after the job
11715 10:05:14.272946 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/ramdisk
11716 10:05:14.285731 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/kernel
11717 10:05:14.308007 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/dtb
11718 10:05:14.308228 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336450/tftp-deploy-8bjmnj5a/modules
11719 10:05:14.315008 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11336450
11720 10:05:14.485336 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11336450
11721 10:05:14.485514 Job finished correctly