Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 62
- Warnings: 1
- Boot result: PASS
- Kernel Errors: 32
- Errors: 2
1 10:00:16.524880 lava-dispatcher, installed at version: 2023.06
2 10:00:16.525077 start: 0 validate
3 10:00:16.525210 Start time: 2023-08-23 10:00:16.525201+00:00 (UTC)
4 10:00:16.525361 Using caching service: 'http://localhost/cache/?uri=%s'
5 10:00:16.525510 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 10:00:16.792060 Using caching service: 'http://localhost/cache/?uri=%s'
7 10:00:16.792249 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 10:00:43.059466 Using caching service: 'http://localhost/cache/?uri=%s'
9 10:00:43.059634 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 10:00:43.325609 Using caching service: 'http://localhost/cache/?uri=%s'
11 10:00:43.325767 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.45-cip3-31-gc9451d303f3d%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 10:00:46.591199 validate duration: 30.07
14 10:00:46.591460 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:00:46.591556 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:00:46.591643 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:00:46.591769 Not decompressing ramdisk as can be used compressed.
18 10:00:46.591853 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 10:00:46.591919 saving as /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/ramdisk/rootfs.cpio.gz
20 10:00:46.591983 total size: 26246609 (25 MB)
21 10:00:46.857854 progress 0 % (0 MB)
22 10:00:46.864907 progress 5 % (1 MB)
23 10:00:46.871615 progress 10 % (2 MB)
24 10:00:46.878499 progress 15 % (3 MB)
25 10:00:46.885470 progress 20 % (5 MB)
26 10:00:46.892284 progress 25 % (6 MB)
27 10:00:46.899090 progress 30 % (7 MB)
28 10:00:46.906194 progress 35 % (8 MB)
29 10:00:46.912983 progress 40 % (10 MB)
30 10:00:46.919883 progress 45 % (11 MB)
31 10:00:46.926695 progress 50 % (12 MB)
32 10:00:46.933362 progress 55 % (13 MB)
33 10:00:46.939922 progress 60 % (15 MB)
34 10:00:46.946649 progress 65 % (16 MB)
35 10:00:46.953240 progress 70 % (17 MB)
36 10:00:46.959902 progress 75 % (18 MB)
37 10:00:46.966487 progress 80 % (20 MB)
38 10:00:46.973104 progress 85 % (21 MB)
39 10:00:46.979690 progress 90 % (22 MB)
40 10:00:46.986214 progress 95 % (23 MB)
41 10:00:46.992808 progress 100 % (25 MB)
42 10:00:46.993072 25 MB downloaded in 0.40 s (62.41 MB/s)
43 10:00:46.993227 end: 1.1.1 http-download (duration 00:00:00) [common]
45 10:00:46.993464 end: 1.1 download-retry (duration 00:00:00) [common]
46 10:00:46.993551 start: 1.2 download-retry (timeout 00:10:00) [common]
47 10:00:46.993634 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 10:00:46.993766 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 10:00:46.993836 saving as /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/kernel/Image
50 10:00:46.993896 total size: 49220096 (46 MB)
51 10:00:46.993956 No compression specified
52 10:00:46.995232 progress 0 % (0 MB)
53 10:00:47.007806 progress 5 % (2 MB)
54 10:00:47.020307 progress 10 % (4 MB)
55 10:00:47.032879 progress 15 % (7 MB)
56 10:00:47.045133 progress 20 % (9 MB)
57 10:00:47.057690 progress 25 % (11 MB)
58 10:00:47.070132 progress 30 % (14 MB)
59 10:00:47.082826 progress 35 % (16 MB)
60 10:00:47.095296 progress 40 % (18 MB)
61 10:00:47.107851 progress 45 % (21 MB)
62 10:00:47.120741 progress 50 % (23 MB)
63 10:00:47.133237 progress 55 % (25 MB)
64 10:00:47.145628 progress 60 % (28 MB)
65 10:00:47.158533 progress 65 % (30 MB)
66 10:00:47.171359 progress 70 % (32 MB)
67 10:00:47.183936 progress 75 % (35 MB)
68 10:00:47.196281 progress 80 % (37 MB)
69 10:00:47.208747 progress 85 % (39 MB)
70 10:00:47.221531 progress 90 % (42 MB)
71 10:00:47.233852 progress 95 % (44 MB)
72 10:00:47.246501 progress 100 % (46 MB)
73 10:00:47.246697 46 MB downloaded in 0.25 s (185.68 MB/s)
74 10:00:47.246950 end: 1.2.1 http-download (duration 00:00:00) [common]
76 10:00:47.247364 end: 1.2 download-retry (duration 00:00:00) [common]
77 10:00:47.247512 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:00:47.247660 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:00:47.247869 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 10:00:47.247982 saving as /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/dtb/mt8192-asurada-spherion-r0.dtb
81 10:00:47.248074 total size: 47278 (0 MB)
82 10:00:47.248165 No compression specified
83 10:00:47.249522 progress 69 % (0 MB)
84 10:00:47.249797 progress 100 % (0 MB)
85 10:00:47.249967 0 MB downloaded in 0.00 s (23.84 MB/s)
86 10:00:47.250104 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:00:47.250366 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:00:47.250449 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:00:47.250530 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:00:47.250639 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.45-cip3-31-gc9451d303f3d/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 10:00:47.250707 saving as /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/modules/modules.tar
93 10:00:47.250766 total size: 8617228 (8 MB)
94 10:00:47.250846 Using unxz to decompress xz
95 10:00:47.254221 progress 0 % (0 MB)
96 10:00:47.276088 progress 5 % (0 MB)
97 10:00:47.299006 progress 10 % (0 MB)
98 10:00:47.326932 progress 15 % (1 MB)
99 10:00:47.352904 progress 20 % (1 MB)
100 10:00:47.378841 progress 25 % (2 MB)
101 10:00:47.405047 progress 30 % (2 MB)
102 10:00:47.431905 progress 35 % (2 MB)
103 10:00:47.456851 progress 40 % (3 MB)
104 10:00:47.481189 progress 45 % (3 MB)
105 10:00:47.507400 progress 50 % (4 MB)
106 10:00:47.532618 progress 55 % (4 MB)
107 10:00:47.557358 progress 60 % (4 MB)
108 10:00:47.580089 progress 65 % (5 MB)
109 10:00:47.607681 progress 70 % (5 MB)
110 10:00:47.633070 progress 75 % (6 MB)
111 10:00:47.659924 progress 80 % (6 MB)
112 10:00:47.690053 progress 85 % (7 MB)
113 10:00:47.716413 progress 90 % (7 MB)
114 10:00:47.740590 progress 95 % (7 MB)
115 10:00:47.763716 progress 100 % (8 MB)
116 10:00:47.770278 8 MB downloaded in 0.52 s (15.82 MB/s)
117 10:00:47.770543 end: 1.4.1 http-download (duration 00:00:01) [common]
119 10:00:47.770835 end: 1.4 download-retry (duration 00:00:01) [common]
120 10:00:47.770943 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 10:00:47.771058 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 10:00:47.771155 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:00:47.771267 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 10:00:47.771518 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv
125 10:00:47.771694 makedir: /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin
126 10:00:47.771845 makedir: /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/tests
127 10:00:47.771987 makedir: /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/results
128 10:00:47.772120 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-add-keys
129 10:00:47.772283 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-add-sources
130 10:00:47.772431 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-background-process-start
131 10:00:47.772578 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-background-process-stop
132 10:00:47.772726 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-common-functions
133 10:00:47.772907 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-echo-ipv4
134 10:00:47.773079 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-install-packages
135 10:00:47.773248 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-installed-packages
136 10:00:47.773412 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-os-build
137 10:00:47.773553 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-probe-channel
138 10:00:47.773694 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-probe-ip
139 10:00:47.773836 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-target-ip
140 10:00:47.773982 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-target-mac
141 10:00:47.774124 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-target-storage
142 10:00:47.774274 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-test-case
143 10:00:47.774444 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-test-event
144 10:00:47.774612 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-test-feedback
145 10:00:47.774777 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-test-raise
146 10:00:47.774919 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-test-reference
147 10:00:47.775062 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-test-runner
148 10:00:47.775202 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-test-set
149 10:00:47.775345 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-test-shell
150 10:00:47.775490 Updating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-install-packages (oe)
151 10:00:47.775667 Updating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/bin/lava-installed-packages (oe)
152 10:00:47.775838 Creating /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/environment
153 10:00:47.775983 LAVA metadata
154 10:00:47.776095 - LAVA_JOB_ID=11336440
155 10:00:47.776199 - LAVA_DISPATCHER_IP=192.168.201.1
156 10:00:47.776350 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 10:00:47.776450 skipped lava-vland-overlay
158 10:00:47.776570 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 10:00:47.776695 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 10:00:47.776804 skipped lava-multinode-overlay
161 10:00:47.776902 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 10:00:47.777006 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 10:00:47.777096 Loading test definitions
164 10:00:47.777236 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 10:00:47.777349 Using /lava-11336440 at stage 0
166 10:00:47.777749 uuid=11336440_1.5.2.3.1 testdef=None
167 10:00:47.777876 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 10:00:47.778006 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 10:00:47.778533 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 10:00:47.778786 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 10:00:47.779661 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 10:00:47.779953 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 10:00:47.780803 runner path: /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11336440_1.5.2.3.1
176 10:00:47.780978 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 10:00:47.781337 Creating lava-test-runner.conf files
179 10:00:47.781440 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11336440/lava-overlay-9185mejv/lava-11336440/0 for stage 0
180 10:00:47.781577 - 0_v4l2-compliance-mtk-vcodec-enc
181 10:00:47.781716 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 10:00:47.781846 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 10:00:47.789060 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 10:00:47.789181 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 10:00:47.789287 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 10:00:47.789394 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 10:00:47.789499 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 10:00:48.473857 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 10:00:48.474236 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 10:00:48.474396 extracting modules file /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11336440/extract-overlay-ramdisk-hdaqsri3/ramdisk
191 10:00:48.719007 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 10:00:48.719191 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 10:00:48.719292 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11336440/compress-overlay-hgwekjk2/overlay-1.5.2.4.tar.gz to ramdisk
194 10:00:48.719370 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11336440/compress-overlay-hgwekjk2/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11336440/extract-overlay-ramdisk-hdaqsri3/ramdisk
195 10:00:48.725807 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 10:00:48.725930 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 10:00:48.726025 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 10:00:48.726116 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 10:00:48.726197 Building ramdisk /var/lib/lava/dispatcher/tmp/11336440/extract-overlay-ramdisk-hdaqsri3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11336440/extract-overlay-ramdisk-hdaqsri3/ramdisk
200 10:00:49.239322 >> 228241 blocks
201 10:00:53.122615 rename /var/lib/lava/dispatcher/tmp/11336440/extract-overlay-ramdisk-hdaqsri3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/ramdisk/ramdisk.cpio.gz
202 10:00:53.123020 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 10:00:53.123148 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 10:00:53.123254 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 10:00:53.123360 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/kernel/Image'
206 10:01:05.963337 Returned 0 in 12 seconds
207 10:01:06.063951 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/kernel/image.itb
208 10:01:06.649409 output: FIT description: Kernel Image image with one or more FDT blobs
209 10:01:06.649867 output: Created: Wed Aug 23 11:01:06 2023
210 10:01:06.650000 output: Image 0 (kernel-1)
211 10:01:06.650121 output: Description:
212 10:01:06.650238 output: Created: Wed Aug 23 11:01:06 2023
213 10:01:06.650357 output: Type: Kernel Image
214 10:01:06.650473 output: Compression: lzma compressed
215 10:01:06.650588 output: Data Size: 11037260 Bytes = 10778.57 KiB = 10.53 MiB
216 10:01:06.650703 output: Architecture: AArch64
217 10:01:06.650820 output: OS: Linux
218 10:01:06.650931 output: Load Address: 0x00000000
219 10:01:06.651041 output: Entry Point: 0x00000000
220 10:01:06.651149 output: Hash algo: crc32
221 10:01:06.651257 output: Hash value: 17b65cb3
222 10:01:06.651364 output: Image 1 (fdt-1)
223 10:01:06.651470 output: Description: mt8192-asurada-spherion-r0
224 10:01:06.651577 output: Created: Wed Aug 23 11:01:06 2023
225 10:01:06.651684 output: Type: Flat Device Tree
226 10:01:06.651792 output: Compression: uncompressed
227 10:01:06.651899 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 10:01:06.652007 output: Architecture: AArch64
229 10:01:06.652118 output: Hash algo: crc32
230 10:01:06.652221 output: Hash value: cc4352de
231 10:01:06.652331 output: Image 2 (ramdisk-1)
232 10:01:06.652440 output: Description: unavailable
233 10:01:06.652544 output: Created: Wed Aug 23 11:01:06 2023
234 10:01:06.652653 output: Type: RAMDisk Image
235 10:01:06.652786 output: Compression: Unknown Compression
236 10:01:06.652906 output: Data Size: 39341225 Bytes = 38419.17 KiB = 37.52 MiB
237 10:01:06.653014 output: Architecture: AArch64
238 10:01:06.653119 output: OS: Linux
239 10:01:06.653225 output: Load Address: unavailable
240 10:01:06.653334 output: Entry Point: unavailable
241 10:01:06.653438 output: Hash algo: crc32
242 10:01:06.653546 output: Hash value: 3945b7e0
243 10:01:06.653653 output: Default Configuration: 'conf-1'
244 10:01:06.653763 output: Configuration 0 (conf-1)
245 10:01:06.653873 output: Description: mt8192-asurada-spherion-r0
246 10:01:06.653978 output: Kernel: kernel-1
247 10:01:06.654085 output: Init Ramdisk: ramdisk-1
248 10:01:06.654196 output: FDT: fdt-1
249 10:01:06.654302 output: Loadables: kernel-1
250 10:01:06.654406 output:
251 10:01:06.654683 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 10:01:06.654848 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 10:01:06.655018 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 10:01:06.655179 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 10:01:06.655320 No LXC device requested
256 10:01:06.655463 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 10:01:06.655621 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 10:01:06.655760 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 10:01:06.655890 Checking files for TFTP limit of 4294967296 bytes.
260 10:01:06.656694 end: 1 tftp-deploy (duration 00:00:20) [common]
261 10:01:06.656895 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 10:01:06.657048 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 10:01:06.657243 substitutions:
264 10:01:06.657358 - {DTB}: 11336440/tftp-deploy-_opjp2ba/dtb/mt8192-asurada-spherion-r0.dtb
265 10:01:06.657478 - {INITRD}: 11336440/tftp-deploy-_opjp2ba/ramdisk/ramdisk.cpio.gz
266 10:01:06.657593 - {KERNEL}: 11336440/tftp-deploy-_opjp2ba/kernel/Image
267 10:01:06.657703 - {LAVA_MAC}: None
268 10:01:06.657813 - {PRESEED_CONFIG}: None
269 10:01:06.657921 - {PRESEED_LOCAL}: None
270 10:01:06.658034 - {RAMDISK}: 11336440/tftp-deploy-_opjp2ba/ramdisk/ramdisk.cpio.gz
271 10:01:06.658140 - {ROOT_PART}: None
272 10:01:06.658248 - {ROOT}: None
273 10:01:06.658354 - {SERVER_IP}: 192.168.201.1
274 10:01:06.658462 - {TEE}: None
275 10:01:06.658578 Parsed boot commands:
276 10:01:06.658687 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 10:01:06.658963 Parsed boot commands: tftpboot 192.168.201.1 11336440/tftp-deploy-_opjp2ba/kernel/image.itb 11336440/tftp-deploy-_opjp2ba/kernel/cmdline
278 10:01:06.659114 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 10:01:06.659266 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 10:01:06.659422 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 10:01:06.659573 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 10:01:06.659704 Not connected, no need to disconnect.
283 10:01:06.659837 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 10:01:06.659973 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 10:01:06.660102 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 10:01:06.663769 Setting prompt string to ['lava-test: # ']
287 10:01:06.664212 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 10:01:06.664404 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 10:01:06.664575 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 10:01:06.664727 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 10:01:06.665092 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 10:01:11.799916 >> Command sent successfully.
293 10:01:11.802290 Returned 0 in 5 seconds
294 10:01:11.902663 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 10:01:11.902978 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 10:01:11.903140 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 10:01:11.903242 Setting prompt string to 'Starting depthcharge on Spherion...'
299 10:01:11.903341 Changing prompt to 'Starting depthcharge on Spherion...'
300 10:01:11.903410 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 10:01:11.903672 [Enter `^Ec?' for help]
302 10:01:12.080809
303 10:01:12.080961
304 10:01:12.081028 F0: 102B 0000
305 10:01:12.081093
306 10:01:12.081155 F3: 1001 0000 [0200]
307 10:01:12.084054
308 10:01:12.084169 F3: 1001 0000
309 10:01:12.084267
310 10:01:12.084359 F7: 102D 0000
311 10:01:12.084449
312 10:01:12.087360 F1: 0000 0000
313 10:01:12.087472
314 10:01:12.087562 V0: 0000 0000 [0001]
315 10:01:12.087650
316 10:01:12.090855 00: 0007 8000
317 10:01:12.090942
318 10:01:12.091008 01: 0000 0000
319 10:01:12.091071
320 10:01:12.094038 BP: 0C00 0209 [0000]
321 10:01:12.094122
322 10:01:12.094190 G0: 1182 0000
323 10:01:12.094252
324 10:01:12.098014 EC: 0000 0021 [4000]
325 10:01:12.098099
326 10:01:12.098166 S7: 0000 0000 [0000]
327 10:01:12.098226
328 10:01:12.101643 CC: 0000 0000 [0001]
329 10:01:12.101727
330 10:01:12.101795 T0: 0000 0040 [010F]
331 10:01:12.101858
332 10:01:12.101918 Jump to BL
333 10:01:12.101976
334 10:01:12.128049
335 10:01:12.128136
336 10:01:12.128203
337 10:01:12.135044 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 10:01:12.138808 ARM64: Exception handlers installed.
339 10:01:12.142295 ARM64: Testing exception
340 10:01:12.145687 ARM64: Done test exception
341 10:01:12.152324 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 10:01:12.162722 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 10:01:12.169271 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 10:01:12.179203 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 10:01:12.185935 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 10:01:12.192484 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 10:01:12.204662 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 10:01:12.211675 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 10:01:12.230631 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 10:01:12.234306 WDT: Last reset was cold boot
351 10:01:12.237356 SPI1(PAD0) initialized at 2873684 Hz
352 10:01:12.240773 SPI5(PAD0) initialized at 992727 Hz
353 10:01:12.244112 VBOOT: Loading verstage.
354 10:01:12.250890 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 10:01:12.254285 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 10:01:12.257349 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 10:01:12.260627 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 10:01:12.268284 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 10:01:12.274737 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 10:01:12.285783 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 10:01:12.285868
362 10:01:12.285935
363 10:01:12.295657 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 10:01:12.299088 ARM64: Exception handlers installed.
365 10:01:12.302630 ARM64: Testing exception
366 10:01:12.302715 ARM64: Done test exception
367 10:01:12.309125 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 10:01:12.312450 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 10:01:12.326567 Probing TPM: . done!
370 10:01:12.326651 TPM ready after 0 ms
371 10:01:12.333311 Connected to device vid:did:rid of 1ae0:0028:00
372 10:01:12.341025 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 10:01:12.398877 Initialized TPM device CR50 revision 0
374 10:01:12.409342 tlcl_send_startup: Startup return code is 0
375 10:01:12.409430 TPM: setup succeeded
376 10:01:12.420815 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 10:01:12.429970 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 10:01:12.439742 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 10:01:12.449289 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 10:01:12.452347 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 10:01:12.459173 in-header: 03 07 00 00 08 00 00 00
382 10:01:12.462773 in-data: aa e4 47 04 13 02 00 00
383 10:01:12.466572 Chrome EC: UHEPI supported
384 10:01:12.473579 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 10:01:12.477346 in-header: 03 ad 00 00 08 00 00 00
386 10:01:12.481347 in-data: 00 20 20 08 00 00 00 00
387 10:01:12.481431 Phase 1
388 10:01:12.484535 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 10:01:12.492052 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 10:01:12.496270 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 10:01:12.499682 Recovery requested (1009000e)
392 10:01:12.508424 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 10:01:12.513861 tlcl_extend: response is 0
394 10:01:12.523274 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 10:01:12.529016 tlcl_extend: response is 0
396 10:01:12.535614 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 10:01:12.556410 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 10:01:12.563327 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 10:01:12.563457
400 10:01:12.563572
401 10:01:12.573323 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 10:01:12.576651 ARM64: Exception handlers installed.
403 10:01:12.576780 ARM64: Testing exception
404 10:01:12.580466 ARM64: Done test exception
405 10:01:12.601393 pmic_efuse_setting: Set efuses in 11 msecs
406 10:01:12.604828 pmwrap_interface_init: Select PMIF_VLD_RDY
407 10:01:12.611447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 10:01:12.615621 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 10:01:12.618503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 10:01:12.625572 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 10:01:12.628710 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 10:01:12.636270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 10:01:12.640274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 10:01:12.643916 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 10:01:12.647476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 10:01:12.655258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 10:01:12.659048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 10:01:12.662203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 10:01:12.665519 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 10:01:12.673180 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 10:01:12.679830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 10:01:12.687267 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 10:01:12.690669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 10:01:12.697783 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 10:01:12.701957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 10:01:12.708427 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 10:01:12.712157 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 10:01:12.719702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 10:01:12.726095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 10:01:12.729445 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 10:01:12.736069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 10:01:12.739572 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 10:01:12.746208 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 10:01:12.749518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 10:01:12.756258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 10:01:12.759479 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 10:01:12.766170 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 10:01:12.769693 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 10:01:12.776115 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 10:01:12.779615 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 10:01:12.786416 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 10:01:12.789478 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 10:01:12.796600 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 10:01:12.799683 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 10:01:12.806294 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 10:01:12.809728 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 10:01:12.813833 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 10:01:12.817474 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 10:01:12.821021 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 10:01:12.827463 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 10:01:12.831006 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 10:01:12.834070 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 10:01:12.841049 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 10:01:12.844217 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 10:01:12.847711 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 10:01:12.850769 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 10:01:12.857816 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 10:01:12.864567 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 10:01:12.874428 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 10:01:12.877563 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 10:01:12.884513 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 10:01:12.894310 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 10:01:12.897777 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 10:01:12.904558 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 10:01:12.908060 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 10:01:12.914627 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1a
467 10:01:12.921125 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 10:01:12.925006 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 10:01:12.927816 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 10:01:12.939359 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 10:01:12.948092 [RTC]rtc_get_frequency_meter,154: input=23, output=958
472 10:01:12.957861 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 10:01:12.967131 [RTC]rtc_get_frequency_meter,154: input=17, output=817
474 10:01:12.977151 [RTC]rtc_get_frequency_meter,154: input=16, output=797
475 10:01:12.986487 [RTC]rtc_get_frequency_meter,154: input=15, output=771
476 10:01:12.996435 [RTC]rtc_get_frequency_meter,154: input=16, output=796
477 10:01:12.999833 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 10:01:13.006923 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 10:01:13.011134 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 10:01:13.014825 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 10:01:13.018013 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 10:01:13.022131 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 10:01:13.025829 ADC[4]: Raw value=902139 ID=7
484 10:01:13.029391 ADC[3]: Raw value=213179 ID=1
485 10:01:13.029523 RAM Code: 0x71
486 10:01:13.032495 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 10:01:13.039352 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 10:01:13.045915 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 10:01:13.052903 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 10:01:13.056224 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 10:01:13.059357 in-header: 03 07 00 00 08 00 00 00
492 10:01:13.063022 in-data: aa e4 47 04 13 02 00 00
493 10:01:13.066380 Chrome EC: UHEPI supported
494 10:01:13.072593 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 10:01:13.076314 in-header: 03 ed 00 00 08 00 00 00
496 10:01:13.079529 in-data: 80 20 60 08 00 00 00 00
497 10:01:13.082808 MRC: failed to locate region type 0.
498 10:01:13.090258 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 10:01:13.093832 DRAM-K: Running full calibration
500 10:01:13.097697 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 10:01:13.101650 header.status = 0x0
502 10:01:13.105197 header.version = 0x6 (expected: 0x6)
503 10:01:13.108667 header.size = 0xd00 (expected: 0xd00)
504 10:01:13.108761 header.flags = 0x0
505 10:01:13.115925 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 10:01:13.132669 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 10:01:13.139337 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 10:01:13.142423 dram_init: ddr_geometry: 2
509 10:01:13.145782 [EMI] MDL number = 2
510 10:01:13.145868 [EMI] Get MDL freq = 0
511 10:01:13.149321 dram_init: ddr_type: 0
512 10:01:13.149406 is_discrete_lpddr4: 1
513 10:01:13.152675 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 10:01:13.152766
515 10:01:13.152834
516 10:01:13.155817 [Bian_co] ETT version 0.0.0.1
517 10:01:13.162736 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 10:01:13.162823
519 10:01:13.165923 dramc_set_vcore_voltage set vcore to 650000
520 10:01:13.166008 Read voltage for 800, 4
521 10:01:13.169105 Vio18 = 0
522 10:01:13.169189 Vcore = 650000
523 10:01:13.169256 Vdram = 0
524 10:01:13.172414 Vddq = 0
525 10:01:13.172500 Vmddr = 0
526 10:01:13.175981 dram_init: config_dvfs: 1
527 10:01:13.179105 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 10:01:13.185736 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 10:01:13.189259 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
530 10:01:13.192461 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
531 10:01:13.195929 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 10:01:13.199479 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 10:01:13.202763 MEM_TYPE=3, freq_sel=18
534 10:01:13.206080 sv_algorithm_assistance_LP4_1600
535 10:01:13.209446 ============ PULL DRAM RESETB DOWN ============
536 10:01:13.212668 ========== PULL DRAM RESETB DOWN end =========
537 10:01:13.219611 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 10:01:13.222608 ===================================
539 10:01:13.222693 LPDDR4 DRAM CONFIGURATION
540 10:01:13.226082 ===================================
541 10:01:13.229568 EX_ROW_EN[0] = 0x0
542 10:01:13.232729 EX_ROW_EN[1] = 0x0
543 10:01:13.232852 LP4Y_EN = 0x0
544 10:01:13.235893 WORK_FSP = 0x0
545 10:01:13.235977 WL = 0x2
546 10:01:13.239411 RL = 0x2
547 10:01:13.239496 BL = 0x2
548 10:01:13.242609 RPST = 0x0
549 10:01:13.242693 RD_PRE = 0x0
550 10:01:13.246388 WR_PRE = 0x1
551 10:01:13.246472 WR_PST = 0x0
552 10:01:13.249513 DBI_WR = 0x0
553 10:01:13.249598 DBI_RD = 0x0
554 10:01:13.252820 OTF = 0x1
555 10:01:13.256165 ===================================
556 10:01:13.259549 ===================================
557 10:01:13.259634 ANA top config
558 10:01:13.263058 ===================================
559 10:01:13.266068 DLL_ASYNC_EN = 0
560 10:01:13.269621 ALL_SLAVE_EN = 1
561 10:01:13.272882 NEW_RANK_MODE = 1
562 10:01:13.272967 DLL_IDLE_MODE = 1
563 10:01:13.276532 LP45_APHY_COMB_EN = 1
564 10:01:13.279416 TX_ODT_DIS = 1
565 10:01:13.282815 NEW_8X_MODE = 1
566 10:01:13.286352 ===================================
567 10:01:13.289428 ===================================
568 10:01:13.289512 data_rate = 1600
569 10:01:13.293144 CKR = 1
570 10:01:13.296240 DQ_P2S_RATIO = 8
571 10:01:13.299768 ===================================
572 10:01:13.302768 CA_P2S_RATIO = 8
573 10:01:13.306383 DQ_CA_OPEN = 0
574 10:01:13.309917 DQ_SEMI_OPEN = 0
575 10:01:13.310002 CA_SEMI_OPEN = 0
576 10:01:13.312981 CA_FULL_RATE = 0
577 10:01:13.316181 DQ_CKDIV4_EN = 1
578 10:01:13.319768 CA_CKDIV4_EN = 1
579 10:01:13.322839 CA_PREDIV_EN = 0
580 10:01:13.326485 PH8_DLY = 0
581 10:01:13.326571 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 10:01:13.329773 DQ_AAMCK_DIV = 4
583 10:01:13.333301 CA_AAMCK_DIV = 4
584 10:01:13.336428 CA_ADMCK_DIV = 4
585 10:01:13.339851 DQ_TRACK_CA_EN = 0
586 10:01:13.339937 CA_PICK = 800
587 10:01:13.343100 CA_MCKIO = 800
588 10:01:13.346562 MCKIO_SEMI = 0
589 10:01:13.350259 PLL_FREQ = 3068
590 10:01:13.353957 DQ_UI_PI_RATIO = 32
591 10:01:13.357632 CA_UI_PI_RATIO = 0
592 10:01:13.357721 ===================================
593 10:01:13.361090 ===================================
594 10:01:13.364676 memory_type:LPDDR4
595 10:01:13.369033 GP_NUM : 10
596 10:01:13.369121 SRAM_EN : 1
597 10:01:13.372340 MD32_EN : 0
598 10:01:13.375622 ===================================
599 10:01:13.375710 [ANA_INIT] >>>>>>>>>>>>>>
600 10:01:13.379032 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 10:01:13.382878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 10:01:13.386631 ===================================
603 10:01:13.389987 data_rate = 1600,PCW = 0X7600
604 10:01:13.393778 ===================================
605 10:01:13.396713 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 10:01:13.400330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 10:01:13.406879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 10:01:13.410269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 10:01:13.413799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 10:01:13.417148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 10:01:13.420437 [ANA_INIT] flow start
612 10:01:13.423617 [ANA_INIT] PLL >>>>>>>>
613 10:01:13.423704 [ANA_INIT] PLL <<<<<<<<
614 10:01:13.426916 [ANA_INIT] MIDPI >>>>>>>>
615 10:01:13.430281 [ANA_INIT] MIDPI <<<<<<<<
616 10:01:13.430365 [ANA_INIT] DLL >>>>>>>>
617 10:01:13.433735 [ANA_INIT] flow end
618 10:01:13.436746 ============ LP4 DIFF to SE enter ============
619 10:01:13.440568 ============ LP4 DIFF to SE exit ============
620 10:01:13.443630 [ANA_INIT] <<<<<<<<<<<<<
621 10:01:13.447042 [Flow] Enable top DCM control >>>>>
622 10:01:13.450263 [Flow] Enable top DCM control <<<<<
623 10:01:13.453545 Enable DLL master slave shuffle
624 10:01:13.460218 ==============================================================
625 10:01:13.460331 Gating Mode config
626 10:01:13.467552 ==============================================================
627 10:01:13.467637 Config description:
628 10:01:13.476980 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 10:01:13.483682 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 10:01:13.490621 SELPH_MODE 0: By rank 1: By Phase
631 10:01:13.493790 ==============================================================
632 10:01:13.497232 GAT_TRACK_EN = 1
633 10:01:13.500504 RX_GATING_MODE = 2
634 10:01:13.503608 RX_GATING_TRACK_MODE = 2
635 10:01:13.507168 SELPH_MODE = 1
636 10:01:13.510431 PICG_EARLY_EN = 1
637 10:01:13.513645 VALID_LAT_VALUE = 1
638 10:01:13.517060 ==============================================================
639 10:01:13.520537 Enter into Gating configuration >>>>
640 10:01:13.524251 Exit from Gating configuration <<<<
641 10:01:13.527888 Enter into DVFS_PRE_config >>>>>
642 10:01:13.538998 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 10:01:13.542722 Exit from DVFS_PRE_config <<<<<
644 10:01:13.546797 Enter into PICG configuration >>>>
645 10:01:13.550602 Exit from PICG configuration <<<<
646 10:01:13.550682 [RX_INPUT] configuration >>>>>
647 10:01:13.554475 [RX_INPUT] configuration <<<<<
648 10:01:13.561964 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 10:01:13.565083 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 10:01:13.572302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 10:01:13.576376 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 10:01:13.583643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 10:01:13.591149 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 10:01:13.595184 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 10:01:13.598734 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 10:01:13.601967 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 10:01:13.605967 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 10:01:13.609821 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 10:01:13.613408 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 10:01:13.617245 ===================================
661 10:01:13.620850 LPDDR4 DRAM CONFIGURATION
662 10:01:13.624671 ===================================
663 10:01:13.624798 EX_ROW_EN[0] = 0x0
664 10:01:13.628832 EX_ROW_EN[1] = 0x0
665 10:01:13.628920 LP4Y_EN = 0x0
666 10:01:13.632074 WORK_FSP = 0x0
667 10:01:13.632168 WL = 0x2
668 10:01:13.636182 RL = 0x2
669 10:01:13.636267 BL = 0x2
670 10:01:13.639409 RPST = 0x0
671 10:01:13.639495 RD_PRE = 0x0
672 10:01:13.643425 WR_PRE = 0x1
673 10:01:13.643511 WR_PST = 0x0
674 10:01:13.643577 DBI_WR = 0x0
675 10:01:13.647116 DBI_RD = 0x0
676 10:01:13.647203 OTF = 0x1
677 10:01:13.651045 ===================================
678 10:01:13.654449 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 10:01:13.658194 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 10:01:13.666110 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 10:01:13.666225 ===================================
682 10:01:13.669605 LPDDR4 DRAM CONFIGURATION
683 10:01:13.673560 ===================================
684 10:01:13.677106 EX_ROW_EN[0] = 0x10
685 10:01:13.677222 EX_ROW_EN[1] = 0x0
686 10:01:13.677321 LP4Y_EN = 0x0
687 10:01:13.680562 WORK_FSP = 0x0
688 10:01:13.680669 WL = 0x2
689 10:01:13.684743 RL = 0x2
690 10:01:13.684878 BL = 0x2
691 10:01:13.688312 RPST = 0x0
692 10:01:13.688441 RD_PRE = 0x0
693 10:01:13.691998 WR_PRE = 0x1
694 10:01:13.692125 WR_PST = 0x0
695 10:01:13.695613 DBI_WR = 0x0
696 10:01:13.695743 DBI_RD = 0x0
697 10:01:13.699186 OTF = 0x1
698 10:01:13.703193 ===================================
699 10:01:13.706433 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 10:01:13.710701 nWR fixed to 40
701 10:01:13.714637 [ModeRegInit_LP4] CH0 RK0
702 10:01:13.714764 [ModeRegInit_LP4] CH0 RK1
703 10:01:13.718293 [ModeRegInit_LP4] CH1 RK0
704 10:01:13.722139 [ModeRegInit_LP4] CH1 RK1
705 10:01:13.722266 match AC timing 13
706 10:01:13.725999 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 10:01:13.729507 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 10:01:13.736569 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 10:01:13.740444 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 10:01:13.744364 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 10:01:13.744491 [EMI DOE] emi_dcm 0
712 10:01:13.751559 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 10:01:13.751689 ==
714 10:01:13.755274 Dram Type= 6, Freq= 0, CH_0, rank 0
715 10:01:13.759059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 10:01:13.759185 ==
717 10:01:13.762538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 10:01:13.769477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 10:01:13.778840 [CA 0] Center 38 (7~69) winsize 63
720 10:01:13.782695 [CA 1] Center 38 (7~69) winsize 63
721 10:01:13.786638 [CA 2] Center 35 (5~66) winsize 62
722 10:01:13.790411 [CA 3] Center 35 (5~66) winsize 62
723 10:01:13.794509 [CA 4] Center 34 (4~65) winsize 62
724 10:01:13.794595 [CA 5] Center 33 (3~64) winsize 62
725 10:01:13.794662
726 10:01:13.798610 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 10:01:13.798696
728 10:01:13.802141 [CATrainingPosCal] consider 1 rank data
729 10:01:13.805744 u2DelayCellTimex100 = 270/100 ps
730 10:01:13.809427 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 10:01:13.813187 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
732 10:01:13.817159 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 10:01:13.820646 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 10:01:13.824551 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 10:01:13.828525 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 10:01:13.828650
737 10:01:13.832011 CA PerBit enable=1, Macro0, CA PI delay=33
738 10:01:13.832132
739 10:01:13.835423 [CBTSetCACLKResult] CA Dly = 33
740 10:01:13.835510 CS Dly: 5 (0~36)
741 10:01:13.835578 ==
742 10:01:13.838637 Dram Type= 6, Freq= 0, CH_0, rank 1
743 10:01:13.845589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 10:01:13.845671 ==
745 10:01:13.848611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 10:01:13.855300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 10:01:13.865348 [CA 0] Center 38 (7~69) winsize 63
748 10:01:13.868536 [CA 1] Center 38 (7~69) winsize 63
749 10:01:13.871505 [CA 2] Center 36 (6~66) winsize 61
750 10:01:13.875105 [CA 3] Center 35 (5~66) winsize 62
751 10:01:13.878223 [CA 4] Center 35 (4~66) winsize 63
752 10:01:13.881798 [CA 5] Center 34 (4~65) winsize 62
753 10:01:13.881883
754 10:01:13.885559 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 10:01:13.885644
756 10:01:13.888303 [CATrainingPosCal] consider 2 rank data
757 10:01:13.892047 u2DelayCellTimex100 = 270/100 ps
758 10:01:13.895032 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
759 10:01:13.898530 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
760 10:01:13.905399 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
761 10:01:13.908387 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
762 10:01:13.911738 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
763 10:01:13.915331 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 10:01:13.915418
765 10:01:13.918480 CA PerBit enable=1, Macro0, CA PI delay=34
766 10:01:13.918567
767 10:01:13.922022 [CBTSetCACLKResult] CA Dly = 34
768 10:01:13.922109 CS Dly: 6 (0~38)
769 10:01:13.922197
770 10:01:13.925170 ----->DramcWriteLeveling(PI) begin...
771 10:01:13.925258 ==
772 10:01:13.928500 Dram Type= 6, Freq= 0, CH_0, rank 0
773 10:01:13.935818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 10:01:13.935928 ==
775 10:01:13.939461 Write leveling (Byte 0): 33 => 33
776 10:01:13.939547 Write leveling (Byte 1): 31 => 31
777 10:01:13.942768 DramcWriteLeveling(PI) end<-----
778 10:01:13.942852
779 10:01:13.942918 ==
780 10:01:13.946631 Dram Type= 6, Freq= 0, CH_0, rank 0
781 10:01:13.950603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 10:01:13.950689 ==
783 10:01:13.953345 [Gating] SW mode calibration
784 10:01:13.960148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 10:01:13.967390 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 10:01:13.970922 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 10:01:13.974498 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 10:01:13.980695 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 10:01:13.984186 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 10:01:13.987318 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 10:01:13.994365 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 10:01:13.997588 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 10:01:14.001021 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 10:01:14.007681 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 10:01:14.010908 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 10:01:14.014245 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 10:01:14.017428 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 10:01:14.024290 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 10:01:14.027714 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 10:01:14.031096 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 10:01:14.037485 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 10:01:14.041186 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 10:01:14.044816 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 10:01:14.051121 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 10:01:14.054615 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 10:01:14.057788 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 10:01:14.064742 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 10:01:14.067782 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 10:01:14.071206 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 10:01:14.077766 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 10:01:14.081294 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
812 10:01:14.084666 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
813 10:01:14.088144 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
814 10:01:14.094902 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 10:01:14.098074 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 10:01:14.101301 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 10:01:14.108374 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 10:01:14.111621 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
819 10:01:14.114727 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
820 10:01:14.121348 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
821 10:01:14.125085 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
822 10:01:14.128410 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 10:01:14.134783 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 10:01:14.138239 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 10:01:14.141717 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 10:01:14.148260 0 11 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
827 10:01:14.151500 0 11 4 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
828 10:01:14.154756 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
829 10:01:14.161681 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
830 10:01:14.164879 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 10:01:14.168018 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 10:01:14.171584 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 10:01:14.178281 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 10:01:14.181793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 10:01:14.185201 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
836 10:01:14.191350 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 10:01:14.194683 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 10:01:14.198255 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 10:01:14.205359 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 10:01:14.208334 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 10:01:14.211838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 10:01:14.218602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 10:01:14.221680 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 10:01:14.225379 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 10:01:14.228516 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 10:01:14.235120 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 10:01:14.238228 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 10:01:14.241697 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 10:01:14.248684 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 10:01:14.251723 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 10:01:14.255030 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 10:01:14.261982 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 10:01:14.262062 Total UI for P1: 0, mck2ui 16
854 10:01:14.268761 best dqsien dly found for B0: ( 0, 14, 2)
855 10:01:14.272094 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 10:01:14.275125 Total UI for P1: 0, mck2ui 16
857 10:01:14.278570 best dqsien dly found for B1: ( 0, 14, 6)
858 10:01:14.281893 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
859 10:01:14.285193 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
860 10:01:14.285274
861 10:01:14.288744 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
862 10:01:14.291685 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 10:01:14.295219 [Gating] SW calibration Done
864 10:01:14.295324 ==
865 10:01:14.298619 Dram Type= 6, Freq= 0, CH_0, rank 0
866 10:01:14.301907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 10:01:14.302011 ==
868 10:01:14.305111 RX Vref Scan: 0
869 10:01:14.305186
870 10:01:14.308731 RX Vref 0 -> 0, step: 1
871 10:01:14.308815
872 10:01:14.308879 RX Delay -130 -> 252, step: 16
873 10:01:14.315162 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 10:01:14.318624 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 10:01:14.322029 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 10:01:14.325202 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 10:01:14.328761 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 10:01:14.335419 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 10:01:14.338419 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
880 10:01:14.342244 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 10:01:14.345236 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 10:01:14.348429 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
883 10:01:14.355025 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 10:01:14.358496 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 10:01:14.361951 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
886 10:01:14.365306 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
887 10:01:14.368607 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 10:01:14.375364 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
889 10:01:14.375451 ==
890 10:01:14.378628 Dram Type= 6, Freq= 0, CH_0, rank 0
891 10:01:14.382083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 10:01:14.382200 ==
893 10:01:14.382298 DQS Delay:
894 10:01:14.385270 DQS0 = 0, DQS1 = 0
895 10:01:14.385356 DQM Delay:
896 10:01:14.388679 DQM0 = 90, DQM1 = 79
897 10:01:14.388794 DQ Delay:
898 10:01:14.392173 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 10:01:14.395616 DQ4 =85, DQ5 =77, DQ6 =109, DQ7 =101
900 10:01:14.398886 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
901 10:01:14.402402 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
902 10:01:14.402489
903 10:01:14.402557
904 10:01:14.402619 ==
905 10:01:14.405582 Dram Type= 6, Freq= 0, CH_0, rank 0
906 10:01:14.408700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 10:01:14.408808 ==
908 10:01:14.412254
909 10:01:14.412343
910 10:01:14.412431 TX Vref Scan disable
911 10:01:14.415512 == TX Byte 0 ==
912 10:01:14.419080 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 10:01:14.422662 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 10:01:14.425812 == TX Byte 1 ==
915 10:01:14.429074 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 10:01:14.432075 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 10:01:14.432164 ==
918 10:01:14.435545 Dram Type= 6, Freq= 0, CH_0, rank 0
919 10:01:14.442189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 10:01:14.442278 ==
921 10:01:14.453987 TX Vref=22, minBit 6, minWin=27, winSum=440
922 10:01:14.457565 TX Vref=24, minBit 6, minWin=27, winSum=440
923 10:01:14.460684 TX Vref=26, minBit 6, minWin=27, winSum=444
924 10:01:14.464365 TX Vref=28, minBit 8, minWin=27, winSum=450
925 10:01:14.467471 TX Vref=30, minBit 8, minWin=27, winSum=455
926 10:01:14.474267 TX Vref=32, minBit 10, minWin=27, winSum=455
927 10:01:14.477567 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 30
928 10:01:14.477688
929 10:01:14.480918 Final TX Range 1 Vref 30
930 10:01:14.481007
931 10:01:14.481094 ==
932 10:01:14.484036 Dram Type= 6, Freq= 0, CH_0, rank 0
933 10:01:14.487769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 10:01:14.487857 ==
935 10:01:14.487942
936 10:01:14.490650
937 10:01:14.490735 TX Vref Scan disable
938 10:01:14.494260 == TX Byte 0 ==
939 10:01:14.497649 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 10:01:14.500598 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 10:01:14.504233 == TX Byte 1 ==
942 10:01:14.507433 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 10:01:14.510786 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 10:01:14.510870
945 10:01:14.514528 [DATLAT]
946 10:01:14.514612 Freq=800, CH0 RK0
947 10:01:14.514678
948 10:01:14.517525 DATLAT Default: 0xa
949 10:01:14.517608 0, 0xFFFF, sum = 0
950 10:01:14.521105 1, 0xFFFF, sum = 0
951 10:01:14.521190 2, 0xFFFF, sum = 0
952 10:01:14.524195 3, 0xFFFF, sum = 0
953 10:01:14.524282 4, 0xFFFF, sum = 0
954 10:01:14.527490 5, 0xFFFF, sum = 0
955 10:01:14.527575 6, 0xFFFF, sum = 0
956 10:01:14.531037 7, 0xFFFF, sum = 0
957 10:01:14.531121 8, 0xFFFF, sum = 0
958 10:01:14.534621 9, 0x0, sum = 1
959 10:01:14.534706 10, 0x0, sum = 2
960 10:01:14.537553 11, 0x0, sum = 3
961 10:01:14.537637 12, 0x0, sum = 4
962 10:01:14.540874 best_step = 10
963 10:01:14.540956
964 10:01:14.541021 ==
965 10:01:14.544571 Dram Type= 6, Freq= 0, CH_0, rank 0
966 10:01:14.547948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 10:01:14.548037 ==
968 10:01:14.550891 RX Vref Scan: 1
969 10:01:14.551020
970 10:01:14.551136 Set Vref Range= 32 -> 127
971 10:01:14.551249
972 10:01:14.554447 RX Vref 32 -> 127, step: 1
973 10:01:14.554572
974 10:01:14.557752 RX Delay -95 -> 252, step: 8
975 10:01:14.557858
976 10:01:14.561142 Set Vref, RX VrefLevel [Byte0]: 32
977 10:01:14.564405 [Byte1]: 32
978 10:01:14.564503
979 10:01:14.567837 Set Vref, RX VrefLevel [Byte0]: 33
980 10:01:14.571132 [Byte1]: 33
981 10:01:14.574671
982 10:01:14.574755 Set Vref, RX VrefLevel [Byte0]: 34
983 10:01:14.577729 [Byte1]: 34
984 10:01:14.581993
985 10:01:14.582077 Set Vref, RX VrefLevel [Byte0]: 35
986 10:01:14.585432 [Byte1]: 35
987 10:01:14.589873
988 10:01:14.589957 Set Vref, RX VrefLevel [Byte0]: 36
989 10:01:14.593173 [Byte1]: 36
990 10:01:14.597121
991 10:01:14.597204 Set Vref, RX VrefLevel [Byte0]: 37
992 10:01:14.600497 [Byte1]: 37
993 10:01:14.605259
994 10:01:14.605343 Set Vref, RX VrefLevel [Byte0]: 38
995 10:01:14.608659 [Byte1]: 38
996 10:01:14.612692
997 10:01:14.612795 Set Vref, RX VrefLevel [Byte0]: 39
998 10:01:14.616070 [Byte1]: 39
999 10:01:14.620187
1000 10:01:14.620270 Set Vref, RX VrefLevel [Byte0]: 40
1001 10:01:14.623700 [Byte1]: 40
1002 10:01:14.627865
1003 10:01:14.627947 Set Vref, RX VrefLevel [Byte0]: 41
1004 10:01:14.631488 [Byte1]: 41
1005 10:01:14.635428
1006 10:01:14.635510 Set Vref, RX VrefLevel [Byte0]: 42
1007 10:01:14.638993 [Byte1]: 42
1008 10:01:14.643059
1009 10:01:14.643142 Set Vref, RX VrefLevel [Byte0]: 43
1010 10:01:14.646008 [Byte1]: 43
1011 10:01:14.650445
1012 10:01:14.650528 Set Vref, RX VrefLevel [Byte0]: 44
1013 10:01:14.653600 [Byte1]: 44
1014 10:01:14.658335
1015 10:01:14.658417 Set Vref, RX VrefLevel [Byte0]: 45
1016 10:01:14.661480 [Byte1]: 45
1017 10:01:14.665448
1018 10:01:14.665530 Set Vref, RX VrefLevel [Byte0]: 46
1019 10:01:14.668653 [Byte1]: 46
1020 10:01:14.673257
1021 10:01:14.673339 Set Vref, RX VrefLevel [Byte0]: 47
1022 10:01:14.676475 [Byte1]: 47
1023 10:01:14.680932
1024 10:01:14.681014 Set Vref, RX VrefLevel [Byte0]: 48
1025 10:01:14.684083 [Byte1]: 48
1026 10:01:14.688096
1027 10:01:14.688178 Set Vref, RX VrefLevel [Byte0]: 49
1028 10:01:14.691640 [Byte1]: 49
1029 10:01:14.695958
1030 10:01:14.696039 Set Vref, RX VrefLevel [Byte0]: 50
1031 10:01:14.699138 [Byte1]: 50
1032 10:01:14.703798
1033 10:01:14.703883 Set Vref, RX VrefLevel [Byte0]: 51
1034 10:01:14.706782 [Byte1]: 51
1035 10:01:14.711195
1036 10:01:14.711311 Set Vref, RX VrefLevel [Byte0]: 52
1037 10:01:14.714330 [Byte1]: 52
1038 10:01:14.718434
1039 10:01:14.721784 Set Vref, RX VrefLevel [Byte0]: 53
1040 10:01:14.725086 [Byte1]: 53
1041 10:01:14.725169
1042 10:01:14.728350 Set Vref, RX VrefLevel [Byte0]: 54
1043 10:01:14.731773 [Byte1]: 54
1044 10:01:14.731881
1045 10:01:14.735206 Set Vref, RX VrefLevel [Byte0]: 55
1046 10:01:14.738539 [Byte1]: 55
1047 10:01:14.738622
1048 10:01:14.741795 Set Vref, RX VrefLevel [Byte0]: 56
1049 10:01:14.745307 [Byte1]: 56
1050 10:01:14.748991
1051 10:01:14.749075 Set Vref, RX VrefLevel [Byte0]: 57
1052 10:01:14.752486 [Byte1]: 57
1053 10:01:14.756581
1054 10:01:14.756679 Set Vref, RX VrefLevel [Byte0]: 58
1055 10:01:14.760315 [Byte1]: 58
1056 10:01:14.764259
1057 10:01:14.764345 Set Vref, RX VrefLevel [Byte0]: 59
1058 10:01:14.768078 [Byte1]: 59
1059 10:01:14.771980
1060 10:01:14.772062 Set Vref, RX VrefLevel [Byte0]: 60
1061 10:01:14.774951 [Byte1]: 60
1062 10:01:14.779603
1063 10:01:14.779685 Set Vref, RX VrefLevel [Byte0]: 61
1064 10:01:14.782664 [Byte1]: 61
1065 10:01:14.787185
1066 10:01:14.787267 Set Vref, RX VrefLevel [Byte0]: 62
1067 10:01:14.790847 [Byte1]: 62
1068 10:01:14.794767
1069 10:01:14.794842 Set Vref, RX VrefLevel [Byte0]: 63
1070 10:01:14.798389 [Byte1]: 63
1071 10:01:14.802201
1072 10:01:14.802322 Set Vref, RX VrefLevel [Byte0]: 64
1073 10:01:14.805465 [Byte1]: 64
1074 10:01:14.809841
1075 10:01:14.809923 Set Vref, RX VrefLevel [Byte0]: 65
1076 10:01:14.813503 [Byte1]: 65
1077 10:01:14.817818
1078 10:01:14.817920 Set Vref, RX VrefLevel [Byte0]: 66
1079 10:01:14.821097 [Byte1]: 66
1080 10:01:14.825306
1081 10:01:14.825444 Set Vref, RX VrefLevel [Byte0]: 67
1082 10:01:14.828687 [Byte1]: 67
1083 10:01:14.832627
1084 10:01:14.832765 Set Vref, RX VrefLevel [Byte0]: 68
1085 10:01:14.835804 [Byte1]: 68
1086 10:01:14.840380
1087 10:01:14.840506 Set Vref, RX VrefLevel [Byte0]: 69
1088 10:01:14.843587 [Byte1]: 69
1089 10:01:14.847914
1090 10:01:14.847998 Set Vref, RX VrefLevel [Byte0]: 70
1091 10:01:14.851057 [Byte1]: 70
1092 10:01:14.855396
1093 10:01:14.855500 Set Vref, RX VrefLevel [Byte0]: 71
1094 10:01:14.859024 [Byte1]: 71
1095 10:01:14.863049
1096 10:01:14.863141 Set Vref, RX VrefLevel [Byte0]: 72
1097 10:01:14.866233 [Byte1]: 72
1098 10:01:14.870765
1099 10:01:14.870856 Set Vref, RX VrefLevel [Byte0]: 73
1100 10:01:14.874043 [Byte1]: 73
1101 10:01:14.878524
1102 10:01:14.878609 Set Vref, RX VrefLevel [Byte0]: 74
1103 10:01:14.881367 [Byte1]: 74
1104 10:01:14.885923
1105 10:01:14.886018 Set Vref, RX VrefLevel [Byte0]: 75
1106 10:01:14.889078 [Byte1]: 75
1107 10:01:14.893291
1108 10:01:14.893375 Set Vref, RX VrefLevel [Byte0]: 76
1109 10:01:14.896656 [Byte1]: 76
1110 10:01:14.900765
1111 10:01:14.900840 Final RX Vref Byte 0 = 61 to rank0
1112 10:01:14.904262 Final RX Vref Byte 1 = 60 to rank0
1113 10:01:14.907618 Final RX Vref Byte 0 = 61 to rank1
1114 10:01:14.911014 Final RX Vref Byte 1 = 60 to rank1==
1115 10:01:14.914494 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 10:01:14.918263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 10:01:14.921224 ==
1118 10:01:14.921309 DQS Delay:
1119 10:01:14.921375 DQS0 = 0, DQS1 = 0
1120 10:01:14.924439 DQM Delay:
1121 10:01:14.924522 DQM0 = 93, DQM1 = 82
1122 10:01:14.927649 DQ Delay:
1123 10:01:14.931409 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1124 10:01:14.931494 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1125 10:01:14.934552 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1126 10:01:14.941043 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =92
1127 10:01:14.941158
1128 10:01:14.941255
1129 10:01:14.947796 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
1130 10:01:14.951388 CH0 RK0: MR19=606, MR18=3B36
1131 10:01:14.957773 CH0_RK0: MR19=0x606, MR18=0x3B36, DQSOSC=394, MR23=63, INC=95, DEC=63
1132 10:01:14.957900
1133 10:01:14.961166 ----->DramcWriteLeveling(PI) begin...
1134 10:01:14.961291 ==
1135 10:01:14.964615 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 10:01:14.967782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 10:01:14.967909 ==
1138 10:01:14.971274 Write leveling (Byte 0): 32 => 32
1139 10:01:14.974719 Write leveling (Byte 1): 28 => 28
1140 10:01:14.977652 DramcWriteLeveling(PI) end<-----
1141 10:01:14.977744
1142 10:01:14.977812 ==
1143 10:01:14.981502 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 10:01:14.984694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 10:01:14.984818 ==
1146 10:01:14.988156 [Gating] SW mode calibration
1147 10:01:14.994684 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 10:01:15.001227 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 10:01:15.004486 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 10:01:15.007968 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 10:01:15.052042 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 10:01:15.052748 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 10:01:15.053045 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 10:01:15.053119 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 10:01:15.053184 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 10:01:15.053256 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 10:01:15.053798 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 10:01:15.054072 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 10:01:15.054187 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 10:01:15.054281 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 10:01:15.092462 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 10:01:15.092774 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 10:01:15.092874 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 10:01:15.093154 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 10:01:15.093251 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 10:01:15.093355 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 10:01:15.093826 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1168 10:01:15.094104 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 10:01:15.096781 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 10:01:15.096868 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 10:01:15.100159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 10:01:15.107037 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 10:01:15.110100 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 10:01:15.113759 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1175 10:01:15.119997 0 9 8 | B1->B0 | 2c2c 3030 | 0 1 | (0 0) (1 1)
1176 10:01:15.123742 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 10:01:15.126676 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 10:01:15.130360 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 10:01:15.137018 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 10:01:15.140432 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 10:01:15.143722 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1182 10:01:15.150270 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
1183 10:01:15.153504 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1184 10:01:15.156964 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 10:01:15.163888 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 10:01:15.167226 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 10:01:15.170438 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 10:01:15.177039 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 10:01:15.180703 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 10:01:15.184342 0 11 4 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
1191 10:01:15.187931 0 11 8 | B1->B0 | 3939 4242 | 1 0 | (0 0) (0 0)
1192 10:01:15.195529 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 10:01:15.199084 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 10:01:15.202381 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 10:01:15.205968 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 10:01:15.212814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 10:01:15.216801 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 10:01:15.219989 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 10:01:15.223080 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 10:01:15.229858 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 10:01:15.233443 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 10:01:15.236551 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 10:01:15.243334 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 10:01:15.247189 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 10:01:15.249981 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 10:01:15.256604 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 10:01:15.260275 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 10:01:15.263390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 10:01:15.266813 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 10:01:15.273379 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 10:01:15.276739 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 10:01:15.280033 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 10:01:15.286923 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 10:01:15.290676 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 10:01:15.293501 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 10:01:15.296631 Total UI for P1: 0, mck2ui 16
1217 10:01:15.300193 best dqsien dly found for B0: ( 0, 14, 4)
1218 10:01:15.303242 Total UI for P1: 0, mck2ui 16
1219 10:01:15.306777 best dqsien dly found for B1: ( 0, 14, 4)
1220 10:01:15.310359 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1221 10:01:15.313399 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1222 10:01:15.313483
1223 10:01:15.317070 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1224 10:01:15.323446 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 10:01:15.323532 [Gating] SW calibration Done
1226 10:01:15.323598 ==
1227 10:01:15.327093 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 10:01:15.333548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 10:01:15.333631 ==
1230 10:01:15.333698 RX Vref Scan: 0
1231 10:01:15.333759
1232 10:01:15.336736 RX Vref 0 -> 0, step: 1
1233 10:01:15.336820
1234 10:01:15.340315 RX Delay -130 -> 252, step: 16
1235 10:01:15.343699 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1236 10:01:15.346815 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1237 10:01:15.350363 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1238 10:01:15.357042 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1239 10:01:15.360536 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1240 10:01:15.363580 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1241 10:01:15.366914 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1242 10:01:15.370555 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1243 10:01:15.377141 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1244 10:01:15.380210 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1245 10:01:15.383868 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1246 10:01:15.386905 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1247 10:01:15.390357 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1248 10:01:15.397158 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1249 10:01:15.400600 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1250 10:01:15.403832 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1251 10:01:15.403954 ==
1252 10:01:15.407117 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 10:01:15.410583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 10:01:15.410703 ==
1255 10:01:15.413911 DQS Delay:
1256 10:01:15.414037 DQS0 = 0, DQS1 = 0
1257 10:01:15.414147 DQM Delay:
1258 10:01:15.417281 DQM0 = 92, DQM1 = 83
1259 10:01:15.417406 DQ Delay:
1260 10:01:15.420676 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1261 10:01:15.424256 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1262 10:01:15.427345 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =85
1263 10:01:15.430770 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1264 10:01:15.430891
1265 10:01:15.431007
1266 10:01:15.431112 ==
1267 10:01:15.434409 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 10:01:15.441017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 10:01:15.441137 ==
1270 10:01:15.441251
1271 10:01:15.441361
1272 10:01:15.441473 TX Vref Scan disable
1273 10:01:15.444402 == TX Byte 0 ==
1274 10:01:15.447745 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1275 10:01:15.451058 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1276 10:01:15.454765 == TX Byte 1 ==
1277 10:01:15.458038 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1278 10:01:15.461362 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1279 10:01:15.464615 ==
1280 10:01:15.467681 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 10:01:15.471218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 10:01:15.471301 ==
1283 10:01:15.483777 TX Vref=22, minBit 3, minWin=27, winSum=445
1284 10:01:15.487478 TX Vref=24, minBit 8, minWin=27, winSum=448
1285 10:01:15.490697 TX Vref=26, minBit 8, minWin=27, winSum=453
1286 10:01:15.494092 TX Vref=28, minBit 8, minWin=27, winSum=454
1287 10:01:15.497305 TX Vref=30, minBit 4, minWin=28, winSum=457
1288 10:01:15.500692 TX Vref=32, minBit 8, minWin=28, winSum=460
1289 10:01:15.507432 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 32
1290 10:01:15.507515
1291 10:01:15.510577 Final TX Range 1 Vref 32
1292 10:01:15.510660
1293 10:01:15.510723 ==
1294 10:01:15.513851 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 10:01:15.517185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 10:01:15.517268 ==
1297 10:01:15.517330
1298 10:01:15.520597
1299 10:01:15.520677 TX Vref Scan disable
1300 10:01:15.523957 == TX Byte 0 ==
1301 10:01:15.527210 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1302 10:01:15.530852 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1303 10:01:15.533826 == TX Byte 1 ==
1304 10:01:15.537237 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1305 10:01:15.540624 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1306 10:01:15.544076
1307 10:01:15.544155 [DATLAT]
1308 10:01:15.544218 Freq=800, CH0 RK1
1309 10:01:15.544277
1310 10:01:15.547480 DATLAT Default: 0xa
1311 10:01:15.547563 0, 0xFFFF, sum = 0
1312 10:01:15.550527 1, 0xFFFF, sum = 0
1313 10:01:15.550654 2, 0xFFFF, sum = 0
1314 10:01:15.553658 3, 0xFFFF, sum = 0
1315 10:01:15.553782 4, 0xFFFF, sum = 0
1316 10:01:15.557418 5, 0xFFFF, sum = 0
1317 10:01:15.557539 6, 0xFFFF, sum = 0
1318 10:01:15.560675 7, 0xFFFF, sum = 0
1319 10:01:15.563996 8, 0xFFFF, sum = 0
1320 10:01:15.564122 9, 0x0, sum = 1
1321 10:01:15.564234 10, 0x0, sum = 2
1322 10:01:15.567340 11, 0x0, sum = 3
1323 10:01:15.567460 12, 0x0, sum = 4
1324 10:01:15.570654 best_step = 10
1325 10:01:15.570774
1326 10:01:15.570880 ==
1327 10:01:15.573954 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 10:01:15.577218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 10:01:15.577340 ==
1330 10:01:15.580835 RX Vref Scan: 0
1331 10:01:15.580955
1332 10:01:15.581061 RX Vref 0 -> 0, step: 1
1333 10:01:15.581170
1334 10:01:15.583878 RX Delay -79 -> 252, step: 8
1335 10:01:15.590463 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1336 10:01:15.594105 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1337 10:01:15.597448 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1338 10:01:15.600575 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1339 10:01:15.604331 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1340 10:01:15.610761 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1341 10:01:15.614127 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1342 10:01:15.617355 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1343 10:01:15.620695 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1344 10:01:15.624049 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1345 10:01:15.630728 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1346 10:01:15.634126 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1347 10:01:15.637396 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1348 10:01:15.641064 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1349 10:01:15.644160 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1350 10:01:15.650588 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1351 10:01:15.650709 ==
1352 10:01:15.654257 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 10:01:15.657374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 10:01:15.657491 ==
1355 10:01:15.657605 DQS Delay:
1356 10:01:15.660806 DQS0 = 0, DQS1 = 0
1357 10:01:15.660924 DQM Delay:
1358 10:01:15.664141 DQM0 = 90, DQM1 = 81
1359 10:01:15.664263 DQ Delay:
1360 10:01:15.667377 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1361 10:01:15.670544 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1362 10:01:15.674085 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1363 10:01:15.677407 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1364 10:01:15.677530
1365 10:01:15.677634
1366 10:01:15.684042 [DQSOSCAuto] RK1, (LSB)MR18= 0x411b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1367 10:01:15.687510 CH0 RK1: MR19=606, MR18=411B
1368 10:01:15.694228 CH0_RK1: MR19=0x606, MR18=0x411B, DQSOSC=393, MR23=63, INC=95, DEC=63
1369 10:01:15.697345 [RxdqsGatingPostProcess] freq 800
1370 10:01:15.704093 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 10:01:15.704214 Pre-setting of DQS Precalculation
1372 10:01:15.711196 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 10:01:15.711316 ==
1374 10:01:15.714214 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 10:01:15.717476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 10:01:15.717596 ==
1377 10:01:15.724018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 10:01:15.730584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 10:01:15.738710 [CA 0] Center 36 (6~67) winsize 62
1380 10:01:15.742140 [CA 1] Center 36 (6~67) winsize 62
1381 10:01:15.745663 [CA 2] Center 34 (4~65) winsize 62
1382 10:01:15.748832 [CA 3] Center 34 (3~65) winsize 63
1383 10:01:15.752215 [CA 4] Center 34 (4~65) winsize 62
1384 10:01:15.755974 [CA 5] Center 33 (3~64) winsize 62
1385 10:01:15.756093
1386 10:01:15.759052 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1387 10:01:15.759170
1388 10:01:15.762114 [CATrainingPosCal] consider 1 rank data
1389 10:01:15.765728 u2DelayCellTimex100 = 270/100 ps
1390 10:01:15.769270 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1391 10:01:15.772430 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 10:01:15.779331 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 10:01:15.782409 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1394 10:01:15.785761 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 10:01:15.788733 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 10:01:15.788855
1397 10:01:15.792215 CA PerBit enable=1, Macro0, CA PI delay=33
1398 10:01:15.792297
1399 10:01:15.795777 [CBTSetCACLKResult] CA Dly = 33
1400 10:01:15.795857 CS Dly: 5 (0~36)
1401 10:01:15.795920 ==
1402 10:01:15.799018 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 10:01:15.805797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 10:01:15.805877 ==
1405 10:01:15.809169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 10:01:15.815915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 10:01:15.825228 [CA 0] Center 37 (6~68) winsize 63
1408 10:01:15.828408 [CA 1] Center 37 (6~68) winsize 63
1409 10:01:15.831807 [CA 2] Center 35 (5~66) winsize 62
1410 10:01:15.835090 [CA 3] Center 34 (4~65) winsize 62
1411 10:01:15.838574 [CA 4] Center 34 (4~65) winsize 62
1412 10:01:15.842207 [CA 5] Center 34 (4~65) winsize 62
1413 10:01:15.842295
1414 10:01:15.845065 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 10:01:15.845147
1416 10:01:15.849017 [CATrainingPosCal] consider 2 rank data
1417 10:01:15.852058 u2DelayCellTimex100 = 270/100 ps
1418 10:01:15.855954 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 10:01:15.859652 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 10:01:15.863607 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1421 10:01:15.867442 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 10:01:15.870864 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 10:01:15.874847 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 10:01:15.874954
1425 10:01:15.878423 CA PerBit enable=1, Macro0, CA PI delay=34
1426 10:01:15.878505
1427 10:01:15.882295 [CBTSetCACLKResult] CA Dly = 34
1428 10:01:15.882393 CS Dly: 6 (0~38)
1429 10:01:15.882458
1430 10:01:15.885962 ----->DramcWriteLeveling(PI) begin...
1431 10:01:15.886045 ==
1432 10:01:15.889301 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 10:01:15.892894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 10:01:15.896124 ==
1435 10:01:15.899206 Write leveling (Byte 0): 29 => 29
1436 10:01:15.899289 Write leveling (Byte 1): 30 => 30
1437 10:01:15.902475 DramcWriteLeveling(PI) end<-----
1438 10:01:15.902556
1439 10:01:15.902620 ==
1440 10:01:15.905806 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 10:01:15.912771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 10:01:15.912867 ==
1443 10:01:15.916425 [Gating] SW mode calibration
1444 10:01:15.922777 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 10:01:15.926228 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 10:01:15.929201 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 10:01:15.936357 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1448 10:01:15.939349 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 10:01:15.943114 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 10:01:15.949272 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 10:01:15.952626 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 10:01:15.956287 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 10:01:15.963182 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 10:01:15.966072 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 10:01:15.969557 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 10:01:15.976279 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 10:01:15.979380 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 10:01:15.983005 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 10:01:15.989494 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 10:01:15.992708 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 10:01:15.996064 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1462 10:01:15.999785 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 10:01:16.006125 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1464 10:01:16.009490 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1465 10:01:16.013069 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 10:01:16.020029 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 10:01:16.022878 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 10:01:16.026190 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 10:01:16.033298 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 10:01:16.036231 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 10:01:16.040082 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
1472 10:01:16.046361 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 10:01:16.050198 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 10:01:16.052986 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 10:01:16.059754 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 10:01:16.063356 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 10:01:16.066497 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 10:01:16.070104 0 10 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1479 10:01:16.076430 0 10 4 | B1->B0 | 2f2f 2b2b | 1 1 | (1 0) (1 0)
1480 10:01:16.079886 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 10:01:16.083603 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 10:01:16.090097 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 10:01:16.093316 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 10:01:16.096778 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 10:01:16.103688 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 10:01:16.107194 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1487 10:01:16.110400 0 11 4 | B1->B0 | 2e2e 3535 | 0 0 | (0 0) (0 0)
1488 10:01:16.116966 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1489 10:01:16.120321 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 10:01:16.123647 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 10:01:16.130349 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 10:01:16.133602 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 10:01:16.136905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 10:01:16.140294 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 10:01:16.146818 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1496 10:01:16.150346 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1497 10:01:16.153525 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 10:01:16.160390 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 10:01:16.163761 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 10:01:16.167145 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 10:01:16.174010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 10:01:16.177335 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 10:01:16.180408 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 10:01:16.186846 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 10:01:16.190422 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 10:01:16.193688 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 10:01:16.200476 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 10:01:16.203770 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 10:01:16.207377 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 10:01:16.210698 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1511 10:01:16.217348 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1512 10:01:16.220596 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 10:01:16.224306 Total UI for P1: 0, mck2ui 16
1514 10:01:16.227443 best dqsien dly found for B0: ( 0, 14, 2)
1515 10:01:16.230509 Total UI for P1: 0, mck2ui 16
1516 10:01:16.234033 best dqsien dly found for B1: ( 0, 14, 4)
1517 10:01:16.237328 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1518 10:01:16.240635 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1519 10:01:16.240733
1520 10:01:16.243862 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1521 10:01:16.247183 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1522 10:01:16.250725 [Gating] SW calibration Done
1523 10:01:16.250830 ==
1524 10:01:16.254199 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 10:01:16.257141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 10:01:16.260565 ==
1527 10:01:16.260648 RX Vref Scan: 0
1528 10:01:16.260713
1529 10:01:16.264035 RX Vref 0 -> 0, step: 1
1530 10:01:16.264118
1531 10:01:16.267162 RX Delay -130 -> 252, step: 16
1532 10:01:16.271004 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1533 10:01:16.274118 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1534 10:01:16.277204 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1535 10:01:16.280589 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1536 10:01:16.284105 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1537 10:01:16.290687 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1538 10:01:16.294018 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1539 10:01:16.297379 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1540 10:01:16.300996 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1541 10:01:16.303875 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1542 10:01:16.310565 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1543 10:01:16.314166 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1544 10:01:16.317696 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1545 10:01:16.320694 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1546 10:01:16.324326 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1547 10:01:16.330696 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1548 10:01:16.330820 ==
1549 10:01:16.334512 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 10:01:16.337376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 10:01:16.337498 ==
1552 10:01:16.337609 DQS Delay:
1553 10:01:16.340636 DQS0 = 0, DQS1 = 0
1554 10:01:16.340758 DQM Delay:
1555 10:01:16.344432 DQM0 = 88, DQM1 = 80
1556 10:01:16.344552 DQ Delay:
1557 10:01:16.347560 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1558 10:01:16.350807 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1559 10:01:16.354392 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1560 10:01:16.357472 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 10:01:16.357597
1562 10:01:16.357711
1563 10:01:16.357817 ==
1564 10:01:16.361023 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 10:01:16.364698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 10:01:16.364825 ==
1567 10:01:16.367623
1568 10:01:16.367749
1569 10:01:16.367860 TX Vref Scan disable
1570 10:01:16.370721 == TX Byte 0 ==
1571 10:01:16.374274 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1572 10:01:16.377420 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1573 10:01:16.380903 == TX Byte 1 ==
1574 10:01:16.384315 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1575 10:01:16.387477 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1576 10:01:16.387559 ==
1577 10:01:16.391026 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 10:01:16.397697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 10:01:16.397805 ==
1580 10:01:16.409191 TX Vref=22, minBit 15, minWin=26, winSum=451
1581 10:01:16.412426 TX Vref=24, minBit 10, minWin=27, winSum=452
1582 10:01:16.415720 TX Vref=26, minBit 15, minWin=27, winSum=458
1583 10:01:16.419288 TX Vref=28, minBit 1, minWin=28, winSum=457
1584 10:01:16.422642 TX Vref=30, minBit 8, minWin=28, winSum=458
1585 10:01:16.429129 TX Vref=32, minBit 12, minWin=27, winSum=455
1586 10:01:16.433038 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
1587 10:01:16.433147
1588 10:01:16.436716 Final TX Range 1 Vref 30
1589 10:01:16.436836
1590 10:01:16.436902 ==
1591 10:01:16.440146 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 10:01:16.443443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 10:01:16.443527 ==
1594 10:01:16.443591
1595 10:01:16.443650
1596 10:01:16.446547 TX Vref Scan disable
1597 10:01:16.450160 == TX Byte 0 ==
1598 10:01:16.453590 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1599 10:01:16.456969 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1600 10:01:16.460160 == TX Byte 1 ==
1601 10:01:16.463415 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1602 10:01:16.466986 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1603 10:01:16.467069
1604 10:01:16.470161 [DATLAT]
1605 10:01:16.470242 Freq=800, CH1 RK0
1606 10:01:16.470307
1607 10:01:16.473544 DATLAT Default: 0xa
1608 10:01:16.473627 0, 0xFFFF, sum = 0
1609 10:01:16.477006 1, 0xFFFF, sum = 0
1610 10:01:16.477089 2, 0xFFFF, sum = 0
1611 10:01:16.480091 3, 0xFFFF, sum = 0
1612 10:01:16.480175 4, 0xFFFF, sum = 0
1613 10:01:16.483679 5, 0xFFFF, sum = 0
1614 10:01:16.483762 6, 0xFFFF, sum = 0
1615 10:01:16.486983 7, 0xFFFF, sum = 0
1616 10:01:16.487067 8, 0xFFFF, sum = 0
1617 10:01:16.490092 9, 0x0, sum = 1
1618 10:01:16.490175 10, 0x0, sum = 2
1619 10:01:16.493574 11, 0x0, sum = 3
1620 10:01:16.493657 12, 0x0, sum = 4
1621 10:01:16.497079 best_step = 10
1622 10:01:16.497206
1623 10:01:16.497317 ==
1624 10:01:16.500352 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 10:01:16.503700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 10:01:16.503823 ==
1627 10:01:16.503935 RX Vref Scan: 1
1628 10:01:16.504044
1629 10:01:16.507021 Set Vref Range= 32 -> 127
1630 10:01:16.507142
1631 10:01:16.510284 RX Vref 32 -> 127, step: 1
1632 10:01:16.510403
1633 10:01:16.513632 RX Delay -95 -> 252, step: 8
1634 10:01:16.513751
1635 10:01:16.517225 Set Vref, RX VrefLevel [Byte0]: 32
1636 10:01:16.520380 [Byte1]: 32
1637 10:01:16.520482
1638 10:01:16.523754 Set Vref, RX VrefLevel [Byte0]: 33
1639 10:01:16.527059 [Byte1]: 33
1640 10:01:16.527155
1641 10:01:16.530376 Set Vref, RX VrefLevel [Byte0]: 34
1642 10:01:16.533553 [Byte1]: 34
1643 10:01:16.537259
1644 10:01:16.537340 Set Vref, RX VrefLevel [Byte0]: 35
1645 10:01:16.540563 [Byte1]: 35
1646 10:01:16.545188
1647 10:01:16.545270 Set Vref, RX VrefLevel [Byte0]: 36
1648 10:01:16.548243 [Byte1]: 36
1649 10:01:16.553046
1650 10:01:16.553128 Set Vref, RX VrefLevel [Byte0]: 37
1651 10:01:16.556023 [Byte1]: 37
1652 10:01:16.560124
1653 10:01:16.560206 Set Vref, RX VrefLevel [Byte0]: 38
1654 10:01:16.563686 [Byte1]: 38
1655 10:01:16.567703
1656 10:01:16.567786 Set Vref, RX VrefLevel [Byte0]: 39
1657 10:01:16.570981 [Byte1]: 39
1658 10:01:16.575612
1659 10:01:16.575694 Set Vref, RX VrefLevel [Byte0]: 40
1660 10:01:16.578724 [Byte1]: 40
1661 10:01:16.582774
1662 10:01:16.582856 Set Vref, RX VrefLevel [Byte0]: 41
1663 10:01:16.586450 [Byte1]: 41
1664 10:01:16.590672
1665 10:01:16.590752 Set Vref, RX VrefLevel [Byte0]: 42
1666 10:01:16.594041 [Byte1]: 42
1667 10:01:16.598078
1668 10:01:16.598159 Set Vref, RX VrefLevel [Byte0]: 43
1669 10:01:16.601271 [Byte1]: 43
1670 10:01:16.605801
1671 10:01:16.605882 Set Vref, RX VrefLevel [Byte0]: 44
1672 10:01:16.609015 [Byte1]: 44
1673 10:01:16.613129
1674 10:01:16.613211 Set Vref, RX VrefLevel [Byte0]: 45
1675 10:01:16.616527 [Byte1]: 45
1676 10:01:16.621044
1677 10:01:16.621125 Set Vref, RX VrefLevel [Byte0]: 46
1678 10:01:16.624074 [Byte1]: 46
1679 10:01:16.628484
1680 10:01:16.628566 Set Vref, RX VrefLevel [Byte0]: 47
1681 10:01:16.632023 [Byte1]: 47
1682 10:01:16.635975
1683 10:01:16.636056 Set Vref, RX VrefLevel [Byte0]: 48
1684 10:01:16.639640 [Byte1]: 48
1685 10:01:16.643759
1686 10:01:16.643840 Set Vref, RX VrefLevel [Byte0]: 49
1687 10:01:16.647290 [Byte1]: 49
1688 10:01:16.651260
1689 10:01:16.651343 Set Vref, RX VrefLevel [Byte0]: 50
1690 10:01:16.654630 [Byte1]: 50
1691 10:01:16.658726
1692 10:01:16.658807 Set Vref, RX VrefLevel [Byte0]: 51
1693 10:01:16.662049 [Byte1]: 51
1694 10:01:16.666354
1695 10:01:16.666435 Set Vref, RX VrefLevel [Byte0]: 52
1696 10:01:16.669865 [Byte1]: 52
1697 10:01:16.673914
1698 10:01:16.673995 Set Vref, RX VrefLevel [Byte0]: 53
1699 10:01:16.677417 [Byte1]: 53
1700 10:01:16.681913
1701 10:01:16.681996 Set Vref, RX VrefLevel [Byte0]: 54
1702 10:01:16.684940 [Byte1]: 54
1703 10:01:16.689137
1704 10:01:16.689219 Set Vref, RX VrefLevel [Byte0]: 55
1705 10:01:16.692639 [Byte1]: 55
1706 10:01:16.696818
1707 10:01:16.696926 Set Vref, RX VrefLevel [Byte0]: 56
1708 10:01:16.700300 [Byte1]: 56
1709 10:01:16.704342
1710 10:01:16.704439 Set Vref, RX VrefLevel [Byte0]: 57
1711 10:01:16.707687 [Byte1]: 57
1712 10:01:16.712715
1713 10:01:16.712812 Set Vref, RX VrefLevel [Byte0]: 58
1714 10:01:16.715476 [Byte1]: 58
1715 10:01:16.719889
1716 10:01:16.719972 Set Vref, RX VrefLevel [Byte0]: 59
1717 10:01:16.723010 [Byte1]: 59
1718 10:01:16.727328
1719 10:01:16.727411 Set Vref, RX VrefLevel [Byte0]: 60
1720 10:01:16.730641 [Byte1]: 60
1721 10:01:16.735080
1722 10:01:16.735162 Set Vref, RX VrefLevel [Byte0]: 61
1723 10:01:16.738070 [Byte1]: 61
1724 10:01:16.742529
1725 10:01:16.742615 Set Vref, RX VrefLevel [Byte0]: 62
1726 10:01:16.745896 [Byte1]: 62
1727 10:01:16.750095
1728 10:01:16.750178 Set Vref, RX VrefLevel [Byte0]: 63
1729 10:01:16.753196 [Byte1]: 63
1730 10:01:16.757900
1731 10:01:16.757983 Set Vref, RX VrefLevel [Byte0]: 64
1732 10:01:16.761027 [Byte1]: 64
1733 10:01:16.765178
1734 10:01:16.765260 Set Vref, RX VrefLevel [Byte0]: 65
1735 10:01:16.768756 [Byte1]: 65
1736 10:01:16.772694
1737 10:01:16.772787 Set Vref, RX VrefLevel [Byte0]: 66
1738 10:01:16.776448 [Byte1]: 66
1739 10:01:16.780320
1740 10:01:16.780403 Set Vref, RX VrefLevel [Byte0]: 67
1741 10:01:16.784010 [Byte1]: 67
1742 10:01:16.788109
1743 10:01:16.788217 Set Vref, RX VrefLevel [Byte0]: 68
1744 10:01:16.791345 [Byte1]: 68
1745 10:01:16.795737
1746 10:01:16.795845 Set Vref, RX VrefLevel [Byte0]: 69
1747 10:01:16.798854 [Byte1]: 69
1748 10:01:16.803444
1749 10:01:16.803541 Set Vref, RX VrefLevel [Byte0]: 70
1750 10:01:16.806415 [Byte1]: 70
1751 10:01:16.810791
1752 10:01:16.810873 Set Vref, RX VrefLevel [Byte0]: 71
1753 10:01:16.814180 [Byte1]: 71
1754 10:01:16.818627
1755 10:01:16.818709 Set Vref, RX VrefLevel [Byte0]: 72
1756 10:01:16.821614 [Byte1]: 72
1757 10:01:16.826166
1758 10:01:16.826249 Set Vref, RX VrefLevel [Byte0]: 73
1759 10:01:16.829219 [Byte1]: 73
1760 10:01:16.833647
1761 10:01:16.833730 Set Vref, RX VrefLevel [Byte0]: 74
1762 10:01:16.836897 [Byte1]: 74
1763 10:01:16.841258
1764 10:01:16.841340 Set Vref, RX VrefLevel [Byte0]: 75
1765 10:01:16.844403 [Byte1]: 75
1766 10:01:16.848798
1767 10:01:16.848881 Set Vref, RX VrefLevel [Byte0]: 76
1768 10:01:16.852350 [Byte1]: 76
1769 10:01:16.856380
1770 10:01:16.856462 Final RX Vref Byte 0 = 53 to rank0
1771 10:01:16.859887 Final RX Vref Byte 1 = 63 to rank0
1772 10:01:16.862945 Final RX Vref Byte 0 = 53 to rank1
1773 10:01:16.866534 Final RX Vref Byte 1 = 63 to rank1==
1774 10:01:16.869614 Dram Type= 6, Freq= 0, CH_1, rank 0
1775 10:01:16.876668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1776 10:01:16.876760 ==
1777 10:01:16.876845 DQS Delay:
1778 10:01:16.876924 DQS0 = 0, DQS1 = 0
1779 10:01:16.880214 DQM Delay:
1780 10:01:16.880297 DQM0 = 92, DQM1 = 82
1781 10:01:16.883028 DQ Delay:
1782 10:01:16.886893 DQ0 =92, DQ1 =88, DQ2 =84, DQ3 =88
1783 10:01:16.886978 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1784 10:01:16.889741 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1785 10:01:16.893600 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1786 10:01:16.896352
1787 10:01:16.896436
1788 10:01:16.903383 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1789 10:01:16.906558 CH1 RK0: MR19=606, MR18=2E4B
1790 10:01:16.913373 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1791 10:01:16.913458
1792 10:01:16.916582 ----->DramcWriteLeveling(PI) begin...
1793 10:01:16.916667 ==
1794 10:01:16.920042 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 10:01:16.923407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 10:01:16.923489 ==
1797 10:01:16.927057 Write leveling (Byte 0): 25 => 25
1798 10:01:16.929994 Write leveling (Byte 1): 30 => 30
1799 10:01:16.933285 DramcWriteLeveling(PI) end<-----
1800 10:01:16.933365
1801 10:01:16.933429 ==
1802 10:01:16.936714 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 10:01:16.939962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 10:01:16.940043 ==
1805 10:01:16.943335 [Gating] SW mode calibration
1806 10:01:16.950135 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1807 10:01:16.956605 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1808 10:01:16.959884 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1809 10:01:16.963531 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1810 10:01:16.970348 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 10:01:16.973475 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 10:01:16.976710 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 10:01:16.983693 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 10:01:16.987169 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 10:01:16.990134 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 10:01:16.993481 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 10:01:17.000246 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 10:01:17.003342 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 10:01:17.007092 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 10:01:17.013705 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 10:01:17.017254 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 10:01:17.020302 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 10:01:17.027002 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 10:01:17.030212 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 10:01:17.034133 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1826 10:01:17.040391 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 10:01:17.043718 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 10:01:17.047329 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 10:01:17.053835 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 10:01:17.056821 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 10:01:17.060183 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 10:01:17.063586 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 10:01:17.070230 0 9 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1834 10:01:17.073601 0 9 8 | B1->B0 | 3131 3333 | 1 1 | (1 1) (1 1)
1835 10:01:17.077481 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 10:01:17.084138 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 10:01:17.087056 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 10:01:17.090425 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 10:01:17.097102 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 10:01:17.100704 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1841 10:01:17.103827 0 10 4 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
1842 10:01:17.110302 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1843 10:01:17.113795 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 10:01:17.117024 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 10:01:17.123925 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 10:01:17.127321 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 10:01:17.130435 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 10:01:17.137133 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 10:01:17.140454 0 11 4 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (1 1)
1850 10:01:17.143683 0 11 8 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
1851 10:01:17.147240 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 10:01:17.154007 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 10:01:17.157203 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 10:01:17.160566 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 10:01:17.167206 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 10:01:17.170684 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 10:01:17.173910 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1858 10:01:17.180677 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 10:01:17.184143 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 10:01:17.187679 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 10:01:17.194069 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 10:01:17.197530 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 10:01:17.201136 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 10:01:17.207746 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 10:01:17.210920 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 10:01:17.214243 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 10:01:17.217677 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 10:01:17.224320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 10:01:17.227718 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 10:01:17.230905 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 10:01:17.237416 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 10:01:17.240907 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1873 10:01:17.244174 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1874 10:01:17.251088 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1875 10:01:17.254296 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 10:01:17.257762 Total UI for P1: 0, mck2ui 16
1877 10:01:17.260856 best dqsien dly found for B0: ( 0, 14, 6)
1878 10:01:17.264213 Total UI for P1: 0, mck2ui 16
1879 10:01:17.267783 best dqsien dly found for B1: ( 0, 14, 4)
1880 10:01:17.271198 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1881 10:01:17.274366 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1882 10:01:17.274448
1883 10:01:17.277698 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 10:01:17.280960 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1885 10:01:17.284240 [Gating] SW calibration Done
1886 10:01:17.284321 ==
1887 10:01:17.287871 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 10:01:17.291367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 10:01:17.291449 ==
1890 10:01:17.294390 RX Vref Scan: 0
1891 10:01:17.294472
1892 10:01:17.297580 RX Vref 0 -> 0, step: 1
1893 10:01:17.297662
1894 10:01:17.297725 RX Delay -130 -> 252, step: 16
1895 10:01:17.304476 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1896 10:01:17.307611 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1897 10:01:17.310942 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1898 10:01:17.314258 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1899 10:01:17.317650 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1900 10:01:17.324261 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1901 10:01:17.327910 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1902 10:01:17.331252 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1903 10:01:17.334391 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1904 10:01:17.338065 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1905 10:01:17.344659 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1906 10:01:17.347880 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1907 10:01:17.351603 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1908 10:01:17.354767 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1909 10:01:17.357900 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1910 10:01:17.364526 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1911 10:01:17.364622 ==
1912 10:01:17.368010 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 10:01:17.371367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 10:01:17.371449 ==
1915 10:01:17.371512 DQS Delay:
1916 10:01:17.374698 DQS0 = 0, DQS1 = 0
1917 10:01:17.374779 DQM Delay:
1918 10:01:17.377971 DQM0 = 89, DQM1 = 79
1919 10:01:17.378096 DQ Delay:
1920 10:01:17.381123 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1921 10:01:17.384706 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1922 10:01:17.387996 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
1923 10:01:17.391567 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1924 10:01:17.391648
1925 10:01:17.391711
1926 10:01:17.391770 ==
1927 10:01:17.394727 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 10:01:17.398174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 10:01:17.398256 ==
1930 10:01:17.398319
1931 10:01:17.398379
1932 10:01:17.401260 TX Vref Scan disable
1933 10:01:17.404581 == TX Byte 0 ==
1934 10:01:17.408085 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1935 10:01:17.411413 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1936 10:01:17.414616 == TX Byte 1 ==
1937 10:01:17.418103 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1938 10:01:17.421276 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1939 10:01:17.421379 ==
1940 10:01:17.424778 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 10:01:17.428162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 10:01:17.431060 ==
1943 10:01:17.443368 TX Vref=22, minBit 13, minWin=27, winSum=453
1944 10:01:17.446474 TX Vref=24, minBit 13, minWin=27, winSum=454
1945 10:01:17.449750 TX Vref=26, minBit 15, minWin=27, winSum=457
1946 10:01:17.453284 TX Vref=28, minBit 13, minWin=27, winSum=458
1947 10:01:17.456640 TX Vref=30, minBit 8, minWin=28, winSum=461
1948 10:01:17.463495 TX Vref=32, minBit 15, minWin=27, winSum=458
1949 10:01:17.466675 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1950 10:01:17.466757
1951 10:01:17.470124 Final TX Range 1 Vref 30
1952 10:01:17.470206
1953 10:01:17.470270 ==
1954 10:01:17.473543 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 10:01:17.476778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 10:01:17.476874 ==
1957 10:01:17.479989
1958 10:01:17.480070
1959 10:01:17.480133 TX Vref Scan disable
1960 10:01:17.483602 == TX Byte 0 ==
1961 10:01:17.486858 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1962 10:01:17.490107 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1963 10:01:17.493402 == TX Byte 1 ==
1964 10:01:17.496613 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1965 10:01:17.500398 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1966 10:01:17.503808
1967 10:01:17.503890 [DATLAT]
1968 10:01:17.503955 Freq=800, CH1 RK1
1969 10:01:17.504016
1970 10:01:17.506840 DATLAT Default: 0xa
1971 10:01:17.506923 0, 0xFFFF, sum = 0
1972 10:01:17.510243 1, 0xFFFF, sum = 0
1973 10:01:17.510325 2, 0xFFFF, sum = 0
1974 10:01:17.513822 3, 0xFFFF, sum = 0
1975 10:01:17.513904 4, 0xFFFF, sum = 0
1976 10:01:17.516865 5, 0xFFFF, sum = 0
1977 10:01:17.516948 6, 0xFFFF, sum = 0
1978 10:01:17.520507 7, 0xFFFF, sum = 0
1979 10:01:17.523496 8, 0xFFFF, sum = 0
1980 10:01:17.523579 9, 0x0, sum = 1
1981 10:01:17.523661 10, 0x0, sum = 2
1982 10:01:17.526952 11, 0x0, sum = 3
1983 10:01:17.527034 12, 0x0, sum = 4
1984 10:01:17.530498 best_step = 10
1985 10:01:17.530579
1986 10:01:17.530643 ==
1987 10:01:17.533575 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 10:01:17.536960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 10:01:17.537042 ==
1990 10:01:17.540404 RX Vref Scan: 0
1991 10:01:17.540487
1992 10:01:17.540552 RX Vref 0 -> 0, step: 1
1993 10:01:17.540626
1994 10:01:17.543372 RX Delay -95 -> 252, step: 8
1995 10:01:17.550119 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1996 10:01:17.553662 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1997 10:01:17.557003 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1998 10:01:17.560317 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1999 10:01:17.563501 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2000 10:01:17.570464 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2001 10:01:17.573522 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2002 10:01:17.577298 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2003 10:01:17.580371 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2004 10:01:17.583559 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2005 10:01:17.587158 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2006 10:01:17.593359 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2007 10:01:17.596737 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2008 10:01:17.600060 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2009 10:01:17.603474 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2010 10:01:17.610292 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2011 10:01:17.610375 ==
2012 10:01:17.613657 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 10:01:17.617044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 10:01:17.617128 ==
2015 10:01:17.617193 DQS Delay:
2016 10:01:17.620239 DQS0 = 0, DQS1 = 0
2017 10:01:17.620347 DQM Delay:
2018 10:01:17.623765 DQM0 = 92, DQM1 = 83
2019 10:01:17.623847 DQ Delay:
2020 10:01:17.627032 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2021 10:01:17.630604 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2022 10:01:17.633703 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2023 10:01:17.636895 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2024 10:01:17.636977
2025 10:01:17.637041
2026 10:01:17.643826 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2027 10:01:17.647065 CH1 RK1: MR19=606, MR18=3E13
2028 10:01:17.654007 CH1_RK1: MR19=0x606, MR18=0x3E13, DQSOSC=394, MR23=63, INC=95, DEC=63
2029 10:01:17.657095 [RxdqsGatingPostProcess] freq 800
2030 10:01:17.660658 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 10:01:17.663825 Pre-setting of DQS Precalculation
2032 10:01:17.670531 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 10:01:17.677383 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 10:01:17.684028 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 10:01:17.684113
2036 10:01:17.684210
2037 10:01:17.687185 [Calibration Summary] 1600 Mbps
2038 10:01:17.690432 CH 0, Rank 0
2039 10:01:17.690515 SW Impedance : PASS
2040 10:01:17.693837 DUTY Scan : NO K
2041 10:01:17.693920 ZQ Calibration : PASS
2042 10:01:17.697241 Jitter Meter : NO K
2043 10:01:17.700480 CBT Training : PASS
2044 10:01:17.700563 Write leveling : PASS
2045 10:01:17.703977 RX DQS gating : PASS
2046 10:01:17.707035 RX DQ/DQS(RDDQC) : PASS
2047 10:01:17.707117 TX DQ/DQS : PASS
2048 10:01:17.710680 RX DATLAT : PASS
2049 10:01:17.713796 RX DQ/DQS(Engine): PASS
2050 10:01:17.713879 TX OE : NO K
2051 10:01:17.717376 All Pass.
2052 10:01:17.717459
2053 10:01:17.717524 CH 0, Rank 1
2054 10:01:17.720622 SW Impedance : PASS
2055 10:01:17.720705 DUTY Scan : NO K
2056 10:01:17.724013 ZQ Calibration : PASS
2057 10:01:17.727523 Jitter Meter : NO K
2058 10:01:17.727643 CBT Training : PASS
2059 10:01:17.730682 Write leveling : PASS
2060 10:01:17.730810 RX DQS gating : PASS
2061 10:01:17.734067 RX DQ/DQS(RDDQC) : PASS
2062 10:01:17.737200 TX DQ/DQS : PASS
2063 10:01:17.737326 RX DATLAT : PASS
2064 10:01:17.740778 RX DQ/DQS(Engine): PASS
2065 10:01:17.744026 TX OE : NO K
2066 10:01:17.744147 All Pass.
2067 10:01:17.744262
2068 10:01:17.744372 CH 1, Rank 0
2069 10:01:17.747581 SW Impedance : PASS
2070 10:01:17.750741 DUTY Scan : NO K
2071 10:01:17.750861 ZQ Calibration : PASS
2072 10:01:17.753979 Jitter Meter : NO K
2073 10:01:17.757372 CBT Training : PASS
2074 10:01:17.757488 Write leveling : PASS
2075 10:01:17.760780 RX DQS gating : PASS
2076 10:01:17.764062 RX DQ/DQS(RDDQC) : PASS
2077 10:01:17.764178 TX DQ/DQS : PASS
2078 10:01:17.767402 RX DATLAT : PASS
2079 10:01:17.767523 RX DQ/DQS(Engine): PASS
2080 10:01:17.771085 TX OE : NO K
2081 10:01:17.771210 All Pass.
2082 10:01:17.771319
2083 10:01:17.773886 CH 1, Rank 1
2084 10:01:17.774002 SW Impedance : PASS
2085 10:01:17.777433 DUTY Scan : NO K
2086 10:01:17.780835 ZQ Calibration : PASS
2087 10:01:17.780953 Jitter Meter : NO K
2088 10:01:17.784124 CBT Training : PASS
2089 10:01:17.787373 Write leveling : PASS
2090 10:01:17.787496 RX DQS gating : PASS
2091 10:01:17.790561 RX DQ/DQS(RDDQC) : PASS
2092 10:01:17.794001 TX DQ/DQS : PASS
2093 10:01:17.794122 RX DATLAT : PASS
2094 10:01:17.797264 RX DQ/DQS(Engine): PASS
2095 10:01:17.800745 TX OE : NO K
2096 10:01:17.800885 All Pass.
2097 10:01:17.800994
2098 10:01:17.801100 DramC Write-DBI off
2099 10:01:17.804246 PER_BANK_REFRESH: Hybrid Mode
2100 10:01:17.807604 TX_TRACKING: ON
2101 10:01:17.810813 [GetDramInforAfterCalByMRR] Vendor 6.
2102 10:01:17.814108 [GetDramInforAfterCalByMRR] Revision 606.
2103 10:01:17.817302 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 10:01:17.817421 MR0 0x3b3b
2105 10:01:17.820698 MR8 0x5151
2106 10:01:17.824118 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 10:01:17.824240
2108 10:01:17.824350 MR0 0x3b3b
2109 10:01:17.824457 MR8 0x5151
2110 10:01:17.827277 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 10:01:17.830890
2112 10:01:17.837501 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 10:01:17.840974 [FAST_K] Save calibration result to emmc
2114 10:01:17.844045 [FAST_K] Save calibration result to emmc
2115 10:01:17.847315 dram_init: config_dvfs: 1
2116 10:01:17.850807 dramc_set_vcore_voltage set vcore to 662500
2117 10:01:17.853998 Read voltage for 1200, 2
2118 10:01:17.854082 Vio18 = 0
2119 10:01:17.857689 Vcore = 662500
2120 10:01:17.857763 Vdram = 0
2121 10:01:17.857829 Vddq = 0
2122 10:01:17.857888 Vmddr = 0
2123 10:01:17.864174 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 10:01:17.867704 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 10:01:17.870849 MEM_TYPE=3, freq_sel=15
2126 10:01:17.874033 sv_algorithm_assistance_LP4_1600
2127 10:01:17.877450 ============ PULL DRAM RESETB DOWN ============
2128 10:01:17.884328 ========== PULL DRAM RESETB DOWN end =========
2129 10:01:17.887799 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 10:01:17.890877 ===================================
2131 10:01:17.894507 LPDDR4 DRAM CONFIGURATION
2132 10:01:17.897702 ===================================
2133 10:01:17.897800 EX_ROW_EN[0] = 0x0
2134 10:01:17.900795 EX_ROW_EN[1] = 0x0
2135 10:01:17.900878 LP4Y_EN = 0x0
2136 10:01:17.904375 WORK_FSP = 0x0
2137 10:01:17.904471 WL = 0x4
2138 10:01:17.907622 RL = 0x4
2139 10:01:17.907705 BL = 0x2
2140 10:01:17.910781 RPST = 0x0
2141 10:01:17.910863 RD_PRE = 0x0
2142 10:01:17.914169 WR_PRE = 0x1
2143 10:01:17.914251 WR_PST = 0x0
2144 10:01:17.917785 DBI_WR = 0x0
2145 10:01:17.917868 DBI_RD = 0x0
2146 10:01:17.920833 OTF = 0x1
2147 10:01:17.924480 ===================================
2148 10:01:17.927739 ===================================
2149 10:01:17.927823 ANA top config
2150 10:01:17.930960 ===================================
2151 10:01:17.934587 DLL_ASYNC_EN = 0
2152 10:01:17.937497 ALL_SLAVE_EN = 0
2153 10:01:17.941033 NEW_RANK_MODE = 1
2154 10:01:17.941116 DLL_IDLE_MODE = 1
2155 10:01:17.944622 LP45_APHY_COMB_EN = 1
2156 10:01:17.947745 TX_ODT_DIS = 1
2157 10:01:17.951134 NEW_8X_MODE = 1
2158 10:01:17.954370 ===================================
2159 10:01:17.957523 ===================================
2160 10:01:17.960896 data_rate = 2400
2161 10:01:17.960989 CKR = 1
2162 10:01:17.964423 DQ_P2S_RATIO = 8
2163 10:01:17.967585 ===================================
2164 10:01:17.971144 CA_P2S_RATIO = 8
2165 10:01:17.974375 DQ_CA_OPEN = 0
2166 10:01:17.977689 DQ_SEMI_OPEN = 0
2167 10:01:17.981274 CA_SEMI_OPEN = 0
2168 10:01:17.981357 CA_FULL_RATE = 0
2169 10:01:17.984531 DQ_CKDIV4_EN = 0
2170 10:01:17.987704 CA_CKDIV4_EN = 0
2171 10:01:17.991389 CA_PREDIV_EN = 0
2172 10:01:17.994690 PH8_DLY = 17
2173 10:01:17.994788 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 10:01:17.997970 DQ_AAMCK_DIV = 4
2175 10:01:18.001276 CA_AAMCK_DIV = 4
2176 10:01:18.004450 CA_ADMCK_DIV = 4
2177 10:01:18.007847 DQ_TRACK_CA_EN = 0
2178 10:01:18.011441 CA_PICK = 1200
2179 10:01:18.014695 CA_MCKIO = 1200
2180 10:01:18.014779 MCKIO_SEMI = 0
2181 10:01:18.018074 PLL_FREQ = 2366
2182 10:01:18.021156 DQ_UI_PI_RATIO = 32
2183 10:01:18.024630 CA_UI_PI_RATIO = 0
2184 10:01:18.027843 ===================================
2185 10:01:18.031161 ===================================
2186 10:01:18.034587 memory_type:LPDDR4
2187 10:01:18.034670 GP_NUM : 10
2188 10:01:18.038199 SRAM_EN : 1
2189 10:01:18.038282 MD32_EN : 0
2190 10:01:18.041259 ===================================
2191 10:01:18.044812 [ANA_INIT] >>>>>>>>>>>>>>
2192 10:01:18.047997 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 10:01:18.051608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 10:01:18.054882 ===================================
2195 10:01:18.058073 data_rate = 2400,PCW = 0X5b00
2196 10:01:18.061483 ===================================
2197 10:01:18.064686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 10:01:18.071288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 10:01:18.074869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 10:01:18.081909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 10:01:18.084891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 10:01:18.088040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 10:01:18.088163 [ANA_INIT] flow start
2204 10:01:18.091476 [ANA_INIT] PLL >>>>>>>>
2205 10:01:18.094718 [ANA_INIT] PLL <<<<<<<<
2206 10:01:18.094820 [ANA_INIT] MIDPI >>>>>>>>
2207 10:01:18.098485 [ANA_INIT] MIDPI <<<<<<<<
2208 10:01:18.101586 [ANA_INIT] DLL >>>>>>>>
2209 10:01:18.101686 [ANA_INIT] DLL <<<<<<<<
2210 10:01:18.104705 [ANA_INIT] flow end
2211 10:01:18.108089 ============ LP4 DIFF to SE enter ============
2212 10:01:18.111470 ============ LP4 DIFF to SE exit ============
2213 10:01:18.114924 [ANA_INIT] <<<<<<<<<<<<<
2214 10:01:18.118265 [Flow] Enable top DCM control >>>>>
2215 10:01:18.121670 [Flow] Enable top DCM control <<<<<
2216 10:01:18.124928 Enable DLL master slave shuffle
2217 10:01:18.131609 ==============================================================
2218 10:01:18.131714 Gating Mode config
2219 10:01:18.138547 ==============================================================
2220 10:01:18.138620 Config description:
2221 10:01:18.148458 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 10:01:18.155030 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 10:01:18.162155 SELPH_MODE 0: By rank 1: By Phase
2224 10:01:18.165207 ==============================================================
2225 10:01:18.168485 GAT_TRACK_EN = 1
2226 10:01:18.171940 RX_GATING_MODE = 2
2227 10:01:18.175186 RX_GATING_TRACK_MODE = 2
2228 10:01:18.178661 SELPH_MODE = 1
2229 10:01:18.181946 PICG_EARLY_EN = 1
2230 10:01:18.185336 VALID_LAT_VALUE = 1
2231 10:01:18.188444 ==============================================================
2232 10:01:18.191929 Enter into Gating configuration >>>>
2233 10:01:18.195127 Exit from Gating configuration <<<<
2234 10:01:18.198939 Enter into DVFS_PRE_config >>>>>
2235 10:01:18.208877 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 10:01:18.212111 Exit from DVFS_PRE_config <<<<<
2237 10:01:18.215635 Enter into PICG configuration >>>>
2238 10:01:18.219070 Exit from PICG configuration <<<<
2239 10:01:18.222360 [RX_INPUT] configuration >>>>>
2240 10:01:18.225617 [RX_INPUT] configuration <<<<<
2241 10:01:18.232098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 10:01:18.235644 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 10:01:18.242584 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 10:01:18.248641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 10:01:18.255240 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 10:01:18.261961 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 10:01:18.265317 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 10:01:18.268868 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 10:01:18.272217 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 10:01:18.275606 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 10:01:18.282595 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 10:01:18.285959 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 10:01:18.289059 ===================================
2254 10:01:18.292414 LPDDR4 DRAM CONFIGURATION
2255 10:01:18.295801 ===================================
2256 10:01:18.295900 EX_ROW_EN[0] = 0x0
2257 10:01:18.298949 EX_ROW_EN[1] = 0x0
2258 10:01:18.299036 LP4Y_EN = 0x0
2259 10:01:18.302168 WORK_FSP = 0x0
2260 10:01:18.302252 WL = 0x4
2261 10:01:18.305566 RL = 0x4
2262 10:01:18.305648 BL = 0x2
2263 10:01:18.308964 RPST = 0x0
2264 10:01:18.309046 RD_PRE = 0x0
2265 10:01:18.312183 WR_PRE = 0x1
2266 10:01:18.312265 WR_PST = 0x0
2267 10:01:18.315764 DBI_WR = 0x0
2268 10:01:18.319512 DBI_RD = 0x0
2269 10:01:18.319594 OTF = 0x1
2270 10:01:18.322383 ===================================
2271 10:01:18.325632 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 10:01:18.329388 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 10:01:18.335930 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 10:01:18.339344 ===================================
2275 10:01:18.339428 LPDDR4 DRAM CONFIGURATION
2276 10:01:18.342405 ===================================
2277 10:01:18.345741 EX_ROW_EN[0] = 0x10
2278 10:01:18.349234 EX_ROW_EN[1] = 0x0
2279 10:01:18.349331 LP4Y_EN = 0x0
2280 10:01:18.352367 WORK_FSP = 0x0
2281 10:01:18.352464 WL = 0x4
2282 10:01:18.355997 RL = 0x4
2283 10:01:18.356094 BL = 0x2
2284 10:01:18.359392 RPST = 0x0
2285 10:01:18.359488 RD_PRE = 0x0
2286 10:01:18.362613 WR_PRE = 0x1
2287 10:01:18.362710 WR_PST = 0x0
2288 10:01:18.365894 DBI_WR = 0x0
2289 10:01:18.365992 DBI_RD = 0x0
2290 10:01:18.369412 OTF = 0x1
2291 10:01:18.372552 ===================================
2292 10:01:18.379364 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 10:01:18.379448 ==
2294 10:01:18.382852 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 10:01:18.385874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 10:01:18.385958 ==
2297 10:01:18.389472 [Duty_Offset_Calibration]
2298 10:01:18.389553 B0:2 B1:0 CA:1
2299 10:01:18.389616
2300 10:01:18.392547 [DutyScan_Calibration_Flow] k_type=0
2301 10:01:18.401951
2302 10:01:18.402033 ==CLK 0==
2303 10:01:18.405545 Final CLK duty delay cell = -4
2304 10:01:18.408675 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2305 10:01:18.411753 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2306 10:01:18.415454 [-4] AVG Duty = 4953%(X100)
2307 10:01:18.415536
2308 10:01:18.418803 CH0 CLK Duty spec in!! Max-Min= 156%
2309 10:01:18.422164 [DutyScan_Calibration_Flow] ====Done====
2310 10:01:18.422246
2311 10:01:18.425407 [DutyScan_Calibration_Flow] k_type=1
2312 10:01:18.441020
2313 10:01:18.441109 ==DQS 0 ==
2314 10:01:18.444217 Final DQS duty delay cell = 0
2315 10:01:18.447253 [0] MAX Duty = 5187%(X100), DQS PI = 30
2316 10:01:18.450674 [0] MIN Duty = 4938%(X100), DQS PI = 0
2317 10:01:18.450755 [0] AVG Duty = 5062%(X100)
2318 10:01:18.454241
2319 10:01:18.454321 ==DQS 1 ==
2320 10:01:18.457407 Final DQS duty delay cell = -4
2321 10:01:18.461071 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2322 10:01:18.464133 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2323 10:01:18.467651 [-4] AVG Duty = 5031%(X100)
2324 10:01:18.467732
2325 10:01:18.470777 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2326 10:01:18.470858
2327 10:01:18.474373 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2328 10:01:18.477759 [DutyScan_Calibration_Flow] ====Done====
2329 10:01:18.477840
2330 10:01:18.481100 [DutyScan_Calibration_Flow] k_type=3
2331 10:01:18.496885
2332 10:01:18.496964 ==DQM 0 ==
2333 10:01:18.499908 Final DQM duty delay cell = 0
2334 10:01:18.503324 [0] MAX Duty = 5062%(X100), DQS PI = 24
2335 10:01:18.506718 [0] MIN Duty = 4844%(X100), DQS PI = 2
2336 10:01:18.506799 [0] AVG Duty = 4953%(X100)
2337 10:01:18.510178
2338 10:01:18.510256 ==DQM 1 ==
2339 10:01:18.513485 Final DQM duty delay cell = -4
2340 10:01:18.516502 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2341 10:01:18.520110 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2342 10:01:18.523463 [-4] AVG Duty = 4906%(X100)
2343 10:01:18.523575
2344 10:01:18.526770 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2345 10:01:18.526851
2346 10:01:18.530008 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2347 10:01:18.533611 [DutyScan_Calibration_Flow] ====Done====
2348 10:01:18.533723
2349 10:01:18.536883 [DutyScan_Calibration_Flow] k_type=2
2350 10:01:18.553560
2351 10:01:18.553647 ==DQ 0 ==
2352 10:01:18.556817 Final DQ duty delay cell = -4
2353 10:01:18.560140 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2354 10:01:18.563763 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2355 10:01:18.566974 [-4] AVG Duty = 4969%(X100)
2356 10:01:18.567057
2357 10:01:18.567122 ==DQ 1 ==
2358 10:01:18.570502 Final DQ duty delay cell = 4
2359 10:01:18.573826 [4] MAX Duty = 5093%(X100), DQS PI = 4
2360 10:01:18.576833 [4] MIN Duty = 5031%(X100), DQS PI = 0
2361 10:01:18.576916 [4] AVG Duty = 5062%(X100)
2362 10:01:18.577019
2363 10:01:18.580239 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2364 10:01:18.583592
2365 10:01:18.587236 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2366 10:01:18.590336 [DutyScan_Calibration_Flow] ====Done====
2367 10:01:18.590421 ==
2368 10:01:18.593394 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 10:01:18.597075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 10:01:18.597160 ==
2371 10:01:18.600394 [Duty_Offset_Calibration]
2372 10:01:18.600505 B0:0 B1:-1 CA:2
2373 10:01:18.600607
2374 10:01:18.603288 [DutyScan_Calibration_Flow] k_type=0
2375 10:01:18.613411
2376 10:01:18.613494 ==CLK 0==
2377 10:01:18.617050 Final CLK duty delay cell = 0
2378 10:01:18.620079 [0] MAX Duty = 5156%(X100), DQS PI = 16
2379 10:01:18.623646 [0] MIN Duty = 4938%(X100), DQS PI = 44
2380 10:01:18.623730 [0] AVG Duty = 5047%(X100)
2381 10:01:18.623823
2382 10:01:18.627230 CH1 CLK Duty spec in!! Max-Min= 218%
2383 10:01:18.633752 [DutyScan_Calibration_Flow] ====Done====
2384 10:01:18.633880
2385 10:01:18.636940 [DutyScan_Calibration_Flow] k_type=1
2386 10:01:18.653173
2387 10:01:18.653301 ==DQS 0 ==
2388 10:01:18.656399 Final DQS duty delay cell = 0
2389 10:01:18.659694 [0] MAX Duty = 5093%(X100), DQS PI = 22
2390 10:01:18.662789 [0] MIN Duty = 4969%(X100), DQS PI = 0
2391 10:01:18.662912 [0] AVG Duty = 5031%(X100)
2392 10:01:18.666470
2393 10:01:18.666593 ==DQS 1 ==
2394 10:01:18.669491 Final DQS duty delay cell = 0
2395 10:01:18.672918 [0] MAX Duty = 5156%(X100), DQS PI = 0
2396 10:01:18.676573 [0] MIN Duty = 4875%(X100), DQS PI = 34
2397 10:01:18.676693 [0] AVG Duty = 5015%(X100)
2398 10:01:18.676847
2399 10:01:18.682951 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2400 10:01:18.683073
2401 10:01:18.686431 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2402 10:01:18.689630 [DutyScan_Calibration_Flow] ====Done====
2403 10:01:18.689750
2404 10:01:18.692818 [DutyScan_Calibration_Flow] k_type=3
2405 10:01:18.709462
2406 10:01:18.709584 ==DQM 0 ==
2407 10:01:18.712911 Final DQM duty delay cell = 4
2408 10:01:18.716443 [4] MAX Duty = 5124%(X100), DQS PI = 22
2409 10:01:18.719566 [4] MIN Duty = 4969%(X100), DQS PI = 28
2410 10:01:18.719677 [4] AVG Duty = 5046%(X100)
2411 10:01:18.722613
2412 10:01:18.722694 ==DQM 1 ==
2413 10:01:18.726003 Final DQM duty delay cell = -4
2414 10:01:18.729661 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2415 10:01:18.732985 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2416 10:01:18.736299 [-4] AVG Duty = 4875%(X100)
2417 10:01:18.736381
2418 10:01:18.740118 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2419 10:01:18.740200
2420 10:01:18.743010 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2421 10:01:18.746312 [DutyScan_Calibration_Flow] ====Done====
2422 10:01:18.746394
2423 10:01:18.749464 [DutyScan_Calibration_Flow] k_type=2
2424 10:01:18.766354
2425 10:01:18.766436 ==DQ 0 ==
2426 10:01:18.769512 Final DQ duty delay cell = 0
2427 10:01:18.773132 [0] MAX Duty = 5062%(X100), DQS PI = 20
2428 10:01:18.776400 [0] MIN Duty = 4938%(X100), DQS PI = 0
2429 10:01:18.776482 [0] AVG Duty = 5000%(X100)
2430 10:01:18.776548
2431 10:01:18.779802 ==DQ 1 ==
2432 10:01:18.783047 Final DQ duty delay cell = 0
2433 10:01:18.786511 [0] MAX Duty = 5062%(X100), DQS PI = 2
2434 10:01:18.789674 [0] MIN Duty = 4813%(X100), DQS PI = 36
2435 10:01:18.789756 [0] AVG Duty = 4937%(X100)
2436 10:01:18.789821
2437 10:01:18.793033 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2438 10:01:18.793115
2439 10:01:18.796473 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2440 10:01:18.803104 [DutyScan_Calibration_Flow] ====Done====
2441 10:01:18.806165 nWR fixed to 30
2442 10:01:18.806248 [ModeRegInit_LP4] CH0 RK0
2443 10:01:18.809752 [ModeRegInit_LP4] CH0 RK1
2444 10:01:18.812958 [ModeRegInit_LP4] CH1 RK0
2445 10:01:18.813041 [ModeRegInit_LP4] CH1 RK1
2446 10:01:18.816320 match AC timing 7
2447 10:01:18.819757 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 10:01:18.823041 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 10:01:18.829859 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 10:01:18.833638 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 10:01:18.839804 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 10:01:18.839887 ==
2453 10:01:18.843249 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 10:01:18.846590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 10:01:18.846669 ==
2456 10:01:18.853202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 10:01:18.856312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2458 10:01:18.866136 [CA 0] Center 38 (7~69) winsize 63
2459 10:01:18.869486 [CA 1] Center 38 (8~69) winsize 62
2460 10:01:18.872688 [CA 2] Center 35 (5~66) winsize 62
2461 10:01:18.876399 [CA 3] Center 35 (4~66) winsize 63
2462 10:01:18.879688 [CA 4] Center 34 (4~65) winsize 62
2463 10:01:18.882742 [CA 5] Center 33 (3~63) winsize 61
2464 10:01:18.882864
2465 10:01:18.886364 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2466 10:01:18.886449
2467 10:01:18.889507 [CATrainingPosCal] consider 1 rank data
2468 10:01:18.892920 u2DelayCellTimex100 = 270/100 ps
2469 10:01:18.896084 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2470 10:01:18.899982 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2471 10:01:18.906289 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2472 10:01:18.909516 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2473 10:01:18.913009 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2474 10:01:18.916619 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2475 10:01:18.916706
2476 10:01:18.919616 CA PerBit enable=1, Macro0, CA PI delay=33
2477 10:01:18.919700
2478 10:01:18.923073 [CBTSetCACLKResult] CA Dly = 33
2479 10:01:18.923172 CS Dly: 6 (0~37)
2480 10:01:18.923255 ==
2481 10:01:18.926635 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 10:01:18.933180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 10:01:18.933265 ==
2484 10:01:18.936320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 10:01:18.943087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2486 10:01:18.951654 [CA 0] Center 39 (8~70) winsize 63
2487 10:01:18.955375 [CA 1] Center 38 (8~69) winsize 62
2488 10:01:18.958474 [CA 2] Center 35 (5~66) winsize 62
2489 10:01:18.961993 [CA 3] Center 35 (5~66) winsize 62
2490 10:01:18.965086 [CA 4] Center 34 (4~65) winsize 62
2491 10:01:18.968609 [CA 5] Center 34 (4~64) winsize 61
2492 10:01:18.968710
2493 10:01:18.971794 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2494 10:01:18.971891
2495 10:01:18.975489 [CATrainingPosCal] consider 2 rank data
2496 10:01:18.978419 u2DelayCellTimex100 = 270/100 ps
2497 10:01:18.982145 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2498 10:01:18.985320 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2499 10:01:18.988531 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2500 10:01:18.995133 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2501 10:01:18.998725 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2502 10:01:19.002105 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2503 10:01:19.002210
2504 10:01:19.005107 CA PerBit enable=1, Macro0, CA PI delay=33
2505 10:01:19.005208
2506 10:01:19.008589 [CBTSetCACLKResult] CA Dly = 33
2507 10:01:19.008689 CS Dly: 7 (0~39)
2508 10:01:19.008815
2509 10:01:19.012038 ----->DramcWriteLeveling(PI) begin...
2510 10:01:19.015131 ==
2511 10:01:19.015236 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 10:01:19.022022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 10:01:19.022172 ==
2514 10:01:19.025276 Write leveling (Byte 0): 36 => 36
2515 10:01:19.028427 Write leveling (Byte 1): 31 => 31
2516 10:01:19.031581 DramcWriteLeveling(PI) end<-----
2517 10:01:19.031678
2518 10:01:19.031776 ==
2519 10:01:19.035276 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 10:01:19.038346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 10:01:19.038445 ==
2522 10:01:19.041668 [Gating] SW mode calibration
2523 10:01:19.048257 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 10:01:19.051598 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 10:01:19.058424 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2526 10:01:19.061969 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2527 10:01:19.065118 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 10:01:19.071729 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 10:01:19.075505 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 10:01:19.078178 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 10:01:19.085335 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2532 10:01:19.088298 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2533 10:01:19.091860 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2534 10:01:19.098474 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 10:01:19.101787 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 10:01:19.105018 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 10:01:19.111757 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 10:01:19.115293 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 10:01:19.118472 1 0 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2540 10:01:19.125102 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2541 10:01:19.128399 1 1 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
2542 10:01:19.131886 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 10:01:19.135011 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 10:01:19.142201 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 10:01:19.145431 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 10:01:19.148453 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 10:01:19.155638 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2548 10:01:19.158611 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 10:01:19.161961 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2550 10:01:19.168527 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 10:01:19.171942 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 10:01:19.175035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 10:01:19.181995 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 10:01:19.185165 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 10:01:19.188621 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 10:01:19.195391 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 10:01:19.198553 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 10:01:19.201765 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 10:01:19.208559 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 10:01:19.211866 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 10:01:19.215466 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 10:01:19.218484 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 10:01:19.225166 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 10:01:19.228934 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 10:01:19.232200 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 10:01:19.235548 Total UI for P1: 0, mck2ui 16
2567 10:01:19.238705 best dqsien dly found for B0: ( 1, 3, 26)
2568 10:01:19.245746 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 10:01:19.245828 Total UI for P1: 0, mck2ui 16
2570 10:01:19.252111 best dqsien dly found for B1: ( 1, 4, 0)
2571 10:01:19.255444 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2572 10:01:19.259053 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2573 10:01:19.259135
2574 10:01:19.262197 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2575 10:01:19.265745 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2576 10:01:19.268862 [Gating] SW calibration Done
2577 10:01:19.268944 ==
2578 10:01:19.272083 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 10:01:19.275621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 10:01:19.275702 ==
2581 10:01:19.278519 RX Vref Scan: 0
2582 10:01:19.278600
2583 10:01:19.278664 RX Vref 0 -> 0, step: 1
2584 10:01:19.278724
2585 10:01:19.282153 RX Delay -40 -> 252, step: 8
2586 10:01:19.285324 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2587 10:01:19.291905 iDelay=208, Bit 1, Center 123 (48 ~ 199) 152
2588 10:01:19.295595 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2589 10:01:19.298665 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2590 10:01:19.302280 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2591 10:01:19.305365 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2592 10:01:19.312333 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2593 10:01:19.315326 iDelay=208, Bit 7, Center 131 (56 ~ 207) 152
2594 10:01:19.318720 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2595 10:01:19.322249 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2596 10:01:19.325654 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2597 10:01:19.328690 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2598 10:01:19.335890 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2599 10:01:19.338812 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2600 10:01:19.342249 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2601 10:01:19.345440 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2602 10:01:19.345550 ==
2603 10:01:19.349080 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 10:01:19.355536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 10:01:19.355618 ==
2606 10:01:19.355683 DQS Delay:
2607 10:01:19.358975 DQS0 = 0, DQS1 = 0
2608 10:01:19.359057 DQM Delay:
2609 10:01:19.359122 DQM0 = 123, DQM1 = 110
2610 10:01:19.362294 DQ Delay:
2611 10:01:19.365870 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2612 10:01:19.368997 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =131
2613 10:01:19.372332 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2614 10:01:19.375614 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2615 10:01:19.375689
2616 10:01:19.375759
2617 10:01:19.375822 ==
2618 10:01:19.378726 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 10:01:19.382445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 10:01:19.382534 ==
2621 10:01:19.382598
2622 10:01:19.385451
2623 10:01:19.385532 TX Vref Scan disable
2624 10:01:19.388572 == TX Byte 0 ==
2625 10:01:19.392348 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2626 10:01:19.395370 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2627 10:01:19.398777 == TX Byte 1 ==
2628 10:01:19.401944 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2629 10:01:19.405733 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2630 10:01:19.405805 ==
2631 10:01:19.409009 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 10:01:19.415534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 10:01:19.415607 ==
2634 10:01:19.426611 TX Vref=22, minBit 0, minWin=24, winSum=408
2635 10:01:19.429857 TX Vref=24, minBit 0, minWin=25, winSum=414
2636 10:01:19.432991 TX Vref=26, minBit 0, minWin=25, winSum=425
2637 10:01:19.436435 TX Vref=28, minBit 5, minWin=25, winSum=424
2638 10:01:19.439672 TX Vref=30, minBit 5, minWin=25, winSum=424
2639 10:01:19.443160 TX Vref=32, minBit 4, minWin=25, winSum=425
2640 10:01:19.450035 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
2641 10:01:19.450160
2642 10:01:19.453062 Final TX Range 1 Vref 26
2643 10:01:19.453185
2644 10:01:19.453294 ==
2645 10:01:19.456458 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 10:01:19.460003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 10:01:19.460128 ==
2648 10:01:19.460239
2649 10:01:19.460350
2650 10:01:19.463071 TX Vref Scan disable
2651 10:01:19.466777 == TX Byte 0 ==
2652 10:01:19.469980 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2653 10:01:19.473294 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2654 10:01:19.476547 == TX Byte 1 ==
2655 10:01:19.480310 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2656 10:01:19.483324 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2657 10:01:19.483443
2658 10:01:19.486386 [DATLAT]
2659 10:01:19.486508 Freq=1200, CH0 RK0
2660 10:01:19.486659
2661 10:01:19.489953 DATLAT Default: 0xd
2662 10:01:19.490080 0, 0xFFFF, sum = 0
2663 10:01:19.493456 1, 0xFFFF, sum = 0
2664 10:01:19.493582 2, 0xFFFF, sum = 0
2665 10:01:19.496711 3, 0xFFFF, sum = 0
2666 10:01:19.496866 4, 0xFFFF, sum = 0
2667 10:01:19.500006 5, 0xFFFF, sum = 0
2668 10:01:19.500132 6, 0xFFFF, sum = 0
2669 10:01:19.503175 7, 0xFFFF, sum = 0
2670 10:01:19.503312 8, 0xFFFF, sum = 0
2671 10:01:19.506805 9, 0xFFFF, sum = 0
2672 10:01:19.506934 10, 0xFFFF, sum = 0
2673 10:01:19.510102 11, 0xFFFF, sum = 0
2674 10:01:19.510226 12, 0x0, sum = 1
2675 10:01:19.513329 13, 0x0, sum = 2
2676 10:01:19.513452 14, 0x0, sum = 3
2677 10:01:19.516995 15, 0x0, sum = 4
2678 10:01:19.517122 best_step = 13
2679 10:01:19.517234
2680 10:01:19.517349 ==
2681 10:01:19.520029 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 10:01:19.526559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 10:01:19.526684 ==
2684 10:01:19.526804 RX Vref Scan: 1
2685 10:01:19.526979
2686 10:01:19.530238 Set Vref Range= 32 -> 127
2687 10:01:19.530358
2688 10:01:19.533223 RX Vref 32 -> 127, step: 1
2689 10:01:19.533345
2690 10:01:19.536653 RX Delay -13 -> 252, step: 4
2691 10:01:19.536806
2692 10:01:19.539785 Set Vref, RX VrefLevel [Byte0]: 32
2693 10:01:19.539906 [Byte1]: 32
2694 10:01:19.544605
2695 10:01:19.544725 Set Vref, RX VrefLevel [Byte0]: 33
2696 10:01:19.547728 [Byte1]: 33
2697 10:01:19.552249
2698 10:01:19.552374 Set Vref, RX VrefLevel [Byte0]: 34
2699 10:01:19.555924 [Byte1]: 34
2700 10:01:19.560445
2701 10:01:19.560591 Set Vref, RX VrefLevel [Byte0]: 35
2702 10:01:19.563645 [Byte1]: 35
2703 10:01:19.568071
2704 10:01:19.568175 Set Vref, RX VrefLevel [Byte0]: 36
2705 10:01:19.571606 [Byte1]: 36
2706 10:01:19.576059
2707 10:01:19.576156 Set Vref, RX VrefLevel [Byte0]: 37
2708 10:01:19.579279 [Byte1]: 37
2709 10:01:19.584479
2710 10:01:19.584606 Set Vref, RX VrefLevel [Byte0]: 38
2711 10:01:19.587118 [Byte1]: 38
2712 10:01:19.591861
2713 10:01:19.591985 Set Vref, RX VrefLevel [Byte0]: 39
2714 10:01:19.594998 [Byte1]: 39
2715 10:01:19.599993
2716 10:01:19.600094 Set Vref, RX VrefLevel [Byte0]: 40
2717 10:01:19.603183 [Byte1]: 40
2718 10:01:19.607697
2719 10:01:19.607774 Set Vref, RX VrefLevel [Byte0]: 41
2720 10:01:19.610913 [Byte1]: 41
2721 10:01:19.615492
2722 10:01:19.615596 Set Vref, RX VrefLevel [Byte0]: 42
2723 10:01:19.619031 [Byte1]: 42
2724 10:01:19.623445
2725 10:01:19.623549 Set Vref, RX VrefLevel [Byte0]: 43
2726 10:01:19.626542 [Byte1]: 43
2727 10:01:19.631576
2728 10:01:19.631682 Set Vref, RX VrefLevel [Byte0]: 44
2729 10:01:19.634603 [Byte1]: 44
2730 10:01:19.639063
2731 10:01:19.639164 Set Vref, RX VrefLevel [Byte0]: 45
2732 10:01:19.642722 [Byte1]: 45
2733 10:01:19.647342
2734 10:01:19.647466 Set Vref, RX VrefLevel [Byte0]: 46
2735 10:01:19.650731 [Byte1]: 46
2736 10:01:19.655016
2737 10:01:19.655162 Set Vref, RX VrefLevel [Byte0]: 47
2738 10:01:19.658212 [Byte1]: 47
2739 10:01:19.662936
2740 10:01:19.663059 Set Vref, RX VrefLevel [Byte0]: 48
2741 10:01:19.666083 [Byte1]: 48
2742 10:01:19.670741
2743 10:01:19.670849 Set Vref, RX VrefLevel [Byte0]: 49
2744 10:01:19.674101 [Byte1]: 49
2745 10:01:19.679634
2746 10:01:19.679735 Set Vref, RX VrefLevel [Byte0]: 50
2747 10:01:19.681979 [Byte1]: 50
2748 10:01:19.686649
2749 10:01:19.686760 Set Vref, RX VrefLevel [Byte0]: 51
2750 10:01:19.689965 [Byte1]: 51
2751 10:01:19.694373
2752 10:01:19.694487 Set Vref, RX VrefLevel [Byte0]: 52
2753 10:01:19.697760 [Byte1]: 52
2754 10:01:19.702537
2755 10:01:19.702643 Set Vref, RX VrefLevel [Byte0]: 53
2756 10:01:19.705607 [Byte1]: 53
2757 10:01:19.710296
2758 10:01:19.710405 Set Vref, RX VrefLevel [Byte0]: 54
2759 10:01:19.713665 [Byte1]: 54
2760 10:01:19.718443
2761 10:01:19.718549 Set Vref, RX VrefLevel [Byte0]: 55
2762 10:01:19.721579 [Byte1]: 55
2763 10:01:19.726039
2764 10:01:19.726152 Set Vref, RX VrefLevel [Byte0]: 56
2765 10:01:19.729439 [Byte1]: 56
2766 10:01:19.734081
2767 10:01:19.734165 Set Vref, RX VrefLevel [Byte0]: 57
2768 10:01:19.737201 [Byte1]: 57
2769 10:01:19.741803
2770 10:01:19.741887 Set Vref, RX VrefLevel [Byte0]: 58
2771 10:01:19.744977 [Byte1]: 58
2772 10:01:19.749861
2773 10:01:19.749945 Set Vref, RX VrefLevel [Byte0]: 59
2774 10:01:19.753344 [Byte1]: 59
2775 10:01:19.757773
2776 10:01:19.757859 Set Vref, RX VrefLevel [Byte0]: 60
2777 10:01:19.760767 [Byte1]: 60
2778 10:01:19.765317
2779 10:01:19.765402 Set Vref, RX VrefLevel [Byte0]: 61
2780 10:01:19.768799 [Byte1]: 61
2781 10:01:19.773279
2782 10:01:19.773407 Set Vref, RX VrefLevel [Byte0]: 62
2783 10:01:19.776898 [Byte1]: 62
2784 10:01:19.781167
2785 10:01:19.781294 Set Vref, RX VrefLevel [Byte0]: 63
2786 10:01:19.784705 [Byte1]: 63
2787 10:01:19.789435
2788 10:01:19.789558 Set Vref, RX VrefLevel [Byte0]: 64
2789 10:01:19.792431 [Byte1]: 64
2790 10:01:19.797109
2791 10:01:19.797233 Set Vref, RX VrefLevel [Byte0]: 65
2792 10:01:19.800227 [Byte1]: 65
2793 10:01:19.804999
2794 10:01:19.805082 Set Vref, RX VrefLevel [Byte0]: 66
2795 10:01:19.808274 [Byte1]: 66
2796 10:01:19.813188
2797 10:01:19.813263 Set Vref, RX VrefLevel [Byte0]: 67
2798 10:01:19.816300 [Byte1]: 67
2799 10:01:19.820808
2800 10:01:19.820904 Set Vref, RX VrefLevel [Byte0]: 68
2801 10:01:19.823945 [Byte1]: 68
2802 10:01:19.828857
2803 10:01:19.828997 Set Vref, RX VrefLevel [Byte0]: 69
2804 10:01:19.831828 [Byte1]: 69
2805 10:01:19.836495
2806 10:01:19.836578 Set Vref, RX VrefLevel [Byte0]: 70
2807 10:01:19.839750 [Byte1]: 70
2808 10:01:19.844592
2809 10:01:19.844675 Final RX Vref Byte 0 = 57 to rank0
2810 10:01:19.847748 Final RX Vref Byte 1 = 48 to rank0
2811 10:01:19.851217 Final RX Vref Byte 0 = 57 to rank1
2812 10:01:19.854349 Final RX Vref Byte 1 = 48 to rank1==
2813 10:01:19.858009 Dram Type= 6, Freq= 0, CH_0, rank 0
2814 10:01:19.864187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 10:01:19.864270 ==
2816 10:01:19.864335 DQS Delay:
2817 10:01:19.864395 DQS0 = 0, DQS1 = 0
2818 10:01:19.867811 DQM Delay:
2819 10:01:19.867893 DQM0 = 123, DQM1 = 109
2820 10:01:19.870816 DQ Delay:
2821 10:01:19.874385 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2822 10:01:19.877498 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =130
2823 10:01:19.880928 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2824 10:01:19.884483 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =118
2825 10:01:19.884565
2826 10:01:19.884630
2827 10:01:19.891264 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2828 10:01:19.894527 CH0 RK0: MR19=404, MR18=B08
2829 10:01:19.901216 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2830 10:01:19.901300
2831 10:01:19.904349 ----->DramcWriteLeveling(PI) begin...
2832 10:01:19.904433 ==
2833 10:01:19.908224 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 10:01:19.911053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 10:01:19.911136 ==
2836 10:01:19.914848 Write leveling (Byte 0): 36 => 36
2837 10:01:19.917693 Write leveling (Byte 1): 29 => 29
2838 10:01:19.921194 DramcWriteLeveling(PI) end<-----
2839 10:01:19.921304
2840 10:01:19.921399 ==
2841 10:01:19.924736 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 10:01:19.928118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 10:01:19.931219 ==
2844 10:01:19.931301 [Gating] SW mode calibration
2845 10:01:19.937962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2846 10:01:19.944450 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2847 10:01:19.948005 0 15 0 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
2848 10:01:19.954729 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 10:01:19.957819 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 10:01:19.961456 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 10:01:19.968578 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 10:01:19.971681 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 10:01:19.975130 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2854 10:01:19.978216 0 15 28 | B1->B0 | 3131 2d2d | 0 0 | (1 0) (0 1)
2855 10:01:19.984881 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 10:01:19.987975 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 10:01:19.991684 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 10:01:19.998284 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 10:01:20.001466 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 10:01:20.005047 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 10:01:20.011749 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2862 10:01:20.015243 1 0 28 | B1->B0 | 3c3c 4444 | 1 0 | (0 0) (0 0)
2863 10:01:20.018278 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 10:01:20.025051 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 10:01:20.028386 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 10:01:20.031589 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 10:01:20.038381 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 10:01:20.041539 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 10:01:20.045109 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 10:01:20.051670 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2871 10:01:20.055152 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2872 10:01:20.058359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 10:01:20.062096 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 10:01:20.068385 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 10:01:20.071857 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 10:01:20.075454 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 10:01:20.082133 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 10:01:20.085252 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 10:01:20.088814 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 10:01:20.095513 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 10:01:20.098605 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 10:01:20.102095 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 10:01:20.108997 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 10:01:20.112150 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 10:01:20.115594 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2886 10:01:20.122004 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2887 10:01:20.125265 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 10:01:20.128698 Total UI for P1: 0, mck2ui 16
2889 10:01:20.131987 best dqsien dly found for B0: ( 1, 3, 26)
2890 10:01:20.135301 Total UI for P1: 0, mck2ui 16
2891 10:01:20.138408 best dqsien dly found for B1: ( 1, 3, 30)
2892 10:01:20.142253 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2893 10:01:20.145322 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2894 10:01:20.145427
2895 10:01:20.148699 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2896 10:01:20.152117 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2897 10:01:20.155265 [Gating] SW calibration Done
2898 10:01:20.155347 ==
2899 10:01:20.158858 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 10:01:20.162009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 10:01:20.162092 ==
2902 10:01:20.165377 RX Vref Scan: 0
2903 10:01:20.165491
2904 10:01:20.165557 RX Vref 0 -> 0, step: 1
2905 10:01:20.165620
2906 10:01:20.168813 RX Delay -40 -> 252, step: 8
2907 10:01:20.175619 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2908 10:01:20.178788 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2909 10:01:20.182142 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2910 10:01:20.185617 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2911 10:01:20.188643 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2912 10:01:20.192224 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2913 10:01:20.198868 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2914 10:01:20.202406 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2915 10:01:20.205490 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2916 10:01:20.209037 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2917 10:01:20.212365 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2918 10:01:20.218818 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2919 10:01:20.222117 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2920 10:01:20.225759 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2921 10:01:20.229241 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2922 10:01:20.232489 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2923 10:01:20.235747 ==
2924 10:01:20.235830 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 10:01:20.242138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 10:01:20.242267 ==
2927 10:01:20.242381 DQS Delay:
2928 10:01:20.245752 DQS0 = 0, DQS1 = 0
2929 10:01:20.245871 DQM Delay:
2930 10:01:20.249146 DQM0 = 120, DQM1 = 108
2931 10:01:20.249268 DQ Delay:
2932 10:01:20.252401 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2933 10:01:20.255849 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2934 10:01:20.259372 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2935 10:01:20.262326 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2936 10:01:20.262452
2937 10:01:20.262564
2938 10:01:20.262669 ==
2939 10:01:20.265797 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 10:01:20.269183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 10:01:20.272545 ==
2942 10:01:20.272648
2943 10:01:20.272740
2944 10:01:20.272878 TX Vref Scan disable
2945 10:01:20.275611 == TX Byte 0 ==
2946 10:01:20.278998 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2947 10:01:20.282336 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2948 10:01:20.286254 == TX Byte 1 ==
2949 10:01:20.289275 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2950 10:01:20.292627 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2951 10:01:20.292723 ==
2952 10:01:20.295682 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 10:01:20.302313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 10:01:20.302396 ==
2955 10:01:20.313731 TX Vref=22, minBit 1, minWin=25, winSum=416
2956 10:01:20.316980 TX Vref=24, minBit 0, minWin=25, winSum=421
2957 10:01:20.320660 TX Vref=26, minBit 5, minWin=25, winSum=430
2958 10:01:20.323780 TX Vref=28, minBit 1, minWin=26, winSum=431
2959 10:01:20.327489 TX Vref=30, minBit 1, minWin=26, winSum=432
2960 10:01:20.330360 TX Vref=32, minBit 5, minWin=25, winSum=430
2961 10:01:20.337008 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
2962 10:01:20.337110
2963 10:01:20.340661 Final TX Range 1 Vref 30
2964 10:01:20.340784
2965 10:01:20.340863 ==
2966 10:01:20.344019 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 10:01:20.347296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 10:01:20.347380 ==
2969 10:01:20.347445
2970 10:01:20.350471
2971 10:01:20.350570 TX Vref Scan disable
2972 10:01:20.354098 == TX Byte 0 ==
2973 10:01:20.357317 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2974 10:01:20.360818 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2975 10:01:20.363854 == TX Byte 1 ==
2976 10:01:20.367011 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2977 10:01:20.370477 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2978 10:01:20.370560
2979 10:01:20.373703 [DATLAT]
2980 10:01:20.373786 Freq=1200, CH0 RK1
2981 10:01:20.373851
2982 10:01:20.377239 DATLAT Default: 0xd
2983 10:01:20.377322 0, 0xFFFF, sum = 0
2984 10:01:20.380417 1, 0xFFFF, sum = 0
2985 10:01:20.380501 2, 0xFFFF, sum = 0
2986 10:01:20.383685 3, 0xFFFF, sum = 0
2987 10:01:20.383769 4, 0xFFFF, sum = 0
2988 10:01:20.387231 5, 0xFFFF, sum = 0
2989 10:01:20.387333 6, 0xFFFF, sum = 0
2990 10:01:20.390906 7, 0xFFFF, sum = 0
2991 10:01:20.390990 8, 0xFFFF, sum = 0
2992 10:01:20.394281 9, 0xFFFF, sum = 0
2993 10:01:20.397462 10, 0xFFFF, sum = 0
2994 10:01:20.397546 11, 0xFFFF, sum = 0
2995 10:01:20.401070 12, 0x0, sum = 1
2996 10:01:20.401154 13, 0x0, sum = 2
2997 10:01:20.401219 14, 0x0, sum = 3
2998 10:01:20.403935 15, 0x0, sum = 4
2999 10:01:20.404019 best_step = 13
3000 10:01:20.404085
3001 10:01:20.404144 ==
3002 10:01:20.407322 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 10:01:20.413998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 10:01:20.414081 ==
3005 10:01:20.414146 RX Vref Scan: 0
3006 10:01:20.414230
3007 10:01:20.417441 RX Vref 0 -> 0, step: 1
3008 10:01:20.417524
3009 10:01:20.420702 RX Delay -21 -> 252, step: 4
3010 10:01:20.424375 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3011 10:01:20.427791 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3012 10:01:20.434013 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3013 10:01:20.437531 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3014 10:01:20.440954 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3015 10:01:20.443988 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3016 10:01:20.447352 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3017 10:01:20.454069 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3018 10:01:20.457436 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3019 10:01:20.460874 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3020 10:01:20.464283 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3021 10:01:20.467396 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3022 10:01:20.474466 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3023 10:01:20.477792 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3024 10:01:20.480967 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3025 10:01:20.484525 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3026 10:01:20.484608 ==
3027 10:01:20.487730 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 10:01:20.491311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 10:01:20.494422 ==
3030 10:01:20.494504 DQS Delay:
3031 10:01:20.494568 DQS0 = 0, DQS1 = 0
3032 10:01:20.497755 DQM Delay:
3033 10:01:20.497873 DQM0 = 119, DQM1 = 108
3034 10:01:20.501288 DQ Delay:
3035 10:01:20.504478 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3036 10:01:20.507815 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3037 10:01:20.511024 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3038 10:01:20.514567 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3039 10:01:20.514653
3040 10:01:20.514738
3041 10:01:20.520945 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3042 10:01:20.524806 CH0 RK1: MR19=403, MR18=13FA
3043 10:01:20.531023 CH0_RK1: MR19=0x403, MR18=0x13FA, DQSOSC=402, MR23=63, INC=40, DEC=27
3044 10:01:20.534714 [RxdqsGatingPostProcess] freq 1200
3045 10:01:20.541025 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3046 10:01:20.541151 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 10:01:20.544327 best DQS1 dly(2T, 0.5T) = (0, 12)
3048 10:01:20.547917 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 10:01:20.551119 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3050 10:01:20.554330 best DQS0 dly(2T, 0.5T) = (0, 11)
3051 10:01:20.557663 best DQS1 dly(2T, 0.5T) = (0, 11)
3052 10:01:20.561149 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3053 10:01:20.564473 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3054 10:01:20.567877 Pre-setting of DQS Precalculation
3055 10:01:20.571415 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3056 10:01:20.571497 ==
3057 10:01:20.574458 Dram Type= 6, Freq= 0, CH_1, rank 0
3058 10:01:20.581547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 10:01:20.581630 ==
3060 10:01:20.584591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3061 10:01:20.591655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3062 10:01:20.600168 [CA 0] Center 37 (7~68) winsize 62
3063 10:01:20.603420 [CA 1] Center 37 (7~68) winsize 62
3064 10:01:20.606766 [CA 2] Center 35 (5~65) winsize 61
3065 10:01:20.609961 [CA 3] Center 34 (4~65) winsize 62
3066 10:01:20.613429 [CA 4] Center 34 (4~64) winsize 61
3067 10:01:20.617079 [CA 5] Center 33 (3~64) winsize 62
3068 10:01:20.617161
3069 10:01:20.620145 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3070 10:01:20.620226
3071 10:01:20.623722 [CATrainingPosCal] consider 1 rank data
3072 10:01:20.626766 u2DelayCellTimex100 = 270/100 ps
3073 10:01:20.630082 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3074 10:01:20.633760 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 10:01:20.640228 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3076 10:01:20.643539 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3077 10:01:20.646790 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3078 10:01:20.650260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3079 10:01:20.650342
3080 10:01:20.653681 CA PerBit enable=1, Macro0, CA PI delay=33
3081 10:01:20.653763
3082 10:01:20.656945 [CBTSetCACLKResult] CA Dly = 33
3083 10:01:20.657028 CS Dly: 5 (0~36)
3084 10:01:20.657094 ==
3085 10:01:20.660374 Dram Type= 6, Freq= 0, CH_1, rank 1
3086 10:01:20.667106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 10:01:20.667217 ==
3088 10:01:20.670248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3089 10:01:20.676893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3090 10:01:20.686000 [CA 0] Center 38 (8~68) winsize 61
3091 10:01:20.689007 [CA 1] Center 38 (8~69) winsize 62
3092 10:01:20.692403 [CA 2] Center 35 (5~66) winsize 62
3093 10:01:20.695826 [CA 3] Center 35 (5~65) winsize 61
3094 10:01:20.699057 [CA 4] Center 34 (4~65) winsize 62
3095 10:01:20.702451 [CA 5] Center 34 (4~64) winsize 61
3096 10:01:20.702532
3097 10:01:20.705754 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3098 10:01:20.705865
3099 10:01:20.709075 [CATrainingPosCal] consider 2 rank data
3100 10:01:20.712433 u2DelayCellTimex100 = 270/100 ps
3101 10:01:20.716027 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3102 10:01:20.719426 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3103 10:01:20.722888 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3104 10:01:20.729349 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3105 10:01:20.732665 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3106 10:01:20.736259 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3107 10:01:20.736367
3108 10:01:20.739326 CA PerBit enable=1, Macro0, CA PI delay=34
3109 10:01:20.739423
3110 10:01:20.742750 [CBTSetCACLKResult] CA Dly = 34
3111 10:01:20.742848 CS Dly: 6 (0~39)
3112 10:01:20.742913
3113 10:01:20.745890 ----->DramcWriteLeveling(PI) begin...
3114 10:01:20.745989 ==
3115 10:01:20.749476 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 10:01:20.756281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 10:01:20.756378 ==
3118 10:01:20.759345 Write leveling (Byte 0): 28 => 28
3119 10:01:20.762807 Write leveling (Byte 1): 28 => 28
3120 10:01:20.762904 DramcWriteLeveling(PI) end<-----
3121 10:01:20.762998
3122 10:01:20.765889 ==
3123 10:01:20.769470 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 10:01:20.772608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 10:01:20.772690 ==
3126 10:01:20.776037 [Gating] SW mode calibration
3127 10:01:20.782600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3128 10:01:20.786181 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3129 10:01:20.792677 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 10:01:20.796074 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 10:01:20.799301 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 10:01:20.806239 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 10:01:20.809807 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 10:01:20.812846 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3135 10:01:20.819627 0 15 24 | B1->B0 | 2e2e 2929 | 0 0 | (0 1) (0 1)
3136 10:01:20.823178 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 10:01:20.826333 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 10:01:20.829805 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 10:01:20.836572 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 10:01:20.839856 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 10:01:20.842991 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 10:01:20.849901 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3143 10:01:20.853001 1 0 24 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
3144 10:01:20.856269 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 10:01:20.863072 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 10:01:20.866484 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 10:01:20.869533 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 10:01:20.876469 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 10:01:20.879759 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 10:01:20.882951 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3151 10:01:20.890281 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3152 10:01:20.893328 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3153 10:01:20.896709 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 10:01:20.900049 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 10:01:20.906433 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 10:01:20.909992 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 10:01:20.913463 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 10:01:20.919984 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 10:01:20.923232 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 10:01:20.926352 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 10:01:20.933066 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 10:01:20.936672 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 10:01:20.939630 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 10:01:20.946773 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 10:01:20.949942 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 10:01:20.953057 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 10:01:20.959828 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3168 10:01:20.963268 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 10:01:20.966650 Total UI for P1: 0, mck2ui 16
3170 10:01:20.970114 best dqsien dly found for B0: ( 1, 3, 24)
3171 10:01:20.973302 Total UI for P1: 0, mck2ui 16
3172 10:01:20.976724 best dqsien dly found for B1: ( 1, 3, 24)
3173 10:01:20.979800 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3174 10:01:20.983131 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3175 10:01:20.983227
3176 10:01:20.986438 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3177 10:01:20.989937 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3178 10:01:20.993414 [Gating] SW calibration Done
3179 10:01:20.993495 ==
3180 10:01:20.996480 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 10:01:20.999926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 10:01:21 ==
3183 10:01:21.003259 RX Vref Scan: 0
3184 10:01:21.003339
3185 10:01:21.006904 RX Vref 0 -> 0, step: 1
3186 10:01:21.006985
3187 10:01:21.007048 RX Delay -40 -> 252, step: 8
3188 10:01:21.013352 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3189 10:01:21.016571 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3190 10:01:21.019982 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3191 10:01:21.023407 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3192 10:01:21.026509 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3193 10:01:21.033702 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3194 10:01:21.036703 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3195 10:01:21.040155 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3196 10:01:21.043432 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3197 10:01:21.046727 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3198 10:01:21.050085 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3199 10:01:21.056710 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3200 10:01:21.060266 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3201 10:01:21.063771 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3202 10:01:21.066768 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3203 10:01:21.070362 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3204 10:01:21.073574 ==
3205 10:01:21.076842 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 10:01:21.080279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 10:01:21.080362 ==
3208 10:01:21.080435 DQS Delay:
3209 10:01:21.083430 DQS0 = 0, DQS1 = 0
3210 10:01:21.083501 DQM Delay:
3211 10:01:21.087045 DQM0 = 119, DQM1 = 112
3212 10:01:21.087116 DQ Delay:
3213 10:01:21.090320 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3214 10:01:21.093774 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3215 10:01:21.096983 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3216 10:01:21.100349 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3217 10:01:21.100422
3218 10:01:21.100491
3219 10:01:21.100552 ==
3220 10:01:21.104022 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 10:01:21.110653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 10:01:21.110744 ==
3223 10:01:21.110806
3224 10:01:21.110863
3225 10:01:21.110918 TX Vref Scan disable
3226 10:01:21.113650 == TX Byte 0 ==
3227 10:01:21.117052 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3228 10:01:21.120468 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3229 10:01:21.123484 == TX Byte 1 ==
3230 10:01:21.126931 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3231 10:01:21.130416 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3232 10:01:21.133645 ==
3233 10:01:21.137251 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 10:01:21.140205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 10:01:21.140282 ==
3236 10:01:21.151356 TX Vref=22, minBit 10, minWin=24, winSum=405
3237 10:01:21.154613 TX Vref=24, minBit 1, minWin=24, winSum=412
3238 10:01:21.157997 TX Vref=26, minBit 1, minWin=25, winSum=416
3239 10:01:21.161303 TX Vref=28, minBit 10, minWin=25, winSum=423
3240 10:01:21.164587 TX Vref=30, minBit 11, minWin=25, winSum=423
3241 10:01:21.171307 TX Vref=32, minBit 14, minWin=25, winSum=424
3242 10:01:21.175058 [TxChooseVref] Worse bit 14, Min win 25, Win sum 424, Final Vref 32
3243 10:01:21.175188
3244 10:01:21.178063 Final TX Range 1 Vref 32
3245 10:01:21.178189
3246 10:01:21.178293 ==
3247 10:01:21.181287 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 10:01:21.184665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 10:01:21.187857 ==
3250 10:01:21.187940
3251 10:01:21.188005
3252 10:01:21.188065 TX Vref Scan disable
3253 10:01:21.191333 == TX Byte 0 ==
3254 10:01:21.194779 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3255 10:01:21.198649 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3256 10:01:21.201536 == TX Byte 1 ==
3257 10:01:21.204639 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3258 10:01:21.207902 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3259 10:01:21.211265
3260 10:01:21.211342 [DATLAT]
3261 10:01:21.211405 Freq=1200, CH1 RK0
3262 10:01:21.211466
3263 10:01:21.214854 DATLAT Default: 0xd
3264 10:01:21.214936 0, 0xFFFF, sum = 0
3265 10:01:21.217996 1, 0xFFFF, sum = 0
3266 10:01:21.218079 2, 0xFFFF, sum = 0
3267 10:01:21.221387 3, 0xFFFF, sum = 0
3268 10:01:21.221485 4, 0xFFFF, sum = 0
3269 10:01:21.224713 5, 0xFFFF, sum = 0
3270 10:01:21.224844 6, 0xFFFF, sum = 0
3271 10:01:21.228104 7, 0xFFFF, sum = 0
3272 10:01:21.231740 8, 0xFFFF, sum = 0
3273 10:01:21.231823 9, 0xFFFF, sum = 0
3274 10:01:21.234655 10, 0xFFFF, sum = 0
3275 10:01:21.234738 11, 0xFFFF, sum = 0
3276 10:01:21.238005 12, 0x0, sum = 1
3277 10:01:21.238088 13, 0x0, sum = 2
3278 10:01:21.241527 14, 0x0, sum = 3
3279 10:01:21.241611 15, 0x0, sum = 4
3280 10:01:21.241677 best_step = 13
3281 10:01:21.241736
3282 10:01:21.244772 ==
3283 10:01:21.248350 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 10:01:21.251590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 10:01:21.251674 ==
3286 10:01:21.251758 RX Vref Scan: 1
3287 10:01:21.251837
3288 10:01:21.254989 Set Vref Range= 32 -> 127
3289 10:01:21.255073
3290 10:01:21.258270 RX Vref 32 -> 127, step: 1
3291 10:01:21.258355
3292 10:01:21.261613 RX Delay -13 -> 252, step: 4
3293 10:01:21.261717
3294 10:01:21.265104 Set Vref, RX VrefLevel [Byte0]: 32
3295 10:01:21.268411 [Byte1]: 32
3296 10:01:21.268516
3297 10:01:21.271690 Set Vref, RX VrefLevel [Byte0]: 33
3298 10:01:21.274757 [Byte1]: 33
3299 10:01:21.274863
3300 10:01:21.278238 Set Vref, RX VrefLevel [Byte0]: 34
3301 10:01:21.281602 [Byte1]: 34
3302 10:01:21.285495
3303 10:01:21.285624 Set Vref, RX VrefLevel [Byte0]: 35
3304 10:01:21.288750 [Byte1]: 35
3305 10:01:21.293600
3306 10:01:21.293749 Set Vref, RX VrefLevel [Byte0]: 36
3307 10:01:21.296900 [Byte1]: 36
3308 10:01:21.301317
3309 10:01:21.301424 Set Vref, RX VrefLevel [Byte0]: 37
3310 10:01:21.304730 [Byte1]: 37
3311 10:01:21.309452
3312 10:01:21.309525 Set Vref, RX VrefLevel [Byte0]: 38
3313 10:01:21.312448 [Byte1]: 38
3314 10:01:21.317410
3315 10:01:21.317496 Set Vref, RX VrefLevel [Byte0]: 39
3316 10:01:21.320548 [Byte1]: 39
3317 10:01:21.325046
3318 10:01:21.325158 Set Vref, RX VrefLevel [Byte0]: 40
3319 10:01:21.328277 [Byte1]: 40
3320 10:01:21.333210
3321 10:01:21.333307 Set Vref, RX VrefLevel [Byte0]: 41
3322 10:01:21.336277 [Byte1]: 41
3323 10:01:21.340860
3324 10:01:21.340940 Set Vref, RX VrefLevel [Byte0]: 42
3325 10:01:21.344181 [Byte1]: 42
3326 10:01:21.348982
3327 10:01:21.349077 Set Vref, RX VrefLevel [Byte0]: 43
3328 10:01:21.351875 [Byte1]: 43
3329 10:01:21.356614
3330 10:01:21.356693 Set Vref, RX VrefLevel [Byte0]: 44
3331 10:01:21.360033 [Byte1]: 44
3332 10:01:21.364391
3333 10:01:21.364470 Set Vref, RX VrefLevel [Byte0]: 45
3334 10:01:21.368027 [Byte1]: 45
3335 10:01:21.372203
3336 10:01:21.372305 Set Vref, RX VrefLevel [Byte0]: 46
3337 10:01:21.375561 [Byte1]: 46
3338 10:01:21.380478
3339 10:01:21.380558 Set Vref, RX VrefLevel [Byte0]: 47
3340 10:01:21.383514 [Byte1]: 47
3341 10:01:21.388291
3342 10:01:21.388371 Set Vref, RX VrefLevel [Byte0]: 48
3343 10:01:21.391552 [Byte1]: 48
3344 10:01:21.396555
3345 10:01:21.396634 Set Vref, RX VrefLevel [Byte0]: 49
3346 10:01:21.399324 [Byte1]: 49
3347 10:01:21.404147
3348 10:01:21.404227 Set Vref, RX VrefLevel [Byte0]: 50
3349 10:01:21.407490 [Byte1]: 50
3350 10:01:21.411712
3351 10:01:21.411818 Set Vref, RX VrefLevel [Byte0]: 51
3352 10:01:21.415203 [Byte1]: 51
3353 10:01:21.419761
3354 10:01:21.419841 Set Vref, RX VrefLevel [Byte0]: 52
3355 10:01:21.422877 [Byte1]: 52
3356 10:01:21.427367
3357 10:01:21.427446 Set Vref, RX VrefLevel [Byte0]: 53
3358 10:01:21.430855 [Byte1]: 53
3359 10:01:21.435407
3360 10:01:21.435486 Set Vref, RX VrefLevel [Byte0]: 54
3361 10:01:21.438617 [Byte1]: 54
3362 10:01:21.443547
3363 10:01:21.443626 Set Vref, RX VrefLevel [Byte0]: 55
3364 10:01:21.446699 [Byte1]: 55
3365 10:01:21.451362
3366 10:01:21.451442 Set Vref, RX VrefLevel [Byte0]: 56
3367 10:01:21.454683 [Byte1]: 56
3368 10:01:21.459051
3369 10:01:21.459131 Set Vref, RX VrefLevel [Byte0]: 57
3370 10:01:21.462631 [Byte1]: 57
3371 10:01:21.467272
3372 10:01:21.467392 Set Vref, RX VrefLevel [Byte0]: 58
3373 10:01:21.470336 [Byte1]: 58
3374 10:01:21.474797
3375 10:01:21.474917 Set Vref, RX VrefLevel [Byte0]: 59
3376 10:01:21.478248 [Byte1]: 59
3377 10:01:21.482741
3378 10:01:21.482859 Set Vref, RX VrefLevel [Byte0]: 60
3379 10:01:21.486198 [Byte1]: 60
3380 10:01:21.490632
3381 10:01:21.490751 Set Vref, RX VrefLevel [Byte0]: 61
3382 10:01:21.494204 [Byte1]: 61
3383 10:01:21.498788
3384 10:01:21.498906 Set Vref, RX VrefLevel [Byte0]: 62
3385 10:01:21.502041 [Byte1]: 62
3386 10:01:21.506634
3387 10:01:21.506768 Set Vref, RX VrefLevel [Byte0]: 63
3388 10:01:21.509605 [Byte1]: 63
3389 10:01:21.514151
3390 10:01:21.514231 Set Vref, RX VrefLevel [Byte0]: 64
3391 10:01:21.517504 [Byte1]: 64
3392 10:01:21.522287
3393 10:01:21.522367 Set Vref, RX VrefLevel [Byte0]: 65
3394 10:01:21.525534 [Byte1]: 65
3395 10:01:21.530105
3396 10:01:21.530184 Set Vref, RX VrefLevel [Byte0]: 66
3397 10:01:21.533470 [Byte1]: 66
3398 10:01:21.537904
3399 10:01:21.537998 Set Vref, RX VrefLevel [Byte0]: 67
3400 10:01:21.541256 [Byte1]: 67
3401 10:01:21.546043
3402 10:01:21.546182 Set Vref, RX VrefLevel [Byte0]: 68
3403 10:01:21.549134 [Byte1]: 68
3404 10:01:21.553740
3405 10:01:21.553822 Final RX Vref Byte 0 = 51 to rank0
3406 10:01:21.557331 Final RX Vref Byte 1 = 58 to rank0
3407 10:01:21.560471 Final RX Vref Byte 0 = 51 to rank1
3408 10:01:21.563886 Final RX Vref Byte 1 = 58 to rank1==
3409 10:01:21.567223 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 10:01:21.570625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 10:01:21.573852 ==
3412 10:01:21.573934 DQS Delay:
3413 10:01:21.573998 DQS0 = 0, DQS1 = 0
3414 10:01:21.577146 DQM Delay:
3415 10:01:21.577227 DQM0 = 119, DQM1 = 113
3416 10:01:21.580767 DQ Delay:
3417 10:01:21.584410 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3418 10:01:21.587098 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3419 10:01:21.590781 DQ8 =102, DQ9 =100, DQ10 =116, DQ11 =106
3420 10:01:21.593865 DQ12 =126, DQ13 =118, DQ14 =120, DQ15 =120
3421 10:01:21.593946
3422 10:01:21.594010
3423 10:01:21.600578 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3424 10:01:21.604252 CH1 RK0: MR19=404, MR18=215
3425 10:01:21.610840 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3426 10:01:21.610922
3427 10:01:21.614001 ----->DramcWriteLeveling(PI) begin...
3428 10:01:21.614083 ==
3429 10:01:21.617247 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 10:01:21.620662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 10:01:21.620744 ==
3432 10:01:21.624044 Write leveling (Byte 0): 27 => 27
3433 10:01:21.627458 Write leveling (Byte 1): 29 => 29
3434 10:01:21.630782 DramcWriteLeveling(PI) end<-----
3435 10:01:21.630863
3436 10:01:21.630926 ==
3437 10:01:21.634060 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 10:01:21.637402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 10:01:21.641063 ==
3440 10:01:21.641144 [Gating] SW mode calibration
3441 10:01:21.647367 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3442 10:01:21.654306 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3443 10:01:21.657377 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 10:01:21.664166 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 10:01:21.667374 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 10:01:21.670726 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 10:01:21.677597 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 10:01:21.680663 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3449 10:01:21.684390 0 15 24 | B1->B0 | 2727 3232 | 0 1 | (0 0) (1 0)
3450 10:01:21.691004 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (0 0)
3451 10:01:21.694042 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 10:01:21.697702 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 10:01:21.701004 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 10:01:21.707567 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 10:01:21.710827 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 10:01:21.713966 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 10:01:21.720562 1 0 24 | B1->B0 | 4040 2c2c | 0 1 | (0 0) (0 0)
3458 10:01:21.724267 1 0 28 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (1 1)
3459 10:01:21.727425 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 10:01:21.734150 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 10:01:21.737428 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 10:01:21.740930 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 10:01:21.747469 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 10:01:21.750634 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 10:01:21.753969 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3466 10:01:21.760646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3467 10:01:21.763811 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 10:01:21.767416 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 10:01:21.773967 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 10:01:21.777303 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 10:01:21.780853 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 10:01:21.787275 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 10:01:21.790912 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 10:01:21.793846 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 10:01:21.800341 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 10:01:21.803715 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 10:01:21.807140 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 10:01:21.813782 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 10:01:21.817467 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 10:01:21.820287 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3481 10:01:21.827212 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 10:01:21.830546 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 10:01:21.833665 Total UI for P1: 0, mck2ui 16
3484 10:01:21.836957 best dqsien dly found for B0: ( 1, 3, 22)
3485 10:01:21.840056 Total UI for P1: 0, mck2ui 16
3486 10:01:21.843407 best dqsien dly found for B1: ( 1, 3, 22)
3487 10:01:21.846822 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3488 10:01:21.849952 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3489 10:01:21.850034
3490 10:01:21.853254 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3491 10:01:21.857069 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3492 10:01:21.860343 [Gating] SW calibration Done
3493 10:01:21.860424 ==
3494 10:01:21.863332 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 10:01:21.866363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 10:01:21.866445 ==
3497 10:01:21.869970 RX Vref Scan: 0
3498 10:01:21.870051
3499 10:01:21.872946 RX Vref 0 -> 0, step: 1
3500 10:01:21.873028
3501 10:01:21.873092 RX Delay -40 -> 252, step: 8
3502 10:01:21.879946 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3503 10:01:21.883110 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3504 10:01:21.886372 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3505 10:01:21.889785 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3506 10:01:21.893331 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3507 10:01:21.899523 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3508 10:01:21.903140 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3509 10:01:21.906186 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3510 10:01:21.909757 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3511 10:01:21.912777 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3512 10:01:21.919901 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3513 10:01:21.922936 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3514 10:01:21.926547 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3515 10:01:21.929373 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3516 10:01:21.936167 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3517 10:01:21.939380 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3518 10:01:21.939477 ==
3519 10:01:21.942689 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 10:01:21.946058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 10:01:21.946148 ==
3522 10:01:21.949518 DQS Delay:
3523 10:01:21.949602 DQS0 = 0, DQS1 = 0
3524 10:01:21.949666 DQM Delay:
3525 10:01:21.952894 DQM0 = 119, DQM1 = 113
3526 10:01:21.953001 DQ Delay:
3527 10:01:21.955833 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3528 10:01:21.959252 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3529 10:01:21.962838 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3530 10:01:21.969106 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3531 10:01:21.969188
3532 10:01:21.969253
3533 10:01:21.969312 ==
3534 10:01:21.972708 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 10:01:21.975827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 10:01:21.975911 ==
3537 10:01:21.975976
3538 10:01:21.976036
3539 10:01:21.978951 TX Vref Scan disable
3540 10:01:21.979034 == TX Byte 0 ==
3541 10:01:21.985932 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3542 10:01:21.989433 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3543 10:01:21.989516 == TX Byte 1 ==
3544 10:01:21.995589 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3545 10:01:21.998758 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3546 10:01:21.998840 ==
3547 10:01:22.002233 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 10:01:22.005326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 10:01:22.005409 ==
3550 10:01:22.018537 TX Vref=22, minBit 1, minWin=25, winSum=418
3551 10:01:22.021478 TX Vref=24, minBit 3, minWin=25, winSum=422
3552 10:01:22.024739 TX Vref=26, minBit 0, minWin=26, winSum=425
3553 10:01:22.028706 TX Vref=28, minBit 3, minWin=26, winSum=431
3554 10:01:22.031875 TX Vref=30, minBit 8, minWin=26, winSum=429
3555 10:01:22.034807 TX Vref=32, minBit 7, minWin=26, winSum=428
3556 10:01:22.041494 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 28
3557 10:01:22.041577
3558 10:01:22.045093 Final TX Range 1 Vref 28
3559 10:01:22.045176
3560 10:01:22.045239 ==
3561 10:01:22.048598 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 10:01:22.051574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 10:01:22.051671 ==
3564 10:01:22.051751
3565 10:01:22.055099
3566 10:01:22.055180 TX Vref Scan disable
3567 10:01:22.058379 == TX Byte 0 ==
3568 10:01:22.061616 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3569 10:01:22.064871 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3570 10:01:22.068152 == TX Byte 1 ==
3571 10:01:22.071774 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3572 10:01:22.075077 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3573 10:01:22.075159
3574 10:01:22.078143 [DATLAT]
3575 10:01:22.078224 Freq=1200, CH1 RK1
3576 10:01:22.078288
3577 10:01:22.081754 DATLAT Default: 0xd
3578 10:01:22.081836 0, 0xFFFF, sum = 0
3579 10:01:22.084771 1, 0xFFFF, sum = 0
3580 10:01:22.084868 2, 0xFFFF, sum = 0
3581 10:01:22.088178 3, 0xFFFF, sum = 0
3582 10:01:22.088261 4, 0xFFFF, sum = 0
3583 10:01:22.091425 5, 0xFFFF, sum = 0
3584 10:01:22.091535 6, 0xFFFF, sum = 0
3585 10:01:22.094809 7, 0xFFFF, sum = 0
3586 10:01:22.098036 8, 0xFFFF, sum = 0
3587 10:01:22.098118 9, 0xFFFF, sum = 0
3588 10:01:22.101637 10, 0xFFFF, sum = 0
3589 10:01:22.101720 11, 0xFFFF, sum = 0
3590 10:01:22.104865 12, 0x0, sum = 1
3591 10:01:22.104947 13, 0x0, sum = 2
3592 10:01:22.108276 14, 0x0, sum = 3
3593 10:01:22.108358 15, 0x0, sum = 4
3594 10:01:22.108423 best_step = 13
3595 10:01:22.108482
3596 10:01:22.111330 ==
3597 10:01:22.115014 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 10:01:22.118188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 10:01:22.118272 ==
3600 10:01:22.118336 RX Vref Scan: 0
3601 10:01:22.118397
3602 10:01:22.121373 RX Vref 0 -> 0, step: 1
3603 10:01:22.121455
3604 10:01:22.124974 RX Delay -13 -> 252, step: 4
3605 10:01:22.128117 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3606 10:01:22.134600 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3607 10:01:22.137917 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3608 10:01:22.141372 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3609 10:01:22.144661 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3610 10:01:22.147907 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3611 10:01:22.154594 iDelay=195, Bit 6, Center 124 (63 ~ 186) 124
3612 10:01:22.158025 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3613 10:01:22.161387 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3614 10:01:22.164585 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3615 10:01:22.167844 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3616 10:01:22.174483 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3617 10:01:22.178006 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3618 10:01:22.181182 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3619 10:01:22.184558 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3620 10:01:22.187867 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3621 10:01:22.191132 ==
3622 10:01:22.194274 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 10:01:22.197770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 10:01:22.197852 ==
3625 10:01:22.197917 DQS Delay:
3626 10:01:22.201346 DQS0 = 0, DQS1 = 0
3627 10:01:22.201428 DQM Delay:
3628 10:01:22.204511 DQM0 = 119, DQM1 = 113
3629 10:01:22.204593 DQ Delay:
3630 10:01:22.207626 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3631 10:01:22.210959 DQ4 =122, DQ5 =130, DQ6 =124, DQ7 =116
3632 10:01:22.214205 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3633 10:01:22.218042 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3634 10:01:22.218124
3635 10:01:22.218189
3636 10:01:22.227976 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3637 10:01:22.228060 CH1 RK1: MR19=403, MR18=8ED
3638 10:01:22.234560 CH1_RK1: MR19=0x403, MR18=0x8ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3639 10:01:22.237827 [RxdqsGatingPostProcess] freq 1200
3640 10:01:22.244706 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 10:01:22.247950 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 10:01:22.251081 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 10:01:22.254471 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 10:01:22.258010 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 10:01:22.261392 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 10:01:22.261513 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 10:01:22.264336 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 10:01:22.267796 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 10:01:22.271241 Pre-setting of DQS Precalculation
3650 10:01:22.277785 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 10:01:22.284537 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 10:01:22.291377 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 10:01:22.291500
3654 10:01:22.291610
3655 10:01:22.294631 [Calibration Summary] 2400 Mbps
3656 10:01:22.294759 CH 0, Rank 0
3657 10:01:22.297561 SW Impedance : PASS
3658 10:01:22.300957 DUTY Scan : NO K
3659 10:01:22.301076 ZQ Calibration : PASS
3660 10:01:22.304386 Jitter Meter : NO K
3661 10:01:22.307564 CBT Training : PASS
3662 10:01:22.307684 Write leveling : PASS
3663 10:01:22.310659 RX DQS gating : PASS
3664 10:01:22.314204 RX DQ/DQS(RDDQC) : PASS
3665 10:01:22.314328 TX DQ/DQS : PASS
3666 10:01:22.317681 RX DATLAT : PASS
3667 10:01:22.320902 RX DQ/DQS(Engine): PASS
3668 10:01:22.321024 TX OE : NO K
3669 10:01:22.324045 All Pass.
3670 10:01:22.324147
3671 10:01:22.324238 CH 0, Rank 1
3672 10:01:22.327431 SW Impedance : PASS
3673 10:01:22.327513 DUTY Scan : NO K
3674 10:01:22.330994 ZQ Calibration : PASS
3675 10:01:22.333949 Jitter Meter : NO K
3676 10:01:22.334032 CBT Training : PASS
3677 10:01:22.337259 Write leveling : PASS
3678 10:01:22.340600 RX DQS gating : PASS
3679 10:01:22.340723 RX DQ/DQS(RDDQC) : PASS
3680 10:01:22.344316 TX DQ/DQS : PASS
3681 10:01:22.347143 RX DATLAT : PASS
3682 10:01:22.347226 RX DQ/DQS(Engine): PASS
3683 10:01:22.350714 TX OE : NO K
3684 10:01:22.350798 All Pass.
3685 10:01:22.350862
3686 10:01:22.353995 CH 1, Rank 0
3687 10:01:22.354077 SW Impedance : PASS
3688 10:01:22.357134 DUTY Scan : NO K
3689 10:01:22.357218 ZQ Calibration : PASS
3690 10:01:22.360708 Jitter Meter : NO K
3691 10:01:22.363927 CBT Training : PASS
3692 10:01:22.364055 Write leveling : PASS
3693 10:01:22.366975 RX DQS gating : PASS
3694 10:01:22.370469 RX DQ/DQS(RDDQC) : PASS
3695 10:01:22.370597 TX DQ/DQS : PASS
3696 10:01:22.373933 RX DATLAT : PASS
3697 10:01:22.377130 RX DQ/DQS(Engine): PASS
3698 10:01:22.377251 TX OE : NO K
3699 10:01:22.380419 All Pass.
3700 10:01:22.380544
3701 10:01:22.380652 CH 1, Rank 1
3702 10:01:22.383927 SW Impedance : PASS
3703 10:01:22.384048 DUTY Scan : NO K
3704 10:01:22.386925 ZQ Calibration : PASS
3705 10:01:22.390335 Jitter Meter : NO K
3706 10:01:22.390457 CBT Training : PASS
3707 10:01:22.394051 Write leveling : PASS
3708 10:01:22.397118 RX DQS gating : PASS
3709 10:01:22.397238 RX DQ/DQS(RDDQC) : PASS
3710 10:01:22.400430 TX DQ/DQS : PASS
3711 10:01:22.400552 RX DATLAT : PASS
3712 10:01:22.403786 RX DQ/DQS(Engine): PASS
3713 10:01:22.407299 TX OE : NO K
3714 10:01:22.407419 All Pass.
3715 10:01:22.407530
3716 10:01:22.410373 DramC Write-DBI off
3717 10:01:22.410499 PER_BANK_REFRESH: Hybrid Mode
3718 10:01:22.413878 TX_TRACKING: ON
3719 10:01:22.423652 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 10:01:22.426891 [FAST_K] Save calibration result to emmc
3721 10:01:22.430416 dramc_set_vcore_voltage set vcore to 650000
3722 10:01:22.430535 Read voltage for 600, 5
3723 10:01:22.433867 Vio18 = 0
3724 10:01:22.433988 Vcore = 650000
3725 10:01:22.434100 Vdram = 0
3726 10:01:22.436990 Vddq = 0
3727 10:01:22.437111 Vmddr = 0
3728 10:01:22.440483 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 10:01:22.446839 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 10:01:22.450423 MEM_TYPE=3, freq_sel=19
3731 10:01:22.453853 sv_algorithm_assistance_LP4_1600
3732 10:01:22.456927 ============ PULL DRAM RESETB DOWN ============
3733 10:01:22.460313 ========== PULL DRAM RESETB DOWN end =========
3734 10:01:22.466903 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 10:01:22.470203 ===================================
3736 10:01:22.470310 LPDDR4 DRAM CONFIGURATION
3737 10:01:22.473542 ===================================
3738 10:01:22.476898 EX_ROW_EN[0] = 0x0
3739 10:01:22.476980 EX_ROW_EN[1] = 0x0
3740 10:01:22.480096 LP4Y_EN = 0x0
3741 10:01:22.480194 WORK_FSP = 0x0
3742 10:01:22.483619 WL = 0x2
3743 10:01:22.483700 RL = 0x2
3744 10:01:22.487001 BL = 0x2
3745 10:01:22.490449 RPST = 0x0
3746 10:01:22.490558 RD_PRE = 0x0
3747 10:01:22.493768 WR_PRE = 0x1
3748 10:01:22.493850 WR_PST = 0x0
3749 10:01:22.496890 DBI_WR = 0x0
3750 10:01:22.496972 DBI_RD = 0x0
3751 10:01:22.500144 OTF = 0x1
3752 10:01:22.503570 ===================================
3753 10:01:22.506822 ===================================
3754 10:01:22.506905 ANA top config
3755 10:01:22.510441 ===================================
3756 10:01:22.513587 DLL_ASYNC_EN = 0
3757 10:01:22.517320 ALL_SLAVE_EN = 1
3758 10:01:22.517427 NEW_RANK_MODE = 1
3759 10:01:22.520281 DLL_IDLE_MODE = 1
3760 10:01:22.523431 LP45_APHY_COMB_EN = 1
3761 10:01:22.527066 TX_ODT_DIS = 1
3762 10:01:22.527149 NEW_8X_MODE = 1
3763 10:01:22.530050 ===================================
3764 10:01:22.533582 ===================================
3765 10:01:22.536988 data_rate = 1200
3766 10:01:22.540215 CKR = 1
3767 10:01:22.543289 DQ_P2S_RATIO = 8
3768 10:01:22.546882 ===================================
3769 10:01:22.549973 CA_P2S_RATIO = 8
3770 10:01:22.553739 DQ_CA_OPEN = 0
3771 10:01:22.553822 DQ_SEMI_OPEN = 0
3772 10:01:22.556715 CA_SEMI_OPEN = 0
3773 10:01:22.559991 CA_FULL_RATE = 0
3774 10:01:22.563498 DQ_CKDIV4_EN = 1
3775 10:01:22.566627 CA_CKDIV4_EN = 1
3776 10:01:22.570040 CA_PREDIV_EN = 0
3777 10:01:22.570122 PH8_DLY = 0
3778 10:01:22.573328 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 10:01:22.576734 DQ_AAMCK_DIV = 4
3780 10:01:22.579982 CA_AAMCK_DIV = 4
3781 10:01:22.583458 CA_ADMCK_DIV = 4
3782 10:01:22.586902 DQ_TRACK_CA_EN = 0
3783 10:01:22.587020 CA_PICK = 600
3784 10:01:22.590291 CA_MCKIO = 600
3785 10:01:22.593452 MCKIO_SEMI = 0
3786 10:01:22.596785 PLL_FREQ = 2288
3787 10:01:22.600225 DQ_UI_PI_RATIO = 32
3788 10:01:22.603506 CA_UI_PI_RATIO = 0
3789 10:01:22.606744 ===================================
3790 10:01:22.610284 ===================================
3791 10:01:22.610413 memory_type:LPDDR4
3792 10:01:22.613532 GP_NUM : 10
3793 10:01:22.616924 SRAM_EN : 1
3794 10:01:22.617060 MD32_EN : 0
3795 10:01:22.620390 ===================================
3796 10:01:22.623450 [ANA_INIT] >>>>>>>>>>>>>>
3797 10:01:22.626976 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 10:01:22.630291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 10:01:22.633559 ===================================
3800 10:01:22.636470 data_rate = 1200,PCW = 0X5800
3801 10:01:22.639983 ===================================
3802 10:01:22.643213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 10:01:22.646828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 10:01:22.653323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 10:01:22.656702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 10:01:22.659694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 10:01:22.666480 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 10:01:22.666564 [ANA_INIT] flow start
3809 10:01:22.669750 [ANA_INIT] PLL >>>>>>>>
3810 10:01:22.669832 [ANA_INIT] PLL <<<<<<<<
3811 10:01:22.672968 [ANA_INIT] MIDPI >>>>>>>>
3812 10:01:22.676238 [ANA_INIT] MIDPI <<<<<<<<
3813 10:01:22.679583 [ANA_INIT] DLL >>>>>>>>
3814 10:01:22.679665 [ANA_INIT] flow end
3815 10:01:22.683057 ============ LP4 DIFF to SE enter ============
3816 10:01:22.689548 ============ LP4 DIFF to SE exit ============
3817 10:01:22.689630 [ANA_INIT] <<<<<<<<<<<<<
3818 10:01:22.693069 [Flow] Enable top DCM control >>>>>
3819 10:01:22.696418 [Flow] Enable top DCM control <<<<<
3820 10:01:22.699489 Enable DLL master slave shuffle
3821 10:01:22.706567 ==============================================================
3822 10:01:22.706650 Gating Mode config
3823 10:01:22.713083 ==============================================================
3824 10:01:22.716394 Config description:
3825 10:01:22.726210 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 10:01:22.732841 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 10:01:22.736021 SELPH_MODE 0: By rank 1: By Phase
3828 10:01:22.742959 ==============================================================
3829 10:01:22.745948 GAT_TRACK_EN = 1
3830 10:01:22.749617 RX_GATING_MODE = 2
3831 10:01:22.749698 RX_GATING_TRACK_MODE = 2
3832 10:01:22.752976 SELPH_MODE = 1
3833 10:01:22.756200 PICG_EARLY_EN = 1
3834 10:01:22.759286 VALID_LAT_VALUE = 1
3835 10:01:22.766189 ==============================================================
3836 10:01:22.769410 Enter into Gating configuration >>>>
3837 10:01:22.772603 Exit from Gating configuration <<<<
3838 10:01:22.776192 Enter into DVFS_PRE_config >>>>>
3839 10:01:22.785978 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 10:01:22.789485 Exit from DVFS_PRE_config <<<<<
3841 10:01:22.792784 Enter into PICG configuration >>>>
3842 10:01:22.795979 Exit from PICG configuration <<<<
3843 10:01:22.799391 [RX_INPUT] configuration >>>>>
3844 10:01:22.802524 [RX_INPUT] configuration <<<<<
3845 10:01:22.806165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 10:01:22.812531 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 10:01:22.819180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 10:01:22.822820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 10:01:22.829348 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 10:01:22.836209 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 10:01:22.839373 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 10:01:22.842479 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 10:01:22.849164 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 10:01:22.852458 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 10:01:22.855930 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 10:01:22.862604 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 10:01:22.865802 ===================================
3858 10:01:22.865905 LPDDR4 DRAM CONFIGURATION
3859 10:01:22.869571 ===================================
3860 10:01:22.872787 EX_ROW_EN[0] = 0x0
3861 10:01:22.875942 EX_ROW_EN[1] = 0x0
3862 10:01:22.876056 LP4Y_EN = 0x0
3863 10:01:22.879266 WORK_FSP = 0x0
3864 10:01:22.879365 WL = 0x2
3865 10:01:22.882616 RL = 0x2
3866 10:01:22.882713 BL = 0x2
3867 10:01:22.885796 RPST = 0x0
3868 10:01:22.885879 RD_PRE = 0x0
3869 10:01:22.889220 WR_PRE = 0x1
3870 10:01:22.889304 WR_PST = 0x0
3871 10:01:22.892336 DBI_WR = 0x0
3872 10:01:22.892419 DBI_RD = 0x0
3873 10:01:22.896035 OTF = 0x1
3874 10:01:22.898874 ===================================
3875 10:01:22.902298 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 10:01:22.905982 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 10:01:22.912870 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 10:01:22.916105 ===================================
3879 10:01:22.916187 LPDDR4 DRAM CONFIGURATION
3880 10:01:22.919088 ===================================
3881 10:01:22.922351 EX_ROW_EN[0] = 0x10
3882 10:01:22.922433 EX_ROW_EN[1] = 0x0
3883 10:01:22.925538 LP4Y_EN = 0x0
3884 10:01:22.925622 WORK_FSP = 0x0
3885 10:01:22.929047 WL = 0x2
3886 10:01:22.932760 RL = 0x2
3887 10:01:22.932881 BL = 0x2
3888 10:01:22.935718 RPST = 0x0
3889 10:01:22.935799 RD_PRE = 0x0
3890 10:01:22.938997 WR_PRE = 0x1
3891 10:01:22.939109 WR_PST = 0x0
3892 10:01:22.942183 DBI_WR = 0x0
3893 10:01:22.942286 DBI_RD = 0x0
3894 10:01:22.945741 OTF = 0x1
3895 10:01:22.948749 ===================================
3896 10:01:22.952419 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 10:01:22.957950 nWR fixed to 30
3898 10:01:22.961150 [ModeRegInit_LP4] CH0 RK0
3899 10:01:22.961248 [ModeRegInit_LP4] CH0 RK1
3900 10:01:22.964133 [ModeRegInit_LP4] CH1 RK0
3901 10:01:22.967800 [ModeRegInit_LP4] CH1 RK1
3902 10:01:22.967897 match AC timing 17
3903 10:01:22.974384 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 10:01:22.978094 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 10:01:22.981213 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 10:01:22.987529 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 10:01:22.990899 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 10:01:22.991003 ==
3909 10:01:22.994134 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 10:01:22.997869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 10:01:22.997964 ==
3912 10:01:23.004160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 10:01:23.010949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3914 10:01:23.014532 [CA 0] Center 36 (6~67) winsize 62
3915 10:01:23.017525 [CA 1] Center 36 (6~67) winsize 62
3916 10:01:23.021018 [CA 2] Center 34 (4~65) winsize 62
3917 10:01:23.024148 [CA 3] Center 34 (4~65) winsize 62
3918 10:01:23.027461 [CA 4] Center 33 (3~64) winsize 62
3919 10:01:23.030930 [CA 5] Center 33 (2~64) winsize 63
3920 10:01:23.031043
3921 10:01:23.034340 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3922 10:01:23.034417
3923 10:01:23.037697 [CATrainingPosCal] consider 1 rank data
3924 10:01:23.041102 u2DelayCellTimex100 = 270/100 ps
3925 10:01:23.044308 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 10:01:23.047859 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 10:01:23.051309 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 10:01:23.054398 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3929 10:01:23.057858 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3930 10:01:23.060960 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3931 10:01:23.061043
3932 10:01:23.067536 CA PerBit enable=1, Macro0, CA PI delay=33
3933 10:01:23.067619
3934 10:01:23.070984 [CBTSetCACLKResult] CA Dly = 33
3935 10:01:23.071066 CS Dly: 5 (0~36)
3936 10:01:23.071132 ==
3937 10:01:23.074627 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 10:01:23.077816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 10:01:23.077900 ==
3940 10:01:23.084286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 10:01:23.090829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3942 10:01:23.094431 [CA 0] Center 36 (6~67) winsize 62
3943 10:01:23.097510 [CA 1] Center 36 (6~67) winsize 62
3944 10:01:23.101065 [CA 2] Center 35 (5~66) winsize 62
3945 10:01:23.104254 [CA 3] Center 34 (4~65) winsize 62
3946 10:01:23.107628 [CA 4] Center 34 (3~65) winsize 63
3947 10:01:23.111181 [CA 5] Center 34 (3~65) winsize 63
3948 10:01:23.111264
3949 10:01:23.114132 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3950 10:01:23.114215
3951 10:01:23.117742 [CATrainingPosCal] consider 2 rank data
3952 10:01:23.120873 u2DelayCellTimex100 = 270/100 ps
3953 10:01:23.124250 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3954 10:01:23.127615 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3955 10:01:23.131337 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3956 10:01:23.134365 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3957 10:01:23.137421 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 10:01:23.144241 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 10:01:23.144324
3960 10:01:23.147295 CA PerBit enable=1, Macro0, CA PI delay=33
3961 10:01:23.147378
3962 10:01:23.150847 [CBTSetCACLKResult] CA Dly = 33
3963 10:01:23.150943 CS Dly: 6 (0~38)
3964 10:01:23.151022
3965 10:01:23.154127 ----->DramcWriteLeveling(PI) begin...
3966 10:01:23.154236 ==
3967 10:01:23.157540 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 10:01:23.164065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 10:01:23.164149 ==
3970 10:01:23.167188 Write leveling (Byte 0): 35 => 35
3971 10:01:23.167271 Write leveling (Byte 1): 32 => 32
3972 10:01:23.170760 DramcWriteLeveling(PI) end<-----
3973 10:01:23.170843
3974 10:01:23.170907 ==
3975 10:01:23.173883 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 10:01:23.180616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 10:01:23.180700 ==
3978 10:01:23.183694 [Gating] SW mode calibration
3979 10:01:23.190488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 10:01:23.193811 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 10:01:23.200503 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 10:01:23.204005 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 10:01:23.207150 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 10:01:23.213970 0 9 12 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (1 0)
3985 10:01:23.217119 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (1 0)
3986 10:01:23.220484 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 10:01:23.224063 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 10:01:23.230491 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 10:01:23.234051 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 10:01:23.237389 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 10:01:23.243911 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3992 10:01:23.247196 0 10 12 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
3993 10:01:23.250573 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3994 10:01:23.257189 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 10:01:23.260316 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 10:01:23.263618 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 10:01:23.270606 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 10:01:23.273798 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 10:01:23.277431 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 10:01:23.284054 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 10:01:23.287106 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4002 10:01:23.290417 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 10:01:23.297350 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 10:01:23.300324 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 10:01:23.303646 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 10:01:23.310507 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 10:01:23.313985 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 10:01:23.317232 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 10:01:23.320506 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 10:01:23.327132 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 10:01:23.330697 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 10:01:23.333931 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 10:01:23.340810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 10:01:23.343723 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 10:01:23.347272 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 10:01:23.353809 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4017 10:01:23.356966 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4018 10:01:23.360456 Total UI for P1: 0, mck2ui 16
4019 10:01:23.363844 best dqsien dly found for B0: ( 0, 13, 14)
4020 10:01:23.367341 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 10:01:23.370590 Total UI for P1: 0, mck2ui 16
4022 10:01:23.373637 best dqsien dly found for B1: ( 0, 13, 14)
4023 10:01:23.377271 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4024 10:01:23.380611 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4025 10:01:23.380693
4026 10:01:23.386895 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4027 10:01:23.390172 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4028 10:01:23.393560 [Gating] SW calibration Done
4029 10:01:23.393647 ==
4030 10:01:23.397003 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 10:01:23.400115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 10:01:23.400202 ==
4033 10:01:23.400295 RX Vref Scan: 0
4034 10:01:23.400386
4035 10:01:23.403681 RX Vref 0 -> 0, step: 1
4036 10:01:23.403788
4037 10:01:23.407085 RX Delay -230 -> 252, step: 16
4038 10:01:23.410093 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4039 10:01:23.416734 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4040 10:01:23.419931 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4041 10:01:23.423531 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4042 10:01:23.427170 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4043 10:01:23.430511 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4044 10:01:23.436956 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4045 10:01:23.440090 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4046 10:01:23.443440 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4047 10:01:23.446720 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4048 10:01:23.450194 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4049 10:01:23.456743 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4050 10:01:23.460018 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4051 10:01:23.463243 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4052 10:01:23.467019 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4053 10:01:23.473380 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4054 10:01:23.473463 ==
4055 10:01:23.476741 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 10:01:23.479848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 10:01:23.479931 ==
4058 10:01:23.479996 DQS Delay:
4059 10:01:23.483101 DQS0 = 0, DQS1 = 0
4060 10:01:23.483183 DQM Delay:
4061 10:01:23.486726 DQM0 = 52, DQM1 = 42
4062 10:01:23.486826 DQ Delay:
4063 10:01:23.489945 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4064 10:01:23.492968 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4065 10:01:23.496726 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4066 10:01:23.500118 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4067 10:01:23.500232
4068 10:01:23.500326
4069 10:01:23.500422 ==
4070 10:01:23.503290 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 10:01:23.506511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 10:01:23.509745 ==
4073 10:01:23.509850
4074 10:01:23.509939
4075 10:01:23.510032 TX Vref Scan disable
4076 10:01:23.513267 == TX Byte 0 ==
4077 10:01:23.516317 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4078 10:01:23.519962 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4079 10:01:23.522922 == TX Byte 1 ==
4080 10:01:23.526418 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4081 10:01:23.529659 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4082 10:01:23.532905 ==
4083 10:01:23.536327 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 10:01:23.539874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 10:01:23.539948 ==
4086 10:01:23.540008
4087 10:01:23.540066
4088 10:01:23.543087 TX Vref Scan disable
4089 10:01:23.543185 == TX Byte 0 ==
4090 10:01:23.549632 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4091 10:01:23.552870 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4092 10:01:23.552942 == TX Byte 1 ==
4093 10:01:23.559702 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4094 10:01:23.562849 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4095 10:01:23.562923
4096 10:01:23.562984 [DATLAT]
4097 10:01:23.566497 Freq=600, CH0 RK0
4098 10:01:23.566575
4099 10:01:23.566654 DATLAT Default: 0x9
4100 10:01:23.569754 0, 0xFFFF, sum = 0
4101 10:01:23.569828 1, 0xFFFF, sum = 0
4102 10:01:23.573085 2, 0xFFFF, sum = 0
4103 10:01:23.573162 3, 0xFFFF, sum = 0
4104 10:01:23.576262 4, 0xFFFF, sum = 0
4105 10:01:23.580122 5, 0xFFFF, sum = 0
4106 10:01:23.580206 6, 0xFFFF, sum = 0
4107 10:01:23.583010 7, 0xFFFF, sum = 0
4108 10:01:23.583098 8, 0x0, sum = 1
4109 10:01:23.583164 9, 0x0, sum = 2
4110 10:01:23.586199 10, 0x0, sum = 3
4111 10:01:23.586284 11, 0x0, sum = 4
4112 10:01:23.589774 best_step = 9
4113 10:01:23.589905
4114 10:01:23.590052 ==
4115 10:01:23.593168 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 10:01:23.596428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 10:01:23.596512 ==
4118 10:01:23.599445 RX Vref Scan: 1
4119 10:01:23.599529
4120 10:01:23.599593 RX Vref 0 -> 0, step: 1
4121 10:01:23.599654
4122 10:01:23.602823 RX Delay -179 -> 252, step: 8
4123 10:01:23.602906
4124 10:01:23.606419 Set Vref, RX VrefLevel [Byte0]: 57
4125 10:01:23.609512 [Byte1]: 48
4126 10:01:23.613603
4127 10:01:23.613710 Final RX Vref Byte 0 = 57 to rank0
4128 10:01:23.616648 Final RX Vref Byte 1 = 48 to rank0
4129 10:01:23.620109 Final RX Vref Byte 0 = 57 to rank1
4130 10:01:23.623670 Final RX Vref Byte 1 = 48 to rank1==
4131 10:01:23.626823 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 10:01:23.633320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 10:01:23.633402 ==
4134 10:01:23.633467 DQS Delay:
4135 10:01:23.633527 DQS0 = 0, DQS1 = 0
4136 10:01:23.636615 DQM Delay:
4137 10:01:23.636738 DQM0 = 50, DQM1 = 39
4138 10:01:23.639851 DQ Delay:
4139 10:01:23.643489 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =48
4140 10:01:23.646691 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4141 10:01:23.649837 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4142 10:01:23.653466 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4143 10:01:23.653548
4144 10:01:23.653612
4145 10:01:23.659755 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4146 10:01:23.663378 CH0 RK0: MR19=808, MR18=5B56
4147 10:01:23.670013 CH0_RK0: MR19=0x808, MR18=0x5B56, DQSOSC=392, MR23=63, INC=170, DEC=113
4148 10:01:23.670097
4149 10:01:23.673058 ----->DramcWriteLeveling(PI) begin...
4150 10:01:23.673143 ==
4151 10:01:23.676550 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 10:01:23.679757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 10:01:23.679840 ==
4154 10:01:23.683202 Write leveling (Byte 0): 35 => 35
4155 10:01:23.686451 Write leveling (Byte 1): 30 => 30
4156 10:01:23.689764 DramcWriteLeveling(PI) end<-----
4157 10:01:23.689847
4158 10:01:23.689912 ==
4159 10:01:23.693573 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 10:01:23.696762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 10:01:23.696859 ==
4162 10:01:23.700015 [Gating] SW mode calibration
4163 10:01:23.706725 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4164 10:01:23.713378 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4165 10:01:23.716405 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 10:01:23.719896 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 10:01:23.726568 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 10:01:23.730029 0 9 12 | B1->B0 | 3131 3232 | 1 0 | (1 0) (0 0)
4169 10:01:23.733347 0 9 16 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
4170 10:01:23.739699 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 10:01:23.743279 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 10:01:23.746447 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 10:01:23.753233 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 10:01:23.756368 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 10:01:23.759777 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 10:01:23.766353 0 10 12 | B1->B0 | 2c2c 2e2d | 0 1 | (0 0) (1 1)
4177 10:01:23.769975 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4178 10:01:23.773097 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 10:01:23.779849 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 10:01:23.783544 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 10:01:23.786667 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 10:01:23.793358 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 10:01:23.796534 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 10:01:23.799975 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4185 10:01:23.803047 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 10:01:23.809793 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 10:01:23.813187 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 10:01:23.816336 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 10:01:23.823013 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 10:01:23.826603 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 10:01:23.830002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 10:01:23.836613 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 10:01:23.839593 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 10:01:23.842955 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 10:01:23.849841 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 10:01:23.853030 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 10:01:23.856225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 10:01:23.863044 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 10:01:23.866499 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 10:01:23.870017 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4201 10:01:23.876633 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4202 10:01:23.879840 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 10:01:23.883218 Total UI for P1: 0, mck2ui 16
4204 10:01:23.886619 best dqsien dly found for B0: ( 0, 13, 14)
4205 10:01:23.889702 Total UI for P1: 0, mck2ui 16
4206 10:01:23.893547 best dqsien dly found for B1: ( 0, 13, 14)
4207 10:01:23.896238 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4208 10:01:23.900017 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4209 10:01:23.900101
4210 10:01:23.903035 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4211 10:01:23.906626 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4212 10:01:23.909836 [Gating] SW calibration Done
4213 10:01:23.909919 ==
4214 10:01:23.913235 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 10:01:23.916650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 10:01:23.916768 ==
4217 10:01:23.920021 RX Vref Scan: 0
4218 10:01:23.920104
4219 10:01:23.923086 RX Vref 0 -> 0, step: 1
4220 10:01:23.923169
4221 10:01:23.923234 RX Delay -230 -> 252, step: 16
4222 10:01:23.929881 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4223 10:01:23.933343 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4224 10:01:23.936687 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4225 10:01:23.939964 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4226 10:01:23.946405 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4227 10:01:23.949922 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4228 10:01:23.953044 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4229 10:01:23.956563 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4230 10:01:23.959754 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4231 10:01:23.966676 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4232 10:01:23.969765 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4233 10:01:23.973163 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4234 10:01:23.976887 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4235 10:01:23.983339 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4236 10:01:23.986572 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4237 10:01:23.989857 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4238 10:01:23.989941 ==
4239 10:01:23.993538 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 10:01:23.996886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 10:01:23.996969 ==
4242 10:01:24.000014 DQS Delay:
4243 10:01:24.000141 DQS0 = 0, DQS1 = 0
4244 10:01:24.003571 DQM Delay:
4245 10:01:24.003654 DQM0 = 48, DQM1 = 41
4246 10:01:24.003719 DQ Delay:
4247 10:01:24.006720 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4248 10:01:24.010099 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4249 10:01:24.013379 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4250 10:01:24.016298 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4251 10:01:24.016383
4252 10:01:24.016450
4253 10:01:24.019955 ==
4254 10:01:24.022990 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 10:01:24.026962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 10:01:24.027045 ==
4257 10:01:24.027110
4258 10:01:24.027168
4259 10:01:24.029613 TX Vref Scan disable
4260 10:01:24.029696 == TX Byte 0 ==
4261 10:01:24.036569 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4262 10:01:24.039598 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4263 10:01:24.039681 == TX Byte 1 ==
4264 10:01:24.046350 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4265 10:01:24.049664 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4266 10:01:24.049747 ==
4267 10:01:24.053270 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 10:01:24.056519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 10:01:24.056619 ==
4270 10:01:24.056686
4271 10:01:24.056748
4272 10:01:24.059489 TX Vref Scan disable
4273 10:01:24.063160 == TX Byte 0 ==
4274 10:01:24.066214 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4275 10:01:24.069423 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4276 10:01:24.073421 == TX Byte 1 ==
4277 10:01:24.076046 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4278 10:01:24.079654 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4279 10:01:24.082676
4280 10:01:24.082759 [DATLAT]
4281 10:01:24.082824 Freq=600, CH0 RK1
4282 10:01:24.082884
4283 10:01:24.086164 DATLAT Default: 0x9
4284 10:01:24.086246 0, 0xFFFF, sum = 0
4285 10:01:24.089398 1, 0xFFFF, sum = 0
4286 10:01:24.089483 2, 0xFFFF, sum = 0
4287 10:01:24.092790 3, 0xFFFF, sum = 0
4288 10:01:24.092874 4, 0xFFFF, sum = 0
4289 10:01:24.095951 5, 0xFFFF, sum = 0
4290 10:01:24.096035 6, 0xFFFF, sum = 0
4291 10:01:24.099381 7, 0xFFFF, sum = 0
4292 10:01:24.099465 8, 0x0, sum = 1
4293 10:01:24.102644 9, 0x0, sum = 2
4294 10:01:24.102727 10, 0x0, sum = 3
4295 10:01:24.105974 11, 0x0, sum = 4
4296 10:01:24.106057 best_step = 9
4297 10:01:24.106120
4298 10:01:24.106179 ==
4299 10:01:24.109386 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 10:01:24.116141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 10:01:24.116222 ==
4302 10:01:24.116285 RX Vref Scan: 0
4303 10:01:24.116376
4304 10:01:24.119302 RX Vref 0 -> 0, step: 1
4305 10:01:24.119396
4306 10:01:24.122668 RX Delay -179 -> 252, step: 8
4307 10:01:24.126095 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4308 10:01:24.132607 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4309 10:01:24.136050 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4310 10:01:24.139197 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4311 10:01:24.142605 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4312 10:01:24.146163 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4313 10:01:24.149280 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4314 10:01:24.156110 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4315 10:01:24.159187 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4316 10:01:24.162708 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4317 10:01:24.165771 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4318 10:01:24.172722 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4319 10:01:24.176218 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4320 10:01:24.179409 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4321 10:01:24.182403 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4322 10:01:24.186008 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4323 10:01:24.189064 ==
4324 10:01:24.192629 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 10:01:24.195735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 10:01:24.195824 ==
4327 10:01:24.195886 DQS Delay:
4328 10:01:24.198999 DQS0 = 0, DQS1 = 0
4329 10:01:24.199117 DQM Delay:
4330 10:01:24.202435 DQM0 = 48, DQM1 = 40
4331 10:01:24.202514 DQ Delay:
4332 10:01:24.205931 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4333 10:01:24.209274 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4334 10:01:24.212770 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4335 10:01:24.215927 DQ12 =44, DQ13 =44, DQ14 =52, DQ15 =44
4336 10:01:24.216007
4337 10:01:24.216069
4338 10:01:24.222918 [DQSOSCAuto] RK1, (LSB)MR18= 0x6432, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4339 10:01:24.226169 CH0 RK1: MR19=808, MR18=6432
4340 10:01:24.232855 CH0_RK1: MR19=0x808, MR18=0x6432, DQSOSC=391, MR23=63, INC=171, DEC=114
4341 10:01:24.235888 [RxdqsGatingPostProcess] freq 600
4342 10:01:24.239329 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4343 10:01:24.242525 Pre-setting of DQS Precalculation
4344 10:01:24.249202 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4345 10:01:24.249307 ==
4346 10:01:24.252413 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 10:01:24.256018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 10:01:24.256229 ==
4349 10:01:24.262446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 10:01:24.268943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4351 10:01:24.272447 [CA 0] Center 35 (5~66) winsize 62
4352 10:01:24.275823 [CA 1] Center 35 (5~66) winsize 62
4353 10:01:24.279238 [CA 2] Center 34 (4~65) winsize 62
4354 10:01:24.282267 [CA 3] Center 33 (3~64) winsize 62
4355 10:01:24.285904 [CA 4] Center 33 (3~64) winsize 62
4356 10:01:24.288938 [CA 5] Center 33 (3~64) winsize 62
4357 10:01:24.289022
4358 10:01:24.292270 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4359 10:01:24.292357
4360 10:01:24.295489 [CATrainingPosCal] consider 1 rank data
4361 10:01:24.299134 u2DelayCellTimex100 = 270/100 ps
4362 10:01:24.302252 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4363 10:01:24.305393 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4364 10:01:24.309000 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 10:01:24.312018 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 10:01:24.315570 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4367 10:01:24.318746 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 10:01:24.318825
4369 10:01:24.325405 CA PerBit enable=1, Macro0, CA PI delay=33
4370 10:01:24.325486
4371 10:01:24.325553 [CBTSetCACLKResult] CA Dly = 33
4372 10:01:24.328689 CS Dly: 4 (0~35)
4373 10:01:24.328773 ==
4374 10:01:24.332131 Dram Type= 6, Freq= 0, CH_1, rank 1
4375 10:01:24.335541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 10:01:24.335652 ==
4377 10:01:24.341991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 10:01:24.348641 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4379 10:01:24.352207 [CA 0] Center 35 (5~66) winsize 62
4380 10:01:24.355622 [CA 1] Center 35 (5~66) winsize 62
4381 10:01:24.358606 [CA 2] Center 34 (4~65) winsize 62
4382 10:01:24.362180 [CA 3] Center 34 (4~64) winsize 61
4383 10:01:24.365234 [CA 4] Center 34 (4~65) winsize 62
4384 10:01:24.368906 [CA 5] Center 33 (3~64) winsize 62
4385 10:01:24.368991
4386 10:01:24.371845 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4387 10:01:24.371929
4388 10:01:24.375534 [CATrainingPosCal] consider 2 rank data
4389 10:01:24.378511 u2DelayCellTimex100 = 270/100 ps
4390 10:01:24.382082 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4391 10:01:24.385395 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4392 10:01:24.388956 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 10:01:24.391994 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4394 10:01:24.395517 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4395 10:01:24.398915 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 10:01:24.398999
4397 10:01:24.405404 CA PerBit enable=1, Macro0, CA PI delay=33
4398 10:01:24.405487
4399 10:01:24.408938 [CBTSetCACLKResult] CA Dly = 33
4400 10:01:24.409021 CS Dly: 4 (0~36)
4401 10:01:24.409086
4402 10:01:24.411896 ----->DramcWriteLeveling(PI) begin...
4403 10:01:24.411981 ==
4404 10:01:24.415293 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 10:01:24.418457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 10:01:24.418541 ==
4407 10:01:24.422313 Write leveling (Byte 0): 30 => 30
4408 10:01:24.425421 Write leveling (Byte 1): 30 => 30
4409 10:01:24.428620 DramcWriteLeveling(PI) end<-----
4410 10:01:24.428703
4411 10:01:24.428787 ==
4412 10:01:24.431954 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 10:01:24.438677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 10:01:24.438761 ==
4415 10:01:24.438828 [Gating] SW mode calibration
4416 10:01:24.448495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 10:01:24.451940 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4418 10:01:24.455288 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 10:01:24.462061 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 10:01:24.465437 0 9 8 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 1)
4421 10:01:24.468928 0 9 12 | B1->B0 | 2e2e 2c2c | 1 1 | (1 0) (1 0)
4422 10:01:24.475023 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 10:01:24.478745 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 10:01:24.481910 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 10:01:24.488451 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 10:01:24.491959 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 10:01:24.495583 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 10:01:24.501825 0 10 8 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
4429 10:01:24.505402 0 10 12 | B1->B0 | 3939 4141 | 1 0 | (0 0) (0 0)
4430 10:01:24.508458 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 10:01:24.515114 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 10:01:24.518810 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 10:01:24.521768 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 10:01:24.525503 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 10:01:24.532045 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 10:01:24.535318 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 10:01:24.538516 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4438 10:01:24.545060 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 10:01:24.548393 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 10:01:24.551997 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 10:01:24.558365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 10:01:24.561741 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 10:01:24.565151 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 10:01:24.571734 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 10:01:24.575187 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 10:01:24.578402 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 10:01:24.585245 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 10:01:24.588264 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 10:01:24.591613 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 10:01:24.598257 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 10:01:24.601703 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 10:01:24.604952 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4453 10:01:24.611614 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4454 10:01:24.614922 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 10:01:24.618354 Total UI for P1: 0, mck2ui 16
4456 10:01:24.621871 best dqsien dly found for B0: ( 0, 13, 10)
4457 10:01:24.625283 Total UI for P1: 0, mck2ui 16
4458 10:01:24.628490 best dqsien dly found for B1: ( 0, 13, 12)
4459 10:01:24.632007 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4460 10:01:24.634980 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4461 10:01:24.635088
4462 10:01:24.638274 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4463 10:01:24.641744 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4464 10:01:24.645235 [Gating] SW calibration Done
4465 10:01:24.645341 ==
4466 10:01:24.648213 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 10:01:24.651742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 10:01:24.651843 ==
4469 10:01:24.655234 RX Vref Scan: 0
4470 10:01:24.655342
4471 10:01:24.658680 RX Vref 0 -> 0, step: 1
4472 10:01:24.658786
4473 10:01:24.658881 RX Delay -230 -> 252, step: 16
4474 10:01:24.665030 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4475 10:01:24.668245 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4476 10:01:24.671925 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4477 10:01:24.675295 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4478 10:01:24.681983 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4479 10:01:24.685133 iDelay=218, Bit 5, Center 73 (-70 ~ 217) 288
4480 10:01:24.688900 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4481 10:01:24.691780 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4482 10:01:24.695069 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4483 10:01:24.702077 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4484 10:01:24.705078 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4485 10:01:24.708397 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4486 10:01:24.711828 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4487 10:01:24.718701 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4488 10:01:24.721994 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4489 10:01:24.725255 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4490 10:01:24.725338 ==
4491 10:01:24.728339 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 10:01:24.731683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 10:01:24.731766 ==
4494 10:01:24.735169 DQS Delay:
4495 10:01:24.735252 DQS0 = 0, DQS1 = 0
4496 10:01:24.738725 DQM Delay:
4497 10:01:24.738808 DQM0 = 53, DQM1 = 40
4498 10:01:24.738873 DQ Delay:
4499 10:01:24.741817 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4500 10:01:24.745215 DQ4 =49, DQ5 =73, DQ6 =57, DQ7 =49
4501 10:01:24.748138 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4502 10:01:24.751722 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4503 10:01:24.751805
4504 10:01:24.751870
4505 10:01:24.754968 ==
4506 10:01:24.758240 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 10:01:24.761668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 10:01:24.761752 ==
4509 10:01:24.761817
4510 10:01:24.761877
4511 10:01:24.764921 TX Vref Scan disable
4512 10:01:24.765004 == TX Byte 0 ==
4513 10:01:24.771358 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4514 10:01:24.774809 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4515 10:01:24.774892 == TX Byte 1 ==
4516 10:01:24.781351 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4517 10:01:24.785081 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4518 10:01:24.785164 ==
4519 10:01:24.788062 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 10:01:24.791621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 10:01:24.791704 ==
4522 10:01:24.791769
4523 10:01:24.791827
4524 10:01:24.794731 TX Vref Scan disable
4525 10:01:24.798011 == TX Byte 0 ==
4526 10:01:24.801367 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4527 10:01:24.804924 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4528 10:01:24.808321 == TX Byte 1 ==
4529 10:01:24.811439 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4530 10:01:24.814716 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4531 10:01:24.814799
4532 10:01:24.818289 [DATLAT]
4533 10:01:24.818371 Freq=600, CH1 RK0
4534 10:01:24.818435
4535 10:01:24.821642 DATLAT Default: 0x9
4536 10:01:24.821724 0, 0xFFFF, sum = 0
4537 10:01:24.824818 1, 0xFFFF, sum = 0
4538 10:01:24.824905 2, 0xFFFF, sum = 0
4539 10:01:24.828196 3, 0xFFFF, sum = 0
4540 10:01:24.828280 4, 0xFFFF, sum = 0
4541 10:01:24.831651 5, 0xFFFF, sum = 0
4542 10:01:24.831724 6, 0xFFFF, sum = 0
4543 10:01:24.835199 7, 0xFFFF, sum = 0
4544 10:01:24.835283 8, 0x0, sum = 1
4545 10:01:24.838234 9, 0x0, sum = 2
4546 10:01:24.838317 10, 0x0, sum = 3
4547 10:01:24.841346 11, 0x0, sum = 4
4548 10:01:24.841429 best_step = 9
4549 10:01:24.841494
4550 10:01:24.841554 ==
4551 10:01:24.845072 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 10:01:24.848215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 10:01:24.848297 ==
4554 10:01:24.851749 RX Vref Scan: 1
4555 10:01:24.851831
4556 10:01:24.855053 RX Vref 0 -> 0, step: 1
4557 10:01:24.855134
4558 10:01:24.855200 RX Delay -179 -> 252, step: 8
4559 10:01:24.855261
4560 10:01:24.857975 Set Vref, RX VrefLevel [Byte0]: 51
4561 10:01:24.861366 [Byte1]: 58
4562 10:01:24.866162
4563 10:01:24.866243 Final RX Vref Byte 0 = 51 to rank0
4564 10:01:24.869339 Final RX Vref Byte 1 = 58 to rank0
4565 10:01:24.872719 Final RX Vref Byte 0 = 51 to rank1
4566 10:01:24.876314 Final RX Vref Byte 1 = 58 to rank1==
4567 10:01:24.879355 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 10:01:24.886230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 10:01:24.886313 ==
4570 10:01:24.886377 DQS Delay:
4571 10:01:24.886438 DQS0 = 0, DQS1 = 0
4572 10:01:24.889277 DQM Delay:
4573 10:01:24.889384 DQM0 = 48, DQM1 = 41
4574 10:01:24.892559 DQ Delay:
4575 10:01:24.896254 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4576 10:01:24.899215 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4577 10:01:24.902503 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4578 10:01:24.906083 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4579 10:01:24.906165
4580 10:01:24.906229
4581 10:01:24.912586 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4582 10:01:24.915989 CH1 RK0: MR19=808, MR18=4E74
4583 10:01:24.922562 CH1_RK0: MR19=0x808, MR18=0x4E74, DQSOSC=388, MR23=63, INC=174, DEC=116
4584 10:01:24.922645
4585 10:01:24.926017 ----->DramcWriteLeveling(PI) begin...
4586 10:01:24.926101 ==
4587 10:01:24.929112 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 10:01:24.932279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 10:01:24.932367 ==
4590 10:01:24.935830 Write leveling (Byte 0): 30 => 30
4591 10:01:24.939304 Write leveling (Byte 1): 32 => 32
4592 10:01:24.942960 DramcWriteLeveling(PI) end<-----
4593 10:01:24.943043
4594 10:01:24.943107 ==
4595 10:01:24.945982 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 10:01:24.949627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 10:01:24.949714 ==
4598 10:01:24.952706 [Gating] SW mode calibration
4599 10:01:24.959546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4600 10:01:24.965950 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4601 10:01:24.969082 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 10:01:24.972459 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 10:01:24.979029 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (0 1) (1 1)
4604 10:01:24.982239 0 9 12 | B1->B0 | 2929 3030 | 1 0 | (1 0) (0 0)
4605 10:01:24.985759 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4606 10:01:24.992482 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 10:01:24.995675 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 10:01:24.999294 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 10:01:25.005459 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 10:01:25.009154 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 10:01:25.012298 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4612 10:01:25.018683 0 10 12 | B1->B0 | 3c3c 2e2e | 0 0 | (0 0) (0 0)
4613 10:01:25.022134 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 10:01:25.025551 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 10:01:25.032159 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 10:01:25.035299 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 10:01:25.038679 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 10:01:25.045280 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 10:01:25.048722 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 10:01:25.051924 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4621 10:01:25.058383 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 10:01:25.061838 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 10:01:25.065010 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 10:01:25.071582 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 10:01:25.074849 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 10:01:25.078231 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 10:01:25.084862 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 10:01:25.088416 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 10:01:25.091549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 10:01:25.098471 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 10:01:25.101588 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 10:01:25.104994 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 10:01:25.111240 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 10:01:25.114520 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 10:01:25.118143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 10:01:25.124809 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4637 10:01:25.127948 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 10:01:25.131427 Total UI for P1: 0, mck2ui 16
4639 10:01:25.134961 best dqsien dly found for B0: ( 0, 13, 12)
4640 10:01:25.137807 Total UI for P1: 0, mck2ui 16
4641 10:01:25.141248 best dqsien dly found for B1: ( 0, 13, 12)
4642 10:01:25.144477 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4643 10:01:25.147844 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4644 10:01:25.147927
4645 10:01:25.151373 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4646 10:01:25.154608 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4647 10:01:25.158087 [Gating] SW calibration Done
4648 10:01:25.158169 ==
4649 10:01:25.161437 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 10:01:25.164575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 10:01:25.164701 ==
4652 10:01:25.168174 RX Vref Scan: 0
4653 10:01:25.168256
4654 10:01:25.171417 RX Vref 0 -> 0, step: 1
4655 10:01:25.171500
4656 10:01:25.171565 RX Delay -230 -> 252, step: 16
4657 10:01:25.178472 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4658 10:01:25.181920 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4659 10:01:25.185372 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4660 10:01:25.188275 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4661 10:01:25.195045 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4662 10:01:25.198193 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4663 10:01:25.201506 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4664 10:01:25.204785 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4665 10:01:25.208324 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4666 10:01:25.214783 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4667 10:01:25.218046 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4668 10:01:25.221461 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4669 10:01:25.225003 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4670 10:01:25.228076 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4671 10:01:25.234944 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4672 10:01:25.238174 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4673 10:01:25.238295 ==
4674 10:01:25.241666 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 10:01:25.245129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 10:01:25.245249 ==
4677 10:01:25.248474 DQS Delay:
4678 10:01:25.248593 DQS0 = 0, DQS1 = 0
4679 10:01:25.248702 DQM Delay:
4680 10:01:25.251461 DQM0 = 52, DQM1 = 47
4681 10:01:25.251579 DQ Delay:
4682 10:01:25.254975 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4683 10:01:25.258154 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4684 10:01:25.261721 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4685 10:01:25.264940 DQ12 =65, DQ13 =57, DQ14 =49, DQ15 =57
4686 10:01:25.265060
4687 10:01:25.265166
4688 10:01:25.265274 ==
4689 10:01:25.268358 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 10:01:25.274880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 10:01:25.275004 ==
4692 10:01:25.275160
4693 10:01:25.275265
4694 10:01:25.275374 TX Vref Scan disable
4695 10:01:25.278882 == TX Byte 0 ==
4696 10:01:25.281967 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4697 10:01:25.285218 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4698 10:01:25.288652 == TX Byte 1 ==
4699 10:01:25.292269 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4700 10:01:25.295499 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4701 10:01:25.298496 ==
4702 10:01:25.301965 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 10:01:25.305484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 10:01:25.305568 ==
4705 10:01:25.305633
4706 10:01:25.305693
4707 10:01:25.308582 TX Vref Scan disable
4708 10:01:25.311963 == TX Byte 0 ==
4709 10:01:25.315309 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4710 10:01:25.318658 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4711 10:01:25.321937 == TX Byte 1 ==
4712 10:01:25.325455 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4713 10:01:25.328571 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4714 10:01:25.328657
4715 10:01:25.328720 [DATLAT]
4716 10:01:25.332101 Freq=600, CH1 RK1
4717 10:01:25.332168
4718 10:01:25.332227 DATLAT Default: 0x9
4719 10:01:25.335228 0, 0xFFFF, sum = 0
4720 10:01:25.335311 1, 0xFFFF, sum = 0
4721 10:01:25.338626 2, 0xFFFF, sum = 0
4722 10:01:25.338708 3, 0xFFFF, sum = 0
4723 10:01:25.341770 4, 0xFFFF, sum = 0
4724 10:01:25.345184 5, 0xFFFF, sum = 0
4725 10:01:25.345267 6, 0xFFFF, sum = 0
4726 10:01:25.348722 7, 0xFFFF, sum = 0
4727 10:01:25.348827 8, 0x0, sum = 1
4728 10:01:25.348893 9, 0x0, sum = 2
4729 10:01:25.351946 10, 0x0, sum = 3
4730 10:01:25.352030 11, 0x0, sum = 4
4731 10:01:25.355096 best_step = 9
4732 10:01:25.355178
4733 10:01:25.355241 ==
4734 10:01:25.358469 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 10:01:25.361597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 10:01:25.361679 ==
4737 10:01:25.365260 RX Vref Scan: 0
4738 10:01:25.365341
4739 10:01:25.365404 RX Vref 0 -> 0, step: 1
4740 10:01:25.365464
4741 10:01:25.368523 RX Delay -179 -> 252, step: 8
4742 10:01:25.375624 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4743 10:01:25.379244 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4744 10:01:25.382476 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4745 10:01:25.385600 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4746 10:01:25.392308 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4747 10:01:25.395612 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4748 10:01:25.399167 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4749 10:01:25.402211 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4750 10:01:25.405353 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4751 10:01:25.412269 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4752 10:01:25.415384 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4753 10:01:25.418910 iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304
4754 10:01:25.422119 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4755 10:01:25.425380 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4756 10:01:25.431978 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4757 10:01:25.435588 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4758 10:01:25.435684 ==
4759 10:01:25.438754 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 10:01:25.442260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 10:01:25.442342 ==
4762 10:01:25.445431 DQS Delay:
4763 10:01:25.445512 DQS0 = 0, DQS1 = 0
4764 10:01:25.445576 DQM Delay:
4765 10:01:25.448792 DQM0 = 49, DQM1 = 42
4766 10:01:25.448874 DQ Delay:
4767 10:01:25.452084 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4768 10:01:25.455458 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4769 10:01:25.458975 DQ8 =24, DQ9 =32, DQ10 =48, DQ11 =36
4770 10:01:25.462056 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4771 10:01:25.462137
4772 10:01:25.462201
4773 10:01:25.471997 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4774 10:01:25.472081 CH1 RK1: MR19=808, MR18=5A20
4775 10:01:25.478654 CH1_RK1: MR19=0x808, MR18=0x5A20, DQSOSC=392, MR23=63, INC=170, DEC=113
4776 10:01:25.482216 [RxdqsGatingPostProcess] freq 600
4777 10:01:25.488510 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4778 10:01:25.492016 Pre-setting of DQS Precalculation
4779 10:01:25.495280 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4780 10:01:25.502000 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4781 10:01:25.511896 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4782 10:01:25.511978
4783 10:01:25.512042
4784 10:01:25.515407 [Calibration Summary] 1200 Mbps
4785 10:01:25.515488 CH 0, Rank 0
4786 10:01:25.518392 SW Impedance : PASS
4787 10:01:25.518474 DUTY Scan : NO K
4788 10:01:25.522066 ZQ Calibration : PASS
4789 10:01:25.525128 Jitter Meter : NO K
4790 10:01:25.525253 CBT Training : PASS
4791 10:01:25.528589 Write leveling : PASS
4792 10:01:25.528723 RX DQS gating : PASS
4793 10:01:25.532076 RX DQ/DQS(RDDQC) : PASS
4794 10:01:25.535084 TX DQ/DQS : PASS
4795 10:01:25.535205 RX DATLAT : PASS
4796 10:01:25.538701 RX DQ/DQS(Engine): PASS
4797 10:01:25.541734 TX OE : NO K
4798 10:01:25.541854 All Pass.
4799 10:01:25.541963
4800 10:01:25.542099 CH 0, Rank 1
4801 10:01:25.545388 SW Impedance : PASS
4802 10:01:25.548497 DUTY Scan : NO K
4803 10:01:25.548614 ZQ Calibration : PASS
4804 10:01:25.551906 Jitter Meter : NO K
4805 10:01:25.555005 CBT Training : PASS
4806 10:01:25.555103 Write leveling : PASS
4807 10:01:25.558415 RX DQS gating : PASS
4808 10:01:25.561599 RX DQ/DQS(RDDQC) : PASS
4809 10:01:25.561681 TX DQ/DQS : PASS
4810 10:01:25.565132 RX DATLAT : PASS
4811 10:01:25.568567 RX DQ/DQS(Engine): PASS
4812 10:01:25.568673 TX OE : NO K
4813 10:01:25.568814 All Pass.
4814 10:01:25.568901
4815 10:01:25.571763 CH 1, Rank 0
4816 10:01:25.575242 SW Impedance : PASS
4817 10:01:25.575344 DUTY Scan : NO K
4818 10:01:25.578793 ZQ Calibration : PASS
4819 10:01:25.578874 Jitter Meter : NO K
4820 10:01:25.581975 CBT Training : PASS
4821 10:01:25.585014 Write leveling : PASS
4822 10:01:25.585089 RX DQS gating : PASS
4823 10:01:25.588530 RX DQ/DQS(RDDQC) : PASS
4824 10:01:25.591638 TX DQ/DQS : PASS
4825 10:01:25.591742 RX DATLAT : PASS
4826 10:01:25.595233 RX DQ/DQS(Engine): PASS
4827 10:01:25.598304 TX OE : NO K
4828 10:01:25.598403 All Pass.
4829 10:01:25.598500
4830 10:01:25.598596 CH 1, Rank 1
4831 10:01:25.601982 SW Impedance : PASS
4832 10:01:25.604938 DUTY Scan : NO K
4833 10:01:25.605040 ZQ Calibration : PASS
4834 10:01:25.608527 Jitter Meter : NO K
4835 10:01:25.612001 CBT Training : PASS
4836 10:01:25.612106 Write leveling : PASS
4837 10:01:25.615205 RX DQS gating : PASS
4838 10:01:25.615303 RX DQ/DQS(RDDQC) : PASS
4839 10:01:25.618450 TX DQ/DQS : PASS
4840 10:01:25.621699 RX DATLAT : PASS
4841 10:01:25.621816 RX DQ/DQS(Engine): PASS
4842 10:01:25.625330 TX OE : NO K
4843 10:01:25.625436 All Pass.
4844 10:01:25.625536
4845 10:01:25.628420 DramC Write-DBI off
4846 10:01:25.631803 PER_BANK_REFRESH: Hybrid Mode
4847 10:01:25.631907 TX_TRACKING: ON
4848 10:01:25.641563 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4849 10:01:25.644931 [FAST_K] Save calibration result to emmc
4850 10:01:25.648628 dramc_set_vcore_voltage set vcore to 662500
4851 10:01:25.651905 Read voltage for 933, 3
4852 10:01:25.652011 Vio18 = 0
4853 10:01:25.652114 Vcore = 662500
4854 10:01:25.655186 Vdram = 0
4855 10:01:25.655291 Vddq = 0
4856 10:01:25.655390 Vmddr = 0
4857 10:01:25.661793 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4858 10:01:25.665191 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4859 10:01:25.668464 MEM_TYPE=3, freq_sel=17
4860 10:01:25.671563 sv_algorithm_assistance_LP4_1600
4861 10:01:25.675070 ============ PULL DRAM RESETB DOWN ============
4862 10:01:25.678369 ========== PULL DRAM RESETB DOWN end =========
4863 10:01:25.685062 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4864 10:01:25.688497 ===================================
4865 10:01:25.691786 LPDDR4 DRAM CONFIGURATION
4866 10:01:25.691889 ===================================
4867 10:01:25.695130 EX_ROW_EN[0] = 0x0
4868 10:01:25.698205 EX_ROW_EN[1] = 0x0
4869 10:01:25.698302 LP4Y_EN = 0x0
4870 10:01:25.701732 WORK_FSP = 0x0
4871 10:01:25.701831 WL = 0x3
4872 10:01:25.704958 RL = 0x3
4873 10:01:25.705075 BL = 0x2
4874 10:01:25.708393 RPST = 0x0
4875 10:01:25.708500 RD_PRE = 0x0
4876 10:01:25.711664 WR_PRE = 0x1
4877 10:01:25.711736 WR_PST = 0x0
4878 10:01:25.714841 DBI_WR = 0x0
4879 10:01:25.714913 DBI_RD = 0x0
4880 10:01:25.718134 OTF = 0x1
4881 10:01:25.721606 ===================================
4882 10:01:25.725088 ===================================
4883 10:01:25.725161 ANA top config
4884 10:01:25.728166 ===================================
4885 10:01:25.731558 DLL_ASYNC_EN = 0
4886 10:01:25.735006 ALL_SLAVE_EN = 1
4887 10:01:25.738356 NEW_RANK_MODE = 1
4888 10:01:25.738448 DLL_IDLE_MODE = 1
4889 10:01:25.741607 LP45_APHY_COMB_EN = 1
4890 10:01:25.744769 TX_ODT_DIS = 1
4891 10:01:25.748157 NEW_8X_MODE = 1
4892 10:01:25.751784 ===================================
4893 10:01:25.754940 ===================================
4894 10:01:25.758183 data_rate = 1866
4895 10:01:25.758270 CKR = 1
4896 10:01:25.761788 DQ_P2S_RATIO = 8
4897 10:01:25.765285 ===================================
4898 10:01:25.768566 CA_P2S_RATIO = 8
4899 10:01:25.772269 DQ_CA_OPEN = 0
4900 10:01:25.775225 DQ_SEMI_OPEN = 0
4901 10:01:25.775325 CA_SEMI_OPEN = 0
4902 10:01:25.778330 CA_FULL_RATE = 0
4903 10:01:25.782154 DQ_CKDIV4_EN = 1
4904 10:01:25.785085 CA_CKDIV4_EN = 1
4905 10:01:25.788620 CA_PREDIV_EN = 0
4906 10:01:25.791621 PH8_DLY = 0
4907 10:01:25.791707 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4908 10:01:25.795244 DQ_AAMCK_DIV = 4
4909 10:01:25.798192 CA_AAMCK_DIV = 4
4910 10:01:25.801763 CA_ADMCK_DIV = 4
4911 10:01:25.805381 DQ_TRACK_CA_EN = 0
4912 10:01:25.808182 CA_PICK = 933
4913 10:01:25.811608 CA_MCKIO = 933
4914 10:01:25.811678 MCKIO_SEMI = 0
4915 10:01:25.814975 PLL_FREQ = 3732
4916 10:01:25.818541 DQ_UI_PI_RATIO = 32
4917 10:01:25.821748 CA_UI_PI_RATIO = 0
4918 10:01:25.824994 ===================================
4919 10:01:25.828190 ===================================
4920 10:01:25.831564 memory_type:LPDDR4
4921 10:01:25.831676 GP_NUM : 10
4922 10:01:25.835080 SRAM_EN : 1
4923 10:01:25.835172 MD32_EN : 0
4924 10:01:25.838453 ===================================
4925 10:01:25.841611 [ANA_INIT] >>>>>>>>>>>>>>
4926 10:01:25.844908 <<<<<< [CONFIGURE PHASE]: ANA_TX
4927 10:01:25.848436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4928 10:01:25.851777 ===================================
4929 10:01:25.855130 data_rate = 1866,PCW = 0X8f00
4930 10:01:25.858220 ===================================
4931 10:01:25.861749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4932 10:01:25.868213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 10:01:25.871581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4934 10:01:25.878124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4935 10:01:25.881571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4936 10:01:25.884649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4937 10:01:25.884732 [ANA_INIT] flow start
4938 10:01:25.888446 [ANA_INIT] PLL >>>>>>>>
4939 10:01:25.891389 [ANA_INIT] PLL <<<<<<<<
4940 10:01:25.891472 [ANA_INIT] MIDPI >>>>>>>>
4941 10:01:25.894777 [ANA_INIT] MIDPI <<<<<<<<
4942 10:01:25.898073 [ANA_INIT] DLL >>>>>>>>
4943 10:01:25.898156 [ANA_INIT] flow end
4944 10:01:25.904619 ============ LP4 DIFF to SE enter ============
4945 10:01:25.907967 ============ LP4 DIFF to SE exit ============
4946 10:01:25.911548 [ANA_INIT] <<<<<<<<<<<<<
4947 10:01:25.915008 [Flow] Enable top DCM control >>>>>
4948 10:01:25.918231 [Flow] Enable top DCM control <<<<<
4949 10:01:25.918314 Enable DLL master slave shuffle
4950 10:01:25.924550 ==============================================================
4951 10:01:25.928263 Gating Mode config
4952 10:01:25.931211 ==============================================================
4953 10:01:25.935038 Config description:
4954 10:01:25.944510 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4955 10:01:25.951373 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4956 10:01:25.954652 SELPH_MODE 0: By rank 1: By Phase
4957 10:01:25.961657 ==============================================================
4958 10:01:25.964837 GAT_TRACK_EN = 1
4959 10:01:25.968198 RX_GATING_MODE = 2
4960 10:01:25.968281 RX_GATING_TRACK_MODE = 2
4961 10:01:25.971725 SELPH_MODE = 1
4962 10:01:25.974766 PICG_EARLY_EN = 1
4963 10:01:25.978162 VALID_LAT_VALUE = 1
4964 10:01:25.984647 ==============================================================
4965 10:01:25.988207 Enter into Gating configuration >>>>
4966 10:01:25.991342 Exit from Gating configuration <<<<
4967 10:01:25.994934 Enter into DVFS_PRE_config >>>>>
4968 10:01:26.004793 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4969 10:01:26.007841 Exit from DVFS_PRE_config <<<<<
4970 10:01:26.011030 Enter into PICG configuration >>>>
4971 10:01:26.014541 Exit from PICG configuration <<<<
4972 10:01:26.017699 [RX_INPUT] configuration >>>>>
4973 10:01:26.020952 [RX_INPUT] configuration <<<<<
4974 10:01:26.024473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4975 10:01:26.031095 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4976 10:01:26.037898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 10:01:26.044783 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 10:01:26.048143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4979 10:01:26.054512 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4980 10:01:26.058045 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4981 10:01:26.064654 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4982 10:01:26.068009 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4983 10:01:26.071489 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4984 10:01:26.074696 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4985 10:01:26.081206 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4986 10:01:26.084618 ===================================
4987 10:01:26.084764 LPDDR4 DRAM CONFIGURATION
4988 10:01:26.087784 ===================================
4989 10:01:26.091151 EX_ROW_EN[0] = 0x0
4990 10:01:26.094598 EX_ROW_EN[1] = 0x0
4991 10:01:26.094717 LP4Y_EN = 0x0
4992 10:01:26.097932 WORK_FSP = 0x0
4993 10:01:26.098052 WL = 0x3
4994 10:01:26.101202 RL = 0x3
4995 10:01:26.101323 BL = 0x2
4996 10:01:26.104642 RPST = 0x0
4997 10:01:26.104796 RD_PRE = 0x0
4998 10:01:26.107805 WR_PRE = 0x1
4999 10:01:26.107923 WR_PST = 0x0
5000 10:01:26.111300 DBI_WR = 0x0
5001 10:01:26.111425 DBI_RD = 0x0
5002 10:01:26.114761 OTF = 0x1
5003 10:01:26.117829 ===================================
5004 10:01:26.121338 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5005 10:01:26.124945 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5006 10:01:26.131167 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5007 10:01:26.134557 ===================================
5008 10:01:26.134678 LPDDR4 DRAM CONFIGURATION
5009 10:01:26.138231 ===================================
5010 10:01:26.141259 EX_ROW_EN[0] = 0x10
5011 10:01:26.141380 EX_ROW_EN[1] = 0x0
5012 10:01:26.144681 LP4Y_EN = 0x0
5013 10:01:26.147760 WORK_FSP = 0x0
5014 10:01:26.147883 WL = 0x3
5015 10:01:26.151304 RL = 0x3
5016 10:01:26.151422 BL = 0x2
5017 10:01:26.154439 RPST = 0x0
5018 10:01:26.154560 RD_PRE = 0x0
5019 10:01:26.157896 WR_PRE = 0x1
5020 10:01:26.158017 WR_PST = 0x0
5021 10:01:26.161392 DBI_WR = 0x0
5022 10:01:26.161515 DBI_RD = 0x0
5023 10:01:26.164805 OTF = 0x1
5024 10:01:26.168132 ===================================
5025 10:01:26.171375 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5026 10:01:26.176733 nWR fixed to 30
5027 10:01:26.180297 [ModeRegInit_LP4] CH0 RK0
5028 10:01:26.180423 [ModeRegInit_LP4] CH0 RK1
5029 10:01:26.183335 [ModeRegInit_LP4] CH1 RK0
5030 10:01:26.186839 [ModeRegInit_LP4] CH1 RK1
5031 10:01:26.186960 match AC timing 9
5032 10:01:26.193461 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5033 10:01:26.196686 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5034 10:01:26.199771 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5035 10:01:26.206699 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5036 10:01:26.209886 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5037 10:01:26.209998 ==
5038 10:01:26.213403 Dram Type= 6, Freq= 0, CH_0, rank 0
5039 10:01:26.216458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5040 10:01:26.216581 ==
5041 10:01:26.223273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5042 10:01:26.229629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5043 10:01:26.233302 [CA 0] Center 38 (7~69) winsize 63
5044 10:01:26.236345 [CA 1] Center 38 (8~69) winsize 62
5045 10:01:26.239780 [CA 2] Center 35 (5~66) winsize 62
5046 10:01:26.243328 [CA 3] Center 34 (4~65) winsize 62
5047 10:01:26.246344 [CA 4] Center 34 (4~64) winsize 61
5048 10:01:26.249795 [CA 5] Center 33 (3~64) winsize 62
5049 10:01:26.249913
5050 10:01:26.253255 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5051 10:01:26.253373
5052 10:01:26.256354 [CATrainingPosCal] consider 1 rank data
5053 10:01:26.259590 u2DelayCellTimex100 = 270/100 ps
5054 10:01:26.262905 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5055 10:01:26.266463 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5056 10:01:26.269663 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5057 10:01:26.273281 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5058 10:01:26.276346 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5059 10:01:26.279734 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5060 10:01:26.283229
5061 10:01:26.286337 CA PerBit enable=1, Macro0, CA PI delay=33
5062 10:01:26.286456
5063 10:01:26.289773 [CBTSetCACLKResult] CA Dly = 33
5064 10:01:26.289893 CS Dly: 7 (0~38)
5065 10:01:26.290005 ==
5066 10:01:26.293155 Dram Type= 6, Freq= 0, CH_0, rank 1
5067 10:01:26.296676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5068 10:01:26.296801 ==
5069 10:01:26.303079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5070 10:01:26.309831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5071 10:01:26.313439 [CA 0] Center 38 (7~69) winsize 63
5072 10:01:26.316565 [CA 1] Center 38 (8~69) winsize 62
5073 10:01:26.319889 [CA 2] Center 36 (6~66) winsize 61
5074 10:01:26.323303 [CA 3] Center 35 (5~66) winsize 62
5075 10:01:26.326513 [CA 4] Center 34 (4~65) winsize 62
5076 10:01:26.330054 [CA 5] Center 34 (4~65) winsize 62
5077 10:01:26.330172
5078 10:01:26.333008 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5079 10:01:26.333099
5080 10:01:26.336286 [CATrainingPosCal] consider 2 rank data
5081 10:01:26.339495 u2DelayCellTimex100 = 270/100 ps
5082 10:01:26.343111 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5083 10:01:26.346112 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 10:01:26.349595 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5085 10:01:26.353114 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5086 10:01:26.356317 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5087 10:01:26.362822 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5088 10:01:26.362895
5089 10:01:26.365935 CA PerBit enable=1, Macro0, CA PI delay=34
5090 10:01:26.366059
5091 10:01:26.369350 [CBTSetCACLKResult] CA Dly = 34
5092 10:01:26.369488 CS Dly: 7 (0~39)
5093 10:01:26.369598
5094 10:01:26.372918 ----->DramcWriteLeveling(PI) begin...
5095 10:01:26.373038 ==
5096 10:01:26.376121 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 10:01:26.382847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 10:01:26.382975 ==
5099 10:01:26.386147 Write leveling (Byte 0): 31 => 31
5100 10:01:26.386276 Write leveling (Byte 1): 29 => 29
5101 10:01:26.389198 DramcWriteLeveling(PI) end<-----
5102 10:01:26.389283
5103 10:01:26.389350 ==
5104 10:01:26.392502 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 10:01:26.399429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 10:01:26.399505 ==
5107 10:01:26.402787 [Gating] SW mode calibration
5108 10:01:26.409231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5109 10:01:26.412641 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5110 10:01:26.419217 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5111 10:01:26.422435 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 10:01:26.426285 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 10:01:26.432451 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 10:01:26.435712 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 10:01:26.438982 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 10:01:26.445587 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5117 10:01:26.449084 0 14 28 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
5118 10:01:26.452090 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5119 10:01:26.459057 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 10:01:26.462876 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 10:01:26.465570 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 10:01:26.472076 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 10:01:26.475760 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 10:01:26.478950 0 15 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5125 10:01:26.482178 0 15 28 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
5126 10:01:26.489132 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 10:01:26.492349 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 10:01:26.495839 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 10:01:26.502203 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 10:01:26.505486 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 10:01:26.509202 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 10:01:26.515496 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5133 10:01:26.518768 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5134 10:01:26.521992 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5135 10:01:26.528756 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 10:01:26.531902 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 10:01:26.535384 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 10:01:26.541778 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 10:01:26.545444 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 10:01:26.548466 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 10:01:26.554974 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 10:01:26.558475 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 10:01:26.562051 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 10:01:26.568192 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 10:01:26.571597 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 10:01:26.575124 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 10:01:26.581530 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 10:01:26.585059 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 10:01:26.588289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5150 10:01:26.591656 Total UI for P1: 0, mck2ui 16
5151 10:01:26.594841 best dqsien dly found for B0: ( 1, 2, 26)
5152 10:01:26.601595 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5153 10:01:26.604944 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 10:01:26.608211 Total UI for P1: 0, mck2ui 16
5155 10:01:26.611355 best dqsien dly found for B1: ( 1, 2, 30)
5156 10:01:26.614959 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5157 10:01:26.617950 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5158 10:01:26.618033
5159 10:01:26.621436 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5160 10:01:26.625034 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5161 10:01:26.628186 [Gating] SW calibration Done
5162 10:01:26.628269 ==
5163 10:01:26.631503 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 10:01:26.634600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 10:01:26.634684 ==
5166 10:01:26.638069 RX Vref Scan: 0
5167 10:01:26.638152
5168 10:01:26.641237 RX Vref 0 -> 0, step: 1
5169 10:01:26.641320
5170 10:01:26.641385 RX Delay -80 -> 252, step: 8
5171 10:01:26.647979 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5172 10:01:26.651446 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5173 10:01:26.654948 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5174 10:01:26.658153 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5175 10:01:26.661308 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5176 10:01:26.668025 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5177 10:01:26.671174 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5178 10:01:26.674798 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5179 10:01:26.677923 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5180 10:01:26.681372 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5181 10:01:26.684885 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5182 10:01:26.691504 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5183 10:01:26.694873 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5184 10:01:26.698168 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5185 10:01:26.701604 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5186 10:01:26.704784 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5187 10:01:26.704881 ==
5188 10:01:26.708281 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 10:01:26.714499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 10:01:26.714583 ==
5191 10:01:26.714648 DQS Delay:
5192 10:01:26.714709 DQS0 = 0, DQS1 = 0
5193 10:01:26.718032 DQM Delay:
5194 10:01:26.718114 DQM0 = 105, DQM1 = 90
5195 10:01:26.721420 DQ Delay:
5196 10:01:26.724670 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5197 10:01:26.727947 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5198 10:01:26.731288 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5199 10:01:26.734540 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5200 10:01:26.734624
5201 10:01:26.734688
5202 10:01:26.734747 ==
5203 10:01:26.737774 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 10:01:26.741350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 10:01:26.741434 ==
5206 10:01:26.741499
5207 10:01:26.741558
5208 10:01:26.744421 TX Vref Scan disable
5209 10:01:26.744504 == TX Byte 0 ==
5210 10:01:26.751124 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5211 10:01:26.754654 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5212 10:01:26.757929 == TX Byte 1 ==
5213 10:01:26.761252 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5214 10:01:26.764709 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5215 10:01:26.764868 ==
5216 10:01:26.767738 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 10:01:26.771250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 10:01:26.771383 ==
5219 10:01:26.771492
5220 10:01:26.774442
5221 10:01:26.774562 TX Vref Scan disable
5222 10:01:26.778057 == TX Byte 0 ==
5223 10:01:26.781164 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5224 10:01:26.784746 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5225 10:01:26.787768 == TX Byte 1 ==
5226 10:01:26.791486 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5227 10:01:26.794680 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5228 10:01:26.794803
5229 10:01:26.797849 [DATLAT]
5230 10:01:26.797973 Freq=933, CH0 RK0
5231 10:01:26.798088
5232 10:01:26.801050 DATLAT Default: 0xd
5233 10:01:26.801171 0, 0xFFFF, sum = 0
5234 10:01:26.804530 1, 0xFFFF, sum = 0
5235 10:01:26.804655 2, 0xFFFF, sum = 0
5236 10:01:26.807994 3, 0xFFFF, sum = 0
5237 10:01:26.808118 4, 0xFFFF, sum = 0
5238 10:01:26.811221 5, 0xFFFF, sum = 0
5239 10:01:26.811345 6, 0xFFFF, sum = 0
5240 10:01:26.814587 7, 0xFFFF, sum = 0
5241 10:01:26.814726 8, 0xFFFF, sum = 0
5242 10:01:26.817954 9, 0xFFFF, sum = 0
5243 10:01:26.818083 10, 0x0, sum = 1
5244 10:01:26.821501 11, 0x0, sum = 2
5245 10:01:26.821621 12, 0x0, sum = 3
5246 10:01:26.824443 13, 0x0, sum = 4
5247 10:01:26.824595 best_step = 11
5248 10:01:26.824710
5249 10:01:26.824854 ==
5250 10:01:26.827918 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 10:01:26.834481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 10:01:26.834588 ==
5253 10:01:26.834682 RX Vref Scan: 1
5254 10:01:26.834771
5255 10:01:26.837683 RX Vref 0 -> 0, step: 1
5256 10:01:26.837805
5257 10:01:26.841324 RX Delay -53 -> 252, step: 4
5258 10:01:26.841407
5259 10:01:26.844461 Set Vref, RX VrefLevel [Byte0]: 57
5260 10:01:26.848064 [Byte1]: 48
5261 10:01:26.848147
5262 10:01:26.851518 Final RX Vref Byte 0 = 57 to rank0
5263 10:01:26.854630 Final RX Vref Byte 1 = 48 to rank0
5264 10:01:26.857656 Final RX Vref Byte 0 = 57 to rank1
5265 10:01:26.861147 Final RX Vref Byte 1 = 48 to rank1==
5266 10:01:26.864342 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 10:01:26.867906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 10:01:26.867989 ==
5269 10:01:26.870998 DQS Delay:
5270 10:01:26.871080 DQS0 = 0, DQS1 = 0
5271 10:01:26.871174 DQM Delay:
5272 10:01:26.874149 DQM0 = 107, DQM1 = 92
5273 10:01:26.874231 DQ Delay:
5274 10:01:26.877826 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5275 10:01:26.880916 DQ4 =106, DQ5 =98, DQ6 =118, DQ7 =116
5276 10:01:26.884576 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5277 10:01:26.887584 DQ12 =94, DQ13 =94, DQ14 =106, DQ15 =96
5278 10:01:26.891129
5279 10:01:26.891212
5280 10:01:26.897513 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5281 10:01:26.901068 CH0 RK0: MR19=505, MR18=2420
5282 10:01:26.907675 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5283 10:01:26.907831
5284 10:01:26.910877 ----->DramcWriteLeveling(PI) begin...
5285 10:01:26.910962 ==
5286 10:01:26.914052 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 10:01:26.917910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 10:01:26.917995 ==
5289 10:01:26.920950 Write leveling (Byte 0): 34 => 34
5290 10:01:26.924175 Write leveling (Byte 1): 30 => 30
5291 10:01:26.927703 DramcWriteLeveling(PI) end<-----
5292 10:01:26.927788
5293 10:01:26.927885 ==
5294 10:01:26.930869 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 10:01:26.934142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 10:01:26.934224 ==
5297 10:01:26.937602 [Gating] SW mode calibration
5298 10:01:26.944420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5299 10:01:26.950911 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5300 10:01:26.954021 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 10:01:26.957520 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 10:01:26.964112 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 10:01:26.967560 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 10:01:26.970714 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 10:01:26.977415 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 10:01:26.980710 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
5307 10:01:26.983765 0 14 28 | B1->B0 | 2e2e 2626 | 0 0 | (0 1) (0 0)
5308 10:01:26.990913 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 10:01:26.994274 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 10:01:26.997337 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 10:01:27.004279 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 10:01:27.007680 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 10:01:27.010928 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 10:01:27.017463 0 15 24 | B1->B0 | 2b2b 3130 | 0 1 | (1 1) (0 0)
5315 10:01:27.020737 0 15 28 | B1->B0 | 4040 4242 | 0 1 | (1 1) (0 0)
5316 10:01:27.024017 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 10:01:27.030747 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 10:01:27.034189 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 10:01:27.037591 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 10:01:27.040769 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 10:01:27.047422 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 10:01:27.050443 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 10:01:27.054009 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5324 10:01:27.060627 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5325 10:01:27.063733 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 10:01:27.067168 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 10:01:27.073634 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 10:01:27.076942 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 10:01:27.080596 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 10:01:27.087001 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 10:01:27.090397 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 10:01:27.093377 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 10:01:27.100122 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 10:01:27.103613 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 10:01:27.106637 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 10:01:27.113386 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 10:01:27.116792 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 10:01:27.119899 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 10:01:27.126412 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5340 10:01:27.130041 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 10:01:27.133342 Total UI for P1: 0, mck2ui 16
5342 10:01:27.136711 best dqsien dly found for B0: ( 1, 2, 28)
5343 10:01:27.139716 Total UI for P1: 0, mck2ui 16
5344 10:01:27.143538 best dqsien dly found for B1: ( 1, 2, 28)
5345 10:01:27.146546 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5346 10:01:27.150090 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5347 10:01:27.150165
5348 10:01:27.153380 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5349 10:01:27.156395 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5350 10:01:27.160087 [Gating] SW calibration Done
5351 10:01:27.160217 ==
5352 10:01:27.163164 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 10:01:27.166859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 10:01:27.169766 ==
5355 10:01:27.169889 RX Vref Scan: 0
5356 10:01:27.170002
5357 10:01:27.173013 RX Vref 0 -> 0, step: 1
5358 10:01:27.173100
5359 10:01:27.176373 RX Delay -80 -> 252, step: 8
5360 10:01:27.179634 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5361 10:01:27.183318 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5362 10:01:27.186319 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5363 10:01:27.189536 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5364 10:01:27.196024 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5365 10:01:27.199500 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5366 10:01:27.203023 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5367 10:01:27.206387 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5368 10:01:27.209435 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5369 10:01:27.212886 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5370 10:01:27.219763 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5371 10:01:27.222719 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5372 10:01:27.226250 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5373 10:01:27.229195 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5374 10:01:27.232636 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5375 10:01:27.239329 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5376 10:01:27.239479 ==
5377 10:01:27.242806 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 10:01:27.246197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 10:01:27.246322 ==
5380 10:01:27.246434 DQS Delay:
5381 10:01:27.249189 DQS0 = 0, DQS1 = 0
5382 10:01:27.249311 DQM Delay:
5383 10:01:27.252897 DQM0 = 105, DQM1 = 91
5384 10:01:27.253018 DQ Delay:
5385 10:01:27.256032 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5386 10:01:27.259162 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =111
5387 10:01:27.262707 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5388 10:01:27.266238 DQ12 =95, DQ13 =95, DQ14 =103, DQ15 =95
5389 10:01:27.266359
5390 10:01:27.266471
5391 10:01:27.266579 ==
5392 10:01:27.269443 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 10:01:27.272858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 10:01:27.272980 ==
5395 10:01:27.276403
5396 10:01:27.276519
5397 10:01:27.276632 TX Vref Scan disable
5398 10:01:27.279689 == TX Byte 0 ==
5399 10:01:27.282756 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5400 10:01:27.285972 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5401 10:01:27.289603 == TX Byte 1 ==
5402 10:01:27.292590 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5403 10:01:27.296175 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5404 10:01:27.296300 ==
5405 10:01:27.299372 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 10:01:27.305964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 10:01:27.306088 ==
5408 10:01:27.306205
5409 10:01:27.306313
5410 10:01:27.309132 TX Vref Scan disable
5411 10:01:27.309253 == TX Byte 0 ==
5412 10:01:27.315846 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5413 10:01:27.319214 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5414 10:01:27.319332 == TX Byte 1 ==
5415 10:01:27.325572 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5416 10:01:27.328915 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5417 10:01:27.329034
5418 10:01:27.329144 [DATLAT]
5419 10:01:27.332864 Freq=933, CH0 RK1
5420 10:01:27.332987
5421 10:01:27.333101 DATLAT Default: 0xb
5422 10:01:27.335663 0, 0xFFFF, sum = 0
5423 10:01:27.335785 1, 0xFFFF, sum = 0
5424 10:01:27.339242 2, 0xFFFF, sum = 0
5425 10:01:27.339370 3, 0xFFFF, sum = 0
5426 10:01:27.342259 4, 0xFFFF, sum = 0
5427 10:01:27.342384 5, 0xFFFF, sum = 0
5428 10:01:27.345662 6, 0xFFFF, sum = 0
5429 10:01:27.345786 7, 0xFFFF, sum = 0
5430 10:01:27.349243 8, 0xFFFF, sum = 0
5431 10:01:27.349363 9, 0xFFFF, sum = 0
5432 10:01:27.352324 10, 0x0, sum = 1
5433 10:01:27.352439 11, 0x0, sum = 2
5434 10:01:27.355708 12, 0x0, sum = 3
5435 10:01:27.355828 13, 0x0, sum = 4
5436 10:01:27.358806 best_step = 11
5437 10:01:27.358925
5438 10:01:27.359035 ==
5439 10:01:27.362387 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 10:01:27.365900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 10:01:27.366019 ==
5442 10:01:27.368900 RX Vref Scan: 0
5443 10:01:27.369023
5444 10:01:27.369134 RX Vref 0 -> 0, step: 1
5445 10:01:27.369242
5446 10:01:27.372271 RX Delay -53 -> 252, step: 4
5447 10:01:27.379537 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5448 10:01:27.382874 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5449 10:01:27.385925 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5450 10:01:27.389432 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5451 10:01:27.392552 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5452 10:01:27.399395 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5453 10:01:27.402767 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5454 10:01:27.406002 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5455 10:01:27.409390 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5456 10:01:27.412527 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5457 10:01:27.416317 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5458 10:01:27.422549 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5459 10:01:27.425986 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5460 10:01:27.429509 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5461 10:01:27.432516 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5462 10:01:27.436138 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5463 10:01:27.439528 ==
5464 10:01:27.442337 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 10:01:27.445640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 10:01:27.445763 ==
5467 10:01:27.445875 DQS Delay:
5468 10:01:27.449019 DQS0 = 0, DQS1 = 0
5469 10:01:27.449139 DQM Delay:
5470 10:01:27.452427 DQM0 = 104, DQM1 = 92
5471 10:01:27.452559 DQ Delay:
5472 10:01:27.455920 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5473 10:01:27.459345 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5474 10:01:27.462492 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =90
5475 10:01:27.466044 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =98
5476 10:01:27.466165
5477 10:01:27.466274
5478 10:01:27.472327 [DQSOSCAuto] RK1, (LSB)MR18= 0x2708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5479 10:01:27.475729 CH0 RK1: MR19=505, MR18=2708
5480 10:01:27.482498 CH0_RK1: MR19=0x505, MR18=0x2708, DQSOSC=409, MR23=63, INC=64, DEC=43
5481 10:01:27.485740 [RxdqsGatingPostProcess] freq 933
5482 10:01:27.492464 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5483 10:01:27.495878 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 10:01:27.498878 best DQS1 dly(2T, 0.5T) = (0, 10)
5485 10:01:27.502362 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 10:01:27.502482 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5487 10:01:27.505474 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 10:01:27.509068 best DQS1 dly(2T, 0.5T) = (0, 10)
5489 10:01:27.512254 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 10:01:27.515518 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5491 10:01:27.519176 Pre-setting of DQS Precalculation
5492 10:01:27.525958 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5493 10:01:27.526080 ==
5494 10:01:27.528997 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 10:01:27.532173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 10:01:27.532295 ==
5497 10:01:27.539017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 10:01:27.542228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5499 10:01:27.546409 [CA 0] Center 37 (7~68) winsize 62
5500 10:01:27.550055 [CA 1] Center 37 (7~68) winsize 62
5501 10:01:27.553333 [CA 2] Center 36 (6~66) winsize 61
5502 10:01:27.556580 [CA 3] Center 34 (4~65) winsize 62
5503 10:01:27.560096 [CA 4] Center 35 (5~65) winsize 61
5504 10:01:27.563144 [CA 5] Center 34 (4~65) winsize 62
5505 10:01:27.563266
5506 10:01:27.566532 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5507 10:01:27.566672
5508 10:01:27.569966 [CATrainingPosCal] consider 1 rank data
5509 10:01:27.573381 u2DelayCellTimex100 = 270/100 ps
5510 10:01:27.576597 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5511 10:01:27.579653 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5512 10:01:27.586675 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5513 10:01:27.590006 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5514 10:01:27.593179 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5515 10:01:27.596307 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5516 10:01:27.596427
5517 10:01:27.599911 CA PerBit enable=1, Macro0, CA PI delay=34
5518 10:01:27.600030
5519 10:01:27.603022 [CBTSetCACLKResult] CA Dly = 34
5520 10:01:27.603143 CS Dly: 6 (0~37)
5521 10:01:27.606195 ==
5522 10:01:27.606316 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 10:01:27.612871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 10:01:27.612992 ==
5525 10:01:27.616232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 10:01:27.622853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5527 10:01:27.626769 [CA 0] Center 37 (7~68) winsize 62
5528 10:01:27.629693 [CA 1] Center 38 (7~69) winsize 63
5529 10:01:27.633067 [CA 2] Center 36 (7~66) winsize 60
5530 10:01:27.636596 [CA 3] Center 35 (6~65) winsize 60
5531 10:01:27.639691 [CA 4] Center 35 (6~65) winsize 60
5532 10:01:27.643116 [CA 5] Center 34 (5~64) winsize 60
5533 10:01:27.643235
5534 10:01:27.646545 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5535 10:01:27.646673
5536 10:01:27.649733 [CATrainingPosCal] consider 2 rank data
5537 10:01:27.653173 u2DelayCellTimex100 = 270/100 ps
5538 10:01:27.656518 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5539 10:01:27.659811 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5540 10:01:27.666609 CA2 delay=36 (7~66),Diff = 2 PI (12 cell)
5541 10:01:27.669786 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5542 10:01:27.673403 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5543 10:01:27.676449 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5544 10:01:27.676567
5545 10:01:27.679566 CA PerBit enable=1, Macro0, CA PI delay=34
5546 10:01:27.679680
5547 10:01:27.683077 [CBTSetCACLKResult] CA Dly = 34
5548 10:01:27.683194 CS Dly: 7 (0~39)
5549 10:01:27.683304
5550 10:01:27.689910 ----->DramcWriteLeveling(PI) begin...
5551 10:01:27.690030 ==
5552 10:01:27.693637 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 10:01:27.696255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 10:01:27.696372 ==
5555 10:01:27.699751 Write leveling (Byte 0): 26 => 26
5556 10:01:27.703322 Write leveling (Byte 1): 28 => 28
5557 10:01:27.706431 DramcWriteLeveling(PI) end<-----
5558 10:01:27.706557
5559 10:01:27.706662 ==
5560 10:01:27.709952 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 10:01:27.713192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 10:01:27.713312 ==
5563 10:01:27.716468 [Gating] SW mode calibration
5564 10:01:27.723088 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5565 10:01:27.729929 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5566 10:01:27.733095 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 10:01:27.736460 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 10:01:27.739582 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 10:01:27.746170 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 10:01:27.749687 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 10:01:27.753293 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 10:01:27.759517 0 14 24 | B1->B0 | 3232 3131 | 0 1 | (0 0) (1 0)
5573 10:01:27.763224 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5574 10:01:27.766262 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 10:01:27.773213 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 10:01:27.776302 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 10:01:27.779357 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 10:01:27.786221 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 10:01:27.789707 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 10:01:27.793055 0 15 24 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0)
5581 10:01:27.799698 0 15 28 | B1->B0 | 3f3f 4343 | 0 0 | (0 0) (0 0)
5582 10:01:27.803169 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 10:01:27.806124 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 10:01:27.813375 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 10:01:27.816276 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 10:01:27.819485 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 10:01:27.825971 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5588 10:01:27.829467 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5589 10:01:27.833056 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 10:01:27.839560 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 10:01:27.842992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 10:01:27.846086 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 10:01:27.852681 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 10:01:27.855800 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 10:01:27.859189 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 10:01:27.865898 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 10:01:27.869314 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 10:01:27.872704 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 10:01:27.879207 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 10:01:27.882405 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 10:01:27.885781 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 10:01:27.889418 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 10:01:27.896006 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 10:01:27.900072 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5605 10:01:27.902655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 10:01:27.905684 Total UI for P1: 0, mck2ui 16
5607 10:01:27.909374 best dqsien dly found for B0: ( 1, 2, 24)
5608 10:01:27.912848 Total UI for P1: 0, mck2ui 16
5609 10:01:27.916056 best dqsien dly found for B1: ( 1, 2, 24)
5610 10:01:27.919012 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5611 10:01:27.922636 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5612 10:01:27.922756
5613 10:01:27.929266 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5614 10:01:27.932315 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5615 10:01:27.935921 [Gating] SW calibration Done
5616 10:01:27.936042 ==
5617 10:01:27.939073 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 10:01:27.942447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 10:01:27.942566 ==
5620 10:01:27.942678 RX Vref Scan: 0
5621 10:01:27.942785
5622 10:01:27.945900 RX Vref 0 -> 0, step: 1
5623 10:01:27.946018
5624 10:01:27.949123 RX Delay -80 -> 252, step: 8
5625 10:01:27.952651 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5626 10:01:27.955659 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5627 10:01:27.959130 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5628 10:01:27.965798 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5629 10:01:27.968987 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5630 10:01:27.972264 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5631 10:01:27.975513 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5632 10:01:27.979056 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5633 10:01:27.982467 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5634 10:01:27.988951 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5635 10:01:27.992203 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5636 10:01:27.995604 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5637 10:01:27.999220 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5638 10:01:28.002408 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5639 10:01:28.008898 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5640 10:01:28.012326 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5641 10:01:28.012445 ==
5642 10:01:28.015619 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 10:01:28.019105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 10:01:28.019224 ==
5645 10:01:28.019335 DQS Delay:
5646 10:01:28.022201 DQS0 = 0, DQS1 = 0
5647 10:01:28.022320 DQM Delay:
5648 10:01:28.025377 DQM0 = 102, DQM1 = 95
5649 10:01:28.025496 DQ Delay:
5650 10:01:28.029044 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5651 10:01:28.032243 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5652 10:01:28.035391 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5653 10:01:28.038872 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5654 10:01:28.038991
5655 10:01:28.039097
5656 10:01:28.039202 ==
5657 10:01:28.042000 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 10:01:28.048475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 10:01:28.048600 ==
5660 10:01:28.048711
5661 10:01:28.048856
5662 10:01:28.048966 TX Vref Scan disable
5663 10:01:28.052014 == TX Byte 0 ==
5664 10:01:28.055340 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5665 10:01:28.062357 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5666 10:01:28.062479 == TX Byte 1 ==
5667 10:01:28.065450 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5668 10:01:28.072152 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5669 10:01:28.072273 ==
5670 10:01:28.075632 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 10:01:28.078710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 10:01:28.078826 ==
5673 10:01:28.078937
5674 10:01:28.079042
5675 10:01:28.081910 TX Vref Scan disable
5676 10:01:28.082027 == TX Byte 0 ==
5677 10:01:28.088875 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5678 10:01:28.091892 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5679 10:01:28.092012 == TX Byte 1 ==
5680 10:01:28.098698 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5681 10:01:28.101879 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5682 10:01:28.102000
5683 10:01:28.102118 [DATLAT]
5684 10:01:28.105349 Freq=933, CH1 RK0
5685 10:01:28.105469
5686 10:01:28.105586 DATLAT Default: 0xd
5687 10:01:28.108693 0, 0xFFFF, sum = 0
5688 10:01:28.108863 1, 0xFFFF, sum = 0
5689 10:01:28.112128 2, 0xFFFF, sum = 0
5690 10:01:28.112252 3, 0xFFFF, sum = 0
5691 10:01:28.115837 4, 0xFFFF, sum = 0
5692 10:01:28.115961 5, 0xFFFF, sum = 0
5693 10:01:28.118699 6, 0xFFFF, sum = 0
5694 10:01:28.118819 7, 0xFFFF, sum = 0
5695 10:01:28.121962 8, 0xFFFF, sum = 0
5696 10:01:28.125746 9, 0xFFFF, sum = 0
5697 10:01:28.125873 10, 0x0, sum = 1
5698 10:01:28.125995 11, 0x0, sum = 2
5699 10:01:28.129031 12, 0x0, sum = 3
5700 10:01:28.129156 13, 0x0, sum = 4
5701 10:01:28.132153 best_step = 11
5702 10:01:28.132276
5703 10:01:28.132387 ==
5704 10:01:28.135341 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 10:01:28.138927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 10:01:28.139050 ==
5707 10:01:28.142226 RX Vref Scan: 1
5708 10:01:28.142309
5709 10:01:28.142374 RX Vref 0 -> 0, step: 1
5710 10:01:28.142434
5711 10:01:28.145349 RX Delay -53 -> 252, step: 4
5712 10:01:28.145421
5713 10:01:28.148948 Set Vref, RX VrefLevel [Byte0]: 51
5714 10:01:28.151965 [Byte1]: 58
5715 10:01:28.155974
5716 10:01:28.156056 Final RX Vref Byte 0 = 51 to rank0
5717 10:01:28.159512 Final RX Vref Byte 1 = 58 to rank0
5718 10:01:28.162773 Final RX Vref Byte 0 = 51 to rank1
5719 10:01:28.165836 Final RX Vref Byte 1 = 58 to rank1==
5720 10:01:28.169198 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 10:01:28.175953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 10:01:28.176059 ==
5723 10:01:28.176153 DQS Delay:
5724 10:01:28.176243 DQS0 = 0, DQS1 = 0
5725 10:01:28.179317 DQM Delay:
5726 10:01:28.179413 DQM0 = 104, DQM1 = 97
5727 10:01:28.182929 DQ Delay:
5728 10:01:28.186238 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5729 10:01:28.189357 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5730 10:01:28.193020 DQ8 =90, DQ9 =84, DQ10 =100, DQ11 =92
5731 10:01:28.196038 DQ12 =108, DQ13 =102, DQ14 =102, DQ15 =102
5732 10:01:28.196122
5733 10:01:28.196185
5734 10:01:28.202549 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5735 10:01:28.205810 CH1 RK0: MR19=505, MR18=1D35
5736 10:01:28.212449 CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44
5737 10:01:28.212547
5738 10:01:28.215662 ----->DramcWriteLeveling(PI) begin...
5739 10:01:28.215747 ==
5740 10:01:28.219030 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 10:01:28.222551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 10:01:28.222635 ==
5743 10:01:28.225820 Write leveling (Byte 0): 29 => 29
5744 10:01:28.229169 Write leveling (Byte 1): 28 => 28
5745 10:01:28.232346 DramcWriteLeveling(PI) end<-----
5746 10:01:28.232431
5747 10:01:28.232494 ==
5748 10:01:28.235720 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 10:01:28.242517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 10:01:28.242608 ==
5751 10:01:28.242674 [Gating] SW mode calibration
5752 10:01:28.252348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5753 10:01:28.255809 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5754 10:01:28.259291 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5755 10:01:28.265924 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 10:01:28.269084 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 10:01:28.272572 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 10:01:28.278986 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 10:01:28.282503 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 10:01:28.285486 0 14 24 | B1->B0 | 2f2f 3333 | 1 1 | (1 1) (1 0)
5761 10:01:28.292173 0 14 28 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (1 0)
5762 10:01:28.295320 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 10:01:28.298701 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 10:01:28.305512 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 10:01:28.308885 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 10:01:28.312247 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 10:01:28.318650 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 10:01:28.322514 0 15 24 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
5769 10:01:28.325651 0 15 28 | B1->B0 | 4040 3d3d | 0 0 | (1 1) (0 0)
5770 10:01:28.332088 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5771 10:01:28.335585 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 10:01:28.338866 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 10:01:28.345558 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 10:01:28.348865 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 10:01:28.352124 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 10:01:28.355678 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5777 10:01:28.362126 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 10:01:28.365355 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 10:01:28.368843 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 10:01:28.375679 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 10:01:28.378744 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 10:01:28.382328 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 10:01:28.388858 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 10:01:28.392209 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 10:01:28.395473 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 10:01:28.402310 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 10:01:28.405584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 10:01:28.409058 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 10:01:28.415221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 10:01:28.418839 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 10:01:28.421843 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 10:01:28.428872 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5793 10:01:28.432041 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5794 10:01:28.435208 Total UI for P1: 0, mck2ui 16
5795 10:01:28.438971 best dqsien dly found for B1: ( 1, 2, 24)
5796 10:01:28.441993 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 10:01:28.445333 Total UI for P1: 0, mck2ui 16
5798 10:01:28.448871 best dqsien dly found for B0: ( 1, 2, 26)
5799 10:01:28.452137 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5800 10:01:28.455577 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5801 10:01:28.455659
5802 10:01:28.458660 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5803 10:01:28.465452 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5804 10:01:28.465535 [Gating] SW calibration Done
5805 10:01:28.465617 ==
5806 10:01:28.468791 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 10:01:28.475311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 10:01:28.475395 ==
5809 10:01:28.475460 RX Vref Scan: 0
5810 10:01:28.475521
5811 10:01:28.478715 RX Vref 0 -> 0, step: 1
5812 10:01:28.478798
5813 10:01:28.481983 RX Delay -80 -> 252, step: 8
5814 10:01:28.485283 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5815 10:01:28.488601 iDelay=200, Bit 1, Center 103 (24 ~ 183) 160
5816 10:01:28.492106 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5817 10:01:28.498494 iDelay=200, Bit 3, Center 107 (24 ~ 191) 168
5818 10:01:28.501754 iDelay=200, Bit 4, Center 107 (24 ~ 191) 168
5819 10:01:28.505286 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5820 10:01:28.508689 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5821 10:01:28.512139 iDelay=200, Bit 7, Center 107 (24 ~ 191) 168
5822 10:01:28.515274 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5823 10:01:28.521779 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5824 10:01:28.525606 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5825 10:01:28.528737 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5826 10:01:28.532056 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5827 10:01:28.535496 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5828 10:01:28.541954 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5829 10:01:28.545236 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5830 10:01:28.545321 ==
5831 10:01:28.548599 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 10:01:28.551573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 10:01:28.551658 ==
5834 10:01:28.551741 DQS Delay:
5835 10:01:28.554872 DQS0 = 0, DQS1 = 0
5836 10:01:28.554959 DQM Delay:
5837 10:01:28.558479 DQM0 = 105, DQM1 = 94
5838 10:01:28.558562 DQ Delay:
5839 10:01:28.561602 DQ0 =107, DQ1 =103, DQ2 =87, DQ3 =107
5840 10:01:28.564924 DQ4 =107, DQ5 =111, DQ6 =111, DQ7 =107
5841 10:01:28.568341 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5842 10:01:28.571688 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5843 10:01:28.571773
5844 10:01:28.571856
5845 10:01:28.575040 ==
5846 10:01:28.578173 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 10:01:28.581685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 10:01:28.581784 ==
5849 10:01:28.581868
5850 10:01:28.581946
5851 10:01:28.584865 TX Vref Scan disable
5852 10:01:28.584974 == TX Byte 0 ==
5853 10:01:28.587997 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5854 10:01:28.595029 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5855 10:01:28.595113 == TX Byte 1 ==
5856 10:01:28.598305 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 10:01:28.604893 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 10:01:28.604976 ==
5859 10:01:28.608608 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 10:01:28.611384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 10:01:28.611468 ==
5862 10:01:28.611534
5863 10:01:28.611594
5864 10:01:28.614691 TX Vref Scan disable
5865 10:01:28.618153 == TX Byte 0 ==
5866 10:01:28.621326 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5867 10:01:28.624741 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5868 10:01:28.628332 == TX Byte 1 ==
5869 10:01:28.631472 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 10:01:28.634810 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 10:01:28.634907
5872 10:01:28.634986 [DATLAT]
5873 10:01:28.638251 Freq=933, CH1 RK1
5874 10:01:28.638334
5875 10:01:28.641629 DATLAT Default: 0xb
5876 10:01:28.641712 0, 0xFFFF, sum = 0
5877 10:01:28.644738 1, 0xFFFF, sum = 0
5878 10:01:28.644843 2, 0xFFFF, sum = 0
5879 10:01:28.648236 3, 0xFFFF, sum = 0
5880 10:01:28.648334 4, 0xFFFF, sum = 0
5881 10:01:28.651573 5, 0xFFFF, sum = 0
5882 10:01:28.651656 6, 0xFFFF, sum = 0
5883 10:01:28.655070 7, 0xFFFF, sum = 0
5884 10:01:28.655154 8, 0xFFFF, sum = 0
5885 10:01:28.658653 9, 0xFFFF, sum = 0
5886 10:01:28.658737 10, 0x0, sum = 1
5887 10:01:28.661614 11, 0x0, sum = 2
5888 10:01:28.661739 12, 0x0, sum = 3
5889 10:01:28.665056 13, 0x0, sum = 4
5890 10:01:28.665140 best_step = 11
5891 10:01:28.665204
5892 10:01:28.665264 ==
5893 10:01:28.668297 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 10:01:28.671521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 10:01:28.671604 ==
5896 10:01:28.674833 RX Vref Scan: 0
5897 10:01:28.674915
5898 10:01:28.678345 RX Vref 0 -> 0, step: 1
5899 10:01:28.678427
5900 10:01:28.678492 RX Delay -53 -> 252, step: 4
5901 10:01:28.685979 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5902 10:01:28.689422 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5903 10:01:28.692623 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5904 10:01:28.696199 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5905 10:01:28.699279 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5906 10:01:28.706407 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5907 10:01:28.709426 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5908 10:01:28.712625 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5909 10:01:28.715867 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5910 10:01:28.719290 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5911 10:01:28.726040 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5912 10:01:28.729466 iDelay=199, Bit 11, Center 92 (3 ~ 182) 180
5913 10:01:28.733091 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5914 10:01:28.736107 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5915 10:01:28.739406 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5916 10:01:28.745932 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5917 10:01:28.746014 ==
5918 10:01:28.749172 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 10:01:28.752417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 10:01:28.752499 ==
5921 10:01:28.752564 DQS Delay:
5922 10:01:28.755955 DQS0 = 0, DQS1 = 0
5923 10:01:28.756037 DQM Delay:
5924 10:01:28.759283 DQM0 = 105, DQM1 = 97
5925 10:01:28.759365 DQ Delay:
5926 10:01:28.762399 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =104
5927 10:01:28.765894 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102
5928 10:01:28.769085 DQ8 =84, DQ9 =86, DQ10 =100, DQ11 =92
5929 10:01:28.772182 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =104
5930 10:01:28.772265
5931 10:01:28.772329
5932 10:01:28.782443 [DQSOSCAuto] RK1, (LSB)MR18= 0x2400, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5933 10:01:28.785519 CH1 RK1: MR19=505, MR18=2400
5934 10:01:28.789044 CH1_RK1: MR19=0x505, MR18=0x2400, DQSOSC=410, MR23=63, INC=64, DEC=42
5935 10:01:28.791975 [RxdqsGatingPostProcess] freq 933
5936 10:01:28.798885 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5937 10:01:28.801935 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 10:01:28.805383 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 10:01:28.808648 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 10:01:28.811875 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 10:01:28.815445 best DQS0 dly(2T, 0.5T) = (0, 10)
5942 10:01:28.818560 best DQS1 dly(2T, 0.5T) = (0, 10)
5943 10:01:28.822060 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5944 10:01:28.825516 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5945 10:01:28.828991 Pre-setting of DQS Precalculation
5946 10:01:28.832085 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5947 10:01:28.838937 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5948 10:01:28.845094 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5949 10:01:28.845223
5950 10:01:28.845330
5951 10:01:28.848501 [Calibration Summary] 1866 Mbps
5952 10:01:28.851707 CH 0, Rank 0
5953 10:01:28.851808 SW Impedance : PASS
5954 10:01:28.855309 DUTY Scan : NO K
5955 10:01:28.858473 ZQ Calibration : PASS
5956 10:01:28.858556 Jitter Meter : NO K
5957 10:01:28.861762 CBT Training : PASS
5958 10:01:28.864969 Write leveling : PASS
5959 10:01:28.865083 RX DQS gating : PASS
5960 10:01:28.868241 RX DQ/DQS(RDDQC) : PASS
5961 10:01:28.871585 TX DQ/DQS : PASS
5962 10:01:28.871685 RX DATLAT : PASS
5963 10:01:28.875271 RX DQ/DQS(Engine): PASS
5964 10:01:28.878305 TX OE : NO K
5965 10:01:28.878404 All Pass.
5966 10:01:28.878499
5967 10:01:28.878575 CH 0, Rank 1
5968 10:01:28.881658 SW Impedance : PASS
5969 10:01:28.885089 DUTY Scan : NO K
5970 10:01:28.885173 ZQ Calibration : PASS
5971 10:01:28.888573 Jitter Meter : NO K
5972 10:01:28.888682 CBT Training : PASS
5973 10:01:28.891607 Write leveling : PASS
5974 10:01:28.894907 RX DQS gating : PASS
5975 10:01:28.894993 RX DQ/DQS(RDDQC) : PASS
5976 10:01:28.898290 TX DQ/DQS : PASS
5977 10:01:28.901653 RX DATLAT : PASS
5978 10:01:28.901736 RX DQ/DQS(Engine): PASS
5979 10:01:28.905000 TX OE : NO K
5980 10:01:28.905083 All Pass.
5981 10:01:28.905148
5982 10:01:28.908148 CH 1, Rank 0
5983 10:01:28.908230 SW Impedance : PASS
5984 10:01:28.911349 DUTY Scan : NO K
5985 10:01:28.914572 ZQ Calibration : PASS
5986 10:01:28.914670 Jitter Meter : NO K
5987 10:01:28.917982 CBT Training : PASS
5988 10:01:28.921512 Write leveling : PASS
5989 10:01:28.921594 RX DQS gating : PASS
5990 10:01:28.924517 RX DQ/DQS(RDDQC) : PASS
5991 10:01:28.928029 TX DQ/DQS : PASS
5992 10:01:28.928139 RX DATLAT : PASS
5993 10:01:28.931358 RX DQ/DQS(Engine): PASS
5994 10:01:28.934758 TX OE : NO K
5995 10:01:28.934840 All Pass.
5996 10:01:28.934905
5997 10:01:28.934964 CH 1, Rank 1
5998 10:01:28.937819 SW Impedance : PASS
5999 10:01:28.940909 DUTY Scan : NO K
6000 10:01:28.940990 ZQ Calibration : PASS
6001 10:01:28.944522 Jitter Meter : NO K
6002 10:01:28.947826 CBT Training : PASS
6003 10:01:28.947907 Write leveling : PASS
6004 10:01:28.951297 RX DQS gating : PASS
6005 10:01:28.951378 RX DQ/DQS(RDDQC) : PASS
6006 10:01:28.954166 TX DQ/DQS : PASS
6007 10:01:28.957962 RX DATLAT : PASS
6008 10:01:28.958044 RX DQ/DQS(Engine): PASS
6009 10:01:28.961056 TX OE : NO K
6010 10:01:28.961152 All Pass.
6011 10:01:28.961217
6012 10:01:28.964236 DramC Write-DBI off
6013 10:01:28.967551 PER_BANK_REFRESH: Hybrid Mode
6014 10:01:28.967659 TX_TRACKING: ON
6015 10:01:28.977370 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6016 10:01:28.981092 [FAST_K] Save calibration result to emmc
6017 10:01:28.983936 dramc_set_vcore_voltage set vcore to 650000
6018 10:01:28.987225 Read voltage for 400, 6
6019 10:01:28.987319 Vio18 = 0
6020 10:01:28.990925 Vcore = 650000
6021 10:01:28.991019 Vdram = 0
6022 10:01:28.991104 Vddq = 0
6023 10:01:28.991188 Vmddr = 0
6024 10:01:28.997298 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6025 10:01:29.003818 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6026 10:01:29.003900 MEM_TYPE=3, freq_sel=20
6027 10:01:29.007135 sv_algorithm_assistance_LP4_800
6028 10:01:29.010503 ============ PULL DRAM RESETB DOWN ============
6029 10:01:29.017349 ========== PULL DRAM RESETB DOWN end =========
6030 10:01:29.020456 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6031 10:01:29.023690 ===================================
6032 10:01:29.027291 LPDDR4 DRAM CONFIGURATION
6033 10:01:29.030256 ===================================
6034 10:01:29.030338 EX_ROW_EN[0] = 0x0
6035 10:01:29.033724 EX_ROW_EN[1] = 0x0
6036 10:01:29.033805 LP4Y_EN = 0x0
6037 10:01:29.036730 WORK_FSP = 0x0
6038 10:01:29.036835 WL = 0x2
6039 10:01:29.040272 RL = 0x2
6040 10:01:29.043557 BL = 0x2
6041 10:01:29.043639 RPST = 0x0
6042 10:01:29.046831 RD_PRE = 0x0
6043 10:01:29.046912 WR_PRE = 0x1
6044 10:01:29.050338 WR_PST = 0x0
6045 10:01:29.050420 DBI_WR = 0x0
6046 10:01:29.053778 DBI_RD = 0x0
6047 10:01:29.053859 OTF = 0x1
6048 10:01:29.056770 ===================================
6049 10:01:29.060321 ===================================
6050 10:01:29.060467 ANA top config
6051 10:01:29.063387 ===================================
6052 10:01:29.066787 DLL_ASYNC_EN = 0
6053 10:01:29.070128 ALL_SLAVE_EN = 1
6054 10:01:29.073294 NEW_RANK_MODE = 1
6055 10:01:29.076914 DLL_IDLE_MODE = 1
6056 10:01:29.076989 LP45_APHY_COMB_EN = 1
6057 10:01:29.080274 TX_ODT_DIS = 1
6058 10:01:29.083667 NEW_8X_MODE = 1
6059 10:01:29.086972 ===================================
6060 10:01:29.090350 ===================================
6061 10:01:29.093462 data_rate = 800
6062 10:01:29.096574 CKR = 1
6063 10:01:29.096681 DQ_P2S_RATIO = 4
6064 10:01:29.100364 ===================================
6065 10:01:29.103391 CA_P2S_RATIO = 4
6066 10:01:29.106871 DQ_CA_OPEN = 0
6067 10:01:29.109942 DQ_SEMI_OPEN = 1
6068 10:01:29.113624 CA_SEMI_OPEN = 1
6069 10:01:29.116697 CA_FULL_RATE = 0
6070 10:01:29.116803 DQ_CKDIV4_EN = 0
6071 10:01:29.119943 CA_CKDIV4_EN = 1
6072 10:01:29.123572 CA_PREDIV_EN = 0
6073 10:01:29.126908 PH8_DLY = 0
6074 10:01:29.129924 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6075 10:01:29.133320 DQ_AAMCK_DIV = 0
6076 10:01:29.133399 CA_AAMCK_DIV = 0
6077 10:01:29.136566 CA_ADMCK_DIV = 4
6078 10:01:29.140132 DQ_TRACK_CA_EN = 0
6079 10:01:29.143125 CA_PICK = 800
6080 10:01:29.146791 CA_MCKIO = 400
6081 10:01:29.149962 MCKIO_SEMI = 400
6082 10:01:29.153142 PLL_FREQ = 3016
6083 10:01:29.153266 DQ_UI_PI_RATIO = 32
6084 10:01:29.156442 CA_UI_PI_RATIO = 32
6085 10:01:29.160087 ===================================
6086 10:01:29.163367 ===================================
6087 10:01:29.166820 memory_type:LPDDR4
6088 10:01:29.169906 GP_NUM : 10
6089 10:01:29.170019 SRAM_EN : 1
6090 10:01:29.173092 MD32_EN : 0
6091 10:01:29.176448 ===================================
6092 10:01:29.179878 [ANA_INIT] >>>>>>>>>>>>>>
6093 10:01:29.180000 <<<<<< [CONFIGURE PHASE]: ANA_TX
6094 10:01:29.183382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6095 10:01:29.186977 ===================================
6096 10:01:29.190342 data_rate = 800,PCW = 0X7400
6097 10:01:29.193279 ===================================
6098 10:01:29.196747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6099 10:01:29.203436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 10:01:29.213222 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 10:01:29.219795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6102 10:01:29.223187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6103 10:01:29.226741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6104 10:01:29.226865 [ANA_INIT] flow start
6105 10:01:29.230241 [ANA_INIT] PLL >>>>>>>>
6106 10:01:29.233394 [ANA_INIT] PLL <<<<<<<<
6107 10:01:29.233519 [ANA_INIT] MIDPI >>>>>>>>
6108 10:01:29.236949 [ANA_INIT] MIDPI <<<<<<<<
6109 10:01:29.240054 [ANA_INIT] DLL >>>>>>>>
6110 10:01:29.240169 [ANA_INIT] flow end
6111 10:01:29.246690 ============ LP4 DIFF to SE enter ============
6112 10:01:29.249879 ============ LP4 DIFF to SE exit ============
6113 10:01:29.253113 [ANA_INIT] <<<<<<<<<<<<<
6114 10:01:29.256496 [Flow] Enable top DCM control >>>>>
6115 10:01:29.260041 [Flow] Enable top DCM control <<<<<
6116 10:01:29.260163 Enable DLL master slave shuffle
6117 10:01:29.266654 ==============================================================
6118 10:01:29.269725 Gating Mode config
6119 10:01:29.273372 ==============================================================
6120 10:01:29.276430 Config description:
6121 10:01:29.286781 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6122 10:01:29.293472 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6123 10:01:29.296479 SELPH_MODE 0: By rank 1: By Phase
6124 10:01:29.303253 ==============================================================
6125 10:01:29.306808 GAT_TRACK_EN = 0
6126 10:01:29.309787 RX_GATING_MODE = 2
6127 10:01:29.313245 RX_GATING_TRACK_MODE = 2
6128 10:01:29.313367 SELPH_MODE = 1
6129 10:01:29.316855 PICG_EARLY_EN = 1
6130 10:01:29.319883 VALID_LAT_VALUE = 1
6131 10:01:29.326718 ==============================================================
6132 10:01:29.329862 Enter into Gating configuration >>>>
6133 10:01:29.333024 Exit from Gating configuration <<<<
6134 10:01:29.336447 Enter into DVFS_PRE_config >>>>>
6135 10:01:29.346373 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6136 10:01:29.349998 Exit from DVFS_PRE_config <<<<<
6137 10:01:29.353182 Enter into PICG configuration >>>>
6138 10:01:29.356845 Exit from PICG configuration <<<<
6139 10:01:29.359897 [RX_INPUT] configuration >>>>>
6140 10:01:29.363450 [RX_INPUT] configuration <<<<<
6141 10:01:29.366509 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6142 10:01:29.373122 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6143 10:01:29.379891 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 10:01:29.386330 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 10:01:29.389745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 10:01:29.396732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 10:01:29.400004 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6148 10:01:29.406594 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6149 10:01:29.409967 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6150 10:01:29.413118 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6151 10:01:29.416531 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6152 10:01:29.422940 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 10:01:29.426602 ===================================
6154 10:01:29.426676 LPDDR4 DRAM CONFIGURATION
6155 10:01:29.429763 ===================================
6156 10:01:29.433117 EX_ROW_EN[0] = 0x0
6157 10:01:29.436453 EX_ROW_EN[1] = 0x0
6158 10:01:29.436534 LP4Y_EN = 0x0
6159 10:01:29.439838 WORK_FSP = 0x0
6160 10:01:29.439919 WL = 0x2
6161 10:01:29.443158 RL = 0x2
6162 10:01:29.443239 BL = 0x2
6163 10:01:29.446572 RPST = 0x0
6164 10:01:29.446653 RD_PRE = 0x0
6165 10:01:29.449687 WR_PRE = 0x1
6166 10:01:29.449768 WR_PST = 0x0
6167 10:01:29.453228 DBI_WR = 0x0
6168 10:01:29.453309 DBI_RD = 0x0
6169 10:01:29.456613 OTF = 0x1
6170 10:01:29.459803 ===================================
6171 10:01:29.463485 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6172 10:01:29.466459 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6173 10:01:29.473087 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 10:01:29.476459 ===================================
6175 10:01:29.476563 LPDDR4 DRAM CONFIGURATION
6176 10:01:29.480125 ===================================
6177 10:01:29.483168 EX_ROW_EN[0] = 0x10
6178 10:01:29.486665 EX_ROW_EN[1] = 0x0
6179 10:01:29.486747 LP4Y_EN = 0x0
6180 10:01:29.490406 WORK_FSP = 0x0
6181 10:01:29.490512 WL = 0x2
6182 10:01:29.492968 RL = 0x2
6183 10:01:29.493049 BL = 0x2
6184 10:01:29.496681 RPST = 0x0
6185 10:01:29.496819 RD_PRE = 0x0
6186 10:01:29.499847 WR_PRE = 0x1
6187 10:01:29.499930 WR_PST = 0x0
6188 10:01:29.503060 DBI_WR = 0x0
6189 10:01:29.503184 DBI_RD = 0x0
6190 10:01:29.506449 OTF = 0x1
6191 10:01:29.509829 ===================================
6192 10:01:29.516373 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6193 10:01:29.519642 nWR fixed to 30
6194 10:01:29.519743 [ModeRegInit_LP4] CH0 RK0
6195 10:01:29.522734 [ModeRegInit_LP4] CH0 RK1
6196 10:01:29.526250 [ModeRegInit_LP4] CH1 RK0
6197 10:01:29.526349 [ModeRegInit_LP4] CH1 RK1
6198 10:01:29.529798 match AC timing 19
6199 10:01:29.532937 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6200 10:01:29.539440 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6201 10:01:29.542630 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6202 10:01:29.546267 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6203 10:01:29.553009 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6204 10:01:29.553091 ==
6205 10:01:29.556331 Dram Type= 6, Freq= 0, CH_0, rank 0
6206 10:01:29.559634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6207 10:01:29.559718 ==
6208 10:01:29.566145 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6209 10:01:29.569272 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6210 10:01:29.572766 [CA 0] Center 36 (8~64) winsize 57
6211 10:01:29.575904 [CA 1] Center 36 (8~64) winsize 57
6212 10:01:29.579374 [CA 2] Center 36 (8~64) winsize 57
6213 10:01:29.582732 [CA 3] Center 36 (8~64) winsize 57
6214 10:01:29.585953 [CA 4] Center 36 (8~64) winsize 57
6215 10:01:29.589256 [CA 5] Center 36 (8~64) winsize 57
6216 10:01:29.589379
6217 10:01:29.592701 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6218 10:01:29.592813
6219 10:01:29.595854 [CATrainingPosCal] consider 1 rank data
6220 10:01:29.599457 u2DelayCellTimex100 = 270/100 ps
6221 10:01:29.602675 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 10:01:29.605881 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 10:01:29.612647 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 10:01:29.615875 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 10:01:29.619458 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 10:01:29.622865 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 10:01:29.622962
6228 10:01:29.625891 CA PerBit enable=1, Macro0, CA PI delay=36
6229 10:01:29.625973
6230 10:01:29.629132 [CBTSetCACLKResult] CA Dly = 36
6231 10:01:29.629215 CS Dly: 1 (0~32)
6232 10:01:29.629280 ==
6233 10:01:29.632360 Dram Type= 6, Freq= 0, CH_0, rank 1
6234 10:01:29.639090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 10:01:29.639173 ==
6236 10:01:29.642911 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 10:01:29.649366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6238 10:01:29.652414 [CA 0] Center 36 (8~64) winsize 57
6239 10:01:29.655599 [CA 1] Center 36 (8~64) winsize 57
6240 10:01:29.659237 [CA 2] Center 36 (8~64) winsize 57
6241 10:01:29.662348 [CA 3] Center 36 (8~64) winsize 57
6242 10:01:29.665642 [CA 4] Center 36 (8~64) winsize 57
6243 10:01:29.668914 [CA 5] Center 36 (8~64) winsize 57
6244 10:01:29.669033
6245 10:01:29.672670 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6246 10:01:29.672801
6247 10:01:29.675706 [CATrainingPosCal] consider 2 rank data
6248 10:01:29.679232 u2DelayCellTimex100 = 270/100 ps
6249 10:01:29.682221 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 10:01:29.685800 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 10:01:29.689040 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 10:01:29.692602 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 10:01:29.695808 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 10:01:29.699142 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 10:01:29.702425
6256 10:01:29.705976 CA PerBit enable=1, Macro0, CA PI delay=36
6257 10:01:29.706081
6258 10:01:29.709168 [CBTSetCACLKResult] CA Dly = 36
6259 10:01:29.709255 CS Dly: 1 (0~32)
6260 10:01:29.709321
6261 10:01:29.712301 ----->DramcWriteLeveling(PI) begin...
6262 10:01:29.712384 ==
6263 10:01:29.715610 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 10:01:29.719060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 10:01:29.722583 ==
6266 10:01:29.722666 Write leveling (Byte 0): 40 => 8
6267 10:01:29.725887 Write leveling (Byte 1): 32 => 0
6268 10:01:29.728958 DramcWriteLeveling(PI) end<-----
6269 10:01:29.729040
6270 10:01:29.729104 ==
6271 10:01:29.732422 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 10:01:29.738931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 10:01:29.739058 ==
6274 10:01:29.739167 [Gating] SW mode calibration
6275 10:01:29.748963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6276 10:01:29.752118 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6277 10:01:29.755845 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 10:01:29.762160 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 10:01:29.765734 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 10:01:29.768687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 10:01:29.775374 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 10:01:29.778969 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 10:01:29.782134 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 10:01:29.788729 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 10:01:29.792347 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 10:01:29.795784 Total UI for P1: 0, mck2ui 16
6287 10:01:29.799510 best dqsien dly found for B0: ( 0, 14, 24)
6288 10:01:29.802287 Total UI for P1: 0, mck2ui 16
6289 10:01:29.805670 best dqsien dly found for B1: ( 0, 14, 24)
6290 10:01:29.808930 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6291 10:01:29.812553 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6292 10:01:29.812672
6293 10:01:29.816040 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 10:01:29.818784 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 10:01:29.822076 [Gating] SW calibration Done
6296 10:01:29.822196 ==
6297 10:01:29.825779 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 10:01:29.828757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 10:01:29.832433 ==
6300 10:01:29.832546 RX Vref Scan: 0
6301 10:01:29.832650
6302 10:01:29.835674 RX Vref 0 -> 0, step: 1
6303 10:01:29.835788
6304 10:01:29.838898 RX Delay -410 -> 252, step: 16
6305 10:01:29.842032 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6306 10:01:29.845545 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6307 10:01:29.848742 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6308 10:01:29.855299 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6309 10:01:29.858758 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6310 10:01:29.862407 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6311 10:01:29.865229 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6312 10:01:29.872276 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6313 10:01:29.875494 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6314 10:01:29.878615 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6315 10:01:29.882511 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6316 10:01:29.888652 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6317 10:01:29.892051 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6318 10:01:29.895365 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6319 10:01:29.898675 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6320 10:01:29.905644 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6321 10:01:29.905723 ==
6322 10:01:29.908907 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 10:01:29.911904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 10:01:29.911984 ==
6325 10:01:29.912046 DQS Delay:
6326 10:01:29.915353 DQS0 = 27, DQS1 = 43
6327 10:01:29.915431 DQM Delay:
6328 10:01:29.918684 DQM0 = 17, DQM1 = 12
6329 10:01:29.918763 DQ Delay:
6330 10:01:29.922073 DQ0 =16, DQ1 =24, DQ2 =16, DQ3 =8
6331 10:01:29.925448 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6332 10:01:29.928439 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6333 10:01:29.931893 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6334 10:01:29.931972
6335 10:01:29.932034
6336 10:01:29.932091 ==
6337 10:01:29.935101 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 10:01:29.938791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 10:01:29.938871 ==
6340 10:01:29.938932
6341 10:01:29.938990
6342 10:01:29.941854 TX Vref Scan disable
6343 10:01:29.945249 == TX Byte 0 ==
6344 10:01:29.948397 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 10:01:29.951970 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 10:01:29.952049 == TX Byte 1 ==
6347 10:01:29.958396 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6348 10:01:29.961950 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6349 10:01:29.962029 ==
6350 10:01:29.965372 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 10:01:29.968590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 10:01:29.968707 ==
6353 10:01:29.968839
6354 10:01:29.971744
6355 10:01:29.971845 TX Vref Scan disable
6356 10:01:29.975396 == TX Byte 0 ==
6357 10:01:29.978584 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 10:01:29.982237 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 10:01:29.985297 == TX Byte 1 ==
6360 10:01:29.988898 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6361 10:01:29.992033 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6362 10:01:29.992150
6363 10:01:29.992240 [DATLAT]
6364 10:01:29.995277 Freq=400, CH0 RK0
6365 10:01:29.995374
6366 10:01:29.998458 DATLAT Default: 0xf
6367 10:01:29.998559 0, 0xFFFF, sum = 0
6368 10:01:30.001643 1, 0xFFFF, sum = 0
6369 10:01:30.001742 2, 0xFFFF, sum = 0
6370 10:01:30.005090 3, 0xFFFF, sum = 0
6371 10:01:30.005190 4, 0xFFFF, sum = 0
6372 10:01:30.008343 5, 0xFFFF, sum = 0
6373 10:01:30.008442 6, 0xFFFF, sum = 0
6374 10:01:30.011639 7, 0xFFFF, sum = 0
6375 10:01:30.011806 8, 0xFFFF, sum = 0
6376 10:01:30.014973 9, 0xFFFF, sum = 0
6377 10:01:30.015082 10, 0xFFFF, sum = 0
6378 10:01:30.018458 11, 0xFFFF, sum = 0
6379 10:01:30.018559 12, 0xFFFF, sum = 0
6380 10:01:30.021886 13, 0x0, sum = 1
6381 10:01:30.021992 14, 0x0, sum = 2
6382 10:01:30.025034 15, 0x0, sum = 3
6383 10:01:30.025141 16, 0x0, sum = 4
6384 10:01:30.028784 best_step = 14
6385 10:01:30.028922
6386 10:01:30.029029 ==
6387 10:01:30.031757 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 10:01:30.035365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 10:01:30.035471 ==
6390 10:01:30.038440 RX Vref Scan: 1
6391 10:01:30.038550
6392 10:01:30.038677 RX Vref 0 -> 0, step: 1
6393 10:01:30.038771
6394 10:01:30.041577 RX Delay -327 -> 252, step: 8
6395 10:01:30.041673
6396 10:01:30.045033 Set Vref, RX VrefLevel [Byte0]: 57
6397 10:01:30.048384 [Byte1]: 48
6398 10:01:30.052486
6399 10:01:30.052585 Final RX Vref Byte 0 = 57 to rank0
6400 10:01:30.055895 Final RX Vref Byte 1 = 48 to rank0
6401 10:01:30.059217 Final RX Vref Byte 0 = 57 to rank1
6402 10:01:30.062449 Final RX Vref Byte 1 = 48 to rank1==
6403 10:01:30.066091 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 10:01:30.072431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 10:01:30.072540 ==
6406 10:01:30.072633 DQS Delay:
6407 10:01:30.072722 DQS0 = 28, DQS1 = 48
6408 10:01:30.075968 DQM Delay:
6409 10:01:30.076050 DQM0 = 12, DQM1 = 15
6410 10:01:30.079191 DQ Delay:
6411 10:01:30.082322 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6412 10:01:30.082404 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6413 10:01:30.085780 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6414 10:01:30.089343 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6415 10:01:30.089456
6416 10:01:30.092481
6417 10:01:30.099063 [DQSOSCAuto] RK0, (LSB)MR18= 0xafa6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6418 10:01:30.102615 CH0 RK0: MR19=C0C, MR18=AFA6
6419 10:01:30.109220 CH0_RK0: MR19=0xC0C, MR18=0xAFA6, DQSOSC=388, MR23=63, INC=392, DEC=261
6420 10:01:30.109303 ==
6421 10:01:30.112293 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 10:01:30.115539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 10:01:30.115647 ==
6424 10:01:30.119058 [Gating] SW mode calibration
6425 10:01:30.125490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6426 10:01:30.132332 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6427 10:01:30.135580 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 10:01:30.138924 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 10:01:30.145774 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 10:01:30.148709 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 10:01:30.152053 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 10:01:30.158658 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 10:01:30.162035 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 10:01:30.165292 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 10:01:30.171912 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 10:01:30.172037 Total UI for P1: 0, mck2ui 16
6437 10:01:30.175316 best dqsien dly found for B0: ( 0, 14, 24)
6438 10:01:30.178720 Total UI for P1: 0, mck2ui 16
6439 10:01:30.182295 best dqsien dly found for B1: ( 0, 14, 24)
6440 10:01:30.185368 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6441 10:01:30.191861 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6442 10:01:30.191994
6443 10:01:30.195431 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 10:01:30.198540 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 10:01:30.201721 [Gating] SW calibration Done
6446 10:01:30.201851 ==
6447 10:01:30.205308 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 10:01:30.208430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 10:01:30.208560 ==
6450 10:01:30.211974 RX Vref Scan: 0
6451 10:01:30.212091
6452 10:01:30.212200 RX Vref 0 -> 0, step: 1
6453 10:01:30.212308
6454 10:01:30.215166 RX Delay -410 -> 252, step: 16
6455 10:01:30.218305 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6456 10:01:30.225110 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6457 10:01:30.228505 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6458 10:01:30.232258 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6459 10:01:30.235055 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6460 10:01:30.241653 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6461 10:01:30.245259 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6462 10:01:30.248714 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6463 10:01:30.251733 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6464 10:01:30.258451 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6465 10:01:30.261931 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6466 10:01:30.265291 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6467 10:01:30.268347 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6468 10:01:30.275203 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6469 10:01:30.278641 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6470 10:01:30.281993 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6471 10:01:30.282077 ==
6472 10:01:30.285365 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 10:01:30.288575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 10:01:30.292022 ==
6475 10:01:30.292105 DQS Delay:
6476 10:01:30.292171 DQS0 = 27, DQS1 = 43
6477 10:01:30.295589 DQM Delay:
6478 10:01:30.295671 DQM0 = 9, DQM1 = 16
6479 10:01:30.298507 DQ Delay:
6480 10:01:30.298590 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6481 10:01:30.302033 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6482 10:01:30.305199 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6483 10:01:30.308884 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6484 10:01:30.308970
6485 10:01:30.309038
6486 10:01:30.309100 ==
6487 10:01:30.311853 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 10:01:30.318956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 10:01:30.319039 ==
6490 10:01:30.319134
6491 10:01:30.319253
6492 10:01:30.319350 TX Vref Scan disable
6493 10:01:30.321882 == TX Byte 0 ==
6494 10:01:30.325304 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6495 10:01:30.329018 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6496 10:01:30.331878 == TX Byte 1 ==
6497 10:01:30.335302 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6498 10:01:30.338530 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6499 10:01:30.342155 ==
6500 10:01:30.342279 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 10:01:30.348586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 10:01:30.348694 ==
6503 10:01:30.348819
6504 10:01:30.348885
6505 10:01:30.348943 TX Vref Scan disable
6506 10:01:30.352417 == TX Byte 0 ==
6507 10:01:30.355330 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6508 10:01:30.359009 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6509 10:01:30.362053 == TX Byte 1 ==
6510 10:01:30.365575 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6511 10:01:30.368872 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6512 10:01:30.368955
6513 10:01:30.372362 [DATLAT]
6514 10:01:30.372444 Freq=400, CH0 RK1
6515 10:01:30.372510
6516 10:01:30.375506 DATLAT Default: 0xe
6517 10:01:30.375589 0, 0xFFFF, sum = 0
6518 10:01:30.379079 1, 0xFFFF, sum = 0
6519 10:01:30.379166 2, 0xFFFF, sum = 0
6520 10:01:30.382526 3, 0xFFFF, sum = 0
6521 10:01:30.382631 4, 0xFFFF, sum = 0
6522 10:01:30.385810 5, 0xFFFF, sum = 0
6523 10:01:30.385894 6, 0xFFFF, sum = 0
6524 10:01:30.389194 7, 0xFFFF, sum = 0
6525 10:01:30.389279 8, 0xFFFF, sum = 0
6526 10:01:30.392241 9, 0xFFFF, sum = 0
6527 10:01:30.392348 10, 0xFFFF, sum = 0
6528 10:01:30.395480 11, 0xFFFF, sum = 0
6529 10:01:30.398835 12, 0xFFFF, sum = 0
6530 10:01:30.398919 13, 0x0, sum = 1
6531 10:01:30.399018 14, 0x0, sum = 2
6532 10:01:30.402413 15, 0x0, sum = 3
6533 10:01:30.402496 16, 0x0, sum = 4
6534 10:01:30.405519 best_step = 14
6535 10:01:30.405592
6536 10:01:30.405686 ==
6537 10:01:30.409056 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 10:01:30.412084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 10:01:30.412155 ==
6540 10:01:30.415589 RX Vref Scan: 0
6541 10:01:30.415657
6542 10:01:30.415716 RX Vref 0 -> 0, step: 1
6543 10:01:30.415773
6544 10:01:30.419150 RX Delay -327 -> 252, step: 8
6545 10:01:30.426904 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6546 10:01:30.430453 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6547 10:01:30.433395 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6548 10:01:30.436683 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6549 10:01:30.443674 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6550 10:01:30.447212 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6551 10:01:30.450225 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6552 10:01:30.453505 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6553 10:01:30.460080 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6554 10:01:30.463413 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6555 10:01:30.466584 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6556 10:01:30.470017 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6557 10:01:30.476626 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6558 10:01:30.479990 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6559 10:01:30.483603 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6560 10:01:30.490173 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6561 10:01:30.490295 ==
6562 10:01:30.493253 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 10:01:30.496589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 10:01:30.496712 ==
6565 10:01:30.496876 DQS Delay:
6566 10:01:30.499943 DQS0 = 28, DQS1 = 44
6567 10:01:30.500064 DQM Delay:
6568 10:01:30.503455 DQM0 = 11, DQM1 = 15
6569 10:01:30.503576 DQ Delay:
6570 10:01:30.506554 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6571 10:01:30.510078 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6572 10:01:30.513187 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6573 10:01:30.516869 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6574 10:01:30.516952
6575 10:01:30.517017
6576 10:01:30.523403 [DQSOSCAuto] RK1, (LSB)MR18= 0xc477, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6577 10:01:30.526763 CH0 RK1: MR19=C0C, MR18=C477
6578 10:01:30.533309 CH0_RK1: MR19=0xC0C, MR18=0xC477, DQSOSC=385, MR23=63, INC=398, DEC=265
6579 10:01:30.536915 [RxdqsGatingPostProcess] freq 400
6580 10:01:30.540128 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6581 10:01:30.543249 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 10:01:30.547301 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 10:01:30.550214 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 10:01:30.553707 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 10:01:30.556690 best DQS0 dly(2T, 0.5T) = (0, 10)
6586 10:01:30.560359 best DQS1 dly(2T, 0.5T) = (0, 10)
6587 10:01:30.563280 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6588 10:01:30.566854 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6589 10:01:30.570250 Pre-setting of DQS Precalculation
6590 10:01:30.573355 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6591 10:01:30.573439 ==
6592 10:01:30.576762 Dram Type= 6, Freq= 0, CH_1, rank 0
6593 10:01:30.583426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 10:01:30.583539 ==
6595 10:01:30.587169 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6596 10:01:30.593647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6597 10:01:30.597215 [CA 0] Center 36 (8~64) winsize 57
6598 10:01:30.600271 [CA 1] Center 36 (8~64) winsize 57
6599 10:01:30.603450 [CA 2] Center 36 (8~64) winsize 57
6600 10:01:30.606716 [CA 3] Center 36 (8~64) winsize 57
6601 10:01:30.610203 [CA 4] Center 36 (8~64) winsize 57
6602 10:01:30.613732 [CA 5] Center 36 (8~64) winsize 57
6603 10:01:30.613832
6604 10:01:30.616994 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6605 10:01:30.617092
6606 10:01:30.620333 [CATrainingPosCal] consider 1 rank data
6607 10:01:30.623273 u2DelayCellTimex100 = 270/100 ps
6608 10:01:30.626769 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 10:01:30.630083 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 10:01:30.633173 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 10:01:30.636701 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 10:01:30.640022 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 10:01:30.643173 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 10:01:30.643255
6615 10:01:30.649902 CA PerBit enable=1, Macro0, CA PI delay=36
6616 10:01:30.649993
6617 10:01:30.653249 [CBTSetCACLKResult] CA Dly = 36
6618 10:01:30.653350 CS Dly: 1 (0~32)
6619 10:01:30.653487 ==
6620 10:01:30.656349 Dram Type= 6, Freq= 0, CH_1, rank 1
6621 10:01:30.659809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 10:01:30.659893 ==
6623 10:01:30.666398 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 10:01:30.673217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6625 10:01:30.676446 [CA 0] Center 36 (8~64) winsize 57
6626 10:01:30.679870 [CA 1] Center 36 (8~64) winsize 57
6627 10:01:30.683011 [CA 2] Center 36 (8~64) winsize 57
6628 10:01:30.686687 [CA 3] Center 36 (8~64) winsize 57
6629 10:01:30.686770 [CA 4] Center 36 (8~64) winsize 57
6630 10:01:30.689843 [CA 5] Center 36 (8~64) winsize 57
6631 10:01:30.689956
6632 10:01:30.696272 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6633 10:01:30.696355
6634 10:01:30.699988 [CATrainingPosCal] consider 2 rank data
6635 10:01:30.703068 u2DelayCellTimex100 = 270/100 ps
6636 10:01:30.706240 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 10:01:30.710100 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 10:01:30.713189 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 10:01:30.716100 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 10:01:30.719781 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 10:01:30.722837 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 10:01:30.722920
6643 10:01:30.726572 CA PerBit enable=1, Macro0, CA PI delay=36
6644 10:01:30.726674
6645 10:01:30.729840 [CBTSetCACLKResult] CA Dly = 36
6646 10:01:30.732749 CS Dly: 1 (0~32)
6647 10:01:30.732847
6648 10:01:30.736000 ----->DramcWriteLeveling(PI) begin...
6649 10:01:30.736088 ==
6650 10:01:30.739550 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 10:01:30.742778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 10:01:30.742852 ==
6653 10:01:30.746238 Write leveling (Byte 0): 40 => 8
6654 10:01:30.749412 Write leveling (Byte 1): 32 => 0
6655 10:01:30.752728 DramcWriteLeveling(PI) end<-----
6656 10:01:30.752844
6657 10:01:30.752905 ==
6658 10:01:30.755975 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 10:01:30.759372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 10:01:30.759455 ==
6661 10:01:30.762779 [Gating] SW mode calibration
6662 10:01:30.769290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6663 10:01:30.776224 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6664 10:01:30.779189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 10:01:30.782889 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 10:01:30.789283 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 10:01:30.792571 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 10:01:30.795648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 10:01:30.802670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 10:01:30.805993 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 10:01:30.809361 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 10:01:30.815761 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 10:01:30.819285 Total UI for P1: 0, mck2ui 16
6674 10:01:30.822451 best dqsien dly found for B0: ( 0, 14, 24)
6675 10:01:30.822525 Total UI for P1: 0, mck2ui 16
6676 10:01:30.829412 best dqsien dly found for B1: ( 0, 14, 24)
6677 10:01:30.832317 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6678 10:01:30.835955 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6679 10:01:30.836037
6680 10:01:30.839006 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 10:01:30.842510 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 10:01:30.845862 [Gating] SW calibration Done
6683 10:01:30.845937 ==
6684 10:01:30.849139 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 10:01:30.852077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 10:01:30.852159 ==
6687 10:01:30.855552 RX Vref Scan: 0
6688 10:01:30.855635
6689 10:01:30.858743 RX Vref 0 -> 0, step: 1
6690 10:01:30.858820
6691 10:01:30.858925 RX Delay -410 -> 252, step: 16
6692 10:01:30.865811 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6693 10:01:30.868738 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6694 10:01:30.872366 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6695 10:01:30.875599 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6696 10:01:30.882574 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6697 10:01:30.885535 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6698 10:01:30.888738 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6699 10:01:30.892177 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6700 10:01:30.898933 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6701 10:01:30.902218 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6702 10:01:30.905536 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6703 10:01:30.909163 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6704 10:01:30.915676 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6705 10:01:30.918713 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6706 10:01:30.922196 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6707 10:01:30.925815 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6708 10:01:30.929014 ==
6709 10:01:30.932396 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 10:01:30.935477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 10:01:30.935576 ==
6712 10:01:30.935676 DQS Delay:
6713 10:01:30.938785 DQS0 = 27, DQS1 = 43
6714 10:01:30.938892 DQM Delay:
6715 10:01:30.941983 DQM0 = 9, DQM1 = 17
6716 10:01:30.942084 DQ Delay:
6717 10:01:30.945485 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6718 10:01:30.949084 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6719 10:01:30.952501 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6720 10:01:30.955538 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6721 10:01:30.955619
6722 10:01:30.955684
6723 10:01:30.955803 ==
6724 10:01:30.959125 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 10:01:30.962200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 10:01:30.962285 ==
6727 10:01:30.962367
6728 10:01:30.962445
6729 10:01:30.965641 TX Vref Scan disable
6730 10:01:30.965724 == TX Byte 0 ==
6731 10:01:30.972019 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 10:01:30.975143 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 10:01:30.975228 == TX Byte 1 ==
6734 10:01:30.982171 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6735 10:01:30.985141 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6736 10:01:30.985227 ==
6737 10:01:30.988619 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 10:01:30.991726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 10:01:30.991817 ==
6740 10:01:30.991902
6741 10:01:30.991988
6742 10:01:30.995098 TX Vref Scan disable
6743 10:01:30.995176 == TX Byte 0 ==
6744 10:01:31.002204 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 10:01:31.005264 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 10:01:31.005350 == TX Byte 1 ==
6747 10:01:31.011755 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6748 10:01:31.015324 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6749 10:01:31.015415
6750 10:01:31.015500 [DATLAT]
6751 10:01:31.018351 Freq=400, CH1 RK0
6752 10:01:31.018437
6753 10:01:31.018521 DATLAT Default: 0xf
6754 10:01:31.021854 0, 0xFFFF, sum = 0
6755 10:01:31.021941 1, 0xFFFF, sum = 0
6756 10:01:31.025081 2, 0xFFFF, sum = 0
6757 10:01:31.025168 3, 0xFFFF, sum = 0
6758 10:01:31.028833 4, 0xFFFF, sum = 0
6759 10:01:31.028920 5, 0xFFFF, sum = 0
6760 10:01:31.031698 6, 0xFFFF, sum = 0
6761 10:01:31.031786 7, 0xFFFF, sum = 0
6762 10:01:31.035287 8, 0xFFFF, sum = 0
6763 10:01:31.035375 9, 0xFFFF, sum = 0
6764 10:01:31.038429 10, 0xFFFF, sum = 0
6765 10:01:31.042074 11, 0xFFFF, sum = 0
6766 10:01:31.042164 12, 0xFFFF, sum = 0
6767 10:01:31.045480 13, 0x0, sum = 1
6768 10:01:31.045567 14, 0x0, sum = 2
6769 10:01:31.045653 15, 0x0, sum = 3
6770 10:01:31.048886 16, 0x0, sum = 4
6771 10:01:31.048973 best_step = 14
6772 10:01:31.049039
6773 10:01:31.052184 ==
6774 10:01:31.052268 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 10:01:31.058682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 10:01:31.058766 ==
6777 10:01:31.058832 RX Vref Scan: 1
6778 10:01:31.058894
6779 10:01:31.061974 RX Vref 0 -> 0, step: 1
6780 10:01:31.062058
6781 10:01:31.065384 RX Delay -327 -> 252, step: 8
6782 10:01:31.065499
6783 10:01:31.068629 Set Vref, RX VrefLevel [Byte0]: 51
6784 10:01:31.071702 [Byte1]: 58
6785 10:01:31.075250
6786 10:01:31.075339 Final RX Vref Byte 0 = 51 to rank0
6787 10:01:31.078553 Final RX Vref Byte 1 = 58 to rank0
6788 10:01:31.082125 Final RX Vref Byte 0 = 51 to rank1
6789 10:01:31.085300 Final RX Vref Byte 1 = 58 to rank1==
6790 10:01:31.088338 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 10:01:31.095076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 10:01:31.095174 ==
6793 10:01:31.095270 DQS Delay:
6794 10:01:31.098419 DQS0 = 32, DQS1 = 40
6795 10:01:31.098530 DQM Delay:
6796 10:01:31.098627 DQM0 = 12, DQM1 = 12
6797 10:01:31.101730 DQ Delay:
6798 10:01:31.105020 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6799 10:01:31.105197 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6800 10:01:31.108229 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6801 10:01:31.111527 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6802 10:01:31.111646
6803 10:01:31.115215
6804 10:01:31.121468 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ad4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6805 10:01:31.125134 CH1 RK0: MR19=C0C, MR18=9AD4
6806 10:01:31.131702 CH1_RK0: MR19=0xC0C, MR18=0x9AD4, DQSOSC=383, MR23=63, INC=402, DEC=268
6807 10:01:31.131791 ==
6808 10:01:31.134871 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 10:01:31.138405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 10:01:31.138489 ==
6811 10:01:31.141517 [Gating] SW mode calibration
6812 10:01:31.148134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6813 10:01:31.155113 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6814 10:01:31.158388 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 10:01:31.161817 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 10:01:31.164928 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 10:01:31.171454 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 10:01:31.174796 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 10:01:31.178333 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 10:01:31.184741 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 10:01:31.188142 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 10:01:31.191563 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 10:01:31.194692 Total UI for P1: 0, mck2ui 16
6824 10:01:31.198327 best dqsien dly found for B0: ( 0, 14, 24)
6825 10:01:31.201731 Total UI for P1: 0, mck2ui 16
6826 10:01:31.204851 best dqsien dly found for B1: ( 0, 14, 24)
6827 10:01:31.208030 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6828 10:01:31.211738 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6829 10:01:31.214883
6830 10:01:31.218291 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 10:01:31.222013 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 10:01:31.222115 [Gating] SW calibration Done
6833 10:01:31.225112 ==
6834 10:01:31.228379 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 10:01:31.231839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 10:01:31.231924 ==
6837 10:01:31.231991 RX Vref Scan: 0
6838 10:01:31.232055
6839 10:01:31.234940 RX Vref 0 -> 0, step: 1
6840 10:01:31.235071
6841 10:01:31.238588 RX Delay -410 -> 252, step: 16
6842 10:01:31.241649 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6843 10:01:31.245423 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6844 10:01:31.251937 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6845 10:01:31.255036 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6846 10:01:31.258662 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6847 10:01:31.261692 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6848 10:01:31.268442 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6849 10:01:31.271866 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6850 10:01:31.274926 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6851 10:01:31.278603 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6852 10:01:31.285477 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6853 10:01:31.288317 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6854 10:01:31.291815 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6855 10:01:31.295178 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6856 10:01:31.301637 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6857 10:01:31.305295 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6858 10:01:31.305419 ==
6859 10:01:31.308611 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 10:01:31.311637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 10:01:31.311761 ==
6862 10:01:31.315030 DQS Delay:
6863 10:01:31.315153 DQS0 = 35, DQS1 = 43
6864 10:01:31.318254 DQM Delay:
6865 10:01:31.318375 DQM0 = 16, DQM1 = 18
6866 10:01:31.318492 DQ Delay:
6867 10:01:31.321586 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6868 10:01:31.324945 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6869 10:01:31.328237 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6870 10:01:31.331655 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6871 10:01:31.331762
6872 10:01:31.331856
6873 10:01:31.331946 ==
6874 10:01:31.335102 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 10:01:31.341693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 10:01:31.341783 ==
6877 10:01:31.341850
6878 10:01:31.341911
6879 10:01:31.341970 TX Vref Scan disable
6880 10:01:31.345297 == TX Byte 0 ==
6881 10:01:31.348378 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6882 10:01:31.351665 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6883 10:01:31.355226 == TX Byte 1 ==
6884 10:01:31.358358 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6885 10:01:31.362057 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6886 10:01:31.362136 ==
6887 10:01:31.365075 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 10:01:31.371628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 10:01:31.371714 ==
6890 10:01:31.371780
6891 10:01:31.371844
6892 10:01:31.371906 TX Vref Scan disable
6893 10:01:31.374940 == TX Byte 0 ==
6894 10:01:31.378604 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6895 10:01:31.381770 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6896 10:01:31.384919 == TX Byte 1 ==
6897 10:01:31.388205 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6898 10:01:31.391721 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6899 10:01:31.391829
6900 10:01:31.395077 [DATLAT]
6901 10:01:31.395189 Freq=400, CH1 RK1
6902 10:01:31.395298
6903 10:01:31.398250 DATLAT Default: 0xe
6904 10:01:31.398367 0, 0xFFFF, sum = 0
6905 10:01:31.401773 1, 0xFFFF, sum = 0
6906 10:01:31.401879 2, 0xFFFF, sum = 0
6907 10:01:31.405058 3, 0xFFFF, sum = 0
6908 10:01:31.405142 4, 0xFFFF, sum = 0
6909 10:01:31.408459 5, 0xFFFF, sum = 0
6910 10:01:31.408573 6, 0xFFFF, sum = 0
6911 10:01:31.411600 7, 0xFFFF, sum = 0
6912 10:01:31.411707 8, 0xFFFF, sum = 0
6913 10:01:31.414789 9, 0xFFFF, sum = 0
6914 10:01:31.414890 10, 0xFFFF, sum = 0
6915 10:01:31.418166 11, 0xFFFF, sum = 0
6916 10:01:31.421521 12, 0xFFFF, sum = 0
6917 10:01:31.421630 13, 0x0, sum = 1
6918 10:01:31.424941 14, 0x0, sum = 2
6919 10:01:31.425058 15, 0x0, sum = 3
6920 10:01:31.425169 16, 0x0, sum = 4
6921 10:01:31.428162 best_step = 14
6922 10:01:31.428258
6923 10:01:31.428351 ==
6924 10:01:31.432100 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 10:01:31.434659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 10:01:31.434743 ==
6927 10:01:31.438269 RX Vref Scan: 0
6928 10:01:31.438345
6929 10:01:31.438427 RX Vref 0 -> 0, step: 1
6930 10:01:31.441640
6931 10:01:31.441722 RX Delay -327 -> 252, step: 8
6932 10:01:31.450277 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6933 10:01:31.453335 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6934 10:01:31.456553 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6935 10:01:31.459862 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6936 10:01:31.466215 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6937 10:01:31.470003 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6938 10:01:31.473222 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6939 10:01:31.476400 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6940 10:01:31.482825 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6941 10:01:31.486180 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6942 10:01:31.489520 iDelay=217, Bit 10, Center -24 (-255 ~ 208) 464
6943 10:01:31.496383 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6944 10:01:31.499535 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
6945 10:01:31.502659 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6946 10:01:31.506247 iDelay=217, Bit 14, Center -24 (-255 ~ 208) 464
6947 10:01:31.512551 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6948 10:01:31.512627 ==
6949 10:01:31.516194 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 10:01:31.519796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 10:01:31.519878 ==
6952 10:01:31.519942 DQS Delay:
6953 10:01:31.522868 DQS0 = 32, DQS1 = 40
6954 10:01:31.522949 DQM Delay:
6955 10:01:31.526062 DQM0 = 12, DQM1 = 14
6956 10:01:31.526145 DQ Delay:
6957 10:01:31.529498 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6958 10:01:31.532548 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12
6959 10:01:31.535944 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6960 10:01:31.539377 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =24
6961 10:01:31.539458
6962 10:01:31.539567
6963 10:01:31.545899 [DQSOSCAuto] RK1, (LSB)MR18= 0xa851, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6964 10:01:31.549158 CH1 RK1: MR19=C0C, MR18=A851
6965 10:01:31.555672 CH1_RK1: MR19=0xC0C, MR18=0xA851, DQSOSC=388, MR23=63, INC=392, DEC=261
6966 10:01:31.559065 [RxdqsGatingPostProcess] freq 400
6967 10:01:31.565679 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6968 10:01:31.569186 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 10:01:31.569304 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 10:01:31.572329 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 10:01:31.575780 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 10:01:31.579313 best DQS0 dly(2T, 0.5T) = (0, 10)
6973 10:01:31.582616 best DQS1 dly(2T, 0.5T) = (0, 10)
6974 10:01:31.586135 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6975 10:01:31.589228 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6976 10:01:31.592654 Pre-setting of DQS Precalculation
6977 10:01:31.598990 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6978 10:01:31.606014 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6979 10:01:31.612454 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6980 10:01:31.612578
6981 10:01:31.612693
6982 10:01:31.615891 [Calibration Summary] 800 Mbps
6983 10:01:31.616052 CH 0, Rank 0
6984 10:01:31.618964 SW Impedance : PASS
6985 10:01:31.622413 DUTY Scan : NO K
6986 10:01:31.622588 ZQ Calibration : PASS
6987 10:01:31.625528 Jitter Meter : NO K
6988 10:01:31.629028 CBT Training : PASS
6989 10:01:31.629148 Write leveling : PASS
6990 10:01:31.632105 RX DQS gating : PASS
6991 10:01:31.632264 RX DQ/DQS(RDDQC) : PASS
6992 10:01:31.635661 TX DQ/DQS : PASS
6993 10:01:31.638822 RX DATLAT : PASS
6994 10:01:31.638938 RX DQ/DQS(Engine): PASS
6995 10:01:31.642336 TX OE : NO K
6996 10:01:31.642462 All Pass.
6997 10:01:31.642570
6998 10:01:31.645875 CH 0, Rank 1
6999 10:01:31.645995 SW Impedance : PASS
7000 10:01:31.648984 DUTY Scan : NO K
7001 10:01:31.652076 ZQ Calibration : PASS
7002 10:01:31.652195 Jitter Meter : NO K
7003 10:01:31.655473 CBT Training : PASS
7004 10:01:31.658794 Write leveling : NO K
7005 10:01:31.658921 RX DQS gating : PASS
7006 10:01:31.662129 RX DQ/DQS(RDDQC) : PASS
7007 10:01:31.665634 TX DQ/DQS : PASS
7008 10:01:31.665756 RX DATLAT : PASS
7009 10:01:31.668746 RX DQ/DQS(Engine): PASS
7010 10:01:31.672226 TX OE : NO K
7011 10:01:31.672348 All Pass.
7012 10:01:31.672461
7013 10:01:31.672570 CH 1, Rank 0
7014 10:01:31.675706 SW Impedance : PASS
7015 10:01:31.678890 DUTY Scan : NO K
7016 10:01:31.679011 ZQ Calibration : PASS
7017 10:01:31.682054 Jitter Meter : NO K
7018 10:01:31.685382 CBT Training : PASS
7019 10:01:31.685503 Write leveling : PASS
7020 10:01:31.688704 RX DQS gating : PASS
7021 10:01:31.688858 RX DQ/DQS(RDDQC) : PASS
7022 10:01:31.692030 TX DQ/DQS : PASS
7023 10:01:31.695351 RX DATLAT : PASS
7024 10:01:31.695475 RX DQ/DQS(Engine): PASS
7025 10:01:31.699143 TX OE : NO K
7026 10:01:31.699267 All Pass.
7027 10:01:31.699382
7028 10:01:31.702103 CH 1, Rank 1
7029 10:01:31.702223 SW Impedance : PASS
7030 10:01:31.705565 DUTY Scan : NO K
7031 10:01:31.708529 ZQ Calibration : PASS
7032 10:01:31.708645 Jitter Meter : NO K
7033 10:01:31.712167 CBT Training : PASS
7034 10:01:31.715503 Write leveling : NO K
7035 10:01:31.715625 RX DQS gating : PASS
7036 10:01:31.718886 RX DQ/DQS(RDDQC) : PASS
7037 10:01:31.722016 TX DQ/DQS : PASS
7038 10:01:31.722143 RX DATLAT : PASS
7039 10:01:31.725355 RX DQ/DQS(Engine): PASS
7040 10:01:31.725479 TX OE : NO K
7041 10:01:31.728582 All Pass.
7042 10:01:31.728700
7043 10:01:31.728849 DramC Write-DBI off
7044 10:01:31.731975 PER_BANK_REFRESH: Hybrid Mode
7045 10:01:31.735146 TX_TRACKING: ON
7046 10:01:31.742073 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7047 10:01:31.745184 [FAST_K] Save calibration result to emmc
7048 10:01:31.751885 dramc_set_vcore_voltage set vcore to 725000
7049 10:01:31.752004 Read voltage for 1600, 0
7050 10:01:31.755282 Vio18 = 0
7051 10:01:31.755400 Vcore = 725000
7052 10:01:31.755508 Vdram = 0
7053 10:01:31.755609 Vddq = 0
7054 10:01:31.758759 Vmddr = 0
7055 10:01:31.761827 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7056 10:01:31.768568 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7057 10:01:31.771926 MEM_TYPE=3, freq_sel=13
7058 10:01:31.772044 sv_algorithm_assistance_LP4_3733
7059 10:01:31.778474 ============ PULL DRAM RESETB DOWN ============
7060 10:01:31.782057 ========== PULL DRAM RESETB DOWN end =========
7061 10:01:31.785005 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7062 10:01:31.788419 ===================================
7063 10:01:31.791956 LPDDR4 DRAM CONFIGURATION
7064 10:01:31.795290 ===================================
7065 10:01:31.798282 EX_ROW_EN[0] = 0x0
7066 10:01:31.798353 EX_ROW_EN[1] = 0x0
7067 10:01:31.801706 LP4Y_EN = 0x0
7068 10:01:31.801777 WORK_FSP = 0x1
7069 10:01:31.804963 WL = 0x5
7070 10:01:31.805046 RL = 0x5
7071 10:01:31.808264 BL = 0x2
7072 10:01:31.808346 RPST = 0x0
7073 10:01:31.811807 RD_PRE = 0x0
7074 10:01:31.811889 WR_PRE = 0x1
7075 10:01:31.815169 WR_PST = 0x1
7076 10:01:31.815251 DBI_WR = 0x0
7077 10:01:31.818388 DBI_RD = 0x0
7078 10:01:31.818470 OTF = 0x1
7079 10:01:31.821728 ===================================
7080 10:01:31.824881 ===================================
7081 10:01:31.828344 ANA top config
7082 10:01:31.831621 ===================================
7083 10:01:31.834871 DLL_ASYNC_EN = 0
7084 10:01:31.834951 ALL_SLAVE_EN = 0
7085 10:01:31.838568 NEW_RANK_MODE = 1
7086 10:01:31.841906 DLL_IDLE_MODE = 1
7087 10:01:31.844977 LP45_APHY_COMB_EN = 1
7088 10:01:31.845078 TX_ODT_DIS = 0
7089 10:01:31.848370 NEW_8X_MODE = 1
7090 10:01:31.851732 ===================================
7091 10:01:31.854981 ===================================
7092 10:01:31.858442 data_rate = 3200
7093 10:01:31.862086 CKR = 1
7094 10:01:31.865073 DQ_P2S_RATIO = 8
7095 10:01:31.868514 ===================================
7096 10:01:31.871590 CA_P2S_RATIO = 8
7097 10:01:31.871708 DQ_CA_OPEN = 0
7098 10:01:31.875045 DQ_SEMI_OPEN = 0
7099 10:01:31.878307 CA_SEMI_OPEN = 0
7100 10:01:31.881925 CA_FULL_RATE = 0
7101 10:01:31.885181 DQ_CKDIV4_EN = 0
7102 10:01:31.888290 CA_CKDIV4_EN = 0
7103 10:01:31.888399 CA_PREDIV_EN = 0
7104 10:01:31.891656 PH8_DLY = 12
7105 10:01:31.895029 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7106 10:01:31.898175 DQ_AAMCK_DIV = 4
7107 10:01:31.901589 CA_AAMCK_DIV = 4
7108 10:01:31.905015 CA_ADMCK_DIV = 4
7109 10:01:31.905090 DQ_TRACK_CA_EN = 0
7110 10:01:31.908122 CA_PICK = 1600
7111 10:01:31.911609 CA_MCKIO = 1600
7112 10:01:31.914859 MCKIO_SEMI = 0
7113 10:01:31.918400 PLL_FREQ = 3068
7114 10:01:31.921419 DQ_UI_PI_RATIO = 32
7115 10:01:31.924928 CA_UI_PI_RATIO = 0
7116 10:01:31.928391 ===================================
7117 10:01:31.931448 ===================================
7118 10:01:31.931530 memory_type:LPDDR4
7119 10:01:31.935060 GP_NUM : 10
7120 10:01:31.938271 SRAM_EN : 1
7121 10:01:31.938372 MD32_EN : 0
7122 10:01:31.941590 ===================================
7123 10:01:31.945087 [ANA_INIT] >>>>>>>>>>>>>>
7124 10:01:31.948183 <<<<<< [CONFIGURE PHASE]: ANA_TX
7125 10:01:31.951946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7126 10:01:31.955088 ===================================
7127 10:01:31.958182 data_rate = 3200,PCW = 0X7600
7128 10:01:31.961737 ===================================
7129 10:01:31.965083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7130 10:01:31.968079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 10:01:31.974658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 10:01:31.977992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7133 10:01:31.981682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7134 10:01:31.984779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7135 10:01:31.988080 [ANA_INIT] flow start
7136 10:01:31.991230 [ANA_INIT] PLL >>>>>>>>
7137 10:01:31.991349 [ANA_INIT] PLL <<<<<<<<
7138 10:01:31.995115 [ANA_INIT] MIDPI >>>>>>>>
7139 10:01:31.997980 [ANA_INIT] MIDPI <<<<<<<<
7140 10:01:31.998104 [ANA_INIT] DLL >>>>>>>>
7141 10:01:32.001458 [ANA_INIT] DLL <<<<<<<<
7142 10:01:32.004552 [ANA_INIT] flow end
7143 10:01:32.008175 ============ LP4 DIFF to SE enter ============
7144 10:01:32.011398 ============ LP4 DIFF to SE exit ============
7145 10:01:32.014400 [ANA_INIT] <<<<<<<<<<<<<
7146 10:01:32.017869 [Flow] Enable top DCM control >>>>>
7147 10:01:32.021436 [Flow] Enable top DCM control <<<<<
7148 10:01:32.024857 Enable DLL master slave shuffle
7149 10:01:32.028116 ==============================================================
7150 10:01:32.031490 Gating Mode config
7151 10:01:32.038224 ==============================================================
7152 10:01:32.038304 Config description:
7153 10:01:32.047892 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7154 10:01:32.054234 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7155 10:01:32.060944 SELPH_MODE 0: By rank 1: By Phase
7156 10:01:32.064391 ==============================================================
7157 10:01:32.067744 GAT_TRACK_EN = 1
7158 10:01:32.071087 RX_GATING_MODE = 2
7159 10:01:32.074601 RX_GATING_TRACK_MODE = 2
7160 10:01:32.077725 SELPH_MODE = 1
7161 10:01:32.080930 PICG_EARLY_EN = 1
7162 10:01:32.084180 VALID_LAT_VALUE = 1
7163 10:01:32.087882 ==============================================================
7164 10:01:32.090741 Enter into Gating configuration >>>>
7165 10:01:32.094157 Exit from Gating configuration <<<<
7166 10:01:32.097556 Enter into DVFS_PRE_config >>>>>
7167 10:01:32.110634 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7168 10:01:32.114062 Exit from DVFS_PRE_config <<<<<
7169 10:01:32.117617 Enter into PICG configuration >>>>
7170 10:01:32.117715 Exit from PICG configuration <<<<
7171 10:01:32.120826 [RX_INPUT] configuration >>>>>
7172 10:01:32.123924 [RX_INPUT] configuration <<<<<
7173 10:01:32.130740 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7174 10:01:32.134001 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7175 10:01:32.140438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 10:01:32.147064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 10:01:32.153714 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 10:01:32.160419 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 10:01:32.163924 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7180 10:01:32.166809 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7181 10:01:32.170211 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7182 10:01:32.176759 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7183 10:01:32.180893 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7184 10:01:32.183516 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7185 10:01:32.186956 ===================================
7186 10:01:32.190202 LPDDR4 DRAM CONFIGURATION
7187 10:01:32.193375 ===================================
7188 10:01:32.196888 EX_ROW_EN[0] = 0x0
7189 10:01:32.196974 EX_ROW_EN[1] = 0x0
7190 10:01:32.200399 LP4Y_EN = 0x0
7191 10:01:32.200502 WORK_FSP = 0x1
7192 10:01:32.203615 WL = 0x5
7193 10:01:32.203696 RL = 0x5
7194 10:01:32.206739 BL = 0x2
7195 10:01:32.206820 RPST = 0x0
7196 10:01:32.209977 RD_PRE = 0x0
7197 10:01:32.210058 WR_PRE = 0x1
7198 10:01:32.213504 WR_PST = 0x1
7199 10:01:32.213585 DBI_WR = 0x0
7200 10:01:32.216942 DBI_RD = 0x0
7201 10:01:32.217023 OTF = 0x1
7202 10:01:32.220146 ===================================
7203 10:01:32.226631 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7204 10:01:32.230232 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7205 10:01:32.233272 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 10:01:32.236959 ===================================
7207 10:01:32.240292 LPDDR4 DRAM CONFIGURATION
7208 10:01:32.243222 ===================================
7209 10:01:32.246958 EX_ROW_EN[0] = 0x10
7210 10:01:32.247079 EX_ROW_EN[1] = 0x0
7211 10:01:32.249950 LP4Y_EN = 0x0
7212 10:01:32.250069 WORK_FSP = 0x1
7213 10:01:32.253225 WL = 0x5
7214 10:01:32.253344 RL = 0x5
7215 10:01:32.256746 BL = 0x2
7216 10:01:32.256903 RPST = 0x0
7217 10:01:32.259837 RD_PRE = 0x0
7218 10:01:32.259953 WR_PRE = 0x1
7219 10:01:32.263371 WR_PST = 0x1
7220 10:01:32.263473 DBI_WR = 0x0
7221 10:01:32.266461 DBI_RD = 0x0
7222 10:01:32.266557 OTF = 0x1
7223 10:01:32.270031 ===================================
7224 10:01:32.276226 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7225 10:01:32.276307 ==
7226 10:01:32.280050 Dram Type= 6, Freq= 0, CH_0, rank 0
7227 10:01:32.286988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7228 10:01:32.287070 ==
7229 10:01:32.287135 [Duty_Offset_Calibration]
7230 10:01:32.289982 B0:2 B1:0 CA:1
7231 10:01:32.290080
7232 10:01:32.293044 [DutyScan_Calibration_Flow] k_type=0
7233 10:01:32.301557
7234 10:01:32.301640 ==CLK 0==
7235 10:01:32.304890 Final CLK duty delay cell = -4
7236 10:01:32.307985 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7237 10:01:32.311508 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7238 10:01:32.314545 [-4] AVG Duty = 4922%(X100)
7239 10:01:32.314631
7240 10:01:32.318132 CH0 CLK Duty spec in!! Max-Min= 218%
7241 10:01:32.321335 [DutyScan_Calibration_Flow] ====Done====
7242 10:01:32.321438
7243 10:01:32.324901 [DutyScan_Calibration_Flow] k_type=1
7244 10:01:32.340878
7245 10:01:32.341004 ==DQS 0 ==
7246 10:01:32.344055 Final DQS duty delay cell = 0
7247 10:01:32.347493 [0] MAX Duty = 5249%(X100), DQS PI = 32
7248 10:01:32.350637 [0] MIN Duty = 4969%(X100), DQS PI = 0
7249 10:01:32.350754 [0] AVG Duty = 5109%(X100)
7250 10:01:32.353825
7251 10:01:32.353943 ==DQS 1 ==
7252 10:01:32.357538 Final DQS duty delay cell = -4
7253 10:01:32.360458 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7254 10:01:32.364256 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7255 10:01:32.367184 [-4] AVG Duty = 5000%(X100)
7256 10:01:32.367303
7257 10:01:32.370675 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7258 10:01:32.370789
7259 10:01:32.373704 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7260 10:01:32.377234 [DutyScan_Calibration_Flow] ====Done====
7261 10:01:32.377356
7262 10:01:32.380695 [DutyScan_Calibration_Flow] k_type=3
7263 10:01:32.398018
7264 10:01:32.398099 ==DQM 0 ==
7265 10:01:32.401244 Final DQM duty delay cell = 0
7266 10:01:32.405014 [0] MAX Duty = 5124%(X100), DQS PI = 26
7267 10:01:32.408115 [0] MIN Duty = 4813%(X100), DQS PI = 50
7268 10:01:32.411456 [0] AVG Duty = 4968%(X100)
7269 10:01:32.411538
7270 10:01:32.411601 ==DQM 1 ==
7271 10:01:32.414870 Final DQM duty delay cell = 0
7272 10:01:32.417948 [0] MAX Duty = 5249%(X100), DQS PI = 44
7273 10:01:32.421728 [0] MIN Duty = 5000%(X100), DQS PI = 20
7274 10:01:32.424749 [0] AVG Duty = 5124%(X100)
7275 10:01:32.424851
7276 10:01:32.428216 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7277 10:01:32.428297
7278 10:01:32.431307 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7279 10:01:32.434519 [DutyScan_Calibration_Flow] ====Done====
7280 10:01:32.434602
7281 10:01:32.437903 [DutyScan_Calibration_Flow] k_type=2
7282 10:01:32.455540
7283 10:01:32.455622 ==DQ 0 ==
7284 10:01:32.458628 Final DQ duty delay cell = 0
7285 10:01:32.461852 [0] MAX Duty = 5156%(X100), DQS PI = 36
7286 10:01:32.465180 [0] MIN Duty = 5000%(X100), DQS PI = 0
7287 10:01:32.465263 [0] AVG Duty = 5078%(X100)
7288 10:01:32.465328
7289 10:01:32.468578 ==DQ 1 ==
7290 10:01:32.471972 Final DQ duty delay cell = 0
7291 10:01:32.475435 [0] MAX Duty = 4969%(X100), DQS PI = 44
7292 10:01:32.478577 [0] MIN Duty = 4875%(X100), DQS PI = 10
7293 10:01:32.478659 [0] AVG Duty = 4922%(X100)
7294 10:01:32.478726
7295 10:01:32.481991 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7296 10:01:32.485626
7297 10:01:32.485705 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7298 10:01:32.492127 [DutyScan_Calibration_Flow] ====Done====
7299 10:01:32.492232 ==
7300 10:01:32.495088 Dram Type= 6, Freq= 0, CH_1, rank 0
7301 10:01:32.498694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7302 10:01:32.498816 ==
7303 10:01:32.502036 [Duty_Offset_Calibration]
7304 10:01:32.502193 B0:0 B1:-1 CA:2
7305 10:01:32.502305
7306 10:01:32.505271 [DutyScan_Calibration_Flow] k_type=0
7307 10:01:32.515733
7308 10:01:32.515838 ==CLK 0==
7309 10:01:32.519076 Final CLK duty delay cell = 0
7310 10:01:32.522215 [0] MAX Duty = 5156%(X100), DQS PI = 10
7311 10:01:32.525430 [0] MIN Duty = 4906%(X100), DQS PI = 46
7312 10:01:32.525511 [0] AVG Duty = 5031%(X100)
7313 10:01:32.528946
7314 10:01:32.532212 CH1 CLK Duty spec in!! Max-Min= 250%
7315 10:01:32.535651 [DutyScan_Calibration_Flow] ====Done====
7316 10:01:32.535731
7317 10:01:32.538861 [DutyScan_Calibration_Flow] k_type=1
7318 10:01:32.555463
7319 10:01:32.555585 ==DQS 0 ==
7320 10:01:32.558461 Final DQS duty delay cell = 0
7321 10:01:32.561948 [0] MAX Duty = 5124%(X100), DQS PI = 26
7322 10:01:32.565331 [0] MIN Duty = 4969%(X100), DQS PI = 60
7323 10:01:32.568638 [0] AVG Duty = 5046%(X100)
7324 10:01:32.568741
7325 10:01:32.568829 ==DQS 1 ==
7326 10:01:32.571989 Final DQS duty delay cell = 0
7327 10:01:32.574929 [0] MAX Duty = 5187%(X100), DQS PI = 0
7328 10:01:32.578364 [0] MIN Duty = 4844%(X100), DQS PI = 34
7329 10:01:32.581552 [0] AVG Duty = 5015%(X100)
7330 10:01:32.581657
7331 10:01:32.584954 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7332 10:01:32.585026
7333 10:01:32.588187 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7334 10:01:32.591848 [DutyScan_Calibration_Flow] ====Done====
7335 10:01:32.591942
7336 10:01:32.594880 [DutyScan_Calibration_Flow] k_type=3
7337 10:01:32.612672
7338 10:01:32.612815 ==DQM 0 ==
7339 10:01:32.616433 Final DQM duty delay cell = 4
7340 10:01:32.619381 [4] MAX Duty = 5125%(X100), DQS PI = 8
7341 10:01:32.622936 [4] MIN Duty = 5000%(X100), DQS PI = 30
7342 10:01:32.623019 [4] AVG Duty = 5062%(X100)
7343 10:01:32.626220
7344 10:01:32.626327 ==DQM 1 ==
7345 10:01:32.629685 Final DQM duty delay cell = 0
7346 10:01:32.633067 [0] MAX Duty = 5281%(X100), DQS PI = 58
7347 10:01:32.636095 [0] MIN Duty = 4876%(X100), DQS PI = 34
7348 10:01:32.639391 [0] AVG Duty = 5078%(X100)
7349 10:01:32.639475
7350 10:01:32.643104 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7351 10:01:32.643188
7352 10:01:32.646043 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7353 10:01:32.649636 [DutyScan_Calibration_Flow] ====Done====
7354 10:01:32.649719
7355 10:01:32.652873 [DutyScan_Calibration_Flow] k_type=2
7356 10:01:32.669706
7357 10:01:32.669805 ==DQ 0 ==
7358 10:01:32.673009 Final DQ duty delay cell = 0
7359 10:01:32.676321 [0] MAX Duty = 5093%(X100), DQS PI = 20
7360 10:01:32.679530 [0] MIN Duty = 5000%(X100), DQS PI = 8
7361 10:01:32.679615 [0] AVG Duty = 5046%(X100)
7362 10:01:32.679682
7363 10:01:32.683119 ==DQ 1 ==
7364 10:01:32.686699 Final DQ duty delay cell = 0
7365 10:01:32.689800 [0] MAX Duty = 5062%(X100), DQS PI = 0
7366 10:01:32.692886 [0] MIN Duty = 4844%(X100), DQS PI = 32
7367 10:01:32.692996 [0] AVG Duty = 4953%(X100)
7368 10:01:32.693096
7369 10:01:32.696334 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7370 10:01:32.696443
7371 10:01:32.699993 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7372 10:01:32.706575 [DutyScan_Calibration_Flow] ====Done====
7373 10:01:32.709703 nWR fixed to 30
7374 10:01:32.709827 [ModeRegInit_LP4] CH0 RK0
7375 10:01:32.713342 [ModeRegInit_LP4] CH0 RK1
7376 10:01:32.716139 [ModeRegInit_LP4] CH1 RK0
7377 10:01:32.716221 [ModeRegInit_LP4] CH1 RK1
7378 10:01:32.719522 match AC timing 5
7379 10:01:32.722882 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7380 10:01:32.726018 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7381 10:01:32.732651 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7382 10:01:32.736221 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7383 10:01:32.743114 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7384 10:01:32.743198 [MiockJmeterHQA]
7385 10:01:32.743263
7386 10:01:32.746064 [DramcMiockJmeter] u1RxGatingPI = 0
7387 10:01:32.749589 0 : 4257, 4030
7388 10:01:32.749673 4 : 4363, 4138
7389 10:01:32.749739 8 : 4363, 4138
7390 10:01:32.752657 12 : 4255, 4027
7391 10:01:32.752764 16 : 4257, 4029
7392 10:01:32.756343 20 : 4252, 4027
7393 10:01:32.756426 24 : 4257, 4029
7394 10:01:32.759361 28 : 4253, 4027
7395 10:01:32.759444 32 : 4252, 4027
7396 10:01:32.759511 36 : 4365, 4140
7397 10:01:32.763173 40 : 4363, 4137
7398 10:01:32.763300 44 : 4363, 4137
7399 10:01:32.766243 48 : 4252, 4027
7400 10:01:32.766345 52 : 4363, 4137
7401 10:01:32.769564 56 : 4253, 4027
7402 10:01:32.769667 60 : 4252, 4027
7403 10:01:32.773095 64 : 4255, 4029
7404 10:01:32.773179 68 : 4250, 4027
7405 10:01:32.773245 72 : 4252, 4027
7406 10:01:32.776277 76 : 4250, 4026
7407 10:01:32.776390 80 : 4252, 4029
7408 10:01:32.779352 84 : 4252, 4027
7409 10:01:32.779463 88 : 4363, 3664
7410 10:01:32.782852 92 : 4253, 0
7411 10:01:32.782936 96 : 4250, 0
7412 10:01:32.783002 100 : 4360, 0
7413 10:01:32.786420 104 : 4361, 0
7414 10:01:32.786526 108 : 4252, 0
7415 10:01:32.786617 112 : 4253, 0
7416 10:01:32.789504 116 : 4252, 0
7417 10:01:32.789575 120 : 4252, 0
7418 10:01:32.792872 124 : 4253, 0
7419 10:01:32.792943 128 : 4255, 0
7420 10:01:32.793002 132 : 4255, 0
7421 10:01:32.796439 136 : 4250, 0
7422 10:01:32.796536 140 : 4250, 0
7423 10:01:32.799549 144 : 4250, 0
7424 10:01:32.799638 148 : 4361, 0
7425 10:01:32.799728 152 : 4249, 0
7426 10:01:32.802693 156 : 4361, 0
7427 10:01:32.802764 160 : 4250, 0
7428 10:01:32.802838 164 : 4249, 0
7429 10:01:32.806311 168 : 4250, 0
7430 10:01:32.806408 172 : 4252, 0
7431 10:01:32.809532 176 : 4250, 0
7432 10:01:32.809602 180 : 4250, 0
7433 10:01:32.809671 184 : 4253, 0
7434 10:01:32.812856 188 : 4253, 0
7435 10:01:32.812953 192 : 4250, 0
7436 10:01:32.815942 196 : 4250, 0
7437 10:01:32.816063 200 : 4363, 3
7438 10:01:32.816172 204 : 4250, 2191
7439 10:01:32.819356 208 : 4361, 4137
7440 10:01:32.819485 212 : 4253, 4029
7441 10:01:32.822664 216 : 4361, 4138
7442 10:01:32.822782 220 : 4360, 4138
7443 10:01:32.825916 224 : 4250, 4027
7444 10:01:32.826038 228 : 4250, 4026
7445 10:01:32.829242 232 : 4253, 4029
7446 10:01:32.829349 236 : 4250, 4027
7447 10:01:32.832937 240 : 4249, 4027
7448 10:01:32.833020 244 : 4363, 4137
7449 10:01:32.836036 248 : 4250, 4026
7450 10:01:32.836120 252 : 4250, 4027
7451 10:01:32.839430 256 : 4250, 4027
7452 10:01:32.839514 260 : 4253, 4027
7453 10:01:32.839581 264 : 4363, 4140
7454 10:01:32.842488 268 : 4250, 4027
7455 10:01:32.842572 272 : 4360, 4138
7456 10:01:32.845799 276 : 4255, 4029
7457 10:01:32.845883 280 : 4250, 4026
7458 10:01:32.849295 284 : 4250, 4027
7459 10:01:32.849379 288 : 4250, 4027
7460 10:01:32.852933 292 : 4254, 4030
7461 10:01:32.853016 296 : 4361, 4137
7462 10:01:32.855954 300 : 4250, 4027
7463 10:01:32.856038 304 : 4250, 4027
7464 10:01:32.859151 308 : 4255, 4030
7465 10:01:32.859238 312 : 4250, 3918
7466 10:01:32.862494 316 : 4363, 2180
7467 10:01:32.862578
7468 10:01:32.862643 MIOCK jitter meter ch=0
7469 10:01:32.862703
7470 10:01:32.865638 1T = (316-92) = 224 dly cells
7471 10:01:32.873057 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7472 10:01:32.873140 ==
7473 10:01:32.876244 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 10:01:32.879365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7475 10:01:32.879449 ==
7476 10:01:32.885925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7477 10:01:32.889316 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7478 10:01:32.892403 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7479 10:01:32.899117 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7480 10:01:32.908195 [CA 0] Center 43 (13~73) winsize 61
7481 10:01:32.911820 [CA 1] Center 43 (13~73) winsize 61
7482 10:01:32.915261 [CA 2] Center 38 (8~68) winsize 61
7483 10:01:32.918873 [CA 3] Center 37 (8~67) winsize 60
7484 10:01:32.921920 [CA 4] Center 36 (6~66) winsize 61
7485 10:01:32.925360 [CA 5] Center 35 (5~65) winsize 61
7486 10:01:32.925442
7487 10:01:32.928657 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7488 10:01:32.928745
7489 10:01:32.931765 [CATrainingPosCal] consider 1 rank data
7490 10:01:32.935347 u2DelayCellTimex100 = 290/100 ps
7491 10:01:32.938697 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7492 10:01:32.945150 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7493 10:01:32.948475 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7494 10:01:32.951977 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7495 10:01:32.955184 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7496 10:01:32.958467 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7497 10:01:32.958541
7498 10:01:32.961773 CA PerBit enable=1, Macro0, CA PI delay=35
7499 10:01:32.961877
7500 10:01:32.965154 [CBTSetCACLKResult] CA Dly = 35
7501 10:01:32.965231 CS Dly: 9 (0~40)
7502 10:01:32.971606 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7503 10:01:32.975241 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7504 10:01:32.975323 ==
7505 10:01:32.978982 Dram Type= 6, Freq= 0, CH_0, rank 1
7506 10:01:32.981511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 10:01:32.981596 ==
7508 10:01:32.988323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 10:01:32.992020 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 10:01:32.998619 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 10:01:33.001716 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 10:01:33.011961 [CA 0] Center 43 (13~73) winsize 61
7513 10:01:33.014986 [CA 1] Center 43 (13~73) winsize 61
7514 10:01:33.018599 [CA 2] Center 37 (8~67) winsize 60
7515 10:01:33.021585 [CA 3] Center 38 (8~68) winsize 61
7516 10:01:33.025023 [CA 4] Center 36 (6~66) winsize 61
7517 10:01:33.028689 [CA 5] Center 36 (6~66) winsize 61
7518 10:01:33.028842
7519 10:01:33.031929 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 10:01:33.032051
7521 10:01:33.034740 [CATrainingPosCal] consider 2 rank data
7522 10:01:33.038308 u2DelayCellTimex100 = 290/100 ps
7523 10:01:33.041527 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7524 10:01:33.048407 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7525 10:01:33.051606 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7526 10:01:33.054808 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7527 10:01:33.058298 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7528 10:01:33.061641 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7529 10:01:33.061752
7530 10:01:33.065019 CA PerBit enable=1, Macro0, CA PI delay=35
7531 10:01:33.065118
7532 10:01:33.068455 [CBTSetCACLKResult] CA Dly = 35
7533 10:01:33.071493 CS Dly: 10 (0~43)
7534 10:01:33.074861 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 10:01:33.078046 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 10:01:33.078129
7537 10:01:33.081353 ----->DramcWriteLeveling(PI) begin...
7538 10:01:33.081437 ==
7539 10:01:33.084696 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 10:01:33.088155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 10:01:33.091329 ==
7542 10:01:33.091412 Write leveling (Byte 0): 35 => 35
7543 10:01:33.094991 Write leveling (Byte 1): 29 => 29
7544 10:01:33.098032 DramcWriteLeveling(PI) end<-----
7545 10:01:33.098114
7546 10:01:33.098178 ==
7547 10:01:33.101620 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 10:01:33.108283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 10:01:33.108369 ==
7550 10:01:33.111414 [Gating] SW mode calibration
7551 10:01:33.117987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7552 10:01:33.121699 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7553 10:01:33.128215 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 10:01:33.131451 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 10:01:33.134713 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7556 10:01:33.137968 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7557 10:01:33.144572 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7558 10:01:33.148063 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7559 10:01:33.151483 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 10:01:33.157945 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 10:01:33.161491 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 10:01:33.164454 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 10:01:33.171539 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
7564 10:01:33.174899 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7565 10:01:33.178045 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7566 10:01:33.184474 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7567 10:01:33.187976 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 10:01:33.191205 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 10:01:33.198115 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 10:01:33.201240 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7571 10:01:33.204786 1 6 8 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
7572 10:01:33.211236 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7573 10:01:33.214465 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7574 10:01:33.217840 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 10:01:33.224577 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 10:01:33.227716 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 10:01:33.231360 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 10:01:33.237895 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 10:01:33.241199 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7580 10:01:33.244389 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7581 10:01:33.251562 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7582 10:01:33.254436 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7583 10:01:33.257842 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 10:01:33.261160 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 10:01:33.267685 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 10:01:33.271154 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 10:01:33.274493 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 10:01:33.281200 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 10:01:33.284376 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 10:01:33.287467 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 10:01:33.294684 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 10:01:33.297528 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 10:01:33.301161 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 10:01:33.307716 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 10:01:33.311170 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7596 10:01:33.314464 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7597 10:01:33.321211 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 10:01:33.321297 Total UI for P1: 0, mck2ui 16
7599 10:01:33.327696 best dqsien dly found for B0: ( 1, 9, 10)
7600 10:01:33.330953 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7601 10:01:33.334174 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 10:01:33.337748 Total UI for P1: 0, mck2ui 16
7603 10:01:33.340884 best dqsien dly found for B1: ( 1, 9, 18)
7604 10:01:33.344469 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7605 10:01:33.347786 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7606 10:01:33.347914
7607 10:01:33.354204 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7608 10:01:33.357522 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7609 10:01:33.357634 [Gating] SW calibration Done
7610 10:01:33.361029 ==
7611 10:01:33.363913 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 10:01:33.367595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 10:01:33.367677 ==
7614 10:01:33.367741 RX Vref Scan: 0
7615 10:01:33.367801
7616 10:01:33.370549 RX Vref 0 -> 0, step: 1
7617 10:01:33.370653
7618 10:01:33.374140 RX Delay 0 -> 252, step: 8
7619 10:01:33.377621 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7620 10:01:33.380720 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7621 10:01:33.384107 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7622 10:01:33.390727 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7623 10:01:33.393874 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7624 10:01:33.397334 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7625 10:01:33.400826 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7626 10:01:33.403974 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7627 10:01:33.407323 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7628 10:01:33.414079 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7629 10:01:33.417262 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7630 10:01:33.420747 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7631 10:01:33.424312 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7632 10:01:33.430991 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7633 10:01:33.434098 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7634 10:01:33.437235 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7635 10:01:33.437341 ==
7636 10:01:33.440784 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 10:01:33.443951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 10:01:33.444032 ==
7639 10:01:33.447237 DQS Delay:
7640 10:01:33.447309 DQS0 = 0, DQS1 = 0
7641 10:01:33.447371 DQM Delay:
7642 10:01:33.450757 DQM0 = 137, DQM1 = 127
7643 10:01:33.450828 DQ Delay:
7644 10:01:33.454004 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7645 10:01:33.457462 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7646 10:01:33.464267 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7647 10:01:33.467269 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7648 10:01:33.467354
7649 10:01:33.467420
7650 10:01:33.467494 ==
7651 10:01:33.470703 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 10:01:33.473832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 10:01:33.473915 ==
7654 10:01:33.473979
7655 10:01:33.474040
7656 10:01:33.477446 TX Vref Scan disable
7657 10:01:33.477528 == TX Byte 0 ==
7658 10:01:33.484134 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7659 10:01:33.487373 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7660 10:01:33.487455 == TX Byte 1 ==
7661 10:01:33.494302 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7662 10:01:33.497574 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7663 10:01:33.497657 ==
7664 10:01:33.500548 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 10:01:33.504151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 10:01:33.504238 ==
7667 10:01:33.518549
7668 10:01:33.521698 TX Vref early break, caculate TX vref
7669 10:01:33.525239 TX Vref=16, minBit 12, minWin=22, winSum=377
7670 10:01:33.528576 TX Vref=18, minBit 6, minWin=23, winSum=385
7671 10:01:33.531813 TX Vref=20, minBit 5, minWin=24, winSum=403
7672 10:01:33.535244 TX Vref=22, minBit 6, minWin=24, winSum=407
7673 10:01:33.538595 TX Vref=24, minBit 5, minWin=25, winSum=414
7674 10:01:33.545317 TX Vref=26, minBit 5, minWin=25, winSum=424
7675 10:01:33.548527 TX Vref=28, minBit 0, minWin=25, winSum=428
7676 10:01:33.552278 TX Vref=30, minBit 0, minWin=26, winSum=428
7677 10:01:33.555432 TX Vref=32, minBit 1, minWin=25, winSum=410
7678 10:01:33.558295 TX Vref=34, minBit 8, minWin=24, winSum=401
7679 10:01:33.564987 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
7680 10:01:33.565070
7681 10:01:33.568424 Final TX Range 0 Vref 30
7682 10:01:33.568561
7683 10:01:33.568626 ==
7684 10:01:33.571590 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 10:01:33.575129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 10:01:33.575211 ==
7687 10:01:33.575274
7688 10:01:33.575333
7689 10:01:33.578542 TX Vref Scan disable
7690 10:01:33.585262 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7691 10:01:33.585344 == TX Byte 0 ==
7692 10:01:33.588245 u2DelayCellOfst[0]=13 cells (4 PI)
7693 10:01:33.591810 u2DelayCellOfst[1]=16 cells (5 PI)
7694 10:01:33.595115 u2DelayCellOfst[2]=10 cells (3 PI)
7695 10:01:33.598135 u2DelayCellOfst[3]=10 cells (3 PI)
7696 10:01:33.601797 u2DelayCellOfst[4]=6 cells (2 PI)
7697 10:01:33.604823 u2DelayCellOfst[5]=0 cells (0 PI)
7698 10:01:33.608574 u2DelayCellOfst[6]=16 cells (5 PI)
7699 10:01:33.608657 u2DelayCellOfst[7]=16 cells (5 PI)
7700 10:01:33.615147 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7701 10:01:33.618198 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7702 10:01:33.618281 == TX Byte 1 ==
7703 10:01:33.621611 u2DelayCellOfst[8]=0 cells (0 PI)
7704 10:01:33.624804 u2DelayCellOfst[9]=0 cells (0 PI)
7705 10:01:33.628036 u2DelayCellOfst[10]=6 cells (2 PI)
7706 10:01:33.631765 u2DelayCellOfst[11]=3 cells (1 PI)
7707 10:01:33.634972 u2DelayCellOfst[12]=13 cells (4 PI)
7708 10:01:33.638101 u2DelayCellOfst[13]=10 cells (3 PI)
7709 10:01:33.641392 u2DelayCellOfst[14]=16 cells (5 PI)
7710 10:01:33.644693 u2DelayCellOfst[15]=10 cells (3 PI)
7711 10:01:33.648302 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7712 10:01:33.654753 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7713 10:01:33.654855 DramC Write-DBI on
7714 10:01:33.654945 ==
7715 10:01:33.658327 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 10:01:33.661562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 10:01:33.661659 ==
7718 10:01:33.664682
7719 10:01:33.664819
7720 10:01:33.664883 TX Vref Scan disable
7721 10:01:33.668161 == TX Byte 0 ==
7722 10:01:33.671690 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7723 10:01:33.674620 == TX Byte 1 ==
7724 10:01:33.678231 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7725 10:01:33.678363 DramC Write-DBI off
7726 10:01:33.678453
7727 10:01:33.681275 [DATLAT]
7728 10:01:33.681357 Freq=1600, CH0 RK0
7729 10:01:33.681422
7730 10:01:33.684741 DATLAT Default: 0xf
7731 10:01:33.684846 0, 0xFFFF, sum = 0
7732 10:01:33.688044 1, 0xFFFF, sum = 0
7733 10:01:33.688127 2, 0xFFFF, sum = 0
7734 10:01:33.691205 3, 0xFFFF, sum = 0
7735 10:01:33.691304 4, 0xFFFF, sum = 0
7736 10:01:33.694697 5, 0xFFFF, sum = 0
7737 10:01:33.697847 6, 0xFFFF, sum = 0
7738 10:01:33.697931 7, 0xFFFF, sum = 0
7739 10:01:33.701416 8, 0xFFFF, sum = 0
7740 10:01:33.701535 9, 0xFFFF, sum = 0
7741 10:01:33.704519 10, 0xFFFF, sum = 0
7742 10:01:33.704643 11, 0xFFFF, sum = 0
7743 10:01:33.707950 12, 0xFFFF, sum = 0
7744 10:01:33.708078 13, 0xFFFF, sum = 0
7745 10:01:33.711464 14, 0x0, sum = 1
7746 10:01:33.711547 15, 0x0, sum = 2
7747 10:01:33.714954 16, 0x0, sum = 3
7748 10:01:33.715031 17, 0x0, sum = 4
7749 10:01:33.717986 best_step = 15
7750 10:01:33.718090
7751 10:01:33.718180 ==
7752 10:01:33.721209 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 10:01:33.724436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 10:01:33.724525 ==
7755 10:01:33.724601 RX Vref Scan: 1
7756 10:01:33.728112
7757 10:01:33.728208 Set Vref Range= 24 -> 127
7758 10:01:33.728304
7759 10:01:33.731070 RX Vref 24 -> 127, step: 1
7760 10:01:33.731168
7761 10:01:33.734552 RX Delay 19 -> 252, step: 4
7762 10:01:33.734648
7763 10:01:33.737663 Set Vref, RX VrefLevel [Byte0]: 24
7764 10:01:33.741202 [Byte1]: 24
7765 10:01:33.741321
7766 10:01:33.744243 Set Vref, RX VrefLevel [Byte0]: 25
7767 10:01:33.747906 [Byte1]: 25
7768 10:01:33.748041
7769 10:01:33.751018 Set Vref, RX VrefLevel [Byte0]: 26
7770 10:01:33.754425 [Byte1]: 26
7771 10:01:33.758052
7772 10:01:33.758134 Set Vref, RX VrefLevel [Byte0]: 27
7773 10:01:33.761606 [Byte1]: 27
7774 10:01:33.765876
7775 10:01:33.765958 Set Vref, RX VrefLevel [Byte0]: 28
7776 10:01:33.768946 [Byte1]: 28
7777 10:01:33.773146
7778 10:01:33.773260 Set Vref, RX VrefLevel [Byte0]: 29
7779 10:01:33.776454 [Byte1]: 29
7780 10:01:33.781023
7781 10:01:33.781100 Set Vref, RX VrefLevel [Byte0]: 30
7782 10:01:33.784185 [Byte1]: 30
7783 10:01:33.788441
7784 10:01:33.788515 Set Vref, RX VrefLevel [Byte0]: 31
7785 10:01:33.791656 [Byte1]: 31
7786 10:01:33.795942
7787 10:01:33.796058 Set Vref, RX VrefLevel [Byte0]: 32
7788 10:01:33.799430 [Byte1]: 32
7789 10:01:33.803660
7790 10:01:33.803790 Set Vref, RX VrefLevel [Byte0]: 33
7791 10:01:33.807101 [Byte1]: 33
7792 10:01:33.811135
7793 10:01:33.811213 Set Vref, RX VrefLevel [Byte0]: 34
7794 10:01:33.814723 [Byte1]: 34
7795 10:01:33.818723
7796 10:01:33.818807 Set Vref, RX VrefLevel [Byte0]: 35
7797 10:01:33.822388 [Byte1]: 35
7798 10:01:33.826296
7799 10:01:33.826381 Set Vref, RX VrefLevel [Byte0]: 36
7800 10:01:33.829802 [Byte1]: 36
7801 10:01:33.833905
7802 10:01:33.833981 Set Vref, RX VrefLevel [Byte0]: 37
7803 10:01:33.837433 [Byte1]: 37
7804 10:01:33.841391
7805 10:01:33.841475 Set Vref, RX VrefLevel [Byte0]: 38
7806 10:01:33.845077 [Byte1]: 38
7807 10:01:33.849154
7808 10:01:33.849282 Set Vref, RX VrefLevel [Byte0]: 39
7809 10:01:33.852650 [Byte1]: 39
7810 10:01:33.856476
7811 10:01:33.856603 Set Vref, RX VrefLevel [Byte0]: 40
7812 10:01:33.859732 [Byte1]: 40
7813 10:01:33.864015
7814 10:01:33.864136 Set Vref, RX VrefLevel [Byte0]: 41
7815 10:01:33.867477 [Byte1]: 41
7816 10:01:33.871619
7817 10:01:33.871726 Set Vref, RX VrefLevel [Byte0]: 42
7818 10:01:33.875138 [Byte1]: 42
7819 10:01:33.879203
7820 10:01:33.879290 Set Vref, RX VrefLevel [Byte0]: 43
7821 10:01:33.882640 [Byte1]: 43
7822 10:01:33.886801
7823 10:01:33.886930 Set Vref, RX VrefLevel [Byte0]: 44
7824 10:01:33.890484 [Byte1]: 44
7825 10:01:33.894734
7826 10:01:33.894859 Set Vref, RX VrefLevel [Byte0]: 45
7827 10:01:33.897797 [Byte1]: 45
7828 10:01:33.902034
7829 10:01:33.902159 Set Vref, RX VrefLevel [Byte0]: 46
7830 10:01:33.905524 [Byte1]: 46
7831 10:01:33.909639
7832 10:01:33.909717 Set Vref, RX VrefLevel [Byte0]: 47
7833 10:01:33.912959 [Byte1]: 47
7834 10:01:33.917342
7835 10:01:33.917429 Set Vref, RX VrefLevel [Byte0]: 48
7836 10:01:33.920594 [Byte1]: 48
7837 10:01:33.924872
7838 10:01:33.924978 Set Vref, RX VrefLevel [Byte0]: 49
7839 10:01:33.927919 [Byte1]: 49
7840 10:01:33.932498
7841 10:01:33.932585 Set Vref, RX VrefLevel [Byte0]: 50
7842 10:01:33.935465 [Byte1]: 50
7843 10:01:33.939846
7844 10:01:33.939969 Set Vref, RX VrefLevel [Byte0]: 51
7845 10:01:33.943464 [Byte1]: 51
7846 10:01:33.947232
7847 10:01:33.947316 Set Vref, RX VrefLevel [Byte0]: 52
7848 10:01:33.950942 [Byte1]: 52
7849 10:01:33.954888
7850 10:01:33.954978 Set Vref, RX VrefLevel [Byte0]: 53
7851 10:01:33.958403 [Byte1]: 53
7852 10:01:33.962743
7853 10:01:33.962826 Set Vref, RX VrefLevel [Byte0]: 54
7854 10:01:33.966141 [Byte1]: 54
7855 10:01:33.970124
7856 10:01:33.970208 Set Vref, RX VrefLevel [Byte0]: 55
7857 10:01:33.973659 [Byte1]: 55
7858 10:01:33.977661
7859 10:01:33.977744 Set Vref, RX VrefLevel [Byte0]: 56
7860 10:01:33.980894 [Byte1]: 56
7861 10:01:33.985141
7862 10:01:33.985224 Set Vref, RX VrefLevel [Byte0]: 57
7863 10:01:33.988565 [Byte1]: 57
7864 10:01:33.993002
7865 10:01:33.996154 Set Vref, RX VrefLevel [Byte0]: 58
7866 10:01:33.996242 [Byte1]: 58
7867 10:01:34.000469
7868 10:01:34.000552 Set Vref, RX VrefLevel [Byte0]: 59
7869 10:01:34.004016 [Byte1]: 59
7870 10:01:34.008048
7871 10:01:34.008161 Set Vref, RX VrefLevel [Byte0]: 60
7872 10:01:34.011270 [Byte1]: 60
7873 10:01:34.015639
7874 10:01:34.015725 Set Vref, RX VrefLevel [Byte0]: 61
7875 10:01:34.018958 [Byte1]: 61
7876 10:01:34.023320
7877 10:01:34.023428 Set Vref, RX VrefLevel [Byte0]: 62
7878 10:01:34.026502 [Byte1]: 62
7879 10:01:34.030832
7880 10:01:34.030919 Set Vref, RX VrefLevel [Byte0]: 63
7881 10:01:34.034273 [Byte1]: 63
7882 10:01:34.038283
7883 10:01:34.038363 Set Vref, RX VrefLevel [Byte0]: 64
7884 10:01:34.041418 [Byte1]: 64
7885 10:01:34.046315
7886 10:01:34.046400 Set Vref, RX VrefLevel [Byte0]: 65
7887 10:01:34.049228 [Byte1]: 65
7888 10:01:34.053710
7889 10:01:34.053796 Set Vref, RX VrefLevel [Byte0]: 66
7890 10:01:34.056993 [Byte1]: 66
7891 10:01:34.061224
7892 10:01:34.061310 Set Vref, RX VrefLevel [Byte0]: 67
7893 10:01:34.064299 [Byte1]: 67
7894 10:01:34.068757
7895 10:01:34.068845 Set Vref, RX VrefLevel [Byte0]: 68
7896 10:01:34.071922 [Byte1]: 68
7897 10:01:34.076053
7898 10:01:34.076138 Set Vref, RX VrefLevel [Byte0]: 69
7899 10:01:34.079481 [Byte1]: 69
7900 10:01:34.083854
7901 10:01:34.083938 Set Vref, RX VrefLevel [Byte0]: 70
7902 10:01:34.087006 [Byte1]: 70
7903 10:01:34.091195
7904 10:01:34.091278 Set Vref, RX VrefLevel [Byte0]: 71
7905 10:01:34.094691 [Byte1]: 71
7906 10:01:34.098887
7907 10:01:34.098984 Set Vref, RX VrefLevel [Byte0]: 72
7908 10:01:34.102210 [Byte1]: 72
7909 10:01:34.106327
7910 10:01:34.106410 Set Vref, RX VrefLevel [Byte0]: 73
7911 10:01:34.109588 [Byte1]: 73
7912 10:01:34.114198
7913 10:01:34.114280 Set Vref, RX VrefLevel [Byte0]: 74
7914 10:01:34.117275 [Byte1]: 74
7915 10:01:34.121570
7916 10:01:34.121654 Set Vref, RX VrefLevel [Byte0]: 75
7917 10:01:34.124934 [Byte1]: 75
7918 10:01:34.129232
7919 10:01:34.129313 Set Vref, RX VrefLevel [Byte0]: 76
7920 10:01:34.132377 [Byte1]: 76
7921 10:01:34.137162
7922 10:01:34.137282 Set Vref, RX VrefLevel [Byte0]: 77
7923 10:01:34.139990 [Byte1]: 77
7924 10:01:34.144262
7925 10:01:34.144344 Set Vref, RX VrefLevel [Byte0]: 78
7926 10:01:34.147872 [Byte1]: 78
7927 10:01:34.151722
7928 10:01:34.151837 Set Vref, RX VrefLevel [Byte0]: 79
7929 10:01:34.155294 [Byte1]: 79
7930 10:01:34.159416
7931 10:01:34.159523 Set Vref, RX VrefLevel [Byte0]: 80
7932 10:01:34.162648 [Byte1]: 80
7933 10:01:34.167087
7934 10:01:34.167192 Set Vref, RX VrefLevel [Byte0]: 81
7935 10:01:34.170333 [Byte1]: 81
7936 10:01:34.174862
7937 10:01:34.174943 Final RX Vref Byte 0 = 62 to rank0
7938 10:01:34.177788 Final RX Vref Byte 1 = 61 to rank0
7939 10:01:34.181299 Final RX Vref Byte 0 = 62 to rank1
7940 10:01:34.184669 Final RX Vref Byte 1 = 61 to rank1==
7941 10:01:34.188198 Dram Type= 6, Freq= 0, CH_0, rank 0
7942 10:01:34.194518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7943 10:01:34.194601 ==
7944 10:01:34.194665 DQS Delay:
7945 10:01:34.197988 DQS0 = 0, DQS1 = 0
7946 10:01:34.198069 DQM Delay:
7947 10:01:34.198133 DQM0 = 136, DQM1 = 124
7948 10:01:34.201273 DQ Delay:
7949 10:01:34.204460 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7950 10:01:34.207591 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
7951 10:01:34.210852 DQ8 =116, DQ9 =114, DQ10 =126, DQ11 =118
7952 10:01:34.214503 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =134
7953 10:01:34.214601
7954 10:01:34.214695
7955 10:01:34.214768
7956 10:01:34.218021 [DramC_TX_OE_Calibration] TA2
7957 10:01:34.221184 Original DQ_B0 (3 6) =30, OEN = 27
7958 10:01:34.224416 Original DQ_B1 (3 6) =30, OEN = 27
7959 10:01:34.227983 24, 0x0, End_B0=24 End_B1=24
7960 10:01:34.228068 25, 0x0, End_B0=25 End_B1=25
7961 10:01:34.231078 26, 0x0, End_B0=26 End_B1=26
7962 10:01:34.234533 27, 0x0, End_B0=27 End_B1=27
7963 10:01:34.237669 28, 0x0, End_B0=28 End_B1=28
7964 10:01:34.237753 29, 0x0, End_B0=29 End_B1=29
7965 10:01:34.241458 30, 0x0, End_B0=30 End_B1=30
7966 10:01:34.244797 31, 0x4141, End_B0=30 End_B1=30
7967 10:01:34.247664 Byte0 end_step=30 best_step=27
7968 10:01:34.251657 Byte1 end_step=30 best_step=27
7969 10:01:34.254712 Byte0 TX OE(2T, 0.5T) = (3, 3)
7970 10:01:34.254802 Byte1 TX OE(2T, 0.5T) = (3, 3)
7971 10:01:34.257662
7972 10:01:34.257760
7973 10:01:34.264312 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7974 10:01:34.267552 CH0 RK0: MR19=303, MR18=1D1B
7975 10:01:34.274524 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7976 10:01:34.274620
7977 10:01:34.277987 ----->DramcWriteLeveling(PI) begin...
7978 10:01:34.278086 ==
7979 10:01:34.280989 Dram Type= 6, Freq= 0, CH_0, rank 1
7980 10:01:34.284300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7981 10:01:34.284398 ==
7982 10:01:34.287705 Write leveling (Byte 0): 36 => 36
7983 10:01:34.291122 Write leveling (Byte 1): 27 => 27
7984 10:01:34.294287 DramcWriteLeveling(PI) end<-----
7985 10:01:34.294369
7986 10:01:34.294433 ==
7987 10:01:34.297427 Dram Type= 6, Freq= 0, CH_0, rank 1
7988 10:01:34.301241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7989 10:01:34.301325 ==
7990 10:01:34.304201 [Gating] SW mode calibration
7991 10:01:34.310989 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7992 10:01:34.317559 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7993 10:01:34.321019 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 10:01:34.324444 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 10:01:34.331098 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7996 10:01:34.334244 1 4 12 | B1->B0 | 2525 3131 | 1 1 | (1 1) (1 1)
7997 10:01:34.337453 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 10:01:34.344114 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 10:01:34.347559 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 10:01:34.351011 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 10:01:34.357351 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 10:01:34.360994 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 10:01:34.364106 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 10:01:34.370730 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
8005 10:01:34.374311 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8006 10:01:34.377776 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 10:01:34.383987 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 10:01:34.387489 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 10:01:34.390713 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 10:01:34.397582 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 10:01:34.400967 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8012 10:01:34.404277 1 6 12 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
8013 10:01:34.407587 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 10:01:34.414232 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 10:01:34.417612 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 10:01:34.421066 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 10:01:34.427632 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 10:01:34.430822 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 10:01:34.434116 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 10:01:34.440833 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 10:01:34.444195 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8022 10:01:34.447168 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 10:01:34.454233 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 10:01:34.457375 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 10:01:34.460614 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 10:01:34.467223 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 10:01:34.470962 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 10:01:34.474379 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 10:01:34.481095 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 10:01:34.483883 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 10:01:34.487426 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 10:01:34.493964 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 10:01:34.497535 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 10:01:34.500648 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 10:01:34.507257 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 10:01:34.510680 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8037 10:01:34.513886 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8038 10:01:34.517390 Total UI for P1: 0, mck2ui 16
8039 10:01:34.520529 best dqsien dly found for B0: ( 1, 9, 12)
8040 10:01:34.523742 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 10:01:34.527291 Total UI for P1: 0, mck2ui 16
8042 10:01:34.530466 best dqsien dly found for B1: ( 1, 9, 14)
8043 10:01:34.534002 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8044 10:01:34.540905 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8045 10:01:34.540988
8046 10:01:34.543812 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8047 10:01:34.546775 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8048 10:01:34.550431 [Gating] SW calibration Done
8049 10:01:34.550539 ==
8050 10:01:34.553586 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 10:01:34.557111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 10:01:34.557193 ==
8053 10:01:34.560340 RX Vref Scan: 0
8054 10:01:34.560421
8055 10:01:34.560485 RX Vref 0 -> 0, step: 1
8056 10:01:34.560543
8057 10:01:34.563811 RX Delay 0 -> 252, step: 8
8058 10:01:34.567246 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8059 10:01:34.570473 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8060 10:01:34.577031 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8061 10:01:34.580619 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8062 10:01:34.583761 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8063 10:01:34.586874 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8064 10:01:34.590498 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8065 10:01:34.597240 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8066 10:01:34.600297 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8067 10:01:34.603808 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8068 10:01:34.606946 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8069 10:01:34.610216 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8070 10:01:34.617368 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8071 10:01:34.620682 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8072 10:01:34.623879 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8073 10:01:34.626988 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8074 10:01:34.627071 ==
8075 10:01:34.630358 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 10:01:34.636738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 10:01:34.636858 ==
8078 10:01:34.636923 DQS Delay:
8079 10:01:34.640264 DQS0 = 0, DQS1 = 0
8080 10:01:34.640349 DQM Delay:
8081 10:01:34.640414 DQM0 = 135, DQM1 = 126
8082 10:01:34.643370 DQ Delay:
8083 10:01:34.647152 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8084 10:01:34.650148 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8085 10:01:34.653588 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
8086 10:01:34.656819 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8087 10:01:34.656902
8088 10:01:34.656966
8089 10:01:34.657025 ==
8090 10:01:34.660199 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 10:01:34.663356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 10:01:34.667008 ==
8093 10:01:34.667109
8094 10:01:34.667207
8095 10:01:34.667298 TX Vref Scan disable
8096 10:01:34.670002 == TX Byte 0 ==
8097 10:01:34.673553 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8098 10:01:34.676740 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8099 10:01:34.680209 == TX Byte 1 ==
8100 10:01:34.683226 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8101 10:01:34.687137 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8102 10:01:34.689910 ==
8103 10:01:34.689984 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 10:01:34.696604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 10:01:34.696687 ==
8106 10:01:34.710991
8107 10:01:34.714195 TX Vref early break, caculate TX vref
8108 10:01:34.717649 TX Vref=16, minBit 8, minWin=22, winSum=386
8109 10:01:34.720859 TX Vref=18, minBit 0, minWin=24, winSum=396
8110 10:01:34.724409 TX Vref=20, minBit 0, minWin=25, winSum=406
8111 10:01:34.727421 TX Vref=22, minBit 0, minWin=25, winSum=409
8112 10:01:34.731015 TX Vref=24, minBit 1, minWin=25, winSum=417
8113 10:01:34.737673 TX Vref=26, minBit 4, minWin=25, winSum=423
8114 10:01:34.740699 TX Vref=28, minBit 0, minWin=26, winSum=425
8115 10:01:34.744286 TX Vref=30, minBit 0, minWin=26, winSum=425
8116 10:01:34.747587 TX Vref=32, minBit 1, minWin=25, winSum=415
8117 10:01:34.750748 TX Vref=34, minBit 0, minWin=25, winSum=409
8118 10:01:34.754268 TX Vref=36, minBit 2, minWin=23, winSum=398
8119 10:01:34.760796 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8120 10:01:34.760883
8121 10:01:34.764038 Final TX Range 0 Vref 28
8122 10:01:34.764122
8123 10:01:34.764205 ==
8124 10:01:34.767478 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 10:01:34.770749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 10:01:34.770834 ==
8127 10:01:34.770918
8128 10:01:34.770997
8129 10:01:34.774259 TX Vref Scan disable
8130 10:01:34.781389 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8131 10:01:34.781474 == TX Byte 0 ==
8132 10:01:34.784382 u2DelayCellOfst[0]=13 cells (4 PI)
8133 10:01:34.787690 u2DelayCellOfst[1]=20 cells (6 PI)
8134 10:01:34.791028 u2DelayCellOfst[2]=13 cells (4 PI)
8135 10:01:34.794236 u2DelayCellOfst[3]=13 cells (4 PI)
8136 10:01:34.797802 u2DelayCellOfst[4]=13 cells (4 PI)
8137 10:01:34.800905 u2DelayCellOfst[5]=0 cells (0 PI)
8138 10:01:34.803956 u2DelayCellOfst[6]=20 cells (6 PI)
8139 10:01:34.807304 u2DelayCellOfst[7]=16 cells (5 PI)
8140 10:01:34.810888 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8141 10:01:34.813904 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8142 10:01:34.817361 == TX Byte 1 ==
8143 10:01:34.820652 u2DelayCellOfst[8]=0 cells (0 PI)
8144 10:01:34.820795 u2DelayCellOfst[9]=0 cells (0 PI)
8145 10:01:34.824227 u2DelayCellOfst[10]=6 cells (2 PI)
8146 10:01:34.827157 u2DelayCellOfst[11]=3 cells (1 PI)
8147 10:01:34.830529 u2DelayCellOfst[12]=13 cells (4 PI)
8148 10:01:34.834171 u2DelayCellOfst[13]=10 cells (3 PI)
8149 10:01:34.837062 u2DelayCellOfst[14]=13 cells (4 PI)
8150 10:01:34.840491 u2DelayCellOfst[15]=10 cells (3 PI)
8151 10:01:34.844014 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8152 10:01:34.850420 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8153 10:01:34.850541 DramC Write-DBI on
8154 10:01:34.850634 ==
8155 10:01:34.853836 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 10:01:34.860516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 10:01:34.860626 ==
8158 10:01:34.860718
8159 10:01:34.860845
8160 10:01:34.860906 TX Vref Scan disable
8161 10:01:34.864624 == TX Byte 0 ==
8162 10:01:34.867828 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8163 10:01:34.871380 == TX Byte 1 ==
8164 10:01:34.874301 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8165 10:01:34.877751 DramC Write-DBI off
8166 10:01:34.877867
8167 10:01:34.877930 [DATLAT]
8168 10:01:34.877989 Freq=1600, CH0 RK1
8169 10:01:34.878046
8170 10:01:34.881021 DATLAT Default: 0xf
8171 10:01:34.881089 0, 0xFFFF, sum = 0
8172 10:01:34.884451 1, 0xFFFF, sum = 0
8173 10:01:34.884527 2, 0xFFFF, sum = 0
8174 10:01:34.887871 3, 0xFFFF, sum = 0
8175 10:01:34.891299 4, 0xFFFF, sum = 0
8176 10:01:34.891379 5, 0xFFFF, sum = 0
8177 10:01:34.894287 6, 0xFFFF, sum = 0
8178 10:01:34.894361 7, 0xFFFF, sum = 0
8179 10:01:34.897852 8, 0xFFFF, sum = 0
8180 10:01:34.897933 9, 0xFFFF, sum = 0
8181 10:01:34.901324 10, 0xFFFF, sum = 0
8182 10:01:34.901396 11, 0xFFFF, sum = 0
8183 10:01:34.904353 12, 0xFFFF, sum = 0
8184 10:01:34.904429 13, 0xFFFF, sum = 0
8185 10:01:34.907884 14, 0x0, sum = 1
8186 10:01:34.907964 15, 0x0, sum = 2
8187 10:01:34.911342 16, 0x0, sum = 3
8188 10:01:34.911441 17, 0x0, sum = 4
8189 10:01:34.914235 best_step = 15
8190 10:01:34.914303
8191 10:01:34.914362 ==
8192 10:01:34.917922 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 10:01:34.921311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 10:01:34.921384 ==
8195 10:01:34.921442 RX Vref Scan: 0
8196 10:01:34.924701
8197 10:01:34.924820 RX Vref 0 -> 0, step: 1
8198 10:01:34.924890
8199 10:01:34.927499 RX Delay 19 -> 252, step: 4
8200 10:01:34.931094 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8201 10:01:34.937659 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8202 10:01:34.941178 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8203 10:01:34.944521 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8204 10:01:34.947965 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8205 10:01:34.951202 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8206 10:01:34.954653 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8207 10:01:34.961119 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8208 10:01:34.964410 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8209 10:01:34.967725 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8210 10:01:34.971090 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8211 10:01:34.974393 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8212 10:01:34.981076 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8213 10:01:34.984653 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8214 10:01:34.987431 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8215 10:01:34.991139 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8216 10:01:34.991221 ==
8217 10:01:34.994101 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 10:01:35.001081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 10:01:35.001168 ==
8220 10:01:35.001234 DQS Delay:
8221 10:01:35.004302 DQS0 = 0, DQS1 = 0
8222 10:01:35.004410 DQM Delay:
8223 10:01:35.007475 DQM0 = 133, DQM1 = 123
8224 10:01:35.007584 DQ Delay:
8225 10:01:35.010851 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8226 10:01:35.014281 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8227 10:01:35.017561 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8228 10:01:35.020929 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8229 10:01:35.021012
8230 10:01:35.021077
8231 10:01:35.021137
8232 10:01:35.024436 [DramC_TX_OE_Calibration] TA2
8233 10:01:35.027386 Original DQ_B0 (3 6) =30, OEN = 27
8234 10:01:35.031122 Original DQ_B1 (3 6) =30, OEN = 27
8235 10:01:35.034261 24, 0x0, End_B0=24 End_B1=24
8236 10:01:35.034379 25, 0x0, End_B0=25 End_B1=25
8237 10:01:35.037898 26, 0x0, End_B0=26 End_B1=26
8238 10:01:35.040947 27, 0x0, End_B0=27 End_B1=27
8239 10:01:35.044030 28, 0x0, End_B0=28 End_B1=28
8240 10:01:35.047653 29, 0x0, End_B0=29 End_B1=29
8241 10:01:35.047755 30, 0x0, End_B0=30 End_B1=30
8242 10:01:35.051016 31, 0x4141, End_B0=30 End_B1=30
8243 10:01:35.054250 Byte0 end_step=30 best_step=27
8244 10:01:35.057342 Byte1 end_step=30 best_step=27
8245 10:01:35.060688 Byte0 TX OE(2T, 0.5T) = (3, 3)
8246 10:01:35.064256 Byte1 TX OE(2T, 0.5T) = (3, 3)
8247 10:01:35.064362
8248 10:01:35.064463
8249 10:01:35.070725 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8250 10:01:35.074406 CH0 RK1: MR19=303, MR18=200D
8251 10:01:35.081002 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8252 10:01:35.084283 [RxdqsGatingPostProcess] freq 1600
8253 10:01:35.087329 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8254 10:01:35.090522 best DQS0 dly(2T, 0.5T) = (1, 1)
8255 10:01:35.093920 best DQS1 dly(2T, 0.5T) = (1, 1)
8256 10:01:35.097252 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8257 10:01:35.100705 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8258 10:01:35.104168 best DQS0 dly(2T, 0.5T) = (1, 1)
8259 10:01:35.107236 best DQS1 dly(2T, 0.5T) = (1, 1)
8260 10:01:35.110550 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8261 10:01:35.114119 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8262 10:01:35.117280 Pre-setting of DQS Precalculation
8263 10:01:35.120701 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8264 10:01:35.120834 ==
8265 10:01:35.124202 Dram Type= 6, Freq= 0, CH_1, rank 0
8266 10:01:35.127178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 10:01:35.130600 ==
8268 10:01:35.134021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8269 10:01:35.137177 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8270 10:01:35.143859 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8271 10:01:35.147482 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8272 10:01:35.157709 [CA 0] Center 40 (11~70) winsize 60
8273 10:01:35.160673 [CA 1] Center 41 (11~71) winsize 61
8274 10:01:35.164117 [CA 2] Center 37 (8~67) winsize 60
8275 10:01:35.167333 [CA 3] Center 36 (7~66) winsize 60
8276 10:01:35.170843 [CA 4] Center 36 (7~66) winsize 60
8277 10:01:35.174360 [CA 5] Center 35 (5~66) winsize 62
8278 10:01:35.174473
8279 10:01:35.177242 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8280 10:01:35.177324
8281 10:01:35.180494 [CATrainingPosCal] consider 1 rank data
8282 10:01:35.184097 u2DelayCellTimex100 = 290/100 ps
8283 10:01:35.187251 CA0 delay=40 (11~70),Diff = 5 PI (16 cell)
8284 10:01:35.193942 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8285 10:01:35.197150 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
8286 10:01:35.200624 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8287 10:01:35.203922 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8288 10:01:35.207345 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
8289 10:01:35.207476
8290 10:01:35.210482 CA PerBit enable=1, Macro0, CA PI delay=35
8291 10:01:35.210604
8292 10:01:35.213792 [CBTSetCACLKResult] CA Dly = 35
8293 10:01:35.217391 CS Dly: 8 (0~39)
8294 10:01:35.220461 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8295 10:01:35.223885 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8296 10:01:35.223965 ==
8297 10:01:35.227090 Dram Type= 6, Freq= 0, CH_1, rank 1
8298 10:01:35.230486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 10:01:35.230566 ==
8300 10:01:35.237156 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8301 10:01:35.240458 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8302 10:01:35.247499 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8303 10:01:35.250626 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8304 10:01:35.260462 [CA 0] Center 41 (12~71) winsize 60
8305 10:01:35.264019 [CA 1] Center 41 (12~71) winsize 60
8306 10:01:35.267456 [CA 2] Center 38 (9~67) winsize 59
8307 10:01:35.270465 [CA 3] Center 37 (8~67) winsize 60
8308 10:01:35.274054 [CA 4] Center 37 (8~67) winsize 60
8309 10:01:35.276999 [CA 5] Center 37 (7~67) winsize 61
8310 10:01:35.277079
8311 10:01:35.280416 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8312 10:01:35.280495
8313 10:01:35.283634 [CATrainingPosCal] consider 2 rank data
8314 10:01:35.286872 u2DelayCellTimex100 = 290/100 ps
8315 10:01:35.290470 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8316 10:01:35.296942 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8317 10:01:35.300256 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8318 10:01:35.303730 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8319 10:01:35.306992 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 10:01:35.310246 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8321 10:01:35.310325
8322 10:01:35.313897 CA PerBit enable=1, Macro0, CA PI delay=36
8323 10:01:35.313976
8324 10:01:35.317100 [CBTSetCACLKResult] CA Dly = 36
8325 10:01:35.320143 CS Dly: 9 (0~41)
8326 10:01:35.323677 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8327 10:01:35.327031 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8328 10:01:35.327110
8329 10:01:35.330233 ----->DramcWriteLeveling(PI) begin...
8330 10:01:35.330314 ==
8331 10:01:35.333692 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 10:01:35.336849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 10:01:35.340229 ==
8334 10:01:35.340335 Write leveling (Byte 0): 24 => 24
8335 10:01:35.343446 Write leveling (Byte 1): 28 => 28
8336 10:01:35.347036 DramcWriteLeveling(PI) end<-----
8337 10:01:35.347115
8338 10:01:35.347177 ==
8339 10:01:35.350164 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 10:01:35.356867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 10:01:35.356946 ==
8342 10:01:35.357008 [Gating] SW mode calibration
8343 10:01:35.366854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8344 10:01:35.370125 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8345 10:01:35.376544 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 10:01:35.380057 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 10:01:35.383289 1 4 8 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
8348 10:01:35.389913 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 10:01:35.393513 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 10:01:35.396639 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 10:01:35.400027 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 10:01:35.406896 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 10:01:35.410033 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 10:01:35.413379 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8355 10:01:35.419902 1 5 8 | B1->B0 | 2d2d 2828 | 0 1 | (0 0) (1 0)
8356 10:01:35.423468 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8357 10:01:35.426634 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 10:01:35.433373 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 10:01:35.436499 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 10:01:35.439923 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 10:01:35.446647 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 10:01:35.449864 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8363 10:01:35.453453 1 6 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8364 10:01:35.459681 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 10:01:35.463231 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 10:01:35.466798 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 10:01:35.473194 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 10:01:35.476666 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 10:01:35.480069 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 10:01:35.486479 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8371 10:01:35.489933 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8372 10:01:35.493004 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8373 10:01:35.499887 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8374 10:01:35.502917 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 10:01:35.506333 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 10:01:35.512979 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 10:01:35.516492 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 10:01:35.519617 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 10:01:35.523132 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 10:01:35.529540 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 10:01:35.533114 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 10:01:35.536469 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 10:01:35.542981 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 10:01:35.546104 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 10:01:35.549386 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 10:01:35.555970 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8387 10:01:35.559551 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8388 10:01:35.562596 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8389 10:01:35.566278 Total UI for P1: 0, mck2ui 16
8390 10:01:35.569286 best dqsien dly found for B0: ( 1, 9, 6)
8391 10:01:35.576308 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8392 10:01:35.579305 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 10:01:35.582649 Total UI for P1: 0, mck2ui 16
8394 10:01:35.586211 best dqsien dly found for B1: ( 1, 9, 12)
8395 10:01:35.589119 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8396 10:01:35.592737 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8397 10:01:35.592842
8398 10:01:35.595899 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8399 10:01:35.599243 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8400 10:01:35.602436 [Gating] SW calibration Done
8401 10:01:35.602511 ==
8402 10:01:35.605947 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 10:01:35.612705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 10:01:35.612830 ==
8405 10:01:35.612921 RX Vref Scan: 0
8406 10:01:35.612995
8407 10:01:35.615874 RX Vref 0 -> 0, step: 1
8408 10:01:35.615967
8409 10:01:35.618893 RX Delay 0 -> 252, step: 8
8410 10:01:35.622306 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8411 10:01:35.625621 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8412 10:01:35.629233 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8413 10:01:35.632565 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8414 10:01:35.635904 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8415 10:01:35.642261 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8416 10:01:35.645725 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8417 10:01:35.648867 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8418 10:01:35.652299 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8419 10:01:35.655435 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8420 10:01:35.662416 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8421 10:01:35.665526 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8422 10:01:35.669151 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8423 10:01:35.672177 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8424 10:01:35.675738 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8425 10:01:35.682289 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8426 10:01:35.682373 ==
8427 10:01:35.685807 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 10:01:35.689471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 10:01:35.689554 ==
8430 10:01:35.689618 DQS Delay:
8431 10:01:35.692235 DQS0 = 0, DQS1 = 0
8432 10:01:35.692317 DQM Delay:
8433 10:01:35.695552 DQM0 = 138, DQM1 = 130
8434 10:01:35.695634 DQ Delay:
8435 10:01:35.699143 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8436 10:01:35.702495 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8437 10:01:35.705681 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8438 10:01:35.708959 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8439 10:01:35.709041
8440 10:01:35.712195
8441 10:01:35.712276 ==
8442 10:01:35.715910 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 10:01:35.718722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 10:01:35.718806 ==
8445 10:01:35.718871
8446 10:01:35.718931
8447 10:01:35.722289 TX Vref Scan disable
8448 10:01:35.722372 == TX Byte 0 ==
8449 10:01:35.728957 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8450 10:01:35.732211 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8451 10:01:35.732297 == TX Byte 1 ==
8452 10:01:35.739173 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8453 10:01:35.742428 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8454 10:01:35.742526 ==
8455 10:01:35.745449 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 10:01:35.748560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 10:01:35.748644 ==
8458 10:01:35.761901
8459 10:01:35.765222 TX Vref early break, caculate TX vref
8460 10:01:35.768706 TX Vref=16, minBit 15, minWin=21, winSum=372
8461 10:01:35.771812 TX Vref=18, minBit 12, minWin=22, winSum=376
8462 10:01:35.775052 TX Vref=20, minBit 8, minWin=23, winSum=392
8463 10:01:35.778933 TX Vref=22, minBit 10, minWin=23, winSum=397
8464 10:01:35.781808 TX Vref=24, minBit 10, minWin=24, winSum=408
8465 10:01:35.788512 TX Vref=26, minBit 10, minWin=24, winSum=417
8466 10:01:35.791926 TX Vref=28, minBit 10, minWin=25, winSum=419
8467 10:01:35.795228 TX Vref=30, minBit 9, minWin=24, winSum=414
8468 10:01:35.798474 TX Vref=32, minBit 9, minWin=23, winSum=406
8469 10:01:35.801977 TX Vref=34, minBit 12, minWin=23, winSum=396
8470 10:01:35.808783 [TxChooseVref] Worse bit 10, Min win 25, Win sum 419, Final Vref 28
8471 10:01:35.808911
8472 10:01:35.812037 Final TX Range 0 Vref 28
8473 10:01:35.812119
8474 10:01:35.812184 ==
8475 10:01:35.815244 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 10:01:35.818317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 10:01:35.818400 ==
8478 10:01:35.818466
8479 10:01:35.818526
8480 10:01:35.821732 TX Vref Scan disable
8481 10:01:35.828932 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8482 10:01:35.829016 == TX Byte 0 ==
8483 10:01:35.832066 u2DelayCellOfst[0]=16 cells (5 PI)
8484 10:01:35.835154 u2DelayCellOfst[1]=10 cells (3 PI)
8485 10:01:35.838555 u2DelayCellOfst[2]=0 cells (0 PI)
8486 10:01:35.841821 u2DelayCellOfst[3]=6 cells (2 PI)
8487 10:01:35.845268 u2DelayCellOfst[4]=6 cells (2 PI)
8488 10:01:35.848277 u2DelayCellOfst[5]=16 cells (5 PI)
8489 10:01:35.851785 u2DelayCellOfst[6]=16 cells (5 PI)
8490 10:01:35.855138 u2DelayCellOfst[7]=3 cells (1 PI)
8491 10:01:35.858513 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8492 10:01:35.861740 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8493 10:01:35.865275 == TX Byte 1 ==
8494 10:01:35.868430 u2DelayCellOfst[8]=0 cells (0 PI)
8495 10:01:35.868521 u2DelayCellOfst[9]=3 cells (1 PI)
8496 10:01:35.871937 u2DelayCellOfst[10]=13 cells (4 PI)
8497 10:01:35.875095 u2DelayCellOfst[11]=3 cells (1 PI)
8498 10:01:35.878516 u2DelayCellOfst[12]=16 cells (5 PI)
8499 10:01:35.881862 u2DelayCellOfst[13]=20 cells (6 PI)
8500 10:01:35.885020 u2DelayCellOfst[14]=20 cells (6 PI)
8501 10:01:35.888568 u2DelayCellOfst[15]=16 cells (5 PI)
8502 10:01:35.891776 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8503 10:01:35.898362 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8504 10:01:35.898445 DramC Write-DBI on
8505 10:01:35.898514 ==
8506 10:01:35.901494 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 10:01:35.908070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 10:01:35.908200 ==
8509 10:01:35.908310
8510 10:01:35.908417
8511 10:01:35.908529 TX Vref Scan disable
8512 10:01:35.912045 == TX Byte 0 ==
8513 10:01:35.915115 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8514 10:01:35.918540 == TX Byte 1 ==
8515 10:01:35.921751 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8516 10:01:35.925071 DramC Write-DBI off
8517 10:01:35.925192
8518 10:01:35.925304 [DATLAT]
8519 10:01:35.925413 Freq=1600, CH1 RK0
8520 10:01:35.925521
8521 10:01:35.928689 DATLAT Default: 0xf
8522 10:01:35.928842 0, 0xFFFF, sum = 0
8523 10:01:35.931791 1, 0xFFFF, sum = 0
8524 10:01:35.935165 2, 0xFFFF, sum = 0
8525 10:01:35.935289 3, 0xFFFF, sum = 0
8526 10:01:35.938289 4, 0xFFFF, sum = 0
8527 10:01:35.938411 5, 0xFFFF, sum = 0
8528 10:01:35.941755 6, 0xFFFF, sum = 0
8529 10:01:35.941874 7, 0xFFFF, sum = 0
8530 10:01:35.945264 8, 0xFFFF, sum = 0
8531 10:01:35.945387 9, 0xFFFF, sum = 0
8532 10:01:35.948277 10, 0xFFFF, sum = 0
8533 10:01:35.948398 11, 0xFFFF, sum = 0
8534 10:01:35.951764 12, 0xFFFF, sum = 0
8535 10:01:35.951886 13, 0xFFFF, sum = 0
8536 10:01:35.955278 14, 0x0, sum = 1
8537 10:01:35.955402 15, 0x0, sum = 2
8538 10:01:35.958622 16, 0x0, sum = 3
8539 10:01:35.958746 17, 0x0, sum = 4
8540 10:01:35.961616 best_step = 15
8541 10:01:35.961738
8542 10:01:35.961844 ==
8543 10:01:35.964848 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 10:01:35.968149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 10:01:35.968270 ==
8546 10:01:35.968384 RX Vref Scan: 1
8547 10:01:35.971921
8548 10:01:35.972038 Set Vref Range= 24 -> 127
8549 10:01:35.972150
8550 10:01:35.974814 RX Vref 24 -> 127, step: 1
8551 10:01:35.974932
8552 10:01:35.978160 RX Delay 19 -> 252, step: 4
8553 10:01:35.978282
8554 10:01:35.981720 Set Vref, RX VrefLevel [Byte0]: 24
8555 10:01:35.984825 [Byte1]: 24
8556 10:01:35.984906
8557 10:01:35.988070 Set Vref, RX VrefLevel [Byte0]: 25
8558 10:01:35.991469 [Byte1]: 25
8559 10:01:35.991551
8560 10:01:35.995007 Set Vref, RX VrefLevel [Byte0]: 26
8561 10:01:35.998060 [Byte1]: 26
8562 10:01:36.002267
8563 10:01:36.002348 Set Vref, RX VrefLevel [Byte0]: 27
8564 10:01:36.005467 [Byte1]: 27
8565 10:01:36.009696
8566 10:01:36.009777 Set Vref, RX VrefLevel [Byte0]: 28
8567 10:01:36.012877 [Byte1]: 28
8568 10:01:36.017101
8569 10:01:36.017182 Set Vref, RX VrefLevel [Byte0]: 29
8570 10:01:36.020627 [Byte1]: 29
8571 10:01:36.024806
8572 10:01:36.024887 Set Vref, RX VrefLevel [Byte0]: 30
8573 10:01:36.028398 [Byte1]: 30
8574 10:01:36.032518
8575 10:01:36.032600 Set Vref, RX VrefLevel [Byte0]: 31
8576 10:01:36.035588 [Byte1]: 31
8577 10:01:36.040166
8578 10:01:36.040247 Set Vref, RX VrefLevel [Byte0]: 32
8579 10:01:36.043230 [Byte1]: 32
8580 10:01:36.047548
8581 10:01:36.047629 Set Vref, RX VrefLevel [Byte0]: 33
8582 10:01:36.050884 [Byte1]: 33
8583 10:01:36.055312
8584 10:01:36.055408 Set Vref, RX VrefLevel [Byte0]: 34
8585 10:01:36.058281 [Byte1]: 34
8586 10:01:36.062781
8587 10:01:36.062925 Set Vref, RX VrefLevel [Byte0]: 35
8588 10:01:36.066035 [Byte1]: 35
8589 10:01:36.070565
8590 10:01:36.070647 Set Vref, RX VrefLevel [Byte0]: 36
8591 10:01:36.073432 [Byte1]: 36
8592 10:01:36.077745
8593 10:01:36.077826 Set Vref, RX VrefLevel [Byte0]: 37
8594 10:01:36.081366 [Byte1]: 37
8595 10:01:36.085611
8596 10:01:36.085693 Set Vref, RX VrefLevel [Byte0]: 38
8597 10:01:36.088882 [Byte1]: 38
8598 10:01:36.093027
8599 10:01:36.093224 Set Vref, RX VrefLevel [Byte0]: 39
8600 10:01:36.096078 [Byte1]: 39
8601 10:01:36.100767
8602 10:01:36.100854 Set Vref, RX VrefLevel [Byte0]: 40
8603 10:01:36.104106 [Byte1]: 40
8604 10:01:36.108242
8605 10:01:36.111178 Set Vref, RX VrefLevel [Byte0]: 41
8606 10:01:36.114830 [Byte1]: 41
8607 10:01:36.114906
8608 10:01:36.117824 Set Vref, RX VrefLevel [Byte0]: 42
8609 10:01:36.121399 [Byte1]: 42
8610 10:01:36.121483
8611 10:01:36.124586 Set Vref, RX VrefLevel [Byte0]: 43
8612 10:01:36.128123 [Byte1]: 43
8613 10:01:36.128221
8614 10:01:36.131438 Set Vref, RX VrefLevel [Byte0]: 44
8615 10:01:36.134530 [Byte1]: 44
8616 10:01:36.138507
8617 10:01:36.138591 Set Vref, RX VrefLevel [Byte0]: 45
8618 10:01:36.141676 [Byte1]: 45
8619 10:01:36.146103
8620 10:01:36.146173 Set Vref, RX VrefLevel [Byte0]: 46
8621 10:01:36.149134 [Byte1]: 46
8622 10:01:36.153665
8623 10:01:36.153736 Set Vref, RX VrefLevel [Byte0]: 47
8624 10:01:36.156899 [Byte1]: 47
8625 10:01:36.160893
8626 10:01:36.160963 Set Vref, RX VrefLevel [Byte0]: 48
8627 10:01:36.164326 [Byte1]: 48
8628 10:01:36.169046
8629 10:01:36.169148 Set Vref, RX VrefLevel [Byte0]: 49
8630 10:01:36.172024 [Byte1]: 49
8631 10:01:36.176214
8632 10:01:36.176297 Set Vref, RX VrefLevel [Byte0]: 50
8633 10:01:36.179920 [Byte1]: 50
8634 10:01:36.184172
8635 10:01:36.184274 Set Vref, RX VrefLevel [Byte0]: 51
8636 10:01:36.187083 [Byte1]: 51
8637 10:01:36.191631
8638 10:01:36.191702 Set Vref, RX VrefLevel [Byte0]: 52
8639 10:01:36.194599 [Byte1]: 52
8640 10:01:36.199130
8641 10:01:36.199227 Set Vref, RX VrefLevel [Byte0]: 53
8642 10:01:36.202137 [Byte1]: 53
8643 10:01:36.206396
8644 10:01:36.206497 Set Vref, RX VrefLevel [Byte0]: 54
8645 10:01:36.209862 [Byte1]: 54
8646 10:01:36.214067
8647 10:01:36.214171 Set Vref, RX VrefLevel [Byte0]: 55
8648 10:01:36.217713 [Byte1]: 55
8649 10:01:36.221961
8650 10:01:36.222059 Set Vref, RX VrefLevel [Byte0]: 56
8651 10:01:36.225132 [Byte1]: 56
8652 10:01:36.229169
8653 10:01:36.229265 Set Vref, RX VrefLevel [Byte0]: 57
8654 10:01:36.232649 [Byte1]: 57
8655 10:01:36.236673
8656 10:01:36.236812 Set Vref, RX VrefLevel [Byte0]: 58
8657 10:01:36.240327 [Byte1]: 58
8658 10:01:36.244263
8659 10:01:36.244334 Set Vref, RX VrefLevel [Byte0]: 59
8660 10:01:36.247790 [Byte1]: 59
8661 10:01:36.252167
8662 10:01:36.252266 Set Vref, RX VrefLevel [Byte0]: 60
8663 10:01:36.255484 [Byte1]: 60
8664 10:01:36.259614
8665 10:01:36.259718 Set Vref, RX VrefLevel [Byte0]: 61
8666 10:01:36.262963 [Byte1]: 61
8667 10:01:36.267301
8668 10:01:36.267397 Set Vref, RX VrefLevel [Byte0]: 62
8669 10:01:36.270375 [Byte1]: 62
8670 10:01:36.274709
8671 10:01:36.274806 Set Vref, RX VrefLevel [Byte0]: 63
8672 10:01:36.278201 [Byte1]: 63
8673 10:01:36.282670
8674 10:01:36.282748 Set Vref, RX VrefLevel [Byte0]: 64
8675 10:01:36.285673 [Byte1]: 64
8676 10:01:36.289876
8677 10:01:36.289973 Set Vref, RX VrefLevel [Byte0]: 65
8678 10:01:36.293188 [Byte1]: 65
8679 10:01:36.297301
8680 10:01:36.297374 Set Vref, RX VrefLevel [Byte0]: 66
8681 10:01:36.300683 [Byte1]: 66
8682 10:01:36.304886
8683 10:01:36.304957 Set Vref, RX VrefLevel [Byte0]: 67
8684 10:01:36.308350 [Byte1]: 67
8685 10:01:36.312526
8686 10:01:36.312627 Set Vref, RX VrefLevel [Byte0]: 68
8687 10:01:36.315969 [Byte1]: 68
8688 10:01:36.320213
8689 10:01:36.320308 Set Vref, RX VrefLevel [Byte0]: 69
8690 10:01:36.323649 [Byte1]: 69
8691 10:01:36.327814
8692 10:01:36.327913 Set Vref, RX VrefLevel [Byte0]: 70
8693 10:01:36.331062 [Byte1]: 70
8694 10:01:36.335291
8695 10:01:36.335363 Set Vref, RX VrefLevel [Byte0]: 71
8696 10:01:36.338753 [Byte1]: 71
8697 10:01:36.343105
8698 10:01:36.343187 Set Vref, RX VrefLevel [Byte0]: 72
8699 10:01:36.346264 [Byte1]: 72
8700 10:01:36.350336
8701 10:01:36.350488 Set Vref, RX VrefLevel [Byte0]: 73
8702 10:01:36.353931 [Byte1]: 73
8703 10:01:36.357987
8704 10:01:36.358070 Set Vref, RX VrefLevel [Byte0]: 74
8705 10:01:36.361165 [Byte1]: 74
8706 10:01:36.365509
8707 10:01:36.365592 Set Vref, RX VrefLevel [Byte0]: 75
8708 10:01:36.368648 [Byte1]: 75
8709 10:01:36.373191
8710 10:01:36.373272 Final RX Vref Byte 0 = 59 to rank0
8711 10:01:36.376378 Final RX Vref Byte 1 = 62 to rank0
8712 10:01:36.379785 Final RX Vref Byte 0 = 59 to rank1
8713 10:01:36.383572 Final RX Vref Byte 1 = 62 to rank1==
8714 10:01:36.386502 Dram Type= 6, Freq= 0, CH_1, rank 0
8715 10:01:36.393153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 10:01:36.393236 ==
8717 10:01:36.393303 DQS Delay:
8718 10:01:36.393363 DQS0 = 0, DQS1 = 0
8719 10:01:36.396293 DQM Delay:
8720 10:01:36.396378 DQM0 = 134, DQM1 = 129
8721 10:01:36.399782 DQ Delay:
8722 10:01:36.403004 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8723 10:01:36.406339 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =132
8724 10:01:36.409765 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8725 10:01:36.412690 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8726 10:01:36.412828
8727 10:01:36.412893
8728 10:01:36.412953
8729 10:01:36.416434 [DramC_TX_OE_Calibration] TA2
8730 10:01:36.419901 Original DQ_B0 (3 6) =30, OEN = 27
8731 10:01:36.422806 Original DQ_B1 (3 6) =30, OEN = 27
8732 10:01:36.426601 24, 0x0, End_B0=24 End_B1=24
8733 10:01:36.426685 25, 0x0, End_B0=25 End_B1=25
8734 10:01:36.429740 26, 0x0, End_B0=26 End_B1=26
8735 10:01:36.433172 27, 0x0, End_B0=27 End_B1=27
8736 10:01:36.436368 28, 0x0, End_B0=28 End_B1=28
8737 10:01:36.436456 29, 0x0, End_B0=29 End_B1=29
8738 10:01:36.439843 30, 0x0, End_B0=30 End_B1=30
8739 10:01:36.442944 31, 0x4141, End_B0=30 End_B1=30
8740 10:01:36.446623 Byte0 end_step=30 best_step=27
8741 10:01:36.449880 Byte1 end_step=30 best_step=27
8742 10:01:36.452961 Byte0 TX OE(2T, 0.5T) = (3, 3)
8743 10:01:36.453076 Byte1 TX OE(2T, 0.5T) = (3, 3)
8744 10:01:36.456460
8745 10:01:36.456557
8746 10:01:36.462950 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8747 10:01:36.466609 CH1 RK0: MR19=303, MR18=1A28
8748 10:01:36.472715 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8749 10:01:36.472824
8750 10:01:36.476116 ----->DramcWriteLeveling(PI) begin...
8751 10:01:36.476233 ==
8752 10:01:36.479608 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 10:01:36.482631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 10:01:36.482744 ==
8755 10:01:36.486212 Write leveling (Byte 0): 23 => 23
8756 10:01:36.489692 Write leveling (Byte 1): 30 => 30
8757 10:01:36.493184 DramcWriteLeveling(PI) end<-----
8758 10:01:36.493270
8759 10:01:36.493354 ==
8760 10:01:36.496217 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 10:01:36.499879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 10:01:36.499965 ==
8763 10:01:36.502849 [Gating] SW mode calibration
8764 10:01:36.509579 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8765 10:01:36.516294 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8766 10:01:36.519220 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 10:01:36.522797 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 10:01:36.529555 1 4 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8769 10:01:36.532635 1 4 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8770 10:01:36.536172 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 10:01:36.542759 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 10:01:36.545938 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 10:01:36.549510 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 10:01:36.555935 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 10:01:36.559346 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 10:01:36.562915 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)
8777 10:01:36.569562 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8778 10:01:36.573006 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 10:01:36.576175 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 10:01:36.582909 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 10:01:36.585947 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 10:01:36.589602 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 10:01:36.592711 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8784 10:01:36.599596 1 6 8 | B1->B0 | 4444 2727 | 0 0 | (0 0) (0 0)
8785 10:01:36.602901 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8786 10:01:36.606327 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 10:01:36.612567 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 10:01:36.616184 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 10:01:36.619412 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 10:01:36.625944 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 10:01:36.629478 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 10:01:36.632616 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8793 10:01:36.639331 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8794 10:01:36.642655 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8795 10:01:36.646022 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 10:01:36.652697 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 10:01:36.655801 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 10:01:36.658960 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 10:01:36.665677 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 10:01:36.669321 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 10:01:36.672602 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 10:01:36.679129 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 10:01:36.682392 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 10:01:36.686034 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 10:01:36.692490 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 10:01:36.695931 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 10:01:36.698934 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 10:01:36.705943 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8809 10:01:36.709203 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8810 10:01:36.712580 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 10:01:36.715636 Total UI for P1: 0, mck2ui 16
8812 10:01:36.719086 best dqsien dly found for B0: ( 1, 9, 10)
8813 10:01:36.722249 Total UI for P1: 0, mck2ui 16
8814 10:01:36.725955 best dqsien dly found for B1: ( 1, 9, 10)
8815 10:01:36.728916 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8816 10:01:36.732042 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8817 10:01:36.732164
8818 10:01:36.735516 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8819 10:01:36.742289 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8820 10:01:36.742374 [Gating] SW calibration Done
8821 10:01:36.742440 ==
8822 10:01:36.745653 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 10:01:36.752475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 10:01:36.752558 ==
8825 10:01:36.752622 RX Vref Scan: 0
8826 10:01:36.752682
8827 10:01:36.755659 RX Vref 0 -> 0, step: 1
8828 10:01:36.755741
8829 10:01:36.759207 RX Delay 0 -> 252, step: 8
8830 10:01:36.762235 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8831 10:01:36.765843 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8832 10:01:36.768936 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8833 10:01:36.772127 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8834 10:01:36.779066 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8835 10:01:36.782223 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8836 10:01:36.785395 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8837 10:01:36.789034 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8838 10:01:36.792014 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8839 10:01:36.799117 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8840 10:01:36.802311 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8841 10:01:36.805426 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8842 10:01:36.809092 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8843 10:01:36.812162 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8844 10:01:36.818975 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8845 10:01:36.822223 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8846 10:01:36.822306 ==
8847 10:01:36.825572 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 10:01:36.828652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 10:01:36.828734 ==
8850 10:01:36.832120 DQS Delay:
8851 10:01:36.832205 DQS0 = 0, DQS1 = 0
8852 10:01:36.832270 DQM Delay:
8853 10:01:36.835245 DQM0 = 137, DQM1 = 133
8854 10:01:36.835327 DQ Delay:
8855 10:01:36.838708 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8856 10:01:36.841990 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8857 10:01:36.845317 DQ8 =115, DQ9 =123, DQ10 =135, DQ11 =127
8858 10:01:36.851912 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8859 10:01:36.852018
8860 10:01:36.852121
8861 10:01:36.852210 ==
8862 10:01:36.855421 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 10:01:36.858656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 10:01:36.858766 ==
8865 10:01:36.858865
8866 10:01:36.858961
8867 10:01:36.862213 TX Vref Scan disable
8868 10:01:36.862309 == TX Byte 0 ==
8869 10:01:36.868972 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8870 10:01:36.871806 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8871 10:01:36.871913 == TX Byte 1 ==
8872 10:01:36.878487 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8873 10:01:36.881960 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8874 10:01:36.882034 ==
8875 10:01:36.885474 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 10:01:36.888639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 10:01:36.888741 ==
8878 10:01:36.904001
8879 10:01:36.907311 TX Vref early break, caculate TX vref
8880 10:01:36.910757 TX Vref=16, minBit 8, minWin=22, winSum=381
8881 10:01:36.914194 TX Vref=18, minBit 8, minWin=23, winSum=387
8882 10:01:36.917522 TX Vref=20, minBit 8, minWin=23, winSum=395
8883 10:01:36.921259 TX Vref=22, minBit 9, minWin=24, winSum=406
8884 10:01:36.924564 TX Vref=24, minBit 8, minWin=24, winSum=412
8885 10:01:36.930665 TX Vref=26, minBit 8, minWin=24, winSum=417
8886 10:01:36.934169 TX Vref=28, minBit 9, minWin=25, winSum=419
8887 10:01:36.937302 TX Vref=30, minBit 15, minWin=24, winSum=408
8888 10:01:36.940881 TX Vref=32, minBit 10, minWin=23, winSum=403
8889 10:01:36.943782 TX Vref=34, minBit 10, minWin=23, winSum=398
8890 10:01:36.947178 TX Vref=36, minBit 8, minWin=22, winSum=389
8891 10:01:36.954139 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8892 10:01:36.954246
8893 10:01:36.957283 Final TX Range 0 Vref 28
8894 10:01:36.957385
8895 10:01:36.957474 ==
8896 10:01:36.960632 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 10:01:36.963837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 10:01:36.963937 ==
8899 10:01:36.967222
8900 10:01:36.967324
8901 10:01:36.967416 TX Vref Scan disable
8902 10:01:36.973743 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8903 10:01:36.973867 == TX Byte 0 ==
8904 10:01:36.977127 u2DelayCellOfst[0]=13 cells (4 PI)
8905 10:01:36.980720 u2DelayCellOfst[1]=10 cells (3 PI)
8906 10:01:36.983779 u2DelayCellOfst[2]=0 cells (0 PI)
8907 10:01:36.987280 u2DelayCellOfst[3]=3 cells (1 PI)
8908 10:01:36.990524 u2DelayCellOfst[4]=6 cells (2 PI)
8909 10:01:36.994047 u2DelayCellOfst[5]=16 cells (5 PI)
8910 10:01:36.997421 u2DelayCellOfst[6]=16 cells (5 PI)
8911 10:01:37.000699 u2DelayCellOfst[7]=3 cells (1 PI)
8912 10:01:37.004000 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8913 10:01:37.007202 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8914 10:01:37.010552 == TX Byte 1 ==
8915 10:01:37.014051 u2DelayCellOfst[8]=0 cells (0 PI)
8916 10:01:37.017132 u2DelayCellOfst[9]=3 cells (1 PI)
8917 10:01:37.017254 u2DelayCellOfst[10]=10 cells (3 PI)
8918 10:01:37.020656 u2DelayCellOfst[11]=3 cells (1 PI)
8919 10:01:37.023692 u2DelayCellOfst[12]=13 cells (4 PI)
8920 10:01:37.027451 u2DelayCellOfst[13]=16 cells (5 PI)
8921 10:01:37.030244 u2DelayCellOfst[14]=16 cells (5 PI)
8922 10:01:37.033911 u2DelayCellOfst[15]=16 cells (5 PI)
8923 10:01:37.040410 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8924 10:01:37.043814 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8925 10:01:37.043897 DramC Write-DBI on
8926 10:01:37.043962 ==
8927 10:01:37.047017 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 10:01:37.053530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 10:01:37.053655 ==
8930 10:01:37.053768
8931 10:01:37.053879
8932 10:01:37.053990 TX Vref Scan disable
8933 10:01:37.057789 == TX Byte 0 ==
8934 10:01:37.060816 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8935 10:01:37.064443 == TX Byte 1 ==
8936 10:01:37.067453 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8937 10:01:37.070959 DramC Write-DBI off
8938 10:01:37.071063
8939 10:01:37.071192 [DATLAT]
8940 10:01:37.071280 Freq=1600, CH1 RK1
8941 10:01:37.071366
8942 10:01:37.074321 DATLAT Default: 0xf
8943 10:01:37.074402 0, 0xFFFF, sum = 0
8944 10:01:37.077880 1, 0xFFFF, sum = 0
8945 10:01:37.077963 2, 0xFFFF, sum = 0
8946 10:01:37.081050 3, 0xFFFF, sum = 0
8947 10:01:37.084523 4, 0xFFFF, sum = 0
8948 10:01:37.084609 5, 0xFFFF, sum = 0
8949 10:01:37.087946 6, 0xFFFF, sum = 0
8950 10:01:37.088030 7, 0xFFFF, sum = 0
8951 10:01:37.091080 8, 0xFFFF, sum = 0
8952 10:01:37.091191 9, 0xFFFF, sum = 0
8953 10:01:37.094396 10, 0xFFFF, sum = 0
8954 10:01:37.094480 11, 0xFFFF, sum = 0
8955 10:01:37.097669 12, 0xFFFF, sum = 0
8956 10:01:37.097752 13, 0xFFFF, sum = 0
8957 10:01:37.101019 14, 0x0, sum = 1
8958 10:01:37.101102 15, 0x0, sum = 2
8959 10:01:37.104184 16, 0x0, sum = 3
8960 10:01:37.104267 17, 0x0, sum = 4
8961 10:01:37.107852 best_step = 15
8962 10:01:37.107934
8963 10:01:37.107997 ==
8964 10:01:37.110885 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 10:01:37.114108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 10:01:37.114190 ==
8967 10:01:37.114253 RX Vref Scan: 0
8968 10:01:37.117803
8969 10:01:37.117884 RX Vref 0 -> 0, step: 1
8970 10:01:37.117947
8971 10:01:37.120883 RX Delay 19 -> 252, step: 4
8972 10:01:37.124309 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8973 10:01:37.130894 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8974 10:01:37.134483 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8975 10:01:37.137503 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8976 10:01:37.140922 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8977 10:01:37.144013 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8978 10:01:37.147534 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8979 10:01:37.153855 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8980 10:01:37.157414 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8981 10:01:37.160548 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8982 10:01:37.164157 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8983 10:01:37.167084 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8984 10:01:37.174015 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8985 10:01:37.177484 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8986 10:01:37.180555 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8987 10:01:37.184121 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8988 10:01:37.184203 ==
8989 10:01:37.187143 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 10:01:37.193790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 10:01:37.193871 ==
8992 10:01:37.193934 DQS Delay:
8993 10:01:37.197314 DQS0 = 0, DQS1 = 0
8994 10:01:37.197395 DQM Delay:
8995 10:01:37.197459 DQM0 = 133, DQM1 = 130
8996 10:01:37.200574 DQ Delay:
8997 10:01:37.204106 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8998 10:01:37.207051 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8999 10:01:37.210552 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9000 10:01:37.214110 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
9001 10:01:37.214191
9002 10:01:37.214255
9003 10:01:37.214328
9004 10:01:37.217313 [DramC_TX_OE_Calibration] TA2
9005 10:01:37.220618 Original DQ_B0 (3 6) =30, OEN = 27
9006 10:01:37.223841 Original DQ_B1 (3 6) =30, OEN = 27
9007 10:01:37.227443 24, 0x0, End_B0=24 End_B1=24
9008 10:01:37.227526 25, 0x0, End_B0=25 End_B1=25
9009 10:01:37.230614 26, 0x0, End_B0=26 End_B1=26
9010 10:01:37.233721 27, 0x0, End_B0=27 End_B1=27
9011 10:01:37.237266 28, 0x0, End_B0=28 End_B1=28
9012 10:01:37.240511 29, 0x0, End_B0=29 End_B1=29
9013 10:01:37.240620 30, 0x0, End_B0=30 End_B1=30
9014 10:01:37.244005 31, 0x4141, End_B0=30 End_B1=30
9015 10:01:37.247066 Byte0 end_step=30 best_step=27
9016 10:01:37.250591 Byte1 end_step=30 best_step=27
9017 10:01:37.253924 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 10:01:37.257115 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 10:01:37.257196
9020 10:01:37.257259
9021 10:01:37.263482 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9022 10:01:37.267278 CH1 RK1: MR19=303, MR18=1A06
9023 10:01:37.273513 CH1_RK1: MR19=0x303, MR18=0x1A06, DQSOSC=396, MR23=63, INC=23, DEC=15
9024 10:01:37.276773 [RxdqsGatingPostProcess] freq 1600
9025 10:01:37.280230 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 10:01:37.283515 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 10:01:37.287026 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 10:01:37.290217 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 10:01:37.293779 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 10:01:37.296977 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 10:01:37.300546 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 10:01:37.303603 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 10:01:37.307160 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 10:01:37.310406 Pre-setting of DQS Precalculation
9035 10:01:37.313925 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 10:01:37.320677 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 10:01:37.327328 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 10:01:37.327426
9039 10:01:37.327505
9040 10:01:37.330525 [Calibration Summary] 3200 Mbps
9041 10:01:37.333549 CH 0, Rank 0
9042 10:01:37.333649 SW Impedance : PASS
9043 10:01:37.337184 DUTY Scan : NO K
9044 10:01:37.340256 ZQ Calibration : PASS
9045 10:01:37.340337 Jitter Meter : NO K
9046 10:01:37.343437 CBT Training : PASS
9047 10:01:37.346829 Write leveling : PASS
9048 10:01:37.346911 RX DQS gating : PASS
9049 10:01:37.350440 RX DQ/DQS(RDDQC) : PASS
9050 10:01:37.353848 TX DQ/DQS : PASS
9051 10:01:37.353978 RX DATLAT : PASS
9052 10:01:37.357366 RX DQ/DQS(Engine): PASS
9053 10:01:37.360443 TX OE : PASS
9054 10:01:37.360544 All Pass.
9055 10:01:37.360643
9056 10:01:37.360747 CH 0, Rank 1
9057 10:01:37.363572 SW Impedance : PASS
9058 10:01:37.366962 DUTY Scan : NO K
9059 10:01:37.367045 ZQ Calibration : PASS
9060 10:01:37.370207 Jitter Meter : NO K
9061 10:01:37.370321 CBT Training : PASS
9062 10:01:37.373540 Write leveling : PASS
9063 10:01:37.376654 RX DQS gating : PASS
9064 10:01:37.376761 RX DQ/DQS(RDDQC) : PASS
9065 10:01:37.380243 TX DQ/DQS : PASS
9066 10:01:37.383240 RX DATLAT : PASS
9067 10:01:37.383322 RX DQ/DQS(Engine): PASS
9068 10:01:37.386787 TX OE : PASS
9069 10:01:37.386877 All Pass.
9070 10:01:37.386960
9071 10:01:37.390205 CH 1, Rank 0
9072 10:01:37.390289 SW Impedance : PASS
9073 10:01:37.393222 DUTY Scan : NO K
9074 10:01:37.396514 ZQ Calibration : PASS
9075 10:01:37.396598 Jitter Meter : NO K
9076 10:01:37.400316 CBT Training : PASS
9077 10:01:37.403194 Write leveling : PASS
9078 10:01:37.403293 RX DQS gating : PASS
9079 10:01:37.406642 RX DQ/DQS(RDDQC) : PASS
9080 10:01:37.410019 TX DQ/DQS : PASS
9081 10:01:37.410102 RX DATLAT : PASS
9082 10:01:37.413778 RX DQ/DQS(Engine): PASS
9083 10:01:37.413861 TX OE : PASS
9084 10:01:37.416543 All Pass.
9085 10:01:37.416624
9086 10:01:37.416689 CH 1, Rank 1
9087 10:01:37.420031 SW Impedance : PASS
9088 10:01:37.420115 DUTY Scan : NO K
9089 10:01:37.423318 ZQ Calibration : PASS
9090 10:01:37.426847 Jitter Meter : NO K
9091 10:01:37.426994 CBT Training : PASS
9092 10:01:37.430154 Write leveling : PASS
9093 10:01:37.433524 RX DQS gating : PASS
9094 10:01:37.433607 RX DQ/DQS(RDDQC) : PASS
9095 10:01:37.436653 TX DQ/DQS : PASS
9096 10:01:37.439985 RX DATLAT : PASS
9097 10:01:37.440107 RX DQ/DQS(Engine): PASS
9098 10:01:37.443273 TX OE : PASS
9099 10:01:37.443369 All Pass.
9100 10:01:37.443436
9101 10:01:37.446590 DramC Write-DBI on
9102 10:01:37.450178 PER_BANK_REFRESH: Hybrid Mode
9103 10:01:37.450302 TX_TRACKING: ON
9104 10:01:37.460014 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 10:01:37.466308 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 10:01:37.473390 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 10:01:37.476560 [FAST_K] Save calibration result to emmc
9108 10:01:37.480114 sync common calibartion params.
9109 10:01:37.483426 sync cbt_mode0:1, 1:1
9110 10:01:37.486743 dram_init: ddr_geometry: 2
9111 10:01:37.486863 dram_init: ddr_geometry: 2
9112 10:01:37.489646 dram_init: ddr_geometry: 2
9113 10:01:37.493248 0:dram_rank_size:100000000
9114 10:01:37.496380 1:dram_rank_size:100000000
9115 10:01:37.499599 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 10:01:37.502910 DFS_SHUFFLE_HW_MODE: ON
9117 10:01:37.506423 dramc_set_vcore_voltage set vcore to 725000
9118 10:01:37.509832 Read voltage for 1600, 0
9119 10:01:37.509952 Vio18 = 0
9120 10:01:37.510064 Vcore = 725000
9121 10:01:37.513192 Vdram = 0
9122 10:01:37.513313 Vddq = 0
9123 10:01:37.513420 Vmddr = 0
9124 10:01:37.516250 switch to 3200 Mbps bootup
9125 10:01:37.519498 [DramcRunTimeConfig]
9126 10:01:37.519617 PHYPLL
9127 10:01:37.519726 DPM_CONTROL_AFTERK: ON
9128 10:01:37.522866 PER_BANK_REFRESH: ON
9129 10:01:37.526296 REFRESH_OVERHEAD_REDUCTION: ON
9130 10:01:37.526420 CMD_PICG_NEW_MODE: OFF
9131 10:01:37.529471 XRTWTW_NEW_MODE: ON
9132 10:01:37.529591 XRTRTR_NEW_MODE: ON
9133 10:01:37.532881 TX_TRACKING: ON
9134 10:01:37.533000 RDSEL_TRACKING: OFF
9135 10:01:37.536263 DQS Precalculation for DVFS: ON
9136 10:01:37.539363 RX_TRACKING: OFF
9137 10:01:37.539481 HW_GATING DBG: ON
9138 10:01:37.542711 ZQCS_ENABLE_LP4: ON
9139 10:01:37.542830 RX_PICG_NEW_MODE: ON
9140 10:01:37.546259 TX_PICG_NEW_MODE: ON
9141 10:01:37.549514 ENABLE_RX_DCM_DPHY: ON
9142 10:01:37.549630 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 10:01:37.552843 DUMMY_READ_FOR_TRACKING: OFF
9144 10:01:37.556611 !!! SPM_CONTROL_AFTERK: OFF
9145 10:01:37.559831 !!! SPM could not control APHY
9146 10:01:37.559950 IMPEDANCE_TRACKING: ON
9147 10:01:37.562711 TEMP_SENSOR: ON
9148 10:01:37.562829 HW_SAVE_FOR_SR: OFF
9149 10:01:37.566308 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 10:01:37.572740 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 10:01:37.572893 Read ODT Tracking: ON
9152 10:01:37.576915 Refresh Rate DeBounce: ON
9153 10:01:37.577036 DFS_NO_QUEUE_FLUSH: ON
9154 10:01:37.579440 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 10:01:37.582674 ENABLE_DFS_RUNTIME_MRW: OFF
9156 10:01:37.585896 DDR_RESERVE_NEW_MODE: ON
9157 10:01:37.586016 MR_CBT_SWITCH_FREQ: ON
9158 10:01:37.589076 =========================
9159 10:01:37.608677 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 10:01:37.612177 dram_init: ddr_geometry: 2
9161 10:01:37.630320 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 10:01:37.633416 dram_init: dram init end (result: 0)
9163 10:01:37.640328 DRAM-K: Full calibration passed in 24536 msecs
9164 10:01:37.643316 MRC: failed to locate region type 0.
9165 10:01:37.643408 DRAM rank0 size:0x100000000,
9166 10:01:37.646925 DRAM rank1 size=0x100000000
9167 10:01:37.656623 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 10:01:37.663536 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 10:01:37.669910 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 10:01:37.676669 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 10:01:37.679926 DRAM rank0 size:0x100000000,
9172 10:01:37.683336 DRAM rank1 size=0x100000000
9173 10:01:37.683458 CBMEM:
9174 10:01:37.686828 IMD: root @ 0xfffff000 254 entries.
9175 10:01:37.690193 IMD: root @ 0xffffec00 62 entries.
9176 10:01:37.693620 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 10:01:37.696613 WARNING: RO_VPD is uninitialized or empty.
9178 10:01:37.703248 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 10:01:37.710099 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 10:01:37.722987 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9181 10:01:37.734513 BS: romstage times (exec / console): total (unknown) / 24044 ms
9182 10:01:37.734597
9183 10:01:37.734661
9184 10:01:37.744190 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 10:01:37.747775 ARM64: Exception handlers installed.
9186 10:01:37.751091 ARM64: Testing exception
9187 10:01:37.754690 ARM64: Done test exception
9188 10:01:37.754773 Enumerating buses...
9189 10:01:37.757945 Show all devs... Before device enumeration.
9190 10:01:37.760857 Root Device: enabled 1
9191 10:01:37.764526 CPU_CLUSTER: 0: enabled 1
9192 10:01:37.764608 CPU: 00: enabled 1
9193 10:01:37.767891 Compare with tree...
9194 10:01:37.767973 Root Device: enabled 1
9195 10:01:37.770948 CPU_CLUSTER: 0: enabled 1
9196 10:01:37.774360 CPU: 00: enabled 1
9197 10:01:37.774442 Root Device scanning...
9198 10:01:37.777560 scan_static_bus for Root Device
9199 10:01:37.781140 CPU_CLUSTER: 0 enabled
9200 10:01:37.784200 scan_static_bus for Root Device done
9201 10:01:37.787440 scan_bus: bus Root Device finished in 8 msecs
9202 10:01:37.787520 done
9203 10:01:37.794276 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 10:01:37.797398 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 10:01:37.804155 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 10:01:37.807385 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 10:01:37.810704 Allocating resources...
9208 10:01:37.813861 Reading resources...
9209 10:01:37.817285 Root Device read_resources bus 0 link: 0
9210 10:01:37.817383 DRAM rank0 size:0x100000000,
9211 10:01:37.820845 DRAM rank1 size=0x100000000
9212 10:01:37.823897 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 10:01:37.827439 CPU: 00 missing read_resources
9214 10:01:37.831124 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 10:01:37.837228 Root Device read_resources bus 0 link: 0 done
9216 10:01:37.837311 Done reading resources.
9217 10:01:37.844191 Show resources in subtree (Root Device)...After reading.
9218 10:01:37.847242 Root Device child on link 0 CPU_CLUSTER: 0
9219 10:01:37.850388 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 10:01:37.860550 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 10:01:37.860648 CPU: 00
9222 10:01:37.864150 Root Device assign_resources, bus 0 link: 0
9223 10:01:37.867338 CPU_CLUSTER: 0 missing set_resources
9224 10:01:37.870630 Root Device assign_resources, bus 0 link: 0 done
9225 10:01:37.873703 Done setting resources.
9226 10:01:37.880268 Show resources in subtree (Root Device)...After assigning values.
9227 10:01:37.883924 Root Device child on link 0 CPU_CLUSTER: 0
9228 10:01:37.887218 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 10:01:37.897203 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 10:01:37.897287 CPU: 00
9231 10:01:37.900902 Done allocating resources.
9232 10:01:37.903552 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 10:01:37.907182 Enabling resources...
9234 10:01:37.907263 done.
9235 10:01:37.913742 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 10:01:37.913847 Initializing devices...
9237 10:01:37.917355 Root Device init
9238 10:01:37.917436 init hardware done!
9239 10:01:37.920099 0x00000018: ctrlr->caps
9240 10:01:37.923737 52.000 MHz: ctrlr->f_max
9241 10:01:37.923834 0.400 MHz: ctrlr->f_min
9242 10:01:37.926751 0x40ff8080: ctrlr->voltages
9243 10:01:37.926835 sclk: 390625
9244 10:01:37.930243 Bus Width = 1
9245 10:01:37.930324 sclk: 390625
9246 10:01:37.933388 Bus Width = 1
9247 10:01:37.933469 Early init status = 3
9248 10:01:37.940333 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 10:01:37.943438 in-header: 03 fc 00 00 01 00 00 00
9250 10:01:37.946692 in-data: 00
9251 10:01:37.950552 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 10:01:37.954429 in-header: 03 fd 00 00 00 00 00 00
9253 10:01:37.958041 in-data:
9254 10:01:37.961026 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 10:01:37.965788 in-header: 03 fc 00 00 01 00 00 00
9256 10:01:37.969172 in-data: 00
9257 10:01:37.972383 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 10:01:37.977820 in-header: 03 fd 00 00 00 00 00 00
9259 10:01:37.981313 in-data:
9260 10:01:37.984892 [SSUSB] Setting up USB HOST controller...
9261 10:01:37.988007 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 10:01:37.991512 [SSUSB] phy power-on done.
9263 10:01:37.994624 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 10:01:38.001433 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 10:01:38.004507 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 10:01:38.011213 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 10:01:38.017756 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9268 10:01:38.024655 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 10:01:38.031461 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 10:01:38.038158 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9271 10:01:38.041189 SPM: binary array size = 0x9dc
9272 10:01:38.044627 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 10:01:38.051030 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 10:01:38.057889 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 10:01:38.061359 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 10:01:38.064458 configure_display: Starting display init
9277 10:01:38.101060 anx7625_power_on_init: Init interface.
9278 10:01:38.104519 anx7625_disable_pd_protocol: Disabled PD feature.
9279 10:01:38.107593 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 10:01:38.135729 anx7625_start_dp_work: Secure OCM version=00
9281 10:01:38.138893 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 10:01:38.153713 sp_tx_get_edid_block: EDID Block = 1
9283 10:01:38.256479 Extracted contents:
9284 10:01:38.259455 header: 00 ff ff ff ff ff ff 00
9285 10:01:38.262790 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 10:01:38.266227 version: 01 04
9287 10:01:38.269420 basic params: 95 1f 11 78 0a
9288 10:01:38.273016 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 10:01:38.276556 established: 00 00 00
9290 10:01:38.282962 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 10:01:38.286165 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 10:01:38.292905 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 10:01:38.299657 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 10:01:38.306301 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 10:01:38.309483 extensions: 00
9296 10:01:38.309563 checksum: fb
9297 10:01:38.309627
9298 10:01:38.313014 Manufacturer: IVO Model 57d Serial Number 0
9299 10:01:38.316249 Made week 0 of 2020
9300 10:01:38.316329 EDID version: 1.4
9301 10:01:38.319554 Digital display
9302 10:01:38.322701 6 bits per primary color channel
9303 10:01:38.322798 DisplayPort interface
9304 10:01:38.326219 Maximum image size: 31 cm x 17 cm
9305 10:01:38.329528 Gamma: 220%
9306 10:01:38.329608 Check DPMS levels
9307 10:01:38.332792 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 10:01:38.335857 First detailed timing is preferred timing
9309 10:01:38.339519 Established timings supported:
9310 10:01:38.342881 Standard timings supported:
9311 10:01:38.342976 Detailed timings
9312 10:01:38.349463 Hex of detail: 383680a07038204018303c0035ae10000019
9313 10:01:38.352601 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 10:01:38.359556 0780 0798 07c8 0820 hborder 0
9315 10:01:38.362886 0438 043b 0447 0458 vborder 0
9316 10:01:38.362966 -hsync -vsync
9317 10:01:38.366260 Did detailed timing
9318 10:01:38.369586 Hex of detail: 000000000000000000000000000000000000
9319 10:01:38.372642 Manufacturer-specified data, tag 0
9320 10:01:38.379208 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 10:01:38.379288 ASCII string: InfoVision
9322 10:01:38.385872 Hex of detail: 000000fe00523134304e574635205248200a
9323 10:01:38.389036 ASCII string: R140NWF5 RH
9324 10:01:38.389109 Checksum
9325 10:01:38.389170 Checksum: 0xfb (valid)
9326 10:01:38.395890 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 10:01:38.399081 DSI data_rate: 832800000 bps
9328 10:01:38.402600 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 10:01:38.409232 anx7625_parse_edid: pixelclock(138800).
9330 10:01:38.412539 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 10:01:38.415730 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 10:01:38.419273 anx7625_dsi_config: config dsi.
9333 10:01:38.425636 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 10:01:38.438473 anx7625_dsi_config: success to config DSI
9335 10:01:38.441367 anx7625_dp_start: MIPI phy setup OK.
9336 10:01:38.445019 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 10:01:38.448241 mtk_ddp_mode_set invalid vrefresh 60
9338 10:01:38.451522 main_disp_path_setup
9339 10:01:38.451645 ovl_layer_smi_id_en
9340 10:01:38.454766 ovl_layer_smi_id_en
9341 10:01:38.454891 ccorr_config
9342 10:01:38.455001 aal_config
9343 10:01:38.458299 gamma_config
9344 10:01:38.458403 postmask_config
9345 10:01:38.461278 dither_config
9346 10:01:38.465161 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 10:01:38.471305 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 10:01:38.474842 Root Device init finished in 555 msecs
9349 10:01:38.477955 CPU_CLUSTER: 0 init
9350 10:01:38.484859 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 10:01:38.487862 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 10:01:38.491766 APU_MBOX 0x190000b0 = 0x10001
9353 10:01:38.494968 APU_MBOX 0x190001b0 = 0x10001
9354 10:01:38.497867 APU_MBOX 0x190005b0 = 0x10001
9355 10:01:38.501482 APU_MBOX 0x190006b0 = 0x10001
9356 10:01:38.504595 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 10:01:38.517238 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9358 10:01:38.529567 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 10:01:38.536142 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 10:01:38.548045 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9361 10:01:38.557178 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 10:01:38.560317 CPU_CLUSTER: 0 init finished in 81 msecs
9363 10:01:38.563832 Devices initialized
9364 10:01:38.566911 Show all devs... After init.
9365 10:01:38.567033 Root Device: enabled 1
9366 10:01:38.570304 CPU_CLUSTER: 0: enabled 1
9367 10:01:38.573821 CPU: 00: enabled 1
9368 10:01:38.576966 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9369 10:01:38.580330 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 10:01:38.583854 ELOG: NV offset 0x57f000 size 0x1000
9371 10:01:38.590490 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9372 10:01:38.597263 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 10:01:38.600330 ELOG: Event(17) added with size 13 at 2023-08-23 10:01:33 UTC
9374 10:01:38.603463 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 10:01:38.607532 in-header: 03 f9 00 00 2c 00 00 00
9376 10:01:38.620645 in-data: 66 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 10:01:38.627367 ELOG: Event(A1) added with size 10 at 2023-08-23 10:01:33 UTC
9378 10:01:38.634139 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9379 10:01:38.640872 ELOG: Event(A0) added with size 9 at 2023-08-23 10:01:33 UTC
9380 10:01:38.643901 elog_add_boot_reason: Logged dev mode boot
9381 10:01:38.647251 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9382 10:01:38.650935 Finalize devices...
9383 10:01:38.651017 Devices finalized
9384 10:01:38.657109 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 10:01:38.660665 Writing coreboot table at 0xffe64000
9386 10:01:38.663859 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 10:01:38.667034 1. 0000000040000000-00000000400fffff: RAM
9388 10:01:38.670579 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 10:01:38.677047 3. 000000004032b000-00000000545fffff: RAM
9390 10:01:38.680485 4. 0000000054600000-000000005465ffff: BL31
9391 10:01:38.683568 5. 0000000054660000-00000000ffe63fff: RAM
9392 10:01:38.687318 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 10:01:38.693638 7. 0000000100000000-000000023fffffff: RAM
9394 10:01:38.693759 Passing 5 GPIOs to payload:
9395 10:01:38.700596 NAME | PORT | POLARITY | VALUE
9396 10:01:38.703690 EC in RW | 0x000000aa | low | undefined
9397 10:01:38.710321 EC interrupt | 0x00000005 | low | undefined
9398 10:01:38.713758 TPM interrupt | 0x000000ab | high | undefined
9399 10:01:38.717234 SD card detect | 0x00000011 | high | undefined
9400 10:01:38.723880 speaker enable | 0x00000093 | high | undefined
9401 10:01:38.727428 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 10:01:38.730631 in-header: 03 f9 00 00 02 00 00 00
9403 10:01:38.730714 in-data: 02 00
9404 10:01:38.733861 ADC[4]: Raw value=900663 ID=7
9405 10:01:38.737579 ADC[3]: Raw value=213179 ID=1
9406 10:01:38.737662 RAM Code: 0x71
9407 10:01:38.740563 ADC[6]: Raw value=74502 ID=0
9408 10:01:38.743888 ADC[5]: Raw value=212441 ID=1
9409 10:01:38.743970 SKU Code: 0x1
9410 10:01:38.750518 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5be8
9411 10:01:38.753630 coreboot table: 964 bytes.
9412 10:01:38.757113 IMD ROOT 0. 0xfffff000 0x00001000
9413 10:01:38.760378 IMD SMALL 1. 0xffffe000 0x00001000
9414 10:01:38.763785 RO MCACHE 2. 0xffffc000 0x00001104
9415 10:01:38.767013 CONSOLE 3. 0xfff7c000 0x00080000
9416 10:01:38.770530 FMAP 4. 0xfff7b000 0x00000452
9417 10:01:38.773771 TIME STAMP 5. 0xfff7a000 0x00000910
9418 10:01:38.776944 VBOOT WORK 6. 0xfff66000 0x00014000
9419 10:01:38.780160 RAMOOPS 7. 0xffe66000 0x00100000
9420 10:01:38.783500 COREBOOT 8. 0xffe64000 0x00002000
9421 10:01:38.783610 IMD small region:
9422 10:01:38.786926 IMD ROOT 0. 0xffffec00 0x00000400
9423 10:01:38.790338 VPD 1. 0xffffeb80 0x0000006c
9424 10:01:38.793759 MMC STATUS 2. 0xffffeb60 0x00000004
9425 10:01:38.800481 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9426 10:01:38.800563 Probing TPM: done!
9427 10:01:38.807178 Connected to device vid:did:rid of 1ae0:0028:00
9428 10:01:38.813794 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9429 10:01:38.821034 Initialized TPM device CR50 revision 0
9430 10:01:38.821117 Checking cr50 for pending updates
9431 10:01:38.826647 Reading cr50 TPM mode
9432 10:01:38.835237 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9433 10:01:38.841768 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9434 10:01:38.881896 read SPI 0x3990ec 0x4f1b0: 34853 us, 9296 KB/s, 74.368 Mbps
9435 10:01:38.885185 Checking segment from ROM address 0x40100000
9436 10:01:38.888699 Checking segment from ROM address 0x4010001c
9437 10:01:38.895432 Loading segment from ROM address 0x40100000
9438 10:01:38.895536 code (compression=0)
9439 10:01:38.901994 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9440 10:01:38.912253 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9441 10:01:38.912387 it's not compressed!
9442 10:01:38.918950 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9443 10:01:38.921962 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9444 10:01:38.942656 Loading segment from ROM address 0x4010001c
9445 10:01:38.942738 Entry Point 0x80000000
9446 10:01:38.945599 Loaded segments
9447 10:01:38.948944 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9448 10:01:38.955739 Jumping to boot code at 0x80000000(0xffe64000)
9449 10:01:38.962312 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9450 10:01:38.969047 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9451 10:01:38.976747 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9452 10:01:38.980486 Checking segment from ROM address 0x40100000
9453 10:01:38.983582 Checking segment from ROM address 0x4010001c
9454 10:01:38.990136 Loading segment from ROM address 0x40100000
9455 10:01:38.990220 code (compression=1)
9456 10:01:38.996866 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9457 10:01:39.007306 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9458 10:01:39.007390 using LZMA
9459 10:01:39.015569 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9460 10:01:39.022019 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9461 10:01:39.025210 Loading segment from ROM address 0x4010001c
9462 10:01:39.025292 Entry Point 0x54601000
9463 10:01:39.028641 Loaded segments
9464 10:01:39.031859 NOTICE: MT8192 bl31_setup
9465 10:01:39.039202 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9466 10:01:39.042194 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9467 10:01:39.045569 WARNING: region 0:
9468 10:01:39.049192 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 10:01:39.049308 WARNING: region 1:
9470 10:01:39.055650 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9471 10:01:39.058931 WARNING: region 2:
9472 10:01:39.062255 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9473 10:01:39.065546 WARNING: region 3:
9474 10:01:39.068843 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 10:01:39.072197 WARNING: region 4:
9476 10:01:39.078816 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 10:01:39.078899 WARNING: region 5:
9478 10:01:39.082484 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 10:01:39.085566 WARNING: region 6:
9480 10:01:39.088900 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 10:01:39.088987 WARNING: region 7:
9482 10:01:39.095604 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 10:01:39.102292 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9484 10:01:39.105716 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9485 10:01:39.109009 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9486 10:01:39.115551 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9487 10:01:39.119136 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9488 10:01:39.122223 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9489 10:01:39.129208 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9490 10:01:39.132358 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9491 10:01:39.135838 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9492 10:01:39.142388 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9493 10:01:39.145889 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9494 10:01:39.152562 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9495 10:01:39.155674 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9496 10:01:39.159104 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9497 10:01:39.165648 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9498 10:01:39.168996 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9499 10:01:39.172252 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9500 10:01:39.179006 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9501 10:01:39.182496 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9502 10:01:39.185881 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9503 10:01:39.192536 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9504 10:01:39.195810 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9505 10:01:39.202374 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9506 10:01:39.205789 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9507 10:01:39.209113 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9508 10:01:39.215694 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9509 10:01:39.219035 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9510 10:01:39.226006 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9511 10:01:39.229434 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9512 10:01:39.232566 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9513 10:01:39.239109 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9514 10:01:39.242673 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9515 10:01:39.245886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9516 10:01:39.252915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9517 10:01:39.256060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9518 10:01:39.259634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9519 10:01:39.262629 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9520 10:01:39.269750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9521 10:01:39.272676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9522 10:01:39.275855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9523 10:01:39.279417 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9524 10:01:39.285894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9525 10:01:39.289230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9526 10:01:39.292660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9527 10:01:39.296263 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9528 10:01:39.302757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9529 10:01:39.305950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9530 10:01:39.309488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9531 10:01:39.315851 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9532 10:01:39.319443 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9533 10:01:39.322707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9534 10:01:39.329272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9535 10:01:39.332918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9536 10:01:39.339428 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9537 10:01:39.342619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9538 10:01:39.349316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9539 10:01:39.352840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9540 10:01:39.356211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9541 10:01:39.362841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9542 10:01:39.366387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9543 10:01:39.373099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9544 10:01:39.376111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9545 10:01:39.383359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9546 10:01:39.386429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9547 10:01:39.389912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9548 10:01:39.396530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9549 10:01:39.399613 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9550 10:01:39.406276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9551 10:01:39.409745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9552 10:01:39.413105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9553 10:01:39.420004 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9554 10:01:39.423095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9555 10:01:39.429878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9556 10:01:39.433333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9557 10:01:39.439845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9558 10:01:39.443162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9559 10:01:39.446306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9560 10:01:39.453063 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9561 10:01:39.456594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9562 10:01:39.463219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9563 10:01:39.466542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9564 10:01:39.473063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9565 10:01:39.476579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9566 10:01:39.479814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9567 10:01:39.486782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9568 10:01:39.489925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9569 10:01:39.496400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9570 10:01:39.499848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9571 10:01:39.506801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9572 10:01:39.509985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9573 10:01:39.513381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9574 10:01:39.520120 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9575 10:01:39.523395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9576 10:01:39.530320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9577 10:01:39.533594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9578 10:01:39.540310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9579 10:01:39.543814 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9580 10:01:39.547056 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9581 10:01:39.550182 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9582 10:01:39.556790 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9583 10:01:39.560307 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9584 10:01:39.563424 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9585 10:01:39.570080 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9586 10:01:39.573681 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9587 10:01:39.580278 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9588 10:01:39.583550 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9589 10:01:39.586835 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9590 10:01:39.593147 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9591 10:01:39.596887 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9592 10:01:39.603398 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9593 10:01:39.607142 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9594 10:01:39.609926 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9595 10:01:39.617098 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9596 10:01:39.620225 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9597 10:01:39.623753 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9598 10:01:39.630261 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9599 10:01:39.633686 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9600 10:01:39.636977 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9601 10:01:39.643547 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9602 10:01:39.646885 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9603 10:01:39.650257 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9604 10:01:39.653682 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9605 10:01:39.656908 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9606 10:01:39.663578 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9607 10:01:39.667026 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9608 10:01:39.673750 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9609 10:01:39.677180 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9610 10:01:39.680698 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9611 10:01:39.686884 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9612 10:01:39.690377 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9613 10:01:39.693765 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9614 10:01:39.700558 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9615 10:01:39.703822 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9616 10:01:39.710449 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9617 10:01:39.713922 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9618 10:01:39.717259 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9619 10:01:39.723801 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9620 10:01:39.727226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9621 10:01:39.730967 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9622 10:01:39.737457 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9623 10:01:39.740970 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9624 10:01:39.747461 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9625 10:01:39.751030 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9626 10:01:39.754093 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9627 10:01:39.760642 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9628 10:01:39.764388 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9629 10:01:39.770927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9630 10:01:39.774277 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9631 10:01:39.777534 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9632 10:01:39.784053 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9633 10:01:39.787608 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9634 10:01:39.790640 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9635 10:01:39.797536 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9636 10:01:39.800906 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9637 10:01:39.807707 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9638 10:01:39.811159 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9639 10:01:39.814390 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9640 10:01:39.820896 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9641 10:01:39.824321 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9642 10:01:39.827928 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9643 10:01:39.834412 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9644 10:01:39.837946 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9645 10:01:39.844506 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9646 10:01:39.847837 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9647 10:01:39.851301 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9648 10:01:39.857711 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9649 10:01:39.861064 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9650 10:01:39.867876 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9651 10:01:39.871346 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9652 10:01:39.874370 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9653 10:01:39.881163 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9654 10:01:39.884291 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9655 10:01:39.887670 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9656 10:01:39.894345 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9657 10:01:39.897848 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9658 10:01:39.904326 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9659 10:01:39.907927 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9660 10:01:39.910920 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9661 10:01:39.917880 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9662 10:01:39.920906 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9663 10:01:39.927566 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9664 10:01:39.930766 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9665 10:01:39.934099 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9666 10:01:39.941020 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9667 10:01:39.944484 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9668 10:01:39.950879 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9669 10:01:39.954058 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9670 10:01:39.957469 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9671 10:01:39.964172 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9672 10:01:39.967632 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9673 10:01:39.974287 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9674 10:01:39.977550 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9675 10:01:39.980986 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9676 10:01:39.987315 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9677 10:01:39.990834 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9678 10:01:39.997378 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9679 10:01:40.000665 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9680 10:01:40.004287 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9681 10:01:40.010869 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9682 10:01:40.014019 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9683 10:01:40.020679 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9684 10:01:40.024018 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9685 10:01:40.030716 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9686 10:01:40.034343 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9687 10:01:40.037509 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9688 10:01:40.044028 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9689 10:01:40.047580 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9690 10:01:40.054148 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9691 10:01:40.057381 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9692 10:01:40.060535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9693 10:01:40.067113 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9694 10:01:40.070616 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9695 10:01:40.076998 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9696 10:01:40.080521 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9697 10:01:40.087313 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9698 10:01:40.090266 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9699 10:01:40.093811 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9700 10:01:40.100351 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9701 10:01:40.103664 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9702 10:01:40.110572 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9703 10:01:40.113938 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9704 10:01:40.116971 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9705 10:01:40.123585 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9706 10:01:40.127195 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9707 10:01:40.133635 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9708 10:01:40.136762 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9709 10:01:40.143742 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9710 10:01:40.146804 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9711 10:01:40.150306 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9712 10:01:40.156671 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9713 10:01:40.159966 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9714 10:01:40.163256 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9715 10:01:40.166535 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9716 10:01:40.169846 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9717 10:01:40.176697 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9718 10:01:40.180290 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9719 10:01:40.186449 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9720 10:01:40.190105 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9721 10:01:40.193551 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9722 10:01:40.199743 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9723 10:01:40.203558 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9724 10:01:40.209739 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9725 10:01:40.213140 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9726 10:01:40.216387 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9727 10:01:40.223086 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9728 10:01:40.226534 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9729 10:01:40.229754 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9730 10:01:40.236291 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9731 10:01:40.239525 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9732 10:01:40.243113 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9733 10:01:40.249521 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9734 10:01:40.253002 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9735 10:01:40.259444 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9736 10:01:40.262657 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9737 10:01:40.266009 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9738 10:01:40.272950 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9739 10:01:40.275889 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9740 10:01:40.279364 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9741 10:01:40.286146 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9742 10:01:40.289378 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9743 10:01:40.292446 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9744 10:01:40.299348 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9745 10:01:40.302836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9746 10:01:40.305896 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9747 10:01:40.312572 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9748 10:01:40.315638 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9749 10:01:40.322192 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9750 10:01:40.325982 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9751 10:01:40.328831 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9752 10:01:40.335832 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9753 10:01:40.338755 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9754 10:01:40.342450 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9755 10:01:40.345810 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9756 10:01:40.348770 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9757 10:01:40.355964 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9758 10:01:40.359109 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9759 10:01:40.362484 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9760 10:01:40.365815 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9761 10:01:40.372533 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9762 10:01:40.375692 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9763 10:01:40.378926 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9764 10:01:40.385682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9765 10:01:40.388947 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9766 10:01:40.392072 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9767 10:01:40.398978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9768 10:01:40.402106 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9769 10:01:40.408694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9770 10:01:40.412315 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9771 10:01:40.418618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9772 10:01:40.421823 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9773 10:01:40.425475 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9774 10:01:40.432142 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9775 10:01:40.435167 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9776 10:01:40.442118 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9777 10:01:40.445149 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9778 10:01:40.448454 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9779 10:01:40.454956 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9780 10:01:40.458903 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9781 10:01:40.465036 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9782 10:01:40.468687 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9783 10:01:40.471794 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9784 10:01:40.478522 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9785 10:01:40.482115 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9786 10:01:40.488841 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9787 10:01:40.491714 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9788 10:01:40.495306 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9789 10:01:40.502008 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9790 10:01:40.505637 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9791 10:01:40.511899 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9792 10:01:40.515227 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9793 10:01:40.518729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9794 10:01:40.524989 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9795 10:01:40.528366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9796 10:01:40.534871 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9797 10:01:40.538487 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9798 10:01:40.541545 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9799 10:01:40.548387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9800 10:01:40.551506 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9801 10:01:40.558195 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9802 10:01:40.561745 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9803 10:01:40.567987 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9804 10:01:40.571566 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9805 10:01:40.574860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9806 10:01:40.581207 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9807 10:01:40.584726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9808 10:01:40.591462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9809 10:01:40.594617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9810 10:01:40.598054 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9811 10:01:40.604335 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9812 10:01:40.607901 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9813 10:01:40.614645 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9814 10:01:40.617823 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9815 10:01:40.621271 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9816 10:01:40.627526 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9817 10:01:40.631058 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9818 10:01:40.638013 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9819 10:01:40.641125 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9820 10:01:40.644256 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9821 10:01:40.650917 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9822 10:01:40.654528 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9823 10:01:40.660961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9824 10:01:40.664382 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9825 10:01:40.671074 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9826 10:01:40.674563 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9827 10:01:40.677871 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9828 10:01:40.684284 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9829 10:01:40.687599 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9830 10:01:40.694495 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9831 10:01:40.697698 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9832 10:01:40.701133 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9833 10:01:40.707486 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9834 10:01:40.711068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9835 10:01:40.717588 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9836 10:01:40.720632 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9837 10:01:40.723992 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9838 10:01:40.730746 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9839 10:01:40.734129 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9840 10:01:40.740672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9841 10:01:40.743864 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9842 10:01:40.750670 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9843 10:01:40.753787 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9844 10:01:40.757497 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9845 10:01:40.764074 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9846 10:01:40.767280 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9847 10:01:40.773850 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9848 10:01:40.777150 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9849 10:01:40.783836 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9850 10:01:40.787231 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9851 10:01:40.793994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9852 10:01:40.796914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9853 10:01:40.800553 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9854 10:01:40.807015 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9855 10:01:40.810358 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9856 10:01:40.817014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9857 10:01:40.820406 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9858 10:01:40.827383 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9859 10:01:40.830209 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9860 10:01:40.833709 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9861 10:01:40.840022 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9862 10:01:40.843350 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9863 10:01:40.849982 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9864 10:01:40.853512 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9865 10:01:40.860125 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9866 10:01:40.863233 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9867 10:01:40.869902 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9868 10:01:40.873454 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9869 10:01:40.876616 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9870 10:01:40.883572 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9871 10:01:40.886910 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9872 10:01:40.893418 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9873 10:01:40.896542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9874 10:01:40.903243 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9875 10:01:40.906662 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9876 10:01:40.909970 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9877 10:01:40.916644 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9878 10:01:40.919832 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9879 10:01:40.926683 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9880 10:01:40.929759 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9881 10:01:40.936628 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9882 10:01:40.939930 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9883 10:01:40.943239 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9884 10:01:40.949578 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9885 10:01:40.953194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9886 10:01:40.959527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9887 10:01:40.963124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9888 10:01:40.969860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9889 10:01:40.972884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9890 10:01:40.979438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9891 10:01:40.983091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9892 10:01:40.986216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9893 10:01:40.993034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9894 10:01:40.996130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9895 10:01:41.003029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9896 10:01:41.006077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9897 10:01:41.012798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9898 10:01:41.016018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9899 10:01:41.022800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9900 10:01:41.026087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9901 10:01:41.032749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9902 10:01:41.035955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9903 10:01:41.042671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9904 10:01:41.045667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9905 10:01:41.052275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9906 10:01:41.055755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9907 10:01:41.062553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9908 10:01:41.065722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9909 10:01:41.072298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9910 10:01:41.075822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9911 10:01:41.082453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9912 10:01:41.085615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9913 10:01:41.092266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9914 10:01:41.095717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9915 10:01:41.102285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9916 10:01:41.105725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9917 10:01:41.112253 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9918 10:01:41.112362 INFO: [APUAPC] vio 0
9919 10:01:41.118750 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9920 10:01:41.122413 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9921 10:01:41.125611 INFO: [APUAPC] D0_APC_0: 0x400510
9922 10:01:41.128848 INFO: [APUAPC] D0_APC_1: 0x0
9923 10:01:41.132132 INFO: [APUAPC] D0_APC_2: 0x1540
9924 10:01:41.136014 INFO: [APUAPC] D0_APC_3: 0x0
9925 10:01:41.138944 INFO: [APUAPC] D1_APC_0: 0xffffffff
9926 10:01:41.142093 INFO: [APUAPC] D1_APC_1: 0xffffffff
9927 10:01:41.145268 INFO: [APUAPC] D1_APC_2: 0x3fffff
9928 10:01:41.148775 INFO: [APUAPC] D1_APC_3: 0x0
9929 10:01:41.152236 INFO: [APUAPC] D2_APC_0: 0xffffffff
9930 10:01:41.155378 INFO: [APUAPC] D2_APC_1: 0xffffffff
9931 10:01:41.158888 INFO: [APUAPC] D2_APC_2: 0x3fffff
9932 10:01:41.161983 INFO: [APUAPC] D2_APC_3: 0x0
9933 10:01:41.165501 INFO: [APUAPC] D3_APC_0: 0xffffffff
9934 10:01:41.169010 INFO: [APUAPC] D3_APC_1: 0xffffffff
9935 10:01:41.172101 INFO: [APUAPC] D3_APC_2: 0x3fffff
9936 10:01:41.172221 INFO: [APUAPC] D3_APC_3: 0x0
9937 10:01:41.175650 INFO: [APUAPC] D4_APC_0: 0xffffffff
9938 10:01:41.182352 INFO: [APUAPC] D4_APC_1: 0xffffffff
9939 10:01:41.185447 INFO: [APUAPC] D4_APC_2: 0x3fffff
9940 10:01:41.185581 INFO: [APUAPC] D4_APC_3: 0x0
9941 10:01:41.188775 INFO: [APUAPC] D5_APC_0: 0xffffffff
9942 10:01:41.191908 INFO: [APUAPC] D5_APC_1: 0xffffffff
9943 10:01:41.195444 INFO: [APUAPC] D5_APC_2: 0x3fffff
9944 10:01:41.198934 INFO: [APUAPC] D5_APC_3: 0x0
9945 10:01:41.202148 INFO: [APUAPC] D6_APC_0: 0xffffffff
9946 10:01:41.205289 INFO: [APUAPC] D6_APC_1: 0xffffffff
9947 10:01:41.208501 INFO: [APUAPC] D6_APC_2: 0x3fffff
9948 10:01:41.212146 INFO: [APUAPC] D6_APC_3: 0x0
9949 10:01:41.215452 INFO: [APUAPC] D7_APC_0: 0xffffffff
9950 10:01:41.218648 INFO: [APUAPC] D7_APC_1: 0xffffffff
9951 10:01:41.222008 INFO: [APUAPC] D7_APC_2: 0x3fffff
9952 10:01:41.225566 INFO: [APUAPC] D7_APC_3: 0x0
9953 10:01:41.228845 INFO: [APUAPC] D8_APC_0: 0xffffffff
9954 10:01:41.232043 INFO: [APUAPC] D8_APC_1: 0xffffffff
9955 10:01:41.235375 INFO: [APUAPC] D8_APC_2: 0x3fffff
9956 10:01:41.239162 INFO: [APUAPC] D8_APC_3: 0x0
9957 10:01:41.242022 INFO: [APUAPC] D9_APC_0: 0xffffffff
9958 10:01:41.245289 INFO: [APUAPC] D9_APC_1: 0xffffffff
9959 10:01:41.248517 INFO: [APUAPC] D9_APC_2: 0x3fffff
9960 10:01:41.251692 INFO: [APUAPC] D9_APC_3: 0x0
9961 10:01:41.255218 INFO: [APUAPC] D10_APC_0: 0xffffffff
9962 10:01:41.258492 INFO: [APUAPC] D10_APC_1: 0xffffffff
9963 10:01:41.261634 INFO: [APUAPC] D10_APC_2: 0x3fffff
9964 10:01:41.265068 INFO: [APUAPC] D10_APC_3: 0x0
9965 10:01:41.268199 INFO: [APUAPC] D11_APC_0: 0xffffffff
9966 10:01:41.271789 INFO: [APUAPC] D11_APC_1: 0xffffffff
9967 10:01:41.274996 INFO: [APUAPC] D11_APC_2: 0x3fffff
9968 10:01:41.278105 INFO: [APUAPC] D11_APC_3: 0x0
9969 10:01:41.281444 INFO: [APUAPC] D12_APC_0: 0xffffffff
9970 10:01:41.284918 INFO: [APUAPC] D12_APC_1: 0xffffffff
9971 10:01:41.288383 INFO: [APUAPC] D12_APC_2: 0x3fffff
9972 10:01:41.291565 INFO: [APUAPC] D12_APC_3: 0x0
9973 10:01:41.294639 INFO: [APUAPC] D13_APC_0: 0xffffffff
9974 10:01:41.298263 INFO: [APUAPC] D13_APC_1: 0xffffffff
9975 10:01:41.301355 INFO: [APUAPC] D13_APC_2: 0x3fffff
9976 10:01:41.304725 INFO: [APUAPC] D13_APC_3: 0x0
9977 10:01:41.308369 INFO: [APUAPC] D14_APC_0: 0xffffffff
9978 10:01:41.311520 INFO: [APUAPC] D14_APC_1: 0xffffffff
9979 10:01:41.314593 INFO: [APUAPC] D14_APC_2: 0x3fffff
9980 10:01:41.318343 INFO: [APUAPC] D14_APC_3: 0x0
9981 10:01:41.321252 INFO: [APUAPC] D15_APC_0: 0xffffffff
9982 10:01:41.324725 INFO: [APUAPC] D15_APC_1: 0xffffffff
9983 10:01:41.327950 INFO: [APUAPC] D15_APC_2: 0x3fffff
9984 10:01:41.331431 INFO: [APUAPC] D15_APC_3: 0x0
9985 10:01:41.334669 INFO: [APUAPC] APC_CON: 0x4
9986 10:01:41.337871 INFO: [NOCDAPC] D0_APC_0: 0x0
9987 10:01:41.341346 INFO: [NOCDAPC] D0_APC_1: 0x0
9988 10:01:41.344846 INFO: [NOCDAPC] D1_APC_0: 0x0
9989 10:01:41.347999 INFO: [NOCDAPC] D1_APC_1: 0xfff
9990 10:01:41.348082 INFO: [NOCDAPC] D2_APC_0: 0x0
9991 10:01:41.351369 INFO: [NOCDAPC] D2_APC_1: 0xfff
9992 10:01:41.354486 INFO: [NOCDAPC] D3_APC_0: 0x0
9993 10:01:41.358041 INFO: [NOCDAPC] D3_APC_1: 0xfff
9994 10:01:41.360939 INFO: [NOCDAPC] D4_APC_0: 0x0
9995 10:01:41.364569 INFO: [NOCDAPC] D4_APC_1: 0xfff
9996 10:01:41.367653 INFO: [NOCDAPC] D5_APC_0: 0x0
9997 10:01:41.371222 INFO: [NOCDAPC] D5_APC_1: 0xfff
9998 10:01:41.374319 INFO: [NOCDAPC] D6_APC_0: 0x0
9999 10:01:41.377806 INFO: [NOCDAPC] D6_APC_1: 0xfff
10000 10:01:41.380888 INFO: [NOCDAPC] D7_APC_0: 0x0
10001 10:01:41.380986 INFO: [NOCDAPC] D7_APC_1: 0xfff
10002 10:01:41.384526 INFO: [NOCDAPC] D8_APC_0: 0x0
10003 10:01:41.387666 INFO: [NOCDAPC] D8_APC_1: 0xfff
10004 10:01:41.390753 INFO: [NOCDAPC] D9_APC_0: 0x0
10005 10:01:41.394231 INFO: [NOCDAPC] D9_APC_1: 0xfff
10006 10:01:41.397326 INFO: [NOCDAPC] D10_APC_0: 0x0
10007 10:01:41.401062 INFO: [NOCDAPC] D10_APC_1: 0xfff
10008 10:01:41.404322 INFO: [NOCDAPC] D11_APC_0: 0x0
10009 10:01:41.407527 INFO: [NOCDAPC] D11_APC_1: 0xfff
10010 10:01:41.410884 INFO: [NOCDAPC] D12_APC_0: 0x0
10011 10:01:41.414155 INFO: [NOCDAPC] D12_APC_1: 0xfff
10012 10:01:41.417357 INFO: [NOCDAPC] D13_APC_0: 0x0
10013 10:01:41.420990 INFO: [NOCDAPC] D13_APC_1: 0xfff
10014 10:01:41.424274 INFO: [NOCDAPC] D14_APC_0: 0x0
10015 10:01:41.424395 INFO: [NOCDAPC] D14_APC_1: 0xfff
10016 10:01:41.427286 INFO: [NOCDAPC] D15_APC_0: 0x0
10017 10:01:41.430893 INFO: [NOCDAPC] D15_APC_1: 0xfff
10018 10:01:41.434283 INFO: [NOCDAPC] APC_CON: 0x4
10019 10:01:41.437601 INFO: [APUAPC] set_apusys_apc done
10020 10:01:41.441007 INFO: [DEVAPC] devapc_init done
10021 10:01:41.444031 INFO: GICv3 without legacy support detected.
10022 10:01:41.450545 INFO: ARM GICv3 driver initialized in EL3
10023 10:01:41.453804 INFO: Maximum SPI INTID supported: 639
10024 10:01:41.457318 INFO: BL31: Initializing runtime services
10025 10:01:41.464187 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10026 10:01:41.464308 INFO: SPM: enable CPC mode
10027 10:01:41.470723 INFO: mcdi ready for mcusys-off-idle and system suspend
10028 10:01:41.473817 INFO: BL31: Preparing for EL3 exit to normal world
10029 10:01:41.480440 INFO: Entry point address = 0x80000000
10030 10:01:41.480553 INFO: SPSR = 0x8
10031 10:01:41.486874
10032 10:01:41.486991
10033 10:01:41.487094
10034 10:01:41.490188 Starting depthcharge on Spherion...
10035 10:01:41.490307
10036 10:01:41.490414 Wipe memory regions:
10037 10:01:41.490522
10038 10:01:41.491340 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10039 10:01:41.491494 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10040 10:01:41.491622 Setting prompt string to ['asurada:']
10041 10:01:41.491749 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10042 10:01:41.493512 [0x00000040000000, 0x00000054600000)
10043 10:01:41.615851
10044 10:01:41.615967 [0x00000054660000, 0x00000080000000)
10045 10:01:41.876507
10046 10:01:41.876636 [0x000000821a7280, 0x000000ffe64000)
10047 10:01:42.621409
10048 10:01:42.621549 [0x00000100000000, 0x00000240000000)
10049 10:01:44.511850
10050 10:01:44.514851 Initializing XHCI USB controller at 0x11200000.
10051 10:01:45.553043
10052 10:01:45.556396 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10053 10:01:45.556485
10054 10:01:45.556550
10055 10:01:45.556612
10056 10:01:45.556890 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 10:01:45.657163 asurada: tftpboot 192.168.201.1 11336440/tftp-deploy-_opjp2ba/kernel/image.itb 11336440/tftp-deploy-_opjp2ba/kernel/cmdline
10059 10:01:45.657294 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 10:01:45.657435 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10061 10:01:45.661921 tftpboot 192.168.201.1 11336440/tftp-deploy-_opjp2ba/kernel/image.ittp-deploy-_opjp2ba/kernel/cmdline
10062 10:01:45.662007
10063 10:01:45.662072 Waiting for link
10064 10:01:45.822103
10065 10:01:45.822226 R8152: Initializing
10066 10:01:45.822294
10067 10:01:45.825235 Version 9 (ocp_data = 6010)
10068 10:01:45.825319
10069 10:01:45.828537 R8152: Done initializing
10070 10:01:45.828620
10071 10:01:45.828687 Adding net device
10072 10:01:47.700917
10073 10:01:47.701064 done.
10074 10:01:47.701131
10075 10:01:47.701192 MAC: 00:e0:4c:72:2d:d6
10076 10:01:47.701253
10077 10:01:47.704180 Sending DHCP discover... done.
10078 10:01:47.704265
10079 10:01:55.649661 Waiting for reply... done.
10080 10:01:55.649810
10081 10:01:55.649876 Sending DHCP request... done.
10082 10:01:55.652399
10083 10:01:55.652496 Waiting for reply... done.
10084 10:01:55.652592
10085 10:01:55.656209 My ip is 192.168.201.21
10086 10:01:55.656291
10087 10:01:55.659192 The DHCP server ip is 192.168.201.1
10088 10:01:55.659276
10089 10:01:55.662889 TFTP server IP predefined by user: 192.168.201.1
10090 10:01:55.662972
10091 10:01:55.669221 Bootfile predefined by user: 11336440/tftp-deploy-_opjp2ba/kernel/image.itb
10092 10:01:55.669303
10093 10:01:55.672684 Sending tftp read request... done.
10094 10:01:55.672763
10095 10:01:55.676115 Waiting for the transfer...
10096 10:01:55.676198
10097 10:01:55.969594 00000000 ################################################################
10098 10:01:55.969736
10099 10:01:56.263850 00080000 ################################################################
10100 10:01:56.263996
10101 10:01:56.557843 00100000 ################################################################
10102 10:01:56.558005
10103 10:01:56.843180 00180000 ################################################################
10104 10:01:56.843319
10105 10:01:57.100979 00200000 ################################################################
10106 10:01:57.101110
10107 10:01:57.353869 00280000 ################################################################
10108 10:01:57.354003
10109 10:01:57.607993 00300000 ################################################################
10110 10:01:57.608127
10111 10:01:57.870071 00380000 ################################################################
10112 10:01:57.870213
10113 10:01:58.144105 00400000 ################################################################
10114 10:01:58.144296
10115 10:01:58.406809 00480000 ################################################################
10116 10:01:58.406997
10117 10:01:58.663570 00500000 ################################################################
10118 10:01:58.663702
10119 10:01:58.923307 00580000 ################################################################
10120 10:01:58.923441
10121 10:01:59.184809 00600000 ################################################################
10122 10:01:59.184945
10123 10:01:59.467913 00680000 ################################################################
10124 10:01:59.468115
10125 10:01:59.742208 00700000 ################################################################
10126 10:01:59.742386
10127 10:01:59.996161 00780000 ################################################################
10128 10:01:59.996304
10129 10:02:00.249012 00800000 ################################################################
10130 10:02:00.249148
10131 10:02:00.501317 00880000 ################################################################
10132 10:02:00.501470
10133 10:02:00.758097 00900000 ################################################################
10134 10:02:00.758235
10135 10:02:01.012680 00980000 ################################################################
10136 10:02:01.012918
10137 10:02:01.276888 00a00000 ################################################################
10138 10:02:01.277020
10139 10:02:01.534125 00a80000 ################################################################
10140 10:02:01.534292
10141 10:02:01.803351 00b00000 ################################################################
10142 10:02:01.803510
10143 10:02:02.054857 00b80000 ################################################################
10144 10:02:02.055051
10145 10:02:02.327612 00c00000 ################################################################
10146 10:02:02.327810
10147 10:02:02.611014 00c80000 ################################################################
10148 10:02:02.611155
10149 10:02:02.905991 00d00000 ################################################################
10150 10:02:02.906214
10151 10:02:03.165612 00d80000 ################################################################
10152 10:02:03.165809
10153 10:02:03.427584 00e00000 ################################################################
10154 10:02:03.427788
10155 10:02:03.692710 00e80000 ################################################################
10156 10:02:03.692943
10157 10:02:03.986296 00f00000 ################################################################
10158 10:02:03.986498
10159 10:02:04.282666 00f80000 ################################################################
10160 10:02:04.282800
10161 10:02:04.561120 01000000 ################################################################
10162 10:02:04.561259
10163 10:02:04.818890 01080000 ################################################################
10164 10:02:04.819029
10165 10:02:05.090350 01100000 ################################################################
10166 10:02:05.090540
10167 10:02:05.360950 01180000 ################################################################
10168 10:02:05.361147
10169 10:02:05.644267 01200000 ################################################################
10170 10:02:05.644427
10171 10:02:05.914110 01280000 ################################################################
10172 10:02:05.914303
10173 10:02:06.204484 01300000 ################################################################
10174 10:02:06.204648
10175 10:02:06.497923 01380000 ################################################################
10176 10:02:06.498119
10177 10:02:06.772934 01400000 ################################################################
10178 10:02:06.773077
10179 10:02:07.069341 01480000 ################################################################
10180 10:02:07.069534
10181 10:02:07.356851 01500000 ################################################################
10182 10:02:07.356979
10183 10:02:07.645803 01580000 ################################################################
10184 10:02:07.645951
10185 10:02:07.944304 01600000 ################################################################
10186 10:02:07.944447
10187 10:02:08.231988 01680000 ################################################################
10188 10:02:08.232185
10189 10:02:08.509124 01700000 ################################################################
10190 10:02:08.509319
10191 10:02:08.782517 01780000 ################################################################
10192 10:02:08.782657
10193 10:02:09.046801 01800000 ################################################################
10194 10:02:09.046939
10195 10:02:09.313647 01880000 ################################################################
10196 10:02:09.313785
10197 10:02:09.585764 01900000 ################################################################
10198 10:02:09.585915
10199 10:02:09.871089 01980000 ################################################################
10200 10:02:09.871293
10201 10:02:10.150873 01a00000 ################################################################
10202 10:02:10.151000
10203 10:02:10.403262 01a80000 ################################################################
10204 10:02:10.403399
10205 10:02:10.655841 01b00000 ################################################################
10206 10:02:10.656027
10207 10:02:10.909138 01b80000 ################################################################
10208 10:02:10.909269
10209 10:02:11.168134 01c00000 ################################################################
10210 10:02:11.168285
10211 10:02:11.426799 01c80000 ################################################################
10212 10:02:11.426945
10213 10:02:11.681213 01d00000 ################################################################
10214 10:02:11.681403
10215 10:02:11.942053 01d80000 ################################################################
10216 10:02:11.942239
10217 10:02:12.194566 01e00000 ################################################################
10218 10:02:12.194727
10219 10:02:12.448061 01e80000 ################################################################
10220 10:02:12.448213
10221 10:02:12.701448 01f00000 ################################################################
10222 10:02:12.701634
10223 10:02:12.956436 01f80000 ################################################################
10224 10:02:12.956634
10225 10:02:13.230369 02000000 ################################################################
10226 10:02:13.230503
10227 10:02:13.514059 02080000 ################################################################
10228 10:02:13.514190
10229 10:02:13.776671 02100000 ################################################################
10230 10:02:13.776864
10231 10:02:14.031439 02180000 ################################################################
10232 10:02:14.031605
10233 10:02:14.299734 02200000 ################################################################
10234 10:02:14.299882
10235 10:02:14.573282 02280000 ################################################################
10236 10:02:14.573459
10237 10:02:14.835750 02300000 ################################################################
10238 10:02:14.835886
10239 10:02:15.097873 02380000 ################################################################
10240 10:02:15.098079
10241 10:02:15.375994 02400000 ################################################################
10242 10:02:15.376131
10243 10:02:15.665737 02480000 ################################################################
10244 10:02:15.665894
10245 10:02:15.959951 02500000 ################################################################
10246 10:02:15.960094
10247 10:02:16.240361 02580000 ################################################################
10248 10:02:16.240500
10249 10:02:16.524305 02600000 ################################################################
10250 10:02:16.524510
10251 10:02:16.795892 02680000 ################################################################
10252 10:02:16.796043
10253 10:02:17.081026 02700000 ################################################################
10254 10:02:17.081167
10255 10:02:17.368012 02780000 ################################################################
10256 10:02:17.368152
10257 10:02:17.646047 02800000 ################################################################
10258 10:02:17.646252
10259 10:02:17.937588 02880000 ################################################################
10260 10:02:17.937726
10261 10:02:18.236901 02900000 ################################################################
10262 10:02:18.237112
10263 10:02:18.532982 02980000 ################################################################
10264 10:02:18.533117
10265 10:02:18.823804 02a00000 ################################################################
10266 10:02:18.823967
10267 10:02:19.093941 02a80000 ################################################################
10268 10:02:19.094085
10269 10:02:19.368655 02b00000 ################################################################
10270 10:02:19.368841
10271 10:02:19.647492 02b80000 ################################################################
10272 10:02:19.647649
10273 10:02:19.915244 02c00000 ################################################################
10274 10:02:19.915435
10275 10:02:20.193435 02c80000 ################################################################
10276 10:02:20.193632
10277 10:02:20.488945 02d00000 ################################################################
10278 10:02:20.489088
10279 10:02:20.771548 02d80000 ################################################################
10280 10:02:20.771684
10281 10:02:21.056162 02e00000 ################################################################
10282 10:02:21.056301
10283 10:02:21.346686 02e80000 ################################################################
10284 10:02:21.346840
10285 10:02:21.634006 02f00000 ################################################################
10286 10:02:21.634152
10287 10:02:21.929581 02f80000 ################################################################
10288 10:02:21.929727
10289 10:02:21.983714 03000000 ############ done.
10290 10:02:21.983813
10291 10:02:21.987038 The bootfile was 50427798 bytes long.
10292 10:02:21.987123
10293 10:02:21.990182 Sending tftp read request... done.
10294 10:02:21.990273
10295 10:02:21.990340 Waiting for the transfer...
10296 10:02:21.990403
10297 10:02:21.993752 00000000 # done.
10298 10:02:21.993837
10299 10:02:22.000279 Command line loaded dynamically from TFTP file: 11336440/tftp-deploy-_opjp2ba/kernel/cmdline
10300 10:02:22.000364
10301 10:02:22.013411 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10302 10:02:22.013496
10303 10:02:22.016649 Loading FIT.
10304 10:02:22.016734
10305 10:02:22.020400 Image ramdisk-1 has 39341225 bytes.
10306 10:02:22.020483
10307 10:02:22.020548 Image fdt-1 has 47278 bytes.
10308 10:02:22.020609
10309 10:02:22.023350 Image kernel-1 has 11037260 bytes.
10310 10:02:22.023433
10311 10:02:22.033556 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10312 10:02:22.033640
10313 10:02:22.049793 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10314 10:02:22.049881
10315 10:02:22.056556 Choosing best match conf-1 for compat google,spherion-rev2.
10316 10:02:22.060320
10317 10:02:22.065046 Connected to device vid:did:rid of 1ae0:0028:00
10318 10:02:22.072060
10319 10:02:22.075124 tpm_get_response: command 0x17b, return code 0x0
10320 10:02:22.075209
10321 10:02:22.078696 ec_init: CrosEC protocol v3 supported (256, 248)
10322 10:02:22.082537
10323 10:02:22.082621 tpm_cleanup: add release locality here.
10324 10:02:22.086125
10325 10:02:22.086207 Shutting down all USB controllers.
10326 10:02:22.086274
10327 10:02:22.089459 Removing current net device
10328 10:02:22.089558
10329 10:02:22.096098 Exiting depthcharge with code 4 at timestamp: 69964552
10330 10:02:22.096182
10331 10:02:22.099191 LZMA decompressing kernel-1 to 0x821a6718
10332 10:02:22.099274
10333 10:02:22.102451 LZMA decompressing kernel-1 to 0x40000000
10334 10:02:23.488745
10335 10:02:23.488991 jumping to kernel
10336 10:02:23.489629 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10337 10:02:23.489794 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10338 10:02:23.489927 Setting prompt string to ['Linux version [0-9]']
10339 10:02:23.490048 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10340 10:02:23.490173 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10341 10:02:23.570537
10342 10:02:23.573994 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10343 10:02:23.577691 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10344 10:02:23.577786 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10345 10:02:23.577859 Setting prompt string to []
10346 10:02:23.577937 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10347 10:02:23.578011 Using line separator: #'\n'#
10348 10:02:23.578071 No login prompt set.
10349 10:02:23.578132 Parsing kernel messages
10350 10:02:23.578188 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10351 10:02:23.578287 [login-action] Waiting for messages, (timeout 00:03:43)
10352 10:02:23.597169 [ 0.000000] Linux version 6.1.45-cip3 (KernelCI@build-j18697-arm64-gcc-10-defconfig-arm64-chromebook-vvl9c) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Aug 23 09:52:58 UTC 2023
10353 10:02:23.600605 [ 0.000000] random: crng init done
10354 10:02:23.607294 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10355 10:02:23.607378 [ 0.000000] efi: UEFI not found.
10356 10:02:23.617490 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10357 10:02:23.623848 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10358 10:02:23.633697 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10359 10:02:23.643778 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10360 10:02:23.650096 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10361 10:02:23.656659 [ 0.000000] printk: bootconsole [mtk8250] enabled
10362 10:02:23.660293 [ 0.000000] NUMA: No NUMA configuration found
10363 10:02:23.670316 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10364 10:02:23.673579 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10365 10:02:23.676880 [ 0.000000] Zone ranges:
10366 10:02:23.683375 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10367 10:02:23.686830 [ 0.000000] DMA32 empty
10368 10:02:23.693457 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10369 10:02:23.696429 [ 0.000000] Movable zone start for each node
10370 10:02:23.699903 [ 0.000000] Early memory node ranges
10371 10:02:23.706666 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10372 10:02:23.713360 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10373 10:02:23.719733 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10374 10:02:23.726582 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10375 10:02:23.729889 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10376 10:02:23.739643 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10377 10:02:23.794991 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10378 10:02:23.801846 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10379 10:02:23.808361 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10380 10:02:23.811900 [ 0.000000] psci: probing for conduit method from DT.
10381 10:02:23.818508 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10382 10:02:23.821651 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10383 10:02:23.828299 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10384 10:02:23.831806 [ 0.000000] psci: SMC Calling Convention v1.2
10385 10:02:23.838648 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10386 10:02:23.841926 [ 0.000000] Detected VIPT I-cache on CPU0
10387 10:02:23.848542 [ 0.000000] CPU features: detected: GIC system register CPU interface
10388 10:02:23.854883 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10389 10:02:23.861581 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10390 10:02:23.868010 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10391 10:02:23.874853 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10392 10:02:23.881697 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10393 10:02:23.888240 [ 0.000000] alternatives: applying boot alternatives
10394 10:02:23.891742 [ 0.000000] Fallback order for Node 0: 0
10395 10:02:23.898401 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10396 10:02:23.901483 [ 0.000000] Policy zone: Normal
10397 10:02:23.918143 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10398 10:02:23.928040 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10399 10:02:23.939579 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10400 10:02:23.949533 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10401 10:02:23.956119 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10402 10:02:23.959326 <6>[ 0.000000] software IO TLB: area num 8.
10403 10:02:24.015951 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10404 10:02:24.165022 <6>[ 0.000000] Memory: 7931136K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 421632K reserved, 32768K cma-reserved)
10405 10:02:24.171507 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10406 10:02:24.178317 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10407 10:02:24.181702 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10408 10:02:24.188165 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10409 10:02:24.194887 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10410 10:02:24.198472 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10411 10:02:24.208220 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10412 10:02:24.214883 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10413 10:02:24.221290 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10414 10:02:24.227746 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10415 10:02:24.231120 <6>[ 0.000000] GICv3: 608 SPIs implemented
10416 10:02:24.234465 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10417 10:02:24.241248 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10418 10:02:24.244305 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10419 10:02:24.250806 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10420 10:02:24.264449 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10421 10:02:24.277644 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10422 10:02:24.284135 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10423 10:02:24.291620 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10424 10:02:24.305365 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10425 10:02:24.311973 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10426 10:02:24.318590 <6>[ 0.009173] Console: colour dummy device 80x25
10427 10:02:24.328151 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10428 10:02:24.331921 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10429 10:02:24.338240 <6>[ 0.029213] LSM: Security Framework initializing
10430 10:02:24.344782 <6>[ 0.034151] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10431 10:02:24.354863 <6>[ 0.041981] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10432 10:02:24.361255 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10433 10:02:24.367920 <6>[ 0.058943] cblist_init_generic: Setting shift to 3 and lim to 1.
10434 10:02:24.378100 <6>[ 0.065282] cblist_init_generic: Setting adjustable number of callback queues.
10435 10:02:24.384467 <6>[ 0.072707] cblist_init_generic: Setting shift to 3 and lim to 1.
10436 10:02:24.387912 <6>[ 0.079106] rcu: Hierarchical SRCU implementation.
10437 10:02:24.394456 <6>[ 0.084120] rcu: Max phase no-delay instances is 1000.
10438 10:02:24.401038 <6>[ 0.091151] EFI services will not be available.
10439 10:02:24.404444 <6>[ 0.096151] smp: Bringing up secondary CPUs ...
10440 10:02:24.412615 <6>[ 0.101232] Detected VIPT I-cache on CPU1
10441 10:02:24.419362 <6>[ 0.101298] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10442 10:02:24.425776 <6>[ 0.101330] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10443 10:02:24.429471 <6>[ 0.101657] Detected VIPT I-cache on CPU2
10444 10:02:24.435679 <6>[ 0.101705] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10445 10:02:24.445761 <6>[ 0.101720] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10446 10:02:24.448914 <6>[ 0.101977] Detected VIPT I-cache on CPU3
10447 10:02:24.455646 <6>[ 0.102023] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10448 10:02:24.462362 <6>[ 0.102037] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10449 10:02:24.465690 <6>[ 0.102343] CPU features: detected: Spectre-v4
10450 10:02:24.471996 <6>[ 0.102349] CPU features: detected: Spectre-BHB
10451 10:02:24.475518 <6>[ 0.102354] Detected PIPT I-cache on CPU4
10452 10:02:24.482068 <6>[ 0.102410] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10453 10:02:24.488686 <6>[ 0.102428] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10454 10:02:24.495468 <6>[ 0.102719] Detected PIPT I-cache on CPU5
10455 10:02:24.501820 <6>[ 0.102782] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10456 10:02:24.509136 <6>[ 0.102800] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10457 10:02:24.512127 <6>[ 0.103082] Detected PIPT I-cache on CPU6
10458 10:02:24.518399 <6>[ 0.103147] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10459 10:02:24.524856 <6>[ 0.103164] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10460 10:02:24.531659 <6>[ 0.103462] Detected PIPT I-cache on CPU7
10461 10:02:24.538645 <6>[ 0.103526] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10462 10:02:24.545090 <6>[ 0.103543] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10463 10:02:24.548090 <6>[ 0.103591] smp: Brought up 1 node, 8 CPUs
10464 10:02:24.554586 <6>[ 0.244966] SMP: Total of 8 processors activated.
10465 10:02:24.558106 <6>[ 0.249887] CPU features: detected: 32-bit EL0 Support
10466 10:02:24.568091 <6>[ 0.255284] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10467 10:02:24.574659 <6>[ 0.264139] CPU features: detected: Common not Private translations
10468 10:02:24.581093 <6>[ 0.270655] CPU features: detected: CRC32 instructions
10469 10:02:24.584601 <6>[ 0.276007] CPU features: detected: RCpc load-acquire (LDAPR)
10470 10:02:24.590777 <6>[ 0.281967] CPU features: detected: LSE atomic instructions
10471 10:02:24.597601 <6>[ 0.287749] CPU features: detected: Privileged Access Never
10472 10:02:24.604122 <6>[ 0.293564] CPU features: detected: RAS Extension Support
10473 10:02:24.610732 <6>[ 0.299173] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10474 10:02:24.614204 <6>[ 0.306438] CPU: All CPU(s) started at EL2
10475 10:02:24.620596 <6>[ 0.310754] alternatives: applying system-wide alternatives
10476 10:02:24.630185 <6>[ 0.321460] devtmpfs: initialized
10477 10:02:24.642496 <6>[ 0.330291] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10478 10:02:24.652674 <6>[ 0.340253] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10479 10:02:24.658905 <6>[ 0.348258] pinctrl core: initialized pinctrl subsystem
10480 10:02:24.662566 <6>[ 0.354938] DMI not present or invalid.
10481 10:02:24.669101 <6>[ 0.359340] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10482 10:02:24.679022 <6>[ 0.366199] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10483 10:02:24.686192 <6>[ 0.373782] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10484 10:02:24.695465 <6>[ 0.381998] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10485 10:02:24.698888 <6>[ 0.390243] audit: initializing netlink subsys (disabled)
10486 10:02:24.708738 <5>[ 0.395938] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10487 10:02:24.715239 <6>[ 0.396644] thermal_sys: Registered thermal governor 'step_wise'
10488 10:02:24.722381 <6>[ 0.403908] thermal_sys: Registered thermal governor 'power_allocator'
10489 10:02:24.725534 <6>[ 0.410162] cpuidle: using governor menu
10490 10:02:24.732271 <6>[ 0.421120] NET: Registered PF_QIPCRTR protocol family
10491 10:02:24.738809 <6>[ 0.426598] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10492 10:02:24.741682 <6>[ 0.433705] ASID allocator initialised with 32768 entries
10493 10:02:24.749104 <6>[ 0.440286] Serial: AMBA PL011 UART driver
10494 10:02:24.757786 <4>[ 0.449084] Trying to register duplicate clock ID: 134
10495 10:02:24.811820 <6>[ 0.506392] KASLR enabled
10496 10:02:24.826151 <6>[ 0.514092] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10497 10:02:24.832837 <6>[ 0.521108] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10498 10:02:24.839887 <6>[ 0.527598] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10499 10:02:24.846215 <6>[ 0.534603] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10500 10:02:24.853083 <6>[ 0.541091] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10501 10:02:24.859328 <6>[ 0.548097] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10502 10:02:24.866133 <6>[ 0.554585] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10503 10:02:24.872717 <6>[ 0.561587] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10504 10:02:24.876077 <6>[ 0.569097] ACPI: Interpreter disabled.
10505 10:02:24.884568 <6>[ 0.575494] iommu: Default domain type: Translated
10506 10:02:24.891161 <6>[ 0.580605] iommu: DMA domain TLB invalidation policy: strict mode
10507 10:02:24.895134 <5>[ 0.587254] SCSI subsystem initialized
10508 10:02:24.901071 <6>[ 0.591417] usbcore: registered new interface driver usbfs
10509 10:02:24.907680 <6>[ 0.597149] usbcore: registered new interface driver hub
10510 10:02:24.910947 <6>[ 0.602701] usbcore: registered new device driver usb
10511 10:02:24.917643 <6>[ 0.608794] pps_core: LinuxPPS API ver. 1 registered
10512 10:02:24.928219 <6>[ 0.613988] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10513 10:02:24.930927 <6>[ 0.623337] PTP clock support registered
10514 10:02:24.934196 <6>[ 0.627578] EDAC MC: Ver: 3.0.0
10515 10:02:24.941688 <6>[ 0.632720] FPGA manager framework
10516 10:02:24.945111 <6>[ 0.636401] Advanced Linux Sound Architecture Driver Initialized.
10517 10:02:24.948928 <6>[ 0.643169] vgaarb: loaded
10518 10:02:24.955528 <6>[ 0.646330] clocksource: Switched to clocksource arch_sys_counter
10519 10:02:24.961871 <5>[ 0.652760] VFS: Disk quotas dquot_6.6.0
10520 10:02:24.968951 <6>[ 0.656945] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10521 10:02:24.971978 <6>[ 0.664131] pnp: PnP ACPI: disabled
10522 10:02:24.979716 <6>[ 0.670794] NET: Registered PF_INET protocol family
10523 10:02:24.989477 <6>[ 0.676378] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10524 10:02:25.000950 <6>[ 0.688671] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10525 10:02:25.010672 <6>[ 0.697485] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10526 10:02:25.017624 <6>[ 0.705456] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10527 10:02:25.027074 <6>[ 0.714153] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10528 10:02:25.033934 <6>[ 0.723901] TCP: Hash tables configured (established 65536 bind 65536)
10529 10:02:25.040382 <6>[ 0.730755] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10530 10:02:25.050685 <6>[ 0.737955] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10531 10:02:25.057275 <6>[ 0.745656] NET: Registered PF_UNIX/PF_LOCAL protocol family
10532 10:02:25.060462 <6>[ 0.751829] RPC: Registered named UNIX socket transport module.
10533 10:02:25.067004 <6>[ 0.757981] RPC: Registered udp transport module.
10534 10:02:25.070604 <6>[ 0.762913] RPC: Registered tcp transport module.
10535 10:02:25.077421 <6>[ 0.767844] RPC: Registered tcp NFSv4.1 backchannel transport module.
10536 10:02:25.083686 <6>[ 0.774511] PCI: CLS 0 bytes, default 64
10537 10:02:25.086866 <6>[ 0.778910] Unpacking initramfs...
10538 10:02:25.110723 <6>[ 0.798443] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10539 10:02:25.120712 <6>[ 0.807118] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10540 10:02:25.123928 <6>[ 0.815980] kvm [1]: IPA Size Limit: 40 bits
10541 10:02:25.130591 <6>[ 0.820506] kvm [1]: GICv3: no GICV resource entry
10542 10:02:25.133813 <6>[ 0.825526] kvm [1]: disabling GICv2 emulation
10543 10:02:25.140895 <6>[ 0.830214] kvm [1]: GIC system register CPU interface enabled
10544 10:02:25.144167 <6>[ 0.836378] kvm [1]: vgic interrupt IRQ18
10545 10:02:25.150522 <6>[ 0.840743] kvm [1]: VHE mode initialized successfully
10546 10:02:25.157140 <5>[ 0.847040] Initialise system trusted keyrings
10547 10:02:25.163707 <6>[ 0.851904] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10548 10:02:25.170683 <6>[ 0.861873] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10549 10:02:25.177900 <5>[ 0.868271] NFS: Registering the id_resolver key type
10550 10:02:25.180904 <5>[ 0.873572] Key type id_resolver registered
10551 10:02:25.187255 <5>[ 0.877986] Key type id_legacy registered
10552 10:02:25.193912 <6>[ 0.882263] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10553 10:02:25.200600 <6>[ 0.889185] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10554 10:02:25.206890 <6>[ 0.896890] 9p: Installing v9fs 9p2000 file system support
10555 10:02:25.244428 <5>[ 0.935183] Key type asymmetric registered
10556 10:02:25.247791 <5>[ 0.939515] Asymmetric key parser 'x509' registered
10557 10:02:25.257514 <6>[ 0.944657] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10558 10:02:25.260898 <6>[ 0.952271] io scheduler mq-deadline registered
10559 10:02:25.264278 <6>[ 0.957050] io scheduler kyber registered
10560 10:02:25.282631 <6>[ 0.973839] EINJ: ACPI disabled.
10561 10:02:25.314706 <4>[ 0.999158] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 10:02:25.324449 <4>[ 1.009810] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10563 10:02:25.339317 <6>[ 1.030577] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10564 10:02:25.347327 <6>[ 1.038600] printk: console [ttyS0] disabled
10565 10:02:25.375552 <6>[ 1.063246] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10566 10:02:25.381979 <6>[ 1.072720] printk: console [ttyS0] enabled
10567 10:02:25.385518 <6>[ 1.072720] printk: console [ttyS0] enabled
10568 10:02:25.391848 <6>[ 1.081614] printk: bootconsole [mtk8250] disabled
10569 10:02:25.395339 <6>[ 1.081614] printk: bootconsole [mtk8250] disabled
10570 10:02:25.401979 <6>[ 1.092829] SuperH (H)SCI(F) driver initialized
10571 10:02:25.405123 <6>[ 1.098093] msm_serial: driver initialized
10572 10:02:25.419451 <6>[ 1.107094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10573 10:02:25.429422 <6>[ 1.115641] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10574 10:02:25.435928 <6>[ 1.124183] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10575 10:02:25.445950 <6>[ 1.132812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10576 10:02:25.456040 <6>[ 1.141521] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10577 10:02:25.462291 <6>[ 1.150244] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10578 10:02:25.472155 <6>[ 1.158785] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10579 10:02:25.479091 <6>[ 1.167597] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10580 10:02:25.488992 <6>[ 1.176142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10581 10:02:25.500652 <6>[ 1.191862] loop: module loaded
10582 10:02:25.507346 <6>[ 1.197864] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10583 10:02:25.530075 <4>[ 1.221251] mtk-pmic-keys: Failed to locate of_node [id: -1]
10584 10:02:25.536888 <6>[ 1.228187] megasas: 07.719.03.00-rc1
10585 10:02:25.546918 <6>[ 1.237895] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10586 10:02:25.555038 <6>[ 1.245737] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10587 10:02:25.571743 <6>[ 1.262427] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10588 10:02:25.628297 <6>[ 1.312684] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10589 10:02:26.682435 <6>[ 2.373491] Freeing initrd memory: 38416K
10590 10:02:26.692379 <6>[ 2.383769] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10591 10:02:26.703561 <6>[ 2.394722] tun: Universal TUN/TAP device driver, 1.6
10592 10:02:26.706974 <6>[ 2.400772] thunder_xcv, ver 1.0
10593 10:02:26.710292 <6>[ 2.404277] thunder_bgx, ver 1.0
10594 10:02:26.713507 <6>[ 2.407775] nicpf, ver 1.0
10595 10:02:26.724003 <6>[ 2.411804] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10596 10:02:26.727069 <6>[ 2.419280] hns3: Copyright (c) 2017 Huawei Corporation.
10597 10:02:26.733728 <6>[ 2.424868] hclge is initializing
10598 10:02:26.737201 <6>[ 2.428448] e1000: Intel(R) PRO/1000 Network Driver
10599 10:02:26.743640 <6>[ 2.433577] e1000: Copyright (c) 1999-2006 Intel Corporation.
10600 10:02:26.746927 <6>[ 2.439589] e1000e: Intel(R) PRO/1000 Network Driver
10601 10:02:26.753721 <6>[ 2.444804] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10602 10:02:26.760415 <6>[ 2.450989] igb: Intel(R) Gigabit Ethernet Network Driver
10603 10:02:26.767061 <6>[ 2.456639] igb: Copyright (c) 2007-2014 Intel Corporation.
10604 10:02:26.773780 <6>[ 2.462475] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10605 10:02:26.780185 <6>[ 2.468993] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10606 10:02:26.783388 <6>[ 2.475459] sky2: driver version 1.30
10607 10:02:26.790026 <6>[ 2.480452] VFIO - User Level meta-driver version: 0.3
10608 10:02:26.797475 <6>[ 2.488701] usbcore: registered new interface driver usb-storage
10609 10:02:26.803924 <6>[ 2.495140] usbcore: registered new device driver onboard-usb-hub
10610 10:02:26.813144 <6>[ 2.504274] mt6397-rtc mt6359-rtc: registered as rtc0
10611 10:02:26.823111 <6>[ 2.509763] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-23T10:02:22 UTC (1692784942)
10612 10:02:26.826135 <6>[ 2.519351] i2c_dev: i2c /dev entries driver
10613 10:02:26.843349 <6>[ 2.531031] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10614 10:02:26.863545 <6>[ 2.555014] cpu cpu0: EM: created perf domain
10615 10:02:26.867189 <6>[ 2.560029] cpu cpu4: EM: created perf domain
10616 10:02:26.874177 <6>[ 2.565611] sdhci: Secure Digital Host Controller Interface driver
10617 10:02:26.881181 <6>[ 2.572045] sdhci: Copyright(c) Pierre Ossman
10618 10:02:26.888006 <6>[ 2.577002] Synopsys Designware Multimedia Card Interface Driver
10619 10:02:26.894318 <6>[ 2.583640] sdhci-pltfm: SDHCI platform and OF driver helper
10620 10:02:26.897549 <6>[ 2.583694] mmc0: CQHCI version 5.10
10621 10:02:26.904592 <6>[ 2.593581] ledtrig-cpu: registered to indicate activity on CPUs
10622 10:02:26.911080 <6>[ 2.600597] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10623 10:02:26.917725 <6>[ 2.607656] usbcore: registered new interface driver usbhid
10624 10:02:26.920701 <6>[ 2.613479] usbhid: USB HID core driver
10625 10:02:26.927226 <6>[ 2.617678] spi_master spi0: will run message pump with realtime priority
10626 10:02:26.971384 <6>[ 2.655929] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10627 10:02:26.990948 <6>[ 2.672295] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10628 10:02:26.994152 <6>[ 2.686012] mmc0: Command Queue Engine enabled
10629 10:02:27.001060 <6>[ 2.690809] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10630 10:02:27.007937 <6>[ 2.698039] mmcblk0: mmc0:0001 DA4128 116 GiB
10631 10:02:27.010922 <6>[ 2.702984] cros-ec-spi spi0.0: Chrome EC device registered
10632 10:02:27.017683 <6>[ 2.706602] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10633 10:02:27.025292 <6>[ 2.716619] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10634 10:02:27.032095 <6>[ 2.722510] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10635 10:02:27.038545 <6>[ 2.728619] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10636 10:02:27.056040 <6>[ 2.743898] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10637 10:02:27.063357 <6>[ 2.754633] NET: Registered PF_PACKET protocol family
10638 10:02:27.069850 <6>[ 2.760032] 9pnet: Installing 9P2000 support
10639 10:02:27.073290 <5>[ 2.764600] Key type dns_resolver registered
10640 10:02:27.076357 <6>[ 2.769582] registered taskstats version 1
10641 10:02:27.083365 <5>[ 2.773966] Loading compiled-in X.509 certificates
10642 10:02:27.113757 <4>[ 2.798180] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 10:02:27.123291 <4>[ 2.808900] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 10:02:27.130313 <3>[ 2.819433] debugfs: File 'uA_load' in directory '/' already present!
10645 10:02:27.137009 <3>[ 2.826137] debugfs: File 'min_uV' in directory '/' already present!
10646 10:02:27.143788 <3>[ 2.832745] debugfs: File 'max_uV' in directory '/' already present!
10647 10:02:27.149942 <3>[ 2.839351] debugfs: File 'constraint_flags' in directory '/' already present!
10648 10:02:27.161424 <3>[ 2.849332] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10649 10:02:27.173561 <6>[ 2.864949] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10650 10:02:27.180337 <6>[ 2.871695] xhci-mtk 11200000.usb: xHCI Host Controller
10651 10:02:27.186823 <6>[ 2.877195] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10652 10:02:27.196938 <6>[ 2.885056] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10653 10:02:27.203881 <6>[ 2.894513] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10654 10:02:27.210767 <6>[ 2.900709] xhci-mtk 11200000.usb: xHCI Host Controller
10655 10:02:27.216970 <6>[ 2.906221] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10656 10:02:27.223670 <6>[ 2.913879] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10657 10:02:27.230519 <6>[ 2.921739] hub 1-0:1.0: USB hub found
10658 10:02:27.233966 <6>[ 2.925765] hub 1-0:1.0: 1 port detected
10659 10:02:27.240599 <6>[ 2.930064] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10660 10:02:27.247707 <6>[ 2.938841] hub 2-0:1.0: USB hub found
10661 10:02:27.250931 <6>[ 2.942865] hub 2-0:1.0: 1 port detected
10662 10:02:27.259011 <6>[ 2.950545] mtk-msdc 11f70000.mmc: Got CD GPIO
10663 10:02:27.271625 <6>[ 2.959425] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10664 10:02:27.278353 <6>[ 2.967636] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10665 10:02:27.288091 <4>[ 2.975780] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10666 10:02:27.298076 <6>[ 2.985329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10667 10:02:27.305104 <6>[ 2.993463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10668 10:02:27.314920 <6>[ 3.001482] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10669 10:02:27.321511 <6>[ 3.009416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10670 10:02:27.328172 <6>[ 3.017233] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10671 10:02:27.338044 <6>[ 3.025061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10672 10:02:27.347991 <6>[ 3.035610] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10673 10:02:27.354843 <6>[ 3.043991] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10674 10:02:27.364645 <6>[ 3.052335] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10675 10:02:27.371043 <6>[ 3.060684] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10676 10:02:27.380992 <6>[ 3.069023] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10677 10:02:27.390971 <6>[ 3.077375] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10678 10:02:27.397755 <6>[ 3.085715] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10679 10:02:27.404731 <6>[ 3.094064] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10680 10:02:27.414324 <6>[ 3.102403] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10681 10:02:27.424509 <6>[ 3.110752] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10682 10:02:27.431027 <6>[ 3.119091] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10683 10:02:27.440699 <6>[ 3.127428] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10684 10:02:27.447670 <6>[ 3.135766] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10685 10:02:27.457614 <6>[ 3.144104] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10686 10:02:27.464161 <6>[ 3.152442] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10687 10:02:27.470595 <6>[ 3.161230] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10688 10:02:27.477038 <6>[ 3.168416] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10689 10:02:27.483930 <6>[ 3.175186] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10690 10:02:27.493811 <6>[ 3.181955] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10691 10:02:27.500440 <6>[ 3.188891] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10692 10:02:27.507074 <6>[ 3.195737] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10693 10:02:27.517224 <6>[ 3.204869] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10694 10:02:27.527133 <6>[ 3.213988] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10695 10:02:27.536710 <6>[ 3.223321] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10696 10:02:27.546937 <6>[ 3.232875] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10697 10:02:27.556486 <6>[ 3.242348] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10698 10:02:27.563332 <6>[ 3.251469] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10699 10:02:27.573439 <6>[ 3.260936] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10700 10:02:27.583374 <6>[ 3.270055] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10701 10:02:27.593082 <6>[ 3.279350] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10702 10:02:27.602982 <6>[ 3.289510] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10703 10:02:27.613134 <6>[ 3.301093] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10704 10:02:27.670545 <6>[ 3.358608] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10705 10:02:27.825097 <6>[ 3.516492] hub 1-1:1.0: USB hub found
10706 10:02:27.828321 <6>[ 3.521027] hub 1-1:1.0: 4 ports detected
10707 10:02:27.950932 <6>[ 3.638793] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10708 10:02:27.977042 <6>[ 3.668479] hub 2-1:1.0: USB hub found
10709 10:02:27.980574 <6>[ 3.672982] hub 2-1:1.0: 3 ports detected
10710 10:02:28.150593 <6>[ 3.838617] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10711 10:02:28.283596 <6>[ 3.975014] hub 1-1.4:1.0: USB hub found
10712 10:02:28.286772 <6>[ 3.979701] hub 1-1.4:1.0: 2 ports detected
10713 10:02:28.362741 <6>[ 4.050865] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10714 10:02:28.586333 <6>[ 4.274654] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10715 10:02:28.778529 <6>[ 4.466591] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10716 10:02:39.903720 <6>[ 15.599594] ALSA device list:
10717 10:02:39.910229 <6>[ 15.602882] No soundcards found.
10718 10:02:39.918363 <6>[ 15.610752] Freeing unused kernel memory: 8384K
10719 10:02:39.921172 <6>[ 15.615752] Run /init as init process
10720 10:02:39.967518 <6>[ 15.660290] NET: Registered PF_INET6 protocol family
10721 10:02:39.974080 <6>[ 15.666418] Segment Routing with IPv6
10722 10:02:39.977694 <6>[ 15.670376] In-situ OAM (IOAM) with IPv6
10723 10:02:40.013666 <30>[ 15.686617] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10724 10:02:40.016780 <30>[ 15.710457] systemd[1]: Detected architecture arm64.
10725 10:02:40.016878
10726 10:02:40.023598 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10727 10:02:40.023681
10728 10:02:40.037848 <30>[ 15.730547] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10729 10:02:40.183956 <30>[ 15.873406] systemd[1]: Queued start job for default target Graphical Interface.
10730 10:02:40.226873 <30>[ 15.919643] systemd[1]: Created slice system-getty.slice.
10731 10:02:40.233238 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10732 10:02:40.250436 <30>[ 15.943176] systemd[1]: Created slice system-modprobe.slice.
10733 10:02:40.257246 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10734 10:02:40.278670 <30>[ 15.971513] systemd[1]: Created slice system-serial\x2dgetty.slice.
10735 10:02:40.288970 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10736 10:02:40.302228 <30>[ 15.995081] systemd[1]: Created slice User and Session Slice.
10737 10:02:40.309049 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10738 10:02:40.330059 <30>[ 16.019478] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10739 10:02:40.339981 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10740 10:02:40.357631 <30>[ 16.046800] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10741 10:02:40.364155 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10742 10:02:40.384656 <30>[ 16.070686] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10743 10:02:40.391588 <30>[ 16.082818] systemd[1]: Reached target Local Encrypted Volumes.
10744 10:02:40.398128 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10745 10:02:40.414571 <30>[ 16.107170] systemd[1]: Reached target Paths.
10746 10:02:40.417773 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10747 10:02:40.433639 <30>[ 16.126623] systemd[1]: Reached target Remote File Systems.
10748 10:02:40.440449 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10749 10:02:40.458227 <30>[ 16.151002] systemd[1]: Reached target Slices.
10750 10:02:40.464637 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10751 10:02:40.478360 <30>[ 16.170656] systemd[1]: Reached target Swap.
10752 10:02:40.481125 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10753 10:02:40.501538 <30>[ 16.191099] systemd[1]: Listening on initctl Compatibility Named Pipe.
10754 10:02:40.508596 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10755 10:02:40.514827 <30>[ 16.206292] systemd[1]: Listening on Journal Audit Socket.
10756 10:02:40.521267 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10757 10:02:40.534169 <30>[ 16.227074] systemd[1]: Listening on Journal Socket (/dev/log).
10758 10:02:40.541142 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10759 10:02:40.559067 <30>[ 16.251838] systemd[1]: Listening on Journal Socket.
10760 10:02:40.565382 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10761 10:02:40.578590 <30>[ 16.271312] systemd[1]: Listening on Network Service Netlink Socket.
10762 10:02:40.588497 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10763 10:02:40.603127 <30>[ 16.295830] systemd[1]: Listening on udev Control Socket.
10764 10:02:40.609418 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10765 10:02:40.626817 <30>[ 16.319727] systemd[1]: Listening on udev Kernel Socket.
10766 10:02:40.633275 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10767 10:02:40.674169 <30>[ 16.366903] systemd[1]: Mounting Huge Pages File System...
10768 10:02:40.680610 Mounting [0;1;39mHuge Pages File System[0m...
10769 10:02:40.696043 <30>[ 16.389028] systemd[1]: Mounting POSIX Message Queue File System...
10770 10:02:40.703233 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10771 10:02:40.721584 <30>[ 16.414440] systemd[1]: Mounting Kernel Debug File System...
10772 10:02:40.728045 Mounting [0;1;39mKernel Debug File System[0m...
10773 10:02:40.745521 <30>[ 16.434735] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10774 10:02:40.789869 <30>[ 16.479063] systemd[1]: Starting Create list of static device nodes for the current kernel...
10775 10:02:40.796462 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10776 10:02:40.817845 <30>[ 16.510722] systemd[1]: Starting Load Kernel Module configfs...
10777 10:02:40.824432 Starting [0;1;39mLoad Kernel Module configfs[0m...
10778 10:02:40.842321 <30>[ 16.534928] systemd[1]: Starting Load Kernel Module drm...
10779 10:02:40.848563 Starting [0;1;39mLoad Kernel Module drm[0m...
10780 10:02:40.865899 <30>[ 16.554966] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10781 10:02:40.914556 <30>[ 16.607441] systemd[1]: Starting Journal Service...
10782 10:02:40.918174 Starting [0;1;39mJournal Service[0m...
10783 10:02:40.938788 <30>[ 16.631392] systemd[1]: Starting Load Kernel Modules...
10784 10:02:40.944966 Starting [0;1;39mLoad Kernel Modules[0m...
10785 10:02:40.965642 <30>[ 16.655430] systemd[1]: Starting Remount Root and Kernel File Systems...
10786 10:02:40.972404 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10787 10:02:40.988437 <30>[ 16.681440] systemd[1]: Starting Coldplug All udev Devices...
10788 10:02:40.995296 Starting [0;1;39mColdplug All udev Devices[0m...
10789 10:02:41.012681 <30>[ 16.705598] systemd[1]: Started Journal Service.
10790 10:02:41.019453 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10791 10:02:41.037134 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10792 10:02:41.054890 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10793 10:02:41.070538 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10794 10:02:41.090277 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10795 10:02:41.107284 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10796 10:02:41.123981 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10797 10:02:41.147711 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10798 10:02:41.172161 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10799 10:02:41.185879 See 'systemctl status systemd-remount-fs.service' for details.
10800 10:02:41.242686 Mounting [0;1;39mKernel Configuration File System[0m...
10801 10:02:41.260101 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10802 10:02:41.278215 <46>[ 16.967646] systemd-journald[178]: Received client request to flush runtime journal.
10803 10:02:41.323693 Starting [0;1;39mLoad/Save Random Seed[0m...
10804 10:02:41.347161 Starting [0;1;39mApply Kernel Variables[0m...
10805 10:02:41.370501 Starting [0;1;39mCreate System Users[0m...
10806 10:02:41.395008 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10807 10:02:41.414859 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10808 10:02:41.434897 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10809 10:02:41.447549 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10810 10:02:41.462184 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10811 10:02:41.479315 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10812 10:02:41.518429 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10813 10:02:41.538472 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10814 10:02:41.550394 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10815 10:02:41.565896 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10816 10:02:41.618452 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10817 10:02:41.645652 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10818 10:02:41.667907 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10819 10:02:41.688171 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10820 10:02:41.711252 Starting [0;1;39mNetwork Service[0m...
10821 10:02:41.733217 Starting [0;1;39mNetwork Time Synchronization[0m...
10822 10:02:41.760844 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10823 10:02:41.811630 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10824 10:02:41.833029 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10825 10:02:41.843785 <6>[ 17.533437] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10826 10:02:41.853930 <6>[ 17.541947] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10827 10:02:41.860457 <4>[ 17.542274] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10828 10:02:41.870817 <6>[ 17.551190] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10829 10:02:41.877636 <4>[ 17.559061] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10830 10:02:41.883542 [[0;32m OK [<6>[ 17.575471] mc: Linux media interface: v0.10
10831 10:02:41.887000 0m] Started [0;1;39mNetwork Time Synchronization[0m.
10832 10:02:41.919232 <3>[ 17.608890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 10:02:41.925785 <3>[ 17.617138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 10:02:41.935976 <3>[ 17.625252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10835 10:02:41.939153 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10836 10:02:41.948861 <3>[ 17.637749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10837 10:02:41.955619 <3>[ 17.646977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 10:02:41.965628 <3>[ 17.655464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 10:02:41.972406 <3>[ 17.663556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 10:02:41.982675 <6>[ 17.669167] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10841 10:02:41.992208 [[0;32m OK [<3>[ 17.671664] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 10:02:41.998981 0m] Created slic<3>[ 17.671734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 10:02:42.009026 <6>[ 17.688521] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10844 10:02:42.018750 e [0;1;39msyste<3>[ 17.688889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10845 10:02:42.025538 m-systemd\x2dbac<6>[ 17.689374] videodev: Linux video capture interface: v2.00
10846 10:02:42.035435 klight.slice[0m<6>[ 17.695791] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10847 10:02:42.035520 .
10848 10:02:42.042078 <6>[ 17.695821] pci_bus 0000:00: root bus resource [bus 00-ff]
10849 10:02:42.048415 <6>[ 17.695837] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10850 10:02:42.058616 <6>[ 17.695848] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10851 10:02:42.065371 <6>[ 17.695938] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10852 10:02:42.071686 <6>[ 17.695958] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10853 10:02:42.075153 <6>[ 17.696036] pci 0000:00:00.0: supports D1 D2
10854 10:02:42.081544 <6>[ 17.696040] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10855 10:02:42.091393 <6>[ 17.698090] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10856 10:02:42.098275 <6>[ 17.698230] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10857 10:02:42.104722 <6>[ 17.698266] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10858 10:02:42.111462 <6>[ 17.698286] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10859 10:02:42.121387 <6>[ 17.698305] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10860 10:02:42.127875 <3>[ 17.707618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 10:02:42.137690 <3>[ 17.707622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 10:02:42.144475 <3>[ 17.707705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 10:02:42.147531 <6>[ 17.717436] pci 0000:01:00.0: supports D1 D2
10864 10:02:42.157592 <3>[ 17.724267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10865 10:02:42.164240 <6>[ 17.732501] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10866 10:02:42.170918 <3>[ 17.738503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10867 10:02:42.180961 <3>[ 17.738515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10868 10:02:42.187672 <3>[ 17.738520] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 10:02:42.197850 <3>[ 17.738618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 10:02:42.204447 <6>[ 17.750697] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10871 10:02:42.215492 <6>[ 17.751249] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10872 10:02:42.222219 <6>[ 17.751567] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10873 10:02:42.232133 <4>[ 17.760282] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10874 10:02:42.235736 <4>[ 17.760282] Fallback method does not support PEC.
10875 10:02:42.242363 <6>[ 17.783276] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10876 10:02:42.252641 <4>[ 17.790562] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10877 10:02:42.261886 <6>[ 17.795920] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10878 10:02:42.268646 <6>[ 17.803171] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10879 10:02:42.275792 <4>[ 17.805273] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10880 10:02:42.283060 <6>[ 17.807655] remoteproc remoteproc0: scp is available
10881 10:02:42.286021 <6>[ 17.807723] remoteproc remoteproc0: powering up scp
10882 10:02:42.296201 <6>[ 17.807727] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10883 10:02:42.299550 <6>[ 17.807745] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10884 10:02:42.309576 <6>[ 17.811401] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10885 10:02:42.312973 <6>[ 17.822851] Bluetooth: Core ver 2.22
10886 10:02:42.319598 <6>[ 17.826506] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10887 10:02:42.327089 <6>[ 17.834665] NET: Registered PF_BLUETOOTH protocol family
10888 10:02:42.333726 <6>[ 17.843054] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10889 10:02:42.340116 <6>[ 17.847277] Bluetooth: HCI device and connection manager initialized
10890 10:02:42.346891 <6>[ 17.847541] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10891 10:02:42.359843 <6>[ 17.848846] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10892 10:02:42.366755 <6>[ 17.848986] usbcore: registered new interface driver uvcvideo
10893 10:02:42.373264 <6>[ 17.855432] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10894 10:02:42.380100 <6>[ 17.856054] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10895 10:02:42.386372 <6>[ 17.862271] Bluetooth: HCI socket layer initialized
10896 10:02:42.389874 <6>[ 17.870559] pci 0000:00:00.0: PCI bridge to [bus 01]
10897 10:02:42.396441 <6>[ 17.878403] Bluetooth: L2CAP socket layer initialized
10898 10:02:42.399627 <6>[ 17.878533] r8152 2-1.3:1.0 eth0: v1.12.13
10899 10:02:42.406159 <6>[ 17.878653] usbcore: registered new interface driver r8152
10900 10:02:42.413074 <6>[ 17.886489] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10901 10:02:42.419519 <6>[ 17.894579] Bluetooth: SCO socket layer initialized
10902 10:02:42.426409 <6>[ 17.894826] usbcore: registered new interface driver cdc_ether
10903 10:02:42.433112 <6>[ 17.901890] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10904 10:02:42.439695 <6>[ 17.901903] usbcore: registered new interface driver r8153_ecm
10905 10:02:42.446113 <3>[ 17.910358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 10:02:42.456289 <3>[ 17.911076] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10907 10:02:42.462442 <6>[ 17.912337] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10908 10:02:42.465906 <6>[ 17.921691] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10909 10:02:42.475623 <3>[ 17.924808] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 10:02:42.482577 <6>[ 17.934585] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10911 10:02:42.492485 <6>[ 17.934614] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10912 10:02:42.498981 <6>[ 17.934627] remoteproc remoteproc0: remote processor scp is now up
10913 10:02:42.502201 <6>[ 17.941967] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10914 10:02:42.509128 <6>[ 17.959440] usbcore: registered new interface driver btusb
10915 10:02:42.518669 <4>[ 17.960228] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10916 10:02:42.525836 <3>[ 17.960249] Bluetooth: hci0: Failed to load firmware file (-2)
10917 10:02:42.532081 <3>[ 17.960255] Bluetooth: hci0: Failed to set up firmware (-2)
10918 10:02:42.542522 <4>[ 17.960261] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10919 10:02:42.551879 <6>[ 17.968183] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10920 10:02:42.558885 <3>[ 17.973734] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 10:02:42.568683 <3>[ 17.975904] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10922 10:02:42.575092 <5>[ 17.982807] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10923 10:02:42.584916 <6>[ 17.985408] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10924 10:02:42.594848 <3>[ 17.996734] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 10:02:42.601234 <5>[ 18.004983] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10926 10:02:42.607846 <3>[ 18.027054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 10:02:42.617869 <4>[ 18.307611] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10928 10:02:42.624646 <6>[ 18.316511] cfg80211: failed to load regulatory.db
10929 10:02:42.627980 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10930 10:02:42.639219 <3>[ 18.328874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 10:02:42.646145 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10932 10:02:42.663603 <6>[ 18.352636] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10933 10:02:42.670126 <3>[ 18.358554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 10:02:42.676633 <6>[ 18.360124] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10935 10:02:42.699761 <3>[ 18.388884] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 10:02:42.706003 <6>[ 18.397882] mt7921e 0000:01:00.0: ASIC revision: 79610010
10937 10:02:42.718114 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10938 10:02:42.742238 Starting [0;1;39mNetwork Name Resolution[0m...
10939 10:02:42.762343 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10940 10:02:42.816603 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m<4>[ 18.501418] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10941 10:02:42.816700 .
10942 10:02:42.950271 [[0;32m OK [<4>[ 18.636611] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10943 10:02:42.956679 0m] Reached target [0;1;39mBluetooth[0m.
10944 10:02:42.970296 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10945 10:02:42.989046 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10946 10:02:43.001888 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10947 10:02:43.021823 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10948 10:02:43.036670 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10949 10:02:43.049675 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10950 10:02:43.070338 <4>[ 18.756773] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10951 10:02:43.080469 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10952 10:02:43.094071 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10953 10:02:43.109976 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10954 10:02:43.129960 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10955 10:02:43.162523 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10956 10:02:43.191653 <4>[ 18.878145] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 10:02:43.206483 Starting [0;1;39mUser Login Management[0m...
10958 10:02:43.226475 Starting [0;1;39mPermit User Sessions[0m...
10959 10:02:43.248075 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10960 10:02:43.269871 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10961 10:02:43.285810 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10962 10:02:43.319842 [[0;32m OK [0m] Started [0;<4>[ 19.005776] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10963 10:02:43.322960 1;39mUser Login Management[0m.
10964 10:02:43.375027 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10965 10:02:43.395511 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10966 10:02:43.415206 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10967 10:02:43.438123 [[0;32m OK [<4>[ 19.124709] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10968 10:02:43.444525 0m] Reached target [0;1;39mMulti-User System[0m.
10969 10:02:43.459210 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10970 10:02:43.507373 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10971 10:02:43.560666 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System R<4>[ 19.245338] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10972 10:02:43.560761 unlevel Changes[0m.
10973 10:02:43.602651
10974 10:02:43.602737
10975 10:02:43.605536 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10976 10:02:43.605619
10977 10:02:43.608996 debian-bullseye-arm64 login: root (automatic login)
10978 10:02:43.609079
10979 10:02:43.609142
10980 10:02:43.626556 Linux debian-bullseye-arm64 6.1.45-cip3 #1 SMP PREEMPT Wed Aug 23 09:52:58 UTC 2023 aarch64
10981 10:02:43.626640
10982 10:02:43.633507 The programs included with the Debian GNU/Linux system are free software;
10983 10:02:43.639914 the exact distribution terms for each program are described in the
10984 10:02:43.643362 individual files in /usr/share/doc/*/copyright.
10985 10:02:43.643444
10986 10:02:43.650130 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10987 10:02:43.653181 permitted by applicable law.
10988 10:02:43.653520 Matched prompt #10: / #
10990 10:02:43.653725 Setting prompt string to ['/ #']
10991 10:02:43.653816 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10993 10:02:43.654004 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10994 10:02:43.654089 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
10995 10:02:43.654158 Setting prompt string to ['/ #']
10996 10:02:43.654216 Forcing a shell prompt, looking for ['/ #']
10998 10:02:43.704423 / #
10999 10:02:43.704521 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11000 10:02:43.704594 Waiting using forced prompt support (timeout 00:02:30)
11001 10:02:43.704687 <4>[ 19.365174] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11002 10:02:43.709296
11003 10:02:43.709562 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11004 10:02:43.709656 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
11005 10:02:43.709746 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11006 10:02:43.709829 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
11007 10:02:43.709913 end: 2 depthcharge-action (duration 00:01:37) [common]
11008 10:02:43.710001 start: 3 lava-test-retry (timeout 00:08:03) [common]
11009 10:02:43.710087 start: 3.1 lava-test-shell (timeout 00:08:03) [common]
11010 10:02:43.710159 Using namespace: common
11012 10:02:43.810475 / # #
11013 10:02:43.810592 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11014 10:02:43.810703 #<4>[ 19.489678] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11015 10:02:43.815517
11016 10:02:43.857097 Using /lava-11336440
11018 10:02:43.957450 / # <6>[ 19.534934] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomexport SHELL=/bin/sh
11019 10:02:43.957595 es ready
11020 10:02:43.957677 <6>[ 19.543153] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11021 10:02:43.957756 export<4>[ 19.609050] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11022 10:02:43.962672 SHELL=/bin/sh
11024 10:02:44.063199 / # . /lava-11336440/environment
11025 10:02:44.063357 . /lava-11336440/environment<3>[ 19.726615] mt7921e 0000:01:00.0: hardware init failed
11026 10:02:44.068617
11028 10:02:44.169141 / # /lava-11336440/bin/lava-test-runner /lava-11336440/0
11029 10:02:44.169247 Test shell timeout: 10s (minimum of the action and connection timeout)
11030 10:02:44.174044 /lava-11336440/bin/lava-test-runner /lava-11336440/0
11031 10:02:44.196165 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11032 10:02:44.202537 + cd /lava-11336440/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11033 10:02:44.202620 + cat uuid
11034 10:02:44.205846 + UUID=11336440_1.5.2.3.1
11035 10:02:44.205930 + set +x
11036 10:02:44.212177 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11336440_1.5.2.3.1>
11037 10:02:44.212432 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11336440_1.5.2.3.1
11038 10:02:44.212508 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11336440_1.5.2.3.1)
11039 10:02:44.212634 Skipping test definition patterns.
11040 10:02:44.215423 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11041 10:02:44.219516 Received signal: <TESTCASE> TEST_CASE_ID=device-presence<4
11042 10:02:44.219641 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'device-presence<4', 'result': 'unknown'}
11043 10:02:44.229003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence<4>[ 19.917148] use of bytesused == 0 is deprecated and will be removed in the future,
11044 10:02:44.232268 <4>[ 19.926142] use the actual size instead.
11045 10:02:44.232351 RESULT=pass>
11046 10:02:44.238965 device: /dev/vide<4>[ 19.932452] ------------[ cut here ]------------
11047 10:02:44.239047 o2
11048 10:02:44.245787 <4>[ 19.938034] get_vaddr_frames() cannot follow VM_IO mapping
11049 10:02:44.259202 <4>[ 19.938189] WARNING: CPU: 6 PID: 303 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11050 10:02:44.308462 <4>[ 19.956533] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 cros_ec_rpmsg btusb btintel btmtk btrtl btbcm r8153_ecm cdc_ether usbnet mtk_vcodec_enc mtk_vcodec_common mtk_vpu uvcvideo v4l2_mem2mem videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops bluetooth ecdh_generic mtk_scp videobuf2_v4l2 hid_google_hammer ecc mtk_rpmsg videobuf2_common rfkill videodev r8152 cros_ec_chardev sbs_battery crct10dif_ce cros_ec_typec elan_i2c hid_vivaldi_common mtk_scp_ipi mc elants_i2c pcie_mediatek_gen3 ip_tables x_tables ipv6
11051 10:02:44.315130 <4>[ 20.005875] CPU: 6 PID: 303 Comm: v4l2-compliance Not tainted 6.1.45-cip3 #1
11052 10:02:44.321671 <4>[ 20.013171] Hardware name: Google Spherion (rev0 - 3) (DT)
11053 10:02:44.328299 <4>[ 20.018904] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11054 10:02:44.335024 <4>[ 20.026112] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11055 10:02:44.341462 <4>[ 20.032198] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11056 10:02:44.344724 <4>[ 20.038283] sp : ffff800008de3850
11057 10:02:44.351756 <4>[ 20.041844] x29: ffff800008de3850 x28: ffffa397d7fd1000 x27: ffffa397d7fcd238
11058 10:02:44.358223 <4>[ 20.049228] x26: 0000000000000000 x25: ffffa39816e2c0e0 x24: ffff6ec24e241298
11059 10:02:44.364740 <4>[ 20.056610] x23: ffff6ec24c03bc00 x22: ffff6ec240d48410 x21: 0000000000000000
11060 10:02:44.371555 <4>[ 20.063993] x20: 00000000fffffff2 x19: ffff6ec24dbecb80 x18: fffffffffffe9770
11061 10:02:44.381187 <4>[ 20.071375] x17: 0000000000000000 x16: ffffa39814c8bb90 x15: 0000000000000038
11062 10:02:44.388161 <4>[ 20.078757] x14: ffffa398177134a8 x13: 000000000000064e x12: 000000000000021a
11063 10:02:44.394489 <4>[ 20.086140] x11: fffffffffffe9770 x10: fffffffffffe9738 x9 : 00000000fffff21a
11064 10:02:44.401127 <4>[ 20.093522] x8 : ffffa398177134a8 x7 : ffffa3981776b4a8 x6 : 0000000000001938
11065 10:02:44.410831 <4>[ 20.100904] x5 : ffff6ec37ef93a18 x4 : 00000000fffff21a x3 : ffffcb2b67f40000
11066 10:02:44.417599 <4>[ 20.108286] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff6ec249ac49c0
11067 10:02:44.420931 <4>[ 20.115668] Call trace:
11068 10:02:44.424271 <4>[ 20.118363] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11069 10:02:44.430885 <4>[ 20.124102] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11070 10:02:44.438074 <4>[ 20.130099] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11071 10:02:44.444084 <4>[ 20.136446] __prepare_userptr+0x280/0x410 [videobuf2_common]
11072 10:02:44.450702 <4>[ 20.142445] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11073 10:02:44.457345 <4>[ 20.148097] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11074 10:02:44.461072 <4>[ 20.154268] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11075 10:02:44.467291 <4>[ 20.159755] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11076 10:02:44.473904 <4>[ 20.165507] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11077 10:02:44.477093 <4>[ 20.171766] v4l_prepare_buf+0x48/0x60 [videodev]
11078 10:02:44.483713 <4>[ 20.176779] __video_do_ioctl+0x184/0x3d0 [videodev]
11079 10:02:44.487109 <4>[ 20.182006] video_usercopy+0x358/0x680 [videodev]
11080 10:02:44.493655 <4>[ 20.187060] video_ioctl2+0x18/0x30 [videodev]
11081 10:02:44.497100 <4>[ 20.191765] v4l2_ioctl+0x40/0x60 [videodev]
11082 10:02:44.503762 <4>[ 20.196297] __arm64_sys_ioctl+0xa8/0xf0
11083 10:02:44.506834 <4>[ 20.200473] invoke_syscall+0x48/0x114
11084 10:02:44.510748 <4>[ 20.204477] el0_svc_common.constprop.0+0x44/0xec
11085 10:02:44.513739 <4>[ 20.209430] do_el0_svc+0x2c/0xd0
11086 10:02:44.517111 <4>[ 20.212994] el0_svc+0x2c/0x84
11087 10:02:44.523585 <4>[ 20.216299] el0t_64_sync_handler+0xb8/0xc0
11088 10:02:44.526677 <4>[ 20.220730] el0t_64_sync+0x18c/0x190
11089 10:02:44.529973 <4>[ 20.224641] ---[ end trace 0000000000000000 ]---
11090 10:02:44.543755 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11091 10:02:44.552259 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11092 10:02:44.560402
11093 10:02:44.575096 Compliance test for mtk-vcodec-enc device /dev/video2:
11094 10:02:44.582172
11095 10:02:44.592451 Driver Info:
11096 10:02:44.607645 Driver name : mtk-vcodec-enc
11097 10:02:44.621034 Card type : MT8192 video encoder
11098 10:02:44.630868 Bus info : platform:17020000.vcodec
11099 10:02:44.643540 Driver version : 6.1.45
11100 10:02:44.655667 Capabilities : 0x84204000
11101 10:02:44.667901 Video Memory-to-Memory Multiplanar
11102 10:02:44.679272 Streaming
11103 10:02:44.691818 Extended Pix Format
11104 10:02:44.704685 Device Capabilities
11105 10:02:44.716175 Device Caps : 0x04204000
11106 10:02:44.729012 Video Memory-to-Memory Multiplanar
11107 10:02:44.741882 Streaming
11108 10:02:44.754571 Extended Pix Format
11109 10:02:44.769032 Detected Stateful Encoder
11110 10:02:44.781479
11111 10:02:44.792925 Required ioctls:
11112 10:02:44.813097 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11113 10:02:44.813182 test VIDIOC_QUERYCAP: OK
11114 10:02:44.813431 Received signal: <TESTSET> START Required-ioctls
11115 10:02:44.813505 Starting test_set Required-ioctls
11116 10:02:44.838134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11117 10:02:44.838387 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11119 10:02:44.841263 test invalid ioctls: OK
11120 10:02:44.863090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11121 10:02:44.863216
11122 10:02:44.863509 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11124 10:02:44.876520 Allow for multiple opens:
11125 10:02:44.884243 <LAVA_SIGNAL_TESTSET STOP>
11126 10:02:44.884539 Received signal: <TESTSET> STOP
11127 10:02:44.884660 Closing test_set Required-ioctls
11128 10:02:44.894133 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11129 10:02:44.894385 Received signal: <TESTSET> START Allow-for-multiple-opens
11130 10:02:44.894454 Starting test_set Allow-for-multiple-opens
11131 10:02:44.897090 test second /dev/video2 open: OK
11132 10:02:44.918774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11133 10:02:44.919026 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11135 10:02:44.921719 test VIDIOC_QUERYCAP: OK
11136 10:02:44.947774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11137 10:02:44.948024 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11139 10:02:44.951104 test VIDIOC_G/S_PRIORITY: OK
11140 10:02:44.972111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11141 10:02:44.972365 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11143 10:02:44.975310 test for unlimited opens: OK
11144 10:02:44.996190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11145 10:02:44.996272
11146 10:02:44.996505 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11148 10:02:45.011660 Debug ioctls:
11149 10:02:45.019857 <LAVA_SIGNAL_TESTSET STOP>
11150 10:02:45.020107 Received signal: <TESTSET> STOP
11151 10:02:45.020185 Closing test_set Allow-for-multiple-opens
11152 10:02:45.029662 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11153 10:02:45.029911 Received signal: <TESTSET> START Debug-ioctls
11154 10:02:45.029978 Starting test_set Debug-ioctls
11155 10:02:45.032860 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11156 10:02:45.054294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11157 10:02:45.054599 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11159 10:02:45.061071 test VIDIOC_LOG_STATUS: OK (Not Supported)
11160 10:02:45.078920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11161 10:02:45.079002
11162 10:02:45.079235 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11164 10:02:45.088941 Input ioctls:
11165 10:02:45.097389 <LAVA_SIGNAL_TESTSET STOP>
11166 10:02:45.097639 Received signal: <TESTSET> STOP
11167 10:02:45.097705 Closing test_set Debug-ioctls
11168 10:02:45.106733 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11169 10:02:45.106983 Received signal: <TESTSET> START Input-ioctls
11170 10:02:45.107050 Starting test_set Input-ioctls
11171 10:02:45.109805 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11172 10:02:45.136067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11173 10:02:45.136347 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11175 10:02:45.138920 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11176 10:02:45.159752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11177 10:02:45.160004 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11179 10:02:45.166372 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11180 10:02:45.185560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11181 10:02:45.185815 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11183 10:02:45.192187 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11184 10:02:45.211150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11185 10:02:45.211454 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11187 10:02:45.214505 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11188 10:02:45.239730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11189 10:02:45.240033 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11191 10:02:45.243282 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11192 10:02:45.263266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11193 10:02:45.263544 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11195 10:02:45.266347 Inputs: 0 Audio Inputs: 0 Tuners: 0
11196 10:02:45.274499
11197 10:02:45.290722 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11198 10:02:45.312706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11199 10:02:45.313009 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11201 10:02:45.318870 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11202 10:02:45.342361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11203 10:02:45.342614 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11205 10:02:45.345611 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11206 10:02:45.371708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11207 10:02:45.371990 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11209 10:02:45.377904 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11210 10:02:45.397174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11211 10:02:45.397427 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11213 10:02:45.403586 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11214 10:02:45.421463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11215 10:02:45.421715 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11217 10:02:45.424587
11218 10:02:45.446639 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11219 10:02:45.467848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11220 10:02:45.468101 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11222 10:02:45.474393 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11223 10:02:45.495513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11224 10:02:45.495766 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11226 10:02:45.499123 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11227 10:02:45.523639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11228 10:02:45.523892 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11230 10:02:45.526892 test VIDIOC_G/S_EDID: OK (Not Supported)
11231 10:02:45.547455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11232 10:02:45.547540
11233 10:02:45.547776 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11235 10:02:45.556229 Control ioctls:
11236 10:02:45.562904 <LAVA_SIGNAL_TESTSET STOP>
11237 10:02:45.563155 Received signal: <TESTSET> STOP
11238 10:02:45.563224 Closing test_set Input-ioctls
11239 10:02:45.571611 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11240 10:02:45.571862 Received signal: <TESTSET> START Control-ioctls
11241 10:02:45.571931 Starting test_set Control-ioctls
11242 10:02:45.574928 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11243 10:02:45.598168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11244 10:02:45.598254 test VIDIOC_QUERYCTRL: OK
11245 10:02:45.598489 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11247 10:02:45.616933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11248 10:02:45.617189 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11250 10:02:45.620048 test VIDIOC_G/S_CTRL: OK
11251 10:02:45.640428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11252 10:02:45.640681 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11254 10:02:45.643608 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11255 10:02:45.664085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11256 10:02:45.664338 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11258 10:02:45.674245 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11259 10:02:45.677465 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11260 10:02:45.702980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11261 10:02:45.703252 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11263 10:02:45.706194 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11264 10:02:45.725176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11265 10:02:45.725445 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11267 10:02:45.728529 Standard Controls: 16 Private Controls: 0
11268 10:02:45.735933
11269 10:02:45.747822 Format ioctls:
11270 10:02:45.754906 <LAVA_SIGNAL_TESTSET STOP>
11271 10:02:45.755158 Received signal: <TESTSET> STOP
11272 10:02:45.755227 Closing test_set Control-ioctls
11273 10:02:45.764292 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11274 10:02:45.764545 Received signal: <TESTSET> START Format-ioctls
11275 10:02:45.764617 Starting test_set Format-ioctls
11276 10:02:45.767288 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11277 10:02:45.793346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11278 10:02:45.793605 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11280 10:02:45.796411 test VIDIOC_G/S_PARM: OK
11281 10:02:45.815202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11282 10:02:45.815455 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11284 10:02:45.818694 test VIDIOC_G_FBUF: OK (Not Supported)
11285 10:02:45.839711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11286 10:02:45.839963 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11288 10:02:45.843155 test VIDIOC_G_FMT: OK
11289 10:02:45.866439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11290 10:02:45.866691 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11292 10:02:45.869785 test VIDIOC_TRY_FMT: OK
11293 10:02:45.891810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11294 10:02:45.892061 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11296 10:02:45.901499 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11297 10:02:45.904746 test VIDIOC_S_FMT: FAIL
11298 10:02:45.930242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11299 10:02:45.930496 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11301 10:02:45.933762 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11302 10:02:45.954953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11303 10:02:45.955207 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11305 10:02:45.957842 test Cropping: OK
11306 10:02:45.979533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11307 10:02:45.979785 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11309 10:02:45.982639 test Composing: OK (Not Supported)
11310 10:02:46.009722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11311 10:02:46.010005 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11313 10:02:46.012942 test Scaling: OK (Not Supported)
11314 10:02:46.034584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11315 10:02:46.034668
11316 10:02:46.034901 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11318 10:02:46.044623 Codec ioctls:
11319 10:02:46.051601 <LAVA_SIGNAL_TESTSET STOP>
11320 10:02:46.051853 Received signal: <TESTSET> STOP
11321 10:02:46.051921 Closing test_set Format-ioctls
11322 10:02:46.061928 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11323 10:02:46.062180 Received signal: <TESTSET> START Codec-ioctls
11324 10:02:46.062249 Starting test_set Codec-ioctls
11325 10:02:46.065397 test VIDIOC_(TRY_)ENCODER_CMD: OK
11326 10:02:46.085125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11327 10:02:46.085377 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11329 10:02:46.091687 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11330 10:02:46.110403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11331 10:02:46.110663 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11333 10:02:46.117348 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11334 10:02:46.133831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11335 10:02:46.133914
11336 10:02:46.134147 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11338 10:02:46.144995 Buffer ioctls:
11339 10:02:46.152938 <LAVA_SIGNAL_TESTSET STOP>
11340 10:02:46.153189 Received signal: <TESTSET> STOP
11341 10:02:46.153256 Closing test_set Codec-ioctls
11342 10:02:46.163484 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11343 10:02:46.163737 Received signal: <TESTSET> START Buffer-ioctls
11344 10:02:46.163814 Starting test_set Buffer-ioctls
11345 10:02:46.166072 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11346 10:02:46.193694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11347 10:02:46.193778 test VIDIOC_EXPBUF: OK
11348 10:02:46.194013 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11350 10:02:46.220426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11351 10:02:46.220678 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11353 10:02:46.223591 test Requests: OK (Not Supported)
11354 10:02:46.246564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11355 10:02:46.246648
11356 10:02:46.246881 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11358 10:02:46.257520 Test input 0:
11359 10:02:46.266783
11360 10:02:46.277591 Streaming ioctls:
11361 10:02:46.284667 <LAVA_SIGNAL_TESTSET STOP>
11362 10:02:46.284924 Received signal: <TESTSET> STOP
11363 10:02:46.284994 Closing test_set Buffer-ioctls
11364 10:02:46.294721 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11365 10:02:46.294974 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11366 10:02:46.295046 Starting test_set Streaming-ioctls_Test-input-0
11367 10:02:46.297717 test read/write: OK (Not Supported)
11368 10:02:46.318894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11369 10:02:46.319147 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11371 10:02:46.325669 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11372 10:02:46.335727 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11373 10:02:46.339784 test blocking wait: FAIL
11374 10:02:46.364235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11375 10:02:46.364511 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11377 10:02:46.374262 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11378 10:02:46.377414 test MMAP (select): FAIL
11379 10:02:46.400731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11380 10:02:46.400991 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11382 10:02:46.407128 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11383 10:02:46.416233 test MMAP (epoll): FAIL
11384 10:02:46.441294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11385 10:02:46.441548 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11387 10:02:46.451202 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11388 10:02:46.457752 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11389 10:02:46.462771 test USERPTR (select): FAIL
11390 10:02:46.492094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11391 10:02:46.492349 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11393 10:02:46.495848 test DMABUF: Cannot test, specify --expbuf-device
11394 10:02:46.506150
11395 10:02:46.526274 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11396 10:02:46.530314 <LAVA_TEST_RUNNER EXIT>
11397 10:02:46.530561 ok: lava_test_shell seems to have completed
11398 10:02:46.530632 Marking unfinished test run as failed
11400 10:02:46.532121 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11401 10:02:46.532246 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11402 10:02:46.532334 end: 3 lava-test-retry (duration 00:00:03) [common]
11403 10:02:46.532418 start: 4 finalize (timeout 00:08:00) [common]
11404 10:02:46.532517 start: 4.1 power-off (timeout 00:00:30) [common]
11405 10:02:46.532835 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11406 10:02:46.601757 >> Command sent successfully.
11407 10:02:46.604139 Returned 0 in 0 seconds
11408 10:02:46.704565 end: 4.1 power-off (duration 00:00:00) [common]
11410 10:02:46.705076 start: 4.2 read-feedback (timeout 00:08:00) [common]
11411 10:02:46.705444 Listened to connection for namespace 'common' for up to 1s
11412 10:02:47.706374 Finalising connection for namespace 'common'
11413 10:02:47.706558 Disconnecting from shell: Finalise
11414 10:02:47.706635 / #
11415 10:02:47.806948 end: 4.2 read-feedback (duration 00:00:01) [common]
11416 10:02:47.807090 end: 4 finalize (duration 00:00:01) [common]
11417 10:02:47.807198 Cleaning after the job
11418 10:02:47.807297 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/ramdisk
11419 10:02:47.811526 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/kernel
11420 10:02:47.817694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/dtb
11421 10:02:47.817849 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11336440/tftp-deploy-_opjp2ba/modules
11422 10:02:47.823064 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11336440
11423 10:02:47.877782 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11336440
11424 10:02:47.877956 Job finished correctly